1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #ifndef _I40E_ADMINQ_CMD_H_
35 #define _I40E_ADMINQ_CMD_H_
37 /* This header file defines the i40e Admin Queue commands and is shared between
38 * i40e Firmware and Software.
40 * This file needs to comply with the Linux Kernel coding style.
43 #define I40E_FW_API_VERSION_MAJOR 0x0001
44 #define I40E_FW_API_VERSION_MINOR 0x0004
70 /* Flags sub-structure
71 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
72 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
75 /* command flags and offsets*/
76 #define I40E_AQ_FLAG_DD_SHIFT 0
77 #define I40E_AQ_FLAG_CMP_SHIFT 1
78 #define I40E_AQ_FLAG_ERR_SHIFT 2
79 #define I40E_AQ_FLAG_VFE_SHIFT 3
80 #define I40E_AQ_FLAG_LB_SHIFT 9
81 #define I40E_AQ_FLAG_RD_SHIFT 10
82 #define I40E_AQ_FLAG_VFC_SHIFT 11
83 #define I40E_AQ_FLAG_BUF_SHIFT 12
84 #define I40E_AQ_FLAG_SI_SHIFT 13
85 #define I40E_AQ_FLAG_EI_SHIFT 14
86 #define I40E_AQ_FLAG_FE_SHIFT 15
88 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
89 #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */
90 #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
91 #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */
92 #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
93 #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
94 #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */
95 #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
96 #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
97 #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */
98 #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */
101 enum i40e_admin_queue_err {
102 I40E_AQ_RC_OK = 0, /* success */
103 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */
104 I40E_AQ_RC_ENOENT = 2, /* No such element */
105 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */
106 I40E_AQ_RC_EINTR = 4, /* operation interrupted */
107 I40E_AQ_RC_EIO = 5, /* I/O error */
108 I40E_AQ_RC_ENXIO = 6, /* No such resource */
109 I40E_AQ_RC_E2BIG = 7, /* Arg too long */
110 I40E_AQ_RC_EAGAIN = 8, /* Try again */
111 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */
112 I40E_AQ_RC_EACCES = 10, /* Permission denied */
113 I40E_AQ_RC_EFAULT = 11, /* Bad address */
114 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */
115 I40E_AQ_RC_EEXIST = 13, /* object already exists */
116 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */
117 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */
118 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
119 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */
120 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */
121 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
122 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
123 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
124 I40E_AQ_RC_EFBIG = 22, /* File too large */
127 /* Admin Queue command opcodes */
128 enum i40e_admin_queue_opc {
130 i40e_aqc_opc_get_version = 0x0001,
131 i40e_aqc_opc_driver_version = 0x0002,
132 i40e_aqc_opc_queue_shutdown = 0x0003,
133 i40e_aqc_opc_set_pf_context = 0x0004,
135 /* resource ownership */
136 i40e_aqc_opc_request_resource = 0x0008,
137 i40e_aqc_opc_release_resource = 0x0009,
139 i40e_aqc_opc_list_func_capabilities = 0x000A,
140 i40e_aqc_opc_list_dev_capabilities = 0x000B,
143 i40e_aqc_opc_mac_address_read = 0x0107,
144 i40e_aqc_opc_mac_address_write = 0x0108,
147 i40e_aqc_opc_clear_pxe_mode = 0x0110,
149 /* internal switch commands */
150 i40e_aqc_opc_get_switch_config = 0x0200,
151 i40e_aqc_opc_add_statistics = 0x0201,
152 i40e_aqc_opc_remove_statistics = 0x0202,
153 i40e_aqc_opc_set_port_parameters = 0x0203,
154 i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
156 i40e_aqc_opc_add_vsi = 0x0210,
157 i40e_aqc_opc_update_vsi_parameters = 0x0211,
158 i40e_aqc_opc_get_vsi_parameters = 0x0212,
160 i40e_aqc_opc_add_pv = 0x0220,
161 i40e_aqc_opc_update_pv_parameters = 0x0221,
162 i40e_aqc_opc_get_pv_parameters = 0x0222,
164 i40e_aqc_opc_add_veb = 0x0230,
165 i40e_aqc_opc_update_veb_parameters = 0x0231,
166 i40e_aqc_opc_get_veb_parameters = 0x0232,
168 i40e_aqc_opc_delete_element = 0x0243,
170 i40e_aqc_opc_add_macvlan = 0x0250,
171 i40e_aqc_opc_remove_macvlan = 0x0251,
172 i40e_aqc_opc_add_vlan = 0x0252,
173 i40e_aqc_opc_remove_vlan = 0x0253,
174 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
175 i40e_aqc_opc_add_tag = 0x0255,
176 i40e_aqc_opc_remove_tag = 0x0256,
177 i40e_aqc_opc_add_multicast_etag = 0x0257,
178 i40e_aqc_opc_remove_multicast_etag = 0x0258,
179 i40e_aqc_opc_update_tag = 0x0259,
180 i40e_aqc_opc_add_control_packet_filter = 0x025A,
181 i40e_aqc_opc_remove_control_packet_filter = 0x025B,
182 i40e_aqc_opc_add_cloud_filters = 0x025C,
183 i40e_aqc_opc_remove_cloud_filters = 0x025D,
185 i40e_aqc_opc_add_mirror_rule = 0x0260,
186 i40e_aqc_opc_delete_mirror_rule = 0x0261,
189 i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
190 i40e_aqc_opc_dcb_updated = 0x0302,
193 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
194 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
195 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
196 i40e_aqc_opc_query_vsi_bw_config = 0x0408,
197 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
198 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
200 i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
201 i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
202 i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
203 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
204 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
205 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
206 i40e_aqc_opc_query_port_ets_config = 0x0419,
207 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
208 i40e_aqc_opc_suspend_port_tx = 0x041B,
209 i40e_aqc_opc_resume_port_tx = 0x041C,
210 i40e_aqc_opc_configure_partition_bw = 0x041D,
213 i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
214 i40e_aqc_opc_set_hmc_resource_profile = 0x0501,
217 i40e_aqc_opc_get_phy_abilities = 0x0600,
218 i40e_aqc_opc_set_phy_config = 0x0601,
219 i40e_aqc_opc_set_mac_config = 0x0603,
220 i40e_aqc_opc_set_link_restart_an = 0x0605,
221 i40e_aqc_opc_get_link_status = 0x0607,
222 i40e_aqc_opc_set_phy_int_mask = 0x0613,
223 i40e_aqc_opc_get_local_advt_reg = 0x0614,
224 i40e_aqc_opc_set_local_advt_reg = 0x0615,
225 i40e_aqc_opc_get_partner_advt = 0x0616,
226 i40e_aqc_opc_set_lb_modes = 0x0618,
227 i40e_aqc_opc_get_phy_wol_caps = 0x0621,
228 i40e_aqc_opc_set_phy_debug = 0x0622,
229 i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
232 i40e_aqc_opc_nvm_read = 0x0701,
233 i40e_aqc_opc_nvm_erase = 0x0702,
234 i40e_aqc_opc_nvm_update = 0x0703,
235 i40e_aqc_opc_nvm_config_read = 0x0704,
236 i40e_aqc_opc_nvm_config_write = 0x0705,
237 i40e_aqc_opc_oem_post_update = 0x0720,
239 /* virtualization commands */
240 i40e_aqc_opc_send_msg_to_pf = 0x0801,
241 i40e_aqc_opc_send_msg_to_vf = 0x0802,
242 i40e_aqc_opc_send_msg_to_peer = 0x0803,
244 /* alternate structure */
245 i40e_aqc_opc_alternate_write = 0x0900,
246 i40e_aqc_opc_alternate_write_indirect = 0x0901,
247 i40e_aqc_opc_alternate_read = 0x0902,
248 i40e_aqc_opc_alternate_read_indirect = 0x0903,
249 i40e_aqc_opc_alternate_write_done = 0x0904,
250 i40e_aqc_opc_alternate_set_mode = 0x0905,
251 i40e_aqc_opc_alternate_clear_port = 0x0906,
254 i40e_aqc_opc_lldp_get_mib = 0x0A00,
255 i40e_aqc_opc_lldp_update_mib = 0x0A01,
256 i40e_aqc_opc_lldp_add_tlv = 0x0A02,
257 i40e_aqc_opc_lldp_update_tlv = 0x0A03,
258 i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
259 i40e_aqc_opc_lldp_stop = 0x0A05,
260 i40e_aqc_opc_lldp_start = 0x0A06,
261 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07,
262 i40e_aqc_opc_lldp_set_local_mib = 0x0A08,
263 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09,
265 /* Tunnel commands */
266 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
267 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
270 i40e_aqc_opc_event_lan_overflow = 0x1001,
273 i40e_aqc_opc_oem_parameter_change = 0xFE00,
274 i40e_aqc_opc_oem_device_status_change = 0xFE01,
275 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02,
276 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03,
279 i40e_aqc_opc_debug_read_reg = 0xFF03,
280 i40e_aqc_opc_debug_write_reg = 0xFF04,
281 i40e_aqc_opc_debug_modify_reg = 0xFF07,
282 i40e_aqc_opc_debug_dump_internals = 0xFF08,
285 /* command structures and indirect data structures */
287 /* Structure naming conventions:
288 * - no suffix for direct command descriptor structures
289 * - _data for indirect sent data
290 * - _resp for indirect return data (data which is both will use _data)
291 * - _completion for direct return data
292 * - _element_ for repeated elements (may also be _data or _resp)
294 * Command structures are expected to overlay the params.raw member of the basic
295 * descriptor, and as such cannot exceed 16 bytes in length.
298 /* This macro is used to generate a compilation error if a structure
299 * is not exactly the correct length. It gives a divide by zero error if the
300 * structure is not of the correct size, otherwise it creates an enum that is
303 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
304 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
306 /* This macro is used extensively to ensure that command structures are 16
307 * bytes in length as they have to map to the raw array of that size.
309 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
311 /* internal (0x00XX) commands */
313 /* Get version (direct 0x0001) */
314 struct i40e_aqc_get_version {
323 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
325 /* Send driver version (indirect 0x0002) */
326 struct i40e_aqc_driver_version {
330 u8 driver_subbuild_ver;
336 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
338 /* Queue Shutdown (direct 0x0003) */
339 struct i40e_aqc_queue_shutdown {
340 __le32 driver_unloading;
341 #define I40E_AQ_DRIVER_UNLOADING 0x1
345 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
347 /* Set PF context (0x0004, direct) */
348 struct i40e_aqc_set_pf_context {
353 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
355 /* Request resource ownership (direct 0x0008)
356 * Release resource ownership (direct 0x0009)
358 #define I40E_AQ_RESOURCE_NVM 1
359 #define I40E_AQ_RESOURCE_SDP 2
360 #define I40E_AQ_RESOURCE_ACCESS_READ 1
361 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2
362 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
363 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
365 struct i40e_aqc_request_resource {
369 __le32 resource_number;
373 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
375 /* Get function capabilities (indirect 0x000A)
376 * Get device capabilities (indirect 0x000B)
378 struct i40e_aqc_list_capabilites {
380 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1
388 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
390 struct i40e_aqc_list_capabilities_element_resp {
402 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
403 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002
404 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
405 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
406 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
407 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006
408 #define I40E_AQ_CAP_ID_SRIOV 0x0012
409 #define I40E_AQ_CAP_ID_VF 0x0013
410 #define I40E_AQ_CAP_ID_VMDQ 0x0014
411 #define I40E_AQ_CAP_ID_8021QBG 0x0015
412 #define I40E_AQ_CAP_ID_8021QBR 0x0016
413 #define I40E_AQ_CAP_ID_VSI 0x0017
414 #define I40E_AQ_CAP_ID_DCB 0x0018
415 #define I40E_AQ_CAP_ID_FCOE 0x0021
416 #define I40E_AQ_CAP_ID_ISCSI 0x0022
417 #define I40E_AQ_CAP_ID_RSS 0x0040
418 #define I40E_AQ_CAP_ID_RXQ 0x0041
419 #define I40E_AQ_CAP_ID_TXQ 0x0042
420 #define I40E_AQ_CAP_ID_MSIX 0x0043
421 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044
422 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
423 #define I40E_AQ_CAP_ID_1588 0x0046
424 #define I40E_AQ_CAP_ID_IWARP 0x0051
425 #define I40E_AQ_CAP_ID_LED 0x0061
426 #define I40E_AQ_CAP_ID_SDP 0x0062
427 #define I40E_AQ_CAP_ID_MDIO 0x0063
428 #define I40E_AQ_CAP_ID_FLEX10 0x00F1
429 #define I40E_AQ_CAP_ID_CEM 0x00F2
431 /* Set CPPM Configuration (direct 0x0103) */
432 struct i40e_aqc_cppm_configuration {
433 __le16 command_flags;
434 #define I40E_AQ_CPPM_EN_LTRC 0x0800
435 #define I40E_AQ_CPPM_EN_DMCTH 0x1000
436 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000
437 #define I40E_AQ_CPPM_EN_HPTC 0x4000
438 #define I40E_AQ_CPPM_EN_DMARC 0x8000
447 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
449 /* Set ARP Proxy command / response (indirect 0x0104) */
450 struct i40e_aqc_arp_proxy_data {
451 __le16 command_flags;
452 #define I40E_AQ_ARP_INIT_IPV4 0x0008
453 #define I40E_AQ_ARP_UNSUP_CTL 0x0010
454 #define I40E_AQ_ARP_ENA 0x0020
455 #define I40E_AQ_ARP_ADD_IPV4 0x0040
456 #define I40E_AQ_ARP_DEL_IPV4 0x0080
464 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
466 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
467 struct i40e_aqc_ns_proxy_data {
468 __le16 table_idx_mac_addr_0;
469 __le16 table_idx_mac_addr_1;
470 __le16 table_idx_ipv6_0;
471 __le16 table_idx_ipv6_1;
473 #define I40E_AQ_NS_PROXY_ADD_0 0x0100
474 #define I40E_AQ_NS_PROXY_DEL_0 0x0200
475 #define I40E_AQ_NS_PROXY_ADD_1 0x0400
476 #define I40E_AQ_NS_PROXY_DEL_1 0x0800
477 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000
478 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000
479 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000
480 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000
481 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001
482 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002
483 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004
486 u8 local_mac_addr[6];
487 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
491 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
493 /* Manage LAA Command (0x0106) - obsolete */
494 struct i40e_aqc_mng_laa {
495 __le16 command_flags;
496 #define I40E_AQ_LAA_FLAG_WR 0x8000
503 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);
505 /* Manage MAC Address Read Command (indirect 0x0107) */
506 struct i40e_aqc_mac_address_read {
507 __le16 command_flags;
508 #define I40E_AQC_LAN_ADDR_VALID 0x10
509 #define I40E_AQC_SAN_ADDR_VALID 0x20
510 #define I40E_AQC_PORT_ADDR_VALID 0x40
511 #define I40E_AQC_WOL_ADDR_VALID 0x80
512 #define I40E_AQC_MC_MAG_EN_VALID 0x100
513 #define I40E_AQC_ADDR_VALID_MASK 0x1F0
519 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
521 struct i40e_aqc_mac_address_read_data {
528 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
530 /* Manage MAC Address Write Command (0x0108) */
531 struct i40e_aqc_mac_address_write {
532 __le16 command_flags;
533 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
534 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
535 #define I40E_AQC_WRITE_TYPE_PORT 0x8000
536 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
537 #define I40E_AQC_WRITE_TYPE_MASK 0xC000
544 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
546 /* PXE commands (0x011x) */
548 /* Clear PXE Command and response (direct 0x0110) */
549 struct i40e_aqc_clear_pxe {
554 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
556 /* Switch configuration commands (0x02xx) */
558 /* Used by many indirect commands that only pass an seid and a buffer in the
561 struct i40e_aqc_switch_seid {
568 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
570 /* Get Switch Configuration command (indirect 0x0200)
571 * uses i40e_aqc_switch_seid for the descriptor
573 struct i40e_aqc_get_switch_config_header_resp {
579 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);
581 struct i40e_aqc_switch_config_element_resp {
583 #define I40E_AQ_SW_ELEM_TYPE_MAC 1
584 #define I40E_AQ_SW_ELEM_TYPE_PF 2
585 #define I40E_AQ_SW_ELEM_TYPE_VF 3
586 #define I40E_AQ_SW_ELEM_TYPE_EMP 4
587 #define I40E_AQ_SW_ELEM_TYPE_BMC 5
588 #define I40E_AQ_SW_ELEM_TYPE_PV 16
589 #define I40E_AQ_SW_ELEM_TYPE_VEB 17
590 #define I40E_AQ_SW_ELEM_TYPE_PA 18
591 #define I40E_AQ_SW_ELEM_TYPE_VSI 19
593 #define I40E_AQ_SW_ELEM_REV_1 1
596 __le16 downlink_seid;
599 #define I40E_AQ_CONN_TYPE_REGULAR 0x1
600 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2
601 #define I40E_AQ_CONN_TYPE_CASCADED 0x3
606 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
608 /* Get Switch Configuration (indirect 0x0200)
609 * an array of elements are returned in the response buffer
610 * the first in the array is the header, remainder are elements
612 struct i40e_aqc_get_switch_config_resp {
613 struct i40e_aqc_get_switch_config_header_resp header;
614 struct i40e_aqc_switch_config_element_resp element[1];
617 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
619 /* Add Statistics (direct 0x0201)
620 * Remove Statistics (direct 0x0202)
622 struct i40e_aqc_add_remove_statistics {
629 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
631 /* Set Port Parameters command (direct 0x0203) */
632 struct i40e_aqc_set_port_parameters {
633 __le16 command_flags;
634 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
635 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
636 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
637 __le16 bad_frame_vsi;
638 __le16 default_seid; /* reserved for command */
642 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
644 /* Get Switch Resource Allocation (indirect 0x0204) */
645 struct i40e_aqc_get_switch_resource_alloc {
646 u8 num_entries; /* reserved for command */
652 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
654 /* expect an array of these structs in the response buffer */
655 struct i40e_aqc_switch_resource_alloc_element_resp {
657 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0
658 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1
659 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2
660 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3
661 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4
662 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
663 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
664 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7
665 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
666 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
667 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
668 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
669 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
670 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
671 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
672 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
673 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
674 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
675 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
680 __le16 total_unalloced;
684 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
686 /* Add VSI (indirect 0x0210)
687 * this indirect command uses struct i40e_aqc_vsi_properties_data
688 * as the indirect buffer (128 bytes)
690 * Update VSI (indirect 0x211)
691 * uses the same data structure as Add VSI
693 * Get VSI (indirect 0x0212)
694 * uses the same completion and data structure as Add VSI
696 struct i40e_aqc_add_get_update_vsi {
699 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
700 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2
701 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3
706 #define I40E_AQ_VSI_TYPE_SHIFT 0x0
707 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
708 #define I40E_AQ_VSI_TYPE_VF 0x0
709 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1
710 #define I40E_AQ_VSI_TYPE_PF 0x2
711 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3
712 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4
717 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
719 struct i40e_aqc_add_get_update_vsi_completion {
728 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
730 struct i40e_aqc_vsi_properties_data {
731 /* first 96 byte are written by SW */
732 __le16 valid_sections;
733 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
734 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
735 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
736 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008
737 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
738 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
739 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
740 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
741 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
742 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
744 __le16 switch_id; /* 12bit id combined with flags below */
745 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
746 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
747 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
748 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
749 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
751 /* security section */
753 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
754 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
755 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
758 __le16 pvid; /* VLANS include priority bits */
761 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
762 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
763 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
764 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
765 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
766 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
767 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
768 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
769 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
770 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
771 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
772 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
773 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
774 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
775 u8 pvlan_reserved[3];
776 /* ingress egress up sections */
777 __le32 ingress_table; /* bitmap, 3 bits per up */
778 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
779 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
780 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
781 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3
782 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
783 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
784 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6
785 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
786 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
787 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9
788 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
789 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
790 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12
791 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
792 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
793 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15
794 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
795 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
796 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18
797 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
798 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
799 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21
800 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
801 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
802 __le32 egress_table; /* same defines as for ingress table */
803 /* cascaded PV section */
806 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
807 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
808 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
809 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
810 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
811 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02
812 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10
813 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
814 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
816 /* queue mapping section */
817 __le16 mapping_flags;
818 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
819 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
820 __le16 queue_mapping[16];
821 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0
822 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
823 __le16 tc_mapping[8];
824 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
825 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
826 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
827 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
828 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
829 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
830 /* queueing option section */
831 u8 queueing_opt_flags;
832 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
833 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
834 u8 queueing_opt_reserved[3];
835 /* scheduler section */
838 /* outer up section */
839 __le32 outer_up_table; /* same structure and defines as ingress table */
841 /* last 32 bytes are written by FW */
843 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
844 __le16 stat_counter_idx;
846 u8 resp_reserved[12];
849 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
851 /* Add Port Virtualizer (direct 0x0220)
852 * also used for update PV (direct 0x0221) but only flags are used
853 * (IS_CTRL_PORT only works on add PV)
855 struct i40e_aqc_add_update_pv {
856 __le16 command_flags;
857 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1
858 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
859 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
860 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8
862 __le16 connected_seid;
866 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
868 struct i40e_aqc_add_update_pv_completion {
869 /* reserved for update; for add also encodes error if rc == ENOSPC */
871 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1
872 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2
873 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
874 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
878 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
880 /* Get PV Params (direct 0x0222)
881 * uses i40e_aqc_switch_seid for the descriptor
884 struct i40e_aqc_get_pv_params_completion {
887 __le16 pv_flags; /* same flags as add_pv */
888 #define I40E_AQC_GET_PV_PV_TYPE 0x1
889 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
890 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
892 __le16 default_port_seid;
895 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
897 /* Add VEB (direct 0x0230) */
898 struct i40e_aqc_add_veb {
900 __le16 downlink_seid;
902 #define I40E_AQC_ADD_VEB_FLOATING 0x1
903 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
904 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
905 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
906 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
907 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
908 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8
913 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
915 struct i40e_aqc_add_veb_completion {
918 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
920 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1
921 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
922 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
923 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
924 __le16 statistic_index;
929 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
931 /* Get VEB Parameters (direct 0x0232)
932 * uses i40e_aqc_switch_seid for the descriptor
934 struct i40e_aqc_get_veb_parameters_completion {
937 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
938 __le16 statistic_index;
944 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
946 /* Delete Element (direct 0x0243)
947 * uses the generic i40e_aqc_switch_seid
950 /* Add MAC-VLAN (indirect 0x0250) */
952 /* used for the command for most vlan commands */
953 struct i40e_aqc_macvlan {
954 __le16 num_addresses;
956 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
957 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
958 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
959 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
964 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
966 /* indirect data for command and response */
967 struct i40e_aqc_add_macvlan_element_data {
971 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
972 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
973 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
974 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
976 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
977 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
978 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
979 /* response section */
981 #define I40E_AQC_MM_PERFECT_MATCH 0x01
982 #define I40E_AQC_MM_HASH_MATCH 0x02
983 #define I40E_AQC_MM_ERR_NO_RES 0xFF
987 struct i40e_aqc_add_remove_macvlan_completion {
988 __le16 perfect_mac_used;
989 __le16 perfect_mac_free;
990 __le16 unicast_hash_free;
991 __le16 multicast_hash_free;
996 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
998 /* Remove MAC-VLAN (indirect 0x0251)
999 * uses i40e_aqc_macvlan for the descriptor
1000 * data points to an array of num_addresses of elements
1003 struct i40e_aqc_remove_macvlan_element_data {
1007 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
1008 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02
1009 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
1010 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10
1014 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0
1015 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF
1016 u8 reply_reserved[3];
1019 /* Add VLAN (indirect 0x0252)
1020 * Remove VLAN (indirect 0x0253)
1021 * use the generic i40e_aqc_macvlan for the command
1023 struct i40e_aqc_add_remove_vlan_element_data {
1026 /* flags for add VLAN */
1027 #define I40E_AQC_ADD_VLAN_LOCAL 0x1
1028 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1
1029 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1030 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
1031 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
1032 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
1033 #define I40E_AQC_VLAN_PTYPE_SHIFT 3
1034 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1035 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
1036 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
1037 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
1038 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
1039 /* flags for remove VLAN */
1040 #define I40E_AQC_REMOVE_VLAN_ALL 0x1
1043 /* flags for add VLAN */
1044 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0
1045 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
1046 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
1047 /* flags for remove VLAN */
1048 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0
1049 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF
1053 struct i40e_aqc_add_remove_vlan_completion {
1061 /* Set VSI Promiscuous Modes (direct 0x0254) */
1062 struct i40e_aqc_set_vsi_promiscuous_modes {
1063 __le16 promiscuous_flags;
1065 /* flags used for both fields above */
1066 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
1067 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1068 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1069 #define I40E_AQC_SET_VSI_DEFAULT 0x08
1070 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
1072 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
1074 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF
1075 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
1079 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1081 /* Add S/E-tag command (direct 0x0255)
1082 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1084 struct i40e_aqc_add_tag {
1086 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
1088 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
1089 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1090 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1092 __le16 queue_number;
1096 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1098 struct i40e_aqc_add_remove_tag_completion {
1104 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1106 /* Remove S/E-tag command (direct 0x0256)
1107 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1109 struct i40e_aqc_remove_tag {
1111 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
1112 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1113 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1118 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);
1120 /* Add multicast E-Tag (direct 0x0257)
1121 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1122 * and no external data
1124 struct i40e_aqc_add_remove_mcast_etag {
1127 u8 num_unicast_etags;
1129 __le32 addr_high; /* address of array of 2-byte s-tags */
1133 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1135 struct i40e_aqc_add_remove_mcast_etag_completion {
1137 __le16 mcast_etags_used;
1138 __le16 mcast_etags_free;
1144 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1146 /* Update S/E-Tag (direct 0x0259) */
1147 struct i40e_aqc_update_tag {
1149 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
1150 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1151 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1157 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1159 struct i40e_aqc_update_tag_completion {
1165 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1167 /* Add Control Packet filter (direct 0x025A)
1168 * Remove Control Packet filter (direct 0x025B)
1169 * uses the i40e_aqc_add_oveb_cloud,
1170 * and the generic direct completion structure
1172 struct i40e_aqc_add_remove_control_packet_filter {
1176 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1177 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1178 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
1179 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1180 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
1182 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
1183 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
1184 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1189 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1191 struct i40e_aqc_add_remove_control_packet_filter_completion {
1192 __le16 mac_etype_used;
1194 __le16 mac_etype_free;
1199 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1201 /* Add Cloud filters (indirect 0x025C)
1202 * Remove Cloud filters (indirect 0x025D)
1203 * uses the i40e_aqc_add_remove_cloud_filters,
1204 * and the generic indirect completion structure
1206 struct i40e_aqc_add_remove_cloud_filters {
1210 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
1211 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
1212 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1218 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1220 struct i40e_aqc_add_remove_cloud_filters_element_data {
1234 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
1235 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
1236 I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1237 /* 0x0000 reserved */
1238 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001
1239 /* 0x0002 reserved */
1240 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1241 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
1242 /* 0x0005 reserved */
1243 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
1244 /* 0x0007 reserved */
1245 /* 0x0008 reserved */
1246 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1247 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1248 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1249 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1251 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
1252 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6
1253 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0
1254 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1255 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1257 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1258 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1259 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN 0
1260 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
1261 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NGE 2
1262 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3
1266 __le16 queue_number;
1267 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
1268 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \
1269 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1271 /* response section */
1272 u8 allocation_result;
1273 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
1274 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
1275 u8 response_reserved[7];
1278 struct i40e_aqc_remove_cloud_filters_completion {
1279 __le16 perfect_ovlan_used;
1280 __le16 perfect_ovlan_free;
1287 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1289 /* Add Mirror Rule (indirect or direct 0x0260)
1290 * Delete Mirror Rule (indirect or direct 0x0261)
1291 * note: some rule types (4,5) do not use an external buffer.
1292 * take care to set the flags correctly.
1294 struct i40e_aqc_add_delete_mirror_rule {
1297 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1298 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1299 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1300 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1301 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
1302 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1303 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1304 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
1306 __le16 destination; /* VSI for add, rule id for delete */
1307 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
1311 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1313 struct i40e_aqc_add_delete_mirror_rule_completion {
1315 __le16 rule_id; /* only used on add */
1316 __le16 mirror_rules_used;
1317 __le16 mirror_rules_free;
1322 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1326 /* PFC Ignore (direct 0x0301)
1327 * the command and response use the same descriptor structure
1329 struct i40e_aqc_pfc_ignore {
1331 u8 command_flags; /* unused on response */
1332 #define I40E_AQC_PFC_IGNORE_SET 0x80
1333 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0
1337 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1339 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1340 * with no parameters
1343 /* TX scheduler 0x04xx */
1345 /* Almost all the indirect commands use
1346 * this generic struct to pass the SEID in param0
1348 struct i40e_aqc_tx_sched_ind {
1355 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1357 /* Several commands respond with a set of queue set handles */
1358 struct i40e_aqc_qs_handles_resp {
1359 __le16 qs_handles[8];
1362 /* Configure VSI BW limits (direct 0x0400) */
1363 struct i40e_aqc_configure_vsi_bw_limit {
1368 u8 max_credit; /* 0-3, limit = 2^max */
1372 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1374 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1375 * responds with i40e_aqc_qs_handles_resp
1377 struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1380 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
1382 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1383 __le16 tc_bw_max[2];
1387 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
1389 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1390 * responds with i40e_aqc_qs_handles_resp
1392 struct i40e_aqc_configure_vsi_tc_bw_data {
1395 u8 tc_bw_credits[8];
1397 __le16 qs_handles[8];
1400 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
1402 /* Query vsi bw configuration (indirect 0x0408) */
1403 struct i40e_aqc_query_vsi_bw_config_resp {
1405 u8 tc_suspended_bits;
1407 __le16 qs_handles[8];
1409 __le16 port_bw_limit;
1411 u8 max_bw; /* 0-3, limit = 2^max */
1415 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
1417 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1418 struct i40e_aqc_query_vsi_ets_sla_config_resp {
1421 u8 share_credits[8];
1424 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1425 __le16 tc_bw_max[2];
1428 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
1430 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1431 struct i40e_aqc_configure_switching_comp_bw_limit {
1436 u8 max_bw; /* 0-3, limit = 2^max */
1440 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1442 /* Enable Physical Port ETS (indirect 0x0413)
1443 * Modify Physical Port ETS (indirect 0x0414)
1444 * Disable Physical Port ETS (indirect 0x0415)
1446 struct i40e_aqc_configure_switching_comp_ets_data {
1450 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1
1451 u8 tc_strict_priority_flags;
1453 u8 tc_bw_share_credits[8];
1457 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
1459 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1460 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1463 __le16 tc_bw_credit[8];
1465 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1466 __le16 tc_bw_max[2];
1470 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_switching_comp_ets_bw_limit_data);
1472 /* Configure Switching Component Bandwidth Allocation per Tc
1475 struct i40e_aqc_configure_switching_comp_bw_config_data {
1478 u8 absolute_credits; /* bool */
1479 u8 tc_bw_share_credits[8];
1483 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
1485 /* Query Switching Component Configuration (indirect 0x0418) */
1486 struct i40e_aqc_query_switching_comp_ets_config_resp {
1489 __le16 port_bw_limit;
1491 u8 tc_bw_max; /* 0-3, limit = 2^max */
1495 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
1497 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1498 struct i40e_aqc_query_port_ets_config_resp {
1502 u8 tc_strict_priority_bits;
1504 u8 tc_bw_share_credits[8];
1505 __le16 tc_bw_limits[8];
1507 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1508 __le16 tc_bw_max[2];
1512 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
1514 /* Query Switching Component Bandwidth Allocation per Traffic Type
1517 struct i40e_aqc_query_switching_comp_bw_config_resp {
1520 u8 absolute_credits_enable; /* bool */
1521 u8 tc_bw_share_credits[8];
1522 __le16 tc_bw_limits[8];
1524 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1525 __le16 tc_bw_max[2];
1528 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
1530 /* Suspend/resume port TX traffic
1531 * (direct 0x041B and 0x041C) uses the generic SEID struct
1534 /* Configure partition BW
1537 struct i40e_aqc_configure_partition_bw_data {
1538 __le16 pf_valid_bits;
1539 u8 min_bw[16]; /* guaranteed bandwidth */
1540 u8 max_bw[16]; /* bandwidth limit */
1543 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
1545 /* Get and set the active HMC resource profile and status.
1546 * (direct 0x0500) and (direct 0x0501)
1548 struct i40e_aq_get_set_hmc_resource_profile {
1554 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1556 enum i40e_aq_hmc_profile {
1557 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
1558 I40E_HMC_PROFILE_DEFAULT = 1,
1559 I40E_HMC_PROFILE_FAVOR_VF = 2,
1560 I40E_HMC_PROFILE_EQUAL = 3,
1563 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF
1564 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F
1566 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1568 /* set in param0 for get phy abilities to report qualified modules */
1569 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1570 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1572 enum i40e_aq_phy_type {
1573 I40E_PHY_TYPE_SGMII = 0x0,
1574 I40E_PHY_TYPE_1000BASE_KX = 0x1,
1575 I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
1576 I40E_PHY_TYPE_10GBASE_KR = 0x3,
1577 I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
1578 I40E_PHY_TYPE_XAUI = 0x5,
1579 I40E_PHY_TYPE_XFI = 0x6,
1580 I40E_PHY_TYPE_SFI = 0x7,
1581 I40E_PHY_TYPE_XLAUI = 0x8,
1582 I40E_PHY_TYPE_XLPPI = 0x9,
1583 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1584 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
1585 I40E_PHY_TYPE_10GBASE_AOC = 0xC,
1586 I40E_PHY_TYPE_40GBASE_AOC = 0xD,
1587 I40E_PHY_TYPE_100BASE_TX = 0x11,
1588 I40E_PHY_TYPE_1000BASE_T = 0x12,
1589 I40E_PHY_TYPE_10GBASE_T = 0x13,
1590 I40E_PHY_TYPE_10GBASE_SR = 0x14,
1591 I40E_PHY_TYPE_10GBASE_LR = 0x15,
1592 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1593 I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
1594 I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
1595 I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
1596 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
1597 I40E_PHY_TYPE_1000BASE_SX = 0x1B,
1598 I40E_PHY_TYPE_1000BASE_LX = 0x1C,
1599 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
1600 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
1604 #define I40E_LINK_SPEED_100MB_SHIFT 0x1
1605 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1606 #define I40E_LINK_SPEED_10GB_SHIFT 0x3
1607 #define I40E_LINK_SPEED_40GB_SHIFT 0x4
1608 #define I40E_LINK_SPEED_20GB_SHIFT 0x5
1610 enum i40e_aq_link_speed {
1611 I40E_LINK_SPEED_UNKNOWN = 0,
1612 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT),
1613 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT),
1614 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT),
1615 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT),
1616 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT)
1619 struct i40e_aqc_module_desc {
1627 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
1629 struct i40e_aq_get_phy_abilities_resp {
1630 __le32 phy_type; /* bitmap using the above enum for offsets */
1631 u8 link_speed; /* bitmap using the above enum bit patterns */
1633 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
1634 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
1635 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04
1636 #define I40E_AQ_PHY_LINK_ENABLED 0x08
1637 #define I40E_AQ_PHY_AN_ENABLED 0x10
1638 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20
1639 __le16 eee_capability;
1640 #define I40E_AQ_EEE_100BASE_TX 0x0002
1641 #define I40E_AQ_EEE_1000BASE_T 0x0004
1642 #define I40E_AQ_EEE_10GBASE_T 0x0008
1643 #define I40E_AQ_EEE_1000BASE_KX 0x0010
1644 #define I40E_AQ_EEE_10GBASE_KX4 0x0020
1645 #define I40E_AQ_EEE_10GBASE_KR 0x0040
1648 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
1652 u8 qualified_module_count;
1653 #define I40E_AQ_PHY_MAX_QMS 16
1654 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS];
1657 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
1659 /* Set PHY Config (direct 0x0601) */
1660 struct i40e_aq_set_phy_config { /* same bits as above in all */
1664 /* bits 0-2 use the values from get_phy_abilities_resp */
1665 #define I40E_AQ_PHY_ENABLE_LINK 0x08
1666 #define I40E_AQ_PHY_ENABLE_AN 0x10
1667 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
1668 __le16 eee_capability;
1674 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
1676 /* Set MAC Config command data structure (direct 0x0603) */
1677 struct i40e_aq_set_mac_config {
1678 __le16 max_frame_size;
1680 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
1681 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
1682 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
1683 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
1684 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
1685 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
1686 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
1687 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
1688 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
1689 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
1690 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
1691 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
1692 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
1693 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
1694 u8 tx_timer_priority; /* bitmap */
1695 __le16 tx_timer_value;
1696 __le16 fc_refresh_threshold;
1700 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
1702 /* Restart Auto-Negotiation (direct 0x605) */
1703 struct i40e_aqc_set_link_restart_an {
1705 #define I40E_AQ_PHY_RESTART_AN 0x02
1706 #define I40E_AQ_PHY_LINK_ENABLE 0x04
1710 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
1712 /* Get Link Status cmd & response data structure (direct 0x0607) */
1713 struct i40e_aqc_get_link_status {
1714 __le16 command_flags; /* only field set on command */
1715 #define I40E_AQ_LSE_MASK 0x3
1716 #define I40E_AQ_LSE_NOP 0x0
1717 #define I40E_AQ_LSE_DISABLE 0x2
1718 #define I40E_AQ_LSE_ENABLE 0x3
1719 /* only response uses this flag */
1720 #define I40E_AQ_LSE_IS_ENABLED 0x1
1721 u8 phy_type; /* i40e_aq_phy_type */
1722 u8 link_speed; /* i40e_aq_link_speed */
1724 #define I40E_AQ_LINK_UP 0x01 /* obsolete */
1725 #define I40E_AQ_LINK_UP_FUNCTION 0x01
1726 #define I40E_AQ_LINK_FAULT 0x02
1727 #define I40E_AQ_LINK_FAULT_TX 0x04
1728 #define I40E_AQ_LINK_FAULT_RX 0x08
1729 #define I40E_AQ_LINK_FAULT_REMOTE 0x10
1730 #define I40E_AQ_LINK_UP_PORT 0x20
1731 #define I40E_AQ_MEDIA_AVAILABLE 0x40
1732 #define I40E_AQ_SIGNAL_DETECT 0x80
1734 #define I40E_AQ_AN_COMPLETED 0x01
1735 #define I40E_AQ_LP_AN_ABILITY 0x02
1736 #define I40E_AQ_PD_FAULT 0x04
1737 #define I40E_AQ_FEC_EN 0x08
1738 #define I40E_AQ_PHY_LOW_POWER 0x10
1739 #define I40E_AQ_LINK_PAUSE_TX 0x20
1740 #define I40E_AQ_LINK_PAUSE_RX 0x40
1741 #define I40E_AQ_QUALIFIED_MODULE 0x80
1743 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01
1744 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02
1745 #define I40E_AQ_LINK_TX_SHIFT 0x02
1746 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT)
1747 #define I40E_AQ_LINK_TX_ACTIVE 0x00
1748 #define I40E_AQ_LINK_TX_DRAINED 0x01
1749 #define I40E_AQ_LINK_TX_FLUSHED 0x03
1750 #define I40E_AQ_LINK_FORCED_40G 0x10
1751 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
1752 __le16 max_frame_size;
1754 #define I40E_AQ_CONFIG_CRC_ENA 0x04
1755 #define I40E_AQ_CONFIG_PACING_MASK 0x78
1759 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
1761 /* Set event mask command (direct 0x613) */
1762 struct i40e_aqc_set_phy_int_mask {
1765 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
1766 #define I40E_AQ_EVENT_MEDIA_NA 0x0004
1767 #define I40E_AQ_EVENT_LINK_FAULT 0x0008
1768 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010
1769 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
1770 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040
1771 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080
1772 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
1773 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
1777 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
1779 /* Get Local AN advt register (direct 0x0614)
1780 * Set Local AN advt register (direct 0x0615)
1781 * Get Link Partner AN advt register (direct 0x0616)
1783 struct i40e_aqc_an_advt_reg {
1784 __le32 local_an_reg0;
1785 __le16 local_an_reg1;
1789 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
1791 /* Set Loopback mode (0x0618) */
1792 struct i40e_aqc_set_lb_mode {
1794 #define I40E_AQ_LB_PHY_LOCAL 0x01
1795 #define I40E_AQ_LB_PHY_REMOTE 0x02
1796 #define I40E_AQ_LB_MAC_LOCAL 0x04
1800 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
1802 /* Set PHY Debug command (0x0622) */
1803 struct i40e_aqc_set_phy_debug {
1805 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
1806 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
1807 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
1808 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
1809 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
1810 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
1811 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
1812 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
1816 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
1818 enum i40e_aq_phy_reg_type {
1819 I40E_AQC_PHY_REG_INTERNAL = 0x1,
1820 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
1821 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
1824 /* NVM Read command (indirect 0x0701)
1825 * NVM Erase commands (direct 0x0702)
1826 * NVM Update commands (indirect 0x0703)
1828 struct i40e_aqc_nvm_update {
1830 #define I40E_AQ_NVM_LAST_CMD 0x01
1831 #define I40E_AQ_NVM_FLASH_ONLY 0x80
1839 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
1841 /* NVM Config Read (indirect 0x0704) */
1842 struct i40e_aqc_nvm_config_read {
1844 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
1845 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0
1846 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1
1847 __le16 element_count;
1848 __le16 element_id; /* Feature/field ID */
1849 __le16 element_id_msw; /* MSWord of field ID */
1850 __le32 address_high;
1854 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
1856 /* NVM Config Write (indirect 0x0705) */
1857 struct i40e_aqc_nvm_config_write {
1859 __le16 element_count;
1861 __le32 address_high;
1865 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
1867 /* Used for 0x0704 as well as for 0x0705 commands */
1868 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1
1869 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
1870 #define I40E_AQ_ANVM_FEATURE 0
1871 #define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT)
1872 struct i40e_aqc_nvm_config_data_feature {
1874 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01
1875 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08
1876 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10
1877 __le16 feature_options;
1878 __le16 feature_selection;
1881 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
1883 struct i40e_aqc_nvm_config_data_immediate_field {
1886 __le16 field_options;
1890 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
1892 /* OEM Post Update (indirect 0x0720)
1893 * no command data struct used
1895 struct i40e_aqc_nvm_oem_post_update {
1896 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01
1901 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
1903 struct i40e_aqc_nvm_oem_post_update_buffer {
1910 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
1912 /* Send to PF command (indirect 0x0801) id is only used by PF
1913 * Send to VF command (indirect 0x0802) id is only used by PF
1914 * Send to Peer PF command (indirect 0x0803)
1916 struct i40e_aqc_pf_vf_message {
1923 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
1925 /* Alternate structure */
1927 /* Direct write (direct 0x0900)
1928 * Direct read (direct 0x0902)
1930 struct i40e_aqc_alternate_write {
1937 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
1939 /* Indirect write (indirect 0x0901)
1940 * Indirect read (indirect 0x0903)
1943 struct i40e_aqc_alternate_ind_write {
1950 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
1952 /* Done alternate write (direct 0x0904)
1955 struct i40e_aqc_alternate_write_done {
1957 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1
1958 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
1959 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1
1960 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2
1964 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
1966 /* Set OEM mode (direct 0x0905) */
1967 struct i40e_aqc_alternate_set_mode {
1969 #define I40E_AQ_ALTERNATE_MODE_NONE 0
1970 #define I40E_AQ_ALTERNATE_MODE_OEM 1
1974 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
1976 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
1978 /* async events 0x10xx */
1980 /* Lan Queue Overflow Event (direct, 0x1001) */
1981 struct i40e_aqc_lan_overflow {
1982 __le32 prtdcb_rupto;
1987 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
1989 /* Get LLDP MIB (indirect 0x0A00) */
1990 struct i40e_aqc_lldp_get_mib {
1993 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
1994 #define I40E_AQ_LLDP_MIB_LOCAL 0x0
1995 #define I40E_AQ_LLDP_MIB_REMOTE 0x1
1996 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
1997 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
1998 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
1999 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
2000 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
2001 #define I40E_AQ_LLDP_TX_SHIFT 0x4
2002 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT)
2003 /* TX pause flags use I40E_AQ_LINK_TX_* above */
2011 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
2013 /* Configure LLDP MIB Change Event (direct 0x0A01)
2014 * also used for the event (with type in the command field)
2016 struct i40e_aqc_lldp_update_mib {
2018 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
2019 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
2025 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
2027 /* Add LLDP TLV (indirect 0x0A02)
2028 * Delete LLDP TLV (indirect 0x0A04)
2030 struct i40e_aqc_lldp_add_tlv {
2031 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2039 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
2041 /* Update LLDP TLV (indirect 0x0A03) */
2042 struct i40e_aqc_lldp_update_tlv {
2043 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2052 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
2054 /* Stop LLDP (direct 0x0A05) */
2055 struct i40e_aqc_lldp_stop {
2057 #define I40E_AQ_LLDP_AGENT_STOP 0x0
2058 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
2062 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
2064 /* Start LLDP (direct 0x0A06) */
2066 struct i40e_aqc_lldp_start {
2068 #define I40E_AQ_LLDP_AGENT_START 0x1
2072 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
2074 /* Get CEE DCBX Oper Config (0x0A07)
2075 * uses the generic descriptor struct
2076 * returns below as indirect response
2079 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2080 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2081 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2082 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2083 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2084 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2085 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2086 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2087 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2088 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2089 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2090 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2091 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8
2092 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT)
2093 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB
2094 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT)
2095 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10
2096 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT)
2098 struct i40e_aqc_get_cee_dcb_cfg_v1_resp {
2106 __le16 oper_app_prio;
2111 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp);
2113 struct i40e_aqc_get_cee_dcb_cfg_resp {
2118 __le16 oper_app_prio;
2123 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp);
2125 /* Set Local LLDP MIB (indirect 0x0A08)
2126 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx
2128 struct i40e_aqc_lldp_set_local_mib {
2129 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0
2130 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \
2131 SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
2132 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0
2133 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1)
2134 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \
2135 SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT)
2136 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1
2141 __le32 address_high;
2145 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib);
2147 /* Stop/Start LLDP Agent (direct 0x0A09)
2148 * Used for stopping/starting specific LLDP agent. e.g. DCBx
2150 struct i40e_aqc_lldp_stop_start_specific_agent {
2151 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0
2152 #define I40E_AQC_START_SPECIFIC_AGENT_MASK (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT)
2157 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent);
2159 /* Add Udp Tunnel command and completion (direct 0x0B00) */
2160 struct i40e_aqc_add_udp_tunnel {
2164 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
2165 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01
2166 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10
2170 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2172 struct i40e_aqc_add_udp_tunnel_completion {
2174 u8 filter_entry_index;
2176 #define I40E_AQC_SINGLE_PF 0x0
2177 #define I40E_AQC_MULTIPLE_PFS 0x1
2182 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2184 /* remove UDP Tunnel command (0x0B01) */
2185 struct i40e_aqc_remove_udp_tunnel {
2187 u8 index; /* 0 to 15 */
2191 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2193 struct i40e_aqc_del_udp_tunnel_completion {
2195 u8 index; /* 0 to 15 */
2197 u8 total_filters_used;
2201 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2203 /* tunnel key structure 0x0B10 */
2205 struct i40e_aqc_tunnel_key_structure {
2208 u8 key1_len; /* 0 to 15 */
2209 u8 key2_len; /* 0 to 15 */
2211 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2212 /* response flags */
2213 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2214 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2215 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2216 u8 network_key_index;
2217 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
2218 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1
2219 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
2220 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3
2224 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2226 /* OEM mode commands (direct 0xFE0x) */
2227 struct i40e_aqc_oem_param_change {
2229 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0
2230 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1
2231 #define I40E_AQ_OEM_PARAM_MAC 2
2232 __le32 param_value1;
2233 __le16 param_value2;
2237 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2239 struct i40e_aqc_oem_state_change {
2241 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0
2242 #define I40E_AQ_OEM_STATE_LINK_UP 0x1
2246 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2248 /* Initialize OCSD (0xFE02, direct) */
2249 struct i40e_aqc_opc_oem_ocsd_initialize {
2252 __le32 ocsd_memory_block_addr_high;
2253 __le32 ocsd_memory_block_addr_low;
2254 __le32 requested_update_interval;
2257 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);
2259 /* Initialize OCBB (0xFE03, direct) */
2260 struct i40e_aqc_opc_oem_ocbb_initialize {
2263 __le32 ocbb_memory_block_addr_high;
2264 __le32 ocbb_memory_block_addr_low;
2268 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);
2270 /* debug commands */
2272 /* get device id (0xFF00) uses the generic structure */
2274 /* set test more (0xFF01, internal) */
2276 struct i40e_acq_set_test_mode {
2278 #define I40E_AQ_TEST_PARTIAL 0
2279 #define I40E_AQ_TEST_FULL 1
2280 #define I40E_AQ_TEST_NVM 2
2283 #define I40E_AQ_TEST_OPEN 0
2284 #define I40E_AQ_TEST_CLOSE 1
2285 #define I40E_AQ_TEST_INC 2
2287 __le32 address_high;
2291 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2293 /* Debug Read Register command (0xFF03)
2294 * Debug Write Register command (0xFF04)
2296 struct i40e_aqc_debug_reg_read_write {
2303 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2305 /* Scatter/gather Reg Read (indirect 0xFF05)
2306 * Scatter/gather Reg Write (indirect 0xFF06)
2309 /* i40e_aq_desc is used for the command */
2310 struct i40e_aqc_debug_reg_sg_element_data {
2315 /* Debug Modify register (direct 0xFF07) */
2316 struct i40e_aqc_debug_modify_reg {
2323 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2325 /* dump internal data (0xFF08, indirect) */
2327 #define I40E_AQ_CLUSTER_ID_AUX 0
2328 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1
2329 #define I40E_AQ_CLUSTER_ID_TXSCHED 2
2330 #define I40E_AQ_CLUSTER_ID_HMC 3
2331 #define I40E_AQ_CLUSTER_ID_MAC0 4
2332 #define I40E_AQ_CLUSTER_ID_MAC1 5
2333 #define I40E_AQ_CLUSTER_ID_MAC2 6
2334 #define I40E_AQ_CLUSTER_ID_MAC3 7
2335 #define I40E_AQ_CLUSTER_ID_DCB 8
2336 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9
2337 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10
2338 #define I40E_AQ_CLUSTER_ID_ALTRAM 11
2340 struct i40e_aqc_debug_dump_internals {
2345 __le32 address_high;
2349 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2351 struct i40e_aqc_debug_modify_internals {
2353 u8 cluster_specific_params[7];
2354 __le32 address_high;
2358 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);