1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
5 #ifndef _I40E_ADMINQ_CMD_H_
6 #define _I40E_ADMINQ_CMD_H_
8 /* This header file defines the i40e Admin Queue commands and is shared between
9 * i40e Firmware and Software.
11 * This file needs to comply with the Linux Kernel coding style.
14 #define I40E_FW_API_VERSION_MAJOR 0x0001
15 #define I40E_FW_API_VERSION_MINOR_X722 0x000A
16 #define I40E_FW_API_VERSION_MINOR_X710 0x000A
18 #define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \
19 I40E_FW_API_VERSION_MINOR_X710 : \
20 I40E_FW_API_VERSION_MINOR_X722)
22 /* API version 1.7 implements additional link and PHY-specific APIs */
23 #define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007
24 /* API version 1.9 for X722 implements additional link and PHY-specific APIs */
25 #define I40E_MINOR_VER_GET_LINK_INFO_X722 0x0009
26 /* API version 1.6 for X722 devices adds ability to stop FW LLDP agent */
27 #define I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722 0x0006
28 /* API version 1.10 for X722 devices adds ability to request FEC encoding */
29 #define I40E_MINOR_VER_FW_REQUEST_FEC_X722 0x000A
55 /* Flags sub-structure
56 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
57 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
60 /* command flags and offsets*/
61 #define I40E_AQ_FLAG_DD_SHIFT 0
62 #define I40E_AQ_FLAG_CMP_SHIFT 1
63 #define I40E_AQ_FLAG_ERR_SHIFT 2
64 #define I40E_AQ_FLAG_VFE_SHIFT 3
65 #define I40E_AQ_FLAG_LB_SHIFT 9
66 #define I40E_AQ_FLAG_RD_SHIFT 10
67 #define I40E_AQ_FLAG_VFC_SHIFT 11
68 #define I40E_AQ_FLAG_BUF_SHIFT 12
69 #define I40E_AQ_FLAG_SI_SHIFT 13
70 #define I40E_AQ_FLAG_EI_SHIFT 14
71 #define I40E_AQ_FLAG_FE_SHIFT 15
73 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
74 #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */
75 #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
76 #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */
77 #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
78 #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
79 #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */
80 #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
81 #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
82 #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */
83 #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */
86 enum i40e_admin_queue_err {
87 I40E_AQ_RC_OK = 0, /* success */
88 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */
89 I40E_AQ_RC_ENOENT = 2, /* No such element */
90 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */
91 I40E_AQ_RC_EINTR = 4, /* operation interrupted */
92 I40E_AQ_RC_EIO = 5, /* I/O error */
93 I40E_AQ_RC_ENXIO = 6, /* No such resource */
94 I40E_AQ_RC_E2BIG = 7, /* Arg too long */
95 I40E_AQ_RC_EAGAIN = 8, /* Try again */
96 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */
97 I40E_AQ_RC_EACCES = 10, /* Permission denied */
98 I40E_AQ_RC_EFAULT = 11, /* Bad address */
99 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */
100 I40E_AQ_RC_EEXIST = 13, /* object already exists */
101 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */
102 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */
103 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
104 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */
105 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */
106 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
107 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
108 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
109 I40E_AQ_RC_EFBIG = 22, /* File too large */
112 /* Admin Queue command opcodes */
113 enum i40e_admin_queue_opc {
115 i40e_aqc_opc_get_version = 0x0001,
116 i40e_aqc_opc_driver_version = 0x0002,
117 i40e_aqc_opc_queue_shutdown = 0x0003,
118 i40e_aqc_opc_set_pf_context = 0x0004,
120 /* resource ownership */
121 i40e_aqc_opc_request_resource = 0x0008,
122 i40e_aqc_opc_release_resource = 0x0009,
124 i40e_aqc_opc_list_func_capabilities = 0x000A,
125 i40e_aqc_opc_list_dev_capabilities = 0x000B,
128 i40e_aqc_opc_set_proxy_config = 0x0104,
129 i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105,
132 i40e_aqc_opc_mac_address_read = 0x0107,
133 i40e_aqc_opc_mac_address_write = 0x0108,
136 i40e_aqc_opc_clear_pxe_mode = 0x0110,
139 i40e_aqc_opc_set_wol_filter = 0x0120,
140 i40e_aqc_opc_get_wake_reason = 0x0121,
141 i40e_aqc_opc_clear_all_wol_filters = 0x025E,
143 /* internal switch commands */
144 i40e_aqc_opc_get_switch_config = 0x0200,
145 i40e_aqc_opc_add_statistics = 0x0201,
146 i40e_aqc_opc_remove_statistics = 0x0202,
147 i40e_aqc_opc_set_port_parameters = 0x0203,
148 i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
149 i40e_aqc_opc_set_switch_config = 0x0205,
150 i40e_aqc_opc_rx_ctl_reg_read = 0x0206,
151 i40e_aqc_opc_rx_ctl_reg_write = 0x0207,
153 i40e_aqc_opc_add_vsi = 0x0210,
154 i40e_aqc_opc_update_vsi_parameters = 0x0211,
155 i40e_aqc_opc_get_vsi_parameters = 0x0212,
157 i40e_aqc_opc_add_pv = 0x0220,
158 i40e_aqc_opc_update_pv_parameters = 0x0221,
159 i40e_aqc_opc_get_pv_parameters = 0x0222,
161 i40e_aqc_opc_add_veb = 0x0230,
162 i40e_aqc_opc_update_veb_parameters = 0x0231,
163 i40e_aqc_opc_get_veb_parameters = 0x0232,
165 i40e_aqc_opc_delete_element = 0x0243,
167 i40e_aqc_opc_add_macvlan = 0x0250,
168 i40e_aqc_opc_remove_macvlan = 0x0251,
169 i40e_aqc_opc_add_vlan = 0x0252,
170 i40e_aqc_opc_remove_vlan = 0x0253,
171 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
172 i40e_aqc_opc_add_tag = 0x0255,
173 i40e_aqc_opc_remove_tag = 0x0256,
174 i40e_aqc_opc_add_multicast_etag = 0x0257,
175 i40e_aqc_opc_remove_multicast_etag = 0x0258,
176 i40e_aqc_opc_update_tag = 0x0259,
177 i40e_aqc_opc_add_control_packet_filter = 0x025A,
178 i40e_aqc_opc_remove_control_packet_filter = 0x025B,
179 i40e_aqc_opc_add_cloud_filters = 0x025C,
180 i40e_aqc_opc_remove_cloud_filters = 0x025D,
181 i40e_aqc_opc_clear_wol_switch_filters = 0x025E,
182 i40e_aqc_opc_replace_cloud_filters = 0x025F,
184 i40e_aqc_opc_add_mirror_rule = 0x0260,
185 i40e_aqc_opc_delete_mirror_rule = 0x0261,
187 /* Dynamic Device Personalization */
188 i40e_aqc_opc_write_personalization_profile = 0x0270,
189 i40e_aqc_opc_get_personalization_profile_list = 0x0271,
192 i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
193 i40e_aqc_opc_dcb_updated = 0x0302,
194 i40e_aqc_opc_set_dcb_parameters = 0x0303,
197 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
198 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
199 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
200 i40e_aqc_opc_query_vsi_bw_config = 0x0408,
201 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
202 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
204 i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
205 i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
206 i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
207 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
208 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
209 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
210 i40e_aqc_opc_query_port_ets_config = 0x0419,
211 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
212 i40e_aqc_opc_suspend_port_tx = 0x041B,
213 i40e_aqc_opc_resume_port_tx = 0x041C,
214 i40e_aqc_opc_configure_partition_bw = 0x041D,
216 i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
217 i40e_aqc_opc_set_hmc_resource_profile = 0x0501,
220 i40e_aqc_opc_get_phy_abilities = 0x0600,
221 i40e_aqc_opc_set_phy_config = 0x0601,
222 i40e_aqc_opc_set_mac_config = 0x0603,
223 i40e_aqc_opc_set_link_restart_an = 0x0605,
224 i40e_aqc_opc_get_link_status = 0x0607,
225 i40e_aqc_opc_set_phy_int_mask = 0x0613,
226 i40e_aqc_opc_get_local_advt_reg = 0x0614,
227 i40e_aqc_opc_set_local_advt_reg = 0x0615,
228 i40e_aqc_opc_get_partner_advt = 0x0616,
229 i40e_aqc_opc_set_lb_modes = 0x0618,
230 i40e_aqc_opc_get_phy_wol_caps = 0x0621,
231 i40e_aqc_opc_set_phy_debug = 0x0622,
232 i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
233 i40e_aqc_opc_run_phy_activity = 0x0626,
234 i40e_aqc_opc_set_phy_register = 0x0628,
235 i40e_aqc_opc_get_phy_register = 0x0629,
238 i40e_aqc_opc_nvm_read = 0x0701,
239 i40e_aqc_opc_nvm_erase = 0x0702,
240 i40e_aqc_opc_nvm_update = 0x0703,
241 i40e_aqc_opc_nvm_config_read = 0x0704,
242 i40e_aqc_opc_nvm_config_write = 0x0705,
243 i40e_aqc_opc_nvm_progress = 0x0706,
244 i40e_aqc_opc_oem_post_update = 0x0720,
245 i40e_aqc_opc_thermal_sensor = 0x0721,
247 /* virtualization commands */
248 i40e_aqc_opc_send_msg_to_pf = 0x0801,
249 i40e_aqc_opc_send_msg_to_vf = 0x0802,
250 i40e_aqc_opc_send_msg_to_peer = 0x0803,
252 /* alternate structure */
253 i40e_aqc_opc_alternate_write = 0x0900,
254 i40e_aqc_opc_alternate_write_indirect = 0x0901,
255 i40e_aqc_opc_alternate_read = 0x0902,
256 i40e_aqc_opc_alternate_read_indirect = 0x0903,
257 i40e_aqc_opc_alternate_write_done = 0x0904,
258 i40e_aqc_opc_alternate_set_mode = 0x0905,
259 i40e_aqc_opc_alternate_clear_port = 0x0906,
262 i40e_aqc_opc_lldp_get_mib = 0x0A00,
263 i40e_aqc_opc_lldp_update_mib = 0x0A01,
264 i40e_aqc_opc_lldp_add_tlv = 0x0A02,
265 i40e_aqc_opc_lldp_update_tlv = 0x0A03,
266 i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
267 i40e_aqc_opc_lldp_stop = 0x0A05,
268 i40e_aqc_opc_lldp_start = 0x0A06,
269 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07,
270 i40e_aqc_opc_lldp_set_local_mib = 0x0A08,
271 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09,
272 i40e_aqc_opc_lldp_restore = 0x0A0A,
274 /* Tunnel commands */
275 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
276 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
277 i40e_aqc_opc_set_rss_key = 0x0B02,
278 i40e_aqc_opc_set_rss_lut = 0x0B03,
279 i40e_aqc_opc_get_rss_key = 0x0B04,
280 i40e_aqc_opc_get_rss_lut = 0x0B05,
283 i40e_aqc_opc_event_lan_overflow = 0x1001,
286 i40e_aqc_opc_oem_parameter_change = 0xFE00,
287 i40e_aqc_opc_oem_device_status_change = 0xFE01,
288 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02,
289 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03,
292 i40e_aqc_opc_debug_read_reg = 0xFF03,
293 i40e_aqc_opc_debug_write_reg = 0xFF04,
294 i40e_aqc_opc_debug_modify_reg = 0xFF07,
295 i40e_aqc_opc_debug_dump_internals = 0xFF08,
298 /* command structures and indirect data structures */
300 /* Structure naming conventions:
301 * - no suffix for direct command descriptor structures
302 * - _data for indirect sent data
303 * - _resp for indirect return data (data which is both will use _data)
304 * - _completion for direct return data
305 * - _element_ for repeated elements (may also be _data or _resp)
307 * Command structures are expected to overlay the params.raw member of the basic
308 * descriptor, and as such cannot exceed 16 bytes in length.
311 /* This macro is used to generate a compilation error if a structure
312 * is not exactly the correct length. It gives a divide by zero error if the
313 * structure is not of the correct size, otherwise it creates an enum that is
316 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
317 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
319 /* This macro is used extensively to ensure that command structures are 16
320 * bytes in length as they have to map to the raw array of that size.
322 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
324 /* internal (0x00XX) commands */
326 /* Get version (direct 0x0001) */
327 struct i40e_aqc_get_version {
336 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
338 /* Send driver version (indirect 0x0002) */
339 struct i40e_aqc_driver_version {
343 u8 driver_subbuild_ver;
349 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
351 /* Queue Shutdown (direct 0x0003) */
352 struct i40e_aqc_queue_shutdown {
353 __le32 driver_unloading;
354 #define I40E_AQ_DRIVER_UNLOADING 0x1
358 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
360 /* Set PF context (0x0004, direct) */
361 struct i40e_aqc_set_pf_context {
366 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
368 /* Request resource ownership (direct 0x0008)
369 * Release resource ownership (direct 0x0009)
371 #define I40E_AQ_RESOURCE_NVM 1
372 #define I40E_AQ_RESOURCE_SDP 2
373 #define I40E_AQ_RESOURCE_ACCESS_READ 1
374 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2
375 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
376 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
378 struct i40e_aqc_request_resource {
382 __le32 resource_number;
386 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
388 /* Get function capabilities (indirect 0x000A)
389 * Get device capabilities (indirect 0x000B)
391 struct i40e_aqc_list_capabilites {
393 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1
401 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
403 struct i40e_aqc_list_capabilities_element_resp {
415 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
416 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002
417 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
418 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
419 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
420 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006
421 #define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008
422 #define I40E_AQ_CAP_ID_SRIOV 0x0012
423 #define I40E_AQ_CAP_ID_VF 0x0013
424 #define I40E_AQ_CAP_ID_VMDQ 0x0014
425 #define I40E_AQ_CAP_ID_8021QBG 0x0015
426 #define I40E_AQ_CAP_ID_8021QBR 0x0016
427 #define I40E_AQ_CAP_ID_VSI 0x0017
428 #define I40E_AQ_CAP_ID_DCB 0x0018
429 #define I40E_AQ_CAP_ID_FCOE 0x0021
430 #define I40E_AQ_CAP_ID_ISCSI 0x0022
431 #define I40E_AQ_CAP_ID_RSS 0x0040
432 #define I40E_AQ_CAP_ID_RXQ 0x0041
433 #define I40E_AQ_CAP_ID_TXQ 0x0042
434 #define I40E_AQ_CAP_ID_MSIX 0x0043
435 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044
436 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
437 #define I40E_AQ_CAP_ID_1588 0x0046
438 #define I40E_AQ_CAP_ID_IWARP 0x0051
439 #define I40E_AQ_CAP_ID_LED 0x0061
440 #define I40E_AQ_CAP_ID_SDP 0x0062
441 #define I40E_AQ_CAP_ID_MDIO 0x0063
442 #define I40E_AQ_CAP_ID_WSR_PROT 0x0064
443 #define I40E_AQ_CAP_ID_NVM_MGMT 0x0080
444 #define I40E_AQ_CAP_ID_FLEX10 0x00F1
445 #define I40E_AQ_CAP_ID_CEM 0x00F2
447 /* Set CPPM Configuration (direct 0x0103) */
448 struct i40e_aqc_cppm_configuration {
449 __le16 command_flags;
450 #define I40E_AQ_CPPM_EN_LTRC 0x0800
451 #define I40E_AQ_CPPM_EN_DMCTH 0x1000
452 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000
453 #define I40E_AQ_CPPM_EN_HPTC 0x4000
454 #define I40E_AQ_CPPM_EN_DMARC 0x8000
463 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
465 /* Set ARP Proxy command / response (indirect 0x0104) */
466 struct i40e_aqc_arp_proxy_data {
467 __le16 command_flags;
468 #define I40E_AQ_ARP_INIT_IPV4 0x0800
469 #define I40E_AQ_ARP_UNSUP_CTL 0x1000
470 #define I40E_AQ_ARP_ENA 0x2000
471 #define I40E_AQ_ARP_ADD_IPV4 0x4000
472 #define I40E_AQ_ARP_DEL_IPV4 0x8000
474 __le32 enabled_offloads;
475 #define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020
476 #define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800
482 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
484 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
485 struct i40e_aqc_ns_proxy_data {
486 __le16 table_idx_mac_addr_0;
487 __le16 table_idx_mac_addr_1;
488 __le16 table_idx_ipv6_0;
489 __le16 table_idx_ipv6_1;
491 #define I40E_AQ_NS_PROXY_ADD_0 0x0001
492 #define I40E_AQ_NS_PROXY_DEL_0 0x0002
493 #define I40E_AQ_NS_PROXY_ADD_1 0x0004
494 #define I40E_AQ_NS_PROXY_DEL_1 0x0008
495 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010
496 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020
497 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040
498 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080
499 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100
500 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200
501 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400
502 #define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800
503 #define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000
506 u8 local_mac_addr[6];
507 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
511 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
513 /* Manage LAA Command (0x0106) - obsolete */
514 struct i40e_aqc_mng_laa {
515 __le16 command_flags;
516 #define I40E_AQ_LAA_FLAG_WR 0x8000
523 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);
525 /* Manage MAC Address Read Command (indirect 0x0107) */
526 struct i40e_aqc_mac_address_read {
527 __le16 command_flags;
528 #define I40E_AQC_LAN_ADDR_VALID 0x10
529 #define I40E_AQC_SAN_ADDR_VALID 0x20
530 #define I40E_AQC_PORT_ADDR_VALID 0x40
531 #define I40E_AQC_WOL_ADDR_VALID 0x80
532 #define I40E_AQC_MC_MAG_EN_VALID 0x100
533 #define I40E_AQC_WOL_PRESERVE_STATUS 0x200
534 #define I40E_AQC_ADDR_VALID_MASK 0x3F0
540 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
542 struct i40e_aqc_mac_address_read_data {
549 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
551 /* Manage MAC Address Write Command (0x0108) */
552 struct i40e_aqc_mac_address_write {
553 __le16 command_flags;
554 #define I40E_AQC_MC_MAG_EN 0x0100
555 #define I40E_AQC_WOL_PRESERVE_ON_PFR 0x0200
556 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
557 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
558 #define I40E_AQC_WRITE_TYPE_PORT 0x8000
559 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
560 #define I40E_AQC_WRITE_TYPE_MASK 0xC000
567 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
569 /* PXE commands (0x011x) */
571 /* Clear PXE Command and response (direct 0x0110) */
572 struct i40e_aqc_clear_pxe {
577 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
579 /* Set WoL Filter (0x0120) */
581 struct i40e_aqc_set_wol_filter {
583 #define I40E_AQC_MAX_NUM_WOL_FILTERS 8
584 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15
585 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \
586 I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT)
588 #define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0
589 #define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \
590 I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT)
592 #define I40E_AQC_SET_WOL_FILTER 0x8000
593 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000
594 #define I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR 0x2000
595 #define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0
596 #define I40E_AQC_SET_WOL_FILTER_ACTION_SET 1
598 #define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000
599 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000
605 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter);
607 struct i40e_aqc_set_wol_filter_data {
612 I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data);
614 /* Get Wake Reason (0x0121) */
616 struct i40e_aqc_get_wake_reason_completion {
619 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0
620 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \
621 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT)
622 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8
623 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \
624 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT)
628 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion);
630 /* Switch configuration commands (0x02xx) */
632 /* Used by many indirect commands that only pass an seid and a buffer in the
635 struct i40e_aqc_switch_seid {
642 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
644 /* Get Switch Configuration command (indirect 0x0200)
645 * uses i40e_aqc_switch_seid for the descriptor
647 struct i40e_aqc_get_switch_config_header_resp {
653 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);
655 struct i40e_aqc_switch_config_element_resp {
657 #define I40E_AQ_SW_ELEM_TYPE_MAC 1
658 #define I40E_AQ_SW_ELEM_TYPE_PF 2
659 #define I40E_AQ_SW_ELEM_TYPE_VF 3
660 #define I40E_AQ_SW_ELEM_TYPE_EMP 4
661 #define I40E_AQ_SW_ELEM_TYPE_BMC 5
662 #define I40E_AQ_SW_ELEM_TYPE_PV 16
663 #define I40E_AQ_SW_ELEM_TYPE_VEB 17
664 #define I40E_AQ_SW_ELEM_TYPE_PA 18
665 #define I40E_AQ_SW_ELEM_TYPE_VSI 19
667 #define I40E_AQ_SW_ELEM_REV_1 1
670 __le16 downlink_seid;
673 #define I40E_AQ_CONN_TYPE_REGULAR 0x1
674 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2
675 #define I40E_AQ_CONN_TYPE_CASCADED 0x3
680 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
682 /* Get Switch Configuration (indirect 0x0200)
683 * an array of elements are returned in the response buffer
684 * the first in the array is the header, remainder are elements
686 struct i40e_aqc_get_switch_config_resp {
687 struct i40e_aqc_get_switch_config_header_resp header;
688 struct i40e_aqc_switch_config_element_resp element[1];
691 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
693 /* Add Statistics (direct 0x0201)
694 * Remove Statistics (direct 0x0202)
696 struct i40e_aqc_add_remove_statistics {
703 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
705 /* Set Port Parameters command (direct 0x0203) */
706 struct i40e_aqc_set_port_parameters {
707 __le16 command_flags;
708 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
709 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
710 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
711 __le16 bad_frame_vsi;
712 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0
713 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF
714 __le16 default_seid; /* reserved for command */
718 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
720 /* Get Switch Resource Allocation (indirect 0x0204) */
721 struct i40e_aqc_get_switch_resource_alloc {
722 u8 num_entries; /* reserved for command */
728 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
730 /* expect an array of these structs in the response buffer */
731 struct i40e_aqc_switch_resource_alloc_element_resp {
733 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0
734 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1
735 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2
736 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3
737 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4
738 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
739 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
740 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7
741 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
742 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
743 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
744 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
745 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
746 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
747 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
748 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
749 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
750 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
751 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
756 __le16 total_unalloced;
760 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
762 /* Set Switch Configuration (direct 0x0205) */
763 struct i40e_aqc_set_switch_config {
765 /* flags used for both fields below */
766 #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001
767 #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002
768 #define I40E_AQ_SET_SWITCH_CFG_HW_ATR_EVICT 0x0004
770 /* The ethertype in switch_tag is dropped on ingress and used
771 * internally by the switch. Set this to zero for the default
772 * of 0x88a8 (802.1ad). Should be zero for firmware API
773 * versions lower than 1.7.
776 /* The ethertypes in first_tag and second_tag are used to
777 * match the outer and inner VLAN tags (respectively) when HW
778 * double VLAN tagging is enabled via the set port parameters
779 * AQ command. Otherwise these are both ignored. Set them to
780 * zero for their defaults of 0x8100 (802.1Q). Should be zero
781 * for firmware API versions lower than 1.7.
785 /* Next byte is split into following:
786 * Bit 7 : 0 : No action, 1: Switch to mode defined by bits 6:0
787 * Bit 6 : 0 : Destination Port, 1: source port
792 * 3: Both TCP and UDP
795 * 1: L4 port only mode
796 * 2: non-tunneled mode
799 #define I40E_AQ_SET_SWITCH_BIT7_VALID 0x80
801 #define I40E_AQ_SET_SWITCH_L4_SRC_PORT 0x40
803 #define I40E_AQ_SET_SWITCH_L4_TYPE_RSVD 0x00
804 #define I40E_AQ_SET_SWITCH_L4_TYPE_TCP 0x10
805 #define I40E_AQ_SET_SWITCH_L4_TYPE_UDP 0x20
806 #define I40E_AQ_SET_SWITCH_L4_TYPE_BOTH 0x30
808 #define I40E_AQ_SET_SWITCH_MODE_DEFAULT 0x00
809 #define I40E_AQ_SET_SWITCH_MODE_L4_PORT 0x01
810 #define I40E_AQ_SET_SWITCH_MODE_NON_TUNNEL 0x02
811 #define I40E_AQ_SET_SWITCH_MODE_TUNNEL 0x03
816 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config);
818 /* Read Receive control registers (direct 0x0206)
819 * Write Receive control registers (direct 0x0207)
820 * used for accessing Rx control registers that can be
821 * slow and need special handling when under high Rx load
823 struct i40e_aqc_rx_ctl_reg_read_write {
830 I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write);
832 /* Add VSI (indirect 0x0210)
833 * this indirect command uses struct i40e_aqc_vsi_properties_data
834 * as the indirect buffer (128 bytes)
836 * Update VSI (indirect 0x211)
837 * uses the same data structure as Add VSI
839 * Get VSI (indirect 0x0212)
840 * uses the same completion and data structure as Add VSI
842 struct i40e_aqc_add_get_update_vsi {
845 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
846 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2
847 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3
852 #define I40E_AQ_VSI_TYPE_SHIFT 0x0
853 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
854 #define I40E_AQ_VSI_TYPE_VF 0x0
855 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1
856 #define I40E_AQ_VSI_TYPE_PF 0x2
857 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3
858 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4
863 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
865 struct i40e_aqc_add_get_update_vsi_completion {
874 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
876 struct i40e_aqc_vsi_properties_data {
877 /* first 96 byte are written by SW */
878 __le16 valid_sections;
879 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
880 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
881 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
882 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008
883 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
884 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
885 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
886 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
887 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
888 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
890 __le16 switch_id; /* 12bit id combined with flags below */
891 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
892 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
893 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
894 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
895 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
897 /* security section */
899 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
900 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
901 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
904 __le16 pvid; /* VLANS include priority bits */
907 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
908 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
909 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
910 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
911 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
912 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
913 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
914 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
915 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
916 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
917 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
918 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
919 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
920 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
921 u8 pvlan_reserved[3];
922 /* ingress egress up sections */
923 __le32 ingress_table; /* bitmap, 3 bits per up */
924 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
925 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
926 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
927 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3
928 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
929 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
930 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6
931 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
932 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
933 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9
934 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
935 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
936 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12
937 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
938 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
939 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15
940 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
941 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
942 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18
943 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
944 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
945 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21
946 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
947 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
948 __le32 egress_table; /* same defines as for ingress table */
949 /* cascaded PV section */
952 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
953 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
954 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
955 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
956 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
957 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02
958 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10
959 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
960 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
962 /* queue mapping section */
963 __le16 mapping_flags;
964 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
965 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
966 __le16 queue_mapping[16];
967 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0
968 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
969 __le16 tc_mapping[8];
970 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
971 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
972 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
973 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
974 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
975 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
976 /* queueing option section */
977 u8 queueing_opt_flags;
978 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04
979 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08
980 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
981 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
982 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00
983 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
984 u8 queueing_opt_reserved[3];
985 /* scheduler section */
988 /* outer up section */
989 __le32 outer_up_table; /* same structure and defines as ingress tbl */
991 /* last 32 bytes are written by FW */
993 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
994 __le16 stat_counter_idx;
996 u8 resp_reserved[12];
999 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
1001 /* Add Port Virtualizer (direct 0x0220)
1002 * also used for update PV (direct 0x0221) but only flags are used
1003 * (IS_CTRL_PORT only works on add PV)
1005 struct i40e_aqc_add_update_pv {
1006 __le16 command_flags;
1007 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1
1008 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
1009 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
1010 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8
1012 __le16 connected_seid;
1016 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
1018 struct i40e_aqc_add_update_pv_completion {
1019 /* reserved for update; for add also encodes error if rc == ENOSPC */
1021 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1
1022 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2
1023 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
1024 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
1028 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
1030 /* Get PV Params (direct 0x0222)
1031 * uses i40e_aqc_switch_seid for the descriptor
1034 struct i40e_aqc_get_pv_params_completion {
1036 __le16 default_stag;
1037 __le16 pv_flags; /* same flags as add_pv */
1038 #define I40E_AQC_GET_PV_PV_TYPE 0x1
1039 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
1040 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
1042 __le16 default_port_seid;
1045 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
1047 /* Add VEB (direct 0x0230) */
1048 struct i40e_aqc_add_veb {
1050 __le16 downlink_seid;
1052 #define I40E_AQC_ADD_VEB_FLOATING 0x1
1053 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
1054 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
1055 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
1056 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
1057 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
1058 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */
1059 #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10
1064 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
1066 struct i40e_aqc_add_veb_completion {
1069 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
1071 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1
1072 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
1073 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
1074 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
1075 __le16 statistic_index;
1080 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
1082 /* Get VEB Parameters (direct 0x0232)
1083 * uses i40e_aqc_switch_seid for the descriptor
1085 struct i40e_aqc_get_veb_parameters_completion {
1088 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
1089 __le16 statistic_index;
1095 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
1097 /* Delete Element (direct 0x0243)
1098 * uses the generic i40e_aqc_switch_seid
1101 /* Add MAC-VLAN (indirect 0x0250) */
1103 /* used for the command for most vlan commands */
1104 struct i40e_aqc_macvlan {
1105 __le16 num_addresses;
1107 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
1108 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
1109 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1110 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
1115 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
1117 /* indirect data for command and response */
1118 struct i40e_aqc_add_macvlan_element_data {
1122 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
1123 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
1124 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
1125 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
1126 #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010
1127 __le16 queue_number;
1128 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
1129 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
1130 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1131 /* response section */
1133 #define I40E_AQC_MM_PERFECT_MATCH 0x01
1134 #define I40E_AQC_MM_HASH_MATCH 0x02
1135 #define I40E_AQC_MM_ERR_NO_RES 0xFF
1139 struct i40e_aqc_add_remove_macvlan_completion {
1140 __le16 perfect_mac_used;
1141 __le16 perfect_mac_free;
1142 __le16 unicast_hash_free;
1143 __le16 multicast_hash_free;
1148 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
1150 /* Remove MAC-VLAN (indirect 0x0251)
1151 * uses i40e_aqc_macvlan for the descriptor
1152 * data points to an array of num_addresses of elements
1155 struct i40e_aqc_remove_macvlan_element_data {
1159 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
1160 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02
1161 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
1162 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10
1166 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0
1167 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF
1168 u8 reply_reserved[3];
1171 /* Add VLAN (indirect 0x0252)
1172 * Remove VLAN (indirect 0x0253)
1173 * use the generic i40e_aqc_macvlan for the command
1175 struct i40e_aqc_add_remove_vlan_element_data {
1178 /* flags for add VLAN */
1179 #define I40E_AQC_ADD_VLAN_LOCAL 0x1
1180 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1
1181 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1182 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
1183 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
1184 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
1185 #define I40E_AQC_VLAN_PTYPE_SHIFT 3
1186 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1187 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
1188 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
1189 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
1190 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
1191 /* flags for remove VLAN */
1192 #define I40E_AQC_REMOVE_VLAN_ALL 0x1
1195 /* flags for add VLAN */
1196 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0
1197 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
1198 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
1199 /* flags for remove VLAN */
1200 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0
1201 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF
1205 struct i40e_aqc_add_remove_vlan_completion {
1213 /* Set VSI Promiscuous Modes (direct 0x0254) */
1214 struct i40e_aqc_set_vsi_promiscuous_modes {
1215 __le16 promiscuous_flags;
1217 /* flags used for both fields above */
1218 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
1219 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1220 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1221 #define I40E_AQC_SET_VSI_DEFAULT 0x08
1222 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
1223 #define I40E_AQC_SET_VSI_PROMISC_TX 0x8000
1225 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
1227 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF
1228 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
1232 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1234 /* Add S/E-tag command (direct 0x0255)
1235 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1237 struct i40e_aqc_add_tag {
1239 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
1241 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
1242 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1243 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1245 __le16 queue_number;
1249 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1251 struct i40e_aqc_add_remove_tag_completion {
1257 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1259 /* Remove S/E-tag command (direct 0x0256)
1260 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1262 struct i40e_aqc_remove_tag {
1264 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
1265 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1266 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1271 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);
1273 /* Add multicast E-Tag (direct 0x0257)
1274 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1275 * and no external data
1277 struct i40e_aqc_add_remove_mcast_etag {
1280 u8 num_unicast_etags;
1282 __le32 addr_high; /* address of array of 2-byte s-tags */
1286 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1288 struct i40e_aqc_add_remove_mcast_etag_completion {
1290 __le16 mcast_etags_used;
1291 __le16 mcast_etags_free;
1297 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1299 /* Update S/E-Tag (direct 0x0259) */
1300 struct i40e_aqc_update_tag {
1302 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
1303 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1304 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1310 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1312 struct i40e_aqc_update_tag_completion {
1318 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1320 /* Add Control Packet filter (direct 0x025A)
1321 * Remove Control Packet filter (direct 0x025B)
1322 * uses the i40e_aqc_add_oveb_cloud,
1323 * and the generic direct completion structure
1325 struct i40e_aqc_add_remove_control_packet_filter {
1329 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1330 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1331 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
1332 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1333 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
1335 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
1336 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
1337 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1342 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1344 struct i40e_aqc_add_remove_control_packet_filter_completion {
1345 __le16 mac_etype_used;
1347 __le16 mac_etype_free;
1352 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1354 /* Add Cloud filters (indirect 0x025C)
1355 * Remove Cloud filters (indirect 0x025D)
1356 * uses the i40e_aqc_add_remove_cloud_filters,
1357 * and the generic indirect completion structure
1359 struct i40e_aqc_add_remove_cloud_filters {
1363 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
1364 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
1365 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1367 #define I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER 1
1368 #define I40E_AQC_ADD_CLOUD_CMD_BB 1
1374 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1376 struct i40e_aqc_cloud_filters_element_data {
1393 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
1394 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
1395 I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1396 /* 0x0000 reserved */
1397 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001
1398 /* 0x0002 reserved */
1399 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1400 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
1401 /* 0x0005 reserved */
1402 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
1403 /* 0x0007 reserved */
1404 /* 0x0008 reserved */
1405 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1406 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1407 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1408 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1409 /* 0x000D reserved */
1410 /* 0x000E reserved */
1411 /* 0x000F reserved */
1412 /* 0x0010 to 0x0017 is for custom filters */
1413 #define I40E_AQC_ADD_CLOUD_FILTER_IP_PORT 0x0010 /* Dest IP + L4 Port */
1414 #define I40E_AQC_ADD_CLOUD_FILTER_MAC_PORT 0x0011 /* Dest MAC + L4 Port */
1415 #define I40E_AQC_ADD_CLOUD_FILTER_MAC_VLAN_PORT 0x0012 /* Dest MAC + VLAN + L4 Port */
1417 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
1418 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6
1419 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0
1420 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1421 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1423 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1424 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1425 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0
1426 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
1427 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2
1428 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3
1429 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4
1430 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5
1432 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000
1433 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000
1434 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000
1438 __le16 queue_number;
1439 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
1440 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \
1441 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1443 /* response section */
1444 u8 allocation_result;
1445 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
1446 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
1447 u8 response_reserved[7];
1450 /* i40e_aqc_add_rm_cloud_filt_elem_ext is used when
1451 * I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER flag is set.
1453 struct i40e_aqc_add_rm_cloud_filt_elem_ext {
1454 struct i40e_aqc_cloud_filters_element_data element;
1455 u16 general_fields[32];
1456 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0 0
1457 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1 1
1458 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2 2
1459 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0 3
1460 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1 4
1461 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2 5
1462 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0 6
1463 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1 7
1464 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2 8
1465 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0 9
1466 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1 10
1467 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2 11
1468 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0 12
1469 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1 13
1470 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2 14
1471 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0 15
1472 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1 16
1473 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2 17
1474 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3 18
1475 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4 19
1476 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5 20
1477 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6 21
1478 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7 22
1479 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0 23
1480 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1 24
1481 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2 25
1482 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3 26
1483 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4 27
1484 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5 28
1485 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6 29
1486 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7 30
1489 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_cloud_filters_element_data);
1491 /* i40e_aqc_cloud_filters_element_bb is used when
1492 * I40E_AQC_CLOUD_CMD_BB flag is set.
1494 struct i40e_aqc_cloud_filters_element_bb {
1495 struct i40e_aqc_cloud_filters_element_data element;
1496 u16 general_fields[32];
1497 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0 0
1498 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1 1
1499 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2 2
1500 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0 3
1501 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1 4
1502 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2 5
1503 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0 6
1504 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1 7
1505 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2 8
1506 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0 9
1507 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1 10
1508 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2 11
1509 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0 12
1510 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1 13
1511 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2 14
1512 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0 15
1513 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1 16
1514 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2 17
1515 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3 18
1516 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4 19
1517 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5 20
1518 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6 21
1519 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7 22
1520 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0 23
1521 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1 24
1522 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2 25
1523 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3 26
1524 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4 27
1525 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5 28
1526 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6 29
1527 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7 30
1530 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_cloud_filters_element_bb);
1532 struct i40e_aqc_remove_cloud_filters_completion {
1533 __le16 perfect_ovlan_used;
1534 __le16 perfect_ovlan_free;
1541 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1543 /* Replace filter Command 0x025F
1544 * uses the i40e_aqc_replace_cloud_filters,
1545 * and the generic indirect completion structure
1547 struct i40e_filter_data {
1552 I40E_CHECK_STRUCT_LEN(4, i40e_filter_data);
1554 struct i40e_aqc_replace_cloud_filters_cmd {
1556 #define I40E_AQC_REPLACE_L1_FILTER 0x0
1557 #define I40E_AQC_REPLACE_CLOUD_FILTER 0x1
1558 #define I40E_AQC_GET_CLOUD_FILTERS 0x2
1559 #define I40E_AQC_MIRROR_CLOUD_FILTER 0x4
1560 #define I40E_AQC_HIGH_PRIORITY_CLOUD_FILTER 0x8
1570 I40E_CHECK_CMD_LENGTH(i40e_aqc_replace_cloud_filters_cmd);
1572 struct i40e_aqc_replace_cloud_filters_cmd_buf {
1574 /* Filter type INPUT codes*/
1575 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_ENTRIES_MAX 3
1576 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED (1 << 7UL)
1578 /* Field Vector offsets */
1579 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_MAC_DA 0
1580 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_ETH 6
1581 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG 7
1582 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN 8
1583 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_OVLAN 9
1584 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN 10
1585 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY 11
1586 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC 12
1588 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IP_DA 14
1590 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_OIP_DA 15
1592 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN 37
1593 struct i40e_filter_data filters[8];
1596 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_replace_cloud_filters_cmd_buf);
1598 /* Add Mirror Rule (indirect or direct 0x0260)
1599 * Delete Mirror Rule (indirect or direct 0x0261)
1600 * note: some rule types (4,5) do not use an external buffer.
1601 * take care to set the flags correctly.
1603 struct i40e_aqc_add_delete_mirror_rule {
1606 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1607 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1608 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1609 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1610 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
1611 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1612 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1613 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
1615 __le16 destination; /* VSI for add, rule id for delete */
1616 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
1620 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1622 struct i40e_aqc_add_delete_mirror_rule_completion {
1624 __le16 rule_id; /* only used on add */
1625 __le16 mirror_rules_used;
1626 __le16 mirror_rules_free;
1631 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1633 /* Dynamic Device Personalization */
1634 struct i40e_aqc_write_personalization_profile {
1637 __le32 profile_track_id;
1642 I40E_CHECK_CMD_LENGTH(i40e_aqc_write_personalization_profile);
1644 struct i40e_aqc_write_ddp_resp {
1645 __le32 error_offset;
1651 struct i40e_aqc_get_applied_profiles {
1653 #define I40E_AQC_GET_DDP_GET_CONF 0x1
1654 #define I40E_AQC_GET_DDP_GET_RDPU_CONF 0x2
1661 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_applied_profiles);
1665 /* PFC Ignore (direct 0x0301)
1666 * the command and response use the same descriptor structure
1668 struct i40e_aqc_pfc_ignore {
1670 u8 command_flags; /* unused on response */
1671 #define I40E_AQC_PFC_IGNORE_SET 0x80
1672 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0
1676 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1678 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1679 * with no parameters
1682 /* TX scheduler 0x04xx */
1684 /* Almost all the indirect commands use
1685 * this generic struct to pass the SEID in param0
1687 struct i40e_aqc_tx_sched_ind {
1694 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1696 /* Several commands respond with a set of queue set handles */
1697 struct i40e_aqc_qs_handles_resp {
1698 __le16 qs_handles[8];
1701 /* Configure VSI BW limits (direct 0x0400) */
1702 struct i40e_aqc_configure_vsi_bw_limit {
1707 u8 max_credit; /* 0-3, limit = 2^max */
1711 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1713 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1714 * responds with i40e_aqc_qs_handles_resp
1716 struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1719 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
1721 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1722 __le16 tc_bw_max[2];
1726 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
1728 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1729 * responds with i40e_aqc_qs_handles_resp
1731 struct i40e_aqc_configure_vsi_tc_bw_data {
1734 u8 tc_bw_credits[8];
1736 __le16 qs_handles[8];
1739 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
1741 /* Query vsi bw configuration (indirect 0x0408) */
1742 struct i40e_aqc_query_vsi_bw_config_resp {
1744 u8 tc_suspended_bits;
1746 __le16 qs_handles[8];
1748 __le16 port_bw_limit;
1750 u8 max_bw; /* 0-3, limit = 2^max */
1754 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
1756 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1757 struct i40e_aqc_query_vsi_ets_sla_config_resp {
1760 u8 share_credits[8];
1763 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1764 __le16 tc_bw_max[2];
1767 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
1769 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1770 struct i40e_aqc_configure_switching_comp_bw_limit {
1775 u8 max_bw; /* 0-3, limit = 2^max */
1779 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1781 /* Enable Physical Port ETS (indirect 0x0413)
1782 * Modify Physical Port ETS (indirect 0x0414)
1783 * Disable Physical Port ETS (indirect 0x0415)
1785 struct i40e_aqc_configure_switching_comp_ets_data {
1789 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1
1790 u8 tc_strict_priority_flags;
1792 u8 tc_bw_share_credits[8];
1796 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
1798 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1799 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1802 __le16 tc_bw_credit[8];
1804 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1805 __le16 tc_bw_max[2];
1809 I40E_CHECK_STRUCT_LEN(0x40,
1810 i40e_aqc_configure_switching_comp_ets_bw_limit_data);
1812 /* Configure Switching Component Bandwidth Allocation per Tc
1815 struct i40e_aqc_configure_switching_comp_bw_config_data {
1818 u8 absolute_credits; /* bool */
1819 u8 tc_bw_share_credits[8];
1823 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
1825 /* Query Switching Component Configuration (indirect 0x0418) */
1826 struct i40e_aqc_query_switching_comp_ets_config_resp {
1829 __le16 port_bw_limit;
1831 u8 tc_bw_max; /* 0-3, limit = 2^max */
1835 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
1837 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1838 struct i40e_aqc_query_port_ets_config_resp {
1842 u8 tc_strict_priority_bits;
1844 u8 tc_bw_share_credits[8];
1845 __le16 tc_bw_limits[8];
1847 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1848 __le16 tc_bw_max[2];
1852 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
1854 /* Query Switching Component Bandwidth Allocation per Traffic Type
1857 struct i40e_aqc_query_switching_comp_bw_config_resp {
1860 u8 absolute_credits_enable; /* bool */
1861 u8 tc_bw_share_credits[8];
1862 __le16 tc_bw_limits[8];
1864 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1865 __le16 tc_bw_max[2];
1868 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
1870 /* Suspend/resume port TX traffic
1871 * (direct 0x041B and 0x041C) uses the generic SEID struct
1874 /* Configure partition BW
1877 struct i40e_aqc_configure_partition_bw_data {
1878 __le16 pf_valid_bits;
1879 u8 min_bw[16]; /* guaranteed bandwidth */
1880 u8 max_bw[16]; /* bandwidth limit */
1883 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
1885 /* Get and set the active HMC resource profile and status.
1886 * (direct 0x0500) and (direct 0x0501)
1888 struct i40e_aq_get_set_hmc_resource_profile {
1894 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1896 enum i40e_aq_hmc_profile {
1897 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
1898 I40E_HMC_PROFILE_DEFAULT = 1,
1899 I40E_HMC_PROFILE_FAVOR_VF = 2,
1900 I40E_HMC_PROFILE_EQUAL = 3,
1903 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1905 /* set in param0 for get phy abilities to report qualified modules */
1906 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1907 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1909 enum i40e_aq_phy_type {
1910 I40E_PHY_TYPE_SGMII = 0x0,
1911 I40E_PHY_TYPE_1000BASE_KX = 0x1,
1912 I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
1913 I40E_PHY_TYPE_10GBASE_KR = 0x3,
1914 I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
1915 I40E_PHY_TYPE_XAUI = 0x5,
1916 I40E_PHY_TYPE_XFI = 0x6,
1917 I40E_PHY_TYPE_SFI = 0x7,
1918 I40E_PHY_TYPE_XLAUI = 0x8,
1919 I40E_PHY_TYPE_XLPPI = 0x9,
1920 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1921 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
1922 I40E_PHY_TYPE_10GBASE_AOC = 0xC,
1923 I40E_PHY_TYPE_40GBASE_AOC = 0xD,
1924 I40E_PHY_TYPE_UNRECOGNIZED = 0xE,
1925 I40E_PHY_TYPE_UNSUPPORTED = 0xF,
1926 I40E_PHY_TYPE_100BASE_TX = 0x11,
1927 I40E_PHY_TYPE_1000BASE_T = 0x12,
1928 I40E_PHY_TYPE_10GBASE_T = 0x13,
1929 I40E_PHY_TYPE_10GBASE_SR = 0x14,
1930 I40E_PHY_TYPE_10GBASE_LR = 0x15,
1931 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1932 I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
1933 I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
1934 I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
1935 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
1936 I40E_PHY_TYPE_1000BASE_SX = 0x1B,
1937 I40E_PHY_TYPE_1000BASE_LX = 0x1C,
1938 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
1939 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
1940 I40E_PHY_TYPE_25GBASE_KR = 0x1F,
1941 I40E_PHY_TYPE_25GBASE_CR = 0x20,
1942 I40E_PHY_TYPE_25GBASE_SR = 0x21,
1943 I40E_PHY_TYPE_25GBASE_LR = 0x22,
1944 I40E_PHY_TYPE_25GBASE_AOC = 0x23,
1945 I40E_PHY_TYPE_25GBASE_ACC = 0x24,
1946 I40E_PHY_TYPE_2_5GBASE_T = 0x30,
1947 I40E_PHY_TYPE_5GBASE_T = 0x31,
1949 I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD,
1950 I40E_PHY_TYPE_EMPTY = 0xFE,
1951 I40E_PHY_TYPE_DEFAULT = 0xFF,
1954 #define I40E_PHY_TYPES_BITMASK (BIT_ULL(I40E_PHY_TYPE_SGMII) | \
1955 BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) | \
1956 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) | \
1957 BIT_ULL(I40E_PHY_TYPE_10GBASE_KR) | \
1958 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4) | \
1959 BIT_ULL(I40E_PHY_TYPE_XAUI) | \
1960 BIT_ULL(I40E_PHY_TYPE_XFI) | \
1961 BIT_ULL(I40E_PHY_TYPE_SFI) | \
1962 BIT_ULL(I40E_PHY_TYPE_XLAUI) | \
1963 BIT_ULL(I40E_PHY_TYPE_XLPPI) | \
1964 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU) | \
1965 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU) | \
1966 BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC) | \
1967 BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) | \
1968 BIT_ULL(I40E_PHY_TYPE_UNRECOGNIZED) | \
1969 BIT_ULL(I40E_PHY_TYPE_UNSUPPORTED) | \
1970 BIT_ULL(I40E_PHY_TYPE_100BASE_TX) | \
1971 BIT_ULL(I40E_PHY_TYPE_1000BASE_T) | \
1972 BIT_ULL(I40E_PHY_TYPE_10GBASE_T) | \
1973 BIT_ULL(I40E_PHY_TYPE_10GBASE_SR) | \
1974 BIT_ULL(I40E_PHY_TYPE_10GBASE_LR) | \
1975 BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU) | \
1976 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1) | \
1977 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4) | \
1978 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4) | \
1979 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4) | \
1980 BIT_ULL(I40E_PHY_TYPE_1000BASE_SX) | \
1981 BIT_ULL(I40E_PHY_TYPE_1000BASE_LX) | \
1982 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) | \
1983 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) | \
1984 BIT_ULL(I40E_PHY_TYPE_25GBASE_KR) | \
1985 BIT_ULL(I40E_PHY_TYPE_25GBASE_CR) | \
1986 BIT_ULL(I40E_PHY_TYPE_25GBASE_SR) | \
1987 BIT_ULL(I40E_PHY_TYPE_25GBASE_LR) | \
1988 BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC) | \
1989 BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC) | \
1990 BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T) | \
1991 BIT_ULL(I40E_PHY_TYPE_5GBASE_T))
1993 #define I40E_LINK_SPEED_2_5GB_SHIFT 0x0
1994 #define I40E_LINK_SPEED_100MB_SHIFT 0x1
1995 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1996 #define I40E_LINK_SPEED_10GB_SHIFT 0x3
1997 #define I40E_LINK_SPEED_40GB_SHIFT 0x4
1998 #define I40E_LINK_SPEED_20GB_SHIFT 0x5
1999 #define I40E_LINK_SPEED_25GB_SHIFT 0x6
2000 #define I40E_LINK_SPEED_5GB_SHIFT 0x7
2002 enum i40e_aq_link_speed {
2003 I40E_LINK_SPEED_UNKNOWN = 0,
2004 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT),
2005 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT),
2006 I40E_LINK_SPEED_2_5GB = (1 << I40E_LINK_SPEED_2_5GB_SHIFT),
2007 I40E_LINK_SPEED_5GB = (1 << I40E_LINK_SPEED_5GB_SHIFT),
2008 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT),
2009 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT),
2010 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT),
2011 I40E_LINK_SPEED_25GB = (1 << I40E_LINK_SPEED_25GB_SHIFT),
2014 struct i40e_aqc_module_desc {
2022 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
2024 struct i40e_aq_get_phy_abilities_resp {
2025 __le32 phy_type; /* bitmap using the above enum for offsets */
2026 u8 link_speed; /* bitmap using the above enum bit patterns */
2028 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
2029 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
2030 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04
2031 #define I40E_AQ_PHY_LINK_ENABLED 0x08
2032 #define I40E_AQ_PHY_AN_ENABLED 0x10
2033 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20
2034 #define I40E_AQ_PHY_FEC_ABILITY_KR 0x40
2035 #define I40E_AQ_PHY_FEC_ABILITY_RS 0x80
2036 __le16 eee_capability;
2037 #define I40E_AQ_EEE_AUTO 0x0001
2038 #define I40E_AQ_EEE_100BASE_TX 0x0002
2039 #define I40E_AQ_EEE_1000BASE_T 0x0004
2040 #define I40E_AQ_EEE_10GBASE_T 0x0008
2041 #define I40E_AQ_EEE_1000BASE_KX 0x0010
2042 #define I40E_AQ_EEE_10GBASE_KX4 0x0020
2043 #define I40E_AQ_EEE_10GBASE_KR 0x0040
2044 #define I40E_AQ_EEE_2_5GBASE_T 0x0100
2045 #define I40E_AQ_EEE_5GBASE_T 0x0200
2048 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
2050 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0x01
2051 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0x02
2052 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04
2053 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
2054 #define I40E_AQ_PHY_TYPE_EXT_25G_AOC 0x10
2055 #define I40E_AQ_PHY_TYPE_EXT_25G_ACC 0x20
2056 #define I40E_AQ_PHY_TYPE_EXT_2_5GBASE_T 0x40
2057 #define I40E_AQ_PHY_TYPE_EXT_5GBASE_T 0x80
2058 u8 fec_cfg_curr_mod_ext_info;
2059 #define I40E_AQ_ENABLE_FEC_KR 0x01
2060 #define I40E_AQ_ENABLE_FEC_RS 0x02
2061 #define I40E_AQ_REQUEST_FEC_KR 0x04
2062 #define I40E_AQ_REQUEST_FEC_RS 0x08
2063 #define I40E_AQ_ENABLE_FEC_AUTO 0x10
2065 #define I40E_AQ_MODULE_TYPE_EXT_MASK 0xE0
2066 #define I40E_AQ_MODULE_TYPE_EXT_SHIFT 5
2071 u8 qualified_module_count;
2072 #define I40E_AQ_PHY_MAX_QMS 16
2073 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS];
2076 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
2078 /* Set PHY Config (direct 0x0601) */
2079 struct i40e_aq_set_phy_config { /* same bits as above in all */
2083 /* bits 0-2 use the values from get_phy_abilities_resp */
2084 #define I40E_AQ_PHY_ENABLE_LINK 0x08
2085 #define I40E_AQ_PHY_ENABLE_AN 0x10
2086 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
2087 __le16 eee_capability;
2092 #define I40E_AQ_SET_FEC_ABILITY_KR BIT(0)
2093 #define I40E_AQ_SET_FEC_ABILITY_RS BIT(1)
2094 #define I40E_AQ_SET_FEC_REQUEST_KR BIT(2)
2095 #define I40E_AQ_SET_FEC_REQUEST_RS BIT(3)
2096 #define I40E_AQ_SET_FEC_AUTO BIT(4)
2097 #define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0
2098 #define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT)
2102 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
2104 /* Set MAC Config command data structure (direct 0x0603) */
2105 struct i40e_aq_set_mac_config {
2106 __le16 max_frame_size;
2108 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
2109 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
2110 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
2111 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
2112 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
2113 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
2114 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
2115 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
2116 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
2117 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
2118 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
2119 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
2120 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
2121 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
2122 #define I40E_AQ_SET_MAC_CONFIG_DROP_BLOCKING_PACKET_EN 0x80
2123 u8 tx_timer_priority; /* bitmap */
2124 __le16 tx_timer_value;
2125 __le16 fc_refresh_threshold;
2129 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
2131 /* Restart Auto-Negotiation (direct 0x605) */
2132 struct i40e_aqc_set_link_restart_an {
2134 #define I40E_AQ_PHY_RESTART_AN 0x02
2135 #define I40E_AQ_PHY_LINK_ENABLE 0x04
2139 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
2141 /* Get Link Status cmd & response data structure (direct 0x0607) */
2142 struct i40e_aqc_get_link_status {
2143 __le16 command_flags; /* only field set on command */
2144 #define I40E_AQ_LSE_MASK 0x3
2145 #define I40E_AQ_LSE_NOP 0x0
2146 #define I40E_AQ_LSE_DISABLE 0x2
2147 #define I40E_AQ_LSE_ENABLE 0x3
2148 /* only response uses this flag */
2149 #define I40E_AQ_LSE_IS_ENABLED 0x1
2150 u8 phy_type; /* i40e_aq_phy_type */
2151 u8 link_speed; /* i40e_aq_link_speed */
2153 #define I40E_AQ_LINK_UP 0x01 /* obsolete */
2154 #define I40E_AQ_LINK_UP_FUNCTION 0x01
2155 #define I40E_AQ_LINK_FAULT 0x02
2156 #define I40E_AQ_LINK_FAULT_TX 0x04
2157 #define I40E_AQ_LINK_FAULT_RX 0x08
2158 #define I40E_AQ_LINK_FAULT_REMOTE 0x10
2159 #define I40E_AQ_LINK_UP_PORT 0x20
2160 #define I40E_AQ_MEDIA_AVAILABLE 0x40
2161 #define I40E_AQ_SIGNAL_DETECT 0x80
2163 #define I40E_AQ_AN_COMPLETED 0x01
2164 #define I40E_AQ_LP_AN_ABILITY 0x02
2165 #define I40E_AQ_PD_FAULT 0x04
2166 #define I40E_AQ_FEC_EN 0x08
2167 #define I40E_AQ_PHY_LOW_POWER 0x10
2168 #define I40E_AQ_LINK_PAUSE_TX 0x20
2169 #define I40E_AQ_LINK_PAUSE_RX 0x40
2170 #define I40E_AQ_QUALIFIED_MODULE 0x80
2172 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01
2173 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02
2174 #define I40E_AQ_LINK_TX_SHIFT 0x02
2175 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT)
2176 #define I40E_AQ_LINK_TX_ACTIVE 0x00
2177 #define I40E_AQ_LINK_TX_DRAINED 0x01
2178 #define I40E_AQ_LINK_TX_FLUSHED 0x03
2179 #define I40E_AQ_LINK_FORCED_40G 0x10
2180 /* 25G Error Codes */
2181 #define I40E_AQ_25G_NO_ERR 0X00
2182 #define I40E_AQ_25G_NOT_PRESENT 0X01
2183 #define I40E_AQ_25G_NVM_CRC_ERR 0X02
2184 #define I40E_AQ_25G_SBUS_UCODE_ERR 0X03
2185 #define I40E_AQ_25G_SERDES_UCODE_ERR 0X04
2186 #define I40E_AQ_25G_NIMB_UCODE_ERR 0X05
2187 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
2188 /* Since firmware API 1.7 loopback field keeps power class info as well */
2189 #define I40E_AQ_LOOPBACK_MASK 0x07
2190 #define I40E_AQ_PWR_CLASS_SHIFT_LB 6
2191 #define I40E_AQ_PWR_CLASS_MASK_LB (0x03 << I40E_AQ_PWR_CLASS_SHIFT_LB)
2192 __le16 max_frame_size;
2194 #define I40E_AQ_CONFIG_FEC_KR_ENA 0x01
2195 #define I40E_AQ_CONFIG_FEC_RS_ENA 0x02
2196 #define I40E_AQ_CONFIG_CRC_ENA 0x04
2197 #define I40E_AQ_CONFIG_PACING_MASK 0x78
2201 #define I40E_AQ_LINK_POWER_CLASS_1 0x00
2202 #define I40E_AQ_LINK_POWER_CLASS_2 0x01
2203 #define I40E_AQ_LINK_POWER_CLASS_3 0x02
2204 #define I40E_AQ_LINK_POWER_CLASS_4 0x03
2205 #define I40E_AQ_PWR_CLASS_MASK 0x03
2215 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
2217 /* Set event mask command (direct 0x613) */
2218 struct i40e_aqc_set_phy_int_mask {
2221 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
2222 #define I40E_AQ_EVENT_MEDIA_NA 0x0004
2223 #define I40E_AQ_EVENT_LINK_FAULT 0x0008
2224 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010
2225 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
2226 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040
2227 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080
2228 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
2229 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
2233 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
2235 /* Get Local AN advt register (direct 0x0614)
2236 * Set Local AN advt register (direct 0x0615)
2237 * Get Link Partner AN advt register (direct 0x0616)
2239 struct i40e_aqc_an_advt_reg {
2240 __le32 local_an_reg0;
2241 __le16 local_an_reg1;
2245 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
2247 /* Set Loopback mode (0x0618) */
2248 struct i40e_aqc_set_lb_mode {
2250 #define I40E_AQ_LB_PHY_LOCAL 0x01
2251 #define I40E_AQ_LB_PHY_REMOTE 0x02
2252 #define I40E_AQ_LB_MAC_LOCAL 0x04
2256 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
2258 /* Set PHY Debug command (0x0622) */
2259 struct i40e_aqc_set_phy_debug {
2261 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
2262 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
2263 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
2264 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
2265 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
2266 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
2267 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
2268 /* Disable link manageability on a single port */
2269 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
2270 /* Disable link manageability on all ports needs both bits 4 and 5 */
2271 #define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20
2275 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
2277 enum i40e_aq_phy_reg_type {
2278 I40E_AQC_PHY_REG_INTERNAL = 0x1,
2279 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
2280 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
2284 /* Run PHY Activity (0x0626) */
2285 struct i40e_aqc_run_phy_activity {
2288 #define I40E_AQ_RUN_PHY_ACT_ID_USR_DFND 0x10
2293 #define I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_STAT_DUR 0x801a
2294 #define I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_STAT 0x801b
2295 #define I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_DUR 0x1801b
2301 #define I40E_AQ_RUN_PHY_ACT_CMD_STAT_SUCC 0x4
2302 #define I40E_AQ_RUN_PHY_ACT_CMD_STAT_MASK 0xFFFF
2310 I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity);
2312 /* Set PHY Register command (0x0628) */
2313 /* Get PHY Register command (0x0629) */
2314 struct i40e_aqc_phy_register_access {
2316 #define I40E_AQ_PHY_REG_ACCESS_INTERNAL 0
2317 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL 1
2318 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE 2
2321 #define I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE 0x01
2322 #define I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER 0x02
2323 #define I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT 2
2324 #define I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK (0x3 << \
2325 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT)
2332 I40E_CHECK_CMD_LENGTH(i40e_aqc_phy_register_access);
2334 /* NVM Read command (indirect 0x0701)
2335 * NVM Erase commands (direct 0x0702)
2336 * NVM Update commands (indirect 0x0703)
2338 struct i40e_aqc_nvm_update {
2340 #define I40E_AQ_NVM_LAST_CMD 0x01
2341 #define I40E_AQ_NVM_REARRANGE_TO_FLAT 0x20
2342 #define I40E_AQ_NVM_REARRANGE_TO_STRUCT 0x40
2343 #define I40E_AQ_NVM_FLASH_ONLY 0x80
2344 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT 1
2345 #define I40E_AQ_NVM_PRESERVATION_FLAGS_MASK 0x03
2346 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED 0x03
2347 #define I40E_AQ_NVM_PRESERVATION_FLAGS_ALL 0x01
2355 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
2357 /* NVM Config Read (indirect 0x0704) */
2358 struct i40e_aqc_nvm_config_read {
2360 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
2361 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0
2362 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1
2363 __le16 element_count;
2364 __le16 element_id; /* Feature/field ID */
2365 __le16 element_id_msw; /* MSWord of field ID */
2366 __le32 address_high;
2370 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
2372 /* NVM Config Write (indirect 0x0705) */
2373 struct i40e_aqc_nvm_config_write {
2375 __le16 element_count;
2377 __le32 address_high;
2381 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
2383 /* Used for 0x0704 as well as for 0x0705 commands */
2384 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1
2385 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \
2386 (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
2387 #define I40E_AQ_ANVM_FEATURE 0
2388 #define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT)
2389 struct i40e_aqc_nvm_config_data_feature {
2391 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01
2392 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08
2393 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10
2394 __le16 feature_options;
2395 __le16 feature_selection;
2398 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
2400 struct i40e_aqc_nvm_config_data_immediate_field {
2403 __le16 field_options;
2407 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
2409 /* OEM Post Update (indirect 0x0720)
2410 * no command data struct used
2412 struct i40e_aqc_nvm_oem_post_update {
2413 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01
2418 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
2420 struct i40e_aqc_nvm_oem_post_update_buffer {
2427 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
2429 /* Thermal Sensor (indirect 0x0721)
2430 * read or set thermal sensor configs and values
2431 * takes a sensor and command specific data buffer, not detailed here
2433 struct i40e_aqc_thermal_sensor {
2435 #define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0
2436 #define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1
2437 #define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2
2443 I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor);
2445 /* Send to PF command (indirect 0x0801) id is only used by PF
2446 * Send to VF command (indirect 0x0802) id is only used by PF
2447 * Send to Peer PF command (indirect 0x0803)
2449 struct i40e_aqc_pf_vf_message {
2456 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
2458 /* Alternate structure */
2460 /* Direct write (direct 0x0900)
2461 * Direct read (direct 0x0902)
2463 struct i40e_aqc_alternate_write {
2470 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
2472 /* Indirect write (indirect 0x0901)
2473 * Indirect read (indirect 0x0903)
2476 struct i40e_aqc_alternate_ind_write {
2483 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
2485 /* Done alternate write (direct 0x0904)
2488 struct i40e_aqc_alternate_write_done {
2490 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1
2491 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
2492 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1
2493 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2
2497 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
2499 /* Set OEM mode (direct 0x0905) */
2500 struct i40e_aqc_alternate_set_mode {
2502 #define I40E_AQ_ALTERNATE_MODE_NONE 0
2503 #define I40E_AQ_ALTERNATE_MODE_OEM 1
2507 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
2509 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
2511 /* async events 0x10xx */
2513 /* Lan Queue Overflow Event (direct, 0x1001) */
2514 struct i40e_aqc_lan_overflow {
2515 __le32 prtdcb_rupto;
2520 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
2522 /* Get LLDP MIB (indirect 0x0A00) */
2523 struct i40e_aqc_lldp_get_mib {
2526 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
2527 #define I40E_AQ_LLDP_MIB_LOCAL 0x0
2528 #define I40E_AQ_LLDP_MIB_REMOTE 0x1
2529 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
2530 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
2531 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
2532 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
2533 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
2534 #define I40E_AQ_LLDP_TX_SHIFT 0x4
2535 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT)
2536 /* TX pause flags use I40E_AQ_LINK_TX_* above */
2544 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
2546 /* Configure LLDP MIB Change Event (direct 0x0A01)
2547 * also used for the event (with type in the command field)
2549 struct i40e_aqc_lldp_update_mib {
2551 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
2552 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
2558 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
2560 /* Add LLDP TLV (indirect 0x0A02)
2561 * Delete LLDP TLV (indirect 0x0A04)
2563 struct i40e_aqc_lldp_add_tlv {
2564 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2572 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
2574 /* Update LLDP TLV (indirect 0x0A03) */
2575 struct i40e_aqc_lldp_update_tlv {
2576 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2585 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
2587 /* Stop LLDP (direct 0x0A05) */
2588 struct i40e_aqc_lldp_stop {
2590 #define I40E_AQ_LLDP_AGENT_STOP 0x0
2591 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
2592 #define I40E_AQ_LLDP_AGENT_STOP_PERSIST 0x2
2596 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
2598 /* Start LLDP (direct 0x0A06) */
2600 struct i40e_aqc_lldp_start {
2602 #define I40E_AQ_LLDP_AGENT_START 0x1
2603 #define I40E_AQ_LLDP_AGENT_START_PERSIST 0x2
2607 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
2609 /* Set DCB (direct 0x0303) */
2610 struct i40e_aqc_set_dcb_parameters {
2612 #define I40E_AQ_DCB_SET_AGENT 0x1
2613 #define I40E_DCB_VALID 0x1
2618 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_dcb_parameters);
2620 /* Get CEE DCBX Oper Config (0x0A07)
2621 * uses the generic descriptor struct
2622 * returns below as indirect response
2625 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2626 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2627 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2628 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2629 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2630 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2632 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2633 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2634 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2635 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2636 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2637 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2638 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8
2639 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT)
2640 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB
2641 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT)
2642 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10
2643 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT)
2645 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with
2646 * word boundary layout issues, which the Linux compilers silently deal
2647 * with by adding padding, making the actual struct larger than designed.
2648 * However, the FW compiler for the NIC is less lenient and complains
2649 * about the struct. Hence, the struct defined here has an extra byte in
2650 * fields reserved3 and reserved4 to directly acknowledge that padding,
2651 * and the new length is used in the length check macro.
2653 struct i40e_aqc_get_cee_dcb_cfg_v1_resp {
2661 __le16 oper_app_prio;
2666 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp);
2668 struct i40e_aqc_get_cee_dcb_cfg_resp {
2673 __le16 oper_app_prio;
2678 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp);
2680 /* Set Local LLDP MIB (indirect 0x0A08)
2681 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx
2683 struct i40e_aqc_lldp_set_local_mib {
2684 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0
2685 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \
2686 SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
2687 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0
2688 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1)
2689 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \
2690 SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT)
2691 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1
2696 __le32 address_high;
2700 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib);
2702 struct i40e_aqc_lldp_set_local_mib_resp {
2703 #define SET_LOCAL_MIB_RESP_EVENT_TRIGGERED_MASK 0x01
2708 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_lldp_set_local_mib_resp);
2710 /* Stop/Start LLDP Agent (direct 0x0A09)
2711 * Used for stopping/starting specific LLDP agent. e.g. DCBx
2713 struct i40e_aqc_lldp_stop_start_specific_agent {
2714 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0
2715 #define I40E_AQC_START_SPECIFIC_AGENT_MASK \
2716 (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT)
2721 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent);
2723 /* Restore LLDP Agent factory settings (direct 0x0A0A) */
2724 struct i40e_aqc_lldp_restore {
2726 #define I40E_AQ_LLDP_AGENT_RESTORE_NOT 0x0
2727 #define I40E_AQ_LLDP_AGENT_RESTORE 0x1
2731 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_restore);
2733 /* Add Udp Tunnel command and completion (direct 0x0B00) */
2734 struct i40e_aqc_add_udp_tunnel {
2738 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
2739 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01
2740 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10
2741 #define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11
2745 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2747 struct i40e_aqc_add_udp_tunnel_completion {
2749 u8 filter_entry_index;
2751 #define I40E_AQC_SINGLE_PF 0x0
2752 #define I40E_AQC_MULTIPLE_PFS 0x1
2757 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2759 /* remove UDP Tunnel command (0x0B01) */
2760 struct i40e_aqc_remove_udp_tunnel {
2762 u8 index; /* 0 to 15 */
2766 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2768 struct i40e_aqc_del_udp_tunnel_completion {
2770 u8 index; /* 0 to 15 */
2772 u8 total_filters_used;
2776 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2778 struct i40e_aqc_get_set_rss_key {
2779 #define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15)
2780 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
2781 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
2782 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2789 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);
2791 struct i40e_aqc_get_set_rss_key_data {
2792 u8 standard_rss_key[0x28];
2793 u8 extended_hash_key[0xc];
2796 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
2798 struct i40e_aqc_get_set_rss_lut {
2799 #define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15)
2800 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
2801 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
2802 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2804 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
2805 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \
2806 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2808 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
2809 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1
2816 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);
2818 /* tunnel key structure 0x0B10 */
2820 struct i40e_aqc_tunnel_key_structure {
2823 u8 key1_len; /* 0 to 15 */
2824 u8 key2_len; /* 0 to 15 */
2826 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2827 /* response flags */
2828 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2829 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2830 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2831 u8 network_key_index;
2832 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
2833 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1
2834 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
2835 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3
2839 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2841 /* OEM mode commands (direct 0xFE0x) */
2842 struct i40e_aqc_oem_param_change {
2844 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0
2845 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1
2846 #define I40E_AQ_OEM_PARAM_MAC 2
2847 __le32 param_value1;
2848 __le16 param_value2;
2852 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2854 struct i40e_aqc_oem_state_change {
2856 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0
2857 #define I40E_AQ_OEM_STATE_LINK_UP 0x1
2861 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2863 /* Initialize OCSD (0xFE02, direct) */
2864 struct i40e_aqc_opc_oem_ocsd_initialize {
2867 __le32 ocsd_memory_block_addr_high;
2868 __le32 ocsd_memory_block_addr_low;
2869 __le32 requested_update_interval;
2872 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);
2874 /* Initialize OCBB (0xFE03, direct) */
2875 struct i40e_aqc_opc_oem_ocbb_initialize {
2878 __le32 ocbb_memory_block_addr_high;
2879 __le32 ocbb_memory_block_addr_low;
2883 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);
2885 /* debug commands */
2887 /* get device id (0xFF00) uses the generic structure */
2889 /* set test more (0xFF01, internal) */
2891 struct i40e_acq_set_test_mode {
2893 #define I40E_AQ_TEST_PARTIAL 0
2894 #define I40E_AQ_TEST_FULL 1
2895 #define I40E_AQ_TEST_NVM 2
2898 #define I40E_AQ_TEST_OPEN 0
2899 #define I40E_AQ_TEST_CLOSE 1
2900 #define I40E_AQ_TEST_INC 2
2902 __le32 address_high;
2906 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2908 /* Debug Read Register command (0xFF03)
2909 * Debug Write Register command (0xFF04)
2911 struct i40e_aqc_debug_reg_read_write {
2918 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2920 /* Scatter/gather Reg Read (indirect 0xFF05)
2921 * Scatter/gather Reg Write (indirect 0xFF06)
2924 /* i40e_aq_desc is used for the command */
2925 struct i40e_aqc_debug_reg_sg_element_data {
2930 /* Debug Modify register (direct 0xFF07) */
2931 struct i40e_aqc_debug_modify_reg {
2938 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2940 /* dump internal data (0xFF08, indirect) */
2942 #define I40E_AQ_CLUSTER_ID_AUX 0
2943 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1
2944 #define I40E_AQ_CLUSTER_ID_TXSCHED 2
2945 #define I40E_AQ_CLUSTER_ID_HMC 3
2946 #define I40E_AQ_CLUSTER_ID_MAC0 4
2947 #define I40E_AQ_CLUSTER_ID_MAC1 5
2948 #define I40E_AQ_CLUSTER_ID_MAC2 6
2949 #define I40E_AQ_CLUSTER_ID_MAC3 7
2950 #define I40E_AQ_CLUSTER_ID_DCB 8
2951 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9
2952 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10
2953 #define I40E_AQ_CLUSTER_ID_ALTRAM 11
2955 struct i40e_aqc_debug_dump_internals {
2960 __le32 address_high;
2964 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2966 struct i40e_aqc_debug_modify_internals {
2968 u8 cluster_specific_params[7];
2969 __le32 address_high;
2973 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
2975 #endif /* _I40E_ADMINQ_CMD_H_ */