1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2018
5 #ifndef _I40E_ADMINQ_CMD_H_
6 #define _I40E_ADMINQ_CMD_H_
8 /* This header file defines the i40e Admin Queue commands and is shared between
9 * i40e Firmware and Software.
11 * This file needs to comply with the Linux Kernel coding style.
14 #define I40E_FW_API_VERSION_MAJOR 0x0001
15 #define I40E_FW_API_VERSION_MINOR_X722 0x0005
16 #define I40E_FW_API_VERSION_MINOR_X710 0x0007
18 #define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \
19 I40E_FW_API_VERSION_MINOR_X710 : \
20 I40E_FW_API_VERSION_MINOR_X722)
22 /* API version 1.7 implements additional link and PHY-specific APIs */
23 #define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007
49 /* Flags sub-structure
50 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
51 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
54 /* command flags and offsets*/
55 #define I40E_AQ_FLAG_DD_SHIFT 0
56 #define I40E_AQ_FLAG_CMP_SHIFT 1
57 #define I40E_AQ_FLAG_ERR_SHIFT 2
58 #define I40E_AQ_FLAG_VFE_SHIFT 3
59 #define I40E_AQ_FLAG_LB_SHIFT 9
60 #define I40E_AQ_FLAG_RD_SHIFT 10
61 #define I40E_AQ_FLAG_VFC_SHIFT 11
62 #define I40E_AQ_FLAG_BUF_SHIFT 12
63 #define I40E_AQ_FLAG_SI_SHIFT 13
64 #define I40E_AQ_FLAG_EI_SHIFT 14
65 #define I40E_AQ_FLAG_FE_SHIFT 15
67 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
68 #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */
69 #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
70 #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */
71 #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
72 #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
73 #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */
74 #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
75 #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
76 #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */
77 #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */
80 enum i40e_admin_queue_err {
81 I40E_AQ_RC_OK = 0, /* success */
82 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */
83 I40E_AQ_RC_ENOENT = 2, /* No such element */
84 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */
85 I40E_AQ_RC_EINTR = 4, /* operation interrupted */
86 I40E_AQ_RC_EIO = 5, /* I/O error */
87 I40E_AQ_RC_ENXIO = 6, /* No such resource */
88 I40E_AQ_RC_E2BIG = 7, /* Arg too long */
89 I40E_AQ_RC_EAGAIN = 8, /* Try again */
90 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */
91 I40E_AQ_RC_EACCES = 10, /* Permission denied */
92 I40E_AQ_RC_EFAULT = 11, /* Bad address */
93 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */
94 I40E_AQ_RC_EEXIST = 13, /* object already exists */
95 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */
96 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */
97 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
98 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */
99 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */
100 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
101 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
102 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
103 I40E_AQ_RC_EFBIG = 22, /* File too large */
106 /* Admin Queue command opcodes */
107 enum i40e_admin_queue_opc {
109 i40e_aqc_opc_get_version = 0x0001,
110 i40e_aqc_opc_driver_version = 0x0002,
111 i40e_aqc_opc_queue_shutdown = 0x0003,
112 i40e_aqc_opc_set_pf_context = 0x0004,
114 /* resource ownership */
115 i40e_aqc_opc_request_resource = 0x0008,
116 i40e_aqc_opc_release_resource = 0x0009,
118 i40e_aqc_opc_list_func_capabilities = 0x000A,
119 i40e_aqc_opc_list_dev_capabilities = 0x000B,
122 i40e_aqc_opc_set_proxy_config = 0x0104,
123 i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105,
126 i40e_aqc_opc_mac_address_read = 0x0107,
127 i40e_aqc_opc_mac_address_write = 0x0108,
130 i40e_aqc_opc_clear_pxe_mode = 0x0110,
133 i40e_aqc_opc_set_wol_filter = 0x0120,
134 i40e_aqc_opc_get_wake_reason = 0x0121,
135 i40e_aqc_opc_clear_all_wol_filters = 0x025E,
137 /* internal switch commands */
138 i40e_aqc_opc_get_switch_config = 0x0200,
139 i40e_aqc_opc_add_statistics = 0x0201,
140 i40e_aqc_opc_remove_statistics = 0x0202,
141 i40e_aqc_opc_set_port_parameters = 0x0203,
142 i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
143 i40e_aqc_opc_set_switch_config = 0x0205,
144 i40e_aqc_opc_rx_ctl_reg_read = 0x0206,
145 i40e_aqc_opc_rx_ctl_reg_write = 0x0207,
147 i40e_aqc_opc_add_vsi = 0x0210,
148 i40e_aqc_opc_update_vsi_parameters = 0x0211,
149 i40e_aqc_opc_get_vsi_parameters = 0x0212,
151 i40e_aqc_opc_add_pv = 0x0220,
152 i40e_aqc_opc_update_pv_parameters = 0x0221,
153 i40e_aqc_opc_get_pv_parameters = 0x0222,
155 i40e_aqc_opc_add_veb = 0x0230,
156 i40e_aqc_opc_update_veb_parameters = 0x0231,
157 i40e_aqc_opc_get_veb_parameters = 0x0232,
159 i40e_aqc_opc_delete_element = 0x0243,
161 i40e_aqc_opc_add_macvlan = 0x0250,
162 i40e_aqc_opc_remove_macvlan = 0x0251,
163 i40e_aqc_opc_add_vlan = 0x0252,
164 i40e_aqc_opc_remove_vlan = 0x0253,
165 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
166 i40e_aqc_opc_add_tag = 0x0255,
167 i40e_aqc_opc_remove_tag = 0x0256,
168 i40e_aqc_opc_add_multicast_etag = 0x0257,
169 i40e_aqc_opc_remove_multicast_etag = 0x0258,
170 i40e_aqc_opc_update_tag = 0x0259,
171 i40e_aqc_opc_add_control_packet_filter = 0x025A,
172 i40e_aqc_opc_remove_control_packet_filter = 0x025B,
173 i40e_aqc_opc_add_cloud_filters = 0x025C,
174 i40e_aqc_opc_remove_cloud_filters = 0x025D,
175 i40e_aqc_opc_clear_wol_switch_filters = 0x025E,
176 i40e_aqc_opc_replace_cloud_filters = 0x025F,
178 i40e_aqc_opc_add_mirror_rule = 0x0260,
179 i40e_aqc_opc_delete_mirror_rule = 0x0261,
181 /* Dynamic Device Personalization */
182 i40e_aqc_opc_write_personalization_profile = 0x0270,
183 i40e_aqc_opc_get_personalization_profile_list = 0x0271,
186 i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
187 i40e_aqc_opc_dcb_updated = 0x0302,
188 i40e_aqc_opc_set_dcb_parameters = 0x0303,
191 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
192 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
193 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
194 i40e_aqc_opc_query_vsi_bw_config = 0x0408,
195 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
196 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
198 i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
199 i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
200 i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
201 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
202 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
203 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
204 i40e_aqc_opc_query_port_ets_config = 0x0419,
205 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
206 i40e_aqc_opc_suspend_port_tx = 0x041B,
207 i40e_aqc_opc_resume_port_tx = 0x041C,
208 i40e_aqc_opc_configure_partition_bw = 0x041D,
210 i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
211 i40e_aqc_opc_set_hmc_resource_profile = 0x0501,
214 i40e_aqc_opc_get_phy_abilities = 0x0600,
215 i40e_aqc_opc_set_phy_config = 0x0601,
216 i40e_aqc_opc_set_mac_config = 0x0603,
217 i40e_aqc_opc_set_link_restart_an = 0x0605,
218 i40e_aqc_opc_get_link_status = 0x0607,
219 i40e_aqc_opc_set_phy_int_mask = 0x0613,
220 i40e_aqc_opc_get_local_advt_reg = 0x0614,
221 i40e_aqc_opc_set_local_advt_reg = 0x0615,
222 i40e_aqc_opc_get_partner_advt = 0x0616,
223 i40e_aqc_opc_set_lb_modes = 0x0618,
224 i40e_aqc_opc_get_phy_wol_caps = 0x0621,
225 i40e_aqc_opc_set_phy_debug = 0x0622,
226 i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
227 i40e_aqc_opc_run_phy_activity = 0x0626,
228 i40e_aqc_opc_set_phy_register = 0x0628,
229 i40e_aqc_opc_get_phy_register = 0x0629,
232 i40e_aqc_opc_nvm_read = 0x0701,
233 i40e_aqc_opc_nvm_erase = 0x0702,
234 i40e_aqc_opc_nvm_update = 0x0703,
235 i40e_aqc_opc_nvm_config_read = 0x0704,
236 i40e_aqc_opc_nvm_config_write = 0x0705,
237 i40e_aqc_opc_nvm_progress = 0x0706,
238 i40e_aqc_opc_oem_post_update = 0x0720,
239 i40e_aqc_opc_thermal_sensor = 0x0721,
241 /* virtualization commands */
242 i40e_aqc_opc_send_msg_to_pf = 0x0801,
243 i40e_aqc_opc_send_msg_to_vf = 0x0802,
244 i40e_aqc_opc_send_msg_to_peer = 0x0803,
246 /* alternate structure */
247 i40e_aqc_opc_alternate_write = 0x0900,
248 i40e_aqc_opc_alternate_write_indirect = 0x0901,
249 i40e_aqc_opc_alternate_read = 0x0902,
250 i40e_aqc_opc_alternate_read_indirect = 0x0903,
251 i40e_aqc_opc_alternate_write_done = 0x0904,
252 i40e_aqc_opc_alternate_set_mode = 0x0905,
253 i40e_aqc_opc_alternate_clear_port = 0x0906,
256 i40e_aqc_opc_lldp_get_mib = 0x0A00,
257 i40e_aqc_opc_lldp_update_mib = 0x0A01,
258 i40e_aqc_opc_lldp_add_tlv = 0x0A02,
259 i40e_aqc_opc_lldp_update_tlv = 0x0A03,
260 i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
261 i40e_aqc_opc_lldp_stop = 0x0A05,
262 i40e_aqc_opc_lldp_start = 0x0A06,
263 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07,
264 i40e_aqc_opc_lldp_set_local_mib = 0x0A08,
265 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09,
267 /* Tunnel commands */
268 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
269 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
270 i40e_aqc_opc_set_rss_key = 0x0B02,
271 i40e_aqc_opc_set_rss_lut = 0x0B03,
272 i40e_aqc_opc_get_rss_key = 0x0B04,
273 i40e_aqc_opc_get_rss_lut = 0x0B05,
276 i40e_aqc_opc_event_lan_overflow = 0x1001,
279 i40e_aqc_opc_oem_parameter_change = 0xFE00,
280 i40e_aqc_opc_oem_device_status_change = 0xFE01,
281 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02,
282 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03,
285 i40e_aqc_opc_debug_read_reg = 0xFF03,
286 i40e_aqc_opc_debug_write_reg = 0xFF04,
287 i40e_aqc_opc_debug_modify_reg = 0xFF07,
288 i40e_aqc_opc_debug_dump_internals = 0xFF08,
291 /* command structures and indirect data structures */
293 /* Structure naming conventions:
294 * - no suffix for direct command descriptor structures
295 * - _data for indirect sent data
296 * - _resp for indirect return data (data which is both will use _data)
297 * - _completion for direct return data
298 * - _element_ for repeated elements (may also be _data or _resp)
300 * Command structures are expected to overlay the params.raw member of the basic
301 * descriptor, and as such cannot exceed 16 bytes in length.
304 /* This macro is used to generate a compilation error if a structure
305 * is not exactly the correct length. It gives a divide by zero error if the
306 * structure is not of the correct size, otherwise it creates an enum that is
309 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
310 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
312 /* This macro is used extensively to ensure that command structures are 16
313 * bytes in length as they have to map to the raw array of that size.
315 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
317 /* internal (0x00XX) commands */
319 /* Get version (direct 0x0001) */
320 struct i40e_aqc_get_version {
329 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
331 /* Send driver version (indirect 0x0002) */
332 struct i40e_aqc_driver_version {
336 u8 driver_subbuild_ver;
342 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
344 /* Queue Shutdown (direct 0x0003) */
345 struct i40e_aqc_queue_shutdown {
346 __le32 driver_unloading;
347 #define I40E_AQ_DRIVER_UNLOADING 0x1
351 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
353 /* Set PF context (0x0004, direct) */
354 struct i40e_aqc_set_pf_context {
359 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
361 /* Request resource ownership (direct 0x0008)
362 * Release resource ownership (direct 0x0009)
364 #define I40E_AQ_RESOURCE_NVM 1
365 #define I40E_AQ_RESOURCE_SDP 2
366 #define I40E_AQ_RESOURCE_ACCESS_READ 1
367 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2
368 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
369 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
371 struct i40e_aqc_request_resource {
375 __le32 resource_number;
379 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
381 /* Get function capabilities (indirect 0x000A)
382 * Get device capabilities (indirect 0x000B)
384 struct i40e_aqc_list_capabilites {
386 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1
394 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
396 struct i40e_aqc_list_capabilities_element_resp {
408 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
409 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002
410 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
411 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
412 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
413 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006
414 #define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008
415 #define I40E_AQ_CAP_ID_SRIOV 0x0012
416 #define I40E_AQ_CAP_ID_VF 0x0013
417 #define I40E_AQ_CAP_ID_VMDQ 0x0014
418 #define I40E_AQ_CAP_ID_8021QBG 0x0015
419 #define I40E_AQ_CAP_ID_8021QBR 0x0016
420 #define I40E_AQ_CAP_ID_VSI 0x0017
421 #define I40E_AQ_CAP_ID_DCB 0x0018
422 #define I40E_AQ_CAP_ID_FCOE 0x0021
423 #define I40E_AQ_CAP_ID_ISCSI 0x0022
424 #define I40E_AQ_CAP_ID_RSS 0x0040
425 #define I40E_AQ_CAP_ID_RXQ 0x0041
426 #define I40E_AQ_CAP_ID_TXQ 0x0042
427 #define I40E_AQ_CAP_ID_MSIX 0x0043
428 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044
429 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
430 #define I40E_AQ_CAP_ID_1588 0x0046
431 #define I40E_AQ_CAP_ID_IWARP 0x0051
432 #define I40E_AQ_CAP_ID_LED 0x0061
433 #define I40E_AQ_CAP_ID_SDP 0x0062
434 #define I40E_AQ_CAP_ID_MDIO 0x0063
435 #define I40E_AQ_CAP_ID_WSR_PROT 0x0064
436 #define I40E_AQ_CAP_ID_NVM_MGMT 0x0080
437 #define I40E_AQ_CAP_ID_FLEX10 0x00F1
438 #define I40E_AQ_CAP_ID_CEM 0x00F2
440 /* Set CPPM Configuration (direct 0x0103) */
441 struct i40e_aqc_cppm_configuration {
442 __le16 command_flags;
443 #define I40E_AQ_CPPM_EN_LTRC 0x0800
444 #define I40E_AQ_CPPM_EN_DMCTH 0x1000
445 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000
446 #define I40E_AQ_CPPM_EN_HPTC 0x4000
447 #define I40E_AQ_CPPM_EN_DMARC 0x8000
456 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
458 /* Set ARP Proxy command / response (indirect 0x0104) */
459 struct i40e_aqc_arp_proxy_data {
460 __le16 command_flags;
461 #define I40E_AQ_ARP_INIT_IPV4 0x0800
462 #define I40E_AQ_ARP_UNSUP_CTL 0x1000
463 #define I40E_AQ_ARP_ENA 0x2000
464 #define I40E_AQ_ARP_ADD_IPV4 0x4000
465 #define I40E_AQ_ARP_DEL_IPV4 0x8000
467 __le32 enabled_offloads;
468 #define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020
469 #define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800
475 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
477 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
478 struct i40e_aqc_ns_proxy_data {
479 __le16 table_idx_mac_addr_0;
480 __le16 table_idx_mac_addr_1;
481 __le16 table_idx_ipv6_0;
482 __le16 table_idx_ipv6_1;
484 #define I40E_AQ_NS_PROXY_ADD_0 0x0001
485 #define I40E_AQ_NS_PROXY_DEL_0 0x0002
486 #define I40E_AQ_NS_PROXY_ADD_1 0x0004
487 #define I40E_AQ_NS_PROXY_DEL_1 0x0008
488 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010
489 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020
490 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040
491 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080
492 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100
493 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200
494 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400
495 #define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800
496 #define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000
499 u8 local_mac_addr[6];
500 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
504 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
506 /* Manage LAA Command (0x0106) - obsolete */
507 struct i40e_aqc_mng_laa {
508 __le16 command_flags;
509 #define I40E_AQ_LAA_FLAG_WR 0x8000
516 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);
518 /* Manage MAC Address Read Command (indirect 0x0107) */
519 struct i40e_aqc_mac_address_read {
520 __le16 command_flags;
521 #define I40E_AQC_LAN_ADDR_VALID 0x10
522 #define I40E_AQC_SAN_ADDR_VALID 0x20
523 #define I40E_AQC_PORT_ADDR_VALID 0x40
524 #define I40E_AQC_WOL_ADDR_VALID 0x80
525 #define I40E_AQC_MC_MAG_EN_VALID 0x100
526 #define I40E_AQC_WOL_PRESERVE_STATUS 0x200
527 #define I40E_AQC_ADDR_VALID_MASK 0x3F0
533 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
535 struct i40e_aqc_mac_address_read_data {
542 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
544 /* Manage MAC Address Write Command (0x0108) */
545 struct i40e_aqc_mac_address_write {
546 __le16 command_flags;
547 #define I40E_AQC_MC_MAG_EN 0x0100
548 #define I40E_AQC_WOL_PRESERVE_ON_PFR 0x0200
549 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
550 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
551 #define I40E_AQC_WRITE_TYPE_PORT 0x8000
552 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
553 #define I40E_AQC_WRITE_TYPE_MASK 0xC000
560 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
562 /* PXE commands (0x011x) */
564 /* Clear PXE Command and response (direct 0x0110) */
565 struct i40e_aqc_clear_pxe {
570 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
572 /* Set WoL Filter (0x0120) */
574 struct i40e_aqc_set_wol_filter {
576 #define I40E_AQC_MAX_NUM_WOL_FILTERS 8
577 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15
578 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \
579 I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT)
581 #define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0
582 #define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \
583 I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT)
585 #define I40E_AQC_SET_WOL_FILTER 0x8000
586 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000
587 #define I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR 0x2000
588 #define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0
589 #define I40E_AQC_SET_WOL_FILTER_ACTION_SET 1
591 #define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000
592 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000
598 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter);
600 struct i40e_aqc_set_wol_filter_data {
605 I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data);
607 /* Get Wake Reason (0x0121) */
609 struct i40e_aqc_get_wake_reason_completion {
612 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0
613 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \
614 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT)
615 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8
616 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \
617 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT)
621 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion);
623 /* Switch configuration commands (0x02xx) */
625 /* Used by many indirect commands that only pass an seid and a buffer in the
628 struct i40e_aqc_switch_seid {
635 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
637 /* Get Switch Configuration command (indirect 0x0200)
638 * uses i40e_aqc_switch_seid for the descriptor
640 struct i40e_aqc_get_switch_config_header_resp {
646 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);
648 struct i40e_aqc_switch_config_element_resp {
650 #define I40E_AQ_SW_ELEM_TYPE_MAC 1
651 #define I40E_AQ_SW_ELEM_TYPE_PF 2
652 #define I40E_AQ_SW_ELEM_TYPE_VF 3
653 #define I40E_AQ_SW_ELEM_TYPE_EMP 4
654 #define I40E_AQ_SW_ELEM_TYPE_BMC 5
655 #define I40E_AQ_SW_ELEM_TYPE_PV 16
656 #define I40E_AQ_SW_ELEM_TYPE_VEB 17
657 #define I40E_AQ_SW_ELEM_TYPE_PA 18
658 #define I40E_AQ_SW_ELEM_TYPE_VSI 19
660 #define I40E_AQ_SW_ELEM_REV_1 1
663 __le16 downlink_seid;
666 #define I40E_AQ_CONN_TYPE_REGULAR 0x1
667 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2
668 #define I40E_AQ_CONN_TYPE_CASCADED 0x3
673 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
675 /* Get Switch Configuration (indirect 0x0200)
676 * an array of elements are returned in the response buffer
677 * the first in the array is the header, remainder are elements
679 struct i40e_aqc_get_switch_config_resp {
680 struct i40e_aqc_get_switch_config_header_resp header;
681 struct i40e_aqc_switch_config_element_resp element[1];
684 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
686 /* Add Statistics (direct 0x0201)
687 * Remove Statistics (direct 0x0202)
689 struct i40e_aqc_add_remove_statistics {
696 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
698 /* Set Port Parameters command (direct 0x0203) */
699 struct i40e_aqc_set_port_parameters {
700 __le16 command_flags;
701 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
702 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
703 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
704 __le16 bad_frame_vsi;
705 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0
706 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF
707 __le16 default_seid; /* reserved for command */
711 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
713 /* Get Switch Resource Allocation (indirect 0x0204) */
714 struct i40e_aqc_get_switch_resource_alloc {
715 u8 num_entries; /* reserved for command */
721 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
723 /* expect an array of these structs in the response buffer */
724 struct i40e_aqc_switch_resource_alloc_element_resp {
726 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0
727 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1
728 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2
729 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3
730 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4
731 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
732 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
733 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7
734 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
735 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
736 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
737 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
738 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
739 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
740 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
741 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
742 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
743 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
744 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
749 __le16 total_unalloced;
753 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
755 /* Set Switch Configuration (direct 0x0205) */
756 struct i40e_aqc_set_switch_config {
758 /* flags used for both fields below */
759 #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001
760 #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002
761 #define I40E_AQ_SET_SWITCH_CFG_HW_ATR_EVICT 0x0004
763 /* The ethertype in switch_tag is dropped on ingress and used
764 * internally by the switch. Set this to zero for the default
765 * of 0x88a8 (802.1ad). Should be zero for firmware API
766 * versions lower than 1.7.
769 /* The ethertypes in first_tag and second_tag are used to
770 * match the outer and inner VLAN tags (respectively) when HW
771 * double VLAN tagging is enabled via the set port parameters
772 * AQ command. Otherwise these are both ignored. Set them to
773 * zero for their defaults of 0x8100 (802.1Q). Should be zero
774 * for firmware API versions lower than 1.7.
778 /* Next byte is split into following:
779 * Bit 7 : 0 : No action, 1: Switch to mode defined by bits 6:0
780 * Bit 6 : 0 : Destination Port, 1: source port
785 * 3: Both TCP and UDP
788 * 1: L4 port only mode
789 * 2: non-tunneled mode
792 #define I40E_AQ_SET_SWITCH_BIT7_VALID 0x80
794 #define I40E_AQ_SET_SWITCH_L4_SRC_PORT 0x40
796 #define I40E_AQ_SET_SWITCH_L4_TYPE_RSVD 0x00
797 #define I40E_AQ_SET_SWITCH_L4_TYPE_TCP 0x10
798 #define I40E_AQ_SET_SWITCH_L4_TYPE_UDP 0x20
799 #define I40E_AQ_SET_SWITCH_L4_TYPE_BOTH 0x30
801 #define I40E_AQ_SET_SWITCH_MODE_DEFAULT 0x00
802 #define I40E_AQ_SET_SWITCH_MODE_L4_PORT 0x01
803 #define I40E_AQ_SET_SWITCH_MODE_NON_TUNNEL 0x02
804 #define I40E_AQ_SET_SWITCH_MODE_TUNNEL 0x03
809 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config);
811 /* Read Receive control registers (direct 0x0206)
812 * Write Receive control registers (direct 0x0207)
813 * used for accessing Rx control registers that can be
814 * slow and need special handling when under high Rx load
816 struct i40e_aqc_rx_ctl_reg_read_write {
823 I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write);
825 /* Add VSI (indirect 0x0210)
826 * this indirect command uses struct i40e_aqc_vsi_properties_data
827 * as the indirect buffer (128 bytes)
829 * Update VSI (indirect 0x211)
830 * uses the same data structure as Add VSI
832 * Get VSI (indirect 0x0212)
833 * uses the same completion and data structure as Add VSI
835 struct i40e_aqc_add_get_update_vsi {
838 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
839 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2
840 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3
845 #define I40E_AQ_VSI_TYPE_SHIFT 0x0
846 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
847 #define I40E_AQ_VSI_TYPE_VF 0x0
848 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1
849 #define I40E_AQ_VSI_TYPE_PF 0x2
850 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3
851 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4
856 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
858 struct i40e_aqc_add_get_update_vsi_completion {
867 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
869 struct i40e_aqc_vsi_properties_data {
870 /* first 96 byte are written by SW */
871 __le16 valid_sections;
872 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
873 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
874 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
875 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008
876 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
877 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
878 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
879 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
880 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
881 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
883 __le16 switch_id; /* 12bit id combined with flags below */
884 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
885 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
886 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
887 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
888 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
890 /* security section */
892 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
893 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
894 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
897 __le16 pvid; /* VLANS include priority bits */
900 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
901 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
902 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
903 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
904 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
905 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
906 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
907 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
908 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
909 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
910 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
911 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
912 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
913 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
914 u8 pvlan_reserved[3];
915 /* ingress egress up sections */
916 __le32 ingress_table; /* bitmap, 3 bits per up */
917 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
918 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
919 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
920 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3
921 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
922 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
923 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6
924 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
925 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
926 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9
927 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
928 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
929 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12
930 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
931 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
932 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15
933 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
934 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
935 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18
936 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
937 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
938 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21
939 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
940 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
941 __le32 egress_table; /* same defines as for ingress table */
942 /* cascaded PV section */
945 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
946 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
947 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
948 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
949 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
950 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02
951 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10
952 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
953 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
955 /* queue mapping section */
956 __le16 mapping_flags;
957 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
958 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
959 __le16 queue_mapping[16];
960 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0
961 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
962 __le16 tc_mapping[8];
963 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
964 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
965 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
966 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
967 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
968 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
969 /* queueing option section */
970 u8 queueing_opt_flags;
971 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04
972 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08
973 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
974 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
975 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00
976 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
977 u8 queueing_opt_reserved[3];
978 /* scheduler section */
981 /* outer up section */
982 __le32 outer_up_table; /* same structure and defines as ingress tbl */
984 /* last 32 bytes are written by FW */
986 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
987 __le16 stat_counter_idx;
989 u8 resp_reserved[12];
992 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
994 /* Add Port Virtualizer (direct 0x0220)
995 * also used for update PV (direct 0x0221) but only flags are used
996 * (IS_CTRL_PORT only works on add PV)
998 struct i40e_aqc_add_update_pv {
999 __le16 command_flags;
1000 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1
1001 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
1002 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
1003 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8
1005 __le16 connected_seid;
1009 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
1011 struct i40e_aqc_add_update_pv_completion {
1012 /* reserved for update; for add also encodes error if rc == ENOSPC */
1014 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1
1015 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2
1016 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
1017 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
1021 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
1023 /* Get PV Params (direct 0x0222)
1024 * uses i40e_aqc_switch_seid for the descriptor
1027 struct i40e_aqc_get_pv_params_completion {
1029 __le16 default_stag;
1030 __le16 pv_flags; /* same flags as add_pv */
1031 #define I40E_AQC_GET_PV_PV_TYPE 0x1
1032 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
1033 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
1035 __le16 default_port_seid;
1038 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
1040 /* Add VEB (direct 0x0230) */
1041 struct i40e_aqc_add_veb {
1043 __le16 downlink_seid;
1045 #define I40E_AQC_ADD_VEB_FLOATING 0x1
1046 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
1047 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
1048 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
1049 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
1050 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
1051 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */
1052 #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10
1057 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
1059 struct i40e_aqc_add_veb_completion {
1062 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
1064 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1
1065 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
1066 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
1067 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
1068 __le16 statistic_index;
1073 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
1075 /* Get VEB Parameters (direct 0x0232)
1076 * uses i40e_aqc_switch_seid for the descriptor
1078 struct i40e_aqc_get_veb_parameters_completion {
1081 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
1082 __le16 statistic_index;
1088 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
1090 /* Delete Element (direct 0x0243)
1091 * uses the generic i40e_aqc_switch_seid
1094 /* Add MAC-VLAN (indirect 0x0250) */
1096 /* used for the command for most vlan commands */
1097 struct i40e_aqc_macvlan {
1098 __le16 num_addresses;
1100 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
1101 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
1102 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1103 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
1108 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
1110 /* indirect data for command and response */
1111 struct i40e_aqc_add_macvlan_element_data {
1115 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
1116 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
1117 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
1118 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
1119 #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010
1120 __le16 queue_number;
1121 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
1122 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
1123 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1124 /* response section */
1126 #define I40E_AQC_MM_PERFECT_MATCH 0x01
1127 #define I40E_AQC_MM_HASH_MATCH 0x02
1128 #define I40E_AQC_MM_ERR_NO_RES 0xFF
1132 struct i40e_aqc_add_remove_macvlan_completion {
1133 __le16 perfect_mac_used;
1134 __le16 perfect_mac_free;
1135 __le16 unicast_hash_free;
1136 __le16 multicast_hash_free;
1141 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
1143 /* Remove MAC-VLAN (indirect 0x0251)
1144 * uses i40e_aqc_macvlan for the descriptor
1145 * data points to an array of num_addresses of elements
1148 struct i40e_aqc_remove_macvlan_element_data {
1152 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
1153 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02
1154 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
1155 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10
1159 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0
1160 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF
1161 u8 reply_reserved[3];
1164 /* Add VLAN (indirect 0x0252)
1165 * Remove VLAN (indirect 0x0253)
1166 * use the generic i40e_aqc_macvlan for the command
1168 struct i40e_aqc_add_remove_vlan_element_data {
1171 /* flags for add VLAN */
1172 #define I40E_AQC_ADD_VLAN_LOCAL 0x1
1173 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1
1174 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1175 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
1176 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
1177 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
1178 #define I40E_AQC_VLAN_PTYPE_SHIFT 3
1179 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1180 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
1181 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
1182 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
1183 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
1184 /* flags for remove VLAN */
1185 #define I40E_AQC_REMOVE_VLAN_ALL 0x1
1188 /* flags for add VLAN */
1189 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0
1190 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
1191 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
1192 /* flags for remove VLAN */
1193 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0
1194 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF
1198 struct i40e_aqc_add_remove_vlan_completion {
1206 /* Set VSI Promiscuous Modes (direct 0x0254) */
1207 struct i40e_aqc_set_vsi_promiscuous_modes {
1208 __le16 promiscuous_flags;
1210 /* flags used for both fields above */
1211 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
1212 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1213 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1214 #define I40E_AQC_SET_VSI_DEFAULT 0x08
1215 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
1216 #define I40E_AQC_SET_VSI_PROMISC_TX 0x8000
1218 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
1220 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF
1221 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
1225 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1227 /* Add S/E-tag command (direct 0x0255)
1228 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1230 struct i40e_aqc_add_tag {
1232 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
1234 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
1235 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1236 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1238 __le16 queue_number;
1242 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1244 struct i40e_aqc_add_remove_tag_completion {
1250 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1252 /* Remove S/E-tag command (direct 0x0256)
1253 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1255 struct i40e_aqc_remove_tag {
1257 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
1258 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1259 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1264 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);
1266 /* Add multicast E-Tag (direct 0x0257)
1267 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1268 * and no external data
1270 struct i40e_aqc_add_remove_mcast_etag {
1273 u8 num_unicast_etags;
1275 __le32 addr_high; /* address of array of 2-byte s-tags */
1279 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1281 struct i40e_aqc_add_remove_mcast_etag_completion {
1283 __le16 mcast_etags_used;
1284 __le16 mcast_etags_free;
1290 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1292 /* Update S/E-Tag (direct 0x0259) */
1293 struct i40e_aqc_update_tag {
1295 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
1296 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1297 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1303 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1305 struct i40e_aqc_update_tag_completion {
1311 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1313 /* Add Control Packet filter (direct 0x025A)
1314 * Remove Control Packet filter (direct 0x025B)
1315 * uses the i40e_aqc_add_oveb_cloud,
1316 * and the generic direct completion structure
1318 struct i40e_aqc_add_remove_control_packet_filter {
1322 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1323 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1324 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
1325 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1326 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
1328 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
1329 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
1330 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1335 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1337 struct i40e_aqc_add_remove_control_packet_filter_completion {
1338 __le16 mac_etype_used;
1340 __le16 mac_etype_free;
1345 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1347 /* Add Cloud filters (indirect 0x025C)
1348 * Remove Cloud filters (indirect 0x025D)
1349 * uses the i40e_aqc_add_remove_cloud_filters,
1350 * and the generic indirect completion structure
1352 struct i40e_aqc_add_remove_cloud_filters {
1356 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
1357 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
1358 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1360 #define I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER 1
1361 #define I40E_AQC_ADD_CLOUD_CMD_BB 1
1367 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1369 struct i40e_aqc_cloud_filters_element_data {
1386 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
1387 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
1388 I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1389 /* 0x0000 reserved */
1390 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001
1391 /* 0x0002 reserved */
1392 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1393 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
1394 /* 0x0005 reserved */
1395 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
1396 /* 0x0007 reserved */
1397 /* 0x0008 reserved */
1398 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1399 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1400 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1401 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1402 /* 0x0010 to 0x0017 is for custom filters */
1403 #define I40E_AQC_ADD_CLOUD_FILTER_IP_PORT 0x0010 /* Dest IP + L4 Port */
1404 #define I40E_AQC_ADD_CLOUD_FILTER_MAC_PORT 0x0011 /* Dest MAC + L4 Port */
1405 #define I40E_AQC_ADD_CLOUD_FILTER_MAC_VLAN_PORT 0x0012 /* Dest MAC + VLAN + L4 Port */
1407 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
1408 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6
1409 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0
1410 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1411 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1413 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1414 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1415 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0
1416 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
1417 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2
1418 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3
1419 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4
1420 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5
1422 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000
1423 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000
1424 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000
1428 __le16 queue_number;
1429 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
1430 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \
1431 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1433 /* response section */
1434 u8 allocation_result;
1435 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
1436 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
1437 u8 response_reserved[7];
1440 /* i40e_aqc_add_rm_cloud_filt_elem_ext is used when
1441 * I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER flag is set. refer to
1444 struct i40e_aqc_add_rm_cloud_filt_elem_ext {
1445 struct i40e_aqc_cloud_filters_element_data element;
1446 u16 general_fields[32];
1447 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0 0
1448 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1 1
1449 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2 2
1450 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0 3
1451 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1 4
1452 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2 5
1453 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0 6
1454 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1 7
1455 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2 8
1456 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0 9
1457 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1 10
1458 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2 11
1459 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0 12
1460 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1 13
1461 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2 14
1462 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0 15
1463 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1 16
1464 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2 17
1465 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3 18
1466 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4 19
1467 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5 20
1468 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6 21
1469 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7 22
1470 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0 23
1471 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1 24
1472 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2 25
1473 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3 26
1474 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4 27
1475 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5 28
1476 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6 29
1477 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7 30
1480 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_cloud_filters_element_data);
1482 /* i40e_aqc_cloud_filters_element_bb is used when
1483 * I40E_AQC_CLOUD_CMD_BB flag is set.
1485 struct i40e_aqc_cloud_filters_element_bb {
1486 struct i40e_aqc_cloud_filters_element_data element;
1487 u16 general_fields[32];
1488 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0 0
1489 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1 1
1490 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2 2
1491 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0 3
1492 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1 4
1493 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2 5
1494 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0 6
1495 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1 7
1496 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2 8
1497 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0 9
1498 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1 10
1499 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2 11
1500 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0 12
1501 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1 13
1502 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2 14
1503 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0 15
1504 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1 16
1505 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2 17
1506 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3 18
1507 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4 19
1508 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5 20
1509 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6 21
1510 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7 22
1511 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0 23
1512 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1 24
1513 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2 25
1514 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3 26
1515 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4 27
1516 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5 28
1517 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6 29
1518 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7 30
1521 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_cloud_filters_element_bb);
1523 struct i40e_aqc_remove_cloud_filters_completion {
1524 __le16 perfect_ovlan_used;
1525 __le16 perfect_ovlan_free;
1532 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1534 /* Replace filter Command 0x025F
1535 * uses the i40e_aqc_replace_cloud_filters,
1536 * and the generic indirect completion structure
1538 struct i40e_filter_data {
1543 I40E_CHECK_STRUCT_LEN(4, i40e_filter_data);
1545 struct i40e_aqc_replace_cloud_filters_cmd {
1547 #define I40E_AQC_REPLACE_L1_FILTER 0x0
1548 #define I40E_AQC_REPLACE_CLOUD_FILTER 0x1
1549 #define I40E_AQC_GET_CLOUD_FILTERS 0x2
1550 #define I40E_AQC_MIRROR_CLOUD_FILTER 0x4
1551 #define I40E_AQC_HIGH_PRIORITY_CLOUD_FILTER 0x8
1560 I40E_CHECK_CMD_LENGTH(i40e_aqc_replace_cloud_filters_cmd);
1562 struct i40e_aqc_replace_cloud_filters_cmd_buf {
1564 /* Filter type INPUT codes*/
1565 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_ENTRIES_MAX 3
1566 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED (1 << 7UL)
1568 /* Field Vector offsets */
1569 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_MAC_DA 0
1570 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_ETH 6
1571 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG 7
1572 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN 8
1573 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_OVLAN 9
1574 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN 10
1575 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY 11
1576 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC 12
1578 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IP_DA 14
1580 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_OIP_DA 15
1582 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN 37
1583 struct i40e_filter_data filters[8];
1586 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_replace_cloud_filters_cmd_buf);
1588 /* Add Mirror Rule (indirect or direct 0x0260)
1589 * Delete Mirror Rule (indirect or direct 0x0261)
1590 * note: some rule types (4,5) do not use an external buffer.
1591 * take care to set the flags correctly.
1593 struct i40e_aqc_add_delete_mirror_rule {
1596 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1597 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1598 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1599 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1600 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
1601 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1602 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1603 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
1605 __le16 destination; /* VSI for add, rule id for delete */
1606 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
1610 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1612 struct i40e_aqc_add_delete_mirror_rule_completion {
1614 __le16 rule_id; /* only used on add */
1615 __le16 mirror_rules_used;
1616 __le16 mirror_rules_free;
1621 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1623 /* Dynamic Device Personalization */
1624 struct i40e_aqc_write_personalization_profile {
1627 __le32 profile_track_id;
1632 I40E_CHECK_CMD_LENGTH(i40e_aqc_write_personalization_profile);
1634 struct i40e_aqc_write_ddp_resp {
1635 __le32 error_offset;
1641 struct i40e_aqc_get_applied_profiles {
1643 #define I40E_AQC_GET_DDP_GET_CONF 0x1
1644 #define I40E_AQC_GET_DDP_GET_RDPU_CONF 0x2
1651 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_applied_profiles);
1655 /* PFC Ignore (direct 0x0301)
1656 * the command and response use the same descriptor structure
1658 struct i40e_aqc_pfc_ignore {
1660 u8 command_flags; /* unused on response */
1661 #define I40E_AQC_PFC_IGNORE_SET 0x80
1662 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0
1666 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1668 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1669 * with no parameters
1672 /* TX scheduler 0x04xx */
1674 /* Almost all the indirect commands use
1675 * this generic struct to pass the SEID in param0
1677 struct i40e_aqc_tx_sched_ind {
1684 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1686 /* Several commands respond with a set of queue set handles */
1687 struct i40e_aqc_qs_handles_resp {
1688 __le16 qs_handles[8];
1691 /* Configure VSI BW limits (direct 0x0400) */
1692 struct i40e_aqc_configure_vsi_bw_limit {
1697 u8 max_credit; /* 0-3, limit = 2^max */
1701 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1703 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1704 * responds with i40e_aqc_qs_handles_resp
1706 struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1709 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
1711 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1712 __le16 tc_bw_max[2];
1716 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
1718 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1719 * responds with i40e_aqc_qs_handles_resp
1721 struct i40e_aqc_configure_vsi_tc_bw_data {
1724 u8 tc_bw_credits[8];
1726 __le16 qs_handles[8];
1729 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
1731 /* Query vsi bw configuration (indirect 0x0408) */
1732 struct i40e_aqc_query_vsi_bw_config_resp {
1734 u8 tc_suspended_bits;
1736 __le16 qs_handles[8];
1738 __le16 port_bw_limit;
1740 u8 max_bw; /* 0-3, limit = 2^max */
1744 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
1746 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1747 struct i40e_aqc_query_vsi_ets_sla_config_resp {
1750 u8 share_credits[8];
1753 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1754 __le16 tc_bw_max[2];
1757 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
1759 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1760 struct i40e_aqc_configure_switching_comp_bw_limit {
1765 u8 max_bw; /* 0-3, limit = 2^max */
1769 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1771 /* Enable Physical Port ETS (indirect 0x0413)
1772 * Modify Physical Port ETS (indirect 0x0414)
1773 * Disable Physical Port ETS (indirect 0x0415)
1775 struct i40e_aqc_configure_switching_comp_ets_data {
1779 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1
1780 u8 tc_strict_priority_flags;
1782 u8 tc_bw_share_credits[8];
1786 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
1788 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1789 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1792 __le16 tc_bw_credit[8];
1794 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1795 __le16 tc_bw_max[2];
1799 I40E_CHECK_STRUCT_LEN(0x40,
1800 i40e_aqc_configure_switching_comp_ets_bw_limit_data);
1802 /* Configure Switching Component Bandwidth Allocation per Tc
1805 struct i40e_aqc_configure_switching_comp_bw_config_data {
1808 u8 absolute_credits; /* bool */
1809 u8 tc_bw_share_credits[8];
1813 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
1815 /* Query Switching Component Configuration (indirect 0x0418) */
1816 struct i40e_aqc_query_switching_comp_ets_config_resp {
1819 __le16 port_bw_limit;
1821 u8 tc_bw_max; /* 0-3, limit = 2^max */
1825 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
1827 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1828 struct i40e_aqc_query_port_ets_config_resp {
1832 u8 tc_strict_priority_bits;
1834 u8 tc_bw_share_credits[8];
1835 __le16 tc_bw_limits[8];
1837 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1838 __le16 tc_bw_max[2];
1842 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
1844 /* Query Switching Component Bandwidth Allocation per Traffic Type
1847 struct i40e_aqc_query_switching_comp_bw_config_resp {
1850 u8 absolute_credits_enable; /* bool */
1851 u8 tc_bw_share_credits[8];
1852 __le16 tc_bw_limits[8];
1854 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1855 __le16 tc_bw_max[2];
1858 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
1860 /* Suspend/resume port TX traffic
1861 * (direct 0x041B and 0x041C) uses the generic SEID struct
1864 /* Configure partition BW
1867 struct i40e_aqc_configure_partition_bw_data {
1868 __le16 pf_valid_bits;
1869 u8 min_bw[16]; /* guaranteed bandwidth */
1870 u8 max_bw[16]; /* bandwidth limit */
1873 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
1875 /* Get and set the active HMC resource profile and status.
1876 * (direct 0x0500) and (direct 0x0501)
1878 struct i40e_aq_get_set_hmc_resource_profile {
1884 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1886 enum i40e_aq_hmc_profile {
1887 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
1888 I40E_HMC_PROFILE_DEFAULT = 1,
1889 I40E_HMC_PROFILE_FAVOR_VF = 2,
1890 I40E_HMC_PROFILE_EQUAL = 3,
1893 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1895 /* set in param0 for get phy abilities to report qualified modules */
1896 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1897 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1899 enum i40e_aq_phy_type {
1900 I40E_PHY_TYPE_SGMII = 0x0,
1901 I40E_PHY_TYPE_1000BASE_KX = 0x1,
1902 I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
1903 I40E_PHY_TYPE_10GBASE_KR = 0x3,
1904 I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
1905 I40E_PHY_TYPE_XAUI = 0x5,
1906 I40E_PHY_TYPE_XFI = 0x6,
1907 I40E_PHY_TYPE_SFI = 0x7,
1908 I40E_PHY_TYPE_XLAUI = 0x8,
1909 I40E_PHY_TYPE_XLPPI = 0x9,
1910 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1911 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
1912 I40E_PHY_TYPE_10GBASE_AOC = 0xC,
1913 I40E_PHY_TYPE_40GBASE_AOC = 0xD,
1914 I40E_PHY_TYPE_UNRECOGNIZED = 0xE,
1915 I40E_PHY_TYPE_UNSUPPORTED = 0xF,
1916 I40E_PHY_TYPE_100BASE_TX = 0x11,
1917 I40E_PHY_TYPE_1000BASE_T = 0x12,
1918 I40E_PHY_TYPE_10GBASE_T = 0x13,
1919 I40E_PHY_TYPE_10GBASE_SR = 0x14,
1920 I40E_PHY_TYPE_10GBASE_LR = 0x15,
1921 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1922 I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
1923 I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
1924 I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
1925 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
1926 I40E_PHY_TYPE_1000BASE_SX = 0x1B,
1927 I40E_PHY_TYPE_1000BASE_LX = 0x1C,
1928 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
1929 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
1930 I40E_PHY_TYPE_25GBASE_KR = 0x1F,
1931 I40E_PHY_TYPE_25GBASE_CR = 0x20,
1932 I40E_PHY_TYPE_25GBASE_SR = 0x21,
1933 I40E_PHY_TYPE_25GBASE_LR = 0x22,
1934 I40E_PHY_TYPE_25GBASE_AOC = 0x23,
1935 I40E_PHY_TYPE_25GBASE_ACC = 0x24,
1937 I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD,
1938 I40E_PHY_TYPE_EMPTY = 0xFE,
1939 I40E_PHY_TYPE_DEFAULT = 0xFF,
1942 #define I40E_PHY_TYPES_BITMASK (BIT_ULL(I40E_PHY_TYPE_SGMII) | \
1943 BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) | \
1944 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) | \
1945 BIT_ULL(I40E_PHY_TYPE_10GBASE_KR) | \
1946 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4) | \
1947 BIT_ULL(I40E_PHY_TYPE_XAUI) | \
1948 BIT_ULL(I40E_PHY_TYPE_XFI) | \
1949 BIT_ULL(I40E_PHY_TYPE_SFI) | \
1950 BIT_ULL(I40E_PHY_TYPE_XLAUI) | \
1951 BIT_ULL(I40E_PHY_TYPE_XLPPI) | \
1952 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU) | \
1953 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU) | \
1954 BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC) | \
1955 BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) | \
1956 BIT_ULL(I40E_PHY_TYPE_UNRECOGNIZED) | \
1957 BIT_ULL(I40E_PHY_TYPE_UNSUPPORTED) | \
1958 BIT_ULL(I40E_PHY_TYPE_100BASE_TX) | \
1959 BIT_ULL(I40E_PHY_TYPE_1000BASE_T) | \
1960 BIT_ULL(I40E_PHY_TYPE_10GBASE_T) | \
1961 BIT_ULL(I40E_PHY_TYPE_10GBASE_SR) | \
1962 BIT_ULL(I40E_PHY_TYPE_10GBASE_LR) | \
1963 BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU) | \
1964 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1) | \
1965 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4) | \
1966 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4) | \
1967 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4) | \
1968 BIT_ULL(I40E_PHY_TYPE_1000BASE_SX) | \
1969 BIT_ULL(I40E_PHY_TYPE_1000BASE_LX) | \
1970 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) | \
1971 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) | \
1972 BIT_ULL(I40E_PHY_TYPE_25GBASE_KR) | \
1973 BIT_ULL(I40E_PHY_TYPE_25GBASE_CR) | \
1974 BIT_ULL(I40E_PHY_TYPE_25GBASE_SR) | \
1975 BIT_ULL(I40E_PHY_TYPE_25GBASE_LR) | \
1976 BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC) | \
1977 BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC))
1979 #define I40E_LINK_SPEED_100MB_SHIFT 0x1
1980 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1981 #define I40E_LINK_SPEED_10GB_SHIFT 0x3
1982 #define I40E_LINK_SPEED_40GB_SHIFT 0x4
1983 #define I40E_LINK_SPEED_20GB_SHIFT 0x5
1984 #define I40E_LINK_SPEED_25GB_SHIFT 0x6
1986 enum i40e_aq_link_speed {
1987 I40E_LINK_SPEED_UNKNOWN = 0,
1988 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT),
1989 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT),
1990 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT),
1991 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT),
1992 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT),
1993 I40E_LINK_SPEED_25GB = (1 << I40E_LINK_SPEED_25GB_SHIFT),
1996 struct i40e_aqc_module_desc {
2004 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
2006 struct i40e_aq_get_phy_abilities_resp {
2007 __le32 phy_type; /* bitmap using the above enum for offsets */
2008 u8 link_speed; /* bitmap using the above enum bit patterns */
2010 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
2011 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
2012 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04
2013 #define I40E_AQ_PHY_LINK_ENABLED 0x08
2014 #define I40E_AQ_PHY_AN_ENABLED 0x10
2015 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20
2016 #define I40E_AQ_PHY_FEC_ABILITY_KR 0x40
2017 #define I40E_AQ_PHY_FEC_ABILITY_RS 0x80
2018 __le16 eee_capability;
2019 #define I40E_AQ_EEE_100BASE_TX 0x0002
2020 #define I40E_AQ_EEE_1000BASE_T 0x0004
2021 #define I40E_AQ_EEE_10GBASE_T 0x0008
2022 #define I40E_AQ_EEE_1000BASE_KX 0x0010
2023 #define I40E_AQ_EEE_10GBASE_KX4 0x0020
2024 #define I40E_AQ_EEE_10GBASE_KR 0x0040
2027 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
2029 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0x01
2030 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0x02
2031 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04
2032 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
2033 #define I40E_AQ_PHY_TYPE_EXT_25G_AOC 0x10
2034 #define I40E_AQ_PHY_TYPE_EXT_25G_ACC 0x20
2035 u8 fec_cfg_curr_mod_ext_info;
2036 #define I40E_AQ_ENABLE_FEC_KR 0x01
2037 #define I40E_AQ_ENABLE_FEC_RS 0x02
2038 #define I40E_AQ_REQUEST_FEC_KR 0x04
2039 #define I40E_AQ_REQUEST_FEC_RS 0x08
2040 #define I40E_AQ_ENABLE_FEC_AUTO 0x10
2042 #define I40E_AQ_MODULE_TYPE_EXT_MASK 0xE0
2043 #define I40E_AQ_MODULE_TYPE_EXT_SHIFT 5
2048 u8 qualified_module_count;
2049 #define I40E_AQ_PHY_MAX_QMS 16
2050 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS];
2053 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
2055 /* Set PHY Config (direct 0x0601) */
2056 struct i40e_aq_set_phy_config { /* same bits as above in all */
2060 /* bits 0-2 use the values from get_phy_abilities_resp */
2061 #define I40E_AQ_PHY_ENABLE_LINK 0x08
2062 #define I40E_AQ_PHY_ENABLE_AN 0x10
2063 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
2064 __le16 eee_capability;
2069 #define I40E_AQ_SET_FEC_ABILITY_KR BIT(0)
2070 #define I40E_AQ_SET_FEC_ABILITY_RS BIT(1)
2071 #define I40E_AQ_SET_FEC_REQUEST_KR BIT(2)
2072 #define I40E_AQ_SET_FEC_REQUEST_RS BIT(3)
2073 #define I40E_AQ_SET_FEC_AUTO BIT(4)
2074 #define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0
2075 #define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT)
2079 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
2081 /* Set MAC Config command data structure (direct 0x0603) */
2082 struct i40e_aq_set_mac_config {
2083 __le16 max_frame_size;
2085 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
2086 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
2087 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
2088 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
2089 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
2090 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
2091 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
2092 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
2093 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
2094 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
2095 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
2096 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
2097 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
2098 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
2099 u8 tx_timer_priority; /* bitmap */
2100 __le16 tx_timer_value;
2101 __le16 fc_refresh_threshold;
2105 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
2107 /* Restart Auto-Negotiation (direct 0x605) */
2108 struct i40e_aqc_set_link_restart_an {
2110 #define I40E_AQ_PHY_RESTART_AN 0x02
2111 #define I40E_AQ_PHY_LINK_ENABLE 0x04
2115 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
2117 /* Get Link Status cmd & response data structure (direct 0x0607) */
2118 struct i40e_aqc_get_link_status {
2119 __le16 command_flags; /* only field set on command */
2120 #define I40E_AQ_LSE_MASK 0x3
2121 #define I40E_AQ_LSE_NOP 0x0
2122 #define I40E_AQ_LSE_DISABLE 0x2
2123 #define I40E_AQ_LSE_ENABLE 0x3
2124 /* only response uses this flag */
2125 #define I40E_AQ_LSE_IS_ENABLED 0x1
2126 u8 phy_type; /* i40e_aq_phy_type */
2127 u8 link_speed; /* i40e_aq_link_speed */
2129 #define I40E_AQ_LINK_UP 0x01 /* obsolete */
2130 #define I40E_AQ_LINK_UP_FUNCTION 0x01
2131 #define I40E_AQ_LINK_FAULT 0x02
2132 #define I40E_AQ_LINK_FAULT_TX 0x04
2133 #define I40E_AQ_LINK_FAULT_RX 0x08
2134 #define I40E_AQ_LINK_FAULT_REMOTE 0x10
2135 #define I40E_AQ_LINK_UP_PORT 0x20
2136 #define I40E_AQ_MEDIA_AVAILABLE 0x40
2137 #define I40E_AQ_SIGNAL_DETECT 0x80
2139 #define I40E_AQ_AN_COMPLETED 0x01
2140 #define I40E_AQ_LP_AN_ABILITY 0x02
2141 #define I40E_AQ_PD_FAULT 0x04
2142 #define I40E_AQ_FEC_EN 0x08
2143 #define I40E_AQ_PHY_LOW_POWER 0x10
2144 #define I40E_AQ_LINK_PAUSE_TX 0x20
2145 #define I40E_AQ_LINK_PAUSE_RX 0x40
2146 #define I40E_AQ_QUALIFIED_MODULE 0x80
2148 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01
2149 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02
2150 #define I40E_AQ_LINK_TX_SHIFT 0x02
2151 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT)
2152 #define I40E_AQ_LINK_TX_ACTIVE 0x00
2153 #define I40E_AQ_LINK_TX_DRAINED 0x01
2154 #define I40E_AQ_LINK_TX_FLUSHED 0x03
2155 #define I40E_AQ_LINK_FORCED_40G 0x10
2156 /* 25G Error Codes */
2157 #define I40E_AQ_25G_NO_ERR 0X00
2158 #define I40E_AQ_25G_NOT_PRESENT 0X01
2159 #define I40E_AQ_25G_NVM_CRC_ERR 0X02
2160 #define I40E_AQ_25G_SBUS_UCODE_ERR 0X03
2161 #define I40E_AQ_25G_SERDES_UCODE_ERR 0X04
2162 #define I40E_AQ_25G_NIMB_UCODE_ERR 0X05
2163 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
2164 /* Since firmware API 1.7 loopback field keeps power class info as well */
2165 #define I40E_AQ_LOOPBACK_MASK 0x07
2166 #define I40E_AQ_PWR_CLASS_SHIFT_LB 6
2167 #define I40E_AQ_PWR_CLASS_MASK_LB (0x03 << I40E_AQ_PWR_CLASS_SHIFT_LB)
2168 __le16 max_frame_size;
2170 #define I40E_AQ_CONFIG_FEC_KR_ENA 0x01
2171 #define I40E_AQ_CONFIG_FEC_RS_ENA 0x02
2172 #define I40E_AQ_CONFIG_CRC_ENA 0x04
2173 #define I40E_AQ_CONFIG_PACING_MASK 0x78
2177 #define I40E_AQ_LINK_POWER_CLASS_1 0x00
2178 #define I40E_AQ_LINK_POWER_CLASS_2 0x01
2179 #define I40E_AQ_LINK_POWER_CLASS_3 0x02
2180 #define I40E_AQ_LINK_POWER_CLASS_4 0x03
2181 #define I40E_AQ_PWR_CLASS_MASK 0x03
2191 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
2193 /* Set event mask command (direct 0x613) */
2194 struct i40e_aqc_set_phy_int_mask {
2197 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
2198 #define I40E_AQ_EVENT_MEDIA_NA 0x0004
2199 #define I40E_AQ_EVENT_LINK_FAULT 0x0008
2200 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010
2201 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
2202 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040
2203 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080
2204 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
2205 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
2209 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
2211 /* Get Local AN advt register (direct 0x0614)
2212 * Set Local AN advt register (direct 0x0615)
2213 * Get Link Partner AN advt register (direct 0x0616)
2215 struct i40e_aqc_an_advt_reg {
2216 __le32 local_an_reg0;
2217 __le16 local_an_reg1;
2221 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
2223 /* Set Loopback mode (0x0618) */
2224 struct i40e_aqc_set_lb_mode {
2226 #define I40E_AQ_LB_PHY_LOCAL 0x01
2227 #define I40E_AQ_LB_PHY_REMOTE 0x02
2228 #define I40E_AQ_LB_MAC_LOCAL 0x04
2232 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
2234 /* Set PHY Debug command (0x0622) */
2235 struct i40e_aqc_set_phy_debug {
2237 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
2238 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
2239 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
2240 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
2241 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
2242 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
2243 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
2244 /* Disable link manageability on a single port */
2245 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
2246 /* Disable link manageability on all ports needs both bits 4 and 5 */
2247 #define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20
2251 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
2253 enum i40e_aq_phy_reg_type {
2254 I40E_AQC_PHY_REG_INTERNAL = 0x1,
2255 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
2256 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
2259 /* Run PHY Activity (0x0626) */
2260 struct i40e_aqc_run_phy_activity {
2269 I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity);
2271 /* Set PHY Register command (0x0628) */
2272 /* Get PHY Register command (0x0629) */
2273 struct i40e_aqc_phy_register_access {
2275 #define I40E_AQ_PHY_REG_ACCESS_INTERNAL 0
2276 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL 1
2277 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE 2
2285 I40E_CHECK_CMD_LENGTH(i40e_aqc_phy_register_access);
2287 /* NVM Read command (indirect 0x0701)
2288 * NVM Erase commands (direct 0x0702)
2289 * NVM Update commands (indirect 0x0703)
2291 struct i40e_aqc_nvm_update {
2293 #define I40E_AQ_NVM_LAST_CMD 0x01
2294 #define I40E_AQ_NVM_FLASH_ONLY 0x80
2295 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT 1
2296 #define I40E_AQ_NVM_PRESERVATION_FLAGS_MASK 0x03
2297 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED 0x03
2298 #define I40E_AQ_NVM_PRESERVATION_FLAGS_ALL 0x01
2306 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
2308 /* NVM Config Read (indirect 0x0704) */
2309 struct i40e_aqc_nvm_config_read {
2311 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
2312 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0
2313 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1
2314 __le16 element_count;
2315 __le16 element_id; /* Feature/field ID */
2316 __le16 element_id_msw; /* MSWord of field ID */
2317 __le32 address_high;
2321 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
2323 /* NVM Config Write (indirect 0x0705) */
2324 struct i40e_aqc_nvm_config_write {
2326 __le16 element_count;
2328 __le32 address_high;
2332 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
2334 /* Used for 0x0704 as well as for 0x0705 commands */
2335 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1
2336 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \
2337 (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
2338 #define I40E_AQ_ANVM_FEATURE 0
2339 #define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT)
2340 struct i40e_aqc_nvm_config_data_feature {
2342 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01
2343 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08
2344 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10
2345 __le16 feature_options;
2346 __le16 feature_selection;
2349 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
2351 struct i40e_aqc_nvm_config_data_immediate_field {
2354 __le16 field_options;
2358 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
2360 /* OEM Post Update (indirect 0x0720)
2361 * no command data struct used
2363 struct i40e_aqc_nvm_oem_post_update {
2364 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01
2369 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
2371 struct i40e_aqc_nvm_oem_post_update_buffer {
2378 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
2380 /* Thermal Sensor (indirect 0x0721)
2381 * read or set thermal sensor configs and values
2382 * takes a sensor and command specific data buffer, not detailed here
2384 struct i40e_aqc_thermal_sensor {
2386 #define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0
2387 #define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1
2388 #define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2
2394 I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor);
2396 /* Send to PF command (indirect 0x0801) id is only used by PF
2397 * Send to VF command (indirect 0x0802) id is only used by PF
2398 * Send to Peer PF command (indirect 0x0803)
2400 struct i40e_aqc_pf_vf_message {
2407 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
2409 /* Alternate structure */
2411 /* Direct write (direct 0x0900)
2412 * Direct read (direct 0x0902)
2414 struct i40e_aqc_alternate_write {
2421 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
2423 /* Indirect write (indirect 0x0901)
2424 * Indirect read (indirect 0x0903)
2427 struct i40e_aqc_alternate_ind_write {
2434 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
2436 /* Done alternate write (direct 0x0904)
2439 struct i40e_aqc_alternate_write_done {
2441 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1
2442 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
2443 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1
2444 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2
2448 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
2450 /* Set OEM mode (direct 0x0905) */
2451 struct i40e_aqc_alternate_set_mode {
2453 #define I40E_AQ_ALTERNATE_MODE_NONE 0
2454 #define I40E_AQ_ALTERNATE_MODE_OEM 1
2458 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
2460 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
2462 /* async events 0x10xx */
2464 /* Lan Queue Overflow Event (direct, 0x1001) */
2465 struct i40e_aqc_lan_overflow {
2466 __le32 prtdcb_rupto;
2471 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
2473 /* Get LLDP MIB (indirect 0x0A00) */
2474 struct i40e_aqc_lldp_get_mib {
2477 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
2478 #define I40E_AQ_LLDP_MIB_LOCAL 0x0
2479 #define I40E_AQ_LLDP_MIB_REMOTE 0x1
2480 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
2481 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
2482 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
2483 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
2484 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
2485 #define I40E_AQ_LLDP_TX_SHIFT 0x4
2486 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT)
2487 /* TX pause flags use I40E_AQ_LINK_TX_* above */
2495 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
2497 /* Configure LLDP MIB Change Event (direct 0x0A01)
2498 * also used for the event (with type in the command field)
2500 struct i40e_aqc_lldp_update_mib {
2502 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
2503 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
2509 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
2511 /* Add LLDP TLV (indirect 0x0A02)
2512 * Delete LLDP TLV (indirect 0x0A04)
2514 struct i40e_aqc_lldp_add_tlv {
2515 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2523 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
2525 /* Update LLDP TLV (indirect 0x0A03) */
2526 struct i40e_aqc_lldp_update_tlv {
2527 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2536 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
2538 /* Stop LLDP (direct 0x0A05) */
2539 struct i40e_aqc_lldp_stop {
2541 #define I40E_AQ_LLDP_AGENT_STOP 0x0
2542 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
2546 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
2548 /* Start LLDP (direct 0x0A06) */
2550 struct i40e_aqc_lldp_start {
2552 #define I40E_AQ_LLDP_AGENT_START 0x1
2556 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
2558 /* Set DCB (direct 0x0303) */
2559 struct i40e_aqc_set_dcb_parameters {
2561 #define I40E_AQ_DCB_SET_AGENT 0x1
2562 #define I40E_DCB_VALID 0x1
2567 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_dcb_parameters);
2569 /* Get CEE DCBX Oper Config (0x0A07)
2570 * uses the generic descriptor struct
2571 * returns below as indirect response
2574 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2575 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2576 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2577 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2578 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2579 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2581 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2582 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2583 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2584 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2585 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2586 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2587 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8
2588 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT)
2589 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB
2590 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT)
2591 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10
2592 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT)
2594 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with
2595 * word boundary layout issues, which the Linux compilers silently deal
2596 * with by adding padding, making the actual struct larger than designed.
2597 * However, the FW compiler for the NIC is less lenient and complains
2598 * about the struct. Hence, the struct defined here has an extra byte in
2599 * fields reserved3 and reserved4 to directly acknowledge that padding,
2600 * and the new length is used in the length check macro.
2602 struct i40e_aqc_get_cee_dcb_cfg_v1_resp {
2610 __le16 oper_app_prio;
2615 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp);
2617 struct i40e_aqc_get_cee_dcb_cfg_resp {
2622 __le16 oper_app_prio;
2627 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp);
2629 /* Set Local LLDP MIB (indirect 0x0A08)
2630 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx
2632 struct i40e_aqc_lldp_set_local_mib {
2633 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0
2634 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \
2635 SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
2636 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0
2637 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1)
2638 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \
2639 SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT)
2640 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1
2645 __le32 address_high;
2649 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib);
2651 struct i40e_aqc_lldp_set_local_mib_resp {
2652 #define SET_LOCAL_MIB_RESP_EVENT_TRIGGERED_MASK 0x01
2657 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_lldp_set_local_mib_resp);
2659 /* Stop/Start LLDP Agent (direct 0x0A09)
2660 * Used for stopping/starting specific LLDP agent. e.g. DCBx
2662 struct i40e_aqc_lldp_stop_start_specific_agent {
2663 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0
2664 #define I40E_AQC_START_SPECIFIC_AGENT_MASK \
2665 (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT)
2670 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent);
2672 /* Add Udp Tunnel command and completion (direct 0x0B00) */
2673 struct i40e_aqc_add_udp_tunnel {
2677 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
2678 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01
2679 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10
2680 #define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11
2684 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2686 struct i40e_aqc_add_udp_tunnel_completion {
2688 u8 filter_entry_index;
2690 #define I40E_AQC_SINGLE_PF 0x0
2691 #define I40E_AQC_MULTIPLE_PFS 0x1
2696 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2698 /* remove UDP Tunnel command (0x0B01) */
2699 struct i40e_aqc_remove_udp_tunnel {
2701 u8 index; /* 0 to 15 */
2705 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2707 struct i40e_aqc_del_udp_tunnel_completion {
2709 u8 index; /* 0 to 15 */
2711 u8 total_filters_used;
2715 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2717 struct i40e_aqc_get_set_rss_key {
2718 #define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15)
2719 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
2720 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
2721 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2728 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);
2730 struct i40e_aqc_get_set_rss_key_data {
2731 u8 standard_rss_key[0x28];
2732 u8 extended_hash_key[0xc];
2735 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
2737 struct i40e_aqc_get_set_rss_lut {
2738 #define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15)
2739 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
2740 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
2741 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2743 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
2744 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \
2745 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2747 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
2748 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1
2755 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);
2757 /* tunnel key structure 0x0B10 */
2759 struct i40e_aqc_tunnel_key_structure {
2762 u8 key1_len; /* 0 to 15 */
2763 u8 key2_len; /* 0 to 15 */
2765 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2766 /* response flags */
2767 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2768 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2769 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2770 u8 network_key_index;
2771 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
2772 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1
2773 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
2774 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3
2778 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2780 /* OEM mode commands (direct 0xFE0x) */
2781 struct i40e_aqc_oem_param_change {
2783 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0
2784 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1
2785 #define I40E_AQ_OEM_PARAM_MAC 2
2786 __le32 param_value1;
2787 __le16 param_value2;
2791 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2793 struct i40e_aqc_oem_state_change {
2795 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0
2796 #define I40E_AQ_OEM_STATE_LINK_UP 0x1
2800 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2802 /* Initialize OCSD (0xFE02, direct) */
2803 struct i40e_aqc_opc_oem_ocsd_initialize {
2806 __le32 ocsd_memory_block_addr_high;
2807 __le32 ocsd_memory_block_addr_low;
2808 __le32 requested_update_interval;
2811 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);
2813 /* Initialize OCBB (0xFE03, direct) */
2814 struct i40e_aqc_opc_oem_ocbb_initialize {
2817 __le32 ocbb_memory_block_addr_high;
2818 __le32 ocbb_memory_block_addr_low;
2822 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);
2824 /* debug commands */
2826 /* get device id (0xFF00) uses the generic structure */
2828 /* set test more (0xFF01, internal) */
2830 struct i40e_acq_set_test_mode {
2832 #define I40E_AQ_TEST_PARTIAL 0
2833 #define I40E_AQ_TEST_FULL 1
2834 #define I40E_AQ_TEST_NVM 2
2837 #define I40E_AQ_TEST_OPEN 0
2838 #define I40E_AQ_TEST_CLOSE 1
2839 #define I40E_AQ_TEST_INC 2
2841 __le32 address_high;
2845 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2847 /* Debug Read Register command (0xFF03)
2848 * Debug Write Register command (0xFF04)
2850 struct i40e_aqc_debug_reg_read_write {
2857 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2859 /* Scatter/gather Reg Read (indirect 0xFF05)
2860 * Scatter/gather Reg Write (indirect 0xFF06)
2863 /* i40e_aq_desc is used for the command */
2864 struct i40e_aqc_debug_reg_sg_element_data {
2869 /* Debug Modify register (direct 0xFF07) */
2870 struct i40e_aqc_debug_modify_reg {
2877 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2879 /* dump internal data (0xFF08, indirect) */
2881 #define I40E_AQ_CLUSTER_ID_AUX 0
2882 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1
2883 #define I40E_AQ_CLUSTER_ID_TXSCHED 2
2884 #define I40E_AQ_CLUSTER_ID_HMC 3
2885 #define I40E_AQ_CLUSTER_ID_MAC0 4
2886 #define I40E_AQ_CLUSTER_ID_MAC1 5
2887 #define I40E_AQ_CLUSTER_ID_MAC2 6
2888 #define I40E_AQ_CLUSTER_ID_MAC3 7
2889 #define I40E_AQ_CLUSTER_ID_DCB 8
2890 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9
2891 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10
2892 #define I40E_AQ_CLUSTER_ID_ALTRAM 11
2894 struct i40e_aqc_debug_dump_internals {
2899 __le32 address_high;
2903 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2905 struct i40e_aqc_debug_modify_internals {
2907 u8 cluster_specific_params[7];
2908 __le32 address_high;
2912 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
2914 #endif /* _I40E_ADMINQ_CMD_H_ */