1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32 ***************************************************************************/
34 #ifndef _I40E_ADMINQ_CMD_H_
35 #define _I40E_ADMINQ_CMD_H_
37 /* This header file defines the i40e Admin Queue commands and is shared between
38 * i40e Firmware and Software.
40 * This file needs to comply with the Linux Kernel coding style.
43 #define I40E_FW_API_VERSION_MAJOR 0x0001
44 #define I40E_FW_API_VERSION_MINOR_X722 0x0005
45 #define I40E_FW_API_VERSION_MINOR_X710 0x0007
47 #define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \
48 I40E_FW_API_VERSION_MINOR_X710 : \
49 I40E_FW_API_VERSION_MINOR_X722)
51 /* API version 1.7 implements additional link and PHY-specific APIs */
52 #define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007
78 /* Flags sub-structure
79 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
80 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
83 /* command flags and offsets*/
84 #define I40E_AQ_FLAG_DD_SHIFT 0
85 #define I40E_AQ_FLAG_CMP_SHIFT 1
86 #define I40E_AQ_FLAG_ERR_SHIFT 2
87 #define I40E_AQ_FLAG_VFE_SHIFT 3
88 #define I40E_AQ_FLAG_LB_SHIFT 9
89 #define I40E_AQ_FLAG_RD_SHIFT 10
90 #define I40E_AQ_FLAG_VFC_SHIFT 11
91 #define I40E_AQ_FLAG_BUF_SHIFT 12
92 #define I40E_AQ_FLAG_SI_SHIFT 13
93 #define I40E_AQ_FLAG_EI_SHIFT 14
94 #define I40E_AQ_FLAG_FE_SHIFT 15
96 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
97 #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */
98 #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
99 #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */
100 #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
101 #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
102 #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */
103 #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
104 #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
105 #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */
106 #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */
109 enum i40e_admin_queue_err {
110 I40E_AQ_RC_OK = 0, /* success */
111 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */
112 I40E_AQ_RC_ENOENT = 2, /* No such element */
113 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */
114 I40E_AQ_RC_EINTR = 4, /* operation interrupted */
115 I40E_AQ_RC_EIO = 5, /* I/O error */
116 I40E_AQ_RC_ENXIO = 6, /* No such resource */
117 I40E_AQ_RC_E2BIG = 7, /* Arg too long */
118 I40E_AQ_RC_EAGAIN = 8, /* Try again */
119 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */
120 I40E_AQ_RC_EACCES = 10, /* Permission denied */
121 I40E_AQ_RC_EFAULT = 11, /* Bad address */
122 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */
123 I40E_AQ_RC_EEXIST = 13, /* object already exists */
124 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */
125 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */
126 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
127 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */
128 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */
129 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
130 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
131 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
132 I40E_AQ_RC_EFBIG = 22, /* File too large */
135 /* Admin Queue command opcodes */
136 enum i40e_admin_queue_opc {
138 i40e_aqc_opc_get_version = 0x0001,
139 i40e_aqc_opc_driver_version = 0x0002,
140 i40e_aqc_opc_queue_shutdown = 0x0003,
141 i40e_aqc_opc_set_pf_context = 0x0004,
143 /* resource ownership */
144 i40e_aqc_opc_request_resource = 0x0008,
145 i40e_aqc_opc_release_resource = 0x0009,
147 i40e_aqc_opc_list_func_capabilities = 0x000A,
148 i40e_aqc_opc_list_dev_capabilities = 0x000B,
151 i40e_aqc_opc_set_proxy_config = 0x0104,
152 i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105,
155 i40e_aqc_opc_mac_address_read = 0x0107,
156 i40e_aqc_opc_mac_address_write = 0x0108,
159 i40e_aqc_opc_clear_pxe_mode = 0x0110,
162 i40e_aqc_opc_set_wol_filter = 0x0120,
163 i40e_aqc_opc_get_wake_reason = 0x0121,
164 i40e_aqc_opc_clear_all_wol_filters = 0x025E,
166 /* internal switch commands */
167 i40e_aqc_opc_get_switch_config = 0x0200,
168 i40e_aqc_opc_add_statistics = 0x0201,
169 i40e_aqc_opc_remove_statistics = 0x0202,
170 i40e_aqc_opc_set_port_parameters = 0x0203,
171 i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
172 i40e_aqc_opc_set_switch_config = 0x0205,
173 i40e_aqc_opc_rx_ctl_reg_read = 0x0206,
174 i40e_aqc_opc_rx_ctl_reg_write = 0x0207,
176 i40e_aqc_opc_add_vsi = 0x0210,
177 i40e_aqc_opc_update_vsi_parameters = 0x0211,
178 i40e_aqc_opc_get_vsi_parameters = 0x0212,
180 i40e_aqc_opc_add_pv = 0x0220,
181 i40e_aqc_opc_update_pv_parameters = 0x0221,
182 i40e_aqc_opc_get_pv_parameters = 0x0222,
184 i40e_aqc_opc_add_veb = 0x0230,
185 i40e_aqc_opc_update_veb_parameters = 0x0231,
186 i40e_aqc_opc_get_veb_parameters = 0x0232,
188 i40e_aqc_opc_delete_element = 0x0243,
190 i40e_aqc_opc_add_macvlan = 0x0250,
191 i40e_aqc_opc_remove_macvlan = 0x0251,
192 i40e_aqc_opc_add_vlan = 0x0252,
193 i40e_aqc_opc_remove_vlan = 0x0253,
194 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
195 i40e_aqc_opc_add_tag = 0x0255,
196 i40e_aqc_opc_remove_tag = 0x0256,
197 i40e_aqc_opc_add_multicast_etag = 0x0257,
198 i40e_aqc_opc_remove_multicast_etag = 0x0258,
199 i40e_aqc_opc_update_tag = 0x0259,
200 i40e_aqc_opc_add_control_packet_filter = 0x025A,
201 i40e_aqc_opc_remove_control_packet_filter = 0x025B,
202 i40e_aqc_opc_add_cloud_filters = 0x025C,
203 i40e_aqc_opc_remove_cloud_filters = 0x025D,
204 i40e_aqc_opc_clear_wol_switch_filters = 0x025E,
205 i40e_aqc_opc_replace_cloud_filters = 0x025F,
207 i40e_aqc_opc_add_mirror_rule = 0x0260,
208 i40e_aqc_opc_delete_mirror_rule = 0x0261,
210 /* Dynamic Device Personalization */
211 i40e_aqc_opc_write_personalization_profile = 0x0270,
212 i40e_aqc_opc_get_personalization_profile_list = 0x0271,
215 i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
216 i40e_aqc_opc_dcb_updated = 0x0302,
217 i40e_aqc_opc_set_dcb_parameters = 0x0303,
220 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
221 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
222 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
223 i40e_aqc_opc_query_vsi_bw_config = 0x0408,
224 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
225 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
227 i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
228 i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
229 i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
230 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
231 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
232 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
233 i40e_aqc_opc_query_port_ets_config = 0x0419,
234 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
235 i40e_aqc_opc_suspend_port_tx = 0x041B,
236 i40e_aqc_opc_resume_port_tx = 0x041C,
237 i40e_aqc_opc_configure_partition_bw = 0x041D,
239 i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
240 i40e_aqc_opc_set_hmc_resource_profile = 0x0501,
243 i40e_aqc_opc_get_phy_abilities = 0x0600,
244 i40e_aqc_opc_set_phy_config = 0x0601,
245 i40e_aqc_opc_set_mac_config = 0x0603,
246 i40e_aqc_opc_set_link_restart_an = 0x0605,
247 i40e_aqc_opc_get_link_status = 0x0607,
248 i40e_aqc_opc_set_phy_int_mask = 0x0613,
249 i40e_aqc_opc_get_local_advt_reg = 0x0614,
250 i40e_aqc_opc_set_local_advt_reg = 0x0615,
251 i40e_aqc_opc_get_partner_advt = 0x0616,
252 i40e_aqc_opc_set_lb_modes = 0x0618,
253 i40e_aqc_opc_get_phy_wol_caps = 0x0621,
254 i40e_aqc_opc_set_phy_debug = 0x0622,
255 i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
256 i40e_aqc_opc_run_phy_activity = 0x0626,
257 i40e_aqc_opc_set_phy_register = 0x0628,
258 i40e_aqc_opc_get_phy_register = 0x0629,
261 i40e_aqc_opc_nvm_read = 0x0701,
262 i40e_aqc_opc_nvm_erase = 0x0702,
263 i40e_aqc_opc_nvm_update = 0x0703,
264 i40e_aqc_opc_nvm_config_read = 0x0704,
265 i40e_aqc_opc_nvm_config_write = 0x0705,
266 i40e_aqc_opc_oem_post_update = 0x0720,
267 i40e_aqc_opc_thermal_sensor = 0x0721,
269 /* virtualization commands */
270 i40e_aqc_opc_send_msg_to_pf = 0x0801,
271 i40e_aqc_opc_send_msg_to_vf = 0x0802,
272 i40e_aqc_opc_send_msg_to_peer = 0x0803,
274 /* alternate structure */
275 i40e_aqc_opc_alternate_write = 0x0900,
276 i40e_aqc_opc_alternate_write_indirect = 0x0901,
277 i40e_aqc_opc_alternate_read = 0x0902,
278 i40e_aqc_opc_alternate_read_indirect = 0x0903,
279 i40e_aqc_opc_alternate_write_done = 0x0904,
280 i40e_aqc_opc_alternate_set_mode = 0x0905,
281 i40e_aqc_opc_alternate_clear_port = 0x0906,
284 i40e_aqc_opc_lldp_get_mib = 0x0A00,
285 i40e_aqc_opc_lldp_update_mib = 0x0A01,
286 i40e_aqc_opc_lldp_add_tlv = 0x0A02,
287 i40e_aqc_opc_lldp_update_tlv = 0x0A03,
288 i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
289 i40e_aqc_opc_lldp_stop = 0x0A05,
290 i40e_aqc_opc_lldp_start = 0x0A06,
291 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07,
292 i40e_aqc_opc_lldp_set_local_mib = 0x0A08,
293 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09,
295 /* Tunnel commands */
296 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
297 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
298 i40e_aqc_opc_set_rss_key = 0x0B02,
299 i40e_aqc_opc_set_rss_lut = 0x0B03,
300 i40e_aqc_opc_get_rss_key = 0x0B04,
301 i40e_aqc_opc_get_rss_lut = 0x0B05,
304 i40e_aqc_opc_event_lan_overflow = 0x1001,
307 i40e_aqc_opc_oem_parameter_change = 0xFE00,
308 i40e_aqc_opc_oem_device_status_change = 0xFE01,
309 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02,
310 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03,
313 i40e_aqc_opc_debug_read_reg = 0xFF03,
314 i40e_aqc_opc_debug_write_reg = 0xFF04,
315 i40e_aqc_opc_debug_modify_reg = 0xFF07,
316 i40e_aqc_opc_debug_dump_internals = 0xFF08,
319 /* command structures and indirect data structures */
321 /* Structure naming conventions:
322 * - no suffix for direct command descriptor structures
323 * - _data for indirect sent data
324 * - _resp for indirect return data (data which is both will use _data)
325 * - _completion for direct return data
326 * - _element_ for repeated elements (may also be _data or _resp)
328 * Command structures are expected to overlay the params.raw member of the basic
329 * descriptor, and as such cannot exceed 16 bytes in length.
332 /* This macro is used to generate a compilation error if a structure
333 * is not exactly the correct length. It gives a divide by zero error if the
334 * structure is not of the correct size, otherwise it creates an enum that is
337 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
338 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
340 /* This macro is used extensively to ensure that command structures are 16
341 * bytes in length as they have to map to the raw array of that size.
343 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
345 /* internal (0x00XX) commands */
347 /* Get version (direct 0x0001) */
348 struct i40e_aqc_get_version {
357 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
359 /* Send driver version (indirect 0x0002) */
360 struct i40e_aqc_driver_version {
364 u8 driver_subbuild_ver;
370 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
372 /* Queue Shutdown (direct 0x0003) */
373 struct i40e_aqc_queue_shutdown {
374 __le32 driver_unloading;
375 #define I40E_AQ_DRIVER_UNLOADING 0x1
379 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
381 /* Set PF context (0x0004, direct) */
382 struct i40e_aqc_set_pf_context {
387 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
389 /* Request resource ownership (direct 0x0008)
390 * Release resource ownership (direct 0x0009)
392 #define I40E_AQ_RESOURCE_NVM 1
393 #define I40E_AQ_RESOURCE_SDP 2
394 #define I40E_AQ_RESOURCE_ACCESS_READ 1
395 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2
396 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
397 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
399 struct i40e_aqc_request_resource {
403 __le32 resource_number;
407 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
409 /* Get function capabilities (indirect 0x000A)
410 * Get device capabilities (indirect 0x000B)
412 struct i40e_aqc_list_capabilites {
414 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1
422 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
424 struct i40e_aqc_list_capabilities_element_resp {
436 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
437 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002
438 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
439 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
440 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
441 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006
442 #define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008
443 #define I40E_AQ_CAP_ID_SRIOV 0x0012
444 #define I40E_AQ_CAP_ID_VF 0x0013
445 #define I40E_AQ_CAP_ID_VMDQ 0x0014
446 #define I40E_AQ_CAP_ID_8021QBG 0x0015
447 #define I40E_AQ_CAP_ID_8021QBR 0x0016
448 #define I40E_AQ_CAP_ID_VSI 0x0017
449 #define I40E_AQ_CAP_ID_DCB 0x0018
450 #define I40E_AQ_CAP_ID_FCOE 0x0021
451 #define I40E_AQ_CAP_ID_ISCSI 0x0022
452 #define I40E_AQ_CAP_ID_RSS 0x0040
453 #define I40E_AQ_CAP_ID_RXQ 0x0041
454 #define I40E_AQ_CAP_ID_TXQ 0x0042
455 #define I40E_AQ_CAP_ID_MSIX 0x0043
456 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044
457 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
458 #define I40E_AQ_CAP_ID_1588 0x0046
459 #define I40E_AQ_CAP_ID_IWARP 0x0051
460 #define I40E_AQ_CAP_ID_LED 0x0061
461 #define I40E_AQ_CAP_ID_SDP 0x0062
462 #define I40E_AQ_CAP_ID_MDIO 0x0063
463 #define I40E_AQ_CAP_ID_WSR_PROT 0x0064
464 #define I40E_AQ_CAP_ID_NVM_MGMT 0x0080
465 #define I40E_AQ_CAP_ID_FLEX10 0x00F1
466 #define I40E_AQ_CAP_ID_CEM 0x00F2
468 /* Set CPPM Configuration (direct 0x0103) */
469 struct i40e_aqc_cppm_configuration {
470 __le16 command_flags;
471 #define I40E_AQ_CPPM_EN_LTRC 0x0800
472 #define I40E_AQ_CPPM_EN_DMCTH 0x1000
473 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000
474 #define I40E_AQ_CPPM_EN_HPTC 0x4000
475 #define I40E_AQ_CPPM_EN_DMARC 0x8000
484 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
486 /* Set ARP Proxy command / response (indirect 0x0104) */
487 struct i40e_aqc_arp_proxy_data {
488 __le16 command_flags;
489 #define I40E_AQ_ARP_INIT_IPV4 0x0800
490 #define I40E_AQ_ARP_UNSUP_CTL 0x1000
491 #define I40E_AQ_ARP_ENA 0x2000
492 #define I40E_AQ_ARP_ADD_IPV4 0x4000
493 #define I40E_AQ_ARP_DEL_IPV4 0x8000
495 __le32 enabled_offloads;
496 #define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020
497 #define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800
503 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
505 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
506 struct i40e_aqc_ns_proxy_data {
507 __le16 table_idx_mac_addr_0;
508 __le16 table_idx_mac_addr_1;
509 __le16 table_idx_ipv6_0;
510 __le16 table_idx_ipv6_1;
512 #define I40E_AQ_NS_PROXY_ADD_0 0x0001
513 #define I40E_AQ_NS_PROXY_DEL_0 0x0002
514 #define I40E_AQ_NS_PROXY_ADD_1 0x0004
515 #define I40E_AQ_NS_PROXY_DEL_1 0x0008
516 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010
517 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020
518 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040
519 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080
520 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100
521 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200
522 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400
523 #define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800
524 #define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000
527 u8 local_mac_addr[6];
528 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
532 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
534 /* Manage LAA Command (0x0106) - obsolete */
535 struct i40e_aqc_mng_laa {
536 __le16 command_flags;
537 #define I40E_AQ_LAA_FLAG_WR 0x8000
544 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);
546 /* Manage MAC Address Read Command (indirect 0x0107) */
547 struct i40e_aqc_mac_address_read {
548 __le16 command_flags;
549 #define I40E_AQC_LAN_ADDR_VALID 0x10
550 #define I40E_AQC_SAN_ADDR_VALID 0x20
551 #define I40E_AQC_PORT_ADDR_VALID 0x40
552 #define I40E_AQC_WOL_ADDR_VALID 0x80
553 #define I40E_AQC_MC_MAG_EN_VALID 0x100
554 #define I40E_AQC_WOL_PRESERVE_STATUS 0x200
555 #define I40E_AQC_ADDR_VALID_MASK 0x3F0
561 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
563 struct i40e_aqc_mac_address_read_data {
570 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
572 /* Manage MAC Address Write Command (0x0108) */
573 struct i40e_aqc_mac_address_write {
574 __le16 command_flags;
575 #define I40E_AQC_MC_MAG_EN 0x0100
576 #define I40E_AQC_WOL_PRESERVE_ON_PFR 0x0200
577 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
578 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
579 #define I40E_AQC_WRITE_TYPE_PORT 0x8000
580 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
581 #define I40E_AQC_WRITE_TYPE_MASK 0xC000
588 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
590 /* PXE commands (0x011x) */
592 /* Clear PXE Command and response (direct 0x0110) */
593 struct i40e_aqc_clear_pxe {
598 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
600 /* Set WoL Filter (0x0120) */
602 struct i40e_aqc_set_wol_filter {
604 #define I40E_AQC_MAX_NUM_WOL_FILTERS 8
605 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15
606 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \
607 I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT)
609 #define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0
610 #define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \
611 I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT)
613 #define I40E_AQC_SET_WOL_FILTER 0x8000
614 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000
615 #define I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR 0x2000
616 #define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0
617 #define I40E_AQC_SET_WOL_FILTER_ACTION_SET 1
619 #define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000
620 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000
626 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter);
628 struct i40e_aqc_set_wol_filter_data {
633 I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data);
635 /* Get Wake Reason (0x0121) */
637 struct i40e_aqc_get_wake_reason_completion {
640 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0
641 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \
642 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT)
643 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8
644 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \
645 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT)
649 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion);
651 /* Switch configuration commands (0x02xx) */
653 /* Used by many indirect commands that only pass an seid and a buffer in the
656 struct i40e_aqc_switch_seid {
663 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
665 /* Get Switch Configuration command (indirect 0x0200)
666 * uses i40e_aqc_switch_seid for the descriptor
668 struct i40e_aqc_get_switch_config_header_resp {
674 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);
676 struct i40e_aqc_switch_config_element_resp {
678 #define I40E_AQ_SW_ELEM_TYPE_MAC 1
679 #define I40E_AQ_SW_ELEM_TYPE_PF 2
680 #define I40E_AQ_SW_ELEM_TYPE_VF 3
681 #define I40E_AQ_SW_ELEM_TYPE_EMP 4
682 #define I40E_AQ_SW_ELEM_TYPE_BMC 5
683 #define I40E_AQ_SW_ELEM_TYPE_PV 16
684 #define I40E_AQ_SW_ELEM_TYPE_VEB 17
685 #define I40E_AQ_SW_ELEM_TYPE_PA 18
686 #define I40E_AQ_SW_ELEM_TYPE_VSI 19
688 #define I40E_AQ_SW_ELEM_REV_1 1
691 __le16 downlink_seid;
694 #define I40E_AQ_CONN_TYPE_REGULAR 0x1
695 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2
696 #define I40E_AQ_CONN_TYPE_CASCADED 0x3
701 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
703 /* Get Switch Configuration (indirect 0x0200)
704 * an array of elements are returned in the response buffer
705 * the first in the array is the header, remainder are elements
707 struct i40e_aqc_get_switch_config_resp {
708 struct i40e_aqc_get_switch_config_header_resp header;
709 struct i40e_aqc_switch_config_element_resp element[1];
712 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
714 /* Add Statistics (direct 0x0201)
715 * Remove Statistics (direct 0x0202)
717 struct i40e_aqc_add_remove_statistics {
724 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
726 /* Set Port Parameters command (direct 0x0203) */
727 struct i40e_aqc_set_port_parameters {
728 __le16 command_flags;
729 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
730 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
731 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
732 __le16 bad_frame_vsi;
733 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0
734 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF
735 __le16 default_seid; /* reserved for command */
739 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
741 /* Get Switch Resource Allocation (indirect 0x0204) */
742 struct i40e_aqc_get_switch_resource_alloc {
743 u8 num_entries; /* reserved for command */
749 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
751 /* expect an array of these structs in the response buffer */
752 struct i40e_aqc_switch_resource_alloc_element_resp {
754 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0
755 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1
756 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2
757 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3
758 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4
759 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
760 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
761 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7
762 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
763 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
764 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
765 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
766 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
767 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
768 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
769 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
770 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
771 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
772 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
777 __le16 total_unalloced;
781 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
783 /* Set Switch Configuration (direct 0x0205) */
784 struct i40e_aqc_set_switch_config {
786 /* flags used for both fields below */
787 #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001
788 #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002
789 #define I40E_AQ_SET_SWITCH_CFG_HW_ATR_EVICT 0x0004
791 /* The ethertype in switch_tag is dropped on ingress and used
792 * internally by the switch. Set this to zero for the default
793 * of 0x88a8 (802.1ad). Should be zero for firmware API
794 * versions lower than 1.7.
797 /* The ethertypes in first_tag and second_tag are used to
798 * match the outer and inner VLAN tags (respectively) when HW
799 * double VLAN tagging is enabled via the set port parameters
800 * AQ command. Otherwise these are both ignored. Set them to
801 * zero for their defaults of 0x8100 (802.1Q). Should be zero
802 * for firmware API versions lower than 1.7.
809 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config);
811 /* Read Receive control registers (direct 0x0206)
812 * Write Receive control registers (direct 0x0207)
813 * used for accessing Rx control registers that can be
814 * slow and need special handling when under high Rx load
816 struct i40e_aqc_rx_ctl_reg_read_write {
823 I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write);
825 /* Add VSI (indirect 0x0210)
826 * this indirect command uses struct i40e_aqc_vsi_properties_data
827 * as the indirect buffer (128 bytes)
829 * Update VSI (indirect 0x211)
830 * uses the same data structure as Add VSI
832 * Get VSI (indirect 0x0212)
833 * uses the same completion and data structure as Add VSI
835 struct i40e_aqc_add_get_update_vsi {
838 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
839 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2
840 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3
845 #define I40E_AQ_VSI_TYPE_SHIFT 0x0
846 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
847 #define I40E_AQ_VSI_TYPE_VF 0x0
848 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1
849 #define I40E_AQ_VSI_TYPE_PF 0x2
850 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3
851 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4
856 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
858 struct i40e_aqc_add_get_update_vsi_completion {
867 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
869 struct i40e_aqc_vsi_properties_data {
870 /* first 96 byte are written by SW */
871 __le16 valid_sections;
872 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
873 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
874 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
875 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008
876 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
877 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
878 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
879 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
880 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
881 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
883 __le16 switch_id; /* 12bit id combined with flags below */
884 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
885 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
886 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
887 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
888 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
890 /* security section */
892 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
893 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
894 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
897 __le16 pvid; /* VLANS include priority bits */
900 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
901 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
902 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
903 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
904 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
905 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
906 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
907 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
908 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
909 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
910 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
911 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
912 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
913 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
914 u8 pvlan_reserved[3];
915 /* ingress egress up sections */
916 __le32 ingress_table; /* bitmap, 3 bits per up */
917 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
918 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
919 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
920 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3
921 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
922 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
923 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6
924 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
925 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
926 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9
927 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
928 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
929 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12
930 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
931 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
932 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15
933 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
934 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
935 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18
936 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
937 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
938 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21
939 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
940 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
941 __le32 egress_table; /* same defines as for ingress table */
942 /* cascaded PV section */
945 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
946 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
947 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
948 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
949 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
950 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02
951 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10
952 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
953 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
955 /* queue mapping section */
956 __le16 mapping_flags;
957 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
958 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
959 __le16 queue_mapping[16];
960 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0
961 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
962 __le16 tc_mapping[8];
963 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
964 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
965 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
966 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
967 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
968 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
969 /* queueing option section */
970 u8 queueing_opt_flags;
971 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04
972 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08
973 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
974 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
975 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00
976 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
977 u8 queueing_opt_reserved[3];
978 /* scheduler section */
981 /* outer up section */
982 __le32 outer_up_table; /* same structure and defines as ingress tbl */
984 /* last 32 bytes are written by FW */
986 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
987 __le16 stat_counter_idx;
989 u8 resp_reserved[12];
992 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
994 /* Add Port Virtualizer (direct 0x0220)
995 * also used for update PV (direct 0x0221) but only flags are used
996 * (IS_CTRL_PORT only works on add PV)
998 struct i40e_aqc_add_update_pv {
999 __le16 command_flags;
1000 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1
1001 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
1002 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
1003 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8
1005 __le16 connected_seid;
1009 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
1011 struct i40e_aqc_add_update_pv_completion {
1012 /* reserved for update; for add also encodes error if rc == ENOSPC */
1014 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1
1015 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2
1016 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
1017 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
1021 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
1023 /* Get PV Params (direct 0x0222)
1024 * uses i40e_aqc_switch_seid for the descriptor
1027 struct i40e_aqc_get_pv_params_completion {
1029 __le16 default_stag;
1030 __le16 pv_flags; /* same flags as add_pv */
1031 #define I40E_AQC_GET_PV_PV_TYPE 0x1
1032 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
1033 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
1035 __le16 default_port_seid;
1038 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
1040 /* Add VEB (direct 0x0230) */
1041 struct i40e_aqc_add_veb {
1043 __le16 downlink_seid;
1045 #define I40E_AQC_ADD_VEB_FLOATING 0x1
1046 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
1047 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
1048 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
1049 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
1050 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
1051 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */
1052 #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10
1057 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
1059 struct i40e_aqc_add_veb_completion {
1062 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
1064 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1
1065 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
1066 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
1067 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
1068 __le16 statistic_index;
1073 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
1075 /* Get VEB Parameters (direct 0x0232)
1076 * uses i40e_aqc_switch_seid for the descriptor
1078 struct i40e_aqc_get_veb_parameters_completion {
1081 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
1082 __le16 statistic_index;
1088 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
1090 /* Delete Element (direct 0x0243)
1091 * uses the generic i40e_aqc_switch_seid
1094 /* Add MAC-VLAN (indirect 0x0250) */
1096 /* used for the command for most vlan commands */
1097 struct i40e_aqc_macvlan {
1098 __le16 num_addresses;
1100 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
1101 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
1102 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1103 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
1108 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
1110 /* indirect data for command and response */
1111 struct i40e_aqc_add_macvlan_element_data {
1115 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
1116 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
1117 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
1118 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
1119 #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010
1120 __le16 queue_number;
1121 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
1122 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
1123 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1124 /* response section */
1126 #define I40E_AQC_MM_PERFECT_MATCH 0x01
1127 #define I40E_AQC_MM_HASH_MATCH 0x02
1128 #define I40E_AQC_MM_ERR_NO_RES 0xFF
1132 struct i40e_aqc_add_remove_macvlan_completion {
1133 __le16 perfect_mac_used;
1134 __le16 perfect_mac_free;
1135 __le16 unicast_hash_free;
1136 __le16 multicast_hash_free;
1141 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
1143 /* Remove MAC-VLAN (indirect 0x0251)
1144 * uses i40e_aqc_macvlan for the descriptor
1145 * data points to an array of num_addresses of elements
1148 struct i40e_aqc_remove_macvlan_element_data {
1152 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
1153 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02
1154 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
1155 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10
1159 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0
1160 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF
1161 u8 reply_reserved[3];
1164 /* Add VLAN (indirect 0x0252)
1165 * Remove VLAN (indirect 0x0253)
1166 * use the generic i40e_aqc_macvlan for the command
1168 struct i40e_aqc_add_remove_vlan_element_data {
1171 /* flags for add VLAN */
1172 #define I40E_AQC_ADD_VLAN_LOCAL 0x1
1173 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1
1174 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1175 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
1176 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
1177 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
1178 #define I40E_AQC_VLAN_PTYPE_SHIFT 3
1179 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1180 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
1181 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
1182 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
1183 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
1184 /* flags for remove VLAN */
1185 #define I40E_AQC_REMOVE_VLAN_ALL 0x1
1188 /* flags for add VLAN */
1189 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0
1190 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
1191 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
1192 /* flags for remove VLAN */
1193 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0
1194 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF
1198 struct i40e_aqc_add_remove_vlan_completion {
1206 /* Set VSI Promiscuous Modes (direct 0x0254) */
1207 struct i40e_aqc_set_vsi_promiscuous_modes {
1208 __le16 promiscuous_flags;
1210 /* flags used for both fields above */
1211 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
1212 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1213 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1214 #define I40E_AQC_SET_VSI_DEFAULT 0x08
1215 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
1216 #define I40E_AQC_SET_VSI_PROMISC_TX 0x8000
1218 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
1220 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF
1221 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
1225 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1227 /* Add S/E-tag command (direct 0x0255)
1228 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1230 struct i40e_aqc_add_tag {
1232 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
1234 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
1235 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1236 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1238 __le16 queue_number;
1242 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1244 struct i40e_aqc_add_remove_tag_completion {
1250 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1252 /* Remove S/E-tag command (direct 0x0256)
1253 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1255 struct i40e_aqc_remove_tag {
1257 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
1258 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1259 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1264 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);
1266 /* Add multicast E-Tag (direct 0x0257)
1267 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1268 * and no external data
1270 struct i40e_aqc_add_remove_mcast_etag {
1273 u8 num_unicast_etags;
1275 __le32 addr_high; /* address of array of 2-byte s-tags */
1279 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1281 struct i40e_aqc_add_remove_mcast_etag_completion {
1283 __le16 mcast_etags_used;
1284 __le16 mcast_etags_free;
1290 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1292 /* Update S/E-Tag (direct 0x0259) */
1293 struct i40e_aqc_update_tag {
1295 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
1296 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1297 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1303 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1305 struct i40e_aqc_update_tag_completion {
1311 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1313 /* Add Control Packet filter (direct 0x025A)
1314 * Remove Control Packet filter (direct 0x025B)
1315 * uses the i40e_aqc_add_oveb_cloud,
1316 * and the generic direct completion structure
1318 struct i40e_aqc_add_remove_control_packet_filter {
1322 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1323 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1324 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
1325 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1326 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
1328 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
1329 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
1330 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1335 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1337 struct i40e_aqc_add_remove_control_packet_filter_completion {
1338 __le16 mac_etype_used;
1340 __le16 mac_etype_free;
1345 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1347 /* Add Cloud filters (indirect 0x025C)
1348 * Remove Cloud filters (indirect 0x025D)
1349 * uses the i40e_aqc_add_remove_cloud_filters,
1350 * and the generic indirect completion structure
1352 struct i40e_aqc_add_remove_cloud_filters {
1356 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
1357 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
1358 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1360 #define I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER 1
1366 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1368 struct i40e_aqc_add_remove_cloud_filters_element_data {
1382 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
1383 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
1384 I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1385 /* 0x0000 reserved */
1386 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001
1387 /* 0x0002 reserved */
1388 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1389 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
1390 /* 0x0005 reserved */
1391 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
1392 /* 0x0007 reserved */
1393 /* 0x0008 reserved */
1394 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1395 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1396 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1397 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1398 /* 0x0010 to 0x0017 is for custom filters */
1400 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
1401 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6
1402 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0
1403 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1404 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1406 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1407 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1408 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0
1409 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
1410 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2
1411 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3
1412 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4
1413 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5
1415 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000
1416 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000
1417 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000
1421 __le16 queue_number;
1422 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
1423 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \
1424 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1426 /* response section */
1427 u8 allocation_result;
1428 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
1429 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
1430 u8 response_reserved[7];
1433 /* i40e_aqc_add_rm_cloud_filt_elem_ext is used when
1434 * I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER flag is set. refer to
1437 struct i40e_aqc_add_rm_cloud_filt_elem_ext {
1438 struct i40e_aqc_add_remove_cloud_filters_element_data element;
1439 u16 general_fields[32];
1440 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0 0
1441 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1 1
1442 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2 2
1443 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0 3
1444 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1 4
1445 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2 5
1446 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0 6
1447 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1 7
1448 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2 8
1449 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0 9
1450 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1 10
1451 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2 11
1452 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0 12
1453 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1 13
1454 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2 14
1455 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0 15
1456 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1 16
1457 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2 17
1458 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3 18
1459 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4 19
1460 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5 20
1461 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6 21
1462 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7 22
1463 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0 23
1464 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1 24
1465 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2 25
1466 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3 26
1467 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4 27
1468 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5 28
1469 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6 29
1470 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7 30
1473 struct i40e_aqc_remove_cloud_filters_completion {
1474 __le16 perfect_ovlan_used;
1475 __le16 perfect_ovlan_free;
1482 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1484 /* Replace filter Command 0x025F
1485 * uses the i40e_aqc_replace_cloud_filters,
1486 * and the generic indirect completion structure
1488 struct i40e_filter_data {
1493 struct i40e_aqc_replace_cloud_filters_cmd {
1495 #define I40E_AQC_REPLACE_L1_FILTER 0x0
1496 #define I40E_AQC_REPLACE_CLOUD_FILTER 0x1
1497 #define I40E_AQC_GET_CLOUD_FILTERS 0x2
1498 #define I40E_AQC_MIRROR_CLOUD_FILTER 0x4
1499 #define I40E_AQC_HIGH_PRIORITY_CLOUD_FILTER 0x8
1508 struct i40e_aqc_replace_cloud_filters_cmd_buf {
1510 /* Filter type INPUT codes*/
1511 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_ENTRIES_MAX 3
1512 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED (1 << 7UL)
1514 /* Field Vector offsets */
1515 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_MAC_DA 0
1516 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_ETH 6
1517 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG 7
1518 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN 8
1519 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_OVLAN 9
1520 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN 10
1521 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY 11
1522 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC 12
1524 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IP_DA 14
1526 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_OIP_DA 15
1528 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN 37
1529 struct i40e_filter_data filters[8];
1532 /* Add Mirror Rule (indirect or direct 0x0260)
1533 * Delete Mirror Rule (indirect or direct 0x0261)
1534 * note: some rule types (4,5) do not use an external buffer.
1535 * take care to set the flags correctly.
1537 struct i40e_aqc_add_delete_mirror_rule {
1540 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1541 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1542 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1543 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1544 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
1545 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1546 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1547 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
1549 __le16 destination; /* VSI for add, rule id for delete */
1550 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
1554 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1556 struct i40e_aqc_add_delete_mirror_rule_completion {
1558 __le16 rule_id; /* only used on add */
1559 __le16 mirror_rules_used;
1560 __le16 mirror_rules_free;
1565 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1567 /* Dynamic Device Personalization */
1568 struct i40e_aqc_write_personalization_profile {
1571 __le32 profile_track_id;
1576 I40E_CHECK_CMD_LENGTH(i40e_aqc_write_personalization_profile);
1578 struct i40e_aqc_write_ddp_resp {
1579 __le32 error_offset;
1585 struct i40e_aqc_get_applied_profiles {
1587 #define I40E_AQC_GET_DDP_GET_CONF 0x1
1588 #define I40E_AQC_GET_DDP_GET_RDPU_CONF 0x2
1595 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_applied_profiles);
1599 /* PFC Ignore (direct 0x0301)
1600 * the command and response use the same descriptor structure
1602 struct i40e_aqc_pfc_ignore {
1604 u8 command_flags; /* unused on response */
1605 #define I40E_AQC_PFC_IGNORE_SET 0x80
1606 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0
1610 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1612 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1613 * with no parameters
1616 /* TX scheduler 0x04xx */
1618 /* Almost all the indirect commands use
1619 * this generic struct to pass the SEID in param0
1621 struct i40e_aqc_tx_sched_ind {
1628 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1630 /* Several commands respond with a set of queue set handles */
1631 struct i40e_aqc_qs_handles_resp {
1632 __le16 qs_handles[8];
1635 /* Configure VSI BW limits (direct 0x0400) */
1636 struct i40e_aqc_configure_vsi_bw_limit {
1641 u8 max_credit; /* 0-3, limit = 2^max */
1645 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1647 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1648 * responds with i40e_aqc_qs_handles_resp
1650 struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1653 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
1655 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1656 __le16 tc_bw_max[2];
1660 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
1662 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1663 * responds with i40e_aqc_qs_handles_resp
1665 struct i40e_aqc_configure_vsi_tc_bw_data {
1668 u8 tc_bw_credits[8];
1670 __le16 qs_handles[8];
1673 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
1675 /* Query vsi bw configuration (indirect 0x0408) */
1676 struct i40e_aqc_query_vsi_bw_config_resp {
1678 u8 tc_suspended_bits;
1680 __le16 qs_handles[8];
1682 __le16 port_bw_limit;
1684 u8 max_bw; /* 0-3, limit = 2^max */
1688 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
1690 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1691 struct i40e_aqc_query_vsi_ets_sla_config_resp {
1694 u8 share_credits[8];
1697 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1698 __le16 tc_bw_max[2];
1701 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
1703 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1704 struct i40e_aqc_configure_switching_comp_bw_limit {
1709 u8 max_bw; /* 0-3, limit = 2^max */
1713 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1715 /* Enable Physical Port ETS (indirect 0x0413)
1716 * Modify Physical Port ETS (indirect 0x0414)
1717 * Disable Physical Port ETS (indirect 0x0415)
1719 struct i40e_aqc_configure_switching_comp_ets_data {
1723 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1
1724 u8 tc_strict_priority_flags;
1726 u8 tc_bw_share_credits[8];
1730 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
1732 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1733 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1736 __le16 tc_bw_credit[8];
1738 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1739 __le16 tc_bw_max[2];
1743 I40E_CHECK_STRUCT_LEN(0x40,
1744 i40e_aqc_configure_switching_comp_ets_bw_limit_data);
1746 /* Configure Switching Component Bandwidth Allocation per Tc
1749 struct i40e_aqc_configure_switching_comp_bw_config_data {
1752 u8 absolute_credits; /* bool */
1753 u8 tc_bw_share_credits[8];
1757 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
1759 /* Query Switching Component Configuration (indirect 0x0418) */
1760 struct i40e_aqc_query_switching_comp_ets_config_resp {
1763 __le16 port_bw_limit;
1765 u8 tc_bw_max; /* 0-3, limit = 2^max */
1769 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
1771 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1772 struct i40e_aqc_query_port_ets_config_resp {
1776 u8 tc_strict_priority_bits;
1778 u8 tc_bw_share_credits[8];
1779 __le16 tc_bw_limits[8];
1781 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1782 __le16 tc_bw_max[2];
1786 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
1788 /* Query Switching Component Bandwidth Allocation per Traffic Type
1791 struct i40e_aqc_query_switching_comp_bw_config_resp {
1794 u8 absolute_credits_enable; /* bool */
1795 u8 tc_bw_share_credits[8];
1796 __le16 tc_bw_limits[8];
1798 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1799 __le16 tc_bw_max[2];
1802 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
1804 /* Suspend/resume port TX traffic
1805 * (direct 0x041B and 0x041C) uses the generic SEID struct
1808 /* Configure partition BW
1811 struct i40e_aqc_configure_partition_bw_data {
1812 __le16 pf_valid_bits;
1813 u8 min_bw[16]; /* guaranteed bandwidth */
1814 u8 max_bw[16]; /* bandwidth limit */
1817 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
1819 /* Get and set the active HMC resource profile and status.
1820 * (direct 0x0500) and (direct 0x0501)
1822 struct i40e_aq_get_set_hmc_resource_profile {
1828 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1830 enum i40e_aq_hmc_profile {
1831 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
1832 I40E_HMC_PROFILE_DEFAULT = 1,
1833 I40E_HMC_PROFILE_FAVOR_VF = 2,
1834 I40E_HMC_PROFILE_EQUAL = 3,
1837 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1839 /* set in param0 for get phy abilities to report qualified modules */
1840 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1841 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1843 enum i40e_aq_phy_type {
1844 I40E_PHY_TYPE_SGMII = 0x0,
1845 I40E_PHY_TYPE_1000BASE_KX = 0x1,
1846 I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
1847 I40E_PHY_TYPE_10GBASE_KR = 0x3,
1848 I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
1849 I40E_PHY_TYPE_XAUI = 0x5,
1850 I40E_PHY_TYPE_XFI = 0x6,
1851 I40E_PHY_TYPE_SFI = 0x7,
1852 I40E_PHY_TYPE_XLAUI = 0x8,
1853 I40E_PHY_TYPE_XLPPI = 0x9,
1854 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1855 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
1856 I40E_PHY_TYPE_10GBASE_AOC = 0xC,
1857 I40E_PHY_TYPE_40GBASE_AOC = 0xD,
1858 I40E_PHY_TYPE_UNRECOGNIZED = 0xE,
1859 I40E_PHY_TYPE_UNSUPPORTED = 0xF,
1860 I40E_PHY_TYPE_100BASE_TX = 0x11,
1861 I40E_PHY_TYPE_1000BASE_T = 0x12,
1862 I40E_PHY_TYPE_10GBASE_T = 0x13,
1863 I40E_PHY_TYPE_10GBASE_SR = 0x14,
1864 I40E_PHY_TYPE_10GBASE_LR = 0x15,
1865 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1866 I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
1867 I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
1868 I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
1869 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
1870 I40E_PHY_TYPE_1000BASE_SX = 0x1B,
1871 I40E_PHY_TYPE_1000BASE_LX = 0x1C,
1872 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
1873 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
1874 I40E_PHY_TYPE_25GBASE_KR = 0x1F,
1875 I40E_PHY_TYPE_25GBASE_CR = 0x20,
1876 I40E_PHY_TYPE_25GBASE_SR = 0x21,
1877 I40E_PHY_TYPE_25GBASE_LR = 0x22,
1878 I40E_PHY_TYPE_25GBASE_AOC = 0x23,
1879 I40E_PHY_TYPE_25GBASE_ACC = 0x24,
1881 I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD,
1882 I40E_PHY_TYPE_EMPTY = 0xFE,
1883 I40E_PHY_TYPE_DEFAULT = 0xFF,
1886 #define I40E_LINK_SPEED_100MB_SHIFT 0x1
1887 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1888 #define I40E_LINK_SPEED_10GB_SHIFT 0x3
1889 #define I40E_LINK_SPEED_40GB_SHIFT 0x4
1890 #define I40E_LINK_SPEED_20GB_SHIFT 0x5
1891 #define I40E_LINK_SPEED_25GB_SHIFT 0x6
1893 enum i40e_aq_link_speed {
1894 I40E_LINK_SPEED_UNKNOWN = 0,
1895 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT),
1896 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT),
1897 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT),
1898 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT),
1899 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT),
1900 I40E_LINK_SPEED_25GB = (1 << I40E_LINK_SPEED_25GB_SHIFT),
1903 struct i40e_aqc_module_desc {
1911 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
1913 struct i40e_aq_get_phy_abilities_resp {
1914 __le32 phy_type; /* bitmap using the above enum for offsets */
1915 u8 link_speed; /* bitmap using the above enum bit patterns */
1917 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
1918 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
1919 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04
1920 #define I40E_AQ_PHY_LINK_ENABLED 0x08
1921 #define I40E_AQ_PHY_AN_ENABLED 0x10
1922 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20
1923 #define I40E_AQ_PHY_FEC_ABILITY_KR 0x40
1924 #define I40E_AQ_PHY_FEC_ABILITY_RS 0x80
1925 __le16 eee_capability;
1926 #define I40E_AQ_EEE_100BASE_TX 0x0002
1927 #define I40E_AQ_EEE_1000BASE_T 0x0004
1928 #define I40E_AQ_EEE_10GBASE_T 0x0008
1929 #define I40E_AQ_EEE_1000BASE_KX 0x0010
1930 #define I40E_AQ_EEE_10GBASE_KX4 0x0020
1931 #define I40E_AQ_EEE_10GBASE_KR 0x0040
1934 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
1936 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0x01
1937 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0x02
1938 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04
1939 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
1940 #define I40E_AQ_PHY_TYPE_EXT_25G_AOC 0x10
1941 #define I40E_AQ_PHY_TYPE_EXT_25G_ACC 0x20
1942 u8 fec_cfg_curr_mod_ext_info;
1943 #define I40E_AQ_ENABLE_FEC_KR 0x01
1944 #define I40E_AQ_ENABLE_FEC_RS 0x02
1945 #define I40E_AQ_REQUEST_FEC_KR 0x04
1946 #define I40E_AQ_REQUEST_FEC_RS 0x08
1947 #define I40E_AQ_ENABLE_FEC_AUTO 0x10
1949 #define I40E_AQ_MODULE_TYPE_EXT_MASK 0xE0
1950 #define I40E_AQ_MODULE_TYPE_EXT_SHIFT 5
1955 u8 qualified_module_count;
1956 #define I40E_AQ_PHY_MAX_QMS 16
1957 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS];
1960 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
1962 /* Set PHY Config (direct 0x0601) */
1963 struct i40e_aq_set_phy_config { /* same bits as above in all */
1967 /* bits 0-2 use the values from get_phy_abilities_resp */
1968 #define I40E_AQ_PHY_ENABLE_LINK 0x08
1969 #define I40E_AQ_PHY_ENABLE_AN 0x10
1970 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
1971 __le16 eee_capability;
1976 #define I40E_AQ_SET_FEC_ABILITY_KR BIT(0)
1977 #define I40E_AQ_SET_FEC_ABILITY_RS BIT(1)
1978 #define I40E_AQ_SET_FEC_REQUEST_KR BIT(2)
1979 #define I40E_AQ_SET_FEC_REQUEST_RS BIT(3)
1980 #define I40E_AQ_SET_FEC_AUTO BIT(4)
1981 #define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0
1982 #define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT)
1986 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
1988 /* Set MAC Config command data structure (direct 0x0603) */
1989 struct i40e_aq_set_mac_config {
1990 __le16 max_frame_size;
1992 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
1993 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
1994 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
1995 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
1996 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
1997 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
1998 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
1999 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
2000 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
2001 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
2002 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
2003 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
2004 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
2005 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
2006 u8 tx_timer_priority; /* bitmap */
2007 __le16 tx_timer_value;
2008 __le16 fc_refresh_threshold;
2012 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
2014 /* Restart Auto-Negotiation (direct 0x605) */
2015 struct i40e_aqc_set_link_restart_an {
2017 #define I40E_AQ_PHY_RESTART_AN 0x02
2018 #define I40E_AQ_PHY_LINK_ENABLE 0x04
2022 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
2024 /* Get Link Status cmd & response data structure (direct 0x0607) */
2025 struct i40e_aqc_get_link_status {
2026 __le16 command_flags; /* only field set on command */
2027 #define I40E_AQ_LSE_MASK 0x3
2028 #define I40E_AQ_LSE_NOP 0x0
2029 #define I40E_AQ_LSE_DISABLE 0x2
2030 #define I40E_AQ_LSE_ENABLE 0x3
2031 /* only response uses this flag */
2032 #define I40E_AQ_LSE_IS_ENABLED 0x1
2033 u8 phy_type; /* i40e_aq_phy_type */
2034 u8 link_speed; /* i40e_aq_link_speed */
2036 #define I40E_AQ_LINK_UP 0x01 /* obsolete */
2037 #define I40E_AQ_LINK_UP_FUNCTION 0x01
2038 #define I40E_AQ_LINK_FAULT 0x02
2039 #define I40E_AQ_LINK_FAULT_TX 0x04
2040 #define I40E_AQ_LINK_FAULT_RX 0x08
2041 #define I40E_AQ_LINK_FAULT_REMOTE 0x10
2042 #define I40E_AQ_LINK_UP_PORT 0x20
2043 #define I40E_AQ_MEDIA_AVAILABLE 0x40
2044 #define I40E_AQ_SIGNAL_DETECT 0x80
2046 #define I40E_AQ_AN_COMPLETED 0x01
2047 #define I40E_AQ_LP_AN_ABILITY 0x02
2048 #define I40E_AQ_PD_FAULT 0x04
2049 #define I40E_AQ_FEC_EN 0x08
2050 #define I40E_AQ_PHY_LOW_POWER 0x10
2051 #define I40E_AQ_LINK_PAUSE_TX 0x20
2052 #define I40E_AQ_LINK_PAUSE_RX 0x40
2053 #define I40E_AQ_QUALIFIED_MODULE 0x80
2055 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01
2056 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02
2057 #define I40E_AQ_LINK_TX_SHIFT 0x02
2058 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT)
2059 #define I40E_AQ_LINK_TX_ACTIVE 0x00
2060 #define I40E_AQ_LINK_TX_DRAINED 0x01
2061 #define I40E_AQ_LINK_TX_FLUSHED 0x03
2062 #define I40E_AQ_LINK_FORCED_40G 0x10
2063 /* 25G Error Codes */
2064 #define I40E_AQ_25G_NO_ERR 0X00
2065 #define I40E_AQ_25G_NOT_PRESENT 0X01
2066 #define I40E_AQ_25G_NVM_CRC_ERR 0X02
2067 #define I40E_AQ_25G_SBUS_UCODE_ERR 0X03
2068 #define I40E_AQ_25G_SERDES_UCODE_ERR 0X04
2069 #define I40E_AQ_25G_NIMB_UCODE_ERR 0X05
2070 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
2071 /* Since firmware API 1.7 loopback field keeps power class info as well */
2072 #define I40E_AQ_LOOPBACK_MASK 0x07
2073 #define I40E_AQ_PWR_CLASS_SHIFT_LB 6
2074 #define I40E_AQ_PWR_CLASS_MASK_LB (0x03 << I40E_AQ_PWR_CLASS_SHIFT_LB)
2075 __le16 max_frame_size;
2077 #define I40E_AQ_CONFIG_FEC_KR_ENA 0x01
2078 #define I40E_AQ_CONFIG_FEC_RS_ENA 0x02
2079 #define I40E_AQ_CONFIG_CRC_ENA 0x04
2080 #define I40E_AQ_CONFIG_PACING_MASK 0x78
2084 #define I40E_AQ_LINK_POWER_CLASS_1 0x00
2085 #define I40E_AQ_LINK_POWER_CLASS_2 0x01
2086 #define I40E_AQ_LINK_POWER_CLASS_3 0x02
2087 #define I40E_AQ_LINK_POWER_CLASS_4 0x03
2088 #define I40E_AQ_PWR_CLASS_MASK 0x03
2098 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
2100 /* Set event mask command (direct 0x613) */
2101 struct i40e_aqc_set_phy_int_mask {
2104 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
2105 #define I40E_AQ_EVENT_MEDIA_NA 0x0004
2106 #define I40E_AQ_EVENT_LINK_FAULT 0x0008
2107 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010
2108 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
2109 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040
2110 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080
2111 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
2112 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
2116 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
2118 /* Get Local AN advt register (direct 0x0614)
2119 * Set Local AN advt register (direct 0x0615)
2120 * Get Link Partner AN advt register (direct 0x0616)
2122 struct i40e_aqc_an_advt_reg {
2123 __le32 local_an_reg0;
2124 __le16 local_an_reg1;
2128 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
2130 /* Set Loopback mode (0x0618) */
2131 struct i40e_aqc_set_lb_mode {
2133 #define I40E_AQ_LB_NONE 0
2134 #define I40E_AQ_LB_MAC 1
2135 #define I40E_AQ_LB_SERDES 2
2136 #define I40E_AQ_LB_PHY_INT 3
2137 #define I40E_AQ_LB_PHY_EXT 4
2138 #define I40E_AQ_LB_CPVL_PCS 5
2139 #define I40E_AQ_LB_CPVL_EXT 6
2140 #define I40E_AQ_LB_PHY_LOCAL 0x01
2141 #define I40E_AQ_LB_PHY_REMOTE 0x02
2142 #define I40E_AQ_LB_MAC_LOCAL 0x04
2144 #define I40E_AQ_LB_LOCAL 0
2145 #define I40E_AQ_LB_FAR 0x01
2147 #define I40E_AQ_LB_SPEED_NONE 0
2148 #define I40E_AQ_LB_SPEED_1G 1
2149 #define I40E_AQ_LB_SPEED_10G 2
2150 #define I40E_AQ_LB_SPEED_40G 3
2151 #define I40E_AQ_LB_SPEED_20G 4
2156 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
2158 /* Set PHY Debug command (0x0622) */
2159 struct i40e_aqc_set_phy_debug {
2161 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
2162 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
2163 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
2164 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
2165 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
2166 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
2167 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
2168 /* Disable link manageability on a single port */
2169 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
2170 /* Disable link manageability on all ports needs both bits 4 and 5 */
2171 #define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20
2175 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
2177 enum i40e_aq_phy_reg_type {
2178 I40E_AQC_PHY_REG_INTERNAL = 0x1,
2179 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
2180 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
2183 /* Run PHY Activity (0x0626) */
2184 struct i40e_aqc_run_phy_activity {
2193 I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity);
2195 /* Set PHY Register command (0x0628) */
2196 /* Get PHY Register command (0x0629) */
2197 struct i40e_aqc_phy_register_access {
2199 #define I40E_AQ_PHY_REG_ACCESS_INTERNAL 0
2200 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL 1
2201 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE 2
2209 I40E_CHECK_CMD_LENGTH(i40e_aqc_phy_register_access);
2211 /* NVM Read command (indirect 0x0701)
2212 * NVM Erase commands (direct 0x0702)
2213 * NVM Update commands (indirect 0x0703)
2215 struct i40e_aqc_nvm_update {
2217 #define I40E_AQ_NVM_LAST_CMD 0x01
2218 #define I40E_AQ_NVM_FLASH_ONLY 0x80
2219 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT 1
2220 #define I40E_AQ_NVM_PRESERVATION_FLAGS_MASK 0x03
2221 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED 0x03
2222 #define I40E_AQ_NVM_PRESERVATION_FLAGS_ALL 0x01
2230 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
2232 /* NVM Config Read (indirect 0x0704) */
2233 struct i40e_aqc_nvm_config_read {
2235 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
2236 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0
2237 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1
2238 __le16 element_count;
2239 __le16 element_id; /* Feature/field ID */
2240 __le16 element_id_msw; /* MSWord of field ID */
2241 __le32 address_high;
2245 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
2247 /* NVM Config Write (indirect 0x0705) */
2248 struct i40e_aqc_nvm_config_write {
2250 __le16 element_count;
2252 __le32 address_high;
2256 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
2258 /* Used for 0x0704 as well as for 0x0705 commands */
2259 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1
2260 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \
2261 (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
2262 #define I40E_AQ_ANVM_FEATURE 0
2263 #define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT)
2264 struct i40e_aqc_nvm_config_data_feature {
2266 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01
2267 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08
2268 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10
2269 __le16 feature_options;
2270 __le16 feature_selection;
2273 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
2275 struct i40e_aqc_nvm_config_data_immediate_field {
2278 __le16 field_options;
2282 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
2284 /* OEM Post Update (indirect 0x0720)
2285 * no command data struct used
2287 struct i40e_aqc_nvm_oem_post_update {
2288 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01
2293 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
2295 struct i40e_aqc_nvm_oem_post_update_buffer {
2302 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
2304 /* Thermal Sensor (indirect 0x0721)
2305 * read or set thermal sensor configs and values
2306 * takes a sensor and command specific data buffer, not detailed here
2308 struct i40e_aqc_thermal_sensor {
2310 #define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0
2311 #define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1
2312 #define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2
2318 I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor);
2320 /* Send to PF command (indirect 0x0801) id is only used by PF
2321 * Send to VF command (indirect 0x0802) id is only used by PF
2322 * Send to Peer PF command (indirect 0x0803)
2324 struct i40e_aqc_pf_vf_message {
2331 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
2333 /* Alternate structure */
2335 /* Direct write (direct 0x0900)
2336 * Direct read (direct 0x0902)
2338 struct i40e_aqc_alternate_write {
2345 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
2347 /* Indirect write (indirect 0x0901)
2348 * Indirect read (indirect 0x0903)
2351 struct i40e_aqc_alternate_ind_write {
2358 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
2360 /* Done alternate write (direct 0x0904)
2363 struct i40e_aqc_alternate_write_done {
2365 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1
2366 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
2367 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1
2368 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2
2372 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
2374 /* Set OEM mode (direct 0x0905) */
2375 struct i40e_aqc_alternate_set_mode {
2377 #define I40E_AQ_ALTERNATE_MODE_NONE 0
2378 #define I40E_AQ_ALTERNATE_MODE_OEM 1
2382 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
2384 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
2386 /* async events 0x10xx */
2388 /* Lan Queue Overflow Event (direct, 0x1001) */
2389 struct i40e_aqc_lan_overflow {
2390 __le32 prtdcb_rupto;
2395 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
2397 /* Get LLDP MIB (indirect 0x0A00) */
2398 struct i40e_aqc_lldp_get_mib {
2401 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
2402 #define I40E_AQ_LLDP_MIB_LOCAL 0x0
2403 #define I40E_AQ_LLDP_MIB_REMOTE 0x1
2404 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
2405 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
2406 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
2407 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
2408 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
2409 #define I40E_AQ_LLDP_TX_SHIFT 0x4
2410 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT)
2411 /* TX pause flags use I40E_AQ_LINK_TX_* above */
2419 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
2421 /* Configure LLDP MIB Change Event (direct 0x0A01)
2422 * also used for the event (with type in the command field)
2424 struct i40e_aqc_lldp_update_mib {
2426 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
2427 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
2433 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
2435 /* Add LLDP TLV (indirect 0x0A02)
2436 * Delete LLDP TLV (indirect 0x0A04)
2438 struct i40e_aqc_lldp_add_tlv {
2439 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2447 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
2449 /* Update LLDP TLV (indirect 0x0A03) */
2450 struct i40e_aqc_lldp_update_tlv {
2451 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2460 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
2462 /* Stop LLDP (direct 0x0A05) */
2463 struct i40e_aqc_lldp_stop {
2465 #define I40E_AQ_LLDP_AGENT_STOP 0x0
2466 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
2470 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
2472 /* Start LLDP (direct 0x0A06) */
2474 struct i40e_aqc_lldp_start {
2476 #define I40E_AQ_LLDP_AGENT_START 0x1
2480 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
2482 /* Set DCB (direct 0x0303) */
2483 struct i40e_aqc_set_dcb_parameters {
2485 #define I40E_AQ_DCB_SET_AGENT 0x1
2486 #define I40E_DCB_VALID 0x1
2491 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_dcb_parameters);
2493 /* Get CEE DCBX Oper Config (0x0A07)
2494 * uses the generic descriptor struct
2495 * returns below as indirect response
2498 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2499 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2500 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2501 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2502 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2503 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2505 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2506 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2507 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2508 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2509 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2510 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2511 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8
2512 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT)
2513 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB
2514 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT)
2515 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10
2516 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT)
2518 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with
2519 * word boundary layout issues, which the Linux compilers silently deal
2520 * with by adding padding, making the actual struct larger than designed.
2521 * However, the FW compiler for the NIC is less lenient and complains
2522 * about the struct. Hence, the struct defined here has an extra byte in
2523 * fields reserved3 and reserved4 to directly acknowledge that padding,
2524 * and the new length is used in the length check macro.
2526 struct i40e_aqc_get_cee_dcb_cfg_v1_resp {
2534 __le16 oper_app_prio;
2539 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp);
2541 struct i40e_aqc_get_cee_dcb_cfg_resp {
2546 __le16 oper_app_prio;
2551 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp);
2553 /* Set Local LLDP MIB (indirect 0x0A08)
2554 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx
2556 struct i40e_aqc_lldp_set_local_mib {
2557 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0
2558 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \
2559 SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
2560 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0
2561 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1)
2562 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \
2563 SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT)
2564 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1
2569 __le32 address_high;
2573 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib);
2575 struct i40e_aqc_lldp_set_local_mib_resp {
2576 #define SET_LOCAL_MIB_RESP_EVENT_TRIGGERED_MASK 0x01
2581 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_lldp_set_local_mib_resp);
2583 /* Stop/Start LLDP Agent (direct 0x0A09)
2584 * Used for stopping/starting specific LLDP agent. e.g. DCBx
2586 struct i40e_aqc_lldp_stop_start_specific_agent {
2587 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0
2588 #define I40E_AQC_START_SPECIFIC_AGENT_MASK \
2589 (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT)
2594 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent);
2596 /* Add Udp Tunnel command and completion (direct 0x0B00) */
2597 struct i40e_aqc_add_udp_tunnel {
2601 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
2602 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01
2603 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10
2604 #define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11
2608 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2610 struct i40e_aqc_add_udp_tunnel_completion {
2612 u8 filter_entry_index;
2614 #define I40E_AQC_SINGLE_PF 0x0
2615 #define I40E_AQC_MULTIPLE_PFS 0x1
2620 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2622 /* remove UDP Tunnel command (0x0B01) */
2623 struct i40e_aqc_remove_udp_tunnel {
2625 u8 index; /* 0 to 15 */
2629 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2631 struct i40e_aqc_del_udp_tunnel_completion {
2633 u8 index; /* 0 to 15 */
2635 u8 total_filters_used;
2639 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2641 struct i40e_aqc_get_set_rss_key {
2642 #define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15)
2643 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
2644 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
2645 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2652 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);
2654 struct i40e_aqc_get_set_rss_key_data {
2655 u8 standard_rss_key[0x28];
2656 u8 extended_hash_key[0xc];
2659 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
2661 struct i40e_aqc_get_set_rss_lut {
2662 #define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15)
2663 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
2664 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
2665 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2667 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
2668 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \
2669 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2671 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
2672 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1
2679 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);
2681 /* tunnel key structure 0x0B10 */
2683 struct i40e_aqc_tunnel_key_structure {
2686 u8 key1_len; /* 0 to 15 */
2687 u8 key2_len; /* 0 to 15 */
2689 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2690 /* response flags */
2691 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2692 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2693 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2694 u8 network_key_index;
2695 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
2696 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1
2697 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
2698 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3
2702 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2704 /* OEM mode commands (direct 0xFE0x) */
2705 struct i40e_aqc_oem_param_change {
2707 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0
2708 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1
2709 #define I40E_AQ_OEM_PARAM_MAC 2
2710 __le32 param_value1;
2711 __le16 param_value2;
2715 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2717 struct i40e_aqc_oem_state_change {
2719 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0
2720 #define I40E_AQ_OEM_STATE_LINK_UP 0x1
2724 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2726 /* Initialize OCSD (0xFE02, direct) */
2727 struct i40e_aqc_opc_oem_ocsd_initialize {
2730 __le32 ocsd_memory_block_addr_high;
2731 __le32 ocsd_memory_block_addr_low;
2732 __le32 requested_update_interval;
2735 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);
2737 /* Initialize OCBB (0xFE03, direct) */
2738 struct i40e_aqc_opc_oem_ocbb_initialize {
2741 __le32 ocbb_memory_block_addr_high;
2742 __le32 ocbb_memory_block_addr_low;
2746 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);
2748 /* debug commands */
2750 /* get device id (0xFF00) uses the generic structure */
2752 /* set test more (0xFF01, internal) */
2754 struct i40e_acq_set_test_mode {
2756 #define I40E_AQ_TEST_PARTIAL 0
2757 #define I40E_AQ_TEST_FULL 1
2758 #define I40E_AQ_TEST_NVM 2
2761 #define I40E_AQ_TEST_OPEN 0
2762 #define I40E_AQ_TEST_CLOSE 1
2763 #define I40E_AQ_TEST_INC 2
2765 __le32 address_high;
2769 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2771 /* Debug Read Register command (0xFF03)
2772 * Debug Write Register command (0xFF04)
2774 struct i40e_aqc_debug_reg_read_write {
2781 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2783 /* Scatter/gather Reg Read (indirect 0xFF05)
2784 * Scatter/gather Reg Write (indirect 0xFF06)
2787 /* i40e_aq_desc is used for the command */
2788 struct i40e_aqc_debug_reg_sg_element_data {
2793 /* Debug Modify register (direct 0xFF07) */
2794 struct i40e_aqc_debug_modify_reg {
2801 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2803 /* dump internal data (0xFF08, indirect) */
2805 #define I40E_AQ_CLUSTER_ID_AUX 0
2806 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1
2807 #define I40E_AQ_CLUSTER_ID_TXSCHED 2
2808 #define I40E_AQ_CLUSTER_ID_HMC 3
2809 #define I40E_AQ_CLUSTER_ID_MAC0 4
2810 #define I40E_AQ_CLUSTER_ID_MAC1 5
2811 #define I40E_AQ_CLUSTER_ID_MAC2 6
2812 #define I40E_AQ_CLUSTER_ID_MAC3 7
2813 #define I40E_AQ_CLUSTER_ID_DCB 8
2814 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9
2815 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10
2816 #define I40E_AQ_CLUSTER_ID_ALTRAM 11
2818 struct i40e_aqc_debug_dump_internals {
2823 __le32 address_high;
2827 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2829 struct i40e_aqc_debug_modify_internals {
2831 u8 cluster_specific_params[7];
2832 __le32 address_high;
2836 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
2838 #endif /* _I40E_ADMINQ_CMD_H_ */