drivers/net/i40e/base/i40e_common.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "i40e_type.h"
  35 #include "i40e_adminq.h"
  36 #include "i40e_prototype.h"
  37 #include "virtchnl.h"
  38
  39
  40 /**
  41  * i40e_set_mac_type - Sets MAC type
  42  * @hw: pointer to the HW structure
  43  *
  44  * This function sets the mac type of the adapter based on the
  45  * vendor ID and device ID stored in the hw structure.
  46  **/
  47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  49 #else
  50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  51 #endif
  52 {
  53         enum i40e_status_code status = I40E_SUCCESS;
  54
  55         DEBUGFUNC("i40e_set_mac_type\n");
  56
  57         if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
  58                 switch (hw->device_id) {
  59                 case I40E_DEV_ID_SFP_XL710:
  60                 case I40E_DEV_ID_QEMU:
  61                 case I40E_DEV_ID_KX_B:
  62                 case I40E_DEV_ID_KX_C:
  63                 case I40E_DEV_ID_QSFP_A:
  64                 case I40E_DEV_ID_QSFP_B:
  65                 case I40E_DEV_ID_QSFP_C:
  66                 case I40E_DEV_ID_10G_BASE_T:
  67                 case I40E_DEV_ID_10G_BASE_T4:
  68                 case I40E_DEV_ID_20G_KR2:
  69                 case I40E_DEV_ID_20G_KR2_A:
  70                 case I40E_DEV_ID_25G_B:
  71                 case I40E_DEV_ID_25G_SFP28:
  72                         hw->mac.type = I40E_MAC_XL710;
  73                         break;
  74 #ifdef X722_A0_SUPPORT
  75                 case I40E_DEV_ID_X722_A0:
  76 #endif
  77                 case I40E_DEV_ID_KX_X722:
  78                 case I40E_DEV_ID_QSFP_X722:
  79                 case I40E_DEV_ID_SFP_X722:
  80                 case I40E_DEV_ID_1G_BASE_T_X722:
  81                 case I40E_DEV_ID_10G_BASE_T_X722:
  82                 case I40E_DEV_ID_SFP_I_X722:
  83                         hw->mac.type = I40E_MAC_X722;
  84                         break;
  85 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  86                 case I40E_DEV_ID_X722_VF:
  87 #ifdef X722_A0_SUPPORT
  88                 case I40E_DEV_ID_X722_A0_VF:
  89 #endif
  90                         hw->mac.type = I40E_MAC_X722_VF;
  91                         break;
  92 #endif /* INTEGRATED_VF || VF_DRIVER */
  93 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  94                 case I40E_DEV_ID_VF:
  95                 case I40E_DEV_ID_VF_HV:
  96                 case I40E_DEV_ID_ADAPTIVE_VF:
  97                         hw->mac.type = I40E_MAC_VF;
  98                         break;
  99 #endif
 100                 default:
 101                         hw->mac.type = I40E_MAC_GENERIC;
 102                         break;
 103                 }
 104         } else {
 105                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
 106         }
 107
 108         DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
 109                   hw->mac.type, status);
 110         return status;
 111 }
 112
 113 /**
 114  * i40e_aq_str - convert AQ err code to a string
 115  * @hw: pointer to the HW structure
 116  * @aq_err: the AQ error code to convert
 117  **/
 118 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
 119 {
 120         switch (aq_err) {
 121         case I40E_AQ_RC_OK:
 122                 return "OK";
 123         case I40E_AQ_RC_EPERM:
 124                 return "I40E_AQ_RC_EPERM";
 125         case I40E_AQ_RC_ENOENT:
 126                 return "I40E_AQ_RC_ENOENT";
 127         case I40E_AQ_RC_ESRCH:
 128                 return "I40E_AQ_RC_ESRCH";
 129         case I40E_AQ_RC_EINTR:
 130                 return "I40E_AQ_RC_EINTR";
 131         case I40E_AQ_RC_EIO:
 132                 return "I40E_AQ_RC_EIO";
 133         case I40E_AQ_RC_ENXIO:
 134                 return "I40E_AQ_RC_ENXIO";
 135         case I40E_AQ_RC_E2BIG:
 136                 return "I40E_AQ_RC_E2BIG";
 137         case I40E_AQ_RC_EAGAIN:
 138                 return "I40E_AQ_RC_EAGAIN";
 139         case I40E_AQ_RC_ENOMEM:
 140                 return "I40E_AQ_RC_ENOMEM";
 141         case I40E_AQ_RC_EACCES:
 142                 return "I40E_AQ_RC_EACCES";
 143         case I40E_AQ_RC_EFAULT:
 144                 return "I40E_AQ_RC_EFAULT";
 145         case I40E_AQ_RC_EBUSY:
 146                 return "I40E_AQ_RC_EBUSY";
 147         case I40E_AQ_RC_EEXIST:
 148                 return "I40E_AQ_RC_EEXIST";
 149         case I40E_AQ_RC_EINVAL:
 150                 return "I40E_AQ_RC_EINVAL";
 151         case I40E_AQ_RC_ENOTTY:
 152                 return "I40E_AQ_RC_ENOTTY";
 153         case I40E_AQ_RC_ENOSPC:
 154                 return "I40E_AQ_RC_ENOSPC";
 155         case I40E_AQ_RC_ENOSYS:
 156                 return "I40E_AQ_RC_ENOSYS";
 157         case I40E_AQ_RC_ERANGE:
 158                 return "I40E_AQ_RC_ERANGE";
 159         case I40E_AQ_RC_EFLUSHED:
 160                 return "I40E_AQ_RC_EFLUSHED";
 161         case I40E_AQ_RC_BAD_ADDR:
 162                 return "I40E_AQ_RC_BAD_ADDR";
 163         case I40E_AQ_RC_EMODE:
 164                 return "I40E_AQ_RC_EMODE";
 165         case I40E_AQ_RC_EFBIG:
 166                 return "I40E_AQ_RC_EFBIG";
 167         }
 168
 169         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 170         return hw->err_str;
 171 }
 172
 173 /**
 174  * i40e_stat_str - convert status err code to a string
 175  * @hw: pointer to the HW structure
 176  * @stat_err: the status error code to convert
 177  **/
 178 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
 179 {
 180         switch (stat_err) {
 181         case I40E_SUCCESS:
 182                 return "OK";
 183         case I40E_ERR_NVM:
 184                 return "I40E_ERR_NVM";
 185         case I40E_ERR_NVM_CHECKSUM:
 186                 return "I40E_ERR_NVM_CHECKSUM";
 187         case I40E_ERR_PHY:
 188                 return "I40E_ERR_PHY";
 189         case I40E_ERR_CONFIG:
 190                 return "I40E_ERR_CONFIG";
 191         case I40E_ERR_PARAM:
 192                 return "I40E_ERR_PARAM";
 193         case I40E_ERR_MAC_TYPE:
 194                 return "I40E_ERR_MAC_TYPE";
 195         case I40E_ERR_UNKNOWN_PHY:
 196                 return "I40E_ERR_UNKNOWN_PHY";
 197         case I40E_ERR_LINK_SETUP:
 198                 return "I40E_ERR_LINK_SETUP";
 199         case I40E_ERR_ADAPTER_STOPPED:
 200                 return "I40E_ERR_ADAPTER_STOPPED";
 201         case I40E_ERR_INVALID_MAC_ADDR:
 202                 return "I40E_ERR_INVALID_MAC_ADDR";
 203         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 204                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 205         case I40E_ERR_MASTER_REQUESTS_PENDING:
 206                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 207         case I40E_ERR_INVALID_LINK_SETTINGS:
 208                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 209         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 210                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 211         case I40E_ERR_RESET_FAILED:
 212                 return "I40E_ERR_RESET_FAILED";
 213         case I40E_ERR_SWFW_SYNC:
 214                 return "I40E_ERR_SWFW_SYNC";
 215         case I40E_ERR_NO_AVAILABLE_VSI:
 216                 return "I40E_ERR_NO_AVAILABLE_VSI";
 217         case I40E_ERR_NO_MEMORY:
 218                 return "I40E_ERR_NO_MEMORY";
 219         case I40E_ERR_BAD_PTR:
 220                 return "I40E_ERR_BAD_PTR";
 221         case I40E_ERR_RING_FULL:
 222                 return "I40E_ERR_RING_FULL";
 223         case I40E_ERR_INVALID_PD_ID:
 224                 return "I40E_ERR_INVALID_PD_ID";
 225         case I40E_ERR_INVALID_QP_ID:
 226                 return "I40E_ERR_INVALID_QP_ID";
 227         case I40E_ERR_INVALID_CQ_ID:
 228                 return "I40E_ERR_INVALID_CQ_ID";
 229         case I40E_ERR_INVALID_CEQ_ID:
 230                 return "I40E_ERR_INVALID_CEQ_ID";
 231         case I40E_ERR_INVALID_AEQ_ID:
 232                 return "I40E_ERR_INVALID_AEQ_ID";
 233         case I40E_ERR_INVALID_SIZE:
 234                 return "I40E_ERR_INVALID_SIZE";
 235         case I40E_ERR_INVALID_ARP_INDEX:
 236                 return "I40E_ERR_INVALID_ARP_INDEX";
 237         case I40E_ERR_INVALID_FPM_FUNC_ID:
 238                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 239         case I40E_ERR_QP_INVALID_MSG_SIZE:
 240                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 241         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 242                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 243         case I40E_ERR_INVALID_FRAG_COUNT:
 244                 return "I40E_ERR_INVALID_FRAG_COUNT";
 245         case I40E_ERR_QUEUE_EMPTY:
 246                 return "I40E_ERR_QUEUE_EMPTY";
 247         case I40E_ERR_INVALID_ALIGNMENT:
 248                 return "I40E_ERR_INVALID_ALIGNMENT";
 249         case I40E_ERR_FLUSHED_QUEUE:
 250                 return "I40E_ERR_FLUSHED_QUEUE";
 251         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 252                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 253         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 254                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 255         case I40E_ERR_TIMEOUT:
 256                 return "I40E_ERR_TIMEOUT";
 257         case I40E_ERR_OPCODE_MISMATCH:
 258                 return "I40E_ERR_OPCODE_MISMATCH";
 259         case I40E_ERR_CQP_COMPL_ERROR:
 260                 return "I40E_ERR_CQP_COMPL_ERROR";
 261         case I40E_ERR_INVALID_VF_ID:
 262                 return "I40E_ERR_INVALID_VF_ID";
 263         case I40E_ERR_INVALID_HMCFN_ID:
 264                 return "I40E_ERR_INVALID_HMCFN_ID";
 265         case I40E_ERR_BACKING_PAGE_ERROR:
 266                 return "I40E_ERR_BACKING_PAGE_ERROR";
 267         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 268                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 269         case I40E_ERR_INVALID_PBLE_INDEX:
 270                 return "I40E_ERR_INVALID_PBLE_INDEX";
 271         case I40E_ERR_INVALID_SD_INDEX:
 272                 return "I40E_ERR_INVALID_SD_INDEX";
 273         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 274                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 275         case I40E_ERR_INVALID_SD_TYPE:
 276                 return "I40E_ERR_INVALID_SD_TYPE";
 277         case I40E_ERR_MEMCPY_FAILED:
 278                 return "I40E_ERR_MEMCPY_FAILED";
 279         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 280                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 281         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 282                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 283         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 284                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 285         case I40E_ERR_SRQ_ENABLED:
 286                 return "I40E_ERR_SRQ_ENABLED";
 287         case I40E_ERR_ADMIN_QUEUE_ERROR:
 288                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 289         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 290                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 291         case I40E_ERR_BUF_TOO_SHORT:
 292                 return "I40E_ERR_BUF_TOO_SHORT";
 293         case I40E_ERR_ADMIN_QUEUE_FULL:
 294                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 295         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 296                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 297         case I40E_ERR_BAD_IWARP_CQE:
 298                 return "I40E_ERR_BAD_IWARP_CQE";
 299         case I40E_ERR_NVM_BLANK_MODE:
 300                 return "I40E_ERR_NVM_BLANK_MODE";
 301         case I40E_ERR_NOT_IMPLEMENTED:
 302                 return "I40E_ERR_NOT_IMPLEMENTED";
 303         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 304                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 305         case I40E_ERR_DIAG_TEST_FAILED:
 306                 return "I40E_ERR_DIAG_TEST_FAILED";
 307         case I40E_ERR_NOT_READY:
 308                 return "I40E_ERR_NOT_READY";
 309         case I40E_NOT_SUPPORTED:
 310                 return "I40E_NOT_SUPPORTED";
 311         case I40E_ERR_FIRMWARE_API_VERSION:
 312                 return "I40E_ERR_FIRMWARE_API_VERSION";
 313         }
 314
 315         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 316         return hw->err_str;
 317 }
 318
 319 /**
 320  * i40e_debug_aq
 321  * @hw: debug mask related to admin queue
 322  * @mask: debug mask
 323  * @desc: pointer to admin queue descriptor
 324  * @buffer: pointer to command buffer
 325  * @buf_len: max length of buffer
 326  *
 327  * Dumps debug log about adminq command with descriptor contents.
 328  **/
 329 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 330                    void *buffer, u16 buf_len)
 331 {
 332         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 333         u16 len = LE16_TO_CPU(aq_desc->datalen);
 334         u8 *buf = (u8 *)buffer;
 335         u16 i = 0;
 336
 337         if ((!(mask & hw->debug_mask)) || (desc == NULL))
 338                 return;
 339
 340         i40e_debug(hw, mask,
 341                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 342                    LE16_TO_CPU(aq_desc->opcode),
 343                    LE16_TO_CPU(aq_desc->flags),
 344                    LE16_TO_CPU(aq_desc->datalen),
 345                    LE16_TO_CPU(aq_desc->retval));
 346         i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
 347                    LE32_TO_CPU(aq_desc->cookie_high),
 348                    LE32_TO_CPU(aq_desc->cookie_low));
 349         i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
 350                    LE32_TO_CPU(aq_desc->params.internal.param0),
 351                    LE32_TO_CPU(aq_desc->params.internal.param1));
 352         i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
 353                    LE32_TO_CPU(aq_desc->params.external.addr_high),
 354                    LE32_TO_CPU(aq_desc->params.external.addr_low));
 355
 356         if ((buffer != NULL) && (aq_desc->datalen != 0)) {
 357                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 358                 if (buf_len < len)
 359                         len = buf_len;
 360                 /* write the full 16-byte chunks */
 361                 for (i = 0; i < (len - 16); i += 16)
 362                         i40e_debug(hw, mask,
 363                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 364                                    i, buf[i], buf[i+1], buf[i+2], buf[i+3],
 365                                    buf[i+4], buf[i+5], buf[i+6], buf[i+7],
 366                                    buf[i+8], buf[i+9], buf[i+10], buf[i+11],
 367                                    buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
 368                 /* the most we could have left is 16 bytes, pad with zeros */
 369                 if (i < len) {
 370                         char d_buf[16];
 371                         int j, i_sav;
 372
 373                         i_sav = i;
 374                         memset(d_buf, 0, sizeof(d_buf));
 375                         for (j = 0; i < len; j++, i++)
 376                                 d_buf[j] = buf[i];
 377                         i40e_debug(hw, mask,
 378                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 379                                    i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
 380                                    d_buf[4], d_buf[5], d_buf[6], d_buf[7],
 381                                    d_buf[8], d_buf[9], d_buf[10], d_buf[11],
 382                                    d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
 383                 }
 384         }
 385 }
 386
 387 /**
 388  * i40e_check_asq_alive
 389  * @hw: pointer to the hw struct
 390  *
 391  * Returns true if Queue is enabled else false.
 392  **/
 393 bool i40e_check_asq_alive(struct i40e_hw *hw)
 394 {
 395         if (hw->aq.asq.len)
 396 #ifdef PF_DRIVER
 397 #ifdef INTEGRATED_VF
 398                 if (!i40e_is_vf(hw))
 399                         return !!(rd32(hw, hw->aq.asq.len) &
 400                                 I40E_PF_ATQLEN_ATQENABLE_MASK);
 401 #else
 402                 return !!(rd32(hw, hw->aq.asq.len) &
 403                         I40E_PF_ATQLEN_ATQENABLE_MASK);
 404 #endif /* INTEGRATED_VF */
 405 #endif /* PF_DRIVER */
 406 #ifdef VF_DRIVER
 407 #ifdef INTEGRATED_VF
 408                 if (i40e_is_vf(hw))
 409                         return !!(rd32(hw, hw->aq.asq.len) &
 410                                 I40E_VF_ATQLEN1_ATQENABLE_MASK);
 411 #else
 412                 return !!(rd32(hw, hw->aq.asq.len) &
 413                         I40E_VF_ATQLEN1_ATQENABLE_MASK);
 414 #endif /* INTEGRATED_VF */
 415 #endif /* VF_DRIVER */
 416         return false;
 417 }
 418
 419 /**
 420  * i40e_aq_queue_shutdown
 421  * @hw: pointer to the hw struct
 422  * @unloading: is the driver unloading itself
 423  *
 424  * Tell the Firmware that we're shutting down the AdminQ and whether
 425  * or not the driver is unloading as well.
 426  **/
 427 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
 428                                              bool unloading)
 429 {
 430         struct i40e_aq_desc desc;
 431         struct i40e_aqc_queue_shutdown *cmd =
 432                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 433         enum i40e_status_code status;
 434
 435         i40e_fill_default_direct_cmd_desc(&desc,
 436                                           i40e_aqc_opc_queue_shutdown);
 437
 438         if (unloading)
 439                 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
 440         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 441
 442         return status;
 443 }
 444
 445 /**
 446  * i40e_aq_get_set_rss_lut
 447  * @hw: pointer to the hardware structure
 448  * @vsi_id: vsi fw index
 449  * @pf_lut: for PF table set true, for VSI table set false
 450  * @lut: pointer to the lut buffer provided by the caller
 451  * @lut_size: size of the lut buffer
 452  * @set: set true to set the table, false to get the table
 453  *
 454  * Internal function to get or set RSS look up table
 455  **/
 456 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 457                                                      u16 vsi_id, bool pf_lut,
 458                                                      u8 *lut, u16 lut_size,
 459                                                      bool set)
 460 {
 461         enum i40e_status_code status;
 462         struct i40e_aq_desc desc;
 463         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 464                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 465
 466         if (set)
 467                 i40e_fill_default_direct_cmd_desc(&desc,
 468                                                   i40e_aqc_opc_set_rss_lut);
 469         else
 470                 i40e_fill_default_direct_cmd_desc(&desc,
 471                                                   i40e_aqc_opc_get_rss_lut);
 472
 473         /* Indirect command */
 474         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 475         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 476
 477         cmd_resp->vsi_id =
 478                         CPU_TO_LE16((u16)((vsi_id <<
 479                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 480                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 481         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 482
 483         if (pf_lut)
 484                 cmd_resp->flags |= CPU_TO_LE16((u16)
 485                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 486                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 487                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 488         else
 489                 cmd_resp->flags |= CPU_TO_LE16((u16)
 490                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 491                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 492                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 493
 494         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 495
 496         return status;
 497 }
 498
 499 /**
 500  * i40e_aq_get_rss_lut
 501  * @hw: pointer to the hardware structure
 502  * @vsi_id: vsi fw index
 503  * @pf_lut: for PF table set true, for VSI table set false
 504  * @lut: pointer to the lut buffer provided by the caller
 505  * @lut_size: size of the lut buffer
 506  *
 507  * get the RSS lookup table, PF or VSI type
 508  **/
 509 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 510                                           bool pf_lut, u8 *lut, u16 lut_size)
 511 {
 512         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 513                                        false);
 514 }
 515
 516 /**
 517  * i40e_aq_set_rss_lut
 518  * @hw: pointer to the hardware structure
 519  * @vsi_id: vsi fw index
 520  * @pf_lut: for PF table set true, for VSI table set false
 521  * @lut: pointer to the lut buffer provided by the caller
 522  * @lut_size: size of the lut buffer
 523  *
 524  * set the RSS lookup table, PF or VSI type
 525  **/
 526 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 527                                           bool pf_lut, u8 *lut, u16 lut_size)
 528 {
 529         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
 530 }
 531
 532 /**
 533  * i40e_aq_get_set_rss_key
 534  * @hw: pointer to the hw struct
 535  * @vsi_id: vsi fw index
 536  * @key: pointer to key info struct
 537  * @set: set true to set the key, false to get the key
 538  *
 539  * get the RSS key per VSI
 540  **/
 541 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 542                                       u16 vsi_id,
 543                                       struct i40e_aqc_get_set_rss_key_data *key,
 544                                       bool set)
 545 {
 546         enum i40e_status_code status;
 547         struct i40e_aq_desc desc;
 548         struct i40e_aqc_get_set_rss_key *cmd_resp =
 549                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 550         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 551
 552         if (set)
 553                 i40e_fill_default_direct_cmd_desc(&desc,
 554                                                   i40e_aqc_opc_set_rss_key);
 555         else
 556                 i40e_fill_default_direct_cmd_desc(&desc,
 557                                                   i40e_aqc_opc_get_rss_key);
 558
 559         /* Indirect command */
 560         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 561         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 562
 563         cmd_resp->vsi_id =
 564                         CPU_TO_LE16((u16)((vsi_id <<
 565                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 566                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 567         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 568
 569         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 570
 571         return status;
 572 }
 573
 574 /**
 575  * i40e_aq_get_rss_key
 576  * @hw: pointer to the hw struct
 577  * @vsi_id: vsi fw index
 578  * @key: pointer to key info struct
 579  *
 580  **/
 581 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
 582                                       u16 vsi_id,
 583                                       struct i40e_aqc_get_set_rss_key_data *key)
 584 {
 585         return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
 586 }
 587
 588 /**
 589  * i40e_aq_set_rss_key
 590  * @hw: pointer to the hw struct
 591  * @vsi_id: vsi fw index
 592  * @key: pointer to key info struct
 593  *
 594  * set the RSS key per VSI
 595  **/
 596 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
 597                                       u16 vsi_id,
 598                                       struct i40e_aqc_get_set_rss_key_data *key)
 599 {
 600         return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
 601 }
 602
 603 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 604  * hardware to a bit-field that can be used by SW to more easily determine the
 605  * packet type.
 606  *
 607  * Macros are used to shorten the table lines and make this table human
 608  * readable.
 609  *
 610  * We store the PTYPE in the top byte of the bit field - this is just so that
 611  * we can check that the table doesn't have a row missing, as the index into
 612  * the table should be the PTYPE.
 613  *
 614  * Typical work flow:
 615  *
 616  * IF NOT i40e_ptype_lookup[ptype].known
 617  * THEN
 618  *      Packet is unknown
 619  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 620  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 621  * ELSE
 622  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 623  * ENDIF
 624  */
 625
 626 /* macro to make the table lines short */
 627 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 628         {       PTYPE, \
 629                 1, \
 630                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 631                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 632                 I40E_RX_PTYPE_##OUTER_FRAG, \
 633                 I40E_RX_PTYPE_TUNNEL_##T, \
 634                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 635                 I40E_RX_PTYPE_##TEF, \
 636                 I40E_RX_PTYPE_INNER_PROT_##I, \
 637                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 638
 639 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 640                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 641
 642 /* shorter macros makes the table fit but are terse */
 643 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 644 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 645 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 646
 647 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 648 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 649         /* L2 Packet types */
 650         I40E_PTT_UNUSED_ENTRY(0),
 651         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 652         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 653         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 654         I40E_PTT_UNUSED_ENTRY(4),
 655         I40E_PTT_UNUSED_ENTRY(5),
 656         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 657         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 658         I40E_PTT_UNUSED_ENTRY(8),
 659         I40E_PTT_UNUSED_ENTRY(9),
 660         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 661         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 662         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 663         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 664         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 665         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 666         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 667         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 668         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 669         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 670         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 671         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 672
 673         /* Non Tunneled IPv4 */
 674         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 675         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 676         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 677         I40E_PTT_UNUSED_ENTRY(25),
 678         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 679         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 680         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 681
 682         /* IPv4 --> IPv4 */
 683         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 684         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 685         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 686         I40E_PTT_UNUSED_ENTRY(32),
 687         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 688         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 689         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 690
 691         /* IPv4 --> IPv6 */
 692         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 693         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 694         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 695         I40E_PTT_UNUSED_ENTRY(39),
 696         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 697         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 698         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 699
 700         /* IPv4 --> GRE/NAT */
 701         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 702
 703         /* IPv4 --> GRE/NAT --> IPv4 */
 704         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 705         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 706         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 707         I40E_PTT_UNUSED_ENTRY(47),
 708         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 709         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 710         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 711
 712         /* IPv4 --> GRE/NAT --> IPv6 */
 713         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 714         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 715         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 716         I40E_PTT_UNUSED_ENTRY(54),
 717         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 718         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 719         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 720
 721         /* IPv4 --> GRE/NAT --> MAC */
 722         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 723
 724         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 725         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 726         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 727         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 728         I40E_PTT_UNUSED_ENTRY(62),
 729         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 730         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 731         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 732
 733         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 734         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 735         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 736         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 737         I40E_PTT_UNUSED_ENTRY(69),
 738         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 739         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 740         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 741
 742         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 743         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 744
 745         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 746         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 747         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 748         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 749         I40E_PTT_UNUSED_ENTRY(77),
 750         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 751         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 752         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 753
 754         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 755         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 756         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 757         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 758         I40E_PTT_UNUSED_ENTRY(84),
 759         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 760         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 761         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 762
 763         /* Non Tunneled IPv6 */
 764         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 765         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 766         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
 767         I40E_PTT_UNUSED_ENTRY(91),
 768         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 769         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 770         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 771
 772         /* IPv6 --> IPv4 */
 773         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 774         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 775         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 776         I40E_PTT_UNUSED_ENTRY(98),
 777         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 778         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 779         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 780
 781         /* IPv6 --> IPv6 */
 782         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 783         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 784         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 785         I40E_PTT_UNUSED_ENTRY(105),
 786         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 787         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 788         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 789
 790         /* IPv6 --> GRE/NAT */
 791         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 792
 793         /* IPv6 --> GRE/NAT -> IPv4 */
 794         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 795         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 796         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 797         I40E_PTT_UNUSED_ENTRY(113),
 798         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 799         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 800         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 801
 802         /* IPv6 --> GRE/NAT -> IPv6 */
 803         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 804         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 805         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 806         I40E_PTT_UNUSED_ENTRY(120),
 807         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 808         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 809         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 810
 811         /* IPv6 --> GRE/NAT -> MAC */
 812         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 813
 814         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 815         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 816         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 817         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 818         I40E_PTT_UNUSED_ENTRY(128),
 819         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 820         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 821         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 822
 823         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 824         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 825         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 826         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 827         I40E_PTT_UNUSED_ENTRY(135),
 828         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 829         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 830         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 831
 832         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 833         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 834
 835         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 836         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 837         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 838         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 839         I40E_PTT_UNUSED_ENTRY(143),
 840         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 841         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 842         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 843
 844         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 845         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 846         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 847         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 848         I40E_PTT_UNUSED_ENTRY(150),
 849         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 850         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 851         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 852
 853         /* unused entries */
 854         I40E_PTT_UNUSED_ENTRY(154),
 855         I40E_PTT_UNUSED_ENTRY(155),
 856         I40E_PTT_UNUSED_ENTRY(156),
 857         I40E_PTT_UNUSED_ENTRY(157),
 858         I40E_PTT_UNUSED_ENTRY(158),
 859         I40E_PTT_UNUSED_ENTRY(159),
 860
 861         I40E_PTT_UNUSED_ENTRY(160),
 862         I40E_PTT_UNUSED_ENTRY(161),
 863         I40E_PTT_UNUSED_ENTRY(162),
 864         I40E_PTT_UNUSED_ENTRY(163),
 865         I40E_PTT_UNUSED_ENTRY(164),
 866         I40E_PTT_UNUSED_ENTRY(165),
 867         I40E_PTT_UNUSED_ENTRY(166),
 868         I40E_PTT_UNUSED_ENTRY(167),
 869         I40E_PTT_UNUSED_ENTRY(168),
 870         I40E_PTT_UNUSED_ENTRY(169),
 871
 872         I40E_PTT_UNUSED_ENTRY(170),
 873         I40E_PTT_UNUSED_ENTRY(171),
 874         I40E_PTT_UNUSED_ENTRY(172),
 875         I40E_PTT_UNUSED_ENTRY(173),
 876         I40E_PTT_UNUSED_ENTRY(174),
 877         I40E_PTT_UNUSED_ENTRY(175),
 878         I40E_PTT_UNUSED_ENTRY(176),
 879         I40E_PTT_UNUSED_ENTRY(177),
 880         I40E_PTT_UNUSED_ENTRY(178),
 881         I40E_PTT_UNUSED_ENTRY(179),
 882
 883         I40E_PTT_UNUSED_ENTRY(180),
 884         I40E_PTT_UNUSED_ENTRY(181),
 885         I40E_PTT_UNUSED_ENTRY(182),
 886         I40E_PTT_UNUSED_ENTRY(183),
 887         I40E_PTT_UNUSED_ENTRY(184),
 888         I40E_PTT_UNUSED_ENTRY(185),
 889         I40E_PTT_UNUSED_ENTRY(186),
 890         I40E_PTT_UNUSED_ENTRY(187),
 891         I40E_PTT_UNUSED_ENTRY(188),
 892         I40E_PTT_UNUSED_ENTRY(189),
 893
 894         I40E_PTT_UNUSED_ENTRY(190),
 895         I40E_PTT_UNUSED_ENTRY(191),
 896         I40E_PTT_UNUSED_ENTRY(192),
 897         I40E_PTT_UNUSED_ENTRY(193),
 898         I40E_PTT_UNUSED_ENTRY(194),
 899         I40E_PTT_UNUSED_ENTRY(195),
 900         I40E_PTT_UNUSED_ENTRY(196),
 901         I40E_PTT_UNUSED_ENTRY(197),
 902         I40E_PTT_UNUSED_ENTRY(198),
 903         I40E_PTT_UNUSED_ENTRY(199),
 904
 905         I40E_PTT_UNUSED_ENTRY(200),
 906         I40E_PTT_UNUSED_ENTRY(201),
 907         I40E_PTT_UNUSED_ENTRY(202),
 908         I40E_PTT_UNUSED_ENTRY(203),
 909         I40E_PTT_UNUSED_ENTRY(204),
 910         I40E_PTT_UNUSED_ENTRY(205),
 911         I40E_PTT_UNUSED_ENTRY(206),
 912         I40E_PTT_UNUSED_ENTRY(207),
 913         I40E_PTT_UNUSED_ENTRY(208),
 914         I40E_PTT_UNUSED_ENTRY(209),
 915
 916         I40E_PTT_UNUSED_ENTRY(210),
 917         I40E_PTT_UNUSED_ENTRY(211),
 918         I40E_PTT_UNUSED_ENTRY(212),
 919         I40E_PTT_UNUSED_ENTRY(213),
 920         I40E_PTT_UNUSED_ENTRY(214),
 921         I40E_PTT_UNUSED_ENTRY(215),
 922         I40E_PTT_UNUSED_ENTRY(216),
 923         I40E_PTT_UNUSED_ENTRY(217),
 924         I40E_PTT_UNUSED_ENTRY(218),
 925         I40E_PTT_UNUSED_ENTRY(219),
 926
 927         I40E_PTT_UNUSED_ENTRY(220),
 928         I40E_PTT_UNUSED_ENTRY(221),
 929         I40E_PTT_UNUSED_ENTRY(222),
 930         I40E_PTT_UNUSED_ENTRY(223),
 931         I40E_PTT_UNUSED_ENTRY(224),
 932         I40E_PTT_UNUSED_ENTRY(225),
 933         I40E_PTT_UNUSED_ENTRY(226),
 934         I40E_PTT_UNUSED_ENTRY(227),
 935         I40E_PTT_UNUSED_ENTRY(228),
 936         I40E_PTT_UNUSED_ENTRY(229),
 937
 938         I40E_PTT_UNUSED_ENTRY(230),
 939         I40E_PTT_UNUSED_ENTRY(231),
 940         I40E_PTT_UNUSED_ENTRY(232),
 941         I40E_PTT_UNUSED_ENTRY(233),
 942         I40E_PTT_UNUSED_ENTRY(234),
 943         I40E_PTT_UNUSED_ENTRY(235),
 944         I40E_PTT_UNUSED_ENTRY(236),
 945         I40E_PTT_UNUSED_ENTRY(237),
 946         I40E_PTT_UNUSED_ENTRY(238),
 947         I40E_PTT_UNUSED_ENTRY(239),
 948
 949         I40E_PTT_UNUSED_ENTRY(240),
 950         I40E_PTT_UNUSED_ENTRY(241),
 951         I40E_PTT_UNUSED_ENTRY(242),
 952         I40E_PTT_UNUSED_ENTRY(243),
 953         I40E_PTT_UNUSED_ENTRY(244),
 954         I40E_PTT_UNUSED_ENTRY(245),
 955         I40E_PTT_UNUSED_ENTRY(246),
 956         I40E_PTT_UNUSED_ENTRY(247),
 957         I40E_PTT_UNUSED_ENTRY(248),
 958         I40E_PTT_UNUSED_ENTRY(249),
 959
 960         I40E_PTT_UNUSED_ENTRY(250),
 961         I40E_PTT_UNUSED_ENTRY(251),
 962         I40E_PTT_UNUSED_ENTRY(252),
 963         I40E_PTT_UNUSED_ENTRY(253),
 964         I40E_PTT_UNUSED_ENTRY(254),
 965         I40E_PTT_UNUSED_ENTRY(255)
 966 };
 967
 968
 969 /**
 970  * i40e_validate_mac_addr - Validate unicast MAC address
 971  * @mac_addr: pointer to MAC address
 972  *
 973  * Tests a MAC address to ensure it is a valid Individual Address
 974  **/
 975 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
 976 {
 977         enum i40e_status_code status = I40E_SUCCESS;
 978
 979         DEBUGFUNC("i40e_validate_mac_addr");
 980
 981         /* Broadcast addresses ARE multicast addresses
 982          * Make sure it is not a multicast address
 983          * Reject the zero address
 984          */
 985         if (I40E_IS_MULTICAST(mac_addr) ||
 986             (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
 987               mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
 988                 status = I40E_ERR_INVALID_MAC_ADDR;
 989
 990         return status;
 991 }
 992 #ifdef PF_DRIVER
 993
 994 /**
 995  * i40e_init_shared_code - Initialize the shared code
 996  * @hw: pointer to hardware structure
 997  *
 998  * This assigns the MAC type and PHY code and inits the NVM.
 999  * Does not touch the hardware. This function must be called prior to any
1000  * other function in the shared code. The i40e_hw structure should be
1001  * memset to 0 prior to calling this function.  The following fields in
1002  * hw structure should be filled in prior to calling this function:
1003  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1004  * subsystem_vendor_id, and revision_id
1005  **/
1006 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
1007 {
1008         enum i40e_status_code status = I40E_SUCCESS;
1009         u32 port, ari, func_rid;
1010
1011         DEBUGFUNC("i40e_init_shared_code");
1012
1013         i40e_set_mac_type(hw);
1014
1015         switch (hw->mac.type) {
1016         case I40E_MAC_XL710:
1017         case I40E_MAC_X722:
1018                 break;
1019         default:
1020                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1021         }
1022
1023         hw->phy.get_link_info = true;
1024
1025         /* Determine port number and PF number*/
1026         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1027                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1028         hw->port = (u8)port;
1029         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1030                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1031         func_rid = rd32(hw, I40E_PF_FUNC_RID);
1032         if (ari)
1033                 hw->pf_id = (u8)(func_rid & 0xff);
1034         else
1035                 hw->pf_id = (u8)(func_rid & 0x7);
1036
1037         if (hw->mac.type == I40E_MAC_X722)
1038                 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
1039
1040         status = i40e_init_nvm(hw);
1041         return status;
1042 }
1043
1044 /**
1045  * i40e_aq_mac_address_read - Retrieve the MAC addresses
1046  * @hw: pointer to the hw struct
1047  * @flags: a return indicator of what addresses were added to the addr store
1048  * @addrs: the requestor's mac addr store
1049  * @cmd_details: pointer to command details structure or NULL
1050  **/
1051 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1052                                    u16 *flags,
1053                                    struct i40e_aqc_mac_address_read_data *addrs,
1054                                    struct i40e_asq_cmd_details *cmd_details)
1055 {
1056         struct i40e_aq_desc desc;
1057         struct i40e_aqc_mac_address_read *cmd_data =
1058                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1059         enum i40e_status_code status;
1060
1061         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1062         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1063
1064         status = i40e_asq_send_command(hw, &desc, addrs,
1065                                        sizeof(*addrs), cmd_details);
1066         *flags = LE16_TO_CPU(cmd_data->command_flags);
1067
1068         return status;
1069 }
1070
1071 /**
1072  * i40e_aq_mac_address_write - Change the MAC addresses
1073  * @hw: pointer to the hw struct
1074  * @flags: indicates which MAC to be written
1075  * @mac_addr: address to write
1076  * @cmd_details: pointer to command details structure or NULL
1077  **/
1078 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1079                                     u16 flags, u8 *mac_addr,
1080                                     struct i40e_asq_cmd_details *cmd_details)
1081 {
1082         struct i40e_aq_desc desc;
1083         struct i40e_aqc_mac_address_write *cmd_data =
1084                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1085         enum i40e_status_code status;
1086
1087         i40e_fill_default_direct_cmd_desc(&desc,
1088                                           i40e_aqc_opc_mac_address_write);
1089         cmd_data->command_flags = CPU_TO_LE16(flags);
1090         cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1091         cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1092                                         ((u32)mac_addr[3] << 16) |
1093                                         ((u32)mac_addr[4] << 8) |
1094                                         mac_addr[5]);
1095
1096         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1097
1098         return status;
1099 }
1100
1101 /**
1102  * i40e_get_mac_addr - get MAC address
1103  * @hw: pointer to the HW structure
1104  * @mac_addr: pointer to MAC address
1105  *
1106  * Reads the adapter's MAC address from register
1107  **/
1108 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1109 {
1110         struct i40e_aqc_mac_address_read_data addrs;
1111         enum i40e_status_code status;
1112         u16 flags = 0;
1113
1114         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1115
1116         if (flags & I40E_AQC_LAN_ADDR_VALID)
1117                 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1118                         I40E_NONDMA_TO_NONDMA);
1119
1120         return status;
1121 }
1122
1123 /**
1124  * i40e_get_port_mac_addr - get Port MAC address
1125  * @hw: pointer to the HW structure
1126  * @mac_addr: pointer to Port MAC address
1127  *
1128  * Reads the adapter's Port MAC address
1129  **/
1130 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1131 {
1132         struct i40e_aqc_mac_address_read_data addrs;
1133         enum i40e_status_code status;
1134         u16 flags = 0;
1135
1136         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1137         if (status)
1138                 return status;
1139
1140         if (flags & I40E_AQC_PORT_ADDR_VALID)
1141                 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1142                         I40E_NONDMA_TO_NONDMA);
1143         else
1144                 status = I40E_ERR_INVALID_MAC_ADDR;
1145
1146         return status;
1147 }
1148
1149 /**
1150  * i40e_pre_tx_queue_cfg - pre tx queue configure
1151  * @hw: pointer to the HW structure
1152  * @queue: target pf queue index
1153  * @enable: state change request
1154  *
1155  * Handles hw requirement to indicate intention to enable
1156  * or disable target queue.
1157  **/
1158 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1159 {
1160         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1161         u32 reg_block = 0;
1162         u32 reg_val;
1163
1164         if (abs_queue_idx >= 128) {
1165                 reg_block = abs_queue_idx / 128;
1166                 abs_queue_idx %= 128;
1167         }
1168
1169         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1170         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1171         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1172
1173         if (enable)
1174                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1175         else
1176                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1177
1178         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1179 }
1180
1181 /**
1182  * i40e_get_san_mac_addr - get SAN MAC address
1183  * @hw: pointer to the HW structure
1184  * @mac_addr: pointer to SAN MAC address
1185  *
1186  * Reads the adapter's SAN MAC address from NVM
1187  **/
1188 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1189                                             u8 *mac_addr)
1190 {
1191         struct i40e_aqc_mac_address_read_data addrs;
1192         enum i40e_status_code status;
1193         u16 flags = 0;
1194
1195         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1196         if (status)
1197                 return status;
1198
1199         if (flags & I40E_AQC_SAN_ADDR_VALID)
1200                 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac),
1201                         I40E_NONDMA_TO_NONDMA);
1202         else
1203                 status = I40E_ERR_INVALID_MAC_ADDR;
1204
1205         return status;
1206 }
1207
1208 /**
1209  *  i40e_read_pba_string - Reads part number string from EEPROM
1210  *  @hw: pointer to hardware structure
1211  *  @pba_num: stores the part number string from the EEPROM
1212  *  @pba_num_size: part number string buffer length
1213  *
1214  *  Reads the part number string from the EEPROM.
1215  **/
1216 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1217                                             u32 pba_num_size)
1218 {
1219         enum i40e_status_code status = I40E_SUCCESS;
1220         u16 pba_word = 0;
1221         u16 pba_size = 0;
1222         u16 pba_ptr = 0;
1223         u16 i = 0;
1224
1225         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1226         if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1227                 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1228                 return status;
1229         }
1230
1231         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1232         if (status != I40E_SUCCESS) {
1233                 DEBUGOUT("Failed to read PBA Block pointer.\n");
1234                 return status;
1235         }
1236
1237         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1238         if (status != I40E_SUCCESS) {
1239                 DEBUGOUT("Failed to read PBA Block size.\n");
1240                 return status;
1241         }
1242
1243         /* Subtract one to get PBA word count (PBA Size word is included in
1244          * total size)
1245          */
1246         pba_size--;
1247         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1248                 DEBUGOUT("Buffer to small for PBA data.\n");
1249                 return I40E_ERR_PARAM;
1250         }
1251
1252         for (i = 0; i < pba_size; i++) {
1253                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1254                 if (status != I40E_SUCCESS) {
1255                         DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1256                         return status;
1257                 }
1258
1259                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1260                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1261         }
1262         pba_num[(pba_size * 2)] = '\0';
1263
1264         return status;
1265 }
1266
1267 /**
1268  * i40e_get_media_type - Gets media type
1269  * @hw: pointer to the hardware structure
1270  **/
1271 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1272 {
1273         enum i40e_media_type media;
1274
1275         switch (hw->phy.link_info.phy_type) {
1276         case I40E_PHY_TYPE_10GBASE_SR:
1277         case I40E_PHY_TYPE_10GBASE_LR:
1278         case I40E_PHY_TYPE_1000BASE_SX:
1279         case I40E_PHY_TYPE_1000BASE_LX:
1280         case I40E_PHY_TYPE_40GBASE_SR4:
1281         case I40E_PHY_TYPE_40GBASE_LR4:
1282         case I40E_PHY_TYPE_25GBASE_LR:
1283         case I40E_PHY_TYPE_25GBASE_SR:
1284                 media = I40E_MEDIA_TYPE_FIBER;
1285                 break;
1286         case I40E_PHY_TYPE_100BASE_TX:
1287         case I40E_PHY_TYPE_1000BASE_T:
1288         case I40E_PHY_TYPE_10GBASE_T:
1289                 media = I40E_MEDIA_TYPE_BASET;
1290                 break;
1291         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1292         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1293         case I40E_PHY_TYPE_10GBASE_CR1:
1294         case I40E_PHY_TYPE_40GBASE_CR4:
1295         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1296         case I40E_PHY_TYPE_40GBASE_AOC:
1297         case I40E_PHY_TYPE_10GBASE_AOC:
1298         case I40E_PHY_TYPE_25GBASE_CR:
1299         case I40E_PHY_TYPE_25GBASE_AOC:
1300         case I40E_PHY_TYPE_25GBASE_ACC:
1301                 media = I40E_MEDIA_TYPE_DA;
1302                 break;
1303         case I40E_PHY_TYPE_1000BASE_KX:
1304         case I40E_PHY_TYPE_10GBASE_KX4:
1305         case I40E_PHY_TYPE_10GBASE_KR:
1306         case I40E_PHY_TYPE_40GBASE_KR4:
1307         case I40E_PHY_TYPE_20GBASE_KR2:
1308         case I40E_PHY_TYPE_25GBASE_KR:
1309                 media = I40E_MEDIA_TYPE_BACKPLANE;
1310                 break;
1311         case I40E_PHY_TYPE_SGMII:
1312         case I40E_PHY_TYPE_XAUI:
1313         case I40E_PHY_TYPE_XFI:
1314         case I40E_PHY_TYPE_XLAUI:
1315         case I40E_PHY_TYPE_XLPPI:
1316         default:
1317                 media = I40E_MEDIA_TYPE_UNKNOWN;
1318                 break;
1319         }
1320
1321         return media;
1322 }
1323
1324 #define I40E_PF_RESET_WAIT_COUNT        200
1325 /**
1326  * i40e_pf_reset - Reset the PF
1327  * @hw: pointer to the hardware structure
1328  *
1329  * Assuming someone else has triggered a global reset,
1330  * assure the global reset is complete and then reset the PF
1331  **/
1332 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1333 {
1334         u32 cnt = 0;
1335         u32 cnt1 = 0;
1336         u32 reg = 0;
1337         u32 grst_del;
1338
1339         /* Poll for Global Reset steady state in case of recent GRST.
1340          * The grst delay value is in 100ms units, and we'll wait a
1341          * couple counts longer to be sure we don't just miss the end.
1342          */
1343         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1344                         I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1345                         I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1346
1347         grst_del = grst_del * 20;
1348
1349         for (cnt = 0; cnt < grst_del; cnt++) {
1350                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1351                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1352                         break;
1353                 i40e_msec_delay(100);
1354         }
1355         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1356                 DEBUGOUT("Global reset polling failed to complete.\n");
1357                 return I40E_ERR_RESET_FAILED;
1358         }
1359
1360         /* Now Wait for the FW to be ready */
1361         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1362                 reg = rd32(hw, I40E_GLNVM_ULD);
1363                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1364                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1365                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1366                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1367                         DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1368                         break;
1369                 }
1370                 i40e_msec_delay(10);
1371         }
1372         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1373                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1374                 DEBUGOUT("wait for FW Reset complete timedout\n");
1375                 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1376                 return I40E_ERR_RESET_FAILED;
1377         }
1378
1379         /* If there was a Global Reset in progress when we got here,
1380          * we don't need to do the PF Reset
1381          */
1382         if (!cnt) {
1383                 reg = rd32(hw, I40E_PFGEN_CTRL);
1384                 wr32(hw, I40E_PFGEN_CTRL,
1385                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1386                 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1387                         reg = rd32(hw, I40E_PFGEN_CTRL);
1388                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1389                                 break;
1390                         i40e_msec_delay(1);
1391                 }
1392                 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1393                         DEBUGOUT("PF reset polling failed to complete.\n");
1394                         return I40E_ERR_RESET_FAILED;
1395                 }
1396         }
1397
1398         i40e_clear_pxe_mode(hw);
1399
1400
1401         return I40E_SUCCESS;
1402 }
1403
1404 /**
1405  * i40e_clear_hw - clear out any left over hw state
1406  * @hw: pointer to the hw struct
1407  *
1408  * Clear queues and interrupts, typically called at init time,
1409  * but after the capabilities have been found so we know how many
1410  * queues and msix vectors have been allocated.
1411  **/
1412 void i40e_clear_hw(struct i40e_hw *hw)
1413 {
1414         u32 num_queues, base_queue;
1415         u32 num_pf_int;
1416         u32 num_vf_int;
1417         u32 num_vfs;
1418         u32 i, j;
1419         u32 val;
1420         u32 eol = 0x7ff;
1421
1422         /* get number of interrupts, queues, and vfs */
1423         val = rd32(hw, I40E_GLPCI_CNF2);
1424         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1425                         I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1426         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1427                         I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1428
1429         val = rd32(hw, I40E_PFLAN_QALLOC);
1430         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1431                         I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1432         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1433                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1434         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1435                 num_queues = (j - base_queue) + 1;
1436         else
1437                 num_queues = 0;
1438
1439         val = rd32(hw, I40E_PF_VT_PFALLOC);
1440         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1441                         I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1442         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1443                         I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1444         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1445                 num_vfs = (j - i) + 1;
1446         else
1447                 num_vfs = 0;
1448
1449         /* stop all the interrupts */
1450         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1451         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1452         for (i = 0; i < num_pf_int - 2; i++)
1453                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1454
1455         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1456         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1457         wr32(hw, I40E_PFINT_LNKLST0, val);
1458         for (i = 0; i < num_pf_int - 2; i++)
1459                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1460         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1461         for (i = 0; i < num_vfs; i++)
1462                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1463         for (i = 0; i < num_vf_int - 2; i++)
1464                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1465
1466         /* warn the HW of the coming Tx disables */
1467         for (i = 0; i < num_queues; i++) {
1468                 u32 abs_queue_idx = base_queue + i;
1469                 u32 reg_block = 0;
1470
1471                 if (abs_queue_idx >= 128) {
1472                         reg_block = abs_queue_idx / 128;
1473                         abs_queue_idx %= 128;
1474                 }
1475
1476                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1477                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1478                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1479                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1480
1481                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1482         }
1483         i40e_usec_delay(400);
1484
1485         /* stop all the queues */
1486         for (i = 0; i < num_queues; i++) {
1487                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1488                 wr32(hw, I40E_QTX_ENA(i), 0);
1489                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1490                 wr32(hw, I40E_QRX_ENA(i), 0);
1491         }
1492
1493         /* short wait for all queue disables to settle */
1494         i40e_usec_delay(50);
1495 }
1496
1497 /**
1498  * i40e_clear_pxe_mode - clear pxe operations mode
1499  * @hw: pointer to the hw struct
1500  *
1501  * Make sure all PXE mode settings are cleared, including things
1502  * like descriptor fetch/write-back mode.
1503  **/
1504 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1505 {
1506         if (i40e_check_asq_alive(hw))
1507                 i40e_aq_clear_pxe_mode(hw, NULL);
1508 }
1509
1510 /**
1511  * i40e_led_is_mine - helper to find matching led
1512  * @hw: pointer to the hw struct
1513  * @idx: index into GPIO registers
1514  *
1515  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1516  */
1517 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1518 {
1519         u32 gpio_val = 0;
1520         u32 port;
1521
1522         if (!hw->func_caps.led[idx])
1523                 return 0;
1524
1525         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1526         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1527                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1528
1529         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1530          * if it is not our port then ignore
1531          */
1532         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1533             (port != hw->port))
1534                 return 0;
1535
1536         return gpio_val;
1537 }
1538
1539 #define I40E_COMBINED_ACTIVITY 0xA
1540 #define I40E_FILTER_ACTIVITY 0xE
1541 #define I40E_LINK_ACTIVITY 0xC
1542 #define I40E_MAC_ACTIVITY 0xD
1543 #define I40E_LED0 22
1544
1545 /**
1546  * i40e_led_get - return current on/off mode
1547  * @hw: pointer to the hw struct
1548  *
1549  * The value returned is the 'mode' field as defined in the
1550  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1551  * values are variations of possible behaviors relating to
1552  * blink, link, and wire.
1553  **/
1554 u32 i40e_led_get(struct i40e_hw *hw)
1555 {
1556         u32 current_mode = 0;
1557         u32 mode = 0;
1558         int i;
1559
1560         /* as per the documentation GPIO 22-29 are the LED
1561          * GPIO pins named LED0..LED7
1562          */
1563         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1564                 u32 gpio_val = i40e_led_is_mine(hw, i);
1565
1566                 if (!gpio_val)
1567                         continue;
1568
1569                 /* ignore gpio LED src mode entries related to the activity
1570                  *  LEDs
1571                  */
1572                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1573                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1574                 switch (current_mode) {
1575                 case I40E_COMBINED_ACTIVITY:
1576                 case I40E_FILTER_ACTIVITY:
1577                 case I40E_MAC_ACTIVITY:
1578                         continue;
1579                 default:
1580                         break;
1581                 }
1582
1583                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1584                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1585                 break;
1586         }
1587
1588         return mode;
1589 }
1590
1591 /**
1592  * i40e_led_set - set new on/off mode
1593  * @hw: pointer to the hw struct
1594  * @mode: 0=off, 0xf=on (else see manual for mode details)
1595  * @blink: true if the LED should blink when on, false if steady
1596  *
1597  * if this function is used to turn on the blink it should
1598  * be used to disable the blink when restoring the original state.
1599  **/
1600 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1601 {
1602         u32 current_mode = 0;
1603         int i;
1604
1605         if (mode & 0xfffffff0)
1606                 DEBUGOUT1("invalid mode passed in %X\n", mode);
1607
1608         /* as per the documentation GPIO 22-29 are the LED
1609          * GPIO pins named LED0..LED7
1610          */
1611         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1612                 u32 gpio_val = i40e_led_is_mine(hw, i);
1613
1614                 if (!gpio_val)
1615                         continue;
1616
1617                 /* ignore gpio LED src mode entries related to the activity
1618                  * LEDs
1619                  */
1620                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1621                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1622                 switch (current_mode) {
1623                 case I40E_COMBINED_ACTIVITY:
1624                 case I40E_FILTER_ACTIVITY:
1625                 case I40E_MAC_ACTIVITY:
1626                         continue;
1627                 default:
1628                         break;
1629                 }
1630
1631                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1632                 /* this & is a bit of paranoia, but serves as a range check */
1633                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1634                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1635
1636                 if (mode == I40E_LINK_ACTIVITY)
1637                         blink = false;
1638
1639                 if (blink)
1640                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1641                 else
1642                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1643
1644                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1645                 break;
1646         }
1647 }
1648
1649 /* Admin command wrappers */
1650
1651 /**
1652  * i40e_aq_get_phy_capabilities
1653  * @hw: pointer to the hw struct
1654  * @abilities: structure for PHY capabilities to be filled
1655  * @qualified_modules: report Qualified Modules
1656  * @report_init: report init capabilities (active are default)
1657  * @cmd_details: pointer to command details structure or NULL
1658  *
1659  * Returns the various PHY abilities supported on the Port.
1660  **/
1661 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1662                         bool qualified_modules, bool report_init,
1663                         struct i40e_aq_get_phy_abilities_resp *abilities,
1664                         struct i40e_asq_cmd_details *cmd_details)
1665 {
1666         struct i40e_aq_desc desc;
1667         enum i40e_status_code status;
1668         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1669
1670         if (!abilities)
1671                 return I40E_ERR_PARAM;
1672
1673         i40e_fill_default_direct_cmd_desc(&desc,
1674                                           i40e_aqc_opc_get_phy_abilities);
1675
1676         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1677         if (abilities_size > I40E_AQ_LARGE_BUF)
1678                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1679
1680         if (qualified_modules)
1681                 desc.params.external.param0 |=
1682                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1683
1684         if (report_init)
1685                 desc.params.external.param0 |=
1686                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1687
1688         status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1689                                     cmd_details);
1690
1691         if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1692                 status = I40E_ERR_UNKNOWN_PHY;
1693
1694         if (report_init) {
1695                 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1696                 hw->phy.phy_types |= ((u64)abilities->phy_type_ext << 32);
1697         }
1698
1699         return status;
1700 }
1701
1702 /**
1703  * i40e_aq_set_phy_config
1704  * @hw: pointer to the hw struct
1705  * @config: structure with PHY configuration to be set
1706  * @cmd_details: pointer to command details structure or NULL
1707  *
1708  * Set the various PHY configuration parameters
1709  * supported on the Port.One or more of the Set PHY config parameters may be
1710  * ignored in an MFP mode as the PF may not have the privilege to set some
1711  * of the PHY Config parameters. This status will be indicated by the
1712  * command response.
1713  **/
1714 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1715                                 struct i40e_aq_set_phy_config *config,
1716                                 struct i40e_asq_cmd_details *cmd_details)
1717 {
1718         struct i40e_aq_desc desc;
1719         struct i40e_aq_set_phy_config *cmd =
1720                 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1721         enum i40e_status_code status;
1722
1723         if (!config)
1724                 return I40E_ERR_PARAM;
1725
1726         i40e_fill_default_direct_cmd_desc(&desc,
1727                                           i40e_aqc_opc_set_phy_config);
1728
1729         *cmd = *config;
1730
1731         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1732
1733         return status;
1734 }
1735
1736 /**
1737  * i40e_set_fc
1738  * @hw: pointer to the hw struct
1739  *
1740  * Set the requested flow control mode using set_phy_config.
1741  **/
1742 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1743                                   bool atomic_restart)
1744 {
1745         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1746         struct i40e_aq_get_phy_abilities_resp abilities;
1747         struct i40e_aq_set_phy_config config;
1748         enum i40e_status_code status;
1749         u8 pause_mask = 0x0;
1750
1751         *aq_failures = 0x0;
1752
1753         switch (fc_mode) {
1754         case I40E_FC_FULL:
1755                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1756                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1757                 break;
1758         case I40E_FC_RX_PAUSE:
1759                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1760                 break;
1761         case I40E_FC_TX_PAUSE:
1762                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1763                 break;
1764         default:
1765                 break;
1766         }
1767
1768         /* Get the current phy config */
1769         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1770                                               NULL);
1771         if (status) {
1772                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1773                 return status;
1774         }
1775
1776         memset(&config, 0, sizeof(config));
1777         /* clear the old pause settings */
1778         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1779                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1780         /* set the new abilities */
1781         config.abilities |= pause_mask;
1782         /* If the abilities have changed, then set the new config */
1783         if (config.abilities != abilities.abilities) {
1784                 /* Auto restart link so settings take effect */
1785                 if (atomic_restart)
1786                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1787                 /* Copy over all the old settings */
1788                 config.phy_type = abilities.phy_type;
1789                 config.phy_type_ext = abilities.phy_type_ext;
1790                 config.link_speed = abilities.link_speed;
1791                 config.eee_capability = abilities.eee_capability;
1792                 config.eeer = abilities.eeer_val;
1793                 config.low_power_ctrl = abilities.d3_lpan;
1794                 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1795                                     I40E_AQ_PHY_FEC_CONFIG_MASK;
1796                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1797
1798                 if (status)
1799                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1800         }
1801         /* Update the link info */
1802         status = i40e_update_link_info(hw);
1803         if (status) {
1804                 /* Wait a little bit (on 40G cards it sometimes takes a really
1805                  * long time for link to come back from the atomic reset)
1806                  * and try once more
1807                  */
1808                 i40e_msec_delay(1000);
1809                 status = i40e_update_link_info(hw);
1810         }
1811         if (status)
1812                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1813
1814         return status;
1815 }
1816
1817 /**
1818  * i40e_aq_set_mac_config
1819  * @hw: pointer to the hw struct
1820  * @max_frame_size: Maximum Frame Size to be supported by the port
1821  * @crc_en: Tell HW to append a CRC to outgoing frames
1822  * @pacing: Pacing configurations
1823  * @cmd_details: pointer to command details structure or NULL
1824  *
1825  * Configure MAC settings for frame size, jumbo frame support and the
1826  * addition of a CRC by the hardware.
1827  **/
1828 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1829                                 u16 max_frame_size,
1830                                 bool crc_en, u16 pacing,
1831                                 struct i40e_asq_cmd_details *cmd_details)
1832 {
1833         struct i40e_aq_desc desc;
1834         struct i40e_aq_set_mac_config *cmd =
1835                 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1836         enum i40e_status_code status;
1837
1838         if (max_frame_size == 0)
1839                 return I40E_ERR_PARAM;
1840
1841         i40e_fill_default_direct_cmd_desc(&desc,
1842                                           i40e_aqc_opc_set_mac_config);
1843
1844         cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1845         cmd->params = ((u8)pacing & 0x0F) << 3;
1846         if (crc_en)
1847                 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1848
1849         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1850
1851         return status;
1852 }
1853
1854 /**
1855  * i40e_aq_clear_pxe_mode
1856  * @hw: pointer to the hw struct
1857  * @cmd_details: pointer to command details structure or NULL
1858  *
1859  * Tell the firmware that the driver is taking over from PXE
1860  **/
1861 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1862                         struct i40e_asq_cmd_details *cmd_details)
1863 {
1864         enum i40e_status_code status;
1865         struct i40e_aq_desc desc;
1866         struct i40e_aqc_clear_pxe *cmd =
1867                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1868
1869         i40e_fill_default_direct_cmd_desc(&desc,
1870                                           i40e_aqc_opc_clear_pxe_mode);
1871
1872         cmd->rx_cnt = 0x2;
1873
1874         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1875
1876         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1877
1878         return status;
1879 }
1880
1881 /**
1882  * i40e_aq_set_link_restart_an
1883  * @hw: pointer to the hw struct
1884  * @enable_link: if true: enable link, if false: disable link
1885  * @cmd_details: pointer to command details structure or NULL
1886  *
1887  * Sets up the link and restarts the Auto-Negotiation over the link.
1888  **/
1889 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1890                 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1891 {
1892         struct i40e_aq_desc desc;
1893         struct i40e_aqc_set_link_restart_an *cmd =
1894                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1895         enum i40e_status_code status;
1896
1897         i40e_fill_default_direct_cmd_desc(&desc,
1898                                           i40e_aqc_opc_set_link_restart_an);
1899
1900         cmd->command = I40E_AQ_PHY_RESTART_AN;
1901         if (enable_link)
1902                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1903         else
1904                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1905
1906         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1907
1908         return status;
1909 }
1910
1911 /**
1912  * i40e_aq_get_link_info
1913  * @hw: pointer to the hw struct
1914  * @enable_lse: enable/disable LinkStatusEvent reporting
1915  * @link: pointer to link status structure - optional
1916  * @cmd_details: pointer to command details structure or NULL
1917  *
1918  * Returns the link status of the adapter.
1919  **/
1920 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1921                                 bool enable_lse, struct i40e_link_status *link,
1922                                 struct i40e_asq_cmd_details *cmd_details)
1923 {
1924         struct i40e_aq_desc desc;
1925         struct i40e_aqc_get_link_status *resp =
1926                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1927         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1928         enum i40e_status_code status;
1929         bool tx_pause, rx_pause;
1930         u16 command_flags;
1931
1932         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1933
1934         if (enable_lse)
1935                 command_flags = I40E_AQ_LSE_ENABLE;
1936         else
1937                 command_flags = I40E_AQ_LSE_DISABLE;
1938         resp->command_flags = CPU_TO_LE16(command_flags);
1939
1940         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1941
1942         if (status != I40E_SUCCESS)
1943                 goto aq_get_link_info_exit;
1944
1945         /* save off old link status information */
1946         i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1947                     sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1948
1949         /* update link status */
1950         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1951         hw->phy.media_type = i40e_get_media_type(hw);
1952         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1953         hw_link_info->link_info = resp->link_info;
1954         hw_link_info->an_info = resp->an_info;
1955         hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
1956                                                  I40E_AQ_CONFIG_FEC_RS_ENA);
1957         hw_link_info->ext_info = resp->ext_info;
1958         hw_link_info->loopback = resp->loopback;
1959         hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1960         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1961
1962         /* update fc info */
1963         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1964         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1965         if (tx_pause & rx_pause)
1966                 hw->fc.current_mode = I40E_FC_FULL;
1967         else if (tx_pause)
1968                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1969         else if (rx_pause)
1970                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1971         else
1972                 hw->fc.current_mode = I40E_FC_NONE;
1973
1974         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1975                 hw_link_info->crc_enable = true;
1976         else
1977                 hw_link_info->crc_enable = false;
1978
1979         if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
1980                 hw_link_info->lse_enable = true;
1981         else
1982                 hw_link_info->lse_enable = false;
1983
1984         if ((hw->mac.type == I40E_MAC_XL710) &&
1985             (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1986              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1987                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1988
1989         /* save link status information */
1990         if (link)
1991                 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1992                             I40E_NONDMA_TO_NONDMA);
1993
1994         /* flag cleared so helper functions don't call AQ again */
1995         hw->phy.get_link_info = false;
1996
1997 aq_get_link_info_exit:
1998         return status;
1999 }
2000
2001 /**
2002  * i40e_aq_set_phy_int_mask
2003  * @hw: pointer to the hw struct
2004  * @mask: interrupt mask to be set
2005  * @cmd_details: pointer to command details structure or NULL
2006  *
2007  * Set link interrupt mask.
2008  **/
2009 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2010                                 u16 mask,
2011                                 struct i40e_asq_cmd_details *cmd_details)
2012 {
2013         struct i40e_aq_desc desc;
2014         struct i40e_aqc_set_phy_int_mask *cmd =
2015                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2016         enum i40e_status_code status;
2017
2018         i40e_fill_default_direct_cmd_desc(&desc,
2019                                           i40e_aqc_opc_set_phy_int_mask);
2020
2021         cmd->event_mask = CPU_TO_LE16(mask);
2022
2023         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2024
2025         return status;
2026 }
2027
2028 /**
2029  * i40e_aq_get_local_advt_reg
2030  * @hw: pointer to the hw struct
2031  * @advt_reg: local AN advertisement register value
2032  * @cmd_details: pointer to command details structure or NULL
2033  *
2034  * Get the Local AN advertisement register value.
2035  **/
2036 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2037                                 u64 *advt_reg,
2038                                 struct i40e_asq_cmd_details *cmd_details)
2039 {
2040         struct i40e_aq_desc desc;
2041         struct i40e_aqc_an_advt_reg *resp =
2042                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2043         enum i40e_status_code status;
2044
2045         i40e_fill_default_direct_cmd_desc(&desc,
2046                                           i40e_aqc_opc_get_local_advt_reg);
2047
2048         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2049
2050         if (status != I40E_SUCCESS)
2051                 goto aq_get_local_advt_reg_exit;
2052
2053         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2054         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2055
2056 aq_get_local_advt_reg_exit:
2057         return status;
2058 }
2059
2060 /**
2061  * i40e_aq_set_local_advt_reg
2062  * @hw: pointer to the hw struct
2063  * @advt_reg: local AN advertisement register value
2064  * @cmd_details: pointer to command details structure or NULL
2065  *
2066  * Get the Local AN advertisement register value.
2067  **/
2068 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2069                                 u64 advt_reg,
2070                                 struct i40e_asq_cmd_details *cmd_details)
2071 {
2072         struct i40e_aq_desc desc;
2073         struct i40e_aqc_an_advt_reg *cmd =
2074                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2075         enum i40e_status_code status;
2076
2077         i40e_fill_default_direct_cmd_desc(&desc,
2078                                           i40e_aqc_opc_get_local_advt_reg);
2079
2080         cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2081         cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2082
2083         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2084
2085         return status;
2086 }
2087
2088 /**
2089  * i40e_aq_get_partner_advt
2090  * @hw: pointer to the hw struct
2091  * @advt_reg: AN partner advertisement register value
2092  * @cmd_details: pointer to command details structure or NULL
2093  *
2094  * Get the link partner AN advertisement register value.
2095  **/
2096 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2097                                 u64 *advt_reg,
2098                                 struct i40e_asq_cmd_details *cmd_details)
2099 {
2100         struct i40e_aq_desc desc;
2101         struct i40e_aqc_an_advt_reg *resp =
2102                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2103         enum i40e_status_code status;
2104
2105         i40e_fill_default_direct_cmd_desc(&desc,
2106                                           i40e_aqc_opc_get_partner_advt);
2107
2108         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2109
2110         if (status != I40E_SUCCESS)
2111                 goto aq_get_partner_advt_exit;
2112
2113         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2114         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2115
2116 aq_get_partner_advt_exit:
2117         return status;
2118 }
2119
2120 /**
2121  * i40e_aq_set_lb_modes
2122  * @hw: pointer to the hw struct
2123  * @lb_modes: loopback mode to be set
2124  * @cmd_details: pointer to command details structure or NULL
2125  *
2126  * Sets loopback modes.
2127  **/
2128 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2129                                 u16 lb_modes,
2130                                 struct i40e_asq_cmd_details *cmd_details)
2131 {
2132         struct i40e_aq_desc desc;
2133         struct i40e_aqc_set_lb_mode *cmd =
2134                 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2135         enum i40e_status_code status;
2136
2137         i40e_fill_default_direct_cmd_desc(&desc,
2138                                           i40e_aqc_opc_set_lb_modes);
2139
2140         cmd->lb_mode = CPU_TO_LE16(lb_modes);
2141
2142         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2143
2144         return status;
2145 }
2146
2147 /**
2148  * i40e_aq_set_phy_debug
2149  * @hw: pointer to the hw struct
2150  * @cmd_flags: debug command flags
2151  * @cmd_details: pointer to command details structure or NULL
2152  *
2153  * Reset the external PHY.
2154  **/
2155 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2156                                 struct i40e_asq_cmd_details *cmd_details)
2157 {
2158         struct i40e_aq_desc desc;
2159         struct i40e_aqc_set_phy_debug *cmd =
2160                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2161         enum i40e_status_code status;
2162
2163         i40e_fill_default_direct_cmd_desc(&desc,
2164                                           i40e_aqc_opc_set_phy_debug);
2165
2166         cmd->command_flags = cmd_flags;
2167
2168         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2169
2170         return status;
2171 }
2172
2173 /**
2174  * i40e_aq_add_vsi
2175  * @hw: pointer to the hw struct
2176  * @vsi_ctx: pointer to a vsi context struct
2177  * @cmd_details: pointer to command details structure or NULL
2178  *
2179  * Add a VSI context to the hardware.
2180 **/
2181 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2182                                 struct i40e_vsi_context *vsi_ctx,
2183                                 struct i40e_asq_cmd_details *cmd_details)
2184 {
2185         struct i40e_aq_desc desc;
2186         struct i40e_aqc_add_get_update_vsi *cmd =
2187                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2188         struct i40e_aqc_add_get_update_vsi_completion *resp =
2189                 (struct i40e_aqc_add_get_update_vsi_completion *)
2190                 &desc.params.raw;
2191         enum i40e_status_code status;
2192
2193         i40e_fill_default_direct_cmd_desc(&desc,
2194                                           i40e_aqc_opc_add_vsi);
2195
2196         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2197         cmd->connection_type = vsi_ctx->connection_type;
2198         cmd->vf_id = vsi_ctx->vf_num;
2199         cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2200
2201         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2202
2203         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2204                                     sizeof(vsi_ctx->info), cmd_details);
2205
2206         if (status != I40E_SUCCESS)
2207                 goto aq_add_vsi_exit;
2208
2209         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2210         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2211         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2212         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2213
2214 aq_add_vsi_exit:
2215         return status;
2216 }
2217
2218 /**
2219  * i40e_aq_set_default_vsi
2220  * @hw: pointer to the hw struct
2221  * @seid: vsi number
2222  * @cmd_details: pointer to command details structure or NULL
2223  **/
2224 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2225                                 u16 seid,
2226                                 struct i40e_asq_cmd_details *cmd_details)
2227 {
2228         struct i40e_aq_desc desc;
2229         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2230                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2231                 &desc.params.raw;
2232         enum i40e_status_code status;
2233
2234         i40e_fill_default_direct_cmd_desc(&desc,
2235                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2236
2237         cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2238         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2239         cmd->seid = CPU_TO_LE16(seid);
2240
2241         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2242
2243         return status;
2244 }
2245
2246 /**
2247  * i40e_aq_clear_default_vsi
2248  * @hw: pointer to the hw struct
2249  * @seid: vsi number
2250  * @cmd_details: pointer to command details structure or NULL
2251  **/
2252 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2253                                 u16 seid,
2254                                 struct i40e_asq_cmd_details *cmd_details)
2255 {
2256         struct i40e_aq_desc desc;
2257         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2258                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2259                 &desc.params.raw;
2260         enum i40e_status_code status;
2261
2262         i40e_fill_default_direct_cmd_desc(&desc,
2263                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2264
2265         cmd->promiscuous_flags = CPU_TO_LE16(0);
2266         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2267         cmd->seid = CPU_TO_LE16(seid);
2268
2269         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2270
2271         return status;
2272 }
2273
2274 /**
2275  * i40e_aq_set_vsi_unicast_promiscuous
2276  * @hw: pointer to the hw struct
2277  * @seid: vsi number
2278  * @set: set unicast promiscuous enable/disable
2279  * @cmd_details: pointer to command details structure or NULL
2280  * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2281  **/
2282 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2283                                 u16 seid, bool set,
2284                                 struct i40e_asq_cmd_details *cmd_details,
2285                                 bool rx_only_promisc)
2286 {
2287         struct i40e_aq_desc desc;
2288         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2289                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2290         enum i40e_status_code status;
2291         u16 flags = 0;
2292
2293         i40e_fill_default_direct_cmd_desc(&desc,
2294                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2295
2296         if (set) {
2297                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2298                 if (rx_only_promisc &&
2299                     (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2300                      (hw->aq.api_maj_ver > 1)))
2301                         flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2302         }
2303
2304         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2305
2306         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2307         if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2308              (hw->aq.api_maj_ver > 1))
2309                 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2310
2311         cmd->seid = CPU_TO_LE16(seid);
2312         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2313
2314         return status;
2315 }
2316
2317 /**
2318  * i40e_aq_set_vsi_multicast_promiscuous
2319  * @hw: pointer to the hw struct
2320  * @seid: vsi number
2321  * @set: set multicast promiscuous enable/disable
2322  * @cmd_details: pointer to command details structure or NULL
2323  **/
2324 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2325                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2326 {
2327         struct i40e_aq_desc desc;
2328         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2329                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2330         enum i40e_status_code status;
2331         u16 flags = 0;
2332
2333         i40e_fill_default_direct_cmd_desc(&desc,
2334                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2335
2336         if (set)
2337                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2338
2339         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2340
2341         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2342
2343         cmd->seid = CPU_TO_LE16(seid);
2344         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2345
2346         return status;
2347 }
2348
2349 /**
2350 * i40e_aq_set_vsi_full_promiscuous
2351 * @hw: pointer to the hw struct
2352 * @seid: VSI number
2353 * @set: set promiscuous enable/disable
2354 * @cmd_details: pointer to command details structure or NULL
2355 **/
2356 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw,
2357                                 u16 seid, bool set,
2358                                 struct i40e_asq_cmd_details *cmd_details)
2359 {
2360         struct i40e_aq_desc desc;
2361         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2362                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2363         enum i40e_status_code status;
2364         u16 flags = 0;
2365
2366         i40e_fill_default_direct_cmd_desc(&desc,
2367                 i40e_aqc_opc_set_vsi_promiscuous_modes);
2368
2369         if (set)
2370                 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2371                         I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2372                         I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2373
2374         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2375
2376         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2377                                        I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2378                                        I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2379
2380         cmd->seid = CPU_TO_LE16(seid);
2381         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2382
2383         return status;
2384 }
2385
2386 /**
2387  * i40e_aq_set_vsi_mc_promisc_on_vlan
2388  * @hw: pointer to the hw struct
2389  * @seid: vsi number
2390  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2391  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2392  * @cmd_details: pointer to command details structure or NULL
2393  **/
2394 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2395                                 u16 seid, bool enable, u16 vid,
2396                                 struct i40e_asq_cmd_details *cmd_details)
2397 {
2398         struct i40e_aq_desc desc;
2399         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2400                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2401         enum i40e_status_code status;
2402         u16 flags = 0;
2403
2404         i40e_fill_default_direct_cmd_desc(&desc,
2405                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2406
2407         if (enable)
2408                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2409
2410         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2411         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2412         cmd->seid = CPU_TO_LE16(seid);
2413         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2414
2415         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2416
2417         return status;
2418 }
2419
2420 /**
2421  * i40e_aq_set_vsi_uc_promisc_on_vlan
2422  * @hw: pointer to the hw struct
2423  * @seid: vsi number
2424  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2425  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2426  * @cmd_details: pointer to command details structure or NULL
2427  **/
2428 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2429                                 u16 seid, bool enable, u16 vid,
2430                                 struct i40e_asq_cmd_details *cmd_details)
2431 {
2432         struct i40e_aq_desc desc;
2433         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2434                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2435         enum i40e_status_code status;
2436         u16 flags = 0;
2437
2438         i40e_fill_default_direct_cmd_desc(&desc,
2439                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2440
2441         if (enable)
2442                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2443
2444         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2445         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2446         cmd->seid = CPU_TO_LE16(seid);
2447         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2448
2449         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2450
2451         return status;
2452 }
2453
2454 /**
2455  * i40e_aq_set_vsi_bc_promisc_on_vlan
2456  * @hw: pointer to the hw struct
2457  * @seid: vsi number
2458  * @enable: set broadcast promiscuous enable/disable for a given VLAN
2459  * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2460  * @cmd_details: pointer to command details structure or NULL
2461  **/
2462 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2463                                 u16 seid, bool enable, u16 vid,
2464                                 struct i40e_asq_cmd_details *cmd_details)
2465 {
2466         struct i40e_aq_desc desc;
2467         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2468                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2469         enum i40e_status_code status;
2470         u16 flags = 0;
2471
2472         i40e_fill_default_direct_cmd_desc(&desc,
2473                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2474
2475         if (enable)
2476                 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2477
2478         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2479         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2480         cmd->seid = CPU_TO_LE16(seid);
2481         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2482
2483         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2484
2485         return status;
2486 }
2487
2488 /**
2489  * i40e_aq_set_vsi_broadcast
2490  * @hw: pointer to the hw struct
2491  * @seid: vsi number
2492  * @set_filter: true to set filter, false to clear filter
2493  * @cmd_details: pointer to command details structure or NULL
2494  *
2495  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2496  **/
2497 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2498                                 u16 seid, bool set_filter,
2499                                 struct i40e_asq_cmd_details *cmd_details)
2500 {
2501         struct i40e_aq_desc desc;
2502         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2503                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2504         enum i40e_status_code status;
2505
2506         i40e_fill_default_direct_cmd_desc(&desc,
2507                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2508
2509         if (set_filter)
2510                 cmd->promiscuous_flags
2511                             |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2512         else
2513                 cmd->promiscuous_flags
2514                             &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2515
2516         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2517         cmd->seid = CPU_TO_LE16(seid);
2518         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2519
2520         return status;
2521 }
2522
2523 /**
2524  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2525  * @hw: pointer to the hw struct
2526  * @seid: vsi number
2527  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2528  * @cmd_details: pointer to command details structure or NULL
2529  **/
2530 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2531                                 u16 seid, bool enable,
2532                                 struct i40e_asq_cmd_details *cmd_details)
2533 {
2534         struct i40e_aq_desc desc;
2535         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2536                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2537         enum i40e_status_code status;
2538         u16 flags = 0;
2539
2540         i40e_fill_default_direct_cmd_desc(&desc,
2541                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2542         if (enable)
2543                 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2544
2545         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2546         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2547         cmd->seid = CPU_TO_LE16(seid);
2548
2549         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2550
2551         return status;
2552 }
2553
2554 /**
2555  * i40e_get_vsi_params - get VSI configuration info
2556  * @hw: pointer to the hw struct
2557  * @vsi_ctx: pointer to a vsi context struct
2558  * @cmd_details: pointer to command details structure or NULL
2559  **/
2560 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2561                                 struct i40e_vsi_context *vsi_ctx,
2562                                 struct i40e_asq_cmd_details *cmd_details)
2563 {
2564         struct i40e_aq_desc desc;
2565         struct i40e_aqc_add_get_update_vsi *cmd =
2566                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2567         struct i40e_aqc_add_get_update_vsi_completion *resp =
2568                 (struct i40e_aqc_add_get_update_vsi_completion *)
2569                 &desc.params.raw;
2570         enum i40e_status_code status;
2571
2572         UNREFERENCED_1PARAMETER(cmd_details);
2573         i40e_fill_default_direct_cmd_desc(&desc,
2574                                           i40e_aqc_opc_get_vsi_parameters);
2575
2576         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2577
2578         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2579
2580         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2581                                     sizeof(vsi_ctx->info), NULL);
2582
2583         if (status != I40E_SUCCESS)
2584                 goto aq_get_vsi_params_exit;
2585
2586         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2587         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2588         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2589         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2590
2591 aq_get_vsi_params_exit:
2592         return status;
2593 }
2594
2595 /**
2596  * i40e_aq_update_vsi_params
2597  * @hw: pointer to the hw struct
2598  * @vsi_ctx: pointer to a vsi context struct
2599  * @cmd_details: pointer to command details structure or NULL
2600  *
2601  * Update a VSI context.
2602  **/
2603 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2604                                 struct i40e_vsi_context *vsi_ctx,
2605                                 struct i40e_asq_cmd_details *cmd_details)
2606 {
2607         struct i40e_aq_desc desc;
2608         struct i40e_aqc_add_get_update_vsi *cmd =
2609                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2610         struct i40e_aqc_add_get_update_vsi_completion *resp =
2611                 (struct i40e_aqc_add_get_update_vsi_completion *)
2612                 &desc.params.raw;
2613         enum i40e_status_code status;
2614
2615         i40e_fill_default_direct_cmd_desc(&desc,
2616                                           i40e_aqc_opc_update_vsi_parameters);
2617         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2618
2619         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2620
2621         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2622                                     sizeof(vsi_ctx->info), cmd_details);
2623
2624         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2625         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2626
2627         return status;
2628 }
2629
2630 /**
2631  * i40e_aq_get_switch_config
2632  * @hw: pointer to the hardware structure
2633  * @buf: pointer to the result buffer
2634  * @buf_size: length of input buffer
2635  * @start_seid: seid to start for the report, 0 == beginning
2636  * @cmd_details: pointer to command details structure or NULL
2637  *
2638  * Fill the buf with switch configuration returned from AdminQ command
2639  **/
2640 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2641                                 struct i40e_aqc_get_switch_config_resp *buf,
2642                                 u16 buf_size, u16 *start_seid,
2643                                 struct i40e_asq_cmd_details *cmd_details)
2644 {
2645         struct i40e_aq_desc desc;
2646         struct i40e_aqc_switch_seid *scfg =
2647                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2648         enum i40e_status_code status;
2649
2650         i40e_fill_default_direct_cmd_desc(&desc,
2651                                           i40e_aqc_opc_get_switch_config);
2652         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2653         if (buf_size > I40E_AQ_LARGE_BUF)
2654                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2655         scfg->seid = CPU_TO_LE16(*start_seid);
2656
2657         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2658         *start_seid = LE16_TO_CPU(scfg->seid);
2659
2660         return status;
2661 }
2662
2663 /**
2664  * i40e_aq_set_switch_config
2665  * @hw: pointer to the hardware structure
2666  * @flags: bit flag values to set
2667  * @valid_flags: which bit flags to set
2668  * @cmd_details: pointer to command details structure or NULL
2669  *
2670  * Set switch configuration bits
2671  **/
2672 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2673                                 u16 flags, u16 valid_flags,
2674                                 struct i40e_asq_cmd_details *cmd_details)
2675 {
2676         struct i40e_aq_desc desc;
2677         struct i40e_aqc_set_switch_config *scfg =
2678                 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2679         enum i40e_status_code status;
2680
2681         i40e_fill_default_direct_cmd_desc(&desc,
2682                                           i40e_aqc_opc_set_switch_config);
2683         scfg->flags = CPU_TO_LE16(flags);
2684         scfg->valid_flags = CPU_TO_LE16(valid_flags);
2685
2686         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2687
2688         return status;
2689 }
2690
2691 /**
2692  * i40e_aq_get_firmware_version
2693  * @hw: pointer to the hw struct
2694  * @fw_major_version: firmware major version
2695  * @fw_minor_version: firmware minor version
2696  * @fw_build: firmware build number
2697  * @api_major_version: major queue version
2698  * @api_minor_version: minor queue version
2699  * @cmd_details: pointer to command details structure or NULL
2700  *
2701  * Get the firmware version from the admin queue commands
2702  **/
2703 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2704                                 u16 *fw_major_version, u16 *fw_minor_version,
2705                                 u32 *fw_build,
2706                                 u16 *api_major_version, u16 *api_minor_version,
2707                                 struct i40e_asq_cmd_details *cmd_details)
2708 {
2709         struct i40e_aq_desc desc;
2710         struct i40e_aqc_get_version *resp =
2711                 (struct i40e_aqc_get_version *)&desc.params.raw;
2712         enum i40e_status_code status;
2713
2714         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2715
2716         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2717
2718         if (status == I40E_SUCCESS) {
2719                 if (fw_major_version != NULL)
2720                         *fw_major_version = LE16_TO_CPU(resp->fw_major);
2721                 if (fw_minor_version != NULL)
2722                         *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2723                 if (fw_build != NULL)
2724                         *fw_build = LE32_TO_CPU(resp->fw_build);
2725                 if (api_major_version != NULL)
2726                         *api_major_version = LE16_TO_CPU(resp->api_major);
2727                 if (api_minor_version != NULL)
2728                         *api_minor_version = LE16_TO_CPU(resp->api_minor);
2729
2730                 /* A workaround to fix the API version in SW */
2731                 if (api_major_version && api_minor_version &&
2732                     fw_major_version && fw_minor_version &&
2733                     ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2734                     (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2735                      (*fw_major_version > 4)))
2736                         *api_minor_version = 2;
2737         }
2738
2739         return status;
2740 }
2741
2742 /**
2743  * i40e_aq_send_driver_version
2744  * @hw: pointer to the hw struct
2745  * @dv: driver's major, minor version
2746  * @cmd_details: pointer to command details structure or NULL
2747  *
2748  * Send the driver version to the firmware
2749  **/
2750 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2751                                 struct i40e_driver_version *dv,
2752                                 struct i40e_asq_cmd_details *cmd_details)
2753 {
2754         struct i40e_aq_desc desc;
2755         struct i40e_aqc_driver_version *cmd =
2756                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2757         enum i40e_status_code status;
2758         u16 len;
2759
2760         if (dv == NULL)
2761                 return I40E_ERR_PARAM;
2762
2763         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2764
2765         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2766         cmd->driver_major_ver = dv->major_version;
2767         cmd->driver_minor_ver = dv->minor_version;
2768         cmd->driver_build_ver = dv->build_version;
2769         cmd->driver_subbuild_ver = dv->subbuild_version;
2770
2771         len = 0;
2772         while (len < sizeof(dv->driver_string) &&
2773                (dv->driver_string[len] < 0x80) &&
2774                dv->driver_string[len])
2775                 len++;
2776         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2777                                        len, cmd_details);
2778
2779         return status;
2780 }
2781
2782 /**
2783  * i40e_get_link_status - get status of the HW network link
2784  * @hw: pointer to the hw struct
2785  * @link_up: pointer to bool (true/false = linkup/linkdown)
2786  *
2787  * Variable link_up true if link is up, false if link is down.
2788  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2789  *
2790  * Side effect: LinkStatusEvent reporting becomes enabled
2791  **/
2792 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2793 {
2794         enum i40e_status_code status = I40E_SUCCESS;
2795
2796         if (hw->phy.get_link_info) {
2797                 status = i40e_update_link_info(hw);
2798
2799                 if (status != I40E_SUCCESS)
2800                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2801                                    status);
2802         }
2803
2804         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2805
2806         return status;
2807 }
2808
2809 /**
2810  * i40e_updatelink_status - update status of the HW network link
2811  * @hw: pointer to the hw struct
2812  **/
2813 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2814 {
2815         struct i40e_aq_get_phy_abilities_resp abilities;
2816         enum i40e_status_code status = I40E_SUCCESS;
2817
2818         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2819         if (status)
2820                 return status;
2821
2822         /* extra checking needed to ensure link info to user is timely */
2823         if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2824             ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2825              !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2826                 status = i40e_aq_get_phy_capabilities(hw, false, false,
2827                                                       &abilities, NULL);
2828                 if (status)
2829                         return status;
2830
2831                 hw->phy.link_info.req_fec_info =
2832                         abilities.fec_cfg_curr_mod_ext_info &
2833                         (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS);
2834
2835                 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2836                         sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2837         }
2838         return status;
2839 }
2840
2841
2842 /**
2843  * i40e_get_link_speed
2844  * @hw: pointer to the hw struct
2845  *
2846  * Returns the link speed of the adapter.
2847  **/
2848 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2849 {
2850         enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2851         enum i40e_status_code status = I40E_SUCCESS;
2852
2853         if (hw->phy.get_link_info) {
2854                 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2855
2856                 if (status != I40E_SUCCESS)
2857                         goto i40e_link_speed_exit;
2858         }
2859
2860         speed = hw->phy.link_info.link_speed;
2861
2862 i40e_link_speed_exit:
2863         return speed;
2864 }
2865
2866 /**
2867  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2868  * @hw: pointer to the hw struct
2869  * @uplink_seid: the MAC or other gizmo SEID
2870  * @downlink_seid: the VSI SEID
2871  * @enabled_tc: bitmap of TCs to be enabled
2872  * @default_port: true for default port VSI, false for control port
2873  * @veb_seid: pointer to where to put the resulting VEB SEID
2874  * @enable_stats: true to turn on VEB stats
2875  * @cmd_details: pointer to command details structure or NULL
2876  *
2877  * This asks the FW to add a VEB between the uplink and downlink
2878  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2879  **/
2880 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2881                                 u16 downlink_seid, u8 enabled_tc,
2882                                 bool default_port, u16 *veb_seid,
2883                                 bool enable_stats,
2884                                 struct i40e_asq_cmd_details *cmd_details)
2885 {
2886         struct i40e_aq_desc desc;
2887         struct i40e_aqc_add_veb *cmd =
2888                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2889         struct i40e_aqc_add_veb_completion *resp =
2890                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2891         enum i40e_status_code status;
2892         u16 veb_flags = 0;
2893
2894         /* SEIDs need to either both be set or both be 0 for floating VEB */
2895         if (!!uplink_seid != !!downlink_seid)
2896                 return I40E_ERR_PARAM;
2897
2898         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2899
2900         cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2901         cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2902         cmd->enable_tcs = enabled_tc;
2903         if (!uplink_seid)
2904                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2905         if (default_port)
2906                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2907         else
2908                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2909
2910         /* reverse logic here: set the bitflag to disable the stats */
2911         if (!enable_stats)
2912                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2913
2914         cmd->veb_flags = CPU_TO_LE16(veb_flags);
2915
2916         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2917
2918         if (!status && veb_seid)
2919                 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2920
2921         return status;
2922 }
2923
2924 /**
2925  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2926  * @hw: pointer to the hw struct
2927  * @veb_seid: the SEID of the VEB to query
2928  * @switch_id: the uplink switch id
2929  * @floating: set to true if the VEB is floating
2930  * @statistic_index: index of the stats counter block for this VEB
2931  * @vebs_used: number of VEB's used by function
2932  * @vebs_free: total VEB's not reserved by any function
2933  * @cmd_details: pointer to command details structure or NULL
2934  *
2935  * This retrieves the parameters for a particular VEB, specified by
2936  * uplink_seid, and returns them to the caller.
2937  **/
2938 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2939                                 u16 veb_seid, u16 *switch_id,
2940                                 bool *floating, u16 *statistic_index,
2941                                 u16 *vebs_used, u16 *vebs_free,
2942                                 struct i40e_asq_cmd_details *cmd_details)
2943 {
2944         struct i40e_aq_desc desc;
2945         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2946                 (struct i40e_aqc_get_veb_parameters_completion *)
2947                 &desc.params.raw;
2948         enum i40e_status_code status;
2949
2950         if (veb_seid == 0)
2951                 return I40E_ERR_PARAM;
2952
2953         i40e_fill_default_direct_cmd_desc(&desc,
2954                                           i40e_aqc_opc_get_veb_parameters);
2955         cmd_resp->seid = CPU_TO_LE16(veb_seid);
2956
2957         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2958         if (status)
2959                 goto get_veb_exit;
2960
2961         if (switch_id)
2962                 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2963         if (statistic_index)
2964                 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2965         if (vebs_used)
2966                 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2967         if (vebs_free)
2968                 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2969         if (floating) {
2970                 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2971
2972                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2973                         *floating = true;
2974                 else
2975                         *floating = false;
2976         }
2977
2978 get_veb_exit:
2979         return status;
2980 }
2981
2982 /**
2983  * i40e_aq_add_macvlan
2984  * @hw: pointer to the hw struct
2985  * @seid: VSI for the mac address
2986  * @mv_list: list of macvlans to be added
2987  * @count: length of the list
2988  * @cmd_details: pointer to command details structure or NULL
2989  *
2990  * Add MAC/VLAN addresses to the HW filtering
2991  **/
2992 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2993                         struct i40e_aqc_add_macvlan_element_data *mv_list,
2994                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2995 {
2996         struct i40e_aq_desc desc;
2997         struct i40e_aqc_macvlan *cmd =
2998                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2999         enum i40e_status_code status;
3000         u16 buf_size;
3001         int i;
3002
3003         if (count == 0 || !mv_list || !hw)
3004                 return I40E_ERR_PARAM;
3005
3006         buf_size = count * sizeof(*mv_list);
3007
3008         /* prep the rest of the request */
3009         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
3010         cmd->num_addresses = CPU_TO_LE16(count);
3011         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3012         cmd->seid[1] = 0;
3013         cmd->seid[2] = 0;
3014
3015         for (i = 0; i < count; i++)
3016                 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
3017                         mv_list[i].flags |=
3018                             CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
3019
3020         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3021         if (buf_size > I40E_AQ_LARGE_BUF)
3022                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3023
3024         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3025                                        cmd_details);
3026
3027         return status;
3028 }
3029
3030 /**
3031  * i40e_aq_remove_macvlan
3032  * @hw: pointer to the hw struct
3033  * @seid: VSI for the mac address
3034  * @mv_list: list of macvlans to be removed
3035  * @count: length of the list
3036  * @cmd_details: pointer to command details structure or NULL
3037  *
3038  * Remove MAC/VLAN addresses from the HW filtering
3039  **/
3040 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
3041                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
3042                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3043 {
3044         struct i40e_aq_desc desc;
3045         struct i40e_aqc_macvlan *cmd =
3046                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3047         enum i40e_status_code status;
3048         u16 buf_size;
3049
3050         if (count == 0 || !mv_list || !hw)
3051                 return I40E_ERR_PARAM;
3052
3053         buf_size = count * sizeof(*mv_list);
3054
3055         /* prep the rest of the request */
3056         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
3057         cmd->num_addresses = CPU_TO_LE16(count);
3058         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3059         cmd->seid[1] = 0;
3060         cmd->seid[2] = 0;
3061
3062         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3063         if (buf_size > I40E_AQ_LARGE_BUF)
3064                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3065
3066         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3067                                        cmd_details);
3068
3069         return status;
3070 }
3071
3072 /**
3073  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3074  * @hw: pointer to the hw struct
3075  * @opcode: AQ opcode for add or delete mirror rule
3076  * @sw_seid: Switch SEID (to which rule refers)
3077  * @rule_type: Rule Type (ingress/egress/VLAN)
3078  * @id: Destination VSI SEID or Rule ID
3079  * @count: length of the list
3080  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3081  * @cmd_details: pointer to command details structure or NULL
3082  * @rule_id: Rule ID returned from FW
3083  * @rule_used: Number of rules used in internal switch
3084  * @rule_free: Number of rules free in internal switch
3085  *
3086  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3087  * VEBs/VEPA elements only
3088  **/
3089 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3090                         u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3091                         u16 count, __le16 *mr_list,
3092                         struct i40e_asq_cmd_details *cmd_details,
3093                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3094 {
3095         struct i40e_aq_desc desc;
3096         struct i40e_aqc_add_delete_mirror_rule *cmd =
3097                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3098         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3099         (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3100         enum i40e_status_code status;
3101         u16 buf_size;
3102
3103         buf_size = count * sizeof(*mr_list);
3104
3105         /* prep the rest of the request */
3106         i40e_fill_default_direct_cmd_desc(&desc, opcode);
3107         cmd->seid = CPU_TO_LE16(sw_seid);
3108         cmd->rule_type = CPU_TO_LE16(rule_type &
3109                                      I40E_AQC_MIRROR_RULE_TYPE_MASK);
3110         cmd->num_entries = CPU_TO_LE16(count);
3111         /* Dest VSI for add, rule_id for delete */
3112         cmd->destination = CPU_TO_LE16(id);
3113         if (mr_list) {
3114                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3115                                                 I40E_AQ_FLAG_RD));
3116                 if (buf_size > I40E_AQ_LARGE_BUF)
3117                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3118         }
3119
3120         status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3121                                        cmd_details);
3122         if (status == I40E_SUCCESS ||
3123             hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3124                 if (rule_id)
3125                         *rule_id = LE16_TO_CPU(resp->rule_id);
3126                 if (rules_used)
3127                         *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3128                 if (rules_free)
3129                         *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3130         }
3131         return status;
3132 }
3133
3134 /**
3135  * i40e_aq_add_mirrorrule - add a mirror rule
3136  * @hw: pointer to the hw struct
3137  * @sw_seid: Switch SEID (to which rule refers)
3138  * @rule_type: Rule Type (ingress/egress/VLAN)
3139  * @dest_vsi: SEID of VSI to which packets will be mirrored
3140  * @count: length of the list
3141  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3142  * @cmd_details: pointer to command details structure or NULL
3143  * @rule_id: Rule ID returned from FW
3144  * @rule_used: Number of rules used in internal switch
3145  * @rule_free: Number of rules free in internal switch
3146  *
3147  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3148  **/
3149 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3150                         u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3151                         struct i40e_asq_cmd_details *cmd_details,
3152                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3153 {
3154         if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3155             rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3156                 if (count == 0 || !mr_list)
3157                         return I40E_ERR_PARAM;
3158         }
3159
3160         return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3161                                   rule_type, dest_vsi, count, mr_list,
3162                                   cmd_details, rule_id, rules_used, rules_free);
3163 }
3164
3165 /**
3166  * i40e_aq_delete_mirrorrule - delete a mirror rule
3167  * @hw: pointer to the hw struct
3168  * @sw_seid: Switch SEID (to which rule refers)
3169  * @rule_type: Rule Type (ingress/egress/VLAN)
3170  * @count: length of the list
3171  * @rule_id: Rule ID that is returned in the receive desc as part of
3172  *              add_mirrorrule.
3173  * @mr_list: list of mirrored VLAN IDs to be removed
3174  * @cmd_details: pointer to command details structure or NULL
3175  * @rule_used: Number of rules used in internal switch
3176  * @rule_free: Number of rules free in internal switch
3177  *
3178  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3179  **/
3180 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3181                         u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3182                         struct i40e_asq_cmd_details *cmd_details,
3183                         u16 *rules_used, u16 *rules_free)
3184 {
3185         /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3186         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3187                 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3188                  * mirroring. For other rule_type, count and rule_type should
3189                  * not matter.
3190                  */
3191                 if (count == 0 || !mr_list)
3192                         return I40E_ERR_PARAM;
3193         }
3194
3195         return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3196                                   rule_type, rule_id, count, mr_list,
3197                                   cmd_details, NULL, rules_used, rules_free);
3198 }
3199
3200 /**
3201  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3202  * @hw: pointer to the hw struct
3203  * @seid: VSI for the vlan filters
3204  * @v_list: list of vlan filters to be added
3205  * @count: length of the list
3206  * @cmd_details: pointer to command details structure or NULL
3207  **/
3208 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3209                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3210                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3211 {
3212         struct i40e_aq_desc desc;
3213         struct i40e_aqc_macvlan *cmd =
3214                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3215         enum i40e_status_code status;
3216         u16 buf_size;
3217
3218         if (count == 0 || !v_list || !hw)
3219                 return I40E_ERR_PARAM;
3220
3221         buf_size = count * sizeof(*v_list);
3222
3223         /* prep the rest of the request */
3224         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3225         cmd->num_addresses = CPU_TO_LE16(count);
3226         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3227         cmd->seid[1] = 0;
3228         cmd->seid[2] = 0;
3229
3230         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3231         if (buf_size > I40E_AQ_LARGE_BUF)
3232                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3233
3234         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3235                                        cmd_details);
3236
3237         return status;
3238 }
3239
3240 /**
3241  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3242  * @hw: pointer to the hw struct
3243  * @seid: VSI for the vlan filters
3244  * @v_list: list of macvlans to be removed
3245  * @count: length of the list
3246  * @cmd_details: pointer to command details structure or NULL
3247  **/
3248 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3249                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3250                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3251 {
3252         struct i40e_aq_desc desc;
3253         struct i40e_aqc_macvlan *cmd =
3254                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3255         enum i40e_status_code status;
3256         u16 buf_size;
3257
3258         if (count == 0 || !v_list || !hw)
3259                 return I40E_ERR_PARAM;
3260
3261         buf_size = count * sizeof(*v_list);
3262
3263         /* prep the rest of the request */
3264         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3265         cmd->num_addresses = CPU_TO_LE16(count);
3266         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3267         cmd->seid[1] = 0;
3268         cmd->seid[2] = 0;
3269
3270         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3271         if (buf_size > I40E_AQ_LARGE_BUF)
3272                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3273
3274         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3275                                        cmd_details);
3276
3277         return status;
3278 }
3279
3280 /**
3281  * i40e_aq_send_msg_to_vf
3282  * @hw: pointer to the hardware structure
3283  * @vfid: vf id to send msg
3284  * @v_opcode: opcodes for VF-PF communication
3285  * @v_retval: return error code
3286  * @msg: pointer to the msg buffer
3287  * @msglen: msg length
3288  * @cmd_details: pointer to command details
3289  *
3290  * send msg to vf
3291  **/
3292 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3293                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3294                                 struct i40e_asq_cmd_details *cmd_details)
3295 {
3296         struct i40e_aq_desc desc;
3297         struct i40e_aqc_pf_vf_message *cmd =
3298                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3299         enum i40e_status_code status;
3300
3301         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3302         cmd->id = CPU_TO_LE32(vfid);
3303         desc.cookie_high = CPU_TO_LE32(v_opcode);
3304         desc.cookie_low = CPU_TO_LE32(v_retval);
3305         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3306         if (msglen) {
3307                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3308                                                 I40E_AQ_FLAG_RD));
3309                 if (msglen > I40E_AQ_LARGE_BUF)
3310                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3311                 desc.datalen = CPU_TO_LE16(msglen);
3312         }
3313         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3314
3315         return status;
3316 }
3317
3318 /**
3319  * i40e_aq_debug_read_register
3320  * @hw: pointer to the hw struct
3321  * @reg_addr: register address
3322  * @reg_val: register value
3323  * @cmd_details: pointer to command details structure or NULL
3324  *
3325  * Read the register using the admin queue commands
3326  **/
3327 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3328                                 u32 reg_addr, u64 *reg_val,
3329                                 struct i40e_asq_cmd_details *cmd_details)
3330 {
3331         struct i40e_aq_desc desc;
3332         struct i40e_aqc_debug_reg_read_write *cmd_resp =
3333                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3334         enum i40e_status_code status;
3335
3336         if (reg_val == NULL)
3337                 return I40E_ERR_PARAM;
3338
3339         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3340
3341         cmd_resp->address = CPU_TO_LE32(reg_addr);
3342
3343         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3344
3345         if (status == I40E_SUCCESS) {
3346                 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3347                            (u64)LE32_TO_CPU(cmd_resp->value_low);
3348         }
3349
3350         return status;
3351 }
3352
3353 /**
3354  * i40e_aq_debug_write_register
3355  * @hw: pointer to the hw struct
3356  * @reg_addr: register address
3357  * @reg_val: register value
3358  * @cmd_details: pointer to command details structure or NULL
3359  *
3360  * Write to a register using the admin queue commands
3361  **/
3362 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3363                                 u32 reg_addr, u64 reg_val,
3364                                 struct i40e_asq_cmd_details *cmd_details)
3365 {
3366         struct i40e_aq_desc desc;
3367         struct i40e_aqc_debug_reg_read_write *cmd =
3368                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3369         enum i40e_status_code status;
3370
3371         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3372
3373         cmd->address = CPU_TO_LE32(reg_addr);
3374         cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3375         cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3376
3377         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3378
3379         return status;
3380 }
3381
3382 /**
3383  * i40e_aq_request_resource
3384  * @hw: pointer to the hw struct
3385  * @resource: resource id
3386  * @access: access type
3387  * @sdp_number: resource number
3388  * @timeout: the maximum time in ms that the driver may hold the resource
3389  * @cmd_details: pointer to command details structure or NULL
3390  *
3391  * requests common resource using the admin queue commands
3392  **/
3393 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3394                                 enum i40e_aq_resources_ids resource,
3395                                 enum i40e_aq_resource_access_type access,
3396                                 u8 sdp_number, u64 *timeout,
3397                                 struct i40e_asq_cmd_details *cmd_details)
3398 {
3399         struct i40e_aq_desc desc;
3400         struct i40e_aqc_request_resource *cmd_resp =
3401                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3402         enum i40e_status_code status;
3403
3404         DEBUGFUNC("i40e_aq_request_resource");
3405
3406         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3407
3408         cmd_resp->resource_id = CPU_TO_LE16(resource);
3409         cmd_resp->access_type = CPU_TO_LE16(access);
3410         cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3411
3412         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3413         /* The completion specifies the maximum time in ms that the driver
3414          * may hold the resource in the Timeout field.
3415          * If the resource is held by someone else, the command completes with
3416          * busy return value and the timeout field indicates the maximum time
3417          * the current owner of the resource has to free it.
3418          */
3419         if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3420                 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3421
3422         return status;
3423 }
3424
3425 /**
3426  * i40e_aq_release_resource
3427  * @hw: pointer to the hw struct
3428  * @resource: resource id
3429  * @sdp_number: resource number
3430  * @cmd_details: pointer to command details structure or NULL
3431  *
3432  * release common resource using the admin queue commands
3433  **/
3434 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3435                                 enum i40e_aq_resources_ids resource,
3436                                 u8 sdp_number,
3437                                 struct i40e_asq_cmd_details *cmd_details)
3438 {
3439         struct i40e_aq_desc desc;
3440         struct i40e_aqc_request_resource *cmd =
3441                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3442         enum i40e_status_code status;
3443
3444         DEBUGFUNC("i40e_aq_release_resource");
3445
3446         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3447
3448         cmd->resource_id = CPU_TO_LE16(resource);
3449         cmd->resource_number = CPU_TO_LE32(sdp_number);
3450
3451         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3452
3453         return status;
3454 }
3455
3456 /**
3457  * i40e_aq_read_nvm
3458  * @hw: pointer to the hw struct
3459  * @module_pointer: module pointer location in words from the NVM beginning
3460  * @offset: byte offset from the module beginning
3461  * @length: length of the section to be read (in bytes from the offset)
3462  * @data: command buffer (size [bytes] = length)
3463  * @last_command: tells if this is the last command in a series
3464  * @cmd_details: pointer to command details structure or NULL
3465  *
3466  * Read the NVM using the admin queue commands
3467  **/
3468 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3469                                 u32 offset, u16 length, void *data,
3470                                 bool last_command,
3471                                 struct i40e_asq_cmd_details *cmd_details)
3472 {
3473         struct i40e_aq_desc desc;
3474         struct i40e_aqc_nvm_update *cmd =
3475                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3476         enum i40e_status_code status;
3477
3478         DEBUGFUNC("i40e_aq_read_nvm");
3479
3480         /* In offset the highest byte must be zeroed. */
3481         if (offset & 0xFF000000) {
3482                 status = I40E_ERR_PARAM;
3483                 goto i40e_aq_read_nvm_exit;
3484         }
3485
3486         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3487
3488         /* If this is the last command in a series, set the proper flag. */
3489         if (last_command)
3490                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3491         cmd->module_pointer = module_pointer;
3492         cmd->offset = CPU_TO_LE32(offset);
3493         cmd->length = CPU_TO_LE16(length);
3494
3495         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3496         if (length > I40E_AQ_LARGE_BUF)
3497                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3498
3499         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3500
3501 i40e_aq_read_nvm_exit:
3502         return status;
3503 }
3504
3505 /**
3506  * i40e_aq_read_nvm_config - read an nvm config block
3507  * @hw: pointer to the hw struct
3508  * @cmd_flags: NVM access admin command bits
3509  * @field_id: field or feature id
3510  * @data: buffer for result
3511  * @buf_size: buffer size
3512  * @element_count: pointer to count of elements read by FW
3513  * @cmd_details: pointer to command details structure or NULL
3514  **/
3515 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3516                                 u8 cmd_flags, u32 field_id, void *data,
3517                                 u16 buf_size, u16 *element_count,
3518                                 struct i40e_asq_cmd_details *cmd_details)
3519 {
3520         struct i40e_aq_desc desc;
3521         struct i40e_aqc_nvm_config_read *cmd =
3522                 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3523         enum i40e_status_code status;
3524
3525         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3526         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3527         if (buf_size > I40E_AQ_LARGE_BUF)
3528                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3529
3530         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3531         cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3532         if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3533                 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3534         else
3535                 cmd->element_id_msw = 0;
3536
3537         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3538
3539         if (!status && element_count)
3540                 *element_count = LE16_TO_CPU(cmd->element_count);
3541
3542         return status;
3543 }
3544
3545 /**
3546  * i40e_aq_write_nvm_config - write an nvm config block
3547  * @hw: pointer to the hw struct
3548  * @cmd_flags: NVM access admin command bits
3549  * @data: buffer for result
3550  * @buf_size: buffer size
3551  * @element_count: count of elements to be written
3552  * @cmd_details: pointer to command details structure or NULL
3553  **/
3554 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3555                                 u8 cmd_flags, void *data, u16 buf_size,
3556                                 u16 element_count,
3557                                 struct i40e_asq_cmd_details *cmd_details)
3558 {
3559         struct i40e_aq_desc desc;
3560         struct i40e_aqc_nvm_config_write *cmd =
3561                 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3562         enum i40e_status_code status;
3563
3564         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3565         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3566         if (buf_size > I40E_AQ_LARGE_BUF)
3567                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3568
3569         cmd->element_count = CPU_TO_LE16(element_count);
3570         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3571         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3572
3573         return status;
3574 }
3575
3576 /**
3577  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3578  * @hw: pointer to the hw struct
3579  * @cmd_details: pointer to command details structure or NULL
3580  **/
3581 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3582                                 void *buff, u16 buff_size,
3583                                 struct i40e_asq_cmd_details *cmd_details)
3584 {
3585         struct i40e_aq_desc desc;
3586         enum i40e_status_code status;
3587
3588         UNREFERENCED_2PARAMETER(buff, buff_size);
3589
3590         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3591         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3592         if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3593                 status = I40E_ERR_NOT_IMPLEMENTED;
3594
3595         return status;
3596 }
3597
3598 /**
3599  * i40e_aq_erase_nvm
3600  * @hw: pointer to the hw struct
3601  * @module_pointer: module pointer location in words from the NVM beginning
3602  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3603  * @length: length of the section to be erased (expressed in 4 KB)
3604  * @last_command: tells if this is the last command in a series
3605  * @cmd_details: pointer to command details structure or NULL
3606  *
3607  * Erase the NVM sector using the admin queue commands
3608  **/
3609 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3610                                 u32 offset, u16 length, bool last_command,
3611                                 struct i40e_asq_cmd_details *cmd_details)
3612 {
3613         struct i40e_aq_desc desc;
3614         struct i40e_aqc_nvm_update *cmd =
3615                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3616         enum i40e_status_code status;
3617
3618         DEBUGFUNC("i40e_aq_erase_nvm");
3619
3620         /* In offset the highest byte must be zeroed. */
3621         if (offset & 0xFF000000) {
3622                 status = I40E_ERR_PARAM;
3623                 goto i40e_aq_erase_nvm_exit;
3624         }
3625
3626         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3627
3628         /* If this is the last command in a series, set the proper flag. */
3629         if (last_command)
3630                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3631         cmd->module_pointer = module_pointer;
3632         cmd->offset = CPU_TO_LE32(offset);
3633         cmd->length = CPU_TO_LE16(length);
3634
3635         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3636
3637 i40e_aq_erase_nvm_exit:
3638         return status;
3639 }
3640
3641 /**
3642  * i40e_parse_discover_capabilities
3643  * @hw: pointer to the hw struct
3644  * @buff: pointer to a buffer containing device/function capability records
3645  * @cap_count: number of capability records in the list
3646  * @list_type_opc: type of capabilities list to parse
3647  *
3648  * Parse the device/function capabilities list.
3649  **/
3650 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3651                                      u32 cap_count,
3652                                      enum i40e_admin_queue_opc list_type_opc)
3653 {
3654         struct i40e_aqc_list_capabilities_element_resp *cap;
3655         u32 valid_functions, num_functions;
3656         u32 number, logical_id, phys_id;
3657         struct i40e_hw_capabilities *p;
3658         u8 major_rev;
3659         u32 i = 0;
3660         u16 id;
3661
3662         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3663
3664         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3665                 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3666         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3667                 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3668         else
3669                 return;
3670
3671         for (i = 0; i < cap_count; i++, cap++) {
3672                 id = LE16_TO_CPU(cap->id);
3673                 number = LE32_TO_CPU(cap->number);
3674                 logical_id = LE32_TO_CPU(cap->logical_id);
3675                 phys_id = LE32_TO_CPU(cap->phys_id);
3676                 major_rev = cap->major_rev;
3677
3678                 switch (id) {
3679                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3680                         p->switch_mode = number;
3681                         i40e_debug(hw, I40E_DEBUG_INIT,
3682                                    "HW Capability: Switch mode = %d\n",
3683                                    p->switch_mode);
3684                         break;
3685                 case I40E_AQ_CAP_ID_MNG_MODE:
3686                         p->management_mode = number;
3687                         if (major_rev > 1) {
3688                                 p->mng_protocols_over_mctp = logical_id;
3689                                 i40e_debug(hw, I40E_DEBUG_INIT,
3690                                            "HW Capability: Protocols over MCTP = %d\n",
3691                                            p->mng_protocols_over_mctp);
3692                         } else {
3693                                 p->mng_protocols_over_mctp = 0;
3694                         }
3695                         i40e_debug(hw, I40E_DEBUG_INIT,
3696                                    "HW Capability: Management Mode = %d\n",
3697                                    p->management_mode);
3698                         break;
3699                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3700                         p->npar_enable = number;
3701                         i40e_debug(hw, I40E_DEBUG_INIT,
3702                                    "HW Capability: NPAR enable = %d\n",
3703                                    p->npar_enable);
3704                         break;
3705                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3706                         p->os2bmc = number;
3707                         i40e_debug(hw, I40E_DEBUG_INIT,
3708                                    "HW Capability: OS2BMC = %d\n", p->os2bmc);
3709                         break;
3710                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3711                         p->valid_functions = number;
3712                         i40e_debug(hw, I40E_DEBUG_INIT,
3713                                    "HW Capability: Valid Functions = %d\n",
3714                                    p->valid_functions);
3715                         break;
3716                 case I40E_AQ_CAP_ID_SRIOV:
3717                         if (number == 1)
3718                                 p->sr_iov_1_1 = true;
3719                         i40e_debug(hw, I40E_DEBUG_INIT,
3720                                    "HW Capability: SR-IOV = %d\n",
3721                                    p->sr_iov_1_1);
3722                         break;
3723                 case I40E_AQ_CAP_ID_VF:
3724                         p->num_vfs = number;
3725                         p->vf_base_id = logical_id;
3726                         i40e_debug(hw, I40E_DEBUG_INIT,
3727                                    "HW Capability: VF count = %d\n",
3728                                    p->num_vfs);
3729                         i40e_debug(hw, I40E_DEBUG_INIT,
3730                                    "HW Capability: VF base_id = %d\n",
3731                                    p->vf_base_id);
3732                         break;
3733                 case I40E_AQ_CAP_ID_VMDQ:
3734                         if (number == 1)
3735                                 p->vmdq = true;
3736                         i40e_debug(hw, I40E_DEBUG_INIT,
3737                                    "HW Capability: VMDQ = %d\n", p->vmdq);
3738                         break;
3739                 case I40E_AQ_CAP_ID_8021QBG:
3740                         if (number == 1)
3741                                 p->evb_802_1_qbg = true;
3742                         i40e_debug(hw, I40E_DEBUG_INIT,
3743                                    "HW Capability: 802.1Qbg = %d\n", number);
3744                         break;
3745                 case I40E_AQ_CAP_ID_8021QBR:
3746                         if (number == 1)
3747                                 p->evb_802_1_qbh = true;
3748                         i40e_debug(hw, I40E_DEBUG_INIT,
3749                                    "HW Capability: 802.1Qbh = %d\n", number);
3750                         break;
3751                 case I40E_AQ_CAP_ID_VSI:
3752                         p->num_vsis = number;
3753                         i40e_debug(hw, I40E_DEBUG_INIT,
3754                                    "HW Capability: VSI count = %d\n",
3755                                    p->num_vsis);
3756                         break;
3757                 case I40E_AQ_CAP_ID_DCB:
3758                         if (number == 1) {
3759                                 p->dcb = true;
3760                                 p->enabled_tcmap = logical_id;
3761                                 p->maxtc = phys_id;
3762                         }
3763                         i40e_debug(hw, I40E_DEBUG_INIT,
3764                                    "HW Capability: DCB = %d\n", p->dcb);
3765                         i40e_debug(hw, I40E_DEBUG_INIT,
3766                                    "HW Capability: TC Mapping = %d\n",
3767                                    logical_id);
3768                         i40e_debug(hw, I40E_DEBUG_INIT,
3769                                    "HW Capability: TC Max = %d\n", p->maxtc);
3770                         break;
3771                 case I40E_AQ_CAP_ID_FCOE:
3772                         if (number == 1)
3773                                 p->fcoe = true;
3774                         i40e_debug(hw, I40E_DEBUG_INIT,
3775                                    "HW Capability: FCOE = %d\n", p->fcoe);
3776                         break;
3777                 case I40E_AQ_CAP_ID_ISCSI:
3778                         if (number == 1)
3779                                 p->iscsi = true;
3780                         i40e_debug(hw, I40E_DEBUG_INIT,
3781                                    "HW Capability: iSCSI = %d\n", p->iscsi);
3782                         break;
3783                 case I40E_AQ_CAP_ID_RSS:
3784                         p->rss = true;
3785                         p->rss_table_size = number;
3786                         p->rss_table_entry_width = logical_id;
3787                         i40e_debug(hw, I40E_DEBUG_INIT,
3788                                    "HW Capability: RSS = %d\n", p->rss);
3789                         i40e_debug(hw, I40E_DEBUG_INIT,
3790                                    "HW Capability: RSS table size = %d\n",
3791                                    p->rss_table_size);
3792                         i40e_debug(hw, I40E_DEBUG_INIT,
3793                                    "HW Capability: RSS table width = %d\n",
3794                                    p->rss_table_entry_width);
3795                         break;
3796                 case I40E_AQ_CAP_ID_RXQ:
3797                         p->num_rx_qp = number;
3798                         p->base_queue = phys_id;
3799                         i40e_debug(hw, I40E_DEBUG_INIT,
3800                                    "HW Capability: Rx QP = %d\n", number);
3801                         i40e_debug(hw, I40E_DEBUG_INIT,
3802                                    "HW Capability: base_queue = %d\n",
3803                                    p->base_queue);
3804                         break;
3805                 case I40E_AQ_CAP_ID_TXQ:
3806                         p->num_tx_qp = number;
3807                         p->base_queue = phys_id;
3808                         i40e_debug(hw, I40E_DEBUG_INIT,
3809                                    "HW Capability: Tx QP = %d\n", number);
3810                         i40e_debug(hw, I40E_DEBUG_INIT,
3811                                    "HW Capability: base_queue = %d\n",
3812                                    p->base_queue);
3813                         break;
3814                 case I40E_AQ_CAP_ID_MSIX:
3815                         p->num_msix_vectors = number;
3816                         i40e_debug(hw, I40E_DEBUG_INIT,
3817                                    "HW Capability: MSIX vector count = %d\n",
3818                                    p->num_msix_vectors);
3819                         break;
3820                 case I40E_AQ_CAP_ID_VF_MSIX:
3821                         p->num_msix_vectors_vf = number;
3822                         i40e_debug(hw, I40E_DEBUG_INIT,
3823                                    "HW Capability: MSIX VF vector count = %d\n",
3824                                    p->num_msix_vectors_vf);
3825                         break;
3826                 case I40E_AQ_CAP_ID_FLEX10:
3827                         if (major_rev == 1) {
3828                                 if (number == 1) {
3829                                         p->flex10_enable = true;
3830                                         p->flex10_capable = true;
3831                                 }
3832                         } else {
3833                                 /* Capability revision >= 2 */
3834                                 if (number & 1)
3835                                         p->flex10_enable = true;
3836                                 if (number & 2)
3837                                         p->flex10_capable = true;
3838                         }
3839                         p->flex10_mode = logical_id;
3840                         p->flex10_status = phys_id;
3841                         i40e_debug(hw, I40E_DEBUG_INIT,
3842                                    "HW Capability: Flex10 mode = %d\n",
3843                                    p->flex10_mode);
3844                         i40e_debug(hw, I40E_DEBUG_INIT,
3845                                    "HW Capability: Flex10 status = %d\n",
3846                                    p->flex10_status);
3847                         break;
3848                 case I40E_AQ_CAP_ID_CEM:
3849                         if (number == 1)
3850                                 p->mgmt_cem = true;
3851                         i40e_debug(hw, I40E_DEBUG_INIT,
3852                                    "HW Capability: CEM = %d\n", p->mgmt_cem);
3853                         break;
3854                 case I40E_AQ_CAP_ID_IWARP:
3855                         if (number == 1)
3856                                 p->iwarp = true;
3857                         i40e_debug(hw, I40E_DEBUG_INIT,
3858                                    "HW Capability: iWARP = %d\n", p->iwarp);
3859                         break;
3860                 case I40E_AQ_CAP_ID_LED:
3861                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3862                                 p->led[phys_id] = true;
3863                         i40e_debug(hw, I40E_DEBUG_INIT,
3864                                    "HW Capability: LED - PIN %d\n", phys_id);
3865                         break;
3866                 case I40E_AQ_CAP_ID_SDP:
3867                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3868                                 p->sdp[phys_id] = true;
3869                         i40e_debug(hw, I40E_DEBUG_INIT,
3870                                    "HW Capability: SDP - PIN %d\n", phys_id);
3871                         break;
3872                 case I40E_AQ_CAP_ID_MDIO:
3873                         if (number == 1) {
3874                                 p->mdio_port_num = phys_id;
3875                                 p->mdio_port_mode = logical_id;
3876                         }
3877                         i40e_debug(hw, I40E_DEBUG_INIT,
3878                                    "HW Capability: MDIO port number = %d\n",
3879                                    p->mdio_port_num);
3880                         i40e_debug(hw, I40E_DEBUG_INIT,
3881                                    "HW Capability: MDIO port mode = %d\n",
3882                                    p->mdio_port_mode);
3883                         break;
3884                 case I40E_AQ_CAP_ID_1588:
3885                         if (number == 1)
3886                                 p->ieee_1588 = true;
3887                         i40e_debug(hw, I40E_DEBUG_INIT,
3888                                    "HW Capability: IEEE 1588 = %d\n",
3889                                    p->ieee_1588);
3890                         break;
3891                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3892                         p->fd = true;
3893                         p->fd_filters_guaranteed = number;
3894                         p->fd_filters_best_effort = logical_id;
3895                         i40e_debug(hw, I40E_DEBUG_INIT,
3896                                    "HW Capability: Flow Director = 1\n");
3897                         i40e_debug(hw, I40E_DEBUG_INIT,
3898                                    "HW Capability: Guaranteed FD filters = %d\n",
3899                                    p->fd_filters_guaranteed);
3900                         break;
3901                 case I40E_AQ_CAP_ID_WSR_PROT:
3902                         p->wr_csr_prot = (u64)number;
3903                         p->wr_csr_prot |= (u64)logical_id << 32;
3904                         i40e_debug(hw, I40E_DEBUG_INIT,
3905                                    "HW Capability: wr_csr_prot = 0x%llX\n\n",
3906                                    (p->wr_csr_prot & 0xffff));
3907                         break;
3908                 case I40E_AQ_CAP_ID_NVM_MGMT:
3909                         if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3910                                 p->sec_rev_disabled = true;
3911                         if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3912                                 p->update_disabled = true;
3913                         break;
3914                 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3915                         hw->num_wol_proxy_filters = (u16)number;
3916                         hw->wol_proxy_vsi_seid = (u16)logical_id;
3917                         p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3918                         if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3919                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3920                         else
3921                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3922                         p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3923                         i40e_debug(hw, I40E_DEBUG_INIT,
3924                                    "HW Capability: WOL proxy filters = %d\n",
3925                                    hw->num_wol_proxy_filters);
3926                         break;
3927                 default:
3928                         break;
3929                 }
3930         }
3931
3932         if (p->fcoe)
3933                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3934
3935         /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3936         p->fcoe = false;
3937
3938         /* count the enabled ports (aka the "not disabled" ports) */
3939         hw->num_ports = 0;
3940         for (i = 0; i < 4; i++) {
3941                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3942                 u64 port_cfg = 0;
3943
3944                 /* use AQ read to get the physical register offset instead
3945                  * of the port relative offset
3946                  */
3947                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3948                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3949                         hw->num_ports++;
3950         }
3951
3952         valid_functions = p->valid_functions;
3953         num_functions = 0;
3954         while (valid_functions) {
3955                 if (valid_functions & 1)
3956                         num_functions++;
3957                 valid_functions >>= 1;
3958         }
3959
3960         /* partition id is 1-based, and functions are evenly spread
3961          * across the ports as partitions
3962          */
3963         if (hw->num_ports != 0) {
3964                 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3965                 hw->num_partitions = num_functions / hw->num_ports;
3966         }
3967
3968         /* additional HW specific goodies that might
3969          * someday be HW version specific
3970          */
3971         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3972 }
3973
3974 /**
3975  * i40e_aq_discover_capabilities
3976  * @hw: pointer to the hw struct
3977  * @buff: a virtual buffer to hold the capabilities
3978  * @buff_size: Size of the virtual buffer
3979  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3980  * @list_type_opc: capabilities type to discover - pass in the command opcode
3981  * @cmd_details: pointer to command details structure or NULL
3982  *
3983  * Get the device capabilities descriptions from the firmware
3984  **/
3985 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3986                                 void *buff, u16 buff_size, u16 *data_size,
3987                                 enum i40e_admin_queue_opc list_type_opc,
3988                                 struct i40e_asq_cmd_details *cmd_details)
3989 {
3990         struct i40e_aqc_list_capabilites *cmd;
3991         struct i40e_aq_desc desc;
3992         enum i40e_status_code status = I40E_SUCCESS;
3993
3994         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3995
3996         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3997                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3998                 status = I40E_ERR_PARAM;
3999                 goto exit;
4000         }
4001
4002         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
4003
4004         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4005         if (buff_size > I40E_AQ_LARGE_BUF)
4006                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4007
4008         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4009         *data_size = LE16_TO_CPU(desc.datalen);
4010
4011         if (status)
4012                 goto exit;
4013
4014         i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
4015                                          list_type_opc);
4016
4017 exit:
4018         return status;
4019 }
4020
4021 /**
4022  * i40e_aq_update_nvm
4023  * @hw: pointer to the hw struct
4024  * @module_pointer: module pointer location in words from the NVM beginning
4025  * @offset: byte offset from the module beginning
4026  * @length: length of the section to be written (in bytes from the offset)
4027  * @data: command buffer (size [bytes] = length)
4028  * @last_command: tells if this is the last command in a series
4029  * @cmd_details: pointer to command details structure or NULL
4030  *
4031  * Update the NVM using the admin queue commands
4032  **/
4033 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
4034                                 u32 offset, u16 length, void *data,
4035                                 bool last_command,
4036                                 struct i40e_asq_cmd_details *cmd_details)
4037 {
4038         struct i40e_aq_desc desc;
4039         struct i40e_aqc_nvm_update *cmd =
4040                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
4041         enum i40e_status_code status;
4042
4043         DEBUGFUNC("i40e_aq_update_nvm");
4044
4045         /* In offset the highest byte must be zeroed. */
4046         if (offset & 0xFF000000) {
4047                 status = I40E_ERR_PARAM;
4048                 goto i40e_aq_update_nvm_exit;
4049         }
4050
4051         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4052
4053         /* If this is the last command in a series, set the proper flag. */
4054         if (last_command)
4055                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
4056         cmd->module_pointer = module_pointer;
4057         cmd->offset = CPU_TO_LE32(offset);
4058         cmd->length = CPU_TO_LE16(length);
4059
4060         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4061         if (length > I40E_AQ_LARGE_BUF)
4062                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4063
4064         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
4065
4066 i40e_aq_update_nvm_exit:
4067         return status;
4068 }
4069
4070 /**
4071  * i40e_aq_get_lldp_mib
4072  * @hw: pointer to the hw struct
4073  * @bridge_type: type of bridge requested
4074  * @mib_type: Local, Remote or both Local and Remote MIBs
4075  * @buff: pointer to a user supplied buffer to store the MIB block
4076  * @buff_size: size of the buffer (in bytes)
4077  * @local_len : length of the returned Local LLDP MIB
4078  * @remote_len: length of the returned Remote LLDP MIB
4079  * @cmd_details: pointer to command details structure or NULL
4080  *
4081  * Requests the complete LLDP MIB (entire packet).
4082  **/
4083 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4084                                 u8 mib_type, void *buff, u16 buff_size,
4085                                 u16 *local_len, u16 *remote_len,
4086                                 struct i40e_asq_cmd_details *cmd_details)
4087 {
4088         struct i40e_aq_desc desc;
4089         struct i40e_aqc_lldp_get_mib *cmd =
4090                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4091         struct i40e_aqc_lldp_get_mib *resp =
4092                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4093         enum i40e_status_code status;
4094
4095         if (buff_size == 0 || !buff)
4096                 return I40E_ERR_PARAM;
4097
4098         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4099         /* Indirect Command */
4100         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4101
4102         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4103         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4104                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4105
4106         desc.datalen = CPU_TO_LE16(buff_size);
4107
4108         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4109         if (buff_size > I40E_AQ_LARGE_BUF)
4110                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4111
4112         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4113         if (!status) {
4114                 if (local_len != NULL)
4115                         *local_len = LE16_TO_CPU(resp->local_len);
4116                 if (remote_len != NULL)
4117                         *remote_len = LE16_TO_CPU(resp->remote_len);
4118         }
4119
4120         return status;
4121 }
4122
4123  /**
4124  * i40e_aq_set_lldp_mib - Set the LLDP MIB
4125  * @hw: pointer to the hw struct
4126  * @mib_type: Local, Remote or both Local and Remote MIBs
4127  * @buff: pointer to a user supplied buffer to store the MIB block
4128  * @buff_size: size of the buffer (in bytes)
4129  * @cmd_details: pointer to command details structure or NULL
4130  *
4131  * Set the LLDP MIB.
4132  **/
4133 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4134                                 u8 mib_type, void *buff, u16 buff_size,
4135                                 struct i40e_asq_cmd_details *cmd_details)
4136 {
4137         struct i40e_aq_desc desc;
4138         struct i40e_aqc_lldp_set_local_mib *cmd =
4139                 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4140         enum i40e_status_code status;
4141
4142         if (buff_size == 0 || !buff)
4143                 return I40E_ERR_PARAM;
4144
4145         i40e_fill_default_direct_cmd_desc(&desc,
4146                                 i40e_aqc_opc_lldp_set_local_mib);
4147         /* Indirect Command */
4148         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4149         if (buff_size > I40E_AQ_LARGE_BUF)
4150                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4151         desc.datalen = CPU_TO_LE16(buff_size);
4152
4153         cmd->type = mib_type;
4154         cmd->length = CPU_TO_LE16(buff_size);
4155         cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4156         cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4157
4158         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4159         return status;
4160 }
4161
4162 /**
4163  * i40e_aq_cfg_lldp_mib_change_event
4164  * @hw: pointer to the hw struct
4165  * @enable_update: Enable or Disable event posting
4166  * @cmd_details: pointer to command details structure or NULL
4167  *
4168  * Enable or Disable posting of an event on ARQ when LLDP MIB
4169  * associated with the interface changes
4170  **/
4171 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4172                                 bool enable_update,
4173                                 struct i40e_asq_cmd_details *cmd_details)
4174 {
4175         struct i40e_aq_desc desc;
4176         struct i40e_aqc_lldp_update_mib *cmd =
4177                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4178         enum i40e_status_code status;
4179
4180         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4181
4182         if (!enable_update)
4183                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4184
4185         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4186
4187         return status;
4188 }
4189
4190 /**
4191  * i40e_aq_add_lldp_tlv
4192  * @hw: pointer to the hw struct
4193  * @bridge_type: type of bridge
4194  * @buff: buffer with TLV to add
4195  * @buff_size: length of the buffer
4196  * @tlv_len: length of the TLV to be added
4197  * @mib_len: length of the LLDP MIB returned in response
4198  * @cmd_details: pointer to command details structure or NULL
4199  *
4200  * Add the specified TLV to LLDP Local MIB for the given bridge type,
4201  * it is responsibility of the caller to make sure that the TLV is not
4202  * already present in the LLDPDU.
4203  * In return firmware will write the complete LLDP MIB with the newly
4204  * added TLV in the response buffer.
4205  **/
4206 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4207                                 void *buff, u16 buff_size, u16 tlv_len,
4208                                 u16 *mib_len,
4209                                 struct i40e_asq_cmd_details *cmd_details)
4210 {
4211         struct i40e_aq_desc desc;
4212         struct i40e_aqc_lldp_add_tlv *cmd =
4213                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4214         enum i40e_status_code status;
4215
4216         if (buff_size == 0 || !buff || tlv_len == 0)
4217                 return I40E_ERR_PARAM;
4218
4219         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4220
4221         /* Indirect Command */
4222         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4223         if (buff_size > I40E_AQ_LARGE_BUF)
4224                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4225         desc.datalen = CPU_TO_LE16(buff_size);
4226
4227         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4228                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4229         cmd->len = CPU_TO_LE16(tlv_len);
4230
4231         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4232         if (!status) {
4233                 if (mib_len != NULL)
4234                         *mib_len = LE16_TO_CPU(desc.datalen);
4235         }
4236
4237         return status;
4238 }
4239
4240 /**
4241  * i40e_aq_update_lldp_tlv
4242  * @hw: pointer to the hw struct
4243  * @bridge_type: type of bridge
4244  * @buff: buffer with TLV to update
4245  * @buff_size: size of the buffer holding original and updated TLVs
4246  * @old_len: Length of the Original TLV
4247  * @new_len: Length of the Updated TLV
4248  * @offset: offset of the updated TLV in the buff
4249  * @mib_len: length of the returned LLDP MIB
4250  * @cmd_details: pointer to command details structure or NULL
4251  *
4252  * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4253  * Firmware will place the complete LLDP MIB in response buffer with the
4254  * updated TLV.
4255  **/
4256 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4257                                 u8 bridge_type, void *buff, u16 buff_size,
4258                                 u16 old_len, u16 new_len, u16 offset,
4259                                 u16 *mib_len,
4260                                 struct i40e_asq_cmd_details *cmd_details)
4261 {
4262         struct i40e_aq_desc desc;
4263         struct i40e_aqc_lldp_update_tlv *cmd =
4264                 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4265         enum i40e_status_code status;
4266
4267         if (buff_size == 0 || !buff || offset == 0 ||
4268             old_len == 0 || new_len == 0)
4269                 return I40E_ERR_PARAM;
4270
4271         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4272
4273         /* Indirect Command */
4274         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4275         if (buff_size > I40E_AQ_LARGE_BUF)
4276                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4277         desc.datalen = CPU_TO_LE16(buff_size);
4278
4279         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4280                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4281         cmd->old_len = CPU_TO_LE16(old_len);
4282         cmd->new_offset = CPU_TO_LE16(offset);
4283         cmd->new_len = CPU_TO_LE16(new_len);
4284
4285         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4286         if (!status) {
4287                 if (mib_len != NULL)
4288                         *mib_len = LE16_TO_CPU(desc.datalen);
4289         }
4290
4291         return status;
4292 }
4293
4294 /**
4295  * i40e_aq_delete_lldp_tlv
4296  * @hw: pointer to the hw struct
4297  * @bridge_type: type of bridge
4298  * @buff: pointer to a user supplied buffer that has the TLV
4299  * @buff_size: length of the buffer
4300  * @tlv_len: length of the TLV to be deleted
4301  * @mib_len: length of the returned LLDP MIB
4302  * @cmd_details: pointer to command details structure or NULL
4303  *
4304  * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4305  * The firmware places the entire LLDP MIB in the response buffer.
4306  **/
4307 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4308                                 u8 bridge_type, void *buff, u16 buff_size,
4309                                 u16 tlv_len, u16 *mib_len,
4310                                 struct i40e_asq_cmd_details *cmd_details)
4311 {
4312         struct i40e_aq_desc desc;
4313         struct i40e_aqc_lldp_add_tlv *cmd =
4314                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4315         enum i40e_status_code status;
4316
4317         if (buff_size == 0 || !buff)
4318                 return I40E_ERR_PARAM;
4319
4320         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4321
4322         /* Indirect Command */
4323         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4324         if (buff_size > I40E_AQ_LARGE_BUF)
4325                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4326         desc.datalen = CPU_TO_LE16(buff_size);
4327         cmd->len = CPU_TO_LE16(tlv_len);
4328         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4329                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4330
4331         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4332         if (!status) {
4333                 if (mib_len != NULL)
4334                         *mib_len = LE16_TO_CPU(desc.datalen);
4335         }
4336
4337         return status;
4338 }
4339
4340 /**
4341  * i40e_aq_stop_lldp
4342  * @hw: pointer to the hw struct
4343  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4344  * @cmd_details: pointer to command details structure or NULL
4345  *
4346  * Stop or Shutdown the embedded LLDP Agent
4347  **/
4348 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4349                                 struct i40e_asq_cmd_details *cmd_details)
4350 {
4351         struct i40e_aq_desc desc;
4352         struct i40e_aqc_lldp_stop *cmd =
4353                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4354         enum i40e_status_code status;
4355
4356         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4357
4358         if (shutdown_agent)
4359                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4360
4361         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4362
4363         return status;
4364 }
4365
4366 /**
4367  * i40e_aq_start_lldp
4368  * @hw: pointer to the hw struct
4369  * @cmd_details: pointer to command details structure or NULL
4370  *
4371  * Start the embedded LLDP Agent on all ports.
4372  **/
4373 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4374                                 struct i40e_asq_cmd_details *cmd_details)
4375 {
4376         struct i40e_aq_desc desc;
4377         struct i40e_aqc_lldp_start *cmd =
4378                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4379         enum i40e_status_code status;
4380
4381         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4382
4383         cmd->command = I40E_AQ_LLDP_AGENT_START;
4384
4385         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4386
4387         return status;
4388 }
4389
4390 /**
4391  * i40e_aq_get_cee_dcb_config
4392  * @hw: pointer to the hw struct
4393  * @buff: response buffer that stores CEE operational configuration
4394  * @buff_size: size of the buffer passed
4395  * @cmd_details: pointer to command details structure or NULL
4396  *
4397  * Get CEE DCBX mode operational configuration from firmware
4398  **/
4399 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4400                                 void *buff, u16 buff_size,
4401                                 struct i40e_asq_cmd_details *cmd_details)
4402 {
4403         struct i40e_aq_desc desc;
4404         enum i40e_status_code status;
4405
4406         if (buff_size == 0 || !buff)
4407                 return I40E_ERR_PARAM;
4408
4409         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4410
4411         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4412         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4413                                        cmd_details);
4414
4415         return status;
4416 }
4417
4418 /**
4419  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4420  * @hw: pointer to the hw struct
4421  * @start_agent: True if DCBx Agent needs to be Started
4422  *                              False if DCBx Agent needs to be Stopped
4423  * @cmd_details: pointer to command details structure or NULL
4424  *
4425  * Start/Stop the embedded dcbx Agent
4426  **/
4427 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4428                                 bool start_agent,
4429                                 struct i40e_asq_cmd_details *cmd_details)
4430 {
4431         struct i40e_aq_desc desc;
4432         struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4433                 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4434                                 &desc.params.raw;
4435         enum i40e_status_code status;
4436
4437         i40e_fill_default_direct_cmd_desc(&desc,
4438                                 i40e_aqc_opc_lldp_stop_start_spec_agent);
4439
4440         if (start_agent)
4441                 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4442
4443         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4444
4445         return status;
4446 }
4447
4448 /**
4449  * i40e_aq_add_udp_tunnel
4450  * @hw: pointer to the hw struct
4451  * @udp_port: the UDP port to add in Host byte order
4452  * @header_len: length of the tunneling header length in DWords
4453  * @protocol_index: protocol index type
4454  * @filter_index: pointer to filter index
4455  * @cmd_details: pointer to command details structure or NULL
4456  *
4457  * Note: Firmware expects the udp_port value to be in Little Endian format,
4458  * and this function will call CPU_TO_LE16 to convert from Host byte order to
4459  * Little Endian order.
4460  **/
4461 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4462                                 u16 udp_port, u8 protocol_index,
4463                                 u8 *filter_index,
4464                                 struct i40e_asq_cmd_details *cmd_details)
4465 {
4466         struct i40e_aq_desc desc;
4467         struct i40e_aqc_add_udp_tunnel *cmd =
4468                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4469         struct i40e_aqc_del_udp_tunnel_completion *resp =
4470                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4471         enum i40e_status_code status;
4472
4473         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4474
4475         cmd->udp_port = CPU_TO_LE16(udp_port);
4476         cmd->protocol_type = protocol_index;
4477
4478         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4479
4480         if (!status && filter_index)
4481                 *filter_index = resp->index;
4482
4483         return status;
4484 }
4485
4486 /**
4487  * i40e_aq_del_udp_tunnel
4488  * @hw: pointer to the hw struct
4489  * @index: filter index
4490  * @cmd_details: pointer to command details structure or NULL
4491  **/
4492 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4493                                 struct i40e_asq_cmd_details *cmd_details)
4494 {
4495         struct i40e_aq_desc desc;
4496         struct i40e_aqc_remove_udp_tunnel *cmd =
4497                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4498         enum i40e_status_code status;
4499
4500         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4501
4502         cmd->index = index;
4503
4504         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4505
4506         return status;
4507 }
4508
4509 /**
4510  * i40e_aq_get_switch_resource_alloc (0x0204)
4511  * @hw: pointer to the hw struct
4512  * @num_entries: pointer to u8 to store the number of resource entries returned
4513  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
4514  *        to store the resource information for all resource types.  Each
4515  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
4516  * @count: size, in bytes, of the buffer provided
4517  * @cmd_details: pointer to command details structure or NULL
4518  *
4519  * Query the resources allocated to a function.
4520  **/
4521 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4522                         u8 *num_entries,
4523                         struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4524                         u16 count,
4525                         struct i40e_asq_cmd_details *cmd_details)
4526 {
4527         struct i40e_aq_desc desc;
4528         struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4529                 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4530         enum i40e_status_code status;
4531         u16 length = count * sizeof(*buf);
4532
4533         i40e_fill_default_direct_cmd_desc(&desc,
4534                                         i40e_aqc_opc_get_switch_resource_alloc);
4535
4536         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4537         if (length > I40E_AQ_LARGE_BUF)
4538                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4539
4540         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4541
4542         if (!status && num_entries)
4543                 *num_entries = cmd_resp->num_entries;
4544
4545         return status;
4546 }
4547
4548 /**
4549  * i40e_aq_delete_element - Delete switch element
4550  * @hw: pointer to the hw struct
4551  * @seid: the SEID to delete from the switch
4552  * @cmd_details: pointer to command details structure or NULL
4553  *
4554  * This deletes a switch element from the switch.
4555  **/
4556 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4557                                 struct i40e_asq_cmd_details *cmd_details)
4558 {
4559         struct i40e_aq_desc desc;
4560         struct i40e_aqc_switch_seid *cmd =
4561                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4562         enum i40e_status_code status;
4563
4564         if (seid == 0)
4565                 return I40E_ERR_PARAM;
4566
4567         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4568
4569         cmd->seid = CPU_TO_LE16(seid);
4570
4571         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4572
4573         return status;
4574 }
4575
4576 /**
4577  * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4578  * @hw: pointer to the hw struct
4579  * @flags: component flags
4580  * @mac_seid: uplink seid (MAC SEID)
4581  * @vsi_seid: connected vsi seid
4582  * @ret_seid: seid of create pv component
4583  *
4584  * This instantiates an i40e port virtualizer with specified flags.
4585  * Depending on specified flags the port virtualizer can act as a
4586  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4587  */
4588 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4589                                        u16 mac_seid, u16 vsi_seid,
4590                                        u16 *ret_seid)
4591 {
4592         struct i40e_aq_desc desc;
4593         struct i40e_aqc_add_update_pv *cmd =
4594                 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4595         struct i40e_aqc_add_update_pv_completion *resp =
4596                 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4597         enum i40e_status_code status;
4598
4599         if (vsi_seid == 0)
4600                 return I40E_ERR_PARAM;
4601
4602         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4603         cmd->command_flags = CPU_TO_LE16(flags);
4604         cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4605         cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4606
4607         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4608         if (!status && ret_seid)
4609                 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4610
4611         return status;
4612 }
4613
4614 /**
4615  * i40e_aq_add_tag - Add an S/E-tag
4616  * @hw: pointer to the hw struct
4617  * @direct_to_queue: should s-tag direct flow to a specific queue
4618  * @vsi_seid: VSI SEID to use this tag
4619  * @tag: value of the tag
4620  * @queue_num: queue number, only valid is direct_to_queue is true
4621  * @tags_used: return value, number of tags in use by this PF
4622  * @tags_free: return value, number of unallocated tags
4623  * @cmd_details: pointer to command details structure or NULL
4624  *
4625  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4626  * the number of tags allocated by the PF, and the number of unallocated
4627  * tags available.
4628  **/
4629 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4630                                 u16 vsi_seid, u16 tag, u16 queue_num,
4631                                 u16 *tags_used, u16 *tags_free,
4632                                 struct i40e_asq_cmd_details *cmd_details)
4633 {
4634         struct i40e_aq_desc desc;
4635         struct i40e_aqc_add_tag *cmd =
4636                 (struct i40e_aqc_add_tag *)&desc.params.raw;
4637         struct i40e_aqc_add_remove_tag_completion *resp =
4638                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4639         enum i40e_status_code status;
4640
4641         if (vsi_seid == 0)
4642                 return I40E_ERR_PARAM;
4643
4644         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4645
4646         cmd->seid = CPU_TO_LE16(vsi_seid);
4647         cmd->tag = CPU_TO_LE16(tag);
4648         if (direct_to_queue) {
4649                 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4650                 cmd->queue_number = CPU_TO_LE16(queue_num);
4651         }
4652
4653         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4654
4655         if (!status) {
4656                 if (tags_used != NULL)
4657                         *tags_used = LE16_TO_CPU(resp->tags_used);
4658                 if (tags_free != NULL)
4659                         *tags_free = LE16_TO_CPU(resp->tags_free);
4660         }
4661
4662         return status;
4663 }
4664
4665 /**
4666  * i40e_aq_remove_tag - Remove an S- or E-tag
4667  * @hw: pointer to the hw struct
4668  * @vsi_seid: VSI SEID this tag is associated with
4669  * @tag: value of the S-tag to delete
4670  * @tags_used: return value, number of tags in use by this PF
4671  * @tags_free: return value, number of unallocated tags
4672  * @cmd_details: pointer to command details structure or NULL
4673  *
4674  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4675  * the number of tags allocated by the PF, and the number of unallocated
4676  * tags available.
4677  **/
4678 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4679                                 u16 tag, u16 *tags_used, u16 *tags_free,
4680                                 struct i40e_asq_cmd_details *cmd_details)
4681 {
4682         struct i40e_aq_desc desc;
4683         struct i40e_aqc_remove_tag *cmd =
4684                 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4685         struct i40e_aqc_add_remove_tag_completion *resp =
4686                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4687         enum i40e_status_code status;
4688
4689         if (vsi_seid == 0)
4690                 return I40E_ERR_PARAM;
4691
4692         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4693
4694         cmd->seid = CPU_TO_LE16(vsi_seid);
4695         cmd->tag = CPU_TO_LE16(tag);
4696
4697         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4698
4699         if (!status) {
4700                 if (tags_used != NULL)
4701                         *tags_used = LE16_TO_CPU(resp->tags_used);
4702                 if (tags_free != NULL)
4703                         *tags_free = LE16_TO_CPU(resp->tags_free);
4704         }
4705
4706         return status;
4707 }
4708
4709 /**
4710  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4711  * @hw: pointer to the hw struct
4712  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4713  * @etag: value of E-tag to add
4714  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4715  * @buf: address of indirect buffer
4716  * @tags_used: return value, number of E-tags in use by this port
4717  * @tags_free: return value, number of unallocated M-tags
4718  * @cmd_details: pointer to command details structure or NULL
4719  *
4720  * This associates a multicast E-tag to a port virtualizer.  It will return
4721  * the number of tags allocated by the PF, and the number of unallocated
4722  * tags available.
4723  *
4724  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4725  * num_tags_in_buf long.
4726  **/
4727 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4728                                 u16 etag, u8 num_tags_in_buf, void *buf,
4729                                 u16 *tags_used, u16 *tags_free,
4730                                 struct i40e_asq_cmd_details *cmd_details)
4731 {
4732         struct i40e_aq_desc desc;
4733         struct i40e_aqc_add_remove_mcast_etag *cmd =
4734                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4735         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4736            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4737         enum i40e_status_code status;
4738         u16 length = sizeof(u16) * num_tags_in_buf;
4739
4740         if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4741                 return I40E_ERR_PARAM;
4742
4743         i40e_fill_default_direct_cmd_desc(&desc,
4744                                           i40e_aqc_opc_add_multicast_etag);
4745
4746         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4747         cmd->etag = CPU_TO_LE16(etag);
4748         cmd->num_unicast_etags = num_tags_in_buf;
4749
4750         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4751         if (length > I40E_AQ_LARGE_BUF)
4752                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4753
4754         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4755
4756         if (!status) {
4757                 if (tags_used != NULL)
4758                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4759                 if (tags_free != NULL)
4760                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4761         }
4762
4763         return status;
4764 }
4765
4766 /**
4767  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4768  * @hw: pointer to the hw struct
4769  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4770  * @etag: value of the E-tag to remove
4771  * @tags_used: return value, number of tags in use by this port
4772  * @tags_free: return value, number of unallocated tags
4773  * @cmd_details: pointer to command details structure or NULL
4774  *
4775  * This deletes an E-tag from the port virtualizer.  It will return
4776  * the number of tags allocated by the port, and the number of unallocated
4777  * tags available.
4778  **/
4779 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4780                                 u16 etag, u16 *tags_used, u16 *tags_free,
4781                                 struct i40e_asq_cmd_details *cmd_details)
4782 {
4783         struct i40e_aq_desc desc;
4784         struct i40e_aqc_add_remove_mcast_etag *cmd =
4785                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4786         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4787            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4788         enum i40e_status_code status;
4789
4790
4791         if (pv_seid == 0)
4792                 return I40E_ERR_PARAM;
4793
4794         i40e_fill_default_direct_cmd_desc(&desc,
4795                                           i40e_aqc_opc_remove_multicast_etag);
4796
4797         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4798         cmd->etag = CPU_TO_LE16(etag);
4799
4800         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4801
4802         if (!status) {
4803                 if (tags_used != NULL)
4804                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4805                 if (tags_free != NULL)
4806                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4807         }
4808
4809         return status;
4810 }
4811
4812 /**
4813  * i40e_aq_update_tag - Update an S/E-tag
4814  * @hw: pointer to the hw struct
4815  * @vsi_seid: VSI SEID using this S-tag
4816  * @old_tag: old tag value
4817  * @new_tag: new tag value
4818  * @tags_used: return value, number of tags in use by this PF
4819  * @tags_free: return value, number of unallocated tags
4820  * @cmd_details: pointer to command details structure or NULL
4821  *
4822  * This updates the value of the tag currently attached to this VSI
4823  * in the switch complex.  It will return the number of tags allocated
4824  * by the PF, and the number of unallocated tags available.
4825  **/
4826 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4827                                 u16 old_tag, u16 new_tag, u16 *tags_used,
4828                                 u16 *tags_free,
4829                                 struct i40e_asq_cmd_details *cmd_details)
4830 {
4831         struct i40e_aq_desc desc;
4832         struct i40e_aqc_update_tag *cmd =
4833                 (struct i40e_aqc_update_tag *)&desc.params.raw;
4834         struct i40e_aqc_update_tag_completion *resp =
4835                 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4836         enum i40e_status_code status;
4837
4838         if (vsi_seid == 0)
4839                 return I40E_ERR_PARAM;
4840
4841         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4842
4843         cmd->seid = CPU_TO_LE16(vsi_seid);
4844         cmd->old_tag = CPU_TO_LE16(old_tag);
4845         cmd->new_tag = CPU_TO_LE16(new_tag);
4846
4847         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4848
4849         if (!status) {
4850                 if (tags_used != NULL)
4851                         *tags_used = LE16_TO_CPU(resp->tags_used);
4852                 if (tags_free != NULL)
4853                         *tags_free = LE16_TO_CPU(resp->tags_free);
4854         }
4855
4856         return status;
4857 }
4858
4859 /**
4860  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4861  * @hw: pointer to the hw struct
4862  * @tcmap: TC map for request/release any ignore PFC condition
4863  * @request: request or release ignore PFC condition
4864  * @tcmap_ret: return TCs for which PFC is currently ignored
4865  * @cmd_details: pointer to command details structure or NULL
4866  *
4867  * This sends out request/release to ignore PFC condition for a TC.
4868  * It will return the TCs for which PFC is currently ignored.
4869  **/
4870 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4871                                 bool request, u8 *tcmap_ret,
4872                                 struct i40e_asq_cmd_details *cmd_details)
4873 {
4874         struct i40e_aq_desc desc;
4875         struct i40e_aqc_pfc_ignore *cmd_resp =
4876                 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4877         enum i40e_status_code status;
4878
4879         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4880
4881         if (request)
4882                 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4883
4884         cmd_resp->tc_bitmap = tcmap;
4885
4886         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4887
4888         if (!status) {
4889                 if (tcmap_ret != NULL)
4890                         *tcmap_ret = cmd_resp->tc_bitmap;
4891         }
4892
4893         return status;
4894 }
4895
4896 /**
4897  * i40e_aq_dcb_updated - DCB Updated Command
4898  * @hw: pointer to the hw struct
4899  * @cmd_details: pointer to command details structure or NULL
4900  *
4901  * When LLDP is handled in PF this command is used by the PF
4902  * to notify EMP that a DCB setting is modified.
4903  * When LLDP is handled in EMP this command is used by the PF
4904  * to notify EMP whenever one of the following parameters get
4905  * modified:
4906  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4907  *   - PCIRTT in PRTDCB_GENC.PCIRTT
4908  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4909  * EMP will return when the shared RPB settings have been
4910  * recomputed and modified. The retval field in the descriptor
4911  * will be set to 0 when RPB is modified.
4912  **/
4913 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4914                                 struct i40e_asq_cmd_details *cmd_details)
4915 {
4916         struct i40e_aq_desc desc;
4917         enum i40e_status_code status;
4918
4919         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4920
4921         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4922
4923         return status;
4924 }
4925
4926 /**
4927  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4928  * @hw: pointer to the hw struct
4929  * @seid: defines the SEID of the switch for which the stats are requested
4930  * @vlan_id: the VLAN ID for which the statistics are requested
4931  * @stat_index: index of the statistics counters block assigned to this VLAN
4932  * @cmd_details: pointer to command details structure or NULL
4933  *
4934  * XL710 supports 128 smonVlanStats counters.This command is used to
4935  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4936  * switch.
4937  **/
4938 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4939                                 u16 vlan_id, u16 *stat_index,
4940                                 struct i40e_asq_cmd_details *cmd_details)
4941 {
4942         struct i40e_aq_desc desc;
4943         struct i40e_aqc_add_remove_statistics *cmd_resp =
4944                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4945         enum i40e_status_code status;
4946
4947         if ((seid == 0) || (stat_index == NULL))
4948                 return I40E_ERR_PARAM;
4949
4950         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4951
4952         cmd_resp->seid = CPU_TO_LE16(seid);
4953         cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4954
4955         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4956
4957         if (!status && stat_index)
4958                 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4959
4960         return status;
4961 }
4962
4963 /**
4964  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4965  * @hw: pointer to the hw struct
4966  * @seid: defines the SEID of the switch for which the stats are requested
4967  * @vlan_id: the VLAN ID for which the statistics are requested
4968  * @stat_index: index of the statistics counters block assigned to this VLAN
4969  * @cmd_details: pointer to command details structure or NULL
4970  *
4971  * XL710 supports 128 smonVlanStats counters.This command is used to
4972  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4973  * switch.
4974  **/
4975 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4976                                 u16 vlan_id, u16 stat_index,
4977                                 struct i40e_asq_cmd_details *cmd_details)
4978 {
4979         struct i40e_aq_desc desc;
4980         struct i40e_aqc_add_remove_statistics *cmd =
4981                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4982         enum i40e_status_code status;
4983
4984         if (seid == 0)
4985                 return I40E_ERR_PARAM;
4986
4987         i40e_fill_default_direct_cmd_desc(&desc,
4988                                           i40e_aqc_opc_remove_statistics);
4989
4990         cmd->seid = CPU_TO_LE16(seid);
4991         cmd->vlan  = CPU_TO_LE16(vlan_id);
4992         cmd->stat_index = CPU_TO_LE16(stat_index);
4993
4994         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4995
4996         return status;
4997 }
4998
4999 /**
5000  * i40e_aq_set_port_parameters - set physical port parameters.
5001  * @hw: pointer to the hw struct
5002  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
5003  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
5004  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
5005  * @double_vlan: if set double VLAN is enabled
5006  * @cmd_details: pointer to command details structure or NULL
5007  **/
5008 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
5009                                 u16 bad_frame_vsi, bool save_bad_pac,
5010                                 bool pad_short_pac, bool double_vlan,
5011                                 struct i40e_asq_cmd_details *cmd_details)
5012 {
5013         struct i40e_aqc_set_port_parameters *cmd;
5014         enum i40e_status_code status;
5015         struct i40e_aq_desc desc;
5016         u16 command_flags = 0;
5017
5018         cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
5019
5020         i40e_fill_default_direct_cmd_desc(&desc,
5021                                           i40e_aqc_opc_set_port_parameters);
5022
5023         cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
5024         if (save_bad_pac)
5025                 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
5026         if (pad_short_pac)
5027                 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
5028         if (double_vlan)
5029                 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
5030         cmd->command_flags = CPU_TO_LE16(command_flags);
5031
5032         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5033
5034         return status;
5035 }
5036
5037 /**
5038  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
5039  * @hw: pointer to the hw struct
5040  * @seid: seid for the physical port/switching component/vsi
5041  * @buff: Indirect buffer to hold data parameters and response
5042  * @buff_size: Indirect buffer size
5043  * @opcode: Tx scheduler AQ command opcode
5044  * @cmd_details: pointer to command details structure or NULL
5045  *
5046  * Generic command handler for Tx scheduler AQ commands
5047  **/
5048 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
5049                                 void *buff, u16 buff_size,
5050                                  enum i40e_admin_queue_opc opcode,
5051                                 struct i40e_asq_cmd_details *cmd_details)
5052 {
5053         struct i40e_aq_desc desc;
5054         struct i40e_aqc_tx_sched_ind *cmd =
5055                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
5056         enum i40e_status_code status;
5057         bool cmd_param_flag = false;
5058
5059         switch (opcode) {
5060         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
5061         case i40e_aqc_opc_configure_vsi_tc_bw:
5062         case i40e_aqc_opc_enable_switching_comp_ets:
5063         case i40e_aqc_opc_modify_switching_comp_ets:
5064         case i40e_aqc_opc_disable_switching_comp_ets:
5065         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
5066         case i40e_aqc_opc_configure_switching_comp_bw_config:
5067                 cmd_param_flag = true;
5068                 break;
5069         case i40e_aqc_opc_query_vsi_bw_config:
5070         case i40e_aqc_opc_query_vsi_ets_sla_config:
5071         case i40e_aqc_opc_query_switching_comp_ets_config:
5072         case i40e_aqc_opc_query_port_ets_config:
5073         case i40e_aqc_opc_query_switching_comp_bw_config:
5074                 cmd_param_flag = false;
5075                 break;
5076         default:
5077                 return I40E_ERR_PARAM;
5078         }
5079
5080         i40e_fill_default_direct_cmd_desc(&desc, opcode);
5081
5082         /* Indirect command */
5083         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5084         if (cmd_param_flag)
5085                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5086         if (buff_size > I40E_AQ_LARGE_BUF)
5087                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5088
5089         desc.datalen = CPU_TO_LE16(buff_size);
5090
5091         cmd->vsi_seid = CPU_TO_LE16(seid);
5092
5093         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5094
5095         return status;
5096 }
5097
5098 /**
5099  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5100  * @hw: pointer to the hw struct
5101  * @seid: VSI seid
5102  * @credit: BW limit credits (0 = disabled)
5103  * @max_credit: Max BW limit credits
5104  * @cmd_details: pointer to command details structure or NULL
5105  **/
5106 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5107                                 u16 seid, u16 credit, u8 max_credit,
5108                                 struct i40e_asq_cmd_details *cmd_details)
5109 {
5110         struct i40e_aq_desc desc;
5111         struct i40e_aqc_configure_vsi_bw_limit *cmd =
5112                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5113         enum i40e_status_code status;
5114
5115         i40e_fill_default_direct_cmd_desc(&desc,
5116                                           i40e_aqc_opc_configure_vsi_bw_limit);
5117
5118         cmd->vsi_seid = CPU_TO_LE16(seid);
5119         cmd->credit = CPU_TO_LE16(credit);
5120         cmd->max_credit = max_credit;
5121
5122         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5123
5124         return status;
5125 }
5126
5127 /**
5128  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5129  * @hw: pointer to the hw struct
5130  * @seid: switching component seid
5131  * @credit: BW limit credits (0 = disabled)
5132  * @max_bw: Max BW limit credits
5133  * @cmd_details: pointer to command details structure or NULL
5134  **/
5135 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5136                                 u16 seid, u16 credit, u8 max_bw,
5137                                 struct i40e_asq_cmd_details *cmd_details)
5138 {
5139         struct i40e_aq_desc desc;
5140         struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5141           (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5142         enum i40e_status_code status;
5143
5144         i40e_fill_default_direct_cmd_desc(&desc,
5145                                 i40e_aqc_opc_configure_switching_comp_bw_limit);
5146
5147         cmd->seid = CPU_TO_LE16(seid);
5148         cmd->credit = CPU_TO_LE16(credit);
5149         cmd->max_bw = max_bw;
5150
5151         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5152
5153         return status;
5154 }
5155
5156 /**
5157  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5158  * @hw: pointer to the hw struct
5159  * @seid: VSI seid
5160  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5161  * @cmd_details: pointer to command details structure or NULL
5162  **/
5163 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5164                         u16 seid,
5165                         struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5166                         struct i40e_asq_cmd_details *cmd_details)
5167 {
5168         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5169                                     i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5170                                     cmd_details);
5171 }
5172
5173 /**
5174  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5175  * @hw: pointer to the hw struct
5176  * @seid: VSI seid
5177  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5178  * @cmd_details: pointer to command details structure or NULL
5179  **/
5180 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5181                         u16 seid,
5182                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5183                         struct i40e_asq_cmd_details *cmd_details)
5184 {
5185         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5186                                     i40e_aqc_opc_configure_vsi_tc_bw,
5187                                     cmd_details);
5188 }
5189
5190 /**
5191  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5192  * @hw: pointer to the hw struct
5193  * @seid: seid of the switching component connected to Physical Port
5194  * @ets_data: Buffer holding ETS parameters
5195  * @cmd_details: pointer to command details structure or NULL
5196  **/
5197 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5198                 u16 seid,
5199                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5200                 enum i40e_admin_queue_opc opcode,
5201                 struct i40e_asq_cmd_details *cmd_details)
5202 {
5203         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5204                                     sizeof(*ets_data), opcode, cmd_details);
5205 }
5206
5207 /**
5208  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5209  * @hw: pointer to the hw struct
5210  * @seid: seid of the switching component
5211  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5212  * @cmd_details: pointer to command details structure or NULL
5213  **/
5214 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5215         u16 seid,
5216         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5217         struct i40e_asq_cmd_details *cmd_details)
5218 {
5219         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5220                             i40e_aqc_opc_configure_switching_comp_bw_config,
5221                             cmd_details);
5222 }
5223
5224 /**
5225  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5226  * @hw: pointer to the hw struct
5227  * @seid: seid of the switching component
5228  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5229  * @cmd_details: pointer to command details structure or NULL
5230  **/
5231 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5232         struct i40e_hw *hw, u16 seid,
5233         struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5234         struct i40e_asq_cmd_details *cmd_details)
5235 {
5236         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5237                             i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5238                             cmd_details);
5239 }
5240
5241 /**
5242  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5243  * @hw: pointer to the hw struct
5244  * @seid: seid of the VSI
5245  * @bw_data: Buffer to hold VSI BW configuration
5246  * @cmd_details: pointer to command details structure or NULL
5247  **/
5248 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5249                         u16 seid,
5250                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5251                         struct i40e_asq_cmd_details *cmd_details)
5252 {
5253         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5254                                     i40e_aqc_opc_query_vsi_bw_config,
5255                                     cmd_details);
5256 }
5257
5258 /**
5259  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5260  * @hw: pointer to the hw struct
5261  * @seid: seid of the VSI
5262  * @bw_data: Buffer to hold VSI BW configuration per TC
5263  * @cmd_details: pointer to command details structure or NULL
5264  **/
5265 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5266                         u16 seid,
5267                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5268                         struct i40e_asq_cmd_details *cmd_details)
5269 {
5270         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5271                                     i40e_aqc_opc_query_vsi_ets_sla_config,
5272                                     cmd_details);
5273 }
5274
5275 /**
5276  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5277  * @hw: pointer to the hw struct
5278  * @seid: seid of the switching component
5279  * @bw_data: Buffer to hold switching component's per TC BW config
5280  * @cmd_details: pointer to command details structure or NULL
5281  **/
5282 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5283                 u16 seid,
5284                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5285                 struct i40e_asq_cmd_details *cmd_details)
5286 {
5287         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5288                                    i40e_aqc_opc_query_switching_comp_ets_config,
5289                                    cmd_details);
5290 }
5291
5292 /**
5293  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5294  * @hw: pointer to the hw struct
5295  * @seid: seid of the VSI or switching component connected to Physical Port
5296  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5297  * @cmd_details: pointer to command details structure or NULL
5298  **/
5299 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5300                         u16 seid,
5301                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
5302                         struct i40e_asq_cmd_details *cmd_details)
5303 {
5304         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5305                                     i40e_aqc_opc_query_port_ets_config,
5306                                     cmd_details);
5307 }
5308
5309 /**
5310  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5311  * @hw: pointer to the hw struct
5312  * @seid: seid of the switching component
5313  * @bw_data: Buffer to hold switching component's BW configuration
5314  * @cmd_details: pointer to command details structure or NULL
5315  **/
5316 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5317                 u16 seid,
5318                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5319                 struct i40e_asq_cmd_details *cmd_details)
5320 {
5321         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5322                                     i40e_aqc_opc_query_switching_comp_bw_config,
5323                                     cmd_details);
5324 }
5325
5326 /**
5327  * i40e_validate_filter_settings
5328  * @hw: pointer to the hardware structure
5329  * @settings: Filter control settings
5330  *
5331  * Check and validate the filter control settings passed.
5332  * The function checks for the valid filter/context sizes being
5333  * passed for FCoE and PE.
5334  *
5335  * Returns I40E_SUCCESS if the values passed are valid and within
5336  * range else returns an error.
5337  **/
5338 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5339                                 struct i40e_filter_control_settings *settings)
5340 {
5341         u32 fcoe_cntx_size, fcoe_filt_size;
5342         u32 pe_cntx_size, pe_filt_size;
5343         u32 fcoe_fmax;
5344
5345         u32 val;
5346
5347         /* Validate FCoE settings passed */
5348         switch (settings->fcoe_filt_num) {
5349         case I40E_HASH_FILTER_SIZE_1K:
5350         case I40E_HASH_FILTER_SIZE_2K:
5351         case I40E_HASH_FILTER_SIZE_4K:
5352         case I40E_HASH_FILTER_SIZE_8K:
5353         case I40E_HASH_FILTER_SIZE_16K:
5354         case I40E_HASH_FILTER_SIZE_32K:
5355                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5356                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5357                 break;
5358         default:
5359                 return I40E_ERR_PARAM;
5360         }
5361
5362         switch (settings->fcoe_cntx_num) {
5363         case I40E_DMA_CNTX_SIZE_512:
5364         case I40E_DMA_CNTX_SIZE_1K:
5365         case I40E_DMA_CNTX_SIZE_2K:
5366         case I40E_DMA_CNTX_SIZE_4K:
5367                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5368                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5369                 break;
5370         default:
5371                 return I40E_ERR_PARAM;
5372         }
5373
5374         /* Validate PE settings passed */
5375         switch (settings->pe_filt_num) {
5376         case I40E_HASH_FILTER_SIZE_1K:
5377         case I40E_HASH_FILTER_SIZE_2K:
5378         case I40E_HASH_FILTER_SIZE_4K:
5379         case I40E_HASH_FILTER_SIZE_8K:
5380         case I40E_HASH_FILTER_SIZE_16K:
5381         case I40E_HASH_FILTER_SIZE_32K:
5382         case I40E_HASH_FILTER_SIZE_64K:
5383         case I40E_HASH_FILTER_SIZE_128K:
5384         case I40E_HASH_FILTER_SIZE_256K:
5385         case I40E_HASH_FILTER_SIZE_512K:
5386         case I40E_HASH_FILTER_SIZE_1M:
5387                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5388                 pe_filt_size <<= (u32)settings->pe_filt_num;
5389                 break;
5390         default:
5391                 return I40E_ERR_PARAM;
5392         }
5393
5394         switch (settings->pe_cntx_num) {
5395         case I40E_DMA_CNTX_SIZE_512:
5396         case I40E_DMA_CNTX_SIZE_1K:
5397         case I40E_DMA_CNTX_SIZE_2K:
5398         case I40E_DMA_CNTX_SIZE_4K:
5399         case I40E_DMA_CNTX_SIZE_8K:
5400         case I40E_DMA_CNTX_SIZE_16K:
5401         case I40E_DMA_CNTX_SIZE_32K:
5402         case I40E_DMA_CNTX_SIZE_64K:
5403         case I40E_DMA_CNTX_SIZE_128K:
5404         case I40E_DMA_CNTX_SIZE_256K:
5405                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5406                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5407                 break;
5408         default:
5409                 return I40E_ERR_PARAM;
5410         }
5411
5412         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5413         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5414         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5415                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5416         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
5417                 return I40E_ERR_INVALID_SIZE;
5418
5419         return I40E_SUCCESS;
5420 }
5421
5422 /**
5423  * i40e_set_filter_control
5424  * @hw: pointer to the hardware structure
5425  * @settings: Filter control settings
5426  *
5427  * Set the Queue Filters for PE/FCoE and enable filters required
5428  * for a single PF. It is expected that these settings are programmed
5429  * at the driver initialization time.
5430  **/
5431 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5432                                 struct i40e_filter_control_settings *settings)
5433 {
5434         enum i40e_status_code ret = I40E_SUCCESS;
5435         u32 hash_lut_size = 0;
5436         u32 val;
5437
5438         if (!settings)
5439                 return I40E_ERR_PARAM;
5440
5441         /* Validate the input settings */
5442         ret = i40e_validate_filter_settings(hw, settings);
5443         if (ret)
5444                 return ret;
5445
5446         /* Read the PF Queue Filter control register */
5447         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5448
5449         /* Program required PE hash buckets for the PF */
5450         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5451         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5452                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5453         /* Program required PE contexts for the PF */
5454         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5455         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5456                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5457
5458         /* Program required FCoE hash buckets for the PF */
5459         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5460         val |= ((u32)settings->fcoe_filt_num <<
5461                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5462                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5463         /* Program required FCoE DDP contexts for the PF */
5464         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5465         val |= ((u32)settings->fcoe_cntx_num <<
5466                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5467                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5468
5469         /* Program Hash LUT size for the PF */
5470         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5471         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5472                 hash_lut_size = 1;
5473         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5474                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5475
5476         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5477         if (settings->enable_fdir)
5478                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5479         if (settings->enable_ethtype)
5480                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5481         if (settings->enable_macvlan)
5482                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5483
5484         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5485
5486         return I40E_SUCCESS;
5487 }
5488
5489 /**
5490  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5491  * @hw: pointer to the hw struct
5492  * @mac_addr: MAC address to use in the filter
5493  * @ethtype: Ethertype to use in the filter
5494  * @flags: Flags that needs to be applied to the filter
5495  * @vsi_seid: seid of the control VSI
5496  * @queue: VSI queue number to send the packet to
5497  * @is_add: Add control packet filter if True else remove
5498  * @stats: Structure to hold information on control filter counts
5499  * @cmd_details: pointer to command details structure or NULL
5500  *
5501  * This command will Add or Remove control packet filter for a control VSI.
5502  * In return it will update the total number of perfect filter count in
5503  * the stats member.
5504  **/
5505 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5506                                 u8 *mac_addr, u16 ethtype, u16 flags,
5507                                 u16 vsi_seid, u16 queue, bool is_add,
5508                                 struct i40e_control_filter_stats *stats,
5509                                 struct i40e_asq_cmd_details *cmd_details)
5510 {
5511         struct i40e_aq_desc desc;
5512         struct i40e_aqc_add_remove_control_packet_filter *cmd =
5513                 (struct i40e_aqc_add_remove_control_packet_filter *)
5514                 &desc.params.raw;
5515         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5516                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5517                 &desc.params.raw;
5518         enum i40e_status_code status;
5519
5520         if (vsi_seid == 0)
5521                 return I40E_ERR_PARAM;
5522
5523         if (is_add) {
5524                 i40e_fill_default_direct_cmd_desc(&desc,
5525                                 i40e_aqc_opc_add_control_packet_filter);
5526                 cmd->queue = CPU_TO_LE16(queue);
5527         } else {
5528                 i40e_fill_default_direct_cmd_desc(&desc,
5529                                 i40e_aqc_opc_remove_control_packet_filter);
5530         }
5531
5532         if (mac_addr)
5533                 i40e_memcpy(cmd->mac, mac_addr, ETH_ALEN,
5534                             I40E_NONDMA_TO_NONDMA);
5535
5536         cmd->etype = CPU_TO_LE16(ethtype);
5537         cmd->flags = CPU_TO_LE16(flags);
5538         cmd->seid = CPU_TO_LE16(vsi_seid);
5539
5540         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5541
5542         if (!status && stats) {
5543                 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5544                 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5545                 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5546                 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5547         }
5548
5549         return status;
5550 }
5551
5552 /**
5553  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5554  * @hw: pointer to the hw struct
5555  * @seid: VSI seid to add ethertype filter from
5556  **/
5557 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5558 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5559                                                     u16 seid)
5560 {
5561         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5562                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5563                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5564         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5565         enum i40e_status_code status;
5566
5567         status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5568                                                        seid, 0, true, NULL,
5569                                                        NULL);
5570         if (status)
5571                 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5572 }
5573
5574 /**
5575  * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5576  * @filters: list of cloud filters
5577  * @filter_count: length of list
5578  *
5579  * There's an issue in the device where the Geneve VNI layout needs
5580  * to be shifted 1 byte over from the VxLAN VNI
5581  **/
5582 STATIC void i40e_fix_up_geneve_vni(
5583         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5584         u8 filter_count)
5585 {
5586         struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters;
5587         int i;
5588
5589         for (i = 0; i < filter_count; i++) {
5590                 u16 tnl_type;
5591                 u32 ti;
5592
5593                 tnl_type = (LE16_TO_CPU(f[i].flags) &
5594                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5595                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5596                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5597                         ti = LE32_TO_CPU(f[i].tenant_id);
5598                         f[i].tenant_id = CPU_TO_LE32(ti << 8);
5599                 }
5600         }
5601 }
5602
5603 /**
5604  * i40e_aq_add_cloud_filters
5605  * @hw: pointer to the hardware structure
5606  * @seid: VSI seid to add cloud filters from
5607  * @filters: Buffer which contains the filters to be added
5608  * @filter_count: number of filters contained in the buffer
5609  *
5610  * Set the cloud filters for a given VSI.  The contents of the
5611  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5612  * in by the caller of the function.
5613  *
5614  **/
5615 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5616         u16 seid,
5617         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5618         u8 filter_count)
5619 {
5620         struct i40e_aq_desc desc;
5621         struct i40e_aqc_add_remove_cloud_filters *cmd =
5622         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5623         enum i40e_status_code status;
5624         u16 buff_len;
5625
5626         i40e_fill_default_direct_cmd_desc(&desc,
5627                                           i40e_aqc_opc_add_cloud_filters);
5628
5629         buff_len = filter_count * sizeof(*filters);
5630         desc.datalen = CPU_TO_LE16(buff_len);
5631         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5632         cmd->num_filters = filter_count;
5633         cmd->seid = CPU_TO_LE16(seid);
5634
5635         i40e_fix_up_geneve_vni(filters, filter_count);
5636
5637         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5638
5639         return status;
5640 }
5641
5642 /**
5643  * i40e_aq_add_cloud_filters_big_buffer
5644  * @hw: pointer to the hardware structure
5645  * @seid: VSI seid to add cloud filters from
5646  * @filters: Buffer which contains the filters in big buffer to be added
5647  * @filter_count: number of filters contained in the buffer
5648  *
5649  * Set the cloud filters for a given VSI.  The contents of the
5650  * i40e_aqc_add_rm_cloud_filt_elem_ext are filled in by the caller of
5651  * the function.
5652  *
5653  **/
5654 enum i40e_status_code i40e_aq_add_cloud_filters_big_buffer(struct i40e_hw *hw,
5655         u16 seid,
5656         struct i40e_aqc_add_rm_cloud_filt_elem_ext *filters,
5657         u8 filter_count)
5658 {
5659         struct i40e_aq_desc desc;
5660         struct i40e_aqc_add_remove_cloud_filters *cmd =
5661         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5662         enum i40e_status_code status;
5663         u16 buff_len;
5664         int i;
5665
5666         i40e_fill_default_direct_cmd_desc(&desc,
5667                                           i40e_aqc_opc_add_cloud_filters);
5668
5669         buff_len = filter_count * sizeof(*filters);
5670         desc.datalen = CPU_TO_LE16(buff_len);
5671         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5672         cmd->num_filters = filter_count;
5673         cmd->seid = CPU_TO_LE16(seid);
5674         cmd->big_buffer_flag = I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER;
5675
5676         /* adjust Geneve VNI for HW issue */
5677         for (i = 0; i < filter_count; i++) {
5678                 u16 tnl_type;
5679                 u32 ti;
5680
5681                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5682                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5683                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5684                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5685                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5686                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5687                 }
5688         }
5689
5690         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5691
5692         return status;
5693 }
5694
5695 /**
5696  * i40e_aq_remove_cloud_filters
5697  * @hw: pointer to the hardware structure
5698  * @seid: VSI seid to remove cloud filters from
5699  * @filters: Buffer which contains the filters to be removed
5700  * @filter_count: number of filters contained in the buffer
5701  *
5702  * Remove the cloud filters for a given VSI.  The contents of the
5703  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5704  * in by the caller of the function.
5705  *
5706  **/
5707 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5708         u16 seid,
5709         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5710         u8 filter_count)
5711 {
5712         struct i40e_aq_desc desc;
5713         struct i40e_aqc_add_remove_cloud_filters *cmd =
5714         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5715         enum i40e_status_code status;
5716         u16 buff_len;
5717
5718         i40e_fill_default_direct_cmd_desc(&desc,
5719                                           i40e_aqc_opc_remove_cloud_filters);
5720
5721         buff_len = filter_count * sizeof(*filters);
5722         desc.datalen = CPU_TO_LE16(buff_len);
5723         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5724         cmd->num_filters = filter_count;
5725         cmd->seid = CPU_TO_LE16(seid);
5726
5727         i40e_fix_up_geneve_vni(filters, filter_count);
5728
5729         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5730
5731         return status;
5732 }
5733
5734 /**
5735  * i40e_aq_remove_cloud_filters_big_buffer
5736  * @hw: pointer to the hardware structure
5737  * @seid: VSI seid to remove cloud filters from
5738  * @filters: Buffer which contains the filters in big buffer to be removed
5739  * @filter_count: number of filters contained in the buffer
5740  *
5741  * Remove the cloud filters for a given VSI.  The contents of the
5742  * i40e_aqc_add_rm_cloud_filt_elem_ext are filled in by the caller of
5743  * the function.
5744  *
5745  **/
5746 enum i40e_status_code i40e_aq_remove_cloud_filters_big_buffer(
5747         struct i40e_hw *hw,
5748         u16 seid,
5749         struct i40e_aqc_add_rm_cloud_filt_elem_ext *filters,
5750         u8 filter_count)
5751 {
5752         struct i40e_aq_desc desc;
5753         struct i40e_aqc_add_remove_cloud_filters *cmd =
5754         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5755         enum i40e_status_code status;
5756         u16 buff_len;
5757         int i;
5758
5759         i40e_fill_default_direct_cmd_desc(&desc,
5760                                           i40e_aqc_opc_remove_cloud_filters);
5761
5762         buff_len = filter_count * sizeof(*filters);
5763         desc.datalen = CPU_TO_LE16(buff_len);
5764         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5765         cmd->num_filters = filter_count;
5766         cmd->seid = CPU_TO_LE16(seid);
5767         cmd->big_buffer_flag = I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER;
5768
5769         /* adjust Geneve VNI for HW issue */
5770         for (i = 0; i < filter_count; i++) {
5771                 u16 tnl_type;
5772                 u32 ti;
5773
5774                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5775                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5776                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5777                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5778                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5779                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5780                 }
5781         }
5782
5783         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5784
5785         return status;
5786 }
5787
5788 /**
5789  * i40e_aq_replace_cloud_filters - Replace cloud filter command
5790  * @hw: pointer to the hw struct
5791  * @filters: pointer to the i40e_aqc_replace_cloud_filter_cmd struct
5792  * @cmd_buf: pointer to the i40e_aqc_replace_cloud_filter_cmd_buf struct
5793  *
5794  **/
5795 enum
5796 i40e_status_code i40e_aq_replace_cloud_filters(struct i40e_hw *hw,
5797         struct i40e_aqc_replace_cloud_filters_cmd *filters,
5798         struct i40e_aqc_replace_cloud_filters_cmd_buf *cmd_buf)
5799 {
5800         struct i40e_aq_desc desc;
5801         struct i40e_aqc_replace_cloud_filters_cmd *cmd =
5802                 (struct i40e_aqc_replace_cloud_filters_cmd *)&desc.params.raw;
5803         enum i40e_status_code status = I40E_SUCCESS;
5804         int i = 0;
5805
5806         i40e_fill_default_direct_cmd_desc(&desc,
5807                                           i40e_aqc_opc_replace_cloud_filters);
5808
5809         desc.datalen = CPU_TO_LE16(32);
5810         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5811         cmd->old_filter_type = filters->old_filter_type;
5812         cmd->new_filter_type = filters->new_filter_type;
5813         cmd->valid_flags = filters->valid_flags;
5814         cmd->tr_bit = filters->tr_bit;
5815
5816         status = i40e_asq_send_command(hw, &desc, cmd_buf,
5817                 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf),  NULL);
5818
5819         /* for get cloud filters command */
5820         for (i = 0; i < 32; i += 4) {
5821                 cmd_buf->filters[i / 4].filter_type = cmd_buf->data[i];
5822                 cmd_buf->filters[i / 4].input[0] = cmd_buf->data[i + 1];
5823                 cmd_buf->filters[i / 4].input[1] = cmd_buf->data[i + 2];
5824                 cmd_buf->filters[i / 4].input[2] = cmd_buf->data[i + 3];
5825         }
5826
5827         return status;
5828 }
5829
5830
5831 /**
5832  * i40e_aq_alternate_write
5833  * @hw: pointer to the hardware structure
5834  * @reg_addr0: address of first dword to be read
5835  * @reg_val0: value to be written under 'reg_addr0'
5836  * @reg_addr1: address of second dword to be read
5837  * @reg_val1: value to be written under 'reg_addr1'
5838  *
5839  * Write one or two dwords to alternate structure. Fields are indicated
5840  * by 'reg_addr0' and 'reg_addr1' register numbers.
5841  *
5842  **/
5843 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5844                                 u32 reg_addr0, u32 reg_val0,
5845                                 u32 reg_addr1, u32 reg_val1)
5846 {
5847         struct i40e_aq_desc desc;
5848         struct i40e_aqc_alternate_write *cmd_resp =
5849                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5850         enum i40e_status_code status;
5851
5852         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5853         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5854         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5855         cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5856         cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5857
5858         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5859
5860         return status;
5861 }
5862
5863 /**
5864  * i40e_aq_alternate_write_indirect
5865  * @hw: pointer to the hardware structure
5866  * @addr: address of a first register to be modified
5867  * @dw_count: number of alternate structure fields to write
5868  * @buffer: pointer to the command buffer
5869  *
5870  * Write 'dw_count' dwords from 'buffer' to alternate structure
5871  * starting at 'addr'.
5872  *
5873  **/
5874 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5875                                 u32 addr, u32 dw_count, void *buffer)
5876 {
5877         struct i40e_aq_desc desc;
5878         struct i40e_aqc_alternate_ind_write *cmd_resp =
5879                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5880         enum i40e_status_code status;
5881
5882         if (buffer == NULL)
5883                 return I40E_ERR_PARAM;
5884
5885         /* Indirect command */
5886         i40e_fill_default_direct_cmd_desc(&desc,
5887                                          i40e_aqc_opc_alternate_write_indirect);
5888
5889         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5890         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5891         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5892                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5893
5894         cmd_resp->address = CPU_TO_LE32(addr);
5895         cmd_resp->length = CPU_TO_LE32(dw_count);
5896
5897         status = i40e_asq_send_command(hw, &desc, buffer,
5898                                        I40E_LO_DWORD(4*dw_count), NULL);
5899
5900         return status;
5901 }
5902
5903 /**
5904  * i40e_aq_alternate_read
5905  * @hw: pointer to the hardware structure
5906  * @reg_addr0: address of first dword to be read
5907  * @reg_val0: pointer for data read from 'reg_addr0'
5908  * @reg_addr1: address of second dword to be read
5909  * @reg_val1: pointer for data read from 'reg_addr1'
5910  *
5911  * Read one or two dwords from alternate structure. Fields are indicated
5912  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5913  * is not passed then only register at 'reg_addr0' is read.
5914  *
5915  **/
5916 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5917                                 u32 reg_addr0, u32 *reg_val0,
5918                                 u32 reg_addr1, u32 *reg_val1)
5919 {
5920         struct i40e_aq_desc desc;
5921         struct i40e_aqc_alternate_write *cmd_resp =
5922                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5923         enum i40e_status_code status;
5924
5925         if (reg_val0 == NULL)
5926                 return I40E_ERR_PARAM;
5927
5928         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5929         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5930         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5931
5932         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5933
5934         if (status == I40E_SUCCESS) {
5935                 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5936
5937                 if (reg_val1 != NULL)
5938                         *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5939         }
5940
5941         return status;
5942 }
5943
5944 /**
5945  * i40e_aq_alternate_read_indirect
5946  * @hw: pointer to the hardware structure
5947  * @addr: address of the alternate structure field
5948  * @dw_count: number of alternate structure fields to read
5949  * @buffer: pointer to the command buffer
5950  *
5951  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5952  * place them in 'buffer'. The buffer should be allocated by caller.
5953  *
5954  **/
5955 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5956                                 u32 addr, u32 dw_count, void *buffer)
5957 {
5958         struct i40e_aq_desc desc;
5959         struct i40e_aqc_alternate_ind_write *cmd_resp =
5960                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5961         enum i40e_status_code status;
5962
5963         if (buffer == NULL)
5964                 return I40E_ERR_PARAM;
5965
5966         /* Indirect command */
5967         i40e_fill_default_direct_cmd_desc(&desc,
5968                 i40e_aqc_opc_alternate_read_indirect);
5969
5970         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5971         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5972         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5973                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5974
5975         cmd_resp->address = CPU_TO_LE32(addr);
5976         cmd_resp->length = CPU_TO_LE32(dw_count);
5977
5978         status = i40e_asq_send_command(hw, &desc, buffer,
5979                                        I40E_LO_DWORD(4*dw_count), NULL);
5980
5981         return status;
5982 }
5983
5984 /**
5985  *  i40e_aq_alternate_clear
5986  *  @hw: pointer to the HW structure.
5987  *
5988  *  Clear the alternate structures of the port from which the function
5989  *  is called.
5990  *
5991  **/
5992 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5993 {
5994         struct i40e_aq_desc desc;
5995         enum i40e_status_code status;
5996
5997         i40e_fill_default_direct_cmd_desc(&desc,
5998                                           i40e_aqc_opc_alternate_clear_port);
5999
6000         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6001
6002         return status;
6003 }
6004
6005 /**
6006  *  i40e_aq_alternate_write_done
6007  *  @hw: pointer to the HW structure.
6008  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
6009  *  @reset_needed: indicates the SW should trigger GLOBAL reset
6010  *
6011  *  Indicates to the FW that alternate structures have been changed.
6012  *
6013  **/
6014 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
6015                 u8 bios_mode, bool *reset_needed)
6016 {
6017         struct i40e_aq_desc desc;
6018         struct i40e_aqc_alternate_write_done *cmd =
6019                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6020         enum i40e_status_code status;
6021
6022         if (reset_needed == NULL)
6023                 return I40E_ERR_PARAM;
6024
6025         i40e_fill_default_direct_cmd_desc(&desc,
6026                                           i40e_aqc_opc_alternate_write_done);
6027
6028         cmd->cmd_flags = CPU_TO_LE16(bios_mode);
6029
6030         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6031         if (!status && reset_needed)
6032                 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
6033                                  I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
6034
6035         return status;
6036 }
6037
6038 /**
6039  *  i40e_aq_set_oem_mode
6040  *  @hw: pointer to the HW structure.
6041  *  @oem_mode: the OEM mode to be used
6042  *
6043  *  Sets the device to a specific operating mode. Currently the only supported
6044  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
6045  *
6046  **/
6047 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
6048                 u8 oem_mode)
6049 {
6050         struct i40e_aq_desc desc;
6051         struct i40e_aqc_alternate_write_done *cmd =
6052                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6053         enum i40e_status_code status;
6054
6055         i40e_fill_default_direct_cmd_desc(&desc,
6056                                           i40e_aqc_opc_alternate_set_mode);
6057
6058         cmd->cmd_flags = CPU_TO_LE16(oem_mode);
6059
6060         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6061
6062         return status;
6063 }
6064
6065 /**
6066  * i40e_aq_resume_port_tx
6067  * @hw: pointer to the hardware structure
6068  * @cmd_details: pointer to command details structure or NULL
6069  *
6070  * Resume port's Tx traffic
6071  **/
6072 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
6073                                 struct i40e_asq_cmd_details *cmd_details)
6074 {
6075         struct i40e_aq_desc desc;
6076         enum i40e_status_code status;
6077
6078         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
6079
6080         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6081
6082         return status;
6083 }
6084
6085 /**
6086  * i40e_set_pci_config_data - store PCI bus info
6087  * @hw: pointer to hardware structure
6088  * @link_status: the link status word from PCI config space
6089  *
6090  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
6091  **/
6092 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
6093 {
6094         hw->bus.type = i40e_bus_type_pci_express;
6095
6096         switch (link_status & I40E_PCI_LINK_WIDTH) {
6097         case I40E_PCI_LINK_WIDTH_1:
6098                 hw->bus.width = i40e_bus_width_pcie_x1;
6099                 break;
6100         case I40E_PCI_LINK_WIDTH_2:
6101                 hw->bus.width = i40e_bus_width_pcie_x2;
6102                 break;
6103         case I40E_PCI_LINK_WIDTH_4:
6104                 hw->bus.width = i40e_bus_width_pcie_x4;
6105                 break;
6106         case I40E_PCI_LINK_WIDTH_8:
6107                 hw->bus.width = i40e_bus_width_pcie_x8;
6108                 break;
6109         default:
6110                 hw->bus.width = i40e_bus_width_unknown;
6111                 break;
6112         }
6113
6114         switch (link_status & I40E_PCI_LINK_SPEED) {
6115         case I40E_PCI_LINK_SPEED_2500:
6116                 hw->bus.speed = i40e_bus_speed_2500;
6117                 break;
6118         case I40E_PCI_LINK_SPEED_5000:
6119                 hw->bus.speed = i40e_bus_speed_5000;
6120                 break;
6121         case I40E_PCI_LINK_SPEED_8000:
6122                 hw->bus.speed = i40e_bus_speed_8000;
6123                 break;
6124         default:
6125                 hw->bus.speed = i40e_bus_speed_unknown;
6126                 break;
6127         }
6128 }
6129
6130 /**
6131  * i40e_aq_debug_dump
6132  * @hw: pointer to the hardware structure
6133  * @cluster_id: specific cluster to dump
6134  * @table_id: table id within cluster
6135  * @start_index: index of line in the block to read
6136  * @buff_size: dump buffer size
6137  * @buff: dump buffer
6138  * @ret_buff_size: actual buffer size returned
6139  * @ret_next_table: next block to read
6140  * @ret_next_index: next index to read
6141  *
6142  * Dump internal FW/HW data for debug purposes.
6143  *
6144  **/
6145 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
6146                                 u8 table_id, u32 start_index, u16 buff_size,
6147                                 void *buff, u16 *ret_buff_size,
6148                                 u8 *ret_next_table, u32 *ret_next_index,
6149                                 struct i40e_asq_cmd_details *cmd_details)
6150 {
6151         struct i40e_aq_desc desc;
6152         struct i40e_aqc_debug_dump_internals *cmd =
6153                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6154         struct i40e_aqc_debug_dump_internals *resp =
6155                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6156         enum i40e_status_code status;
6157
6158         if (buff_size == 0 || !buff)
6159                 return I40E_ERR_PARAM;
6160
6161         i40e_fill_default_direct_cmd_desc(&desc,
6162                                           i40e_aqc_opc_debug_dump_internals);
6163         /* Indirect Command */
6164         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6165         if (buff_size > I40E_AQ_LARGE_BUF)
6166                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6167
6168         cmd->cluster_id = cluster_id;
6169         cmd->table_id = table_id;
6170         cmd->idx = CPU_TO_LE32(start_index);
6171
6172         desc.datalen = CPU_TO_LE16(buff_size);
6173
6174         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
6175         if (!status) {
6176                 if (ret_buff_size != NULL)
6177                         *ret_buff_size = LE16_TO_CPU(desc.datalen);
6178                 if (ret_next_table != NULL)
6179                         *ret_next_table = resp->table_id;
6180                 if (ret_next_index != NULL)
6181                         *ret_next_index = LE32_TO_CPU(resp->idx);
6182         }
6183
6184         return status;
6185 }
6186
6187 /**
6188  * i40e_read_bw_from_alt_ram
6189  * @hw: pointer to the hardware structure
6190  * @max_bw: pointer for max_bw read
6191  * @min_bw: pointer for min_bw read
6192  * @min_valid: pointer for bool that is true if min_bw is a valid value
6193  * @max_valid: pointer for bool that is true if max_bw is a valid value
6194  *
6195  * Read bw from the alternate ram for the given pf
6196  **/
6197 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
6198                                         u32 *max_bw, u32 *min_bw,
6199                                         bool *min_valid, bool *max_valid)
6200 {
6201         enum i40e_status_code status;
6202         u32 max_bw_addr, min_bw_addr;
6203
6204         /* Calculate the address of the min/max bw registers */
6205         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6206                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
6207                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6208         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6209                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
6210                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6211
6212         /* Read the bandwidths from alt ram */
6213         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
6214                                         min_bw_addr, min_bw);
6215
6216         if (*min_bw & I40E_ALT_BW_VALID_MASK)
6217                 *min_valid = true;
6218         else
6219                 *min_valid = false;
6220
6221         if (*max_bw & I40E_ALT_BW_VALID_MASK)
6222                 *max_valid = true;
6223         else
6224                 *max_valid = false;
6225
6226         return status;
6227 }
6228
6229 /**
6230  * i40e_aq_configure_partition_bw
6231  * @hw: pointer to the hardware structure
6232  * @bw_data: Buffer holding valid pfs and bw limits
6233  * @cmd_details: pointer to command details
6234  *
6235  * Configure partitions guaranteed/max bw
6236  **/
6237 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6238                         struct i40e_aqc_configure_partition_bw_data *bw_data,
6239                         struct i40e_asq_cmd_details *cmd_details)
6240 {
6241         enum i40e_status_code status;
6242         struct i40e_aq_desc desc;
6243         u16 bwd_size = sizeof(*bw_data);
6244
6245         i40e_fill_default_direct_cmd_desc(&desc,
6246                                 i40e_aqc_opc_configure_partition_bw);
6247
6248         /* Indirect command */
6249         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6250         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6251
6252         desc.datalen = CPU_TO_LE16(bwd_size);
6253
6254         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6255
6256         return status;
6257 }
6258
6259 /**
6260  * i40e_read_phy_register_clause22
6261  * @hw: pointer to the HW structure
6262  * @reg: register address in the page
6263  * @phy_adr: PHY address on MDIO interface
6264  * @value: PHY register value
6265  *
6266  * Reads specified PHY register value
6267  **/
6268 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
6269                                         u16 reg, u8 phy_addr, u16 *value)
6270 {
6271         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6272         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6273         u32 command = 0;
6274         u16 retry = 1000;
6275
6276         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6277                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6278                   (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
6279                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6280                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6281         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6282         do {
6283                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6284                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6285                         status = I40E_SUCCESS;
6286                         break;
6287                 }
6288                 i40e_usec_delay(10);
6289                 retry--;
6290         } while (retry);
6291
6292         if (status) {
6293                 i40e_debug(hw, I40E_DEBUG_PHY,
6294                            "PHY: Can't write command to external PHY.\n");
6295         } else {
6296                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6297                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6298                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6299         }
6300
6301         return status;
6302 }
6303
6304 /**
6305  * i40e_write_phy_register_clause22
6306  * @hw: pointer to the HW structure
6307  * @reg: register address in the page
6308  * @phy_adr: PHY address on MDIO interface
6309  * @value: PHY register value
6310  *
6311  * Writes specified PHY register value
6312  **/
6313 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6314                                         u16 reg, u8 phy_addr, u16 value)
6315 {
6316         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6317         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6318         u32 command  = 0;
6319         u16 retry = 1000;
6320
6321         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6322         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6323
6324         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6325                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6326                   (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6327                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6328                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6329
6330         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6331         do {
6332                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6333                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6334                         status = I40E_SUCCESS;
6335                         break;
6336                 }
6337                 i40e_usec_delay(10);
6338                 retry--;
6339         } while (retry);
6340
6341         return status;
6342 }
6343
6344 /**
6345  * i40e_read_phy_register_clause45
6346  * @hw: pointer to the HW structure
6347  * @page: registers page number
6348  * @reg: register address in the page
6349  * @phy_adr: PHY address on MDIO interface
6350  * @value: PHY register value
6351  *
6352  * Reads specified PHY register value
6353  **/
6354 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6355                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6356 {
6357         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6358         u32 command  = 0;
6359         u16 retry = 1000;
6360         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6361
6362         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6363                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6364                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6365                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6366                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6367                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6368                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6369         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6370         do {
6371                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6372                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6373                         status = I40E_SUCCESS;
6374                         break;
6375                 }
6376                 i40e_usec_delay(10);
6377                 retry--;
6378         } while (retry);
6379
6380         if (status) {
6381                 i40e_debug(hw, I40E_DEBUG_PHY,
6382                            "PHY: Can't write command to external PHY.\n");
6383                 goto phy_read_end;
6384         }
6385
6386         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6387                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6388                   (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6389                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6390                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6391                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6392         status = I40E_ERR_TIMEOUT;
6393         retry = 1000;
6394         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6395         do {
6396                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6397                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6398                         status = I40E_SUCCESS;
6399                         break;
6400                 }
6401                 i40e_usec_delay(10);
6402                 retry--;
6403         } while (retry);
6404
6405         if (!status) {
6406                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6407                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6408                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6409         } else {
6410                 i40e_debug(hw, I40E_DEBUG_PHY,
6411                            "PHY: Can't read register value from external PHY.\n");
6412         }
6413
6414 phy_read_end:
6415         return status;
6416 }
6417
6418 /**
6419  * i40e_write_phy_register_clause45
6420  * @hw: pointer to the HW structure
6421  * @page: registers page number
6422  * @reg: register address in the page
6423  * @phy_adr: PHY address on MDIO interface
6424  * @value: PHY register value
6425  *
6426  * Writes value to specified PHY register
6427  **/
6428 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6429                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6430 {
6431         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6432         u32 command  = 0;
6433         u16 retry = 1000;
6434         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6435
6436         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6437                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6438                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6439                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6440                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6441                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6442                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6443         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6444         do {
6445                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6446                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6447                         status = I40E_SUCCESS;
6448                         break;
6449                 }
6450                 i40e_usec_delay(10);
6451                 retry--;
6452         } while (retry);
6453         if (status) {
6454                 i40e_debug(hw, I40E_DEBUG_PHY,
6455                            "PHY: Can't write command to external PHY.\n");
6456                 goto phy_write_end;
6457         }
6458
6459         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6460         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6461
6462         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6463                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6464                   (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6465                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6466                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6467                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6468         status = I40E_ERR_TIMEOUT;
6469         retry = 1000;
6470         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6471         do {
6472                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6473                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6474                         status = I40E_SUCCESS;
6475                         break;
6476                 }
6477                 i40e_usec_delay(10);
6478                 retry--;
6479         } while (retry);
6480
6481 phy_write_end:
6482         return status;
6483 }
6484
6485 /**
6486  * i40e_write_phy_register
6487  * @hw: pointer to the HW structure
6488  * @page: registers page number
6489  * @reg: register address in the page
6490  * @phy_adr: PHY address on MDIO interface
6491  * @value: PHY register value
6492  *
6493  * Writes value to specified PHY register
6494  **/
6495 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6496                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6497 {
6498         enum i40e_status_code status;
6499
6500         switch (hw->device_id) {
6501         case I40E_DEV_ID_1G_BASE_T_X722:
6502                 status = i40e_write_phy_register_clause22(hw,
6503                         reg, phy_addr, value);
6504                 break;
6505         case I40E_DEV_ID_10G_BASE_T:
6506         case I40E_DEV_ID_10G_BASE_T4:
6507         case I40E_DEV_ID_10G_BASE_T_X722:
6508         case I40E_DEV_ID_25G_B:
6509         case I40E_DEV_ID_25G_SFP28:
6510                 status = i40e_write_phy_register_clause45(hw,
6511                         page, reg, phy_addr, value);
6512                 break;
6513         default:
6514                 status = I40E_ERR_UNKNOWN_PHY;
6515                 break;
6516         }
6517
6518         return status;
6519 }
6520
6521 /**
6522  * i40e_read_phy_register
6523  * @hw: pointer to the HW structure
6524  * @page: registers page number
6525  * @reg: register address in the page
6526  * @phy_adr: PHY address on MDIO interface
6527  * @value: PHY register value
6528  *
6529  * Reads specified PHY register value
6530  **/
6531 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6532                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6533 {
6534         enum i40e_status_code status;
6535
6536         switch (hw->device_id) {
6537         case I40E_DEV_ID_1G_BASE_T_X722:
6538                 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6539                                                          value);
6540                 break;
6541         case I40E_DEV_ID_10G_BASE_T:
6542         case I40E_DEV_ID_10G_BASE_T4:
6543         case I40E_DEV_ID_10G_BASE_T_X722:
6544         case I40E_DEV_ID_25G_B:
6545         case I40E_DEV_ID_25G_SFP28:
6546                 status = i40e_read_phy_register_clause45(hw, page, reg,
6547                                                          phy_addr, value);
6548                 break;
6549         default:
6550                 status = I40E_ERR_UNKNOWN_PHY;
6551                 break;
6552         }
6553
6554         return status;
6555 }
6556
6557 /**
6558  * i40e_get_phy_address
6559  * @hw: pointer to the HW structure
6560  * @dev_num: PHY port num that address we want
6561  * @phy_addr: Returned PHY address
6562  *
6563  * Gets PHY address for current port
6564  **/
6565 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6566 {
6567         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6568         u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6569
6570         return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6571 }
6572
6573 /**
6574  * i40e_blink_phy_led
6575  * @hw: pointer to the HW structure
6576  * @time: time how long led will blinks in secs
6577  * @interval: gap between LED on and off in msecs
6578  *
6579  * Blinks PHY link LED
6580  **/
6581 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6582                                               u32 time, u32 interval)
6583 {
6584         enum i40e_status_code status = I40E_SUCCESS;
6585         u32 i;
6586         u16 led_ctl = 0;
6587         u16 gpio_led_port;
6588         u16 led_reg;
6589         u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6590         u8 phy_addr = 0;
6591         u8 port_num;
6592
6593         i = rd32(hw, I40E_PFGEN_PORTNUM);
6594         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6595         phy_addr = i40e_get_phy_address(hw, port_num);
6596
6597         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6598              led_addr++) {
6599                 status = i40e_read_phy_register_clause45(hw,
6600                                                          I40E_PHY_COM_REG_PAGE,
6601                                                          led_addr, phy_addr,
6602                                                          &led_reg);
6603                 if (status)
6604                         goto phy_blinking_end;
6605                 led_ctl = led_reg;
6606                 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6607                         led_reg = 0;
6608                         status = i40e_write_phy_register_clause45(hw,
6609                                                          I40E_PHY_COM_REG_PAGE,
6610                                                          led_addr, phy_addr,
6611                                                          led_reg);
6612                         if (status)
6613                                 goto phy_blinking_end;
6614                         break;
6615                 }
6616         }
6617
6618         if (time > 0 && interval > 0) {
6619                 for (i = 0; i < time * 1000; i += interval) {
6620                         status = i40e_read_phy_register_clause45(hw,
6621                                                 I40E_PHY_COM_REG_PAGE,
6622                                                 led_addr, phy_addr, &led_reg);
6623                         if (status)
6624                                 goto restore_config;
6625                         if (led_reg & I40E_PHY_LED_MANUAL_ON)
6626                                 led_reg = 0;
6627                         else
6628                                 led_reg = I40E_PHY_LED_MANUAL_ON;
6629                         status = i40e_write_phy_register_clause45(hw,
6630                                                 I40E_PHY_COM_REG_PAGE,
6631                                                 led_addr, phy_addr, led_reg);
6632                         if (status)
6633                                 goto restore_config;
6634                         i40e_msec_delay(interval);
6635                 }
6636         }
6637
6638 restore_config:
6639         status = i40e_write_phy_register_clause45(hw,
6640                                                   I40E_PHY_COM_REG_PAGE,
6641                                                   led_addr, phy_addr, led_ctl);
6642
6643 phy_blinking_end:
6644         return status;
6645 }
6646
6647 /**
6648  * i40e_led_get_phy - return current on/off mode
6649  * @hw: pointer to the hw struct
6650  * @led_addr: address of led register to use
6651  * @val: original value of register to use
6652  *
6653  **/
6654 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6655                                        u16 *val)
6656 {
6657         enum i40e_status_code status = I40E_SUCCESS;
6658         u16 gpio_led_port;
6659         u8 phy_addr = 0;
6660         u16 reg_val;
6661         u16 temp_addr;
6662         u8 port_num;
6663         u32 i;
6664
6665         temp_addr = I40E_PHY_LED_PROV_REG_1;
6666         i = rd32(hw, I40E_PFGEN_PORTNUM);
6667         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6668         phy_addr = i40e_get_phy_address(hw, port_num);
6669
6670         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6671              temp_addr++) {
6672                 status = i40e_read_phy_register_clause45(hw,
6673                                                          I40E_PHY_COM_REG_PAGE,
6674                                                          temp_addr, phy_addr,
6675                                                          &reg_val);
6676                 if (status)
6677                         return status;
6678                 *val = reg_val;
6679                 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6680                         *led_addr = temp_addr;
6681                         break;
6682                 }
6683         }
6684         return status;
6685 }
6686
6687 /**
6688  * i40e_led_set_phy
6689  * @hw: pointer to the HW structure
6690  * @on: true or false
6691  * @mode: original val plus bit for set or ignore
6692  * Set led's on or off when controlled by the PHY
6693  *
6694  **/
6695 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6696                                        u16 led_addr, u32 mode)
6697 {
6698         enum i40e_status_code status = I40E_SUCCESS;
6699         u16 led_ctl = 0;
6700         u16 led_reg = 0;
6701         u8 phy_addr = 0;
6702         u8 port_num;
6703         u32 i;
6704
6705         i = rd32(hw, I40E_PFGEN_PORTNUM);
6706         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6707         phy_addr = i40e_get_phy_address(hw, port_num);
6708         status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6709                                                  led_addr, phy_addr, &led_reg);
6710         if (status)
6711                 return status;
6712         led_ctl = led_reg;
6713         if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6714                 led_reg = 0;
6715                 status = i40e_write_phy_register_clause45(hw,
6716                                                           I40E_PHY_COM_REG_PAGE,
6717                                                           led_addr, phy_addr,
6718                                                           led_reg);
6719                 if (status)
6720                         return status;
6721         }
6722         status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6723                                                  led_addr, phy_addr, &led_reg);
6724         if (status)
6725                 goto restore_config;
6726         if (on)
6727                 led_reg = I40E_PHY_LED_MANUAL_ON;
6728         else
6729                 led_reg = 0;
6730         status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6731                                                   led_addr, phy_addr, led_reg);
6732         if (status)
6733                 goto restore_config;
6734         if (mode & I40E_PHY_LED_MODE_ORIG) {
6735                 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6736                 status = i40e_write_phy_register_clause45(hw,
6737                                                  I40E_PHY_COM_REG_PAGE,
6738                                                  led_addr, phy_addr, led_ctl);
6739         }
6740         return status;
6741 restore_config:
6742         status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6743                                                   led_addr, phy_addr, led_ctl);
6744         return status;
6745 }
6746 #endif /* PF_DRIVER */
6747
6748 /**
6749  * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6750  * @hw: pointer to the hw struct
6751  * @reg_addr: register address
6752  * @reg_val: ptr to register value
6753  * @cmd_details: pointer to command details structure or NULL
6754  *
6755  * Use the firmware to read the Rx control register,
6756  * especially useful if the Rx unit is under heavy pressure
6757  **/
6758 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6759                                 u32 reg_addr, u32 *reg_val,
6760                                 struct i40e_asq_cmd_details *cmd_details)
6761 {
6762         struct i40e_aq_desc desc;
6763         struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
6764                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6765         enum i40e_status_code status;
6766
6767         if (reg_val == NULL)
6768                 return I40E_ERR_PARAM;
6769
6770         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
6771
6772         cmd_resp->address = CPU_TO_LE32(reg_addr);
6773
6774         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6775
6776         if (status == I40E_SUCCESS)
6777                 *reg_val = LE32_TO_CPU(cmd_resp->value);
6778
6779         return status;
6780 }
6781
6782 /**
6783  * i40e_read_rx_ctl - read from an Rx control register
6784  * @hw: pointer to the hw struct
6785  * @reg_addr: register address
6786  **/
6787 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
6788 {
6789         enum i40e_status_code status = I40E_SUCCESS;
6790         bool use_register;
6791         int retry = 5;
6792         u32 val = 0;
6793
6794         use_register = (((hw->aq.api_maj_ver == 1) &&
6795                         (hw->aq.api_min_ver < 5)) ||
6796                         (hw->mac.type == I40E_MAC_X722));
6797         if (!use_register) {
6798 do_retry:
6799                 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
6800                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6801                         i40e_msec_delay(1);
6802                         retry--;
6803                         goto do_retry;
6804                 }
6805         }
6806
6807         /* if the AQ access failed, try the old-fashioned way */
6808         if (status || use_register)
6809                 val = rd32(hw, reg_addr);
6810
6811         return val;
6812 }
6813
6814 /**
6815  * i40e_aq_rx_ctl_write_register
6816  * @hw: pointer to the hw struct
6817  * @reg_addr: register address
6818  * @reg_val: register value
6819  * @cmd_details: pointer to command details structure or NULL
6820  *
6821  * Use the firmware to write to an Rx control register,
6822  * especially useful if the Rx unit is under heavy pressure
6823  **/
6824 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
6825                                 u32 reg_addr, u32 reg_val,
6826                                 struct i40e_asq_cmd_details *cmd_details)
6827 {
6828         struct i40e_aq_desc desc;
6829         struct i40e_aqc_rx_ctl_reg_read_write *cmd =
6830                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6831         enum i40e_status_code status;
6832
6833         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
6834
6835         cmd->address = CPU_TO_LE32(reg_addr);
6836         cmd->value = CPU_TO_LE32(reg_val);
6837
6838         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6839
6840         return status;
6841 }
6842
6843 /**
6844  * i40e_write_rx_ctl - write to an Rx control register
6845  * @hw: pointer to the hw struct
6846  * @reg_addr: register address
6847  * @reg_val: register value
6848  **/
6849 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
6850 {
6851         enum i40e_status_code status = I40E_SUCCESS;
6852         bool use_register;
6853         int retry = 5;
6854
6855         use_register = (((hw->aq.api_maj_ver == 1) &&
6856                         (hw->aq.api_min_ver < 5)) ||
6857                         (hw->mac.type == I40E_MAC_X722));
6858         if (!use_register) {
6859 do_retry:
6860                 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
6861                                                        reg_val, NULL);
6862                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6863                         i40e_msec_delay(1);
6864                         retry--;
6865                         goto do_retry;
6866                 }
6867         }
6868
6869         /* if the AQ access failed, try the old-fashioned way */
6870         if (status || use_register)
6871                 wr32(hw, reg_addr, reg_val);
6872 }
6873
6874 /**
6875  * i40e_aq_set_phy_register
6876  * @hw: pointer to the hw struct
6877  * @phy_select: select which phy should be accessed
6878  * @dev_addr: PHY device address
6879  * @reg_addr: PHY register address
6880  * @reg_val: new register value
6881  * @cmd_details: pointer to command details structure or NULL
6882  *
6883  * Write the external PHY register.
6884  **/
6885 enum i40e_status_code i40e_aq_set_phy_register(struct i40e_hw *hw,
6886                                 u8 phy_select, u8 dev_addr,
6887                                 u32 reg_addr, u32 reg_val,
6888                                 struct i40e_asq_cmd_details *cmd_details)
6889 {
6890         struct i40e_aq_desc desc;
6891         struct i40e_aqc_phy_register_access *cmd =
6892                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
6893         enum i40e_status_code status;
6894
6895         i40e_fill_default_direct_cmd_desc(&desc,
6896                                           i40e_aqc_opc_set_phy_register);
6897
6898         cmd->phy_interface = phy_select;
6899         cmd->dev_addres = dev_addr;
6900         cmd->reg_address = reg_addr;
6901         cmd->reg_value = reg_val;
6902
6903         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6904
6905         return status;
6906 }
6907
6908 /**
6909  * i40e_aq_get_phy_register
6910  * @hw: pointer to the hw struct
6911  * @phy_select: select which phy should be accessed
6912  * @dev_addr: PHY device address
6913  * @reg_addr: PHY register address
6914  * @reg_val: read register value
6915  * @cmd_details: pointer to command details structure or NULL
6916  *
6917  * Read the external PHY register.
6918  **/
6919 enum i40e_status_code i40e_aq_get_phy_register(struct i40e_hw *hw,
6920                                 u8 phy_select, u8 dev_addr,
6921                                 u32 reg_addr, u32 *reg_val,
6922                                 struct i40e_asq_cmd_details *cmd_details)
6923 {
6924         struct i40e_aq_desc desc;
6925         struct i40e_aqc_phy_register_access *cmd =
6926                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
6927         enum i40e_status_code status;
6928
6929         i40e_fill_default_direct_cmd_desc(&desc,
6930                                           i40e_aqc_opc_get_phy_register);
6931
6932         cmd->phy_interface = phy_select;
6933         cmd->dev_addres = dev_addr;
6934         cmd->reg_address = reg_addr;
6935
6936         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6937         if (!status)
6938                 *reg_val = cmd->reg_value;
6939
6940         return status;
6941 }
6942
6943 #ifdef VF_DRIVER
6944
6945 /**
6946  * i40e_aq_send_msg_to_pf
6947  * @hw: pointer to the hardware structure
6948  * @v_opcode: opcodes for VF-PF communication
6949  * @v_retval: return error code
6950  * @msg: pointer to the msg buffer
6951  * @msglen: msg length
6952  * @cmd_details: pointer to command details
6953  *
6954  * Send message to PF driver using admin queue. By default, this message
6955  * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
6956  * completion before returning.
6957  **/
6958 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
6959                                 enum virtchnl_ops v_opcode,
6960                                 enum i40e_status_code v_retval,
6961                                 u8 *msg, u16 msglen,
6962                                 struct i40e_asq_cmd_details *cmd_details)
6963 {
6964         struct i40e_aq_desc desc;
6965         struct i40e_asq_cmd_details details;
6966         enum i40e_status_code status;
6967
6968         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
6969         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
6970         desc.cookie_high = CPU_TO_LE32(v_opcode);
6971         desc.cookie_low = CPU_TO_LE32(v_retval);
6972         if (msglen) {
6973                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
6974                                                 | I40E_AQ_FLAG_RD));
6975                 if (msglen > I40E_AQ_LARGE_BUF)
6976                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6977                 desc.datalen = CPU_TO_LE16(msglen);
6978         }
6979         if (!cmd_details) {
6980                 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
6981                 details.async = true;
6982                 cmd_details = &details;
6983         }
6984         status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
6985                                        msglen, cmd_details);
6986         return status;
6987 }
6988
6989 /**
6990  * i40e_vf_parse_hw_config
6991  * @hw: pointer to the hardware structure
6992  * @msg: pointer to the virtual channel VF resource structure
6993  *
6994  * Given a VF resource message from the PF, populate the hw struct
6995  * with appropriate information.
6996  **/
6997 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
6998                              struct virtchnl_vf_resource *msg)
6999 {
7000         struct virtchnl_vsi_resource *vsi_res;
7001         int i;
7002
7003         vsi_res = &msg->vsi_res[0];
7004
7005         hw->dev_caps.num_vsis = msg->num_vsis;
7006         hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
7007         hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
7008         hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
7009         hw->dev_caps.dcb = msg->vf_offload_flags &
7010                            VIRTCHNL_VF_OFFLOAD_L2;
7011         hw->dev_caps.iwarp = (msg->vf_offload_flags &
7012                               VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
7013         for (i = 0; i < msg->num_vsis; i++) {
7014                 if (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) {
7015                         i40e_memcpy(hw->mac.perm_addr,
7016                                     vsi_res->default_mac_addr,
7017                                     ETH_ALEN,
7018                                     I40E_NONDMA_TO_NONDMA);
7019                         i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
7020                                     ETH_ALEN,
7021                                     I40E_NONDMA_TO_NONDMA);
7022                 }
7023                 vsi_res++;
7024         }
7025 }
7026
7027 /**
7028  * i40e_vf_reset
7029  * @hw: pointer to the hardware structure
7030  *
7031  * Send a VF_RESET message to the PF. Does not wait for response from PF
7032  * as none will be forthcoming. Immediately after calling this function,
7033  * the admin queue should be shut down and (optionally) reinitialized.
7034  **/
7035 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
7036 {
7037         return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF,
7038                                       I40E_SUCCESS, NULL, 0, NULL);
7039 }
7040 #endif /* VF_DRIVER */
7041
7042 /**
7043  * i40e_aq_set_arp_proxy_config
7044  * @hw: pointer to the HW structure
7045  * @proxy_config - pointer to proxy config command table struct
7046  * @cmd_details: pointer to command details
7047  *
7048  * Set ARP offload parameters from pre-populated
7049  * i40e_aqc_arp_proxy_data struct
7050  **/
7051 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
7052                                 struct i40e_aqc_arp_proxy_data *proxy_config,
7053                                 struct i40e_asq_cmd_details *cmd_details)
7054 {
7055         struct i40e_aq_desc desc;
7056         enum i40e_status_code status;
7057
7058         if (!proxy_config)
7059                 return I40E_ERR_PARAM;
7060
7061         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
7062
7063         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7064         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7065         desc.params.external.addr_high =
7066                                   CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
7067         desc.params.external.addr_low =
7068                                   CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
7069         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_arp_proxy_data));
7070
7071         status = i40e_asq_send_command(hw, &desc, proxy_config,
7072                                        sizeof(struct i40e_aqc_arp_proxy_data),
7073                                        cmd_details);
7074
7075         return status;
7076 }
7077
7078 /**
7079  * i40e_aq_opc_set_ns_proxy_table_entry
7080  * @hw: pointer to the HW structure
7081  * @ns_proxy_table_entry: pointer to NS table entry command struct
7082  * @cmd_details: pointer to command details
7083  *
7084  * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
7085  * from pre-populated i40e_aqc_ns_proxy_data struct
7086  **/
7087 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
7088                         struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
7089                         struct i40e_asq_cmd_details *cmd_details)
7090 {
7091         struct i40e_aq_desc desc;
7092         enum i40e_status_code status;
7093
7094         if (!ns_proxy_table_entry)
7095                 return I40E_ERR_PARAM;
7096
7097         i40e_fill_default_direct_cmd_desc(&desc,
7098                                 i40e_aqc_opc_set_ns_proxy_table_entry);
7099
7100         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7101         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7102         desc.params.external.addr_high =
7103                 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
7104         desc.params.external.addr_low =
7105                 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
7106         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_ns_proxy_data));
7107
7108         status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
7109                                        sizeof(struct i40e_aqc_ns_proxy_data),
7110                                        cmd_details);
7111
7112         return status;
7113 }
7114
7115 /**
7116  * i40e_aq_set_clear_wol_filter
7117  * @hw: pointer to the hw struct
7118  * @filter_index: index of filter to modify (0-7)
7119  * @filter: buffer containing filter to be set
7120  * @set_filter: true to set filter, false to clear filter
7121  * @no_wol_tco: if true, pass through packets cannot cause wake-up
7122  *              if false, pass through packets may cause wake-up
7123  * @filter_valid: true if filter action is valid
7124  * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
7125  * @cmd_details: pointer to command details structure or NULL
7126  *
7127  * Set or clear WoL filter for port attached to the PF
7128  **/
7129 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
7130                                 u8 filter_index,
7131                                 struct i40e_aqc_set_wol_filter_data *filter,
7132                                 bool set_filter, bool no_wol_tco,
7133                                 bool filter_valid, bool no_wol_tco_valid,
7134                                 struct i40e_asq_cmd_details *cmd_details)
7135 {
7136         struct i40e_aq_desc desc;
7137         struct i40e_aqc_set_wol_filter *cmd =
7138                 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
7139         enum i40e_status_code status;
7140         u16 cmd_flags = 0;
7141         u16 valid_flags = 0;
7142         u16 buff_len = 0;
7143
7144         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
7145
7146         if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
7147                 return  I40E_ERR_PARAM;
7148         cmd->filter_index = CPU_TO_LE16(filter_index);
7149
7150         if (set_filter) {
7151                 if (!filter)
7152                         return  I40E_ERR_PARAM;
7153
7154                 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
7155                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR;
7156         }
7157
7158         if (no_wol_tco)
7159                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
7160         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
7161
7162         if (filter_valid)
7163                 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
7164         if (no_wol_tco_valid)
7165                 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
7166         cmd->valid_flags = CPU_TO_LE16(valid_flags);
7167
7168         buff_len = sizeof(*filter);
7169         desc.datalen = CPU_TO_LE16(buff_len);
7170
7171         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7172         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7173
7174         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
7175         cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
7176
7177         status = i40e_asq_send_command(hw, &desc, filter,
7178                                        buff_len, cmd_details);
7179
7180         return status;
7181 }
7182
7183 /**
7184  * i40e_aq_get_wake_event_reason
7185  * @hw: pointer to the hw struct
7186  * @wake_reason: return value, index of matching filter
7187  * @cmd_details: pointer to command details structure or NULL
7188  *
7189  * Get information for the reason of a Wake Up event
7190  **/
7191 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
7192                                 u16 *wake_reason,
7193                                 struct i40e_asq_cmd_details *cmd_details)
7194 {
7195         struct i40e_aq_desc desc;
7196         struct i40e_aqc_get_wake_reason_completion *resp =
7197                 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
7198         enum i40e_status_code status;
7199
7200         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
7201
7202         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7203
7204         if (status == I40E_SUCCESS)
7205                 *wake_reason = LE16_TO_CPU(resp->wake_reason);
7206
7207         return status;
7208 }
7209
7210 /**
7211 * i40e_aq_clear_all_wol_filters
7212 * @hw: pointer to the hw struct
7213 * @cmd_details: pointer to command details structure or NULL
7214 *
7215 * Get information for the reason of a Wake Up event
7216 **/
7217 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw,
7218         struct i40e_asq_cmd_details *cmd_details)
7219 {
7220         struct i40e_aq_desc desc;
7221         enum i40e_status_code status;
7222
7223         i40e_fill_default_direct_cmd_desc(&desc,
7224                                           i40e_aqc_opc_clear_all_wol_filters);
7225
7226         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7227
7228         return status;
7229 }
7230
7231
7232 /**
7233  * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
7234  * @hw: pointer to the hw struct
7235  * @buff: command buffer (size in bytes = buff_size)
7236  * @buff_size: buffer size in bytes
7237  * @track_id: package tracking id
7238  * @error_offset: returns error offset
7239  * @error_info: returns error information
7240  * @cmd_details: pointer to command details structure or NULL
7241  **/
7242 enum
7243 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
7244                                    u16 buff_size, u32 track_id,
7245                                    u32 *error_offset, u32 *error_info,
7246                                    struct i40e_asq_cmd_details *cmd_details)
7247 {
7248         struct i40e_aq_desc desc;
7249         struct i40e_aqc_write_personalization_profile *cmd =
7250                 (struct i40e_aqc_write_personalization_profile *)
7251                 &desc.params.raw;
7252         struct i40e_aqc_write_ddp_resp *resp;
7253         enum i40e_status_code status;
7254
7255         i40e_fill_default_direct_cmd_desc(&desc,
7256                                   i40e_aqc_opc_write_personalization_profile);
7257
7258         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
7259         if (buff_size > I40E_AQ_LARGE_BUF)
7260                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7261
7262         desc.datalen = CPU_TO_LE16(buff_size);
7263
7264         cmd->profile_track_id = CPU_TO_LE32(track_id);
7265
7266         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7267         if (!status) {
7268                 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
7269                 if (error_offset)
7270                         *error_offset = LE32_TO_CPU(resp->error_offset);
7271                 if (error_info)
7272                         *error_info = LE32_TO_CPU(resp->error_info);
7273         }
7274
7275         return status;
7276 }
7277
7278 /**
7279  * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
7280  * @hw: pointer to the hw struct
7281  * @buff: command buffer (size in bytes = buff_size)
7282  * @buff_size: buffer size in bytes
7283  * @cmd_details: pointer to command details structure or NULL
7284  **/
7285 enum
7286 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
7287                                       u16 buff_size, u8 flags,
7288                                       struct i40e_asq_cmd_details *cmd_details)
7289 {
7290         struct i40e_aq_desc desc;
7291         struct i40e_aqc_get_applied_profiles *cmd =
7292                 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
7293         enum i40e_status_code status;
7294
7295         i40e_fill_default_direct_cmd_desc(&desc,
7296                           i40e_aqc_opc_get_personalization_profile_list);
7297
7298         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7299         if (buff_size > I40E_AQ_LARGE_BUF)
7300                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7301         desc.datalen = CPU_TO_LE16(buff_size);
7302
7303         cmd->flags = flags;
7304
7305         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7306
7307         return status;
7308 }
7309
7310 /**
7311  * i40e_find_segment_in_package
7312  * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
7313  * @pkg_hdr: pointer to the package header to be searched
7314  *
7315  * This function searches a package file for a particular segment type. On
7316  * success it returns a pointer to the segment header, otherwise it will
7317  * return NULL.
7318  **/
7319 struct i40e_generic_seg_header *
7320 i40e_find_segment_in_package(u32 segment_type,
7321                              struct i40e_package_header *pkg_hdr)
7322 {
7323         struct i40e_generic_seg_header *segment;
7324         u32 i;
7325
7326         /* Search all package segments for the requested segment type */
7327         for (i = 0; i < pkg_hdr->segment_count; i++) {
7328                 segment =
7329                         (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
7330                          pkg_hdr->segment_offset[i]);
7331
7332                 if (segment->type == segment_type)
7333                         return segment;
7334         }
7335
7336         return NULL;
7337 }
7338
7339 /**
7340  * i40e_write_profile
7341  * @hw: pointer to the hardware structure
7342  * @profile: pointer to the profile segment of the package to be downloaded
7343  * @track_id: package tracking id
7344  *
7345  * Handles the download of a complete package.
7346  */
7347 enum i40e_status_code
7348 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7349                    u32 track_id)
7350 {
7351         enum i40e_status_code status = I40E_SUCCESS;
7352         struct i40e_section_table *sec_tbl;
7353         struct i40e_profile_section_header *sec = NULL;
7354         u32 dev_cnt;
7355         u32 vendor_dev_id;
7356         u32 *nvm;
7357         u32 section_size = 0;
7358         u32 offset = 0, info = 0;
7359         u32 i;
7360
7361         if (!track_id) {
7362                 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Track_id can't be 0.");
7363                 return I40E_NOT_SUPPORTED;
7364         }
7365
7366         dev_cnt = profile->device_table_count;
7367
7368         for (i = 0; i < dev_cnt; i++) {
7369                 vendor_dev_id = profile->device_table[i].vendor_dev_id;
7370                 if ((vendor_dev_id >> 16) == I40E_INTEL_VENDOR_ID)
7371                         if (hw->device_id == (vendor_dev_id & 0xFFFF))
7372                                 break;
7373         }
7374         if (i == dev_cnt) {
7375                 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Device doesn't support DDP");
7376                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
7377         }
7378
7379         nvm = (u32 *)&profile->device_table[dev_cnt];
7380         sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1];
7381
7382         for (i = 0; i < sec_tbl->section_count; i++) {
7383                 sec = (struct i40e_profile_section_header *)((u8 *)profile +
7384                                              sec_tbl->section_offset[i]);
7385
7386                 /* Skip 'AQ', 'note' and 'name' sections */
7387                 if (sec->section.type != SECTION_TYPE_MMIO)
7388                         continue;
7389
7390                 section_size = sec->section.size +
7391                         sizeof(struct i40e_profile_section_header);
7392
7393                 /* Write profile */
7394                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
7395                                            track_id, &offset, &info, NULL);
7396                 if (status) {
7397                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
7398                                    "Failed to write profile: offset %d, info %d",
7399                                    offset, info);
7400                         break;
7401                 }
7402         }
7403         return status;
7404 }
7405
7406 /**
7407  * i40e_add_pinfo_to_list
7408  * @hw: pointer to the hardware structure
7409  * @profile: pointer to the profile segment of the package
7410  * @profile_info_sec: buffer for information section
7411  * @track_id: package tracking id
7412  *
7413  * Register a profile to the list of loaded profiles.
7414  */
7415 enum i40e_status_code
7416 i40e_add_pinfo_to_list(struct i40e_hw *hw,
7417                        struct i40e_profile_segment *profile,
7418                        u8 *profile_info_sec, u32 track_id)
7419 {
7420         enum i40e_status_code status = I40E_SUCCESS;
7421         struct i40e_profile_section_header *sec = NULL;
7422         struct i40e_profile_info *pinfo;
7423         u32 offset = 0, info = 0;
7424
7425         sec = (struct i40e_profile_section_header *)profile_info_sec;
7426         sec->tbl_size = 1;
7427         sec->data_end = sizeof(struct i40e_profile_section_header) +
7428                         sizeof(struct i40e_profile_info);
7429         sec->section.type = SECTION_TYPE_INFO;
7430         sec->section.offset = sizeof(struct i40e_profile_section_header);
7431         sec->section.size = sizeof(struct i40e_profile_info);
7432         pinfo = (struct i40e_profile_info *)(profile_info_sec +
7433                                              sec->section.offset);
7434         pinfo->track_id = track_id;
7435         pinfo->version = profile->version;
7436         pinfo->op = I40E_DDP_ADD_TRACKID;
7437         memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE);
7438
7439         status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
7440                                 track_id, &offset, &info, NULL);
7441         return status;
7442 }