1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "i40e_type.h"
35 #include "i40e_adminq.h"
36 #include "i40e_prototype.h"
37 #include "i40e_virtchnl.h"
41 * i40e_set_mac_type - Sets MAC type
42 * @hw: pointer to the HW structure
44 * This function sets the mac type of the adapter based on the
45 * vendor ID and device ID stored in the hw structure.
47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
53 enum i40e_status_code status = I40E_SUCCESS;
55 DEBUGFUNC("i40e_set_mac_type\n");
57 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
58 switch (hw->device_id) {
59 case I40E_DEV_ID_SFP_XL710:
60 case I40E_DEV_ID_QEMU:
61 case I40E_DEV_ID_KX_A:
62 case I40E_DEV_ID_KX_B:
63 case I40E_DEV_ID_KX_C:
64 case I40E_DEV_ID_QSFP_A:
65 case I40E_DEV_ID_QSFP_B:
66 case I40E_DEV_ID_QSFP_C:
67 case I40E_DEV_ID_10G_BASE_T:
68 hw->mac.type = I40E_MAC_XL710;
71 case I40E_DEV_ID_VF_HV:
72 hw->mac.type = I40E_MAC_VF;
75 hw->mac.type = I40E_MAC_GENERIC;
79 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
82 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
83 hw->mac.type, status);
89 * @hw: debug mask related to admin queue
91 * @desc: pointer to admin queue descriptor
92 * @buffer: pointer to command buffer
93 * @buf_len: max length of buffer
95 * Dumps debug log about adminq command with descriptor contents.
97 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
98 void *buffer, u16 buf_len)
100 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
101 u16 len = LE16_TO_CPU(aq_desc->datalen);
102 u8 *buf = (u8 *)buffer;
105 if ((!(mask & hw->debug_mask)) || (desc == NULL))
109 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
110 LE16_TO_CPU(aq_desc->opcode),
111 LE16_TO_CPU(aq_desc->flags),
112 LE16_TO_CPU(aq_desc->datalen),
113 LE16_TO_CPU(aq_desc->retval));
114 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
115 LE32_TO_CPU(aq_desc->cookie_high),
116 LE32_TO_CPU(aq_desc->cookie_low));
117 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
118 LE32_TO_CPU(aq_desc->params.internal.param0),
119 LE32_TO_CPU(aq_desc->params.internal.param1));
120 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
121 LE32_TO_CPU(aq_desc->params.external.addr_high),
122 LE32_TO_CPU(aq_desc->params.external.addr_low));
124 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
125 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
128 /* write the full 16-byte chunks */
129 for (i = 0; i < (len - 16); i += 16)
131 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
132 i, buf[i], buf[i+1], buf[i+2], buf[i+3],
133 buf[i+4], buf[i+5], buf[i+6], buf[i+7],
134 buf[i+8], buf[i+9], buf[i+10], buf[i+11],
135 buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
136 /* write whatever's left over without overrunning the buffer */
141 memset(d_buf, 0, sizeof(d_buf));
142 j += sprintf(d_buf, "\t0x%04X ", i);
144 j += sprintf(&d_buf[j], " %02X", buf[i++]);
145 i40e_debug(hw, mask, "%s\n", d_buf);
151 * i40e_check_asq_alive
152 * @hw: pointer to the hw struct
154 * Returns true if Queue is enabled else false.
156 bool i40e_check_asq_alive(struct i40e_hw *hw)
159 return !!(rd32(hw, hw->aq.asq.len) & I40E_PF_ATQLEN_ATQENABLE_MASK);
165 * i40e_aq_queue_shutdown
166 * @hw: pointer to the hw struct
167 * @unloading: is the driver unloading itself
169 * Tell the Firmware that we're shutting down the AdminQ and whether
170 * or not the driver is unloading as well.
172 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
175 struct i40e_aq_desc desc;
176 struct i40e_aqc_queue_shutdown *cmd =
177 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
178 enum i40e_status_code status;
180 i40e_fill_default_direct_cmd_desc(&desc,
181 i40e_aqc_opc_queue_shutdown);
184 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
185 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
190 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
191 * hardware to a bit-field that can be used by SW to more easily determine the
194 * Macros are used to shorten the table lines and make this table human
197 * We store the PTYPE in the top byte of the bit field - this is just so that
198 * we can check that the table doesn't have a row missing, as the index into
199 * the table should be the PTYPE.
203 * IF NOT i40e_ptype_lookup[ptype].known
206 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
207 * Use the rest of the fields to look at the tunnels, inner protocols, etc
209 * Use the enum i40e_rx_l2_ptype to decode the packet type
213 /* macro to make the table lines short */
214 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
217 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
218 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
219 I40E_RX_PTYPE_##OUTER_FRAG, \
220 I40E_RX_PTYPE_TUNNEL_##T, \
221 I40E_RX_PTYPE_TUNNEL_END_##TE, \
222 I40E_RX_PTYPE_##TEF, \
223 I40E_RX_PTYPE_INNER_PROT_##I, \
224 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
226 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
227 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
229 /* shorter macros makes the table fit but are terse */
230 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
231 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
232 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
234 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
235 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
236 /* L2 Packet types */
237 I40E_PTT_UNUSED_ENTRY(0),
238 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
239 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
240 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
241 I40E_PTT_UNUSED_ENTRY(4),
242 I40E_PTT_UNUSED_ENTRY(5),
243 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
244 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
245 I40E_PTT_UNUSED_ENTRY(8),
246 I40E_PTT_UNUSED_ENTRY(9),
247 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
248 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
249 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
250 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
251 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
252 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
253 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
254 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
255 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
256 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
257 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
258 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
260 /* Non Tunneled IPv4 */
261 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
262 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
263 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
264 I40E_PTT_UNUSED_ENTRY(25),
265 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
266 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
267 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
270 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
271 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
272 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
273 I40E_PTT_UNUSED_ENTRY(32),
274 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
275 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
276 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
279 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
280 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
281 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
282 I40E_PTT_UNUSED_ENTRY(39),
283 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
284 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
285 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
287 /* IPv4 --> GRE/NAT */
288 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
290 /* IPv4 --> GRE/NAT --> IPv4 */
291 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
292 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
293 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
294 I40E_PTT_UNUSED_ENTRY(47),
295 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
296 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
297 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
299 /* IPv4 --> GRE/NAT --> IPv6 */
300 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
301 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
302 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
303 I40E_PTT_UNUSED_ENTRY(54),
304 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
305 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
306 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
308 /* IPv4 --> GRE/NAT --> MAC */
309 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
311 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
312 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
313 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
314 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
315 I40E_PTT_UNUSED_ENTRY(62),
316 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
317 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
318 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
320 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
321 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
322 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
323 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
324 I40E_PTT_UNUSED_ENTRY(69),
325 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
326 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
327 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
329 /* IPv4 --> GRE/NAT --> MAC/VLAN */
330 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
332 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
333 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
334 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
335 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
336 I40E_PTT_UNUSED_ENTRY(77),
337 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
338 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
339 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
341 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
342 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
343 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
344 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
345 I40E_PTT_UNUSED_ENTRY(84),
346 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
347 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
348 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
350 /* Non Tunneled IPv6 */
351 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
352 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
353 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
354 I40E_PTT_UNUSED_ENTRY(91),
355 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
356 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
357 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
360 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
361 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
362 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
363 I40E_PTT_UNUSED_ENTRY(98),
364 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
365 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
366 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
369 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
370 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
371 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
372 I40E_PTT_UNUSED_ENTRY(105),
373 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
374 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
375 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
377 /* IPv6 --> GRE/NAT */
378 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
380 /* IPv6 --> GRE/NAT -> IPv4 */
381 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
382 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
383 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
384 I40E_PTT_UNUSED_ENTRY(113),
385 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
386 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
387 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
389 /* IPv6 --> GRE/NAT -> IPv6 */
390 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
391 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
392 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
393 I40E_PTT_UNUSED_ENTRY(120),
394 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
395 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
396 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
398 /* IPv6 --> GRE/NAT -> MAC */
399 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
401 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
402 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
403 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
404 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
405 I40E_PTT_UNUSED_ENTRY(128),
406 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
407 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
408 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
410 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
411 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
412 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
413 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
414 I40E_PTT_UNUSED_ENTRY(135),
415 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
416 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
417 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
419 /* IPv6 --> GRE/NAT -> MAC/VLAN */
420 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
422 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
423 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
424 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
425 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
426 I40E_PTT_UNUSED_ENTRY(143),
427 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
428 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
429 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
431 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
432 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
433 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
434 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
435 I40E_PTT_UNUSED_ENTRY(150),
436 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
437 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
438 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
441 I40E_PTT_UNUSED_ENTRY(154),
442 I40E_PTT_UNUSED_ENTRY(155),
443 I40E_PTT_UNUSED_ENTRY(156),
444 I40E_PTT_UNUSED_ENTRY(157),
445 I40E_PTT_UNUSED_ENTRY(158),
446 I40E_PTT_UNUSED_ENTRY(159),
448 I40E_PTT_UNUSED_ENTRY(160),
449 I40E_PTT_UNUSED_ENTRY(161),
450 I40E_PTT_UNUSED_ENTRY(162),
451 I40E_PTT_UNUSED_ENTRY(163),
452 I40E_PTT_UNUSED_ENTRY(164),
453 I40E_PTT_UNUSED_ENTRY(165),
454 I40E_PTT_UNUSED_ENTRY(166),
455 I40E_PTT_UNUSED_ENTRY(167),
456 I40E_PTT_UNUSED_ENTRY(168),
457 I40E_PTT_UNUSED_ENTRY(169),
459 I40E_PTT_UNUSED_ENTRY(170),
460 I40E_PTT_UNUSED_ENTRY(171),
461 I40E_PTT_UNUSED_ENTRY(172),
462 I40E_PTT_UNUSED_ENTRY(173),
463 I40E_PTT_UNUSED_ENTRY(174),
464 I40E_PTT_UNUSED_ENTRY(175),
465 I40E_PTT_UNUSED_ENTRY(176),
466 I40E_PTT_UNUSED_ENTRY(177),
467 I40E_PTT_UNUSED_ENTRY(178),
468 I40E_PTT_UNUSED_ENTRY(179),
470 I40E_PTT_UNUSED_ENTRY(180),
471 I40E_PTT_UNUSED_ENTRY(181),
472 I40E_PTT_UNUSED_ENTRY(182),
473 I40E_PTT_UNUSED_ENTRY(183),
474 I40E_PTT_UNUSED_ENTRY(184),
475 I40E_PTT_UNUSED_ENTRY(185),
476 I40E_PTT_UNUSED_ENTRY(186),
477 I40E_PTT_UNUSED_ENTRY(187),
478 I40E_PTT_UNUSED_ENTRY(188),
479 I40E_PTT_UNUSED_ENTRY(189),
481 I40E_PTT_UNUSED_ENTRY(190),
482 I40E_PTT_UNUSED_ENTRY(191),
483 I40E_PTT_UNUSED_ENTRY(192),
484 I40E_PTT_UNUSED_ENTRY(193),
485 I40E_PTT_UNUSED_ENTRY(194),
486 I40E_PTT_UNUSED_ENTRY(195),
487 I40E_PTT_UNUSED_ENTRY(196),
488 I40E_PTT_UNUSED_ENTRY(197),
489 I40E_PTT_UNUSED_ENTRY(198),
490 I40E_PTT_UNUSED_ENTRY(199),
492 I40E_PTT_UNUSED_ENTRY(200),
493 I40E_PTT_UNUSED_ENTRY(201),
494 I40E_PTT_UNUSED_ENTRY(202),
495 I40E_PTT_UNUSED_ENTRY(203),
496 I40E_PTT_UNUSED_ENTRY(204),
497 I40E_PTT_UNUSED_ENTRY(205),
498 I40E_PTT_UNUSED_ENTRY(206),
499 I40E_PTT_UNUSED_ENTRY(207),
500 I40E_PTT_UNUSED_ENTRY(208),
501 I40E_PTT_UNUSED_ENTRY(209),
503 I40E_PTT_UNUSED_ENTRY(210),
504 I40E_PTT_UNUSED_ENTRY(211),
505 I40E_PTT_UNUSED_ENTRY(212),
506 I40E_PTT_UNUSED_ENTRY(213),
507 I40E_PTT_UNUSED_ENTRY(214),
508 I40E_PTT_UNUSED_ENTRY(215),
509 I40E_PTT_UNUSED_ENTRY(216),
510 I40E_PTT_UNUSED_ENTRY(217),
511 I40E_PTT_UNUSED_ENTRY(218),
512 I40E_PTT_UNUSED_ENTRY(219),
514 I40E_PTT_UNUSED_ENTRY(220),
515 I40E_PTT_UNUSED_ENTRY(221),
516 I40E_PTT_UNUSED_ENTRY(222),
517 I40E_PTT_UNUSED_ENTRY(223),
518 I40E_PTT_UNUSED_ENTRY(224),
519 I40E_PTT_UNUSED_ENTRY(225),
520 I40E_PTT_UNUSED_ENTRY(226),
521 I40E_PTT_UNUSED_ENTRY(227),
522 I40E_PTT_UNUSED_ENTRY(228),
523 I40E_PTT_UNUSED_ENTRY(229),
525 I40E_PTT_UNUSED_ENTRY(230),
526 I40E_PTT_UNUSED_ENTRY(231),
527 I40E_PTT_UNUSED_ENTRY(232),
528 I40E_PTT_UNUSED_ENTRY(233),
529 I40E_PTT_UNUSED_ENTRY(234),
530 I40E_PTT_UNUSED_ENTRY(235),
531 I40E_PTT_UNUSED_ENTRY(236),
532 I40E_PTT_UNUSED_ENTRY(237),
533 I40E_PTT_UNUSED_ENTRY(238),
534 I40E_PTT_UNUSED_ENTRY(239),
536 I40E_PTT_UNUSED_ENTRY(240),
537 I40E_PTT_UNUSED_ENTRY(241),
538 I40E_PTT_UNUSED_ENTRY(242),
539 I40E_PTT_UNUSED_ENTRY(243),
540 I40E_PTT_UNUSED_ENTRY(244),
541 I40E_PTT_UNUSED_ENTRY(245),
542 I40E_PTT_UNUSED_ENTRY(246),
543 I40E_PTT_UNUSED_ENTRY(247),
544 I40E_PTT_UNUSED_ENTRY(248),
545 I40E_PTT_UNUSED_ENTRY(249),
547 I40E_PTT_UNUSED_ENTRY(250),
548 I40E_PTT_UNUSED_ENTRY(251),
549 I40E_PTT_UNUSED_ENTRY(252),
550 I40E_PTT_UNUSED_ENTRY(253),
551 I40E_PTT_UNUSED_ENTRY(254),
552 I40E_PTT_UNUSED_ENTRY(255)
557 * i40e_validate_mac_addr - Validate unicast MAC address
558 * @mac_addr: pointer to MAC address
560 * Tests a MAC address to ensure it is a valid Individual Address
562 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
564 enum i40e_status_code status = I40E_SUCCESS;
566 DEBUGFUNC("i40e_validate_mac_addr");
568 /* Broadcast addresses ARE multicast addresses
569 * Make sure it is not a multicast address
570 * Reject the zero address
572 if (I40E_IS_MULTICAST(mac_addr) ||
573 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
574 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
575 status = I40E_ERR_INVALID_MAC_ADDR;
582 * i40e_init_shared_code - Initialize the shared code
583 * @hw: pointer to hardware structure
585 * This assigns the MAC type and PHY code and inits the NVM.
586 * Does not touch the hardware. This function must be called prior to any
587 * other function in the shared code. The i40e_hw structure should be
588 * memset to 0 prior to calling this function. The following fields in
589 * hw structure should be filled in prior to calling this function:
590 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
591 * subsystem_vendor_id, and revision_id
593 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
595 enum i40e_status_code status = I40E_SUCCESS;
596 u32 port, ari, func_rid;
598 DEBUGFUNC("i40e_init_shared_code");
600 i40e_set_mac_type(hw);
602 switch (hw->mac.type) {
606 return I40E_ERR_DEVICE_NOT_SUPPORTED;
609 hw->phy.get_link_info = true;
611 /* Determine port number and PF number*/
612 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
613 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
615 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
616 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
617 func_rid = rd32(hw, I40E_PF_FUNC_RID);
619 hw->pf_id = (u8)(func_rid & 0xff);
621 hw->pf_id = (u8)(func_rid & 0x7);
623 status = i40e_init_nvm(hw);
628 * i40e_aq_mac_address_read - Retrieve the MAC addresses
629 * @hw: pointer to the hw struct
630 * @flags: a return indicator of what addresses were added to the addr store
631 * @addrs: the requestor's mac addr store
632 * @cmd_details: pointer to command details structure or NULL
634 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
636 struct i40e_aqc_mac_address_read_data *addrs,
637 struct i40e_asq_cmd_details *cmd_details)
639 struct i40e_aq_desc desc;
640 struct i40e_aqc_mac_address_read *cmd_data =
641 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
642 enum i40e_status_code status;
644 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
645 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
647 status = i40e_asq_send_command(hw, &desc, addrs,
648 sizeof(*addrs), cmd_details);
649 *flags = LE16_TO_CPU(cmd_data->command_flags);
655 * i40e_aq_mac_address_write - Change the MAC addresses
656 * @hw: pointer to the hw struct
657 * @flags: indicates which MAC to be written
658 * @mac_addr: address to write
659 * @cmd_details: pointer to command details structure or NULL
661 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
662 u16 flags, u8 *mac_addr,
663 struct i40e_asq_cmd_details *cmd_details)
665 struct i40e_aq_desc desc;
666 struct i40e_aqc_mac_address_write *cmd_data =
667 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
668 enum i40e_status_code status;
670 i40e_fill_default_direct_cmd_desc(&desc,
671 i40e_aqc_opc_mac_address_write);
672 cmd_data->command_flags = CPU_TO_LE16(flags);
673 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
674 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
675 ((u32)mac_addr[3] << 16) |
676 ((u32)mac_addr[4] << 8) |
679 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
685 * i40e_get_mac_addr - get MAC address
686 * @hw: pointer to the HW structure
687 * @mac_addr: pointer to MAC address
689 * Reads the adapter's MAC address from register
691 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
693 struct i40e_aqc_mac_address_read_data addrs;
694 enum i40e_status_code status;
697 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
699 if (flags & I40E_AQC_LAN_ADDR_VALID)
700 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
706 * i40e_get_port_mac_addr - get Port MAC address
707 * @hw: pointer to the HW structure
708 * @mac_addr: pointer to Port MAC address
710 * Reads the adapter's Port MAC address
712 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
714 struct i40e_aqc_mac_address_read_data addrs;
715 enum i40e_status_code status;
718 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
722 if (flags & I40E_AQC_PORT_ADDR_VALID)
723 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
725 status = I40E_ERR_INVALID_MAC_ADDR;
731 * i40e_pre_tx_queue_cfg - pre tx queue configure
732 * @hw: pointer to the HW structure
733 * @queue: target pf queue index
734 * @enable: state change request
736 * Handles hw requirement to indicate intention to enable
737 * or disable target queue.
739 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
741 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
745 if (abs_queue_idx >= 128) {
746 reg_block = abs_queue_idx / 128;
747 abs_queue_idx %= 128;
750 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
751 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
752 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
755 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
757 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
759 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
763 * i40e_read_pba_string - Reads part number string from EEPROM
764 * @hw: pointer to hardware structure
765 * @pba_num: stores the part number string from the EEPROM
766 * @pba_num_size: part number string buffer length
768 * Reads the part number string from the EEPROM.
770 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
773 enum i40e_status_code status = I40E_SUCCESS;
779 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
780 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
781 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
785 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
786 if (status != I40E_SUCCESS) {
787 DEBUGOUT("Failed to read PBA Block pointer.\n");
791 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
792 if (status != I40E_SUCCESS) {
793 DEBUGOUT("Failed to read PBA Block size.\n");
797 /* Subtract one to get PBA word count (PBA Size word is included in
801 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
802 DEBUGOUT("Buffer to small for PBA data.\n");
803 return I40E_ERR_PARAM;
806 for (i = 0; i < pba_size; i++) {
807 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
808 if (status != I40E_SUCCESS) {
809 DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
813 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
814 pba_num[(i * 2) + 1] = pba_word & 0xFF;
816 pba_num[(pba_size * 2)] = '\0';
822 * i40e_get_media_type - Gets media type
823 * @hw: pointer to the hardware structure
825 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
827 enum i40e_media_type media;
829 switch (hw->phy.link_info.phy_type) {
830 case I40E_PHY_TYPE_10GBASE_SR:
831 case I40E_PHY_TYPE_10GBASE_LR:
832 case I40E_PHY_TYPE_1000BASE_SX:
833 case I40E_PHY_TYPE_1000BASE_LX:
834 case I40E_PHY_TYPE_40GBASE_SR4:
835 case I40E_PHY_TYPE_40GBASE_LR4:
836 media = I40E_MEDIA_TYPE_FIBER;
838 case I40E_PHY_TYPE_100BASE_TX:
839 case I40E_PHY_TYPE_1000BASE_T:
840 case I40E_PHY_TYPE_10GBASE_T:
841 media = I40E_MEDIA_TYPE_BASET;
843 case I40E_PHY_TYPE_10GBASE_CR1_CU:
844 case I40E_PHY_TYPE_40GBASE_CR4_CU:
845 case I40E_PHY_TYPE_10GBASE_CR1:
846 case I40E_PHY_TYPE_40GBASE_CR4:
847 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
848 case I40E_PHY_TYPE_40GBASE_AOC:
849 case I40E_PHY_TYPE_10GBASE_AOC:
850 media = I40E_MEDIA_TYPE_DA;
852 case I40E_PHY_TYPE_1000BASE_KX:
853 case I40E_PHY_TYPE_10GBASE_KX4:
854 case I40E_PHY_TYPE_10GBASE_KR:
855 case I40E_PHY_TYPE_40GBASE_KR4:
856 media = I40E_MEDIA_TYPE_BACKPLANE;
858 case I40E_PHY_TYPE_SGMII:
859 case I40E_PHY_TYPE_XAUI:
860 case I40E_PHY_TYPE_XFI:
861 case I40E_PHY_TYPE_XLAUI:
862 case I40E_PHY_TYPE_XLPPI:
864 media = I40E_MEDIA_TYPE_UNKNOWN;
871 #define I40E_PF_RESET_WAIT_COUNT 110
873 * i40e_pf_reset - Reset the PF
874 * @hw: pointer to the hardware structure
876 * Assuming someone else has triggered a global reset,
877 * assure the global reset is complete and then reset the PF
879 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
886 /* Poll for Global Reset steady state in case of recent GRST.
887 * The grst delay value is in 100ms units, and we'll wait a
888 * couple counts longer to be sure we don't just miss the end.
890 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
891 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
892 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
893 for (cnt = 0; cnt < grst_del + 2; cnt++) {
894 reg = rd32(hw, I40E_GLGEN_RSTAT);
895 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
897 i40e_msec_delay(100);
899 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
900 DEBUGOUT("Global reset polling failed to complete.\n");
901 return I40E_ERR_RESET_FAILED;
904 /* Now Wait for the FW to be ready */
905 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
906 reg = rd32(hw, I40E_GLNVM_ULD);
907 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
908 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
909 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
910 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
911 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
916 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
917 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
918 DEBUGOUT("wait for FW Reset complete timedout\n");
919 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
920 return I40E_ERR_RESET_FAILED;
923 /* If there was a Global Reset in progress when we got here,
924 * we don't need to do the PF Reset
927 reg = rd32(hw, I40E_PFGEN_CTRL);
928 wr32(hw, I40E_PFGEN_CTRL,
929 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
930 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
931 reg = rd32(hw, I40E_PFGEN_CTRL);
932 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
936 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
937 DEBUGOUT("PF reset polling failed to complete.\n");
938 return I40E_ERR_RESET_FAILED;
942 i40e_clear_pxe_mode(hw);
949 * i40e_clear_hw - clear out any left over hw state
950 * @hw: pointer to the hw struct
952 * Clear queues and interrupts, typically called at init time,
953 * but after the capabilities have been found so we know how many
954 * queues and msix vectors have been allocated.
956 void i40e_clear_hw(struct i40e_hw *hw)
958 u32 num_queues, base_queue;
966 /* get number of interrupts, queues, and vfs */
967 val = rd32(hw, I40E_GLPCI_CNF2);
968 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
969 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
970 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
971 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
973 val = rd32(hw, I40E_PFLAN_QALLOC);
974 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
975 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
976 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
977 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
978 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
979 num_queues = (j - base_queue) + 1;
983 val = rd32(hw, I40E_PF_VT_PFALLOC);
984 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
985 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
986 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
987 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
988 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
989 num_vfs = (j - i) + 1;
993 /* stop all the interrupts */
994 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
995 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
996 for (i = 0; i < num_pf_int - 2; i++)
997 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
999 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1000 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1001 wr32(hw, I40E_PFINT_LNKLST0, val);
1002 for (i = 0; i < num_pf_int - 2; i++)
1003 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1004 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1005 for (i = 0; i < num_vfs; i++)
1006 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1007 for (i = 0; i < num_vf_int - 2; i++)
1008 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1010 /* warn the HW of the coming Tx disables */
1011 for (i = 0; i < num_queues; i++) {
1012 u32 abs_queue_idx = base_queue + i;
1015 if (abs_queue_idx >= 128) {
1016 reg_block = abs_queue_idx / 128;
1017 abs_queue_idx %= 128;
1020 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1021 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1022 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1023 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1025 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1027 i40e_usec_delay(400);
1029 /* stop all the queues */
1030 for (i = 0; i < num_queues; i++) {
1031 wr32(hw, I40E_QINT_TQCTL(i), 0);
1032 wr32(hw, I40E_QTX_ENA(i), 0);
1033 wr32(hw, I40E_QINT_RQCTL(i), 0);
1034 wr32(hw, I40E_QRX_ENA(i), 0);
1037 /* short wait for all queue disables to settle */
1038 i40e_usec_delay(50);
1042 * i40e_clear_pxe_mode - clear pxe operations mode
1043 * @hw: pointer to the hw struct
1045 * Make sure all PXE mode settings are cleared, including things
1046 * like descriptor fetch/write-back mode.
1048 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1050 if (i40e_check_asq_alive(hw))
1051 i40e_aq_clear_pxe_mode(hw, NULL);
1055 * i40e_led_is_mine - helper to find matching led
1056 * @hw: pointer to the hw struct
1057 * @idx: index into GPIO registers
1059 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1061 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1066 if (!hw->func_caps.led[idx])
1069 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1070 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1071 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1073 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1074 * if it is not our port then ignore
1076 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1083 #define I40E_COMBINED_ACTIVITY 0xA
1084 #define I40E_FILTER_ACTIVITY 0xE
1085 #define I40E_LINK_ACTIVITY 0xC
1086 #define I40E_MAC_ACTIVITY 0xD
1087 #define I40E_LED0 22
1090 * i40e_led_get - return current on/off mode
1091 * @hw: pointer to the hw struct
1093 * The value returned is the 'mode' field as defined in the
1094 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1095 * values are variations of possible behaviors relating to
1096 * blink, link, and wire.
1098 u32 i40e_led_get(struct i40e_hw *hw)
1100 u32 current_mode = 0;
1104 /* as per the documentation GPIO 22-29 are the LED
1105 * GPIO pins named LED0..LED7
1107 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1108 u32 gpio_val = i40e_led_is_mine(hw, i);
1113 /* ignore gpio LED src mode entries related to the activity LEDs */
1114 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1115 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1116 switch (current_mode) {
1117 case I40E_COMBINED_ACTIVITY:
1118 case I40E_FILTER_ACTIVITY:
1119 case I40E_MAC_ACTIVITY:
1125 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1126 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1134 * i40e_led_set - set new on/off mode
1135 * @hw: pointer to the hw struct
1136 * @mode: 0=off, 0xf=on (else see manual for mode details)
1137 * @blink: true if the LED should blink when on, false if steady
1139 * if this function is used to turn on the blink it should
1140 * be used to disable the blink when restoring the original state.
1142 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1144 u32 current_mode = 0;
1147 if (mode & 0xfffffff0)
1148 DEBUGOUT1("invalid mode passed in %X\n", mode);
1150 /* as per the documentation GPIO 22-29 are the LED
1151 * GPIO pins named LED0..LED7
1153 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1154 u32 gpio_val = i40e_led_is_mine(hw, i);
1159 /* ignore gpio LED src mode entries related to the activity LEDs */
1160 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1161 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1162 switch (current_mode) {
1163 case I40E_COMBINED_ACTIVITY:
1164 case I40E_FILTER_ACTIVITY:
1165 case I40E_MAC_ACTIVITY:
1171 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1172 /* this & is a bit of paranoia, but serves as a range check */
1173 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1174 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1176 if (mode == I40E_LINK_ACTIVITY)
1180 gpio_val |= (1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1182 gpio_val &= ~(1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1184 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1189 /* Admin command wrappers */
1192 * i40e_aq_get_phy_capabilities
1193 * @hw: pointer to the hw struct
1194 * @abilities: structure for PHY capabilities to be filled
1195 * @qualified_modules: report Qualified Modules
1196 * @report_init: report init capabilities (active are default)
1197 * @cmd_details: pointer to command details structure or NULL
1199 * Returns the various PHY abilities supported on the Port.
1201 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1202 bool qualified_modules, bool report_init,
1203 struct i40e_aq_get_phy_abilities_resp *abilities,
1204 struct i40e_asq_cmd_details *cmd_details)
1206 struct i40e_aq_desc desc;
1207 enum i40e_status_code status;
1208 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1211 return I40E_ERR_PARAM;
1213 i40e_fill_default_direct_cmd_desc(&desc,
1214 i40e_aqc_opc_get_phy_abilities);
1216 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1217 if (abilities_size > I40E_AQ_LARGE_BUF)
1218 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1220 if (qualified_modules)
1221 desc.params.external.param0 |=
1222 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1225 desc.params.external.param0 |=
1226 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1228 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1231 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1232 status = I40E_ERR_UNKNOWN_PHY;
1238 * i40e_aq_set_phy_config
1239 * @hw: pointer to the hw struct
1240 * @config: structure with PHY configuration to be set
1241 * @cmd_details: pointer to command details structure or NULL
1243 * Set the various PHY configuration parameters
1244 * supported on the Port.One or more of the Set PHY config parameters may be
1245 * ignored in an MFP mode as the PF may not have the privilege to set some
1246 * of the PHY Config parameters. This status will be indicated by the
1249 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1250 struct i40e_aq_set_phy_config *config,
1251 struct i40e_asq_cmd_details *cmd_details)
1253 struct i40e_aq_desc desc;
1254 struct i40e_aq_set_phy_config *cmd =
1255 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1256 enum i40e_status_code status;
1259 return I40E_ERR_PARAM;
1261 i40e_fill_default_direct_cmd_desc(&desc,
1262 i40e_aqc_opc_set_phy_config);
1266 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1273 * @hw: pointer to the hw struct
1275 * Set the requested flow control mode using set_phy_config.
1277 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1278 bool atomic_restart)
1280 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1281 struct i40e_aq_get_phy_abilities_resp abilities;
1282 struct i40e_aq_set_phy_config config;
1283 enum i40e_status_code status;
1284 u8 pause_mask = 0x0;
1290 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1291 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1293 case I40E_FC_RX_PAUSE:
1294 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1296 case I40E_FC_TX_PAUSE:
1297 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1303 /* Get the current phy config */
1304 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1307 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1311 memset(&config, 0, sizeof(config));
1312 /* clear the old pause settings */
1313 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1314 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1315 /* set the new abilities */
1316 config.abilities |= pause_mask;
1317 /* If the abilities have changed, then set the new config */
1318 if (config.abilities != abilities.abilities) {
1319 /* Auto restart link so settings take effect */
1321 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1322 /* Copy over all the old settings */
1323 config.phy_type = abilities.phy_type;
1324 config.link_speed = abilities.link_speed;
1325 config.eee_capability = abilities.eee_capability;
1326 config.eeer = abilities.eeer_val;
1327 config.low_power_ctrl = abilities.d3_lpan;
1328 status = i40e_aq_set_phy_config(hw, &config, NULL);
1331 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1333 /* Update the link info */
1334 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1336 /* Wait a little bit (on 40G cards it sometimes takes a really
1337 * long time for link to come back from the atomic reset)
1340 i40e_msec_delay(1000);
1341 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1344 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1350 * i40e_aq_set_mac_config
1351 * @hw: pointer to the hw struct
1352 * @max_frame_size: Maximum Frame Size to be supported by the port
1353 * @crc_en: Tell HW to append a CRC to outgoing frames
1354 * @pacing: Pacing configurations
1355 * @cmd_details: pointer to command details structure or NULL
1357 * Configure MAC settings for frame size, jumbo frame support and the
1358 * addition of a CRC by the hardware.
1360 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1362 bool crc_en, u16 pacing,
1363 struct i40e_asq_cmd_details *cmd_details)
1365 struct i40e_aq_desc desc;
1366 struct i40e_aq_set_mac_config *cmd =
1367 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1368 enum i40e_status_code status;
1370 if (max_frame_size == 0)
1371 return I40E_ERR_PARAM;
1373 i40e_fill_default_direct_cmd_desc(&desc,
1374 i40e_aqc_opc_set_mac_config);
1376 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1377 cmd->params = ((u8)pacing & 0x0F) << 3;
1379 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1381 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1387 * i40e_aq_clear_pxe_mode
1388 * @hw: pointer to the hw struct
1389 * @cmd_details: pointer to command details structure or NULL
1391 * Tell the firmware that the driver is taking over from PXE
1393 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1394 struct i40e_asq_cmd_details *cmd_details)
1396 enum i40e_status_code status;
1397 struct i40e_aq_desc desc;
1398 struct i40e_aqc_clear_pxe *cmd =
1399 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1401 i40e_fill_default_direct_cmd_desc(&desc,
1402 i40e_aqc_opc_clear_pxe_mode);
1406 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1408 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1414 * i40e_aq_set_link_restart_an
1415 * @hw: pointer to the hw struct
1416 * @enable_link: if true: enable link, if false: disable link
1417 * @cmd_details: pointer to command details structure or NULL
1419 * Sets up the link and restarts the Auto-Negotiation over the link.
1421 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1422 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1424 struct i40e_aq_desc desc;
1425 struct i40e_aqc_set_link_restart_an *cmd =
1426 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1427 enum i40e_status_code status;
1429 i40e_fill_default_direct_cmd_desc(&desc,
1430 i40e_aqc_opc_set_link_restart_an);
1432 cmd->command = I40E_AQ_PHY_RESTART_AN;
1434 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1436 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1438 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1444 * i40e_aq_get_link_info
1445 * @hw: pointer to the hw struct
1446 * @enable_lse: enable/disable LinkStatusEvent reporting
1447 * @link: pointer to link status structure - optional
1448 * @cmd_details: pointer to command details structure or NULL
1450 * Returns the link status of the adapter.
1452 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1453 bool enable_lse, struct i40e_link_status *link,
1454 struct i40e_asq_cmd_details *cmd_details)
1456 struct i40e_aq_desc desc;
1457 struct i40e_aqc_get_link_status *resp =
1458 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1459 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1460 enum i40e_status_code status;
1461 bool tx_pause, rx_pause;
1464 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1467 command_flags = I40E_AQ_LSE_ENABLE;
1469 command_flags = I40E_AQ_LSE_DISABLE;
1470 resp->command_flags = CPU_TO_LE16(command_flags);
1472 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1474 if (status != I40E_SUCCESS)
1475 goto aq_get_link_info_exit;
1477 /* save off old link status information */
1478 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1479 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1481 /* update link status */
1482 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1483 hw->phy.media_type = i40e_get_media_type(hw);
1484 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1485 hw_link_info->link_info = resp->link_info;
1486 hw_link_info->an_info = resp->an_info;
1487 hw_link_info->ext_info = resp->ext_info;
1488 hw_link_info->loopback = resp->loopback;
1489 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1490 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1492 /* update fc info */
1493 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1494 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1495 if (tx_pause & rx_pause)
1496 hw->fc.current_mode = I40E_FC_FULL;
1498 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1500 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1502 hw->fc.current_mode = I40E_FC_NONE;
1504 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1505 hw_link_info->crc_enable = true;
1507 hw_link_info->crc_enable = false;
1509 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1510 hw_link_info->lse_enable = true;
1512 hw_link_info->lse_enable = false;
1514 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1515 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1516 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1518 /* save link status information */
1520 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1521 I40E_NONDMA_TO_NONDMA);
1523 /* flag cleared so helper functions don't call AQ again */
1524 hw->phy.get_link_info = false;
1526 aq_get_link_info_exit:
1532 * i40e_aq_set_phy_int_mask
1533 * @hw: pointer to the hw struct
1534 * @mask: interrupt mask to be set
1535 * @cmd_details: pointer to command details structure or NULL
1537 * Set link interrupt mask.
1539 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1541 struct i40e_asq_cmd_details *cmd_details)
1543 struct i40e_aq_desc desc;
1544 struct i40e_aqc_set_phy_int_mask *cmd =
1545 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1546 enum i40e_status_code status;
1548 i40e_fill_default_direct_cmd_desc(&desc,
1549 i40e_aqc_opc_set_phy_int_mask);
1551 cmd->event_mask = CPU_TO_LE16(mask);
1553 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1559 * i40e_aq_get_local_advt_reg
1560 * @hw: pointer to the hw struct
1561 * @advt_reg: local AN advertisement register value
1562 * @cmd_details: pointer to command details structure or NULL
1564 * Get the Local AN advertisement register value.
1566 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
1568 struct i40e_asq_cmd_details *cmd_details)
1570 struct i40e_aq_desc desc;
1571 struct i40e_aqc_an_advt_reg *resp =
1572 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1573 enum i40e_status_code status;
1575 i40e_fill_default_direct_cmd_desc(&desc,
1576 i40e_aqc_opc_get_local_advt_reg);
1578 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1580 if (status != I40E_SUCCESS)
1581 goto aq_get_local_advt_reg_exit;
1583 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1584 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1586 aq_get_local_advt_reg_exit:
1591 * i40e_aq_set_local_advt_reg
1592 * @hw: pointer to the hw struct
1593 * @advt_reg: local AN advertisement register value
1594 * @cmd_details: pointer to command details structure or NULL
1596 * Get the Local AN advertisement register value.
1598 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
1600 struct i40e_asq_cmd_details *cmd_details)
1602 struct i40e_aq_desc desc;
1603 struct i40e_aqc_an_advt_reg *cmd =
1604 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1605 enum i40e_status_code status;
1607 i40e_fill_default_direct_cmd_desc(&desc,
1608 i40e_aqc_opc_get_local_advt_reg);
1610 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
1611 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
1613 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1619 * i40e_aq_get_partner_advt
1620 * @hw: pointer to the hw struct
1621 * @advt_reg: AN partner advertisement register value
1622 * @cmd_details: pointer to command details structure or NULL
1624 * Get the link partner AN advertisement register value.
1626 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
1628 struct i40e_asq_cmd_details *cmd_details)
1630 struct i40e_aq_desc desc;
1631 struct i40e_aqc_an_advt_reg *resp =
1632 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1633 enum i40e_status_code status;
1635 i40e_fill_default_direct_cmd_desc(&desc,
1636 i40e_aqc_opc_get_partner_advt);
1638 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1640 if (status != I40E_SUCCESS)
1641 goto aq_get_partner_advt_exit;
1643 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1644 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1646 aq_get_partner_advt_exit:
1651 * i40e_aq_set_lb_modes
1652 * @hw: pointer to the hw struct
1653 * @lb_modes: loopback mode to be set
1654 * @cmd_details: pointer to command details structure or NULL
1656 * Sets loopback modes.
1658 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
1660 struct i40e_asq_cmd_details *cmd_details)
1662 struct i40e_aq_desc desc;
1663 struct i40e_aqc_set_lb_mode *cmd =
1664 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
1665 enum i40e_status_code status;
1667 i40e_fill_default_direct_cmd_desc(&desc,
1668 i40e_aqc_opc_set_lb_modes);
1670 cmd->lb_mode = CPU_TO_LE16(lb_modes);
1672 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1678 * i40e_aq_set_phy_debug
1679 * @hw: pointer to the hw struct
1680 * @cmd_flags: debug command flags
1681 * @cmd_details: pointer to command details structure or NULL
1683 * Reset the external PHY.
1685 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1686 struct i40e_asq_cmd_details *cmd_details)
1688 struct i40e_aq_desc desc;
1689 struct i40e_aqc_set_phy_debug *cmd =
1690 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1691 enum i40e_status_code status;
1693 i40e_fill_default_direct_cmd_desc(&desc,
1694 i40e_aqc_opc_set_phy_debug);
1696 cmd->command_flags = cmd_flags;
1698 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1705 * @hw: pointer to the hw struct
1706 * @vsi_ctx: pointer to a vsi context struct
1707 * @cmd_details: pointer to command details structure or NULL
1709 * Add a VSI context to the hardware.
1711 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
1712 struct i40e_vsi_context *vsi_ctx,
1713 struct i40e_asq_cmd_details *cmd_details)
1715 struct i40e_aq_desc desc;
1716 struct i40e_aqc_add_get_update_vsi *cmd =
1717 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1718 struct i40e_aqc_add_get_update_vsi_completion *resp =
1719 (struct i40e_aqc_add_get_update_vsi_completion *)
1721 enum i40e_status_code status;
1723 i40e_fill_default_direct_cmd_desc(&desc,
1724 i40e_aqc_opc_add_vsi);
1726 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
1727 cmd->connection_type = vsi_ctx->connection_type;
1728 cmd->vf_id = vsi_ctx->vf_num;
1729 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
1731 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1733 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1734 sizeof(vsi_ctx->info), cmd_details);
1736 if (status != I40E_SUCCESS)
1737 goto aq_add_vsi_exit;
1739 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
1740 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
1741 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
1742 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
1749 * i40e_aq_set_default_vsi
1750 * @hw: pointer to the hw struct
1752 * @cmd_details: pointer to command details structure or NULL
1754 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
1756 struct i40e_asq_cmd_details *cmd_details)
1758 struct i40e_aq_desc desc;
1759 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1760 (struct i40e_aqc_set_vsi_promiscuous_modes *)
1762 enum i40e_status_code status;
1764 i40e_fill_default_direct_cmd_desc(&desc,
1765 i40e_aqc_opc_set_vsi_promiscuous_modes);
1767 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
1768 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
1769 cmd->seid = CPU_TO_LE16(seid);
1771 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1777 * i40e_aq_set_vsi_unicast_promiscuous
1778 * @hw: pointer to the hw struct
1780 * @set: set unicast promiscuous enable/disable
1781 * @cmd_details: pointer to command details structure or NULL
1783 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
1785 struct i40e_asq_cmd_details *cmd_details)
1787 struct i40e_aq_desc desc;
1788 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1789 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1790 enum i40e_status_code status;
1793 i40e_fill_default_direct_cmd_desc(&desc,
1794 i40e_aqc_opc_set_vsi_promiscuous_modes);
1797 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1799 cmd->promiscuous_flags = CPU_TO_LE16(flags);
1801 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1803 cmd->seid = CPU_TO_LE16(seid);
1804 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1810 * i40e_aq_set_vsi_multicast_promiscuous
1811 * @hw: pointer to the hw struct
1813 * @set: set multicast promiscuous enable/disable
1814 * @cmd_details: pointer to command details structure or NULL
1816 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
1817 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
1819 struct i40e_aq_desc desc;
1820 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1821 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1822 enum i40e_status_code status;
1825 i40e_fill_default_direct_cmd_desc(&desc,
1826 i40e_aqc_opc_set_vsi_promiscuous_modes);
1829 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1831 cmd->promiscuous_flags = CPU_TO_LE16(flags);
1833 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
1835 cmd->seid = CPU_TO_LE16(seid);
1836 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1842 * i40e_aq_set_vsi_broadcast
1843 * @hw: pointer to the hw struct
1845 * @set_filter: true to set filter, false to clear filter
1846 * @cmd_details: pointer to command details structure or NULL
1848 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
1850 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
1851 u16 seid, bool set_filter,
1852 struct i40e_asq_cmd_details *cmd_details)
1854 struct i40e_aq_desc desc;
1855 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1856 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1857 enum i40e_status_code status;
1859 i40e_fill_default_direct_cmd_desc(&desc,
1860 i40e_aqc_opc_set_vsi_promiscuous_modes);
1863 cmd->promiscuous_flags
1864 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1866 cmd->promiscuous_flags
1867 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1869 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1870 cmd->seid = CPU_TO_LE16(seid);
1871 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1877 * i40e_get_vsi_params - get VSI configuration info
1878 * @hw: pointer to the hw struct
1879 * @vsi_ctx: pointer to a vsi context struct
1880 * @cmd_details: pointer to command details structure or NULL
1882 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
1883 struct i40e_vsi_context *vsi_ctx,
1884 struct i40e_asq_cmd_details *cmd_details)
1886 struct i40e_aq_desc desc;
1887 struct i40e_aqc_add_get_update_vsi *cmd =
1888 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1889 struct i40e_aqc_add_get_update_vsi_completion *resp =
1890 (struct i40e_aqc_add_get_update_vsi_completion *)
1892 enum i40e_status_code status;
1894 UNREFERENCED_1PARAMETER(cmd_details);
1895 i40e_fill_default_direct_cmd_desc(&desc,
1896 i40e_aqc_opc_get_vsi_parameters);
1898 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
1900 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1902 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1903 sizeof(vsi_ctx->info), NULL);
1905 if (status != I40E_SUCCESS)
1906 goto aq_get_vsi_params_exit;
1908 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
1909 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
1910 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
1911 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
1913 aq_get_vsi_params_exit:
1918 * i40e_aq_update_vsi_params
1919 * @hw: pointer to the hw struct
1920 * @vsi_ctx: pointer to a vsi context struct
1921 * @cmd_details: pointer to command details structure or NULL
1923 * Update a VSI context.
1925 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
1926 struct i40e_vsi_context *vsi_ctx,
1927 struct i40e_asq_cmd_details *cmd_details)
1929 struct i40e_aq_desc desc;
1930 struct i40e_aqc_add_get_update_vsi *cmd =
1931 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1932 enum i40e_status_code status;
1934 i40e_fill_default_direct_cmd_desc(&desc,
1935 i40e_aqc_opc_update_vsi_parameters);
1936 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
1938 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1940 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1941 sizeof(vsi_ctx->info), cmd_details);
1947 * i40e_aq_get_switch_config
1948 * @hw: pointer to the hardware structure
1949 * @buf: pointer to the result buffer
1950 * @buf_size: length of input buffer
1951 * @start_seid: seid to start for the report, 0 == beginning
1952 * @cmd_details: pointer to command details structure or NULL
1954 * Fill the buf with switch configuration returned from AdminQ command
1956 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
1957 struct i40e_aqc_get_switch_config_resp *buf,
1958 u16 buf_size, u16 *start_seid,
1959 struct i40e_asq_cmd_details *cmd_details)
1961 struct i40e_aq_desc desc;
1962 struct i40e_aqc_switch_seid *scfg =
1963 (struct i40e_aqc_switch_seid *)&desc.params.raw;
1964 enum i40e_status_code status;
1966 i40e_fill_default_direct_cmd_desc(&desc,
1967 i40e_aqc_opc_get_switch_config);
1968 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1969 if (buf_size > I40E_AQ_LARGE_BUF)
1970 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1971 scfg->seid = CPU_TO_LE16(*start_seid);
1973 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
1974 *start_seid = LE16_TO_CPU(scfg->seid);
1980 * i40e_aq_get_firmware_version
1981 * @hw: pointer to the hw struct
1982 * @fw_major_version: firmware major version
1983 * @fw_minor_version: firmware minor version
1984 * @fw_build: firmware build number
1985 * @api_major_version: major queue version
1986 * @api_minor_version: minor queue version
1987 * @cmd_details: pointer to command details structure or NULL
1989 * Get the firmware version from the admin queue commands
1991 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
1992 u16 *fw_major_version, u16 *fw_minor_version,
1994 u16 *api_major_version, u16 *api_minor_version,
1995 struct i40e_asq_cmd_details *cmd_details)
1997 struct i40e_aq_desc desc;
1998 struct i40e_aqc_get_version *resp =
1999 (struct i40e_aqc_get_version *)&desc.params.raw;
2000 enum i40e_status_code status;
2002 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2004 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2006 if (status == I40E_SUCCESS) {
2007 if (fw_major_version != NULL)
2008 *fw_major_version = LE16_TO_CPU(resp->fw_major);
2009 if (fw_minor_version != NULL)
2010 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2011 if (fw_build != NULL)
2012 *fw_build = LE32_TO_CPU(resp->fw_build);
2013 if (api_major_version != NULL)
2014 *api_major_version = LE16_TO_CPU(resp->api_major);
2015 if (api_minor_version != NULL)
2016 *api_minor_version = LE16_TO_CPU(resp->api_minor);
2018 /* A workaround to fix the API version in SW */
2019 if (api_major_version && api_minor_version &&
2020 fw_major_version && fw_minor_version &&
2021 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2022 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2023 (*fw_major_version > 4)))
2024 *api_minor_version = 2;
2031 * i40e_aq_send_driver_version
2032 * @hw: pointer to the hw struct
2033 * @dv: driver's major, minor version
2034 * @cmd_details: pointer to command details structure or NULL
2036 * Send the driver version to the firmware
2038 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2039 struct i40e_driver_version *dv,
2040 struct i40e_asq_cmd_details *cmd_details)
2042 struct i40e_aq_desc desc;
2043 struct i40e_aqc_driver_version *cmd =
2044 (struct i40e_aqc_driver_version *)&desc.params.raw;
2045 enum i40e_status_code status;
2049 return I40E_ERR_PARAM;
2051 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2053 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2054 cmd->driver_major_ver = dv->major_version;
2055 cmd->driver_minor_ver = dv->minor_version;
2056 cmd->driver_build_ver = dv->build_version;
2057 cmd->driver_subbuild_ver = dv->subbuild_version;
2060 while (len < sizeof(dv->driver_string) &&
2061 (dv->driver_string[len] < 0x80) &&
2062 dv->driver_string[len])
2064 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2071 * i40e_get_link_status - get status of the HW network link
2072 * @hw: pointer to the hw struct
2074 * Returns true if link is up, false if link is down.
2076 * Side effect: LinkStatusEvent reporting becomes enabled
2078 bool i40e_get_link_status(struct i40e_hw *hw)
2080 enum i40e_status_code status = I40E_SUCCESS;
2081 bool link_status = false;
2083 if (hw->phy.get_link_info) {
2084 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2086 if (status != I40E_SUCCESS)
2087 goto i40e_get_link_status_exit;
2090 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2092 i40e_get_link_status_exit:
2097 * i40e_get_link_speed
2098 * @hw: pointer to the hw struct
2100 * Returns the link speed of the adapter.
2102 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2104 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2105 enum i40e_status_code status = I40E_SUCCESS;
2107 if (hw->phy.get_link_info) {
2108 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2110 if (status != I40E_SUCCESS)
2111 goto i40e_link_speed_exit;
2114 speed = hw->phy.link_info.link_speed;
2116 i40e_link_speed_exit:
2121 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2122 * @hw: pointer to the hw struct
2123 * @uplink_seid: the MAC or other gizmo SEID
2124 * @downlink_seid: the VSI SEID
2125 * @enabled_tc: bitmap of TCs to be enabled
2126 * @default_port: true for default port VSI, false for control port
2127 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
2128 * @veb_seid: pointer to where to put the resulting VEB SEID
2129 * @cmd_details: pointer to command details structure or NULL
2131 * This asks the FW to add a VEB between the uplink and downlink
2132 * elements. If the uplink SEID is 0, this will be a floating VEB.
2134 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2135 u16 downlink_seid, u8 enabled_tc,
2136 bool default_port, bool enable_l2_filtering,
2138 struct i40e_asq_cmd_details *cmd_details)
2140 struct i40e_aq_desc desc;
2141 struct i40e_aqc_add_veb *cmd =
2142 (struct i40e_aqc_add_veb *)&desc.params.raw;
2143 struct i40e_aqc_add_veb_completion *resp =
2144 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2145 enum i40e_status_code status;
2148 /* SEIDs need to either both be set or both be 0 for floating VEB */
2149 if (!!uplink_seid != !!downlink_seid)
2150 return I40E_ERR_PARAM;
2152 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2154 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2155 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2156 cmd->enable_tcs = enabled_tc;
2158 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2160 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2162 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2164 if (enable_l2_filtering)
2165 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
2167 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2169 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2171 if (!status && veb_seid)
2172 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2178 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2179 * @hw: pointer to the hw struct
2180 * @veb_seid: the SEID of the VEB to query
2181 * @switch_id: the uplink switch id
2182 * @floating: set to true if the VEB is floating
2183 * @statistic_index: index of the stats counter block for this VEB
2184 * @vebs_used: number of VEB's used by function
2185 * @vebs_free: total VEB's not reserved by any function
2186 * @cmd_details: pointer to command details structure or NULL
2188 * This retrieves the parameters for a particular VEB, specified by
2189 * uplink_seid, and returns them to the caller.
2191 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2192 u16 veb_seid, u16 *switch_id,
2193 bool *floating, u16 *statistic_index,
2194 u16 *vebs_used, u16 *vebs_free,
2195 struct i40e_asq_cmd_details *cmd_details)
2197 struct i40e_aq_desc desc;
2198 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2199 (struct i40e_aqc_get_veb_parameters_completion *)
2201 enum i40e_status_code status;
2204 return I40E_ERR_PARAM;
2206 i40e_fill_default_direct_cmd_desc(&desc,
2207 i40e_aqc_opc_get_veb_parameters);
2208 cmd_resp->seid = CPU_TO_LE16(veb_seid);
2210 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2215 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2216 if (statistic_index)
2217 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2219 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2221 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2223 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2224 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2235 * i40e_aq_add_macvlan
2236 * @hw: pointer to the hw struct
2237 * @seid: VSI for the mac address
2238 * @mv_list: list of macvlans to be added
2239 * @count: length of the list
2240 * @cmd_details: pointer to command details structure or NULL
2242 * Add MAC/VLAN addresses to the HW filtering
2244 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2245 struct i40e_aqc_add_macvlan_element_data *mv_list,
2246 u16 count, struct i40e_asq_cmd_details *cmd_details)
2248 struct i40e_aq_desc desc;
2249 struct i40e_aqc_macvlan *cmd =
2250 (struct i40e_aqc_macvlan *)&desc.params.raw;
2251 enum i40e_status_code status;
2254 if (count == 0 || !mv_list || !hw)
2255 return I40E_ERR_PARAM;
2257 buf_size = count * sizeof(*mv_list);
2259 /* prep the rest of the request */
2260 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2261 cmd->num_addresses = CPU_TO_LE16(count);
2262 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2266 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2267 if (buf_size > I40E_AQ_LARGE_BUF)
2268 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2270 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2277 * i40e_aq_remove_macvlan
2278 * @hw: pointer to the hw struct
2279 * @seid: VSI for the mac address
2280 * @mv_list: list of macvlans to be removed
2281 * @count: length of the list
2282 * @cmd_details: pointer to command details structure or NULL
2284 * Remove MAC/VLAN addresses from the HW filtering
2286 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2287 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2288 u16 count, struct i40e_asq_cmd_details *cmd_details)
2290 struct i40e_aq_desc desc;
2291 struct i40e_aqc_macvlan *cmd =
2292 (struct i40e_aqc_macvlan *)&desc.params.raw;
2293 enum i40e_status_code status;
2296 if (count == 0 || !mv_list || !hw)
2297 return I40E_ERR_PARAM;
2299 buf_size = count * sizeof(*mv_list);
2301 /* prep the rest of the request */
2302 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2303 cmd->num_addresses = CPU_TO_LE16(count);
2304 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2308 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2309 if (buf_size > I40E_AQ_LARGE_BUF)
2310 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2312 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2319 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
2320 * @hw: pointer to the hw struct
2321 * @seid: VSI for the vlan filters
2322 * @v_list: list of vlan filters to be added
2323 * @count: length of the list
2324 * @cmd_details: pointer to command details structure or NULL
2326 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
2327 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2328 u8 count, struct i40e_asq_cmd_details *cmd_details)
2330 struct i40e_aq_desc desc;
2331 struct i40e_aqc_macvlan *cmd =
2332 (struct i40e_aqc_macvlan *)&desc.params.raw;
2333 enum i40e_status_code status;
2336 if (count == 0 || !v_list || !hw)
2337 return I40E_ERR_PARAM;
2339 buf_size = count * sizeof(*v_list);
2341 /* prep the rest of the request */
2342 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
2343 cmd->num_addresses = CPU_TO_LE16(count);
2344 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2348 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2349 if (buf_size > I40E_AQ_LARGE_BUF)
2350 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2352 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2359 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
2360 * @hw: pointer to the hw struct
2361 * @seid: VSI for the vlan filters
2362 * @v_list: list of macvlans to be removed
2363 * @count: length of the list
2364 * @cmd_details: pointer to command details structure or NULL
2366 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
2367 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2368 u8 count, struct i40e_asq_cmd_details *cmd_details)
2370 struct i40e_aq_desc desc;
2371 struct i40e_aqc_macvlan *cmd =
2372 (struct i40e_aqc_macvlan *)&desc.params.raw;
2373 enum i40e_status_code status;
2376 if (count == 0 || !v_list || !hw)
2377 return I40E_ERR_PARAM;
2379 buf_size = count * sizeof(*v_list);
2381 /* prep the rest of the request */
2382 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
2383 cmd->num_addresses = CPU_TO_LE16(count);
2384 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2388 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2389 if (buf_size > I40E_AQ_LARGE_BUF)
2390 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2392 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2399 * i40e_aq_send_msg_to_vf
2400 * @hw: pointer to the hardware structure
2401 * @vfid: vf id to send msg
2402 * @v_opcode: opcodes for VF-PF communication
2403 * @v_retval: return error code
2404 * @msg: pointer to the msg buffer
2405 * @msglen: msg length
2406 * @cmd_details: pointer to command details
2410 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2411 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2412 struct i40e_asq_cmd_details *cmd_details)
2414 struct i40e_aq_desc desc;
2415 struct i40e_aqc_pf_vf_message *cmd =
2416 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2417 enum i40e_status_code status;
2419 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2420 cmd->id = CPU_TO_LE32(vfid);
2421 desc.cookie_high = CPU_TO_LE32(v_opcode);
2422 desc.cookie_low = CPU_TO_LE32(v_retval);
2423 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
2425 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
2427 if (msglen > I40E_AQ_LARGE_BUF)
2428 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2429 desc.datalen = CPU_TO_LE16(msglen);
2431 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2437 * i40e_aq_debug_read_register
2438 * @hw: pointer to the hw struct
2439 * @reg_addr: register address
2440 * @reg_val: register value
2441 * @cmd_details: pointer to command details structure or NULL
2443 * Read the register using the admin queue commands
2445 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
2446 u32 reg_addr, u64 *reg_val,
2447 struct i40e_asq_cmd_details *cmd_details)
2449 struct i40e_aq_desc desc;
2450 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2451 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2452 enum i40e_status_code status;
2454 if (reg_val == NULL)
2455 return I40E_ERR_PARAM;
2457 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2459 cmd_resp->address = CPU_TO_LE32(reg_addr);
2461 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2463 if (status == I40E_SUCCESS) {
2464 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
2465 (u64)LE32_TO_CPU(cmd_resp->value_low);
2472 * i40e_aq_debug_write_register
2473 * @hw: pointer to the hw struct
2474 * @reg_addr: register address
2475 * @reg_val: register value
2476 * @cmd_details: pointer to command details structure or NULL
2478 * Write to a register using the admin queue commands
2480 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
2481 u32 reg_addr, u64 reg_val,
2482 struct i40e_asq_cmd_details *cmd_details)
2484 struct i40e_aq_desc desc;
2485 struct i40e_aqc_debug_reg_read_write *cmd =
2486 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2487 enum i40e_status_code status;
2489 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2491 cmd->address = CPU_TO_LE32(reg_addr);
2492 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
2493 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
2495 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2501 * i40e_aq_get_hmc_resource_profile
2502 * @hw: pointer to the hw struct
2503 * @profile: type of profile the HMC is to be set as
2504 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2505 * @cmd_details: pointer to command details structure or NULL
2507 * query the HMC profile of the device.
2509 enum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw,
2510 enum i40e_aq_hmc_profile *profile,
2511 u8 *pe_vf_enabled_count,
2512 struct i40e_asq_cmd_details *cmd_details)
2514 struct i40e_aq_desc desc;
2515 struct i40e_aq_get_set_hmc_resource_profile *resp =
2516 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2517 enum i40e_status_code status;
2519 i40e_fill_default_direct_cmd_desc(&desc,
2520 i40e_aqc_opc_query_hmc_resource_profile);
2521 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2523 *profile = (enum i40e_aq_hmc_profile)(resp->pm_profile &
2524 I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK);
2525 *pe_vf_enabled_count = resp->pe_vf_enabled &
2526 I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK;
2532 * i40e_aq_set_hmc_resource_profile
2533 * @hw: pointer to the hw struct
2534 * @profile: type of profile the HMC is to be set as
2535 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2536 * @cmd_details: pointer to command details structure or NULL
2538 * set the HMC profile of the device.
2540 enum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2541 enum i40e_aq_hmc_profile profile,
2542 u8 pe_vf_enabled_count,
2543 struct i40e_asq_cmd_details *cmd_details)
2545 struct i40e_aq_desc desc;
2546 struct i40e_aq_get_set_hmc_resource_profile *cmd =
2547 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2548 enum i40e_status_code status;
2550 i40e_fill_default_direct_cmd_desc(&desc,
2551 i40e_aqc_opc_set_hmc_resource_profile);
2553 cmd->pm_profile = (u8)profile;
2554 cmd->pe_vf_enabled = pe_vf_enabled_count;
2556 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2562 * i40e_aq_request_resource
2563 * @hw: pointer to the hw struct
2564 * @resource: resource id
2565 * @access: access type
2566 * @sdp_number: resource number
2567 * @timeout: the maximum time in ms that the driver may hold the resource
2568 * @cmd_details: pointer to command details structure or NULL
2570 * requests common resource using the admin queue commands
2572 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
2573 enum i40e_aq_resources_ids resource,
2574 enum i40e_aq_resource_access_type access,
2575 u8 sdp_number, u64 *timeout,
2576 struct i40e_asq_cmd_details *cmd_details)
2578 struct i40e_aq_desc desc;
2579 struct i40e_aqc_request_resource *cmd_resp =
2580 (struct i40e_aqc_request_resource *)&desc.params.raw;
2581 enum i40e_status_code status;
2583 DEBUGFUNC("i40e_aq_request_resource");
2585 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2587 cmd_resp->resource_id = CPU_TO_LE16(resource);
2588 cmd_resp->access_type = CPU_TO_LE16(access);
2589 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
2591 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2592 /* The completion specifies the maximum time in ms that the driver
2593 * may hold the resource in the Timeout field.
2594 * If the resource is held by someone else, the command completes with
2595 * busy return value and the timeout field indicates the maximum time
2596 * the current owner of the resource has to free it.
2598 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2599 *timeout = LE32_TO_CPU(cmd_resp->timeout);
2605 * i40e_aq_release_resource
2606 * @hw: pointer to the hw struct
2607 * @resource: resource id
2608 * @sdp_number: resource number
2609 * @cmd_details: pointer to command details structure or NULL
2611 * release common resource using the admin queue commands
2613 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
2614 enum i40e_aq_resources_ids resource,
2616 struct i40e_asq_cmd_details *cmd_details)
2618 struct i40e_aq_desc desc;
2619 struct i40e_aqc_request_resource *cmd =
2620 (struct i40e_aqc_request_resource *)&desc.params.raw;
2621 enum i40e_status_code status;
2623 DEBUGFUNC("i40e_aq_release_resource");
2625 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2627 cmd->resource_id = CPU_TO_LE16(resource);
2628 cmd->resource_number = CPU_TO_LE32(sdp_number);
2630 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2637 * @hw: pointer to the hw struct
2638 * @module_pointer: module pointer location in words from the NVM beginning
2639 * @offset: byte offset from the module beginning
2640 * @length: length of the section to be read (in bytes from the offset)
2641 * @data: command buffer (size [bytes] = length)
2642 * @last_command: tells if this is the last command in a series
2643 * @cmd_details: pointer to command details structure or NULL
2645 * Read the NVM using the admin queue commands
2647 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2648 u32 offset, u16 length, void *data,
2650 struct i40e_asq_cmd_details *cmd_details)
2652 struct i40e_aq_desc desc;
2653 struct i40e_aqc_nvm_update *cmd =
2654 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2655 enum i40e_status_code status;
2657 DEBUGFUNC("i40e_aq_read_nvm");
2659 /* In offset the highest byte must be zeroed. */
2660 if (offset & 0xFF000000) {
2661 status = I40E_ERR_PARAM;
2662 goto i40e_aq_read_nvm_exit;
2665 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2667 /* If this is the last command in a series, set the proper flag. */
2669 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2670 cmd->module_pointer = module_pointer;
2671 cmd->offset = CPU_TO_LE32(offset);
2672 cmd->length = CPU_TO_LE16(length);
2674 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2675 if (length > I40E_AQ_LARGE_BUF)
2676 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2678 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2680 i40e_aq_read_nvm_exit:
2685 * i40e_aq_read_nvm_config - read an nvm config block
2686 * @hw: pointer to the hw struct
2687 * @cmd_flags: NVM access admin command bits
2688 * @field_id: field or feature id
2689 * @data: buffer for result
2690 * @buf_size: buffer size
2691 * @element_count: pointer to count of elements read by FW
2692 * @cmd_details: pointer to command details structure or NULL
2694 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
2695 u8 cmd_flags, u32 field_id, void *data,
2696 u16 buf_size, u16 *element_count,
2697 struct i40e_asq_cmd_details *cmd_details)
2699 struct i40e_aq_desc desc;
2700 struct i40e_aqc_nvm_config_read *cmd =
2701 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
2702 enum i40e_status_code status;
2704 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
2705 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
2706 if (buf_size > I40E_AQ_LARGE_BUF)
2707 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2709 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
2710 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
2711 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
2712 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
2714 cmd->element_id_msw = 0;
2716 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
2718 if (!status && element_count)
2719 *element_count = LE16_TO_CPU(cmd->element_count);
2725 * i40e_aq_write_nvm_config - write an nvm config block
2726 * @hw: pointer to the hw struct
2727 * @cmd_flags: NVM access admin command bits
2728 * @data: buffer for result
2729 * @buf_size: buffer size
2730 * @element_count: count of elements to be written
2731 * @cmd_details: pointer to command details structure or NULL
2733 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
2734 u8 cmd_flags, void *data, u16 buf_size,
2736 struct i40e_asq_cmd_details *cmd_details)
2738 struct i40e_aq_desc desc;
2739 struct i40e_aqc_nvm_config_write *cmd =
2740 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
2741 enum i40e_status_code status;
2743 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
2744 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2745 if (buf_size > I40E_AQ_LARGE_BUF)
2746 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2748 cmd->element_count = CPU_TO_LE16(element_count);
2749 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
2750 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
2757 * @hw: pointer to the hw struct
2758 * @module_pointer: module pointer location in words from the NVM beginning
2759 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2760 * @length: length of the section to be erased (expressed in 4 KB)
2761 * @last_command: tells if this is the last command in a series
2762 * @cmd_details: pointer to command details structure or NULL
2764 * Erase the NVM sector using the admin queue commands
2766 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
2767 u32 offset, u16 length, bool last_command,
2768 struct i40e_asq_cmd_details *cmd_details)
2770 struct i40e_aq_desc desc;
2771 struct i40e_aqc_nvm_update *cmd =
2772 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2773 enum i40e_status_code status;
2775 DEBUGFUNC("i40e_aq_erase_nvm");
2777 /* In offset the highest byte must be zeroed. */
2778 if (offset & 0xFF000000) {
2779 status = I40E_ERR_PARAM;
2780 goto i40e_aq_erase_nvm_exit;
2783 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
2785 /* If this is the last command in a series, set the proper flag. */
2787 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2788 cmd->module_pointer = module_pointer;
2789 cmd->offset = CPU_TO_LE32(offset);
2790 cmd->length = CPU_TO_LE16(length);
2792 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2794 i40e_aq_erase_nvm_exit:
2798 #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
2799 #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
2800 #define I40E_DEV_FUNC_CAP_NPAR 0x03
2801 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04
2802 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
2803 #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
2804 #define I40E_DEV_FUNC_CAP_VF 0x13
2805 #define I40E_DEV_FUNC_CAP_VMDQ 0x14
2806 #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
2807 #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
2808 #define I40E_DEV_FUNC_CAP_VSI 0x17
2809 #define I40E_DEV_FUNC_CAP_DCB 0x18
2810 #define I40E_DEV_FUNC_CAP_FCOE 0x21
2811 #define I40E_DEV_FUNC_CAP_ISCSI 0x22
2812 #define I40E_DEV_FUNC_CAP_RSS 0x40
2813 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
2814 #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
2815 #define I40E_DEV_FUNC_CAP_MSIX 0x43
2816 #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
2817 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
2818 #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
2819 #define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1
2820 #define I40E_DEV_FUNC_CAP_CEM 0xF2
2821 #define I40E_DEV_FUNC_CAP_IWARP 0x51
2822 #define I40E_DEV_FUNC_CAP_LED 0x61
2823 #define I40E_DEV_FUNC_CAP_SDP 0x62
2824 #define I40E_DEV_FUNC_CAP_MDIO 0x63
2827 * i40e_parse_discover_capabilities
2828 * @hw: pointer to the hw struct
2829 * @buff: pointer to a buffer containing device/function capability records
2830 * @cap_count: number of capability records in the list
2831 * @list_type_opc: type of capabilities list to parse
2833 * Parse the device/function capabilities list.
2835 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
2837 enum i40e_admin_queue_opc list_type_opc)
2839 struct i40e_aqc_list_capabilities_element_resp *cap;
2840 u32 valid_functions, num_functions;
2841 u32 number, logical_id, phys_id;
2842 struct i40e_hw_capabilities *p;
2846 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
2848 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
2849 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
2850 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
2851 p = (struct i40e_hw_capabilities *)&hw->func_caps;
2855 for (i = 0; i < cap_count; i++, cap++) {
2856 id = LE16_TO_CPU(cap->id);
2857 number = LE32_TO_CPU(cap->number);
2858 logical_id = LE32_TO_CPU(cap->logical_id);
2859 phys_id = LE32_TO_CPU(cap->phys_id);
2862 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
2863 p->switch_mode = number;
2865 case I40E_DEV_FUNC_CAP_MGMT_MODE:
2866 p->management_mode = number;
2868 case I40E_DEV_FUNC_CAP_NPAR:
2869 p->npar_enable = number;
2871 case I40E_DEV_FUNC_CAP_OS2BMC:
2874 case I40E_DEV_FUNC_CAP_VALID_FUNC:
2875 p->valid_functions = number;
2877 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
2879 p->sr_iov_1_1 = true;
2881 case I40E_DEV_FUNC_CAP_VF:
2882 p->num_vfs = number;
2883 p->vf_base_id = logical_id;
2885 case I40E_DEV_FUNC_CAP_VMDQ:
2889 case I40E_DEV_FUNC_CAP_802_1_QBG:
2891 p->evb_802_1_qbg = true;
2893 case I40E_DEV_FUNC_CAP_802_1_QBH:
2895 p->evb_802_1_qbh = true;
2897 case I40E_DEV_FUNC_CAP_VSI:
2898 p->num_vsis = number;
2900 case I40E_DEV_FUNC_CAP_DCB:
2903 p->enabled_tcmap = logical_id;
2907 case I40E_DEV_FUNC_CAP_FCOE:
2911 case I40E_DEV_FUNC_CAP_ISCSI:
2915 case I40E_DEV_FUNC_CAP_RSS:
2917 p->rss_table_size = number;
2918 p->rss_table_entry_width = logical_id;
2920 case I40E_DEV_FUNC_CAP_RX_QUEUES:
2921 p->num_rx_qp = number;
2922 p->base_queue = phys_id;
2924 case I40E_DEV_FUNC_CAP_TX_QUEUES:
2925 p->num_tx_qp = number;
2926 p->base_queue = phys_id;
2928 case I40E_DEV_FUNC_CAP_MSIX:
2929 p->num_msix_vectors = number;
2931 case I40E_DEV_FUNC_CAP_MSIX_VF:
2932 p->num_msix_vectors_vf = number;
2934 case I40E_DEV_FUNC_CAP_MFP_MODE_1:
2936 p->mfp_mode_1 = true;
2938 case I40E_DEV_FUNC_CAP_CEM:
2942 case I40E_DEV_FUNC_CAP_IWARP:
2946 case I40E_DEV_FUNC_CAP_LED:
2947 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2948 p->led[phys_id] = true;
2950 case I40E_DEV_FUNC_CAP_SDP:
2951 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2952 p->sdp[phys_id] = true;
2954 case I40E_DEV_FUNC_CAP_MDIO:
2956 p->mdio_port_num = phys_id;
2957 p->mdio_port_mode = logical_id;
2960 case I40E_DEV_FUNC_CAP_IEEE_1588:
2962 p->ieee_1588 = true;
2964 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
2966 p->fd_filters_guaranteed = number;
2967 p->fd_filters_best_effort = logical_id;
2974 #ifdef I40E_FCOE_ENA
2975 /* Software override ensuring FCoE is disabled if npar or mfp
2976 * mode because it is not supported in these modes.
2978 if (p->npar_enable || p->mfp_mode_1)
2981 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
2985 /* count the enabled ports (aka the "not disabled" ports) */
2987 for (i = 0; i < 4; i++) {
2988 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
2991 /* use AQ read to get the physical register offset instead
2992 * of the port relative offset
2994 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
2995 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
2999 valid_functions = p->valid_functions;
3001 while (valid_functions) {
3002 if (valid_functions & 1)
3004 valid_functions >>= 1;
3007 /* partition id is 1-based, and functions are evenly spread
3008 * across the ports as partitions
3010 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3011 hw->num_partitions = num_functions / hw->num_ports;
3013 /* additional HW specific goodies that might
3014 * someday be HW version specific
3016 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3020 * i40e_aq_discover_capabilities
3021 * @hw: pointer to the hw struct
3022 * @buff: a virtual buffer to hold the capabilities
3023 * @buff_size: Size of the virtual buffer
3024 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3025 * @list_type_opc: capabilities type to discover - pass in the command opcode
3026 * @cmd_details: pointer to command details structure or NULL
3028 * Get the device capabilities descriptions from the firmware
3030 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3031 void *buff, u16 buff_size, u16 *data_size,
3032 enum i40e_admin_queue_opc list_type_opc,
3033 struct i40e_asq_cmd_details *cmd_details)
3035 struct i40e_aqc_list_capabilites *cmd;
3036 struct i40e_aq_desc desc;
3037 enum i40e_status_code status = I40E_SUCCESS;
3039 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3041 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3042 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3043 status = I40E_ERR_PARAM;
3047 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3049 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3050 if (buff_size > I40E_AQ_LARGE_BUF)
3051 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3053 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3054 *data_size = LE16_TO_CPU(desc.datalen);
3059 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3067 * i40e_aq_update_nvm
3068 * @hw: pointer to the hw struct
3069 * @module_pointer: module pointer location in words from the NVM beginning
3070 * @offset: byte offset from the module beginning
3071 * @length: length of the section to be written (in bytes from the offset)
3072 * @data: command buffer (size [bytes] = length)
3073 * @last_command: tells if this is the last command in a series
3074 * @cmd_details: pointer to command details structure or NULL
3076 * Update the NVM using the admin queue commands
3078 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3079 u32 offset, u16 length, void *data,
3081 struct i40e_asq_cmd_details *cmd_details)
3083 struct i40e_aq_desc desc;
3084 struct i40e_aqc_nvm_update *cmd =
3085 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3086 enum i40e_status_code status;
3088 DEBUGFUNC("i40e_aq_update_nvm");
3090 /* In offset the highest byte must be zeroed. */
3091 if (offset & 0xFF000000) {
3092 status = I40E_ERR_PARAM;
3093 goto i40e_aq_update_nvm_exit;
3096 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3098 /* If this is the last command in a series, set the proper flag. */
3100 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3101 cmd->module_pointer = module_pointer;
3102 cmd->offset = CPU_TO_LE32(offset);
3103 cmd->length = CPU_TO_LE16(length);
3105 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3106 if (length > I40E_AQ_LARGE_BUF)
3107 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3109 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3111 i40e_aq_update_nvm_exit:
3116 * i40e_aq_get_lldp_mib
3117 * @hw: pointer to the hw struct
3118 * @bridge_type: type of bridge requested
3119 * @mib_type: Local, Remote or both Local and Remote MIBs
3120 * @buff: pointer to a user supplied buffer to store the MIB block
3121 * @buff_size: size of the buffer (in bytes)
3122 * @local_len : length of the returned Local LLDP MIB
3123 * @remote_len: length of the returned Remote LLDP MIB
3124 * @cmd_details: pointer to command details structure or NULL
3126 * Requests the complete LLDP MIB (entire packet).
3128 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3129 u8 mib_type, void *buff, u16 buff_size,
3130 u16 *local_len, u16 *remote_len,
3131 struct i40e_asq_cmd_details *cmd_details)
3133 struct i40e_aq_desc desc;
3134 struct i40e_aqc_lldp_get_mib *cmd =
3135 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3136 struct i40e_aqc_lldp_get_mib *resp =
3137 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3138 enum i40e_status_code status;
3140 if (buff_size == 0 || !buff)
3141 return I40E_ERR_PARAM;
3143 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3144 /* Indirect Command */
3145 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3147 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3148 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3149 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3151 desc.datalen = CPU_TO_LE16(buff_size);
3153 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3154 if (buff_size > I40E_AQ_LARGE_BUF)
3155 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3157 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3159 if (local_len != NULL)
3160 *local_len = LE16_TO_CPU(resp->local_len);
3161 if (remote_len != NULL)
3162 *remote_len = LE16_TO_CPU(resp->remote_len);
3169 * i40e_aq_set_lldp_mib - Set the LLDP MIB
3170 * @hw: pointer to the hw struct
3171 * @mib_type: Local, Remote or both Local and Remote MIBs
3172 * @buff: pointer to a user supplied buffer to store the MIB block
3173 * @buff_size: size of the buffer (in bytes)
3174 * @cmd_details: pointer to command details structure or NULL
3178 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
3179 u8 mib_type, void *buff, u16 buff_size,
3180 struct i40e_asq_cmd_details *cmd_details)
3182 struct i40e_aq_desc desc;
3183 struct i40e_aqc_lldp_set_local_mib *cmd =
3184 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
3185 enum i40e_status_code status;
3187 if (buff_size == 0 || !buff)
3188 return I40E_ERR_PARAM;
3190 i40e_fill_default_direct_cmd_desc(&desc,
3191 i40e_aqc_opc_lldp_set_local_mib);
3192 /* Indirect Command */
3193 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3194 if (buff_size > I40E_AQ_LARGE_BUF)
3195 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3196 desc.datalen = CPU_TO_LE16(buff_size);
3198 cmd->type = mib_type;
3199 cmd->length = CPU_TO_LE16(buff_size);
3200 cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
3201 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
3203 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3208 * i40e_aq_cfg_lldp_mib_change_event
3209 * @hw: pointer to the hw struct
3210 * @enable_update: Enable or Disable event posting
3211 * @cmd_details: pointer to command details structure or NULL
3213 * Enable or Disable posting of an event on ARQ when LLDP MIB
3214 * associated with the interface changes
3216 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3218 struct i40e_asq_cmd_details *cmd_details)
3220 struct i40e_aq_desc desc;
3221 struct i40e_aqc_lldp_update_mib *cmd =
3222 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3223 enum i40e_status_code status;
3225 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3228 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3230 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3236 * i40e_aq_add_lldp_tlv
3237 * @hw: pointer to the hw struct
3238 * @bridge_type: type of bridge
3239 * @buff: buffer with TLV to add
3240 * @buff_size: length of the buffer
3241 * @tlv_len: length of the TLV to be added
3242 * @mib_len: length of the LLDP MIB returned in response
3243 * @cmd_details: pointer to command details structure or NULL
3245 * Add the specified TLV to LLDP Local MIB for the given bridge type,
3246 * it is responsibility of the caller to make sure that the TLV is not
3247 * already present in the LLDPDU.
3248 * In return firmware will write the complete LLDP MIB with the newly
3249 * added TLV in the response buffer.
3251 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
3252 void *buff, u16 buff_size, u16 tlv_len,
3254 struct i40e_asq_cmd_details *cmd_details)
3256 struct i40e_aq_desc desc;
3257 struct i40e_aqc_lldp_add_tlv *cmd =
3258 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3259 enum i40e_status_code status;
3261 if (buff_size == 0 || !buff || tlv_len == 0)
3262 return I40E_ERR_PARAM;
3264 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
3266 /* Indirect Command */
3267 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3268 if (buff_size > I40E_AQ_LARGE_BUF)
3269 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3270 desc.datalen = CPU_TO_LE16(buff_size);
3272 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3273 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3274 cmd->len = CPU_TO_LE16(tlv_len);
3276 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3278 if (mib_len != NULL)
3279 *mib_len = LE16_TO_CPU(desc.datalen);
3286 * i40e_aq_update_lldp_tlv
3287 * @hw: pointer to the hw struct
3288 * @bridge_type: type of bridge
3289 * @buff: buffer with TLV to update
3290 * @buff_size: size of the buffer holding original and updated TLVs
3291 * @old_len: Length of the Original TLV
3292 * @new_len: Length of the Updated TLV
3293 * @offset: offset of the updated TLV in the buff
3294 * @mib_len: length of the returned LLDP MIB
3295 * @cmd_details: pointer to command details structure or NULL
3297 * Update the specified TLV to the LLDP Local MIB for the given bridge type.
3298 * Firmware will place the complete LLDP MIB in response buffer with the
3301 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
3302 u8 bridge_type, void *buff, u16 buff_size,
3303 u16 old_len, u16 new_len, u16 offset,
3305 struct i40e_asq_cmd_details *cmd_details)
3307 struct i40e_aq_desc desc;
3308 struct i40e_aqc_lldp_update_tlv *cmd =
3309 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
3310 enum i40e_status_code status;
3312 if (buff_size == 0 || !buff || offset == 0 ||
3313 old_len == 0 || new_len == 0)
3314 return I40E_ERR_PARAM;
3316 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
3318 /* Indirect Command */
3319 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3320 if (buff_size > I40E_AQ_LARGE_BUF)
3321 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3322 desc.datalen = CPU_TO_LE16(buff_size);
3324 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3325 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3326 cmd->old_len = CPU_TO_LE16(old_len);
3327 cmd->new_offset = CPU_TO_LE16(offset);
3328 cmd->new_len = CPU_TO_LE16(new_len);
3330 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3332 if (mib_len != NULL)
3333 *mib_len = LE16_TO_CPU(desc.datalen);
3340 * i40e_aq_delete_lldp_tlv
3341 * @hw: pointer to the hw struct
3342 * @bridge_type: type of bridge
3343 * @buff: pointer to a user supplied buffer that has the TLV
3344 * @buff_size: length of the buffer
3345 * @tlv_len: length of the TLV to be deleted
3346 * @mib_len: length of the returned LLDP MIB
3347 * @cmd_details: pointer to command details structure or NULL
3349 * Delete the specified TLV from LLDP Local MIB for the given bridge type.
3350 * The firmware places the entire LLDP MIB in the response buffer.
3352 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
3353 u8 bridge_type, void *buff, u16 buff_size,
3354 u16 tlv_len, u16 *mib_len,
3355 struct i40e_asq_cmd_details *cmd_details)
3357 struct i40e_aq_desc desc;
3358 struct i40e_aqc_lldp_add_tlv *cmd =
3359 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3360 enum i40e_status_code status;
3362 if (buff_size == 0 || !buff)
3363 return I40E_ERR_PARAM;
3365 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
3367 /* Indirect Command */
3368 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3369 if (buff_size > I40E_AQ_LARGE_BUF)
3370 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3371 desc.datalen = CPU_TO_LE16(buff_size);
3372 cmd->len = CPU_TO_LE16(tlv_len);
3373 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3374 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3376 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3378 if (mib_len != NULL)
3379 *mib_len = LE16_TO_CPU(desc.datalen);
3387 * @hw: pointer to the hw struct
3388 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3389 * @cmd_details: pointer to command details structure or NULL
3391 * Stop or Shutdown the embedded LLDP Agent
3393 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3394 struct i40e_asq_cmd_details *cmd_details)
3396 struct i40e_aq_desc desc;
3397 struct i40e_aqc_lldp_stop *cmd =
3398 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3399 enum i40e_status_code status;
3401 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3404 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3406 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3412 * i40e_aq_start_lldp
3413 * @hw: pointer to the hw struct
3414 * @cmd_details: pointer to command details structure or NULL
3416 * Start the embedded LLDP Agent on all ports.
3418 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
3419 struct i40e_asq_cmd_details *cmd_details)
3421 struct i40e_aq_desc desc;
3422 struct i40e_aqc_lldp_start *cmd =
3423 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3424 enum i40e_status_code status;
3426 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3428 cmd->command = I40E_AQ_LLDP_AGENT_START;
3430 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3436 * i40e_aq_get_cee_dcb_config
3437 * @hw: pointer to the hw struct
3438 * @buff: response buffer that stores CEE operational configuration
3439 * @buff_size: size of the buffer passed
3440 * @cmd_details: pointer to command details structure or NULL
3442 * Get CEE DCBX mode operational configuration from firmware
3444 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3445 void *buff, u16 buff_size,
3446 struct i40e_asq_cmd_details *cmd_details)
3448 struct i40e_aq_desc desc;
3449 enum i40e_status_code status;
3451 if (buff_size == 0 || !buff)
3452 return I40E_ERR_PARAM;
3454 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3456 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3457 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3464 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
3465 * @hw: pointer to the hw struct
3466 * @start_agent: True if DCBx Agent needs to be Started
3467 * False if DCBx Agent needs to be Stopped
3468 * @cmd_details: pointer to command details structure or NULL
3470 * Start/Stop the embedded dcbx Agent
3472 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
3474 struct i40e_asq_cmd_details *cmd_details)
3476 struct i40e_aq_desc desc;
3477 struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
3478 (struct i40e_aqc_lldp_stop_start_specific_agent *)
3480 enum i40e_status_code status;
3482 i40e_fill_default_direct_cmd_desc(&desc,
3483 i40e_aqc_opc_lldp_stop_start_spec_agent);
3486 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
3488 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3494 * i40e_aq_add_udp_tunnel
3495 * @hw: pointer to the hw struct
3496 * @udp_port: the UDP port to add
3497 * @header_len: length of the tunneling header length in DWords
3498 * @protocol_index: protocol index type
3499 * @filter_index: pointer to filter index
3500 * @cmd_details: pointer to command details structure or NULL
3502 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3503 u16 udp_port, u8 protocol_index,
3505 struct i40e_asq_cmd_details *cmd_details)
3507 struct i40e_aq_desc desc;
3508 struct i40e_aqc_add_udp_tunnel *cmd =
3509 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3510 struct i40e_aqc_del_udp_tunnel_completion *resp =
3511 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3512 enum i40e_status_code status;
3514 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3516 cmd->udp_port = CPU_TO_LE16(udp_port);
3517 cmd->protocol_type = protocol_index;
3519 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3521 if (!status && filter_index)
3522 *filter_index = resp->index;
3528 * i40e_aq_del_udp_tunnel
3529 * @hw: pointer to the hw struct
3530 * @index: filter index
3531 * @cmd_details: pointer to command details structure or NULL
3533 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3534 struct i40e_asq_cmd_details *cmd_details)
3536 struct i40e_aq_desc desc;
3537 struct i40e_aqc_remove_udp_tunnel *cmd =
3538 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3539 enum i40e_status_code status;
3541 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3545 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3551 * i40e_aq_get_switch_resource_alloc (0x0204)
3552 * @hw: pointer to the hw struct
3553 * @num_entries: pointer to u8 to store the number of resource entries returned
3554 * @buf: pointer to a user supplied buffer. This buffer must be large enough
3555 * to store the resource information for all resource types. Each
3556 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
3557 * @count: size, in bytes, of the buffer provided
3558 * @cmd_details: pointer to command details structure or NULL
3560 * Query the resources allocated to a function.
3562 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
3564 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
3566 struct i40e_asq_cmd_details *cmd_details)
3568 struct i40e_aq_desc desc;
3569 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
3570 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
3571 enum i40e_status_code status;
3572 u16 length = count * sizeof(*buf);
3574 i40e_fill_default_direct_cmd_desc(&desc,
3575 i40e_aqc_opc_get_switch_resource_alloc);
3577 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3578 if (length > I40E_AQ_LARGE_BUF)
3579 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3581 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
3583 if (!status && num_entries)
3584 *num_entries = cmd_resp->num_entries;
3590 * i40e_aq_delete_element - Delete switch element
3591 * @hw: pointer to the hw struct
3592 * @seid: the SEID to delete from the switch
3593 * @cmd_details: pointer to command details structure or NULL
3595 * This deletes a switch element from the switch.
3597 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3598 struct i40e_asq_cmd_details *cmd_details)
3600 struct i40e_aq_desc desc;
3601 struct i40e_aqc_switch_seid *cmd =
3602 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3603 enum i40e_status_code status;
3606 return I40E_ERR_PARAM;
3608 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3610 cmd->seid = CPU_TO_LE16(seid);
3612 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3618 * i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port
3619 * @hw: pointer to the hw struct
3620 * @flags: component flags
3621 * @mac_seid: uplink seid (MAC SEID)
3622 * @vsi_seid: connected vsi seid
3623 * @ret_seid: seid of create pv component
3625 * This instantiates an i40e port virtualizer with specified flags.
3626 * Depending on specified flags the port virtualizer can act as a
3627 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
3629 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
3630 u16 mac_seid, u16 vsi_seid,
3633 struct i40e_aq_desc desc;
3634 struct i40e_aqc_add_update_pv *cmd =
3635 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
3636 struct i40e_aqc_add_update_pv_completion *resp =
3637 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
3638 enum i40e_status_code status;
3641 return I40E_ERR_PARAM;
3643 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
3644 cmd->command_flags = CPU_TO_LE16(flags);
3645 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
3646 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
3648 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
3649 if (!status && ret_seid)
3650 *ret_seid = LE16_TO_CPU(resp->pv_seid);
3656 * i40e_aq_add_tag - Add an S/E-tag
3657 * @hw: pointer to the hw struct
3658 * @direct_to_queue: should s-tag direct flow to a specific queue
3659 * @vsi_seid: VSI SEID to use this tag
3660 * @tag: value of the tag
3661 * @queue_num: queue number, only valid is direct_to_queue is true
3662 * @tags_used: return value, number of tags in use by this PF
3663 * @tags_free: return value, number of unallocated tags
3664 * @cmd_details: pointer to command details structure or NULL
3666 * This associates an S- or E-tag to a VSI in the switch complex. It returns
3667 * the number of tags allocated by the PF, and the number of unallocated
3670 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
3671 u16 vsi_seid, u16 tag, u16 queue_num,
3672 u16 *tags_used, u16 *tags_free,
3673 struct i40e_asq_cmd_details *cmd_details)
3675 struct i40e_aq_desc desc;
3676 struct i40e_aqc_add_tag *cmd =
3677 (struct i40e_aqc_add_tag *)&desc.params.raw;
3678 struct i40e_aqc_add_remove_tag_completion *resp =
3679 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
3680 enum i40e_status_code status;
3683 return I40E_ERR_PARAM;
3685 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
3687 cmd->seid = CPU_TO_LE16(vsi_seid);
3688 cmd->tag = CPU_TO_LE16(tag);
3689 if (direct_to_queue) {
3690 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
3691 cmd->queue_number = CPU_TO_LE16(queue_num);
3694 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3697 if (tags_used != NULL)
3698 *tags_used = LE16_TO_CPU(resp->tags_used);
3699 if (tags_free != NULL)
3700 *tags_free = LE16_TO_CPU(resp->tags_free);
3707 * i40e_aq_remove_tag - Remove an S- or E-tag
3708 * @hw: pointer to the hw struct
3709 * @vsi_seid: VSI SEID this tag is associated with
3710 * @tag: value of the S-tag to delete
3711 * @tags_used: return value, number of tags in use by this PF
3712 * @tags_free: return value, number of unallocated tags
3713 * @cmd_details: pointer to command details structure or NULL
3715 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
3716 * the number of tags allocated by the PF, and the number of unallocated
3719 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
3720 u16 tag, u16 *tags_used, u16 *tags_free,
3721 struct i40e_asq_cmd_details *cmd_details)
3723 struct i40e_aq_desc desc;
3724 struct i40e_aqc_remove_tag *cmd =
3725 (struct i40e_aqc_remove_tag *)&desc.params.raw;
3726 struct i40e_aqc_add_remove_tag_completion *resp =
3727 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
3728 enum i40e_status_code status;
3731 return I40E_ERR_PARAM;
3733 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
3735 cmd->seid = CPU_TO_LE16(vsi_seid);
3736 cmd->tag = CPU_TO_LE16(tag);
3738 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3741 if (tags_used != NULL)
3742 *tags_used = LE16_TO_CPU(resp->tags_used);
3743 if (tags_free != NULL)
3744 *tags_free = LE16_TO_CPU(resp->tags_free);
3751 * i40e_aq_add_mcast_etag - Add a multicast E-tag
3752 * @hw: pointer to the hw struct
3753 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
3754 * @etag: value of E-tag to add
3755 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
3756 * @buf: address of indirect buffer
3757 * @tags_used: return value, number of E-tags in use by this port
3758 * @tags_free: return value, number of unallocated M-tags
3759 * @cmd_details: pointer to command details structure or NULL
3761 * This associates a multicast E-tag to a port virtualizer. It will return
3762 * the number of tags allocated by the PF, and the number of unallocated
3765 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
3766 * num_tags_in_buf long.
3768 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
3769 u16 etag, u8 num_tags_in_buf, void *buf,
3770 u16 *tags_used, u16 *tags_free,
3771 struct i40e_asq_cmd_details *cmd_details)
3773 struct i40e_aq_desc desc;
3774 struct i40e_aqc_add_remove_mcast_etag *cmd =
3775 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
3776 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
3777 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
3778 enum i40e_status_code status;
3779 u16 length = sizeof(u16) * num_tags_in_buf;
3781 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
3782 return I40E_ERR_PARAM;
3784 i40e_fill_default_direct_cmd_desc(&desc,
3785 i40e_aqc_opc_add_multicast_etag);
3787 cmd->pv_seid = CPU_TO_LE16(pv_seid);
3788 cmd->etag = CPU_TO_LE16(etag);
3789 cmd->num_unicast_etags = num_tags_in_buf;
3791 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3792 if (length > I40E_AQ_LARGE_BUF)
3793 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3795 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
3798 if (tags_used != NULL)
3799 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
3800 if (tags_free != NULL)
3801 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
3808 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
3809 * @hw: pointer to the hw struct
3810 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
3811 * @etag: value of the E-tag to remove
3812 * @tags_used: return value, number of tags in use by this port
3813 * @tags_free: return value, number of unallocated tags
3814 * @cmd_details: pointer to command details structure or NULL
3816 * This deletes an E-tag from the port virtualizer. It will return
3817 * the number of tags allocated by the port, and the number of unallocated
3820 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
3821 u16 etag, u16 *tags_used, u16 *tags_free,
3822 struct i40e_asq_cmd_details *cmd_details)
3824 struct i40e_aq_desc desc;
3825 struct i40e_aqc_add_remove_mcast_etag *cmd =
3826 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
3827 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
3828 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
3829 enum i40e_status_code status;
3833 return I40E_ERR_PARAM;
3835 i40e_fill_default_direct_cmd_desc(&desc,
3836 i40e_aqc_opc_remove_multicast_etag);
3838 cmd->pv_seid = CPU_TO_LE16(pv_seid);
3839 cmd->etag = CPU_TO_LE16(etag);
3841 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3844 if (tags_used != NULL)
3845 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
3846 if (tags_free != NULL)
3847 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
3854 * i40e_aq_update_tag - Update an S/E-tag
3855 * @hw: pointer to the hw struct
3856 * @vsi_seid: VSI SEID using this S-tag
3857 * @old_tag: old tag value
3858 * @new_tag: new tag value
3859 * @tags_used: return value, number of tags in use by this PF
3860 * @tags_free: return value, number of unallocated tags
3861 * @cmd_details: pointer to command details structure or NULL
3863 * This updates the value of the tag currently attached to this VSI
3864 * in the switch complex. It will return the number of tags allocated
3865 * by the PF, and the number of unallocated tags available.
3867 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
3868 u16 old_tag, u16 new_tag, u16 *tags_used,
3870 struct i40e_asq_cmd_details *cmd_details)
3872 struct i40e_aq_desc desc;
3873 struct i40e_aqc_update_tag *cmd =
3874 (struct i40e_aqc_update_tag *)&desc.params.raw;
3875 struct i40e_aqc_update_tag_completion *resp =
3876 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
3877 enum i40e_status_code status;
3880 return I40E_ERR_PARAM;
3882 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
3884 cmd->seid = CPU_TO_LE16(vsi_seid);
3885 cmd->old_tag = CPU_TO_LE16(old_tag);
3886 cmd->new_tag = CPU_TO_LE16(new_tag);
3888 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3891 if (tags_used != NULL)
3892 *tags_used = LE16_TO_CPU(resp->tags_used);
3893 if (tags_free != NULL)
3894 *tags_free = LE16_TO_CPU(resp->tags_free);
3901 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
3902 * @hw: pointer to the hw struct
3903 * @tcmap: TC map for request/release any ignore PFC condition
3904 * @request: request or release ignore PFC condition
3905 * @tcmap_ret: return TCs for which PFC is currently ignored
3906 * @cmd_details: pointer to command details structure or NULL
3908 * This sends out request/release to ignore PFC condition for a TC.
3909 * It will return the TCs for which PFC is currently ignored.
3911 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
3912 bool request, u8 *tcmap_ret,
3913 struct i40e_asq_cmd_details *cmd_details)
3915 struct i40e_aq_desc desc;
3916 struct i40e_aqc_pfc_ignore *cmd_resp =
3917 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
3918 enum i40e_status_code status;
3920 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
3923 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
3925 cmd_resp->tc_bitmap = tcmap;
3927 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3930 if (tcmap_ret != NULL)
3931 *tcmap_ret = cmd_resp->tc_bitmap;
3938 * i40e_aq_dcb_updated - DCB Updated Command
3939 * @hw: pointer to the hw struct
3940 * @cmd_details: pointer to command details structure or NULL
3942 * When LLDP is handled in PF this command is used by the PF
3943 * to notify EMP that a DCB setting is modified.
3944 * When LLDP is handled in EMP this command is used by the PF
3945 * to notify EMP whenever one of the following parameters get
3947 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
3948 * - PCIRTT in PRTDCB_GENC.PCIRTT
3949 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
3950 * EMP will return when the shared RPB settings have been
3951 * recomputed and modified. The retval field in the descriptor
3952 * will be set to 0 when RPB is modified.
3954 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
3955 struct i40e_asq_cmd_details *cmd_details)
3957 struct i40e_aq_desc desc;
3958 enum i40e_status_code status;
3960 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3962 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3968 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
3969 * @hw: pointer to the hw struct
3970 * @seid: defines the SEID of the switch for which the stats are requested
3971 * @vlan_id: the VLAN ID for which the statistics are requested
3972 * @stat_index: index of the statistics counters block assigned to this VLAN
3973 * @cmd_details: pointer to command details structure or NULL
3975 * XL710 supports 128 smonVlanStats counters.This command is used to
3976 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
3979 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
3980 u16 vlan_id, u16 *stat_index,
3981 struct i40e_asq_cmd_details *cmd_details)
3983 struct i40e_aq_desc desc;
3984 struct i40e_aqc_add_remove_statistics *cmd_resp =
3985 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
3986 enum i40e_status_code status;
3988 if ((seid == 0) || (stat_index == NULL))
3989 return I40E_ERR_PARAM;
3991 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
3993 cmd_resp->seid = CPU_TO_LE16(seid);
3994 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
3996 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3998 if (!status && stat_index)
3999 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4005 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4006 * @hw: pointer to the hw struct
4007 * @seid: defines the SEID of the switch for which the stats are requested
4008 * @vlan_id: the VLAN ID for which the statistics are requested
4009 * @stat_index: index of the statistics counters block assigned to this VLAN
4010 * @cmd_details: pointer to command details structure or NULL
4012 * XL710 supports 128 smonVlanStats counters.This command is used to
4013 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4016 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4017 u16 vlan_id, u16 stat_index,
4018 struct i40e_asq_cmd_details *cmd_details)
4020 struct i40e_aq_desc desc;
4021 struct i40e_aqc_add_remove_statistics *cmd =
4022 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4023 enum i40e_status_code status;
4026 return I40E_ERR_PARAM;
4028 i40e_fill_default_direct_cmd_desc(&desc,
4029 i40e_aqc_opc_remove_statistics);
4031 cmd->seid = CPU_TO_LE16(seid);
4032 cmd->vlan = CPU_TO_LE16(vlan_id);
4033 cmd->stat_index = CPU_TO_LE16(stat_index);
4035 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4041 * i40e_aq_set_port_parameters - set physical port parameters.
4042 * @hw: pointer to the hw struct
4043 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4044 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4045 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4046 * @double_vlan: if set double VLAN is enabled
4047 * @cmd_details: pointer to command details structure or NULL
4049 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4050 u16 bad_frame_vsi, bool save_bad_pac,
4051 bool pad_short_pac, bool double_vlan,
4052 struct i40e_asq_cmd_details *cmd_details)
4054 struct i40e_aqc_set_port_parameters *cmd;
4055 enum i40e_status_code status;
4056 struct i40e_aq_desc desc;
4057 u16 command_flags = 0;
4059 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4061 i40e_fill_default_direct_cmd_desc(&desc,
4062 i40e_aqc_opc_set_port_parameters);
4064 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4066 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4068 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4070 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4071 cmd->command_flags = CPU_TO_LE16(command_flags);
4073 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4079 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
4080 * @hw: pointer to the hw struct
4081 * @seid: seid for the physical port/switching component/vsi
4082 * @buff: Indirect buffer to hold data parameters and response
4083 * @buff_size: Indirect buffer size
4084 * @opcode: Tx scheduler AQ command opcode
4085 * @cmd_details: pointer to command details structure or NULL
4087 * Generic command handler for Tx scheduler AQ commands
4089 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
4090 void *buff, u16 buff_size,
4091 enum i40e_admin_queue_opc opcode,
4092 struct i40e_asq_cmd_details *cmd_details)
4094 struct i40e_aq_desc desc;
4095 struct i40e_aqc_tx_sched_ind *cmd =
4096 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4097 enum i40e_status_code status;
4098 bool cmd_param_flag = false;
4101 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
4102 case i40e_aqc_opc_configure_vsi_tc_bw:
4103 case i40e_aqc_opc_enable_switching_comp_ets:
4104 case i40e_aqc_opc_modify_switching_comp_ets:
4105 case i40e_aqc_opc_disable_switching_comp_ets:
4106 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
4107 case i40e_aqc_opc_configure_switching_comp_bw_config:
4108 cmd_param_flag = true;
4110 case i40e_aqc_opc_query_vsi_bw_config:
4111 case i40e_aqc_opc_query_vsi_ets_sla_config:
4112 case i40e_aqc_opc_query_switching_comp_ets_config:
4113 case i40e_aqc_opc_query_port_ets_config:
4114 case i40e_aqc_opc_query_switching_comp_bw_config:
4115 cmd_param_flag = false;
4118 return I40E_ERR_PARAM;
4121 i40e_fill_default_direct_cmd_desc(&desc, opcode);
4123 /* Indirect command */
4124 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4126 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4127 if (buff_size > I40E_AQ_LARGE_BUF)
4128 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4130 desc.datalen = CPU_TO_LE16(buff_size);
4132 cmd->vsi_seid = CPU_TO_LE16(seid);
4134 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4140 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
4141 * @hw: pointer to the hw struct
4143 * @credit: BW limit credits (0 = disabled)
4144 * @max_credit: Max BW limit credits
4145 * @cmd_details: pointer to command details structure or NULL
4147 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
4148 u16 seid, u16 credit, u8 max_credit,
4149 struct i40e_asq_cmd_details *cmd_details)
4151 struct i40e_aq_desc desc;
4152 struct i40e_aqc_configure_vsi_bw_limit *cmd =
4153 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
4154 enum i40e_status_code status;
4156 i40e_fill_default_direct_cmd_desc(&desc,
4157 i40e_aqc_opc_configure_vsi_bw_limit);
4159 cmd->vsi_seid = CPU_TO_LE16(seid);
4160 cmd->credit = CPU_TO_LE16(credit);
4161 cmd->max_credit = max_credit;
4163 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4169 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
4170 * @hw: pointer to the hw struct
4171 * @seid: switching component seid
4172 * @credit: BW limit credits (0 = disabled)
4173 * @max_bw: Max BW limit credits
4174 * @cmd_details: pointer to command details structure or NULL
4176 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
4177 u16 seid, u16 credit, u8 max_bw,
4178 struct i40e_asq_cmd_details *cmd_details)
4180 struct i40e_aq_desc desc;
4181 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
4182 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
4183 enum i40e_status_code status;
4185 i40e_fill_default_direct_cmd_desc(&desc,
4186 i40e_aqc_opc_configure_switching_comp_bw_limit);
4188 cmd->seid = CPU_TO_LE16(seid);
4189 cmd->credit = CPU_TO_LE16(credit);
4190 cmd->max_bw = max_bw;
4192 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4198 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
4199 * @hw: pointer to the hw struct
4201 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4202 * @cmd_details: pointer to command details structure or NULL
4204 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
4206 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
4207 struct i40e_asq_cmd_details *cmd_details)
4209 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4210 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
4215 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
4216 * @hw: pointer to the hw struct
4218 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
4219 * @cmd_details: pointer to command details structure or NULL
4221 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
4223 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
4224 struct i40e_asq_cmd_details *cmd_details)
4226 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4227 i40e_aqc_opc_configure_vsi_tc_bw,
4232 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
4233 * @hw: pointer to the hw struct
4234 * @seid: seid of the switching component
4235 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4236 * @cmd_details: pointer to command details structure or NULL
4238 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
4239 struct i40e_hw *hw, u16 seid,
4240 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
4241 struct i40e_asq_cmd_details *cmd_details)
4243 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4244 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
4249 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
4250 * @hw: pointer to the hw struct
4251 * @seid: seid of the VSI
4252 * @bw_data: Buffer to hold VSI BW configuration
4253 * @cmd_details: pointer to command details structure or NULL
4255 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
4257 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
4258 struct i40e_asq_cmd_details *cmd_details)
4260 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4261 i40e_aqc_opc_query_vsi_bw_config,
4266 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
4267 * @hw: pointer to the hw struct
4268 * @seid: seid of the VSI
4269 * @bw_data: Buffer to hold VSI BW configuration per TC
4270 * @cmd_details: pointer to command details structure or NULL
4272 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
4274 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
4275 struct i40e_asq_cmd_details *cmd_details)
4277 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4278 i40e_aqc_opc_query_vsi_ets_sla_config,
4283 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
4284 * @hw: pointer to the hw struct
4285 * @seid: seid of the switching component
4286 * @bw_data: Buffer to hold switching component's per TC BW config
4287 * @cmd_details: pointer to command details structure or NULL
4289 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
4291 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
4292 struct i40e_asq_cmd_details *cmd_details)
4294 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4295 i40e_aqc_opc_query_switching_comp_ets_config,
4300 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
4301 * @hw: pointer to the hw struct
4302 * @seid: seid of the VSI or switching component connected to Physical Port
4303 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
4304 * @cmd_details: pointer to command details structure or NULL
4306 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
4308 struct i40e_aqc_query_port_ets_config_resp *bw_data,
4309 struct i40e_asq_cmd_details *cmd_details)
4311 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4312 i40e_aqc_opc_query_port_ets_config,
4317 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
4318 * @hw: pointer to the hw struct
4319 * @seid: seid of the switching component
4320 * @bw_data: Buffer to hold switching component's BW configuration
4321 * @cmd_details: pointer to command details structure or NULL
4323 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
4325 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
4326 struct i40e_asq_cmd_details *cmd_details)
4328 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4329 i40e_aqc_opc_query_switching_comp_bw_config,
4334 * i40e_validate_filter_settings
4335 * @hw: pointer to the hardware structure
4336 * @settings: Filter control settings
4338 * Check and validate the filter control settings passed.
4339 * The function checks for the valid filter/context sizes being
4340 * passed for FCoE and PE.
4342 * Returns I40E_SUCCESS if the values passed are valid and within
4343 * range else returns an error.
4345 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
4346 struct i40e_filter_control_settings *settings)
4348 u32 fcoe_cntx_size, fcoe_filt_size;
4349 u32 pe_cntx_size, pe_filt_size;
4354 /* Validate FCoE settings passed */
4355 switch (settings->fcoe_filt_num) {
4356 case I40E_HASH_FILTER_SIZE_1K:
4357 case I40E_HASH_FILTER_SIZE_2K:
4358 case I40E_HASH_FILTER_SIZE_4K:
4359 case I40E_HASH_FILTER_SIZE_8K:
4360 case I40E_HASH_FILTER_SIZE_16K:
4361 case I40E_HASH_FILTER_SIZE_32K:
4362 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4363 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
4366 return I40E_ERR_PARAM;
4369 switch (settings->fcoe_cntx_num) {
4370 case I40E_DMA_CNTX_SIZE_512:
4371 case I40E_DMA_CNTX_SIZE_1K:
4372 case I40E_DMA_CNTX_SIZE_2K:
4373 case I40E_DMA_CNTX_SIZE_4K:
4374 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4375 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
4378 return I40E_ERR_PARAM;
4381 /* Validate PE settings passed */
4382 switch (settings->pe_filt_num) {
4383 case I40E_HASH_FILTER_SIZE_1K:
4384 case I40E_HASH_FILTER_SIZE_2K:
4385 case I40E_HASH_FILTER_SIZE_4K:
4386 case I40E_HASH_FILTER_SIZE_8K:
4387 case I40E_HASH_FILTER_SIZE_16K:
4388 case I40E_HASH_FILTER_SIZE_32K:
4389 case I40E_HASH_FILTER_SIZE_64K:
4390 case I40E_HASH_FILTER_SIZE_128K:
4391 case I40E_HASH_FILTER_SIZE_256K:
4392 case I40E_HASH_FILTER_SIZE_512K:
4393 case I40E_HASH_FILTER_SIZE_1M:
4394 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4395 pe_filt_size <<= (u32)settings->pe_filt_num;
4398 return I40E_ERR_PARAM;
4401 switch (settings->pe_cntx_num) {
4402 case I40E_DMA_CNTX_SIZE_512:
4403 case I40E_DMA_CNTX_SIZE_1K:
4404 case I40E_DMA_CNTX_SIZE_2K:
4405 case I40E_DMA_CNTX_SIZE_4K:
4406 case I40E_DMA_CNTX_SIZE_8K:
4407 case I40E_DMA_CNTX_SIZE_16K:
4408 case I40E_DMA_CNTX_SIZE_32K:
4409 case I40E_DMA_CNTX_SIZE_64K:
4410 case I40E_DMA_CNTX_SIZE_128K:
4411 case I40E_DMA_CNTX_SIZE_256K:
4412 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4413 pe_cntx_size <<= (u32)settings->pe_cntx_num;
4416 return I40E_ERR_PARAM;
4419 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
4420 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
4421 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
4422 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
4423 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
4424 return I40E_ERR_INVALID_SIZE;
4426 return I40E_SUCCESS;
4430 * i40e_set_filter_control
4431 * @hw: pointer to the hardware structure
4432 * @settings: Filter control settings
4434 * Set the Queue Filters for PE/FCoE and enable filters required
4435 * for a single PF. It is expected that these settings are programmed
4436 * at the driver initialization time.
4438 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
4439 struct i40e_filter_control_settings *settings)
4441 enum i40e_status_code ret = I40E_SUCCESS;
4442 u32 hash_lut_size = 0;
4446 return I40E_ERR_PARAM;
4448 /* Validate the input settings */
4449 ret = i40e_validate_filter_settings(hw, settings);
4453 /* Read the PF Queue Filter control register */
4454 val = rd32(hw, I40E_PFQF_CTL_0);
4456 /* Program required PE hash buckets for the PF */
4457 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
4458 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
4459 I40E_PFQF_CTL_0_PEHSIZE_MASK;
4460 /* Program required PE contexts for the PF */
4461 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
4462 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
4463 I40E_PFQF_CTL_0_PEDSIZE_MASK;
4465 /* Program required FCoE hash buckets for the PF */
4466 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4467 val |= ((u32)settings->fcoe_filt_num <<
4468 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
4469 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4470 /* Program required FCoE DDP contexts for the PF */
4471 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4472 val |= ((u32)settings->fcoe_cntx_num <<
4473 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
4474 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4476 /* Program Hash LUT size for the PF */
4477 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4478 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
4480 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
4481 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4483 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
4484 if (settings->enable_fdir)
4485 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
4486 if (settings->enable_ethtype)
4487 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
4488 if (settings->enable_macvlan)
4489 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
4491 wr32(hw, I40E_PFQF_CTL_0, val);
4493 return I40E_SUCCESS;
4497 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
4498 * @hw: pointer to the hw struct
4499 * @mac_addr: MAC address to use in the filter
4500 * @ethtype: Ethertype to use in the filter
4501 * @flags: Flags that needs to be applied to the filter
4502 * @vsi_seid: seid of the control VSI
4503 * @queue: VSI queue number to send the packet to
4504 * @is_add: Add control packet filter if True else remove
4505 * @stats: Structure to hold information on control filter counts
4506 * @cmd_details: pointer to command details structure or NULL
4508 * This command will Add or Remove control packet filter for a control VSI.
4509 * In return it will update the total number of perfect filter count in
4512 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
4513 u8 *mac_addr, u16 ethtype, u16 flags,
4514 u16 vsi_seid, u16 queue, bool is_add,
4515 struct i40e_control_filter_stats *stats,
4516 struct i40e_asq_cmd_details *cmd_details)
4518 struct i40e_aq_desc desc;
4519 struct i40e_aqc_add_remove_control_packet_filter *cmd =
4520 (struct i40e_aqc_add_remove_control_packet_filter *)
4522 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
4523 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
4525 enum i40e_status_code status;
4528 return I40E_ERR_PARAM;
4531 i40e_fill_default_direct_cmd_desc(&desc,
4532 i40e_aqc_opc_add_control_packet_filter);
4533 cmd->queue = CPU_TO_LE16(queue);
4535 i40e_fill_default_direct_cmd_desc(&desc,
4536 i40e_aqc_opc_remove_control_packet_filter);
4540 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
4541 I40E_NONDMA_TO_NONDMA);
4543 cmd->etype = CPU_TO_LE16(ethtype);
4544 cmd->flags = CPU_TO_LE16(flags);
4545 cmd->seid = CPU_TO_LE16(vsi_seid);
4547 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4549 if (!status && stats) {
4550 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
4551 stats->etype_used = LE16_TO_CPU(resp->etype_used);
4552 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
4553 stats->etype_free = LE16_TO_CPU(resp->etype_free);
4560 * i40e_aq_add_cloud_filters
4561 * @hw: pointer to the hardware structure
4562 * @seid: VSI seid to add cloud filters from
4563 * @filters: Buffer which contains the filters to be added
4564 * @filter_count: number of filters contained in the buffer
4566 * Set the cloud filters for a given VSI. The contents of the
4567 * i40e_aqc_add_remove_cloud_filters_element_data are filled
4568 * in by the caller of the function.
4571 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
4573 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
4576 struct i40e_aq_desc desc;
4577 struct i40e_aqc_add_remove_cloud_filters *cmd =
4578 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
4580 enum i40e_status_code status;
4582 i40e_fill_default_direct_cmd_desc(&desc,
4583 i40e_aqc_opc_add_cloud_filters);
4585 buff_len = filter_count * sizeof(*filters);
4586 desc.datalen = CPU_TO_LE16(buff_len);
4587 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4588 cmd->num_filters = filter_count;
4589 cmd->seid = CPU_TO_LE16(seid);
4591 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
4597 * i40e_aq_remove_cloud_filters
4598 * @hw: pointer to the hardware structure
4599 * @seid: VSI seid to remove cloud filters from
4600 * @filters: Buffer which contains the filters to be removed
4601 * @filter_count: number of filters contained in the buffer
4603 * Remove the cloud filters for a given VSI. The contents of the
4604 * i40e_aqc_add_remove_cloud_filters_element_data are filled
4605 * in by the caller of the function.
4608 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
4610 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
4613 struct i40e_aq_desc desc;
4614 struct i40e_aqc_add_remove_cloud_filters *cmd =
4615 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
4616 enum i40e_status_code status;
4619 i40e_fill_default_direct_cmd_desc(&desc,
4620 i40e_aqc_opc_remove_cloud_filters);
4622 buff_len = filter_count * sizeof(*filters);
4623 desc.datalen = CPU_TO_LE16(buff_len);
4624 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4625 cmd->num_filters = filter_count;
4626 cmd->seid = CPU_TO_LE16(seid);
4628 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
4634 * i40e_aq_alternate_write
4635 * @hw: pointer to the hardware structure
4636 * @reg_addr0: address of first dword to be read
4637 * @reg_val0: value to be written under 'reg_addr0'
4638 * @reg_addr1: address of second dword to be read
4639 * @reg_val1: value to be written under 'reg_addr1'
4641 * Write one or two dwords to alternate structure. Fields are indicated
4642 * by 'reg_addr0' and 'reg_addr1' register numbers.
4645 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
4646 u32 reg_addr0, u32 reg_val0,
4647 u32 reg_addr1, u32 reg_val1)
4649 struct i40e_aq_desc desc;
4650 struct i40e_aqc_alternate_write *cmd_resp =
4651 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4652 enum i40e_status_code status;
4654 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
4655 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
4656 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
4657 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
4658 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
4660 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4666 * i40e_aq_alternate_write_indirect
4667 * @hw: pointer to the hardware structure
4668 * @addr: address of a first register to be modified
4669 * @dw_count: number of alternate structure fields to write
4670 * @buffer: pointer to the command buffer
4672 * Write 'dw_count' dwords from 'buffer' to alternate structure
4673 * starting at 'addr'.
4676 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
4677 u32 addr, u32 dw_count, void *buffer)
4679 struct i40e_aq_desc desc;
4680 struct i40e_aqc_alternate_ind_write *cmd_resp =
4681 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
4682 enum i40e_status_code status;
4685 return I40E_ERR_PARAM;
4687 /* Indirect command */
4688 i40e_fill_default_direct_cmd_desc(&desc,
4689 i40e_aqc_opc_alternate_write_indirect);
4691 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
4692 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
4693 if (dw_count > (I40E_AQ_LARGE_BUF/4))
4694 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4696 cmd_resp->address = CPU_TO_LE32(addr);
4697 cmd_resp->length = CPU_TO_LE32(dw_count);
4698 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_WORD((u64)buffer));
4699 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
4701 status = i40e_asq_send_command(hw, &desc, buffer,
4702 I40E_LO_DWORD(4*dw_count), NULL);
4708 * i40e_aq_alternate_read
4709 * @hw: pointer to the hardware structure
4710 * @reg_addr0: address of first dword to be read
4711 * @reg_val0: pointer for data read from 'reg_addr0'
4712 * @reg_addr1: address of second dword to be read
4713 * @reg_val1: pointer for data read from 'reg_addr1'
4715 * Read one or two dwords from alternate structure. Fields are indicated
4716 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
4717 * is not passed then only register at 'reg_addr0' is read.
4720 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
4721 u32 reg_addr0, u32 *reg_val0,
4722 u32 reg_addr1, u32 *reg_val1)
4724 struct i40e_aq_desc desc;
4725 struct i40e_aqc_alternate_write *cmd_resp =
4726 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4727 enum i40e_status_code status;
4729 if (reg_val0 == NULL)
4730 return I40E_ERR_PARAM;
4732 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
4733 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
4734 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
4736 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4738 if (status == I40E_SUCCESS) {
4739 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
4741 if (reg_val1 != NULL)
4742 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
4749 * i40e_aq_alternate_read_indirect
4750 * @hw: pointer to the hardware structure
4751 * @addr: address of the alternate structure field
4752 * @dw_count: number of alternate structure fields to read
4753 * @buffer: pointer to the command buffer
4755 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
4756 * place them in 'buffer'. The buffer should be allocated by caller.
4759 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
4760 u32 addr, u32 dw_count, void *buffer)
4762 struct i40e_aq_desc desc;
4763 struct i40e_aqc_alternate_ind_write *cmd_resp =
4764 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
4765 enum i40e_status_code status;
4768 return I40E_ERR_PARAM;
4770 /* Indirect command */
4771 i40e_fill_default_direct_cmd_desc(&desc,
4772 i40e_aqc_opc_alternate_read_indirect);
4774 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
4775 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
4776 if (dw_count > (I40E_AQ_LARGE_BUF/4))
4777 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4779 cmd_resp->address = CPU_TO_LE32(addr);
4780 cmd_resp->length = CPU_TO_LE32(dw_count);
4781 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_DWORD((u64)buffer));
4782 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
4784 status = i40e_asq_send_command(hw, &desc, buffer,
4785 I40E_LO_DWORD(4*dw_count), NULL);
4791 * i40e_aq_alternate_clear
4792 * @hw: pointer to the HW structure.
4794 * Clear the alternate structures of the port from which the function
4798 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
4800 struct i40e_aq_desc desc;
4801 enum i40e_status_code status;
4803 i40e_fill_default_direct_cmd_desc(&desc,
4804 i40e_aqc_opc_alternate_clear_port);
4806 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4812 * i40e_aq_alternate_write_done
4813 * @hw: pointer to the HW structure.
4814 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
4815 * @reset_needed: indicates the SW should trigger GLOBAL reset
4817 * Indicates to the FW that alternate structures have been changed.
4820 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
4821 u8 bios_mode, bool *reset_needed)
4823 struct i40e_aq_desc desc;
4824 struct i40e_aqc_alternate_write_done *cmd =
4825 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
4826 enum i40e_status_code status;
4828 if (reset_needed == NULL)
4829 return I40E_ERR_PARAM;
4831 i40e_fill_default_direct_cmd_desc(&desc,
4832 i40e_aqc_opc_alternate_write_done);
4834 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
4836 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4837 if (!status && reset_needed)
4838 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
4839 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
4845 * i40e_aq_set_oem_mode
4846 * @hw: pointer to the HW structure.
4847 * @oem_mode: the OEM mode to be used
4849 * Sets the device to a specific operating mode. Currently the only supported
4850 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
4853 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
4856 struct i40e_aq_desc desc;
4857 struct i40e_aqc_alternate_write_done *cmd =
4858 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
4859 enum i40e_status_code status;
4861 i40e_fill_default_direct_cmd_desc(&desc,
4862 i40e_aqc_opc_alternate_set_mode);
4864 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
4866 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4872 * i40e_aq_resume_port_tx
4873 * @hw: pointer to the hardware structure
4874 * @cmd_details: pointer to command details structure or NULL
4876 * Resume port's Tx traffic
4878 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
4879 struct i40e_asq_cmd_details *cmd_details)
4881 struct i40e_aq_desc desc;
4882 enum i40e_status_code status;
4884 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
4886 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4892 * i40e_set_pci_config_data - store PCI bus info
4893 * @hw: pointer to hardware structure
4894 * @link_status: the link status word from PCI config space
4896 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
4898 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
4900 hw->bus.type = i40e_bus_type_pci_express;
4902 switch (link_status & I40E_PCI_LINK_WIDTH) {
4903 case I40E_PCI_LINK_WIDTH_1:
4904 hw->bus.width = i40e_bus_width_pcie_x1;
4906 case I40E_PCI_LINK_WIDTH_2:
4907 hw->bus.width = i40e_bus_width_pcie_x2;
4909 case I40E_PCI_LINK_WIDTH_4:
4910 hw->bus.width = i40e_bus_width_pcie_x4;
4912 case I40E_PCI_LINK_WIDTH_8:
4913 hw->bus.width = i40e_bus_width_pcie_x8;
4916 hw->bus.width = i40e_bus_width_unknown;
4920 switch (link_status & I40E_PCI_LINK_SPEED) {
4921 case I40E_PCI_LINK_SPEED_2500:
4922 hw->bus.speed = i40e_bus_speed_2500;
4924 case I40E_PCI_LINK_SPEED_5000:
4925 hw->bus.speed = i40e_bus_speed_5000;
4927 case I40E_PCI_LINK_SPEED_8000:
4928 hw->bus.speed = i40e_bus_speed_8000;
4931 hw->bus.speed = i40e_bus_speed_unknown;
4937 * i40e_read_bw_from_alt_ram
4938 * @hw: pointer to the hardware structure
4939 * @max_bw: pointer for max_bw read
4940 * @min_bw: pointer for min_bw read
4941 * @min_valid: pointer for bool that is true if min_bw is a valid value
4942 * @max_valid: pointer for bool that is true if max_bw is a valid value
4944 * Read bw from the alternate ram for the given pf
4946 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
4947 u32 *max_bw, u32 *min_bw,
4948 bool *min_valid, bool *max_valid)
4950 enum i40e_status_code status;
4951 u32 max_bw_addr, min_bw_addr;
4953 /* Calculate the address of the min/max bw registers */
4954 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4955 I40E_ALT_STRUCT_MAX_BW_OFFSET +
4956 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
4957 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4958 I40E_ALT_STRUCT_MIN_BW_OFFSET +
4959 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
4961 /* Read the bandwidths from alt ram */
4962 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
4963 min_bw_addr, min_bw);
4965 if (*min_bw & I40E_ALT_BW_VALID_MASK)
4970 if (*max_bw & I40E_ALT_BW_VALID_MASK)
4979 * i40e_aq_configure_partition_bw
4980 * @hw: pointer to the hardware structure
4981 * @bw_data: Buffer holding valid pfs and bw limits
4982 * @cmd_details: pointer to command details
4984 * Configure partitions guaranteed/max bw
4986 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
4987 struct i40e_aqc_configure_partition_bw_data *bw_data,
4988 struct i40e_asq_cmd_details *cmd_details)
4990 enum i40e_status_code status;
4991 struct i40e_aq_desc desc;
4992 u16 bwd_size = sizeof(*bw_data);
4994 i40e_fill_default_direct_cmd_desc(&desc,
4995 i40e_aqc_opc_configure_partition_bw);
4997 /* Indirect command */
4998 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4999 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5001 if (bwd_size > I40E_AQ_LARGE_BUF)
5002 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5004 desc.datalen = CPU_TO_LE16(bwd_size);
5006 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
5010 #endif /* PF_DRIVER */
5014 * i40e_aq_send_msg_to_pf
5015 * @hw: pointer to the hardware structure
5016 * @v_opcode: opcodes for VF-PF communication
5017 * @v_retval: return error code
5018 * @msg: pointer to the msg buffer
5019 * @msglen: msg length
5020 * @cmd_details: pointer to command details
5022 * Send message to PF driver using admin queue. By default, this message
5023 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
5024 * completion before returning.
5026 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
5027 enum i40e_virtchnl_ops v_opcode,
5028 enum i40e_status_code v_retval,
5029 u8 *msg, u16 msglen,
5030 struct i40e_asq_cmd_details *cmd_details)
5032 struct i40e_aq_desc desc;
5033 struct i40e_asq_cmd_details details;
5034 enum i40e_status_code status;
5036 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
5037 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
5038 desc.cookie_high = CPU_TO_LE32(v_opcode);
5039 desc.cookie_low = CPU_TO_LE32(v_retval);
5041 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
5042 | I40E_AQ_FLAG_RD));
5043 if (msglen > I40E_AQ_LARGE_BUF)
5044 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5045 desc.datalen = CPU_TO_LE16(msglen);
5048 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
5049 details.async = true;
5050 cmd_details = &details;
5052 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
5053 msglen, cmd_details);
5058 * i40e_vf_parse_hw_config
5059 * @hw: pointer to the hardware structure
5060 * @msg: pointer to the virtual channel VF resource structure
5062 * Given a VF resource message from the PF, populate the hw struct
5063 * with appropriate information.
5065 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
5066 struct i40e_virtchnl_vf_resource *msg)
5068 struct i40e_virtchnl_vsi_resource *vsi_res;
5071 vsi_res = &msg->vsi_res[0];
5073 hw->dev_caps.num_vsis = msg->num_vsis;
5074 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
5075 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
5076 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
5077 hw->dev_caps.dcb = msg->vf_offload_flags &
5078 I40E_VIRTCHNL_VF_OFFLOAD_L2;
5079 hw->dev_caps.fcoe = (msg->vf_offload_flags &
5080 I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
5081 hw->dev_caps.iwarp = (msg->vf_offload_flags &
5082 I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
5083 for (i = 0; i < msg->num_vsis; i++) {
5084 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
5085 i40e_memcpy(hw->mac.perm_addr,
5086 vsi_res->default_mac_addr,
5087 I40E_ETH_LENGTH_OF_ADDRESS,
5088 I40E_NONDMA_TO_NONDMA);
5089 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
5090 I40E_ETH_LENGTH_OF_ADDRESS,
5091 I40E_NONDMA_TO_NONDMA);
5099 * @hw: pointer to the hardware structure
5101 * Send a VF_RESET message to the PF. Does not wait for response from PF
5102 * as none will be forthcoming. Immediately after calling this function,
5103 * the admin queue should be shut down and (optionally) reinitialized.
5105 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
5107 return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
5108 I40E_SUCCESS, NULL, 0, NULL);
5110 #endif /* VF_DRIVER */