drivers/net/i40e/base/i40e_common.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "i40e_type.h"
  35 #include "i40e_adminq.h"
  36 #include "i40e_prototype.h"
  37 #include "i40e_virtchnl.h"
  38
  39
  40 /**
  41  * i40e_set_mac_type - Sets MAC type
  42  * @hw: pointer to the HW structure
  43  *
  44  * This function sets the mac type of the adapter based on the
  45  * vendor ID and device ID stored in the hw structure.
  46  **/
  47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  49 #else
  50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  51 #endif
  52 {
  53         enum i40e_status_code status = I40E_SUCCESS;
  54
  55         DEBUGFUNC("i40e_set_mac_type\n");
  56
  57         if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
  58                 switch (hw->device_id) {
  59                 case I40E_DEV_ID_SFP_XL710:
  60                 case I40E_DEV_ID_QEMU:
  61                 case I40E_DEV_ID_KX_B:
  62                 case I40E_DEV_ID_KX_C:
  63                 case I40E_DEV_ID_QSFP_A:
  64                 case I40E_DEV_ID_QSFP_B:
  65                 case I40E_DEV_ID_QSFP_C:
  66                 case I40E_DEV_ID_10G_BASE_T:
  67                 case I40E_DEV_ID_10G_BASE_T4:
  68                 case I40E_DEV_ID_20G_KR2:
  69                 case I40E_DEV_ID_20G_KR2_A:
  70                 case I40E_DEV_ID_25G_B:
  71                 case I40E_DEV_ID_25G_SFP28:
  72                         hw->mac.type = I40E_MAC_XL710;
  73                         break;
  74 #ifdef X722_SUPPORT
  75 #ifdef X722_A0_SUPPORT
  76                 case I40E_DEV_ID_X722_A0:
  77 #endif
  78                 case I40E_DEV_ID_KX_X722:
  79                 case I40E_DEV_ID_QSFP_X722:
  80                 case I40E_DEV_ID_SFP_X722:
  81                 case I40E_DEV_ID_1G_BASE_T_X722:
  82                 case I40E_DEV_ID_10G_BASE_T_X722:
  83                 case I40E_DEV_ID_SFP_I_X722:
  84                         hw->mac.type = I40E_MAC_X722;
  85                         break;
  86 #endif
  87 #ifdef X722_SUPPORT
  88 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  89                 case I40E_DEV_ID_X722_VF:
  90 #ifdef X722_A0_SUPPORT
  91                 case I40E_DEV_ID_X722_A0_VF:
  92 #endif
  93                         hw->mac.type = I40E_MAC_X722_VF;
  94                         break;
  95 #endif /* INTEGRATED_VF || VF_DRIVER */
  96 #endif /* X722_SUPPORT */
  97 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  98                 case I40E_DEV_ID_VF:
  99                 case I40E_DEV_ID_VF_HV:
 100                         hw->mac.type = I40E_MAC_VF;
 101                         break;
 102 #endif
 103                 default:
 104                         hw->mac.type = I40E_MAC_GENERIC;
 105                         break;
 106                 }
 107         } else {
 108                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
 109         }
 110
 111         DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
 112                   hw->mac.type, status);
 113         return status;
 114 }
 115
 116 #ifndef I40E_NDIS_SUPPORT
 117 /**
 118  * i40e_aq_str - convert AQ err code to a string
 119  * @hw: pointer to the HW structure
 120  * @aq_err: the AQ error code to convert
 121  **/
 122 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
 123 {
 124         switch (aq_err) {
 125         case I40E_AQ_RC_OK:
 126                 return "OK";
 127         case I40E_AQ_RC_EPERM:
 128                 return "I40E_AQ_RC_EPERM";
 129         case I40E_AQ_RC_ENOENT:
 130                 return "I40E_AQ_RC_ENOENT";
 131         case I40E_AQ_RC_ESRCH:
 132                 return "I40E_AQ_RC_ESRCH";
 133         case I40E_AQ_RC_EINTR:
 134                 return "I40E_AQ_RC_EINTR";
 135         case I40E_AQ_RC_EIO:
 136                 return "I40E_AQ_RC_EIO";
 137         case I40E_AQ_RC_ENXIO:
 138                 return "I40E_AQ_RC_ENXIO";
 139         case I40E_AQ_RC_E2BIG:
 140                 return "I40E_AQ_RC_E2BIG";
 141         case I40E_AQ_RC_EAGAIN:
 142                 return "I40E_AQ_RC_EAGAIN";
 143         case I40E_AQ_RC_ENOMEM:
 144                 return "I40E_AQ_RC_ENOMEM";
 145         case I40E_AQ_RC_EACCES:
 146                 return "I40E_AQ_RC_EACCES";
 147         case I40E_AQ_RC_EFAULT:
 148                 return "I40E_AQ_RC_EFAULT";
 149         case I40E_AQ_RC_EBUSY:
 150                 return "I40E_AQ_RC_EBUSY";
 151         case I40E_AQ_RC_EEXIST:
 152                 return "I40E_AQ_RC_EEXIST";
 153         case I40E_AQ_RC_EINVAL:
 154                 return "I40E_AQ_RC_EINVAL";
 155         case I40E_AQ_RC_ENOTTY:
 156                 return "I40E_AQ_RC_ENOTTY";
 157         case I40E_AQ_RC_ENOSPC:
 158                 return "I40E_AQ_RC_ENOSPC";
 159         case I40E_AQ_RC_ENOSYS:
 160                 return "I40E_AQ_RC_ENOSYS";
 161         case I40E_AQ_RC_ERANGE:
 162                 return "I40E_AQ_RC_ERANGE";
 163         case I40E_AQ_RC_EFLUSHED:
 164                 return "I40E_AQ_RC_EFLUSHED";
 165         case I40E_AQ_RC_BAD_ADDR:
 166                 return "I40E_AQ_RC_BAD_ADDR";
 167         case I40E_AQ_RC_EMODE:
 168                 return "I40E_AQ_RC_EMODE";
 169         case I40E_AQ_RC_EFBIG:
 170                 return "I40E_AQ_RC_EFBIG";
 171         }
 172
 173         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 174         return hw->err_str;
 175 }
 176
 177 /**
 178  * i40e_stat_str - convert status err code to a string
 179  * @hw: pointer to the HW structure
 180  * @stat_err: the status error code to convert
 181  **/
 182 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
 183 {
 184         switch (stat_err) {
 185         case I40E_SUCCESS:
 186                 return "OK";
 187         case I40E_ERR_NVM:
 188                 return "I40E_ERR_NVM";
 189         case I40E_ERR_NVM_CHECKSUM:
 190                 return "I40E_ERR_NVM_CHECKSUM";
 191         case I40E_ERR_PHY:
 192                 return "I40E_ERR_PHY";
 193         case I40E_ERR_CONFIG:
 194                 return "I40E_ERR_CONFIG";
 195         case I40E_ERR_PARAM:
 196                 return "I40E_ERR_PARAM";
 197         case I40E_ERR_MAC_TYPE:
 198                 return "I40E_ERR_MAC_TYPE";
 199         case I40E_ERR_UNKNOWN_PHY:
 200                 return "I40E_ERR_UNKNOWN_PHY";
 201         case I40E_ERR_LINK_SETUP:
 202                 return "I40E_ERR_LINK_SETUP";
 203         case I40E_ERR_ADAPTER_STOPPED:
 204                 return "I40E_ERR_ADAPTER_STOPPED";
 205         case I40E_ERR_INVALID_MAC_ADDR:
 206                 return "I40E_ERR_INVALID_MAC_ADDR";
 207         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 208                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 209         case I40E_ERR_MASTER_REQUESTS_PENDING:
 210                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 211         case I40E_ERR_INVALID_LINK_SETTINGS:
 212                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 213         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 214                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 215         case I40E_ERR_RESET_FAILED:
 216                 return "I40E_ERR_RESET_FAILED";
 217         case I40E_ERR_SWFW_SYNC:
 218                 return "I40E_ERR_SWFW_SYNC";
 219         case I40E_ERR_NO_AVAILABLE_VSI:
 220                 return "I40E_ERR_NO_AVAILABLE_VSI";
 221         case I40E_ERR_NO_MEMORY:
 222                 return "I40E_ERR_NO_MEMORY";
 223         case I40E_ERR_BAD_PTR:
 224                 return "I40E_ERR_BAD_PTR";
 225         case I40E_ERR_RING_FULL:
 226                 return "I40E_ERR_RING_FULL";
 227         case I40E_ERR_INVALID_PD_ID:
 228                 return "I40E_ERR_INVALID_PD_ID";
 229         case I40E_ERR_INVALID_QP_ID:
 230                 return "I40E_ERR_INVALID_QP_ID";
 231         case I40E_ERR_INVALID_CQ_ID:
 232                 return "I40E_ERR_INVALID_CQ_ID";
 233         case I40E_ERR_INVALID_CEQ_ID:
 234                 return "I40E_ERR_INVALID_CEQ_ID";
 235         case I40E_ERR_INVALID_AEQ_ID:
 236                 return "I40E_ERR_INVALID_AEQ_ID";
 237         case I40E_ERR_INVALID_SIZE:
 238                 return "I40E_ERR_INVALID_SIZE";
 239         case I40E_ERR_INVALID_ARP_INDEX:
 240                 return "I40E_ERR_INVALID_ARP_INDEX";
 241         case I40E_ERR_INVALID_FPM_FUNC_ID:
 242                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 243         case I40E_ERR_QP_INVALID_MSG_SIZE:
 244                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 245         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 246                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 247         case I40E_ERR_INVALID_FRAG_COUNT:
 248                 return "I40E_ERR_INVALID_FRAG_COUNT";
 249         case I40E_ERR_QUEUE_EMPTY:
 250                 return "I40E_ERR_QUEUE_EMPTY";
 251         case I40E_ERR_INVALID_ALIGNMENT:
 252                 return "I40E_ERR_INVALID_ALIGNMENT";
 253         case I40E_ERR_FLUSHED_QUEUE:
 254                 return "I40E_ERR_FLUSHED_QUEUE";
 255         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 256                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 257         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 258                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 259         case I40E_ERR_TIMEOUT:
 260                 return "I40E_ERR_TIMEOUT";
 261         case I40E_ERR_OPCODE_MISMATCH:
 262                 return "I40E_ERR_OPCODE_MISMATCH";
 263         case I40E_ERR_CQP_COMPL_ERROR:
 264                 return "I40E_ERR_CQP_COMPL_ERROR";
 265         case I40E_ERR_INVALID_VF_ID:
 266                 return "I40E_ERR_INVALID_VF_ID";
 267         case I40E_ERR_INVALID_HMCFN_ID:
 268                 return "I40E_ERR_INVALID_HMCFN_ID";
 269         case I40E_ERR_BACKING_PAGE_ERROR:
 270                 return "I40E_ERR_BACKING_PAGE_ERROR";
 271         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 272                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 273         case I40E_ERR_INVALID_PBLE_INDEX:
 274                 return "I40E_ERR_INVALID_PBLE_INDEX";
 275         case I40E_ERR_INVALID_SD_INDEX:
 276                 return "I40E_ERR_INVALID_SD_INDEX";
 277         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 278                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 279         case I40E_ERR_INVALID_SD_TYPE:
 280                 return "I40E_ERR_INVALID_SD_TYPE";
 281         case I40E_ERR_MEMCPY_FAILED:
 282                 return "I40E_ERR_MEMCPY_FAILED";
 283         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 284                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 285         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 286                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 287         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 288                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 289         case I40E_ERR_SRQ_ENABLED:
 290                 return "I40E_ERR_SRQ_ENABLED";
 291         case I40E_ERR_ADMIN_QUEUE_ERROR:
 292                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 293         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 294                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 295         case I40E_ERR_BUF_TOO_SHORT:
 296                 return "I40E_ERR_BUF_TOO_SHORT";
 297         case I40E_ERR_ADMIN_QUEUE_FULL:
 298                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 299         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 300                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 301         case I40E_ERR_BAD_IWARP_CQE:
 302                 return "I40E_ERR_BAD_IWARP_CQE";
 303         case I40E_ERR_NVM_BLANK_MODE:
 304                 return "I40E_ERR_NVM_BLANK_MODE";
 305         case I40E_ERR_NOT_IMPLEMENTED:
 306                 return "I40E_ERR_NOT_IMPLEMENTED";
 307         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 308                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 309         case I40E_ERR_DIAG_TEST_FAILED:
 310                 return "I40E_ERR_DIAG_TEST_FAILED";
 311         case I40E_ERR_NOT_READY:
 312                 return "I40E_ERR_NOT_READY";
 313         case I40E_NOT_SUPPORTED:
 314                 return "I40E_NOT_SUPPORTED";
 315         case I40E_ERR_FIRMWARE_API_VERSION:
 316                 return "I40E_ERR_FIRMWARE_API_VERSION";
 317         }
 318
 319         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 320         return hw->err_str;
 321 }
 322
 323 #endif /* I40E_NDIS_SUPPORT */
 324 /**
 325  * i40e_debug_aq
 326  * @hw: debug mask related to admin queue
 327  * @mask: debug mask
 328  * @desc: pointer to admin queue descriptor
 329  * @buffer: pointer to command buffer
 330  * @buf_len: max length of buffer
 331  *
 332  * Dumps debug log about adminq command with descriptor contents.
 333  **/
 334 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 335                    void *buffer, u16 buf_len)
 336 {
 337         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 338         u16 len = LE16_TO_CPU(aq_desc->datalen);
 339         u8 *buf = (u8 *)buffer;
 340         u16 i = 0;
 341
 342         if ((!(mask & hw->debug_mask)) || (desc == NULL))
 343                 return;
 344
 345         i40e_debug(hw, mask,
 346                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 347                    LE16_TO_CPU(aq_desc->opcode),
 348                    LE16_TO_CPU(aq_desc->flags),
 349                    LE16_TO_CPU(aq_desc->datalen),
 350                    LE16_TO_CPU(aq_desc->retval));
 351         i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
 352                    LE32_TO_CPU(aq_desc->cookie_high),
 353                    LE32_TO_CPU(aq_desc->cookie_low));
 354         i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
 355                    LE32_TO_CPU(aq_desc->params.internal.param0),
 356                    LE32_TO_CPU(aq_desc->params.internal.param1));
 357         i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
 358                    LE32_TO_CPU(aq_desc->params.external.addr_high),
 359                    LE32_TO_CPU(aq_desc->params.external.addr_low));
 360
 361         if ((buffer != NULL) && (aq_desc->datalen != 0)) {
 362                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 363                 if (buf_len < len)
 364                         len = buf_len;
 365                 /* write the full 16-byte chunks */
 366                 for (i = 0; i < (len - 16); i += 16)
 367                         i40e_debug(hw, mask,
 368                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 369                                    i, buf[i], buf[i+1], buf[i+2], buf[i+3],
 370                                    buf[i+4], buf[i+5], buf[i+6], buf[i+7],
 371                                    buf[i+8], buf[i+9], buf[i+10], buf[i+11],
 372                                    buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
 373                 /* the most we could have left is 16 bytes, pad with zeros */
 374                 if (i < len) {
 375                         char d_buf[16];
 376                         int j, i_sav;
 377
 378                         i_sav = i;
 379                         memset(d_buf, 0, sizeof(d_buf));
 380                         for (j = 0; i < len; j++, i++)
 381                                 d_buf[j] = buf[i];
 382                         i40e_debug(hw, mask,
 383                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 384                                    i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
 385                                    d_buf[4], d_buf[5], d_buf[6], d_buf[7],
 386                                    d_buf[8], d_buf[9], d_buf[10], d_buf[11],
 387                                    d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
 388                 }
 389         }
 390 }
 391
 392 /**
 393  * i40e_check_asq_alive
 394  * @hw: pointer to the hw struct
 395  *
 396  * Returns true if Queue is enabled else false.
 397  **/
 398 bool i40e_check_asq_alive(struct i40e_hw *hw)
 399 {
 400         if (hw->aq.asq.len)
 401 #ifdef PF_DRIVER
 402 #ifdef INTEGRATED_VF
 403                 if (!i40e_is_vf(hw))
 404                         return !!(rd32(hw, hw->aq.asq.len) &
 405                                 I40E_PF_ATQLEN_ATQENABLE_MASK);
 406 #else
 407                 return !!(rd32(hw, hw->aq.asq.len) &
 408                         I40E_PF_ATQLEN_ATQENABLE_MASK);
 409 #endif /* INTEGRATED_VF */
 410 #endif /* PF_DRIVER */
 411 #ifdef VF_DRIVER
 412 #ifdef INTEGRATED_VF
 413                 if (i40e_is_vf(hw))
 414                         return !!(rd32(hw, hw->aq.asq.len) &
 415                                 I40E_VF_ATQLEN1_ATQENABLE_MASK);
 416 #else
 417                 return !!(rd32(hw, hw->aq.asq.len) &
 418                         I40E_VF_ATQLEN1_ATQENABLE_MASK);
 419 #endif /* INTEGRATED_VF */
 420 #endif /* VF_DRIVER */
 421         return false;
 422 }
 423
 424 /**
 425  * i40e_aq_queue_shutdown
 426  * @hw: pointer to the hw struct
 427  * @unloading: is the driver unloading itself
 428  *
 429  * Tell the Firmware that we're shutting down the AdminQ and whether
 430  * or not the driver is unloading as well.
 431  **/
 432 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
 433                                              bool unloading)
 434 {
 435         struct i40e_aq_desc desc;
 436         struct i40e_aqc_queue_shutdown *cmd =
 437                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 438         enum i40e_status_code status;
 439
 440         i40e_fill_default_direct_cmd_desc(&desc,
 441                                           i40e_aqc_opc_queue_shutdown);
 442
 443         if (unloading)
 444                 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
 445         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 446
 447         return status;
 448 }
 449 #ifdef X722_SUPPORT
 450
 451 /**
 452  * i40e_aq_get_set_rss_lut
 453  * @hw: pointer to the hardware structure
 454  * @vsi_id: vsi fw index
 455  * @pf_lut: for PF table set true, for VSI table set false
 456  * @lut: pointer to the lut buffer provided by the caller
 457  * @lut_size: size of the lut buffer
 458  * @set: set true to set the table, false to get the table
 459  *
 460  * Internal function to get or set RSS look up table
 461  **/
 462 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 463                                                      u16 vsi_id, bool pf_lut,
 464                                                      u8 *lut, u16 lut_size,
 465                                                      bool set)
 466 {
 467         enum i40e_status_code status;
 468         struct i40e_aq_desc desc;
 469         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 470                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 471
 472         if (set)
 473                 i40e_fill_default_direct_cmd_desc(&desc,
 474                                                   i40e_aqc_opc_set_rss_lut);
 475         else
 476                 i40e_fill_default_direct_cmd_desc(&desc,
 477                                                   i40e_aqc_opc_get_rss_lut);
 478
 479         /* Indirect command */
 480         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 481         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 482
 483         cmd_resp->vsi_id =
 484                         CPU_TO_LE16((u16)((vsi_id <<
 485                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 486                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 487         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 488
 489         if (pf_lut)
 490                 cmd_resp->flags |= CPU_TO_LE16((u16)
 491                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 492                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 493                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 494         else
 495                 cmd_resp->flags |= CPU_TO_LE16((u16)
 496                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 497                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 498                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 499
 500         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 501
 502         return status;
 503 }
 504
 505 /**
 506  * i40e_aq_get_rss_lut
 507  * @hw: pointer to the hardware structure
 508  * @vsi_id: vsi fw index
 509  * @pf_lut: for PF table set true, for VSI table set false
 510  * @lut: pointer to the lut buffer provided by the caller
 511  * @lut_size: size of the lut buffer
 512  *
 513  * get the RSS lookup table, PF or VSI type
 514  **/
 515 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 516                                           bool pf_lut, u8 *lut, u16 lut_size)
 517 {
 518         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 519                                        false);
 520 }
 521
 522 /**
 523  * i40e_aq_set_rss_lut
 524  * @hw: pointer to the hardware structure
 525  * @vsi_id: vsi fw index
 526  * @pf_lut: for PF table set true, for VSI table set false
 527  * @lut: pointer to the lut buffer provided by the caller
 528  * @lut_size: size of the lut buffer
 529  *
 530  * set the RSS lookup table, PF or VSI type
 531  **/
 532 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 533                                           bool pf_lut, u8 *lut, u16 lut_size)
 534 {
 535         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
 536 }
 537
 538 /**
 539  * i40e_aq_get_set_rss_key
 540  * @hw: pointer to the hw struct
 541  * @vsi_id: vsi fw index
 542  * @key: pointer to key info struct
 543  * @set: set true to set the key, false to get the key
 544  *
 545  * get the RSS key per VSI
 546  **/
 547 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 548                                       u16 vsi_id,
 549                                       struct i40e_aqc_get_set_rss_key_data *key,
 550                                       bool set)
 551 {
 552         enum i40e_status_code status;
 553         struct i40e_aq_desc desc;
 554         struct i40e_aqc_get_set_rss_key *cmd_resp =
 555                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 556         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 557
 558         if (set)
 559                 i40e_fill_default_direct_cmd_desc(&desc,
 560                                                   i40e_aqc_opc_set_rss_key);
 561         else
 562                 i40e_fill_default_direct_cmd_desc(&desc,
 563                                                   i40e_aqc_opc_get_rss_key);
 564
 565         /* Indirect command */
 566         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 567         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 568
 569         cmd_resp->vsi_id =
 570                         CPU_TO_LE16((u16)((vsi_id <<
 571                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 572                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 573         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 574
 575         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 576
 577         return status;
 578 }
 579
 580 /**
 581  * i40e_aq_get_rss_key
 582  * @hw: pointer to the hw struct
 583  * @vsi_id: vsi fw index
 584  * @key: pointer to key info struct
 585  *
 586  **/
 587 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
 588                                       u16 vsi_id,
 589                                       struct i40e_aqc_get_set_rss_key_data *key)
 590 {
 591         return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
 592 }
 593
 594 /**
 595  * i40e_aq_set_rss_key
 596  * @hw: pointer to the hw struct
 597  * @vsi_id: vsi fw index
 598  * @key: pointer to key info struct
 599  *
 600  * set the RSS key per VSI
 601  **/
 602 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
 603                                       u16 vsi_id,
 604                                       struct i40e_aqc_get_set_rss_key_data *key)
 605 {
 606         return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
 607 }
 608 #endif /* X722_SUPPORT */
 609
 610 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 611  * hardware to a bit-field that can be used by SW to more easily determine the
 612  * packet type.
 613  *
 614  * Macros are used to shorten the table lines and make this table human
 615  * readable.
 616  *
 617  * We store the PTYPE in the top byte of the bit field - this is just so that
 618  * we can check that the table doesn't have a row missing, as the index into
 619  * the table should be the PTYPE.
 620  *
 621  * Typical work flow:
 622  *
 623  * IF NOT i40e_ptype_lookup[ptype].known
 624  * THEN
 625  *      Packet is unknown
 626  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 627  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 628  * ELSE
 629  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 630  * ENDIF
 631  */
 632
 633 /* macro to make the table lines short */
 634 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 635         {       PTYPE, \
 636                 1, \
 637                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 638                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 639                 I40E_RX_PTYPE_##OUTER_FRAG, \
 640                 I40E_RX_PTYPE_TUNNEL_##T, \
 641                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 642                 I40E_RX_PTYPE_##TEF, \
 643                 I40E_RX_PTYPE_INNER_PROT_##I, \
 644                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 645
 646 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 647                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 648
 649 /* shorter macros makes the table fit but are terse */
 650 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 651 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 652 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 653
 654 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 655 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 656         /* L2 Packet types */
 657         I40E_PTT_UNUSED_ENTRY(0),
 658         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 659         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 660         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 661         I40E_PTT_UNUSED_ENTRY(4),
 662         I40E_PTT_UNUSED_ENTRY(5),
 663         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 664         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 665         I40E_PTT_UNUSED_ENTRY(8),
 666         I40E_PTT_UNUSED_ENTRY(9),
 667         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 668         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 669         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 670         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 671         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 672         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 673         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 674         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 675         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 676         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 677         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 678         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 679
 680         /* Non Tunneled IPv4 */
 681         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 682         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 683         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 684         I40E_PTT_UNUSED_ENTRY(25),
 685         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 686         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 687         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 688
 689         /* IPv4 --> IPv4 */
 690         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 691         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 692         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 693         I40E_PTT_UNUSED_ENTRY(32),
 694         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 695         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 696         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 697
 698         /* IPv4 --> IPv6 */
 699         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 700         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 701         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 702         I40E_PTT_UNUSED_ENTRY(39),
 703         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 704         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 705         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 706
 707         /* IPv4 --> GRE/NAT */
 708         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 709
 710         /* IPv4 --> GRE/NAT --> IPv4 */
 711         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 712         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 713         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 714         I40E_PTT_UNUSED_ENTRY(47),
 715         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 716         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 717         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 718
 719         /* IPv4 --> GRE/NAT --> IPv6 */
 720         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 721         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 722         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 723         I40E_PTT_UNUSED_ENTRY(54),
 724         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 725         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 726         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 727
 728         /* IPv4 --> GRE/NAT --> MAC */
 729         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 730
 731         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 732         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 733         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 734         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 735         I40E_PTT_UNUSED_ENTRY(62),
 736         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 737         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 738         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 739
 740         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 741         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 742         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 743         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 744         I40E_PTT_UNUSED_ENTRY(69),
 745         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 746         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 747         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 748
 749         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 750         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 751
 752         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 753         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 754         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 755         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 756         I40E_PTT_UNUSED_ENTRY(77),
 757         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 758         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 759         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 760
 761         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 762         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 763         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 764         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 765         I40E_PTT_UNUSED_ENTRY(84),
 766         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 767         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 768         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 769
 770         /* Non Tunneled IPv6 */
 771         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 772         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 773         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
 774         I40E_PTT_UNUSED_ENTRY(91),
 775         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 776         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 777         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 778
 779         /* IPv6 --> IPv4 */
 780         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 781         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 782         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 783         I40E_PTT_UNUSED_ENTRY(98),
 784         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 785         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 786         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 787
 788         /* IPv6 --> IPv6 */
 789         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 790         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 791         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 792         I40E_PTT_UNUSED_ENTRY(105),
 793         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 794         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 795         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 796
 797         /* IPv6 --> GRE/NAT */
 798         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 799
 800         /* IPv6 --> GRE/NAT -> IPv4 */
 801         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 802         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 803         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 804         I40E_PTT_UNUSED_ENTRY(113),
 805         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 806         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 807         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 808
 809         /* IPv6 --> GRE/NAT -> IPv6 */
 810         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 811         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 812         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 813         I40E_PTT_UNUSED_ENTRY(120),
 814         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 815         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 816         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 817
 818         /* IPv6 --> GRE/NAT -> MAC */
 819         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 820
 821         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 822         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 823         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 824         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 825         I40E_PTT_UNUSED_ENTRY(128),
 826         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 827         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 828         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 829
 830         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 831         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 832         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 833         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 834         I40E_PTT_UNUSED_ENTRY(135),
 835         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 836         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 837         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 838
 839         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 840         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 841
 842         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 843         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 844         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 845         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 846         I40E_PTT_UNUSED_ENTRY(143),
 847         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 848         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 849         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 850
 851         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 852         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 853         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 854         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 855         I40E_PTT_UNUSED_ENTRY(150),
 856         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 857         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 858         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 859
 860         /* unused entries */
 861         I40E_PTT_UNUSED_ENTRY(154),
 862         I40E_PTT_UNUSED_ENTRY(155),
 863         I40E_PTT_UNUSED_ENTRY(156),
 864         I40E_PTT_UNUSED_ENTRY(157),
 865         I40E_PTT_UNUSED_ENTRY(158),
 866         I40E_PTT_UNUSED_ENTRY(159),
 867
 868         I40E_PTT_UNUSED_ENTRY(160),
 869         I40E_PTT_UNUSED_ENTRY(161),
 870         I40E_PTT_UNUSED_ENTRY(162),
 871         I40E_PTT_UNUSED_ENTRY(163),
 872         I40E_PTT_UNUSED_ENTRY(164),
 873         I40E_PTT_UNUSED_ENTRY(165),
 874         I40E_PTT_UNUSED_ENTRY(166),
 875         I40E_PTT_UNUSED_ENTRY(167),
 876         I40E_PTT_UNUSED_ENTRY(168),
 877         I40E_PTT_UNUSED_ENTRY(169),
 878
 879         I40E_PTT_UNUSED_ENTRY(170),
 880         I40E_PTT_UNUSED_ENTRY(171),
 881         I40E_PTT_UNUSED_ENTRY(172),
 882         I40E_PTT_UNUSED_ENTRY(173),
 883         I40E_PTT_UNUSED_ENTRY(174),
 884         I40E_PTT_UNUSED_ENTRY(175),
 885         I40E_PTT_UNUSED_ENTRY(176),
 886         I40E_PTT_UNUSED_ENTRY(177),
 887         I40E_PTT_UNUSED_ENTRY(178),
 888         I40E_PTT_UNUSED_ENTRY(179),
 889
 890         I40E_PTT_UNUSED_ENTRY(180),
 891         I40E_PTT_UNUSED_ENTRY(181),
 892         I40E_PTT_UNUSED_ENTRY(182),
 893         I40E_PTT_UNUSED_ENTRY(183),
 894         I40E_PTT_UNUSED_ENTRY(184),
 895         I40E_PTT_UNUSED_ENTRY(185),
 896         I40E_PTT_UNUSED_ENTRY(186),
 897         I40E_PTT_UNUSED_ENTRY(187),
 898         I40E_PTT_UNUSED_ENTRY(188),
 899         I40E_PTT_UNUSED_ENTRY(189),
 900
 901         I40E_PTT_UNUSED_ENTRY(190),
 902         I40E_PTT_UNUSED_ENTRY(191),
 903         I40E_PTT_UNUSED_ENTRY(192),
 904         I40E_PTT_UNUSED_ENTRY(193),
 905         I40E_PTT_UNUSED_ENTRY(194),
 906         I40E_PTT_UNUSED_ENTRY(195),
 907         I40E_PTT_UNUSED_ENTRY(196),
 908         I40E_PTT_UNUSED_ENTRY(197),
 909         I40E_PTT_UNUSED_ENTRY(198),
 910         I40E_PTT_UNUSED_ENTRY(199),
 911
 912         I40E_PTT_UNUSED_ENTRY(200),
 913         I40E_PTT_UNUSED_ENTRY(201),
 914         I40E_PTT_UNUSED_ENTRY(202),
 915         I40E_PTT_UNUSED_ENTRY(203),
 916         I40E_PTT_UNUSED_ENTRY(204),
 917         I40E_PTT_UNUSED_ENTRY(205),
 918         I40E_PTT_UNUSED_ENTRY(206),
 919         I40E_PTT_UNUSED_ENTRY(207),
 920         I40E_PTT_UNUSED_ENTRY(208),
 921         I40E_PTT_UNUSED_ENTRY(209),
 922
 923         I40E_PTT_UNUSED_ENTRY(210),
 924         I40E_PTT_UNUSED_ENTRY(211),
 925         I40E_PTT_UNUSED_ENTRY(212),
 926         I40E_PTT_UNUSED_ENTRY(213),
 927         I40E_PTT_UNUSED_ENTRY(214),
 928         I40E_PTT_UNUSED_ENTRY(215),
 929         I40E_PTT_UNUSED_ENTRY(216),
 930         I40E_PTT_UNUSED_ENTRY(217),
 931         I40E_PTT_UNUSED_ENTRY(218),
 932         I40E_PTT_UNUSED_ENTRY(219),
 933
 934         I40E_PTT_UNUSED_ENTRY(220),
 935         I40E_PTT_UNUSED_ENTRY(221),
 936         I40E_PTT_UNUSED_ENTRY(222),
 937         I40E_PTT_UNUSED_ENTRY(223),
 938         I40E_PTT_UNUSED_ENTRY(224),
 939         I40E_PTT_UNUSED_ENTRY(225),
 940         I40E_PTT_UNUSED_ENTRY(226),
 941         I40E_PTT_UNUSED_ENTRY(227),
 942         I40E_PTT_UNUSED_ENTRY(228),
 943         I40E_PTT_UNUSED_ENTRY(229),
 944
 945         I40E_PTT_UNUSED_ENTRY(230),
 946         I40E_PTT_UNUSED_ENTRY(231),
 947         I40E_PTT_UNUSED_ENTRY(232),
 948         I40E_PTT_UNUSED_ENTRY(233),
 949         I40E_PTT_UNUSED_ENTRY(234),
 950         I40E_PTT_UNUSED_ENTRY(235),
 951         I40E_PTT_UNUSED_ENTRY(236),
 952         I40E_PTT_UNUSED_ENTRY(237),
 953         I40E_PTT_UNUSED_ENTRY(238),
 954         I40E_PTT_UNUSED_ENTRY(239),
 955
 956         I40E_PTT_UNUSED_ENTRY(240),
 957         I40E_PTT_UNUSED_ENTRY(241),
 958         I40E_PTT_UNUSED_ENTRY(242),
 959         I40E_PTT_UNUSED_ENTRY(243),
 960         I40E_PTT_UNUSED_ENTRY(244),
 961         I40E_PTT_UNUSED_ENTRY(245),
 962         I40E_PTT_UNUSED_ENTRY(246),
 963         I40E_PTT_UNUSED_ENTRY(247),
 964         I40E_PTT_UNUSED_ENTRY(248),
 965         I40E_PTT_UNUSED_ENTRY(249),
 966
 967         I40E_PTT_UNUSED_ENTRY(250),
 968         I40E_PTT_UNUSED_ENTRY(251),
 969         I40E_PTT_UNUSED_ENTRY(252),
 970         I40E_PTT_UNUSED_ENTRY(253),
 971         I40E_PTT_UNUSED_ENTRY(254),
 972         I40E_PTT_UNUSED_ENTRY(255)
 973 };
 974
 975
 976 /**
 977  * i40e_validate_mac_addr - Validate unicast MAC address
 978  * @mac_addr: pointer to MAC address
 979  *
 980  * Tests a MAC address to ensure it is a valid Individual Address
 981  **/
 982 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
 983 {
 984         enum i40e_status_code status = I40E_SUCCESS;
 985
 986         DEBUGFUNC("i40e_validate_mac_addr");
 987
 988         /* Broadcast addresses ARE multicast addresses
 989          * Make sure it is not a multicast address
 990          * Reject the zero address
 991          */
 992         if (I40E_IS_MULTICAST(mac_addr) ||
 993             (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
 994               mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
 995                 status = I40E_ERR_INVALID_MAC_ADDR;
 996
 997         return status;
 998 }
 999 #ifdef PF_DRIVER
1000
1001 /**
1002  * i40e_init_shared_code - Initialize the shared code
1003  * @hw: pointer to hardware structure
1004  *
1005  * This assigns the MAC type and PHY code and inits the NVM.
1006  * Does not touch the hardware. This function must be called prior to any
1007  * other function in the shared code. The i40e_hw structure should be
1008  * memset to 0 prior to calling this function.  The following fields in
1009  * hw structure should be filled in prior to calling this function:
1010  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1011  * subsystem_vendor_id, and revision_id
1012  **/
1013 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
1014 {
1015         enum i40e_status_code status = I40E_SUCCESS;
1016         u32 port, ari, func_rid;
1017
1018         DEBUGFUNC("i40e_init_shared_code");
1019
1020         i40e_set_mac_type(hw);
1021
1022         switch (hw->mac.type) {
1023         case I40E_MAC_XL710:
1024 #ifdef X722_SUPPORT
1025         case I40E_MAC_X722:
1026 #endif
1027                 break;
1028         default:
1029                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1030         }
1031
1032         hw->phy.get_link_info = true;
1033
1034         /* Determine port number and PF number*/
1035         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1036                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1037         hw->port = (u8)port;
1038         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1039                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1040         func_rid = rd32(hw, I40E_PF_FUNC_RID);
1041         if (ari)
1042                 hw->pf_id = (u8)(func_rid & 0xff);
1043         else
1044                 hw->pf_id = (u8)(func_rid & 0x7);
1045
1046 #ifdef X722_SUPPORT
1047         if (hw->mac.type == I40E_MAC_X722)
1048                 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
1049
1050 #endif
1051         status = i40e_init_nvm(hw);
1052         return status;
1053 }
1054
1055 /**
1056  * i40e_aq_mac_address_read - Retrieve the MAC addresses
1057  * @hw: pointer to the hw struct
1058  * @flags: a return indicator of what addresses were added to the addr store
1059  * @addrs: the requestor's mac addr store
1060  * @cmd_details: pointer to command details structure or NULL
1061  **/
1062 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1063                                    u16 *flags,
1064                                    struct i40e_aqc_mac_address_read_data *addrs,
1065                                    struct i40e_asq_cmd_details *cmd_details)
1066 {
1067         struct i40e_aq_desc desc;
1068         struct i40e_aqc_mac_address_read *cmd_data =
1069                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1070         enum i40e_status_code status;
1071
1072         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1073         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1074
1075         status = i40e_asq_send_command(hw, &desc, addrs,
1076                                        sizeof(*addrs), cmd_details);
1077         *flags = LE16_TO_CPU(cmd_data->command_flags);
1078
1079         return status;
1080 }
1081
1082 /**
1083  * i40e_aq_mac_address_write - Change the MAC addresses
1084  * @hw: pointer to the hw struct
1085  * @flags: indicates which MAC to be written
1086  * @mac_addr: address to write
1087  * @cmd_details: pointer to command details structure or NULL
1088  **/
1089 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1090                                     u16 flags, u8 *mac_addr,
1091                                     struct i40e_asq_cmd_details *cmd_details)
1092 {
1093         struct i40e_aq_desc desc;
1094         struct i40e_aqc_mac_address_write *cmd_data =
1095                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1096         enum i40e_status_code status;
1097
1098         i40e_fill_default_direct_cmd_desc(&desc,
1099                                           i40e_aqc_opc_mac_address_write);
1100         cmd_data->command_flags = CPU_TO_LE16(flags);
1101         cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1102         cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1103                                         ((u32)mac_addr[3] << 16) |
1104                                         ((u32)mac_addr[4] << 8) |
1105                                         mac_addr[5]);
1106
1107         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1108
1109         return status;
1110 }
1111
1112 /**
1113  * i40e_get_mac_addr - get MAC address
1114  * @hw: pointer to the HW structure
1115  * @mac_addr: pointer to MAC address
1116  *
1117  * Reads the adapter's MAC address from register
1118  **/
1119 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1120 {
1121         struct i40e_aqc_mac_address_read_data addrs;
1122         enum i40e_status_code status;
1123         u16 flags = 0;
1124
1125         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1126
1127         if (flags & I40E_AQC_LAN_ADDR_VALID)
1128                 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1129                         I40E_NONDMA_TO_NONDMA);
1130
1131         return status;
1132 }
1133
1134 /**
1135  * i40e_get_port_mac_addr - get Port MAC address
1136  * @hw: pointer to the HW structure
1137  * @mac_addr: pointer to Port MAC address
1138  *
1139  * Reads the adapter's Port MAC address
1140  **/
1141 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1142 {
1143         struct i40e_aqc_mac_address_read_data addrs;
1144         enum i40e_status_code status;
1145         u16 flags = 0;
1146
1147         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1148         if (status)
1149                 return status;
1150
1151         if (flags & I40E_AQC_PORT_ADDR_VALID)
1152                 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1153                         I40E_NONDMA_TO_NONDMA);
1154         else
1155                 status = I40E_ERR_INVALID_MAC_ADDR;
1156
1157         return status;
1158 }
1159
1160 /**
1161  * i40e_pre_tx_queue_cfg - pre tx queue configure
1162  * @hw: pointer to the HW structure
1163  * @queue: target pf queue index
1164  * @enable: state change request
1165  *
1166  * Handles hw requirement to indicate intention to enable
1167  * or disable target queue.
1168  **/
1169 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1170 {
1171         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1172         u32 reg_block = 0;
1173         u32 reg_val;
1174
1175         if (abs_queue_idx >= 128) {
1176                 reg_block = abs_queue_idx / 128;
1177                 abs_queue_idx %= 128;
1178         }
1179
1180         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1181         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1182         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1183
1184         if (enable)
1185                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1186         else
1187                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1188
1189         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1190 }
1191
1192 /**
1193  * i40e_get_san_mac_addr - get SAN MAC address
1194  * @hw: pointer to the HW structure
1195  * @mac_addr: pointer to SAN MAC address
1196  *
1197  * Reads the adapter's SAN MAC address from NVM
1198  **/
1199 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1200                                             u8 *mac_addr)
1201 {
1202         struct i40e_aqc_mac_address_read_data addrs;
1203         enum i40e_status_code status;
1204         u16 flags = 0;
1205
1206         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1207         if (status)
1208                 return status;
1209
1210         if (flags & I40E_AQC_SAN_ADDR_VALID)
1211                 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac),
1212                         I40E_NONDMA_TO_NONDMA);
1213         else
1214                 status = I40E_ERR_INVALID_MAC_ADDR;
1215
1216         return status;
1217 }
1218
1219 /**
1220  *  i40e_read_pba_string - Reads part number string from EEPROM
1221  *  @hw: pointer to hardware structure
1222  *  @pba_num: stores the part number string from the EEPROM
1223  *  @pba_num_size: part number string buffer length
1224  *
1225  *  Reads the part number string from the EEPROM.
1226  **/
1227 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1228                                             u32 pba_num_size)
1229 {
1230         enum i40e_status_code status = I40E_SUCCESS;
1231         u16 pba_word = 0;
1232         u16 pba_size = 0;
1233         u16 pba_ptr = 0;
1234         u16 i = 0;
1235
1236         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1237         if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1238                 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1239                 return status;
1240         }
1241
1242         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1243         if (status != I40E_SUCCESS) {
1244                 DEBUGOUT("Failed to read PBA Block pointer.\n");
1245                 return status;
1246         }
1247
1248         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1249         if (status != I40E_SUCCESS) {
1250                 DEBUGOUT("Failed to read PBA Block size.\n");
1251                 return status;
1252         }
1253
1254         /* Subtract one to get PBA word count (PBA Size word is included in
1255          * total size)
1256          */
1257         pba_size--;
1258         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1259                 DEBUGOUT("Buffer to small for PBA data.\n");
1260                 return I40E_ERR_PARAM;
1261         }
1262
1263         for (i = 0; i < pba_size; i++) {
1264                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1265                 if (status != I40E_SUCCESS) {
1266                         DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1267                         return status;
1268                 }
1269
1270                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1271                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1272         }
1273         pba_num[(pba_size * 2)] = '\0';
1274
1275         return status;
1276 }
1277
1278 /**
1279  * i40e_get_media_type - Gets media type
1280  * @hw: pointer to the hardware structure
1281  **/
1282 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1283 {
1284         enum i40e_media_type media;
1285
1286         switch (hw->phy.link_info.phy_type) {
1287         case I40E_PHY_TYPE_10GBASE_SR:
1288         case I40E_PHY_TYPE_10GBASE_LR:
1289         case I40E_PHY_TYPE_1000BASE_SX:
1290         case I40E_PHY_TYPE_1000BASE_LX:
1291         case I40E_PHY_TYPE_40GBASE_SR4:
1292         case I40E_PHY_TYPE_40GBASE_LR4:
1293         case I40E_PHY_TYPE_25GBASE_LR:
1294         case I40E_PHY_TYPE_25GBASE_SR:
1295                 media = I40E_MEDIA_TYPE_FIBER;
1296                 break;
1297         case I40E_PHY_TYPE_100BASE_TX:
1298         case I40E_PHY_TYPE_1000BASE_T:
1299         case I40E_PHY_TYPE_10GBASE_T:
1300                 media = I40E_MEDIA_TYPE_BASET;
1301                 break;
1302         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1303         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1304         case I40E_PHY_TYPE_10GBASE_CR1:
1305         case I40E_PHY_TYPE_40GBASE_CR4:
1306         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1307         case I40E_PHY_TYPE_40GBASE_AOC:
1308         case I40E_PHY_TYPE_10GBASE_AOC:
1309         case I40E_PHY_TYPE_25GBASE_CR:
1310                 media = I40E_MEDIA_TYPE_DA;
1311                 break;
1312         case I40E_PHY_TYPE_1000BASE_KX:
1313         case I40E_PHY_TYPE_10GBASE_KX4:
1314         case I40E_PHY_TYPE_10GBASE_KR:
1315         case I40E_PHY_TYPE_40GBASE_KR4:
1316         case I40E_PHY_TYPE_20GBASE_KR2:
1317         case I40E_PHY_TYPE_25GBASE_KR:
1318                 media = I40E_MEDIA_TYPE_BACKPLANE;
1319                 break;
1320         case I40E_PHY_TYPE_SGMII:
1321         case I40E_PHY_TYPE_XAUI:
1322         case I40E_PHY_TYPE_XFI:
1323         case I40E_PHY_TYPE_XLAUI:
1324         case I40E_PHY_TYPE_XLPPI:
1325         default:
1326                 media = I40E_MEDIA_TYPE_UNKNOWN;
1327                 break;
1328         }
1329
1330         return media;
1331 }
1332
1333 #define I40E_PF_RESET_WAIT_COUNT        200
1334 /**
1335  * i40e_pf_reset - Reset the PF
1336  * @hw: pointer to the hardware structure
1337  *
1338  * Assuming someone else has triggered a global reset,
1339  * assure the global reset is complete and then reset the PF
1340  **/
1341 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1342 {
1343         u32 cnt = 0;
1344         u32 cnt1 = 0;
1345         u32 reg = 0;
1346         u32 grst_del;
1347
1348         /* Poll for Global Reset steady state in case of recent GRST.
1349          * The grst delay value is in 100ms units, and we'll wait a
1350          * couple counts longer to be sure we don't just miss the end.
1351          */
1352         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1353                         I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1354                         I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1355
1356         grst_del = grst_del * 20;
1357
1358         for (cnt = 0; cnt < grst_del; cnt++) {
1359                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1360                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1361                         break;
1362                 i40e_msec_delay(100);
1363         }
1364         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1365                 DEBUGOUT("Global reset polling failed to complete.\n");
1366                 return I40E_ERR_RESET_FAILED;
1367         }
1368
1369         /* Now Wait for the FW to be ready */
1370         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1371                 reg = rd32(hw, I40E_GLNVM_ULD);
1372                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1373                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1374                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1375                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1376                         DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1377                         break;
1378                 }
1379                 i40e_msec_delay(10);
1380         }
1381         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1382                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1383                 DEBUGOUT("wait for FW Reset complete timedout\n");
1384                 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1385                 return I40E_ERR_RESET_FAILED;
1386         }
1387
1388         /* If there was a Global Reset in progress when we got here,
1389          * we don't need to do the PF Reset
1390          */
1391         if (!cnt) {
1392                 reg = rd32(hw, I40E_PFGEN_CTRL);
1393                 wr32(hw, I40E_PFGEN_CTRL,
1394                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1395                 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1396                         reg = rd32(hw, I40E_PFGEN_CTRL);
1397                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1398                                 break;
1399                         i40e_msec_delay(1);
1400                 }
1401                 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1402                         DEBUGOUT("PF reset polling failed to complete.\n");
1403                         return I40E_ERR_RESET_FAILED;
1404                 }
1405         }
1406
1407         i40e_clear_pxe_mode(hw);
1408
1409
1410         return I40E_SUCCESS;
1411 }
1412
1413 /**
1414  * i40e_clear_hw - clear out any left over hw state
1415  * @hw: pointer to the hw struct
1416  *
1417  * Clear queues and interrupts, typically called at init time,
1418  * but after the capabilities have been found so we know how many
1419  * queues and msix vectors have been allocated.
1420  **/
1421 void i40e_clear_hw(struct i40e_hw *hw)
1422 {
1423         u32 num_queues, base_queue;
1424         u32 num_pf_int;
1425         u32 num_vf_int;
1426         u32 num_vfs;
1427         u32 i, j;
1428         u32 val;
1429         u32 eol = 0x7ff;
1430
1431         /* get number of interrupts, queues, and vfs */
1432         val = rd32(hw, I40E_GLPCI_CNF2);
1433         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1434                         I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1435         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1436                         I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1437
1438         val = rd32(hw, I40E_PFLAN_QALLOC);
1439         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1440                         I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1441         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1442                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1443         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1444                 num_queues = (j - base_queue) + 1;
1445         else
1446                 num_queues = 0;
1447
1448         val = rd32(hw, I40E_PF_VT_PFALLOC);
1449         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1450                         I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1451         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1452                         I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1453         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1454                 num_vfs = (j - i) + 1;
1455         else
1456                 num_vfs = 0;
1457
1458         /* stop all the interrupts */
1459         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1460         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1461         for (i = 0; i < num_pf_int - 2; i++)
1462                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1463
1464         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1465         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1466         wr32(hw, I40E_PFINT_LNKLST0, val);
1467         for (i = 0; i < num_pf_int - 2; i++)
1468                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1469         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1470         for (i = 0; i < num_vfs; i++)
1471                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1472         for (i = 0; i < num_vf_int - 2; i++)
1473                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1474
1475         /* warn the HW of the coming Tx disables */
1476         for (i = 0; i < num_queues; i++) {
1477                 u32 abs_queue_idx = base_queue + i;
1478                 u32 reg_block = 0;
1479
1480                 if (abs_queue_idx >= 128) {
1481                         reg_block = abs_queue_idx / 128;
1482                         abs_queue_idx %= 128;
1483                 }
1484
1485                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1486                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1487                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1488                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1489
1490                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1491         }
1492         i40e_usec_delay(400);
1493
1494         /* stop all the queues */
1495         for (i = 0; i < num_queues; i++) {
1496                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1497                 wr32(hw, I40E_QTX_ENA(i), 0);
1498                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1499                 wr32(hw, I40E_QRX_ENA(i), 0);
1500         }
1501
1502         /* short wait for all queue disables to settle */
1503         i40e_usec_delay(50);
1504 }
1505
1506 /**
1507  * i40e_clear_pxe_mode - clear pxe operations mode
1508  * @hw: pointer to the hw struct
1509  *
1510  * Make sure all PXE mode settings are cleared, including things
1511  * like descriptor fetch/write-back mode.
1512  **/
1513 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1514 {
1515         if (i40e_check_asq_alive(hw))
1516                 i40e_aq_clear_pxe_mode(hw, NULL);
1517 }
1518
1519 /**
1520  * i40e_led_is_mine - helper to find matching led
1521  * @hw: pointer to the hw struct
1522  * @idx: index into GPIO registers
1523  *
1524  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1525  */
1526 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1527 {
1528         u32 gpio_val = 0;
1529         u32 port;
1530
1531         if (!hw->func_caps.led[idx])
1532                 return 0;
1533
1534         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1535         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1536                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1537
1538         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1539          * if it is not our port then ignore
1540          */
1541         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1542             (port != hw->port))
1543                 return 0;
1544
1545         return gpio_val;
1546 }
1547
1548 #define I40E_COMBINED_ACTIVITY 0xA
1549 #define I40E_FILTER_ACTIVITY 0xE
1550 #define I40E_LINK_ACTIVITY 0xC
1551 #define I40E_MAC_ACTIVITY 0xD
1552 #define I40E_LED0 22
1553
1554 /**
1555  * i40e_led_get - return current on/off mode
1556  * @hw: pointer to the hw struct
1557  *
1558  * The value returned is the 'mode' field as defined in the
1559  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1560  * values are variations of possible behaviors relating to
1561  * blink, link, and wire.
1562  **/
1563 u32 i40e_led_get(struct i40e_hw *hw)
1564 {
1565         u32 current_mode = 0;
1566         u32 mode = 0;
1567         int i;
1568
1569         /* as per the documentation GPIO 22-29 are the LED
1570          * GPIO pins named LED0..LED7
1571          */
1572         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1573                 u32 gpio_val = i40e_led_is_mine(hw, i);
1574
1575                 if (!gpio_val)
1576                         continue;
1577
1578                 /* ignore gpio LED src mode entries related to the activity
1579                  *  LEDs
1580                  */
1581                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1582                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1583                 switch (current_mode) {
1584                 case I40E_COMBINED_ACTIVITY:
1585                 case I40E_FILTER_ACTIVITY:
1586                 case I40E_MAC_ACTIVITY:
1587                         continue;
1588                 default:
1589                         break;
1590                 }
1591
1592                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1593                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1594                 break;
1595         }
1596
1597         return mode;
1598 }
1599
1600 /**
1601  * i40e_led_set - set new on/off mode
1602  * @hw: pointer to the hw struct
1603  * @mode: 0=off, 0xf=on (else see manual for mode details)
1604  * @blink: true if the LED should blink when on, false if steady
1605  *
1606  * if this function is used to turn on the blink it should
1607  * be used to disable the blink when restoring the original state.
1608  **/
1609 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1610 {
1611         u32 current_mode = 0;
1612         int i;
1613
1614         if (mode & 0xfffffff0)
1615                 DEBUGOUT1("invalid mode passed in %X\n", mode);
1616
1617         /* as per the documentation GPIO 22-29 are the LED
1618          * GPIO pins named LED0..LED7
1619          */
1620         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1621                 u32 gpio_val = i40e_led_is_mine(hw, i);
1622
1623                 if (!gpio_val)
1624                         continue;
1625
1626                 /* ignore gpio LED src mode entries related to the activity
1627                  * LEDs
1628                  */
1629                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1630                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1631                 switch (current_mode) {
1632                 case I40E_COMBINED_ACTIVITY:
1633                 case I40E_FILTER_ACTIVITY:
1634                 case I40E_MAC_ACTIVITY:
1635                         continue;
1636                 default:
1637                         break;
1638                 }
1639
1640                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1641                 /* this & is a bit of paranoia, but serves as a range check */
1642                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1643                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1644
1645                 if (mode == I40E_LINK_ACTIVITY)
1646                         blink = false;
1647
1648                 if (blink)
1649                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1650                 else
1651                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1652
1653                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1654                 break;
1655         }
1656 }
1657
1658 /* Admin command wrappers */
1659
1660 /**
1661  * i40e_aq_get_phy_capabilities
1662  * @hw: pointer to the hw struct
1663  * @abilities: structure for PHY capabilities to be filled
1664  * @qualified_modules: report Qualified Modules
1665  * @report_init: report init capabilities (active are default)
1666  * @cmd_details: pointer to command details structure or NULL
1667  *
1668  * Returns the various PHY abilities supported on the Port.
1669  **/
1670 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1671                         bool qualified_modules, bool report_init,
1672                         struct i40e_aq_get_phy_abilities_resp *abilities,
1673                         struct i40e_asq_cmd_details *cmd_details)
1674 {
1675         struct i40e_aq_desc desc;
1676         enum i40e_status_code status;
1677         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1678
1679         if (!abilities)
1680                 return I40E_ERR_PARAM;
1681
1682         i40e_fill_default_direct_cmd_desc(&desc,
1683                                           i40e_aqc_opc_get_phy_abilities);
1684
1685         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1686         if (abilities_size > I40E_AQ_LARGE_BUF)
1687                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1688
1689         if (qualified_modules)
1690                 desc.params.external.param0 |=
1691                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1692
1693         if (report_init)
1694                 desc.params.external.param0 |=
1695                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1696
1697         status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1698                                     cmd_details);
1699
1700         if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1701                 status = I40E_ERR_UNKNOWN_PHY;
1702
1703         if (report_init) {
1704                 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1705                 hw->phy.phy_types |= ((u64)abilities->phy_type_ext << 32);
1706         }
1707
1708         return status;
1709 }
1710
1711 /**
1712  * i40e_aq_set_phy_config
1713  * @hw: pointer to the hw struct
1714  * @config: structure with PHY configuration to be set
1715  * @cmd_details: pointer to command details structure or NULL
1716  *
1717  * Set the various PHY configuration parameters
1718  * supported on the Port.One or more of the Set PHY config parameters may be
1719  * ignored in an MFP mode as the PF may not have the privilege to set some
1720  * of the PHY Config parameters. This status will be indicated by the
1721  * command response.
1722  **/
1723 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1724                                 struct i40e_aq_set_phy_config *config,
1725                                 struct i40e_asq_cmd_details *cmd_details)
1726 {
1727         struct i40e_aq_desc desc;
1728         struct i40e_aq_set_phy_config *cmd =
1729                 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1730         enum i40e_status_code status;
1731
1732         if (!config)
1733                 return I40E_ERR_PARAM;
1734
1735         i40e_fill_default_direct_cmd_desc(&desc,
1736                                           i40e_aqc_opc_set_phy_config);
1737
1738         *cmd = *config;
1739
1740         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1741
1742         return status;
1743 }
1744
1745 /**
1746  * i40e_set_fc
1747  * @hw: pointer to the hw struct
1748  *
1749  * Set the requested flow control mode using set_phy_config.
1750  **/
1751 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1752                                   bool atomic_restart)
1753 {
1754         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1755         struct i40e_aq_get_phy_abilities_resp abilities;
1756         struct i40e_aq_set_phy_config config;
1757         enum i40e_status_code status;
1758         u8 pause_mask = 0x0;
1759
1760         *aq_failures = 0x0;
1761
1762         switch (fc_mode) {
1763         case I40E_FC_FULL:
1764                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1765                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1766                 break;
1767         case I40E_FC_RX_PAUSE:
1768                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1769                 break;
1770         case I40E_FC_TX_PAUSE:
1771                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1772                 break;
1773         default:
1774                 break;
1775         }
1776
1777         /* Get the current phy config */
1778         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1779                                               NULL);
1780         if (status) {
1781                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1782                 return status;
1783         }
1784
1785         memset(&config, 0, sizeof(config));
1786         /* clear the old pause settings */
1787         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1788                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1789         /* set the new abilities */
1790         config.abilities |= pause_mask;
1791         /* If the abilities have changed, then set the new config */
1792         if (config.abilities != abilities.abilities) {
1793                 /* Auto restart link so settings take effect */
1794                 if (atomic_restart)
1795                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1796                 /* Copy over all the old settings */
1797                 config.phy_type = abilities.phy_type;
1798                 config.phy_type_ext = abilities.phy_type_ext;
1799                 config.link_speed = abilities.link_speed;
1800                 config.eee_capability = abilities.eee_capability;
1801                 config.eeer = abilities.eeer_val;
1802                 config.low_power_ctrl = abilities.d3_lpan;
1803                 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1804                                     I40E_AQ_PHY_FEC_CONFIG_MASK;
1805                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1806
1807                 if (status)
1808                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1809         }
1810         /* Update the link info */
1811         status = i40e_update_link_info(hw);
1812         if (status) {
1813                 /* Wait a little bit (on 40G cards it sometimes takes a really
1814                  * long time for link to come back from the atomic reset)
1815                  * and try once more
1816                  */
1817                 i40e_msec_delay(1000);
1818                 status = i40e_update_link_info(hw);
1819         }
1820         if (status)
1821                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1822
1823         return status;
1824 }
1825
1826 /**
1827  * i40e_aq_set_mac_config
1828  * @hw: pointer to the hw struct
1829  * @max_frame_size: Maximum Frame Size to be supported by the port
1830  * @crc_en: Tell HW to append a CRC to outgoing frames
1831  * @pacing: Pacing configurations
1832  * @cmd_details: pointer to command details structure or NULL
1833  *
1834  * Configure MAC settings for frame size, jumbo frame support and the
1835  * addition of a CRC by the hardware.
1836  **/
1837 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1838                                 u16 max_frame_size,
1839                                 bool crc_en, u16 pacing,
1840                                 struct i40e_asq_cmd_details *cmd_details)
1841 {
1842         struct i40e_aq_desc desc;
1843         struct i40e_aq_set_mac_config *cmd =
1844                 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1845         enum i40e_status_code status;
1846
1847         if (max_frame_size == 0)
1848                 return I40E_ERR_PARAM;
1849
1850         i40e_fill_default_direct_cmd_desc(&desc,
1851                                           i40e_aqc_opc_set_mac_config);
1852
1853         cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1854         cmd->params = ((u8)pacing & 0x0F) << 3;
1855         if (crc_en)
1856                 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1857
1858         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1859
1860         return status;
1861 }
1862
1863 /**
1864  * i40e_aq_clear_pxe_mode
1865  * @hw: pointer to the hw struct
1866  * @cmd_details: pointer to command details structure or NULL
1867  *
1868  * Tell the firmware that the driver is taking over from PXE
1869  **/
1870 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1871                         struct i40e_asq_cmd_details *cmd_details)
1872 {
1873         enum i40e_status_code status;
1874         struct i40e_aq_desc desc;
1875         struct i40e_aqc_clear_pxe *cmd =
1876                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1877
1878         i40e_fill_default_direct_cmd_desc(&desc,
1879                                           i40e_aqc_opc_clear_pxe_mode);
1880
1881         cmd->rx_cnt = 0x2;
1882
1883         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1884
1885         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1886
1887         return status;
1888 }
1889
1890 /**
1891  * i40e_aq_set_link_restart_an
1892  * @hw: pointer to the hw struct
1893  * @enable_link: if true: enable link, if false: disable link
1894  * @cmd_details: pointer to command details structure or NULL
1895  *
1896  * Sets up the link and restarts the Auto-Negotiation over the link.
1897  **/
1898 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1899                 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1900 {
1901         struct i40e_aq_desc desc;
1902         struct i40e_aqc_set_link_restart_an *cmd =
1903                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1904         enum i40e_status_code status;
1905
1906         i40e_fill_default_direct_cmd_desc(&desc,
1907                                           i40e_aqc_opc_set_link_restart_an);
1908
1909         cmd->command = I40E_AQ_PHY_RESTART_AN;
1910         if (enable_link)
1911                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1912         else
1913                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1914
1915         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1916
1917         return status;
1918 }
1919
1920 /**
1921  * i40e_aq_get_link_info
1922  * @hw: pointer to the hw struct
1923  * @enable_lse: enable/disable LinkStatusEvent reporting
1924  * @link: pointer to link status structure - optional
1925  * @cmd_details: pointer to command details structure or NULL
1926  *
1927  * Returns the link status of the adapter.
1928  **/
1929 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1930                                 bool enable_lse, struct i40e_link_status *link,
1931                                 struct i40e_asq_cmd_details *cmd_details)
1932 {
1933         struct i40e_aq_desc desc;
1934         struct i40e_aqc_get_link_status *resp =
1935                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1936         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1937         enum i40e_status_code status;
1938         bool tx_pause, rx_pause;
1939         u16 command_flags;
1940
1941         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1942
1943         if (enable_lse)
1944                 command_flags = I40E_AQ_LSE_ENABLE;
1945         else
1946                 command_flags = I40E_AQ_LSE_DISABLE;
1947         resp->command_flags = CPU_TO_LE16(command_flags);
1948
1949         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1950
1951         if (status != I40E_SUCCESS)
1952                 goto aq_get_link_info_exit;
1953
1954         /* save off old link status information */
1955         i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1956                     sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1957
1958         /* update link status */
1959         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1960         hw->phy.media_type = i40e_get_media_type(hw);
1961         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1962         hw_link_info->link_info = resp->link_info;
1963         hw_link_info->an_info = resp->an_info;
1964         hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
1965                                                  I40E_AQ_CONFIG_FEC_RS_ENA);
1966         hw_link_info->ext_info = resp->ext_info;
1967         hw_link_info->loopback = resp->loopback;
1968         hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1969         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1970
1971         /* update fc info */
1972         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1973         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1974         if (tx_pause & rx_pause)
1975                 hw->fc.current_mode = I40E_FC_FULL;
1976         else if (tx_pause)
1977                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1978         else if (rx_pause)
1979                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1980         else
1981                 hw->fc.current_mode = I40E_FC_NONE;
1982
1983         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1984                 hw_link_info->crc_enable = true;
1985         else
1986                 hw_link_info->crc_enable = false;
1987
1988         if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
1989                 hw_link_info->lse_enable = true;
1990         else
1991                 hw_link_info->lse_enable = false;
1992
1993         if ((hw->mac.type == I40E_MAC_XL710) &&
1994             (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1995              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1996                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1997
1998         /* save link status information */
1999         if (link)
2000                 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
2001                             I40E_NONDMA_TO_NONDMA);
2002
2003         /* flag cleared so helper functions don't call AQ again */
2004         hw->phy.get_link_info = false;
2005
2006 aq_get_link_info_exit:
2007         return status;
2008 }
2009
2010 /**
2011  * i40e_aq_set_phy_int_mask
2012  * @hw: pointer to the hw struct
2013  * @mask: interrupt mask to be set
2014  * @cmd_details: pointer to command details structure or NULL
2015  *
2016  * Set link interrupt mask.
2017  **/
2018 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2019                                 u16 mask,
2020                                 struct i40e_asq_cmd_details *cmd_details)
2021 {
2022         struct i40e_aq_desc desc;
2023         struct i40e_aqc_set_phy_int_mask *cmd =
2024                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2025         enum i40e_status_code status;
2026
2027         i40e_fill_default_direct_cmd_desc(&desc,
2028                                           i40e_aqc_opc_set_phy_int_mask);
2029
2030         cmd->event_mask = CPU_TO_LE16(mask);
2031
2032         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2033
2034         return status;
2035 }
2036
2037 /**
2038  * i40e_aq_get_local_advt_reg
2039  * @hw: pointer to the hw struct
2040  * @advt_reg: local AN advertisement register value
2041  * @cmd_details: pointer to command details structure or NULL
2042  *
2043  * Get the Local AN advertisement register value.
2044  **/
2045 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2046                                 u64 *advt_reg,
2047                                 struct i40e_asq_cmd_details *cmd_details)
2048 {
2049         struct i40e_aq_desc desc;
2050         struct i40e_aqc_an_advt_reg *resp =
2051                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2052         enum i40e_status_code status;
2053
2054         i40e_fill_default_direct_cmd_desc(&desc,
2055                                           i40e_aqc_opc_get_local_advt_reg);
2056
2057         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2058
2059         if (status != I40E_SUCCESS)
2060                 goto aq_get_local_advt_reg_exit;
2061
2062         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2063         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2064
2065 aq_get_local_advt_reg_exit:
2066         return status;
2067 }
2068
2069 /**
2070  * i40e_aq_set_local_advt_reg
2071  * @hw: pointer to the hw struct
2072  * @advt_reg: local AN advertisement register value
2073  * @cmd_details: pointer to command details structure or NULL
2074  *
2075  * Get the Local AN advertisement register value.
2076  **/
2077 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2078                                 u64 advt_reg,
2079                                 struct i40e_asq_cmd_details *cmd_details)
2080 {
2081         struct i40e_aq_desc desc;
2082         struct i40e_aqc_an_advt_reg *cmd =
2083                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2084         enum i40e_status_code status;
2085
2086         i40e_fill_default_direct_cmd_desc(&desc,
2087                                           i40e_aqc_opc_get_local_advt_reg);
2088
2089         cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2090         cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2091
2092         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2093
2094         return status;
2095 }
2096
2097 /**
2098  * i40e_aq_get_partner_advt
2099  * @hw: pointer to the hw struct
2100  * @advt_reg: AN partner advertisement register value
2101  * @cmd_details: pointer to command details structure or NULL
2102  *
2103  * Get the link partner AN advertisement register value.
2104  **/
2105 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2106                                 u64 *advt_reg,
2107                                 struct i40e_asq_cmd_details *cmd_details)
2108 {
2109         struct i40e_aq_desc desc;
2110         struct i40e_aqc_an_advt_reg *resp =
2111                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2112         enum i40e_status_code status;
2113
2114         i40e_fill_default_direct_cmd_desc(&desc,
2115                                           i40e_aqc_opc_get_partner_advt);
2116
2117         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2118
2119         if (status != I40E_SUCCESS)
2120                 goto aq_get_partner_advt_exit;
2121
2122         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2123         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2124
2125 aq_get_partner_advt_exit:
2126         return status;
2127 }
2128
2129 /**
2130  * i40e_aq_set_lb_modes
2131  * @hw: pointer to the hw struct
2132  * @lb_modes: loopback mode to be set
2133  * @cmd_details: pointer to command details structure or NULL
2134  *
2135  * Sets loopback modes.
2136  **/
2137 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2138                                 u16 lb_modes,
2139                                 struct i40e_asq_cmd_details *cmd_details)
2140 {
2141         struct i40e_aq_desc desc;
2142         struct i40e_aqc_set_lb_mode *cmd =
2143                 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2144         enum i40e_status_code status;
2145
2146         i40e_fill_default_direct_cmd_desc(&desc,
2147                                           i40e_aqc_opc_set_lb_modes);
2148
2149         cmd->lb_mode = CPU_TO_LE16(lb_modes);
2150
2151         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2152
2153         return status;
2154 }
2155
2156 /**
2157  * i40e_aq_set_phy_debug
2158  * @hw: pointer to the hw struct
2159  * @cmd_flags: debug command flags
2160  * @cmd_details: pointer to command details structure or NULL
2161  *
2162  * Reset the external PHY.
2163  **/
2164 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2165                                 struct i40e_asq_cmd_details *cmd_details)
2166 {
2167         struct i40e_aq_desc desc;
2168         struct i40e_aqc_set_phy_debug *cmd =
2169                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2170         enum i40e_status_code status;
2171
2172         i40e_fill_default_direct_cmd_desc(&desc,
2173                                           i40e_aqc_opc_set_phy_debug);
2174
2175         cmd->command_flags = cmd_flags;
2176
2177         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2178
2179         return status;
2180 }
2181
2182 /**
2183  * i40e_aq_add_vsi
2184  * @hw: pointer to the hw struct
2185  * @vsi_ctx: pointer to a vsi context struct
2186  * @cmd_details: pointer to command details structure or NULL
2187  *
2188  * Add a VSI context to the hardware.
2189 **/
2190 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2191                                 struct i40e_vsi_context *vsi_ctx,
2192                                 struct i40e_asq_cmd_details *cmd_details)
2193 {
2194         struct i40e_aq_desc desc;
2195         struct i40e_aqc_add_get_update_vsi *cmd =
2196                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2197         struct i40e_aqc_add_get_update_vsi_completion *resp =
2198                 (struct i40e_aqc_add_get_update_vsi_completion *)
2199                 &desc.params.raw;
2200         enum i40e_status_code status;
2201
2202         i40e_fill_default_direct_cmd_desc(&desc,
2203                                           i40e_aqc_opc_add_vsi);
2204
2205         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2206         cmd->connection_type = vsi_ctx->connection_type;
2207         cmd->vf_id = vsi_ctx->vf_num;
2208         cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2209
2210         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2211
2212         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2213                                     sizeof(vsi_ctx->info), cmd_details);
2214
2215         if (status != I40E_SUCCESS)
2216                 goto aq_add_vsi_exit;
2217
2218         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2219         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2220         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2221         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2222
2223 aq_add_vsi_exit:
2224         return status;
2225 }
2226
2227 /**
2228  * i40e_aq_set_default_vsi
2229  * @hw: pointer to the hw struct
2230  * @seid: vsi number
2231  * @cmd_details: pointer to command details structure or NULL
2232  **/
2233 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2234                                 u16 seid,
2235                                 struct i40e_asq_cmd_details *cmd_details)
2236 {
2237         struct i40e_aq_desc desc;
2238         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2239                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2240                 &desc.params.raw;
2241         enum i40e_status_code status;
2242
2243         i40e_fill_default_direct_cmd_desc(&desc,
2244                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2245
2246         cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2247         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2248         cmd->seid = CPU_TO_LE16(seid);
2249
2250         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2251
2252         return status;
2253 }
2254
2255 /**
2256  * i40e_aq_clear_default_vsi
2257  * @hw: pointer to the hw struct
2258  * @seid: vsi number
2259  * @cmd_details: pointer to command details structure or NULL
2260  **/
2261 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2262                                 u16 seid,
2263                                 struct i40e_asq_cmd_details *cmd_details)
2264 {
2265         struct i40e_aq_desc desc;
2266         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2267                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2268                 &desc.params.raw;
2269         enum i40e_status_code status;
2270
2271         i40e_fill_default_direct_cmd_desc(&desc,
2272                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2273
2274         cmd->promiscuous_flags = CPU_TO_LE16(0);
2275         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2276         cmd->seid = CPU_TO_LE16(seid);
2277
2278         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2279
2280         return status;
2281 }
2282
2283 /**
2284  * i40e_aq_set_vsi_unicast_promiscuous
2285  * @hw: pointer to the hw struct
2286  * @seid: vsi number
2287  * @set: set unicast promiscuous enable/disable
2288  * @cmd_details: pointer to command details structure or NULL
2289  * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2290  **/
2291 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2292                                 u16 seid, bool set,
2293                                 struct i40e_asq_cmd_details *cmd_details,
2294                                 bool rx_only_promisc)
2295 {
2296         struct i40e_aq_desc desc;
2297         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2298                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2299         enum i40e_status_code status;
2300         u16 flags = 0;
2301
2302         i40e_fill_default_direct_cmd_desc(&desc,
2303                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2304
2305         if (set) {
2306                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2307                 if (rx_only_promisc &&
2308                     (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2309                      (hw->aq.api_maj_ver > 1)))
2310                         flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2311         }
2312
2313         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2314
2315         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2316         if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2317              (hw->aq.api_maj_ver > 1))
2318                 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2319
2320         cmd->seid = CPU_TO_LE16(seid);
2321         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2322
2323         return status;
2324 }
2325
2326 /**
2327  * i40e_aq_set_vsi_multicast_promiscuous
2328  * @hw: pointer to the hw struct
2329  * @seid: vsi number
2330  * @set: set multicast promiscuous enable/disable
2331  * @cmd_details: pointer to command details structure or NULL
2332  **/
2333 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2334                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2335 {
2336         struct i40e_aq_desc desc;
2337         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2338                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2339         enum i40e_status_code status;
2340         u16 flags = 0;
2341
2342         i40e_fill_default_direct_cmd_desc(&desc,
2343                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2344
2345         if (set)
2346                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2347
2348         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2349
2350         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2351
2352         cmd->seid = CPU_TO_LE16(seid);
2353         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2354
2355         return status;
2356 }
2357
2358 /**
2359 * i40e_aq_set_vsi_full_promiscuous
2360 * @hw: pointer to the hw struct
2361 * @seid: VSI number
2362 * @set: set promiscuous enable/disable
2363 * @cmd_details: pointer to command details structure or NULL
2364 **/
2365 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw,
2366                                 u16 seid, bool set,
2367                                 struct i40e_asq_cmd_details *cmd_details)
2368 {
2369         struct i40e_aq_desc desc;
2370         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2371                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2372         enum i40e_status_code status;
2373         u16 flags = 0;
2374
2375         i40e_fill_default_direct_cmd_desc(&desc,
2376                 i40e_aqc_opc_set_vsi_promiscuous_modes);
2377
2378         if (set)
2379                 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2380                         I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2381                         I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2382
2383         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2384
2385         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2386                                        I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2387                                        I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2388
2389         cmd->seid = CPU_TO_LE16(seid);
2390         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2391
2392         return status;
2393 }
2394
2395 /**
2396  * i40e_aq_set_vsi_mc_promisc_on_vlan
2397  * @hw: pointer to the hw struct
2398  * @seid: vsi number
2399  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2400  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2401  * @cmd_details: pointer to command details structure or NULL
2402  **/
2403 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2404                                 u16 seid, bool enable, u16 vid,
2405                                 struct i40e_asq_cmd_details *cmd_details)
2406 {
2407         struct i40e_aq_desc desc;
2408         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2409                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2410         enum i40e_status_code status;
2411         u16 flags = 0;
2412
2413         i40e_fill_default_direct_cmd_desc(&desc,
2414                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2415
2416         if (enable)
2417                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2418
2419         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2420         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2421         cmd->seid = CPU_TO_LE16(seid);
2422         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2423
2424         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2425
2426         return status;
2427 }
2428
2429 /**
2430  * i40e_aq_set_vsi_uc_promisc_on_vlan
2431  * @hw: pointer to the hw struct
2432  * @seid: vsi number
2433  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2434  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2435  * @cmd_details: pointer to command details structure or NULL
2436  **/
2437 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2438                                 u16 seid, bool enable, u16 vid,
2439                                 struct i40e_asq_cmd_details *cmd_details)
2440 {
2441         struct i40e_aq_desc desc;
2442         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2443                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2444         enum i40e_status_code status;
2445         u16 flags = 0;
2446
2447         i40e_fill_default_direct_cmd_desc(&desc,
2448                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2449
2450         if (enable)
2451                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2452
2453         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2454         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2455         cmd->seid = CPU_TO_LE16(seid);
2456         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2457
2458         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2459
2460         return status;
2461 }
2462
2463 /**
2464  * i40e_aq_set_vsi_bc_promisc_on_vlan
2465  * @hw: pointer to the hw struct
2466  * @seid: vsi number
2467  * @enable: set broadcast promiscuous enable/disable for a given VLAN
2468  * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2469  * @cmd_details: pointer to command details structure or NULL
2470  **/
2471 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2472                                 u16 seid, bool enable, u16 vid,
2473                                 struct i40e_asq_cmd_details *cmd_details)
2474 {
2475         struct i40e_aq_desc desc;
2476         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2477                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2478         enum i40e_status_code status;
2479         u16 flags = 0;
2480
2481         i40e_fill_default_direct_cmd_desc(&desc,
2482                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2483
2484         if (enable)
2485                 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2486
2487         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2488         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2489         cmd->seid = CPU_TO_LE16(seid);
2490         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2491
2492         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2493
2494         return status;
2495 }
2496
2497 /**
2498  * i40e_aq_set_vsi_broadcast
2499  * @hw: pointer to the hw struct
2500  * @seid: vsi number
2501  * @set_filter: true to set filter, false to clear filter
2502  * @cmd_details: pointer to command details structure or NULL
2503  *
2504  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2505  **/
2506 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2507                                 u16 seid, bool set_filter,
2508                                 struct i40e_asq_cmd_details *cmd_details)
2509 {
2510         struct i40e_aq_desc desc;
2511         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2512                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2513         enum i40e_status_code status;
2514
2515         i40e_fill_default_direct_cmd_desc(&desc,
2516                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2517
2518         if (set_filter)
2519                 cmd->promiscuous_flags
2520                             |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2521         else
2522                 cmd->promiscuous_flags
2523                             &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2524
2525         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2526         cmd->seid = CPU_TO_LE16(seid);
2527         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2528
2529         return status;
2530 }
2531
2532 /**
2533  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2534  * @hw: pointer to the hw struct
2535  * @seid: vsi number
2536  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2537  * @cmd_details: pointer to command details structure or NULL
2538  **/
2539 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2540                                 u16 seid, bool enable,
2541                                 struct i40e_asq_cmd_details *cmd_details)
2542 {
2543         struct i40e_aq_desc desc;
2544         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2545                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2546         enum i40e_status_code status;
2547         u16 flags = 0;
2548
2549         i40e_fill_default_direct_cmd_desc(&desc,
2550                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2551         if (enable)
2552                 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2553
2554         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2555         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2556         cmd->seid = CPU_TO_LE16(seid);
2557
2558         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2559
2560         return status;
2561 }
2562
2563 /**
2564  * i40e_get_vsi_params - get VSI configuration info
2565  * @hw: pointer to the hw struct
2566  * @vsi_ctx: pointer to a vsi context struct
2567  * @cmd_details: pointer to command details structure or NULL
2568  **/
2569 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2570                                 struct i40e_vsi_context *vsi_ctx,
2571                                 struct i40e_asq_cmd_details *cmd_details)
2572 {
2573         struct i40e_aq_desc desc;
2574         struct i40e_aqc_add_get_update_vsi *cmd =
2575                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2576         struct i40e_aqc_add_get_update_vsi_completion *resp =
2577                 (struct i40e_aqc_add_get_update_vsi_completion *)
2578                 &desc.params.raw;
2579         enum i40e_status_code status;
2580
2581         UNREFERENCED_1PARAMETER(cmd_details);
2582         i40e_fill_default_direct_cmd_desc(&desc,
2583                                           i40e_aqc_opc_get_vsi_parameters);
2584
2585         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2586
2587         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2588
2589         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2590                                     sizeof(vsi_ctx->info), NULL);
2591
2592         if (status != I40E_SUCCESS)
2593                 goto aq_get_vsi_params_exit;
2594
2595         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2596         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2597         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2598         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2599
2600 aq_get_vsi_params_exit:
2601         return status;
2602 }
2603
2604 /**
2605  * i40e_aq_update_vsi_params
2606  * @hw: pointer to the hw struct
2607  * @vsi_ctx: pointer to a vsi context struct
2608  * @cmd_details: pointer to command details structure or NULL
2609  *
2610  * Update a VSI context.
2611  **/
2612 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2613                                 struct i40e_vsi_context *vsi_ctx,
2614                                 struct i40e_asq_cmd_details *cmd_details)
2615 {
2616         struct i40e_aq_desc desc;
2617         struct i40e_aqc_add_get_update_vsi *cmd =
2618                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2619         struct i40e_aqc_add_get_update_vsi_completion *resp =
2620                 (struct i40e_aqc_add_get_update_vsi_completion *)
2621                 &desc.params.raw;
2622         enum i40e_status_code status;
2623
2624         i40e_fill_default_direct_cmd_desc(&desc,
2625                                           i40e_aqc_opc_update_vsi_parameters);
2626         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2627
2628         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2629
2630         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2631                                     sizeof(vsi_ctx->info), cmd_details);
2632
2633         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2634         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2635
2636         return status;
2637 }
2638
2639 /**
2640  * i40e_aq_get_switch_config
2641  * @hw: pointer to the hardware structure
2642  * @buf: pointer to the result buffer
2643  * @buf_size: length of input buffer
2644  * @start_seid: seid to start for the report, 0 == beginning
2645  * @cmd_details: pointer to command details structure or NULL
2646  *
2647  * Fill the buf with switch configuration returned from AdminQ command
2648  **/
2649 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2650                                 struct i40e_aqc_get_switch_config_resp *buf,
2651                                 u16 buf_size, u16 *start_seid,
2652                                 struct i40e_asq_cmd_details *cmd_details)
2653 {
2654         struct i40e_aq_desc desc;
2655         struct i40e_aqc_switch_seid *scfg =
2656                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2657         enum i40e_status_code status;
2658
2659         i40e_fill_default_direct_cmd_desc(&desc,
2660                                           i40e_aqc_opc_get_switch_config);
2661         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2662         if (buf_size > I40E_AQ_LARGE_BUF)
2663                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2664         scfg->seid = CPU_TO_LE16(*start_seid);
2665
2666         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2667         *start_seid = LE16_TO_CPU(scfg->seid);
2668
2669         return status;
2670 }
2671
2672 /**
2673  * i40e_aq_set_switch_config
2674  * @hw: pointer to the hardware structure
2675  * @flags: bit flag values to set
2676  * @valid_flags: which bit flags to set
2677  * @cmd_details: pointer to command details structure or NULL
2678  *
2679  * Set switch configuration bits
2680  **/
2681 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2682                                 u16 flags, u16 valid_flags,
2683                                 struct i40e_asq_cmd_details *cmd_details)
2684 {
2685         struct i40e_aq_desc desc;
2686         struct i40e_aqc_set_switch_config *scfg =
2687                 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2688         enum i40e_status_code status;
2689
2690         i40e_fill_default_direct_cmd_desc(&desc,
2691                                           i40e_aqc_opc_set_switch_config);
2692         scfg->flags = CPU_TO_LE16(flags);
2693         scfg->valid_flags = CPU_TO_LE16(valid_flags);
2694
2695         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2696
2697         return status;
2698 }
2699
2700 /**
2701  * i40e_aq_get_firmware_version
2702  * @hw: pointer to the hw struct
2703  * @fw_major_version: firmware major version
2704  * @fw_minor_version: firmware minor version
2705  * @fw_build: firmware build number
2706  * @api_major_version: major queue version
2707  * @api_minor_version: minor queue version
2708  * @cmd_details: pointer to command details structure or NULL
2709  *
2710  * Get the firmware version from the admin queue commands
2711  **/
2712 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2713                                 u16 *fw_major_version, u16 *fw_minor_version,
2714                                 u32 *fw_build,
2715                                 u16 *api_major_version, u16 *api_minor_version,
2716                                 struct i40e_asq_cmd_details *cmd_details)
2717 {
2718         struct i40e_aq_desc desc;
2719         struct i40e_aqc_get_version *resp =
2720                 (struct i40e_aqc_get_version *)&desc.params.raw;
2721         enum i40e_status_code status;
2722
2723         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2724
2725         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2726
2727         if (status == I40E_SUCCESS) {
2728                 if (fw_major_version != NULL)
2729                         *fw_major_version = LE16_TO_CPU(resp->fw_major);
2730                 if (fw_minor_version != NULL)
2731                         *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2732                 if (fw_build != NULL)
2733                         *fw_build = LE32_TO_CPU(resp->fw_build);
2734                 if (api_major_version != NULL)
2735                         *api_major_version = LE16_TO_CPU(resp->api_major);
2736                 if (api_minor_version != NULL)
2737                         *api_minor_version = LE16_TO_CPU(resp->api_minor);
2738
2739                 /* A workaround to fix the API version in SW */
2740                 if (api_major_version && api_minor_version &&
2741                     fw_major_version && fw_minor_version &&
2742                     ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2743                     (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2744                      (*fw_major_version > 4)))
2745                         *api_minor_version = 2;
2746         }
2747
2748         return status;
2749 }
2750
2751 /**
2752  * i40e_aq_send_driver_version
2753  * @hw: pointer to the hw struct
2754  * @dv: driver's major, minor version
2755  * @cmd_details: pointer to command details structure or NULL
2756  *
2757  * Send the driver version to the firmware
2758  **/
2759 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2760                                 struct i40e_driver_version *dv,
2761                                 struct i40e_asq_cmd_details *cmd_details)
2762 {
2763         struct i40e_aq_desc desc;
2764         struct i40e_aqc_driver_version *cmd =
2765                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2766         enum i40e_status_code status;
2767         u16 len;
2768
2769         if (dv == NULL)
2770                 return I40E_ERR_PARAM;
2771
2772         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2773
2774         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2775         cmd->driver_major_ver = dv->major_version;
2776         cmd->driver_minor_ver = dv->minor_version;
2777         cmd->driver_build_ver = dv->build_version;
2778         cmd->driver_subbuild_ver = dv->subbuild_version;
2779
2780         len = 0;
2781         while (len < sizeof(dv->driver_string) &&
2782                (dv->driver_string[len] < 0x80) &&
2783                dv->driver_string[len])
2784                 len++;
2785         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2786                                        len, cmd_details);
2787
2788         return status;
2789 }
2790
2791 /**
2792  * i40e_get_link_status - get status of the HW network link
2793  * @hw: pointer to the hw struct
2794  * @link_up: pointer to bool (true/false = linkup/linkdown)
2795  *
2796  * Variable link_up true if link is up, false if link is down.
2797  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2798  *
2799  * Side effect: LinkStatusEvent reporting becomes enabled
2800  **/
2801 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2802 {
2803         enum i40e_status_code status = I40E_SUCCESS;
2804
2805         if (hw->phy.get_link_info) {
2806                 status = i40e_update_link_info(hw);
2807
2808                 if (status != I40E_SUCCESS)
2809                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2810                                    status);
2811         }
2812
2813         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2814
2815         return status;
2816 }
2817
2818 /**
2819  * i40e_updatelink_status - update status of the HW network link
2820  * @hw: pointer to the hw struct
2821  **/
2822 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2823 {
2824         struct i40e_aq_get_phy_abilities_resp abilities;
2825         enum i40e_status_code status = I40E_SUCCESS;
2826
2827         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2828         if (status)
2829                 return status;
2830
2831         /* extra checking needed to ensure link info to user is timely */
2832         if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2833             ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2834              !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2835                 status = i40e_aq_get_phy_capabilities(hw, false, false,
2836                                                       &abilities, NULL);
2837                 if (status)
2838                         return status;
2839
2840                 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2841                         sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2842         }
2843         return status;
2844 }
2845
2846
2847 /**
2848  * i40e_get_link_speed
2849  * @hw: pointer to the hw struct
2850  *
2851  * Returns the link speed of the adapter.
2852  **/
2853 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2854 {
2855         enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2856         enum i40e_status_code status = I40E_SUCCESS;
2857
2858         if (hw->phy.get_link_info) {
2859                 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2860
2861                 if (status != I40E_SUCCESS)
2862                         goto i40e_link_speed_exit;
2863         }
2864
2865         speed = hw->phy.link_info.link_speed;
2866
2867 i40e_link_speed_exit:
2868         return speed;
2869 }
2870
2871 /**
2872  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2873  * @hw: pointer to the hw struct
2874  * @uplink_seid: the MAC or other gizmo SEID
2875  * @downlink_seid: the VSI SEID
2876  * @enabled_tc: bitmap of TCs to be enabled
2877  * @default_port: true for default port VSI, false for control port
2878  * @veb_seid: pointer to where to put the resulting VEB SEID
2879  * @enable_stats: true to turn on VEB stats
2880  * @cmd_details: pointer to command details structure or NULL
2881  *
2882  * This asks the FW to add a VEB between the uplink and downlink
2883  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2884  **/
2885 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2886                                 u16 downlink_seid, u8 enabled_tc,
2887                                 bool default_port, u16 *veb_seid,
2888                                 bool enable_stats,
2889                                 struct i40e_asq_cmd_details *cmd_details)
2890 {
2891         struct i40e_aq_desc desc;
2892         struct i40e_aqc_add_veb *cmd =
2893                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2894         struct i40e_aqc_add_veb_completion *resp =
2895                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2896         enum i40e_status_code status;
2897         u16 veb_flags = 0;
2898
2899         /* SEIDs need to either both be set or both be 0 for floating VEB */
2900         if (!!uplink_seid != !!downlink_seid)
2901                 return I40E_ERR_PARAM;
2902
2903         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2904
2905         cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2906         cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2907         cmd->enable_tcs = enabled_tc;
2908         if (!uplink_seid)
2909                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2910         if (default_port)
2911                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2912         else
2913                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2914
2915         /* reverse logic here: set the bitflag to disable the stats */
2916         if (!enable_stats)
2917                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2918
2919         cmd->veb_flags = CPU_TO_LE16(veb_flags);
2920
2921         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2922
2923         if (!status && veb_seid)
2924                 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2925
2926         return status;
2927 }
2928
2929 /**
2930  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2931  * @hw: pointer to the hw struct
2932  * @veb_seid: the SEID of the VEB to query
2933  * @switch_id: the uplink switch id
2934  * @floating: set to true if the VEB is floating
2935  * @statistic_index: index of the stats counter block for this VEB
2936  * @vebs_used: number of VEB's used by function
2937  * @vebs_free: total VEB's not reserved by any function
2938  * @cmd_details: pointer to command details structure or NULL
2939  *
2940  * This retrieves the parameters for a particular VEB, specified by
2941  * uplink_seid, and returns them to the caller.
2942  **/
2943 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2944                                 u16 veb_seid, u16 *switch_id,
2945                                 bool *floating, u16 *statistic_index,
2946                                 u16 *vebs_used, u16 *vebs_free,
2947                                 struct i40e_asq_cmd_details *cmd_details)
2948 {
2949         struct i40e_aq_desc desc;
2950         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2951                 (struct i40e_aqc_get_veb_parameters_completion *)
2952                 &desc.params.raw;
2953         enum i40e_status_code status;
2954
2955         if (veb_seid == 0)
2956                 return I40E_ERR_PARAM;
2957
2958         i40e_fill_default_direct_cmd_desc(&desc,
2959                                           i40e_aqc_opc_get_veb_parameters);
2960         cmd_resp->seid = CPU_TO_LE16(veb_seid);
2961
2962         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2963         if (status)
2964                 goto get_veb_exit;
2965
2966         if (switch_id)
2967                 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2968         if (statistic_index)
2969                 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2970         if (vebs_used)
2971                 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2972         if (vebs_free)
2973                 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2974         if (floating) {
2975                 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2976
2977                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2978                         *floating = true;
2979                 else
2980                         *floating = false;
2981         }
2982
2983 get_veb_exit:
2984         return status;
2985 }
2986
2987 /**
2988  * i40e_aq_add_macvlan
2989  * @hw: pointer to the hw struct
2990  * @seid: VSI for the mac address
2991  * @mv_list: list of macvlans to be added
2992  * @count: length of the list
2993  * @cmd_details: pointer to command details structure or NULL
2994  *
2995  * Add MAC/VLAN addresses to the HW filtering
2996  **/
2997 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2998                         struct i40e_aqc_add_macvlan_element_data *mv_list,
2999                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3000 {
3001         struct i40e_aq_desc desc;
3002         struct i40e_aqc_macvlan *cmd =
3003                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3004         enum i40e_status_code status;
3005         u16 buf_size;
3006         int i;
3007
3008         if (count == 0 || !mv_list || !hw)
3009                 return I40E_ERR_PARAM;
3010
3011         buf_size = count * sizeof(*mv_list);
3012
3013         /* prep the rest of the request */
3014         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
3015         cmd->num_addresses = CPU_TO_LE16(count);
3016         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3017         cmd->seid[1] = 0;
3018         cmd->seid[2] = 0;
3019
3020         for (i = 0; i < count; i++)
3021                 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
3022                         mv_list[i].flags |=
3023                             CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
3024
3025         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3026         if (buf_size > I40E_AQ_LARGE_BUF)
3027                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3028
3029         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3030                                        cmd_details);
3031
3032         return status;
3033 }
3034
3035 /**
3036  * i40e_aq_remove_macvlan
3037  * @hw: pointer to the hw struct
3038  * @seid: VSI for the mac address
3039  * @mv_list: list of macvlans to be removed
3040  * @count: length of the list
3041  * @cmd_details: pointer to command details structure or NULL
3042  *
3043  * Remove MAC/VLAN addresses from the HW filtering
3044  **/
3045 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
3046                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
3047                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3048 {
3049         struct i40e_aq_desc desc;
3050         struct i40e_aqc_macvlan *cmd =
3051                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3052         enum i40e_status_code status;
3053         u16 buf_size;
3054
3055         if (count == 0 || !mv_list || !hw)
3056                 return I40E_ERR_PARAM;
3057
3058         buf_size = count * sizeof(*mv_list);
3059
3060         /* prep the rest of the request */
3061         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
3062         cmd->num_addresses = CPU_TO_LE16(count);
3063         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3064         cmd->seid[1] = 0;
3065         cmd->seid[2] = 0;
3066
3067         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3068         if (buf_size > I40E_AQ_LARGE_BUF)
3069                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3070
3071         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3072                                        cmd_details);
3073
3074         return status;
3075 }
3076
3077 /**
3078  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3079  * @hw: pointer to the hw struct
3080  * @opcode: AQ opcode for add or delete mirror rule
3081  * @sw_seid: Switch SEID (to which rule refers)
3082  * @rule_type: Rule Type (ingress/egress/VLAN)
3083  * @id: Destination VSI SEID or Rule ID
3084  * @count: length of the list
3085  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3086  * @cmd_details: pointer to command details structure or NULL
3087  * @rule_id: Rule ID returned from FW
3088  * @rule_used: Number of rules used in internal switch
3089  * @rule_free: Number of rules free in internal switch
3090  *
3091  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3092  * VEBs/VEPA elements only
3093  **/
3094 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3095                         u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3096                         u16 count, __le16 *mr_list,
3097                         struct i40e_asq_cmd_details *cmd_details,
3098                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3099 {
3100         struct i40e_aq_desc desc;
3101         struct i40e_aqc_add_delete_mirror_rule *cmd =
3102                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3103         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3104         (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3105         enum i40e_status_code status;
3106         u16 buf_size;
3107
3108         buf_size = count * sizeof(*mr_list);
3109
3110         /* prep the rest of the request */
3111         i40e_fill_default_direct_cmd_desc(&desc, opcode);
3112         cmd->seid = CPU_TO_LE16(sw_seid);
3113         cmd->rule_type = CPU_TO_LE16(rule_type &
3114                                      I40E_AQC_MIRROR_RULE_TYPE_MASK);
3115         cmd->num_entries = CPU_TO_LE16(count);
3116         /* Dest VSI for add, rule_id for delete */
3117         cmd->destination = CPU_TO_LE16(id);
3118         if (mr_list) {
3119                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3120                                                 I40E_AQ_FLAG_RD));
3121                 if (buf_size > I40E_AQ_LARGE_BUF)
3122                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3123         }
3124
3125         status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3126                                        cmd_details);
3127         if (status == I40E_SUCCESS ||
3128             hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3129                 if (rule_id)
3130                         *rule_id = LE16_TO_CPU(resp->rule_id);
3131                 if (rules_used)
3132                         *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3133                 if (rules_free)
3134                         *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3135         }
3136         return status;
3137 }
3138
3139 /**
3140  * i40e_aq_add_mirrorrule - add a mirror rule
3141  * @hw: pointer to the hw struct
3142  * @sw_seid: Switch SEID (to which rule refers)
3143  * @rule_type: Rule Type (ingress/egress/VLAN)
3144  * @dest_vsi: SEID of VSI to which packets will be mirrored
3145  * @count: length of the list
3146  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3147  * @cmd_details: pointer to command details structure or NULL
3148  * @rule_id: Rule ID returned from FW
3149  * @rule_used: Number of rules used in internal switch
3150  * @rule_free: Number of rules free in internal switch
3151  *
3152  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3153  **/
3154 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3155                         u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3156                         struct i40e_asq_cmd_details *cmd_details,
3157                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3158 {
3159         if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3160             rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3161                 if (count == 0 || !mr_list)
3162                         return I40E_ERR_PARAM;
3163         }
3164
3165         return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3166                                   rule_type, dest_vsi, count, mr_list,
3167                                   cmd_details, rule_id, rules_used, rules_free);
3168 }
3169
3170 /**
3171  * i40e_aq_delete_mirrorrule - delete a mirror rule
3172  * @hw: pointer to the hw struct
3173  * @sw_seid: Switch SEID (to which rule refers)
3174  * @rule_type: Rule Type (ingress/egress/VLAN)
3175  * @count: length of the list
3176  * @rule_id: Rule ID that is returned in the receive desc as part of
3177  *              add_mirrorrule.
3178  * @mr_list: list of mirrored VLAN IDs to be removed
3179  * @cmd_details: pointer to command details structure or NULL
3180  * @rule_used: Number of rules used in internal switch
3181  * @rule_free: Number of rules free in internal switch
3182  *
3183  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3184  **/
3185 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3186                         u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3187                         struct i40e_asq_cmd_details *cmd_details,
3188                         u16 *rules_used, u16 *rules_free)
3189 {
3190         /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3191         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3192                 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3193                  * mirroring. For other rule_type, count and rule_type should
3194                  * not matter.
3195                  */
3196                 if (count == 0 || !mr_list)
3197                         return I40E_ERR_PARAM;
3198         }
3199
3200         return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3201                                   rule_type, rule_id, count, mr_list,
3202                                   cmd_details, NULL, rules_used, rules_free);
3203 }
3204
3205 /**
3206  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3207  * @hw: pointer to the hw struct
3208  * @seid: VSI for the vlan filters
3209  * @v_list: list of vlan filters to be added
3210  * @count: length of the list
3211  * @cmd_details: pointer to command details structure or NULL
3212  **/
3213 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3214                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3215                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3216 {
3217         struct i40e_aq_desc desc;
3218         struct i40e_aqc_macvlan *cmd =
3219                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3220         enum i40e_status_code status;
3221         u16 buf_size;
3222
3223         if (count == 0 || !v_list || !hw)
3224                 return I40E_ERR_PARAM;
3225
3226         buf_size = count * sizeof(*v_list);
3227
3228         /* prep the rest of the request */
3229         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3230         cmd->num_addresses = CPU_TO_LE16(count);
3231         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3232         cmd->seid[1] = 0;
3233         cmd->seid[2] = 0;
3234
3235         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3236         if (buf_size > I40E_AQ_LARGE_BUF)
3237                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3238
3239         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3240                                        cmd_details);
3241
3242         return status;
3243 }
3244
3245 /**
3246  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3247  * @hw: pointer to the hw struct
3248  * @seid: VSI for the vlan filters
3249  * @v_list: list of macvlans to be removed
3250  * @count: length of the list
3251  * @cmd_details: pointer to command details structure or NULL
3252  **/
3253 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3254                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3255                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3256 {
3257         struct i40e_aq_desc desc;
3258         struct i40e_aqc_macvlan *cmd =
3259                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3260         enum i40e_status_code status;
3261         u16 buf_size;
3262
3263         if (count == 0 || !v_list || !hw)
3264                 return I40E_ERR_PARAM;
3265
3266         buf_size = count * sizeof(*v_list);
3267
3268         /* prep the rest of the request */
3269         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3270         cmd->num_addresses = CPU_TO_LE16(count);
3271         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3272         cmd->seid[1] = 0;
3273         cmd->seid[2] = 0;
3274
3275         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3276         if (buf_size > I40E_AQ_LARGE_BUF)
3277                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3278
3279         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3280                                        cmd_details);
3281
3282         return status;
3283 }
3284
3285 /**
3286  * i40e_aq_send_msg_to_vf
3287  * @hw: pointer to the hardware structure
3288  * @vfid: vf id to send msg
3289  * @v_opcode: opcodes for VF-PF communication
3290  * @v_retval: return error code
3291  * @msg: pointer to the msg buffer
3292  * @msglen: msg length
3293  * @cmd_details: pointer to command details
3294  *
3295  * send msg to vf
3296  **/
3297 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3298                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3299                                 struct i40e_asq_cmd_details *cmd_details)
3300 {
3301         struct i40e_aq_desc desc;
3302         struct i40e_aqc_pf_vf_message *cmd =
3303                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3304         enum i40e_status_code status;
3305
3306         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3307         cmd->id = CPU_TO_LE32(vfid);
3308         desc.cookie_high = CPU_TO_LE32(v_opcode);
3309         desc.cookie_low = CPU_TO_LE32(v_retval);
3310         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3311         if (msglen) {
3312                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3313                                                 I40E_AQ_FLAG_RD));
3314                 if (msglen > I40E_AQ_LARGE_BUF)
3315                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3316                 desc.datalen = CPU_TO_LE16(msglen);
3317         }
3318         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3319
3320         return status;
3321 }
3322
3323 /**
3324  * i40e_aq_debug_read_register
3325  * @hw: pointer to the hw struct
3326  * @reg_addr: register address
3327  * @reg_val: register value
3328  * @cmd_details: pointer to command details structure or NULL
3329  *
3330  * Read the register using the admin queue commands
3331  **/
3332 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3333                                 u32 reg_addr, u64 *reg_val,
3334                                 struct i40e_asq_cmd_details *cmd_details)
3335 {
3336         struct i40e_aq_desc desc;
3337         struct i40e_aqc_debug_reg_read_write *cmd_resp =
3338                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3339         enum i40e_status_code status;
3340
3341         if (reg_val == NULL)
3342                 return I40E_ERR_PARAM;
3343
3344         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3345
3346         cmd_resp->address = CPU_TO_LE32(reg_addr);
3347
3348         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3349
3350         if (status == I40E_SUCCESS) {
3351                 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3352                            (u64)LE32_TO_CPU(cmd_resp->value_low);
3353         }
3354
3355         return status;
3356 }
3357
3358 /**
3359  * i40e_aq_debug_write_register
3360  * @hw: pointer to the hw struct
3361  * @reg_addr: register address
3362  * @reg_val: register value
3363  * @cmd_details: pointer to command details structure or NULL
3364  *
3365  * Write to a register using the admin queue commands
3366  **/
3367 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3368                                 u32 reg_addr, u64 reg_val,
3369                                 struct i40e_asq_cmd_details *cmd_details)
3370 {
3371         struct i40e_aq_desc desc;
3372         struct i40e_aqc_debug_reg_read_write *cmd =
3373                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3374         enum i40e_status_code status;
3375
3376         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3377
3378         cmd->address = CPU_TO_LE32(reg_addr);
3379         cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3380         cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3381
3382         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3383
3384         return status;
3385 }
3386
3387 /**
3388  * i40e_aq_request_resource
3389  * @hw: pointer to the hw struct
3390  * @resource: resource id
3391  * @access: access type
3392  * @sdp_number: resource number
3393  * @timeout: the maximum time in ms that the driver may hold the resource
3394  * @cmd_details: pointer to command details structure or NULL
3395  *
3396  * requests common resource using the admin queue commands
3397  **/
3398 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3399                                 enum i40e_aq_resources_ids resource,
3400                                 enum i40e_aq_resource_access_type access,
3401                                 u8 sdp_number, u64 *timeout,
3402                                 struct i40e_asq_cmd_details *cmd_details)
3403 {
3404         struct i40e_aq_desc desc;
3405         struct i40e_aqc_request_resource *cmd_resp =
3406                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3407         enum i40e_status_code status;
3408
3409         DEBUGFUNC("i40e_aq_request_resource");
3410
3411         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3412
3413         cmd_resp->resource_id = CPU_TO_LE16(resource);
3414         cmd_resp->access_type = CPU_TO_LE16(access);
3415         cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3416
3417         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3418         /* The completion specifies the maximum time in ms that the driver
3419          * may hold the resource in the Timeout field.
3420          * If the resource is held by someone else, the command completes with
3421          * busy return value and the timeout field indicates the maximum time
3422          * the current owner of the resource has to free it.
3423          */
3424         if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3425                 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3426
3427         return status;
3428 }
3429
3430 /**
3431  * i40e_aq_release_resource
3432  * @hw: pointer to the hw struct
3433  * @resource: resource id
3434  * @sdp_number: resource number
3435  * @cmd_details: pointer to command details structure or NULL
3436  *
3437  * release common resource using the admin queue commands
3438  **/
3439 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3440                                 enum i40e_aq_resources_ids resource,
3441                                 u8 sdp_number,
3442                                 struct i40e_asq_cmd_details *cmd_details)
3443 {
3444         struct i40e_aq_desc desc;
3445         struct i40e_aqc_request_resource *cmd =
3446                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3447         enum i40e_status_code status;
3448
3449         DEBUGFUNC("i40e_aq_release_resource");
3450
3451         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3452
3453         cmd->resource_id = CPU_TO_LE16(resource);
3454         cmd->resource_number = CPU_TO_LE32(sdp_number);
3455
3456         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3457
3458         return status;
3459 }
3460
3461 /**
3462  * i40e_aq_read_nvm
3463  * @hw: pointer to the hw struct
3464  * @module_pointer: module pointer location in words from the NVM beginning
3465  * @offset: byte offset from the module beginning
3466  * @length: length of the section to be read (in bytes from the offset)
3467  * @data: command buffer (size [bytes] = length)
3468  * @last_command: tells if this is the last command in a series
3469  * @cmd_details: pointer to command details structure or NULL
3470  *
3471  * Read the NVM using the admin queue commands
3472  **/
3473 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3474                                 u32 offset, u16 length, void *data,
3475                                 bool last_command,
3476                                 struct i40e_asq_cmd_details *cmd_details)
3477 {
3478         struct i40e_aq_desc desc;
3479         struct i40e_aqc_nvm_update *cmd =
3480                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3481         enum i40e_status_code status;
3482
3483         DEBUGFUNC("i40e_aq_read_nvm");
3484
3485         /* In offset the highest byte must be zeroed. */
3486         if (offset & 0xFF000000) {
3487                 status = I40E_ERR_PARAM;
3488                 goto i40e_aq_read_nvm_exit;
3489         }
3490
3491         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3492
3493         /* If this is the last command in a series, set the proper flag. */
3494         if (last_command)
3495                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3496         cmd->module_pointer = module_pointer;
3497         cmd->offset = CPU_TO_LE32(offset);
3498         cmd->length = CPU_TO_LE16(length);
3499
3500         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3501         if (length > I40E_AQ_LARGE_BUF)
3502                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3503
3504         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3505
3506 i40e_aq_read_nvm_exit:
3507         return status;
3508 }
3509
3510 /**
3511  * i40e_aq_read_nvm_config - read an nvm config block
3512  * @hw: pointer to the hw struct
3513  * @cmd_flags: NVM access admin command bits
3514  * @field_id: field or feature id
3515  * @data: buffer for result
3516  * @buf_size: buffer size
3517  * @element_count: pointer to count of elements read by FW
3518  * @cmd_details: pointer to command details structure or NULL
3519  **/
3520 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3521                                 u8 cmd_flags, u32 field_id, void *data,
3522                                 u16 buf_size, u16 *element_count,
3523                                 struct i40e_asq_cmd_details *cmd_details)
3524 {
3525         struct i40e_aq_desc desc;
3526         struct i40e_aqc_nvm_config_read *cmd =
3527                 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3528         enum i40e_status_code status;
3529
3530         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3531         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3532         if (buf_size > I40E_AQ_LARGE_BUF)
3533                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3534
3535         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3536         cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3537         if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3538                 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3539         else
3540                 cmd->element_id_msw = 0;
3541
3542         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3543
3544         if (!status && element_count)
3545                 *element_count = LE16_TO_CPU(cmd->element_count);
3546
3547         return status;
3548 }
3549
3550 /**
3551  * i40e_aq_write_nvm_config - write an nvm config block
3552  * @hw: pointer to the hw struct
3553  * @cmd_flags: NVM access admin command bits
3554  * @data: buffer for result
3555  * @buf_size: buffer size
3556  * @element_count: count of elements to be written
3557  * @cmd_details: pointer to command details structure or NULL
3558  **/
3559 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3560                                 u8 cmd_flags, void *data, u16 buf_size,
3561                                 u16 element_count,
3562                                 struct i40e_asq_cmd_details *cmd_details)
3563 {
3564         struct i40e_aq_desc desc;
3565         struct i40e_aqc_nvm_config_write *cmd =
3566                 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3567         enum i40e_status_code status;
3568
3569         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3570         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3571         if (buf_size > I40E_AQ_LARGE_BUF)
3572                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3573
3574         cmd->element_count = CPU_TO_LE16(element_count);
3575         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3576         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3577
3578         return status;
3579 }
3580
3581 /**
3582  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3583  * @hw: pointer to the hw struct
3584  * @cmd_details: pointer to command details structure or NULL
3585  **/
3586 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3587                                 void *buff, u16 buff_size,
3588                                 struct i40e_asq_cmd_details *cmd_details)
3589 {
3590         struct i40e_aq_desc desc;
3591         enum i40e_status_code status;
3592
3593         UNREFERENCED_2PARAMETER(buff, buff_size);
3594
3595         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3596         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3597         if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3598                 status = I40E_ERR_NOT_IMPLEMENTED;
3599
3600         return status;
3601 }
3602
3603 /**
3604  * i40e_aq_erase_nvm
3605  * @hw: pointer to the hw struct
3606  * @module_pointer: module pointer location in words from the NVM beginning
3607  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3608  * @length: length of the section to be erased (expressed in 4 KB)
3609  * @last_command: tells if this is the last command in a series
3610  * @cmd_details: pointer to command details structure or NULL
3611  *
3612  * Erase the NVM sector using the admin queue commands
3613  **/
3614 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3615                                 u32 offset, u16 length, bool last_command,
3616                                 struct i40e_asq_cmd_details *cmd_details)
3617 {
3618         struct i40e_aq_desc desc;
3619         struct i40e_aqc_nvm_update *cmd =
3620                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3621         enum i40e_status_code status;
3622
3623         DEBUGFUNC("i40e_aq_erase_nvm");
3624
3625         /* In offset the highest byte must be zeroed. */
3626         if (offset & 0xFF000000) {
3627                 status = I40E_ERR_PARAM;
3628                 goto i40e_aq_erase_nvm_exit;
3629         }
3630
3631         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3632
3633         /* If this is the last command in a series, set the proper flag. */
3634         if (last_command)
3635                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3636         cmd->module_pointer = module_pointer;
3637         cmd->offset = CPU_TO_LE32(offset);
3638         cmd->length = CPU_TO_LE16(length);
3639
3640         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3641
3642 i40e_aq_erase_nvm_exit:
3643         return status;
3644 }
3645
3646 /**
3647  * i40e_parse_discover_capabilities
3648  * @hw: pointer to the hw struct
3649  * @buff: pointer to a buffer containing device/function capability records
3650  * @cap_count: number of capability records in the list
3651  * @list_type_opc: type of capabilities list to parse
3652  *
3653  * Parse the device/function capabilities list.
3654  **/
3655 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3656                                      u32 cap_count,
3657                                      enum i40e_admin_queue_opc list_type_opc)
3658 {
3659         struct i40e_aqc_list_capabilities_element_resp *cap;
3660         u32 valid_functions, num_functions;
3661         u32 number, logical_id, phys_id;
3662         struct i40e_hw_capabilities *p;
3663         u8 major_rev;
3664         u32 i = 0;
3665         u16 id;
3666
3667         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3668
3669         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3670                 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3671         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3672                 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3673         else
3674                 return;
3675
3676         for (i = 0; i < cap_count; i++, cap++) {
3677                 id = LE16_TO_CPU(cap->id);
3678                 number = LE32_TO_CPU(cap->number);
3679                 logical_id = LE32_TO_CPU(cap->logical_id);
3680                 phys_id = LE32_TO_CPU(cap->phys_id);
3681                 major_rev = cap->major_rev;
3682
3683                 switch (id) {
3684                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3685                         p->switch_mode = number;
3686                         i40e_debug(hw, I40E_DEBUG_INIT,
3687                                    "HW Capability: Switch mode = %d\n",
3688                                    p->switch_mode);
3689                         break;
3690                 case I40E_AQ_CAP_ID_MNG_MODE:
3691                         p->management_mode = number;
3692                         if (major_rev > 1) {
3693                                 p->mng_protocols_over_mctp = logical_id;
3694                                 i40e_debug(hw, I40E_DEBUG_INIT,
3695                                            "HW Capability: Protocols over MCTP = %d\n",
3696                                            p->mng_protocols_over_mctp);
3697                         } else {
3698                                 p->mng_protocols_over_mctp = 0;
3699                         }
3700                         i40e_debug(hw, I40E_DEBUG_INIT,
3701                                    "HW Capability: Management Mode = %d\n",
3702                                    p->management_mode);
3703                         break;
3704                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3705                         p->npar_enable = number;
3706                         i40e_debug(hw, I40E_DEBUG_INIT,
3707                                    "HW Capability: NPAR enable = %d\n",
3708                                    p->npar_enable);
3709                         break;
3710                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3711                         p->os2bmc = number;
3712                         i40e_debug(hw, I40E_DEBUG_INIT,
3713                                    "HW Capability: OS2BMC = %d\n", p->os2bmc);
3714                         break;
3715                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3716                         p->valid_functions = number;
3717                         i40e_debug(hw, I40E_DEBUG_INIT,
3718                                    "HW Capability: Valid Functions = %d\n",
3719                                    p->valid_functions);
3720                         break;
3721                 case I40E_AQ_CAP_ID_SRIOV:
3722                         if (number == 1)
3723                                 p->sr_iov_1_1 = true;
3724                         i40e_debug(hw, I40E_DEBUG_INIT,
3725                                    "HW Capability: SR-IOV = %d\n",
3726                                    p->sr_iov_1_1);
3727                         break;
3728                 case I40E_AQ_CAP_ID_VF:
3729                         p->num_vfs = number;
3730                         p->vf_base_id = logical_id;
3731                         i40e_debug(hw, I40E_DEBUG_INIT,
3732                                    "HW Capability: VF count = %d\n",
3733                                    p->num_vfs);
3734                         i40e_debug(hw, I40E_DEBUG_INIT,
3735                                    "HW Capability: VF base_id = %d\n",
3736                                    p->vf_base_id);
3737                         break;
3738                 case I40E_AQ_CAP_ID_VMDQ:
3739                         if (number == 1)
3740                                 p->vmdq = true;
3741                         i40e_debug(hw, I40E_DEBUG_INIT,
3742                                    "HW Capability: VMDQ = %d\n", p->vmdq);
3743                         break;
3744                 case I40E_AQ_CAP_ID_8021QBG:
3745                         if (number == 1)
3746                                 p->evb_802_1_qbg = true;
3747                         i40e_debug(hw, I40E_DEBUG_INIT,
3748                                    "HW Capability: 802.1Qbg = %d\n", number);
3749                         break;
3750                 case I40E_AQ_CAP_ID_8021QBR:
3751                         if (number == 1)
3752                                 p->evb_802_1_qbh = true;
3753                         i40e_debug(hw, I40E_DEBUG_INIT,
3754                                    "HW Capability: 802.1Qbh = %d\n", number);
3755                         break;
3756                 case I40E_AQ_CAP_ID_VSI:
3757                         p->num_vsis = number;
3758                         i40e_debug(hw, I40E_DEBUG_INIT,
3759                                    "HW Capability: VSI count = %d\n",
3760                                    p->num_vsis);
3761                         break;
3762                 case I40E_AQ_CAP_ID_DCB:
3763                         if (number == 1) {
3764                                 p->dcb = true;
3765                                 p->enabled_tcmap = logical_id;
3766                                 p->maxtc = phys_id;
3767                         }
3768                         i40e_debug(hw, I40E_DEBUG_INIT,
3769                                    "HW Capability: DCB = %d\n", p->dcb);
3770                         i40e_debug(hw, I40E_DEBUG_INIT,
3771                                    "HW Capability: TC Mapping = %d\n",
3772                                    logical_id);
3773                         i40e_debug(hw, I40E_DEBUG_INIT,
3774                                    "HW Capability: TC Max = %d\n", p->maxtc);
3775                         break;
3776                 case I40E_AQ_CAP_ID_FCOE:
3777                         if (number == 1)
3778                                 p->fcoe = true;
3779                         i40e_debug(hw, I40E_DEBUG_INIT,
3780                                    "HW Capability: FCOE = %d\n", p->fcoe);
3781                         break;
3782                 case I40E_AQ_CAP_ID_ISCSI:
3783                         if (number == 1)
3784                                 p->iscsi = true;
3785                         i40e_debug(hw, I40E_DEBUG_INIT,
3786                                    "HW Capability: iSCSI = %d\n", p->iscsi);
3787                         break;
3788                 case I40E_AQ_CAP_ID_RSS:
3789                         p->rss = true;
3790                         p->rss_table_size = number;
3791                         p->rss_table_entry_width = logical_id;
3792                         i40e_debug(hw, I40E_DEBUG_INIT,
3793                                    "HW Capability: RSS = %d\n", p->rss);
3794                         i40e_debug(hw, I40E_DEBUG_INIT,
3795                                    "HW Capability: RSS table size = %d\n",
3796                                    p->rss_table_size);
3797                         i40e_debug(hw, I40E_DEBUG_INIT,
3798                                    "HW Capability: RSS table width = %d\n",
3799                                    p->rss_table_entry_width);
3800                         break;
3801                 case I40E_AQ_CAP_ID_RXQ:
3802                         p->num_rx_qp = number;
3803                         p->base_queue = phys_id;
3804                         i40e_debug(hw, I40E_DEBUG_INIT,
3805                                    "HW Capability: Rx QP = %d\n", number);
3806                         i40e_debug(hw, I40E_DEBUG_INIT,
3807                                    "HW Capability: base_queue = %d\n",
3808                                    p->base_queue);
3809                         break;
3810                 case I40E_AQ_CAP_ID_TXQ:
3811                         p->num_tx_qp = number;
3812                         p->base_queue = phys_id;
3813                         i40e_debug(hw, I40E_DEBUG_INIT,
3814                                    "HW Capability: Tx QP = %d\n", number);
3815                         i40e_debug(hw, I40E_DEBUG_INIT,
3816                                    "HW Capability: base_queue = %d\n",
3817                                    p->base_queue);
3818                         break;
3819                 case I40E_AQ_CAP_ID_MSIX:
3820                         p->num_msix_vectors = number;
3821                         i40e_debug(hw, I40E_DEBUG_INIT,
3822                                    "HW Capability: MSIX vector count = %d\n",
3823                                    p->num_msix_vectors);
3824                         break;
3825                 case I40E_AQ_CAP_ID_VF_MSIX:
3826                         p->num_msix_vectors_vf = number;
3827                         i40e_debug(hw, I40E_DEBUG_INIT,
3828                                    "HW Capability: MSIX VF vector count = %d\n",
3829                                    p->num_msix_vectors_vf);
3830                         break;
3831                 case I40E_AQ_CAP_ID_FLEX10:
3832                         if (major_rev == 1) {
3833                                 if (number == 1) {
3834                                         p->flex10_enable = true;
3835                                         p->flex10_capable = true;
3836                                 }
3837                         } else {
3838                                 /* Capability revision >= 2 */
3839                                 if (number & 1)
3840                                         p->flex10_enable = true;
3841                                 if (number & 2)
3842                                         p->flex10_capable = true;
3843                         }
3844                         p->flex10_mode = logical_id;
3845                         p->flex10_status = phys_id;
3846                         i40e_debug(hw, I40E_DEBUG_INIT,
3847                                    "HW Capability: Flex10 mode = %d\n",
3848                                    p->flex10_mode);
3849                         i40e_debug(hw, I40E_DEBUG_INIT,
3850                                    "HW Capability: Flex10 status = %d\n",
3851                                    p->flex10_status);
3852                         break;
3853                 case I40E_AQ_CAP_ID_CEM:
3854                         if (number == 1)
3855                                 p->mgmt_cem = true;
3856                         i40e_debug(hw, I40E_DEBUG_INIT,
3857                                    "HW Capability: CEM = %d\n", p->mgmt_cem);
3858                         break;
3859                 case I40E_AQ_CAP_ID_IWARP:
3860                         if (number == 1)
3861                                 p->iwarp = true;
3862                         i40e_debug(hw, I40E_DEBUG_INIT,
3863                                    "HW Capability: iWARP = %d\n", p->iwarp);
3864                         break;
3865                 case I40E_AQ_CAP_ID_LED:
3866                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3867                                 p->led[phys_id] = true;
3868                         i40e_debug(hw, I40E_DEBUG_INIT,
3869                                    "HW Capability: LED - PIN %d\n", phys_id);
3870                         break;
3871                 case I40E_AQ_CAP_ID_SDP:
3872                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3873                                 p->sdp[phys_id] = true;
3874                         i40e_debug(hw, I40E_DEBUG_INIT,
3875                                    "HW Capability: SDP - PIN %d\n", phys_id);
3876                         break;
3877                 case I40E_AQ_CAP_ID_MDIO:
3878                         if (number == 1) {
3879                                 p->mdio_port_num = phys_id;
3880                                 p->mdio_port_mode = logical_id;
3881                         }
3882                         i40e_debug(hw, I40E_DEBUG_INIT,
3883                                    "HW Capability: MDIO port number = %d\n",
3884                                    p->mdio_port_num);
3885                         i40e_debug(hw, I40E_DEBUG_INIT,
3886                                    "HW Capability: MDIO port mode = %d\n",
3887                                    p->mdio_port_mode);
3888                         break;
3889                 case I40E_AQ_CAP_ID_1588:
3890                         if (number == 1)
3891                                 p->ieee_1588 = true;
3892                         i40e_debug(hw, I40E_DEBUG_INIT,
3893                                    "HW Capability: IEEE 1588 = %d\n",
3894                                    p->ieee_1588);
3895                         break;
3896                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3897                         p->fd = true;
3898                         p->fd_filters_guaranteed = number;
3899                         p->fd_filters_best_effort = logical_id;
3900                         i40e_debug(hw, I40E_DEBUG_INIT,
3901                                    "HW Capability: Flow Director = 1\n");
3902                         i40e_debug(hw, I40E_DEBUG_INIT,
3903                                    "HW Capability: Guaranteed FD filters = %d\n",
3904                                    p->fd_filters_guaranteed);
3905                         break;
3906                 case I40E_AQ_CAP_ID_WSR_PROT:
3907                         p->wr_csr_prot = (u64)number;
3908                         p->wr_csr_prot |= (u64)logical_id << 32;
3909                         i40e_debug(hw, I40E_DEBUG_INIT,
3910                                    "HW Capability: wr_csr_prot = 0x%llX\n\n",
3911                                    (p->wr_csr_prot & 0xffff));
3912                         break;
3913                 case I40E_AQ_CAP_ID_NVM_MGMT:
3914                         if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3915                                 p->sec_rev_disabled = true;
3916                         if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3917                                 p->update_disabled = true;
3918                         break;
3919 #ifdef X722_SUPPORT
3920                 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3921                         hw->num_wol_proxy_filters = (u16)number;
3922                         hw->wol_proxy_vsi_seid = (u16)logical_id;
3923                         p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3924                         if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3925                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3926                         else
3927                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3928                         p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3929                         i40e_debug(hw, I40E_DEBUG_INIT,
3930                                    "HW Capability: WOL proxy filters = %d\n",
3931                                    hw->num_wol_proxy_filters);
3932                         break;
3933 #endif
3934                 default:
3935                         break;
3936                 }
3937         }
3938
3939         if (p->fcoe)
3940                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3941
3942         /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3943         p->fcoe = false;
3944
3945         /* count the enabled ports (aka the "not disabled" ports) */
3946         hw->num_ports = 0;
3947         for (i = 0; i < 4; i++) {
3948                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3949                 u64 port_cfg = 0;
3950
3951                 /* use AQ read to get the physical register offset instead
3952                  * of the port relative offset
3953                  */
3954                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3955                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3956                         hw->num_ports++;
3957         }
3958
3959         valid_functions = p->valid_functions;
3960         num_functions = 0;
3961         while (valid_functions) {
3962                 if (valid_functions & 1)
3963                         num_functions++;
3964                 valid_functions >>= 1;
3965         }
3966
3967         /* partition id is 1-based, and functions are evenly spread
3968          * across the ports as partitions
3969          */
3970         hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3971         hw->num_partitions = num_functions / hw->num_ports;
3972
3973         /* additional HW specific goodies that might
3974          * someday be HW version specific
3975          */
3976         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3977 }
3978
3979 /**
3980  * i40e_aq_discover_capabilities
3981  * @hw: pointer to the hw struct
3982  * @buff: a virtual buffer to hold the capabilities
3983  * @buff_size: Size of the virtual buffer
3984  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3985  * @list_type_opc: capabilities type to discover - pass in the command opcode
3986  * @cmd_details: pointer to command details structure or NULL
3987  *
3988  * Get the device capabilities descriptions from the firmware
3989  **/
3990 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3991                                 void *buff, u16 buff_size, u16 *data_size,
3992                                 enum i40e_admin_queue_opc list_type_opc,
3993                                 struct i40e_asq_cmd_details *cmd_details)
3994 {
3995         struct i40e_aqc_list_capabilites *cmd;
3996         struct i40e_aq_desc desc;
3997         enum i40e_status_code status = I40E_SUCCESS;
3998
3999         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
4000
4001         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
4002                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
4003                 status = I40E_ERR_PARAM;
4004                 goto exit;
4005         }
4006
4007         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
4008
4009         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4010         if (buff_size > I40E_AQ_LARGE_BUF)
4011                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4012
4013         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4014         *data_size = LE16_TO_CPU(desc.datalen);
4015
4016         if (status)
4017                 goto exit;
4018
4019         i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
4020                                          list_type_opc);
4021
4022 exit:
4023         return status;
4024 }
4025
4026 /**
4027  * i40e_aq_update_nvm
4028  * @hw: pointer to the hw struct
4029  * @module_pointer: module pointer location in words from the NVM beginning
4030  * @offset: byte offset from the module beginning
4031  * @length: length of the section to be written (in bytes from the offset)
4032  * @data: command buffer (size [bytes] = length)
4033  * @last_command: tells if this is the last command in a series
4034  * @cmd_details: pointer to command details structure or NULL
4035  *
4036  * Update the NVM using the admin queue commands
4037  **/
4038 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
4039                                 u32 offset, u16 length, void *data,
4040                                 bool last_command,
4041                                 struct i40e_asq_cmd_details *cmd_details)
4042 {
4043         struct i40e_aq_desc desc;
4044         struct i40e_aqc_nvm_update *cmd =
4045                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
4046         enum i40e_status_code status;
4047
4048         DEBUGFUNC("i40e_aq_update_nvm");
4049
4050         /* In offset the highest byte must be zeroed. */
4051         if (offset & 0xFF000000) {
4052                 status = I40E_ERR_PARAM;
4053                 goto i40e_aq_update_nvm_exit;
4054         }
4055
4056         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4057
4058         /* If this is the last command in a series, set the proper flag. */
4059         if (last_command)
4060                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
4061         cmd->module_pointer = module_pointer;
4062         cmd->offset = CPU_TO_LE32(offset);
4063         cmd->length = CPU_TO_LE16(length);
4064
4065         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4066         if (length > I40E_AQ_LARGE_BUF)
4067                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4068
4069         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
4070
4071 i40e_aq_update_nvm_exit:
4072         return status;
4073 }
4074
4075 /**
4076  * i40e_aq_get_lldp_mib
4077  * @hw: pointer to the hw struct
4078  * @bridge_type: type of bridge requested
4079  * @mib_type: Local, Remote or both Local and Remote MIBs
4080  * @buff: pointer to a user supplied buffer to store the MIB block
4081  * @buff_size: size of the buffer (in bytes)
4082  * @local_len : length of the returned Local LLDP MIB
4083  * @remote_len: length of the returned Remote LLDP MIB
4084  * @cmd_details: pointer to command details structure or NULL
4085  *
4086  * Requests the complete LLDP MIB (entire packet).
4087  **/
4088 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4089                                 u8 mib_type, void *buff, u16 buff_size,
4090                                 u16 *local_len, u16 *remote_len,
4091                                 struct i40e_asq_cmd_details *cmd_details)
4092 {
4093         struct i40e_aq_desc desc;
4094         struct i40e_aqc_lldp_get_mib *cmd =
4095                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4096         struct i40e_aqc_lldp_get_mib *resp =
4097                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4098         enum i40e_status_code status;
4099
4100         if (buff_size == 0 || !buff)
4101                 return I40E_ERR_PARAM;
4102
4103         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4104         /* Indirect Command */
4105         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4106
4107         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4108         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4109                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4110
4111         desc.datalen = CPU_TO_LE16(buff_size);
4112
4113         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4114         if (buff_size > I40E_AQ_LARGE_BUF)
4115                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4116
4117         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4118         if (!status) {
4119                 if (local_len != NULL)
4120                         *local_len = LE16_TO_CPU(resp->local_len);
4121                 if (remote_len != NULL)
4122                         *remote_len = LE16_TO_CPU(resp->remote_len);
4123         }
4124
4125         return status;
4126 }
4127
4128  /**
4129  * i40e_aq_set_lldp_mib - Set the LLDP MIB
4130  * @hw: pointer to the hw struct
4131  * @mib_type: Local, Remote or both Local and Remote MIBs
4132  * @buff: pointer to a user supplied buffer to store the MIB block
4133  * @buff_size: size of the buffer (in bytes)
4134  * @cmd_details: pointer to command details structure or NULL
4135  *
4136  * Set the LLDP MIB.
4137  **/
4138 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4139                                 u8 mib_type, void *buff, u16 buff_size,
4140                                 struct i40e_asq_cmd_details *cmd_details)
4141 {
4142         struct i40e_aq_desc desc;
4143         struct i40e_aqc_lldp_set_local_mib *cmd =
4144                 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4145         enum i40e_status_code status;
4146
4147         if (buff_size == 0 || !buff)
4148                 return I40E_ERR_PARAM;
4149
4150         i40e_fill_default_direct_cmd_desc(&desc,
4151                                 i40e_aqc_opc_lldp_set_local_mib);
4152         /* Indirect Command */
4153         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4154         if (buff_size > I40E_AQ_LARGE_BUF)
4155                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4156         desc.datalen = CPU_TO_LE16(buff_size);
4157
4158         cmd->type = mib_type;
4159         cmd->length = CPU_TO_LE16(buff_size);
4160         cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4161         cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4162
4163         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4164         return status;
4165 }
4166
4167 /**
4168  * i40e_aq_cfg_lldp_mib_change_event
4169  * @hw: pointer to the hw struct
4170  * @enable_update: Enable or Disable event posting
4171  * @cmd_details: pointer to command details structure or NULL
4172  *
4173  * Enable or Disable posting of an event on ARQ when LLDP MIB
4174  * associated with the interface changes
4175  **/
4176 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4177                                 bool enable_update,
4178                                 struct i40e_asq_cmd_details *cmd_details)
4179 {
4180         struct i40e_aq_desc desc;
4181         struct i40e_aqc_lldp_update_mib *cmd =
4182                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4183         enum i40e_status_code status;
4184
4185         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4186
4187         if (!enable_update)
4188                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4189
4190         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4191
4192         return status;
4193 }
4194
4195 /**
4196  * i40e_aq_add_lldp_tlv
4197  * @hw: pointer to the hw struct
4198  * @bridge_type: type of bridge
4199  * @buff: buffer with TLV to add
4200  * @buff_size: length of the buffer
4201  * @tlv_len: length of the TLV to be added
4202  * @mib_len: length of the LLDP MIB returned in response
4203  * @cmd_details: pointer to command details structure or NULL
4204  *
4205  * Add the specified TLV to LLDP Local MIB for the given bridge type,
4206  * it is responsibility of the caller to make sure that the TLV is not
4207  * already present in the LLDPDU.
4208  * In return firmware will write the complete LLDP MIB with the newly
4209  * added TLV in the response buffer.
4210  **/
4211 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4212                                 void *buff, u16 buff_size, u16 tlv_len,
4213                                 u16 *mib_len,
4214                                 struct i40e_asq_cmd_details *cmd_details)
4215 {
4216         struct i40e_aq_desc desc;
4217         struct i40e_aqc_lldp_add_tlv *cmd =
4218                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4219         enum i40e_status_code status;
4220
4221         if (buff_size == 0 || !buff || tlv_len == 0)
4222                 return I40E_ERR_PARAM;
4223
4224         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4225
4226         /* Indirect Command */
4227         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4228         if (buff_size > I40E_AQ_LARGE_BUF)
4229                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4230         desc.datalen = CPU_TO_LE16(buff_size);
4231
4232         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4233                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4234         cmd->len = CPU_TO_LE16(tlv_len);
4235
4236         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4237         if (!status) {
4238                 if (mib_len != NULL)
4239                         *mib_len = LE16_TO_CPU(desc.datalen);
4240         }
4241
4242         return status;
4243 }
4244
4245 /**
4246  * i40e_aq_update_lldp_tlv
4247  * @hw: pointer to the hw struct
4248  * @bridge_type: type of bridge
4249  * @buff: buffer with TLV to update
4250  * @buff_size: size of the buffer holding original and updated TLVs
4251  * @old_len: Length of the Original TLV
4252  * @new_len: Length of the Updated TLV
4253  * @offset: offset of the updated TLV in the buff
4254  * @mib_len: length of the returned LLDP MIB
4255  * @cmd_details: pointer to command details structure or NULL
4256  *
4257  * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4258  * Firmware will place the complete LLDP MIB in response buffer with the
4259  * updated TLV.
4260  **/
4261 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4262                                 u8 bridge_type, void *buff, u16 buff_size,
4263                                 u16 old_len, u16 new_len, u16 offset,
4264                                 u16 *mib_len,
4265                                 struct i40e_asq_cmd_details *cmd_details)
4266 {
4267         struct i40e_aq_desc desc;
4268         struct i40e_aqc_lldp_update_tlv *cmd =
4269                 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4270         enum i40e_status_code status;
4271
4272         if (buff_size == 0 || !buff || offset == 0 ||
4273             old_len == 0 || new_len == 0)
4274                 return I40E_ERR_PARAM;
4275
4276         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4277
4278         /* Indirect Command */
4279         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4280         if (buff_size > I40E_AQ_LARGE_BUF)
4281                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4282         desc.datalen = CPU_TO_LE16(buff_size);
4283
4284         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4285                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4286         cmd->old_len = CPU_TO_LE16(old_len);
4287         cmd->new_offset = CPU_TO_LE16(offset);
4288         cmd->new_len = CPU_TO_LE16(new_len);
4289
4290         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4291         if (!status) {
4292                 if (mib_len != NULL)
4293                         *mib_len = LE16_TO_CPU(desc.datalen);
4294         }
4295
4296         return status;
4297 }
4298
4299 /**
4300  * i40e_aq_delete_lldp_tlv
4301  * @hw: pointer to the hw struct
4302  * @bridge_type: type of bridge
4303  * @buff: pointer to a user supplied buffer that has the TLV
4304  * @buff_size: length of the buffer
4305  * @tlv_len: length of the TLV to be deleted
4306  * @mib_len: length of the returned LLDP MIB
4307  * @cmd_details: pointer to command details structure or NULL
4308  *
4309  * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4310  * The firmware places the entire LLDP MIB in the response buffer.
4311  **/
4312 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4313                                 u8 bridge_type, void *buff, u16 buff_size,
4314                                 u16 tlv_len, u16 *mib_len,
4315                                 struct i40e_asq_cmd_details *cmd_details)
4316 {
4317         struct i40e_aq_desc desc;
4318         struct i40e_aqc_lldp_add_tlv *cmd =
4319                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4320         enum i40e_status_code status;
4321
4322         if (buff_size == 0 || !buff)
4323                 return I40E_ERR_PARAM;
4324
4325         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4326
4327         /* Indirect Command */
4328         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4329         if (buff_size > I40E_AQ_LARGE_BUF)
4330                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4331         desc.datalen = CPU_TO_LE16(buff_size);
4332         cmd->len = CPU_TO_LE16(tlv_len);
4333         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4334                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4335
4336         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4337         if (!status) {
4338                 if (mib_len != NULL)
4339                         *mib_len = LE16_TO_CPU(desc.datalen);
4340         }
4341
4342         return status;
4343 }
4344
4345 /**
4346  * i40e_aq_stop_lldp
4347  * @hw: pointer to the hw struct
4348  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4349  * @cmd_details: pointer to command details structure or NULL
4350  *
4351  * Stop or Shutdown the embedded LLDP Agent
4352  **/
4353 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4354                                 struct i40e_asq_cmd_details *cmd_details)
4355 {
4356         struct i40e_aq_desc desc;
4357         struct i40e_aqc_lldp_stop *cmd =
4358                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4359         enum i40e_status_code status;
4360
4361         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4362
4363         if (shutdown_agent)
4364                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4365
4366         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4367
4368         return status;
4369 }
4370
4371 /**
4372  * i40e_aq_start_lldp
4373  * @hw: pointer to the hw struct
4374  * @cmd_details: pointer to command details structure or NULL
4375  *
4376  * Start the embedded LLDP Agent on all ports.
4377  **/
4378 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4379                                 struct i40e_asq_cmd_details *cmd_details)
4380 {
4381         struct i40e_aq_desc desc;
4382         struct i40e_aqc_lldp_start *cmd =
4383                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4384         enum i40e_status_code status;
4385
4386         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4387
4388         cmd->command = I40E_AQ_LLDP_AGENT_START;
4389
4390         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4391
4392         return status;
4393 }
4394
4395 /**
4396  * i40e_aq_get_cee_dcb_config
4397  * @hw: pointer to the hw struct
4398  * @buff: response buffer that stores CEE operational configuration
4399  * @buff_size: size of the buffer passed
4400  * @cmd_details: pointer to command details structure or NULL
4401  *
4402  * Get CEE DCBX mode operational configuration from firmware
4403  **/
4404 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4405                                 void *buff, u16 buff_size,
4406                                 struct i40e_asq_cmd_details *cmd_details)
4407 {
4408         struct i40e_aq_desc desc;
4409         enum i40e_status_code status;
4410
4411         if (buff_size == 0 || !buff)
4412                 return I40E_ERR_PARAM;
4413
4414         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4415
4416         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4417         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4418                                        cmd_details);
4419
4420         return status;
4421 }
4422
4423 /**
4424  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4425  * @hw: pointer to the hw struct
4426  * @start_agent: True if DCBx Agent needs to be Started
4427  *                              False if DCBx Agent needs to be Stopped
4428  * @cmd_details: pointer to command details structure or NULL
4429  *
4430  * Start/Stop the embedded dcbx Agent
4431  **/
4432 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4433                                 bool start_agent,
4434                                 struct i40e_asq_cmd_details *cmd_details)
4435 {
4436         struct i40e_aq_desc desc;
4437         struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4438                 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4439                                 &desc.params.raw;
4440         enum i40e_status_code status;
4441
4442         i40e_fill_default_direct_cmd_desc(&desc,
4443                                 i40e_aqc_opc_lldp_stop_start_spec_agent);
4444
4445         if (start_agent)
4446                 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4447
4448         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4449
4450         return status;
4451 }
4452
4453 /**
4454  * i40e_aq_add_udp_tunnel
4455  * @hw: pointer to the hw struct
4456  * @udp_port: the UDP port to add in Host byte order
4457  * @header_len: length of the tunneling header length in DWords
4458  * @protocol_index: protocol index type
4459  * @filter_index: pointer to filter index
4460  * @cmd_details: pointer to command details structure or NULL
4461  *
4462  * Note: Firmware expects the udp_port value to be in Little Endian format,
4463  * and this function will call CPU_TO_LE16 to convert from Host byte order to
4464  * Little Endian order.
4465  **/
4466 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4467                                 u16 udp_port, u8 protocol_index,
4468                                 u8 *filter_index,
4469                                 struct i40e_asq_cmd_details *cmd_details)
4470 {
4471         struct i40e_aq_desc desc;
4472         struct i40e_aqc_add_udp_tunnel *cmd =
4473                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4474         struct i40e_aqc_del_udp_tunnel_completion *resp =
4475                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4476         enum i40e_status_code status;
4477
4478         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4479
4480         cmd->udp_port = CPU_TO_LE16(udp_port);
4481         cmd->protocol_type = protocol_index;
4482
4483         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4484
4485         if (!status && filter_index)
4486                 *filter_index = resp->index;
4487
4488         return status;
4489 }
4490
4491 /**
4492  * i40e_aq_del_udp_tunnel
4493  * @hw: pointer to the hw struct
4494  * @index: filter index
4495  * @cmd_details: pointer to command details structure or NULL
4496  **/
4497 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4498                                 struct i40e_asq_cmd_details *cmd_details)
4499 {
4500         struct i40e_aq_desc desc;
4501         struct i40e_aqc_remove_udp_tunnel *cmd =
4502                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4503         enum i40e_status_code status;
4504
4505         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4506
4507         cmd->index = index;
4508
4509         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4510
4511         return status;
4512 }
4513
4514 /**
4515  * i40e_aq_get_switch_resource_alloc (0x0204)
4516  * @hw: pointer to the hw struct
4517  * @num_entries: pointer to u8 to store the number of resource entries returned
4518  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
4519  *        to store the resource information for all resource types.  Each
4520  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
4521  * @count: size, in bytes, of the buffer provided
4522  * @cmd_details: pointer to command details structure or NULL
4523  *
4524  * Query the resources allocated to a function.
4525  **/
4526 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4527                         u8 *num_entries,
4528                         struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4529                         u16 count,
4530                         struct i40e_asq_cmd_details *cmd_details)
4531 {
4532         struct i40e_aq_desc desc;
4533         struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4534                 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4535         enum i40e_status_code status;
4536         u16 length = count * sizeof(*buf);
4537
4538         i40e_fill_default_direct_cmd_desc(&desc,
4539                                         i40e_aqc_opc_get_switch_resource_alloc);
4540
4541         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4542         if (length > I40E_AQ_LARGE_BUF)
4543                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4544
4545         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4546
4547         if (!status && num_entries)
4548                 *num_entries = cmd_resp->num_entries;
4549
4550         return status;
4551 }
4552
4553 /**
4554  * i40e_aq_delete_element - Delete switch element
4555  * @hw: pointer to the hw struct
4556  * @seid: the SEID to delete from the switch
4557  * @cmd_details: pointer to command details structure or NULL
4558  *
4559  * This deletes a switch element from the switch.
4560  **/
4561 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4562                                 struct i40e_asq_cmd_details *cmd_details)
4563 {
4564         struct i40e_aq_desc desc;
4565         struct i40e_aqc_switch_seid *cmd =
4566                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4567         enum i40e_status_code status;
4568
4569         if (seid == 0)
4570                 return I40E_ERR_PARAM;
4571
4572         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4573
4574         cmd->seid = CPU_TO_LE16(seid);
4575
4576         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4577
4578         return status;
4579 }
4580
4581 /**
4582  * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4583  * @hw: pointer to the hw struct
4584  * @flags: component flags
4585  * @mac_seid: uplink seid (MAC SEID)
4586  * @vsi_seid: connected vsi seid
4587  * @ret_seid: seid of create pv component
4588  *
4589  * This instantiates an i40e port virtualizer with specified flags.
4590  * Depending on specified flags the port virtualizer can act as a
4591  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4592  */
4593 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4594                                        u16 mac_seid, u16 vsi_seid,
4595                                        u16 *ret_seid)
4596 {
4597         struct i40e_aq_desc desc;
4598         struct i40e_aqc_add_update_pv *cmd =
4599                 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4600         struct i40e_aqc_add_update_pv_completion *resp =
4601                 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4602         enum i40e_status_code status;
4603
4604         if (vsi_seid == 0)
4605                 return I40E_ERR_PARAM;
4606
4607         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4608         cmd->command_flags = CPU_TO_LE16(flags);
4609         cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4610         cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4611
4612         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4613         if (!status && ret_seid)
4614                 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4615
4616         return status;
4617 }
4618
4619 /**
4620  * i40e_aq_add_tag - Add an S/E-tag
4621  * @hw: pointer to the hw struct
4622  * @direct_to_queue: should s-tag direct flow to a specific queue
4623  * @vsi_seid: VSI SEID to use this tag
4624  * @tag: value of the tag
4625  * @queue_num: queue number, only valid is direct_to_queue is true
4626  * @tags_used: return value, number of tags in use by this PF
4627  * @tags_free: return value, number of unallocated tags
4628  * @cmd_details: pointer to command details structure or NULL
4629  *
4630  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4631  * the number of tags allocated by the PF, and the number of unallocated
4632  * tags available.
4633  **/
4634 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4635                                 u16 vsi_seid, u16 tag, u16 queue_num,
4636                                 u16 *tags_used, u16 *tags_free,
4637                                 struct i40e_asq_cmd_details *cmd_details)
4638 {
4639         struct i40e_aq_desc desc;
4640         struct i40e_aqc_add_tag *cmd =
4641                 (struct i40e_aqc_add_tag *)&desc.params.raw;
4642         struct i40e_aqc_add_remove_tag_completion *resp =
4643                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4644         enum i40e_status_code status;
4645
4646         if (vsi_seid == 0)
4647                 return I40E_ERR_PARAM;
4648
4649         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4650
4651         cmd->seid = CPU_TO_LE16(vsi_seid);
4652         cmd->tag = CPU_TO_LE16(tag);
4653         if (direct_to_queue) {
4654                 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4655                 cmd->queue_number = CPU_TO_LE16(queue_num);
4656         }
4657
4658         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4659
4660         if (!status) {
4661                 if (tags_used != NULL)
4662                         *tags_used = LE16_TO_CPU(resp->tags_used);
4663                 if (tags_free != NULL)
4664                         *tags_free = LE16_TO_CPU(resp->tags_free);
4665         }
4666
4667         return status;
4668 }
4669
4670 /**
4671  * i40e_aq_remove_tag - Remove an S- or E-tag
4672  * @hw: pointer to the hw struct
4673  * @vsi_seid: VSI SEID this tag is associated with
4674  * @tag: value of the S-tag to delete
4675  * @tags_used: return value, number of tags in use by this PF
4676  * @tags_free: return value, number of unallocated tags
4677  * @cmd_details: pointer to command details structure or NULL
4678  *
4679  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4680  * the number of tags allocated by the PF, and the number of unallocated
4681  * tags available.
4682  **/
4683 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4684                                 u16 tag, u16 *tags_used, u16 *tags_free,
4685                                 struct i40e_asq_cmd_details *cmd_details)
4686 {
4687         struct i40e_aq_desc desc;
4688         struct i40e_aqc_remove_tag *cmd =
4689                 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4690         struct i40e_aqc_add_remove_tag_completion *resp =
4691                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4692         enum i40e_status_code status;
4693
4694         if (vsi_seid == 0)
4695                 return I40E_ERR_PARAM;
4696
4697         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4698
4699         cmd->seid = CPU_TO_LE16(vsi_seid);
4700         cmd->tag = CPU_TO_LE16(tag);
4701
4702         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4703
4704         if (!status) {
4705                 if (tags_used != NULL)
4706                         *tags_used = LE16_TO_CPU(resp->tags_used);
4707                 if (tags_free != NULL)
4708                         *tags_free = LE16_TO_CPU(resp->tags_free);
4709         }
4710
4711         return status;
4712 }
4713
4714 /**
4715  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4716  * @hw: pointer to the hw struct
4717  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4718  * @etag: value of E-tag to add
4719  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4720  * @buf: address of indirect buffer
4721  * @tags_used: return value, number of E-tags in use by this port
4722  * @tags_free: return value, number of unallocated M-tags
4723  * @cmd_details: pointer to command details structure or NULL
4724  *
4725  * This associates a multicast E-tag to a port virtualizer.  It will return
4726  * the number of tags allocated by the PF, and the number of unallocated
4727  * tags available.
4728  *
4729  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4730  * num_tags_in_buf long.
4731  **/
4732 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4733                                 u16 etag, u8 num_tags_in_buf, void *buf,
4734                                 u16 *tags_used, u16 *tags_free,
4735                                 struct i40e_asq_cmd_details *cmd_details)
4736 {
4737         struct i40e_aq_desc desc;
4738         struct i40e_aqc_add_remove_mcast_etag *cmd =
4739                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4740         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4741            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4742         enum i40e_status_code status;
4743         u16 length = sizeof(u16) * num_tags_in_buf;
4744
4745         if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4746                 return I40E_ERR_PARAM;
4747
4748         i40e_fill_default_direct_cmd_desc(&desc,
4749                                           i40e_aqc_opc_add_multicast_etag);
4750
4751         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4752         cmd->etag = CPU_TO_LE16(etag);
4753         cmd->num_unicast_etags = num_tags_in_buf;
4754
4755         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4756         if (length > I40E_AQ_LARGE_BUF)
4757                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4758
4759         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4760
4761         if (!status) {
4762                 if (tags_used != NULL)
4763                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4764                 if (tags_free != NULL)
4765                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4766         }
4767
4768         return status;
4769 }
4770
4771 /**
4772  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4773  * @hw: pointer to the hw struct
4774  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4775  * @etag: value of the E-tag to remove
4776  * @tags_used: return value, number of tags in use by this port
4777  * @tags_free: return value, number of unallocated tags
4778  * @cmd_details: pointer to command details structure or NULL
4779  *
4780  * This deletes an E-tag from the port virtualizer.  It will return
4781  * the number of tags allocated by the port, and the number of unallocated
4782  * tags available.
4783  **/
4784 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4785                                 u16 etag, u16 *tags_used, u16 *tags_free,
4786                                 struct i40e_asq_cmd_details *cmd_details)
4787 {
4788         struct i40e_aq_desc desc;
4789         struct i40e_aqc_add_remove_mcast_etag *cmd =
4790                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4791         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4792            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4793         enum i40e_status_code status;
4794
4795
4796         if (pv_seid == 0)
4797                 return I40E_ERR_PARAM;
4798
4799         i40e_fill_default_direct_cmd_desc(&desc,
4800                                           i40e_aqc_opc_remove_multicast_etag);
4801
4802         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4803         cmd->etag = CPU_TO_LE16(etag);
4804
4805         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4806
4807         if (!status) {
4808                 if (tags_used != NULL)
4809                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4810                 if (tags_free != NULL)
4811                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4812         }
4813
4814         return status;
4815 }
4816
4817 /**
4818  * i40e_aq_update_tag - Update an S/E-tag
4819  * @hw: pointer to the hw struct
4820  * @vsi_seid: VSI SEID using this S-tag
4821  * @old_tag: old tag value
4822  * @new_tag: new tag value
4823  * @tags_used: return value, number of tags in use by this PF
4824  * @tags_free: return value, number of unallocated tags
4825  * @cmd_details: pointer to command details structure or NULL
4826  *
4827  * This updates the value of the tag currently attached to this VSI
4828  * in the switch complex.  It will return the number of tags allocated
4829  * by the PF, and the number of unallocated tags available.
4830  **/
4831 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4832                                 u16 old_tag, u16 new_tag, u16 *tags_used,
4833                                 u16 *tags_free,
4834                                 struct i40e_asq_cmd_details *cmd_details)
4835 {
4836         struct i40e_aq_desc desc;
4837         struct i40e_aqc_update_tag *cmd =
4838                 (struct i40e_aqc_update_tag *)&desc.params.raw;
4839         struct i40e_aqc_update_tag_completion *resp =
4840                 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4841         enum i40e_status_code status;
4842
4843         if (vsi_seid == 0)
4844                 return I40E_ERR_PARAM;
4845
4846         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4847
4848         cmd->seid = CPU_TO_LE16(vsi_seid);
4849         cmd->old_tag = CPU_TO_LE16(old_tag);
4850         cmd->new_tag = CPU_TO_LE16(new_tag);
4851
4852         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4853
4854         if (!status) {
4855                 if (tags_used != NULL)
4856                         *tags_used = LE16_TO_CPU(resp->tags_used);
4857                 if (tags_free != NULL)
4858                         *tags_free = LE16_TO_CPU(resp->tags_free);
4859         }
4860
4861         return status;
4862 }
4863
4864 /**
4865  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4866  * @hw: pointer to the hw struct
4867  * @tcmap: TC map for request/release any ignore PFC condition
4868  * @request: request or release ignore PFC condition
4869  * @tcmap_ret: return TCs for which PFC is currently ignored
4870  * @cmd_details: pointer to command details structure or NULL
4871  *
4872  * This sends out request/release to ignore PFC condition for a TC.
4873  * It will return the TCs for which PFC is currently ignored.
4874  **/
4875 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4876                                 bool request, u8 *tcmap_ret,
4877                                 struct i40e_asq_cmd_details *cmd_details)
4878 {
4879         struct i40e_aq_desc desc;
4880         struct i40e_aqc_pfc_ignore *cmd_resp =
4881                 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4882         enum i40e_status_code status;
4883
4884         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4885
4886         if (request)
4887                 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4888
4889         cmd_resp->tc_bitmap = tcmap;
4890
4891         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4892
4893         if (!status) {
4894                 if (tcmap_ret != NULL)
4895                         *tcmap_ret = cmd_resp->tc_bitmap;
4896         }
4897
4898         return status;
4899 }
4900
4901 /**
4902  * i40e_aq_dcb_updated - DCB Updated Command
4903  * @hw: pointer to the hw struct
4904  * @cmd_details: pointer to command details structure or NULL
4905  *
4906  * When LLDP is handled in PF this command is used by the PF
4907  * to notify EMP that a DCB setting is modified.
4908  * When LLDP is handled in EMP this command is used by the PF
4909  * to notify EMP whenever one of the following parameters get
4910  * modified:
4911  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4912  *   - PCIRTT in PRTDCB_GENC.PCIRTT
4913  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4914  * EMP will return when the shared RPB settings have been
4915  * recomputed and modified. The retval field in the descriptor
4916  * will be set to 0 when RPB is modified.
4917  **/
4918 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4919                                 struct i40e_asq_cmd_details *cmd_details)
4920 {
4921         struct i40e_aq_desc desc;
4922         enum i40e_status_code status;
4923
4924         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4925
4926         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4927
4928         return status;
4929 }
4930
4931 /**
4932  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4933  * @hw: pointer to the hw struct
4934  * @seid: defines the SEID of the switch for which the stats are requested
4935  * @vlan_id: the VLAN ID for which the statistics are requested
4936  * @stat_index: index of the statistics counters block assigned to this VLAN
4937  * @cmd_details: pointer to command details structure or NULL
4938  *
4939  * XL710 supports 128 smonVlanStats counters.This command is used to
4940  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4941  * switch.
4942  **/
4943 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4944                                 u16 vlan_id, u16 *stat_index,
4945                                 struct i40e_asq_cmd_details *cmd_details)
4946 {
4947         struct i40e_aq_desc desc;
4948         struct i40e_aqc_add_remove_statistics *cmd_resp =
4949                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4950         enum i40e_status_code status;
4951
4952         if ((seid == 0) || (stat_index == NULL))
4953                 return I40E_ERR_PARAM;
4954
4955         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4956
4957         cmd_resp->seid = CPU_TO_LE16(seid);
4958         cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4959
4960         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4961
4962         if (!status && stat_index)
4963                 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4964
4965         return status;
4966 }
4967
4968 /**
4969  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4970  * @hw: pointer to the hw struct
4971  * @seid: defines the SEID of the switch for which the stats are requested
4972  * @vlan_id: the VLAN ID for which the statistics are requested
4973  * @stat_index: index of the statistics counters block assigned to this VLAN
4974  * @cmd_details: pointer to command details structure or NULL
4975  *
4976  * XL710 supports 128 smonVlanStats counters.This command is used to
4977  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4978  * switch.
4979  **/
4980 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4981                                 u16 vlan_id, u16 stat_index,
4982                                 struct i40e_asq_cmd_details *cmd_details)
4983 {
4984         struct i40e_aq_desc desc;
4985         struct i40e_aqc_add_remove_statistics *cmd =
4986                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4987         enum i40e_status_code status;
4988
4989         if (seid == 0)
4990                 return I40E_ERR_PARAM;
4991
4992         i40e_fill_default_direct_cmd_desc(&desc,
4993                                           i40e_aqc_opc_remove_statistics);
4994
4995         cmd->seid = CPU_TO_LE16(seid);
4996         cmd->vlan  = CPU_TO_LE16(vlan_id);
4997         cmd->stat_index = CPU_TO_LE16(stat_index);
4998
4999         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5000
5001         return status;
5002 }
5003
5004 /**
5005  * i40e_aq_set_port_parameters - set physical port parameters.
5006  * @hw: pointer to the hw struct
5007  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
5008  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
5009  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
5010  * @double_vlan: if set double VLAN is enabled
5011  * @cmd_details: pointer to command details structure or NULL
5012  **/
5013 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
5014                                 u16 bad_frame_vsi, bool save_bad_pac,
5015                                 bool pad_short_pac, bool double_vlan,
5016                                 struct i40e_asq_cmd_details *cmd_details)
5017 {
5018         struct i40e_aqc_set_port_parameters *cmd;
5019         enum i40e_status_code status;
5020         struct i40e_aq_desc desc;
5021         u16 command_flags = 0;
5022
5023         cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
5024
5025         i40e_fill_default_direct_cmd_desc(&desc,
5026                                           i40e_aqc_opc_set_port_parameters);
5027
5028         cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
5029         if (save_bad_pac)
5030                 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
5031         if (pad_short_pac)
5032                 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
5033         if (double_vlan)
5034                 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
5035         cmd->command_flags = CPU_TO_LE16(command_flags);
5036
5037         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5038
5039         return status;
5040 }
5041
5042 /**
5043  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
5044  * @hw: pointer to the hw struct
5045  * @seid: seid for the physical port/switching component/vsi
5046  * @buff: Indirect buffer to hold data parameters and response
5047  * @buff_size: Indirect buffer size
5048  * @opcode: Tx scheduler AQ command opcode
5049  * @cmd_details: pointer to command details structure or NULL
5050  *
5051  * Generic command handler for Tx scheduler AQ commands
5052  **/
5053 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
5054                                 void *buff, u16 buff_size,
5055                                  enum i40e_admin_queue_opc opcode,
5056                                 struct i40e_asq_cmd_details *cmd_details)
5057 {
5058         struct i40e_aq_desc desc;
5059         struct i40e_aqc_tx_sched_ind *cmd =
5060                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
5061         enum i40e_status_code status;
5062         bool cmd_param_flag = false;
5063
5064         switch (opcode) {
5065         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
5066         case i40e_aqc_opc_configure_vsi_tc_bw:
5067         case i40e_aqc_opc_enable_switching_comp_ets:
5068         case i40e_aqc_opc_modify_switching_comp_ets:
5069         case i40e_aqc_opc_disable_switching_comp_ets:
5070         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
5071         case i40e_aqc_opc_configure_switching_comp_bw_config:
5072                 cmd_param_flag = true;
5073                 break;
5074         case i40e_aqc_opc_query_vsi_bw_config:
5075         case i40e_aqc_opc_query_vsi_ets_sla_config:
5076         case i40e_aqc_opc_query_switching_comp_ets_config:
5077         case i40e_aqc_opc_query_port_ets_config:
5078         case i40e_aqc_opc_query_switching_comp_bw_config:
5079                 cmd_param_flag = false;
5080                 break;
5081         default:
5082                 return I40E_ERR_PARAM;
5083         }
5084
5085         i40e_fill_default_direct_cmd_desc(&desc, opcode);
5086
5087         /* Indirect command */
5088         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5089         if (cmd_param_flag)
5090                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5091         if (buff_size > I40E_AQ_LARGE_BUF)
5092                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5093
5094         desc.datalen = CPU_TO_LE16(buff_size);
5095
5096         cmd->vsi_seid = CPU_TO_LE16(seid);
5097
5098         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5099
5100         return status;
5101 }
5102
5103 /**
5104  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5105  * @hw: pointer to the hw struct
5106  * @seid: VSI seid
5107  * @credit: BW limit credits (0 = disabled)
5108  * @max_credit: Max BW limit credits
5109  * @cmd_details: pointer to command details structure or NULL
5110  **/
5111 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5112                                 u16 seid, u16 credit, u8 max_credit,
5113                                 struct i40e_asq_cmd_details *cmd_details)
5114 {
5115         struct i40e_aq_desc desc;
5116         struct i40e_aqc_configure_vsi_bw_limit *cmd =
5117                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5118         enum i40e_status_code status;
5119
5120         i40e_fill_default_direct_cmd_desc(&desc,
5121                                           i40e_aqc_opc_configure_vsi_bw_limit);
5122
5123         cmd->vsi_seid = CPU_TO_LE16(seid);
5124         cmd->credit = CPU_TO_LE16(credit);
5125         cmd->max_credit = max_credit;
5126
5127         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5128
5129         return status;
5130 }
5131
5132 /**
5133  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5134  * @hw: pointer to the hw struct
5135  * @seid: switching component seid
5136  * @credit: BW limit credits (0 = disabled)
5137  * @max_bw: Max BW limit credits
5138  * @cmd_details: pointer to command details structure or NULL
5139  **/
5140 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5141                                 u16 seid, u16 credit, u8 max_bw,
5142                                 struct i40e_asq_cmd_details *cmd_details)
5143 {
5144         struct i40e_aq_desc desc;
5145         struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5146           (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5147         enum i40e_status_code status;
5148
5149         i40e_fill_default_direct_cmd_desc(&desc,
5150                                 i40e_aqc_opc_configure_switching_comp_bw_limit);
5151
5152         cmd->seid = CPU_TO_LE16(seid);
5153         cmd->credit = CPU_TO_LE16(credit);
5154         cmd->max_bw = max_bw;
5155
5156         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5157
5158         return status;
5159 }
5160
5161 /**
5162  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5163  * @hw: pointer to the hw struct
5164  * @seid: VSI seid
5165  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5166  * @cmd_details: pointer to command details structure or NULL
5167  **/
5168 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5169                         u16 seid,
5170                         struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5171                         struct i40e_asq_cmd_details *cmd_details)
5172 {
5173         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5174                                     i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5175                                     cmd_details);
5176 }
5177
5178 /**
5179  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5180  * @hw: pointer to the hw struct
5181  * @seid: VSI seid
5182  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5183  * @cmd_details: pointer to command details structure or NULL
5184  **/
5185 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5186                         u16 seid,
5187                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5188                         struct i40e_asq_cmd_details *cmd_details)
5189 {
5190         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5191                                     i40e_aqc_opc_configure_vsi_tc_bw,
5192                                     cmd_details);
5193 }
5194
5195 /**
5196  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5197  * @hw: pointer to the hw struct
5198  * @seid: seid of the switching component connected to Physical Port
5199  * @ets_data: Buffer holding ETS parameters
5200  * @cmd_details: pointer to command details structure or NULL
5201  **/
5202 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5203                 u16 seid,
5204                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5205                 enum i40e_admin_queue_opc opcode,
5206                 struct i40e_asq_cmd_details *cmd_details)
5207 {
5208         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5209                                     sizeof(*ets_data), opcode, cmd_details);
5210 }
5211
5212 /**
5213  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5214  * @hw: pointer to the hw struct
5215  * @seid: seid of the switching component
5216  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5217  * @cmd_details: pointer to command details structure or NULL
5218  **/
5219 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5220         u16 seid,
5221         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5222         struct i40e_asq_cmd_details *cmd_details)
5223 {
5224         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5225                             i40e_aqc_opc_configure_switching_comp_bw_config,
5226                             cmd_details);
5227 }
5228
5229 /**
5230  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5231  * @hw: pointer to the hw struct
5232  * @seid: seid of the switching component
5233  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5234  * @cmd_details: pointer to command details structure or NULL
5235  **/
5236 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5237         struct i40e_hw *hw, u16 seid,
5238         struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5239         struct i40e_asq_cmd_details *cmd_details)
5240 {
5241         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5242                             i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5243                             cmd_details);
5244 }
5245
5246 /**
5247  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5248  * @hw: pointer to the hw struct
5249  * @seid: seid of the VSI
5250  * @bw_data: Buffer to hold VSI BW configuration
5251  * @cmd_details: pointer to command details structure or NULL
5252  **/
5253 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5254                         u16 seid,
5255                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5256                         struct i40e_asq_cmd_details *cmd_details)
5257 {
5258         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5259                                     i40e_aqc_opc_query_vsi_bw_config,
5260                                     cmd_details);
5261 }
5262
5263 /**
5264  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5265  * @hw: pointer to the hw struct
5266  * @seid: seid of the VSI
5267  * @bw_data: Buffer to hold VSI BW configuration per TC
5268  * @cmd_details: pointer to command details structure or NULL
5269  **/
5270 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5271                         u16 seid,
5272                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5273                         struct i40e_asq_cmd_details *cmd_details)
5274 {
5275         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5276                                     i40e_aqc_opc_query_vsi_ets_sla_config,
5277                                     cmd_details);
5278 }
5279
5280 /**
5281  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5282  * @hw: pointer to the hw struct
5283  * @seid: seid of the switching component
5284  * @bw_data: Buffer to hold switching component's per TC BW config
5285  * @cmd_details: pointer to command details structure or NULL
5286  **/
5287 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5288                 u16 seid,
5289                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5290                 struct i40e_asq_cmd_details *cmd_details)
5291 {
5292         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5293                                    i40e_aqc_opc_query_switching_comp_ets_config,
5294                                    cmd_details);
5295 }
5296
5297 /**
5298  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5299  * @hw: pointer to the hw struct
5300  * @seid: seid of the VSI or switching component connected to Physical Port
5301  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5302  * @cmd_details: pointer to command details structure or NULL
5303  **/
5304 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5305                         u16 seid,
5306                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
5307                         struct i40e_asq_cmd_details *cmd_details)
5308 {
5309         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5310                                     i40e_aqc_opc_query_port_ets_config,
5311                                     cmd_details);
5312 }
5313
5314 /**
5315  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5316  * @hw: pointer to the hw struct
5317  * @seid: seid of the switching component
5318  * @bw_data: Buffer to hold switching component's BW configuration
5319  * @cmd_details: pointer to command details structure or NULL
5320  **/
5321 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5322                 u16 seid,
5323                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5324                 struct i40e_asq_cmd_details *cmd_details)
5325 {
5326         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5327                                     i40e_aqc_opc_query_switching_comp_bw_config,
5328                                     cmd_details);
5329 }
5330
5331 /**
5332  * i40e_validate_filter_settings
5333  * @hw: pointer to the hardware structure
5334  * @settings: Filter control settings
5335  *
5336  * Check and validate the filter control settings passed.
5337  * The function checks for the valid filter/context sizes being
5338  * passed for FCoE and PE.
5339  *
5340  * Returns I40E_SUCCESS if the values passed are valid and within
5341  * range else returns an error.
5342  **/
5343 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5344                                 struct i40e_filter_control_settings *settings)
5345 {
5346         u32 fcoe_cntx_size, fcoe_filt_size;
5347         u32 pe_cntx_size, pe_filt_size;
5348         u32 fcoe_fmax;
5349
5350         u32 val;
5351
5352         /* Validate FCoE settings passed */
5353         switch (settings->fcoe_filt_num) {
5354         case I40E_HASH_FILTER_SIZE_1K:
5355         case I40E_HASH_FILTER_SIZE_2K:
5356         case I40E_HASH_FILTER_SIZE_4K:
5357         case I40E_HASH_FILTER_SIZE_8K:
5358         case I40E_HASH_FILTER_SIZE_16K:
5359         case I40E_HASH_FILTER_SIZE_32K:
5360                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5361                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5362                 break;
5363         default:
5364                 return I40E_ERR_PARAM;
5365         }
5366
5367         switch (settings->fcoe_cntx_num) {
5368         case I40E_DMA_CNTX_SIZE_512:
5369         case I40E_DMA_CNTX_SIZE_1K:
5370         case I40E_DMA_CNTX_SIZE_2K:
5371         case I40E_DMA_CNTX_SIZE_4K:
5372                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5373                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5374                 break;
5375         default:
5376                 return I40E_ERR_PARAM;
5377         }
5378
5379         /* Validate PE settings passed */
5380         switch (settings->pe_filt_num) {
5381         case I40E_HASH_FILTER_SIZE_1K:
5382         case I40E_HASH_FILTER_SIZE_2K:
5383         case I40E_HASH_FILTER_SIZE_4K:
5384         case I40E_HASH_FILTER_SIZE_8K:
5385         case I40E_HASH_FILTER_SIZE_16K:
5386         case I40E_HASH_FILTER_SIZE_32K:
5387         case I40E_HASH_FILTER_SIZE_64K:
5388         case I40E_HASH_FILTER_SIZE_128K:
5389         case I40E_HASH_FILTER_SIZE_256K:
5390         case I40E_HASH_FILTER_SIZE_512K:
5391         case I40E_HASH_FILTER_SIZE_1M:
5392                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5393                 pe_filt_size <<= (u32)settings->pe_filt_num;
5394                 break;
5395         default:
5396                 return I40E_ERR_PARAM;
5397         }
5398
5399         switch (settings->pe_cntx_num) {
5400         case I40E_DMA_CNTX_SIZE_512:
5401         case I40E_DMA_CNTX_SIZE_1K:
5402         case I40E_DMA_CNTX_SIZE_2K:
5403         case I40E_DMA_CNTX_SIZE_4K:
5404         case I40E_DMA_CNTX_SIZE_8K:
5405         case I40E_DMA_CNTX_SIZE_16K:
5406         case I40E_DMA_CNTX_SIZE_32K:
5407         case I40E_DMA_CNTX_SIZE_64K:
5408         case I40E_DMA_CNTX_SIZE_128K:
5409         case I40E_DMA_CNTX_SIZE_256K:
5410                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5411                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5412                 break;
5413         default:
5414                 return I40E_ERR_PARAM;
5415         }
5416
5417         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5418         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5419         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5420                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5421         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
5422                 return I40E_ERR_INVALID_SIZE;
5423
5424         return I40E_SUCCESS;
5425 }
5426
5427 /**
5428  * i40e_set_filter_control
5429  * @hw: pointer to the hardware structure
5430  * @settings: Filter control settings
5431  *
5432  * Set the Queue Filters for PE/FCoE and enable filters required
5433  * for a single PF. It is expected that these settings are programmed
5434  * at the driver initialization time.
5435  **/
5436 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5437                                 struct i40e_filter_control_settings *settings)
5438 {
5439         enum i40e_status_code ret = I40E_SUCCESS;
5440         u32 hash_lut_size = 0;
5441         u32 val;
5442
5443         if (!settings)
5444                 return I40E_ERR_PARAM;
5445
5446         /* Validate the input settings */
5447         ret = i40e_validate_filter_settings(hw, settings);
5448         if (ret)
5449                 return ret;
5450
5451         /* Read the PF Queue Filter control register */
5452         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5453
5454         /* Program required PE hash buckets for the PF */
5455         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5456         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5457                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5458         /* Program required PE contexts for the PF */
5459         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5460         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5461                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5462
5463         /* Program required FCoE hash buckets for the PF */
5464         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5465         val |= ((u32)settings->fcoe_filt_num <<
5466                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5467                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5468         /* Program required FCoE DDP contexts for the PF */
5469         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5470         val |= ((u32)settings->fcoe_cntx_num <<
5471                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5472                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5473
5474         /* Program Hash LUT size for the PF */
5475         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5476         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5477                 hash_lut_size = 1;
5478         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5479                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5480
5481         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5482         if (settings->enable_fdir)
5483                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5484         if (settings->enable_ethtype)
5485                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5486         if (settings->enable_macvlan)
5487                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5488
5489         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5490
5491         return I40E_SUCCESS;
5492 }
5493
5494 /**
5495  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5496  * @hw: pointer to the hw struct
5497  * @mac_addr: MAC address to use in the filter
5498  * @ethtype: Ethertype to use in the filter
5499  * @flags: Flags that needs to be applied to the filter
5500  * @vsi_seid: seid of the control VSI
5501  * @queue: VSI queue number to send the packet to
5502  * @is_add: Add control packet filter if True else remove
5503  * @stats: Structure to hold information on control filter counts
5504  * @cmd_details: pointer to command details structure or NULL
5505  *
5506  * This command will Add or Remove control packet filter for a control VSI.
5507  * In return it will update the total number of perfect filter count in
5508  * the stats member.
5509  **/
5510 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5511                                 u8 *mac_addr, u16 ethtype, u16 flags,
5512                                 u16 vsi_seid, u16 queue, bool is_add,
5513                                 struct i40e_control_filter_stats *stats,
5514                                 struct i40e_asq_cmd_details *cmd_details)
5515 {
5516         struct i40e_aq_desc desc;
5517         struct i40e_aqc_add_remove_control_packet_filter *cmd =
5518                 (struct i40e_aqc_add_remove_control_packet_filter *)
5519                 &desc.params.raw;
5520         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5521                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5522                 &desc.params.raw;
5523         enum i40e_status_code status;
5524
5525         if (vsi_seid == 0)
5526                 return I40E_ERR_PARAM;
5527
5528         if (is_add) {
5529                 i40e_fill_default_direct_cmd_desc(&desc,
5530                                 i40e_aqc_opc_add_control_packet_filter);
5531                 cmd->queue = CPU_TO_LE16(queue);
5532         } else {
5533                 i40e_fill_default_direct_cmd_desc(&desc,
5534                                 i40e_aqc_opc_remove_control_packet_filter);
5535         }
5536
5537         if (mac_addr)
5538                 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
5539                             I40E_NONDMA_TO_NONDMA);
5540
5541         cmd->etype = CPU_TO_LE16(ethtype);
5542         cmd->flags = CPU_TO_LE16(flags);
5543         cmd->seid = CPU_TO_LE16(vsi_seid);
5544
5545         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5546
5547         if (!status && stats) {
5548                 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5549                 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5550                 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5551                 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5552         }
5553
5554         return status;
5555 }
5556
5557 /**
5558  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5559  * @hw: pointer to the hw struct
5560  * @seid: VSI seid to add ethertype filter from
5561  **/
5562 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5563 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5564                                                     u16 seid)
5565 {
5566         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5567                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5568                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5569         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5570         enum i40e_status_code status;
5571
5572         status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5573                                                        seid, 0, true, NULL,
5574                                                        NULL);
5575         if (status)
5576                 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5577 }
5578
5579 /**
5580  * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5581  * @filters: list of cloud filters
5582  * @filter_count: length of list
5583  *
5584  * There's an issue in the device where the Geneve VNI layout needs
5585  * to be shifted 1 byte over from the VxLAN VNI
5586  **/
5587 STATIC void i40e_fix_up_geneve_vni(
5588         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5589         u8 filter_count)
5590 {
5591         struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters;
5592         int i;
5593
5594         for (i = 0; i < filter_count; i++) {
5595                 u16 tnl_type;
5596                 u32 ti;
5597
5598                 tnl_type = (LE16_TO_CPU(f[i].flags) &
5599                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5600                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5601                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5602                         ti = LE32_TO_CPU(f[i].tenant_id);
5603                         f[i].tenant_id = CPU_TO_LE32(ti << 8);
5604                 }
5605         }
5606 }
5607
5608 /**
5609  * i40e_aq_add_cloud_filters
5610  * @hw: pointer to the hardware structure
5611  * @seid: VSI seid to add cloud filters from
5612  * @filters: Buffer which contains the filters to be added
5613  * @filter_count: number of filters contained in the buffer
5614  *
5615  * Set the cloud filters for a given VSI.  The contents of the
5616  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5617  * in by the caller of the function.
5618  *
5619  **/
5620 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5621         u16 seid,
5622         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5623         u8 filter_count)
5624 {
5625         struct i40e_aq_desc desc;
5626         struct i40e_aqc_add_remove_cloud_filters *cmd =
5627         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5628         enum i40e_status_code status;
5629         u16 buff_len;
5630
5631         i40e_fill_default_direct_cmd_desc(&desc,
5632                                           i40e_aqc_opc_add_cloud_filters);
5633
5634         buff_len = filter_count * sizeof(*filters);
5635         desc.datalen = CPU_TO_LE16(buff_len);
5636         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5637         cmd->num_filters = filter_count;
5638         cmd->seid = CPU_TO_LE16(seid);
5639
5640         i40e_fix_up_geneve_vni(filters, filter_count);
5641
5642         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5643
5644         return status;
5645 }
5646
5647 /**
5648  * i40e_aq_remove_cloud_filters
5649  * @hw: pointer to the hardware structure
5650  * @seid: VSI seid to remove cloud filters from
5651  * @filters: Buffer which contains the filters to be removed
5652  * @filter_count: number of filters contained in the buffer
5653  *
5654  * Remove the cloud filters for a given VSI.  The contents of the
5655  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5656  * in by the caller of the function.
5657  *
5658  **/
5659 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5660                 u16 seid,
5661                 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5662                 u8 filter_count)
5663 {
5664         struct i40e_aq_desc desc;
5665         struct i40e_aqc_add_remove_cloud_filters *cmd =
5666         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5667         enum i40e_status_code status;
5668         u16 buff_len;
5669
5670         i40e_fill_default_direct_cmd_desc(&desc,
5671                                           i40e_aqc_opc_remove_cloud_filters);
5672
5673         buff_len = filter_count * sizeof(*filters);
5674         desc.datalen = CPU_TO_LE16(buff_len);
5675         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5676         cmd->num_filters = filter_count;
5677         cmd->seid = CPU_TO_LE16(seid);
5678
5679         i40e_fix_up_geneve_vni(filters, filter_count);
5680
5681         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5682
5683         return status;
5684 }
5685
5686 /**
5687  * i40e_aq_alternate_write
5688  * @hw: pointer to the hardware structure
5689  * @reg_addr0: address of first dword to be read
5690  * @reg_val0: value to be written under 'reg_addr0'
5691  * @reg_addr1: address of second dword to be read
5692  * @reg_val1: value to be written under 'reg_addr1'
5693  *
5694  * Write one or two dwords to alternate structure. Fields are indicated
5695  * by 'reg_addr0' and 'reg_addr1' register numbers.
5696  *
5697  **/
5698 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5699                                 u32 reg_addr0, u32 reg_val0,
5700                                 u32 reg_addr1, u32 reg_val1)
5701 {
5702         struct i40e_aq_desc desc;
5703         struct i40e_aqc_alternate_write *cmd_resp =
5704                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5705         enum i40e_status_code status;
5706
5707         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5708         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5709         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5710         cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5711         cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5712
5713         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5714
5715         return status;
5716 }
5717
5718 /**
5719  * i40e_aq_alternate_write_indirect
5720  * @hw: pointer to the hardware structure
5721  * @addr: address of a first register to be modified
5722  * @dw_count: number of alternate structure fields to write
5723  * @buffer: pointer to the command buffer
5724  *
5725  * Write 'dw_count' dwords from 'buffer' to alternate structure
5726  * starting at 'addr'.
5727  *
5728  **/
5729 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5730                                 u32 addr, u32 dw_count, void *buffer)
5731 {
5732         struct i40e_aq_desc desc;
5733         struct i40e_aqc_alternate_ind_write *cmd_resp =
5734                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5735         enum i40e_status_code status;
5736
5737         if (buffer == NULL)
5738                 return I40E_ERR_PARAM;
5739
5740         /* Indirect command */
5741         i40e_fill_default_direct_cmd_desc(&desc,
5742                                          i40e_aqc_opc_alternate_write_indirect);
5743
5744         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5745         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5746         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5747                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5748
5749         cmd_resp->address = CPU_TO_LE32(addr);
5750         cmd_resp->length = CPU_TO_LE32(dw_count);
5751
5752         status = i40e_asq_send_command(hw, &desc, buffer,
5753                                        I40E_LO_DWORD(4*dw_count), NULL);
5754
5755         return status;
5756 }
5757
5758 /**
5759  * i40e_aq_alternate_read
5760  * @hw: pointer to the hardware structure
5761  * @reg_addr0: address of first dword to be read
5762  * @reg_val0: pointer for data read from 'reg_addr0'
5763  * @reg_addr1: address of second dword to be read
5764  * @reg_val1: pointer for data read from 'reg_addr1'
5765  *
5766  * Read one or two dwords from alternate structure. Fields are indicated
5767  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5768  * is not passed then only register at 'reg_addr0' is read.
5769  *
5770  **/
5771 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5772                                 u32 reg_addr0, u32 *reg_val0,
5773                                 u32 reg_addr1, u32 *reg_val1)
5774 {
5775         struct i40e_aq_desc desc;
5776         struct i40e_aqc_alternate_write *cmd_resp =
5777                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5778         enum i40e_status_code status;
5779
5780         if (reg_val0 == NULL)
5781                 return I40E_ERR_PARAM;
5782
5783         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5784         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5785         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5786
5787         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5788
5789         if (status == I40E_SUCCESS) {
5790                 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5791
5792                 if (reg_val1 != NULL)
5793                         *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5794         }
5795
5796         return status;
5797 }
5798
5799 /**
5800  * i40e_aq_alternate_read_indirect
5801  * @hw: pointer to the hardware structure
5802  * @addr: address of the alternate structure field
5803  * @dw_count: number of alternate structure fields to read
5804  * @buffer: pointer to the command buffer
5805  *
5806  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5807  * place them in 'buffer'. The buffer should be allocated by caller.
5808  *
5809  **/
5810 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5811                                 u32 addr, u32 dw_count, void *buffer)
5812 {
5813         struct i40e_aq_desc desc;
5814         struct i40e_aqc_alternate_ind_write *cmd_resp =
5815                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5816         enum i40e_status_code status;
5817
5818         if (buffer == NULL)
5819                 return I40E_ERR_PARAM;
5820
5821         /* Indirect command */
5822         i40e_fill_default_direct_cmd_desc(&desc,
5823                 i40e_aqc_opc_alternate_read_indirect);
5824
5825         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5826         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5827         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5828                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5829
5830         cmd_resp->address = CPU_TO_LE32(addr);
5831         cmd_resp->length = CPU_TO_LE32(dw_count);
5832
5833         status = i40e_asq_send_command(hw, &desc, buffer,
5834                                        I40E_LO_DWORD(4*dw_count), NULL);
5835
5836         return status;
5837 }
5838
5839 /**
5840  *  i40e_aq_alternate_clear
5841  *  @hw: pointer to the HW structure.
5842  *
5843  *  Clear the alternate structures of the port from which the function
5844  *  is called.
5845  *
5846  **/
5847 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5848 {
5849         struct i40e_aq_desc desc;
5850         enum i40e_status_code status;
5851
5852         i40e_fill_default_direct_cmd_desc(&desc,
5853                                           i40e_aqc_opc_alternate_clear_port);
5854
5855         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5856
5857         return status;
5858 }
5859
5860 /**
5861  *  i40e_aq_alternate_write_done
5862  *  @hw: pointer to the HW structure.
5863  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
5864  *  @reset_needed: indicates the SW should trigger GLOBAL reset
5865  *
5866  *  Indicates to the FW that alternate structures have been changed.
5867  *
5868  **/
5869 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
5870                 u8 bios_mode, bool *reset_needed)
5871 {
5872         struct i40e_aq_desc desc;
5873         struct i40e_aqc_alternate_write_done *cmd =
5874                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5875         enum i40e_status_code status;
5876
5877         if (reset_needed == NULL)
5878                 return I40E_ERR_PARAM;
5879
5880         i40e_fill_default_direct_cmd_desc(&desc,
5881                                           i40e_aqc_opc_alternate_write_done);
5882
5883         cmd->cmd_flags = CPU_TO_LE16(bios_mode);
5884
5885         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5886         if (!status && reset_needed)
5887                 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
5888                                  I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
5889
5890         return status;
5891 }
5892
5893 /**
5894  *  i40e_aq_set_oem_mode
5895  *  @hw: pointer to the HW structure.
5896  *  @oem_mode: the OEM mode to be used
5897  *
5898  *  Sets the device to a specific operating mode. Currently the only supported
5899  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
5900  *
5901  **/
5902 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
5903                 u8 oem_mode)
5904 {
5905         struct i40e_aq_desc desc;
5906         struct i40e_aqc_alternate_write_done *cmd =
5907                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5908         enum i40e_status_code status;
5909
5910         i40e_fill_default_direct_cmd_desc(&desc,
5911                                           i40e_aqc_opc_alternate_set_mode);
5912
5913         cmd->cmd_flags = CPU_TO_LE16(oem_mode);
5914
5915         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5916
5917         return status;
5918 }
5919
5920 /**
5921  * i40e_aq_resume_port_tx
5922  * @hw: pointer to the hardware structure
5923  * @cmd_details: pointer to command details structure or NULL
5924  *
5925  * Resume port's Tx traffic
5926  **/
5927 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
5928                                 struct i40e_asq_cmd_details *cmd_details)
5929 {
5930         struct i40e_aq_desc desc;
5931         enum i40e_status_code status;
5932
5933         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
5934
5935         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5936
5937         return status;
5938 }
5939
5940 /**
5941  * i40e_set_pci_config_data - store PCI bus info
5942  * @hw: pointer to hardware structure
5943  * @link_status: the link status word from PCI config space
5944  *
5945  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
5946  **/
5947 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
5948 {
5949         hw->bus.type = i40e_bus_type_pci_express;
5950
5951         switch (link_status & I40E_PCI_LINK_WIDTH) {
5952         case I40E_PCI_LINK_WIDTH_1:
5953                 hw->bus.width = i40e_bus_width_pcie_x1;
5954                 break;
5955         case I40E_PCI_LINK_WIDTH_2:
5956                 hw->bus.width = i40e_bus_width_pcie_x2;
5957                 break;
5958         case I40E_PCI_LINK_WIDTH_4:
5959                 hw->bus.width = i40e_bus_width_pcie_x4;
5960                 break;
5961         case I40E_PCI_LINK_WIDTH_8:
5962                 hw->bus.width = i40e_bus_width_pcie_x8;
5963                 break;
5964         default:
5965                 hw->bus.width = i40e_bus_width_unknown;
5966                 break;
5967         }
5968
5969         switch (link_status & I40E_PCI_LINK_SPEED) {
5970         case I40E_PCI_LINK_SPEED_2500:
5971                 hw->bus.speed = i40e_bus_speed_2500;
5972                 break;
5973         case I40E_PCI_LINK_SPEED_5000:
5974                 hw->bus.speed = i40e_bus_speed_5000;
5975                 break;
5976         case I40E_PCI_LINK_SPEED_8000:
5977                 hw->bus.speed = i40e_bus_speed_8000;
5978                 break;
5979         default:
5980                 hw->bus.speed = i40e_bus_speed_unknown;
5981                 break;
5982         }
5983 }
5984
5985 /**
5986  * i40e_aq_debug_dump
5987  * @hw: pointer to the hardware structure
5988  * @cluster_id: specific cluster to dump
5989  * @table_id: table id within cluster
5990  * @start_index: index of line in the block to read
5991  * @buff_size: dump buffer size
5992  * @buff: dump buffer
5993  * @ret_buff_size: actual buffer size returned
5994  * @ret_next_table: next block to read
5995  * @ret_next_index: next index to read
5996  *
5997  * Dump internal FW/HW data for debug purposes.
5998  *
5999  **/
6000 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
6001                                 u8 table_id, u32 start_index, u16 buff_size,
6002                                 void *buff, u16 *ret_buff_size,
6003                                 u8 *ret_next_table, u32 *ret_next_index,
6004                                 struct i40e_asq_cmd_details *cmd_details)
6005 {
6006         struct i40e_aq_desc desc;
6007         struct i40e_aqc_debug_dump_internals *cmd =
6008                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6009         struct i40e_aqc_debug_dump_internals *resp =
6010                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6011         enum i40e_status_code status;
6012
6013         if (buff_size == 0 || !buff)
6014                 return I40E_ERR_PARAM;
6015
6016         i40e_fill_default_direct_cmd_desc(&desc,
6017                                           i40e_aqc_opc_debug_dump_internals);
6018         /* Indirect Command */
6019         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6020         if (buff_size > I40E_AQ_LARGE_BUF)
6021                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6022
6023         cmd->cluster_id = cluster_id;
6024         cmd->table_id = table_id;
6025         cmd->idx = CPU_TO_LE32(start_index);
6026
6027         desc.datalen = CPU_TO_LE16(buff_size);
6028
6029         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
6030         if (!status) {
6031                 if (ret_buff_size != NULL)
6032                         *ret_buff_size = LE16_TO_CPU(desc.datalen);
6033                 if (ret_next_table != NULL)
6034                         *ret_next_table = resp->table_id;
6035                 if (ret_next_index != NULL)
6036                         *ret_next_index = LE32_TO_CPU(resp->idx);
6037         }
6038
6039         return status;
6040 }
6041
6042 /**
6043  * i40e_read_bw_from_alt_ram
6044  * @hw: pointer to the hardware structure
6045  * @max_bw: pointer for max_bw read
6046  * @min_bw: pointer for min_bw read
6047  * @min_valid: pointer for bool that is true if min_bw is a valid value
6048  * @max_valid: pointer for bool that is true if max_bw is a valid value
6049  *
6050  * Read bw from the alternate ram for the given pf
6051  **/
6052 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
6053                                         u32 *max_bw, u32 *min_bw,
6054                                         bool *min_valid, bool *max_valid)
6055 {
6056         enum i40e_status_code status;
6057         u32 max_bw_addr, min_bw_addr;
6058
6059         /* Calculate the address of the min/max bw registers */
6060         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6061                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
6062                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6063         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6064                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
6065                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6066
6067         /* Read the bandwidths from alt ram */
6068         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
6069                                         min_bw_addr, min_bw);
6070
6071         if (*min_bw & I40E_ALT_BW_VALID_MASK)
6072                 *min_valid = true;
6073         else
6074                 *min_valid = false;
6075
6076         if (*max_bw & I40E_ALT_BW_VALID_MASK)
6077                 *max_valid = true;
6078         else
6079                 *max_valid = false;
6080
6081         return status;
6082 }
6083
6084 /**
6085  * i40e_aq_configure_partition_bw
6086  * @hw: pointer to the hardware structure
6087  * @bw_data: Buffer holding valid pfs and bw limits
6088  * @cmd_details: pointer to command details
6089  *
6090  * Configure partitions guaranteed/max bw
6091  **/
6092 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6093                         struct i40e_aqc_configure_partition_bw_data *bw_data,
6094                         struct i40e_asq_cmd_details *cmd_details)
6095 {
6096         enum i40e_status_code status;
6097         struct i40e_aq_desc desc;
6098         u16 bwd_size = sizeof(*bw_data);
6099
6100         i40e_fill_default_direct_cmd_desc(&desc,
6101                                 i40e_aqc_opc_configure_partition_bw);
6102
6103         /* Indirect command */
6104         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6105         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6106
6107         desc.datalen = CPU_TO_LE16(bwd_size);
6108
6109         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6110
6111         return status;
6112 }
6113
6114 /**
6115  * i40e_read_phy_register_clause22
6116  * @hw: pointer to the HW structure
6117  * @reg: register address in the page
6118  * @phy_adr: PHY address on MDIO interface
6119  * @value: PHY register value
6120  *
6121  * Reads specified PHY register value
6122  **/
6123 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
6124                                         u16 reg, u8 phy_addr, u16 *value)
6125 {
6126         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6127         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6128         u32 command = 0;
6129         u16 retry = 1000;
6130
6131         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6132                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6133                   (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
6134                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6135                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6136         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6137         do {
6138                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6139                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6140                         status = I40E_SUCCESS;
6141                         break;
6142                 }
6143                 i40e_usec_delay(10);
6144                 retry--;
6145         } while (retry);
6146
6147         if (status) {
6148                 i40e_debug(hw, I40E_DEBUG_PHY,
6149                            "PHY: Can't write command to external PHY.\n");
6150         } else {
6151                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6152                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6153                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6154         }
6155
6156         return status;
6157 }
6158
6159 /**
6160  * i40e_write_phy_register_clause22
6161  * @hw: pointer to the HW structure
6162  * @reg: register address in the page
6163  * @phy_adr: PHY address on MDIO interface
6164  * @value: PHY register value
6165  *
6166  * Writes specified PHY register value
6167  **/
6168 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6169                                         u16 reg, u8 phy_addr, u16 value)
6170 {
6171         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6172         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6173         u32 command  = 0;
6174         u16 retry = 1000;
6175
6176         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6177         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6178
6179         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6180                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6181                   (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6182                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6183                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6184
6185         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6186         do {
6187                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6188                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6189                         status = I40E_SUCCESS;
6190                         break;
6191                 }
6192                 i40e_usec_delay(10);
6193                 retry--;
6194         } while (retry);
6195
6196         return status;
6197 }
6198
6199 /**
6200  * i40e_read_phy_register_clause45
6201  * @hw: pointer to the HW structure
6202  * @page: registers page number
6203  * @reg: register address in the page
6204  * @phy_adr: PHY address on MDIO interface
6205  * @value: PHY register value
6206  *
6207  * Reads specified PHY register value
6208  **/
6209 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6210                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6211 {
6212         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6213         u32 command  = 0;
6214         u16 retry = 1000;
6215         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6216
6217         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6218                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6219                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6220                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6221                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6222                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6223                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6224         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6225         do {
6226                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6227                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6228                         status = I40E_SUCCESS;
6229                         break;
6230                 }
6231                 i40e_usec_delay(10);
6232                 retry--;
6233         } while (retry);
6234
6235         if (status) {
6236                 i40e_debug(hw, I40E_DEBUG_PHY,
6237                            "PHY: Can't write command to external PHY.\n");
6238                 goto phy_read_end;
6239         }
6240
6241         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6242                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6243                   (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6244                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6245                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6246                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6247         status = I40E_ERR_TIMEOUT;
6248         retry = 1000;
6249         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6250         do {
6251                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6252                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6253                         status = I40E_SUCCESS;
6254                         break;
6255                 }
6256                 i40e_usec_delay(10);
6257                 retry--;
6258         } while (retry);
6259
6260         if (!status) {
6261                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6262                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6263                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6264         } else {
6265                 i40e_debug(hw, I40E_DEBUG_PHY,
6266                            "PHY: Can't read register value from external PHY.\n");
6267         }
6268
6269 phy_read_end:
6270         return status;
6271 }
6272
6273 /**
6274  * i40e_write_phy_register_clause45
6275  * @hw: pointer to the HW structure
6276  * @page: registers page number
6277  * @reg: register address in the page
6278  * @phy_adr: PHY address on MDIO interface
6279  * @value: PHY register value
6280  *
6281  * Writes value to specified PHY register
6282  **/
6283 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6284                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6285 {
6286         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6287         u32 command  = 0;
6288         u16 retry = 1000;
6289         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6290
6291         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6292                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6293                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6294                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6295                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6296                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6297                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6298         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6299         do {
6300                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6301                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6302                         status = I40E_SUCCESS;
6303                         break;
6304                 }
6305                 i40e_usec_delay(10);
6306                 retry--;
6307         } while (retry);
6308         if (status) {
6309                 i40e_debug(hw, I40E_DEBUG_PHY,
6310                            "PHY: Can't write command to external PHY.\n");
6311                 goto phy_write_end;
6312         }
6313
6314         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6315         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6316
6317         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6318                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6319                   (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6320                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6321                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6322                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6323         status = I40E_ERR_TIMEOUT;
6324         retry = 1000;
6325         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6326         do {
6327                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6328                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6329                         status = I40E_SUCCESS;
6330                         break;
6331                 }
6332                 i40e_usec_delay(10);
6333                 retry--;
6334         } while (retry);
6335
6336 phy_write_end:
6337         return status;
6338 }
6339
6340 /**
6341  * i40e_write_phy_register
6342  * @hw: pointer to the HW structure
6343  * @page: registers page number
6344  * @reg: register address in the page
6345  * @phy_adr: PHY address on MDIO interface
6346  * @value: PHY register value
6347  *
6348  * Writes value to specified PHY register
6349  **/
6350 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6351                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6352 {
6353         enum i40e_status_code status;
6354
6355         switch (hw->device_id) {
6356         case I40E_DEV_ID_1G_BASE_T_X722:
6357                 status = i40e_write_phy_register_clause22(hw,
6358                         reg, phy_addr, value);
6359                 break;
6360         case I40E_DEV_ID_10G_BASE_T:
6361         case I40E_DEV_ID_10G_BASE_T4:
6362         case I40E_DEV_ID_10G_BASE_T_X722:
6363         case I40E_DEV_ID_25G_B:
6364         case I40E_DEV_ID_25G_SFP28:
6365                 status = i40e_write_phy_register_clause45(hw,
6366                         page, reg, phy_addr, value);
6367                 break;
6368         default:
6369                 status = I40E_ERR_UNKNOWN_PHY;
6370                 break;
6371         }
6372
6373         return status;
6374 }
6375
6376 /**
6377  * i40e_read_phy_register
6378  * @hw: pointer to the HW structure
6379  * @page: registers page number
6380  * @reg: register address in the page
6381  * @phy_adr: PHY address on MDIO interface
6382  * @value: PHY register value
6383  *
6384  * Reads specified PHY register value
6385  **/
6386 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6387                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6388 {
6389         enum i40e_status_code status;
6390
6391         switch (hw->device_id) {
6392         case I40E_DEV_ID_1G_BASE_T_X722:
6393                 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6394                                                          value);
6395                 break;
6396         case I40E_DEV_ID_10G_BASE_T:
6397         case I40E_DEV_ID_10G_BASE_T4:
6398         case I40E_DEV_ID_10G_BASE_T_X722:
6399         case I40E_DEV_ID_25G_B:
6400         case I40E_DEV_ID_25G_SFP28:
6401                 status = i40e_read_phy_register_clause45(hw, page, reg,
6402                                                          phy_addr, value);
6403                 break;
6404         default:
6405                 status = I40E_ERR_UNKNOWN_PHY;
6406                 break;
6407         }
6408
6409         return status;
6410 }
6411
6412 /**
6413  * i40e_get_phy_address
6414  * @hw: pointer to the HW structure
6415  * @dev_num: PHY port num that address we want
6416  * @phy_addr: Returned PHY address
6417  *
6418  * Gets PHY address for current port
6419  **/
6420 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6421 {
6422         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6423         u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6424
6425         return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6426 }
6427
6428 /**
6429  * i40e_blink_phy_led
6430  * @hw: pointer to the HW structure
6431  * @time: time how long led will blinks in secs
6432  * @interval: gap between LED on and off in msecs
6433  *
6434  * Blinks PHY link LED
6435  **/
6436 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6437                                               u32 time, u32 interval)
6438 {
6439         enum i40e_status_code status = I40E_SUCCESS;
6440         u32 i;
6441         u16 led_ctl = 0;
6442         u16 gpio_led_port;
6443         u16 led_reg;
6444         u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6445         u8 phy_addr = 0;
6446         u8 port_num;
6447
6448         i = rd32(hw, I40E_PFGEN_PORTNUM);
6449         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6450         phy_addr = i40e_get_phy_address(hw, port_num);
6451
6452         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6453              led_addr++) {
6454                 status = i40e_read_phy_register_clause45(hw,
6455                                                          I40E_PHY_COM_REG_PAGE,
6456                                                          led_addr, phy_addr,
6457                                                          &led_reg);
6458                 if (status)
6459                         goto phy_blinking_end;
6460                 led_ctl = led_reg;
6461                 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6462                         led_reg = 0;
6463                         status = i40e_write_phy_register_clause45(hw,
6464                                                          I40E_PHY_COM_REG_PAGE,
6465                                                          led_addr, phy_addr,
6466                                                          led_reg);
6467                         if (status)
6468                                 goto phy_blinking_end;
6469                         break;
6470                 }
6471         }
6472
6473         if (time > 0 && interval > 0) {
6474                 for (i = 0; i < time * 1000; i += interval) {
6475                         status = i40e_read_phy_register_clause45(hw,
6476                                                 I40E_PHY_COM_REG_PAGE,
6477                                                 led_addr, phy_addr, &led_reg);
6478                         if (status)
6479                                 goto restore_config;
6480                         if (led_reg & I40E_PHY_LED_MANUAL_ON)
6481                                 led_reg = 0;
6482                         else
6483                                 led_reg = I40E_PHY_LED_MANUAL_ON;
6484                         status = i40e_write_phy_register_clause45(hw,
6485                                                 I40E_PHY_COM_REG_PAGE,
6486                                                 led_addr, phy_addr, led_reg);
6487                         if (status)
6488                                 goto restore_config;
6489                         i40e_msec_delay(interval);
6490                 }
6491         }
6492
6493 restore_config:
6494         status = i40e_write_phy_register_clause45(hw,
6495                                                   I40E_PHY_COM_REG_PAGE,
6496                                                   led_addr, phy_addr, led_ctl);
6497
6498 phy_blinking_end:
6499         return status;
6500 }
6501
6502 /**
6503  * i40e_led_get_phy - return current on/off mode
6504  * @hw: pointer to the hw struct
6505  * @led_addr: address of led register to use
6506  * @val: original value of register to use
6507  *
6508  **/
6509 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6510                                        u16 *val)
6511 {
6512         enum i40e_status_code status = I40E_SUCCESS;
6513         u16 gpio_led_port;
6514         u8 phy_addr = 0;
6515         u16 reg_val;
6516         u16 temp_addr;
6517         u8 port_num;
6518         u32 i;
6519
6520         temp_addr = I40E_PHY_LED_PROV_REG_1;
6521         i = rd32(hw, I40E_PFGEN_PORTNUM);
6522         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6523         phy_addr = i40e_get_phy_address(hw, port_num);
6524
6525         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6526              temp_addr++) {
6527                 status = i40e_read_phy_register_clause45(hw,
6528                                                          I40E_PHY_COM_REG_PAGE,
6529                                                          temp_addr, phy_addr,
6530                                                          &reg_val);
6531                 if (status)
6532                         return status;
6533                 *val = reg_val;
6534                 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6535                         *led_addr = temp_addr;
6536                         break;
6537                 }
6538         }
6539         return status;
6540 }
6541
6542 /**
6543  * i40e_led_set_phy
6544  * @hw: pointer to the HW structure
6545  * @on: true or false
6546  * @mode: original val plus bit for set or ignore
6547  * Set led's on or off when controlled by the PHY
6548  *
6549  **/
6550 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6551                                        u16 led_addr, u32 mode)
6552 {
6553         enum i40e_status_code status = I40E_SUCCESS;
6554         u16 led_ctl = 0;
6555         u16 led_reg = 0;
6556         u8 phy_addr = 0;
6557         u8 port_num;
6558         u32 i;
6559
6560         i = rd32(hw, I40E_PFGEN_PORTNUM);
6561         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6562         phy_addr = i40e_get_phy_address(hw, port_num);
6563         status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6564                                                  led_addr, phy_addr, &led_reg);
6565         if (status)
6566                 return status;
6567         led_ctl = led_reg;
6568         if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6569                 led_reg = 0;
6570                 status = i40e_write_phy_register_clause45(hw,
6571                                                           I40E_PHY_COM_REG_PAGE,
6572                                                           led_addr, phy_addr,
6573                                                           led_reg);
6574                 if (status)
6575                         return status;
6576         }
6577         status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6578                                                  led_addr, phy_addr, &led_reg);
6579         if (status)
6580                 goto restore_config;
6581         if (on)
6582                 led_reg = I40E_PHY_LED_MANUAL_ON;
6583         else
6584                 led_reg = 0;
6585         status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6586                                                   led_addr, phy_addr, led_reg);
6587         if (status)
6588                 goto restore_config;
6589         if (mode & I40E_PHY_LED_MODE_ORIG) {
6590                 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6591                 status = i40e_write_phy_register_clause45(hw,
6592                                                  I40E_PHY_COM_REG_PAGE,
6593                                                  led_addr, phy_addr, led_ctl);
6594         }
6595         return status;
6596 restore_config:
6597         status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6598                                                   led_addr, phy_addr, led_ctl);
6599         return status;
6600 }
6601 #endif /* PF_DRIVER */
6602
6603 /**
6604  * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6605  * @hw: pointer to the hw struct
6606  * @reg_addr: register address
6607  * @reg_val: ptr to register value
6608  * @cmd_details: pointer to command details structure or NULL
6609  *
6610  * Use the firmware to read the Rx control register,
6611  * especially useful if the Rx unit is under heavy pressure
6612  **/
6613 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6614                                 u32 reg_addr, u32 *reg_val,
6615                                 struct i40e_asq_cmd_details *cmd_details)
6616 {
6617         struct i40e_aq_desc desc;
6618         struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
6619                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6620         enum i40e_status_code status;
6621
6622         if (reg_val == NULL)
6623                 return I40E_ERR_PARAM;
6624
6625         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
6626
6627         cmd_resp->address = CPU_TO_LE32(reg_addr);
6628
6629         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6630
6631         if (status == I40E_SUCCESS)
6632                 *reg_val = LE32_TO_CPU(cmd_resp->value);
6633
6634         return status;
6635 }
6636
6637 /**
6638  * i40e_read_rx_ctl - read from an Rx control register
6639  * @hw: pointer to the hw struct
6640  * @reg_addr: register address
6641  **/
6642 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
6643 {
6644         enum i40e_status_code status = I40E_SUCCESS;
6645         bool use_register;
6646         int retry = 5;
6647         u32 val = 0;
6648
6649         use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6650         if (!use_register) {
6651 do_retry:
6652                 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
6653                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6654                         i40e_msec_delay(1);
6655                         retry--;
6656                         goto do_retry;
6657                 }
6658         }
6659
6660         /* if the AQ access failed, try the old-fashioned way */
6661         if (status || use_register)
6662                 val = rd32(hw, reg_addr);
6663
6664         return val;
6665 }
6666
6667 /**
6668  * i40e_aq_rx_ctl_write_register
6669  * @hw: pointer to the hw struct
6670  * @reg_addr: register address
6671  * @reg_val: register value
6672  * @cmd_details: pointer to command details structure or NULL
6673  *
6674  * Use the firmware to write to an Rx control register,
6675  * especially useful if the Rx unit is under heavy pressure
6676  **/
6677 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
6678                                 u32 reg_addr, u32 reg_val,
6679                                 struct i40e_asq_cmd_details *cmd_details)
6680 {
6681         struct i40e_aq_desc desc;
6682         struct i40e_aqc_rx_ctl_reg_read_write *cmd =
6683                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6684         enum i40e_status_code status;
6685
6686         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
6687
6688         cmd->address = CPU_TO_LE32(reg_addr);
6689         cmd->value = CPU_TO_LE32(reg_val);
6690
6691         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6692
6693         return status;
6694 }
6695
6696 /**
6697  * i40e_write_rx_ctl - write to an Rx control register
6698  * @hw: pointer to the hw struct
6699  * @reg_addr: register address
6700  * @reg_val: register value
6701  **/
6702 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
6703 {
6704         enum i40e_status_code status = I40E_SUCCESS;
6705         bool use_register;
6706         int retry = 5;
6707
6708         use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6709         if (!use_register) {
6710 do_retry:
6711                 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
6712                                                        reg_val, NULL);
6713                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6714                         i40e_msec_delay(1);
6715                         retry--;
6716                         goto do_retry;
6717                 }
6718         }
6719
6720         /* if the AQ access failed, try the old-fashioned way */
6721         if (status || use_register)
6722                 wr32(hw, reg_addr, reg_val);
6723 }
6724 #ifdef VF_DRIVER
6725
6726 /**
6727  * i40e_aq_send_msg_to_pf
6728  * @hw: pointer to the hardware structure
6729  * @v_opcode: opcodes for VF-PF communication
6730  * @v_retval: return error code
6731  * @msg: pointer to the msg buffer
6732  * @msglen: msg length
6733  * @cmd_details: pointer to command details
6734  *
6735  * Send message to PF driver using admin queue. By default, this message
6736  * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
6737  * completion before returning.
6738  **/
6739 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
6740                                 enum i40e_virtchnl_ops v_opcode,
6741                                 enum i40e_status_code v_retval,
6742                                 u8 *msg, u16 msglen,
6743                                 struct i40e_asq_cmd_details *cmd_details)
6744 {
6745         struct i40e_aq_desc desc;
6746         struct i40e_asq_cmd_details details;
6747         enum i40e_status_code status;
6748
6749         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
6750         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
6751         desc.cookie_high = CPU_TO_LE32(v_opcode);
6752         desc.cookie_low = CPU_TO_LE32(v_retval);
6753         if (msglen) {
6754                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
6755                                                 | I40E_AQ_FLAG_RD));
6756                 if (msglen > I40E_AQ_LARGE_BUF)
6757                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6758                 desc.datalen = CPU_TO_LE16(msglen);
6759         }
6760         if (!cmd_details) {
6761                 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
6762                 details.async = true;
6763                 cmd_details = &details;
6764         }
6765         status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
6766                                        msglen, cmd_details);
6767         return status;
6768 }
6769
6770 /**
6771  * i40e_vf_parse_hw_config
6772  * @hw: pointer to the hardware structure
6773  * @msg: pointer to the virtual channel VF resource structure
6774  *
6775  * Given a VF resource message from the PF, populate the hw struct
6776  * with appropriate information.
6777  **/
6778 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
6779                              struct i40e_virtchnl_vf_resource *msg)
6780 {
6781         struct i40e_virtchnl_vsi_resource *vsi_res;
6782         int i;
6783
6784         vsi_res = &msg->vsi_res[0];
6785
6786         hw->dev_caps.num_vsis = msg->num_vsis;
6787         hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
6788         hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
6789         hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
6790         hw->dev_caps.dcb = msg->vf_offload_flags &
6791                            I40E_VIRTCHNL_VF_OFFLOAD_L2;
6792         hw->dev_caps.fcoe = (msg->vf_offload_flags &
6793                              I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
6794         hw->dev_caps.iwarp = (msg->vf_offload_flags &
6795                               I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
6796         for (i = 0; i < msg->num_vsis; i++) {
6797                 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
6798                         i40e_memcpy(hw->mac.perm_addr,
6799                                     vsi_res->default_mac_addr,
6800                                     I40E_ETH_LENGTH_OF_ADDRESS,
6801                                     I40E_NONDMA_TO_NONDMA);
6802                         i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
6803                                     I40E_ETH_LENGTH_OF_ADDRESS,
6804                                     I40E_NONDMA_TO_NONDMA);
6805                 }
6806                 vsi_res++;
6807         }
6808 }
6809
6810 /**
6811  * i40e_vf_reset
6812  * @hw: pointer to the hardware structure
6813  *
6814  * Send a VF_RESET message to the PF. Does not wait for response from PF
6815  * as none will be forthcoming. Immediately after calling this function,
6816  * the admin queue should be shut down and (optionally) reinitialized.
6817  **/
6818 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
6819 {
6820         return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
6821                                       I40E_SUCCESS, NULL, 0, NULL);
6822 }
6823 #endif /* VF_DRIVER */
6824 #ifdef X722_SUPPORT
6825
6826 /**
6827  * i40e_aq_set_arp_proxy_config
6828  * @hw: pointer to the HW structure
6829  * @proxy_config - pointer to proxy config command table struct
6830  * @cmd_details: pointer to command details
6831  *
6832  * Set ARP offload parameters from pre-populated
6833  * i40e_aqc_arp_proxy_data struct
6834  **/
6835 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
6836                                 struct i40e_aqc_arp_proxy_data *proxy_config,
6837                                 struct i40e_asq_cmd_details *cmd_details)
6838 {
6839         struct i40e_aq_desc desc;
6840         enum i40e_status_code status;
6841
6842         if (!proxy_config)
6843                 return I40E_ERR_PARAM;
6844
6845         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
6846
6847         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6848         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6849         desc.params.external.addr_high =
6850                                   CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
6851         desc.params.external.addr_low =
6852                                   CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
6853         desc.datalen = sizeof(struct i40e_aqc_arp_proxy_data);
6854
6855         status = i40e_asq_send_command(hw, &desc, proxy_config,
6856                                        sizeof(struct i40e_aqc_arp_proxy_data),
6857                                        cmd_details);
6858
6859         return status;
6860 }
6861
6862 /**
6863  * i40e_aq_opc_set_ns_proxy_table_entry
6864  * @hw: pointer to the HW structure
6865  * @ns_proxy_table_entry: pointer to NS table entry command struct
6866  * @cmd_details: pointer to command details
6867  *
6868  * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
6869  * from pre-populated i40e_aqc_ns_proxy_data struct
6870  **/
6871 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
6872                         struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
6873                         struct i40e_asq_cmd_details *cmd_details)
6874 {
6875         struct i40e_aq_desc desc;
6876         enum i40e_status_code status;
6877
6878         if (!ns_proxy_table_entry)
6879                 return I40E_ERR_PARAM;
6880
6881         i40e_fill_default_direct_cmd_desc(&desc,
6882                                 i40e_aqc_opc_set_ns_proxy_table_entry);
6883
6884         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6885         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6886         desc.params.external.addr_high =
6887                 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
6888         desc.params.external.addr_low =
6889                 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
6890         desc.datalen = sizeof(struct i40e_aqc_ns_proxy_data);
6891
6892         status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
6893                                        sizeof(struct i40e_aqc_ns_proxy_data),
6894                                        cmd_details);
6895
6896         return status;
6897 }
6898
6899 /**
6900  * i40e_aq_set_clear_wol_filter
6901  * @hw: pointer to the hw struct
6902  * @filter_index: index of filter to modify (0-7)
6903  * @filter: buffer containing filter to be set
6904  * @set_filter: true to set filter, false to clear filter
6905  * @no_wol_tco: if true, pass through packets cannot cause wake-up
6906  *              if false, pass through packets may cause wake-up
6907  * @filter_valid: true if filter action is valid
6908  * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
6909  * @cmd_details: pointer to command details structure or NULL
6910  *
6911  * Set or clear WoL filter for port attached to the PF
6912  **/
6913 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
6914                                 u8 filter_index,
6915                                 struct i40e_aqc_set_wol_filter_data *filter,
6916                                 bool set_filter, bool no_wol_tco,
6917                                 bool filter_valid, bool no_wol_tco_valid,
6918                                 struct i40e_asq_cmd_details *cmd_details)
6919 {
6920         struct i40e_aq_desc desc;
6921         struct i40e_aqc_set_wol_filter *cmd =
6922                 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
6923         enum i40e_status_code status;
6924         u16 cmd_flags = 0;
6925         u16 valid_flags = 0;
6926         u16 buff_len = 0;
6927
6928         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
6929
6930         if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
6931                 return  I40E_ERR_PARAM;
6932         cmd->filter_index = CPU_TO_LE16(filter_index);
6933
6934         if (set_filter) {
6935                 if (!filter)
6936                         return  I40E_ERR_PARAM;
6937
6938                 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
6939                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR;
6940         }
6941
6942         if (no_wol_tco)
6943                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
6944         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
6945
6946         if (filter_valid)
6947                 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
6948         if (no_wol_tco_valid)
6949                 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
6950         cmd->valid_flags = CPU_TO_LE16(valid_flags);
6951
6952         buff_len = sizeof(*filter);
6953         desc.datalen = buff_len;
6954
6955         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6956         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6957
6958         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
6959         cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
6960
6961         status = i40e_asq_send_command(hw, &desc, filter,
6962                                        buff_len, cmd_details);
6963
6964         return status;
6965 }
6966
6967 /**
6968  * i40e_aq_get_wake_event_reason
6969  * @hw: pointer to the hw struct
6970  * @wake_reason: return value, index of matching filter
6971  * @cmd_details: pointer to command details structure or NULL
6972  *
6973  * Get information for the reason of a Wake Up event
6974  **/
6975 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
6976                                 u16 *wake_reason,
6977                                 struct i40e_asq_cmd_details *cmd_details)
6978 {
6979         struct i40e_aq_desc desc;
6980         struct i40e_aqc_get_wake_reason_completion *resp =
6981                 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
6982         enum i40e_status_code status;
6983
6984         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
6985
6986         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6987
6988         if (status == I40E_SUCCESS)
6989                 *wake_reason = LE16_TO_CPU(resp->wake_reason);
6990
6991         return status;
6992 }
6993
6994 /**
6995 * i40e_aq_clear_all_wol_filters
6996 * @hw: pointer to the hw struct
6997 * @cmd_details: pointer to command details structure or NULL
6998 *
6999 * Get information for the reason of a Wake Up event
7000 **/
7001 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw,
7002         struct i40e_asq_cmd_details *cmd_details)
7003 {
7004         struct i40e_aq_desc desc;
7005         enum i40e_status_code status;
7006
7007         i40e_fill_default_direct_cmd_desc(&desc,
7008                                           i40e_aqc_opc_clear_all_wol_filters);
7009
7010         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7011
7012         return status;
7013 }
7014 #endif /* X722_SUPPORT */