drivers/net/i40e/base/i40e_common.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001-2020 Intel Corporation
   3  */
   4
   5 #include "i40e_type.h"
   6 #include "i40e_adminq.h"
   7 #include "i40e_prototype.h"
   8 #include "virtchnl.h"
   9
  10 /**
  11  * i40e_set_mac_type - Sets MAC type
  12  * @hw: pointer to the HW structure
  13  *
  14  * This function sets the mac type of the adapter based on the
  15  * vendor ID and device ID stored in the hw structure.
  16  **/
  17 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  18 {
  19         enum i40e_status_code status = I40E_SUCCESS;
  20
  21         DEBUGFUNC("i40e_set_mac_type\n");
  22
  23         if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
  24                 switch (hw->device_id) {
  25                 case I40E_DEV_ID_SFP_XL710:
  26                 case I40E_DEV_ID_QEMU:
  27                 case I40E_DEV_ID_KX_B:
  28                 case I40E_DEV_ID_KX_C:
  29                 case I40E_DEV_ID_QSFP_A:
  30                 case I40E_DEV_ID_QSFP_B:
  31                 case I40E_DEV_ID_QSFP_C:
  32                 case I40E_DEV_ID_10G_BASE_T:
  33                 case I40E_DEV_ID_10G_BASE_T4:
  34                 case I40E_DEV_ID_10G_BASE_T_BC:
  35                 case I40E_DEV_ID_10G_B:
  36                 case I40E_DEV_ID_10G_SFP:
  37                 case I40E_DEV_ID_5G_BASE_T_BC:
  38                 case I40E_DEV_ID_20G_KR2:
  39                 case I40E_DEV_ID_20G_KR2_A:
  40                 case I40E_DEV_ID_25G_B:
  41                 case I40E_DEV_ID_25G_SFP28:
  42                 case I40E_DEV_ID_X710_N3000:
  43                 case I40E_DEV_ID_XXV710_N3000:
  44                         hw->mac.type = I40E_MAC_XL710;
  45                         break;
  46 #ifdef X722_A0_SUPPORT
  47                 case I40E_DEV_ID_X722_A0:
  48 #endif
  49                 case I40E_DEV_ID_KX_X722:
  50                 case I40E_DEV_ID_QSFP_X722:
  51                 case I40E_DEV_ID_SFP_X722:
  52                 case I40E_DEV_ID_1G_BASE_T_X722:
  53                 case I40E_DEV_ID_10G_BASE_T_X722:
  54                 case I40E_DEV_ID_SFP_I_X722:
  55                         hw->mac.type = I40E_MAC_X722;
  56                         break;
  57 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  58                 case I40E_DEV_ID_X722_VF:
  59 #ifdef X722_A0_SUPPORT
  60                 case I40E_DEV_ID_X722_A0_VF:
  61 #endif
  62                         hw->mac.type = I40E_MAC_X722_VF;
  63                         break;
  64 #endif /* INTEGRATED_VF || VF_DRIVER */
  65 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  66                 case I40E_DEV_ID_VF:
  67                 case I40E_DEV_ID_VF_HV:
  68                 case I40E_DEV_ID_ADAPTIVE_VF:
  69                         hw->mac.type = I40E_MAC_VF;
  70                         break;
  71 #endif
  72                 default:
  73                         hw->mac.type = I40E_MAC_GENERIC;
  74                         break;
  75                 }
  76         } else {
  77                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
  78         }
  79
  80         DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
  81                   hw->mac.type, status);
  82         return status;
  83 }
  84
  85 /**
  86  * i40e_aq_str - convert AQ err code to a string
  87  * @hw: pointer to the HW structure
  88  * @aq_err: the AQ error code to convert
  89  **/
  90 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
  91 {
  92         switch (aq_err) {
  93         case I40E_AQ_RC_OK:
  94                 return "OK";
  95         case I40E_AQ_RC_EPERM:
  96                 return "I40E_AQ_RC_EPERM";
  97         case I40E_AQ_RC_ENOENT:
  98                 return "I40E_AQ_RC_ENOENT";
  99         case I40E_AQ_RC_ESRCH:
 100                 return "I40E_AQ_RC_ESRCH";
 101         case I40E_AQ_RC_EINTR:
 102                 return "I40E_AQ_RC_EINTR";
 103         case I40E_AQ_RC_EIO:
 104                 return "I40E_AQ_RC_EIO";
 105         case I40E_AQ_RC_ENXIO:
 106                 return "I40E_AQ_RC_ENXIO";
 107         case I40E_AQ_RC_E2BIG:
 108                 return "I40E_AQ_RC_E2BIG";
 109         case I40E_AQ_RC_EAGAIN:
 110                 return "I40E_AQ_RC_EAGAIN";
 111         case I40E_AQ_RC_ENOMEM:
 112                 return "I40E_AQ_RC_ENOMEM";
 113         case I40E_AQ_RC_EACCES:
 114                 return "I40E_AQ_RC_EACCES";
 115         case I40E_AQ_RC_EFAULT:
 116                 return "I40E_AQ_RC_EFAULT";
 117         case I40E_AQ_RC_EBUSY:
 118                 return "I40E_AQ_RC_EBUSY";
 119         case I40E_AQ_RC_EEXIST:
 120                 return "I40E_AQ_RC_EEXIST";
 121         case I40E_AQ_RC_EINVAL:
 122                 return "I40E_AQ_RC_EINVAL";
 123         case I40E_AQ_RC_ENOTTY:
 124                 return "I40E_AQ_RC_ENOTTY";
 125         case I40E_AQ_RC_ENOSPC:
 126                 return "I40E_AQ_RC_ENOSPC";
 127         case I40E_AQ_RC_ENOSYS:
 128                 return "I40E_AQ_RC_ENOSYS";
 129         case I40E_AQ_RC_ERANGE:
 130                 return "I40E_AQ_RC_ERANGE";
 131         case I40E_AQ_RC_EFLUSHED:
 132                 return "I40E_AQ_RC_EFLUSHED";
 133         case I40E_AQ_RC_BAD_ADDR:
 134                 return "I40E_AQ_RC_BAD_ADDR";
 135         case I40E_AQ_RC_EMODE:
 136                 return "I40E_AQ_RC_EMODE";
 137         case I40E_AQ_RC_EFBIG:
 138                 return "I40E_AQ_RC_EFBIG";
 139         }
 140
 141         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 142         return hw->err_str;
 143 }
 144
 145 /**
 146  * i40e_stat_str - convert status err code to a string
 147  * @hw: pointer to the HW structure
 148  * @stat_err: the status error code to convert
 149  **/
 150 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
 151 {
 152         switch (stat_err) {
 153         case I40E_SUCCESS:
 154                 return "OK";
 155         case I40E_ERR_NVM:
 156                 return "I40E_ERR_NVM";
 157         case I40E_ERR_NVM_CHECKSUM:
 158                 return "I40E_ERR_NVM_CHECKSUM";
 159         case I40E_ERR_PHY:
 160                 return "I40E_ERR_PHY";
 161         case I40E_ERR_CONFIG:
 162                 return "I40E_ERR_CONFIG";
 163         case I40E_ERR_PARAM:
 164                 return "I40E_ERR_PARAM";
 165         case I40E_ERR_MAC_TYPE:
 166                 return "I40E_ERR_MAC_TYPE";
 167         case I40E_ERR_UNKNOWN_PHY:
 168                 return "I40E_ERR_UNKNOWN_PHY";
 169         case I40E_ERR_LINK_SETUP:
 170                 return "I40E_ERR_LINK_SETUP";
 171         case I40E_ERR_ADAPTER_STOPPED:
 172                 return "I40E_ERR_ADAPTER_STOPPED";
 173         case I40E_ERR_INVALID_MAC_ADDR:
 174                 return "I40E_ERR_INVALID_MAC_ADDR";
 175         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 176                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 177         case I40E_ERR_MASTER_REQUESTS_PENDING:
 178                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 179         case I40E_ERR_INVALID_LINK_SETTINGS:
 180                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 181         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 182                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 183         case I40E_ERR_RESET_FAILED:
 184                 return "I40E_ERR_RESET_FAILED";
 185         case I40E_ERR_SWFW_SYNC:
 186                 return "I40E_ERR_SWFW_SYNC";
 187         case I40E_ERR_NO_AVAILABLE_VSI:
 188                 return "I40E_ERR_NO_AVAILABLE_VSI";
 189         case I40E_ERR_NO_MEMORY:
 190                 return "I40E_ERR_NO_MEMORY";
 191         case I40E_ERR_BAD_PTR:
 192                 return "I40E_ERR_BAD_PTR";
 193         case I40E_ERR_RING_FULL:
 194                 return "I40E_ERR_RING_FULL";
 195         case I40E_ERR_INVALID_PD_ID:
 196                 return "I40E_ERR_INVALID_PD_ID";
 197         case I40E_ERR_INVALID_QP_ID:
 198                 return "I40E_ERR_INVALID_QP_ID";
 199         case I40E_ERR_INVALID_CQ_ID:
 200                 return "I40E_ERR_INVALID_CQ_ID";
 201         case I40E_ERR_INVALID_CEQ_ID:
 202                 return "I40E_ERR_INVALID_CEQ_ID";
 203         case I40E_ERR_INVALID_AEQ_ID:
 204                 return "I40E_ERR_INVALID_AEQ_ID";
 205         case I40E_ERR_INVALID_SIZE:
 206                 return "I40E_ERR_INVALID_SIZE";
 207         case I40E_ERR_INVALID_ARP_INDEX:
 208                 return "I40E_ERR_INVALID_ARP_INDEX";
 209         case I40E_ERR_INVALID_FPM_FUNC_ID:
 210                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 211         case I40E_ERR_QP_INVALID_MSG_SIZE:
 212                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 213         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 214                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 215         case I40E_ERR_INVALID_FRAG_COUNT:
 216                 return "I40E_ERR_INVALID_FRAG_COUNT";
 217         case I40E_ERR_QUEUE_EMPTY:
 218                 return "I40E_ERR_QUEUE_EMPTY";
 219         case I40E_ERR_INVALID_ALIGNMENT:
 220                 return "I40E_ERR_INVALID_ALIGNMENT";
 221         case I40E_ERR_FLUSHED_QUEUE:
 222                 return "I40E_ERR_FLUSHED_QUEUE";
 223         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 224                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 225         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 226                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 227         case I40E_ERR_TIMEOUT:
 228                 return "I40E_ERR_TIMEOUT";
 229         case I40E_ERR_OPCODE_MISMATCH:
 230                 return "I40E_ERR_OPCODE_MISMATCH";
 231         case I40E_ERR_CQP_COMPL_ERROR:
 232                 return "I40E_ERR_CQP_COMPL_ERROR";
 233         case I40E_ERR_INVALID_VF_ID:
 234                 return "I40E_ERR_INVALID_VF_ID";
 235         case I40E_ERR_INVALID_HMCFN_ID:
 236                 return "I40E_ERR_INVALID_HMCFN_ID";
 237         case I40E_ERR_BACKING_PAGE_ERROR:
 238                 return "I40E_ERR_BACKING_PAGE_ERROR";
 239         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 240                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 241         case I40E_ERR_INVALID_PBLE_INDEX:
 242                 return "I40E_ERR_INVALID_PBLE_INDEX";
 243         case I40E_ERR_INVALID_SD_INDEX:
 244                 return "I40E_ERR_INVALID_SD_INDEX";
 245         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 246                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 247         case I40E_ERR_INVALID_SD_TYPE:
 248                 return "I40E_ERR_INVALID_SD_TYPE";
 249         case I40E_ERR_MEMCPY_FAILED:
 250                 return "I40E_ERR_MEMCPY_FAILED";
 251         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 252                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 253         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 254                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 255         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 256                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 257         case I40E_ERR_SRQ_ENABLED:
 258                 return "I40E_ERR_SRQ_ENABLED";
 259         case I40E_ERR_ADMIN_QUEUE_ERROR:
 260                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 261         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 262                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 263         case I40E_ERR_BUF_TOO_SHORT:
 264                 return "I40E_ERR_BUF_TOO_SHORT";
 265         case I40E_ERR_ADMIN_QUEUE_FULL:
 266                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 267         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 268                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 269         case I40E_ERR_BAD_IWARP_CQE:
 270                 return "I40E_ERR_BAD_IWARP_CQE";
 271         case I40E_ERR_NVM_BLANK_MODE:
 272                 return "I40E_ERR_NVM_BLANK_MODE";
 273         case I40E_ERR_NOT_IMPLEMENTED:
 274                 return "I40E_ERR_NOT_IMPLEMENTED";
 275         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 276                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 277         case I40E_ERR_DIAG_TEST_FAILED:
 278                 return "I40E_ERR_DIAG_TEST_FAILED";
 279         case I40E_ERR_NOT_READY:
 280                 return "I40E_ERR_NOT_READY";
 281         case I40E_NOT_SUPPORTED:
 282                 return "I40E_NOT_SUPPORTED";
 283         case I40E_ERR_FIRMWARE_API_VERSION:
 284                 return "I40E_ERR_FIRMWARE_API_VERSION";
 285         case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR:
 286                 return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR";
 287         }
 288
 289         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 290         return hw->err_str;
 291 }
 292
 293 /**
 294  * i40e_debug_aq
 295  * @hw: debug mask related to admin queue
 296  * @mask: debug mask
 297  * @desc: pointer to admin queue descriptor
 298  * @buffer: pointer to command buffer
 299  * @buf_len: max length of buffer
 300  *
 301  * Dumps debug log about adminq command with descriptor contents.
 302  **/
 303 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 304                    void *buffer, u16 buf_len)
 305 {
 306         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 307         u32 effective_mask = hw->debug_mask & mask;
 308         u8 *buf = (u8 *)buffer;
 309         u16 len;
 310         u16 i;
 311
 312         if (!effective_mask || !desc)
 313                 return;
 314
 315         len = LE16_TO_CPU(aq_desc->datalen);
 316
 317         i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
 318                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 319                    LE16_TO_CPU(aq_desc->opcode),
 320                    LE16_TO_CPU(aq_desc->flags),
 321                    LE16_TO_CPU(aq_desc->datalen),
 322                    LE16_TO_CPU(aq_desc->retval));
 323         i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
 324                    "\tcookie (h,l) 0x%08X 0x%08X\n",
 325                    LE32_TO_CPU(aq_desc->cookie_high),
 326                    LE32_TO_CPU(aq_desc->cookie_low));
 327         i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
 328                    "\tparam (0,1)  0x%08X 0x%08X\n",
 329                    LE32_TO_CPU(aq_desc->params.internal.param0),
 330                    LE32_TO_CPU(aq_desc->params.internal.param1));
 331         i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
 332                    "\taddr (h,l)   0x%08X 0x%08X\n",
 333                    LE32_TO_CPU(aq_desc->params.external.addr_high),
 334                    LE32_TO_CPU(aq_desc->params.external.addr_low));
 335
 336         if (buffer && (buf_len != 0) && (len != 0) &&
 337             (effective_mask & I40E_DEBUG_AQ_DESC_BUFFER)) {
 338                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 339                 if (buf_len < len)
 340                         len = buf_len;
 341                 /* write the full 16-byte chunks */
 342                 for (i = 0; i < (len - 16); i += 16)
 343                         i40e_debug(hw, mask,
 344                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 345                                    i, buf[i], buf[i+1], buf[i+2], buf[i+3],
 346                                    buf[i+4], buf[i+5], buf[i+6], buf[i+7],
 347                                    buf[i+8], buf[i+9], buf[i+10], buf[i+11],
 348                                    buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
 349                 /* the most we could have left is 16 bytes, pad with zeros */
 350                 if (i < len) {
 351                         char d_buf[16];
 352                         int j, i_sav;
 353
 354                         i_sav = i;
 355                         memset(d_buf, 0, sizeof(d_buf));
 356                         for (j = 0; i < len; j++, i++)
 357                                 d_buf[j] = buf[i];
 358                         i40e_debug(hw, mask,
 359                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 360                                    i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
 361                                    d_buf[4], d_buf[5], d_buf[6], d_buf[7],
 362                                    d_buf[8], d_buf[9], d_buf[10], d_buf[11],
 363                                    d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
 364                 }
 365         }
 366 }
 367
 368 /**
 369  * i40e_check_asq_alive
 370  * @hw: pointer to the hw struct
 371  *
 372  * Returns true if Queue is enabled else false.
 373  **/
 374 bool i40e_check_asq_alive(struct i40e_hw *hw)
 375 {
 376         if (hw->aq.asq.len)
 377 #ifdef PF_DRIVER
 378 #ifdef INTEGRATED_VF
 379                 if (!i40e_is_vf(hw))
 380                         return !!(rd32(hw, hw->aq.asq.len) &
 381                                 I40E_PF_ATQLEN_ATQENABLE_MASK);
 382 #else
 383                 return !!(rd32(hw, hw->aq.asq.len) &
 384                         I40E_PF_ATQLEN_ATQENABLE_MASK);
 385 #endif /* INTEGRATED_VF */
 386 #endif /* PF_DRIVER */
 387 #ifdef VF_DRIVER
 388 #ifdef INTEGRATED_VF
 389                 if (i40e_is_vf(hw))
 390                         return !!(rd32(hw, hw->aq.asq.len) &
 391                                 I40E_VF_ATQLEN1_ATQENABLE_MASK);
 392 #else
 393                 return !!(rd32(hw, hw->aq.asq.len) &
 394                         I40E_VF_ATQLEN1_ATQENABLE_MASK);
 395 #endif /* INTEGRATED_VF */
 396 #endif /* VF_DRIVER */
 397         return false;
 398 }
 399
 400 /**
 401  * i40e_aq_queue_shutdown
 402  * @hw: pointer to the hw struct
 403  * @unloading: is the driver unloading itself
 404  *
 405  * Tell the Firmware that we're shutting down the AdminQ and whether
 406  * or not the driver is unloading as well.
 407  **/
 408 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
 409                                              bool unloading)
 410 {
 411         struct i40e_aq_desc desc;
 412         struct i40e_aqc_queue_shutdown *cmd =
 413                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 414         enum i40e_status_code status;
 415
 416         i40e_fill_default_direct_cmd_desc(&desc,
 417                                           i40e_aqc_opc_queue_shutdown);
 418
 419         if (unloading)
 420                 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
 421         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 422
 423         return status;
 424 }
 425
 426 /**
 427  * i40e_aq_get_set_rss_lut
 428  * @hw: pointer to the hardware structure
 429  * @vsi_id: vsi fw index
 430  * @pf_lut: for PF table set true, for VSI table set false
 431  * @lut: pointer to the lut buffer provided by the caller
 432  * @lut_size: size of the lut buffer
 433  * @set: set true to set the table, false to get the table
 434  *
 435  * Internal function to get or set RSS look up table
 436  **/
 437 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 438                                                      u16 vsi_id, bool pf_lut,
 439                                                      u8 *lut, u16 lut_size,
 440                                                      bool set)
 441 {
 442         enum i40e_status_code status;
 443         struct i40e_aq_desc desc;
 444         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 445                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 446
 447         if (set)
 448                 i40e_fill_default_direct_cmd_desc(&desc,
 449                                                   i40e_aqc_opc_set_rss_lut);
 450         else
 451                 i40e_fill_default_direct_cmd_desc(&desc,
 452                                                   i40e_aqc_opc_get_rss_lut);
 453
 454         /* Indirect command */
 455         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 456         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 457
 458         cmd_resp->vsi_id =
 459                         CPU_TO_LE16((u16)((vsi_id <<
 460                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 461                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 462         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 463
 464         if (pf_lut)
 465                 cmd_resp->flags |= CPU_TO_LE16((u16)
 466                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 467                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 468                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 469         else
 470                 cmd_resp->flags |= CPU_TO_LE16((u16)
 471                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 472                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 473                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 474
 475         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 476
 477         return status;
 478 }
 479
 480 /**
 481  * i40e_aq_get_rss_lut
 482  * @hw: pointer to the hardware structure
 483  * @vsi_id: vsi fw index
 484  * @pf_lut: for PF table set true, for VSI table set false
 485  * @lut: pointer to the lut buffer provided by the caller
 486  * @lut_size: size of the lut buffer
 487  *
 488  * get the RSS lookup table, PF or VSI type
 489  **/
 490 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 491                                           bool pf_lut, u8 *lut, u16 lut_size)
 492 {
 493         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 494                                        false);
 495 }
 496
 497 /**
 498  * i40e_aq_set_rss_lut
 499  * @hw: pointer to the hardware structure
 500  * @vsi_id: vsi fw index
 501  * @pf_lut: for PF table set true, for VSI table set false
 502  * @lut: pointer to the lut buffer provided by the caller
 503  * @lut_size: size of the lut buffer
 504  *
 505  * set the RSS lookup table, PF or VSI type
 506  **/
 507 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 508                                           bool pf_lut, u8 *lut, u16 lut_size)
 509 {
 510         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
 511 }
 512
 513 /**
 514  * i40e_aq_get_set_rss_key
 515  * @hw: pointer to the hw struct
 516  * @vsi_id: vsi fw index
 517  * @key: pointer to key info struct
 518  * @set: set true to set the key, false to get the key
 519  *
 520  * get the RSS key per VSI
 521  **/
 522 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 523                                       u16 vsi_id,
 524                                       struct i40e_aqc_get_set_rss_key_data *key,
 525                                       bool set)
 526 {
 527         enum i40e_status_code status;
 528         struct i40e_aq_desc desc;
 529         struct i40e_aqc_get_set_rss_key *cmd_resp =
 530                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 531         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 532
 533         if (set)
 534                 i40e_fill_default_direct_cmd_desc(&desc,
 535                                                   i40e_aqc_opc_set_rss_key);
 536         else
 537                 i40e_fill_default_direct_cmd_desc(&desc,
 538                                                   i40e_aqc_opc_get_rss_key);
 539
 540         /* Indirect command */
 541         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 542         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 543
 544         cmd_resp->vsi_id =
 545                         CPU_TO_LE16((u16)((vsi_id <<
 546                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 547                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 548         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 549
 550         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 551
 552         return status;
 553 }
 554
 555 /**
 556  * i40e_aq_get_rss_key
 557  * @hw: pointer to the hw struct
 558  * @vsi_id: vsi fw index
 559  * @key: pointer to key info struct
 560  *
 561  **/
 562 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
 563                                       u16 vsi_id,
 564                                       struct i40e_aqc_get_set_rss_key_data *key)
 565 {
 566         return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
 567 }
 568
 569 /**
 570  * i40e_aq_set_rss_key
 571  * @hw: pointer to the hw struct
 572  * @vsi_id: vsi fw index
 573  * @key: pointer to key info struct
 574  *
 575  * set the RSS key per VSI
 576  **/
 577 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
 578                                       u16 vsi_id,
 579                                       struct i40e_aqc_get_set_rss_key_data *key)
 580 {
 581         return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
 582 }
 583
 584 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 585  * hardware to a bit-field that can be used by SW to more easily determine the
 586  * packet type.
 587  *
 588  * Macros are used to shorten the table lines and make this table human
 589  * readable.
 590  *
 591  * We store the PTYPE in the top byte of the bit field - this is just so that
 592  * we can check that the table doesn't have a row missing, as the index into
 593  * the table should be the PTYPE.
 594  *
 595  * Typical work flow:
 596  *
 597  * IF NOT i40e_ptype_lookup[ptype].known
 598  * THEN
 599  *      Packet is unknown
 600  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 601  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 602  * ELSE
 603  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 604  * ENDIF
 605  */
 606
 607 /* macro to make the table lines short */
 608 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 609         {       PTYPE, \
 610                 1, \
 611                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 612                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 613                 I40E_RX_PTYPE_##OUTER_FRAG, \
 614                 I40E_RX_PTYPE_TUNNEL_##T, \
 615                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 616                 I40E_RX_PTYPE_##TEF, \
 617                 I40E_RX_PTYPE_INNER_PROT_##I, \
 618                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 619
 620 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 621                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 622
 623 /* shorter macros makes the table fit but are terse */
 624 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 625 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 626 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 627
 628 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 629 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 630         /* L2 Packet types */
 631         I40E_PTT_UNUSED_ENTRY(0),
 632         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 633         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 634         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 635         I40E_PTT_UNUSED_ENTRY(4),
 636         I40E_PTT_UNUSED_ENTRY(5),
 637         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 638         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 639         I40E_PTT_UNUSED_ENTRY(8),
 640         I40E_PTT_UNUSED_ENTRY(9),
 641         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 642         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 643         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 644         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 645         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 646         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 647         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 648         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 649         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 650         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 651         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 652         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 653
 654         /* Non Tunneled IPv4 */
 655         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 656         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 657         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 658         I40E_PTT_UNUSED_ENTRY(25),
 659         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 660         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 661         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 662
 663         /* IPv4 --> IPv4 */
 664         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 665         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 666         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 667         I40E_PTT_UNUSED_ENTRY(32),
 668         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 669         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 670         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 671
 672         /* IPv4 --> IPv6 */
 673         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 674         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 675         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 676         I40E_PTT_UNUSED_ENTRY(39),
 677         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 678         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 679         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 680
 681         /* IPv4 --> GRE/NAT */
 682         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 683
 684         /* IPv4 --> GRE/NAT --> IPv4 */
 685         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 686         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 687         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 688         I40E_PTT_UNUSED_ENTRY(47),
 689         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 690         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 691         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 692
 693         /* IPv4 --> GRE/NAT --> IPv6 */
 694         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 695         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 696         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 697         I40E_PTT_UNUSED_ENTRY(54),
 698         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 699         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 700         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 701
 702         /* IPv4 --> GRE/NAT --> MAC */
 703         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 704
 705         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 706         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 707         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 708         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 709         I40E_PTT_UNUSED_ENTRY(62),
 710         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 711         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 712         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 713
 714         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 715         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 716         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 717         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 718         I40E_PTT_UNUSED_ENTRY(69),
 719         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 720         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 721         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 722
 723         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 724         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 725
 726         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 727         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 728         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 729         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 730         I40E_PTT_UNUSED_ENTRY(77),
 731         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 732         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 733         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 734
 735         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 736         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 737         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 738         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 739         I40E_PTT_UNUSED_ENTRY(84),
 740         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 741         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 742         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 743
 744         /* Non Tunneled IPv6 */
 745         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 746         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 747         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
 748         I40E_PTT_UNUSED_ENTRY(91),
 749         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 750         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 751         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 752
 753         /* IPv6 --> IPv4 */
 754         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 755         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 756         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 757         I40E_PTT_UNUSED_ENTRY(98),
 758         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 759         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 760         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 761
 762         /* IPv6 --> IPv6 */
 763         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 764         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 765         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 766         I40E_PTT_UNUSED_ENTRY(105),
 767         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 768         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 769         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 770
 771         /* IPv6 --> GRE/NAT */
 772         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 773
 774         /* IPv6 --> GRE/NAT -> IPv4 */
 775         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 776         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 777         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 778         I40E_PTT_UNUSED_ENTRY(113),
 779         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 780         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 781         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 782
 783         /* IPv6 --> GRE/NAT -> IPv6 */
 784         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 785         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 786         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 787         I40E_PTT_UNUSED_ENTRY(120),
 788         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 789         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 790         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 791
 792         /* IPv6 --> GRE/NAT -> MAC */
 793         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 794
 795         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 796         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 797         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 798         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 799         I40E_PTT_UNUSED_ENTRY(128),
 800         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 801         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 802         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 803
 804         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 805         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 806         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 807         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 808         I40E_PTT_UNUSED_ENTRY(135),
 809         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 810         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 811         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 812
 813         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 814         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 815
 816         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 817         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 818         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 819         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 820         I40E_PTT_UNUSED_ENTRY(143),
 821         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 822         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 823         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 824
 825         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 826         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 827         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 828         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 829         I40E_PTT_UNUSED_ENTRY(150),
 830         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 831         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 832         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 833
 834         /* unused entries */
 835         I40E_PTT_UNUSED_ENTRY(154),
 836         I40E_PTT_UNUSED_ENTRY(155),
 837         I40E_PTT_UNUSED_ENTRY(156),
 838         I40E_PTT_UNUSED_ENTRY(157),
 839         I40E_PTT_UNUSED_ENTRY(158),
 840         I40E_PTT_UNUSED_ENTRY(159),
 841
 842         I40E_PTT_UNUSED_ENTRY(160),
 843         I40E_PTT_UNUSED_ENTRY(161),
 844         I40E_PTT_UNUSED_ENTRY(162),
 845         I40E_PTT_UNUSED_ENTRY(163),
 846         I40E_PTT_UNUSED_ENTRY(164),
 847         I40E_PTT_UNUSED_ENTRY(165),
 848         I40E_PTT_UNUSED_ENTRY(166),
 849         I40E_PTT_UNUSED_ENTRY(167),
 850         I40E_PTT_UNUSED_ENTRY(168),
 851         I40E_PTT_UNUSED_ENTRY(169),
 852
 853         I40E_PTT_UNUSED_ENTRY(170),
 854         I40E_PTT_UNUSED_ENTRY(171),
 855         I40E_PTT_UNUSED_ENTRY(172),
 856         I40E_PTT_UNUSED_ENTRY(173),
 857         I40E_PTT_UNUSED_ENTRY(174),
 858         I40E_PTT_UNUSED_ENTRY(175),
 859         I40E_PTT_UNUSED_ENTRY(176),
 860         I40E_PTT_UNUSED_ENTRY(177),
 861         I40E_PTT_UNUSED_ENTRY(178),
 862         I40E_PTT_UNUSED_ENTRY(179),
 863
 864         I40E_PTT_UNUSED_ENTRY(180),
 865         I40E_PTT_UNUSED_ENTRY(181),
 866         I40E_PTT_UNUSED_ENTRY(182),
 867         I40E_PTT_UNUSED_ENTRY(183),
 868         I40E_PTT_UNUSED_ENTRY(184),
 869         I40E_PTT_UNUSED_ENTRY(185),
 870         I40E_PTT_UNUSED_ENTRY(186),
 871         I40E_PTT_UNUSED_ENTRY(187),
 872         I40E_PTT_UNUSED_ENTRY(188),
 873         I40E_PTT_UNUSED_ENTRY(189),
 874
 875         I40E_PTT_UNUSED_ENTRY(190),
 876         I40E_PTT_UNUSED_ENTRY(191),
 877         I40E_PTT_UNUSED_ENTRY(192),
 878         I40E_PTT_UNUSED_ENTRY(193),
 879         I40E_PTT_UNUSED_ENTRY(194),
 880         I40E_PTT_UNUSED_ENTRY(195),
 881         I40E_PTT_UNUSED_ENTRY(196),
 882         I40E_PTT_UNUSED_ENTRY(197),
 883         I40E_PTT_UNUSED_ENTRY(198),
 884         I40E_PTT_UNUSED_ENTRY(199),
 885
 886         I40E_PTT_UNUSED_ENTRY(200),
 887         I40E_PTT_UNUSED_ENTRY(201),
 888         I40E_PTT_UNUSED_ENTRY(202),
 889         I40E_PTT_UNUSED_ENTRY(203),
 890         I40E_PTT_UNUSED_ENTRY(204),
 891         I40E_PTT_UNUSED_ENTRY(205),
 892         I40E_PTT_UNUSED_ENTRY(206),
 893         I40E_PTT_UNUSED_ENTRY(207),
 894         I40E_PTT_UNUSED_ENTRY(208),
 895         I40E_PTT_UNUSED_ENTRY(209),
 896
 897         I40E_PTT_UNUSED_ENTRY(210),
 898         I40E_PTT_UNUSED_ENTRY(211),
 899         I40E_PTT_UNUSED_ENTRY(212),
 900         I40E_PTT_UNUSED_ENTRY(213),
 901         I40E_PTT_UNUSED_ENTRY(214),
 902         I40E_PTT_UNUSED_ENTRY(215),
 903         I40E_PTT_UNUSED_ENTRY(216),
 904         I40E_PTT_UNUSED_ENTRY(217),
 905         I40E_PTT_UNUSED_ENTRY(218),
 906         I40E_PTT_UNUSED_ENTRY(219),
 907
 908         I40E_PTT_UNUSED_ENTRY(220),
 909         I40E_PTT_UNUSED_ENTRY(221),
 910         I40E_PTT_UNUSED_ENTRY(222),
 911         I40E_PTT_UNUSED_ENTRY(223),
 912         I40E_PTT_UNUSED_ENTRY(224),
 913         I40E_PTT_UNUSED_ENTRY(225),
 914         I40E_PTT_UNUSED_ENTRY(226),
 915         I40E_PTT_UNUSED_ENTRY(227),
 916         I40E_PTT_UNUSED_ENTRY(228),
 917         I40E_PTT_UNUSED_ENTRY(229),
 918
 919         I40E_PTT_UNUSED_ENTRY(230),
 920         I40E_PTT_UNUSED_ENTRY(231),
 921         I40E_PTT_UNUSED_ENTRY(232),
 922         I40E_PTT_UNUSED_ENTRY(233),
 923         I40E_PTT_UNUSED_ENTRY(234),
 924         I40E_PTT_UNUSED_ENTRY(235),
 925         I40E_PTT_UNUSED_ENTRY(236),
 926         I40E_PTT_UNUSED_ENTRY(237),
 927         I40E_PTT_UNUSED_ENTRY(238),
 928         I40E_PTT_UNUSED_ENTRY(239),
 929
 930         I40E_PTT_UNUSED_ENTRY(240),
 931         I40E_PTT_UNUSED_ENTRY(241),
 932         I40E_PTT_UNUSED_ENTRY(242),
 933         I40E_PTT_UNUSED_ENTRY(243),
 934         I40E_PTT_UNUSED_ENTRY(244),
 935         I40E_PTT_UNUSED_ENTRY(245),
 936         I40E_PTT_UNUSED_ENTRY(246),
 937         I40E_PTT_UNUSED_ENTRY(247),
 938         I40E_PTT_UNUSED_ENTRY(248),
 939         I40E_PTT_UNUSED_ENTRY(249),
 940
 941         I40E_PTT_UNUSED_ENTRY(250),
 942         I40E_PTT_UNUSED_ENTRY(251),
 943         I40E_PTT_UNUSED_ENTRY(252),
 944         I40E_PTT_UNUSED_ENTRY(253),
 945         I40E_PTT_UNUSED_ENTRY(254),
 946         I40E_PTT_UNUSED_ENTRY(255)
 947 };
 948
 949
 950 /**
 951  * i40e_validate_mac_addr - Validate unicast MAC address
 952  * @mac_addr: pointer to MAC address
 953  *
 954  * Tests a MAC address to ensure it is a valid Individual Address
 955  **/
 956 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
 957 {
 958         enum i40e_status_code status = I40E_SUCCESS;
 959
 960         DEBUGFUNC("i40e_validate_mac_addr");
 961
 962         /* Broadcast addresses ARE multicast addresses
 963          * Make sure it is not a multicast address
 964          * Reject the zero address
 965          */
 966         if (I40E_IS_MULTICAST(mac_addr) ||
 967             (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
 968               mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
 969                 status = I40E_ERR_INVALID_MAC_ADDR;
 970
 971         return status;
 972 }
 973 #ifdef PF_DRIVER
 974
 975 /**
 976  * i40e_init_shared_code - Initialize the shared code
 977  * @hw: pointer to hardware structure
 978  *
 979  * This assigns the MAC type and PHY code and inits the NVM.
 980  * Does not touch the hardware. This function must be called prior to any
 981  * other function in the shared code. The i40e_hw structure should be
 982  * memset to 0 prior to calling this function.  The following fields in
 983  * hw structure should be filled in prior to calling this function:
 984  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
 985  * subsystem_vendor_id, and revision_id
 986  **/
 987 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
 988 {
 989         enum i40e_status_code status = I40E_SUCCESS;
 990         u32 port, ari, func_rid;
 991
 992         DEBUGFUNC("i40e_init_shared_code");
 993
 994         i40e_set_mac_type(hw);
 995
 996         switch (hw->mac.type) {
 997         case I40E_MAC_XL710:
 998         case I40E_MAC_X722:
 999                 break;
1000         default:
1001                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1002         }
1003
1004         hw->phy.get_link_info = true;
1005
1006         /* Determine port number and PF number*/
1007         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1008                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1009         hw->port = (u8)port;
1010         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1011                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1012         func_rid = rd32(hw, I40E_PF_FUNC_RID);
1013         if (ari)
1014                 hw->pf_id = (u8)(func_rid & 0xff);
1015         else
1016                 hw->pf_id = (u8)(func_rid & 0x7);
1017
1018         if (hw->mac.type == I40E_MAC_X722)
1019                 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE |
1020                              I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK;
1021         /* NVMUpdate features structure initialization */
1022         hw->nvmupd_features.major = I40E_NVMUPD_FEATURES_API_VER_MAJOR;
1023         hw->nvmupd_features.minor = I40E_NVMUPD_FEATURES_API_VER_MINOR;
1024         hw->nvmupd_features.size = sizeof(hw->nvmupd_features);
1025         i40e_memset(hw->nvmupd_features.features, 0x0,
1026                     I40E_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN *
1027                     sizeof(*hw->nvmupd_features.features),
1028                     I40E_NONDMA_MEM);
1029
1030         /* No features supported at the moment */
1031         hw->nvmupd_features.features[0] = 0;
1032
1033         status = i40e_init_nvm(hw);
1034         return status;
1035 }
1036
1037 /**
1038  * i40e_aq_mac_address_read - Retrieve the MAC addresses
1039  * @hw: pointer to the hw struct
1040  * @flags: a return indicator of what addresses were added to the addr store
1041  * @addrs: the requestor's mac addr store
1042  * @cmd_details: pointer to command details structure or NULL
1043  **/
1044 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1045                                    u16 *flags,
1046                                    struct i40e_aqc_mac_address_read_data *addrs,
1047                                    struct i40e_asq_cmd_details *cmd_details)
1048 {
1049         struct i40e_aq_desc desc;
1050         struct i40e_aqc_mac_address_read *cmd_data =
1051                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1052         enum i40e_status_code status;
1053
1054         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1055         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1056
1057         status = i40e_asq_send_command(hw, &desc, addrs,
1058                                        sizeof(*addrs), cmd_details);
1059         *flags = LE16_TO_CPU(cmd_data->command_flags);
1060
1061         return status;
1062 }
1063
1064 /**
1065  * i40e_aq_mac_address_write - Change the MAC addresses
1066  * @hw: pointer to the hw struct
1067  * @flags: indicates which MAC to be written
1068  * @mac_addr: address to write
1069  * @cmd_details: pointer to command details structure or NULL
1070  **/
1071 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1072                                     u16 flags, u8 *mac_addr,
1073                                     struct i40e_asq_cmd_details *cmd_details)
1074 {
1075         struct i40e_aq_desc desc;
1076         struct i40e_aqc_mac_address_write *cmd_data =
1077                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1078         enum i40e_status_code status;
1079
1080         i40e_fill_default_direct_cmd_desc(&desc,
1081                                           i40e_aqc_opc_mac_address_write);
1082         cmd_data->command_flags = CPU_TO_LE16(flags);
1083         cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1084         cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1085                                         ((u32)mac_addr[3] << 16) |
1086                                         ((u32)mac_addr[4] << 8) |
1087                                         mac_addr[5]);
1088
1089         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1090
1091         return status;
1092 }
1093
1094 /**
1095  * i40e_get_mac_addr - get MAC address
1096  * @hw: pointer to the HW structure
1097  * @mac_addr: pointer to MAC address
1098  *
1099  * Reads the adapter's MAC address from register
1100  **/
1101 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1102 {
1103         struct i40e_aqc_mac_address_read_data addrs;
1104         enum i40e_status_code status;
1105         u16 flags = 0;
1106
1107         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1108
1109         if (flags & I40E_AQC_LAN_ADDR_VALID)
1110                 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1111                         I40E_NONDMA_TO_NONDMA);
1112
1113         return status;
1114 }
1115
1116 /**
1117  * i40e_get_port_mac_addr - get Port MAC address
1118  * @hw: pointer to the HW structure
1119  * @mac_addr: pointer to Port MAC address
1120  *
1121  * Reads the adapter's Port MAC address
1122  **/
1123 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1124 {
1125         struct i40e_aqc_mac_address_read_data addrs;
1126         enum i40e_status_code status;
1127         u16 flags = 0;
1128
1129         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1130         if (status)
1131                 return status;
1132
1133         if (flags & I40E_AQC_PORT_ADDR_VALID)
1134                 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1135                         I40E_NONDMA_TO_NONDMA);
1136         else
1137                 status = I40E_ERR_INVALID_MAC_ADDR;
1138
1139         return status;
1140 }
1141
1142 /**
1143  * i40e_pre_tx_queue_cfg - pre tx queue configure
1144  * @hw: pointer to the HW structure
1145  * @queue: target pf queue index
1146  * @enable: state change request
1147  *
1148  * Handles hw requirement to indicate intention to enable
1149  * or disable target queue.
1150  **/
1151 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1152 {
1153         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1154         u32 reg_block = 0;
1155         u32 reg_val;
1156
1157         if (abs_queue_idx >= 128) {
1158                 reg_block = abs_queue_idx / 128;
1159                 abs_queue_idx %= 128;
1160         }
1161
1162         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1163         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1164         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1165
1166         if (enable)
1167                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1168         else
1169                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1170
1171         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1172 }
1173
1174 /**
1175  * i40e_get_san_mac_addr - get SAN MAC address
1176  * @hw: pointer to the HW structure
1177  * @mac_addr: pointer to SAN MAC address
1178  *
1179  * Reads the adapter's SAN MAC address from NVM
1180  **/
1181 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1182                                             u8 *mac_addr)
1183 {
1184         struct i40e_aqc_mac_address_read_data addrs;
1185         enum i40e_status_code status;
1186         u16 flags = 0;
1187
1188         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1189         if (status)
1190                 return status;
1191
1192         if (flags & I40E_AQC_SAN_ADDR_VALID)
1193                 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac),
1194                         I40E_NONDMA_TO_NONDMA);
1195         else
1196                 status = I40E_ERR_INVALID_MAC_ADDR;
1197
1198         return status;
1199 }
1200
1201 /**
1202  *  i40e_read_pba_string - Reads part number string from EEPROM
1203  *  @hw: pointer to hardware structure
1204  *  @pba_num: stores the part number string from the EEPROM
1205  *  @pba_num_size: part number string buffer length
1206  *
1207  *  Reads the part number string from the EEPROM.
1208  **/
1209 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1210                                             u32 pba_num_size)
1211 {
1212         enum i40e_status_code status = I40E_SUCCESS;
1213         u16 pba_word = 0;
1214         u16 pba_size = 0;
1215         u16 pba_ptr = 0;
1216         u16 i = 0;
1217
1218         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1219         if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1220                 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1221                 return status;
1222         }
1223
1224         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1225         if (status != I40E_SUCCESS) {
1226                 DEBUGOUT("Failed to read PBA Block pointer.\n");
1227                 return status;
1228         }
1229
1230         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1231         if (status != I40E_SUCCESS) {
1232                 DEBUGOUT("Failed to read PBA Block size.\n");
1233                 return status;
1234         }
1235
1236         /* Subtract one to get PBA word count (PBA Size word is included in
1237          * total size)
1238          */
1239         pba_size--;
1240         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1241                 DEBUGOUT("Buffer to small for PBA data.\n");
1242                 return I40E_ERR_PARAM;
1243         }
1244
1245         for (i = 0; i < pba_size; i++) {
1246                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1247                 if (status != I40E_SUCCESS) {
1248                         DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1249                         return status;
1250                 }
1251
1252                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1253                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1254         }
1255         pba_num[(pba_size * 2)] = '\0';
1256
1257         return status;
1258 }
1259
1260 /**
1261  * i40e_get_media_type - Gets media type
1262  * @hw: pointer to the hardware structure
1263  **/
1264 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1265 {
1266         enum i40e_media_type media;
1267
1268         switch (hw->phy.link_info.phy_type) {
1269         case I40E_PHY_TYPE_10GBASE_SR:
1270         case I40E_PHY_TYPE_10GBASE_LR:
1271         case I40E_PHY_TYPE_1000BASE_SX:
1272         case I40E_PHY_TYPE_1000BASE_LX:
1273         case I40E_PHY_TYPE_40GBASE_SR4:
1274         case I40E_PHY_TYPE_40GBASE_LR4:
1275         case I40E_PHY_TYPE_25GBASE_LR:
1276         case I40E_PHY_TYPE_25GBASE_SR:
1277                 media = I40E_MEDIA_TYPE_FIBER;
1278                 break;
1279         case I40E_PHY_TYPE_100BASE_TX:
1280         case I40E_PHY_TYPE_1000BASE_T:
1281         case I40E_PHY_TYPE_2_5GBASE_T:
1282         case I40E_PHY_TYPE_5GBASE_T:
1283         case I40E_PHY_TYPE_10GBASE_T:
1284                 media = I40E_MEDIA_TYPE_BASET;
1285                 break;
1286         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1287         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1288         case I40E_PHY_TYPE_10GBASE_CR1:
1289         case I40E_PHY_TYPE_40GBASE_CR4:
1290         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1291         case I40E_PHY_TYPE_40GBASE_AOC:
1292         case I40E_PHY_TYPE_10GBASE_AOC:
1293         case I40E_PHY_TYPE_25GBASE_CR:
1294         case I40E_PHY_TYPE_25GBASE_AOC:
1295         case I40E_PHY_TYPE_25GBASE_ACC:
1296                 media = I40E_MEDIA_TYPE_DA;
1297                 break;
1298         case I40E_PHY_TYPE_1000BASE_KX:
1299         case I40E_PHY_TYPE_10GBASE_KX4:
1300         case I40E_PHY_TYPE_10GBASE_KR:
1301         case I40E_PHY_TYPE_40GBASE_KR4:
1302         case I40E_PHY_TYPE_20GBASE_KR2:
1303         case I40E_PHY_TYPE_25GBASE_KR:
1304                 media = I40E_MEDIA_TYPE_BACKPLANE;
1305                 break;
1306         case I40E_PHY_TYPE_SGMII:
1307         case I40E_PHY_TYPE_XAUI:
1308         case I40E_PHY_TYPE_XFI:
1309         case I40E_PHY_TYPE_XLAUI:
1310         case I40E_PHY_TYPE_XLPPI:
1311         default:
1312                 media = I40E_MEDIA_TYPE_UNKNOWN;
1313                 break;
1314         }
1315
1316         return media;
1317 }
1318
1319 /**
1320  * i40e_poll_globr - Poll for Global Reset completion
1321  * @hw: pointer to the hardware structure
1322  * @retry_limit: how many times to retry before failure
1323  **/
1324 STATIC enum i40e_status_code i40e_poll_globr(struct i40e_hw *hw,
1325                                              u32 retry_limit)
1326 {
1327         u32 cnt, reg = 0;
1328
1329         for (cnt = 0; cnt < retry_limit; cnt++) {
1330                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1331                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1332                         return I40E_SUCCESS;
1333                 i40e_msec_delay(100);
1334         }
1335
1336         DEBUGOUT("Global reset failed.\n");
1337         DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg);
1338
1339         return I40E_ERR_RESET_FAILED;
1340 }
1341
1342 #define I40E_PF_RESET_WAIT_COUNT        200
1343 /**
1344  * i40e_pf_reset - Reset the PF
1345  * @hw: pointer to the hardware structure
1346  *
1347  * Assuming someone else has triggered a global reset,
1348  * assure the global reset is complete and then reset the PF
1349  **/
1350 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1351 {
1352         u32 cnt = 0;
1353         u32 cnt1 = 0;
1354         u32 reg = 0;
1355         u32 grst_del;
1356
1357         /* Poll for Global Reset steady state in case of recent GRST.
1358          * The grst delay value is in 100ms units, and we'll wait a
1359          * couple counts longer to be sure we don't just miss the end.
1360          */
1361         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1362                         I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1363                         I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1364
1365         grst_del = min(grst_del * 20, 160U);
1366
1367         for (cnt = 0; cnt < grst_del; cnt++) {
1368                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1369                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1370                         break;
1371                 i40e_msec_delay(100);
1372         }
1373         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1374                 DEBUGOUT("Global reset polling failed to complete.\n");
1375                 return I40E_ERR_RESET_FAILED;
1376         }
1377
1378         /* Now Wait for the FW to be ready */
1379         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1380                 reg = rd32(hw, I40E_GLNVM_ULD);
1381                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1382                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1383                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1384                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1385                         DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1386                         break;
1387                 }
1388                 i40e_msec_delay(10);
1389         }
1390         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1391                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1392                 DEBUGOUT("wait for FW Reset complete timedout\n");
1393                 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1394                 return I40E_ERR_RESET_FAILED;
1395         }
1396
1397         /* If there was a Global Reset in progress when we got here,
1398          * we don't need to do the PF Reset
1399          */
1400         if (!cnt) {
1401                 u32 reg2 = 0;
1402
1403                 reg = rd32(hw, I40E_PFGEN_CTRL);
1404                 wr32(hw, I40E_PFGEN_CTRL,
1405                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1406                 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1407                         reg = rd32(hw, I40E_PFGEN_CTRL);
1408                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1409                                 break;
1410                         reg2 = rd32(hw, I40E_GLGEN_RSTAT);
1411                         if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK)
1412                                 break;
1413                         i40e_msec_delay(1);
1414                 }
1415                 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1416                         if (i40e_poll_globr(hw, grst_del) != I40E_SUCCESS)
1417                                 return I40E_ERR_RESET_FAILED;
1418                 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1419                         DEBUGOUT("PF reset polling failed to complete.\n");
1420                         return I40E_ERR_RESET_FAILED;
1421                 }
1422         }
1423
1424         i40e_clear_pxe_mode(hw);
1425
1426
1427         return I40E_SUCCESS;
1428 }
1429
1430 /**
1431  * i40e_clear_hw - clear out any left over hw state
1432  * @hw: pointer to the hw struct
1433  *
1434  * Clear queues and interrupts, typically called at init time,
1435  * but after the capabilities have been found so we know how many
1436  * queues and msix vectors have been allocated.
1437  **/
1438 void i40e_clear_hw(struct i40e_hw *hw)
1439 {
1440         u32 num_queues, base_queue;
1441         u32 num_pf_int;
1442         u32 num_vf_int;
1443         u32 num_vfs;
1444         u32 i, j;
1445         u32 val;
1446         u32 eol = 0x7ff;
1447
1448         /* get number of interrupts, queues, and vfs */
1449         val = rd32(hw, I40E_GLPCI_CNF2);
1450         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1451                         I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1452         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1453                         I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1454
1455         val = rd32(hw, I40E_PFLAN_QALLOC);
1456         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1457                         I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1458         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1459                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1460         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1461                 num_queues = (j - base_queue) + 1;
1462         else
1463                 num_queues = 0;
1464
1465         val = rd32(hw, I40E_PF_VT_PFALLOC);
1466         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1467                         I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1468         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1469                         I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1470         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1471                 num_vfs = (j - i) + 1;
1472         else
1473                 num_vfs = 0;
1474
1475         /* stop all the interrupts */
1476         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1477         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1478         for (i = 0; i < num_pf_int - 2; i++)
1479                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1480
1481         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1482         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1483         wr32(hw, I40E_PFINT_LNKLST0, val);
1484         for (i = 0; i < num_pf_int - 2; i++)
1485                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1486         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1487         for (i = 0; i < num_vfs; i++)
1488                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1489         for (i = 0; i < num_vf_int - 2; i++)
1490                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1491
1492         /* warn the HW of the coming Tx disables */
1493         for (i = 0; i < num_queues; i++) {
1494                 u32 abs_queue_idx = base_queue + i;
1495                 u32 reg_block = 0;
1496
1497                 if (abs_queue_idx >= 128) {
1498                         reg_block = abs_queue_idx / 128;
1499                         abs_queue_idx %= 128;
1500                 }
1501
1502                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1503                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1504                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1505                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1506
1507                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1508         }
1509         i40e_usec_delay(400);
1510
1511         /* stop all the queues */
1512         for (i = 0; i < num_queues; i++) {
1513                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1514                 wr32(hw, I40E_QTX_ENA(i), 0);
1515                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1516                 wr32(hw, I40E_QRX_ENA(i), 0);
1517         }
1518
1519         /* short wait for all queue disables to settle */
1520         i40e_usec_delay(50);
1521 }
1522
1523 /**
1524  * i40e_clear_pxe_mode - clear pxe operations mode
1525  * @hw: pointer to the hw struct
1526  *
1527  * Make sure all PXE mode settings are cleared, including things
1528  * like descriptor fetch/write-back mode.
1529  **/
1530 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1531 {
1532         if (i40e_check_asq_alive(hw))
1533                 i40e_aq_clear_pxe_mode(hw, NULL);
1534 }
1535
1536 /**
1537  * i40e_led_is_mine - helper to find matching led
1538  * @hw: pointer to the hw struct
1539  * @idx: index into GPIO registers
1540  *
1541  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1542  */
1543 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1544 {
1545         u32 gpio_val = 0;
1546         u32 port;
1547
1548         if (!I40E_IS_X710TL_DEVICE(hw->device_id) &&
1549             !hw->func_caps.led[idx])
1550                 return 0;
1551         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1552         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1553                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1554
1555         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1556          * if it is not our port then ignore
1557          */
1558         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1559             (port != hw->port))
1560                 return 0;
1561
1562         return gpio_val;
1563 }
1564
1565 #define I40E_COMBINED_ACTIVITY 0xA
1566 #define I40E_FILTER_ACTIVITY 0xE
1567 #define I40E_LINK_ACTIVITY 0xC
1568 #define I40E_MAC_ACTIVITY 0xD
1569 #define I40E_FW_LED BIT(4)
1570 #define I40E_LED_MODE_VALID (I40E_GLGEN_GPIO_CTL_LED_MODE_MASK >> \
1571                              I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT)
1572
1573 #define I40E_LED0 22
1574
1575 #define I40E_PIN_FUNC_SDP 0x0
1576 #define I40E_PIN_FUNC_LED 0x1
1577
1578 /**
1579  * i40e_led_get - return current on/off mode
1580  * @hw: pointer to the hw struct
1581  *
1582  * The value returned is the 'mode' field as defined in the
1583  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1584  * values are variations of possible behaviors relating to
1585  * blink, link, and wire.
1586  **/
1587 u32 i40e_led_get(struct i40e_hw *hw)
1588 {
1589         u32 current_mode = 0;
1590         u32 mode = 0;
1591         int i;
1592
1593         /* as per the documentation GPIO 22-29 are the LED
1594          * GPIO pins named LED0..LED7
1595          */
1596         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1597                 u32 gpio_val = i40e_led_is_mine(hw, i);
1598
1599                 if (!gpio_val)
1600                         continue;
1601
1602                 /* ignore gpio LED src mode entries related to the activity
1603                  *  LEDs
1604                  */
1605                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1606                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1607                 switch (current_mode) {
1608                 case I40E_COMBINED_ACTIVITY:
1609                 case I40E_FILTER_ACTIVITY:
1610                 case I40E_MAC_ACTIVITY:
1611                 case I40E_LINK_ACTIVITY:
1612                         continue;
1613                 default:
1614                         break;
1615                 }
1616
1617                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1618                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1619                 break;
1620         }
1621
1622         return mode;
1623 }
1624
1625 /**
1626  * i40e_led_set - set new on/off mode
1627  * @hw: pointer to the hw struct
1628  * @mode: 0=off, 0xf=on (else see manual for mode details)
1629  * @blink: true if the LED should blink when on, false if steady
1630  *
1631  * if this function is used to turn on the blink it should
1632  * be used to disable the blink when restoring the original state.
1633  **/
1634 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1635 {
1636         u32 current_mode = 0;
1637         int i;
1638
1639         if (mode & ~I40E_LED_MODE_VALID) {
1640                 DEBUGOUT1("invalid mode passed in %X\n", mode);
1641                 return;
1642         }
1643
1644         /* as per the documentation GPIO 22-29 are the LED
1645          * GPIO pins named LED0..LED7
1646          */
1647         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1648                 u32 gpio_val = i40e_led_is_mine(hw, i);
1649
1650                 if (!gpio_val)
1651                         continue;
1652
1653                 /* ignore gpio LED src mode entries related to the activity
1654                  * LEDs
1655                  */
1656                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1657                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1658                 switch (current_mode) {
1659                 case I40E_COMBINED_ACTIVITY:
1660                 case I40E_FILTER_ACTIVITY:
1661                 case I40E_MAC_ACTIVITY:
1662                 case I40E_LINK_ACTIVITY:
1663                         continue;
1664                 default:
1665                         break;
1666                 }
1667
1668                 if (I40E_IS_X710TL_DEVICE(hw->device_id)) {
1669                         u32 pin_func = 0;
1670
1671                         if (mode & I40E_FW_LED)
1672                                 pin_func = I40E_PIN_FUNC_SDP;
1673                         else
1674                                 pin_func = I40E_PIN_FUNC_LED;
1675
1676                         gpio_val &= ~I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK;
1677                         gpio_val |= ((pin_func <<
1678                                      I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT) &
1679                                      I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK);
1680                 }
1681                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1682                 /* this & is a bit of paranoia, but serves as a range check */
1683                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1684                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1685
1686                 if (blink)
1687                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1688                 else
1689                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1690
1691                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1692                 break;
1693         }
1694 }
1695
1696 /* Admin command wrappers */
1697
1698 /**
1699  * i40e_aq_get_phy_capabilities
1700  * @hw: pointer to the hw struct
1701  * @abilities: structure for PHY capabilities to be filled
1702  * @qualified_modules: report Qualified Modules
1703  * @report_init: report init capabilities (active are default)
1704  * @cmd_details: pointer to command details structure or NULL
1705  *
1706  * Returns the various PHY abilities supported on the Port.
1707  **/
1708 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1709                         bool qualified_modules, bool report_init,
1710                         struct i40e_aq_get_phy_abilities_resp *abilities,
1711                         struct i40e_asq_cmd_details *cmd_details)
1712 {
1713         struct i40e_aq_desc desc;
1714         enum i40e_status_code status;
1715         u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0;
1716         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1717
1718         if (!abilities)
1719                 return I40E_ERR_PARAM;
1720
1721         do {
1722                 i40e_fill_default_direct_cmd_desc(&desc,
1723                                                i40e_aqc_opc_get_phy_abilities);
1724
1725                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1726                 if (abilities_size > I40E_AQ_LARGE_BUF)
1727                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1728
1729                 if (qualified_modules)
1730                         desc.params.external.param0 |=
1731                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1732
1733                 if (report_init)
1734                         desc.params.external.param0 |=
1735                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1736
1737                 status = i40e_asq_send_command(hw, &desc, abilities,
1738                                                abilities_size, cmd_details);
1739
1740                 switch (hw->aq.asq_last_status) {
1741                 case I40E_AQ_RC_EIO:
1742                         status = I40E_ERR_UNKNOWN_PHY;
1743                         break;
1744                 case I40E_AQ_RC_EAGAIN:
1745                         i40e_msec_delay(1);
1746                         total_delay++;
1747                         status = I40E_ERR_TIMEOUT;
1748                         break;
1749                 /* also covers I40E_AQ_RC_OK */
1750                 default:
1751                         break;
1752                 }
1753
1754         } while ((hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) &&
1755                 (total_delay < max_delay));
1756
1757         if (status != I40E_SUCCESS)
1758                 return status;
1759
1760         if (report_init) {
1761                 if (hw->mac.type ==  I40E_MAC_XL710 &&
1762                     hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1763                     hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
1764                         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1765                 } else {
1766                         hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1767                         hw->phy.phy_types |=
1768                                         ((u64)abilities->phy_type_ext << 32);
1769                 }
1770         }
1771
1772         return status;
1773 }
1774
1775 /**
1776  * i40e_aq_set_phy_config
1777  * @hw: pointer to the hw struct
1778  * @config: structure with PHY configuration to be set
1779  * @cmd_details: pointer to command details structure or NULL
1780  *
1781  * Set the various PHY configuration parameters
1782  * supported on the Port.One or more of the Set PHY config parameters may be
1783  * ignored in an MFP mode as the PF may not have the privilege to set some
1784  * of the PHY Config parameters. This status will be indicated by the
1785  * command response.
1786  **/
1787 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1788                                 struct i40e_aq_set_phy_config *config,
1789                                 struct i40e_asq_cmd_details *cmd_details)
1790 {
1791         struct i40e_aq_desc desc;
1792         struct i40e_aq_set_phy_config *cmd =
1793                 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1794         enum i40e_status_code status;
1795
1796         if (!config)
1797                 return I40E_ERR_PARAM;
1798
1799         i40e_fill_default_direct_cmd_desc(&desc,
1800                                           i40e_aqc_opc_set_phy_config);
1801
1802         *cmd = *config;
1803
1804         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1805
1806         return status;
1807 }
1808
1809 /**
1810  * i40e_set_fc
1811  * @hw: pointer to the hw struct
1812  * @aq_failures: buffer to return AdminQ failure information
1813  * @atomic_restart: whether to enable atomic link restart
1814  *
1815  * Set the requested flow control mode using set_phy_config.
1816  **/
1817 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1818                                   bool atomic_restart)
1819 {
1820         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1821         struct i40e_aq_get_phy_abilities_resp abilities;
1822         struct i40e_aq_set_phy_config config;
1823         enum i40e_status_code status;
1824         u8 pause_mask = 0x0;
1825
1826         *aq_failures = 0x0;
1827
1828         switch (fc_mode) {
1829         case I40E_FC_FULL:
1830                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1831                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1832                 break;
1833         case I40E_FC_RX_PAUSE:
1834                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1835                 break;
1836         case I40E_FC_TX_PAUSE:
1837                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1838                 break;
1839         default:
1840                 break;
1841         }
1842
1843         /* Get the current phy config */
1844         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1845                                               NULL);
1846         if (status) {
1847                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1848                 return status;
1849         }
1850
1851         memset(&config, 0, sizeof(config));
1852         /* clear the old pause settings */
1853         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1854                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1855         /* set the new abilities */
1856         config.abilities |= pause_mask;
1857         /* If the abilities have changed, then set the new config */
1858         if (config.abilities != abilities.abilities) {
1859                 /* Auto restart link so settings take effect */
1860                 if (atomic_restart)
1861                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1862                 /* Copy over all the old settings */
1863                 config.phy_type = abilities.phy_type;
1864                 config.phy_type_ext = abilities.phy_type_ext;
1865                 config.link_speed = abilities.link_speed;
1866                 config.eee_capability = abilities.eee_capability;
1867                 config.eeer = abilities.eeer_val;
1868                 config.low_power_ctrl = abilities.d3_lpan;
1869                 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1870                                     I40E_AQ_PHY_FEC_CONFIG_MASK;
1871                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1872
1873                 if (status)
1874                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1875         }
1876         /* Update the link info */
1877         status = i40e_update_link_info(hw);
1878         if (status) {
1879                 /* Wait a little bit (on 40G cards it sometimes takes a really
1880                  * long time for link to come back from the atomic reset)
1881                  * and try once more
1882                  */
1883                 i40e_msec_delay(1000);
1884                 status = i40e_update_link_info(hw);
1885         }
1886         if (status)
1887                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1888
1889         return status;
1890 }
1891
1892 /**
1893  * i40e_aq_set_mac_config
1894  * @hw: pointer to the hw struct
1895  * @max_frame_size: Maximum Frame Size to be supported by the port
1896  * @crc_en: Tell HW to append a CRC to outgoing frames
1897  * @pacing: Pacing configurations
1898  * @auto_drop_blocking_packets: Tell HW to drop packets if TC queue is blocked
1899  * @cmd_details: pointer to command details structure or NULL
1900  *
1901  * Configure MAC settings for frame size, jumbo frame support and the
1902  * addition of a CRC by the hardware.
1903  **/
1904 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1905                                 u16 max_frame_size,
1906                                 bool crc_en, u16 pacing,
1907                                 bool auto_drop_blocking_packets,
1908                                 struct i40e_asq_cmd_details *cmd_details)
1909 {
1910         struct i40e_aq_desc desc;
1911         struct i40e_aq_set_mac_config *cmd =
1912                 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1913         enum i40e_status_code status;
1914
1915         if (max_frame_size == 0)
1916                 return I40E_ERR_PARAM;
1917
1918         i40e_fill_default_direct_cmd_desc(&desc,
1919                                           i40e_aqc_opc_set_mac_config);
1920
1921         cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1922         cmd->params = ((u8)pacing & 0x0F) << 3;
1923         if (crc_en)
1924                 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1925
1926         if (auto_drop_blocking_packets) {
1927                 if (hw->flags & I40E_HW_FLAG_DROP_MODE)
1928                         cmd->params |=
1929                                 I40E_AQ_SET_MAC_CONFIG_DROP_BLOCKING_PACKET_EN;
1930                 else
1931                         i40e_debug(hw, I40E_DEBUG_ALL,
1932                                    "This FW api version does not support drop mode.\n");
1933         }
1934
1935 #define I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD     0x7FFF
1936         cmd->fc_refresh_threshold =
1937                 CPU_TO_LE16(I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD);
1938
1939         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1940
1941         return status;
1942 }
1943
1944 /**
1945  * i40e_aq_clear_pxe_mode
1946  * @hw: pointer to the hw struct
1947  * @cmd_details: pointer to command details structure or NULL
1948  *
1949  * Tell the firmware that the driver is taking over from PXE
1950  **/
1951 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1952                         struct i40e_asq_cmd_details *cmd_details)
1953 {
1954         enum i40e_status_code status;
1955         struct i40e_aq_desc desc;
1956         struct i40e_aqc_clear_pxe *cmd =
1957                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1958
1959         i40e_fill_default_direct_cmd_desc(&desc,
1960                                           i40e_aqc_opc_clear_pxe_mode);
1961
1962         cmd->rx_cnt = 0x2;
1963
1964         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1965
1966         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1967
1968         return status;
1969 }
1970
1971 /**
1972  * i40e_aq_set_link_restart_an
1973  * @hw: pointer to the hw struct
1974  * @enable_link: if true: enable link, if false: disable link
1975  * @cmd_details: pointer to command details structure or NULL
1976  *
1977  * Sets up the link and restarts the Auto-Negotiation over the link.
1978  **/
1979 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1980                 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1981 {
1982         struct i40e_aq_desc desc;
1983         struct i40e_aqc_set_link_restart_an *cmd =
1984                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1985         enum i40e_status_code status;
1986
1987         i40e_fill_default_direct_cmd_desc(&desc,
1988                                           i40e_aqc_opc_set_link_restart_an);
1989
1990         cmd->command = I40E_AQ_PHY_RESTART_AN;
1991         if (enable_link)
1992                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1993         else
1994                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1995
1996         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1997
1998         return status;
1999 }
2000
2001 /**
2002  * i40e_aq_get_link_info
2003  * @hw: pointer to the hw struct
2004  * @enable_lse: enable/disable LinkStatusEvent reporting
2005  * @link: pointer to link status structure - optional
2006  * @cmd_details: pointer to command details structure or NULL
2007  *
2008  * Returns the link status of the adapter.
2009  **/
2010 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
2011                                 bool enable_lse, struct i40e_link_status *link,
2012                                 struct i40e_asq_cmd_details *cmd_details)
2013 {
2014         struct i40e_aq_desc desc;
2015         struct i40e_aqc_get_link_status *resp =
2016                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
2017         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
2018         enum i40e_status_code status;
2019         bool tx_pause, rx_pause;
2020         u16 command_flags;
2021
2022         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
2023
2024         if (enable_lse)
2025                 command_flags = I40E_AQ_LSE_ENABLE;
2026         else
2027                 command_flags = I40E_AQ_LSE_DISABLE;
2028         resp->command_flags = CPU_TO_LE16(command_flags);
2029
2030         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2031
2032         if (status != I40E_SUCCESS)
2033                 goto aq_get_link_info_exit;
2034
2035         /* save off old link status information */
2036         i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
2037                     sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
2038
2039         /* update link status */
2040         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
2041         hw->phy.media_type = i40e_get_media_type(hw);
2042         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
2043         hw_link_info->link_info = resp->link_info;
2044         hw_link_info->an_info = resp->an_info;
2045         hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
2046                                                  I40E_AQ_CONFIG_FEC_RS_ENA);
2047         hw_link_info->ext_info = resp->ext_info;
2048         hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
2049         hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
2050         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
2051
2052         /* update fc info */
2053         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
2054         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
2055         if (tx_pause & rx_pause)
2056                 hw->fc.current_mode = I40E_FC_FULL;
2057         else if (tx_pause)
2058                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
2059         else if (rx_pause)
2060                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
2061         else
2062                 hw->fc.current_mode = I40E_FC_NONE;
2063
2064         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
2065                 hw_link_info->crc_enable = true;
2066         else
2067                 hw_link_info->crc_enable = false;
2068
2069         if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
2070                 hw_link_info->lse_enable = true;
2071         else
2072                 hw_link_info->lse_enable = false;
2073
2074         if ((hw->mac.type == I40E_MAC_XL710) &&
2075             (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
2076              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
2077                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
2078
2079         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE &&
2080             hw->mac.type != I40E_MAC_X722) {
2081                 __le32 tmp;
2082
2083                 i40e_memcpy(&tmp, resp->link_type, sizeof(tmp),
2084                             I40E_NONDMA_TO_NONDMA);
2085                 hw->phy.phy_types = LE32_TO_CPU(tmp);
2086                 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
2087         }
2088
2089         /* save link status information */
2090         if (link)
2091                 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
2092                             I40E_NONDMA_TO_NONDMA);
2093
2094         /* flag cleared so helper functions don't call AQ again */
2095         hw->phy.get_link_info = false;
2096
2097 aq_get_link_info_exit:
2098         return status;
2099 }
2100
2101 /**
2102  * i40e_aq_set_phy_int_mask
2103  * @hw: pointer to the hw struct
2104  * @mask: interrupt mask to be set
2105  * @cmd_details: pointer to command details structure or NULL
2106  *
2107  * Set link interrupt mask.
2108  **/
2109 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2110                                 u16 mask,
2111                                 struct i40e_asq_cmd_details *cmd_details)
2112 {
2113         struct i40e_aq_desc desc;
2114         struct i40e_aqc_set_phy_int_mask *cmd =
2115                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2116         enum i40e_status_code status;
2117
2118         i40e_fill_default_direct_cmd_desc(&desc,
2119                                           i40e_aqc_opc_set_phy_int_mask);
2120
2121         cmd->event_mask = CPU_TO_LE16(mask);
2122
2123         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2124
2125         return status;
2126 }
2127
2128 /**
2129  * i40e_aq_get_local_advt_reg
2130  * @hw: pointer to the hw struct
2131  * @advt_reg: local AN advertisement register value
2132  * @cmd_details: pointer to command details structure or NULL
2133  *
2134  * Get the Local AN advertisement register value.
2135  **/
2136 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2137                                 u64 *advt_reg,
2138                                 struct i40e_asq_cmd_details *cmd_details)
2139 {
2140         struct i40e_aq_desc desc;
2141         struct i40e_aqc_an_advt_reg *resp =
2142                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2143         enum i40e_status_code status;
2144
2145         i40e_fill_default_direct_cmd_desc(&desc,
2146                                           i40e_aqc_opc_get_local_advt_reg);
2147
2148         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2149
2150         if (status != I40E_SUCCESS)
2151                 goto aq_get_local_advt_reg_exit;
2152
2153         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2154         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2155
2156 aq_get_local_advt_reg_exit:
2157         return status;
2158 }
2159
2160 /**
2161  * i40e_aq_set_local_advt_reg
2162  * @hw: pointer to the hw struct
2163  * @advt_reg: local AN advertisement register value
2164  * @cmd_details: pointer to command details structure or NULL
2165  *
2166  * Get the Local AN advertisement register value.
2167  **/
2168 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2169                                 u64 advt_reg,
2170                                 struct i40e_asq_cmd_details *cmd_details)
2171 {
2172         struct i40e_aq_desc desc;
2173         struct i40e_aqc_an_advt_reg *cmd =
2174                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2175         enum i40e_status_code status;
2176
2177         i40e_fill_default_direct_cmd_desc(&desc,
2178                                           i40e_aqc_opc_get_local_advt_reg);
2179
2180         cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2181         cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2182
2183         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2184
2185         return status;
2186 }
2187
2188 /**
2189  * i40e_aq_get_partner_advt
2190  * @hw: pointer to the hw struct
2191  * @advt_reg: AN partner advertisement register value
2192  * @cmd_details: pointer to command details structure or NULL
2193  *
2194  * Get the link partner AN advertisement register value.
2195  **/
2196 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2197                                 u64 *advt_reg,
2198                                 struct i40e_asq_cmd_details *cmd_details)
2199 {
2200         struct i40e_aq_desc desc;
2201         struct i40e_aqc_an_advt_reg *resp =
2202                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2203         enum i40e_status_code status;
2204
2205         i40e_fill_default_direct_cmd_desc(&desc,
2206                                           i40e_aqc_opc_get_partner_advt);
2207
2208         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2209
2210         if (status != I40E_SUCCESS)
2211                 goto aq_get_partner_advt_exit;
2212
2213         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2214         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2215
2216 aq_get_partner_advt_exit:
2217         return status;
2218 }
2219
2220 /**
2221  * i40e_aq_set_lb_modes
2222  * @hw: pointer to the hw struct
2223  * @lb_modes: loopback mode to be set
2224  * @cmd_details: pointer to command details structure or NULL
2225  *
2226  * Sets loopback modes.
2227  **/
2228 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2229                                 u16 lb_modes,
2230                                 struct i40e_asq_cmd_details *cmd_details)
2231 {
2232         struct i40e_aq_desc desc;
2233         struct i40e_aqc_set_lb_mode *cmd =
2234                 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2235         enum i40e_status_code status;
2236
2237         i40e_fill_default_direct_cmd_desc(&desc,
2238                                           i40e_aqc_opc_set_lb_modes);
2239
2240         cmd->lb_mode = CPU_TO_LE16(lb_modes);
2241
2242         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2243
2244         return status;
2245 }
2246
2247 /**
2248  * i40e_aq_set_phy_debug
2249  * @hw: pointer to the hw struct
2250  * @cmd_flags: debug command flags
2251  * @cmd_details: pointer to command details structure or NULL
2252  *
2253  * Reset the external PHY.
2254  **/
2255 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2256                                 struct i40e_asq_cmd_details *cmd_details)
2257 {
2258         struct i40e_aq_desc desc;
2259         struct i40e_aqc_set_phy_debug *cmd =
2260                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2261         enum i40e_status_code status;
2262
2263         i40e_fill_default_direct_cmd_desc(&desc,
2264                                           i40e_aqc_opc_set_phy_debug);
2265
2266         cmd->command_flags = cmd_flags;
2267
2268         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2269
2270         return status;
2271 }
2272
2273 /**
2274  * i40e_aq_add_vsi
2275  * @hw: pointer to the hw struct
2276  * @vsi_ctx: pointer to a vsi context struct
2277  * @cmd_details: pointer to command details structure or NULL
2278  *
2279  * Add a VSI context to the hardware.
2280 **/
2281 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2282                                 struct i40e_vsi_context *vsi_ctx,
2283                                 struct i40e_asq_cmd_details *cmd_details)
2284 {
2285         struct i40e_aq_desc desc;
2286         struct i40e_aqc_add_get_update_vsi *cmd =
2287                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2288         struct i40e_aqc_add_get_update_vsi_completion *resp =
2289                 (struct i40e_aqc_add_get_update_vsi_completion *)
2290                 &desc.params.raw;
2291         enum i40e_status_code status;
2292
2293         i40e_fill_default_direct_cmd_desc(&desc,
2294                                           i40e_aqc_opc_add_vsi);
2295
2296         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2297         cmd->connection_type = vsi_ctx->connection_type;
2298         cmd->vf_id = vsi_ctx->vf_num;
2299         cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2300
2301         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2302
2303         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2304                                     sizeof(vsi_ctx->info), cmd_details);
2305
2306         if (status != I40E_SUCCESS)
2307                 goto aq_add_vsi_exit;
2308
2309         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2310         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2311         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2312         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2313
2314 aq_add_vsi_exit:
2315         return status;
2316 }
2317
2318 /**
2319  * i40e_aq_set_default_vsi
2320  * @hw: pointer to the hw struct
2321  * @seid: vsi number
2322  * @cmd_details: pointer to command details structure or NULL
2323  **/
2324 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2325                                 u16 seid,
2326                                 struct i40e_asq_cmd_details *cmd_details)
2327 {
2328         struct i40e_aq_desc desc;
2329         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2330                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2331                 &desc.params.raw;
2332         enum i40e_status_code status;
2333
2334         i40e_fill_default_direct_cmd_desc(&desc,
2335                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2336
2337         cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2338         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2339         cmd->seid = CPU_TO_LE16(seid);
2340
2341         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2342
2343         return status;
2344 }
2345
2346 /**
2347  * i40e_aq_clear_default_vsi
2348  * @hw: pointer to the hw struct
2349  * @seid: vsi number
2350  * @cmd_details: pointer to command details structure or NULL
2351  **/
2352 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2353                                 u16 seid,
2354                                 struct i40e_asq_cmd_details *cmd_details)
2355 {
2356         struct i40e_aq_desc desc;
2357         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2358                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2359                 &desc.params.raw;
2360         enum i40e_status_code status;
2361
2362         i40e_fill_default_direct_cmd_desc(&desc,
2363                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2364
2365         cmd->promiscuous_flags = CPU_TO_LE16(0);
2366         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2367         cmd->seid = CPU_TO_LE16(seid);
2368
2369         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2370
2371         return status;
2372 }
2373
2374 /**
2375  * i40e_aq_set_vsi_unicast_promiscuous
2376  * @hw: pointer to the hw struct
2377  * @seid: vsi number
2378  * @set: set unicast promiscuous enable/disable
2379  * @cmd_details: pointer to command details structure or NULL
2380  * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2381  **/
2382 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2383                                 u16 seid, bool set,
2384                                 struct i40e_asq_cmd_details *cmd_details,
2385                                 bool rx_only_promisc)
2386 {
2387         struct i40e_aq_desc desc;
2388         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2389                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2390         enum i40e_status_code status;
2391         u16 flags = 0;
2392
2393         i40e_fill_default_direct_cmd_desc(&desc,
2394                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2395
2396         if (set) {
2397                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2398                 if (rx_only_promisc &&
2399                     (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2400                      (hw->aq.api_maj_ver > 1)))
2401                         flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2402         }
2403
2404         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2405
2406         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2407         if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2408              (hw->aq.api_maj_ver > 1))
2409                 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2410
2411         cmd->seid = CPU_TO_LE16(seid);
2412         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2413
2414         return status;
2415 }
2416
2417 /**
2418  * i40e_aq_set_vsi_multicast_promiscuous
2419  * @hw: pointer to the hw struct
2420  * @seid: vsi number
2421  * @set: set multicast promiscuous enable/disable
2422  * @cmd_details: pointer to command details structure or NULL
2423  **/
2424 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2425                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2426 {
2427         struct i40e_aq_desc desc;
2428         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2429                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2430         enum i40e_status_code status;
2431         u16 flags = 0;
2432
2433         i40e_fill_default_direct_cmd_desc(&desc,
2434                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2435
2436         if (set)
2437                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2438
2439         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2440
2441         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2442
2443         cmd->seid = CPU_TO_LE16(seid);
2444         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2445
2446         return status;
2447 }
2448
2449 /**
2450 * i40e_aq_set_vsi_full_promiscuous
2451 * @hw: pointer to the hw struct
2452 * @seid: VSI number
2453 * @set: set promiscuous enable/disable
2454 * @cmd_details: pointer to command details structure or NULL
2455 **/
2456 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw,
2457                                 u16 seid, bool set,
2458                                 struct i40e_asq_cmd_details *cmd_details)
2459 {
2460         struct i40e_aq_desc desc;
2461         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2462                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2463         enum i40e_status_code status;
2464         u16 flags = 0;
2465
2466         i40e_fill_default_direct_cmd_desc(&desc,
2467                 i40e_aqc_opc_set_vsi_promiscuous_modes);
2468
2469         if (set)
2470                 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2471                         I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2472                         I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2473
2474         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2475
2476         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2477                                        I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2478                                        I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2479
2480         cmd->seid = CPU_TO_LE16(seid);
2481         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2482
2483         return status;
2484 }
2485
2486 /**
2487  * i40e_aq_set_vsi_mc_promisc_on_vlan
2488  * @hw: pointer to the hw struct
2489  * @seid: vsi number
2490  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2491  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2492  * @cmd_details: pointer to command details structure or NULL
2493  **/
2494 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2495                                 u16 seid, bool enable, u16 vid,
2496                                 struct i40e_asq_cmd_details *cmd_details)
2497 {
2498         struct i40e_aq_desc desc;
2499         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2500                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2501         enum i40e_status_code status;
2502         u16 flags = 0;
2503
2504         i40e_fill_default_direct_cmd_desc(&desc,
2505                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2506
2507         if (enable)
2508                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2509
2510         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2511         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2512         cmd->seid = CPU_TO_LE16(seid);
2513         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2514
2515         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2516
2517         return status;
2518 }
2519
2520 /**
2521  * i40e_aq_set_vsi_uc_promisc_on_vlan
2522  * @hw: pointer to the hw struct
2523  * @seid: vsi number
2524  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2525  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2526  * @cmd_details: pointer to command details structure or NULL
2527  **/
2528 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2529                                 u16 seid, bool enable, u16 vid,
2530                                 struct i40e_asq_cmd_details *cmd_details)
2531 {
2532         struct i40e_aq_desc desc;
2533         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2534                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2535         enum i40e_status_code status;
2536         u16 flags = 0;
2537
2538         i40e_fill_default_direct_cmd_desc(&desc,
2539                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2540
2541         if (enable)
2542                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2543
2544         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2545         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2546         cmd->seid = CPU_TO_LE16(seid);
2547         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2548
2549         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2550
2551         return status;
2552 }
2553
2554 /**
2555  * i40e_aq_set_vsi_bc_promisc_on_vlan
2556  * @hw: pointer to the hw struct
2557  * @seid: vsi number
2558  * @enable: set broadcast promiscuous enable/disable for a given VLAN
2559  * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2560  * @cmd_details: pointer to command details structure or NULL
2561  **/
2562 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2563                                 u16 seid, bool enable, u16 vid,
2564                                 struct i40e_asq_cmd_details *cmd_details)
2565 {
2566         struct i40e_aq_desc desc;
2567         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2568                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2569         enum i40e_status_code status;
2570         u16 flags = 0;
2571
2572         i40e_fill_default_direct_cmd_desc(&desc,
2573                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2574
2575         if (enable)
2576                 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2577
2578         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2579         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2580         cmd->seid = CPU_TO_LE16(seid);
2581         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2582
2583         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2584
2585         return status;
2586 }
2587
2588 /**
2589  * i40e_aq_set_vsi_broadcast
2590  * @hw: pointer to the hw struct
2591  * @seid: vsi number
2592  * @set_filter: true to set filter, false to clear filter
2593  * @cmd_details: pointer to command details structure or NULL
2594  *
2595  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2596  **/
2597 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2598                                 u16 seid, bool set_filter,
2599                                 struct i40e_asq_cmd_details *cmd_details)
2600 {
2601         struct i40e_aq_desc desc;
2602         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2603                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2604         enum i40e_status_code status;
2605
2606         i40e_fill_default_direct_cmd_desc(&desc,
2607                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2608
2609         if (set_filter)
2610                 cmd->promiscuous_flags
2611                             |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2612         else
2613                 cmd->promiscuous_flags
2614                             &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2615
2616         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2617         cmd->seid = CPU_TO_LE16(seid);
2618         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2619
2620         return status;
2621 }
2622
2623 /**
2624  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2625  * @hw: pointer to the hw struct
2626  * @seid: vsi number
2627  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2628  * @cmd_details: pointer to command details structure or NULL
2629  **/
2630 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2631                                 u16 seid, bool enable,
2632                                 struct i40e_asq_cmd_details *cmd_details)
2633 {
2634         struct i40e_aq_desc desc;
2635         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2636                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2637         enum i40e_status_code status;
2638         u16 flags = 0;
2639
2640         i40e_fill_default_direct_cmd_desc(&desc,
2641                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2642         if (enable)
2643                 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2644
2645         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2646         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2647         cmd->seid = CPU_TO_LE16(seid);
2648
2649         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2650
2651         return status;
2652 }
2653
2654 /**
2655  * i40e_get_vsi_params - get VSI configuration info
2656  * @hw: pointer to the hw struct
2657  * @vsi_ctx: pointer to a vsi context struct
2658  * @cmd_details: pointer to command details structure or NULL
2659  **/
2660 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2661                                 struct i40e_vsi_context *vsi_ctx,
2662                                 struct i40e_asq_cmd_details *cmd_details)
2663 {
2664         struct i40e_aq_desc desc;
2665         struct i40e_aqc_add_get_update_vsi *cmd =
2666                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2667         struct i40e_aqc_add_get_update_vsi_completion *resp =
2668                 (struct i40e_aqc_add_get_update_vsi_completion *)
2669                 &desc.params.raw;
2670         enum i40e_status_code status;
2671
2672         UNREFERENCED_1PARAMETER(cmd_details);
2673         i40e_fill_default_direct_cmd_desc(&desc,
2674                                           i40e_aqc_opc_get_vsi_parameters);
2675
2676         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2677
2678         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2679
2680         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2681                                     sizeof(vsi_ctx->info), NULL);
2682
2683         if (status != I40E_SUCCESS)
2684                 goto aq_get_vsi_params_exit;
2685
2686         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2687         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2688         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2689         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2690
2691 aq_get_vsi_params_exit:
2692         return status;
2693 }
2694
2695 /**
2696  * i40e_aq_update_vsi_params
2697  * @hw: pointer to the hw struct
2698  * @vsi_ctx: pointer to a vsi context struct
2699  * @cmd_details: pointer to command details structure or NULL
2700  *
2701  * Update a VSI context.
2702  **/
2703 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2704                                 struct i40e_vsi_context *vsi_ctx,
2705                                 struct i40e_asq_cmd_details *cmd_details)
2706 {
2707         struct i40e_aq_desc desc;
2708         struct i40e_aqc_add_get_update_vsi *cmd =
2709                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2710         struct i40e_aqc_add_get_update_vsi_completion *resp =
2711                 (struct i40e_aqc_add_get_update_vsi_completion *)
2712                 &desc.params.raw;
2713         enum i40e_status_code status;
2714
2715         i40e_fill_default_direct_cmd_desc(&desc,
2716                                           i40e_aqc_opc_update_vsi_parameters);
2717         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2718
2719         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2720
2721         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2722                                     sizeof(vsi_ctx->info), cmd_details);
2723
2724         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2725         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2726
2727         return status;
2728 }
2729
2730 /**
2731  * i40e_aq_get_switch_config
2732  * @hw: pointer to the hardware structure
2733  * @buf: pointer to the result buffer
2734  * @buf_size: length of input buffer
2735  * @start_seid: seid to start for the report, 0 == beginning
2736  * @cmd_details: pointer to command details structure or NULL
2737  *
2738  * Fill the buf with switch configuration returned from AdminQ command
2739  **/
2740 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2741                                 struct i40e_aqc_get_switch_config_resp *buf,
2742                                 u16 buf_size, u16 *start_seid,
2743                                 struct i40e_asq_cmd_details *cmd_details)
2744 {
2745         struct i40e_aq_desc desc;
2746         struct i40e_aqc_switch_seid *scfg =
2747                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2748         enum i40e_status_code status;
2749
2750         i40e_fill_default_direct_cmd_desc(&desc,
2751                                           i40e_aqc_opc_get_switch_config);
2752         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2753         if (buf_size > I40E_AQ_LARGE_BUF)
2754                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2755         scfg->seid = CPU_TO_LE16(*start_seid);
2756
2757         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2758         *start_seid = LE16_TO_CPU(scfg->seid);
2759
2760         return status;
2761 }
2762
2763 /**
2764  * i40e_aq_set_switch_config
2765  * @hw: pointer to the hardware structure
2766  * @flags: bit flag values to set
2767  * @mode: cloud filter mode
2768  * @valid_flags: which bit flags to set
2769  * @cmd_details: pointer to command details structure or NULL
2770  *
2771  * Set switch configuration bits
2772  **/
2773 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2774                                 u16 flags, u16 valid_flags, u8 mode,
2775                                 struct i40e_asq_cmd_details *cmd_details)
2776 {
2777         struct i40e_aq_desc desc;
2778         struct i40e_aqc_set_switch_config *scfg =
2779                 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2780         enum i40e_status_code status;
2781
2782         i40e_fill_default_direct_cmd_desc(&desc,
2783                                           i40e_aqc_opc_set_switch_config);
2784         scfg->flags = CPU_TO_LE16(flags);
2785         scfg->valid_flags = CPU_TO_LE16(valid_flags);
2786         scfg->mode = mode;
2787         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
2788                 scfg->switch_tag = CPU_TO_LE16(hw->switch_tag);
2789                 scfg->first_tag = CPU_TO_LE16(hw->first_tag);
2790                 scfg->second_tag = CPU_TO_LE16(hw->second_tag);
2791         }
2792         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2793
2794         return status;
2795 }
2796
2797 /**
2798  * i40e_aq_get_firmware_version
2799  * @hw: pointer to the hw struct
2800  * @fw_major_version: firmware major version
2801  * @fw_minor_version: firmware minor version
2802  * @fw_build: firmware build number
2803  * @api_major_version: major queue version
2804  * @api_minor_version: minor queue version
2805  * @cmd_details: pointer to command details structure or NULL
2806  *
2807  * Get the firmware version from the admin queue commands
2808  **/
2809 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2810                                 u16 *fw_major_version, u16 *fw_minor_version,
2811                                 u32 *fw_build,
2812                                 u16 *api_major_version, u16 *api_minor_version,
2813                                 struct i40e_asq_cmd_details *cmd_details)
2814 {
2815         struct i40e_aq_desc desc;
2816         struct i40e_aqc_get_version *resp =
2817                 (struct i40e_aqc_get_version *)&desc.params.raw;
2818         enum i40e_status_code status;
2819
2820         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2821
2822         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2823
2824         if (status == I40E_SUCCESS) {
2825                 if (fw_major_version != NULL)
2826                         *fw_major_version = LE16_TO_CPU(resp->fw_major);
2827                 if (fw_minor_version != NULL)
2828                         *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2829                 if (fw_build != NULL)
2830                         *fw_build = LE32_TO_CPU(resp->fw_build);
2831                 if (api_major_version != NULL)
2832                         *api_major_version = LE16_TO_CPU(resp->api_major);
2833                 if (api_minor_version != NULL)
2834                         *api_minor_version = LE16_TO_CPU(resp->api_minor);
2835
2836                 /* A workaround to fix the API version in SW */
2837                 if (api_major_version && api_minor_version &&
2838                     fw_major_version && fw_minor_version &&
2839                     ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2840                     (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2841                      (*fw_major_version > 4)))
2842                         *api_minor_version = 2;
2843         }
2844
2845         return status;
2846 }
2847
2848 /**
2849  * i40e_aq_send_driver_version
2850  * @hw: pointer to the hw struct
2851  * @dv: driver's major, minor version
2852  * @cmd_details: pointer to command details structure or NULL
2853  *
2854  * Send the driver version to the firmware
2855  **/
2856 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2857                                 struct i40e_driver_version *dv,
2858                                 struct i40e_asq_cmd_details *cmd_details)
2859 {
2860         struct i40e_aq_desc desc;
2861         struct i40e_aqc_driver_version *cmd =
2862                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2863         enum i40e_status_code status;
2864         u16 len;
2865
2866         if (dv == NULL)
2867                 return I40E_ERR_PARAM;
2868
2869         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2870
2871         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2872         cmd->driver_major_ver = dv->major_version;
2873         cmd->driver_minor_ver = dv->minor_version;
2874         cmd->driver_build_ver = dv->build_version;
2875         cmd->driver_subbuild_ver = dv->subbuild_version;
2876
2877         len = 0;
2878         while (len < sizeof(dv->driver_string) &&
2879                (dv->driver_string[len] < 0x80) &&
2880                dv->driver_string[len])
2881                 len++;
2882         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2883                                        len, cmd_details);
2884
2885         return status;
2886 }
2887
2888 /**
2889  * i40e_get_link_status - get status of the HW network link
2890  * @hw: pointer to the hw struct
2891  * @link_up: pointer to bool (true/false = linkup/linkdown)
2892  *
2893  * Variable link_up true if link is up, false if link is down.
2894  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2895  *
2896  * Side effect: LinkStatusEvent reporting becomes enabled
2897  **/
2898 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2899 {
2900         enum i40e_status_code status = I40E_SUCCESS;
2901
2902         if (hw->phy.get_link_info) {
2903                 status = i40e_update_link_info(hw);
2904
2905                 if (status != I40E_SUCCESS)
2906                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2907                                    status);
2908         }
2909
2910         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2911
2912         return status;
2913 }
2914
2915 /**
2916  * i40e_updatelink_status - update status of the HW network link
2917  * @hw: pointer to the hw struct
2918  **/
2919 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2920 {
2921         struct i40e_aq_get_phy_abilities_resp abilities;
2922         enum i40e_status_code status = I40E_SUCCESS;
2923
2924         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2925         if (status)
2926                 return status;
2927
2928         /* extra checking needed to ensure link info to user is timely */
2929         if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2930             ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2931              !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2932                 status = i40e_aq_get_phy_capabilities(hw, false, false,
2933                                                       &abilities, NULL);
2934                 if (status)
2935                         return status;
2936
2937                 if (abilities.fec_cfg_curr_mod_ext_info &
2938                     I40E_AQ_ENABLE_FEC_AUTO)
2939                         hw->phy.link_info.req_fec_info =
2940                                 (I40E_AQ_REQUEST_FEC_KR |
2941                                  I40E_AQ_REQUEST_FEC_RS);
2942                 else
2943                         hw->phy.link_info.req_fec_info =
2944                                 abilities.fec_cfg_curr_mod_ext_info &
2945                                 (I40E_AQ_REQUEST_FEC_KR |
2946                                  I40E_AQ_REQUEST_FEC_RS);
2947
2948                 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2949                         sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2950         }
2951         return status;
2952 }
2953
2954
2955 /**
2956  * i40e_get_link_speed
2957  * @hw: pointer to the hw struct
2958  *
2959  * Returns the link speed of the adapter.
2960  **/
2961 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2962 {
2963         enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2964         enum i40e_status_code status = I40E_SUCCESS;
2965
2966         if (hw->phy.get_link_info) {
2967                 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2968
2969                 if (status != I40E_SUCCESS)
2970                         goto i40e_link_speed_exit;
2971         }
2972
2973         speed = hw->phy.link_info.link_speed;
2974
2975 i40e_link_speed_exit:
2976         return speed;
2977 }
2978
2979 /**
2980  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2981  * @hw: pointer to the hw struct
2982  * @uplink_seid: the MAC or other gizmo SEID
2983  * @downlink_seid: the VSI SEID
2984  * @enabled_tc: bitmap of TCs to be enabled
2985  * @default_port: true for default port VSI, false for control port
2986  * @veb_seid: pointer to where to put the resulting VEB SEID
2987  * @enable_stats: true to turn on VEB stats
2988  * @cmd_details: pointer to command details structure or NULL
2989  *
2990  * This asks the FW to add a VEB between the uplink and downlink
2991  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2992  **/
2993 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2994                                 u16 downlink_seid, u8 enabled_tc,
2995                                 bool default_port, u16 *veb_seid,
2996                                 bool enable_stats,
2997                                 struct i40e_asq_cmd_details *cmd_details)
2998 {
2999         struct i40e_aq_desc desc;
3000         struct i40e_aqc_add_veb *cmd =
3001                 (struct i40e_aqc_add_veb *)&desc.params.raw;
3002         struct i40e_aqc_add_veb_completion *resp =
3003                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
3004         enum i40e_status_code status;
3005         u16 veb_flags = 0;
3006
3007         /* SEIDs need to either both be set or both be 0 for floating VEB */
3008         if (!!uplink_seid != !!downlink_seid)
3009                 return I40E_ERR_PARAM;
3010
3011         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
3012
3013         cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
3014         cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
3015         cmd->enable_tcs = enabled_tc;
3016         if (!uplink_seid)
3017                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
3018         if (default_port)
3019                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
3020         else
3021                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
3022
3023         /* reverse logic here: set the bitflag to disable the stats */
3024         if (!enable_stats)
3025                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
3026
3027         cmd->veb_flags = CPU_TO_LE16(veb_flags);
3028
3029         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3030
3031         if (!status && veb_seid)
3032                 *veb_seid = LE16_TO_CPU(resp->veb_seid);
3033
3034         return status;
3035 }
3036
3037 /**
3038  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
3039  * @hw: pointer to the hw struct
3040  * @veb_seid: the SEID of the VEB to query
3041  * @switch_id: the uplink switch id
3042  * @floating: set to true if the VEB is floating
3043  * @statistic_index: index of the stats counter block for this VEB
3044  * @vebs_used: number of VEB's used by function
3045  * @vebs_free: total VEB's not reserved by any function
3046  * @cmd_details: pointer to command details structure or NULL
3047  *
3048  * This retrieves the parameters for a particular VEB, specified by
3049  * uplink_seid, and returns them to the caller.
3050  **/
3051 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
3052                                 u16 veb_seid, u16 *switch_id,
3053                                 bool *floating, u16 *statistic_index,
3054                                 u16 *vebs_used, u16 *vebs_free,
3055                                 struct i40e_asq_cmd_details *cmd_details)
3056 {
3057         struct i40e_aq_desc desc;
3058         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
3059                 (struct i40e_aqc_get_veb_parameters_completion *)
3060                 &desc.params.raw;
3061         enum i40e_status_code status;
3062
3063         if (veb_seid == 0)
3064                 return I40E_ERR_PARAM;
3065
3066         i40e_fill_default_direct_cmd_desc(&desc,
3067                                           i40e_aqc_opc_get_veb_parameters);
3068         cmd_resp->seid = CPU_TO_LE16(veb_seid);
3069
3070         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3071         if (status)
3072                 goto get_veb_exit;
3073
3074         if (switch_id)
3075                 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
3076         if (statistic_index)
3077                 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
3078         if (vebs_used)
3079                 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
3080         if (vebs_free)
3081                 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
3082         if (floating) {
3083                 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
3084
3085                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
3086                         *floating = true;
3087                 else
3088                         *floating = false;
3089         }
3090
3091 get_veb_exit:
3092         return status;
3093 }
3094
3095 /**
3096  * i40e_aq_add_macvlan
3097  * @hw: pointer to the hw struct
3098  * @seid: VSI for the mac address
3099  * @mv_list: list of macvlans to be added
3100  * @count: length of the list
3101  * @cmd_details: pointer to command details structure or NULL
3102  *
3103  * Add MAC/VLAN addresses to the HW filtering
3104  **/
3105 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
3106                         struct i40e_aqc_add_macvlan_element_data *mv_list,
3107                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3108 {
3109         struct i40e_aq_desc desc;
3110         struct i40e_aqc_macvlan *cmd =
3111                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3112         enum i40e_status_code status;
3113         u16 buf_size;
3114         int i;
3115
3116         if (count == 0 || !mv_list || !hw)
3117                 return I40E_ERR_PARAM;
3118
3119         buf_size = count * sizeof(*mv_list);
3120
3121         /* prep the rest of the request */
3122         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
3123         cmd->num_addresses = CPU_TO_LE16(count);
3124         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3125         cmd->seid[1] = 0;
3126         cmd->seid[2] = 0;
3127
3128         for (i = 0; i < count; i++)
3129                 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
3130                         mv_list[i].flags |=
3131                             CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
3132
3133         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3134         if (buf_size > I40E_AQ_LARGE_BUF)
3135                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3136
3137         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3138                                        cmd_details);
3139
3140         return status;
3141 }
3142
3143 /**
3144  * i40e_aq_remove_macvlan
3145  * @hw: pointer to the hw struct
3146  * @seid: VSI for the mac address
3147  * @mv_list: list of macvlans to be removed
3148  * @count: length of the list
3149  * @cmd_details: pointer to command details structure or NULL
3150  *
3151  * Remove MAC/VLAN addresses from the HW filtering
3152  **/
3153 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
3154                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
3155                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3156 {
3157         struct i40e_aq_desc desc;
3158         struct i40e_aqc_macvlan *cmd =
3159                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3160         enum i40e_status_code status;
3161         u16 buf_size;
3162
3163         if (count == 0 || !mv_list || !hw)
3164                 return I40E_ERR_PARAM;
3165
3166         buf_size = count * sizeof(*mv_list);
3167
3168         /* prep the rest of the request */
3169         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
3170         cmd->num_addresses = CPU_TO_LE16(count);
3171         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3172         cmd->seid[1] = 0;
3173         cmd->seid[2] = 0;
3174
3175         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3176         if (buf_size > I40E_AQ_LARGE_BUF)
3177                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3178
3179         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3180                                        cmd_details);
3181
3182         return status;
3183 }
3184
3185 /**
3186  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3187  * @hw: pointer to the hw struct
3188  * @opcode: AQ opcode for add or delete mirror rule
3189  * @sw_seid: Switch SEID (to which rule refers)
3190  * @rule_type: Rule Type (ingress/egress/VLAN)
3191  * @id: Destination VSI SEID or Rule ID
3192  * @count: length of the list
3193  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3194  * @cmd_details: pointer to command details structure or NULL
3195  * @rule_id: Rule ID returned from FW
3196  * @rules_used: Number of rules used in internal switch
3197  * @rules_free: Number of rules free in internal switch
3198  *
3199  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3200  * VEBs/VEPA elements only
3201  **/
3202 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3203                         u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3204                         u16 count, __le16 *mr_list,
3205                         struct i40e_asq_cmd_details *cmd_details,
3206                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3207 {
3208         struct i40e_aq_desc desc;
3209         struct i40e_aqc_add_delete_mirror_rule *cmd =
3210                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3211         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3212         (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3213         enum i40e_status_code status;
3214         u16 buf_size;
3215
3216         buf_size = count * sizeof(*mr_list);
3217
3218         /* prep the rest of the request */
3219         i40e_fill_default_direct_cmd_desc(&desc, opcode);
3220         cmd->seid = CPU_TO_LE16(sw_seid);
3221         cmd->rule_type = CPU_TO_LE16(rule_type &
3222                                      I40E_AQC_MIRROR_RULE_TYPE_MASK);
3223         cmd->num_entries = CPU_TO_LE16(count);
3224         /* Dest VSI for add, rule_id for delete */
3225         cmd->destination = CPU_TO_LE16(id);
3226         if (mr_list) {
3227                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3228                                                 I40E_AQ_FLAG_RD));
3229                 if (buf_size > I40E_AQ_LARGE_BUF)
3230                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3231         }
3232
3233         status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3234                                        cmd_details);
3235         if (status == I40E_SUCCESS ||
3236             hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3237                 if (rule_id)
3238                         *rule_id = LE16_TO_CPU(resp->rule_id);
3239                 if (rules_used)
3240                         *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3241                 if (rules_free)
3242                         *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3243         }
3244         return status;
3245 }
3246
3247 /**
3248  * i40e_aq_add_mirrorrule - add a mirror rule
3249  * @hw: pointer to the hw struct
3250  * @sw_seid: Switch SEID (to which rule refers)
3251  * @rule_type: Rule Type (ingress/egress/VLAN)
3252  * @dest_vsi: SEID of VSI to which packets will be mirrored
3253  * @count: length of the list
3254  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3255  * @cmd_details: pointer to command details structure or NULL
3256  * @rule_id: Rule ID returned from FW
3257  * @rules_used: Number of rules used in internal switch
3258  * @rules_free: Number of rules free in internal switch
3259  *
3260  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3261  **/
3262 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3263                         u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3264                         struct i40e_asq_cmd_details *cmd_details,
3265                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3266 {
3267         if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3268             rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3269                 if (count == 0 || !mr_list)
3270                         return I40E_ERR_PARAM;
3271         }
3272
3273         return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3274                                   rule_type, dest_vsi, count, mr_list,
3275                                   cmd_details, rule_id, rules_used, rules_free);
3276 }
3277
3278 /**
3279  * i40e_aq_delete_mirrorrule - delete a mirror rule
3280  * @hw: pointer to the hw struct
3281  * @sw_seid: Switch SEID (to which rule refers)
3282  * @rule_type: Rule Type (ingress/egress/VLAN)
3283  * @count: length of the list
3284  * @rule_id: Rule ID that is returned in the receive desc as part of
3285  *              add_mirrorrule.
3286  * @mr_list: list of mirrored VLAN IDs to be removed
3287  * @cmd_details: pointer to command details structure or NULL
3288  * @rules_used: Number of rules used in internal switch
3289  * @rules_free: Number of rules free in internal switch
3290  *
3291  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3292  **/
3293 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3294                         u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3295                         struct i40e_asq_cmd_details *cmd_details,
3296                         u16 *rules_used, u16 *rules_free)
3297 {
3298         /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3299         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3300                 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3301                  * mirroring. For other rule_type, count and rule_type should
3302                  * not matter.
3303                  */
3304                 if (count == 0 || !mr_list)
3305                         return I40E_ERR_PARAM;
3306         }
3307
3308         return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3309                                   rule_type, rule_id, count, mr_list,
3310                                   cmd_details, NULL, rules_used, rules_free);
3311 }
3312
3313 /**
3314  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3315  * @hw: pointer to the hw struct
3316  * @seid: VSI for the vlan filters
3317  * @v_list: list of vlan filters to be added
3318  * @count: length of the list
3319  * @cmd_details: pointer to command details structure or NULL
3320  **/
3321 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3322                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3323                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3324 {
3325         struct i40e_aq_desc desc;
3326         struct i40e_aqc_macvlan *cmd =
3327                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3328         enum i40e_status_code status;
3329         u16 buf_size;
3330
3331         if (count == 0 || !v_list || !hw)
3332                 return I40E_ERR_PARAM;
3333
3334         buf_size = count * sizeof(*v_list);
3335
3336         /* prep the rest of the request */
3337         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3338         cmd->num_addresses = CPU_TO_LE16(count);
3339         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3340         cmd->seid[1] = 0;
3341         cmd->seid[2] = 0;
3342
3343         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3344         if (buf_size > I40E_AQ_LARGE_BUF)
3345                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3346
3347         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3348                                        cmd_details);
3349
3350         return status;
3351 }
3352
3353 /**
3354  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3355  * @hw: pointer to the hw struct
3356  * @seid: VSI for the vlan filters
3357  * @v_list: list of macvlans to be removed
3358  * @count: length of the list
3359  * @cmd_details: pointer to command details structure or NULL
3360  **/
3361 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3362                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3363                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3364 {
3365         struct i40e_aq_desc desc;
3366         struct i40e_aqc_macvlan *cmd =
3367                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3368         enum i40e_status_code status;
3369         u16 buf_size;
3370
3371         if (count == 0 || !v_list || !hw)
3372                 return I40E_ERR_PARAM;
3373
3374         buf_size = count * sizeof(*v_list);
3375
3376         /* prep the rest of the request */
3377         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3378         cmd->num_addresses = CPU_TO_LE16(count);
3379         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3380         cmd->seid[1] = 0;
3381         cmd->seid[2] = 0;
3382
3383         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3384         if (buf_size > I40E_AQ_LARGE_BUF)
3385                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3386
3387         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3388                                        cmd_details);
3389
3390         return status;
3391 }
3392
3393 /**
3394  * i40e_aq_send_msg_to_vf
3395  * @hw: pointer to the hardware structure
3396  * @vfid: vf id to send msg
3397  * @v_opcode: opcodes for VF-PF communication
3398  * @v_retval: return error code
3399  * @msg: pointer to the msg buffer
3400  * @msglen: msg length
3401  * @cmd_details: pointer to command details
3402  *
3403  * send msg to vf
3404  **/
3405 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3406                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3407                                 struct i40e_asq_cmd_details *cmd_details)
3408 {
3409         struct i40e_aq_desc desc;
3410         struct i40e_aqc_pf_vf_message *cmd =
3411                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3412         enum i40e_status_code status;
3413
3414         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3415         cmd->id = CPU_TO_LE32(vfid);
3416         desc.cookie_high = CPU_TO_LE32(v_opcode);
3417         desc.cookie_low = CPU_TO_LE32(v_retval);
3418         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3419         if (msglen) {
3420                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3421                                                 I40E_AQ_FLAG_RD));
3422                 if (msglen > I40E_AQ_LARGE_BUF)
3423                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3424                 desc.datalen = CPU_TO_LE16(msglen);
3425         }
3426         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3427
3428         return status;
3429 }
3430
3431 /**
3432  * i40e_aq_debug_read_register
3433  * @hw: pointer to the hw struct
3434  * @reg_addr: register address
3435  * @reg_val: register value
3436  * @cmd_details: pointer to command details structure or NULL
3437  *
3438  * Read the register using the admin queue commands
3439  **/
3440 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3441                                 u32 reg_addr, u64 *reg_val,
3442                                 struct i40e_asq_cmd_details *cmd_details)
3443 {
3444         struct i40e_aq_desc desc;
3445         struct i40e_aqc_debug_reg_read_write *cmd_resp =
3446                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3447         enum i40e_status_code status;
3448
3449         if (reg_val == NULL)
3450                 return I40E_ERR_PARAM;
3451
3452         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3453
3454         cmd_resp->address = CPU_TO_LE32(reg_addr);
3455
3456         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3457
3458         if (status == I40E_SUCCESS) {
3459                 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3460                            (u64)LE32_TO_CPU(cmd_resp->value_low);
3461         }
3462
3463         return status;
3464 }
3465
3466 /**
3467  * i40e_aq_debug_write_register
3468  * @hw: pointer to the hw struct
3469  * @reg_addr: register address
3470  * @reg_val: register value
3471  * @cmd_details: pointer to command details structure or NULL
3472  *
3473  * Write to a register using the admin queue commands
3474  **/
3475 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3476                                 u32 reg_addr, u64 reg_val,
3477                                 struct i40e_asq_cmd_details *cmd_details)
3478 {
3479         struct i40e_aq_desc desc;
3480         struct i40e_aqc_debug_reg_read_write *cmd =
3481                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3482         enum i40e_status_code status;
3483
3484         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3485
3486         cmd->address = CPU_TO_LE32(reg_addr);
3487         cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3488         cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3489
3490         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3491
3492         return status;
3493 }
3494
3495 /**
3496  * i40e_aq_request_resource
3497  * @hw: pointer to the hw struct
3498  * @resource: resource id
3499  * @access: access type
3500  * @sdp_number: resource number
3501  * @timeout: the maximum time in ms that the driver may hold the resource
3502  * @cmd_details: pointer to command details structure or NULL
3503  *
3504  * requests common resource using the admin queue commands
3505  **/
3506 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3507                                 enum i40e_aq_resources_ids resource,
3508                                 enum i40e_aq_resource_access_type access,
3509                                 u8 sdp_number, u64 *timeout,
3510                                 struct i40e_asq_cmd_details *cmd_details)
3511 {
3512         struct i40e_aq_desc desc;
3513         struct i40e_aqc_request_resource *cmd_resp =
3514                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3515         enum i40e_status_code status;
3516
3517         DEBUGFUNC("i40e_aq_request_resource");
3518
3519         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3520
3521         cmd_resp->resource_id = CPU_TO_LE16(resource);
3522         cmd_resp->access_type = CPU_TO_LE16(access);
3523         cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3524
3525         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3526         /* The completion specifies the maximum time in ms that the driver
3527          * may hold the resource in the Timeout field.
3528          * If the resource is held by someone else, the command completes with
3529          * busy return value and the timeout field indicates the maximum time
3530          * the current owner of the resource has to free it.
3531          */
3532         if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3533                 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3534
3535         return status;
3536 }
3537
3538 /**
3539  * i40e_aq_release_resource
3540  * @hw: pointer to the hw struct
3541  * @resource: resource id
3542  * @sdp_number: resource number
3543  * @cmd_details: pointer to command details structure or NULL
3544  *
3545  * release common resource using the admin queue commands
3546  **/
3547 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3548                                 enum i40e_aq_resources_ids resource,
3549                                 u8 sdp_number,
3550                                 struct i40e_asq_cmd_details *cmd_details)
3551 {
3552         struct i40e_aq_desc desc;
3553         struct i40e_aqc_request_resource *cmd =
3554                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3555         enum i40e_status_code status;
3556
3557         DEBUGFUNC("i40e_aq_release_resource");
3558
3559         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3560
3561         cmd->resource_id = CPU_TO_LE16(resource);
3562         cmd->resource_number = CPU_TO_LE32(sdp_number);
3563
3564         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3565
3566         return status;
3567 }
3568
3569 /**
3570  * i40e_aq_read_nvm
3571  * @hw: pointer to the hw struct
3572  * @module_pointer: module pointer location in words from the NVM beginning
3573  * @offset: byte offset from the module beginning
3574  * @length: length of the section to be read (in bytes from the offset)
3575  * @data: command buffer (size [bytes] = length)
3576  * @last_command: tells if this is the last command in a series
3577  * @cmd_details: pointer to command details structure or NULL
3578  *
3579  * Read the NVM using the admin queue commands
3580  **/
3581 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3582                                 u32 offset, u16 length, void *data,
3583                                 bool last_command,
3584                                 struct i40e_asq_cmd_details *cmd_details)
3585 {
3586         struct i40e_aq_desc desc;
3587         struct i40e_aqc_nvm_update *cmd =
3588                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3589         enum i40e_status_code status;
3590
3591         DEBUGFUNC("i40e_aq_read_nvm");
3592
3593         /* In offset the highest byte must be zeroed. */
3594         if (offset & 0xFF000000) {
3595                 status = I40E_ERR_PARAM;
3596                 goto i40e_aq_read_nvm_exit;
3597         }
3598
3599         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3600
3601         /* If this is the last command in a series, set the proper flag. */
3602         if (last_command)
3603                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3604         cmd->module_pointer = module_pointer;
3605         cmd->offset = CPU_TO_LE32(offset);
3606         cmd->length = CPU_TO_LE16(length);
3607
3608         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3609         if (length > I40E_AQ_LARGE_BUF)
3610                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3611
3612         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3613
3614 i40e_aq_read_nvm_exit:
3615         return status;
3616 }
3617
3618 /**
3619  * i40e_aq_read_nvm_config - read an nvm config block
3620  * @hw: pointer to the hw struct
3621  * @cmd_flags: NVM access admin command bits
3622  * @field_id: field or feature id
3623  * @data: buffer for result
3624  * @buf_size: buffer size
3625  * @element_count: pointer to count of elements read by FW
3626  * @cmd_details: pointer to command details structure or NULL
3627  **/
3628 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3629                                 u8 cmd_flags, u32 field_id, void *data,
3630                                 u16 buf_size, u16 *element_count,
3631                                 struct i40e_asq_cmd_details *cmd_details)
3632 {
3633         struct i40e_aq_desc desc;
3634         struct i40e_aqc_nvm_config_read *cmd =
3635                 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3636         enum i40e_status_code status;
3637
3638         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3639         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3640         if (buf_size > I40E_AQ_LARGE_BUF)
3641                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3642
3643         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3644         cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3645         if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3646                 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3647         else
3648                 cmd->element_id_msw = 0;
3649
3650         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3651
3652         if (!status && element_count)
3653                 *element_count = LE16_TO_CPU(cmd->element_count);
3654
3655         return status;
3656 }
3657
3658 /**
3659  * i40e_aq_write_nvm_config - write an nvm config block
3660  * @hw: pointer to the hw struct
3661  * @cmd_flags: NVM access admin command bits
3662  * @data: buffer for result
3663  * @buf_size: buffer size
3664  * @element_count: count of elements to be written
3665  * @cmd_details: pointer to command details structure or NULL
3666  **/
3667 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3668                                 u8 cmd_flags, void *data, u16 buf_size,
3669                                 u16 element_count,
3670                                 struct i40e_asq_cmd_details *cmd_details)
3671 {
3672         struct i40e_aq_desc desc;
3673         struct i40e_aqc_nvm_config_write *cmd =
3674                 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3675         enum i40e_status_code status;
3676
3677         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3678         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3679         if (buf_size > I40E_AQ_LARGE_BUF)
3680                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3681
3682         cmd->element_count = CPU_TO_LE16(element_count);
3683         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3684         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3685
3686         return status;
3687 }
3688
3689 /**
3690  * i40e_aq_nvm_update_in_process
3691  * @hw: pointer to the hw struct
3692  * @update_flow_state: True indicates that update flow starts, false that ends
3693  * @cmd_details: pointer to command details structure or NULL
3694  *
3695  * Indicate NVM update in process.
3696  **/
3697 enum i40e_status_code
3698 i40e_aq_nvm_update_in_process(struct i40e_hw *hw,
3699                               bool update_flow_state,
3700                               struct i40e_asq_cmd_details *cmd_details)
3701 {
3702         struct i40e_aq_desc desc;
3703         struct i40e_aqc_nvm_update_in_process *cmd =
3704                 (struct i40e_aqc_nvm_update_in_process *)&desc.params.raw;
3705         enum i40e_status_code status;
3706
3707         i40e_fill_default_direct_cmd_desc(&desc,
3708                                           i40e_aqc_opc_nvm_update_in_process);
3709
3710         cmd->command = I40E_AQ_UPDATE_FLOW_END;
3711
3712         if (update_flow_state)
3713                 cmd->command |= I40E_AQ_UPDATE_FLOW_START;
3714
3715         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3716
3717         return status;
3718 }
3719
3720 /**
3721  * i40e_aq_min_rollback_rev_update - triggers an ow after update
3722  * @hw: pointer to the hw struct
3723  * @mode: opt-in mode, 1b for single module update, 0b for bulk update
3724  * @module: module to be updated. Ignored if mode is 0b
3725  * @min_rrev: value of the new minimal version. Ignored if mode is 0b
3726  * @cmd_details: pointer to command details structure or NULL
3727  **/
3728 enum i40e_status_code
3729 i40e_aq_min_rollback_rev_update(struct i40e_hw *hw, u8 mode, u8 module,
3730                                 u32 min_rrev,
3731                                 struct i40e_asq_cmd_details *cmd_details)
3732 {
3733         struct i40e_aq_desc desc;
3734         struct i40e_aqc_rollback_revision_update *cmd =
3735                 (struct i40e_aqc_rollback_revision_update *)&desc.params.raw;
3736         enum i40e_status_code status;
3737
3738         i40e_fill_default_direct_cmd_desc(&desc,
3739                 i40e_aqc_opc_rollback_revision_update);
3740         cmd->optin_mode = mode;
3741         cmd->module_selected = module;
3742         cmd->min_rrev = min_rrev;
3743
3744         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3745
3746         return status;
3747 }
3748
3749 /**
3750  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3751  * @hw: pointer to the hw struct
3752  * @buff: buffer for result
3753  * @buff_size: buffer size
3754  * @cmd_details: pointer to command details structure or NULL
3755  **/
3756 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3757                                 void *buff, u16 buff_size,
3758                                 struct i40e_asq_cmd_details *cmd_details)
3759 {
3760         struct i40e_aq_desc desc;
3761         enum i40e_status_code status;
3762
3763         UNREFERENCED_2PARAMETER(buff, buff_size);
3764
3765         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3766         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3767         if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3768                 status = I40E_ERR_NOT_IMPLEMENTED;
3769
3770         return status;
3771 }
3772
3773 /**
3774  * i40e_aq_erase_nvm
3775  * @hw: pointer to the hw struct
3776  * @module_pointer: module pointer location in words from the NVM beginning
3777  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3778  * @length: length of the section to be erased (expressed in 4 KB)
3779  * @last_command: tells if this is the last command in a series
3780  * @cmd_details: pointer to command details structure or NULL
3781  *
3782  * Erase the NVM sector using the admin queue commands
3783  **/
3784 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3785                                 u32 offset, u16 length, bool last_command,
3786                                 struct i40e_asq_cmd_details *cmd_details)
3787 {
3788         struct i40e_aq_desc desc;
3789         struct i40e_aqc_nvm_update *cmd =
3790                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3791         enum i40e_status_code status;
3792
3793         DEBUGFUNC("i40e_aq_erase_nvm");
3794
3795         /* In offset the highest byte must be zeroed. */
3796         if (offset & 0xFF000000) {
3797                 status = I40E_ERR_PARAM;
3798                 goto i40e_aq_erase_nvm_exit;
3799         }
3800
3801         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3802
3803         /* If this is the last command in a series, set the proper flag. */
3804         if (last_command)
3805                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3806         cmd->module_pointer = module_pointer;
3807         cmd->offset = CPU_TO_LE32(offset);
3808         cmd->length = CPU_TO_LE16(length);
3809
3810         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3811
3812 i40e_aq_erase_nvm_exit:
3813         return status;
3814 }
3815
3816 /**
3817  * i40e_parse_discover_capabilities
3818  * @hw: pointer to the hw struct
3819  * @buff: pointer to a buffer containing device/function capability records
3820  * @cap_count: number of capability records in the list
3821  * @list_type_opc: type of capabilities list to parse
3822  *
3823  * Parse the device/function capabilities list.
3824  **/
3825 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3826                                      u32 cap_count,
3827                                      enum i40e_admin_queue_opc list_type_opc)
3828 {
3829         struct i40e_aqc_list_capabilities_element_resp *cap;
3830         u32 valid_functions, num_functions;
3831         u32 number, logical_id, phys_id;
3832         struct i40e_hw_capabilities *p;
3833         enum i40e_status_code status;
3834         u16 id, ocp_cfg_word0;
3835         u8 major_rev;
3836         u32 i = 0;
3837
3838         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3839
3840         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3841                 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3842         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3843                 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3844         else
3845                 return;
3846
3847         for (i = 0; i < cap_count; i++, cap++) {
3848                 id = LE16_TO_CPU(cap->id);
3849                 number = LE32_TO_CPU(cap->number);
3850                 logical_id = LE32_TO_CPU(cap->logical_id);
3851                 phys_id = LE32_TO_CPU(cap->phys_id);
3852                 major_rev = cap->major_rev;
3853
3854                 switch (id) {
3855                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3856                         p->switch_mode = number;
3857                         i40e_debug(hw, I40E_DEBUG_INIT,
3858                                    "HW Capability: Switch mode = %d\n",
3859                                    p->switch_mode);
3860                         break;
3861                 case I40E_AQ_CAP_ID_MNG_MODE:
3862                         p->management_mode = number;
3863                         if (major_rev > 1) {
3864                                 p->mng_protocols_over_mctp = logical_id;
3865                                 i40e_debug(hw, I40E_DEBUG_INIT,
3866                                            "HW Capability: Protocols over MCTP = %d\n",
3867                                            p->mng_protocols_over_mctp);
3868                         } else {
3869                                 p->mng_protocols_over_mctp = 0;
3870                         }
3871                         i40e_debug(hw, I40E_DEBUG_INIT,
3872                                    "HW Capability: Management Mode = %d\n",
3873                                    p->management_mode);
3874                         break;
3875                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3876                         p->npar_enable = number;
3877                         i40e_debug(hw, I40E_DEBUG_INIT,
3878                                    "HW Capability: NPAR enable = %d\n",
3879                                    p->npar_enable);
3880                         break;
3881                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3882                         p->os2bmc = number;
3883                         i40e_debug(hw, I40E_DEBUG_INIT,
3884                                    "HW Capability: OS2BMC = %d\n", p->os2bmc);
3885                         break;
3886                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3887                         p->valid_functions = number;
3888                         i40e_debug(hw, I40E_DEBUG_INIT,
3889                                    "HW Capability: Valid Functions = %d\n",
3890                                    p->valid_functions);
3891                         break;
3892                 case I40E_AQ_CAP_ID_SRIOV:
3893                         if (number == 1)
3894                                 p->sr_iov_1_1 = true;
3895                         i40e_debug(hw, I40E_DEBUG_INIT,
3896                                    "HW Capability: SR-IOV = %d\n",
3897                                    p->sr_iov_1_1);
3898                         break;
3899                 case I40E_AQ_CAP_ID_VF:
3900                         p->num_vfs = number;
3901                         p->vf_base_id = logical_id;
3902                         i40e_debug(hw, I40E_DEBUG_INIT,
3903                                    "HW Capability: VF count = %d\n",
3904                                    p->num_vfs);
3905                         i40e_debug(hw, I40E_DEBUG_INIT,
3906                                    "HW Capability: VF base_id = %d\n",
3907                                    p->vf_base_id);
3908                         break;
3909                 case I40E_AQ_CAP_ID_VMDQ:
3910                         if (number == 1)
3911                                 p->vmdq = true;
3912                         i40e_debug(hw, I40E_DEBUG_INIT,
3913                                    "HW Capability: VMDQ = %d\n", p->vmdq);
3914                         break;
3915                 case I40E_AQ_CAP_ID_8021QBG:
3916                         if (number == 1)
3917                                 p->evb_802_1_qbg = true;
3918                         i40e_debug(hw, I40E_DEBUG_INIT,
3919                                    "HW Capability: 802.1Qbg = %d\n", number);
3920                         break;
3921                 case I40E_AQ_CAP_ID_8021QBR:
3922                         if (number == 1)
3923                                 p->evb_802_1_qbh = true;
3924                         i40e_debug(hw, I40E_DEBUG_INIT,
3925                                    "HW Capability: 802.1Qbh = %d\n", number);
3926                         break;
3927                 case I40E_AQ_CAP_ID_VSI:
3928                         p->num_vsis = number;
3929                         i40e_debug(hw, I40E_DEBUG_INIT,
3930                                    "HW Capability: VSI count = %d\n",
3931                                    p->num_vsis);
3932                         break;
3933                 case I40E_AQ_CAP_ID_DCB:
3934                         if (number == 1) {
3935                                 p->dcb = true;
3936                                 p->enabled_tcmap = logical_id;
3937                                 p->maxtc = phys_id;
3938                         }
3939                         i40e_debug(hw, I40E_DEBUG_INIT,
3940                                    "HW Capability: DCB = %d\n", p->dcb);
3941                         i40e_debug(hw, I40E_DEBUG_INIT,
3942                                    "HW Capability: TC Mapping = %d\n",
3943                                    logical_id);
3944                         i40e_debug(hw, I40E_DEBUG_INIT,
3945                                    "HW Capability: TC Max = %d\n", p->maxtc);
3946                         break;
3947                 case I40E_AQ_CAP_ID_FCOE:
3948                         if (number == 1)
3949                                 p->fcoe = true;
3950                         i40e_debug(hw, I40E_DEBUG_INIT,
3951                                    "HW Capability: FCOE = %d\n", p->fcoe);
3952                         break;
3953                 case I40E_AQ_CAP_ID_ISCSI:
3954                         if (number == 1)
3955                                 p->iscsi = true;
3956                         i40e_debug(hw, I40E_DEBUG_INIT,
3957                                    "HW Capability: iSCSI = %d\n", p->iscsi);
3958                         break;
3959                 case I40E_AQ_CAP_ID_RSS:
3960                         p->rss = true;
3961                         p->rss_table_size = number;
3962                         p->rss_table_entry_width = logical_id;
3963                         i40e_debug(hw, I40E_DEBUG_INIT,
3964                                    "HW Capability: RSS = %d\n", p->rss);
3965                         i40e_debug(hw, I40E_DEBUG_INIT,
3966                                    "HW Capability: RSS table size = %d\n",
3967                                    p->rss_table_size);
3968                         i40e_debug(hw, I40E_DEBUG_INIT,
3969                                    "HW Capability: RSS table width = %d\n",
3970                                    p->rss_table_entry_width);
3971                         break;
3972                 case I40E_AQ_CAP_ID_RXQ:
3973                         p->num_rx_qp = number;
3974                         p->base_queue = phys_id;
3975                         i40e_debug(hw, I40E_DEBUG_INIT,
3976                                    "HW Capability: Rx QP = %d\n", number);
3977                         i40e_debug(hw, I40E_DEBUG_INIT,
3978                                    "HW Capability: base_queue = %d\n",
3979                                    p->base_queue);
3980                         break;
3981                 case I40E_AQ_CAP_ID_TXQ:
3982                         p->num_tx_qp = number;
3983                         p->base_queue = phys_id;
3984                         i40e_debug(hw, I40E_DEBUG_INIT,
3985                                    "HW Capability: Tx QP = %d\n", number);
3986                         i40e_debug(hw, I40E_DEBUG_INIT,
3987                                    "HW Capability: base_queue = %d\n",
3988                                    p->base_queue);
3989                         break;
3990                 case I40E_AQ_CAP_ID_MSIX:
3991                         p->num_msix_vectors = number;
3992                         i40e_debug(hw, I40E_DEBUG_INIT,
3993                                    "HW Capability: MSIX vector count = %d\n",
3994                                    p->num_msix_vectors);
3995                         break;
3996                 case I40E_AQ_CAP_ID_VF_MSIX:
3997                         p->num_msix_vectors_vf = number;
3998                         i40e_debug(hw, I40E_DEBUG_INIT,
3999                                    "HW Capability: MSIX VF vector count = %d\n",
4000                                    p->num_msix_vectors_vf);
4001                         break;
4002                 case I40E_AQ_CAP_ID_FLEX10:
4003                         if (major_rev == 1) {
4004                                 if (number == 1) {
4005                                         p->flex10_enable = true;
4006                                         p->flex10_capable = true;
4007                                 }
4008                         } else {
4009                                 /* Capability revision >= 2 */
4010                                 if (number & 1)
4011                                         p->flex10_enable = true;
4012                                 if (number & 2)
4013                                         p->flex10_capable = true;
4014                         }
4015                         p->flex10_mode = logical_id;
4016                         p->flex10_status = phys_id;
4017                         i40e_debug(hw, I40E_DEBUG_INIT,
4018                                    "HW Capability: Flex10 mode = %d\n",
4019                                    p->flex10_mode);
4020                         i40e_debug(hw, I40E_DEBUG_INIT,
4021                                    "HW Capability: Flex10 status = %d\n",
4022                                    p->flex10_status);
4023                         break;
4024                 case I40E_AQ_CAP_ID_CEM:
4025                         if (number == 1)
4026                                 p->mgmt_cem = true;
4027                         i40e_debug(hw, I40E_DEBUG_INIT,
4028                                    "HW Capability: CEM = %d\n", p->mgmt_cem);
4029                         break;
4030                 case I40E_AQ_CAP_ID_IWARP:
4031                         if (number == 1)
4032                                 p->iwarp = true;
4033                         i40e_debug(hw, I40E_DEBUG_INIT,
4034                                    "HW Capability: iWARP = %d\n", p->iwarp);
4035                         break;
4036                 case I40E_AQ_CAP_ID_LED:
4037                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
4038                                 p->led[phys_id] = true;
4039                         i40e_debug(hw, I40E_DEBUG_INIT,
4040                                    "HW Capability: LED - PIN %d\n", phys_id);
4041                         break;
4042                 case I40E_AQ_CAP_ID_SDP:
4043                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
4044                                 p->sdp[phys_id] = true;
4045                         i40e_debug(hw, I40E_DEBUG_INIT,
4046                                    "HW Capability: SDP - PIN %d\n", phys_id);
4047                         break;
4048                 case I40E_AQ_CAP_ID_MDIO:
4049                         if (number == 1) {
4050                                 p->mdio_port_num = phys_id;
4051                                 p->mdio_port_mode = logical_id;
4052                         }
4053                         i40e_debug(hw, I40E_DEBUG_INIT,
4054                                    "HW Capability: MDIO port number = %d\n",
4055                                    p->mdio_port_num);
4056                         i40e_debug(hw, I40E_DEBUG_INIT,
4057                                    "HW Capability: MDIO port mode = %d\n",
4058                                    p->mdio_port_mode);
4059                         break;
4060                 case I40E_AQ_CAP_ID_1588:
4061                         if (number == 1)
4062                                 p->ieee_1588 = true;
4063                         i40e_debug(hw, I40E_DEBUG_INIT,
4064                                    "HW Capability: IEEE 1588 = %d\n",
4065                                    p->ieee_1588);
4066                         break;
4067                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
4068                         p->fd = true;
4069                         p->fd_filters_guaranteed = number;
4070                         p->fd_filters_best_effort = logical_id;
4071                         i40e_debug(hw, I40E_DEBUG_INIT,
4072                                    "HW Capability: Flow Director = 1\n");
4073                         i40e_debug(hw, I40E_DEBUG_INIT,
4074                                    "HW Capability: Guaranteed FD filters = %d\n",
4075                                    p->fd_filters_guaranteed);
4076                         break;
4077                 case I40E_AQ_CAP_ID_WSR_PROT:
4078                         p->wr_csr_prot = (u64)number;
4079                         p->wr_csr_prot |= (u64)logical_id << 32;
4080                         i40e_debug(hw, I40E_DEBUG_INIT,
4081                                    "HW Capability: wr_csr_prot = 0x%llX\n\n",
4082                                    (p->wr_csr_prot & 0xffff));
4083                         break;
4084                 case I40E_AQ_CAP_ID_DIS_UNUSED_PORTS:
4085                         p->dis_unused_ports = (bool)number;
4086                         i40e_debug(hw, I40E_DEBUG_INIT,
4087                                    "HW Capability: dis_unused_ports = %d\n\n",
4088                                    p->dis_unused_ports);
4089                         break;
4090                 case I40E_AQ_CAP_ID_NVM_MGMT:
4091                         if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
4092                                 p->sec_rev_disabled = true;
4093                         if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
4094                                 p->update_disabled = true;
4095                         break;
4096                 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
4097                         hw->num_wol_proxy_filters = (u16)number;
4098                         hw->wol_proxy_vsi_seid = (u16)logical_id;
4099                         p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
4100                         if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
4101                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
4102                         else
4103                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
4104                         p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
4105                         i40e_debug(hw, I40E_DEBUG_INIT,
4106                                    "HW Capability: WOL proxy filters = %d\n",
4107                                    hw->num_wol_proxy_filters);
4108                         break;
4109                 default:
4110                         break;
4111                 }
4112         }
4113
4114         if (p->fcoe)
4115                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
4116
4117         /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
4118         p->fcoe = false;
4119
4120         /* count the enabled ports (aka the "not disabled" ports) */
4121         hw->num_ports = 0;
4122         for (i = 0; i < 4; i++) {
4123                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
4124                 u64 port_cfg = 0;
4125
4126                 /* use AQ read to get the physical register offset instead
4127                  * of the port relative offset
4128                  */
4129                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
4130                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
4131                         hw->num_ports++;
4132         }
4133
4134         /* OCP cards case: if a mezz is removed the ethernet port is at
4135          * disabled state in PRTGEN_CNF register. Additional NVM read is
4136          * needed in order to check if we are dealing with OCP card.
4137          * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting
4138          * physical ports results in wrong partition id calculation and thus
4139          * not supporting WoL.
4140          */
4141         if (hw->mac.type == I40E_MAC_X722) {
4142                 if (i40e_acquire_nvm(hw, I40E_RESOURCE_READ) == I40E_SUCCESS) {
4143                         status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR,
4144                                                   2 * I40E_SR_OCP_CFG_WORD0,
4145                                                   sizeof(ocp_cfg_word0),
4146                                                   &ocp_cfg_word0, true, NULL);
4147                         if (status == I40E_SUCCESS &&
4148                             (ocp_cfg_word0 & I40E_SR_OCP_ENABLED))
4149                                 hw->num_ports = 4;
4150                         i40e_release_nvm(hw);
4151                 }
4152         }
4153
4154         valid_functions = p->valid_functions;
4155         num_functions = 0;
4156         while (valid_functions) {
4157                 if (valid_functions & 1)
4158                         num_functions++;
4159                 valid_functions >>= 1;
4160         }
4161
4162         /* partition id is 1-based, and functions are evenly spread
4163          * across the ports as partitions
4164          */
4165         if (hw->num_ports != 0) {
4166                 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
4167                 hw->num_partitions = num_functions / hw->num_ports;
4168         }
4169
4170         /* additional HW specific goodies that might
4171          * someday be HW version specific
4172          */
4173         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
4174 }
4175
4176 /**
4177  * i40e_aq_discover_capabilities
4178  * @hw: pointer to the hw struct
4179  * @buff: a virtual buffer to hold the capabilities
4180  * @buff_size: Size of the virtual buffer
4181  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
4182  * @list_type_opc: capabilities type to discover - pass in the command opcode
4183  * @cmd_details: pointer to command details structure or NULL
4184  *
4185  * Get the device capabilities descriptions from the firmware
4186  **/
4187 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
4188                                 void *buff, u16 buff_size, u16 *data_size,
4189                                 enum i40e_admin_queue_opc list_type_opc,
4190                                 struct i40e_asq_cmd_details *cmd_details)
4191 {
4192         struct i40e_aqc_list_capabilites *cmd;
4193         struct i40e_aq_desc desc;
4194         enum i40e_status_code status = I40E_SUCCESS;
4195
4196         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
4197
4198         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
4199                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
4200                 status = I40E_ERR_PARAM;
4201                 goto exit;
4202         }
4203
4204         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
4205
4206         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4207         if (buff_size > I40E_AQ_LARGE_BUF)
4208                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4209
4210         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4211         *data_size = LE16_TO_CPU(desc.datalen);
4212
4213         if (status)
4214                 goto exit;
4215
4216         i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
4217                                          list_type_opc);
4218
4219 exit:
4220         return status;
4221 }
4222
4223 /**
4224  * i40e_aq_update_nvm
4225  * @hw: pointer to the hw struct
4226  * @module_pointer: module pointer location in words from the NVM beginning
4227  * @offset: byte offset from the module beginning
4228  * @length: length of the section to be written (in bytes from the offset)
4229  * @data: command buffer (size [bytes] = length)
4230  * @last_command: tells if this is the last command in a series
4231  * @preservation_flags: Preservation mode flags
4232  * @cmd_details: pointer to command details structure or NULL
4233  *
4234  * Update the NVM using the admin queue commands
4235  **/
4236 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
4237                                 u32 offset, u16 length, void *data,
4238                                 bool last_command, u8 preservation_flags,
4239                                 struct i40e_asq_cmd_details *cmd_details)
4240 {
4241         struct i40e_aq_desc desc;
4242         struct i40e_aqc_nvm_update *cmd =
4243                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
4244         enum i40e_status_code status;
4245
4246         DEBUGFUNC("i40e_aq_update_nvm");
4247
4248         /* In offset the highest byte must be zeroed. */
4249         if (offset & 0xFF000000) {
4250                 status = I40E_ERR_PARAM;
4251                 goto i40e_aq_update_nvm_exit;
4252         }
4253
4254         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4255
4256         /* If this is the last command in a series, set the proper flag. */
4257         if (last_command)
4258                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
4259         if (hw->mac.type == I40E_MAC_X722) {
4260                 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED)
4261                         cmd->command_flags |=
4262                                 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED <<
4263                                  I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4264                 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL)
4265                         cmd->command_flags |=
4266                                 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL <<
4267                                  I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4268         }
4269         cmd->module_pointer = module_pointer;
4270         cmd->offset = CPU_TO_LE32(offset);
4271         cmd->length = CPU_TO_LE16(length);
4272
4273         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4274         if (length > I40E_AQ_LARGE_BUF)
4275                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4276
4277         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
4278
4279 i40e_aq_update_nvm_exit:
4280         return status;
4281 }
4282
4283 /**
4284  * i40e_aq_rearrange_nvm
4285  * @hw: pointer to the hw struct
4286  * @rearrange_nvm: defines direction of rearrangement
4287  * @cmd_details: pointer to command details structure or NULL
4288  *
4289  * Rearrange NVM structure, available only for transition FW
4290  **/
4291 enum i40e_status_code i40e_aq_rearrange_nvm(struct i40e_hw *hw,
4292                                 u8 rearrange_nvm,
4293                                 struct i40e_asq_cmd_details *cmd_details)
4294 {
4295         struct i40e_aqc_nvm_update *cmd;
4296         enum i40e_status_code status;
4297         struct i40e_aq_desc desc;
4298
4299         DEBUGFUNC("i40e_aq_rearrange_nvm");
4300
4301         cmd = (struct i40e_aqc_nvm_update *)&desc.params.raw;
4302
4303         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4304
4305         rearrange_nvm &= (I40E_AQ_NVM_REARRANGE_TO_FLAT |
4306                          I40E_AQ_NVM_REARRANGE_TO_STRUCT);
4307
4308         if (!rearrange_nvm) {
4309                 status = I40E_ERR_PARAM;
4310                 goto i40e_aq_rearrange_nvm_exit;
4311         }
4312
4313         cmd->command_flags |= rearrange_nvm;
4314         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4315
4316 i40e_aq_rearrange_nvm_exit:
4317         return status;
4318 }
4319
4320 /**
4321  * i40e_aq_get_lldp_mib
4322  * @hw: pointer to the hw struct
4323  * @bridge_type: type of bridge requested
4324  * @mib_type: Local, Remote or both Local and Remote MIBs
4325  * @buff: pointer to a user supplied buffer to store the MIB block
4326  * @buff_size: size of the buffer (in bytes)
4327  * @local_len : length of the returned Local LLDP MIB
4328  * @remote_len: length of the returned Remote LLDP MIB
4329  * @cmd_details: pointer to command details structure or NULL
4330  *
4331  * Requests the complete LLDP MIB (entire packet).
4332  **/
4333 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4334                                 u8 mib_type, void *buff, u16 buff_size,
4335                                 u16 *local_len, u16 *remote_len,
4336                                 struct i40e_asq_cmd_details *cmd_details)
4337 {
4338         struct i40e_aq_desc desc;
4339         struct i40e_aqc_lldp_get_mib *cmd =
4340                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4341         struct i40e_aqc_lldp_get_mib *resp =
4342                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4343         enum i40e_status_code status;
4344
4345         if (buff_size == 0 || !buff)
4346                 return I40E_ERR_PARAM;
4347
4348         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4349         /* Indirect Command */
4350         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4351
4352         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4353         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4354                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4355
4356         desc.datalen = CPU_TO_LE16(buff_size);
4357
4358         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4359         if (buff_size > I40E_AQ_LARGE_BUF)
4360                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4361
4362         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4363         if (!status) {
4364                 if (local_len != NULL)
4365                         *local_len = LE16_TO_CPU(resp->local_len);
4366                 if (remote_len != NULL)
4367                         *remote_len = LE16_TO_CPU(resp->remote_len);
4368         }
4369
4370         return status;
4371 }
4372
4373  /**
4374  * i40e_aq_set_lldp_mib - Set the LLDP MIB
4375  * @hw: pointer to the hw struct
4376  * @mib_type: Local, Remote or both Local and Remote MIBs
4377  * @buff: pointer to a user supplied buffer to store the MIB block
4378  * @buff_size: size of the buffer (in bytes)
4379  * @cmd_details: pointer to command details structure or NULL
4380  *
4381  * Set the LLDP MIB.
4382  **/
4383 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4384                                 u8 mib_type, void *buff, u16 buff_size,
4385                                 struct i40e_asq_cmd_details *cmd_details)
4386 {
4387         struct i40e_aq_desc desc;
4388         struct i40e_aqc_lldp_set_local_mib *cmd =
4389                 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4390         enum i40e_status_code status;
4391
4392         if (buff_size == 0 || !buff)
4393                 return I40E_ERR_PARAM;
4394
4395         i40e_fill_default_direct_cmd_desc(&desc,
4396                                 i40e_aqc_opc_lldp_set_local_mib);
4397         /* Indirect Command */
4398         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4399         if (buff_size > I40E_AQ_LARGE_BUF)
4400                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4401         desc.datalen = CPU_TO_LE16(buff_size);
4402
4403         cmd->type = mib_type;
4404         cmd->length = CPU_TO_LE16(buff_size);
4405         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)buff));
4406         cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4407
4408         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4409         return status;
4410 }
4411
4412 /**
4413  * i40e_aq_cfg_lldp_mib_change_event
4414  * @hw: pointer to the hw struct
4415  * @enable_update: Enable or Disable event posting
4416  * @cmd_details: pointer to command details structure or NULL
4417  *
4418  * Enable or Disable posting of an event on ARQ when LLDP MIB
4419  * associated with the interface changes
4420  **/
4421 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4422                                 bool enable_update,
4423                                 struct i40e_asq_cmd_details *cmd_details)
4424 {
4425         struct i40e_aq_desc desc;
4426         struct i40e_aqc_lldp_update_mib *cmd =
4427                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4428         enum i40e_status_code status;
4429
4430         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4431
4432         if (!enable_update)
4433                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4434
4435         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4436
4437         return status;
4438 }
4439
4440 /**
4441  * i40e_aq_restore_lldp
4442  * @hw: pointer to the hw struct
4443  * @setting: pointer to factory setting variable or NULL
4444  * @restore: True if factory settings should be restored
4445  * @cmd_details: pointer to command details structure or NULL
4446  *
4447  * Restore LLDP Agent factory settings if @restore set to True. In other case
4448  * only returns factory setting in AQ response.
4449  **/
4450 enum i40e_status_code
4451 i40e_aq_restore_lldp(struct i40e_hw *hw, u8 *setting, bool restore,
4452                      struct i40e_asq_cmd_details *cmd_details)
4453 {
4454         struct i40e_aq_desc desc;
4455         struct i40e_aqc_lldp_restore *cmd =
4456                 (struct i40e_aqc_lldp_restore *)&desc.params.raw;
4457         enum i40e_status_code status;
4458
4459         if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)) {
4460                 i40e_debug(hw, I40E_DEBUG_ALL,
4461                            "Restore LLDP not supported by current FW version.\n");
4462                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
4463         }
4464
4465         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_restore);
4466
4467         if (restore)
4468                 cmd->command |= I40E_AQ_LLDP_AGENT_RESTORE;
4469
4470         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4471
4472         if (setting)
4473                 *setting = cmd->command & 1;
4474
4475         return status;
4476 }
4477
4478 /**
4479  * i40e_aq_stop_lldp
4480  * @hw: pointer to the hw struct
4481  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4482  * @persist: True if stop of LLDP should be persistent across power cycles
4483  * @cmd_details: pointer to command details structure or NULL
4484  *
4485  * Stop or Shutdown the embedded LLDP Agent
4486  **/
4487 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4488                                 bool persist,
4489                                 struct i40e_asq_cmd_details *cmd_details)
4490 {
4491         struct i40e_aq_desc desc;
4492         struct i40e_aqc_lldp_stop *cmd =
4493                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4494         enum i40e_status_code status;
4495
4496         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4497
4498         if (shutdown_agent)
4499                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4500
4501         if (persist) {
4502                 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)
4503                         cmd->command |= I40E_AQ_LLDP_AGENT_STOP_PERSIST;
4504                 else
4505                         i40e_debug(hw, I40E_DEBUG_ALL,
4506                                    "Persistent Stop LLDP not supported by current FW version.\n");
4507         }
4508
4509         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4510
4511         return status;
4512 }
4513
4514 /**
4515  * i40e_aq_start_lldp
4516  * @hw: pointer to the hw struct
4517  * @persist: True if start of LLDP should be persistent across power cycles
4518  * @cmd_details: pointer to command details structure or NULL
4519  *
4520  * Start the embedded LLDP Agent on all ports.
4521  **/
4522 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4523                                 bool persist,
4524                                 struct i40e_asq_cmd_details *cmd_details)
4525 {
4526         struct i40e_aq_desc desc;
4527         struct i40e_aqc_lldp_start *cmd =
4528                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4529         enum i40e_status_code status;
4530
4531         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4532
4533         cmd->command = I40E_AQ_LLDP_AGENT_START;
4534
4535         if (persist) {
4536                 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)
4537                         cmd->command |= I40E_AQ_LLDP_AGENT_START_PERSIST;
4538                 else
4539                         i40e_debug(hw, I40E_DEBUG_ALL,
4540                                    "Persistent Start LLDP not supported by current FW version.\n");
4541         }
4542
4543         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4544
4545         return status;
4546 }
4547
4548 /**
4549  * i40e_aq_set_dcb_parameters
4550  * @hw: pointer to the hw struct
4551  * @cmd_details: pointer to command details structure or NULL
4552  * @dcb_enable: True if DCB configuration needs to be applied
4553  *
4554  **/
4555 enum i40e_status_code
4556 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable,
4557                            struct i40e_asq_cmd_details *cmd_details)
4558 {
4559         struct i40e_aq_desc desc;
4560         struct i40e_aqc_set_dcb_parameters *cmd =
4561                 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw;
4562         enum i40e_status_code status;
4563
4564         if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_STOPPABLE))
4565                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
4566
4567         i40e_fill_default_direct_cmd_desc(&desc,
4568                                           i40e_aqc_opc_set_dcb_parameters);
4569
4570         if (dcb_enable) {
4571                 cmd->valid_flags = I40E_DCB_VALID;
4572                 cmd->command = I40E_AQ_DCB_SET_AGENT;
4573         }
4574         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4575
4576         return status;
4577 }
4578
4579 /**
4580  * i40e_aq_get_cee_dcb_config
4581  * @hw: pointer to the hw struct
4582  * @buff: response buffer that stores CEE operational configuration
4583  * @buff_size: size of the buffer passed
4584  * @cmd_details: pointer to command details structure or NULL
4585  *
4586  * Get CEE DCBX mode operational configuration from firmware
4587  **/
4588 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4589                                 void *buff, u16 buff_size,
4590                                 struct i40e_asq_cmd_details *cmd_details)
4591 {
4592         struct i40e_aq_desc desc;
4593         enum i40e_status_code status;
4594
4595         if (buff_size == 0 || !buff)
4596                 return I40E_ERR_PARAM;
4597
4598         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4599
4600         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4601         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4602                                        cmd_details);
4603
4604         return status;
4605 }
4606
4607 /**
4608  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4609  * @hw: pointer to the hw struct
4610  * @start_agent: True if DCBx Agent needs to be Started
4611  *                              False if DCBx Agent needs to be Stopped
4612  * @cmd_details: pointer to command details structure or NULL
4613  *
4614  * Start/Stop the embedded dcbx Agent
4615  **/
4616 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4617                                 bool start_agent,
4618                                 struct i40e_asq_cmd_details *cmd_details)
4619 {
4620         struct i40e_aq_desc desc;
4621         struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4622                 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4623                                 &desc.params.raw;
4624         enum i40e_status_code status;
4625
4626         i40e_fill_default_direct_cmd_desc(&desc,
4627                                 i40e_aqc_opc_lldp_stop_start_spec_agent);
4628
4629         if (start_agent)
4630                 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4631
4632         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4633
4634         return status;
4635 }
4636
4637 /**
4638  * i40e_aq_add_udp_tunnel
4639  * @hw: pointer to the hw struct
4640  * @udp_port: the UDP port to add in Host byte order
4641  * @protocol_index: protocol index type
4642  * @filter_index: pointer to filter index
4643  * @cmd_details: pointer to command details structure or NULL
4644  *
4645  * Note: Firmware expects the udp_port value to be in Little Endian format,
4646  * and this function will call CPU_TO_LE16 to convert from Host byte order to
4647  * Little Endian order.
4648  **/
4649 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4650                                 u16 udp_port, u8 protocol_index,
4651                                 u8 *filter_index,
4652                                 struct i40e_asq_cmd_details *cmd_details)
4653 {
4654         struct i40e_aq_desc desc;
4655         struct i40e_aqc_add_udp_tunnel *cmd =
4656                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4657         struct i40e_aqc_del_udp_tunnel_completion *resp =
4658                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4659         enum i40e_status_code status;
4660
4661         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4662
4663         cmd->udp_port = CPU_TO_LE16(udp_port);
4664         cmd->protocol_type = protocol_index;
4665
4666         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4667
4668         if (!status && filter_index)
4669                 *filter_index = resp->index;
4670
4671         return status;
4672 }
4673
4674 /**
4675  * i40e_aq_del_udp_tunnel
4676  * @hw: pointer to the hw struct
4677  * @index: filter index
4678  * @cmd_details: pointer to command details structure or NULL
4679  **/
4680 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4681                                 struct i40e_asq_cmd_details *cmd_details)
4682 {
4683         struct i40e_aq_desc desc;
4684         struct i40e_aqc_remove_udp_tunnel *cmd =
4685                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4686         enum i40e_status_code status;
4687
4688         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4689
4690         cmd->index = index;
4691
4692         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4693
4694         return status;
4695 }
4696
4697 /**
4698  * i40e_aq_get_switch_resource_alloc (0x0204)
4699  * @hw: pointer to the hw struct
4700  * @num_entries: pointer to u8 to store the number of resource entries returned
4701  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
4702  *        to store the resource information for all resource types.  Each
4703  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
4704  * @count: size, in bytes, of the buffer provided
4705  * @cmd_details: pointer to command details structure or NULL
4706  *
4707  * Query the resources allocated to a function.
4708  **/
4709 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4710                         u8 *num_entries,
4711                         struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4712                         u16 count,
4713                         struct i40e_asq_cmd_details *cmd_details)
4714 {
4715         struct i40e_aq_desc desc;
4716         struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4717                 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4718         enum i40e_status_code status;
4719         u16 length = count * sizeof(*buf);
4720
4721         i40e_fill_default_direct_cmd_desc(&desc,
4722                                         i40e_aqc_opc_get_switch_resource_alloc);
4723
4724         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4725         if (length > I40E_AQ_LARGE_BUF)
4726                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4727
4728         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4729
4730         if (!status && num_entries)
4731                 *num_entries = cmd_resp->num_entries;
4732
4733         return status;
4734 }
4735
4736 /**
4737  * i40e_aq_delete_element - Delete switch element
4738  * @hw: pointer to the hw struct
4739  * @seid: the SEID to delete from the switch
4740  * @cmd_details: pointer to command details structure or NULL
4741  *
4742  * This deletes a switch element from the switch.
4743  **/
4744 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4745                                 struct i40e_asq_cmd_details *cmd_details)
4746 {
4747         struct i40e_aq_desc desc;
4748         struct i40e_aqc_switch_seid *cmd =
4749                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4750         enum i40e_status_code status;
4751
4752         if (seid == 0)
4753                 return I40E_ERR_PARAM;
4754
4755         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4756
4757         cmd->seid = CPU_TO_LE16(seid);
4758
4759         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4760
4761         return status;
4762 }
4763
4764 /**
4765  * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4766  * @hw: pointer to the hw struct
4767  * @flags: component flags
4768  * @mac_seid: uplink seid (MAC SEID)
4769  * @vsi_seid: connected vsi seid
4770  * @ret_seid: seid of create pv component
4771  *
4772  * This instantiates an i40e port virtualizer with specified flags.
4773  * Depending on specified flags the port virtualizer can act as a
4774  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4775  */
4776 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4777                                        u16 mac_seid, u16 vsi_seid,
4778                                        u16 *ret_seid)
4779 {
4780         struct i40e_aq_desc desc;
4781         struct i40e_aqc_add_update_pv *cmd =
4782                 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4783         struct i40e_aqc_add_update_pv_completion *resp =
4784                 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4785         enum i40e_status_code status;
4786
4787         if (vsi_seid == 0)
4788                 return I40E_ERR_PARAM;
4789
4790         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4791         cmd->command_flags = CPU_TO_LE16(flags);
4792         cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4793         cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4794
4795         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4796         if (!status && ret_seid)
4797                 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4798
4799         return status;
4800 }
4801
4802 /**
4803  * i40e_aq_add_tag - Add an S/E-tag
4804  * @hw: pointer to the hw struct
4805  * @direct_to_queue: should s-tag direct flow to a specific queue
4806  * @vsi_seid: VSI SEID to use this tag
4807  * @tag: value of the tag
4808  * @queue_num: queue number, only valid is direct_to_queue is true
4809  * @tags_used: return value, number of tags in use by this PF
4810  * @tags_free: return value, number of unallocated tags
4811  * @cmd_details: pointer to command details structure or NULL
4812  *
4813  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4814  * the number of tags allocated by the PF, and the number of unallocated
4815  * tags available.
4816  **/
4817 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4818                                 u16 vsi_seid, u16 tag, u16 queue_num,
4819                                 u16 *tags_used, u16 *tags_free,
4820                                 struct i40e_asq_cmd_details *cmd_details)
4821 {
4822         struct i40e_aq_desc desc;
4823         struct i40e_aqc_add_tag *cmd =
4824                 (struct i40e_aqc_add_tag *)&desc.params.raw;
4825         struct i40e_aqc_add_remove_tag_completion *resp =
4826                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4827         enum i40e_status_code status;
4828
4829         if (vsi_seid == 0)
4830                 return I40E_ERR_PARAM;
4831
4832         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4833
4834         cmd->seid = CPU_TO_LE16(vsi_seid);
4835         cmd->tag = CPU_TO_LE16(tag);
4836         if (direct_to_queue) {
4837                 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4838                 cmd->queue_number = CPU_TO_LE16(queue_num);
4839         }
4840
4841         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4842
4843         if (!status) {
4844                 if (tags_used != NULL)
4845                         *tags_used = LE16_TO_CPU(resp->tags_used);
4846                 if (tags_free != NULL)
4847                         *tags_free = LE16_TO_CPU(resp->tags_free);
4848         }
4849
4850         return status;
4851 }
4852
4853 /**
4854  * i40e_aq_remove_tag - Remove an S- or E-tag
4855  * @hw: pointer to the hw struct
4856  * @vsi_seid: VSI SEID this tag is associated with
4857  * @tag: value of the S-tag to delete
4858  * @tags_used: return value, number of tags in use by this PF
4859  * @tags_free: return value, number of unallocated tags
4860  * @cmd_details: pointer to command details structure or NULL
4861  *
4862  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4863  * the number of tags allocated by the PF, and the number of unallocated
4864  * tags available.
4865  **/
4866 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4867                                 u16 tag, u16 *tags_used, u16 *tags_free,
4868                                 struct i40e_asq_cmd_details *cmd_details)
4869 {
4870         struct i40e_aq_desc desc;
4871         struct i40e_aqc_remove_tag *cmd =
4872                 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4873         struct i40e_aqc_add_remove_tag_completion *resp =
4874                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4875         enum i40e_status_code status;
4876
4877         if (vsi_seid == 0)
4878                 return I40E_ERR_PARAM;
4879
4880         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4881
4882         cmd->seid = CPU_TO_LE16(vsi_seid);
4883         cmd->tag = CPU_TO_LE16(tag);
4884
4885         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4886
4887         if (!status) {
4888                 if (tags_used != NULL)
4889                         *tags_used = LE16_TO_CPU(resp->tags_used);
4890                 if (tags_free != NULL)
4891                         *tags_free = LE16_TO_CPU(resp->tags_free);
4892         }
4893
4894         return status;
4895 }
4896
4897 /**
4898  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4899  * @hw: pointer to the hw struct
4900  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4901  * @etag: value of E-tag to add
4902  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4903  * @buf: address of indirect buffer
4904  * @tags_used: return value, number of E-tags in use by this port
4905  * @tags_free: return value, number of unallocated M-tags
4906  * @cmd_details: pointer to command details structure or NULL
4907  *
4908  * This associates a multicast E-tag to a port virtualizer.  It will return
4909  * the number of tags allocated by the PF, and the number of unallocated
4910  * tags available.
4911  *
4912  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4913  * num_tags_in_buf long.
4914  **/
4915 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4916                                 u16 etag, u8 num_tags_in_buf, void *buf,
4917                                 u16 *tags_used, u16 *tags_free,
4918                                 struct i40e_asq_cmd_details *cmd_details)
4919 {
4920         struct i40e_aq_desc desc;
4921         struct i40e_aqc_add_remove_mcast_etag *cmd =
4922                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4923         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4924            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4925         enum i40e_status_code status;
4926         u16 length = sizeof(u16) * num_tags_in_buf;
4927
4928         if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4929                 return I40E_ERR_PARAM;
4930
4931         i40e_fill_default_direct_cmd_desc(&desc,
4932                                           i40e_aqc_opc_add_multicast_etag);
4933
4934         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4935         cmd->etag = CPU_TO_LE16(etag);
4936         cmd->num_unicast_etags = num_tags_in_buf;
4937
4938         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4939
4940         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4941
4942         if (!status) {
4943                 if (tags_used != NULL)
4944                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4945                 if (tags_free != NULL)
4946                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4947         }
4948
4949         return status;
4950 }
4951
4952 /**
4953  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4954  * @hw: pointer to the hw struct
4955  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4956  * @etag: value of the E-tag to remove
4957  * @tags_used: return value, number of tags in use by this port
4958  * @tags_free: return value, number of unallocated tags
4959  * @cmd_details: pointer to command details structure or NULL
4960  *
4961  * This deletes an E-tag from the port virtualizer.  It will return
4962  * the number of tags allocated by the port, and the number of unallocated
4963  * tags available.
4964  **/
4965 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4966                                 u16 etag, u16 *tags_used, u16 *tags_free,
4967                                 struct i40e_asq_cmd_details *cmd_details)
4968 {
4969         struct i40e_aq_desc desc;
4970         struct i40e_aqc_add_remove_mcast_etag *cmd =
4971                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4972         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4973            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4974         enum i40e_status_code status;
4975
4976
4977         if (pv_seid == 0)
4978                 return I40E_ERR_PARAM;
4979
4980         i40e_fill_default_direct_cmd_desc(&desc,
4981                                           i40e_aqc_opc_remove_multicast_etag);
4982
4983         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4984         cmd->etag = CPU_TO_LE16(etag);
4985
4986         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4987
4988         if (!status) {
4989                 if (tags_used != NULL)
4990                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4991                 if (tags_free != NULL)
4992                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4993         }
4994
4995         return status;
4996 }
4997
4998 /**
4999  * i40e_aq_update_tag - Update an S/E-tag
5000  * @hw: pointer to the hw struct
5001  * @vsi_seid: VSI SEID using this S-tag
5002  * @old_tag: old tag value
5003  * @new_tag: new tag value
5004  * @tags_used: return value, number of tags in use by this PF
5005  * @tags_free: return value, number of unallocated tags
5006  * @cmd_details: pointer to command details structure or NULL
5007  *
5008  * This updates the value of the tag currently attached to this VSI
5009  * in the switch complex.  It will return the number of tags allocated
5010  * by the PF, and the number of unallocated tags available.
5011  **/
5012 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
5013                                 u16 old_tag, u16 new_tag, u16 *tags_used,
5014                                 u16 *tags_free,
5015                                 struct i40e_asq_cmd_details *cmd_details)
5016 {
5017         struct i40e_aq_desc desc;
5018         struct i40e_aqc_update_tag *cmd =
5019                 (struct i40e_aqc_update_tag *)&desc.params.raw;
5020         struct i40e_aqc_update_tag_completion *resp =
5021                 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
5022         enum i40e_status_code status;
5023
5024         if (vsi_seid == 0)
5025                 return I40E_ERR_PARAM;
5026
5027         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
5028
5029         cmd->seid = CPU_TO_LE16(vsi_seid);
5030         cmd->old_tag = CPU_TO_LE16(old_tag);
5031         cmd->new_tag = CPU_TO_LE16(new_tag);
5032
5033         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5034
5035         if (!status) {
5036                 if (tags_used != NULL)
5037                         *tags_used = LE16_TO_CPU(resp->tags_used);
5038                 if (tags_free != NULL)
5039                         *tags_free = LE16_TO_CPU(resp->tags_free);
5040         }
5041
5042         return status;
5043 }
5044
5045 /**
5046  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
5047  * @hw: pointer to the hw struct
5048  * @tcmap: TC map for request/release any ignore PFC condition
5049  * @request: request or release ignore PFC condition
5050  * @tcmap_ret: return TCs for which PFC is currently ignored
5051  * @cmd_details: pointer to command details structure or NULL
5052  *
5053  * This sends out request/release to ignore PFC condition for a TC.
5054  * It will return the TCs for which PFC is currently ignored.
5055  **/
5056 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
5057                                 bool request, u8 *tcmap_ret,
5058                                 struct i40e_asq_cmd_details *cmd_details)
5059 {
5060         struct i40e_aq_desc desc;
5061         struct i40e_aqc_pfc_ignore *cmd_resp =
5062                 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
5063         enum i40e_status_code status;
5064
5065         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
5066
5067         if (request)
5068                 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
5069
5070         cmd_resp->tc_bitmap = tcmap;
5071
5072         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5073
5074         if (!status) {
5075                 if (tcmap_ret != NULL)
5076                         *tcmap_ret = cmd_resp->tc_bitmap;
5077         }
5078
5079         return status;
5080 }
5081
5082 /**
5083  * i40e_aq_dcb_updated - DCB Updated Command
5084  * @hw: pointer to the hw struct
5085  * @cmd_details: pointer to command details structure or NULL
5086  *
5087  * When LLDP is handled in PF this command is used by the PF
5088  * to notify EMP that a DCB setting is modified.
5089  * When LLDP is handled in EMP this command is used by the PF
5090  * to notify EMP whenever one of the following parameters get
5091  * modified:
5092  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
5093  *   - PCIRTT in PRTDCB_GENC.PCIRTT
5094  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
5095  * EMP will return when the shared RPB settings have been
5096  * recomputed and modified. The retval field in the descriptor
5097  * will be set to 0 when RPB is modified.
5098  **/
5099 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
5100                                 struct i40e_asq_cmd_details *cmd_details)
5101 {
5102         struct i40e_aq_desc desc;
5103         enum i40e_status_code status;
5104
5105         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
5106
5107         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5108
5109         return status;
5110 }
5111
5112 /**
5113  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
5114  * @hw: pointer to the hw struct
5115  * @seid: defines the SEID of the switch for which the stats are requested
5116  * @vlan_id: the VLAN ID for which the statistics are requested
5117  * @stat_index: index of the statistics counters block assigned to this VLAN
5118  * @cmd_details: pointer to command details structure or NULL
5119  *
5120  * XL710 supports 128 smonVlanStats counters.This command is used to
5121  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
5122  * switch.
5123  **/
5124 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
5125                                 u16 vlan_id, u16 *stat_index,
5126                                 struct i40e_asq_cmd_details *cmd_details)
5127 {
5128         struct i40e_aq_desc desc;
5129         struct i40e_aqc_add_remove_statistics *cmd_resp =
5130                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5131         enum i40e_status_code status;
5132
5133         if ((seid == 0) || (stat_index == NULL))
5134                 return I40E_ERR_PARAM;
5135
5136         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
5137
5138         cmd_resp->seid = CPU_TO_LE16(seid);
5139         cmd_resp->vlan = CPU_TO_LE16(vlan_id);
5140
5141         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5142
5143         if (!status && stat_index)
5144                 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
5145
5146         return status;
5147 }
5148
5149 /**
5150  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
5151  * @hw: pointer to the hw struct
5152  * @seid: defines the SEID of the switch for which the stats are requested
5153  * @vlan_id: the VLAN ID for which the statistics are requested
5154  * @stat_index: index of the statistics counters block assigned to this VLAN
5155  * @cmd_details: pointer to command details structure or NULL
5156  *
5157  * XL710 supports 128 smonVlanStats counters.This command is used to
5158  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
5159  * switch.
5160  **/
5161 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
5162                                 u16 vlan_id, u16 stat_index,
5163                                 struct i40e_asq_cmd_details *cmd_details)
5164 {
5165         struct i40e_aq_desc desc;
5166         struct i40e_aqc_add_remove_statistics *cmd =
5167                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5168         enum i40e_status_code status;
5169
5170         if (seid == 0)
5171                 return I40E_ERR_PARAM;
5172
5173         i40e_fill_default_direct_cmd_desc(&desc,
5174                                           i40e_aqc_opc_remove_statistics);
5175
5176         cmd->seid = CPU_TO_LE16(seid);
5177         cmd->vlan  = CPU_TO_LE16(vlan_id);
5178         cmd->stat_index = CPU_TO_LE16(stat_index);
5179
5180         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5181
5182         return status;
5183 }
5184
5185 /**
5186  * i40e_aq_set_port_parameters - set physical port parameters.
5187  * @hw: pointer to the hw struct
5188  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
5189  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
5190  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
5191  * @double_vlan: if set double VLAN is enabled
5192  * @cmd_details: pointer to command details structure or NULL
5193  **/
5194 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
5195                                 u16 bad_frame_vsi, bool save_bad_pac,
5196                                 bool pad_short_pac, bool double_vlan,
5197                                 struct i40e_asq_cmd_details *cmd_details)
5198 {
5199         struct i40e_aqc_set_port_parameters *cmd;
5200         enum i40e_status_code status;
5201         struct i40e_aq_desc desc;
5202         u16 command_flags = 0;
5203
5204         cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
5205
5206         i40e_fill_default_direct_cmd_desc(&desc,
5207                                           i40e_aqc_opc_set_port_parameters);
5208
5209         cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
5210         if (save_bad_pac)
5211                 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
5212         if (pad_short_pac)
5213                 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
5214         if (double_vlan)
5215                 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
5216         cmd->command_flags = CPU_TO_LE16(command_flags);
5217
5218         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5219
5220         return status;
5221 }
5222
5223 /**
5224  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
5225  * @hw: pointer to the hw struct
5226  * @seid: seid for the physical port/switching component/vsi
5227  * @buff: Indirect buffer to hold data parameters and response
5228  * @buff_size: Indirect buffer size
5229  * @opcode: Tx scheduler AQ command opcode
5230  * @cmd_details: pointer to command details structure or NULL
5231  *
5232  * Generic command handler for Tx scheduler AQ commands
5233  **/
5234 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
5235                                 void *buff, u16 buff_size,
5236                                  enum i40e_admin_queue_opc opcode,
5237                                 struct i40e_asq_cmd_details *cmd_details)
5238 {
5239         struct i40e_aq_desc desc;
5240         struct i40e_aqc_tx_sched_ind *cmd =
5241                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
5242         enum i40e_status_code status;
5243         bool cmd_param_flag = false;
5244
5245         switch (opcode) {
5246         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
5247         case i40e_aqc_opc_configure_vsi_tc_bw:
5248         case i40e_aqc_opc_enable_switching_comp_ets:
5249         case i40e_aqc_opc_modify_switching_comp_ets:
5250         case i40e_aqc_opc_disable_switching_comp_ets:
5251         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
5252         case i40e_aqc_opc_configure_switching_comp_bw_config:
5253                 cmd_param_flag = true;
5254                 break;
5255         case i40e_aqc_opc_query_vsi_bw_config:
5256         case i40e_aqc_opc_query_vsi_ets_sla_config:
5257         case i40e_aqc_opc_query_switching_comp_ets_config:
5258         case i40e_aqc_opc_query_port_ets_config:
5259         case i40e_aqc_opc_query_switching_comp_bw_config:
5260                 cmd_param_flag = false;
5261                 break;
5262         default:
5263                 return I40E_ERR_PARAM;
5264         }
5265
5266         i40e_fill_default_direct_cmd_desc(&desc, opcode);
5267
5268         /* Indirect command */
5269         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5270         if (cmd_param_flag)
5271                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5272         if (buff_size > I40E_AQ_LARGE_BUF)
5273                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5274
5275         desc.datalen = CPU_TO_LE16(buff_size);
5276
5277         cmd->vsi_seid = CPU_TO_LE16(seid);
5278
5279         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5280
5281         return status;
5282 }
5283
5284 /**
5285  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5286  * @hw: pointer to the hw struct
5287  * @seid: VSI seid
5288  * @credit: BW limit credits (0 = disabled)
5289  * @max_credit: Max BW limit credits
5290  * @cmd_details: pointer to command details structure or NULL
5291  **/
5292 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5293                                 u16 seid, u16 credit, u8 max_credit,
5294                                 struct i40e_asq_cmd_details *cmd_details)
5295 {
5296         struct i40e_aq_desc desc;
5297         struct i40e_aqc_configure_vsi_bw_limit *cmd =
5298                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5299         enum i40e_status_code status;
5300
5301         i40e_fill_default_direct_cmd_desc(&desc,
5302                                           i40e_aqc_opc_configure_vsi_bw_limit);
5303
5304         cmd->vsi_seid = CPU_TO_LE16(seid);
5305         cmd->credit = CPU_TO_LE16(credit);
5306         cmd->max_credit = max_credit;
5307
5308         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5309
5310         return status;
5311 }
5312
5313 /**
5314  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5315  * @hw: pointer to the hw struct
5316  * @seid: switching component seid
5317  * @credit: BW limit credits (0 = disabled)
5318  * @max_bw: Max BW limit credits
5319  * @cmd_details: pointer to command details structure or NULL
5320  **/
5321 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5322                                 u16 seid, u16 credit, u8 max_bw,
5323                                 struct i40e_asq_cmd_details *cmd_details)
5324 {
5325         struct i40e_aq_desc desc;
5326         struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5327           (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5328         enum i40e_status_code status;
5329
5330         i40e_fill_default_direct_cmd_desc(&desc,
5331                                 i40e_aqc_opc_configure_switching_comp_bw_limit);
5332
5333         cmd->seid = CPU_TO_LE16(seid);
5334         cmd->credit = CPU_TO_LE16(credit);
5335         cmd->max_bw = max_bw;
5336
5337         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5338
5339         return status;
5340 }
5341
5342 /**
5343  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5344  * @hw: pointer to the hw struct
5345  * @seid: VSI seid
5346  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5347  * @cmd_details: pointer to command details structure or NULL
5348  **/
5349 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5350                         u16 seid,
5351                         struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5352                         struct i40e_asq_cmd_details *cmd_details)
5353 {
5354         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5355                                     i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5356                                     cmd_details);
5357 }
5358
5359 /**
5360  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5361  * @hw: pointer to the hw struct
5362  * @seid: VSI seid
5363  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5364  * @cmd_details: pointer to command details structure or NULL
5365  **/
5366 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5367                         u16 seid,
5368                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5369                         struct i40e_asq_cmd_details *cmd_details)
5370 {
5371         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5372                                     i40e_aqc_opc_configure_vsi_tc_bw,
5373                                     cmd_details);
5374 }
5375
5376 /**
5377  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5378  * @hw: pointer to the hw struct
5379  * @seid: seid of the switching component connected to Physical Port
5380  * @ets_data: Buffer holding ETS parameters
5381  * @opcode: Tx scheduler AQ command opcode
5382  * @cmd_details: pointer to command details structure or NULL
5383  **/
5384 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5385                 u16 seid,
5386                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5387                 enum i40e_admin_queue_opc opcode,
5388                 struct i40e_asq_cmd_details *cmd_details)
5389 {
5390         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5391                                     sizeof(*ets_data), opcode, cmd_details);
5392 }
5393
5394 /**
5395  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5396  * @hw: pointer to the hw struct
5397  * @seid: seid of the switching component
5398  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5399  * @cmd_details: pointer to command details structure or NULL
5400  **/
5401 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5402         u16 seid,
5403         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5404         struct i40e_asq_cmd_details *cmd_details)
5405 {
5406         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5407                             i40e_aqc_opc_configure_switching_comp_bw_config,
5408                             cmd_details);
5409 }
5410
5411 /**
5412  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5413  * @hw: pointer to the hw struct
5414  * @seid: seid of the switching component
5415  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5416  * @cmd_details: pointer to command details structure or NULL
5417  **/
5418 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5419         struct i40e_hw *hw, u16 seid,
5420         struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5421         struct i40e_asq_cmd_details *cmd_details)
5422 {
5423         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5424                             i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5425                             cmd_details);
5426 }
5427
5428 /**
5429  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5430  * @hw: pointer to the hw struct
5431  * @seid: seid of the VSI
5432  * @bw_data: Buffer to hold VSI BW configuration
5433  * @cmd_details: pointer to command details structure or NULL
5434  **/
5435 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5436                         u16 seid,
5437                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5438                         struct i40e_asq_cmd_details *cmd_details)
5439 {
5440         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5441                                     i40e_aqc_opc_query_vsi_bw_config,
5442                                     cmd_details);
5443 }
5444
5445 /**
5446  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5447  * @hw: pointer to the hw struct
5448  * @seid: seid of the VSI
5449  * @bw_data: Buffer to hold VSI BW configuration per TC
5450  * @cmd_details: pointer to command details structure or NULL
5451  **/
5452 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5453                         u16 seid,
5454                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5455                         struct i40e_asq_cmd_details *cmd_details)
5456 {
5457         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5458                                     i40e_aqc_opc_query_vsi_ets_sla_config,
5459                                     cmd_details);
5460 }
5461
5462 /**
5463  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5464  * @hw: pointer to the hw struct
5465  * @seid: seid of the switching component
5466  * @bw_data: Buffer to hold switching component's per TC BW config
5467  * @cmd_details: pointer to command details structure or NULL
5468  **/
5469 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5470                 u16 seid,
5471                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5472                 struct i40e_asq_cmd_details *cmd_details)
5473 {
5474         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5475                                    i40e_aqc_opc_query_switching_comp_ets_config,
5476                                    cmd_details);
5477 }
5478
5479 /**
5480  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5481  * @hw: pointer to the hw struct
5482  * @seid: seid of the VSI or switching component connected to Physical Port
5483  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5484  * @cmd_details: pointer to command details structure or NULL
5485  **/
5486 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5487                         u16 seid,
5488                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
5489                         struct i40e_asq_cmd_details *cmd_details)
5490 {
5491         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5492                                     i40e_aqc_opc_query_port_ets_config,
5493                                     cmd_details);
5494 }
5495
5496 /**
5497  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5498  * @hw: pointer to the hw struct
5499  * @seid: seid of the switching component
5500  * @bw_data: Buffer to hold switching component's BW configuration
5501  * @cmd_details: pointer to command details structure or NULL
5502  **/
5503 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5504                 u16 seid,
5505                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5506                 struct i40e_asq_cmd_details *cmd_details)
5507 {
5508         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5509                                     i40e_aqc_opc_query_switching_comp_bw_config,
5510                                     cmd_details);
5511 }
5512
5513 /**
5514  * i40e_validate_filter_settings
5515  * @hw: pointer to the hardware structure
5516  * @settings: Filter control settings
5517  *
5518  * Check and validate the filter control settings passed.
5519  * The function checks for the valid filter/context sizes being
5520  * passed for FCoE and PE.
5521  *
5522  * Returns I40E_SUCCESS if the values passed are valid and within
5523  * range else returns an error.
5524  **/
5525 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5526                                 struct i40e_filter_control_settings *settings)
5527 {
5528         u32 fcoe_cntx_size, fcoe_filt_size;
5529         u32 pe_cntx_size, pe_filt_size;
5530         u32 fcoe_fmax;
5531
5532         u32 val;
5533
5534         /* Validate FCoE settings passed */
5535         switch (settings->fcoe_filt_num) {
5536         case I40E_HASH_FILTER_SIZE_1K:
5537         case I40E_HASH_FILTER_SIZE_2K:
5538         case I40E_HASH_FILTER_SIZE_4K:
5539         case I40E_HASH_FILTER_SIZE_8K:
5540         case I40E_HASH_FILTER_SIZE_16K:
5541         case I40E_HASH_FILTER_SIZE_32K:
5542                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5543                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5544                 break;
5545         default:
5546                 return I40E_ERR_PARAM;
5547         }
5548
5549         switch (settings->fcoe_cntx_num) {
5550         case I40E_DMA_CNTX_SIZE_512:
5551         case I40E_DMA_CNTX_SIZE_1K:
5552         case I40E_DMA_CNTX_SIZE_2K:
5553         case I40E_DMA_CNTX_SIZE_4K:
5554                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5555                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5556                 break;
5557         default:
5558                 return I40E_ERR_PARAM;
5559         }
5560
5561         /* Validate PE settings passed */
5562         switch (settings->pe_filt_num) {
5563         case I40E_HASH_FILTER_SIZE_1K:
5564         case I40E_HASH_FILTER_SIZE_2K:
5565         case I40E_HASH_FILTER_SIZE_4K:
5566         case I40E_HASH_FILTER_SIZE_8K:
5567         case I40E_HASH_FILTER_SIZE_16K:
5568         case I40E_HASH_FILTER_SIZE_32K:
5569         case I40E_HASH_FILTER_SIZE_64K:
5570         case I40E_HASH_FILTER_SIZE_128K:
5571         case I40E_HASH_FILTER_SIZE_256K:
5572         case I40E_HASH_FILTER_SIZE_512K:
5573         case I40E_HASH_FILTER_SIZE_1M:
5574                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5575                 pe_filt_size <<= (u32)settings->pe_filt_num;
5576                 break;
5577         default:
5578                 return I40E_ERR_PARAM;
5579         }
5580
5581         switch (settings->pe_cntx_num) {
5582         case I40E_DMA_CNTX_SIZE_512:
5583         case I40E_DMA_CNTX_SIZE_1K:
5584         case I40E_DMA_CNTX_SIZE_2K:
5585         case I40E_DMA_CNTX_SIZE_4K:
5586         case I40E_DMA_CNTX_SIZE_8K:
5587         case I40E_DMA_CNTX_SIZE_16K:
5588         case I40E_DMA_CNTX_SIZE_32K:
5589         case I40E_DMA_CNTX_SIZE_64K:
5590         case I40E_DMA_CNTX_SIZE_128K:
5591         case I40E_DMA_CNTX_SIZE_256K:
5592                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5593                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5594                 break;
5595         default:
5596                 return I40E_ERR_PARAM;
5597         }
5598
5599         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5600         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5601         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5602                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5603         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
5604                 return I40E_ERR_INVALID_SIZE;
5605
5606         return I40E_SUCCESS;
5607 }
5608
5609 /**
5610  * i40e_set_filter_control
5611  * @hw: pointer to the hardware structure
5612  * @settings: Filter control settings
5613  *
5614  * Set the Queue Filters for PE/FCoE and enable filters required
5615  * for a single PF. It is expected that these settings are programmed
5616  * at the driver initialization time.
5617  **/
5618 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5619                                 struct i40e_filter_control_settings *settings)
5620 {
5621         enum i40e_status_code ret = I40E_SUCCESS;
5622         u32 hash_lut_size = 0;
5623         u32 val;
5624
5625         if (!settings)
5626                 return I40E_ERR_PARAM;
5627
5628         /* Validate the input settings */
5629         ret = i40e_validate_filter_settings(hw, settings);
5630         if (ret)
5631                 return ret;
5632
5633         /* Read the PF Queue Filter control register */
5634         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5635
5636         /* Program required PE hash buckets for the PF */
5637         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5638         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5639                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5640         /* Program required PE contexts for the PF */
5641         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5642         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5643                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5644
5645         /* Program required FCoE hash buckets for the PF */
5646         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5647         val |= ((u32)settings->fcoe_filt_num <<
5648                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5649                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5650         /* Program required FCoE DDP contexts for the PF */
5651         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5652         val |= ((u32)settings->fcoe_cntx_num <<
5653                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5654                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5655
5656         /* Program Hash LUT size for the PF */
5657         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5658         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5659                 hash_lut_size = 1;
5660         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5661                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5662
5663         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5664         if (settings->enable_fdir)
5665                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5666         if (settings->enable_ethtype)
5667                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5668         if (settings->enable_macvlan)
5669                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5670
5671         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5672
5673         return I40E_SUCCESS;
5674 }
5675
5676 /**
5677  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5678  * @hw: pointer to the hw struct
5679  * @mac_addr: MAC address to use in the filter
5680  * @ethtype: Ethertype to use in the filter
5681  * @flags: Flags that needs to be applied to the filter
5682  * @vsi_seid: seid of the control VSI
5683  * @queue: VSI queue number to send the packet to
5684  * @is_add: Add control packet filter if True else remove
5685  * @stats: Structure to hold information on control filter counts
5686  * @cmd_details: pointer to command details structure or NULL
5687  *
5688  * This command will Add or Remove control packet filter for a control VSI.
5689  * In return it will update the total number of perfect filter count in
5690  * the stats member.
5691  **/
5692 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5693                                 u8 *mac_addr, u16 ethtype, u16 flags,
5694                                 u16 vsi_seid, u16 queue, bool is_add,
5695                                 struct i40e_control_filter_stats *stats,
5696                                 struct i40e_asq_cmd_details *cmd_details)
5697 {
5698         struct i40e_aq_desc desc;
5699         struct i40e_aqc_add_remove_control_packet_filter *cmd =
5700                 (struct i40e_aqc_add_remove_control_packet_filter *)
5701                 &desc.params.raw;
5702         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5703                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5704                 &desc.params.raw;
5705         enum i40e_status_code status;
5706
5707         if (vsi_seid == 0)
5708                 return I40E_ERR_PARAM;
5709
5710         if (is_add) {
5711                 i40e_fill_default_direct_cmd_desc(&desc,
5712                                 i40e_aqc_opc_add_control_packet_filter);
5713                 cmd->queue = CPU_TO_LE16(queue);
5714         } else {
5715                 i40e_fill_default_direct_cmd_desc(&desc,
5716                                 i40e_aqc_opc_remove_control_packet_filter);
5717         }
5718
5719         if (mac_addr)
5720                 i40e_memcpy(cmd->mac, mac_addr, ETH_ALEN,
5721                             I40E_NONDMA_TO_NONDMA);
5722
5723         cmd->etype = CPU_TO_LE16(ethtype);
5724         cmd->flags = CPU_TO_LE16(flags);
5725         cmd->seid = CPU_TO_LE16(vsi_seid);
5726
5727         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5728
5729         if (!status && stats) {
5730                 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5731                 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5732                 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5733                 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5734         }
5735
5736         return status;
5737 }
5738
5739 /**
5740  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5741  * @hw: pointer to the hw struct
5742  * @seid: VSI seid to add ethertype filter from
5743  **/
5744 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5745                                                     u16 seid)
5746 {
5747 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5748         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5749                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5750                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5751         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5752         enum i40e_status_code status;
5753
5754         status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5755                                                        seid, 0, true, NULL,
5756                                                        NULL);
5757         if (status)
5758                 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5759 }
5760
5761 /**
5762  * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5763  * @filters: list of cloud filters
5764  * @filter_count: length of list
5765  *
5766  * There's an issue in the device where the Geneve VNI layout needs
5767  * to be shifted 1 byte over from the VxLAN VNI
5768  **/
5769 STATIC void i40e_fix_up_geneve_vni(
5770         struct i40e_aqc_cloud_filters_element_data *filters,
5771         u8 filter_count)
5772 {
5773         struct i40e_aqc_cloud_filters_element_data *f = filters;
5774         int i;
5775
5776         for (i = 0; i < filter_count; i++) {
5777                 u16 tnl_type;
5778                 u32 ti;
5779
5780                 tnl_type = (LE16_TO_CPU(f[i].flags) &
5781                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5782                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5783                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5784                         ti = LE32_TO_CPU(f[i].tenant_id);
5785                         f[i].tenant_id = CPU_TO_LE32(ti << 8);
5786                 }
5787         }
5788 }
5789
5790 /**
5791  * i40e_aq_add_cloud_filters
5792  * @hw: pointer to the hardware structure
5793  * @seid: VSI seid to add cloud filters from
5794  * @filters: Buffer which contains the filters to be added
5795  * @filter_count: number of filters contained in the buffer
5796  *
5797  * Set the cloud filters for a given VSI.  The contents of the
5798  * i40e_aqc_cloud_filters_element_data are filled
5799  * in by the caller of the function.
5800  *
5801  **/
5802 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5803         u16 seid,
5804         struct i40e_aqc_cloud_filters_element_data *filters,
5805         u8 filter_count)
5806 {
5807         struct i40e_aq_desc desc;
5808         struct i40e_aqc_add_remove_cloud_filters *cmd =
5809         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5810         enum i40e_status_code status;
5811         u16 buff_len;
5812
5813         i40e_fill_default_direct_cmd_desc(&desc,
5814                                           i40e_aqc_opc_add_cloud_filters);
5815
5816         buff_len = filter_count * sizeof(*filters);
5817         desc.datalen = CPU_TO_LE16(buff_len);
5818         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5819         cmd->num_filters = filter_count;
5820         cmd->seid = CPU_TO_LE16(seid);
5821
5822         i40e_fix_up_geneve_vni(filters, filter_count);
5823
5824         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5825
5826         return status;
5827 }
5828
5829 /**
5830  * i40e_aq_add_cloud_filters_bb
5831  * @hw: pointer to the hardware structure
5832  * @seid: VSI seid to add cloud filters from
5833  * @filters: Buffer which contains the filters in big buffer to be added
5834  * @filter_count: number of filters contained in the buffer
5835  *
5836  * Set the cloud filters for a given VSI.  The contents of the
5837  * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5838  * the function.
5839  *
5840  **/
5841 enum i40e_status_code
5842 i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5843                              struct i40e_aqc_cloud_filters_element_bb *filters,
5844                              u8 filter_count)
5845 {
5846         struct i40e_aq_desc desc;
5847         struct i40e_aqc_add_remove_cloud_filters *cmd =
5848         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5849         enum i40e_status_code status;
5850         u16 buff_len;
5851         int i;
5852
5853         i40e_fill_default_direct_cmd_desc(&desc,
5854                                           i40e_aqc_opc_add_cloud_filters);
5855
5856         buff_len = filter_count * sizeof(*filters);
5857         desc.datalen = CPU_TO_LE16(buff_len);
5858         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5859         cmd->num_filters = filter_count;
5860         cmd->seid = CPU_TO_LE16(seid);
5861         cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5862
5863         for (i = 0; i < filter_count; i++) {
5864                 u16 tnl_type;
5865                 u32 ti;
5866
5867                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5868                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5869                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5870
5871                 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5872                  * one more byte further than normally used for Tenant ID in
5873                  * other tunnel types.
5874                  */
5875                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5876                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5877                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5878                 }
5879         }
5880
5881         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5882
5883         return status;
5884 }
5885
5886 /**
5887  * i40e_aq_rem_cloud_filters
5888  * @hw: pointer to the hardware structure
5889  * @seid: VSI seid to remove cloud filters from
5890  * @filters: Buffer which contains the filters to be removed
5891  * @filter_count: number of filters contained in the buffer
5892  *
5893  * Remove the cloud filters for a given VSI.  The contents of the
5894  * i40e_aqc_cloud_filters_element_data are filled in by the caller
5895  * of the function.
5896  *
5897  **/
5898 enum i40e_status_code
5899 i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid,
5900                           struct i40e_aqc_cloud_filters_element_data *filters,
5901                           u8 filter_count)
5902 {
5903         struct i40e_aq_desc desc;
5904         struct i40e_aqc_add_remove_cloud_filters *cmd =
5905         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5906         enum i40e_status_code status;
5907         u16 buff_len;
5908
5909         i40e_fill_default_direct_cmd_desc(&desc,
5910                                           i40e_aqc_opc_remove_cloud_filters);
5911
5912         buff_len = filter_count * sizeof(*filters);
5913         desc.datalen = CPU_TO_LE16(buff_len);
5914         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5915         cmd->num_filters = filter_count;
5916         cmd->seid = CPU_TO_LE16(seid);
5917
5918         i40e_fix_up_geneve_vni(filters, filter_count);
5919
5920         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5921
5922         return status;
5923 }
5924
5925 /**
5926  * i40e_aq_rem_cloud_filters_bb
5927  * @hw: pointer to the hardware structure
5928  * @seid: VSI seid to remove cloud filters from
5929  * @filters: Buffer which contains the filters in big buffer to be removed
5930  * @filter_count: number of filters contained in the buffer
5931  *
5932  * Remove the big buffer cloud filters for a given VSI.  The contents of the
5933  * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5934  * function.
5935  *
5936  **/
5937 enum i40e_status_code
5938 i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5939                              struct i40e_aqc_cloud_filters_element_bb *filters,
5940                              u8 filter_count)
5941 {
5942         struct i40e_aq_desc desc;
5943         struct i40e_aqc_add_remove_cloud_filters *cmd =
5944         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5945         enum i40e_status_code status;
5946         u16 buff_len;
5947         int i;
5948
5949         i40e_fill_default_direct_cmd_desc(&desc,
5950                                           i40e_aqc_opc_remove_cloud_filters);
5951
5952         buff_len = filter_count * sizeof(*filters);
5953         desc.datalen = CPU_TO_LE16(buff_len);
5954         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5955         cmd->num_filters = filter_count;
5956         cmd->seid = CPU_TO_LE16(seid);
5957         cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5958
5959         for (i = 0; i < filter_count; i++) {
5960                 u16 tnl_type;
5961                 u32 ti;
5962
5963                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5964                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5965                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5966
5967                 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5968                  * one more byte further than normally used for Tenant ID in
5969                  * other tunnel types.
5970                  */
5971                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5972                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5973                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5974                 }
5975         }
5976
5977         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5978
5979         return status;
5980 }
5981
5982 /**
5983  * i40e_aq_replace_cloud_filters - Replace cloud filter command
5984  * @hw: pointer to the hw struct
5985  * @filters: pointer to the i40e_aqc_replace_cloud_filter_cmd struct
5986  * @cmd_buf: pointer to the i40e_aqc_replace_cloud_filter_cmd_buf struct
5987  *
5988  **/
5989 enum
5990 i40e_status_code i40e_aq_replace_cloud_filters(struct i40e_hw *hw,
5991         struct i40e_aqc_replace_cloud_filters_cmd *filters,
5992         struct i40e_aqc_replace_cloud_filters_cmd_buf *cmd_buf)
5993 {
5994         struct i40e_aq_desc desc;
5995         struct i40e_aqc_replace_cloud_filters_cmd *cmd =
5996                 (struct i40e_aqc_replace_cloud_filters_cmd *)&desc.params.raw;
5997         enum i40e_status_code status = I40E_SUCCESS;
5998         int i = 0;
5999
6000         /* X722 doesn't support this command */
6001         if (hw->mac.type == I40E_MAC_X722)
6002                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
6003
6004         /* need FW version greater than 6.00 */
6005         if (hw->aq.fw_maj_ver < 6)
6006                 return I40E_NOT_SUPPORTED;
6007
6008         i40e_fill_default_direct_cmd_desc(&desc,
6009                                           i40e_aqc_opc_replace_cloud_filters);
6010
6011         desc.datalen = CPU_TO_LE16(32);
6012         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
6013         cmd->old_filter_type = filters->old_filter_type;
6014         cmd->new_filter_type = filters->new_filter_type;
6015         cmd->valid_flags = filters->valid_flags;
6016         cmd->tr_bit = filters->tr_bit;
6017         cmd->tr_bit2 = filters->tr_bit2;
6018
6019         status = i40e_asq_send_command(hw, &desc, cmd_buf,
6020                 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf),  NULL);
6021
6022         /* for get cloud filters command */
6023         for (i = 0; i < 32; i += 4) {
6024                 cmd_buf->filters[i / 4].filter_type = cmd_buf->data[i];
6025                 cmd_buf->filters[i / 4].input[0] = cmd_buf->data[i + 1];
6026                 cmd_buf->filters[i / 4].input[1] = cmd_buf->data[i + 2];
6027                 cmd_buf->filters[i / 4].input[2] = cmd_buf->data[i + 3];
6028         }
6029
6030         return status;
6031 }
6032
6033
6034 /**
6035  * i40e_aq_alternate_write
6036  * @hw: pointer to the hardware structure
6037  * @reg_addr0: address of first dword to be read
6038  * @reg_val0: value to be written under 'reg_addr0'
6039  * @reg_addr1: address of second dword to be read
6040  * @reg_val1: value to be written under 'reg_addr1'
6041  *
6042  * Write one or two dwords to alternate structure. Fields are indicated
6043  * by 'reg_addr0' and 'reg_addr1' register numbers.
6044  *
6045  **/
6046 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
6047                                 u32 reg_addr0, u32 reg_val0,
6048                                 u32 reg_addr1, u32 reg_val1)
6049 {
6050         struct i40e_aq_desc desc;
6051         struct i40e_aqc_alternate_write *cmd_resp =
6052                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
6053         enum i40e_status_code status;
6054
6055         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
6056         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
6057         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
6058         cmd_resp->data0 = CPU_TO_LE32(reg_val0);
6059         cmd_resp->data1 = CPU_TO_LE32(reg_val1);
6060
6061         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6062
6063         return status;
6064 }
6065
6066 /**
6067  * i40e_aq_alternate_write_indirect
6068  * @hw: pointer to the hardware structure
6069  * @addr: address of a first register to be modified
6070  * @dw_count: number of alternate structure fields to write
6071  * @buffer: pointer to the command buffer
6072  *
6073  * Write 'dw_count' dwords from 'buffer' to alternate structure
6074  * starting at 'addr'.
6075  *
6076  **/
6077 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
6078                                 u32 addr, u32 dw_count, void *buffer)
6079 {
6080         struct i40e_aq_desc desc;
6081         struct i40e_aqc_alternate_ind_write *cmd_resp =
6082                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
6083         enum i40e_status_code status;
6084
6085         if (buffer == NULL)
6086                 return I40E_ERR_PARAM;
6087
6088         /* Indirect command */
6089         i40e_fill_default_direct_cmd_desc(&desc,
6090                                          i40e_aqc_opc_alternate_write_indirect);
6091
6092         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6093         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6094         if (dw_count > (I40E_AQ_LARGE_BUF/4))
6095                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6096
6097         cmd_resp->address = CPU_TO_LE32(addr);
6098         cmd_resp->length = CPU_TO_LE32(dw_count);
6099
6100         status = i40e_asq_send_command(hw, &desc, buffer,
6101                                        I40E_LO_DWORD(4*dw_count), NULL);
6102
6103         return status;
6104 }
6105
6106 /**
6107  * i40e_aq_alternate_read
6108  * @hw: pointer to the hardware structure
6109  * @reg_addr0: address of first dword to be read
6110  * @reg_val0: pointer for data read from 'reg_addr0'
6111  * @reg_addr1: address of second dword to be read
6112  * @reg_val1: pointer for data read from 'reg_addr1'
6113  *
6114  * Read one or two dwords from alternate structure. Fields are indicated
6115  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
6116  * is not passed then only register at 'reg_addr0' is read.
6117  *
6118  **/
6119 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
6120                                 u32 reg_addr0, u32 *reg_val0,
6121                                 u32 reg_addr1, u32 *reg_val1)
6122 {
6123         struct i40e_aq_desc desc;
6124         struct i40e_aqc_alternate_write *cmd_resp =
6125                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
6126         enum i40e_status_code status;
6127
6128         if (reg_val0 == NULL)
6129                 return I40E_ERR_PARAM;
6130
6131         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
6132         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
6133         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
6134
6135         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6136
6137         if (status == I40E_SUCCESS) {
6138                 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
6139
6140                 if (reg_val1 != NULL)
6141                         *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
6142         }
6143
6144         return status;
6145 }
6146
6147 /**
6148  * i40e_aq_alternate_read_indirect
6149  * @hw: pointer to the hardware structure
6150  * @addr: address of the alternate structure field
6151  * @dw_count: number of alternate structure fields to read
6152  * @buffer: pointer to the command buffer
6153  *
6154  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
6155  * place them in 'buffer'. The buffer should be allocated by caller.
6156  *
6157  **/
6158 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
6159                                 u32 addr, u32 dw_count, void *buffer)
6160 {
6161         struct i40e_aq_desc desc;
6162         struct i40e_aqc_alternate_ind_write *cmd_resp =
6163                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
6164         enum i40e_status_code status;
6165
6166         if (buffer == NULL)
6167                 return I40E_ERR_PARAM;
6168
6169         /* Indirect command */
6170         i40e_fill_default_direct_cmd_desc(&desc,
6171                 i40e_aqc_opc_alternate_read_indirect);
6172
6173         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6174         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6175         if (dw_count > (I40E_AQ_LARGE_BUF/4))
6176                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6177
6178         cmd_resp->address = CPU_TO_LE32(addr);
6179         cmd_resp->length = CPU_TO_LE32(dw_count);
6180
6181         status = i40e_asq_send_command(hw, &desc, buffer,
6182                                        I40E_LO_DWORD(4*dw_count), NULL);
6183
6184         return status;
6185 }
6186
6187 /**
6188  *  i40e_aq_alternate_clear
6189  *  @hw: pointer to the HW structure.
6190  *
6191  *  Clear the alternate structures of the port from which the function
6192  *  is called.
6193  *
6194  **/
6195 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
6196 {
6197         struct i40e_aq_desc desc;
6198         enum i40e_status_code status;
6199
6200         i40e_fill_default_direct_cmd_desc(&desc,
6201                                           i40e_aqc_opc_alternate_clear_port);
6202
6203         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6204
6205         return status;
6206 }
6207
6208 /**
6209  *  i40e_aq_alternate_write_done
6210  *  @hw: pointer to the HW structure.
6211  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
6212  *  @reset_needed: indicates the SW should trigger GLOBAL reset
6213  *
6214  *  Indicates to the FW that alternate structures have been changed.
6215  *
6216  **/
6217 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
6218                 u8 bios_mode, bool *reset_needed)
6219 {
6220         struct i40e_aq_desc desc;
6221         struct i40e_aqc_alternate_write_done *cmd =
6222                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6223         enum i40e_status_code status;
6224
6225         if (reset_needed == NULL)
6226                 return I40E_ERR_PARAM;
6227
6228         i40e_fill_default_direct_cmd_desc(&desc,
6229                                           i40e_aqc_opc_alternate_write_done);
6230
6231         cmd->cmd_flags = CPU_TO_LE16(bios_mode);
6232
6233         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6234         if (!status && reset_needed)
6235                 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
6236                                  I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
6237
6238         return status;
6239 }
6240
6241 /**
6242  *  i40e_aq_set_oem_mode
6243  *  @hw: pointer to the HW structure.
6244  *  @oem_mode: the OEM mode to be used
6245  *
6246  *  Sets the device to a specific operating mode. Currently the only supported
6247  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
6248  *
6249  **/
6250 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
6251                 u8 oem_mode)
6252 {
6253         struct i40e_aq_desc desc;
6254         struct i40e_aqc_alternate_write_done *cmd =
6255                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6256         enum i40e_status_code status;
6257
6258         i40e_fill_default_direct_cmd_desc(&desc,
6259                                           i40e_aqc_opc_alternate_set_mode);
6260
6261         cmd->cmd_flags = CPU_TO_LE16(oem_mode);
6262
6263         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6264
6265         return status;
6266 }
6267
6268 /**
6269  * i40e_aq_resume_port_tx
6270  * @hw: pointer to the hardware structure
6271  * @cmd_details: pointer to command details structure or NULL
6272  *
6273  * Resume port's Tx traffic
6274  **/
6275 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
6276                                 struct i40e_asq_cmd_details *cmd_details)
6277 {
6278         struct i40e_aq_desc desc;
6279         enum i40e_status_code status;
6280
6281         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
6282
6283         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6284
6285         return status;
6286 }
6287
6288 /**
6289  * i40e_set_pci_config_data - store PCI bus info
6290  * @hw: pointer to hardware structure
6291  * @link_status: the link status word from PCI config space
6292  *
6293  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
6294  **/
6295 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
6296 {
6297         hw->bus.type = i40e_bus_type_pci_express;
6298
6299         switch (link_status & I40E_PCI_LINK_WIDTH) {
6300         case I40E_PCI_LINK_WIDTH_1:
6301                 hw->bus.width = i40e_bus_width_pcie_x1;
6302                 break;
6303         case I40E_PCI_LINK_WIDTH_2:
6304                 hw->bus.width = i40e_bus_width_pcie_x2;
6305                 break;
6306         case I40E_PCI_LINK_WIDTH_4:
6307                 hw->bus.width = i40e_bus_width_pcie_x4;
6308                 break;
6309         case I40E_PCI_LINK_WIDTH_8:
6310                 hw->bus.width = i40e_bus_width_pcie_x8;
6311                 break;
6312         default:
6313                 hw->bus.width = i40e_bus_width_unknown;
6314                 break;
6315         }
6316
6317         switch (link_status & I40E_PCI_LINK_SPEED) {
6318         case I40E_PCI_LINK_SPEED_2500:
6319                 hw->bus.speed = i40e_bus_speed_2500;
6320                 break;
6321         case I40E_PCI_LINK_SPEED_5000:
6322                 hw->bus.speed = i40e_bus_speed_5000;
6323                 break;
6324         case I40E_PCI_LINK_SPEED_8000:
6325                 hw->bus.speed = i40e_bus_speed_8000;
6326                 break;
6327         default:
6328                 hw->bus.speed = i40e_bus_speed_unknown;
6329                 break;
6330         }
6331 }
6332
6333 /**
6334  * i40e_aq_debug_dump
6335  * @hw: pointer to the hardware structure
6336  * @cluster_id: specific cluster to dump
6337  * @table_id: table id within cluster
6338  * @start_index: index of line in the block to read
6339  * @buff_size: dump buffer size
6340  * @buff: dump buffer
6341  * @ret_buff_size: actual buffer size returned
6342  * @ret_next_table: next block to read
6343  * @ret_next_index: next index to read
6344  * @cmd_details: pointer to command details structure or NULL
6345  *
6346  * Dump internal FW/HW data for debug purposes.
6347  *
6348  **/
6349 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
6350                                 u8 table_id, u32 start_index, u16 buff_size,
6351                                 void *buff, u16 *ret_buff_size,
6352                                 u8 *ret_next_table, u32 *ret_next_index,
6353                                 struct i40e_asq_cmd_details *cmd_details)
6354 {
6355         struct i40e_aq_desc desc;
6356         struct i40e_aqc_debug_dump_internals *cmd =
6357                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6358         struct i40e_aqc_debug_dump_internals *resp =
6359                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6360         enum i40e_status_code status;
6361
6362         if (buff_size == 0 || !buff)
6363                 return I40E_ERR_PARAM;
6364
6365         i40e_fill_default_direct_cmd_desc(&desc,
6366                                           i40e_aqc_opc_debug_dump_internals);
6367         /* Indirect Command */
6368         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6369         if (buff_size > I40E_AQ_LARGE_BUF)
6370                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6371
6372         cmd->cluster_id = cluster_id;
6373         cmd->table_id = table_id;
6374         cmd->idx = CPU_TO_LE32(start_index);
6375
6376         desc.datalen = CPU_TO_LE16(buff_size);
6377
6378         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
6379         if (!status) {
6380                 if (ret_buff_size != NULL)
6381                         *ret_buff_size = LE16_TO_CPU(desc.datalen);
6382                 if (ret_next_table != NULL)
6383                         *ret_next_table = resp->table_id;
6384                 if (ret_next_index != NULL)
6385                         *ret_next_index = LE32_TO_CPU(resp->idx);
6386         }
6387
6388         return status;
6389 }
6390
6391
6392 /**
6393  * i40e_enable_eee
6394  * @hw: pointer to the hardware structure
6395  * @enable: state of Energy Efficient Ethernet mode to be set
6396  *
6397  * Enables or disables Energy Efficient Ethernet (EEE) mode
6398  * accordingly to @enable parameter.
6399  **/
6400 enum i40e_status_code i40e_enable_eee(struct i40e_hw *hw, bool enable)
6401 {
6402         struct i40e_aq_get_phy_abilities_resp abilities;
6403         struct i40e_aq_set_phy_config config;
6404         enum i40e_status_code status;
6405         __le16 eee_capability;
6406
6407         /* Get initial PHY capabilities */
6408         status = i40e_aq_get_phy_capabilities(hw, false, true, &abilities,
6409                                               NULL);
6410         if (status)
6411                 goto err;
6412
6413         /* Check whether NIC configuration is compatible with Energy Efficient
6414          * Ethernet (EEE) mode.
6415          */
6416         if (abilities.eee_capability == 0) {
6417                 status = I40E_ERR_CONFIG;
6418                 goto err;
6419         }
6420
6421         /* Cache initial EEE capability */
6422         eee_capability = abilities.eee_capability;
6423
6424         /* Get current configuration */
6425         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
6426                                               NULL);
6427         if (status)
6428                 goto err;
6429
6430         /* Cache current configuration */
6431         config.phy_type = abilities.phy_type;
6432         config.link_speed = abilities.link_speed;
6433         config.abilities = abilities.abilities |
6434                            I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
6435         config.eeer = abilities.eeer_val;
6436         config.low_power_ctrl = abilities.d3_lpan;
6437         config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
6438                             I40E_AQ_PHY_FEC_CONFIG_MASK;
6439
6440         /* Set desired EEE state */
6441         if (enable) {
6442                 config.eee_capability = eee_capability;
6443                 config.eeer |= I40E_PRTPM_EEER_TX_LPI_EN_MASK;
6444         } else {
6445                 config.eee_capability = 0;
6446                 config.eeer &= ~I40E_PRTPM_EEER_TX_LPI_EN_MASK;
6447         }
6448
6449         /* Save modified config */
6450         status = i40e_aq_set_phy_config(hw, &config, NULL);
6451 err:
6452         return status;
6453 }
6454
6455 /**
6456  * i40e_read_bw_from_alt_ram
6457  * @hw: pointer to the hardware structure
6458  * @max_bw: pointer for max_bw read
6459  * @min_bw: pointer for min_bw read
6460  * @min_valid: pointer for bool that is true if min_bw is a valid value
6461  * @max_valid: pointer for bool that is true if max_bw is a valid value
6462  *
6463  * Read bw from the alternate ram for the given pf
6464  **/
6465 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
6466                                         u32 *max_bw, u32 *min_bw,
6467                                         bool *min_valid, bool *max_valid)
6468 {
6469         enum i40e_status_code status;
6470         u32 max_bw_addr, min_bw_addr;
6471
6472         /* Calculate the address of the min/max bw registers */
6473         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6474                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
6475                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6476         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6477                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
6478                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6479
6480         /* Read the bandwidths from alt ram */
6481         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
6482                                         min_bw_addr, min_bw);
6483
6484         if (*min_bw & I40E_ALT_BW_VALID_MASK)
6485                 *min_valid = true;
6486         else
6487                 *min_valid = false;
6488
6489         if (*max_bw & I40E_ALT_BW_VALID_MASK)
6490                 *max_valid = true;
6491         else
6492                 *max_valid = false;
6493
6494         return status;
6495 }
6496
6497 /**
6498  * i40e_aq_configure_partition_bw
6499  * @hw: pointer to the hardware structure
6500  * @bw_data: Buffer holding valid pfs and bw limits
6501  * @cmd_details: pointer to command details
6502  *
6503  * Configure partitions guaranteed/max bw
6504  **/
6505 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6506                         struct i40e_aqc_configure_partition_bw_data *bw_data,
6507                         struct i40e_asq_cmd_details *cmd_details)
6508 {
6509         enum i40e_status_code status;
6510         struct i40e_aq_desc desc;
6511         u16 bwd_size = sizeof(*bw_data);
6512
6513         i40e_fill_default_direct_cmd_desc(&desc,
6514                                 i40e_aqc_opc_configure_partition_bw);
6515
6516         /* Indirect command */
6517         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6518         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6519
6520         desc.datalen = CPU_TO_LE16(bwd_size);
6521
6522         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6523
6524         return status;
6525 }
6526
6527 /**
6528  * i40e_read_phy_register_clause22
6529  * @hw: pointer to the HW structure
6530  * @reg: register address in the page
6531  * @phy_addr: PHY address on MDIO interface
6532  * @value: PHY register value
6533  *
6534  * Reads specified PHY register value
6535  **/
6536 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
6537                                         u16 reg, u8 phy_addr, u16 *value)
6538 {
6539         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6540         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6541         u32 command = 0;
6542         u16 retry = 1000;
6543
6544         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6545                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6546                   (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
6547                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6548                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6549         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6550         do {
6551                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6552                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6553                         status = I40E_SUCCESS;
6554                         break;
6555                 }
6556                 i40e_usec_delay(10);
6557                 retry--;
6558         } while (retry);
6559
6560         if (status) {
6561                 i40e_debug(hw, I40E_DEBUG_PHY,
6562                            "PHY: Can't write command to external PHY.\n");
6563         } else {
6564                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6565                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6566                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6567         }
6568
6569         return status;
6570 }
6571
6572 /**
6573  * i40e_write_phy_register_clause22
6574  * @hw: pointer to the HW structure
6575  * @reg: register address in the page
6576  * @phy_addr: PHY address on MDIO interface
6577  * @value: PHY register value
6578  *
6579  * Writes specified PHY register value
6580  **/
6581 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6582                                         u16 reg, u8 phy_addr, u16 value)
6583 {
6584         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6585         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6586         u32 command  = 0;
6587         u16 retry = 1000;
6588
6589         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6590         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6591
6592         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6593                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6594                   (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6595                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6596                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6597
6598         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6599         do {
6600                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6601                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6602                         status = I40E_SUCCESS;
6603                         break;
6604                 }
6605                 i40e_usec_delay(10);
6606                 retry--;
6607         } while (retry);
6608
6609         return status;
6610 }
6611
6612 /**
6613  * i40e_read_phy_register_clause45
6614  * @hw: pointer to the HW structure
6615  * @page: registers page number
6616  * @reg: register address in the page
6617  * @phy_addr: PHY address on MDIO interface
6618  * @value: PHY register value
6619  *
6620  * Reads specified PHY register value
6621  **/
6622 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6623                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6624 {
6625         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6626         u32 command  = 0;
6627         u16 retry = 1000;
6628         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6629
6630         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6631                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6632                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6633                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6634                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6635                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6636                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6637         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6638         do {
6639                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6640                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6641                         status = I40E_SUCCESS;
6642                         break;
6643                 }
6644                 i40e_usec_delay(10);
6645                 retry--;
6646         } while (retry);
6647
6648         if (status) {
6649                 i40e_debug(hw, I40E_DEBUG_PHY,
6650                            "PHY: Can't write command to external PHY.\n");
6651                 goto phy_read_end;
6652         }
6653
6654         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6655                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6656                   (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6657                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6658                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6659                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6660         status = I40E_ERR_TIMEOUT;
6661         retry = 1000;
6662         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6663         do {
6664                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6665                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6666                         status = I40E_SUCCESS;
6667                         break;
6668                 }
6669                 i40e_usec_delay(10);
6670                 retry--;
6671         } while (retry);
6672
6673         if (!status) {
6674                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6675                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6676                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6677         } else {
6678                 i40e_debug(hw, I40E_DEBUG_PHY,
6679                            "PHY: Can't read register value from external PHY.\n");
6680         }
6681
6682 phy_read_end:
6683         return status;
6684 }
6685
6686 /**
6687  * i40e_write_phy_register_clause45
6688  * @hw: pointer to the HW structure
6689  * @page: registers page number
6690  * @reg: register address in the page
6691  * @phy_addr: PHY address on MDIO interface
6692  * @value: PHY register value
6693  *
6694  * Writes value to specified PHY register
6695  **/
6696 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6697                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6698 {
6699         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6700         u32 command  = 0;
6701         u16 retry = 1000;
6702         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6703
6704         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6705                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6706                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6707                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6708                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6709                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6710                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6711         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6712         do {
6713                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6714                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6715                         status = I40E_SUCCESS;
6716                         break;
6717                 }
6718                 i40e_usec_delay(10);
6719                 retry--;
6720         } while (retry);
6721         if (status) {
6722                 i40e_debug(hw, I40E_DEBUG_PHY,
6723                            "PHY: Can't write command to external PHY.\n");
6724                 goto phy_write_end;
6725         }
6726
6727         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6728         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6729
6730         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6731                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6732                   (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6733                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6734                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6735                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6736         status = I40E_ERR_TIMEOUT;
6737         retry = 1000;
6738         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6739         do {
6740                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6741                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6742                         status = I40E_SUCCESS;
6743                         break;
6744                 }
6745                 i40e_usec_delay(10);
6746                 retry--;
6747         } while (retry);
6748
6749 phy_write_end:
6750         return status;
6751 }
6752
6753 /**
6754  * i40e_write_phy_register
6755  * @hw: pointer to the HW structure
6756  * @page: registers page number
6757  * @reg: register address in the page
6758  * @phy_addr: PHY address on MDIO interface
6759  * @value: PHY register value
6760  *
6761  * Writes value to specified PHY register
6762  **/
6763 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6764                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6765 {
6766         enum i40e_status_code status;
6767
6768         switch (hw->device_id) {
6769         case I40E_DEV_ID_1G_BASE_T_X722:
6770                 status = i40e_write_phy_register_clause22(hw,
6771                         reg, phy_addr, value);
6772                 break;
6773         case I40E_DEV_ID_10G_BASE_T:
6774         case I40E_DEV_ID_10G_BASE_T4:
6775         case I40E_DEV_ID_10G_BASE_T_BC:
6776         case I40E_DEV_ID_5G_BASE_T_BC:
6777         case I40E_DEV_ID_10G_BASE_T_X722:
6778         case I40E_DEV_ID_25G_B:
6779         case I40E_DEV_ID_25G_SFP28:
6780                 status = i40e_write_phy_register_clause45(hw,
6781                         page, reg, phy_addr, value);
6782                 break;
6783         default:
6784                 status = I40E_ERR_UNKNOWN_PHY;
6785                 break;
6786         }
6787
6788         return status;
6789 }
6790
6791 /**
6792  * i40e_read_phy_register
6793  * @hw: pointer to the HW structure
6794  * @page: registers page number
6795  * @reg: register address in the page
6796  * @phy_addr: PHY address on MDIO interface
6797  * @value: PHY register value
6798  *
6799  * Reads specified PHY register value
6800  **/
6801 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6802                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6803 {
6804         enum i40e_status_code status;
6805
6806         switch (hw->device_id) {
6807         case I40E_DEV_ID_1G_BASE_T_X722:
6808                 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6809                                                          value);
6810                 break;
6811         case I40E_DEV_ID_10G_BASE_T:
6812         case I40E_DEV_ID_10G_BASE_T4:
6813         case I40E_DEV_ID_5G_BASE_T_BC:
6814         case I40E_DEV_ID_10G_BASE_T_X722:
6815         case I40E_DEV_ID_25G_B:
6816         case I40E_DEV_ID_25G_SFP28:
6817                 status = i40e_read_phy_register_clause45(hw, page, reg,
6818                                                          phy_addr, value);
6819                 break;
6820         default:
6821                 status = I40E_ERR_UNKNOWN_PHY;
6822                 break;
6823         }
6824
6825         return status;
6826 }
6827
6828 /**
6829  * i40e_get_phy_address
6830  * @hw: pointer to the HW structure
6831  * @dev_num: PHY port num that address we want
6832  *
6833  * Gets PHY address for current port
6834  **/
6835 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6836 {
6837         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6838         u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6839
6840         return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6841 }
6842
6843 /**
6844  * i40e_blink_phy_led
6845  * @hw: pointer to the HW structure
6846  * @time: time how long led will blinks in secs
6847  * @interval: gap between LED on and off in msecs
6848  *
6849  * Blinks PHY link LED
6850  **/
6851 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6852                                               u32 time, u32 interval)
6853 {
6854         enum i40e_status_code status = I40E_SUCCESS;
6855         u32 i;
6856         u16 led_ctl = 0;
6857         u16 gpio_led_port;
6858         u16 led_reg;
6859         u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6860         u8 phy_addr = 0;
6861         u8 port_num;
6862
6863         i = rd32(hw, I40E_PFGEN_PORTNUM);
6864         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6865         phy_addr = i40e_get_phy_address(hw, port_num);
6866
6867         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6868              led_addr++) {
6869                 status = i40e_read_phy_register_clause45(hw,
6870                                                          I40E_PHY_COM_REG_PAGE,
6871                                                          led_addr, phy_addr,
6872                                                          &led_reg);
6873                 if (status)
6874                         goto phy_blinking_end;
6875                 led_ctl = led_reg;
6876                 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6877                         led_reg = 0;
6878                         status = i40e_write_phy_register_clause45(hw,
6879                                                          I40E_PHY_COM_REG_PAGE,
6880                                                          led_addr, phy_addr,
6881                                                          led_reg);
6882                         if (status)
6883                                 goto phy_blinking_end;
6884                         break;
6885                 }
6886         }
6887
6888         if (time > 0 && interval > 0) {
6889                 for (i = 0; i < time * 1000; i += interval) {
6890                         status = i40e_read_phy_register_clause45(hw,
6891                                                 I40E_PHY_COM_REG_PAGE,
6892                                                 led_addr, phy_addr, &led_reg);
6893                         if (status)
6894                                 goto restore_config;
6895                         if (led_reg & I40E_PHY_LED_MANUAL_ON)
6896                                 led_reg = 0;
6897                         else
6898                                 led_reg = I40E_PHY_LED_MANUAL_ON;
6899                         status = i40e_write_phy_register_clause45(hw,
6900                                                 I40E_PHY_COM_REG_PAGE,
6901                                                 led_addr, phy_addr, led_reg);
6902                         if (status)
6903                                 goto restore_config;
6904                         i40e_msec_delay(interval);
6905                 }
6906         }
6907
6908 restore_config:
6909         status = i40e_write_phy_register_clause45(hw,
6910                                                   I40E_PHY_COM_REG_PAGE,
6911                                                   led_addr, phy_addr, led_ctl);
6912
6913 phy_blinking_end:
6914         return status;
6915 }
6916
6917 /**
6918  * i40e_led_get_reg - read LED register
6919  * @hw: pointer to the HW structure
6920  * @led_addr: LED register address
6921  * @reg_val: read register value
6922  **/
6923 enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr,
6924                                        u32 *reg_val)
6925 {
6926         enum i40e_status_code status;
6927         u8 phy_addr = 0;
6928
6929         *reg_val = 0;
6930         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6931                 status = i40e_aq_get_phy_register(hw,
6932                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6933                                                 I40E_PHY_COM_REG_PAGE, true,
6934                                                 I40E_PHY_LED_PROV_REG_1,
6935                                                 reg_val, NULL);
6936         } else {
6937                 phy_addr = i40e_get_phy_address(hw, hw->port);
6938                 status = i40e_read_phy_register_clause45(hw,
6939                                                          I40E_PHY_COM_REG_PAGE,
6940                                                          led_addr, phy_addr,
6941                                                          (u16 *)reg_val);
6942         }
6943         return status;
6944 }
6945
6946 /**
6947  * i40e_led_set_reg - write LED register
6948  * @hw: pointer to the HW structure
6949  * @led_addr: LED register address
6950  * @reg_val: register value to write
6951  **/
6952 enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr,
6953                                        u32 reg_val)
6954 {
6955         enum i40e_status_code status;
6956         u8 phy_addr = 0;
6957
6958         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6959                 status = i40e_aq_set_phy_register(hw,
6960                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6961                                                 I40E_PHY_COM_REG_PAGE, true,
6962                                                 I40E_PHY_LED_PROV_REG_1,
6963                                                 reg_val, NULL);
6964         } else {
6965                 phy_addr = i40e_get_phy_address(hw, hw->port);
6966                 status = i40e_write_phy_register_clause45(hw,
6967                                                           I40E_PHY_COM_REG_PAGE,
6968                                                           led_addr, phy_addr,
6969                                                           (u16)reg_val);
6970         }
6971
6972         return status;
6973 }
6974
6975 /**
6976  * i40e_led_get_phy - return current on/off mode
6977  * @hw: pointer to the hw struct
6978  * @led_addr: address of led register to use
6979  * @val: original value of register to use
6980  *
6981  **/
6982 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6983                                        u16 *val)
6984 {
6985         enum i40e_status_code status = I40E_SUCCESS;
6986         u16 gpio_led_port;
6987         u32 reg_val_aq;
6988         u16 temp_addr;
6989         u8 phy_addr = 0;
6990         u16 reg_val;
6991
6992         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6993                 status = i40e_aq_get_phy_register(hw,
6994                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6995                                                 I40E_PHY_COM_REG_PAGE, true,
6996                                                 I40E_PHY_LED_PROV_REG_1,
6997                                                 &reg_val_aq, NULL);
6998                 if (status == I40E_SUCCESS)
6999                         *val = (u16)reg_val_aq;
7000                 return status;
7001         }
7002         temp_addr = I40E_PHY_LED_PROV_REG_1;
7003         phy_addr = i40e_get_phy_address(hw, hw->port);
7004         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
7005              temp_addr++) {
7006                 status = i40e_read_phy_register_clause45(hw,
7007                                                          I40E_PHY_COM_REG_PAGE,
7008                                                          temp_addr, phy_addr,
7009                                                          &reg_val);
7010                 if (status)
7011                         return status;
7012                 *val = reg_val;
7013                 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
7014                         *led_addr = temp_addr;
7015                         break;
7016                 }
7017         }
7018         return status;
7019 }
7020
7021 /**
7022  * i40e_led_set_phy
7023  * @hw: pointer to the HW structure
7024  * @on: true or false
7025  * @led_addr: address of led register to use
7026  * @mode: original val plus bit for set or ignore
7027  *
7028  * Set led's on or off when controlled by the PHY
7029  *
7030  **/
7031 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
7032                                        u16 led_addr, u32 mode)
7033 {
7034         enum i40e_status_code status = I40E_SUCCESS;
7035         u32 led_ctl = 0;
7036         u32 led_reg = 0;
7037
7038         status = i40e_led_get_reg(hw, led_addr, &led_reg);
7039         if (status)
7040                 return status;
7041         led_ctl = led_reg;
7042         if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
7043                 led_reg = 0;
7044                 status = i40e_led_set_reg(hw, led_addr, led_reg);
7045                 if (status)
7046                         return status;
7047         }
7048         status = i40e_led_get_reg(hw, led_addr, &led_reg);
7049         if (status)
7050                 goto restore_config;
7051         if (on)
7052                 led_reg = I40E_PHY_LED_MANUAL_ON;
7053         else
7054                 led_reg = 0;
7055         status = i40e_led_set_reg(hw, led_addr, led_reg);
7056         if (status)
7057                 goto restore_config;
7058         if (mode & I40E_PHY_LED_MODE_ORIG) {
7059                 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
7060                 status = i40e_led_set_reg(hw, led_addr, led_ctl);
7061         }
7062         return status;
7063
7064 restore_config:
7065         status = i40e_led_set_reg(hw, led_addr, led_ctl);
7066         return status;
7067 }
7068 #endif /* PF_DRIVER */
7069 /**
7070  * i40e_get_phy_lpi_status - read LPI status from PHY or MAC register
7071  * @hw: pointer to the hw struct
7072  * @stat: pointer to structure with status of rx and tx lpi
7073  *
7074  * Read LPI state directly from external PHY register or from MAC
7075  * register, depending on device ID and current link speed.
7076  */
7077 enum i40e_status_code i40e_get_phy_lpi_status(struct i40e_hw *hw,
7078                                               struct i40e_hw_port_stats *stat)
7079 {
7080         enum i40e_status_code ret = I40E_SUCCESS;
7081         u32 val;
7082
7083         stat->rx_lpi_status = 0;
7084         stat->tx_lpi_status = 0;
7085
7086         if ((hw->device_id == I40E_DEV_ID_10G_BASE_T_BC ||
7087              hw->device_id == I40E_DEV_ID_5G_BASE_T_BC) &&
7088             (hw->phy.link_info.link_speed == I40E_LINK_SPEED_2_5GB ||
7089              hw->phy.link_info.link_speed == I40E_LINK_SPEED_5GB)) {
7090                 ret = i40e_aq_get_phy_register(hw,
7091                                                I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
7092                                                I40E_BCM_PHY_PCS_STATUS1_PAGE,
7093                                                true,
7094                                                I40E_BCM_PHY_PCS_STATUS1_REG,
7095                                                &val, NULL);
7096
7097                 if (ret != I40E_SUCCESS)
7098                         return ret;
7099
7100                 stat->rx_lpi_status = !!(val & I40E_BCM_PHY_PCS_STATUS1_RX_LPI);
7101                 stat->tx_lpi_status = !!(val & I40E_BCM_PHY_PCS_STATUS1_TX_LPI);
7102
7103                 return ret;
7104         }
7105
7106         val = rd32(hw, I40E_PRTPM_EEE_STAT);
7107         stat->rx_lpi_status = (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
7108                                I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
7109         stat->tx_lpi_status = (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
7110                                I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
7111
7112         return ret;
7113 }
7114
7115 /**
7116  * i40e_get_lpi_counters - read LPI counters from EEE statistics
7117  * @hw: pointer to the hw struct
7118  * @tx_counter: pointer to memory for TX LPI counter
7119  * @rx_counter: pointer to memory for RX LPI counter
7120  * @is_clear:   returns true if counters are clear after read
7121  *
7122  * Read Low Power Idle (LPI) mode counters from Energy Efficient
7123  * Ethernet (EEE) statistics.
7124  **/
7125 enum i40e_status_code i40e_get_lpi_counters(struct i40e_hw *hw,
7126                                             u32 *tx_counter, u32 *rx_counter,
7127                                             bool *is_clear)
7128 {
7129         /* only X710-T*L requires special handling of counters
7130          * for other devices we just read the MAC registers
7131          */
7132         if ((hw->device_id == I40E_DEV_ID_10G_BASE_T_BC ||
7133              hw->device_id == I40E_DEV_ID_5G_BASE_T_BC) &&
7134             hw->phy.link_info.link_speed != I40E_LINK_SPEED_1GB) {
7135                 enum i40e_status_code retval;
7136                 u32 cmd_status = 0;
7137
7138                 *is_clear = false;
7139                 retval = i40e_aq_run_phy_activity(hw,
7140                                 I40E_AQ_RUN_PHY_ACT_ID_USR_DFND,
7141                                 I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_STAT,
7142                                 &cmd_status, tx_counter, rx_counter, NULL);
7143
7144                 if (!retval && cmd_status != I40E_AQ_RUN_PHY_ACT_CMD_STAT_SUCC)
7145                         retval = I40E_ERR_ADMIN_QUEUE_ERROR;
7146
7147                 return retval;
7148         }
7149
7150         *is_clear = true;
7151         *tx_counter = rd32(hw, I40E_PRTPM_TLPIC);
7152         *rx_counter = rd32(hw, I40E_PRTPM_RLPIC);
7153
7154         return I40E_SUCCESS;
7155 }
7156
7157 /**
7158  * i40e_get_lpi_duration - read LPI time duration from EEE statistics
7159  * @hw: pointer to the hw struct
7160  * @stat: pointer to structure with status of rx and tx lpi
7161  * @tx_duration: pointer to memory for TX LPI time duration
7162  * @rx_duration: pointer to memory for RX LPI time duration
7163  *
7164  * Read Low Power Idle (LPI) mode time duration from Energy Efficient
7165  * Ethernet (EEE) statistics.
7166  */
7167 enum i40e_status_code i40e_get_lpi_duration(struct i40e_hw *hw,
7168                                             struct i40e_hw_port_stats *stat,
7169                                             u64 *tx_duration, u64 *rx_duration)
7170 {
7171         u32 tx_time_dur, rx_time_dur;
7172         enum i40e_status_code retval;
7173         u32 cmd_status;
7174
7175         if (hw->device_id != I40E_DEV_ID_10G_BASE_T_BC &&
7176             hw->device_id != I40E_DEV_ID_5G_BASE_T_BC)
7177                 return I40E_ERR_NOT_IMPLEMENTED;
7178
7179         retval = i40e_aq_run_phy_activity
7180                 (hw, I40E_AQ_RUN_PHY_ACT_ID_USR_DFND,
7181                 I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_DUR,
7182                 &cmd_status, &tx_time_dur, &rx_time_dur, NULL);
7183
7184         if (retval)
7185                 return retval;
7186         if ((cmd_status & I40E_AQ_RUN_PHY_ACT_CMD_STAT_MASK) !=
7187             I40E_AQ_RUN_PHY_ACT_CMD_STAT_SUCC)
7188                 return I40E_ERR_ADMIN_QUEUE_ERROR;
7189
7190         if (hw->phy.link_info.link_speed == I40E_LINK_SPEED_1GB &&
7191             !tx_time_dur && !rx_time_dur &&
7192             stat->tx_lpi_status && stat->rx_lpi_status) {
7193                 retval = i40e_aq_run_phy_activity
7194                         (hw, I40E_AQ_RUN_PHY_ACT_ID_USR_DFND,
7195                         I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_STAT_DUR,
7196                         &cmd_status,
7197                         &tx_time_dur, &rx_time_dur, NULL);
7198
7199                 if (retval)
7200                         return retval;
7201                 if ((cmd_status & I40E_AQ_RUN_PHY_ACT_CMD_STAT_MASK) !=
7202                     I40E_AQ_RUN_PHY_ACT_CMD_STAT_SUCC)
7203                         return I40E_ERR_ADMIN_QUEUE_ERROR;
7204                 tx_time_dur = 0;
7205                 rx_time_dur = 0;
7206         }
7207
7208         *tx_duration = tx_time_dur;
7209         *rx_duration = rx_time_dur;
7210
7211         return retval;
7212 }
7213
7214 /**
7215  * i40e_lpi_stat_update - update LPI counters with values relative to offset
7216  * @hw: pointer to the hw struct
7217  * @offset_loaded: flag indicating need of writing current value to offset
7218  * @tx_offset: pointer to offset of TX LPI counter
7219  * @tx_stat: pointer to value of TX LPI counter
7220  * @rx_offset: pointer to offset of RX LPI counter
7221  * @rx_stat: pointer to value of RX LPI counter
7222  *
7223  * Update Low Power Idle (LPI) mode counters while having regard to passed
7224  * offsets.
7225  **/
7226 enum i40e_status_code i40e_lpi_stat_update(struct i40e_hw *hw,
7227                                            bool offset_loaded, u64 *tx_offset,
7228                                            u64 *tx_stat, u64 *rx_offset,
7229                                            u64 *rx_stat)
7230 {
7231         enum i40e_status_code retval;
7232         u32 tx_counter, rx_counter;
7233         bool is_clear;
7234
7235         retval = i40e_get_lpi_counters(hw, &tx_counter, &rx_counter, &is_clear);
7236         if (retval)
7237                 goto err;
7238
7239         if (is_clear) {
7240                 *tx_stat += tx_counter;
7241                 *rx_stat += rx_counter;
7242         } else {
7243                 if (!offset_loaded) {
7244                         *tx_offset = tx_counter;
7245                         *rx_offset = rx_counter;
7246                 }
7247
7248                 *tx_stat = (tx_counter >= *tx_offset) ?
7249                         (u32)(tx_counter - *tx_offset) :
7250                         (u32)((tx_counter + BIT_ULL(32)) - *tx_offset);
7251                 *rx_stat = (rx_counter >= *rx_offset) ?
7252                         (u32)(rx_counter - *rx_offset) :
7253                         (u32)((rx_counter + BIT_ULL(32)) - *rx_offset);
7254         }
7255 err:
7256         return retval;
7257 }
7258
7259 /**
7260  * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
7261  * @hw: pointer to the hw struct
7262  * @reg_addr: register address
7263  * @reg_val: ptr to register value
7264  * @cmd_details: pointer to command details structure or NULL
7265  *
7266  * Use the firmware to read the Rx control register,
7267  * especially useful if the Rx unit is under heavy pressure
7268  **/
7269 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
7270                                 u32 reg_addr, u32 *reg_val,
7271                                 struct i40e_asq_cmd_details *cmd_details)
7272 {
7273         struct i40e_aq_desc desc;
7274         struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
7275                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
7276         enum i40e_status_code status;
7277
7278         if (reg_val == NULL)
7279                 return I40E_ERR_PARAM;
7280
7281         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
7282
7283         cmd_resp->address = CPU_TO_LE32(reg_addr);
7284
7285         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7286
7287         if (status == I40E_SUCCESS)
7288                 *reg_val = LE32_TO_CPU(cmd_resp->value);
7289
7290         return status;
7291 }
7292
7293 /**
7294  * i40e_read_rx_ctl - read from an Rx control register
7295  * @hw: pointer to the hw struct
7296  * @reg_addr: register address
7297  **/
7298 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
7299 {
7300         enum i40e_status_code status = I40E_SUCCESS;
7301         bool use_register;
7302         int retry = 5;
7303         u32 val = 0;
7304
7305         use_register = (((hw->aq.api_maj_ver == 1) &&
7306                         (hw->aq.api_min_ver < 5)) ||
7307                         (hw->mac.type == I40E_MAC_X722));
7308         if (!use_register) {
7309 do_retry:
7310                 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
7311                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
7312                         i40e_msec_delay(1);
7313                         retry--;
7314                         goto do_retry;
7315                 }
7316         }
7317
7318         /* if the AQ access failed, try the old-fashioned way */
7319         if (status || use_register)
7320                 val = rd32(hw, reg_addr);
7321
7322         return val;
7323 }
7324
7325 /**
7326  * i40e_aq_rx_ctl_write_register
7327  * @hw: pointer to the hw struct
7328  * @reg_addr: register address
7329  * @reg_val: register value
7330  * @cmd_details: pointer to command details structure or NULL
7331  *
7332  * Use the firmware to write to an Rx control register,
7333  * especially useful if the Rx unit is under heavy pressure
7334  **/
7335 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
7336                                 u32 reg_addr, u32 reg_val,
7337                                 struct i40e_asq_cmd_details *cmd_details)
7338 {
7339         struct i40e_aq_desc desc;
7340         struct i40e_aqc_rx_ctl_reg_read_write *cmd =
7341                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
7342         enum i40e_status_code status;
7343
7344         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
7345
7346         cmd->address = CPU_TO_LE32(reg_addr);
7347         cmd->value = CPU_TO_LE32(reg_val);
7348
7349         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7350
7351         return status;
7352 }
7353
7354 /**
7355  * i40e_write_rx_ctl - write to an Rx control register
7356  * @hw: pointer to the hw struct
7357  * @reg_addr: register address
7358  * @reg_val: register value
7359  **/
7360 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
7361 {
7362         enum i40e_status_code status = I40E_SUCCESS;
7363         bool use_register;
7364         int retry = 5;
7365
7366         use_register = (((hw->aq.api_maj_ver == 1) &&
7367                         (hw->aq.api_min_ver < 5)) ||
7368                         (hw->mac.type == I40E_MAC_X722));
7369         if (!use_register) {
7370 do_retry:
7371                 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
7372                                                        reg_val, NULL);
7373                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
7374                         i40e_msec_delay(1);
7375                         retry--;
7376                         goto do_retry;
7377                 }
7378         }
7379
7380         /* if the AQ access failed, try the old-fashioned way */
7381         if (status || use_register)
7382                 wr32(hw, reg_addr, reg_val);
7383 }
7384
7385 /**
7386  * i40e_mdio_if_number_selection - MDIO I/F number selection
7387  * @hw: pointer to the hw struct
7388  * @set_mdio: use MDIO I/F number specified by mdio_num
7389  * @mdio_num: MDIO I/F number
7390  * @cmd: pointer to PHY Register command structure
7391  **/
7392 static void
7393 i40e_mdio_if_number_selection(struct i40e_hw *hw, bool set_mdio, u8 mdio_num,
7394                               struct i40e_aqc_phy_register_access *cmd)
7395 {
7396         if (set_mdio && cmd->phy_interface == I40E_AQ_PHY_REG_ACCESS_EXTERNAL) {
7397                 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_EXTENDED)
7398                         cmd->cmd_flags |=
7399                                 I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER |
7400                                 ((mdio_num <<
7401                                 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT) &
7402                                 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK);
7403                 else
7404                         i40e_debug(hw, I40E_DEBUG_PHY,
7405                                    "MDIO I/F number selection not supported by current FW version.\n");
7406         }
7407 }
7408
7409 /**
7410  * i40e_aq_set_phy_register_ext
7411  * @hw: pointer to the hw struct
7412  * @phy_select: select which phy should be accessed
7413  * @dev_addr: PHY device address
7414  * @page_change: enable auto page change
7415  * @set_mdio: use MDIO I/F number specified by mdio_num
7416  * @mdio_num: MDIO I/F number
7417  * @reg_addr: PHY register address
7418  * @reg_val: new register value
7419  * @cmd_details: pointer to command details structure or NULL
7420  *
7421  * Write the external PHY register.
7422  * NOTE: In common cases MDIO I/F number should not be changed, thats why you
7423  * may use simple wrapper i40e_aq_set_phy_register.
7424  **/
7425 enum i40e_status_code
7426 i40e_aq_set_phy_register_ext(struct i40e_hw *hw,
7427                              u8 phy_select, u8 dev_addr, bool page_change,
7428                              bool set_mdio, u8 mdio_num,
7429                              u32 reg_addr, u32 reg_val,
7430                              struct i40e_asq_cmd_details *cmd_details)
7431 {
7432         struct i40e_aq_desc desc;
7433         struct i40e_aqc_phy_register_access *cmd =
7434                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7435         enum i40e_status_code status;
7436
7437         i40e_fill_default_direct_cmd_desc(&desc,
7438                                           i40e_aqc_opc_set_phy_register);
7439
7440         cmd->phy_interface = phy_select;
7441         cmd->dev_addres = dev_addr;
7442         cmd->reg_address = CPU_TO_LE32(reg_addr);
7443         cmd->reg_value = CPU_TO_LE32(reg_val);
7444
7445         if (!page_change)
7446                 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
7447
7448         i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd);
7449
7450         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7451
7452         return status;
7453 }
7454
7455 /**
7456  * i40e_aq_get_phy_register_ext
7457  * @hw: pointer to the hw struct
7458  * @phy_select: select which phy should be accessed
7459  * @dev_addr: PHY device address
7460  * @page_change: enable auto page change
7461  * @set_mdio: use MDIO I/F number specified by mdio_num
7462  * @mdio_num: MDIO I/F number
7463  * @reg_addr: PHY register address
7464  * @reg_val: read register value
7465  * @cmd_details: pointer to command details structure or NULL
7466  *
7467  * Read the external PHY register.
7468  * NOTE: In common cases MDIO I/F number should not be changed, thats why you
7469  * may use simple wrapper i40e_aq_get_phy_register.
7470  **/
7471 enum i40e_status_code
7472 i40e_aq_get_phy_register_ext(struct i40e_hw *hw,
7473                              u8 phy_select, u8 dev_addr, bool page_change,
7474                              bool set_mdio, u8 mdio_num,
7475                              u32 reg_addr, u32 *reg_val,
7476                              struct i40e_asq_cmd_details *cmd_details)
7477 {
7478         struct i40e_aq_desc desc;
7479         struct i40e_aqc_phy_register_access *cmd =
7480                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7481         enum i40e_status_code status;
7482
7483         i40e_fill_default_direct_cmd_desc(&desc,
7484                                           i40e_aqc_opc_get_phy_register);
7485
7486         cmd->phy_interface = phy_select;
7487         cmd->dev_addres = dev_addr;
7488         cmd->reg_address = CPU_TO_LE32(reg_addr);
7489
7490         if (!page_change)
7491                 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
7492
7493         i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd);
7494
7495         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7496         if (!status)
7497                 *reg_val = LE32_TO_CPU(cmd->reg_value);
7498
7499         return status;
7500 }
7501
7502 /**
7503  * i40e_aq_run_phy_activity
7504  * @hw: pointer to the hw struct
7505  * @activity_id: ID of DNL activity to run
7506  * @dnl_opcode: opcode passed to DNL script
7507  * @cmd_status: pointer to memory to write return value of DNL script
7508  * @data0: pointer to memory for first 4 bytes of data returned by DNL script
7509  * @data1: pointer to memory for last 4 bytes of data returned by DNL script
7510  * @cmd_details: pointer to command details structure or NULL
7511  *
7512  * Run DNL admin command.
7513  **/
7514 enum i40e_status_code
7515 i40e_aq_run_phy_activity(struct i40e_hw *hw, u16 activity_id, u32 dnl_opcode,
7516                          u32 *cmd_status, u32 *data0, u32 *data1,
7517                          struct i40e_asq_cmd_details *cmd_details)
7518 {
7519         struct i40e_aqc_run_phy_activity *cmd;
7520         enum i40e_status_code retval;
7521         struct i40e_aq_desc desc;
7522
7523         cmd = (struct i40e_aqc_run_phy_activity *)&desc.params.raw;
7524
7525         if (!cmd_status || !data0 || !data1) {
7526                 retval = I40E_ERR_PARAM;
7527                 goto err;
7528         }
7529
7530         i40e_fill_default_direct_cmd_desc(&desc,
7531                                           i40e_aqc_opc_run_phy_activity);
7532
7533         cmd->activity_id = CPU_TO_LE16(activity_id);
7534         cmd->params.cmd.dnl_opcode = CPU_TO_LE32(dnl_opcode);
7535
7536         retval = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7537         if (retval)
7538                 goto err;
7539
7540         *cmd_status = LE32_TO_CPU(cmd->params.resp.cmd_status);
7541         *data0 = LE32_TO_CPU(cmd->params.resp.data0);
7542         *data1 = LE32_TO_CPU(cmd->params.resp.data1);
7543 err:
7544         return retval;
7545 }
7546
7547 #ifdef VF_DRIVER
7548
7549 /**
7550  * i40e_aq_send_msg_to_pf
7551  * @hw: pointer to the hardware structure
7552  * @v_opcode: opcodes for VF-PF communication
7553  * @v_retval: return error code
7554  * @msg: pointer to the msg buffer
7555  * @msglen: msg length
7556  * @cmd_details: pointer to command details
7557  *
7558  * Send message to PF driver using admin queue. By default, this message
7559  * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
7560  * completion before returning.
7561  **/
7562 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
7563                                 enum virtchnl_ops v_opcode,
7564                                 enum i40e_status_code v_retval,
7565                                 u8 *msg, u16 msglen,
7566                                 struct i40e_asq_cmd_details *cmd_details)
7567 {
7568         struct i40e_aq_desc desc;
7569         struct i40e_asq_cmd_details details;
7570         enum i40e_status_code status;
7571
7572         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
7573         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
7574         desc.cookie_high = CPU_TO_LE32(v_opcode);
7575         desc.cookie_low = CPU_TO_LE32(v_retval);
7576         if (msglen) {
7577                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
7578                                                 | I40E_AQ_FLAG_RD));
7579                 if (msglen > I40E_AQ_LARGE_BUF)
7580                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7581                 desc.datalen = CPU_TO_LE16(msglen);
7582         }
7583         if (!cmd_details) {
7584                 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
7585                 details.async = true;
7586                 cmd_details = &details;
7587         }
7588         status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
7589                                        msglen, cmd_details);
7590         return status;
7591 }
7592
7593 /**
7594  * i40e_vf_parse_hw_config
7595  * @hw: pointer to the hardware structure
7596  * @msg: pointer to the virtual channel VF resource structure
7597  *
7598  * Given a VF resource message from the PF, populate the hw struct
7599  * with appropriate information.
7600  **/
7601 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
7602                              struct virtchnl_vf_resource *msg)
7603 {
7604         struct virtchnl_vsi_resource *vsi_res;
7605         int i;
7606
7607         vsi_res = &msg->vsi_res[0];
7608
7609         hw->dev_caps.num_vsis = msg->num_vsis;
7610         hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
7611         hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
7612         hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
7613         hw->dev_caps.dcb = msg->vf_cap_flags &
7614                            VIRTCHNL_VF_OFFLOAD_L2;
7615         hw->dev_caps.iwarp = (msg->vf_cap_flags &
7616                               VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
7617         for (i = 0; i < msg->num_vsis; i++) {
7618                 if (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) {
7619                         i40e_memcpy(hw->mac.perm_addr,
7620                                     vsi_res->default_mac_addr,
7621                                     ETH_ALEN,
7622                                     I40E_NONDMA_TO_NONDMA);
7623                         i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
7624                                     ETH_ALEN,
7625                                     I40E_NONDMA_TO_NONDMA);
7626                 }
7627                 vsi_res++;
7628         }
7629 }
7630
7631 /**
7632  * i40e_vf_reset
7633  * @hw: pointer to the hardware structure
7634  *
7635  * Send a VF_RESET message to the PF. Does not wait for response from PF
7636  * as none will be forthcoming. Immediately after calling this function,
7637  * the admin queue should be shut down and (optionally) reinitialized.
7638  **/
7639 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
7640 {
7641         return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF,
7642                                       I40E_SUCCESS, NULL, 0, NULL);
7643 }
7644 #endif /* VF_DRIVER */
7645
7646 /**
7647  * i40e_aq_set_arp_proxy_config
7648  * @hw: pointer to the HW structure
7649  * @proxy_config: pointer to proxy config command table struct
7650  * @cmd_details: pointer to command details
7651  *
7652  * Set ARP offload parameters from pre-populated
7653  * i40e_aqc_arp_proxy_data struct
7654  **/
7655 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
7656                                 struct i40e_aqc_arp_proxy_data *proxy_config,
7657                                 struct i40e_asq_cmd_details *cmd_details)
7658 {
7659         struct i40e_aq_desc desc;
7660         enum i40e_status_code status;
7661
7662         if (!proxy_config)
7663                 return I40E_ERR_PARAM;
7664
7665         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
7666
7667         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7668         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7669         desc.params.external.addr_high =
7670                                   CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
7671         desc.params.external.addr_low =
7672                                   CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
7673         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_arp_proxy_data));
7674
7675         status = i40e_asq_send_command(hw, &desc, proxy_config,
7676                                        sizeof(struct i40e_aqc_arp_proxy_data),
7677                                        cmd_details);
7678
7679         return status;
7680 }
7681
7682 /**
7683  * i40e_aq_opc_set_ns_proxy_table_entry
7684  * @hw: pointer to the HW structure
7685  * @ns_proxy_table_entry: pointer to NS table entry command struct
7686  * @cmd_details: pointer to command details
7687  *
7688  * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
7689  * from pre-populated i40e_aqc_ns_proxy_data struct
7690  **/
7691 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
7692                         struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
7693                         struct i40e_asq_cmd_details *cmd_details)
7694 {
7695         struct i40e_aq_desc desc;
7696         enum i40e_status_code status;
7697
7698         if (!ns_proxy_table_entry)
7699                 return I40E_ERR_PARAM;
7700
7701         i40e_fill_default_direct_cmd_desc(&desc,
7702                                 i40e_aqc_opc_set_ns_proxy_table_entry);
7703
7704         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7705         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7706         desc.params.external.addr_high =
7707                 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
7708         desc.params.external.addr_low =
7709                 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
7710         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_ns_proxy_data));
7711
7712         status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
7713                                        sizeof(struct i40e_aqc_ns_proxy_data),
7714                                        cmd_details);
7715
7716         return status;
7717 }
7718
7719 /**
7720  * i40e_aq_set_clear_wol_filter
7721  * @hw: pointer to the hw struct
7722  * @filter_index: index of filter to modify (0-7)
7723  * @filter: buffer containing filter to be set
7724  * @set_filter: true to set filter, false to clear filter
7725  * @no_wol_tco: if true, pass through packets cannot cause wake-up
7726  *              if false, pass through packets may cause wake-up
7727  * @filter_valid: true if filter action is valid
7728  * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
7729  * @cmd_details: pointer to command details structure or NULL
7730  *
7731  * Set or clear WoL filter for port attached to the PF
7732  **/
7733 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
7734                                 u8 filter_index,
7735                                 struct i40e_aqc_set_wol_filter_data *filter,
7736                                 bool set_filter, bool no_wol_tco,
7737                                 bool filter_valid, bool no_wol_tco_valid,
7738                                 struct i40e_asq_cmd_details *cmd_details)
7739 {
7740         struct i40e_aq_desc desc;
7741         struct i40e_aqc_set_wol_filter *cmd =
7742                 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
7743         enum i40e_status_code status;
7744         u16 cmd_flags = 0;
7745         u16 valid_flags = 0;
7746         u16 buff_len = 0;
7747
7748         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
7749
7750         if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
7751                 return  I40E_ERR_PARAM;
7752         cmd->filter_index = CPU_TO_LE16(filter_index);
7753
7754         if (set_filter) {
7755                 if (!filter)
7756                         return  I40E_ERR_PARAM;
7757
7758                 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
7759                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR;
7760         }
7761
7762         if (no_wol_tco)
7763                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
7764         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
7765
7766         if (filter_valid)
7767                 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
7768         if (no_wol_tco_valid)
7769                 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
7770         cmd->valid_flags = CPU_TO_LE16(valid_flags);
7771
7772         buff_len = sizeof(*filter);
7773         desc.datalen = CPU_TO_LE16(buff_len);
7774
7775         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7776         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7777
7778         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
7779         cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
7780
7781         status = i40e_asq_send_command(hw, &desc, filter,
7782                                        buff_len, cmd_details);
7783
7784         return status;
7785 }
7786
7787 /**
7788  * i40e_aq_get_wake_event_reason
7789  * @hw: pointer to the hw struct
7790  * @wake_reason: return value, index of matching filter
7791  * @cmd_details: pointer to command details structure or NULL
7792  *
7793  * Get information for the reason of a Wake Up event
7794  **/
7795 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
7796                                 u16 *wake_reason,
7797                                 struct i40e_asq_cmd_details *cmd_details)
7798 {
7799         struct i40e_aq_desc desc;
7800         struct i40e_aqc_get_wake_reason_completion *resp =
7801                 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
7802         enum i40e_status_code status;
7803
7804         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
7805
7806         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7807
7808         if (status == I40E_SUCCESS)
7809                 *wake_reason = LE16_TO_CPU(resp->wake_reason);
7810
7811         return status;
7812 }
7813
7814 /**
7815 * i40e_aq_clear_all_wol_filters
7816 * @hw: pointer to the hw struct
7817 * @cmd_details: pointer to command details structure or NULL
7818 *
7819 * Get information for the reason of a Wake Up event
7820 **/
7821 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw,
7822         struct i40e_asq_cmd_details *cmd_details)
7823 {
7824         struct i40e_aq_desc desc;
7825         enum i40e_status_code status;
7826
7827         i40e_fill_default_direct_cmd_desc(&desc,
7828                                           i40e_aqc_opc_clear_all_wol_filters);
7829
7830         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7831
7832         return status;
7833 }
7834
7835 /**
7836  * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
7837  * @hw: pointer to the hw struct
7838  * @buff: command buffer (size in bytes = buff_size)
7839  * @buff_size: buffer size in bytes
7840  * @track_id: package tracking id
7841  * @error_offset: returns error offset
7842  * @error_info: returns error information
7843  * @cmd_details: pointer to command details structure or NULL
7844  **/
7845 enum
7846 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
7847                                    u16 buff_size, u32 track_id,
7848                                    u32 *error_offset, u32 *error_info,
7849                                    struct i40e_asq_cmd_details *cmd_details)
7850 {
7851         struct i40e_aq_desc desc;
7852         struct i40e_aqc_write_personalization_profile *cmd =
7853                 (struct i40e_aqc_write_personalization_profile *)
7854                 &desc.params.raw;
7855         struct i40e_aqc_write_ddp_resp *resp;
7856         enum i40e_status_code status;
7857
7858         i40e_fill_default_direct_cmd_desc(&desc,
7859                                   i40e_aqc_opc_write_personalization_profile);
7860
7861         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
7862         if (buff_size > I40E_AQ_LARGE_BUF)
7863                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7864
7865         desc.datalen = CPU_TO_LE16(buff_size);
7866
7867         cmd->profile_track_id = CPU_TO_LE32(track_id);
7868
7869         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7870         if (!status) {
7871                 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
7872                 if (error_offset)
7873                         *error_offset = LE32_TO_CPU(resp->error_offset);
7874                 if (error_info)
7875                         *error_info = LE32_TO_CPU(resp->error_info);
7876         }
7877
7878         return status;
7879 }
7880
7881 /**
7882  * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
7883  * @hw: pointer to the hw struct
7884  * @buff: command buffer (size in bytes = buff_size)
7885  * @buff_size: buffer size in bytes
7886  * @flags: AdminQ command flags
7887  * @cmd_details: pointer to command details structure or NULL
7888  **/
7889 enum
7890 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
7891                                       u16 buff_size, u8 flags,
7892                                       struct i40e_asq_cmd_details *cmd_details)
7893 {
7894         struct i40e_aq_desc desc;
7895         struct i40e_aqc_get_applied_profiles *cmd =
7896                 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
7897         enum i40e_status_code status;
7898
7899         i40e_fill_default_direct_cmd_desc(&desc,
7900                           i40e_aqc_opc_get_personalization_profile_list);
7901
7902         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7903         if (buff_size > I40E_AQ_LARGE_BUF)
7904                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7905         desc.datalen = CPU_TO_LE16(buff_size);
7906
7907         cmd->flags = flags;
7908
7909         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7910
7911         return status;
7912 }
7913
7914 /**
7915  * i40e_find_segment_in_package
7916  * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
7917  * @pkg_hdr: pointer to the package header to be searched
7918  *
7919  * This function searches a package file for a particular segment type. On
7920  * success it returns a pointer to the segment header, otherwise it will
7921  * return NULL.
7922  **/
7923 struct i40e_generic_seg_header *
7924 i40e_find_segment_in_package(u32 segment_type,
7925                              struct i40e_package_header *pkg_hdr)
7926 {
7927         struct i40e_generic_seg_header *segment;
7928         u32 i;
7929
7930         /* Search all package segments for the requested segment type */
7931         for (i = 0; i < pkg_hdr->segment_count; i++) {
7932                 segment =
7933                         (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
7934                          pkg_hdr->segment_offset[i]);
7935
7936                 if (segment->type == segment_type)
7937                         return segment;
7938         }
7939
7940         return NULL;
7941 }
7942
7943 /* Get section table in profile */
7944 #define I40E_SECTION_TABLE(profile, sec_tbl)                            \
7945         do {                                                            \
7946                 struct i40e_profile_segment *p = (profile);             \
7947                 u32 count;                                              \
7948                 u32 *nvm;                                               \
7949                 count = p->device_table_count;                          \
7950                 nvm = (u32 *)&p->device_table[count];                   \
7951                 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \
7952         } while (0)
7953
7954 /* Get section header in profile */
7955 #define I40E_SECTION_HEADER(profile, offset)                            \
7956         (struct i40e_profile_section_header *)((u8 *)(profile) + (offset))
7957
7958 /**
7959  * i40e_find_section_in_profile
7960  * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE)
7961  * @profile: pointer to the i40e segment header to be searched
7962  *
7963  * This function searches i40e segment for a particular section type. On
7964  * success it returns a pointer to the section header, otherwise it will
7965  * return NULL.
7966  **/
7967 struct i40e_profile_section_header *
7968 i40e_find_section_in_profile(u32 section_type,
7969                              struct i40e_profile_segment *profile)
7970 {
7971         struct i40e_profile_section_header *sec;
7972         struct i40e_section_table *sec_tbl;
7973         u32 sec_off;
7974         u32 i;
7975
7976         if (profile->header.type != SEGMENT_TYPE_I40E)
7977                 return NULL;
7978
7979         I40E_SECTION_TABLE(profile, sec_tbl);
7980
7981         for (i = 0; i < sec_tbl->section_count; i++) {
7982                 sec_off = sec_tbl->section_offset[i];
7983                 sec = I40E_SECTION_HEADER(profile, sec_off);
7984                 if (sec->section.type == section_type)
7985                         return sec;
7986         }
7987
7988         return NULL;
7989 }
7990
7991 /**
7992  * i40e_ddp_exec_aq_section - Execute generic AQ for DDP
7993  * @hw: pointer to the hw struct
7994  * @aq: command buffer containing all data to execute AQ
7995  **/
7996 STATIC enum
7997 i40e_status_code i40e_ddp_exec_aq_section(struct i40e_hw *hw,
7998                                           struct i40e_profile_aq_section *aq)
7999 {
8000         enum i40e_status_code status;
8001         struct i40e_aq_desc desc;
8002         u8 *msg = NULL;
8003         u16 msglen;
8004
8005         i40e_fill_default_direct_cmd_desc(&desc, aq->opcode);
8006         desc.flags |= CPU_TO_LE16(aq->flags);
8007         i40e_memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw),
8008                     I40E_NONDMA_TO_NONDMA);
8009
8010         msglen = aq->datalen;
8011         if (msglen) {
8012                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
8013                                                 I40E_AQ_FLAG_RD));
8014                 if (msglen > I40E_AQ_LARGE_BUF)
8015                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
8016                 desc.datalen = CPU_TO_LE16(msglen);
8017                 msg = &aq->data[0];
8018         }
8019
8020         status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL);
8021
8022         if (status != I40E_SUCCESS) {
8023                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
8024                            "unable to exec DDP AQ opcode %u, error %d\n",
8025                            aq->opcode, status);
8026                 return status;
8027         }
8028
8029         /* copy returned desc to aq_buf */
8030         i40e_memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw),
8031                     I40E_NONDMA_TO_NONDMA);
8032
8033         return I40E_SUCCESS;
8034 }
8035
8036 /**
8037  * i40e_validate_profile
8038  * @hw: pointer to the hardware structure
8039  * @profile: pointer to the profile segment of the package to be validated
8040  * @track_id: package tracking id
8041  * @rollback: flag if the profile is for rollback.
8042  *
8043  * Validates supported devices and profile's sections.
8044  */
8045 STATIC enum i40e_status_code
8046 i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
8047                       u32 track_id, bool rollback)
8048 {
8049         struct i40e_profile_section_header *sec = NULL;
8050         enum i40e_status_code status = I40E_SUCCESS;
8051         struct i40e_section_table *sec_tbl;
8052         u32 vendor_dev_id;
8053         u32 dev_cnt;
8054         u32 sec_off;
8055         u32 i;
8056
8057         if (track_id == I40E_DDP_TRACKID_INVALID) {
8058                 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n");
8059                 return I40E_NOT_SUPPORTED;
8060         }
8061
8062         dev_cnt = profile->device_table_count;
8063         for (i = 0; i < dev_cnt; i++) {
8064                 vendor_dev_id = profile->device_table[i].vendor_dev_id;
8065                 if ((vendor_dev_id >> 16) == I40E_INTEL_VENDOR_ID &&
8066                     hw->device_id == (vendor_dev_id & 0xFFFF))
8067                         break;
8068         }
8069         if (dev_cnt && (i == dev_cnt)) {
8070                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
8071                            "Device doesn't support DDP\n");
8072                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
8073         }
8074
8075         I40E_SECTION_TABLE(profile, sec_tbl);
8076
8077         /* Validate sections types */
8078         for (i = 0; i < sec_tbl->section_count; i++) {
8079                 sec_off = sec_tbl->section_offset[i];
8080                 sec = I40E_SECTION_HEADER(profile, sec_off);
8081                 if (rollback) {
8082                         if (sec->section.type == SECTION_TYPE_MMIO ||
8083                             sec->section.type == SECTION_TYPE_AQ ||
8084                             sec->section.type == SECTION_TYPE_RB_AQ) {
8085                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
8086                                            "Not a roll-back package\n");
8087                                 return I40E_NOT_SUPPORTED;
8088                         }
8089                 } else {
8090                         if (sec->section.type == SECTION_TYPE_RB_AQ ||
8091                             sec->section.type == SECTION_TYPE_RB_MMIO) {
8092                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
8093                                            "Not an original package\n");
8094                                 return I40E_NOT_SUPPORTED;
8095                         }
8096                 }
8097         }
8098
8099         return status;
8100 }
8101
8102 /**
8103  * i40e_write_profile
8104  * @hw: pointer to the hardware structure
8105  * @profile: pointer to the profile segment of the package to be downloaded
8106  * @track_id: package tracking id
8107  *
8108  * Handles the download of a complete package.
8109  */
8110 enum i40e_status_code
8111 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
8112                    u32 track_id)
8113 {
8114         enum i40e_status_code status = I40E_SUCCESS;
8115         struct i40e_section_table *sec_tbl;
8116         struct i40e_profile_section_header *sec = NULL;
8117         struct i40e_profile_aq_section *ddp_aq;
8118         u32 section_size = 0;
8119         u32 offset = 0, info = 0;
8120         u32 sec_off;
8121         u32 i;
8122
8123         status = i40e_validate_profile(hw, profile, track_id, false);
8124         if (status)
8125                 return status;
8126
8127         I40E_SECTION_TABLE(profile, sec_tbl);
8128
8129         for (i = 0; i < sec_tbl->section_count; i++) {
8130                 sec_off = sec_tbl->section_offset[i];
8131                 sec = I40E_SECTION_HEADER(profile, sec_off);
8132                 /* Process generic admin command */
8133                 if (sec->section.type == SECTION_TYPE_AQ) {
8134                         ddp_aq = (struct i40e_profile_aq_section *)&sec[1];
8135                         status = i40e_ddp_exec_aq_section(hw, ddp_aq);
8136                         if (status) {
8137                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
8138                                            "Failed to execute aq: section %d, opcode %u\n",
8139                                            i, ddp_aq->opcode);
8140                                 break;
8141                         }
8142                         sec->section.type = SECTION_TYPE_RB_AQ;
8143                 }
8144
8145                 /* Skip any non-mmio sections */
8146                 if (sec->section.type != SECTION_TYPE_MMIO)
8147                         continue;
8148
8149                 section_size = sec->section.size +
8150                         sizeof(struct i40e_profile_section_header);
8151
8152                 /* Write MMIO section */
8153                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
8154                                            track_id, &offset, &info, NULL);
8155                 if (status) {
8156                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
8157                                    "Failed to write profile: section %d, offset %d, info %d\n",
8158                                    i, offset, info);
8159                         break;
8160                 }
8161         }
8162         return status;
8163 }
8164
8165 /**
8166  * i40e_rollback_profile
8167  * @hw: pointer to the hardware structure
8168  * @profile: pointer to the profile segment of the package to be removed
8169  * @track_id: package tracking id
8170  *
8171  * Rolls back previously loaded package.
8172  */
8173 enum i40e_status_code
8174 i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
8175                       u32 track_id)
8176 {
8177         struct i40e_profile_section_header *sec = NULL;
8178         enum i40e_status_code status = I40E_SUCCESS;
8179         struct i40e_section_table *sec_tbl;
8180         u32 offset = 0, info = 0;
8181         u32 section_size = 0;
8182         u32 sec_off;
8183         int i;
8184
8185         status = i40e_validate_profile(hw, profile, track_id, true);
8186         if (status)
8187                 return status;
8188
8189         I40E_SECTION_TABLE(profile, sec_tbl);
8190
8191         /* For rollback write sections in reverse */
8192         for (i = sec_tbl->section_count - 1; i >= 0; i--) {
8193                 sec_off = sec_tbl->section_offset[i];
8194                 sec = I40E_SECTION_HEADER(profile, sec_off);
8195
8196                 /* Skip any non-rollback sections */
8197                 if (sec->section.type != SECTION_TYPE_RB_MMIO)
8198                         continue;
8199
8200                 section_size = sec->section.size +
8201                         sizeof(struct i40e_profile_section_header);
8202
8203                 /* Write roll-back MMIO section */
8204                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
8205                                            track_id, &offset, &info, NULL);
8206                 if (status) {
8207                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
8208                                    "Failed to write profile: section %d, offset %d, info %d\n",
8209                                    i, offset, info);
8210                         break;
8211                 }
8212         }
8213         return status;
8214 }
8215
8216 /**
8217  * i40e_add_pinfo_to_list
8218  * @hw: pointer to the hardware structure
8219  * @profile: pointer to the profile segment of the package
8220  * @profile_info_sec: buffer for information section
8221  * @track_id: package tracking id
8222  *
8223  * Register a profile to the list of loaded profiles.
8224  */
8225 enum i40e_status_code
8226 i40e_add_pinfo_to_list(struct i40e_hw *hw,
8227                        struct i40e_profile_segment *profile,
8228                        u8 *profile_info_sec, u32 track_id)
8229 {
8230         enum i40e_status_code status = I40E_SUCCESS;
8231         struct i40e_profile_section_header *sec = NULL;
8232         struct i40e_profile_info *pinfo;
8233         u32 offset = 0, info = 0;
8234
8235         sec = (struct i40e_profile_section_header *)profile_info_sec;
8236         sec->tbl_size = 1;
8237         sec->data_end = sizeof(struct i40e_profile_section_header) +
8238                         sizeof(struct i40e_profile_info);
8239         sec->section.type = SECTION_TYPE_INFO;
8240         sec->section.offset = sizeof(struct i40e_profile_section_header);
8241         sec->section.size = sizeof(struct i40e_profile_info);
8242         pinfo = (struct i40e_profile_info *)(profile_info_sec +
8243                                              sec->section.offset);
8244         pinfo->track_id = track_id;
8245         pinfo->version = profile->version;
8246         pinfo->op = I40E_DDP_ADD_TRACKID;
8247         i40e_memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE,
8248                     I40E_NONDMA_TO_NONDMA);
8249
8250         status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
8251                                    track_id, &offset, &info, NULL);
8252         return status;
8253 }