drivers/net/i40e/base/i40e_common.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "i40e_type.h"
  35 #include "i40e_adminq.h"
  36 #include "i40e_prototype.h"
  37 #include "i40e_virtchnl.h"
  38
  39
  40 /**
  41  * i40e_set_mac_type - Sets MAC type
  42  * @hw: pointer to the HW structure
  43  *
  44  * This function sets the mac type of the adapter based on the
  45  * vendor ID and device ID stored in the hw structure.
  46  **/
  47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  49 #else
  50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  51 #endif
  52 {
  53         enum i40e_status_code status = I40E_SUCCESS;
  54
  55         DEBUGFUNC("i40e_set_mac_type\n");
  56
  57         if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
  58                 switch (hw->device_id) {
  59                 case I40E_DEV_ID_SFP_XL710:
  60                 case I40E_DEV_ID_QEMU:
  61                 case I40E_DEV_ID_KX_B:
  62                 case I40E_DEV_ID_KX_C:
  63                 case I40E_DEV_ID_QSFP_A:
  64                 case I40E_DEV_ID_QSFP_B:
  65                 case I40E_DEV_ID_QSFP_C:
  66                 case I40E_DEV_ID_10G_BASE_T:
  67                 case I40E_DEV_ID_10G_BASE_T4:
  68                 case I40E_DEV_ID_20G_KR2:
  69                 case I40E_DEV_ID_20G_KR2_A:
  70                 case I40E_DEV_ID_25G_B:
  71                 case I40E_DEV_ID_25G_SFP28:
  72                         hw->mac.type = I40E_MAC_XL710;
  73                         break;
  74 #ifdef X722_SUPPORT
  75 #ifdef X722_A0_SUPPORT
  76                 case I40E_DEV_ID_X722_A0:
  77 #endif
  78                 case I40E_DEV_ID_KX_X722:
  79                 case I40E_DEV_ID_QSFP_X722:
  80                 case I40E_DEV_ID_SFP_X722:
  81                 case I40E_DEV_ID_1G_BASE_T_X722:
  82                 case I40E_DEV_ID_10G_BASE_T_X722:
  83                 case I40E_DEV_ID_SFP_I_X722:
  84                         hw->mac.type = I40E_MAC_X722;
  85                         break;
  86 #endif
  87 #ifdef X722_SUPPORT
  88 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  89                 case I40E_DEV_ID_X722_VF:
  90                 case I40E_DEV_ID_X722_VF_HV:
  91 #ifdef X722_A0_SUPPORT
  92                 case I40E_DEV_ID_X722_A0_VF:
  93 #endif
  94                         hw->mac.type = I40E_MAC_X722_VF;
  95                         break;
  96 #endif /* INTEGRATED_VF || VF_DRIVER */
  97 #endif /* X722_SUPPORT */
  98 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  99                 case I40E_DEV_ID_VF:
 100                 case I40E_DEV_ID_VF_HV:
 101                         hw->mac.type = I40E_MAC_VF;
 102                         break;
 103 #endif
 104                 default:
 105                         hw->mac.type = I40E_MAC_GENERIC;
 106                         break;
 107                 }
 108         } else {
 109                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
 110         }
 111
 112         DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
 113                   hw->mac.type, status);
 114         return status;
 115 }
 116
 117 #ifndef I40E_NDIS_SUPPORT
 118 /**
 119  * i40e_aq_str - convert AQ err code to a string
 120  * @hw: pointer to the HW structure
 121  * @aq_err: the AQ error code to convert
 122  **/
 123 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
 124 {
 125         switch (aq_err) {
 126         case I40E_AQ_RC_OK:
 127                 return "OK";
 128         case I40E_AQ_RC_EPERM:
 129                 return "I40E_AQ_RC_EPERM";
 130         case I40E_AQ_RC_ENOENT:
 131                 return "I40E_AQ_RC_ENOENT";
 132         case I40E_AQ_RC_ESRCH:
 133                 return "I40E_AQ_RC_ESRCH";
 134         case I40E_AQ_RC_EINTR:
 135                 return "I40E_AQ_RC_EINTR";
 136         case I40E_AQ_RC_EIO:
 137                 return "I40E_AQ_RC_EIO";
 138         case I40E_AQ_RC_ENXIO:
 139                 return "I40E_AQ_RC_ENXIO";
 140         case I40E_AQ_RC_E2BIG:
 141                 return "I40E_AQ_RC_E2BIG";
 142         case I40E_AQ_RC_EAGAIN:
 143                 return "I40E_AQ_RC_EAGAIN";
 144         case I40E_AQ_RC_ENOMEM:
 145                 return "I40E_AQ_RC_ENOMEM";
 146         case I40E_AQ_RC_EACCES:
 147                 return "I40E_AQ_RC_EACCES";
 148         case I40E_AQ_RC_EFAULT:
 149                 return "I40E_AQ_RC_EFAULT";
 150         case I40E_AQ_RC_EBUSY:
 151                 return "I40E_AQ_RC_EBUSY";
 152         case I40E_AQ_RC_EEXIST:
 153                 return "I40E_AQ_RC_EEXIST";
 154         case I40E_AQ_RC_EINVAL:
 155                 return "I40E_AQ_RC_EINVAL";
 156         case I40E_AQ_RC_ENOTTY:
 157                 return "I40E_AQ_RC_ENOTTY";
 158         case I40E_AQ_RC_ENOSPC:
 159                 return "I40E_AQ_RC_ENOSPC";
 160         case I40E_AQ_RC_ENOSYS:
 161                 return "I40E_AQ_RC_ENOSYS";
 162         case I40E_AQ_RC_ERANGE:
 163                 return "I40E_AQ_RC_ERANGE";
 164         case I40E_AQ_RC_EFLUSHED:
 165                 return "I40E_AQ_RC_EFLUSHED";
 166         case I40E_AQ_RC_BAD_ADDR:
 167                 return "I40E_AQ_RC_BAD_ADDR";
 168         case I40E_AQ_RC_EMODE:
 169                 return "I40E_AQ_RC_EMODE";
 170         case I40E_AQ_RC_EFBIG:
 171                 return "I40E_AQ_RC_EFBIG";
 172         }
 173
 174         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 175         return hw->err_str;
 176 }
 177
 178 /**
 179  * i40e_stat_str - convert status err code to a string
 180  * @hw: pointer to the HW structure
 181  * @stat_err: the status error code to convert
 182  **/
 183 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
 184 {
 185         switch (stat_err) {
 186         case I40E_SUCCESS:
 187                 return "OK";
 188         case I40E_ERR_NVM:
 189                 return "I40E_ERR_NVM";
 190         case I40E_ERR_NVM_CHECKSUM:
 191                 return "I40E_ERR_NVM_CHECKSUM";
 192         case I40E_ERR_PHY:
 193                 return "I40E_ERR_PHY";
 194         case I40E_ERR_CONFIG:
 195                 return "I40E_ERR_CONFIG";
 196         case I40E_ERR_PARAM:
 197                 return "I40E_ERR_PARAM";
 198         case I40E_ERR_MAC_TYPE:
 199                 return "I40E_ERR_MAC_TYPE";
 200         case I40E_ERR_UNKNOWN_PHY:
 201                 return "I40E_ERR_UNKNOWN_PHY";
 202         case I40E_ERR_LINK_SETUP:
 203                 return "I40E_ERR_LINK_SETUP";
 204         case I40E_ERR_ADAPTER_STOPPED:
 205                 return "I40E_ERR_ADAPTER_STOPPED";
 206         case I40E_ERR_INVALID_MAC_ADDR:
 207                 return "I40E_ERR_INVALID_MAC_ADDR";
 208         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 209                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 210         case I40E_ERR_MASTER_REQUESTS_PENDING:
 211                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 212         case I40E_ERR_INVALID_LINK_SETTINGS:
 213                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 214         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 215                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 216         case I40E_ERR_RESET_FAILED:
 217                 return "I40E_ERR_RESET_FAILED";
 218         case I40E_ERR_SWFW_SYNC:
 219                 return "I40E_ERR_SWFW_SYNC";
 220         case I40E_ERR_NO_AVAILABLE_VSI:
 221                 return "I40E_ERR_NO_AVAILABLE_VSI";
 222         case I40E_ERR_NO_MEMORY:
 223                 return "I40E_ERR_NO_MEMORY";
 224         case I40E_ERR_BAD_PTR:
 225                 return "I40E_ERR_BAD_PTR";
 226         case I40E_ERR_RING_FULL:
 227                 return "I40E_ERR_RING_FULL";
 228         case I40E_ERR_INVALID_PD_ID:
 229                 return "I40E_ERR_INVALID_PD_ID";
 230         case I40E_ERR_INVALID_QP_ID:
 231                 return "I40E_ERR_INVALID_QP_ID";
 232         case I40E_ERR_INVALID_CQ_ID:
 233                 return "I40E_ERR_INVALID_CQ_ID";
 234         case I40E_ERR_INVALID_CEQ_ID:
 235                 return "I40E_ERR_INVALID_CEQ_ID";
 236         case I40E_ERR_INVALID_AEQ_ID:
 237                 return "I40E_ERR_INVALID_AEQ_ID";
 238         case I40E_ERR_INVALID_SIZE:
 239                 return "I40E_ERR_INVALID_SIZE";
 240         case I40E_ERR_INVALID_ARP_INDEX:
 241                 return "I40E_ERR_INVALID_ARP_INDEX";
 242         case I40E_ERR_INVALID_FPM_FUNC_ID:
 243                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 244         case I40E_ERR_QP_INVALID_MSG_SIZE:
 245                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 246         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 247                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 248         case I40E_ERR_INVALID_FRAG_COUNT:
 249                 return "I40E_ERR_INVALID_FRAG_COUNT";
 250         case I40E_ERR_QUEUE_EMPTY:
 251                 return "I40E_ERR_QUEUE_EMPTY";
 252         case I40E_ERR_INVALID_ALIGNMENT:
 253                 return "I40E_ERR_INVALID_ALIGNMENT";
 254         case I40E_ERR_FLUSHED_QUEUE:
 255                 return "I40E_ERR_FLUSHED_QUEUE";
 256         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 257                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 258         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 259                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 260         case I40E_ERR_TIMEOUT:
 261                 return "I40E_ERR_TIMEOUT";
 262         case I40E_ERR_OPCODE_MISMATCH:
 263                 return "I40E_ERR_OPCODE_MISMATCH";
 264         case I40E_ERR_CQP_COMPL_ERROR:
 265                 return "I40E_ERR_CQP_COMPL_ERROR";
 266         case I40E_ERR_INVALID_VF_ID:
 267                 return "I40E_ERR_INVALID_VF_ID";
 268         case I40E_ERR_INVALID_HMCFN_ID:
 269                 return "I40E_ERR_INVALID_HMCFN_ID";
 270         case I40E_ERR_BACKING_PAGE_ERROR:
 271                 return "I40E_ERR_BACKING_PAGE_ERROR";
 272         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 273                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 274         case I40E_ERR_INVALID_PBLE_INDEX:
 275                 return "I40E_ERR_INVALID_PBLE_INDEX";
 276         case I40E_ERR_INVALID_SD_INDEX:
 277                 return "I40E_ERR_INVALID_SD_INDEX";
 278         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 279                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 280         case I40E_ERR_INVALID_SD_TYPE:
 281                 return "I40E_ERR_INVALID_SD_TYPE";
 282         case I40E_ERR_MEMCPY_FAILED:
 283                 return "I40E_ERR_MEMCPY_FAILED";
 284         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 285                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 286         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 287                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 288         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 289                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 290         case I40E_ERR_SRQ_ENABLED:
 291                 return "I40E_ERR_SRQ_ENABLED";
 292         case I40E_ERR_ADMIN_QUEUE_ERROR:
 293                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 294         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 295                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 296         case I40E_ERR_BUF_TOO_SHORT:
 297                 return "I40E_ERR_BUF_TOO_SHORT";
 298         case I40E_ERR_ADMIN_QUEUE_FULL:
 299                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 300         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 301                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 302         case I40E_ERR_BAD_IWARP_CQE:
 303                 return "I40E_ERR_BAD_IWARP_CQE";
 304         case I40E_ERR_NVM_BLANK_MODE:
 305                 return "I40E_ERR_NVM_BLANK_MODE";
 306         case I40E_ERR_NOT_IMPLEMENTED:
 307                 return "I40E_ERR_NOT_IMPLEMENTED";
 308         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 309                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 310         case I40E_ERR_DIAG_TEST_FAILED:
 311                 return "I40E_ERR_DIAG_TEST_FAILED";
 312         case I40E_ERR_NOT_READY:
 313                 return "I40E_ERR_NOT_READY";
 314         case I40E_NOT_SUPPORTED:
 315                 return "I40E_NOT_SUPPORTED";
 316         case I40E_ERR_FIRMWARE_API_VERSION:
 317                 return "I40E_ERR_FIRMWARE_API_VERSION";
 318         }
 319
 320         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 321         return hw->err_str;
 322 }
 323
 324 #endif /* I40E_NDIS_SUPPORT */
 325 /**
 326  * i40e_debug_aq
 327  * @hw: debug mask related to admin queue
 328  * @mask: debug mask
 329  * @desc: pointer to admin queue descriptor
 330  * @buffer: pointer to command buffer
 331  * @buf_len: max length of buffer
 332  *
 333  * Dumps debug log about adminq command with descriptor contents.
 334  **/
 335 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 336                    void *buffer, u16 buf_len)
 337 {
 338         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 339         u16 len = LE16_TO_CPU(aq_desc->datalen);
 340         u8 *buf = (u8 *)buffer;
 341         u16 i = 0;
 342
 343         if ((!(mask & hw->debug_mask)) || (desc == NULL))
 344                 return;
 345
 346         i40e_debug(hw, mask,
 347                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 348                    LE16_TO_CPU(aq_desc->opcode),
 349                    LE16_TO_CPU(aq_desc->flags),
 350                    LE16_TO_CPU(aq_desc->datalen),
 351                    LE16_TO_CPU(aq_desc->retval));
 352         i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
 353                    LE32_TO_CPU(aq_desc->cookie_high),
 354                    LE32_TO_CPU(aq_desc->cookie_low));
 355         i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
 356                    LE32_TO_CPU(aq_desc->params.internal.param0),
 357                    LE32_TO_CPU(aq_desc->params.internal.param1));
 358         i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
 359                    LE32_TO_CPU(aq_desc->params.external.addr_high),
 360                    LE32_TO_CPU(aq_desc->params.external.addr_low));
 361
 362         if ((buffer != NULL) && (aq_desc->datalen != 0)) {
 363                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 364                 if (buf_len < len)
 365                         len = buf_len;
 366                 /* write the full 16-byte chunks */
 367                 for (i = 0; i < (len - 16); i += 16)
 368                         i40e_debug(hw, mask,
 369                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 370                                    i, buf[i], buf[i+1], buf[i+2], buf[i+3],
 371                                    buf[i+4], buf[i+5], buf[i+6], buf[i+7],
 372                                    buf[i+8], buf[i+9], buf[i+10], buf[i+11],
 373                                    buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
 374                 /* the most we could have left is 16 bytes, pad with zeros */
 375                 if (i < len) {
 376                         char d_buf[16];
 377                         int j, i_sav;
 378
 379                         i_sav = i;
 380                         memset(d_buf, 0, sizeof(d_buf));
 381                         for (j = 0; i < len; j++, i++)
 382                                 d_buf[j] = buf[i];
 383                         i40e_debug(hw, mask,
 384                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 385                                    i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
 386                                    d_buf[4], d_buf[5], d_buf[6], d_buf[7],
 387                                    d_buf[8], d_buf[9], d_buf[10], d_buf[11],
 388                                    d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
 389                 }
 390         }
 391 }
 392
 393 /**
 394  * i40e_check_asq_alive
 395  * @hw: pointer to the hw struct
 396  *
 397  * Returns true if Queue is enabled else false.
 398  **/
 399 bool i40e_check_asq_alive(struct i40e_hw *hw)
 400 {
 401         if (hw->aq.asq.len)
 402 #ifdef PF_DRIVER
 403 #ifdef INTEGRATED_VF
 404                 if (!i40e_is_vf(hw))
 405                         return !!(rd32(hw, hw->aq.asq.len) &
 406                                 I40E_PF_ATQLEN_ATQENABLE_MASK);
 407 #else
 408                 return !!(rd32(hw, hw->aq.asq.len) &
 409                         I40E_PF_ATQLEN_ATQENABLE_MASK);
 410 #endif /* INTEGRATED_VF */
 411 #endif /* PF_DRIVER */
 412 #ifdef VF_DRIVER
 413 #ifdef INTEGRATED_VF
 414                 if (i40e_is_vf(hw))
 415                         return !!(rd32(hw, hw->aq.asq.len) &
 416                                 I40E_VF_ATQLEN1_ATQENABLE_MASK);
 417 #else
 418                 return !!(rd32(hw, hw->aq.asq.len) &
 419                         I40E_VF_ATQLEN1_ATQENABLE_MASK);
 420 #endif /* INTEGRATED_VF */
 421 #endif /* VF_DRIVER */
 422         return false;
 423 }
 424
 425 /**
 426  * i40e_aq_queue_shutdown
 427  * @hw: pointer to the hw struct
 428  * @unloading: is the driver unloading itself
 429  *
 430  * Tell the Firmware that we're shutting down the AdminQ and whether
 431  * or not the driver is unloading as well.
 432  **/
 433 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
 434                                              bool unloading)
 435 {
 436         struct i40e_aq_desc desc;
 437         struct i40e_aqc_queue_shutdown *cmd =
 438                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 439         enum i40e_status_code status;
 440
 441         i40e_fill_default_direct_cmd_desc(&desc,
 442                                           i40e_aqc_opc_queue_shutdown);
 443
 444         if (unloading)
 445                 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
 446         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 447
 448         return status;
 449 }
 450 #ifdef X722_SUPPORT
 451
 452 /**
 453  * i40e_aq_get_set_rss_lut
 454  * @hw: pointer to the hardware structure
 455  * @vsi_id: vsi fw index
 456  * @pf_lut: for PF table set true, for VSI table set false
 457  * @lut: pointer to the lut buffer provided by the caller
 458  * @lut_size: size of the lut buffer
 459  * @set: set true to set the table, false to get the table
 460  *
 461  * Internal function to get or set RSS look up table
 462  **/
 463 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 464                                                      u16 vsi_id, bool pf_lut,
 465                                                      u8 *lut, u16 lut_size,
 466                                                      bool set)
 467 {
 468         enum i40e_status_code status;
 469         struct i40e_aq_desc desc;
 470         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 471                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 472
 473         if (set)
 474                 i40e_fill_default_direct_cmd_desc(&desc,
 475                                                   i40e_aqc_opc_set_rss_lut);
 476         else
 477                 i40e_fill_default_direct_cmd_desc(&desc,
 478                                                   i40e_aqc_opc_get_rss_lut);
 479
 480         /* Indirect command */
 481         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 482         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 483
 484         cmd_resp->vsi_id =
 485                         CPU_TO_LE16((u16)((vsi_id <<
 486                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 487                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 488         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 489
 490         if (pf_lut)
 491                 cmd_resp->flags |= CPU_TO_LE16((u16)
 492                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 493                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 494                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 495         else
 496                 cmd_resp->flags |= CPU_TO_LE16((u16)
 497                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 498                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 499                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 500
 501         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 502
 503         return status;
 504 }
 505
 506 /**
 507  * i40e_aq_get_rss_lut
 508  * @hw: pointer to the hardware structure
 509  * @vsi_id: vsi fw index
 510  * @pf_lut: for PF table set true, for VSI table set false
 511  * @lut: pointer to the lut buffer provided by the caller
 512  * @lut_size: size of the lut buffer
 513  *
 514  * get the RSS lookup table, PF or VSI type
 515  **/
 516 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 517                                           bool pf_lut, u8 *lut, u16 lut_size)
 518 {
 519         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 520                                        false);
 521 }
 522
 523 /**
 524  * i40e_aq_set_rss_lut
 525  * @hw: pointer to the hardware structure
 526  * @vsi_id: vsi fw index
 527  * @pf_lut: for PF table set true, for VSI table set false
 528  * @lut: pointer to the lut buffer provided by the caller
 529  * @lut_size: size of the lut buffer
 530  *
 531  * set the RSS lookup table, PF or VSI type
 532  **/
 533 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 534                                           bool pf_lut, u8 *lut, u16 lut_size)
 535 {
 536         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
 537 }
 538
 539 /**
 540  * i40e_aq_get_set_rss_key
 541  * @hw: pointer to the hw struct
 542  * @vsi_id: vsi fw index
 543  * @key: pointer to key info struct
 544  * @set: set true to set the key, false to get the key
 545  *
 546  * get the RSS key per VSI
 547  **/
 548 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 549                                       u16 vsi_id,
 550                                       struct i40e_aqc_get_set_rss_key_data *key,
 551                                       bool set)
 552 {
 553         enum i40e_status_code status;
 554         struct i40e_aq_desc desc;
 555         struct i40e_aqc_get_set_rss_key *cmd_resp =
 556                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 557         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 558
 559         if (set)
 560                 i40e_fill_default_direct_cmd_desc(&desc,
 561                                                   i40e_aqc_opc_set_rss_key);
 562         else
 563                 i40e_fill_default_direct_cmd_desc(&desc,
 564                                                   i40e_aqc_opc_get_rss_key);
 565
 566         /* Indirect command */
 567         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 568         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 569
 570         cmd_resp->vsi_id =
 571                         CPU_TO_LE16((u16)((vsi_id <<
 572                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 573                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 574         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 575
 576         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 577
 578         return status;
 579 }
 580
 581 /**
 582  * i40e_aq_get_rss_key
 583  * @hw: pointer to the hw struct
 584  * @vsi_id: vsi fw index
 585  * @key: pointer to key info struct
 586  *
 587  **/
 588 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
 589                                       u16 vsi_id,
 590                                       struct i40e_aqc_get_set_rss_key_data *key)
 591 {
 592         return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
 593 }
 594
 595 /**
 596  * i40e_aq_set_rss_key
 597  * @hw: pointer to the hw struct
 598  * @vsi_id: vsi fw index
 599  * @key: pointer to key info struct
 600  *
 601  * set the RSS key per VSI
 602  **/
 603 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
 604                                       u16 vsi_id,
 605                                       struct i40e_aqc_get_set_rss_key_data *key)
 606 {
 607         return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
 608 }
 609 #endif /* X722_SUPPORT */
 610
 611 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 612  * hardware to a bit-field that can be used by SW to more easily determine the
 613  * packet type.
 614  *
 615  * Macros are used to shorten the table lines and make this table human
 616  * readable.
 617  *
 618  * We store the PTYPE in the top byte of the bit field - this is just so that
 619  * we can check that the table doesn't have a row missing, as the index into
 620  * the table should be the PTYPE.
 621  *
 622  * Typical work flow:
 623  *
 624  * IF NOT i40e_ptype_lookup[ptype].known
 625  * THEN
 626  *      Packet is unknown
 627  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 628  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 629  * ELSE
 630  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 631  * ENDIF
 632  */
 633
 634 /* macro to make the table lines short */
 635 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 636         {       PTYPE, \
 637                 1, \
 638                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 639                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 640                 I40E_RX_PTYPE_##OUTER_FRAG, \
 641                 I40E_RX_PTYPE_TUNNEL_##T, \
 642                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 643                 I40E_RX_PTYPE_##TEF, \
 644                 I40E_RX_PTYPE_INNER_PROT_##I, \
 645                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 646
 647 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 648                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 649
 650 /* shorter macros makes the table fit but are terse */
 651 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 652 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 653 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 654
 655 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 656 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 657         /* L2 Packet types */
 658         I40E_PTT_UNUSED_ENTRY(0),
 659         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 660         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 661         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 662         I40E_PTT_UNUSED_ENTRY(4),
 663         I40E_PTT_UNUSED_ENTRY(5),
 664         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 665         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 666         I40E_PTT_UNUSED_ENTRY(8),
 667         I40E_PTT_UNUSED_ENTRY(9),
 668         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 669         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 670         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 671         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 672         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 673         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 674         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 675         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 676         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 677         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 678         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 679         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 680
 681         /* Non Tunneled IPv4 */
 682         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 683         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 684         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 685         I40E_PTT_UNUSED_ENTRY(25),
 686         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 687         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 688         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 689
 690         /* IPv4 --> IPv4 */
 691         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 692         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 693         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 694         I40E_PTT_UNUSED_ENTRY(32),
 695         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 696         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 697         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 698
 699         /* IPv4 --> IPv6 */
 700         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 701         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 702         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 703         I40E_PTT_UNUSED_ENTRY(39),
 704         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 705         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 706         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 707
 708         /* IPv4 --> GRE/NAT */
 709         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 710
 711         /* IPv4 --> GRE/NAT --> IPv4 */
 712         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 713         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 714         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 715         I40E_PTT_UNUSED_ENTRY(47),
 716         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 717         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 718         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 719
 720         /* IPv4 --> GRE/NAT --> IPv6 */
 721         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 722         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 723         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 724         I40E_PTT_UNUSED_ENTRY(54),
 725         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 726         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 727         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 728
 729         /* IPv4 --> GRE/NAT --> MAC */
 730         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 731
 732         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 733         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 734         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 735         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 736         I40E_PTT_UNUSED_ENTRY(62),
 737         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 738         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 739         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 740
 741         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 742         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 743         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 744         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 745         I40E_PTT_UNUSED_ENTRY(69),
 746         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 747         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 748         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 749
 750         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 751         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 752
 753         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 754         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 755         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 756         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 757         I40E_PTT_UNUSED_ENTRY(77),
 758         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 759         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 760         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 761
 762         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 763         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 764         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 765         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 766         I40E_PTT_UNUSED_ENTRY(84),
 767         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 768         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 769         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 770
 771         /* Non Tunneled IPv6 */
 772         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 773         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 774         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
 775         I40E_PTT_UNUSED_ENTRY(91),
 776         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 777         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 778         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 779
 780         /* IPv6 --> IPv4 */
 781         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 782         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 783         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 784         I40E_PTT_UNUSED_ENTRY(98),
 785         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 786         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 787         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 788
 789         /* IPv6 --> IPv6 */
 790         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 791         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 792         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 793         I40E_PTT_UNUSED_ENTRY(105),
 794         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 795         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 796         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 797
 798         /* IPv6 --> GRE/NAT */
 799         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 800
 801         /* IPv6 --> GRE/NAT -> IPv4 */
 802         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 803         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 804         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 805         I40E_PTT_UNUSED_ENTRY(113),
 806         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 807         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 808         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 809
 810         /* IPv6 --> GRE/NAT -> IPv6 */
 811         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 812         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 813         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 814         I40E_PTT_UNUSED_ENTRY(120),
 815         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 816         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 817         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 818
 819         /* IPv6 --> GRE/NAT -> MAC */
 820         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 821
 822         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 823         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 824         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 825         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 826         I40E_PTT_UNUSED_ENTRY(128),
 827         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 828         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 829         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 830
 831         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 832         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 833         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 834         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 835         I40E_PTT_UNUSED_ENTRY(135),
 836         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 837         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 838         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 839
 840         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 841         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 842
 843         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 844         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 845         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 846         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 847         I40E_PTT_UNUSED_ENTRY(143),
 848         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 849         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 850         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 851
 852         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 853         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 854         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 855         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 856         I40E_PTT_UNUSED_ENTRY(150),
 857         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 858         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 859         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 860
 861         /* unused entries */
 862         I40E_PTT_UNUSED_ENTRY(154),
 863         I40E_PTT_UNUSED_ENTRY(155),
 864         I40E_PTT_UNUSED_ENTRY(156),
 865         I40E_PTT_UNUSED_ENTRY(157),
 866         I40E_PTT_UNUSED_ENTRY(158),
 867         I40E_PTT_UNUSED_ENTRY(159),
 868
 869         I40E_PTT_UNUSED_ENTRY(160),
 870         I40E_PTT_UNUSED_ENTRY(161),
 871         I40E_PTT_UNUSED_ENTRY(162),
 872         I40E_PTT_UNUSED_ENTRY(163),
 873         I40E_PTT_UNUSED_ENTRY(164),
 874         I40E_PTT_UNUSED_ENTRY(165),
 875         I40E_PTT_UNUSED_ENTRY(166),
 876         I40E_PTT_UNUSED_ENTRY(167),
 877         I40E_PTT_UNUSED_ENTRY(168),
 878         I40E_PTT_UNUSED_ENTRY(169),
 879
 880         I40E_PTT_UNUSED_ENTRY(170),
 881         I40E_PTT_UNUSED_ENTRY(171),
 882         I40E_PTT_UNUSED_ENTRY(172),
 883         I40E_PTT_UNUSED_ENTRY(173),
 884         I40E_PTT_UNUSED_ENTRY(174),
 885         I40E_PTT_UNUSED_ENTRY(175),
 886         I40E_PTT_UNUSED_ENTRY(176),
 887         I40E_PTT_UNUSED_ENTRY(177),
 888         I40E_PTT_UNUSED_ENTRY(178),
 889         I40E_PTT_UNUSED_ENTRY(179),
 890
 891         I40E_PTT_UNUSED_ENTRY(180),
 892         I40E_PTT_UNUSED_ENTRY(181),
 893         I40E_PTT_UNUSED_ENTRY(182),
 894         I40E_PTT_UNUSED_ENTRY(183),
 895         I40E_PTT_UNUSED_ENTRY(184),
 896         I40E_PTT_UNUSED_ENTRY(185),
 897         I40E_PTT_UNUSED_ENTRY(186),
 898         I40E_PTT_UNUSED_ENTRY(187),
 899         I40E_PTT_UNUSED_ENTRY(188),
 900         I40E_PTT_UNUSED_ENTRY(189),
 901
 902         I40E_PTT_UNUSED_ENTRY(190),
 903         I40E_PTT_UNUSED_ENTRY(191),
 904         I40E_PTT_UNUSED_ENTRY(192),
 905         I40E_PTT_UNUSED_ENTRY(193),
 906         I40E_PTT_UNUSED_ENTRY(194),
 907         I40E_PTT_UNUSED_ENTRY(195),
 908         I40E_PTT_UNUSED_ENTRY(196),
 909         I40E_PTT_UNUSED_ENTRY(197),
 910         I40E_PTT_UNUSED_ENTRY(198),
 911         I40E_PTT_UNUSED_ENTRY(199),
 912
 913         I40E_PTT_UNUSED_ENTRY(200),
 914         I40E_PTT_UNUSED_ENTRY(201),
 915         I40E_PTT_UNUSED_ENTRY(202),
 916         I40E_PTT_UNUSED_ENTRY(203),
 917         I40E_PTT_UNUSED_ENTRY(204),
 918         I40E_PTT_UNUSED_ENTRY(205),
 919         I40E_PTT_UNUSED_ENTRY(206),
 920         I40E_PTT_UNUSED_ENTRY(207),
 921         I40E_PTT_UNUSED_ENTRY(208),
 922         I40E_PTT_UNUSED_ENTRY(209),
 923
 924         I40E_PTT_UNUSED_ENTRY(210),
 925         I40E_PTT_UNUSED_ENTRY(211),
 926         I40E_PTT_UNUSED_ENTRY(212),
 927         I40E_PTT_UNUSED_ENTRY(213),
 928         I40E_PTT_UNUSED_ENTRY(214),
 929         I40E_PTT_UNUSED_ENTRY(215),
 930         I40E_PTT_UNUSED_ENTRY(216),
 931         I40E_PTT_UNUSED_ENTRY(217),
 932         I40E_PTT_UNUSED_ENTRY(218),
 933         I40E_PTT_UNUSED_ENTRY(219),
 934
 935         I40E_PTT_UNUSED_ENTRY(220),
 936         I40E_PTT_UNUSED_ENTRY(221),
 937         I40E_PTT_UNUSED_ENTRY(222),
 938         I40E_PTT_UNUSED_ENTRY(223),
 939         I40E_PTT_UNUSED_ENTRY(224),
 940         I40E_PTT_UNUSED_ENTRY(225),
 941         I40E_PTT_UNUSED_ENTRY(226),
 942         I40E_PTT_UNUSED_ENTRY(227),
 943         I40E_PTT_UNUSED_ENTRY(228),
 944         I40E_PTT_UNUSED_ENTRY(229),
 945
 946         I40E_PTT_UNUSED_ENTRY(230),
 947         I40E_PTT_UNUSED_ENTRY(231),
 948         I40E_PTT_UNUSED_ENTRY(232),
 949         I40E_PTT_UNUSED_ENTRY(233),
 950         I40E_PTT_UNUSED_ENTRY(234),
 951         I40E_PTT_UNUSED_ENTRY(235),
 952         I40E_PTT_UNUSED_ENTRY(236),
 953         I40E_PTT_UNUSED_ENTRY(237),
 954         I40E_PTT_UNUSED_ENTRY(238),
 955         I40E_PTT_UNUSED_ENTRY(239),
 956
 957         I40E_PTT_UNUSED_ENTRY(240),
 958         I40E_PTT_UNUSED_ENTRY(241),
 959         I40E_PTT_UNUSED_ENTRY(242),
 960         I40E_PTT_UNUSED_ENTRY(243),
 961         I40E_PTT_UNUSED_ENTRY(244),
 962         I40E_PTT_UNUSED_ENTRY(245),
 963         I40E_PTT_UNUSED_ENTRY(246),
 964         I40E_PTT_UNUSED_ENTRY(247),
 965         I40E_PTT_UNUSED_ENTRY(248),
 966         I40E_PTT_UNUSED_ENTRY(249),
 967
 968         I40E_PTT_UNUSED_ENTRY(250),
 969         I40E_PTT_UNUSED_ENTRY(251),
 970         I40E_PTT_UNUSED_ENTRY(252),
 971         I40E_PTT_UNUSED_ENTRY(253),
 972         I40E_PTT_UNUSED_ENTRY(254),
 973         I40E_PTT_UNUSED_ENTRY(255)
 974 };
 975
 976
 977 /**
 978  * i40e_validate_mac_addr - Validate unicast MAC address
 979  * @mac_addr: pointer to MAC address
 980  *
 981  * Tests a MAC address to ensure it is a valid Individual Address
 982  **/
 983 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
 984 {
 985         enum i40e_status_code status = I40E_SUCCESS;
 986
 987         DEBUGFUNC("i40e_validate_mac_addr");
 988
 989         /* Broadcast addresses ARE multicast addresses
 990          * Make sure it is not a multicast address
 991          * Reject the zero address
 992          */
 993         if (I40E_IS_MULTICAST(mac_addr) ||
 994             (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
 995               mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
 996                 status = I40E_ERR_INVALID_MAC_ADDR;
 997
 998         return status;
 999 }
1000 #ifdef PF_DRIVER
1001
1002 /**
1003  * i40e_init_shared_code - Initialize the shared code
1004  * @hw: pointer to hardware structure
1005  *
1006  * This assigns the MAC type and PHY code and inits the NVM.
1007  * Does not touch the hardware. This function must be called prior to any
1008  * other function in the shared code. The i40e_hw structure should be
1009  * memset to 0 prior to calling this function.  The following fields in
1010  * hw structure should be filled in prior to calling this function:
1011  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1012  * subsystem_vendor_id, and revision_id
1013  **/
1014 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
1015 {
1016         enum i40e_status_code status = I40E_SUCCESS;
1017         u32 port, ari, func_rid;
1018
1019         DEBUGFUNC("i40e_init_shared_code");
1020
1021         i40e_set_mac_type(hw);
1022
1023         switch (hw->mac.type) {
1024         case I40E_MAC_XL710:
1025 #ifdef X722_SUPPORT
1026         case I40E_MAC_X722:
1027 #endif
1028                 break;
1029         default:
1030                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1031         }
1032
1033         hw->phy.get_link_info = true;
1034
1035         /* Determine port number and PF number*/
1036         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1037                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1038         hw->port = (u8)port;
1039         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1040                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1041         func_rid = rd32(hw, I40E_PF_FUNC_RID);
1042         if (ari)
1043                 hw->pf_id = (u8)(func_rid & 0xff);
1044         else
1045                 hw->pf_id = (u8)(func_rid & 0x7);
1046
1047 #ifdef X722_SUPPORT
1048         if (hw->mac.type == I40E_MAC_X722)
1049                 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
1050
1051 #endif
1052         status = i40e_init_nvm(hw);
1053         return status;
1054 }
1055
1056 /**
1057  * i40e_aq_mac_address_read - Retrieve the MAC addresses
1058  * @hw: pointer to the hw struct
1059  * @flags: a return indicator of what addresses were added to the addr store
1060  * @addrs: the requestor's mac addr store
1061  * @cmd_details: pointer to command details structure or NULL
1062  **/
1063 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1064                                    u16 *flags,
1065                                    struct i40e_aqc_mac_address_read_data *addrs,
1066                                    struct i40e_asq_cmd_details *cmd_details)
1067 {
1068         struct i40e_aq_desc desc;
1069         struct i40e_aqc_mac_address_read *cmd_data =
1070                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1071         enum i40e_status_code status;
1072
1073         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1074         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1075
1076         status = i40e_asq_send_command(hw, &desc, addrs,
1077                                        sizeof(*addrs), cmd_details);
1078         *flags = LE16_TO_CPU(cmd_data->command_flags);
1079
1080         return status;
1081 }
1082
1083 /**
1084  * i40e_aq_mac_address_write - Change the MAC addresses
1085  * @hw: pointer to the hw struct
1086  * @flags: indicates which MAC to be written
1087  * @mac_addr: address to write
1088  * @cmd_details: pointer to command details structure or NULL
1089  **/
1090 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1091                                     u16 flags, u8 *mac_addr,
1092                                     struct i40e_asq_cmd_details *cmd_details)
1093 {
1094         struct i40e_aq_desc desc;
1095         struct i40e_aqc_mac_address_write *cmd_data =
1096                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1097         enum i40e_status_code status;
1098
1099         i40e_fill_default_direct_cmd_desc(&desc,
1100                                           i40e_aqc_opc_mac_address_write);
1101         cmd_data->command_flags = CPU_TO_LE16(flags);
1102         cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1103         cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1104                                         ((u32)mac_addr[3] << 16) |
1105                                         ((u32)mac_addr[4] << 8) |
1106                                         mac_addr[5]);
1107
1108         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1109
1110         return status;
1111 }
1112
1113 /**
1114  * i40e_get_mac_addr - get MAC address
1115  * @hw: pointer to the HW structure
1116  * @mac_addr: pointer to MAC address
1117  *
1118  * Reads the adapter's MAC address from register
1119  **/
1120 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1121 {
1122         struct i40e_aqc_mac_address_read_data addrs;
1123         enum i40e_status_code status;
1124         u16 flags = 0;
1125
1126         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1127
1128         if (flags & I40E_AQC_LAN_ADDR_VALID)
1129                 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
1130
1131         return status;
1132 }
1133
1134 /**
1135  * i40e_get_port_mac_addr - get Port MAC address
1136  * @hw: pointer to the HW structure
1137  * @mac_addr: pointer to Port MAC address
1138  *
1139  * Reads the adapter's Port MAC address
1140  **/
1141 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1142 {
1143         struct i40e_aqc_mac_address_read_data addrs;
1144         enum i40e_status_code status;
1145         u16 flags = 0;
1146
1147         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1148         if (status)
1149                 return status;
1150
1151         if (flags & I40E_AQC_PORT_ADDR_VALID)
1152                 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
1153         else
1154                 status = I40E_ERR_INVALID_MAC_ADDR;
1155
1156         return status;
1157 }
1158
1159 /**
1160  * i40e_pre_tx_queue_cfg - pre tx queue configure
1161  * @hw: pointer to the HW structure
1162  * @queue: target pf queue index
1163  * @enable: state change request
1164  *
1165  * Handles hw requirement to indicate intention to enable
1166  * or disable target queue.
1167  **/
1168 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1169 {
1170         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1171         u32 reg_block = 0;
1172         u32 reg_val;
1173
1174         if (abs_queue_idx >= 128) {
1175                 reg_block = abs_queue_idx / 128;
1176                 abs_queue_idx %= 128;
1177         }
1178
1179         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1180         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1181         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1182
1183         if (enable)
1184                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1185         else
1186                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1187
1188         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1189 }
1190
1191 /**
1192  * i40e_get_san_mac_addr - get SAN MAC address
1193  * @hw: pointer to the HW structure
1194  * @mac_addr: pointer to SAN MAC address
1195  *
1196  * Reads the adapter's SAN MAC address from NVM
1197  **/
1198 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1199                                             u8 *mac_addr)
1200 {
1201         struct i40e_aqc_mac_address_read_data addrs;
1202         enum i40e_status_code status;
1203         u16 flags = 0;
1204
1205         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1206         if (status)
1207                 return status;
1208
1209         if (flags & I40E_AQC_SAN_ADDR_VALID)
1210                 memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac));
1211         else
1212                 status = I40E_ERR_INVALID_MAC_ADDR;
1213
1214         return status;
1215 }
1216
1217 /**
1218  *  i40e_read_pba_string - Reads part number string from EEPROM
1219  *  @hw: pointer to hardware structure
1220  *  @pba_num: stores the part number string from the EEPROM
1221  *  @pba_num_size: part number string buffer length
1222  *
1223  *  Reads the part number string from the EEPROM.
1224  **/
1225 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1226                                             u32 pba_num_size)
1227 {
1228         enum i40e_status_code status = I40E_SUCCESS;
1229         u16 pba_word = 0;
1230         u16 pba_size = 0;
1231         u16 pba_ptr = 0;
1232         u16 i = 0;
1233
1234         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1235         if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1236                 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1237                 return status;
1238         }
1239
1240         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1241         if (status != I40E_SUCCESS) {
1242                 DEBUGOUT("Failed to read PBA Block pointer.\n");
1243                 return status;
1244         }
1245
1246         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1247         if (status != I40E_SUCCESS) {
1248                 DEBUGOUT("Failed to read PBA Block size.\n");
1249                 return status;
1250         }
1251
1252         /* Subtract one to get PBA word count (PBA Size word is included in
1253          * total size)
1254          */
1255         pba_size--;
1256         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1257                 DEBUGOUT("Buffer to small for PBA data.\n");
1258                 return I40E_ERR_PARAM;
1259         }
1260
1261         for (i = 0; i < pba_size; i++) {
1262                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1263                 if (status != I40E_SUCCESS) {
1264                         DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1265                         return status;
1266                 }
1267
1268                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1269                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1270         }
1271         pba_num[(pba_size * 2)] = '\0';
1272
1273         return status;
1274 }
1275
1276 /**
1277  * i40e_get_media_type - Gets media type
1278  * @hw: pointer to the hardware structure
1279  **/
1280 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1281 {
1282         enum i40e_media_type media;
1283
1284         switch (hw->phy.link_info.phy_type) {
1285         case I40E_PHY_TYPE_10GBASE_SR:
1286         case I40E_PHY_TYPE_10GBASE_LR:
1287         case I40E_PHY_TYPE_1000BASE_SX:
1288         case I40E_PHY_TYPE_1000BASE_LX:
1289         case I40E_PHY_TYPE_40GBASE_SR4:
1290         case I40E_PHY_TYPE_40GBASE_LR4:
1291                 media = I40E_MEDIA_TYPE_FIBER;
1292                 break;
1293         case I40E_PHY_TYPE_100BASE_TX:
1294         case I40E_PHY_TYPE_1000BASE_T:
1295         case I40E_PHY_TYPE_10GBASE_T:
1296                 media = I40E_MEDIA_TYPE_BASET;
1297                 break;
1298         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1299         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1300         case I40E_PHY_TYPE_10GBASE_CR1:
1301         case I40E_PHY_TYPE_40GBASE_CR4:
1302         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1303         case I40E_PHY_TYPE_40GBASE_AOC:
1304         case I40E_PHY_TYPE_10GBASE_AOC:
1305                 media = I40E_MEDIA_TYPE_DA;
1306                 break;
1307         case I40E_PHY_TYPE_1000BASE_KX:
1308         case I40E_PHY_TYPE_10GBASE_KX4:
1309         case I40E_PHY_TYPE_10GBASE_KR:
1310         case I40E_PHY_TYPE_40GBASE_KR4:
1311         case I40E_PHY_TYPE_20GBASE_KR2:
1312                 media = I40E_MEDIA_TYPE_BACKPLANE;
1313                 break;
1314         case I40E_PHY_TYPE_SGMII:
1315         case I40E_PHY_TYPE_XAUI:
1316         case I40E_PHY_TYPE_XFI:
1317         case I40E_PHY_TYPE_XLAUI:
1318         case I40E_PHY_TYPE_XLPPI:
1319         default:
1320                 media = I40E_MEDIA_TYPE_UNKNOWN;
1321                 break;
1322         }
1323
1324         return media;
1325 }
1326
1327 #define I40E_PF_RESET_WAIT_COUNT        200
1328 /**
1329  * i40e_pf_reset - Reset the PF
1330  * @hw: pointer to the hardware structure
1331  *
1332  * Assuming someone else has triggered a global reset,
1333  * assure the global reset is complete and then reset the PF
1334  **/
1335 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1336 {
1337         u32 cnt = 0;
1338         u32 cnt1 = 0;
1339         u32 reg = 0;
1340         u32 grst_del;
1341
1342         /* Poll for Global Reset steady state in case of recent GRST.
1343          * The grst delay value is in 100ms units, and we'll wait a
1344          * couple counts longer to be sure we don't just miss the end.
1345          */
1346         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1347                         I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1348                         I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1349
1350         grst_del = grst_del * 20;
1351
1352         for (cnt = 0; cnt < grst_del; cnt++) {
1353                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1354                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1355                         break;
1356                 i40e_msec_delay(100);
1357         }
1358         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1359                 DEBUGOUT("Global reset polling failed to complete.\n");
1360                 return I40E_ERR_RESET_FAILED;
1361         }
1362
1363         /* Now Wait for the FW to be ready */
1364         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1365                 reg = rd32(hw, I40E_GLNVM_ULD);
1366                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1367                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1368                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1369                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1370                         DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1371                         break;
1372                 }
1373                 i40e_msec_delay(10);
1374         }
1375         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1376                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1377                 DEBUGOUT("wait for FW Reset complete timedout\n");
1378                 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1379                 return I40E_ERR_RESET_FAILED;
1380         }
1381
1382         /* If there was a Global Reset in progress when we got here,
1383          * we don't need to do the PF Reset
1384          */
1385         if (!cnt) {
1386                 reg = rd32(hw, I40E_PFGEN_CTRL);
1387                 wr32(hw, I40E_PFGEN_CTRL,
1388                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1389                 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1390                         reg = rd32(hw, I40E_PFGEN_CTRL);
1391                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1392                                 break;
1393                         i40e_msec_delay(1);
1394                 }
1395                 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1396                         DEBUGOUT("PF reset polling failed to complete.\n");
1397                         return I40E_ERR_RESET_FAILED;
1398                 }
1399         }
1400
1401         i40e_clear_pxe_mode(hw);
1402
1403
1404         return I40E_SUCCESS;
1405 }
1406
1407 /**
1408  * i40e_clear_hw - clear out any left over hw state
1409  * @hw: pointer to the hw struct
1410  *
1411  * Clear queues and interrupts, typically called at init time,
1412  * but after the capabilities have been found so we know how many
1413  * queues and msix vectors have been allocated.
1414  **/
1415 void i40e_clear_hw(struct i40e_hw *hw)
1416 {
1417         u32 num_queues, base_queue;
1418         u32 num_pf_int;
1419         u32 num_vf_int;
1420         u32 num_vfs;
1421         u32 i, j;
1422         u32 val;
1423         u32 eol = 0x7ff;
1424
1425         /* get number of interrupts, queues, and vfs */
1426         val = rd32(hw, I40E_GLPCI_CNF2);
1427         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1428                         I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1429         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1430                         I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1431
1432         val = rd32(hw, I40E_PFLAN_QALLOC);
1433         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1434                         I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1435         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1436                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1437         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1438                 num_queues = (j - base_queue) + 1;
1439         else
1440                 num_queues = 0;
1441
1442         val = rd32(hw, I40E_PF_VT_PFALLOC);
1443         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1444                         I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1445         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1446                         I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1447         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1448                 num_vfs = (j - i) + 1;
1449         else
1450                 num_vfs = 0;
1451
1452         /* stop all the interrupts */
1453         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1454         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1455         for (i = 0; i < num_pf_int - 2; i++)
1456                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1457
1458         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1459         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1460         wr32(hw, I40E_PFINT_LNKLST0, val);
1461         for (i = 0; i < num_pf_int - 2; i++)
1462                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1463         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1464         for (i = 0; i < num_vfs; i++)
1465                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1466         for (i = 0; i < num_vf_int - 2; i++)
1467                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1468
1469         /* warn the HW of the coming Tx disables */
1470         for (i = 0; i < num_queues; i++) {
1471                 u32 abs_queue_idx = base_queue + i;
1472                 u32 reg_block = 0;
1473
1474                 if (abs_queue_idx >= 128) {
1475                         reg_block = abs_queue_idx / 128;
1476                         abs_queue_idx %= 128;
1477                 }
1478
1479                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1480                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1481                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1482                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1483
1484                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1485         }
1486         i40e_usec_delay(400);
1487
1488         /* stop all the queues */
1489         for (i = 0; i < num_queues; i++) {
1490                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1491                 wr32(hw, I40E_QTX_ENA(i), 0);
1492                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1493                 wr32(hw, I40E_QRX_ENA(i), 0);
1494         }
1495
1496         /* short wait for all queue disables to settle */
1497         i40e_usec_delay(50);
1498 }
1499
1500 /**
1501  * i40e_clear_pxe_mode - clear pxe operations mode
1502  * @hw: pointer to the hw struct
1503  *
1504  * Make sure all PXE mode settings are cleared, including things
1505  * like descriptor fetch/write-back mode.
1506  **/
1507 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1508 {
1509         if (i40e_check_asq_alive(hw))
1510                 i40e_aq_clear_pxe_mode(hw, NULL);
1511 }
1512
1513 /**
1514  * i40e_led_is_mine - helper to find matching led
1515  * @hw: pointer to the hw struct
1516  * @idx: index into GPIO registers
1517  *
1518  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1519  */
1520 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1521 {
1522         u32 gpio_val = 0;
1523         u32 port;
1524
1525         if (!hw->func_caps.led[idx])
1526                 return 0;
1527
1528         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1529         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1530                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1531
1532         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1533          * if it is not our port then ignore
1534          */
1535         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1536             (port != hw->port))
1537                 return 0;
1538
1539         return gpio_val;
1540 }
1541
1542 #define I40E_COMBINED_ACTIVITY 0xA
1543 #define I40E_FILTER_ACTIVITY 0xE
1544 #define I40E_LINK_ACTIVITY 0xC
1545 #define I40E_MAC_ACTIVITY 0xD
1546 #define I40E_LED0 22
1547
1548 /**
1549  * i40e_led_get - return current on/off mode
1550  * @hw: pointer to the hw struct
1551  *
1552  * The value returned is the 'mode' field as defined in the
1553  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1554  * values are variations of possible behaviors relating to
1555  * blink, link, and wire.
1556  **/
1557 u32 i40e_led_get(struct i40e_hw *hw)
1558 {
1559         u32 current_mode = 0;
1560         u32 mode = 0;
1561         int i;
1562
1563         /* as per the documentation GPIO 22-29 are the LED
1564          * GPIO pins named LED0..LED7
1565          */
1566         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1567                 u32 gpio_val = i40e_led_is_mine(hw, i);
1568
1569                 if (!gpio_val)
1570                         continue;
1571
1572                 /* ignore gpio LED src mode entries related to the activity
1573                  *  LEDs
1574                  */
1575                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1576                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1577                 switch (current_mode) {
1578                 case I40E_COMBINED_ACTIVITY:
1579                 case I40E_FILTER_ACTIVITY:
1580                 case I40E_MAC_ACTIVITY:
1581                         continue;
1582                 default:
1583                         break;
1584                 }
1585
1586                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1587                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1588                 break;
1589         }
1590
1591         return mode;
1592 }
1593
1594 /**
1595  * i40e_led_set - set new on/off mode
1596  * @hw: pointer to the hw struct
1597  * @mode: 0=off, 0xf=on (else see manual for mode details)
1598  * @blink: true if the LED should blink when on, false if steady
1599  *
1600  * if this function is used to turn on the blink it should
1601  * be used to disable the blink when restoring the original state.
1602  **/
1603 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1604 {
1605         u32 current_mode = 0;
1606         int i;
1607
1608         if (mode & 0xfffffff0)
1609                 DEBUGOUT1("invalid mode passed in %X\n", mode);
1610
1611         /* as per the documentation GPIO 22-29 are the LED
1612          * GPIO pins named LED0..LED7
1613          */
1614         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1615                 u32 gpio_val = i40e_led_is_mine(hw, i);
1616
1617                 if (!gpio_val)
1618                         continue;
1619
1620                 /* ignore gpio LED src mode entries related to the activity
1621                  * LEDs
1622                  */
1623                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1624                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1625                 switch (current_mode) {
1626                 case I40E_COMBINED_ACTIVITY:
1627                 case I40E_FILTER_ACTIVITY:
1628                 case I40E_MAC_ACTIVITY:
1629                         continue;
1630                 default:
1631                         break;
1632                 }
1633
1634                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1635                 /* this & is a bit of paranoia, but serves as a range check */
1636                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1637                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1638
1639                 if (mode == I40E_LINK_ACTIVITY)
1640                         blink = false;
1641
1642                 if (blink)
1643                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1644                 else
1645                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1646
1647                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1648                 break;
1649         }
1650 }
1651
1652 /* Admin command wrappers */
1653
1654 /**
1655  * i40e_aq_get_phy_capabilities
1656  * @hw: pointer to the hw struct
1657  * @abilities: structure for PHY capabilities to be filled
1658  * @qualified_modules: report Qualified Modules
1659  * @report_init: report init capabilities (active are default)
1660  * @cmd_details: pointer to command details structure or NULL
1661  *
1662  * Returns the various PHY abilities supported on the Port.
1663  **/
1664 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1665                         bool qualified_modules, bool report_init,
1666                         struct i40e_aq_get_phy_abilities_resp *abilities,
1667                         struct i40e_asq_cmd_details *cmd_details)
1668 {
1669         struct i40e_aq_desc desc;
1670         enum i40e_status_code status;
1671         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1672
1673         if (!abilities)
1674                 return I40E_ERR_PARAM;
1675
1676         i40e_fill_default_direct_cmd_desc(&desc,
1677                                           i40e_aqc_opc_get_phy_abilities);
1678
1679         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1680         if (abilities_size > I40E_AQ_LARGE_BUF)
1681                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1682
1683         if (qualified_modules)
1684                 desc.params.external.param0 |=
1685                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1686
1687         if (report_init)
1688                 desc.params.external.param0 |=
1689                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1690
1691         status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1692                                     cmd_details);
1693
1694         if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1695                 status = I40E_ERR_UNKNOWN_PHY;
1696
1697         if (report_init) {
1698                 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1699                 hw->phy.phy_types |= ((u64)abilities->phy_type_ext << 32);
1700         }
1701
1702         return status;
1703 }
1704
1705 /**
1706  * i40e_aq_set_phy_config
1707  * @hw: pointer to the hw struct
1708  * @config: structure with PHY configuration to be set
1709  * @cmd_details: pointer to command details structure or NULL
1710  *
1711  * Set the various PHY configuration parameters
1712  * supported on the Port.One or more of the Set PHY config parameters may be
1713  * ignored in an MFP mode as the PF may not have the privilege to set some
1714  * of the PHY Config parameters. This status will be indicated by the
1715  * command response.
1716  **/
1717 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1718                                 struct i40e_aq_set_phy_config *config,
1719                                 struct i40e_asq_cmd_details *cmd_details)
1720 {
1721         struct i40e_aq_desc desc;
1722         struct i40e_aq_set_phy_config *cmd =
1723                 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1724         enum i40e_status_code status;
1725
1726         if (!config)
1727                 return I40E_ERR_PARAM;
1728
1729         i40e_fill_default_direct_cmd_desc(&desc,
1730                                           i40e_aqc_opc_set_phy_config);
1731
1732         *cmd = *config;
1733
1734         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1735
1736         return status;
1737 }
1738
1739 /**
1740  * i40e_set_fc
1741  * @hw: pointer to the hw struct
1742  *
1743  * Set the requested flow control mode using set_phy_config.
1744  **/
1745 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1746                                   bool atomic_restart)
1747 {
1748         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1749         struct i40e_aq_get_phy_abilities_resp abilities;
1750         struct i40e_aq_set_phy_config config;
1751         enum i40e_status_code status;
1752         u8 pause_mask = 0x0;
1753
1754         *aq_failures = 0x0;
1755
1756         switch (fc_mode) {
1757         case I40E_FC_FULL:
1758                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1759                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1760                 break;
1761         case I40E_FC_RX_PAUSE:
1762                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1763                 break;
1764         case I40E_FC_TX_PAUSE:
1765                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1766                 break;
1767         default:
1768                 break;
1769         }
1770
1771         /* Get the current phy config */
1772         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1773                                               NULL);
1774         if (status) {
1775                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1776                 return status;
1777         }
1778
1779         memset(&config, 0, sizeof(config));
1780         /* clear the old pause settings */
1781         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1782                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1783         /* set the new abilities */
1784         config.abilities |= pause_mask;
1785         /* If the abilities have changed, then set the new config */
1786         if (config.abilities != abilities.abilities) {
1787                 /* Auto restart link so settings take effect */
1788                 if (atomic_restart)
1789                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1790                 /* Copy over all the old settings */
1791                 config.phy_type = abilities.phy_type;
1792                 config.phy_type_ext = abilities.phy_type_ext;
1793                 config.link_speed = abilities.link_speed;
1794                 config.eee_capability = abilities.eee_capability;
1795                 config.eeer = abilities.eeer_val;
1796                 config.low_power_ctrl = abilities.d3_lpan;
1797                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1798
1799                 if (status)
1800                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1801         }
1802         /* Update the link info */
1803         status = i40e_update_link_info(hw);
1804         if (status) {
1805                 /* Wait a little bit (on 40G cards it sometimes takes a really
1806                  * long time for link to come back from the atomic reset)
1807                  * and try once more
1808                  */
1809                 i40e_msec_delay(1000);
1810                 status = i40e_update_link_info(hw);
1811         }
1812         if (status)
1813                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1814
1815         return status;
1816 }
1817
1818 /**
1819  * i40e_aq_set_mac_config
1820  * @hw: pointer to the hw struct
1821  * @max_frame_size: Maximum Frame Size to be supported by the port
1822  * @crc_en: Tell HW to append a CRC to outgoing frames
1823  * @pacing: Pacing configurations
1824  * @cmd_details: pointer to command details structure or NULL
1825  *
1826  * Configure MAC settings for frame size, jumbo frame support and the
1827  * addition of a CRC by the hardware.
1828  **/
1829 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1830                                 u16 max_frame_size,
1831                                 bool crc_en, u16 pacing,
1832                                 struct i40e_asq_cmd_details *cmd_details)
1833 {
1834         struct i40e_aq_desc desc;
1835         struct i40e_aq_set_mac_config *cmd =
1836                 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1837         enum i40e_status_code status;
1838
1839         if (max_frame_size == 0)
1840                 return I40E_ERR_PARAM;
1841
1842         i40e_fill_default_direct_cmd_desc(&desc,
1843                                           i40e_aqc_opc_set_mac_config);
1844
1845         cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1846         cmd->params = ((u8)pacing & 0x0F) << 3;
1847         if (crc_en)
1848                 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1849
1850         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1851
1852         return status;
1853 }
1854
1855 /**
1856  * i40e_aq_clear_pxe_mode
1857  * @hw: pointer to the hw struct
1858  * @cmd_details: pointer to command details structure or NULL
1859  *
1860  * Tell the firmware that the driver is taking over from PXE
1861  **/
1862 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1863                         struct i40e_asq_cmd_details *cmd_details)
1864 {
1865         enum i40e_status_code status;
1866         struct i40e_aq_desc desc;
1867         struct i40e_aqc_clear_pxe *cmd =
1868                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1869
1870         i40e_fill_default_direct_cmd_desc(&desc,
1871                                           i40e_aqc_opc_clear_pxe_mode);
1872
1873         cmd->rx_cnt = 0x2;
1874
1875         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1876
1877         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1878
1879         return status;
1880 }
1881
1882 /**
1883  * i40e_aq_set_link_restart_an
1884  * @hw: pointer to the hw struct
1885  * @enable_link: if true: enable link, if false: disable link
1886  * @cmd_details: pointer to command details structure or NULL
1887  *
1888  * Sets up the link and restarts the Auto-Negotiation over the link.
1889  **/
1890 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1891                 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1892 {
1893         struct i40e_aq_desc desc;
1894         struct i40e_aqc_set_link_restart_an *cmd =
1895                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1896         enum i40e_status_code status;
1897
1898         i40e_fill_default_direct_cmd_desc(&desc,
1899                                           i40e_aqc_opc_set_link_restart_an);
1900
1901         cmd->command = I40E_AQ_PHY_RESTART_AN;
1902         if (enable_link)
1903                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1904         else
1905                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1906
1907         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1908
1909         return status;
1910 }
1911
1912 /**
1913  * i40e_aq_get_link_info
1914  * @hw: pointer to the hw struct
1915  * @enable_lse: enable/disable LinkStatusEvent reporting
1916  * @link: pointer to link status structure - optional
1917  * @cmd_details: pointer to command details structure or NULL
1918  *
1919  * Returns the link status of the adapter.
1920  **/
1921 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1922                                 bool enable_lse, struct i40e_link_status *link,
1923                                 struct i40e_asq_cmd_details *cmd_details)
1924 {
1925         struct i40e_aq_desc desc;
1926         struct i40e_aqc_get_link_status *resp =
1927                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1928         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1929         enum i40e_status_code status;
1930         bool tx_pause, rx_pause;
1931         u16 command_flags;
1932
1933         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1934
1935         if (enable_lse)
1936                 command_flags = I40E_AQ_LSE_ENABLE;
1937         else
1938                 command_flags = I40E_AQ_LSE_DISABLE;
1939         resp->command_flags = CPU_TO_LE16(command_flags);
1940
1941         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1942
1943         if (status != I40E_SUCCESS)
1944                 goto aq_get_link_info_exit;
1945
1946         /* save off old link status information */
1947         i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1948                     sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1949
1950         /* update link status */
1951         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1952         hw->phy.media_type = i40e_get_media_type(hw);
1953         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1954         hw_link_info->link_info = resp->link_info;
1955         hw_link_info->an_info = resp->an_info;
1956         hw_link_info->ext_info = resp->ext_info;
1957         hw_link_info->loopback = resp->loopback;
1958         hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1959         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1960
1961         /* update fc info */
1962         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1963         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1964         if (tx_pause & rx_pause)
1965                 hw->fc.current_mode = I40E_FC_FULL;
1966         else if (tx_pause)
1967                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1968         else if (rx_pause)
1969                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1970         else
1971                 hw->fc.current_mode = I40E_FC_NONE;
1972
1973         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1974                 hw_link_info->crc_enable = true;
1975         else
1976                 hw_link_info->crc_enable = false;
1977
1978         if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
1979                 hw_link_info->lse_enable = true;
1980         else
1981                 hw_link_info->lse_enable = false;
1982
1983         if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1984              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1985                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1986
1987         /* save link status information */
1988         if (link)
1989                 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1990                             I40E_NONDMA_TO_NONDMA);
1991
1992         /* flag cleared so helper functions don't call AQ again */
1993         hw->phy.get_link_info = false;
1994
1995 aq_get_link_info_exit:
1996         return status;
1997 }
1998
1999 /**
2000  * i40e_aq_set_phy_int_mask
2001  * @hw: pointer to the hw struct
2002  * @mask: interrupt mask to be set
2003  * @cmd_details: pointer to command details structure or NULL
2004  *
2005  * Set link interrupt mask.
2006  **/
2007 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2008                                 u16 mask,
2009                                 struct i40e_asq_cmd_details *cmd_details)
2010 {
2011         struct i40e_aq_desc desc;
2012         struct i40e_aqc_set_phy_int_mask *cmd =
2013                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2014         enum i40e_status_code status;
2015
2016         i40e_fill_default_direct_cmd_desc(&desc,
2017                                           i40e_aqc_opc_set_phy_int_mask);
2018
2019         cmd->event_mask = CPU_TO_LE16(mask);
2020
2021         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2022
2023         return status;
2024 }
2025
2026 /**
2027  * i40e_aq_get_local_advt_reg
2028  * @hw: pointer to the hw struct
2029  * @advt_reg: local AN advertisement register value
2030  * @cmd_details: pointer to command details structure or NULL
2031  *
2032  * Get the Local AN advertisement register value.
2033  **/
2034 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2035                                 u64 *advt_reg,
2036                                 struct i40e_asq_cmd_details *cmd_details)
2037 {
2038         struct i40e_aq_desc desc;
2039         struct i40e_aqc_an_advt_reg *resp =
2040                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2041         enum i40e_status_code status;
2042
2043         i40e_fill_default_direct_cmd_desc(&desc,
2044                                           i40e_aqc_opc_get_local_advt_reg);
2045
2046         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2047
2048         if (status != I40E_SUCCESS)
2049                 goto aq_get_local_advt_reg_exit;
2050
2051         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2052         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2053
2054 aq_get_local_advt_reg_exit:
2055         return status;
2056 }
2057
2058 /**
2059  * i40e_aq_set_local_advt_reg
2060  * @hw: pointer to the hw struct
2061  * @advt_reg: local AN advertisement register value
2062  * @cmd_details: pointer to command details structure or NULL
2063  *
2064  * Get the Local AN advertisement register value.
2065  **/
2066 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2067                                 u64 advt_reg,
2068                                 struct i40e_asq_cmd_details *cmd_details)
2069 {
2070         struct i40e_aq_desc desc;
2071         struct i40e_aqc_an_advt_reg *cmd =
2072                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2073         enum i40e_status_code status;
2074
2075         i40e_fill_default_direct_cmd_desc(&desc,
2076                                           i40e_aqc_opc_get_local_advt_reg);
2077
2078         cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2079         cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2080
2081         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2082
2083         return status;
2084 }
2085
2086 /**
2087  * i40e_aq_get_partner_advt
2088  * @hw: pointer to the hw struct
2089  * @advt_reg: AN partner advertisement register value
2090  * @cmd_details: pointer to command details structure or NULL
2091  *
2092  * Get the link partner AN advertisement register value.
2093  **/
2094 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2095                                 u64 *advt_reg,
2096                                 struct i40e_asq_cmd_details *cmd_details)
2097 {
2098         struct i40e_aq_desc desc;
2099         struct i40e_aqc_an_advt_reg *resp =
2100                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2101         enum i40e_status_code status;
2102
2103         i40e_fill_default_direct_cmd_desc(&desc,
2104                                           i40e_aqc_opc_get_partner_advt);
2105
2106         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2107
2108         if (status != I40E_SUCCESS)
2109                 goto aq_get_partner_advt_exit;
2110
2111         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2112         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2113
2114 aq_get_partner_advt_exit:
2115         return status;
2116 }
2117
2118 /**
2119  * i40e_aq_set_lb_modes
2120  * @hw: pointer to the hw struct
2121  * @lb_modes: loopback mode to be set
2122  * @cmd_details: pointer to command details structure or NULL
2123  *
2124  * Sets loopback modes.
2125  **/
2126 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2127                                 u16 lb_modes,
2128                                 struct i40e_asq_cmd_details *cmd_details)
2129 {
2130         struct i40e_aq_desc desc;
2131         struct i40e_aqc_set_lb_mode *cmd =
2132                 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2133         enum i40e_status_code status;
2134
2135         i40e_fill_default_direct_cmd_desc(&desc,
2136                                           i40e_aqc_opc_set_lb_modes);
2137
2138         cmd->lb_mode = CPU_TO_LE16(lb_modes);
2139
2140         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2141
2142         return status;
2143 }
2144
2145 /**
2146  * i40e_aq_set_phy_debug
2147  * @hw: pointer to the hw struct
2148  * @cmd_flags: debug command flags
2149  * @cmd_details: pointer to command details structure or NULL
2150  *
2151  * Reset the external PHY.
2152  **/
2153 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2154                                 struct i40e_asq_cmd_details *cmd_details)
2155 {
2156         struct i40e_aq_desc desc;
2157         struct i40e_aqc_set_phy_debug *cmd =
2158                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2159         enum i40e_status_code status;
2160
2161         i40e_fill_default_direct_cmd_desc(&desc,
2162                                           i40e_aqc_opc_set_phy_debug);
2163
2164         cmd->command_flags = cmd_flags;
2165
2166         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2167
2168         return status;
2169 }
2170
2171 /**
2172  * i40e_aq_add_vsi
2173  * @hw: pointer to the hw struct
2174  * @vsi_ctx: pointer to a vsi context struct
2175  * @cmd_details: pointer to command details structure or NULL
2176  *
2177  * Add a VSI context to the hardware.
2178 **/
2179 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2180                                 struct i40e_vsi_context *vsi_ctx,
2181                                 struct i40e_asq_cmd_details *cmd_details)
2182 {
2183         struct i40e_aq_desc desc;
2184         struct i40e_aqc_add_get_update_vsi *cmd =
2185                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2186         struct i40e_aqc_add_get_update_vsi_completion *resp =
2187                 (struct i40e_aqc_add_get_update_vsi_completion *)
2188                 &desc.params.raw;
2189         enum i40e_status_code status;
2190
2191         i40e_fill_default_direct_cmd_desc(&desc,
2192                                           i40e_aqc_opc_add_vsi);
2193
2194         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2195         cmd->connection_type = vsi_ctx->connection_type;
2196         cmd->vf_id = vsi_ctx->vf_num;
2197         cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2198
2199         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2200
2201         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2202                                     sizeof(vsi_ctx->info), cmd_details);
2203
2204         if (status != I40E_SUCCESS)
2205                 goto aq_add_vsi_exit;
2206
2207         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2208         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2209         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2210         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2211
2212 aq_add_vsi_exit:
2213         return status;
2214 }
2215
2216 /**
2217  * i40e_aq_set_default_vsi
2218  * @hw: pointer to the hw struct
2219  * @seid: vsi number
2220  * @cmd_details: pointer to command details structure or NULL
2221  **/
2222 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2223                                 u16 seid,
2224                                 struct i40e_asq_cmd_details *cmd_details)
2225 {
2226         struct i40e_aq_desc desc;
2227         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2228                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2229                 &desc.params.raw;
2230         enum i40e_status_code status;
2231
2232         i40e_fill_default_direct_cmd_desc(&desc,
2233                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2234
2235         cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2236         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2237         cmd->seid = CPU_TO_LE16(seid);
2238
2239         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2240
2241         return status;
2242 }
2243
2244 /**
2245  * i40e_aq_clear_default_vsi
2246  * @hw: pointer to the hw struct
2247  * @seid: vsi number
2248  * @cmd_details: pointer to command details structure or NULL
2249  **/
2250 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2251                                 u16 seid,
2252                                 struct i40e_asq_cmd_details *cmd_details)
2253 {
2254         struct i40e_aq_desc desc;
2255         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2256                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2257                 &desc.params.raw;
2258         enum i40e_status_code status;
2259
2260         i40e_fill_default_direct_cmd_desc(&desc,
2261                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2262
2263         cmd->promiscuous_flags = CPU_TO_LE16(0);
2264         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2265         cmd->seid = CPU_TO_LE16(seid);
2266
2267         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2268
2269         return status;
2270 }
2271
2272 /**
2273  * i40e_aq_set_vsi_unicast_promiscuous
2274  * @hw: pointer to the hw struct
2275  * @seid: vsi number
2276  * @set: set unicast promiscuous enable/disable
2277  * @cmd_details: pointer to command details structure or NULL
2278  * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2279  **/
2280 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2281                                 u16 seid, bool set,
2282                                 struct i40e_asq_cmd_details *cmd_details,
2283                                 bool rx_only_promisc)
2284 {
2285         struct i40e_aq_desc desc;
2286         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2287                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2288         enum i40e_status_code status;
2289         u16 flags = 0;
2290
2291         i40e_fill_default_direct_cmd_desc(&desc,
2292                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2293
2294         if (set) {
2295                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2296                 if (rx_only_promisc &&
2297                     (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2298                      (hw->aq.api_maj_ver > 1)))
2299                         flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2300         }
2301
2302         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2303
2304         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2305         if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2306              (hw->aq.api_maj_ver > 1))
2307                 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2308
2309         cmd->seid = CPU_TO_LE16(seid);
2310         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2311
2312         return status;
2313 }
2314
2315 /**
2316  * i40e_aq_set_vsi_multicast_promiscuous
2317  * @hw: pointer to the hw struct
2318  * @seid: vsi number
2319  * @set: set multicast promiscuous enable/disable
2320  * @cmd_details: pointer to command details structure or NULL
2321  **/
2322 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2323                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2324 {
2325         struct i40e_aq_desc desc;
2326         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2327                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2328         enum i40e_status_code status;
2329         u16 flags = 0;
2330
2331         i40e_fill_default_direct_cmd_desc(&desc,
2332                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2333
2334         if (set)
2335                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2336
2337         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2338
2339         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2340
2341         cmd->seid = CPU_TO_LE16(seid);
2342         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2343
2344         return status;
2345 }
2346
2347 /**
2348  * i40e_aq_set_vsi_mc_promisc_on_vlan
2349  * @hw: pointer to the hw struct
2350  * @seid: vsi number
2351  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2352  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2353  * @cmd_details: pointer to command details structure or NULL
2354  **/
2355 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2356                                 u16 seid, bool enable, u16 vid,
2357                                 struct i40e_asq_cmd_details *cmd_details)
2358 {
2359         struct i40e_aq_desc desc;
2360         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2361                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2362         enum i40e_status_code status;
2363         u16 flags = 0;
2364
2365         i40e_fill_default_direct_cmd_desc(&desc,
2366                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2367
2368         if (enable)
2369                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2370
2371         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2372         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2373         cmd->seid = CPU_TO_LE16(seid);
2374         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2375
2376         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2377
2378         return status;
2379 }
2380
2381 /**
2382  * i40e_aq_set_vsi_uc_promisc_on_vlan
2383  * @hw: pointer to the hw struct
2384  * @seid: vsi number
2385  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2386  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2387  * @cmd_details: pointer to command details structure or NULL
2388  **/
2389 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2390                                 u16 seid, bool enable, u16 vid,
2391                                 struct i40e_asq_cmd_details *cmd_details)
2392 {
2393         struct i40e_aq_desc desc;
2394         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2395                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2396         enum i40e_status_code status;
2397         u16 flags = 0;
2398
2399         i40e_fill_default_direct_cmd_desc(&desc,
2400                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2401
2402         if (enable)
2403                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2404
2405         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2406         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2407         cmd->seid = CPU_TO_LE16(seid);
2408         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2409
2410         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2411
2412         return status;
2413 }
2414
2415 /**
2416  * i40e_aq_set_vsi_broadcast
2417  * @hw: pointer to the hw struct
2418  * @seid: vsi number
2419  * @set_filter: true to set filter, false to clear filter
2420  * @cmd_details: pointer to command details structure or NULL
2421  *
2422  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2423  **/
2424 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2425                                 u16 seid, bool set_filter,
2426                                 struct i40e_asq_cmd_details *cmd_details)
2427 {
2428         struct i40e_aq_desc desc;
2429         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2430                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2431         enum i40e_status_code status;
2432
2433         i40e_fill_default_direct_cmd_desc(&desc,
2434                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2435
2436         if (set_filter)
2437                 cmd->promiscuous_flags
2438                             |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2439         else
2440                 cmd->promiscuous_flags
2441                             &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2442
2443         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2444         cmd->seid = CPU_TO_LE16(seid);
2445         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2446
2447         return status;
2448 }
2449
2450 /**
2451  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2452  * @hw: pointer to the hw struct
2453  * @seid: vsi number
2454  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2455  * @cmd_details: pointer to command details structure or NULL
2456  **/
2457 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2458                                 u16 seid, bool enable,
2459                                 struct i40e_asq_cmd_details *cmd_details)
2460 {
2461         struct i40e_aq_desc desc;
2462         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2463                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2464         enum i40e_status_code status;
2465         u16 flags = 0;
2466
2467         i40e_fill_default_direct_cmd_desc(&desc,
2468                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2469         if (enable)
2470                 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2471
2472         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2473         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2474         cmd->seid = CPU_TO_LE16(seid);
2475
2476         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2477
2478         return status;
2479 }
2480
2481 /**
2482  * i40e_get_vsi_params - get VSI configuration info
2483  * @hw: pointer to the hw struct
2484  * @vsi_ctx: pointer to a vsi context struct
2485  * @cmd_details: pointer to command details structure or NULL
2486  **/
2487 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2488                                 struct i40e_vsi_context *vsi_ctx,
2489                                 struct i40e_asq_cmd_details *cmd_details)
2490 {
2491         struct i40e_aq_desc desc;
2492         struct i40e_aqc_add_get_update_vsi *cmd =
2493                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2494         struct i40e_aqc_add_get_update_vsi_completion *resp =
2495                 (struct i40e_aqc_add_get_update_vsi_completion *)
2496                 &desc.params.raw;
2497         enum i40e_status_code status;
2498
2499         UNREFERENCED_1PARAMETER(cmd_details);
2500         i40e_fill_default_direct_cmd_desc(&desc,
2501                                           i40e_aqc_opc_get_vsi_parameters);
2502
2503         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2504
2505         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2506
2507         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2508                                     sizeof(vsi_ctx->info), NULL);
2509
2510         if (status != I40E_SUCCESS)
2511                 goto aq_get_vsi_params_exit;
2512
2513         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2514         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2515         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2516         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2517
2518 aq_get_vsi_params_exit:
2519         return status;
2520 }
2521
2522 /**
2523  * i40e_aq_update_vsi_params
2524  * @hw: pointer to the hw struct
2525  * @vsi_ctx: pointer to a vsi context struct
2526  * @cmd_details: pointer to command details structure or NULL
2527  *
2528  * Update a VSI context.
2529  **/
2530 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2531                                 struct i40e_vsi_context *vsi_ctx,
2532                                 struct i40e_asq_cmd_details *cmd_details)
2533 {
2534         struct i40e_aq_desc desc;
2535         struct i40e_aqc_add_get_update_vsi *cmd =
2536                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2537         struct i40e_aqc_add_get_update_vsi_completion *resp =
2538                 (struct i40e_aqc_add_get_update_vsi_completion *)
2539                 &desc.params.raw;
2540         enum i40e_status_code status;
2541
2542         i40e_fill_default_direct_cmd_desc(&desc,
2543                                           i40e_aqc_opc_update_vsi_parameters);
2544         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2545
2546         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2547
2548         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2549                                     sizeof(vsi_ctx->info), cmd_details);
2550
2551         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2552         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2553
2554         return status;
2555 }
2556
2557 /**
2558  * i40e_aq_get_switch_config
2559  * @hw: pointer to the hardware structure
2560  * @buf: pointer to the result buffer
2561  * @buf_size: length of input buffer
2562  * @start_seid: seid to start for the report, 0 == beginning
2563  * @cmd_details: pointer to command details structure or NULL
2564  *
2565  * Fill the buf with switch configuration returned from AdminQ command
2566  **/
2567 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2568                                 struct i40e_aqc_get_switch_config_resp *buf,
2569                                 u16 buf_size, u16 *start_seid,
2570                                 struct i40e_asq_cmd_details *cmd_details)
2571 {
2572         struct i40e_aq_desc desc;
2573         struct i40e_aqc_switch_seid *scfg =
2574                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2575         enum i40e_status_code status;
2576
2577         i40e_fill_default_direct_cmd_desc(&desc,
2578                                           i40e_aqc_opc_get_switch_config);
2579         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2580         if (buf_size > I40E_AQ_LARGE_BUF)
2581                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2582         scfg->seid = CPU_TO_LE16(*start_seid);
2583
2584         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2585         *start_seid = LE16_TO_CPU(scfg->seid);
2586
2587         return status;
2588 }
2589
2590 /**
2591  * i40e_aq_set_switch_config
2592  * @hw: pointer to the hardware structure
2593  * @flags: bit flag values to set
2594  * @valid_flags: which bit flags to set
2595  * @cmd_details: pointer to command details structure or NULL
2596  *
2597  * Set switch configuration bits
2598  **/
2599 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2600                                 u16 flags, u16 valid_flags,
2601                                 struct i40e_asq_cmd_details *cmd_details)
2602 {
2603         struct i40e_aq_desc desc;
2604         struct i40e_aqc_set_switch_config *scfg =
2605                 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2606         enum i40e_status_code status;
2607
2608         i40e_fill_default_direct_cmd_desc(&desc,
2609                                           i40e_aqc_opc_set_switch_config);
2610         scfg->flags = CPU_TO_LE16(flags);
2611         scfg->valid_flags = CPU_TO_LE16(valid_flags);
2612
2613         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2614
2615         return status;
2616 }
2617
2618 /**
2619  * i40e_aq_get_firmware_version
2620  * @hw: pointer to the hw struct
2621  * @fw_major_version: firmware major version
2622  * @fw_minor_version: firmware minor version
2623  * @fw_build: firmware build number
2624  * @api_major_version: major queue version
2625  * @api_minor_version: minor queue version
2626  * @cmd_details: pointer to command details structure or NULL
2627  *
2628  * Get the firmware version from the admin queue commands
2629  **/
2630 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2631                                 u16 *fw_major_version, u16 *fw_minor_version,
2632                                 u32 *fw_build,
2633                                 u16 *api_major_version, u16 *api_minor_version,
2634                                 struct i40e_asq_cmd_details *cmd_details)
2635 {
2636         struct i40e_aq_desc desc;
2637         struct i40e_aqc_get_version *resp =
2638                 (struct i40e_aqc_get_version *)&desc.params.raw;
2639         enum i40e_status_code status;
2640
2641         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2642
2643         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2644
2645         if (status == I40E_SUCCESS) {
2646                 if (fw_major_version != NULL)
2647                         *fw_major_version = LE16_TO_CPU(resp->fw_major);
2648                 if (fw_minor_version != NULL)
2649                         *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2650                 if (fw_build != NULL)
2651                         *fw_build = LE32_TO_CPU(resp->fw_build);
2652                 if (api_major_version != NULL)
2653                         *api_major_version = LE16_TO_CPU(resp->api_major);
2654                 if (api_minor_version != NULL)
2655                         *api_minor_version = LE16_TO_CPU(resp->api_minor);
2656
2657                 /* A workaround to fix the API version in SW */
2658                 if (api_major_version && api_minor_version &&
2659                     fw_major_version && fw_minor_version &&
2660                     ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2661                     (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2662                      (*fw_major_version > 4)))
2663                         *api_minor_version = 2;
2664         }
2665
2666         return status;
2667 }
2668
2669 /**
2670  * i40e_aq_send_driver_version
2671  * @hw: pointer to the hw struct
2672  * @dv: driver's major, minor version
2673  * @cmd_details: pointer to command details structure or NULL
2674  *
2675  * Send the driver version to the firmware
2676  **/
2677 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2678                                 struct i40e_driver_version *dv,
2679                                 struct i40e_asq_cmd_details *cmd_details)
2680 {
2681         struct i40e_aq_desc desc;
2682         struct i40e_aqc_driver_version *cmd =
2683                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2684         enum i40e_status_code status;
2685         u16 len;
2686
2687         if (dv == NULL)
2688                 return I40E_ERR_PARAM;
2689
2690         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2691
2692         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2693         cmd->driver_major_ver = dv->major_version;
2694         cmd->driver_minor_ver = dv->minor_version;
2695         cmd->driver_build_ver = dv->build_version;
2696         cmd->driver_subbuild_ver = dv->subbuild_version;
2697
2698         len = 0;
2699         while (len < sizeof(dv->driver_string) &&
2700                (dv->driver_string[len] < 0x80) &&
2701                dv->driver_string[len])
2702                 len++;
2703         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2704                                        len, cmd_details);
2705
2706         return status;
2707 }
2708
2709 /**
2710  * i40e_get_link_status - get status of the HW network link
2711  * @hw: pointer to the hw struct
2712  * @link_up: pointer to bool (true/false = linkup/linkdown)
2713  *
2714  * Variable link_up true if link is up, false if link is down.
2715  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2716  *
2717  * Side effect: LinkStatusEvent reporting becomes enabled
2718  **/
2719 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2720 {
2721         enum i40e_status_code status = I40E_SUCCESS;
2722
2723         if (hw->phy.get_link_info) {
2724                 status = i40e_update_link_info(hw);
2725
2726                 if (status != I40E_SUCCESS)
2727                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2728                                    status);
2729         }
2730
2731         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2732
2733         return status;
2734 }
2735
2736 /**
2737  * i40e_updatelink_status - update status of the HW network link
2738  * @hw: pointer to the hw struct
2739  **/
2740 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2741 {
2742         struct i40e_aq_get_phy_abilities_resp abilities;
2743         enum i40e_status_code status = I40E_SUCCESS;
2744
2745         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2746         if (status)
2747                 return status;
2748
2749         /* extra checking needed to ensure link info to user is timely */
2750         if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2751             ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2752              !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2753                 status = i40e_aq_get_phy_capabilities(hw, false, false,
2754                                                       &abilities, NULL);
2755                 if (status)
2756                         return status;
2757
2758                 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2759                         sizeof(hw->phy.link_info.module_type));
2760         }
2761         return status;
2762 }
2763
2764
2765 /**
2766  * i40e_get_link_speed
2767  * @hw: pointer to the hw struct
2768  *
2769  * Returns the link speed of the adapter.
2770  **/
2771 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2772 {
2773         enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2774         enum i40e_status_code status = I40E_SUCCESS;
2775
2776         if (hw->phy.get_link_info) {
2777                 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2778
2779                 if (status != I40E_SUCCESS)
2780                         goto i40e_link_speed_exit;
2781         }
2782
2783         speed = hw->phy.link_info.link_speed;
2784
2785 i40e_link_speed_exit:
2786         return speed;
2787 }
2788
2789 /**
2790  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2791  * @hw: pointer to the hw struct
2792  * @uplink_seid: the MAC or other gizmo SEID
2793  * @downlink_seid: the VSI SEID
2794  * @enabled_tc: bitmap of TCs to be enabled
2795  * @default_port: true for default port VSI, false for control port
2796  * @veb_seid: pointer to where to put the resulting VEB SEID
2797  * @enable_stats: true to turn on VEB stats
2798  * @cmd_details: pointer to command details structure or NULL
2799  *
2800  * This asks the FW to add a VEB between the uplink and downlink
2801  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2802  **/
2803 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2804                                 u16 downlink_seid, u8 enabled_tc,
2805                                 bool default_port, u16 *veb_seid,
2806                                 bool enable_stats,
2807                                 struct i40e_asq_cmd_details *cmd_details)
2808 {
2809         struct i40e_aq_desc desc;
2810         struct i40e_aqc_add_veb *cmd =
2811                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2812         struct i40e_aqc_add_veb_completion *resp =
2813                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2814         enum i40e_status_code status;
2815         u16 veb_flags = 0;
2816
2817         /* SEIDs need to either both be set or both be 0 for floating VEB */
2818         if (!!uplink_seid != !!downlink_seid)
2819                 return I40E_ERR_PARAM;
2820
2821         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2822
2823         cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2824         cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2825         cmd->enable_tcs = enabled_tc;
2826         if (!uplink_seid)
2827                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2828         if (default_port)
2829                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2830         else
2831                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2832
2833         /* reverse logic here: set the bitflag to disable the stats */
2834         if (!enable_stats)
2835                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2836
2837         cmd->veb_flags = CPU_TO_LE16(veb_flags);
2838
2839         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2840
2841         if (!status && veb_seid)
2842                 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2843
2844         return status;
2845 }
2846
2847 /**
2848  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2849  * @hw: pointer to the hw struct
2850  * @veb_seid: the SEID of the VEB to query
2851  * @switch_id: the uplink switch id
2852  * @floating: set to true if the VEB is floating
2853  * @statistic_index: index of the stats counter block for this VEB
2854  * @vebs_used: number of VEB's used by function
2855  * @vebs_free: total VEB's not reserved by any function
2856  * @cmd_details: pointer to command details structure or NULL
2857  *
2858  * This retrieves the parameters for a particular VEB, specified by
2859  * uplink_seid, and returns them to the caller.
2860  **/
2861 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2862                                 u16 veb_seid, u16 *switch_id,
2863                                 bool *floating, u16 *statistic_index,
2864                                 u16 *vebs_used, u16 *vebs_free,
2865                                 struct i40e_asq_cmd_details *cmd_details)
2866 {
2867         struct i40e_aq_desc desc;
2868         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2869                 (struct i40e_aqc_get_veb_parameters_completion *)
2870                 &desc.params.raw;
2871         enum i40e_status_code status;
2872
2873         if (veb_seid == 0)
2874                 return I40E_ERR_PARAM;
2875
2876         i40e_fill_default_direct_cmd_desc(&desc,
2877                                           i40e_aqc_opc_get_veb_parameters);
2878         cmd_resp->seid = CPU_TO_LE16(veb_seid);
2879
2880         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2881         if (status)
2882                 goto get_veb_exit;
2883
2884         if (switch_id)
2885                 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2886         if (statistic_index)
2887                 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2888         if (vebs_used)
2889                 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2890         if (vebs_free)
2891                 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2892         if (floating) {
2893                 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2894
2895                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2896                         *floating = true;
2897                 else
2898                         *floating = false;
2899         }
2900
2901 get_veb_exit:
2902         return status;
2903 }
2904
2905 /**
2906  * i40e_aq_add_macvlan
2907  * @hw: pointer to the hw struct
2908  * @seid: VSI for the mac address
2909  * @mv_list: list of macvlans to be added
2910  * @count: length of the list
2911  * @cmd_details: pointer to command details structure or NULL
2912  *
2913  * Add MAC/VLAN addresses to the HW filtering
2914  **/
2915 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2916                         struct i40e_aqc_add_macvlan_element_data *mv_list,
2917                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2918 {
2919         struct i40e_aq_desc desc;
2920         struct i40e_aqc_macvlan *cmd =
2921                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2922         enum i40e_status_code status;
2923         u16 buf_size;
2924         int i;
2925
2926         if (count == 0 || !mv_list || !hw)
2927                 return I40E_ERR_PARAM;
2928
2929         buf_size = count * sizeof(*mv_list);
2930
2931         /* prep the rest of the request */
2932         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2933         cmd->num_addresses = CPU_TO_LE16(count);
2934         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2935         cmd->seid[1] = 0;
2936         cmd->seid[2] = 0;
2937
2938         for (i = 0; i < count; i++)
2939                 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
2940                         mv_list[i].flags |=
2941                             CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2942
2943         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2944         if (buf_size > I40E_AQ_LARGE_BUF)
2945                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2946
2947         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2948                                        cmd_details);
2949
2950         return status;
2951 }
2952
2953 /**
2954  * i40e_aq_remove_macvlan
2955  * @hw: pointer to the hw struct
2956  * @seid: VSI for the mac address
2957  * @mv_list: list of macvlans to be removed
2958  * @count: length of the list
2959  * @cmd_details: pointer to command details structure or NULL
2960  *
2961  * Remove MAC/VLAN addresses from the HW filtering
2962  **/
2963 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2964                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
2965                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2966 {
2967         struct i40e_aq_desc desc;
2968         struct i40e_aqc_macvlan *cmd =
2969                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2970         enum i40e_status_code status;
2971         u16 buf_size;
2972
2973         if (count == 0 || !mv_list || !hw)
2974                 return I40E_ERR_PARAM;
2975
2976         buf_size = count * sizeof(*mv_list);
2977
2978         /* prep the rest of the request */
2979         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2980         cmd->num_addresses = CPU_TO_LE16(count);
2981         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2982         cmd->seid[1] = 0;
2983         cmd->seid[2] = 0;
2984
2985         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2986         if (buf_size > I40E_AQ_LARGE_BUF)
2987                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2988
2989         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2990                                        cmd_details);
2991
2992         return status;
2993 }
2994
2995 /**
2996  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
2997  * @hw: pointer to the hw struct
2998  * @opcode: AQ opcode for add or delete mirror rule
2999  * @sw_seid: Switch SEID (to which rule refers)
3000  * @rule_type: Rule Type (ingress/egress/VLAN)
3001  * @id: Destination VSI SEID or Rule ID
3002  * @count: length of the list
3003  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3004  * @cmd_details: pointer to command details structure or NULL
3005  * @rule_id: Rule ID returned from FW
3006  * @rule_used: Number of rules used in internal switch
3007  * @rule_free: Number of rules free in internal switch
3008  *
3009  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3010  * VEBs/VEPA elements only
3011  **/
3012 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3013                         u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3014                         u16 count, __le16 *mr_list,
3015                         struct i40e_asq_cmd_details *cmd_details,
3016                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3017 {
3018         struct i40e_aq_desc desc;
3019         struct i40e_aqc_add_delete_mirror_rule *cmd =
3020                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3021         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3022         (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3023         enum i40e_status_code status;
3024         u16 buf_size;
3025
3026         buf_size = count * sizeof(*mr_list);
3027
3028         /* prep the rest of the request */
3029         i40e_fill_default_direct_cmd_desc(&desc, opcode);
3030         cmd->seid = CPU_TO_LE16(sw_seid);
3031         cmd->rule_type = CPU_TO_LE16(rule_type &
3032                                      I40E_AQC_MIRROR_RULE_TYPE_MASK);
3033         cmd->num_entries = CPU_TO_LE16(count);
3034         /* Dest VSI for add, rule_id for delete */
3035         cmd->destination = CPU_TO_LE16(id);
3036         if (mr_list) {
3037                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3038                                                 I40E_AQ_FLAG_RD));
3039                 if (buf_size > I40E_AQ_LARGE_BUF)
3040                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3041         }
3042
3043         status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3044                                        cmd_details);
3045         if (status == I40E_SUCCESS ||
3046             hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3047                 if (rule_id)
3048                         *rule_id = LE16_TO_CPU(resp->rule_id);
3049                 if (rules_used)
3050                         *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3051                 if (rules_free)
3052                         *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3053         }
3054         return status;
3055 }
3056
3057 /**
3058  * i40e_aq_add_mirrorrule - add a mirror rule
3059  * @hw: pointer to the hw struct
3060  * @sw_seid: Switch SEID (to which rule refers)
3061  * @rule_type: Rule Type (ingress/egress/VLAN)
3062  * @dest_vsi: SEID of VSI to which packets will be mirrored
3063  * @count: length of the list
3064  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3065  * @cmd_details: pointer to command details structure or NULL
3066  * @rule_id: Rule ID returned from FW
3067  * @rule_used: Number of rules used in internal switch
3068  * @rule_free: Number of rules free in internal switch
3069  *
3070  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3071  **/
3072 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3073                         u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3074                         struct i40e_asq_cmd_details *cmd_details,
3075                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3076 {
3077         if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3078             rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3079                 if (count == 0 || !mr_list)
3080                         return I40E_ERR_PARAM;
3081         }
3082
3083         return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3084                                   rule_type, dest_vsi, count, mr_list,
3085                                   cmd_details, rule_id, rules_used, rules_free);
3086 }
3087
3088 /**
3089  * i40e_aq_delete_mirrorrule - delete a mirror rule
3090  * @hw: pointer to the hw struct
3091  * @sw_seid: Switch SEID (to which rule refers)
3092  * @rule_type: Rule Type (ingress/egress/VLAN)
3093  * @count: length of the list
3094  * @rule_id: Rule ID that is returned in the receive desc as part of
3095  *              add_mirrorrule.
3096  * @mr_list: list of mirrored VLAN IDs to be removed
3097  * @cmd_details: pointer to command details structure or NULL
3098  * @rule_used: Number of rules used in internal switch
3099  * @rule_free: Number of rules free in internal switch
3100  *
3101  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3102  **/
3103 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3104                         u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3105                         struct i40e_asq_cmd_details *cmd_details,
3106                         u16 *rules_used, u16 *rules_free)
3107 {
3108         /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3109         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3110                 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3111                  * mirroring. For other rule_type, count and rule_type should
3112                  * not matter.
3113                  */
3114                 if (count == 0 || !mr_list)
3115                         return I40E_ERR_PARAM;
3116         }
3117
3118         return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3119                                   rule_type, rule_id, count, mr_list,
3120                                   cmd_details, NULL, rules_used, rules_free);
3121 }
3122
3123 /**
3124  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3125  * @hw: pointer to the hw struct
3126  * @seid: VSI for the vlan filters
3127  * @v_list: list of vlan filters to be added
3128  * @count: length of the list
3129  * @cmd_details: pointer to command details structure or NULL
3130  **/
3131 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3132                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3133                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3134 {
3135         struct i40e_aq_desc desc;
3136         struct i40e_aqc_macvlan *cmd =
3137                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3138         enum i40e_status_code status;
3139         u16 buf_size;
3140
3141         if (count == 0 || !v_list || !hw)
3142                 return I40E_ERR_PARAM;
3143
3144         buf_size = count * sizeof(*v_list);
3145
3146         /* prep the rest of the request */
3147         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3148         cmd->num_addresses = CPU_TO_LE16(count);
3149         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3150         cmd->seid[1] = 0;
3151         cmd->seid[2] = 0;
3152
3153         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3154         if (buf_size > I40E_AQ_LARGE_BUF)
3155                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3156
3157         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3158                                        cmd_details);
3159
3160         return status;
3161 }
3162
3163 /**
3164  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3165  * @hw: pointer to the hw struct
3166  * @seid: VSI for the vlan filters
3167  * @v_list: list of macvlans to be removed
3168  * @count: length of the list
3169  * @cmd_details: pointer to command details structure or NULL
3170  **/
3171 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3172                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3173                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3174 {
3175         struct i40e_aq_desc desc;
3176         struct i40e_aqc_macvlan *cmd =
3177                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3178         enum i40e_status_code status;
3179         u16 buf_size;
3180
3181         if (count == 0 || !v_list || !hw)
3182                 return I40E_ERR_PARAM;
3183
3184         buf_size = count * sizeof(*v_list);
3185
3186         /* prep the rest of the request */
3187         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3188         cmd->num_addresses = CPU_TO_LE16(count);
3189         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3190         cmd->seid[1] = 0;
3191         cmd->seid[2] = 0;
3192
3193         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3194         if (buf_size > I40E_AQ_LARGE_BUF)
3195                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3196
3197         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3198                                        cmd_details);
3199
3200         return status;
3201 }
3202
3203 /**
3204  * i40e_aq_send_msg_to_vf
3205  * @hw: pointer to the hardware structure
3206  * @vfid: vf id to send msg
3207  * @v_opcode: opcodes for VF-PF communication
3208  * @v_retval: return error code
3209  * @msg: pointer to the msg buffer
3210  * @msglen: msg length
3211  * @cmd_details: pointer to command details
3212  *
3213  * send msg to vf
3214  **/
3215 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3216                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3217                                 struct i40e_asq_cmd_details *cmd_details)
3218 {
3219         struct i40e_aq_desc desc;
3220         struct i40e_aqc_pf_vf_message *cmd =
3221                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3222         enum i40e_status_code status;
3223
3224         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3225         cmd->id = CPU_TO_LE32(vfid);
3226         desc.cookie_high = CPU_TO_LE32(v_opcode);
3227         desc.cookie_low = CPU_TO_LE32(v_retval);
3228         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3229         if (msglen) {
3230                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3231                                                 I40E_AQ_FLAG_RD));
3232                 if (msglen > I40E_AQ_LARGE_BUF)
3233                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3234                 desc.datalen = CPU_TO_LE16(msglen);
3235         }
3236         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3237
3238         return status;
3239 }
3240
3241 /**
3242  * i40e_aq_debug_read_register
3243  * @hw: pointer to the hw struct
3244  * @reg_addr: register address
3245  * @reg_val: register value
3246  * @cmd_details: pointer to command details structure or NULL
3247  *
3248  * Read the register using the admin queue commands
3249  **/
3250 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3251                                 u32 reg_addr, u64 *reg_val,
3252                                 struct i40e_asq_cmd_details *cmd_details)
3253 {
3254         struct i40e_aq_desc desc;
3255         struct i40e_aqc_debug_reg_read_write *cmd_resp =
3256                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3257         enum i40e_status_code status;
3258
3259         if (reg_val == NULL)
3260                 return I40E_ERR_PARAM;
3261
3262         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3263
3264         cmd_resp->address = CPU_TO_LE32(reg_addr);
3265
3266         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3267
3268         if (status == I40E_SUCCESS) {
3269                 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3270                            (u64)LE32_TO_CPU(cmd_resp->value_low);
3271         }
3272
3273         return status;
3274 }
3275
3276 /**
3277  * i40e_aq_debug_write_register
3278  * @hw: pointer to the hw struct
3279  * @reg_addr: register address
3280  * @reg_val: register value
3281  * @cmd_details: pointer to command details structure or NULL
3282  *
3283  * Write to a register using the admin queue commands
3284  **/
3285 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3286                                 u32 reg_addr, u64 reg_val,
3287                                 struct i40e_asq_cmd_details *cmd_details)
3288 {
3289         struct i40e_aq_desc desc;
3290         struct i40e_aqc_debug_reg_read_write *cmd =
3291                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3292         enum i40e_status_code status;
3293
3294         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3295
3296         cmd->address = CPU_TO_LE32(reg_addr);
3297         cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3298         cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3299
3300         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3301
3302         return status;
3303 }
3304
3305 /**
3306  * i40e_aq_request_resource
3307  * @hw: pointer to the hw struct
3308  * @resource: resource id
3309  * @access: access type
3310  * @sdp_number: resource number
3311  * @timeout: the maximum time in ms that the driver may hold the resource
3312  * @cmd_details: pointer to command details structure or NULL
3313  *
3314  * requests common resource using the admin queue commands
3315  **/
3316 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3317                                 enum i40e_aq_resources_ids resource,
3318                                 enum i40e_aq_resource_access_type access,
3319                                 u8 sdp_number, u64 *timeout,
3320                                 struct i40e_asq_cmd_details *cmd_details)
3321 {
3322         struct i40e_aq_desc desc;
3323         struct i40e_aqc_request_resource *cmd_resp =
3324                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3325         enum i40e_status_code status;
3326
3327         DEBUGFUNC("i40e_aq_request_resource");
3328
3329         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3330
3331         cmd_resp->resource_id = CPU_TO_LE16(resource);
3332         cmd_resp->access_type = CPU_TO_LE16(access);
3333         cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3334
3335         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3336         /* The completion specifies the maximum time in ms that the driver
3337          * may hold the resource in the Timeout field.
3338          * If the resource is held by someone else, the command completes with
3339          * busy return value and the timeout field indicates the maximum time
3340          * the current owner of the resource has to free it.
3341          */
3342         if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3343                 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3344
3345         return status;
3346 }
3347
3348 /**
3349  * i40e_aq_release_resource
3350  * @hw: pointer to the hw struct
3351  * @resource: resource id
3352  * @sdp_number: resource number
3353  * @cmd_details: pointer to command details structure or NULL
3354  *
3355  * release common resource using the admin queue commands
3356  **/
3357 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3358                                 enum i40e_aq_resources_ids resource,
3359                                 u8 sdp_number,
3360                                 struct i40e_asq_cmd_details *cmd_details)
3361 {
3362         struct i40e_aq_desc desc;
3363         struct i40e_aqc_request_resource *cmd =
3364                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3365         enum i40e_status_code status;
3366
3367         DEBUGFUNC("i40e_aq_release_resource");
3368
3369         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3370
3371         cmd->resource_id = CPU_TO_LE16(resource);
3372         cmd->resource_number = CPU_TO_LE32(sdp_number);
3373
3374         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3375
3376         return status;
3377 }
3378
3379 /**
3380  * i40e_aq_read_nvm
3381  * @hw: pointer to the hw struct
3382  * @module_pointer: module pointer location in words from the NVM beginning
3383  * @offset: byte offset from the module beginning
3384  * @length: length of the section to be read (in bytes from the offset)
3385  * @data: command buffer (size [bytes] = length)
3386  * @last_command: tells if this is the last command in a series
3387  * @cmd_details: pointer to command details structure or NULL
3388  *
3389  * Read the NVM using the admin queue commands
3390  **/
3391 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3392                                 u32 offset, u16 length, void *data,
3393                                 bool last_command,
3394                                 struct i40e_asq_cmd_details *cmd_details)
3395 {
3396         struct i40e_aq_desc desc;
3397         struct i40e_aqc_nvm_update *cmd =
3398                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3399         enum i40e_status_code status;
3400
3401         DEBUGFUNC("i40e_aq_read_nvm");
3402
3403         /* In offset the highest byte must be zeroed. */
3404         if (offset & 0xFF000000) {
3405                 status = I40E_ERR_PARAM;
3406                 goto i40e_aq_read_nvm_exit;
3407         }
3408
3409         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3410
3411         /* If this is the last command in a series, set the proper flag. */
3412         if (last_command)
3413                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3414         cmd->module_pointer = module_pointer;
3415         cmd->offset = CPU_TO_LE32(offset);
3416         cmd->length = CPU_TO_LE16(length);
3417
3418         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3419         if (length > I40E_AQ_LARGE_BUF)
3420                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3421
3422         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3423
3424 i40e_aq_read_nvm_exit:
3425         return status;
3426 }
3427
3428 /**
3429  * i40e_aq_read_nvm_config - read an nvm config block
3430  * @hw: pointer to the hw struct
3431  * @cmd_flags: NVM access admin command bits
3432  * @field_id: field or feature id
3433  * @data: buffer for result
3434  * @buf_size: buffer size
3435  * @element_count: pointer to count of elements read by FW
3436  * @cmd_details: pointer to command details structure or NULL
3437  **/
3438 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3439                                 u8 cmd_flags, u32 field_id, void *data,
3440                                 u16 buf_size, u16 *element_count,
3441                                 struct i40e_asq_cmd_details *cmd_details)
3442 {
3443         struct i40e_aq_desc desc;
3444         struct i40e_aqc_nvm_config_read *cmd =
3445                 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3446         enum i40e_status_code status;
3447
3448         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3449         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3450         if (buf_size > I40E_AQ_LARGE_BUF)
3451                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3452
3453         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3454         cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3455         if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3456                 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3457         else
3458                 cmd->element_id_msw = 0;
3459
3460         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3461
3462         if (!status && element_count)
3463                 *element_count = LE16_TO_CPU(cmd->element_count);
3464
3465         return status;
3466 }
3467
3468 /**
3469  * i40e_aq_write_nvm_config - write an nvm config block
3470  * @hw: pointer to the hw struct
3471  * @cmd_flags: NVM access admin command bits
3472  * @data: buffer for result
3473  * @buf_size: buffer size
3474  * @element_count: count of elements to be written
3475  * @cmd_details: pointer to command details structure or NULL
3476  **/
3477 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3478                                 u8 cmd_flags, void *data, u16 buf_size,
3479                                 u16 element_count,
3480                                 struct i40e_asq_cmd_details *cmd_details)
3481 {
3482         struct i40e_aq_desc desc;
3483         struct i40e_aqc_nvm_config_write *cmd =
3484                 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3485         enum i40e_status_code status;
3486
3487         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3488         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3489         if (buf_size > I40E_AQ_LARGE_BUF)
3490                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3491
3492         cmd->element_count = CPU_TO_LE16(element_count);
3493         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3494         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3495
3496         return status;
3497 }
3498
3499 /**
3500  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3501  * @hw: pointer to the hw struct
3502  * @cmd_details: pointer to command details structure or NULL
3503  **/
3504 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3505                                 void *buff, u16 buff_size,
3506                                 struct i40e_asq_cmd_details *cmd_details)
3507 {
3508         struct i40e_aq_desc desc;
3509         enum i40e_status_code status;
3510
3511         UNREFERENCED_2PARAMETER(buff, buff_size);
3512
3513         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3514         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3515         if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3516                 status = I40E_ERR_NOT_IMPLEMENTED;
3517
3518         return status;
3519 }
3520
3521 /**
3522  * i40e_aq_erase_nvm
3523  * @hw: pointer to the hw struct
3524  * @module_pointer: module pointer location in words from the NVM beginning
3525  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3526  * @length: length of the section to be erased (expressed in 4 KB)
3527  * @last_command: tells if this is the last command in a series
3528  * @cmd_details: pointer to command details structure or NULL
3529  *
3530  * Erase the NVM sector using the admin queue commands
3531  **/
3532 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3533                                 u32 offset, u16 length, bool last_command,
3534                                 struct i40e_asq_cmd_details *cmd_details)
3535 {
3536         struct i40e_aq_desc desc;
3537         struct i40e_aqc_nvm_update *cmd =
3538                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3539         enum i40e_status_code status;
3540
3541         DEBUGFUNC("i40e_aq_erase_nvm");
3542
3543         /* In offset the highest byte must be zeroed. */
3544         if (offset & 0xFF000000) {
3545                 status = I40E_ERR_PARAM;
3546                 goto i40e_aq_erase_nvm_exit;
3547         }
3548
3549         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3550
3551         /* If this is the last command in a series, set the proper flag. */
3552         if (last_command)
3553                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3554         cmd->module_pointer = module_pointer;
3555         cmd->offset = CPU_TO_LE32(offset);
3556         cmd->length = CPU_TO_LE16(length);
3557
3558         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3559
3560 i40e_aq_erase_nvm_exit:
3561         return status;
3562 }
3563
3564 /**
3565  * i40e_parse_discover_capabilities
3566  * @hw: pointer to the hw struct
3567  * @buff: pointer to a buffer containing device/function capability records
3568  * @cap_count: number of capability records in the list
3569  * @list_type_opc: type of capabilities list to parse
3570  *
3571  * Parse the device/function capabilities list.
3572  **/
3573 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3574                                      u32 cap_count,
3575                                      enum i40e_admin_queue_opc list_type_opc)
3576 {
3577         struct i40e_aqc_list_capabilities_element_resp *cap;
3578         u32 valid_functions, num_functions;
3579         u32 number, logical_id, phys_id;
3580         struct i40e_hw_capabilities *p;
3581         u8 major_rev;
3582         u32 i = 0;
3583         u16 id;
3584
3585         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3586
3587         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3588                 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3589         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3590                 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3591         else
3592                 return;
3593
3594         for (i = 0; i < cap_count; i++, cap++) {
3595                 id = LE16_TO_CPU(cap->id);
3596                 number = LE32_TO_CPU(cap->number);
3597                 logical_id = LE32_TO_CPU(cap->logical_id);
3598                 phys_id = LE32_TO_CPU(cap->phys_id);
3599                 major_rev = cap->major_rev;
3600
3601                 switch (id) {
3602                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3603                         p->switch_mode = number;
3604                         i40e_debug(hw, I40E_DEBUG_INIT,
3605                                    "HW Capability: Switch mode = %d\n",
3606                                    p->switch_mode);
3607                         break;
3608                 case I40E_AQ_CAP_ID_MNG_MODE:
3609                         p->management_mode = number;
3610                         i40e_debug(hw, I40E_DEBUG_INIT,
3611                                    "HW Capability: Management Mode = %d\n",
3612                                    p->management_mode);
3613                         break;
3614                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3615                         p->npar_enable = number;
3616                         i40e_debug(hw, I40E_DEBUG_INIT,
3617                                    "HW Capability: NPAR enable = %d\n",
3618                                    p->npar_enable);
3619                         break;
3620                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3621                         p->os2bmc = number;
3622                         i40e_debug(hw, I40E_DEBUG_INIT,
3623                                    "HW Capability: OS2BMC = %d\n", p->os2bmc);
3624                         break;
3625                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3626                         p->valid_functions = number;
3627                         i40e_debug(hw, I40E_DEBUG_INIT,
3628                                    "HW Capability: Valid Functions = %d\n",
3629                                    p->valid_functions);
3630                         break;
3631                 case I40E_AQ_CAP_ID_SRIOV:
3632                         if (number == 1)
3633                                 p->sr_iov_1_1 = true;
3634                         i40e_debug(hw, I40E_DEBUG_INIT,
3635                                    "HW Capability: SR-IOV = %d\n",
3636                                    p->sr_iov_1_1);
3637                         break;
3638                 case I40E_AQ_CAP_ID_VF:
3639                         p->num_vfs = number;
3640                         p->vf_base_id = logical_id;
3641                         i40e_debug(hw, I40E_DEBUG_INIT,
3642                                    "HW Capability: VF count = %d\n",
3643                                    p->num_vfs);
3644                         i40e_debug(hw, I40E_DEBUG_INIT,
3645                                    "HW Capability: VF base_id = %d\n",
3646                                    p->vf_base_id);
3647                         break;
3648                 case I40E_AQ_CAP_ID_VMDQ:
3649                         if (number == 1)
3650                                 p->vmdq = true;
3651                         i40e_debug(hw, I40E_DEBUG_INIT,
3652                                    "HW Capability: VMDQ = %d\n", p->vmdq);
3653                         break;
3654                 case I40E_AQ_CAP_ID_8021QBG:
3655                         if (number == 1)
3656                                 p->evb_802_1_qbg = true;
3657                         i40e_debug(hw, I40E_DEBUG_INIT,
3658                                    "HW Capability: 802.1Qbg = %d\n", number);
3659                         break;
3660                 case I40E_AQ_CAP_ID_8021QBR:
3661                         if (number == 1)
3662                                 p->evb_802_1_qbh = true;
3663                         i40e_debug(hw, I40E_DEBUG_INIT,
3664                                    "HW Capability: 802.1Qbh = %d\n", number);
3665                         break;
3666                 case I40E_AQ_CAP_ID_VSI:
3667                         p->num_vsis = number;
3668                         i40e_debug(hw, I40E_DEBUG_INIT,
3669                                    "HW Capability: VSI count = %d\n",
3670                                    p->num_vsis);
3671                         break;
3672                 case I40E_AQ_CAP_ID_DCB:
3673                         if (number == 1) {
3674                                 p->dcb = true;
3675                                 p->enabled_tcmap = logical_id;
3676                                 p->maxtc = phys_id;
3677                         }
3678                         i40e_debug(hw, I40E_DEBUG_INIT,
3679                                    "HW Capability: DCB = %d\n", p->dcb);
3680                         i40e_debug(hw, I40E_DEBUG_INIT,
3681                                    "HW Capability: TC Mapping = %d\n",
3682                                    logical_id);
3683                         i40e_debug(hw, I40E_DEBUG_INIT,
3684                                    "HW Capability: TC Max = %d\n", p->maxtc);
3685                         break;
3686                 case I40E_AQ_CAP_ID_FCOE:
3687                         if (number == 1)
3688                                 p->fcoe = true;
3689                         i40e_debug(hw, I40E_DEBUG_INIT,
3690                                    "HW Capability: FCOE = %d\n", p->fcoe);
3691                         break;
3692                 case I40E_AQ_CAP_ID_ISCSI:
3693                         if (number == 1)
3694                                 p->iscsi = true;
3695                         i40e_debug(hw, I40E_DEBUG_INIT,
3696                                    "HW Capability: iSCSI = %d\n", p->iscsi);
3697                         break;
3698                 case I40E_AQ_CAP_ID_RSS:
3699                         p->rss = true;
3700                         p->rss_table_size = number;
3701                         p->rss_table_entry_width = logical_id;
3702                         i40e_debug(hw, I40E_DEBUG_INIT,
3703                                    "HW Capability: RSS = %d\n", p->rss);
3704                         i40e_debug(hw, I40E_DEBUG_INIT,
3705                                    "HW Capability: RSS table size = %d\n",
3706                                    p->rss_table_size);
3707                         i40e_debug(hw, I40E_DEBUG_INIT,
3708                                    "HW Capability: RSS table width = %d\n",
3709                                    p->rss_table_entry_width);
3710                         break;
3711                 case I40E_AQ_CAP_ID_RXQ:
3712                         p->num_rx_qp = number;
3713                         p->base_queue = phys_id;
3714                         i40e_debug(hw, I40E_DEBUG_INIT,
3715                                    "HW Capability: Rx QP = %d\n", number);
3716                         i40e_debug(hw, I40E_DEBUG_INIT,
3717                                    "HW Capability: base_queue = %d\n",
3718                                    p->base_queue);
3719                         break;
3720                 case I40E_AQ_CAP_ID_TXQ:
3721                         p->num_tx_qp = number;
3722                         p->base_queue = phys_id;
3723                         i40e_debug(hw, I40E_DEBUG_INIT,
3724                                    "HW Capability: Tx QP = %d\n", number);
3725                         i40e_debug(hw, I40E_DEBUG_INIT,
3726                                    "HW Capability: base_queue = %d\n",
3727                                    p->base_queue);
3728                         break;
3729                 case I40E_AQ_CAP_ID_MSIX:
3730                         p->num_msix_vectors = number;
3731                         i40e_debug(hw, I40E_DEBUG_INIT,
3732                                    "HW Capability: MSIX vector count = %d\n",
3733                                    p->num_msix_vectors);
3734                         break;
3735                 case I40E_AQ_CAP_ID_VF_MSIX:
3736                         p->num_msix_vectors_vf = number;
3737                         i40e_debug(hw, I40E_DEBUG_INIT,
3738                                    "HW Capability: MSIX VF vector count = %d\n",
3739                                    p->num_msix_vectors_vf);
3740                         break;
3741                 case I40E_AQ_CAP_ID_FLEX10:
3742                         if (major_rev == 1) {
3743                                 if (number == 1) {
3744                                         p->flex10_enable = true;
3745                                         p->flex10_capable = true;
3746                                 }
3747                         } else {
3748                                 /* Capability revision >= 2 */
3749                                 if (number & 1)
3750                                         p->flex10_enable = true;
3751                                 if (number & 2)
3752                                         p->flex10_capable = true;
3753                         }
3754                         p->flex10_mode = logical_id;
3755                         p->flex10_status = phys_id;
3756                         i40e_debug(hw, I40E_DEBUG_INIT,
3757                                    "HW Capability: Flex10 mode = %d\n",
3758                                    p->flex10_mode);
3759                         i40e_debug(hw, I40E_DEBUG_INIT,
3760                                    "HW Capability: Flex10 status = %d\n",
3761                                    p->flex10_status);
3762                         break;
3763                 case I40E_AQ_CAP_ID_CEM:
3764                         if (number == 1)
3765                                 p->mgmt_cem = true;
3766                         i40e_debug(hw, I40E_DEBUG_INIT,
3767                                    "HW Capability: CEM = %d\n", p->mgmt_cem);
3768                         break;
3769                 case I40E_AQ_CAP_ID_IWARP:
3770                         if (number == 1)
3771                                 p->iwarp = true;
3772                         i40e_debug(hw, I40E_DEBUG_INIT,
3773                                    "HW Capability: iWARP = %d\n", p->iwarp);
3774                         break;
3775                 case I40E_AQ_CAP_ID_LED:
3776                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3777                                 p->led[phys_id] = true;
3778                         i40e_debug(hw, I40E_DEBUG_INIT,
3779                                    "HW Capability: LED - PIN %d\n", phys_id);
3780                         break;
3781                 case I40E_AQ_CAP_ID_SDP:
3782                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3783                                 p->sdp[phys_id] = true;
3784                         i40e_debug(hw, I40E_DEBUG_INIT,
3785                                    "HW Capability: SDP - PIN %d\n", phys_id);
3786                         break;
3787                 case I40E_AQ_CAP_ID_MDIO:
3788                         if (number == 1) {
3789                                 p->mdio_port_num = phys_id;
3790                                 p->mdio_port_mode = logical_id;
3791                         }
3792                         i40e_debug(hw, I40E_DEBUG_INIT,
3793                                    "HW Capability: MDIO port number = %d\n",
3794                                    p->mdio_port_num);
3795                         i40e_debug(hw, I40E_DEBUG_INIT,
3796                                    "HW Capability: MDIO port mode = %d\n",
3797                                    p->mdio_port_mode);
3798                         break;
3799                 case I40E_AQ_CAP_ID_1588:
3800                         if (number == 1)
3801                                 p->ieee_1588 = true;
3802                         i40e_debug(hw, I40E_DEBUG_INIT,
3803                                    "HW Capability: IEEE 1588 = %d\n",
3804                                    p->ieee_1588);
3805                         break;
3806                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3807                         p->fd = true;
3808                         p->fd_filters_guaranteed = number;
3809                         p->fd_filters_best_effort = logical_id;
3810                         i40e_debug(hw, I40E_DEBUG_INIT,
3811                                    "HW Capability: Flow Director = 1\n");
3812                         i40e_debug(hw, I40E_DEBUG_INIT,
3813                                    "HW Capability: Guaranteed FD filters = %d\n",
3814                                    p->fd_filters_guaranteed);
3815                         break;
3816                 case I40E_AQ_CAP_ID_WSR_PROT:
3817                         p->wr_csr_prot = (u64)number;
3818                         p->wr_csr_prot |= (u64)logical_id << 32;
3819                         i40e_debug(hw, I40E_DEBUG_INIT,
3820                                    "HW Capability: wr_csr_prot = 0x%llX\n\n",
3821                                    (p->wr_csr_prot & 0xffff));
3822                         break;
3823                 case I40E_AQ_CAP_ID_NVM_MGMT:
3824                         if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3825                                 p->sec_rev_disabled = true;
3826                         if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3827                                 p->update_disabled = true;
3828                         break;
3829 #ifdef X722_SUPPORT
3830                 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3831                         hw->num_wol_proxy_filters = (u16)number;
3832                         hw->wol_proxy_vsi_seid = (u16)logical_id;
3833                         p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3834                         if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3835                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3836                         else
3837                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3838                         p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3839                         i40e_debug(hw, I40E_DEBUG_INIT,
3840                                    "HW Capability: WOL proxy filters = %d\n",
3841                                    hw->num_wol_proxy_filters);
3842                         break;
3843 #endif
3844                 default:
3845                         break;
3846                 }
3847         }
3848
3849         if (p->fcoe)
3850                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3851
3852         /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3853         p->fcoe = false;
3854
3855         /* count the enabled ports (aka the "not disabled" ports) */
3856         hw->num_ports = 0;
3857         for (i = 0; i < 4; i++) {
3858                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3859                 u64 port_cfg = 0;
3860
3861                 /* use AQ read to get the physical register offset instead
3862                  * of the port relative offset
3863                  */
3864                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3865                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3866                         hw->num_ports++;
3867         }
3868
3869         valid_functions = p->valid_functions;
3870         num_functions = 0;
3871         while (valid_functions) {
3872                 if (valid_functions & 1)
3873                         num_functions++;
3874                 valid_functions >>= 1;
3875         }
3876
3877         /* partition id is 1-based, and functions are evenly spread
3878          * across the ports as partitions
3879          */
3880         hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3881         hw->num_partitions = num_functions / hw->num_ports;
3882
3883         /* additional HW specific goodies that might
3884          * someday be HW version specific
3885          */
3886         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3887 }
3888
3889 /**
3890  * i40e_aq_discover_capabilities
3891  * @hw: pointer to the hw struct
3892  * @buff: a virtual buffer to hold the capabilities
3893  * @buff_size: Size of the virtual buffer
3894  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3895  * @list_type_opc: capabilities type to discover - pass in the command opcode
3896  * @cmd_details: pointer to command details structure or NULL
3897  *
3898  * Get the device capabilities descriptions from the firmware
3899  **/
3900 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3901                                 void *buff, u16 buff_size, u16 *data_size,
3902                                 enum i40e_admin_queue_opc list_type_opc,
3903                                 struct i40e_asq_cmd_details *cmd_details)
3904 {
3905         struct i40e_aqc_list_capabilites *cmd;
3906         struct i40e_aq_desc desc;
3907         enum i40e_status_code status = I40E_SUCCESS;
3908
3909         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3910
3911         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3912                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3913                 status = I40E_ERR_PARAM;
3914                 goto exit;
3915         }
3916
3917         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3918
3919         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3920         if (buff_size > I40E_AQ_LARGE_BUF)
3921                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3922
3923         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3924         *data_size = LE16_TO_CPU(desc.datalen);
3925
3926         if (status)
3927                 goto exit;
3928
3929         i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3930                                          list_type_opc);
3931
3932 exit:
3933         return status;
3934 }
3935
3936 /**
3937  * i40e_aq_update_nvm
3938  * @hw: pointer to the hw struct
3939  * @module_pointer: module pointer location in words from the NVM beginning
3940  * @offset: byte offset from the module beginning
3941  * @length: length of the section to be written (in bytes from the offset)
3942  * @data: command buffer (size [bytes] = length)
3943  * @last_command: tells if this is the last command in a series
3944  * @cmd_details: pointer to command details structure or NULL
3945  *
3946  * Update the NVM using the admin queue commands
3947  **/
3948 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3949                                 u32 offset, u16 length, void *data,
3950                                 bool last_command,
3951                                 struct i40e_asq_cmd_details *cmd_details)
3952 {
3953         struct i40e_aq_desc desc;
3954         struct i40e_aqc_nvm_update *cmd =
3955                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3956         enum i40e_status_code status;
3957
3958         DEBUGFUNC("i40e_aq_update_nvm");
3959
3960         /* In offset the highest byte must be zeroed. */
3961         if (offset & 0xFF000000) {
3962                 status = I40E_ERR_PARAM;
3963                 goto i40e_aq_update_nvm_exit;
3964         }
3965
3966         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3967
3968         /* If this is the last command in a series, set the proper flag. */
3969         if (last_command)
3970                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3971         cmd->module_pointer = module_pointer;
3972         cmd->offset = CPU_TO_LE32(offset);
3973         cmd->length = CPU_TO_LE16(length);
3974
3975         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3976         if (length > I40E_AQ_LARGE_BUF)
3977                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3978
3979         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3980
3981 i40e_aq_update_nvm_exit:
3982         return status;
3983 }
3984
3985 /**
3986  * i40e_aq_get_lldp_mib
3987  * @hw: pointer to the hw struct
3988  * @bridge_type: type of bridge requested
3989  * @mib_type: Local, Remote or both Local and Remote MIBs
3990  * @buff: pointer to a user supplied buffer to store the MIB block
3991  * @buff_size: size of the buffer (in bytes)
3992  * @local_len : length of the returned Local LLDP MIB
3993  * @remote_len: length of the returned Remote LLDP MIB
3994  * @cmd_details: pointer to command details structure or NULL
3995  *
3996  * Requests the complete LLDP MIB (entire packet).
3997  **/
3998 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3999                                 u8 mib_type, void *buff, u16 buff_size,
4000                                 u16 *local_len, u16 *remote_len,
4001                                 struct i40e_asq_cmd_details *cmd_details)
4002 {
4003         struct i40e_aq_desc desc;
4004         struct i40e_aqc_lldp_get_mib *cmd =
4005                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4006         struct i40e_aqc_lldp_get_mib *resp =
4007                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4008         enum i40e_status_code status;
4009
4010         if (buff_size == 0 || !buff)
4011                 return I40E_ERR_PARAM;
4012
4013         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4014         /* Indirect Command */
4015         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4016
4017         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4018         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4019                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4020
4021         desc.datalen = CPU_TO_LE16(buff_size);
4022
4023         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4024         if (buff_size > I40E_AQ_LARGE_BUF)
4025                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4026
4027         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4028         if (!status) {
4029                 if (local_len != NULL)
4030                         *local_len = LE16_TO_CPU(resp->local_len);
4031                 if (remote_len != NULL)
4032                         *remote_len = LE16_TO_CPU(resp->remote_len);
4033         }
4034
4035         return status;
4036 }
4037
4038  /**
4039  * i40e_aq_set_lldp_mib - Set the LLDP MIB
4040  * @hw: pointer to the hw struct
4041  * @mib_type: Local, Remote or both Local and Remote MIBs
4042  * @buff: pointer to a user supplied buffer to store the MIB block
4043  * @buff_size: size of the buffer (in bytes)
4044  * @cmd_details: pointer to command details structure or NULL
4045  *
4046  * Set the LLDP MIB.
4047  **/
4048 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4049                                 u8 mib_type, void *buff, u16 buff_size,
4050                                 struct i40e_asq_cmd_details *cmd_details)
4051 {
4052         struct i40e_aq_desc desc;
4053         struct i40e_aqc_lldp_set_local_mib *cmd =
4054                 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4055         enum i40e_status_code status;
4056
4057         if (buff_size == 0 || !buff)
4058                 return I40E_ERR_PARAM;
4059
4060         i40e_fill_default_direct_cmd_desc(&desc,
4061                                 i40e_aqc_opc_lldp_set_local_mib);
4062         /* Indirect Command */
4063         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4064         if (buff_size > I40E_AQ_LARGE_BUF)
4065                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4066         desc.datalen = CPU_TO_LE16(buff_size);
4067
4068         cmd->type = mib_type;
4069         cmd->length = CPU_TO_LE16(buff_size);
4070         cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4071         cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4072
4073         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4074         return status;
4075 }
4076
4077 /**
4078  * i40e_aq_cfg_lldp_mib_change_event
4079  * @hw: pointer to the hw struct
4080  * @enable_update: Enable or Disable event posting
4081  * @cmd_details: pointer to command details structure or NULL
4082  *
4083  * Enable or Disable posting of an event on ARQ when LLDP MIB
4084  * associated with the interface changes
4085  **/
4086 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4087                                 bool enable_update,
4088                                 struct i40e_asq_cmd_details *cmd_details)
4089 {
4090         struct i40e_aq_desc desc;
4091         struct i40e_aqc_lldp_update_mib *cmd =
4092                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4093         enum i40e_status_code status;
4094
4095         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4096
4097         if (!enable_update)
4098                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4099
4100         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4101
4102         return status;
4103 }
4104
4105 /**
4106  * i40e_aq_add_lldp_tlv
4107  * @hw: pointer to the hw struct
4108  * @bridge_type: type of bridge
4109  * @buff: buffer with TLV to add
4110  * @buff_size: length of the buffer
4111  * @tlv_len: length of the TLV to be added
4112  * @mib_len: length of the LLDP MIB returned in response
4113  * @cmd_details: pointer to command details structure or NULL
4114  *
4115  * Add the specified TLV to LLDP Local MIB for the given bridge type,
4116  * it is responsibility of the caller to make sure that the TLV is not
4117  * already present in the LLDPDU.
4118  * In return firmware will write the complete LLDP MIB with the newly
4119  * added TLV in the response buffer.
4120  **/
4121 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4122                                 void *buff, u16 buff_size, u16 tlv_len,
4123                                 u16 *mib_len,
4124                                 struct i40e_asq_cmd_details *cmd_details)
4125 {
4126         struct i40e_aq_desc desc;
4127         struct i40e_aqc_lldp_add_tlv *cmd =
4128                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4129         enum i40e_status_code status;
4130
4131         if (buff_size == 0 || !buff || tlv_len == 0)
4132                 return I40E_ERR_PARAM;
4133
4134         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4135
4136         /* Indirect Command */
4137         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4138         if (buff_size > I40E_AQ_LARGE_BUF)
4139                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4140         desc.datalen = CPU_TO_LE16(buff_size);
4141
4142         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4143                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4144         cmd->len = CPU_TO_LE16(tlv_len);
4145
4146         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4147         if (!status) {
4148                 if (mib_len != NULL)
4149                         *mib_len = LE16_TO_CPU(desc.datalen);
4150         }
4151
4152         return status;
4153 }
4154
4155 /**
4156  * i40e_aq_update_lldp_tlv
4157  * @hw: pointer to the hw struct
4158  * @bridge_type: type of bridge
4159  * @buff: buffer with TLV to update
4160  * @buff_size: size of the buffer holding original and updated TLVs
4161  * @old_len: Length of the Original TLV
4162  * @new_len: Length of the Updated TLV
4163  * @offset: offset of the updated TLV in the buff
4164  * @mib_len: length of the returned LLDP MIB
4165  * @cmd_details: pointer to command details structure or NULL
4166  *
4167  * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4168  * Firmware will place the complete LLDP MIB in response buffer with the
4169  * updated TLV.
4170  **/
4171 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4172                                 u8 bridge_type, void *buff, u16 buff_size,
4173                                 u16 old_len, u16 new_len, u16 offset,
4174                                 u16 *mib_len,
4175                                 struct i40e_asq_cmd_details *cmd_details)
4176 {
4177         struct i40e_aq_desc desc;
4178         struct i40e_aqc_lldp_update_tlv *cmd =
4179                 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4180         enum i40e_status_code status;
4181
4182         if (buff_size == 0 || !buff || offset == 0 ||
4183             old_len == 0 || new_len == 0)
4184                 return I40E_ERR_PARAM;
4185
4186         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4187
4188         /* Indirect Command */
4189         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4190         if (buff_size > I40E_AQ_LARGE_BUF)
4191                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4192         desc.datalen = CPU_TO_LE16(buff_size);
4193
4194         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4195                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4196         cmd->old_len = CPU_TO_LE16(old_len);
4197         cmd->new_offset = CPU_TO_LE16(offset);
4198         cmd->new_len = CPU_TO_LE16(new_len);
4199
4200         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4201         if (!status) {
4202                 if (mib_len != NULL)
4203                         *mib_len = LE16_TO_CPU(desc.datalen);
4204         }
4205
4206         return status;
4207 }
4208
4209 /**
4210  * i40e_aq_delete_lldp_tlv
4211  * @hw: pointer to the hw struct
4212  * @bridge_type: type of bridge
4213  * @buff: pointer to a user supplied buffer that has the TLV
4214  * @buff_size: length of the buffer
4215  * @tlv_len: length of the TLV to be deleted
4216  * @mib_len: length of the returned LLDP MIB
4217  * @cmd_details: pointer to command details structure or NULL
4218  *
4219  * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4220  * The firmware places the entire LLDP MIB in the response buffer.
4221  **/
4222 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4223                                 u8 bridge_type, void *buff, u16 buff_size,
4224                                 u16 tlv_len, u16 *mib_len,
4225                                 struct i40e_asq_cmd_details *cmd_details)
4226 {
4227         struct i40e_aq_desc desc;
4228         struct i40e_aqc_lldp_add_tlv *cmd =
4229                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4230         enum i40e_status_code status;
4231
4232         if (buff_size == 0 || !buff)
4233                 return I40E_ERR_PARAM;
4234
4235         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4236
4237         /* Indirect Command */
4238         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4239         if (buff_size > I40E_AQ_LARGE_BUF)
4240                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4241         desc.datalen = CPU_TO_LE16(buff_size);
4242         cmd->len = CPU_TO_LE16(tlv_len);
4243         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4244                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4245
4246         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4247         if (!status) {
4248                 if (mib_len != NULL)
4249                         *mib_len = LE16_TO_CPU(desc.datalen);
4250         }
4251
4252         return status;
4253 }
4254
4255 /**
4256  * i40e_aq_stop_lldp
4257  * @hw: pointer to the hw struct
4258  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4259  * @cmd_details: pointer to command details structure or NULL
4260  *
4261  * Stop or Shutdown the embedded LLDP Agent
4262  **/
4263 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4264                                 struct i40e_asq_cmd_details *cmd_details)
4265 {
4266         struct i40e_aq_desc desc;
4267         struct i40e_aqc_lldp_stop *cmd =
4268                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4269         enum i40e_status_code status;
4270
4271         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4272
4273         if (shutdown_agent)
4274                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4275
4276         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4277
4278         return status;
4279 }
4280
4281 /**
4282  * i40e_aq_start_lldp
4283  * @hw: pointer to the hw struct
4284  * @cmd_details: pointer to command details structure or NULL
4285  *
4286  * Start the embedded LLDP Agent on all ports.
4287  **/
4288 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4289                                 struct i40e_asq_cmd_details *cmd_details)
4290 {
4291         struct i40e_aq_desc desc;
4292         struct i40e_aqc_lldp_start *cmd =
4293                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4294         enum i40e_status_code status;
4295
4296         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4297
4298         cmd->command = I40E_AQ_LLDP_AGENT_START;
4299
4300         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4301
4302         return status;
4303 }
4304
4305 /**
4306  * i40e_aq_get_cee_dcb_config
4307  * @hw: pointer to the hw struct
4308  * @buff: response buffer that stores CEE operational configuration
4309  * @buff_size: size of the buffer passed
4310  * @cmd_details: pointer to command details structure or NULL
4311  *
4312  * Get CEE DCBX mode operational configuration from firmware
4313  **/
4314 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4315                                 void *buff, u16 buff_size,
4316                                 struct i40e_asq_cmd_details *cmd_details)
4317 {
4318         struct i40e_aq_desc desc;
4319         enum i40e_status_code status;
4320
4321         if (buff_size == 0 || !buff)
4322                 return I40E_ERR_PARAM;
4323
4324         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4325
4326         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4327         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4328                                        cmd_details);
4329
4330         return status;
4331 }
4332
4333 /**
4334  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4335  * @hw: pointer to the hw struct
4336  * @start_agent: True if DCBx Agent needs to be Started
4337  *                              False if DCBx Agent needs to be Stopped
4338  * @cmd_details: pointer to command details structure or NULL
4339  *
4340  * Start/Stop the embedded dcbx Agent
4341  **/
4342 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4343                                 bool start_agent,
4344                                 struct i40e_asq_cmd_details *cmd_details)
4345 {
4346         struct i40e_aq_desc desc;
4347         struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4348                 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4349                                 &desc.params.raw;
4350         enum i40e_status_code status;
4351
4352         i40e_fill_default_direct_cmd_desc(&desc,
4353                                 i40e_aqc_opc_lldp_stop_start_spec_agent);
4354
4355         if (start_agent)
4356                 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4357
4358         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4359
4360         return status;
4361 }
4362
4363 /**
4364  * i40e_aq_add_udp_tunnel
4365  * @hw: pointer to the hw struct
4366  * @udp_port: the UDP port to add
4367  * @header_len: length of the tunneling header length in DWords
4368  * @protocol_index: protocol index type
4369  * @filter_index: pointer to filter index
4370  * @cmd_details: pointer to command details structure or NULL
4371  **/
4372 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4373                                 u16 udp_port, u8 protocol_index,
4374                                 u8 *filter_index,
4375                                 struct i40e_asq_cmd_details *cmd_details)
4376 {
4377         struct i40e_aq_desc desc;
4378         struct i40e_aqc_add_udp_tunnel *cmd =
4379                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4380         struct i40e_aqc_del_udp_tunnel_completion *resp =
4381                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4382         enum i40e_status_code status;
4383
4384         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4385
4386         cmd->udp_port = CPU_TO_LE16(udp_port);
4387         cmd->protocol_type = protocol_index;
4388
4389         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4390
4391         if (!status && filter_index)
4392                 *filter_index = resp->index;
4393
4394         return status;
4395 }
4396
4397 /**
4398  * i40e_aq_del_udp_tunnel
4399  * @hw: pointer to the hw struct
4400  * @index: filter index
4401  * @cmd_details: pointer to command details structure or NULL
4402  **/
4403 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4404                                 struct i40e_asq_cmd_details *cmd_details)
4405 {
4406         struct i40e_aq_desc desc;
4407         struct i40e_aqc_remove_udp_tunnel *cmd =
4408                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4409         enum i40e_status_code status;
4410
4411         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4412
4413         cmd->index = index;
4414
4415         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4416
4417         return status;
4418 }
4419
4420 /**
4421  * i40e_aq_get_switch_resource_alloc (0x0204)
4422  * @hw: pointer to the hw struct
4423  * @num_entries: pointer to u8 to store the number of resource entries returned
4424  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
4425  *        to store the resource information for all resource types.  Each
4426  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
4427  * @count: size, in bytes, of the buffer provided
4428  * @cmd_details: pointer to command details structure or NULL
4429  *
4430  * Query the resources allocated to a function.
4431  **/
4432 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4433                         u8 *num_entries,
4434                         struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4435                         u16 count,
4436                         struct i40e_asq_cmd_details *cmd_details)
4437 {
4438         struct i40e_aq_desc desc;
4439         struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4440                 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4441         enum i40e_status_code status;
4442         u16 length = count * sizeof(*buf);
4443
4444         i40e_fill_default_direct_cmd_desc(&desc,
4445                                         i40e_aqc_opc_get_switch_resource_alloc);
4446
4447         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4448         if (length > I40E_AQ_LARGE_BUF)
4449                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4450
4451         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4452
4453         if (!status && num_entries)
4454                 *num_entries = cmd_resp->num_entries;
4455
4456         return status;
4457 }
4458
4459 /**
4460  * i40e_aq_delete_element - Delete switch element
4461  * @hw: pointer to the hw struct
4462  * @seid: the SEID to delete from the switch
4463  * @cmd_details: pointer to command details structure or NULL
4464  *
4465  * This deletes a switch element from the switch.
4466  **/
4467 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4468                                 struct i40e_asq_cmd_details *cmd_details)
4469 {
4470         struct i40e_aq_desc desc;
4471         struct i40e_aqc_switch_seid *cmd =
4472                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4473         enum i40e_status_code status;
4474
4475         if (seid == 0)
4476                 return I40E_ERR_PARAM;
4477
4478         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4479
4480         cmd->seid = CPU_TO_LE16(seid);
4481
4482         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4483
4484         return status;
4485 }
4486
4487 /**
4488  * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4489  * @hw: pointer to the hw struct
4490  * @flags: component flags
4491  * @mac_seid: uplink seid (MAC SEID)
4492  * @vsi_seid: connected vsi seid
4493  * @ret_seid: seid of create pv component
4494  *
4495  * This instantiates an i40e port virtualizer with specified flags.
4496  * Depending on specified flags the port virtualizer can act as a
4497  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4498  */
4499 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4500                                        u16 mac_seid, u16 vsi_seid,
4501                                        u16 *ret_seid)
4502 {
4503         struct i40e_aq_desc desc;
4504         struct i40e_aqc_add_update_pv *cmd =
4505                 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4506         struct i40e_aqc_add_update_pv_completion *resp =
4507                 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4508         enum i40e_status_code status;
4509
4510         if (vsi_seid == 0)
4511                 return I40E_ERR_PARAM;
4512
4513         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4514         cmd->command_flags = CPU_TO_LE16(flags);
4515         cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4516         cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4517
4518         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4519         if (!status && ret_seid)
4520                 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4521
4522         return status;
4523 }
4524
4525 /**
4526  * i40e_aq_add_tag - Add an S/E-tag
4527  * @hw: pointer to the hw struct
4528  * @direct_to_queue: should s-tag direct flow to a specific queue
4529  * @vsi_seid: VSI SEID to use this tag
4530  * @tag: value of the tag
4531  * @queue_num: queue number, only valid is direct_to_queue is true
4532  * @tags_used: return value, number of tags in use by this PF
4533  * @tags_free: return value, number of unallocated tags
4534  * @cmd_details: pointer to command details structure or NULL
4535  *
4536  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4537  * the number of tags allocated by the PF, and the number of unallocated
4538  * tags available.
4539  **/
4540 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4541                                 u16 vsi_seid, u16 tag, u16 queue_num,
4542                                 u16 *tags_used, u16 *tags_free,
4543                                 struct i40e_asq_cmd_details *cmd_details)
4544 {
4545         struct i40e_aq_desc desc;
4546         struct i40e_aqc_add_tag *cmd =
4547                 (struct i40e_aqc_add_tag *)&desc.params.raw;
4548         struct i40e_aqc_add_remove_tag_completion *resp =
4549                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4550         enum i40e_status_code status;
4551
4552         if (vsi_seid == 0)
4553                 return I40E_ERR_PARAM;
4554
4555         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4556
4557         cmd->seid = CPU_TO_LE16(vsi_seid);
4558         cmd->tag = CPU_TO_LE16(tag);
4559         if (direct_to_queue) {
4560                 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4561                 cmd->queue_number = CPU_TO_LE16(queue_num);
4562         }
4563
4564         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4565
4566         if (!status) {
4567                 if (tags_used != NULL)
4568                         *tags_used = LE16_TO_CPU(resp->tags_used);
4569                 if (tags_free != NULL)
4570                         *tags_free = LE16_TO_CPU(resp->tags_free);
4571         }
4572
4573         return status;
4574 }
4575
4576 /**
4577  * i40e_aq_remove_tag - Remove an S- or E-tag
4578  * @hw: pointer to the hw struct
4579  * @vsi_seid: VSI SEID this tag is associated with
4580  * @tag: value of the S-tag to delete
4581  * @tags_used: return value, number of tags in use by this PF
4582  * @tags_free: return value, number of unallocated tags
4583  * @cmd_details: pointer to command details structure or NULL
4584  *
4585  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4586  * the number of tags allocated by the PF, and the number of unallocated
4587  * tags available.
4588  **/
4589 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4590                                 u16 tag, u16 *tags_used, u16 *tags_free,
4591                                 struct i40e_asq_cmd_details *cmd_details)
4592 {
4593         struct i40e_aq_desc desc;
4594         struct i40e_aqc_remove_tag *cmd =
4595                 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4596         struct i40e_aqc_add_remove_tag_completion *resp =
4597                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4598         enum i40e_status_code status;
4599
4600         if (vsi_seid == 0)
4601                 return I40E_ERR_PARAM;
4602
4603         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4604
4605         cmd->seid = CPU_TO_LE16(vsi_seid);
4606         cmd->tag = CPU_TO_LE16(tag);
4607
4608         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4609
4610         if (!status) {
4611                 if (tags_used != NULL)
4612                         *tags_used = LE16_TO_CPU(resp->tags_used);
4613                 if (tags_free != NULL)
4614                         *tags_free = LE16_TO_CPU(resp->tags_free);
4615         }
4616
4617         return status;
4618 }
4619
4620 /**
4621  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4622  * @hw: pointer to the hw struct
4623  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4624  * @etag: value of E-tag to add
4625  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4626  * @buf: address of indirect buffer
4627  * @tags_used: return value, number of E-tags in use by this port
4628  * @tags_free: return value, number of unallocated M-tags
4629  * @cmd_details: pointer to command details structure or NULL
4630  *
4631  * This associates a multicast E-tag to a port virtualizer.  It will return
4632  * the number of tags allocated by the PF, and the number of unallocated
4633  * tags available.
4634  *
4635  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4636  * num_tags_in_buf long.
4637  **/
4638 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4639                                 u16 etag, u8 num_tags_in_buf, void *buf,
4640                                 u16 *tags_used, u16 *tags_free,
4641                                 struct i40e_asq_cmd_details *cmd_details)
4642 {
4643         struct i40e_aq_desc desc;
4644         struct i40e_aqc_add_remove_mcast_etag *cmd =
4645                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4646         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4647            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4648         enum i40e_status_code status;
4649         u16 length = sizeof(u16) * num_tags_in_buf;
4650
4651         if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4652                 return I40E_ERR_PARAM;
4653
4654         i40e_fill_default_direct_cmd_desc(&desc,
4655                                           i40e_aqc_opc_add_multicast_etag);
4656
4657         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4658         cmd->etag = CPU_TO_LE16(etag);
4659         cmd->num_unicast_etags = num_tags_in_buf;
4660
4661         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4662         if (length > I40E_AQ_LARGE_BUF)
4663                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4664
4665         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4666
4667         if (!status) {
4668                 if (tags_used != NULL)
4669                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4670                 if (tags_free != NULL)
4671                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4672         }
4673
4674         return status;
4675 }
4676
4677 /**
4678  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4679  * @hw: pointer to the hw struct
4680  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4681  * @etag: value of the E-tag to remove
4682  * @tags_used: return value, number of tags in use by this port
4683  * @tags_free: return value, number of unallocated tags
4684  * @cmd_details: pointer to command details structure or NULL
4685  *
4686  * This deletes an E-tag from the port virtualizer.  It will return
4687  * the number of tags allocated by the port, and the number of unallocated
4688  * tags available.
4689  **/
4690 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4691                                 u16 etag, u16 *tags_used, u16 *tags_free,
4692                                 struct i40e_asq_cmd_details *cmd_details)
4693 {
4694         struct i40e_aq_desc desc;
4695         struct i40e_aqc_add_remove_mcast_etag *cmd =
4696                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4697         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4698            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4699         enum i40e_status_code status;
4700
4701
4702         if (pv_seid == 0)
4703                 return I40E_ERR_PARAM;
4704
4705         i40e_fill_default_direct_cmd_desc(&desc,
4706                                           i40e_aqc_opc_remove_multicast_etag);
4707
4708         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4709         cmd->etag = CPU_TO_LE16(etag);
4710
4711         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4712
4713         if (!status) {
4714                 if (tags_used != NULL)
4715                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4716                 if (tags_free != NULL)
4717                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4718         }
4719
4720         return status;
4721 }
4722
4723 /**
4724  * i40e_aq_update_tag - Update an S/E-tag
4725  * @hw: pointer to the hw struct
4726  * @vsi_seid: VSI SEID using this S-tag
4727  * @old_tag: old tag value
4728  * @new_tag: new tag value
4729  * @tags_used: return value, number of tags in use by this PF
4730  * @tags_free: return value, number of unallocated tags
4731  * @cmd_details: pointer to command details structure or NULL
4732  *
4733  * This updates the value of the tag currently attached to this VSI
4734  * in the switch complex.  It will return the number of tags allocated
4735  * by the PF, and the number of unallocated tags available.
4736  **/
4737 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4738                                 u16 old_tag, u16 new_tag, u16 *tags_used,
4739                                 u16 *tags_free,
4740                                 struct i40e_asq_cmd_details *cmd_details)
4741 {
4742         struct i40e_aq_desc desc;
4743         struct i40e_aqc_update_tag *cmd =
4744                 (struct i40e_aqc_update_tag *)&desc.params.raw;
4745         struct i40e_aqc_update_tag_completion *resp =
4746                 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4747         enum i40e_status_code status;
4748
4749         if (vsi_seid == 0)
4750                 return I40E_ERR_PARAM;
4751
4752         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4753
4754         cmd->seid = CPU_TO_LE16(vsi_seid);
4755         cmd->old_tag = CPU_TO_LE16(old_tag);
4756         cmd->new_tag = CPU_TO_LE16(new_tag);
4757
4758         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4759
4760         if (!status) {
4761                 if (tags_used != NULL)
4762                         *tags_used = LE16_TO_CPU(resp->tags_used);
4763                 if (tags_free != NULL)
4764                         *tags_free = LE16_TO_CPU(resp->tags_free);
4765         }
4766
4767         return status;
4768 }
4769
4770 /**
4771  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4772  * @hw: pointer to the hw struct
4773  * @tcmap: TC map for request/release any ignore PFC condition
4774  * @request: request or release ignore PFC condition
4775  * @tcmap_ret: return TCs for which PFC is currently ignored
4776  * @cmd_details: pointer to command details structure or NULL
4777  *
4778  * This sends out request/release to ignore PFC condition for a TC.
4779  * It will return the TCs for which PFC is currently ignored.
4780  **/
4781 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4782                                 bool request, u8 *tcmap_ret,
4783                                 struct i40e_asq_cmd_details *cmd_details)
4784 {
4785         struct i40e_aq_desc desc;
4786         struct i40e_aqc_pfc_ignore *cmd_resp =
4787                 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4788         enum i40e_status_code status;
4789
4790         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4791
4792         if (request)
4793                 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4794
4795         cmd_resp->tc_bitmap = tcmap;
4796
4797         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4798
4799         if (!status) {
4800                 if (tcmap_ret != NULL)
4801                         *tcmap_ret = cmd_resp->tc_bitmap;
4802         }
4803
4804         return status;
4805 }
4806
4807 /**
4808  * i40e_aq_dcb_updated - DCB Updated Command
4809  * @hw: pointer to the hw struct
4810  * @cmd_details: pointer to command details structure or NULL
4811  *
4812  * When LLDP is handled in PF this command is used by the PF
4813  * to notify EMP that a DCB setting is modified.
4814  * When LLDP is handled in EMP this command is used by the PF
4815  * to notify EMP whenever one of the following parameters get
4816  * modified:
4817  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4818  *   - PCIRTT in PRTDCB_GENC.PCIRTT
4819  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4820  * EMP will return when the shared RPB settings have been
4821  * recomputed and modified. The retval field in the descriptor
4822  * will be set to 0 when RPB is modified.
4823  **/
4824 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4825                                 struct i40e_asq_cmd_details *cmd_details)
4826 {
4827         struct i40e_aq_desc desc;
4828         enum i40e_status_code status;
4829
4830         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4831
4832         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4833
4834         return status;
4835 }
4836
4837 /**
4838  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4839  * @hw: pointer to the hw struct
4840  * @seid: defines the SEID of the switch for which the stats are requested
4841  * @vlan_id: the VLAN ID for which the statistics are requested
4842  * @stat_index: index of the statistics counters block assigned to this VLAN
4843  * @cmd_details: pointer to command details structure or NULL
4844  *
4845  * XL710 supports 128 smonVlanStats counters.This command is used to
4846  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4847  * switch.
4848  **/
4849 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4850                                 u16 vlan_id, u16 *stat_index,
4851                                 struct i40e_asq_cmd_details *cmd_details)
4852 {
4853         struct i40e_aq_desc desc;
4854         struct i40e_aqc_add_remove_statistics *cmd_resp =
4855                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4856         enum i40e_status_code status;
4857
4858         if ((seid == 0) || (stat_index == NULL))
4859                 return I40E_ERR_PARAM;
4860
4861         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4862
4863         cmd_resp->seid = CPU_TO_LE16(seid);
4864         cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4865
4866         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4867
4868         if (!status && stat_index)
4869                 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4870
4871         return status;
4872 }
4873
4874 /**
4875  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4876  * @hw: pointer to the hw struct
4877  * @seid: defines the SEID of the switch for which the stats are requested
4878  * @vlan_id: the VLAN ID for which the statistics are requested
4879  * @stat_index: index of the statistics counters block assigned to this VLAN
4880  * @cmd_details: pointer to command details structure or NULL
4881  *
4882  * XL710 supports 128 smonVlanStats counters.This command is used to
4883  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4884  * switch.
4885  **/
4886 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4887                                 u16 vlan_id, u16 stat_index,
4888                                 struct i40e_asq_cmd_details *cmd_details)
4889 {
4890         struct i40e_aq_desc desc;
4891         struct i40e_aqc_add_remove_statistics *cmd =
4892                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4893         enum i40e_status_code status;
4894
4895         if (seid == 0)
4896                 return I40E_ERR_PARAM;
4897
4898         i40e_fill_default_direct_cmd_desc(&desc,
4899                                           i40e_aqc_opc_remove_statistics);
4900
4901         cmd->seid = CPU_TO_LE16(seid);
4902         cmd->vlan  = CPU_TO_LE16(vlan_id);
4903         cmd->stat_index = CPU_TO_LE16(stat_index);
4904
4905         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4906
4907         return status;
4908 }
4909
4910 /**
4911  * i40e_aq_set_port_parameters - set physical port parameters.
4912  * @hw: pointer to the hw struct
4913  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4914  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4915  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4916  * @double_vlan: if set double VLAN is enabled
4917  * @cmd_details: pointer to command details structure or NULL
4918  **/
4919 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4920                                 u16 bad_frame_vsi, bool save_bad_pac,
4921                                 bool pad_short_pac, bool double_vlan,
4922                                 struct i40e_asq_cmd_details *cmd_details)
4923 {
4924         struct i40e_aqc_set_port_parameters *cmd;
4925         enum i40e_status_code status;
4926         struct i40e_aq_desc desc;
4927         u16 command_flags = 0;
4928
4929         cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4930
4931         i40e_fill_default_direct_cmd_desc(&desc,
4932                                           i40e_aqc_opc_set_port_parameters);
4933
4934         cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4935         if (save_bad_pac)
4936                 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4937         if (pad_short_pac)
4938                 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4939         if (double_vlan)
4940                 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4941         cmd->command_flags = CPU_TO_LE16(command_flags);
4942
4943         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4944
4945         return status;
4946 }
4947
4948 /**
4949  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
4950  * @hw: pointer to the hw struct
4951  * @seid: seid for the physical port/switching component/vsi
4952  * @buff: Indirect buffer to hold data parameters and response
4953  * @buff_size: Indirect buffer size
4954  * @opcode: Tx scheduler AQ command opcode
4955  * @cmd_details: pointer to command details structure or NULL
4956  *
4957  * Generic command handler for Tx scheduler AQ commands
4958  **/
4959 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
4960                                 void *buff, u16 buff_size,
4961                                  enum i40e_admin_queue_opc opcode,
4962                                 struct i40e_asq_cmd_details *cmd_details)
4963 {
4964         struct i40e_aq_desc desc;
4965         struct i40e_aqc_tx_sched_ind *cmd =
4966                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4967         enum i40e_status_code status;
4968         bool cmd_param_flag = false;
4969
4970         switch (opcode) {
4971         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
4972         case i40e_aqc_opc_configure_vsi_tc_bw:
4973         case i40e_aqc_opc_enable_switching_comp_ets:
4974         case i40e_aqc_opc_modify_switching_comp_ets:
4975         case i40e_aqc_opc_disable_switching_comp_ets:
4976         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
4977         case i40e_aqc_opc_configure_switching_comp_bw_config:
4978                 cmd_param_flag = true;
4979                 break;
4980         case i40e_aqc_opc_query_vsi_bw_config:
4981         case i40e_aqc_opc_query_vsi_ets_sla_config:
4982         case i40e_aqc_opc_query_switching_comp_ets_config:
4983         case i40e_aqc_opc_query_port_ets_config:
4984         case i40e_aqc_opc_query_switching_comp_bw_config:
4985                 cmd_param_flag = false;
4986                 break;
4987         default:
4988                 return I40E_ERR_PARAM;
4989         }
4990
4991         i40e_fill_default_direct_cmd_desc(&desc, opcode);
4992
4993         /* Indirect command */
4994         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4995         if (cmd_param_flag)
4996                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4997         if (buff_size > I40E_AQ_LARGE_BUF)
4998                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4999
5000         desc.datalen = CPU_TO_LE16(buff_size);
5001
5002         cmd->vsi_seid = CPU_TO_LE16(seid);
5003
5004         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5005
5006         return status;
5007 }
5008
5009 /**
5010  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5011  * @hw: pointer to the hw struct
5012  * @seid: VSI seid
5013  * @credit: BW limit credits (0 = disabled)
5014  * @max_credit: Max BW limit credits
5015  * @cmd_details: pointer to command details structure or NULL
5016  **/
5017 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5018                                 u16 seid, u16 credit, u8 max_credit,
5019                                 struct i40e_asq_cmd_details *cmd_details)
5020 {
5021         struct i40e_aq_desc desc;
5022         struct i40e_aqc_configure_vsi_bw_limit *cmd =
5023                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5024         enum i40e_status_code status;
5025
5026         i40e_fill_default_direct_cmd_desc(&desc,
5027                                           i40e_aqc_opc_configure_vsi_bw_limit);
5028
5029         cmd->vsi_seid = CPU_TO_LE16(seid);
5030         cmd->credit = CPU_TO_LE16(credit);
5031         cmd->max_credit = max_credit;
5032
5033         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5034
5035         return status;
5036 }
5037
5038 /**
5039  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5040  * @hw: pointer to the hw struct
5041  * @seid: switching component seid
5042  * @credit: BW limit credits (0 = disabled)
5043  * @max_bw: Max BW limit credits
5044  * @cmd_details: pointer to command details structure or NULL
5045  **/
5046 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5047                                 u16 seid, u16 credit, u8 max_bw,
5048                                 struct i40e_asq_cmd_details *cmd_details)
5049 {
5050         struct i40e_aq_desc desc;
5051         struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5052           (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5053         enum i40e_status_code status;
5054
5055         i40e_fill_default_direct_cmd_desc(&desc,
5056                                 i40e_aqc_opc_configure_switching_comp_bw_limit);
5057
5058         cmd->seid = CPU_TO_LE16(seid);
5059         cmd->credit = CPU_TO_LE16(credit);
5060         cmd->max_bw = max_bw;
5061
5062         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5063
5064         return status;
5065 }
5066
5067 /**
5068  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5069  * @hw: pointer to the hw struct
5070  * @seid: VSI seid
5071  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5072  * @cmd_details: pointer to command details structure or NULL
5073  **/
5074 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5075                         u16 seid,
5076                         struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5077                         struct i40e_asq_cmd_details *cmd_details)
5078 {
5079         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5080                                     i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5081                                     cmd_details);
5082 }
5083
5084 /**
5085  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5086  * @hw: pointer to the hw struct
5087  * @seid: VSI seid
5088  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5089  * @cmd_details: pointer to command details structure or NULL
5090  **/
5091 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5092                         u16 seid,
5093                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5094                         struct i40e_asq_cmd_details *cmd_details)
5095 {
5096         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5097                                     i40e_aqc_opc_configure_vsi_tc_bw,
5098                                     cmd_details);
5099 }
5100
5101 /**
5102  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5103  * @hw: pointer to the hw struct
5104  * @seid: seid of the switching component connected to Physical Port
5105  * @ets_data: Buffer holding ETS parameters
5106  * @cmd_details: pointer to command details structure or NULL
5107  **/
5108 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5109                 u16 seid,
5110                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5111                 enum i40e_admin_queue_opc opcode,
5112                 struct i40e_asq_cmd_details *cmd_details)
5113 {
5114         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5115                                     sizeof(*ets_data), opcode, cmd_details);
5116 }
5117
5118 /**
5119  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5120  * @hw: pointer to the hw struct
5121  * @seid: seid of the switching component
5122  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5123  * @cmd_details: pointer to command details structure or NULL
5124  **/
5125 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5126         u16 seid,
5127         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5128         struct i40e_asq_cmd_details *cmd_details)
5129 {
5130         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5131                             i40e_aqc_opc_configure_switching_comp_bw_config,
5132                             cmd_details);
5133 }
5134
5135 /**
5136  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5137  * @hw: pointer to the hw struct
5138  * @seid: seid of the switching component
5139  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5140  * @cmd_details: pointer to command details structure or NULL
5141  **/
5142 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5143         struct i40e_hw *hw, u16 seid,
5144         struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5145         struct i40e_asq_cmd_details *cmd_details)
5146 {
5147         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5148                             i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5149                             cmd_details);
5150 }
5151
5152 /**
5153  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5154  * @hw: pointer to the hw struct
5155  * @seid: seid of the VSI
5156  * @bw_data: Buffer to hold VSI BW configuration
5157  * @cmd_details: pointer to command details structure or NULL
5158  **/
5159 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5160                         u16 seid,
5161                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5162                         struct i40e_asq_cmd_details *cmd_details)
5163 {
5164         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5165                                     i40e_aqc_opc_query_vsi_bw_config,
5166                                     cmd_details);
5167 }
5168
5169 /**
5170  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5171  * @hw: pointer to the hw struct
5172  * @seid: seid of the VSI
5173  * @bw_data: Buffer to hold VSI BW configuration per TC
5174  * @cmd_details: pointer to command details structure or NULL
5175  **/
5176 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5177                         u16 seid,
5178                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5179                         struct i40e_asq_cmd_details *cmd_details)
5180 {
5181         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5182                                     i40e_aqc_opc_query_vsi_ets_sla_config,
5183                                     cmd_details);
5184 }
5185
5186 /**
5187  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5188  * @hw: pointer to the hw struct
5189  * @seid: seid of the switching component
5190  * @bw_data: Buffer to hold switching component's per TC BW config
5191  * @cmd_details: pointer to command details structure or NULL
5192  **/
5193 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5194                 u16 seid,
5195                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5196                 struct i40e_asq_cmd_details *cmd_details)
5197 {
5198         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5199                                    i40e_aqc_opc_query_switching_comp_ets_config,
5200                                    cmd_details);
5201 }
5202
5203 /**
5204  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5205  * @hw: pointer to the hw struct
5206  * @seid: seid of the VSI or switching component connected to Physical Port
5207  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5208  * @cmd_details: pointer to command details structure or NULL
5209  **/
5210 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5211                         u16 seid,
5212                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
5213                         struct i40e_asq_cmd_details *cmd_details)
5214 {
5215         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5216                                     i40e_aqc_opc_query_port_ets_config,
5217                                     cmd_details);
5218 }
5219
5220 /**
5221  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5222  * @hw: pointer to the hw struct
5223  * @seid: seid of the switching component
5224  * @bw_data: Buffer to hold switching component's BW configuration
5225  * @cmd_details: pointer to command details structure or NULL
5226  **/
5227 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5228                 u16 seid,
5229                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5230                 struct i40e_asq_cmd_details *cmd_details)
5231 {
5232         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5233                                     i40e_aqc_opc_query_switching_comp_bw_config,
5234                                     cmd_details);
5235 }
5236
5237 /**
5238  * i40e_validate_filter_settings
5239  * @hw: pointer to the hardware structure
5240  * @settings: Filter control settings
5241  *
5242  * Check and validate the filter control settings passed.
5243  * The function checks for the valid filter/context sizes being
5244  * passed for FCoE and PE.
5245  *
5246  * Returns I40E_SUCCESS if the values passed are valid and within
5247  * range else returns an error.
5248  **/
5249 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5250                                 struct i40e_filter_control_settings *settings)
5251 {
5252         u32 fcoe_cntx_size, fcoe_filt_size;
5253         u32 pe_cntx_size, pe_filt_size;
5254         u32 fcoe_fmax;
5255
5256         u32 val;
5257
5258         /* Validate FCoE settings passed */
5259         switch (settings->fcoe_filt_num) {
5260         case I40E_HASH_FILTER_SIZE_1K:
5261         case I40E_HASH_FILTER_SIZE_2K:
5262         case I40E_HASH_FILTER_SIZE_4K:
5263         case I40E_HASH_FILTER_SIZE_8K:
5264         case I40E_HASH_FILTER_SIZE_16K:
5265         case I40E_HASH_FILTER_SIZE_32K:
5266                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5267                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5268                 break;
5269         default:
5270                 return I40E_ERR_PARAM;
5271         }
5272
5273         switch (settings->fcoe_cntx_num) {
5274         case I40E_DMA_CNTX_SIZE_512:
5275         case I40E_DMA_CNTX_SIZE_1K:
5276         case I40E_DMA_CNTX_SIZE_2K:
5277         case I40E_DMA_CNTX_SIZE_4K:
5278                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5279                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5280                 break;
5281         default:
5282                 return I40E_ERR_PARAM;
5283         }
5284
5285         /* Validate PE settings passed */
5286         switch (settings->pe_filt_num) {
5287         case I40E_HASH_FILTER_SIZE_1K:
5288         case I40E_HASH_FILTER_SIZE_2K:
5289         case I40E_HASH_FILTER_SIZE_4K:
5290         case I40E_HASH_FILTER_SIZE_8K:
5291         case I40E_HASH_FILTER_SIZE_16K:
5292         case I40E_HASH_FILTER_SIZE_32K:
5293         case I40E_HASH_FILTER_SIZE_64K:
5294         case I40E_HASH_FILTER_SIZE_128K:
5295         case I40E_HASH_FILTER_SIZE_256K:
5296         case I40E_HASH_FILTER_SIZE_512K:
5297         case I40E_HASH_FILTER_SIZE_1M:
5298                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5299                 pe_filt_size <<= (u32)settings->pe_filt_num;
5300                 break;
5301         default:
5302                 return I40E_ERR_PARAM;
5303         }
5304
5305         switch (settings->pe_cntx_num) {
5306         case I40E_DMA_CNTX_SIZE_512:
5307         case I40E_DMA_CNTX_SIZE_1K:
5308         case I40E_DMA_CNTX_SIZE_2K:
5309         case I40E_DMA_CNTX_SIZE_4K:
5310         case I40E_DMA_CNTX_SIZE_8K:
5311         case I40E_DMA_CNTX_SIZE_16K:
5312         case I40E_DMA_CNTX_SIZE_32K:
5313         case I40E_DMA_CNTX_SIZE_64K:
5314         case I40E_DMA_CNTX_SIZE_128K:
5315         case I40E_DMA_CNTX_SIZE_256K:
5316                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5317                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5318                 break;
5319         default:
5320                 return I40E_ERR_PARAM;
5321         }
5322
5323         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5324         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5325         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5326                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5327         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
5328                 return I40E_ERR_INVALID_SIZE;
5329
5330         return I40E_SUCCESS;
5331 }
5332
5333 /**
5334  * i40e_set_filter_control
5335  * @hw: pointer to the hardware structure
5336  * @settings: Filter control settings
5337  *
5338  * Set the Queue Filters for PE/FCoE and enable filters required
5339  * for a single PF. It is expected that these settings are programmed
5340  * at the driver initialization time.
5341  **/
5342 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5343                                 struct i40e_filter_control_settings *settings)
5344 {
5345         enum i40e_status_code ret = I40E_SUCCESS;
5346         u32 hash_lut_size = 0;
5347         u32 val;
5348
5349         if (!settings)
5350                 return I40E_ERR_PARAM;
5351
5352         /* Validate the input settings */
5353         ret = i40e_validate_filter_settings(hw, settings);
5354         if (ret)
5355                 return ret;
5356
5357         /* Read the PF Queue Filter control register */
5358         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5359
5360         /* Program required PE hash buckets for the PF */
5361         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5362         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5363                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5364         /* Program required PE contexts for the PF */
5365         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5366         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5367                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5368
5369         /* Program required FCoE hash buckets for the PF */
5370         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5371         val |= ((u32)settings->fcoe_filt_num <<
5372                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5373                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5374         /* Program required FCoE DDP contexts for the PF */
5375         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5376         val |= ((u32)settings->fcoe_cntx_num <<
5377                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5378                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5379
5380         /* Program Hash LUT size for the PF */
5381         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5382         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5383                 hash_lut_size = 1;
5384         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5385                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5386
5387         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5388         if (settings->enable_fdir)
5389                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5390         if (settings->enable_ethtype)
5391                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5392         if (settings->enable_macvlan)
5393                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5394
5395         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5396
5397         return I40E_SUCCESS;
5398 }
5399
5400 /**
5401  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5402  * @hw: pointer to the hw struct
5403  * @mac_addr: MAC address to use in the filter
5404  * @ethtype: Ethertype to use in the filter
5405  * @flags: Flags that needs to be applied to the filter
5406  * @vsi_seid: seid of the control VSI
5407  * @queue: VSI queue number to send the packet to
5408  * @is_add: Add control packet filter if True else remove
5409  * @stats: Structure to hold information on control filter counts
5410  * @cmd_details: pointer to command details structure or NULL
5411  *
5412  * This command will Add or Remove control packet filter for a control VSI.
5413  * In return it will update the total number of perfect filter count in
5414  * the stats member.
5415  **/
5416 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5417                                 u8 *mac_addr, u16 ethtype, u16 flags,
5418                                 u16 vsi_seid, u16 queue, bool is_add,
5419                                 struct i40e_control_filter_stats *stats,
5420                                 struct i40e_asq_cmd_details *cmd_details)
5421 {
5422         struct i40e_aq_desc desc;
5423         struct i40e_aqc_add_remove_control_packet_filter *cmd =
5424                 (struct i40e_aqc_add_remove_control_packet_filter *)
5425                 &desc.params.raw;
5426         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5427                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5428                 &desc.params.raw;
5429         enum i40e_status_code status;
5430
5431         if (vsi_seid == 0)
5432                 return I40E_ERR_PARAM;
5433
5434         if (is_add) {
5435                 i40e_fill_default_direct_cmd_desc(&desc,
5436                                 i40e_aqc_opc_add_control_packet_filter);
5437                 cmd->queue = CPU_TO_LE16(queue);
5438         } else {
5439                 i40e_fill_default_direct_cmd_desc(&desc,
5440                                 i40e_aqc_opc_remove_control_packet_filter);
5441         }
5442
5443         if (mac_addr)
5444                 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
5445                             I40E_NONDMA_TO_NONDMA);
5446
5447         cmd->etype = CPU_TO_LE16(ethtype);
5448         cmd->flags = CPU_TO_LE16(flags);
5449         cmd->seid = CPU_TO_LE16(vsi_seid);
5450
5451         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5452
5453         if (!status && stats) {
5454                 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5455                 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5456                 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5457                 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5458         }
5459
5460         return status;
5461 }
5462
5463 /**
5464  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5465  * @hw: pointer to the hw struct
5466  * @seid: VSI seid to add ethertype filter from
5467  **/
5468 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5469 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5470                                                     u16 seid)
5471 {
5472         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5473                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5474                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5475         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5476         enum i40e_status_code status;
5477
5478         status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5479                                                        seid, 0, true, NULL,
5480                                                        NULL);
5481         if (status)
5482                 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5483 }
5484
5485 /**
5486  * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5487  * @filters: list of cloud filters
5488  * @filter_count: length of list
5489  *
5490  * There's an issue in the device where the Geneve VNI layout needs
5491  * to be shifted 1 byte over from the VxLAN VNI
5492  **/
5493 STATIC void i40e_fix_up_geneve_vni(
5494         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5495         u8 filter_count)
5496 {
5497         struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters;
5498         int i;
5499
5500         for (i = 0; i < filter_count; i++) {
5501                 u16 tnl_type;
5502                 u32 ti;
5503
5504                 tnl_type = (LE16_TO_CPU(f[i].flags) &
5505                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5506                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5507                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5508                         ti = LE32_TO_CPU(f[i].tenant_id);
5509                         f[i].tenant_id = CPU_TO_LE32(ti << 8);
5510                 }
5511         }
5512 }
5513
5514 /**
5515  * i40e_aq_add_cloud_filters
5516  * @hw: pointer to the hardware structure
5517  * @seid: VSI seid to add cloud filters from
5518  * @filters: Buffer which contains the filters to be added
5519  * @filter_count: number of filters contained in the buffer
5520  *
5521  * Set the cloud filters for a given VSI.  The contents of the
5522  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5523  * in by the caller of the function.
5524  *
5525  **/
5526 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5527         u16 seid,
5528         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5529         u8 filter_count)
5530 {
5531         struct i40e_aq_desc desc;
5532         struct i40e_aqc_add_remove_cloud_filters *cmd =
5533         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5534         enum i40e_status_code status;
5535         u16 buff_len;
5536
5537         i40e_fill_default_direct_cmd_desc(&desc,
5538                                           i40e_aqc_opc_add_cloud_filters);
5539
5540         buff_len = filter_count * sizeof(*filters);
5541         desc.datalen = CPU_TO_LE16(buff_len);
5542         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5543         cmd->num_filters = filter_count;
5544         cmd->seid = CPU_TO_LE16(seid);
5545
5546         i40e_fix_up_geneve_vni(filters, filter_count);
5547
5548         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5549
5550         return status;
5551 }
5552
5553 /**
5554  * i40e_aq_remove_cloud_filters
5555  * @hw: pointer to the hardware structure
5556  * @seid: VSI seid to remove cloud filters from
5557  * @filters: Buffer which contains the filters to be removed
5558  * @filter_count: number of filters contained in the buffer
5559  *
5560  * Remove the cloud filters for a given VSI.  The contents of the
5561  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5562  * in by the caller of the function.
5563  *
5564  **/
5565 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5566                 u16 seid,
5567                 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5568                 u8 filter_count)
5569 {
5570         struct i40e_aq_desc desc;
5571         struct i40e_aqc_add_remove_cloud_filters *cmd =
5572         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5573         enum i40e_status_code status;
5574         u16 buff_len;
5575
5576         i40e_fill_default_direct_cmd_desc(&desc,
5577                                           i40e_aqc_opc_remove_cloud_filters);
5578
5579         buff_len = filter_count * sizeof(*filters);
5580         desc.datalen = CPU_TO_LE16(buff_len);
5581         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5582         cmd->num_filters = filter_count;
5583         cmd->seid = CPU_TO_LE16(seid);
5584
5585         i40e_fix_up_geneve_vni(filters, filter_count);
5586
5587         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5588
5589         return status;
5590 }
5591
5592 /**
5593  * i40e_aq_alternate_write
5594  * @hw: pointer to the hardware structure
5595  * @reg_addr0: address of first dword to be read
5596  * @reg_val0: value to be written under 'reg_addr0'
5597  * @reg_addr1: address of second dword to be read
5598  * @reg_val1: value to be written under 'reg_addr1'
5599  *
5600  * Write one or two dwords to alternate structure. Fields are indicated
5601  * by 'reg_addr0' and 'reg_addr1' register numbers.
5602  *
5603  **/
5604 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5605                                 u32 reg_addr0, u32 reg_val0,
5606                                 u32 reg_addr1, u32 reg_val1)
5607 {
5608         struct i40e_aq_desc desc;
5609         struct i40e_aqc_alternate_write *cmd_resp =
5610                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5611         enum i40e_status_code status;
5612
5613         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5614         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5615         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5616         cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5617         cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5618
5619         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5620
5621         return status;
5622 }
5623
5624 /**
5625  * i40e_aq_alternate_write_indirect
5626  * @hw: pointer to the hardware structure
5627  * @addr: address of a first register to be modified
5628  * @dw_count: number of alternate structure fields to write
5629  * @buffer: pointer to the command buffer
5630  *
5631  * Write 'dw_count' dwords from 'buffer' to alternate structure
5632  * starting at 'addr'.
5633  *
5634  **/
5635 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5636                                 u32 addr, u32 dw_count, void *buffer)
5637 {
5638         struct i40e_aq_desc desc;
5639         struct i40e_aqc_alternate_ind_write *cmd_resp =
5640                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5641         enum i40e_status_code status;
5642
5643         if (buffer == NULL)
5644                 return I40E_ERR_PARAM;
5645
5646         /* Indirect command */
5647         i40e_fill_default_direct_cmd_desc(&desc,
5648                                          i40e_aqc_opc_alternate_write_indirect);
5649
5650         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5651         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5652         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5653                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5654
5655         cmd_resp->address = CPU_TO_LE32(addr);
5656         cmd_resp->length = CPU_TO_LE32(dw_count);
5657
5658         status = i40e_asq_send_command(hw, &desc, buffer,
5659                                        I40E_LO_DWORD(4*dw_count), NULL);
5660
5661         return status;
5662 }
5663
5664 /**
5665  * i40e_aq_alternate_read
5666  * @hw: pointer to the hardware structure
5667  * @reg_addr0: address of first dword to be read
5668  * @reg_val0: pointer for data read from 'reg_addr0'
5669  * @reg_addr1: address of second dword to be read
5670  * @reg_val1: pointer for data read from 'reg_addr1'
5671  *
5672  * Read one or two dwords from alternate structure. Fields are indicated
5673  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5674  * is not passed then only register at 'reg_addr0' is read.
5675  *
5676  **/
5677 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5678                                 u32 reg_addr0, u32 *reg_val0,
5679                                 u32 reg_addr1, u32 *reg_val1)
5680 {
5681         struct i40e_aq_desc desc;
5682         struct i40e_aqc_alternate_write *cmd_resp =
5683                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5684         enum i40e_status_code status;
5685
5686         if (reg_val0 == NULL)
5687                 return I40E_ERR_PARAM;
5688
5689         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5690         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5691         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5692
5693         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5694
5695         if (status == I40E_SUCCESS) {
5696                 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5697
5698                 if (reg_val1 != NULL)
5699                         *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5700         }
5701
5702         return status;
5703 }
5704
5705 /**
5706  * i40e_aq_alternate_read_indirect
5707  * @hw: pointer to the hardware structure
5708  * @addr: address of the alternate structure field
5709  * @dw_count: number of alternate structure fields to read
5710  * @buffer: pointer to the command buffer
5711  *
5712  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5713  * place them in 'buffer'. The buffer should be allocated by caller.
5714  *
5715  **/
5716 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5717                                 u32 addr, u32 dw_count, void *buffer)
5718 {
5719         struct i40e_aq_desc desc;
5720         struct i40e_aqc_alternate_ind_write *cmd_resp =
5721                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5722         enum i40e_status_code status;
5723
5724         if (buffer == NULL)
5725                 return I40E_ERR_PARAM;
5726
5727         /* Indirect command */
5728         i40e_fill_default_direct_cmd_desc(&desc,
5729                 i40e_aqc_opc_alternate_read_indirect);
5730
5731         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5732         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5733         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5734                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5735
5736         cmd_resp->address = CPU_TO_LE32(addr);
5737         cmd_resp->length = CPU_TO_LE32(dw_count);
5738
5739         status = i40e_asq_send_command(hw, &desc, buffer,
5740                                        I40E_LO_DWORD(4*dw_count), NULL);
5741
5742         return status;
5743 }
5744
5745 /**
5746  *  i40e_aq_alternate_clear
5747  *  @hw: pointer to the HW structure.
5748  *
5749  *  Clear the alternate structures of the port from which the function
5750  *  is called.
5751  *
5752  **/
5753 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5754 {
5755         struct i40e_aq_desc desc;
5756         enum i40e_status_code status;
5757
5758         i40e_fill_default_direct_cmd_desc(&desc,
5759                                           i40e_aqc_opc_alternate_clear_port);
5760
5761         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5762
5763         return status;
5764 }
5765
5766 /**
5767  *  i40e_aq_alternate_write_done
5768  *  @hw: pointer to the HW structure.
5769  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
5770  *  @reset_needed: indicates the SW should trigger GLOBAL reset
5771  *
5772  *  Indicates to the FW that alternate structures have been changed.
5773  *
5774  **/
5775 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
5776                 u8 bios_mode, bool *reset_needed)
5777 {
5778         struct i40e_aq_desc desc;
5779         struct i40e_aqc_alternate_write_done *cmd =
5780                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5781         enum i40e_status_code status;
5782
5783         if (reset_needed == NULL)
5784                 return I40E_ERR_PARAM;
5785
5786         i40e_fill_default_direct_cmd_desc(&desc,
5787                                           i40e_aqc_opc_alternate_write_done);
5788
5789         cmd->cmd_flags = CPU_TO_LE16(bios_mode);
5790
5791         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5792         if (!status && reset_needed)
5793                 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
5794                                  I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
5795
5796         return status;
5797 }
5798
5799 /**
5800  *  i40e_aq_set_oem_mode
5801  *  @hw: pointer to the HW structure.
5802  *  @oem_mode: the OEM mode to be used
5803  *
5804  *  Sets the device to a specific operating mode. Currently the only supported
5805  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
5806  *
5807  **/
5808 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
5809                 u8 oem_mode)
5810 {
5811         struct i40e_aq_desc desc;
5812         struct i40e_aqc_alternate_write_done *cmd =
5813                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5814         enum i40e_status_code status;
5815
5816         i40e_fill_default_direct_cmd_desc(&desc,
5817                                           i40e_aqc_opc_alternate_set_mode);
5818
5819         cmd->cmd_flags = CPU_TO_LE16(oem_mode);
5820
5821         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5822
5823         return status;
5824 }
5825
5826 /**
5827  * i40e_aq_resume_port_tx
5828  * @hw: pointer to the hardware structure
5829  * @cmd_details: pointer to command details structure or NULL
5830  *
5831  * Resume port's Tx traffic
5832  **/
5833 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
5834                                 struct i40e_asq_cmd_details *cmd_details)
5835 {
5836         struct i40e_aq_desc desc;
5837         enum i40e_status_code status;
5838
5839         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
5840
5841         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5842
5843         return status;
5844 }
5845
5846 /**
5847  * i40e_set_pci_config_data - store PCI bus info
5848  * @hw: pointer to hardware structure
5849  * @link_status: the link status word from PCI config space
5850  *
5851  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
5852  **/
5853 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
5854 {
5855         hw->bus.type = i40e_bus_type_pci_express;
5856
5857         switch (link_status & I40E_PCI_LINK_WIDTH) {
5858         case I40E_PCI_LINK_WIDTH_1:
5859                 hw->bus.width = i40e_bus_width_pcie_x1;
5860                 break;
5861         case I40E_PCI_LINK_WIDTH_2:
5862                 hw->bus.width = i40e_bus_width_pcie_x2;
5863                 break;
5864         case I40E_PCI_LINK_WIDTH_4:
5865                 hw->bus.width = i40e_bus_width_pcie_x4;
5866                 break;
5867         case I40E_PCI_LINK_WIDTH_8:
5868                 hw->bus.width = i40e_bus_width_pcie_x8;
5869                 break;
5870         default:
5871                 hw->bus.width = i40e_bus_width_unknown;
5872                 break;
5873         }
5874
5875         switch (link_status & I40E_PCI_LINK_SPEED) {
5876         case I40E_PCI_LINK_SPEED_2500:
5877                 hw->bus.speed = i40e_bus_speed_2500;
5878                 break;
5879         case I40E_PCI_LINK_SPEED_5000:
5880                 hw->bus.speed = i40e_bus_speed_5000;
5881                 break;
5882         case I40E_PCI_LINK_SPEED_8000:
5883                 hw->bus.speed = i40e_bus_speed_8000;
5884                 break;
5885         default:
5886                 hw->bus.speed = i40e_bus_speed_unknown;
5887                 break;
5888         }
5889 }
5890
5891 /**
5892  * i40e_aq_debug_dump
5893  * @hw: pointer to the hardware structure
5894  * @cluster_id: specific cluster to dump
5895  * @table_id: table id within cluster
5896  * @start_index: index of line in the block to read
5897  * @buff_size: dump buffer size
5898  * @buff: dump buffer
5899  * @ret_buff_size: actual buffer size returned
5900  * @ret_next_table: next block to read
5901  * @ret_next_index: next index to read
5902  *
5903  * Dump internal FW/HW data for debug purposes.
5904  *
5905  **/
5906 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
5907                                 u8 table_id, u32 start_index, u16 buff_size,
5908                                 void *buff, u16 *ret_buff_size,
5909                                 u8 *ret_next_table, u32 *ret_next_index,
5910                                 struct i40e_asq_cmd_details *cmd_details)
5911 {
5912         struct i40e_aq_desc desc;
5913         struct i40e_aqc_debug_dump_internals *cmd =
5914                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5915         struct i40e_aqc_debug_dump_internals *resp =
5916                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5917         enum i40e_status_code status;
5918
5919         if (buff_size == 0 || !buff)
5920                 return I40E_ERR_PARAM;
5921
5922         i40e_fill_default_direct_cmd_desc(&desc,
5923                                           i40e_aqc_opc_debug_dump_internals);
5924         /* Indirect Command */
5925         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5926         if (buff_size > I40E_AQ_LARGE_BUF)
5927                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5928
5929         cmd->cluster_id = cluster_id;
5930         cmd->table_id = table_id;
5931         cmd->idx = CPU_TO_LE32(start_index);
5932
5933         desc.datalen = CPU_TO_LE16(buff_size);
5934
5935         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5936         if (!status) {
5937                 if (ret_buff_size != NULL)
5938                         *ret_buff_size = LE16_TO_CPU(desc.datalen);
5939                 if (ret_next_table != NULL)
5940                         *ret_next_table = resp->table_id;
5941                 if (ret_next_index != NULL)
5942                         *ret_next_index = LE32_TO_CPU(resp->idx);
5943         }
5944
5945         return status;
5946 }
5947
5948 /**
5949  * i40e_read_bw_from_alt_ram
5950  * @hw: pointer to the hardware structure
5951  * @max_bw: pointer for max_bw read
5952  * @min_bw: pointer for min_bw read
5953  * @min_valid: pointer for bool that is true if min_bw is a valid value
5954  * @max_valid: pointer for bool that is true if max_bw is a valid value
5955  *
5956  * Read bw from the alternate ram for the given pf
5957  **/
5958 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
5959                                         u32 *max_bw, u32 *min_bw,
5960                                         bool *min_valid, bool *max_valid)
5961 {
5962         enum i40e_status_code status;
5963         u32 max_bw_addr, min_bw_addr;
5964
5965         /* Calculate the address of the min/max bw registers */
5966         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5967                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
5968                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5969         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5970                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
5971                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5972
5973         /* Read the bandwidths from alt ram */
5974         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
5975                                         min_bw_addr, min_bw);
5976
5977         if (*min_bw & I40E_ALT_BW_VALID_MASK)
5978                 *min_valid = true;
5979         else
5980                 *min_valid = false;
5981
5982         if (*max_bw & I40E_ALT_BW_VALID_MASK)
5983                 *max_valid = true;
5984         else
5985                 *max_valid = false;
5986
5987         return status;
5988 }
5989
5990 /**
5991  * i40e_aq_configure_partition_bw
5992  * @hw: pointer to the hardware structure
5993  * @bw_data: Buffer holding valid pfs and bw limits
5994  * @cmd_details: pointer to command details
5995  *
5996  * Configure partitions guaranteed/max bw
5997  **/
5998 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
5999                         struct i40e_aqc_configure_partition_bw_data *bw_data,
6000                         struct i40e_asq_cmd_details *cmd_details)
6001 {
6002         enum i40e_status_code status;
6003         struct i40e_aq_desc desc;
6004         u16 bwd_size = sizeof(*bw_data);
6005
6006         i40e_fill_default_direct_cmd_desc(&desc,
6007                                 i40e_aqc_opc_configure_partition_bw);
6008
6009         /* Indirect command */
6010         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6011         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6012
6013         desc.datalen = CPU_TO_LE16(bwd_size);
6014
6015         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6016
6017         return status;
6018 }
6019
6020 /**
6021  * i40e_read_phy_register
6022  * @hw: pointer to the HW structure
6023  * @page: registers page number
6024  * @reg: register address in the page
6025  * @phy_adr: PHY address on MDIO interface
6026  * @value: PHY register value
6027  *
6028  * Reads specified PHY register value
6029  **/
6030 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6031                                              u8 page, u16 reg, u8 phy_addr,
6032                                              u16 *value)
6033 {
6034         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6035         u32 command  = 0;
6036         u16 retry = 1000;
6037         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6038
6039         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6040                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6041                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6042                   (I40E_MDIO_OPCODE_ADDRESS) |
6043                   (I40E_MDIO_STCODE) |
6044                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6045                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6046         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6047         do {
6048                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6049                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6050                         status = I40E_SUCCESS;
6051                         break;
6052                 }
6053                 i40e_usec_delay(10);
6054                 retry--;
6055         } while (retry);
6056
6057         if (status) {
6058                 i40e_debug(hw, I40E_DEBUG_PHY,
6059                            "PHY: Can't write command to external PHY.\n");
6060                 goto phy_read_end;
6061         }
6062
6063         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6064                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6065                   (I40E_MDIO_OPCODE_READ) |
6066                   (I40E_MDIO_STCODE) |
6067                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6068                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6069         status = I40E_ERR_TIMEOUT;
6070         retry = 1000;
6071         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6072         do {
6073                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6074                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6075                         status = I40E_SUCCESS;
6076                         break;
6077                 }
6078                 i40e_usec_delay(10);
6079                 retry--;
6080         } while (retry);
6081
6082         if (!status) {
6083                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6084                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6085                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6086         } else {
6087                 i40e_debug(hw, I40E_DEBUG_PHY,
6088                            "PHY: Can't read register value from external PHY.\n");
6089         }
6090
6091 phy_read_end:
6092         return status;
6093 }
6094
6095 /**
6096  * i40e_write_phy_register
6097  * @hw: pointer to the HW structure
6098  * @page: registers page number
6099  * @reg: register address in the page
6100  * @phy_adr: PHY address on MDIO interface
6101  * @value: PHY register value
6102  *
6103  * Writes value to specified PHY register
6104  **/
6105 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6106                                               u8 page, u16 reg, u8 phy_addr,
6107                                               u16 value)
6108 {
6109         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6110         u32 command  = 0;
6111         u16 retry = 1000;
6112         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6113
6114         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6115                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6116                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6117                   (I40E_MDIO_OPCODE_ADDRESS) |
6118                   (I40E_MDIO_STCODE) |
6119                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6120                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6121         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6122         do {
6123                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6124                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6125                         status = I40E_SUCCESS;
6126                         break;
6127                 }
6128                 i40e_usec_delay(10);
6129                 retry--;
6130         } while (retry);
6131         if (status) {
6132                 i40e_debug(hw, I40E_DEBUG_PHY,
6133                            "PHY: Can't write command to external PHY.\n");
6134                 goto phy_write_end;
6135         }
6136
6137         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6138         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6139
6140         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6141                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6142                   (I40E_MDIO_OPCODE_WRITE) |
6143                   (I40E_MDIO_STCODE) |
6144                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6145                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6146         status = I40E_ERR_TIMEOUT;
6147         retry = 1000;
6148         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6149         do {
6150                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6151                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6152                         status = I40E_SUCCESS;
6153                         break;
6154                 }
6155                 i40e_usec_delay(10);
6156                 retry--;
6157         } while (retry);
6158
6159 phy_write_end:
6160         return status;
6161 }
6162
6163 /**
6164  * i40e_get_phy_address
6165  * @hw: pointer to the HW structure
6166  * @dev_num: PHY port num that address we want
6167  * @phy_addr: Returned PHY address
6168  *
6169  * Gets PHY address for current port
6170  **/
6171 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6172 {
6173         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6174         u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6175
6176         return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6177 }
6178
6179 /**
6180  * i40e_blink_phy_led
6181  * @hw: pointer to the HW structure
6182  * @time: time how long led will blinks in secs
6183  * @interval: gap between LED on and off in msecs
6184  *
6185  * Blinks PHY link LED
6186  **/
6187 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6188                                               u32 time, u32 interval)
6189 {
6190         enum i40e_status_code status = I40E_SUCCESS;
6191         u32 i;
6192         u16 led_ctl = 0;
6193         u16 gpio_led_port;
6194         u16 led_reg;
6195         u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6196         u8 phy_addr = 0;
6197         u8 port_num;
6198
6199         i = rd32(hw, I40E_PFGEN_PORTNUM);
6200         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6201         phy_addr = i40e_get_phy_address(hw, port_num);
6202
6203         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6204              led_addr++) {
6205                 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6206                                                 led_addr, phy_addr, &led_reg);
6207                 if (status)
6208                         goto phy_blinking_end;
6209                 led_ctl = led_reg;
6210                 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6211                         led_reg = 0;
6212                         status = i40e_write_phy_register(hw,
6213                                                          I40E_PHY_COM_REG_PAGE,
6214                                                          led_addr, phy_addr,
6215                                                          led_reg);
6216                         if (status)
6217                                 goto phy_blinking_end;
6218                         break;
6219                 }
6220         }
6221
6222         if (time > 0 && interval > 0) {
6223                 for (i = 0; i < time * 1000; i += interval) {
6224                         status = i40e_read_phy_register(hw,
6225                                                         I40E_PHY_COM_REG_PAGE,
6226                                                         led_addr, phy_addr,
6227                                                         &led_reg);
6228                         if (status)
6229                                 goto restore_config;
6230                         if (led_reg & I40E_PHY_LED_MANUAL_ON)
6231                                 led_reg = 0;
6232                         else
6233                                 led_reg = I40E_PHY_LED_MANUAL_ON;
6234                         status = i40e_write_phy_register(hw,
6235                                                          I40E_PHY_COM_REG_PAGE,
6236                                                          led_addr, phy_addr,
6237                                                          led_reg);
6238                         if (status)
6239                                 goto restore_config;
6240                         i40e_msec_delay(interval);
6241                 }
6242         }
6243
6244 restore_config:
6245         status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6246                                          phy_addr, led_ctl);
6247
6248 phy_blinking_end:
6249         return status;
6250 }
6251
6252 /**
6253  * i40e_led_get_phy - return current on/off mode
6254  * @hw: pointer to the hw struct
6255  * @led_addr: address of led register to use
6256  * @val: original value of register to use
6257  *
6258  **/
6259 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6260                                        u16 *val)
6261 {
6262         enum i40e_status_code status = I40E_SUCCESS;
6263         u16 gpio_led_port;
6264         u8 phy_addr = 0;
6265         u16 reg_val;
6266         u16 temp_addr;
6267         u8 port_num;
6268         u32 i;
6269
6270         temp_addr = I40E_PHY_LED_PROV_REG_1;
6271         i = rd32(hw, I40E_PFGEN_PORTNUM);
6272         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6273         phy_addr = i40e_get_phy_address(hw, port_num);
6274
6275         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6276              temp_addr++) {
6277                 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6278                                                 temp_addr, phy_addr, &reg_val);
6279                 if (status)
6280                         return status;
6281                 *val = reg_val;
6282                 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6283                         *led_addr = temp_addr;
6284                         break;
6285                 }
6286         }
6287         return status;
6288 }
6289
6290 /**
6291  * i40e_led_set_phy
6292  * @hw: pointer to the HW structure
6293  * @on: true or false
6294  * @mode: original val plus bit for set or ignore
6295  * Set led's on or off when controlled by the PHY
6296  *
6297  **/
6298 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6299                                        u16 led_addr, u32 mode)
6300 {
6301         enum i40e_status_code status = I40E_SUCCESS;
6302         u16 led_ctl = 0;
6303         u16 led_reg = 0;
6304         u8 phy_addr = 0;
6305         u8 port_num;
6306         u32 i;
6307
6308         i = rd32(hw, I40E_PFGEN_PORTNUM);
6309         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6310         phy_addr = i40e_get_phy_address(hw, port_num);
6311
6312         status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6313                                         phy_addr, &led_reg);
6314         if (status)
6315                 return status;
6316         led_ctl = led_reg;
6317         if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6318                 led_reg = 0;
6319                 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6320                                                  led_addr, phy_addr, led_reg);
6321                 if (status)
6322                         return status;
6323         }
6324         status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6325                                         led_addr, phy_addr, &led_reg);
6326         if (status)
6327                 goto restore_config;
6328         if (on)
6329                 led_reg = I40E_PHY_LED_MANUAL_ON;
6330         else
6331                 led_reg = 0;
6332         status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6333                                          led_addr, phy_addr, led_reg);
6334         if (status)
6335                 goto restore_config;
6336         if (mode & I40E_PHY_LED_MODE_ORIG) {
6337                 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6338                 status = i40e_write_phy_register(hw,
6339                                                  I40E_PHY_COM_REG_PAGE,
6340                                                  led_addr, phy_addr, led_ctl);
6341         }
6342         return status;
6343 restore_config:
6344         status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6345                                          phy_addr, led_ctl);
6346         return status;
6347 }
6348 #endif /* PF_DRIVER */
6349
6350 /**
6351  * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6352  * @hw: pointer to the hw struct
6353  * @reg_addr: register address
6354  * @reg_val: ptr to register value
6355  * @cmd_details: pointer to command details structure or NULL
6356  *
6357  * Use the firmware to read the Rx control register,
6358  * especially useful if the Rx unit is under heavy pressure
6359  **/
6360 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6361                                 u32 reg_addr, u32 *reg_val,
6362                                 struct i40e_asq_cmd_details *cmd_details)
6363 {
6364         struct i40e_aq_desc desc;
6365         struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
6366                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6367         enum i40e_status_code status;
6368
6369         if (reg_val == NULL)
6370                 return I40E_ERR_PARAM;
6371
6372         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
6373
6374         cmd_resp->address = CPU_TO_LE32(reg_addr);
6375
6376         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6377
6378         if (status == I40E_SUCCESS)
6379                 *reg_val = LE32_TO_CPU(cmd_resp->value);
6380
6381         return status;
6382 }
6383
6384 /**
6385  * i40e_read_rx_ctl - read from an Rx control register
6386  * @hw: pointer to the hw struct
6387  * @reg_addr: register address
6388  **/
6389 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
6390 {
6391         enum i40e_status_code status = I40E_SUCCESS;
6392         bool use_register;
6393         int retry = 5;
6394         u32 val = 0;
6395
6396         use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6397         if (!use_register) {
6398 do_retry:
6399                 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
6400                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6401                         i40e_msec_delay(1);
6402                         retry--;
6403                         goto do_retry;
6404                 }
6405         }
6406
6407         /* if the AQ access failed, try the old-fashioned way */
6408         if (status || use_register)
6409                 val = rd32(hw, reg_addr);
6410
6411         return val;
6412 }
6413
6414 /**
6415  * i40e_aq_rx_ctl_write_register
6416  * @hw: pointer to the hw struct
6417  * @reg_addr: register address
6418  * @reg_val: register value
6419  * @cmd_details: pointer to command details structure or NULL
6420  *
6421  * Use the firmware to write to an Rx control register,
6422  * especially useful if the Rx unit is under heavy pressure
6423  **/
6424 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
6425                                 u32 reg_addr, u32 reg_val,
6426                                 struct i40e_asq_cmd_details *cmd_details)
6427 {
6428         struct i40e_aq_desc desc;
6429         struct i40e_aqc_rx_ctl_reg_read_write *cmd =
6430                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6431         enum i40e_status_code status;
6432
6433         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
6434
6435         cmd->address = CPU_TO_LE32(reg_addr);
6436         cmd->value = CPU_TO_LE32(reg_val);
6437
6438         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6439
6440         return status;
6441 }
6442
6443 /**
6444  * i40e_write_rx_ctl - write to an Rx control register
6445  * @hw: pointer to the hw struct
6446  * @reg_addr: register address
6447  * @reg_val: register value
6448  **/
6449 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
6450 {
6451         enum i40e_status_code status = I40E_SUCCESS;
6452         bool use_register;
6453         int retry = 5;
6454
6455         use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6456         if (!use_register) {
6457 do_retry:
6458                 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
6459                                                        reg_val, NULL);
6460                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6461                         i40e_msec_delay(1);
6462                         retry--;
6463                         goto do_retry;
6464                 }
6465         }
6466
6467         /* if the AQ access failed, try the old-fashioned way */
6468         if (status || use_register)
6469                 wr32(hw, reg_addr, reg_val);
6470 }
6471 #ifdef VF_DRIVER
6472
6473 /**
6474  * i40e_aq_send_msg_to_pf
6475  * @hw: pointer to the hardware structure
6476  * @v_opcode: opcodes for VF-PF communication
6477  * @v_retval: return error code
6478  * @msg: pointer to the msg buffer
6479  * @msglen: msg length
6480  * @cmd_details: pointer to command details
6481  *
6482  * Send message to PF driver using admin queue. By default, this message
6483  * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
6484  * completion before returning.
6485  **/
6486 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
6487                                 enum i40e_virtchnl_ops v_opcode,
6488                                 enum i40e_status_code v_retval,
6489                                 u8 *msg, u16 msglen,
6490                                 struct i40e_asq_cmd_details *cmd_details)
6491 {
6492         struct i40e_aq_desc desc;
6493         struct i40e_asq_cmd_details details;
6494         enum i40e_status_code status;
6495
6496         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
6497         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
6498         desc.cookie_high = CPU_TO_LE32(v_opcode);
6499         desc.cookie_low = CPU_TO_LE32(v_retval);
6500         if (msglen) {
6501                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
6502                                                 | I40E_AQ_FLAG_RD));
6503                 if (msglen > I40E_AQ_LARGE_BUF)
6504                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6505                 desc.datalen = CPU_TO_LE16(msglen);
6506         }
6507         if (!cmd_details) {
6508                 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
6509                 details.async = true;
6510                 cmd_details = &details;
6511         }
6512         status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
6513                                        msglen, cmd_details);
6514         return status;
6515 }
6516
6517 /**
6518  * i40e_vf_parse_hw_config
6519  * @hw: pointer to the hardware structure
6520  * @msg: pointer to the virtual channel VF resource structure
6521  *
6522  * Given a VF resource message from the PF, populate the hw struct
6523  * with appropriate information.
6524  **/
6525 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
6526                              struct i40e_virtchnl_vf_resource *msg)
6527 {
6528         struct i40e_virtchnl_vsi_resource *vsi_res;
6529         int i;
6530
6531         vsi_res = &msg->vsi_res[0];
6532
6533         hw->dev_caps.num_vsis = msg->num_vsis;
6534         hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
6535         hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
6536         hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
6537         hw->dev_caps.dcb = msg->vf_offload_flags &
6538                            I40E_VIRTCHNL_VF_OFFLOAD_L2;
6539         hw->dev_caps.fcoe = (msg->vf_offload_flags &
6540                              I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
6541         hw->dev_caps.iwarp = (msg->vf_offload_flags &
6542                               I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
6543         for (i = 0; i < msg->num_vsis; i++) {
6544                 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
6545                         i40e_memcpy(hw->mac.perm_addr,
6546                                     vsi_res->default_mac_addr,
6547                                     I40E_ETH_LENGTH_OF_ADDRESS,
6548                                     I40E_NONDMA_TO_NONDMA);
6549                         i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
6550                                     I40E_ETH_LENGTH_OF_ADDRESS,
6551                                     I40E_NONDMA_TO_NONDMA);
6552                 }
6553                 vsi_res++;
6554         }
6555 }
6556
6557 /**
6558  * i40e_vf_reset
6559  * @hw: pointer to the hardware structure
6560  *
6561  * Send a VF_RESET message to the PF. Does not wait for response from PF
6562  * as none will be forthcoming. Immediately after calling this function,
6563  * the admin queue should be shut down and (optionally) reinitialized.
6564  **/
6565 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
6566 {
6567         return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
6568                                       I40E_SUCCESS, NULL, 0, NULL);
6569 }
6570 #endif /* VF_DRIVER */
6571 #ifdef X722_SUPPORT
6572
6573 /**
6574  * i40e_aq_set_arp_proxy_config
6575  * @hw: pointer to the HW structure
6576  * @proxy_config - pointer to proxy config command table struct
6577  * @cmd_details: pointer to command details
6578  *
6579  * Set ARP offload parameters from pre-populated
6580  * i40e_aqc_arp_proxy_data struct
6581  **/
6582 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
6583                                 struct i40e_aqc_arp_proxy_data *proxy_config,
6584                                 struct i40e_asq_cmd_details *cmd_details)
6585 {
6586         struct i40e_aq_desc desc;
6587         enum i40e_status_code status;
6588
6589         if (!proxy_config)
6590                 return I40E_ERR_PARAM;
6591
6592         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
6593
6594         desc.params.external.addr_high =
6595                                   CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
6596         desc.params.external.addr_low =
6597                                   CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
6598
6599         status = i40e_asq_send_command(hw, &desc, proxy_config,
6600                                        sizeof(struct i40e_aqc_arp_proxy_data),
6601                                        cmd_details);
6602
6603         return status;
6604 }
6605
6606 /**
6607  * i40e_aq_opc_set_ns_proxy_table_entry
6608  * @hw: pointer to the HW structure
6609  * @ns_proxy_table_entry: pointer to NS table entry command struct
6610  * @cmd_details: pointer to command details
6611  *
6612  * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
6613  * from pre-populated i40e_aqc_ns_proxy_data struct
6614  **/
6615 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
6616                         struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
6617                         struct i40e_asq_cmd_details *cmd_details)
6618 {
6619         struct i40e_aq_desc desc;
6620         enum i40e_status_code status;
6621
6622         if (!ns_proxy_table_entry)
6623                 return I40E_ERR_PARAM;
6624
6625         i40e_fill_default_direct_cmd_desc(&desc,
6626                                 i40e_aqc_opc_set_ns_proxy_table_entry);
6627
6628         desc.params.external.addr_high =
6629                 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
6630         desc.params.external.addr_low =
6631                 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
6632
6633         status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
6634                                        sizeof(struct i40e_aqc_ns_proxy_data),
6635                                        cmd_details);
6636
6637         return status;
6638 }
6639
6640 /**
6641  * i40e_aq_set_clear_wol_filter
6642  * @hw: pointer to the hw struct
6643  * @filter_index: index of filter to modify (0-7)
6644  * @filter: buffer containing filter to be set
6645  * @set_filter: true to set filter, false to clear filter
6646  * @no_wol_tco: if true, pass through packets cannot cause wake-up
6647  *              if false, pass through packets may cause wake-up
6648  * @filter_valid: true if filter action is valid
6649  * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
6650  * @cmd_details: pointer to command details structure or NULL
6651  *
6652  * Set or clear WoL filter for port attached to the PF
6653  **/
6654 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
6655                                 u8 filter_index,
6656                                 struct i40e_aqc_set_wol_filter_data *filter,
6657                                 bool set_filter, bool no_wol_tco,
6658                                 bool filter_valid, bool no_wol_tco_valid,
6659                                 struct i40e_asq_cmd_details *cmd_details)
6660 {
6661         struct i40e_aq_desc desc;
6662         struct i40e_aqc_set_wol_filter *cmd =
6663                 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
6664         enum i40e_status_code status;
6665         u16 cmd_flags = 0;
6666         u16 valid_flags = 0;
6667         u16 buff_len = 0;
6668
6669         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
6670
6671         if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
6672                 return  I40E_ERR_PARAM;
6673         cmd->filter_index = CPU_TO_LE16(filter_index);
6674
6675         if (set_filter) {
6676                 if (!filter)
6677                         return  I40E_ERR_PARAM;
6678                 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
6679                 buff_len = sizeof(*filter);
6680         }
6681         if (no_wol_tco)
6682                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
6683         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
6684
6685         if (filter_valid)
6686                 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
6687         if (no_wol_tco_valid)
6688                 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
6689         cmd->valid_flags = CPU_TO_LE16(valid_flags);
6690
6691         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
6692         cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
6693
6694         status = i40e_asq_send_command(hw, &desc, filter,
6695                                        buff_len, cmd_details);
6696
6697         return status;
6698 }
6699
6700 /**
6701  * i40e_aq_get_wake_event_reason
6702  * @hw: pointer to the hw struct
6703  * @wake_reason: return value, index of matching filter
6704  * @cmd_details: pointer to command details structure or NULL
6705  *
6706  * Get information for the reason of a Wake Up event
6707  **/
6708 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
6709                                 u16 *wake_reason,
6710                                 struct i40e_asq_cmd_details *cmd_details)
6711 {
6712         struct i40e_aq_desc desc;
6713         struct i40e_aqc_get_wake_reason_completion *resp =
6714                 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
6715         enum i40e_status_code status;
6716
6717         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
6718
6719         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6720
6721         if (status == I40E_SUCCESS)
6722                 *wake_reason = LE16_TO_CPU(resp->wake_reason);
6723
6724         return status;
6725 }
6726
6727 #endif /* X722_SUPPORT */