1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2018
6 #include "i40e_adminq.h"
7 #include "i40e_prototype.h"
11 * i40e_set_mac_type - Sets MAC type
12 * @hw: pointer to the HW structure
14 * This function sets the mac type of the adapter based on the
15 * vendor ID and device ID stored in the hw structure.
17 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
18 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
20 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
23 enum i40e_status_code status = I40E_SUCCESS;
25 DEBUGFUNC("i40e_set_mac_type\n");
27 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
28 switch (hw->device_id) {
29 case I40E_DEV_ID_SFP_XL710:
30 case I40E_DEV_ID_QEMU:
31 case I40E_DEV_ID_KX_B:
32 case I40E_DEV_ID_KX_C:
33 case I40E_DEV_ID_QSFP_A:
34 case I40E_DEV_ID_QSFP_B:
35 case I40E_DEV_ID_QSFP_C:
36 case I40E_DEV_ID_10G_BASE_T:
37 case I40E_DEV_ID_10G_BASE_T4:
38 case I40E_DEV_ID_10G_BASE_T_BC:
39 case I40E_DEV_ID_20G_KR2:
40 case I40E_DEV_ID_20G_KR2_A:
41 case I40E_DEV_ID_25G_B:
42 case I40E_DEV_ID_25G_SFP28:
43 case I40E_DEV_ID_X710_N3000:
44 case I40E_DEV_ID_XXV710_N3000:
45 hw->mac.type = I40E_MAC_XL710;
47 #ifdef X722_A0_SUPPORT
48 case I40E_DEV_ID_X722_A0:
50 case I40E_DEV_ID_KX_X722:
51 case I40E_DEV_ID_QSFP_X722:
52 case I40E_DEV_ID_SFP_X722:
53 case I40E_DEV_ID_1G_BASE_T_X722:
54 case I40E_DEV_ID_10G_BASE_T_X722:
55 case I40E_DEV_ID_SFP_I_X722:
56 hw->mac.type = I40E_MAC_X722;
58 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
59 case I40E_DEV_ID_X722_VF:
60 #ifdef X722_A0_SUPPORT
61 case I40E_DEV_ID_X722_A0_VF:
63 hw->mac.type = I40E_MAC_X722_VF;
65 #endif /* INTEGRATED_VF || VF_DRIVER */
66 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
68 case I40E_DEV_ID_VF_HV:
69 case I40E_DEV_ID_ADAPTIVE_VF:
70 hw->mac.type = I40E_MAC_VF;
74 hw->mac.type = I40E_MAC_GENERIC;
78 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
81 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
82 hw->mac.type, status);
87 * i40e_aq_str - convert AQ err code to a string
88 * @hw: pointer to the HW structure
89 * @aq_err: the AQ error code to convert
91 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
96 case I40E_AQ_RC_EPERM:
97 return "I40E_AQ_RC_EPERM";
98 case I40E_AQ_RC_ENOENT:
99 return "I40E_AQ_RC_ENOENT";
100 case I40E_AQ_RC_ESRCH:
101 return "I40E_AQ_RC_ESRCH";
102 case I40E_AQ_RC_EINTR:
103 return "I40E_AQ_RC_EINTR";
105 return "I40E_AQ_RC_EIO";
106 case I40E_AQ_RC_ENXIO:
107 return "I40E_AQ_RC_ENXIO";
108 case I40E_AQ_RC_E2BIG:
109 return "I40E_AQ_RC_E2BIG";
110 case I40E_AQ_RC_EAGAIN:
111 return "I40E_AQ_RC_EAGAIN";
112 case I40E_AQ_RC_ENOMEM:
113 return "I40E_AQ_RC_ENOMEM";
114 case I40E_AQ_RC_EACCES:
115 return "I40E_AQ_RC_EACCES";
116 case I40E_AQ_RC_EFAULT:
117 return "I40E_AQ_RC_EFAULT";
118 case I40E_AQ_RC_EBUSY:
119 return "I40E_AQ_RC_EBUSY";
120 case I40E_AQ_RC_EEXIST:
121 return "I40E_AQ_RC_EEXIST";
122 case I40E_AQ_RC_EINVAL:
123 return "I40E_AQ_RC_EINVAL";
124 case I40E_AQ_RC_ENOTTY:
125 return "I40E_AQ_RC_ENOTTY";
126 case I40E_AQ_RC_ENOSPC:
127 return "I40E_AQ_RC_ENOSPC";
128 case I40E_AQ_RC_ENOSYS:
129 return "I40E_AQ_RC_ENOSYS";
130 case I40E_AQ_RC_ERANGE:
131 return "I40E_AQ_RC_ERANGE";
132 case I40E_AQ_RC_EFLUSHED:
133 return "I40E_AQ_RC_EFLUSHED";
134 case I40E_AQ_RC_BAD_ADDR:
135 return "I40E_AQ_RC_BAD_ADDR";
136 case I40E_AQ_RC_EMODE:
137 return "I40E_AQ_RC_EMODE";
138 case I40E_AQ_RC_EFBIG:
139 return "I40E_AQ_RC_EFBIG";
142 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
147 * i40e_stat_str - convert status err code to a string
148 * @hw: pointer to the HW structure
149 * @stat_err: the status error code to convert
151 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
157 return "I40E_ERR_NVM";
158 case I40E_ERR_NVM_CHECKSUM:
159 return "I40E_ERR_NVM_CHECKSUM";
161 return "I40E_ERR_PHY";
162 case I40E_ERR_CONFIG:
163 return "I40E_ERR_CONFIG";
165 return "I40E_ERR_PARAM";
166 case I40E_ERR_MAC_TYPE:
167 return "I40E_ERR_MAC_TYPE";
168 case I40E_ERR_UNKNOWN_PHY:
169 return "I40E_ERR_UNKNOWN_PHY";
170 case I40E_ERR_LINK_SETUP:
171 return "I40E_ERR_LINK_SETUP";
172 case I40E_ERR_ADAPTER_STOPPED:
173 return "I40E_ERR_ADAPTER_STOPPED";
174 case I40E_ERR_INVALID_MAC_ADDR:
175 return "I40E_ERR_INVALID_MAC_ADDR";
176 case I40E_ERR_DEVICE_NOT_SUPPORTED:
177 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
178 case I40E_ERR_MASTER_REQUESTS_PENDING:
179 return "I40E_ERR_MASTER_REQUESTS_PENDING";
180 case I40E_ERR_INVALID_LINK_SETTINGS:
181 return "I40E_ERR_INVALID_LINK_SETTINGS";
182 case I40E_ERR_AUTONEG_NOT_COMPLETE:
183 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
184 case I40E_ERR_RESET_FAILED:
185 return "I40E_ERR_RESET_FAILED";
186 case I40E_ERR_SWFW_SYNC:
187 return "I40E_ERR_SWFW_SYNC";
188 case I40E_ERR_NO_AVAILABLE_VSI:
189 return "I40E_ERR_NO_AVAILABLE_VSI";
190 case I40E_ERR_NO_MEMORY:
191 return "I40E_ERR_NO_MEMORY";
192 case I40E_ERR_BAD_PTR:
193 return "I40E_ERR_BAD_PTR";
194 case I40E_ERR_RING_FULL:
195 return "I40E_ERR_RING_FULL";
196 case I40E_ERR_INVALID_PD_ID:
197 return "I40E_ERR_INVALID_PD_ID";
198 case I40E_ERR_INVALID_QP_ID:
199 return "I40E_ERR_INVALID_QP_ID";
200 case I40E_ERR_INVALID_CQ_ID:
201 return "I40E_ERR_INVALID_CQ_ID";
202 case I40E_ERR_INVALID_CEQ_ID:
203 return "I40E_ERR_INVALID_CEQ_ID";
204 case I40E_ERR_INVALID_AEQ_ID:
205 return "I40E_ERR_INVALID_AEQ_ID";
206 case I40E_ERR_INVALID_SIZE:
207 return "I40E_ERR_INVALID_SIZE";
208 case I40E_ERR_INVALID_ARP_INDEX:
209 return "I40E_ERR_INVALID_ARP_INDEX";
210 case I40E_ERR_INVALID_FPM_FUNC_ID:
211 return "I40E_ERR_INVALID_FPM_FUNC_ID";
212 case I40E_ERR_QP_INVALID_MSG_SIZE:
213 return "I40E_ERR_QP_INVALID_MSG_SIZE";
214 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
215 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
216 case I40E_ERR_INVALID_FRAG_COUNT:
217 return "I40E_ERR_INVALID_FRAG_COUNT";
218 case I40E_ERR_QUEUE_EMPTY:
219 return "I40E_ERR_QUEUE_EMPTY";
220 case I40E_ERR_INVALID_ALIGNMENT:
221 return "I40E_ERR_INVALID_ALIGNMENT";
222 case I40E_ERR_FLUSHED_QUEUE:
223 return "I40E_ERR_FLUSHED_QUEUE";
224 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
225 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
226 case I40E_ERR_INVALID_IMM_DATA_SIZE:
227 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
228 case I40E_ERR_TIMEOUT:
229 return "I40E_ERR_TIMEOUT";
230 case I40E_ERR_OPCODE_MISMATCH:
231 return "I40E_ERR_OPCODE_MISMATCH";
232 case I40E_ERR_CQP_COMPL_ERROR:
233 return "I40E_ERR_CQP_COMPL_ERROR";
234 case I40E_ERR_INVALID_VF_ID:
235 return "I40E_ERR_INVALID_VF_ID";
236 case I40E_ERR_INVALID_HMCFN_ID:
237 return "I40E_ERR_INVALID_HMCFN_ID";
238 case I40E_ERR_BACKING_PAGE_ERROR:
239 return "I40E_ERR_BACKING_PAGE_ERROR";
240 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
241 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
242 case I40E_ERR_INVALID_PBLE_INDEX:
243 return "I40E_ERR_INVALID_PBLE_INDEX";
244 case I40E_ERR_INVALID_SD_INDEX:
245 return "I40E_ERR_INVALID_SD_INDEX";
246 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
247 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
248 case I40E_ERR_INVALID_SD_TYPE:
249 return "I40E_ERR_INVALID_SD_TYPE";
250 case I40E_ERR_MEMCPY_FAILED:
251 return "I40E_ERR_MEMCPY_FAILED";
252 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
253 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
254 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
255 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
256 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
257 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
258 case I40E_ERR_SRQ_ENABLED:
259 return "I40E_ERR_SRQ_ENABLED";
260 case I40E_ERR_ADMIN_QUEUE_ERROR:
261 return "I40E_ERR_ADMIN_QUEUE_ERROR";
262 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
263 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
264 case I40E_ERR_BUF_TOO_SHORT:
265 return "I40E_ERR_BUF_TOO_SHORT";
266 case I40E_ERR_ADMIN_QUEUE_FULL:
267 return "I40E_ERR_ADMIN_QUEUE_FULL";
268 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
269 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
270 case I40E_ERR_BAD_IWARP_CQE:
271 return "I40E_ERR_BAD_IWARP_CQE";
272 case I40E_ERR_NVM_BLANK_MODE:
273 return "I40E_ERR_NVM_BLANK_MODE";
274 case I40E_ERR_NOT_IMPLEMENTED:
275 return "I40E_ERR_NOT_IMPLEMENTED";
276 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
277 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
278 case I40E_ERR_DIAG_TEST_FAILED:
279 return "I40E_ERR_DIAG_TEST_FAILED";
280 case I40E_ERR_NOT_READY:
281 return "I40E_ERR_NOT_READY";
282 case I40E_NOT_SUPPORTED:
283 return "I40E_NOT_SUPPORTED";
284 case I40E_ERR_FIRMWARE_API_VERSION:
285 return "I40E_ERR_FIRMWARE_API_VERSION";
286 case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR:
287 return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR";
290 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
296 * @hw: debug mask related to admin queue
298 * @desc: pointer to admin queue descriptor
299 * @buffer: pointer to command buffer
300 * @buf_len: max length of buffer
302 * Dumps debug log about adminq command with descriptor contents.
304 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
305 void *buffer, u16 buf_len)
307 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
308 u8 *buf = (u8 *)buffer;
312 if ((!(mask & hw->debug_mask)) || (desc == NULL))
315 len = LE16_TO_CPU(aq_desc->datalen);
318 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
319 LE16_TO_CPU(aq_desc->opcode),
320 LE16_TO_CPU(aq_desc->flags),
321 LE16_TO_CPU(aq_desc->datalen),
322 LE16_TO_CPU(aq_desc->retval));
323 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
324 LE32_TO_CPU(aq_desc->cookie_high),
325 LE32_TO_CPU(aq_desc->cookie_low));
326 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
327 LE32_TO_CPU(aq_desc->params.internal.param0),
328 LE32_TO_CPU(aq_desc->params.internal.param1));
329 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
330 LE32_TO_CPU(aq_desc->params.external.addr_high),
331 LE32_TO_CPU(aq_desc->params.external.addr_low));
333 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
334 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
337 /* write the full 16-byte chunks */
338 for (i = 0; i < (len - 16); i += 16)
340 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
341 i, buf[i], buf[i+1], buf[i+2], buf[i+3],
342 buf[i+4], buf[i+5], buf[i+6], buf[i+7],
343 buf[i+8], buf[i+9], buf[i+10], buf[i+11],
344 buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
345 /* the most we could have left is 16 bytes, pad with zeros */
351 memset(d_buf, 0, sizeof(d_buf));
352 for (j = 0; i < len; j++, i++)
355 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
356 i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
357 d_buf[4], d_buf[5], d_buf[6], d_buf[7],
358 d_buf[8], d_buf[9], d_buf[10], d_buf[11],
359 d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
365 * i40e_check_asq_alive
366 * @hw: pointer to the hw struct
368 * Returns true if Queue is enabled else false.
370 bool i40e_check_asq_alive(struct i40e_hw *hw)
376 return !!(rd32(hw, hw->aq.asq.len) &
377 I40E_PF_ATQLEN_ATQENABLE_MASK);
379 return !!(rd32(hw, hw->aq.asq.len) &
380 I40E_PF_ATQLEN_ATQENABLE_MASK);
381 #endif /* INTEGRATED_VF */
382 #endif /* PF_DRIVER */
386 return !!(rd32(hw, hw->aq.asq.len) &
387 I40E_VF_ATQLEN1_ATQENABLE_MASK);
389 return !!(rd32(hw, hw->aq.asq.len) &
390 I40E_VF_ATQLEN1_ATQENABLE_MASK);
391 #endif /* INTEGRATED_VF */
392 #endif /* VF_DRIVER */
397 * i40e_aq_queue_shutdown
398 * @hw: pointer to the hw struct
399 * @unloading: is the driver unloading itself
401 * Tell the Firmware that we're shutting down the AdminQ and whether
402 * or not the driver is unloading as well.
404 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
407 struct i40e_aq_desc desc;
408 struct i40e_aqc_queue_shutdown *cmd =
409 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
410 enum i40e_status_code status;
412 i40e_fill_default_direct_cmd_desc(&desc,
413 i40e_aqc_opc_queue_shutdown);
416 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
417 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
423 * i40e_aq_get_set_rss_lut
424 * @hw: pointer to the hardware structure
425 * @vsi_id: vsi fw index
426 * @pf_lut: for PF table set true, for VSI table set false
427 * @lut: pointer to the lut buffer provided by the caller
428 * @lut_size: size of the lut buffer
429 * @set: set true to set the table, false to get the table
431 * Internal function to get or set RSS look up table
433 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
434 u16 vsi_id, bool pf_lut,
435 u8 *lut, u16 lut_size,
438 enum i40e_status_code status;
439 struct i40e_aq_desc desc;
440 struct i40e_aqc_get_set_rss_lut *cmd_resp =
441 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
444 i40e_fill_default_direct_cmd_desc(&desc,
445 i40e_aqc_opc_set_rss_lut);
447 i40e_fill_default_direct_cmd_desc(&desc,
448 i40e_aqc_opc_get_rss_lut);
450 /* Indirect command */
451 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
452 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
455 CPU_TO_LE16((u16)((vsi_id <<
456 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
457 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
458 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
461 cmd_resp->flags |= CPU_TO_LE16((u16)
462 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
463 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
464 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
466 cmd_resp->flags |= CPU_TO_LE16((u16)
467 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
468 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
469 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
471 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
477 * i40e_aq_get_rss_lut
478 * @hw: pointer to the hardware structure
479 * @vsi_id: vsi fw index
480 * @pf_lut: for PF table set true, for VSI table set false
481 * @lut: pointer to the lut buffer provided by the caller
482 * @lut_size: size of the lut buffer
484 * get the RSS lookup table, PF or VSI type
486 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
487 bool pf_lut, u8 *lut, u16 lut_size)
489 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
494 * i40e_aq_set_rss_lut
495 * @hw: pointer to the hardware structure
496 * @vsi_id: vsi fw index
497 * @pf_lut: for PF table set true, for VSI table set false
498 * @lut: pointer to the lut buffer provided by the caller
499 * @lut_size: size of the lut buffer
501 * set the RSS lookup table, PF or VSI type
503 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
504 bool pf_lut, u8 *lut, u16 lut_size)
506 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
510 * i40e_aq_get_set_rss_key
511 * @hw: pointer to the hw struct
512 * @vsi_id: vsi fw index
513 * @key: pointer to key info struct
514 * @set: set true to set the key, false to get the key
516 * get the RSS key per VSI
518 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
520 struct i40e_aqc_get_set_rss_key_data *key,
523 enum i40e_status_code status;
524 struct i40e_aq_desc desc;
525 struct i40e_aqc_get_set_rss_key *cmd_resp =
526 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
527 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
530 i40e_fill_default_direct_cmd_desc(&desc,
531 i40e_aqc_opc_set_rss_key);
533 i40e_fill_default_direct_cmd_desc(&desc,
534 i40e_aqc_opc_get_rss_key);
536 /* Indirect command */
537 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
538 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
541 CPU_TO_LE16((u16)((vsi_id <<
542 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
543 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
544 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
546 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
552 * i40e_aq_get_rss_key
553 * @hw: pointer to the hw struct
554 * @vsi_id: vsi fw index
555 * @key: pointer to key info struct
558 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
560 struct i40e_aqc_get_set_rss_key_data *key)
562 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
566 * i40e_aq_set_rss_key
567 * @hw: pointer to the hw struct
568 * @vsi_id: vsi fw index
569 * @key: pointer to key info struct
571 * set the RSS key per VSI
573 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
575 struct i40e_aqc_get_set_rss_key_data *key)
577 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
580 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
581 * hardware to a bit-field that can be used by SW to more easily determine the
584 * Macros are used to shorten the table lines and make this table human
587 * We store the PTYPE in the top byte of the bit field - this is just so that
588 * we can check that the table doesn't have a row missing, as the index into
589 * the table should be the PTYPE.
593 * IF NOT i40e_ptype_lookup[ptype].known
596 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
597 * Use the rest of the fields to look at the tunnels, inner protocols, etc
599 * Use the enum i40e_rx_l2_ptype to decode the packet type
603 /* macro to make the table lines short */
604 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
607 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
608 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
609 I40E_RX_PTYPE_##OUTER_FRAG, \
610 I40E_RX_PTYPE_TUNNEL_##T, \
611 I40E_RX_PTYPE_TUNNEL_END_##TE, \
612 I40E_RX_PTYPE_##TEF, \
613 I40E_RX_PTYPE_INNER_PROT_##I, \
614 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
616 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
617 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
619 /* shorter macros makes the table fit but are terse */
620 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
621 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
622 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
624 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
625 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
626 /* L2 Packet types */
627 I40E_PTT_UNUSED_ENTRY(0),
628 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
629 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
630 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
631 I40E_PTT_UNUSED_ENTRY(4),
632 I40E_PTT_UNUSED_ENTRY(5),
633 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
634 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
635 I40E_PTT_UNUSED_ENTRY(8),
636 I40E_PTT_UNUSED_ENTRY(9),
637 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
638 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
639 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
640 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
641 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
642 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
643 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
644 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
645 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
646 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
647 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
648 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
650 /* Non Tunneled IPv4 */
651 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
652 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
653 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
654 I40E_PTT_UNUSED_ENTRY(25),
655 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
656 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
657 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
660 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
661 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
662 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
663 I40E_PTT_UNUSED_ENTRY(32),
664 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
665 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
666 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
669 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
670 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
671 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
672 I40E_PTT_UNUSED_ENTRY(39),
673 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
674 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
675 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
677 /* IPv4 --> GRE/NAT */
678 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
680 /* IPv4 --> GRE/NAT --> IPv4 */
681 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
682 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
683 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
684 I40E_PTT_UNUSED_ENTRY(47),
685 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
686 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
687 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
689 /* IPv4 --> GRE/NAT --> IPv6 */
690 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
691 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
692 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
693 I40E_PTT_UNUSED_ENTRY(54),
694 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
695 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
696 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
698 /* IPv4 --> GRE/NAT --> MAC */
699 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
701 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
702 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
703 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
704 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
705 I40E_PTT_UNUSED_ENTRY(62),
706 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
707 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
708 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
710 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
711 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
712 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
713 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
714 I40E_PTT_UNUSED_ENTRY(69),
715 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
716 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
717 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
719 /* IPv4 --> GRE/NAT --> MAC/VLAN */
720 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
722 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
723 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
724 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
725 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
726 I40E_PTT_UNUSED_ENTRY(77),
727 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
728 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
729 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
731 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
732 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
733 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
734 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
735 I40E_PTT_UNUSED_ENTRY(84),
736 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
737 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
738 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
740 /* Non Tunneled IPv6 */
741 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
742 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
743 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4),
744 I40E_PTT_UNUSED_ENTRY(91),
745 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
746 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
747 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
750 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
751 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
752 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
753 I40E_PTT_UNUSED_ENTRY(98),
754 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
755 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
756 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
759 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
760 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
761 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
762 I40E_PTT_UNUSED_ENTRY(105),
763 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
764 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
765 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
767 /* IPv6 --> GRE/NAT */
768 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
770 /* IPv6 --> GRE/NAT -> IPv4 */
771 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
772 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
773 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
774 I40E_PTT_UNUSED_ENTRY(113),
775 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
776 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
777 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
779 /* IPv6 --> GRE/NAT -> IPv6 */
780 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
781 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
782 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
783 I40E_PTT_UNUSED_ENTRY(120),
784 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
785 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
786 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
788 /* IPv6 --> GRE/NAT -> MAC */
789 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
791 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
792 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
793 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
794 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
795 I40E_PTT_UNUSED_ENTRY(128),
796 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
797 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
798 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
800 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
801 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
802 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
803 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
804 I40E_PTT_UNUSED_ENTRY(135),
805 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
806 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
807 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
809 /* IPv6 --> GRE/NAT -> MAC/VLAN */
810 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
812 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
813 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
814 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
815 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
816 I40E_PTT_UNUSED_ENTRY(143),
817 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
818 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
819 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
821 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
822 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
823 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
824 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
825 I40E_PTT_UNUSED_ENTRY(150),
826 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
827 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
828 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
831 I40E_PTT_UNUSED_ENTRY(154),
832 I40E_PTT_UNUSED_ENTRY(155),
833 I40E_PTT_UNUSED_ENTRY(156),
834 I40E_PTT_UNUSED_ENTRY(157),
835 I40E_PTT_UNUSED_ENTRY(158),
836 I40E_PTT_UNUSED_ENTRY(159),
838 I40E_PTT_UNUSED_ENTRY(160),
839 I40E_PTT_UNUSED_ENTRY(161),
840 I40E_PTT_UNUSED_ENTRY(162),
841 I40E_PTT_UNUSED_ENTRY(163),
842 I40E_PTT_UNUSED_ENTRY(164),
843 I40E_PTT_UNUSED_ENTRY(165),
844 I40E_PTT_UNUSED_ENTRY(166),
845 I40E_PTT_UNUSED_ENTRY(167),
846 I40E_PTT_UNUSED_ENTRY(168),
847 I40E_PTT_UNUSED_ENTRY(169),
849 I40E_PTT_UNUSED_ENTRY(170),
850 I40E_PTT_UNUSED_ENTRY(171),
851 I40E_PTT_UNUSED_ENTRY(172),
852 I40E_PTT_UNUSED_ENTRY(173),
853 I40E_PTT_UNUSED_ENTRY(174),
854 I40E_PTT_UNUSED_ENTRY(175),
855 I40E_PTT_UNUSED_ENTRY(176),
856 I40E_PTT_UNUSED_ENTRY(177),
857 I40E_PTT_UNUSED_ENTRY(178),
858 I40E_PTT_UNUSED_ENTRY(179),
860 I40E_PTT_UNUSED_ENTRY(180),
861 I40E_PTT_UNUSED_ENTRY(181),
862 I40E_PTT_UNUSED_ENTRY(182),
863 I40E_PTT_UNUSED_ENTRY(183),
864 I40E_PTT_UNUSED_ENTRY(184),
865 I40E_PTT_UNUSED_ENTRY(185),
866 I40E_PTT_UNUSED_ENTRY(186),
867 I40E_PTT_UNUSED_ENTRY(187),
868 I40E_PTT_UNUSED_ENTRY(188),
869 I40E_PTT_UNUSED_ENTRY(189),
871 I40E_PTT_UNUSED_ENTRY(190),
872 I40E_PTT_UNUSED_ENTRY(191),
873 I40E_PTT_UNUSED_ENTRY(192),
874 I40E_PTT_UNUSED_ENTRY(193),
875 I40E_PTT_UNUSED_ENTRY(194),
876 I40E_PTT_UNUSED_ENTRY(195),
877 I40E_PTT_UNUSED_ENTRY(196),
878 I40E_PTT_UNUSED_ENTRY(197),
879 I40E_PTT_UNUSED_ENTRY(198),
880 I40E_PTT_UNUSED_ENTRY(199),
882 I40E_PTT_UNUSED_ENTRY(200),
883 I40E_PTT_UNUSED_ENTRY(201),
884 I40E_PTT_UNUSED_ENTRY(202),
885 I40E_PTT_UNUSED_ENTRY(203),
886 I40E_PTT_UNUSED_ENTRY(204),
887 I40E_PTT_UNUSED_ENTRY(205),
888 I40E_PTT_UNUSED_ENTRY(206),
889 I40E_PTT_UNUSED_ENTRY(207),
890 I40E_PTT_UNUSED_ENTRY(208),
891 I40E_PTT_UNUSED_ENTRY(209),
893 I40E_PTT_UNUSED_ENTRY(210),
894 I40E_PTT_UNUSED_ENTRY(211),
895 I40E_PTT_UNUSED_ENTRY(212),
896 I40E_PTT_UNUSED_ENTRY(213),
897 I40E_PTT_UNUSED_ENTRY(214),
898 I40E_PTT_UNUSED_ENTRY(215),
899 I40E_PTT_UNUSED_ENTRY(216),
900 I40E_PTT_UNUSED_ENTRY(217),
901 I40E_PTT_UNUSED_ENTRY(218),
902 I40E_PTT_UNUSED_ENTRY(219),
904 I40E_PTT_UNUSED_ENTRY(220),
905 I40E_PTT_UNUSED_ENTRY(221),
906 I40E_PTT_UNUSED_ENTRY(222),
907 I40E_PTT_UNUSED_ENTRY(223),
908 I40E_PTT_UNUSED_ENTRY(224),
909 I40E_PTT_UNUSED_ENTRY(225),
910 I40E_PTT_UNUSED_ENTRY(226),
911 I40E_PTT_UNUSED_ENTRY(227),
912 I40E_PTT_UNUSED_ENTRY(228),
913 I40E_PTT_UNUSED_ENTRY(229),
915 I40E_PTT_UNUSED_ENTRY(230),
916 I40E_PTT_UNUSED_ENTRY(231),
917 I40E_PTT_UNUSED_ENTRY(232),
918 I40E_PTT_UNUSED_ENTRY(233),
919 I40E_PTT_UNUSED_ENTRY(234),
920 I40E_PTT_UNUSED_ENTRY(235),
921 I40E_PTT_UNUSED_ENTRY(236),
922 I40E_PTT_UNUSED_ENTRY(237),
923 I40E_PTT_UNUSED_ENTRY(238),
924 I40E_PTT_UNUSED_ENTRY(239),
926 I40E_PTT_UNUSED_ENTRY(240),
927 I40E_PTT_UNUSED_ENTRY(241),
928 I40E_PTT_UNUSED_ENTRY(242),
929 I40E_PTT_UNUSED_ENTRY(243),
930 I40E_PTT_UNUSED_ENTRY(244),
931 I40E_PTT_UNUSED_ENTRY(245),
932 I40E_PTT_UNUSED_ENTRY(246),
933 I40E_PTT_UNUSED_ENTRY(247),
934 I40E_PTT_UNUSED_ENTRY(248),
935 I40E_PTT_UNUSED_ENTRY(249),
937 I40E_PTT_UNUSED_ENTRY(250),
938 I40E_PTT_UNUSED_ENTRY(251),
939 I40E_PTT_UNUSED_ENTRY(252),
940 I40E_PTT_UNUSED_ENTRY(253),
941 I40E_PTT_UNUSED_ENTRY(254),
942 I40E_PTT_UNUSED_ENTRY(255)
947 * i40e_validate_mac_addr - Validate unicast MAC address
948 * @mac_addr: pointer to MAC address
950 * Tests a MAC address to ensure it is a valid Individual Address
952 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
954 enum i40e_status_code status = I40E_SUCCESS;
956 DEBUGFUNC("i40e_validate_mac_addr");
958 /* Broadcast addresses ARE multicast addresses
959 * Make sure it is not a multicast address
960 * Reject the zero address
962 if (I40E_IS_MULTICAST(mac_addr) ||
963 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
964 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
965 status = I40E_ERR_INVALID_MAC_ADDR;
972 * i40e_init_shared_code - Initialize the shared code
973 * @hw: pointer to hardware structure
975 * This assigns the MAC type and PHY code and inits the NVM.
976 * Does not touch the hardware. This function must be called prior to any
977 * other function in the shared code. The i40e_hw structure should be
978 * memset to 0 prior to calling this function. The following fields in
979 * hw structure should be filled in prior to calling this function:
980 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
981 * subsystem_vendor_id, and revision_id
983 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
985 enum i40e_status_code status = I40E_SUCCESS;
986 u32 port, ari, func_rid;
988 DEBUGFUNC("i40e_init_shared_code");
990 i40e_set_mac_type(hw);
992 switch (hw->mac.type) {
997 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1000 hw->phy.get_link_info = true;
1002 /* Determine port number and PF number*/
1003 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1004 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1005 hw->port = (u8)port;
1006 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1007 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1008 func_rid = rd32(hw, I40E_PF_FUNC_RID);
1010 hw->pf_id = (u8)(func_rid & 0xff);
1012 hw->pf_id = (u8)(func_rid & 0x7);
1014 if (hw->mac.type == I40E_MAC_X722)
1015 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE |
1016 I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK;
1018 status = i40e_init_nvm(hw);
1023 * i40e_aq_mac_address_read - Retrieve the MAC addresses
1024 * @hw: pointer to the hw struct
1025 * @flags: a return indicator of what addresses were added to the addr store
1026 * @addrs: the requestor's mac addr store
1027 * @cmd_details: pointer to command details structure or NULL
1029 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1031 struct i40e_aqc_mac_address_read_data *addrs,
1032 struct i40e_asq_cmd_details *cmd_details)
1034 struct i40e_aq_desc desc;
1035 struct i40e_aqc_mac_address_read *cmd_data =
1036 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1037 enum i40e_status_code status;
1039 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1040 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1042 status = i40e_asq_send_command(hw, &desc, addrs,
1043 sizeof(*addrs), cmd_details);
1044 *flags = LE16_TO_CPU(cmd_data->command_flags);
1050 * i40e_aq_mac_address_write - Change the MAC addresses
1051 * @hw: pointer to the hw struct
1052 * @flags: indicates which MAC to be written
1053 * @mac_addr: address to write
1054 * @cmd_details: pointer to command details structure or NULL
1056 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1057 u16 flags, u8 *mac_addr,
1058 struct i40e_asq_cmd_details *cmd_details)
1060 struct i40e_aq_desc desc;
1061 struct i40e_aqc_mac_address_write *cmd_data =
1062 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1063 enum i40e_status_code status;
1065 i40e_fill_default_direct_cmd_desc(&desc,
1066 i40e_aqc_opc_mac_address_write);
1067 cmd_data->command_flags = CPU_TO_LE16(flags);
1068 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1069 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1070 ((u32)mac_addr[3] << 16) |
1071 ((u32)mac_addr[4] << 8) |
1074 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1080 * i40e_get_mac_addr - get MAC address
1081 * @hw: pointer to the HW structure
1082 * @mac_addr: pointer to MAC address
1084 * Reads the adapter's MAC address from register
1086 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1088 struct i40e_aqc_mac_address_read_data addrs;
1089 enum i40e_status_code status;
1092 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1094 if (flags & I40E_AQC_LAN_ADDR_VALID)
1095 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1096 I40E_NONDMA_TO_NONDMA);
1102 * i40e_get_port_mac_addr - get Port MAC address
1103 * @hw: pointer to the HW structure
1104 * @mac_addr: pointer to Port MAC address
1106 * Reads the adapter's Port MAC address
1108 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1110 struct i40e_aqc_mac_address_read_data addrs;
1111 enum i40e_status_code status;
1114 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1118 if (flags & I40E_AQC_PORT_ADDR_VALID)
1119 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1120 I40E_NONDMA_TO_NONDMA);
1122 status = I40E_ERR_INVALID_MAC_ADDR;
1128 * i40e_pre_tx_queue_cfg - pre tx queue configure
1129 * @hw: pointer to the HW structure
1130 * @queue: target pf queue index
1131 * @enable: state change request
1133 * Handles hw requirement to indicate intention to enable
1134 * or disable target queue.
1136 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1138 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1142 if (abs_queue_idx >= 128) {
1143 reg_block = abs_queue_idx / 128;
1144 abs_queue_idx %= 128;
1147 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1148 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1149 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1152 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1154 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1156 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1160 * i40e_get_san_mac_addr - get SAN MAC address
1161 * @hw: pointer to the HW structure
1162 * @mac_addr: pointer to SAN MAC address
1164 * Reads the adapter's SAN MAC address from NVM
1166 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1169 struct i40e_aqc_mac_address_read_data addrs;
1170 enum i40e_status_code status;
1173 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1177 if (flags & I40E_AQC_SAN_ADDR_VALID)
1178 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac),
1179 I40E_NONDMA_TO_NONDMA);
1181 status = I40E_ERR_INVALID_MAC_ADDR;
1187 * i40e_read_pba_string - Reads part number string from EEPROM
1188 * @hw: pointer to hardware structure
1189 * @pba_num: stores the part number string from the EEPROM
1190 * @pba_num_size: part number string buffer length
1192 * Reads the part number string from the EEPROM.
1194 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1197 enum i40e_status_code status = I40E_SUCCESS;
1203 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1204 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1205 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1209 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1210 if (status != I40E_SUCCESS) {
1211 DEBUGOUT("Failed to read PBA Block pointer.\n");
1215 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1216 if (status != I40E_SUCCESS) {
1217 DEBUGOUT("Failed to read PBA Block size.\n");
1221 /* Subtract one to get PBA word count (PBA Size word is included in
1225 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1226 DEBUGOUT("Buffer to small for PBA data.\n");
1227 return I40E_ERR_PARAM;
1230 for (i = 0; i < pba_size; i++) {
1231 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1232 if (status != I40E_SUCCESS) {
1233 DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1237 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1238 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1240 pba_num[(pba_size * 2)] = '\0';
1246 * i40e_get_media_type - Gets media type
1247 * @hw: pointer to the hardware structure
1249 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1251 enum i40e_media_type media;
1253 switch (hw->phy.link_info.phy_type) {
1254 case I40E_PHY_TYPE_10GBASE_SR:
1255 case I40E_PHY_TYPE_10GBASE_LR:
1256 case I40E_PHY_TYPE_1000BASE_SX:
1257 case I40E_PHY_TYPE_1000BASE_LX:
1258 case I40E_PHY_TYPE_40GBASE_SR4:
1259 case I40E_PHY_TYPE_40GBASE_LR4:
1260 case I40E_PHY_TYPE_25GBASE_LR:
1261 case I40E_PHY_TYPE_25GBASE_SR:
1262 media = I40E_MEDIA_TYPE_FIBER;
1264 case I40E_PHY_TYPE_100BASE_TX:
1265 case I40E_PHY_TYPE_1000BASE_T:
1266 case I40E_PHY_TYPE_2_5GBASE_T:
1267 case I40E_PHY_TYPE_5GBASE_T:
1268 case I40E_PHY_TYPE_10GBASE_T:
1269 media = I40E_MEDIA_TYPE_BASET;
1271 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1272 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1273 case I40E_PHY_TYPE_10GBASE_CR1:
1274 case I40E_PHY_TYPE_40GBASE_CR4:
1275 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1276 case I40E_PHY_TYPE_40GBASE_AOC:
1277 case I40E_PHY_TYPE_10GBASE_AOC:
1278 case I40E_PHY_TYPE_25GBASE_CR:
1279 case I40E_PHY_TYPE_25GBASE_AOC:
1280 case I40E_PHY_TYPE_25GBASE_ACC:
1281 media = I40E_MEDIA_TYPE_DA;
1283 case I40E_PHY_TYPE_1000BASE_KX:
1284 case I40E_PHY_TYPE_10GBASE_KX4:
1285 case I40E_PHY_TYPE_10GBASE_KR:
1286 case I40E_PHY_TYPE_40GBASE_KR4:
1287 case I40E_PHY_TYPE_20GBASE_KR2:
1288 case I40E_PHY_TYPE_25GBASE_KR:
1289 media = I40E_MEDIA_TYPE_BACKPLANE;
1291 case I40E_PHY_TYPE_SGMII:
1292 case I40E_PHY_TYPE_XAUI:
1293 case I40E_PHY_TYPE_XFI:
1294 case I40E_PHY_TYPE_XLAUI:
1295 case I40E_PHY_TYPE_XLPPI:
1297 media = I40E_MEDIA_TYPE_UNKNOWN;
1305 * i40e_poll_globr - Poll for Global Reset completion
1306 * @hw: pointer to the hardware structure
1307 * @retry_limit: how many times to retry before failure
1309 STATIC enum i40e_status_code i40e_poll_globr(struct i40e_hw *hw,
1314 for (cnt = 0; cnt < retry_limit; cnt++) {
1315 reg = rd32(hw, I40E_GLGEN_RSTAT);
1316 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1317 return I40E_SUCCESS;
1318 i40e_msec_delay(100);
1321 DEBUGOUT("Global reset failed.\n");
1322 DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg);
1324 return I40E_ERR_RESET_FAILED;
1327 #define I40E_PF_RESET_WAIT_COUNT 200
1329 * i40e_pf_reset - Reset the PF
1330 * @hw: pointer to the hardware structure
1332 * Assuming someone else has triggered a global reset,
1333 * assure the global reset is complete and then reset the PF
1335 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1342 /* Poll for Global Reset steady state in case of recent GRST.
1343 * The grst delay value is in 100ms units, and we'll wait a
1344 * couple counts longer to be sure we don't just miss the end.
1346 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1347 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1348 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1350 grst_del = min(grst_del * 20, 160U);
1352 for (cnt = 0; cnt < grst_del; cnt++) {
1353 reg = rd32(hw, I40E_GLGEN_RSTAT);
1354 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1356 i40e_msec_delay(100);
1358 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1359 DEBUGOUT("Global reset polling failed to complete.\n");
1360 return I40E_ERR_RESET_FAILED;
1363 /* Now Wait for the FW to be ready */
1364 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1365 reg = rd32(hw, I40E_GLNVM_ULD);
1366 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1367 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1368 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1369 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1370 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1373 i40e_msec_delay(10);
1375 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1376 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1377 DEBUGOUT("wait for FW Reset complete timedout\n");
1378 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1379 return I40E_ERR_RESET_FAILED;
1382 /* If there was a Global Reset in progress when we got here,
1383 * we don't need to do the PF Reset
1388 reg = rd32(hw, I40E_PFGEN_CTRL);
1389 wr32(hw, I40E_PFGEN_CTRL,
1390 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1391 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1392 reg = rd32(hw, I40E_PFGEN_CTRL);
1393 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1395 reg2 = rd32(hw, I40E_GLGEN_RSTAT);
1396 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK)
1400 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1401 if (i40e_poll_globr(hw, grst_del) != I40E_SUCCESS)
1402 return I40E_ERR_RESET_FAILED;
1403 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1404 DEBUGOUT("PF reset polling failed to complete.\n");
1405 return I40E_ERR_RESET_FAILED;
1409 i40e_clear_pxe_mode(hw);
1412 return I40E_SUCCESS;
1416 * i40e_clear_hw - clear out any left over hw state
1417 * @hw: pointer to the hw struct
1419 * Clear queues and interrupts, typically called at init time,
1420 * but after the capabilities have been found so we know how many
1421 * queues and msix vectors have been allocated.
1423 void i40e_clear_hw(struct i40e_hw *hw)
1425 u32 num_queues, base_queue;
1433 /* get number of interrupts, queues, and vfs */
1434 val = rd32(hw, I40E_GLPCI_CNF2);
1435 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1436 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1437 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1438 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1440 val = rd32(hw, I40E_PFLAN_QALLOC);
1441 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1442 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1443 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1444 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1445 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1446 num_queues = (j - base_queue) + 1;
1450 val = rd32(hw, I40E_PF_VT_PFALLOC);
1451 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1452 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1453 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1454 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1455 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1456 num_vfs = (j - i) + 1;
1460 /* stop all the interrupts */
1461 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1462 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1463 for (i = 0; i < num_pf_int - 2; i++)
1464 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1466 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1467 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1468 wr32(hw, I40E_PFINT_LNKLST0, val);
1469 for (i = 0; i < num_pf_int - 2; i++)
1470 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1471 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1472 for (i = 0; i < num_vfs; i++)
1473 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1474 for (i = 0; i < num_vf_int - 2; i++)
1475 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1477 /* warn the HW of the coming Tx disables */
1478 for (i = 0; i < num_queues; i++) {
1479 u32 abs_queue_idx = base_queue + i;
1482 if (abs_queue_idx >= 128) {
1483 reg_block = abs_queue_idx / 128;
1484 abs_queue_idx %= 128;
1487 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1488 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1489 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1490 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1492 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1494 i40e_usec_delay(400);
1496 /* stop all the queues */
1497 for (i = 0; i < num_queues; i++) {
1498 wr32(hw, I40E_QINT_TQCTL(i), 0);
1499 wr32(hw, I40E_QTX_ENA(i), 0);
1500 wr32(hw, I40E_QINT_RQCTL(i), 0);
1501 wr32(hw, I40E_QRX_ENA(i), 0);
1504 /* short wait for all queue disables to settle */
1505 i40e_usec_delay(50);
1509 * i40e_clear_pxe_mode - clear pxe operations mode
1510 * @hw: pointer to the hw struct
1512 * Make sure all PXE mode settings are cleared, including things
1513 * like descriptor fetch/write-back mode.
1515 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1517 if (i40e_check_asq_alive(hw))
1518 i40e_aq_clear_pxe_mode(hw, NULL);
1522 * i40e_led_is_mine - helper to find matching led
1523 * @hw: pointer to the hw struct
1524 * @idx: index into GPIO registers
1526 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1528 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1533 if (!hw->func_caps.led[idx])
1536 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1537 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1538 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1540 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1541 * if it is not our port then ignore
1543 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1550 #define I40E_COMBINED_ACTIVITY 0xA
1551 #define I40E_FILTER_ACTIVITY 0xE
1552 #define I40E_LINK_ACTIVITY 0xC
1553 #define I40E_MAC_ACTIVITY 0xD
1554 #define I40E_LED0 22
1557 * i40e_led_get - return current on/off mode
1558 * @hw: pointer to the hw struct
1560 * The value returned is the 'mode' field as defined in the
1561 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1562 * values are variations of possible behaviors relating to
1563 * blink, link, and wire.
1565 u32 i40e_led_get(struct i40e_hw *hw)
1567 u32 current_mode = 0;
1571 /* as per the documentation GPIO 22-29 are the LED
1572 * GPIO pins named LED0..LED7
1574 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1575 u32 gpio_val = i40e_led_is_mine(hw, i);
1580 /* ignore gpio LED src mode entries related to the activity
1583 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1584 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1585 switch (current_mode) {
1586 case I40E_COMBINED_ACTIVITY:
1587 case I40E_FILTER_ACTIVITY:
1588 case I40E_MAC_ACTIVITY:
1589 case I40E_LINK_ACTIVITY:
1595 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1596 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1604 * i40e_led_set - set new on/off mode
1605 * @hw: pointer to the hw struct
1606 * @mode: 0=off, 0xf=on (else see manual for mode details)
1607 * @blink: true if the LED should blink when on, false if steady
1609 * if this function is used to turn on the blink it should
1610 * be used to disable the blink when restoring the original state.
1612 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1614 u32 current_mode = 0;
1617 if (mode & 0xfffffff0)
1618 DEBUGOUT1("invalid mode passed in %X\n", mode);
1620 /* as per the documentation GPIO 22-29 are the LED
1621 * GPIO pins named LED0..LED7
1623 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1624 u32 gpio_val = i40e_led_is_mine(hw, i);
1629 /* ignore gpio LED src mode entries related to the activity
1632 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1633 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1634 switch (current_mode) {
1635 case I40E_COMBINED_ACTIVITY:
1636 case I40E_FILTER_ACTIVITY:
1637 case I40E_MAC_ACTIVITY:
1638 case I40E_LINK_ACTIVITY:
1644 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1645 /* this & is a bit of paranoia, but serves as a range check */
1646 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1647 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1650 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1652 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1654 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1659 /* Admin command wrappers */
1662 * i40e_aq_get_phy_capabilities
1663 * @hw: pointer to the hw struct
1664 * @abilities: structure for PHY capabilities to be filled
1665 * @qualified_modules: report Qualified Modules
1666 * @report_init: report init capabilities (active are default)
1667 * @cmd_details: pointer to command details structure or NULL
1669 * Returns the various PHY abilities supported on the Port.
1671 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1672 bool qualified_modules, bool report_init,
1673 struct i40e_aq_get_phy_abilities_resp *abilities,
1674 struct i40e_asq_cmd_details *cmd_details)
1676 struct i40e_aq_desc desc;
1677 enum i40e_status_code status;
1678 u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0;
1679 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1682 return I40E_ERR_PARAM;
1685 i40e_fill_default_direct_cmd_desc(&desc,
1686 i40e_aqc_opc_get_phy_abilities);
1688 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1689 if (abilities_size > I40E_AQ_LARGE_BUF)
1690 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1692 if (qualified_modules)
1693 desc.params.external.param0 |=
1694 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1697 desc.params.external.param0 |=
1698 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1700 status = i40e_asq_send_command(hw, &desc, abilities,
1701 abilities_size, cmd_details);
1703 if (status != I40E_SUCCESS)
1706 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) {
1707 status = I40E_ERR_UNKNOWN_PHY;
1709 } else if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) {
1712 status = I40E_ERR_TIMEOUT;
1714 } while ((hw->aq.asq_last_status != I40E_AQ_RC_OK) &&
1715 (total_delay < max_delay));
1717 if (status != I40E_SUCCESS)
1721 if (hw->mac.type == I40E_MAC_XL710 &&
1722 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1723 hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
1724 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1726 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1727 hw->phy.phy_types |=
1728 ((u64)abilities->phy_type_ext << 32);
1736 * i40e_aq_set_phy_config
1737 * @hw: pointer to the hw struct
1738 * @config: structure with PHY configuration to be set
1739 * @cmd_details: pointer to command details structure or NULL
1741 * Set the various PHY configuration parameters
1742 * supported on the Port.One or more of the Set PHY config parameters may be
1743 * ignored in an MFP mode as the PF may not have the privilege to set some
1744 * of the PHY Config parameters. This status will be indicated by the
1747 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1748 struct i40e_aq_set_phy_config *config,
1749 struct i40e_asq_cmd_details *cmd_details)
1751 struct i40e_aq_desc desc;
1752 struct i40e_aq_set_phy_config *cmd =
1753 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1754 enum i40e_status_code status;
1757 return I40E_ERR_PARAM;
1759 i40e_fill_default_direct_cmd_desc(&desc,
1760 i40e_aqc_opc_set_phy_config);
1764 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1771 * @hw: pointer to the hw struct
1772 * @aq_failures: buffer to return AdminQ failure information
1773 * @atomic_restart: whether to enable atomic link restart
1775 * Set the requested flow control mode using set_phy_config.
1777 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1778 bool atomic_restart)
1780 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1781 struct i40e_aq_get_phy_abilities_resp abilities;
1782 struct i40e_aq_set_phy_config config;
1783 enum i40e_status_code status;
1784 u8 pause_mask = 0x0;
1790 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1791 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1793 case I40E_FC_RX_PAUSE:
1794 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1796 case I40E_FC_TX_PAUSE:
1797 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1803 /* Get the current phy config */
1804 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1807 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1811 memset(&config, 0, sizeof(config));
1812 /* clear the old pause settings */
1813 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1814 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1815 /* set the new abilities */
1816 config.abilities |= pause_mask;
1817 /* If the abilities have changed, then set the new config */
1818 if (config.abilities != abilities.abilities) {
1819 /* Auto restart link so settings take effect */
1821 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1822 /* Copy over all the old settings */
1823 config.phy_type = abilities.phy_type;
1824 config.phy_type_ext = abilities.phy_type_ext;
1825 config.link_speed = abilities.link_speed;
1826 config.eee_capability = abilities.eee_capability;
1827 config.eeer = abilities.eeer_val;
1828 config.low_power_ctrl = abilities.d3_lpan;
1829 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1830 I40E_AQ_PHY_FEC_CONFIG_MASK;
1831 status = i40e_aq_set_phy_config(hw, &config, NULL);
1834 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1836 /* Update the link info */
1837 status = i40e_update_link_info(hw);
1839 /* Wait a little bit (on 40G cards it sometimes takes a really
1840 * long time for link to come back from the atomic reset)
1843 i40e_msec_delay(1000);
1844 status = i40e_update_link_info(hw);
1847 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1853 * i40e_aq_set_mac_config
1854 * @hw: pointer to the hw struct
1855 * @max_frame_size: Maximum Frame Size to be supported by the port
1856 * @crc_en: Tell HW to append a CRC to outgoing frames
1857 * @pacing: Pacing configurations
1858 * @cmd_details: pointer to command details structure or NULL
1860 * Configure MAC settings for frame size, jumbo frame support and the
1861 * addition of a CRC by the hardware.
1863 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1865 bool crc_en, u16 pacing,
1866 struct i40e_asq_cmd_details *cmd_details)
1868 struct i40e_aq_desc desc;
1869 struct i40e_aq_set_mac_config *cmd =
1870 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1871 enum i40e_status_code status;
1873 if (max_frame_size == 0)
1874 return I40E_ERR_PARAM;
1876 i40e_fill_default_direct_cmd_desc(&desc,
1877 i40e_aqc_opc_set_mac_config);
1879 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1880 cmd->params = ((u8)pacing & 0x0F) << 3;
1882 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1884 #define I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD 0x7FFF
1885 cmd->fc_refresh_threshold =
1886 CPU_TO_LE16(I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD);
1888 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1894 * i40e_aq_clear_pxe_mode
1895 * @hw: pointer to the hw struct
1896 * @cmd_details: pointer to command details structure or NULL
1898 * Tell the firmware that the driver is taking over from PXE
1900 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1901 struct i40e_asq_cmd_details *cmd_details)
1903 enum i40e_status_code status;
1904 struct i40e_aq_desc desc;
1905 struct i40e_aqc_clear_pxe *cmd =
1906 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1908 i40e_fill_default_direct_cmd_desc(&desc,
1909 i40e_aqc_opc_clear_pxe_mode);
1913 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1915 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1921 * i40e_aq_set_link_restart_an
1922 * @hw: pointer to the hw struct
1923 * @enable_link: if true: enable link, if false: disable link
1924 * @cmd_details: pointer to command details structure or NULL
1926 * Sets up the link and restarts the Auto-Negotiation over the link.
1928 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1929 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1931 struct i40e_aq_desc desc;
1932 struct i40e_aqc_set_link_restart_an *cmd =
1933 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1934 enum i40e_status_code status;
1936 i40e_fill_default_direct_cmd_desc(&desc,
1937 i40e_aqc_opc_set_link_restart_an);
1939 cmd->command = I40E_AQ_PHY_RESTART_AN;
1941 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1943 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1945 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1951 * i40e_aq_get_link_info
1952 * @hw: pointer to the hw struct
1953 * @enable_lse: enable/disable LinkStatusEvent reporting
1954 * @link: pointer to link status structure - optional
1955 * @cmd_details: pointer to command details structure or NULL
1957 * Returns the link status of the adapter.
1959 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1960 bool enable_lse, struct i40e_link_status *link,
1961 struct i40e_asq_cmd_details *cmd_details)
1963 struct i40e_aq_desc desc;
1964 struct i40e_aqc_get_link_status *resp =
1965 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1966 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1967 enum i40e_status_code status;
1968 bool tx_pause, rx_pause;
1971 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1974 command_flags = I40E_AQ_LSE_ENABLE;
1976 command_flags = I40E_AQ_LSE_DISABLE;
1977 resp->command_flags = CPU_TO_LE16(command_flags);
1979 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1981 if (status != I40E_SUCCESS)
1982 goto aq_get_link_info_exit;
1984 /* save off old link status information */
1985 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1986 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1988 /* update link status */
1989 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1990 hw->phy.media_type = i40e_get_media_type(hw);
1991 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1992 hw_link_info->link_info = resp->link_info;
1993 hw_link_info->an_info = resp->an_info;
1994 hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
1995 I40E_AQ_CONFIG_FEC_RS_ENA);
1996 hw_link_info->ext_info = resp->ext_info;
1997 hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
1998 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1999 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
2001 /* update fc info */
2002 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
2003 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
2004 if (tx_pause & rx_pause)
2005 hw->fc.current_mode = I40E_FC_FULL;
2007 hw->fc.current_mode = I40E_FC_TX_PAUSE;
2009 hw->fc.current_mode = I40E_FC_RX_PAUSE;
2011 hw->fc.current_mode = I40E_FC_NONE;
2013 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
2014 hw_link_info->crc_enable = true;
2016 hw_link_info->crc_enable = false;
2018 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
2019 hw_link_info->lse_enable = true;
2021 hw_link_info->lse_enable = false;
2023 if ((hw->mac.type == I40E_MAC_XL710) &&
2024 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
2025 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
2026 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
2028 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
2029 hw->aq.api_min_ver >= 7) {
2032 i40e_memcpy(&tmp, resp->link_type, sizeof(tmp),
2033 I40E_NONDMA_TO_NONDMA);
2034 hw->phy.phy_types = LE32_TO_CPU(tmp);
2035 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
2038 /* save link status information */
2040 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
2041 I40E_NONDMA_TO_NONDMA);
2043 /* flag cleared so helper functions don't call AQ again */
2044 hw->phy.get_link_info = false;
2046 aq_get_link_info_exit:
2051 * i40e_aq_set_phy_int_mask
2052 * @hw: pointer to the hw struct
2053 * @mask: interrupt mask to be set
2054 * @cmd_details: pointer to command details structure or NULL
2056 * Set link interrupt mask.
2058 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2060 struct i40e_asq_cmd_details *cmd_details)
2062 struct i40e_aq_desc desc;
2063 struct i40e_aqc_set_phy_int_mask *cmd =
2064 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2065 enum i40e_status_code status;
2067 i40e_fill_default_direct_cmd_desc(&desc,
2068 i40e_aqc_opc_set_phy_int_mask);
2070 cmd->event_mask = CPU_TO_LE16(mask);
2072 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2078 * i40e_aq_get_local_advt_reg
2079 * @hw: pointer to the hw struct
2080 * @advt_reg: local AN advertisement register value
2081 * @cmd_details: pointer to command details structure or NULL
2083 * Get the Local AN advertisement register value.
2085 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2087 struct i40e_asq_cmd_details *cmd_details)
2089 struct i40e_aq_desc desc;
2090 struct i40e_aqc_an_advt_reg *resp =
2091 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2092 enum i40e_status_code status;
2094 i40e_fill_default_direct_cmd_desc(&desc,
2095 i40e_aqc_opc_get_local_advt_reg);
2097 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2099 if (status != I40E_SUCCESS)
2100 goto aq_get_local_advt_reg_exit;
2102 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2103 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2105 aq_get_local_advt_reg_exit:
2110 * i40e_aq_set_local_advt_reg
2111 * @hw: pointer to the hw struct
2112 * @advt_reg: local AN advertisement register value
2113 * @cmd_details: pointer to command details structure or NULL
2115 * Get the Local AN advertisement register value.
2117 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2119 struct i40e_asq_cmd_details *cmd_details)
2121 struct i40e_aq_desc desc;
2122 struct i40e_aqc_an_advt_reg *cmd =
2123 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2124 enum i40e_status_code status;
2126 i40e_fill_default_direct_cmd_desc(&desc,
2127 i40e_aqc_opc_get_local_advt_reg);
2129 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2130 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2132 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2138 * i40e_aq_get_partner_advt
2139 * @hw: pointer to the hw struct
2140 * @advt_reg: AN partner advertisement register value
2141 * @cmd_details: pointer to command details structure or NULL
2143 * Get the link partner AN advertisement register value.
2145 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2147 struct i40e_asq_cmd_details *cmd_details)
2149 struct i40e_aq_desc desc;
2150 struct i40e_aqc_an_advt_reg *resp =
2151 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2152 enum i40e_status_code status;
2154 i40e_fill_default_direct_cmd_desc(&desc,
2155 i40e_aqc_opc_get_partner_advt);
2157 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2159 if (status != I40E_SUCCESS)
2160 goto aq_get_partner_advt_exit;
2162 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2163 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2165 aq_get_partner_advt_exit:
2170 * i40e_aq_set_lb_modes
2171 * @hw: pointer to the hw struct
2172 * @lb_modes: loopback mode to be set
2173 * @cmd_details: pointer to command details structure or NULL
2175 * Sets loopback modes.
2177 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2179 struct i40e_asq_cmd_details *cmd_details)
2181 struct i40e_aq_desc desc;
2182 struct i40e_aqc_set_lb_mode *cmd =
2183 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2184 enum i40e_status_code status;
2186 i40e_fill_default_direct_cmd_desc(&desc,
2187 i40e_aqc_opc_set_lb_modes);
2189 cmd->lb_mode = CPU_TO_LE16(lb_modes);
2191 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2197 * i40e_aq_set_phy_debug
2198 * @hw: pointer to the hw struct
2199 * @cmd_flags: debug command flags
2200 * @cmd_details: pointer to command details structure or NULL
2202 * Reset the external PHY.
2204 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2205 struct i40e_asq_cmd_details *cmd_details)
2207 struct i40e_aq_desc desc;
2208 struct i40e_aqc_set_phy_debug *cmd =
2209 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2210 enum i40e_status_code status;
2212 i40e_fill_default_direct_cmd_desc(&desc,
2213 i40e_aqc_opc_set_phy_debug);
2215 cmd->command_flags = cmd_flags;
2217 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2224 * @hw: pointer to the hw struct
2225 * @vsi_ctx: pointer to a vsi context struct
2226 * @cmd_details: pointer to command details structure or NULL
2228 * Add a VSI context to the hardware.
2230 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2231 struct i40e_vsi_context *vsi_ctx,
2232 struct i40e_asq_cmd_details *cmd_details)
2234 struct i40e_aq_desc desc;
2235 struct i40e_aqc_add_get_update_vsi *cmd =
2236 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2237 struct i40e_aqc_add_get_update_vsi_completion *resp =
2238 (struct i40e_aqc_add_get_update_vsi_completion *)
2240 enum i40e_status_code status;
2242 i40e_fill_default_direct_cmd_desc(&desc,
2243 i40e_aqc_opc_add_vsi);
2245 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2246 cmd->connection_type = vsi_ctx->connection_type;
2247 cmd->vf_id = vsi_ctx->vf_num;
2248 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2250 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2252 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2253 sizeof(vsi_ctx->info), cmd_details);
2255 if (status != I40E_SUCCESS)
2256 goto aq_add_vsi_exit;
2258 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2259 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2260 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2261 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2268 * i40e_aq_set_default_vsi
2269 * @hw: pointer to the hw struct
2271 * @cmd_details: pointer to command details structure or NULL
2273 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2275 struct i40e_asq_cmd_details *cmd_details)
2277 struct i40e_aq_desc desc;
2278 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2279 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2281 enum i40e_status_code status;
2283 i40e_fill_default_direct_cmd_desc(&desc,
2284 i40e_aqc_opc_set_vsi_promiscuous_modes);
2286 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2287 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2288 cmd->seid = CPU_TO_LE16(seid);
2290 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2296 * i40e_aq_clear_default_vsi
2297 * @hw: pointer to the hw struct
2299 * @cmd_details: pointer to command details structure or NULL
2301 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2303 struct i40e_asq_cmd_details *cmd_details)
2305 struct i40e_aq_desc desc;
2306 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2307 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2309 enum i40e_status_code status;
2311 i40e_fill_default_direct_cmd_desc(&desc,
2312 i40e_aqc_opc_set_vsi_promiscuous_modes);
2314 cmd->promiscuous_flags = CPU_TO_LE16(0);
2315 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2316 cmd->seid = CPU_TO_LE16(seid);
2318 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2324 * i40e_aq_set_vsi_unicast_promiscuous
2325 * @hw: pointer to the hw struct
2327 * @set: set unicast promiscuous enable/disable
2328 * @cmd_details: pointer to command details structure or NULL
2329 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2331 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2333 struct i40e_asq_cmd_details *cmd_details,
2334 bool rx_only_promisc)
2336 struct i40e_aq_desc desc;
2337 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2338 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2339 enum i40e_status_code status;
2342 i40e_fill_default_direct_cmd_desc(&desc,
2343 i40e_aqc_opc_set_vsi_promiscuous_modes);
2346 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2347 if (rx_only_promisc &&
2348 (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2349 (hw->aq.api_maj_ver > 1)))
2350 flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2353 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2355 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2356 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2357 (hw->aq.api_maj_ver > 1))
2358 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2360 cmd->seid = CPU_TO_LE16(seid);
2361 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2367 * i40e_aq_set_vsi_multicast_promiscuous
2368 * @hw: pointer to the hw struct
2370 * @set: set multicast promiscuous enable/disable
2371 * @cmd_details: pointer to command details structure or NULL
2373 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2374 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2376 struct i40e_aq_desc desc;
2377 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2378 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2379 enum i40e_status_code status;
2382 i40e_fill_default_direct_cmd_desc(&desc,
2383 i40e_aqc_opc_set_vsi_promiscuous_modes);
2386 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2388 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2390 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2392 cmd->seid = CPU_TO_LE16(seid);
2393 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2399 * i40e_aq_set_vsi_full_promiscuous
2400 * @hw: pointer to the hw struct
2402 * @set: set promiscuous enable/disable
2403 * @cmd_details: pointer to command details structure or NULL
2405 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw,
2407 struct i40e_asq_cmd_details *cmd_details)
2409 struct i40e_aq_desc desc;
2410 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2411 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2412 enum i40e_status_code status;
2415 i40e_fill_default_direct_cmd_desc(&desc,
2416 i40e_aqc_opc_set_vsi_promiscuous_modes);
2419 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST |
2420 I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2421 I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2423 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2425 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST |
2426 I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2427 I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2429 cmd->seid = CPU_TO_LE16(seid);
2430 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2436 * i40e_aq_set_vsi_mc_promisc_on_vlan
2437 * @hw: pointer to the hw struct
2439 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2440 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2441 * @cmd_details: pointer to command details structure or NULL
2443 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2444 u16 seid, bool enable, u16 vid,
2445 struct i40e_asq_cmd_details *cmd_details)
2447 struct i40e_aq_desc desc;
2448 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2449 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2450 enum i40e_status_code status;
2453 i40e_fill_default_direct_cmd_desc(&desc,
2454 i40e_aqc_opc_set_vsi_promiscuous_modes);
2457 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2459 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2460 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2461 cmd->seid = CPU_TO_LE16(seid);
2462 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2464 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2470 * i40e_aq_set_vsi_uc_promisc_on_vlan
2471 * @hw: pointer to the hw struct
2473 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2474 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2475 * @cmd_details: pointer to command details structure or NULL
2477 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2478 u16 seid, bool enable, u16 vid,
2479 struct i40e_asq_cmd_details *cmd_details)
2481 struct i40e_aq_desc desc;
2482 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2483 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2484 enum i40e_status_code status;
2487 i40e_fill_default_direct_cmd_desc(&desc,
2488 i40e_aqc_opc_set_vsi_promiscuous_modes);
2491 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2493 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2494 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2495 cmd->seid = CPU_TO_LE16(seid);
2496 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2498 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2504 * i40e_aq_set_vsi_bc_promisc_on_vlan
2505 * @hw: pointer to the hw struct
2507 * @enable: set broadcast promiscuous enable/disable for a given VLAN
2508 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2509 * @cmd_details: pointer to command details structure or NULL
2511 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2512 u16 seid, bool enable, u16 vid,
2513 struct i40e_asq_cmd_details *cmd_details)
2515 struct i40e_aq_desc desc;
2516 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2517 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2518 enum i40e_status_code status;
2521 i40e_fill_default_direct_cmd_desc(&desc,
2522 i40e_aqc_opc_set_vsi_promiscuous_modes);
2525 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2527 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2528 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2529 cmd->seid = CPU_TO_LE16(seid);
2530 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2532 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2538 * i40e_aq_set_vsi_broadcast
2539 * @hw: pointer to the hw struct
2541 * @set_filter: true to set filter, false to clear filter
2542 * @cmd_details: pointer to command details structure or NULL
2544 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2546 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2547 u16 seid, bool set_filter,
2548 struct i40e_asq_cmd_details *cmd_details)
2550 struct i40e_aq_desc desc;
2551 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2552 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2553 enum i40e_status_code status;
2555 i40e_fill_default_direct_cmd_desc(&desc,
2556 i40e_aqc_opc_set_vsi_promiscuous_modes);
2559 cmd->promiscuous_flags
2560 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2562 cmd->promiscuous_flags
2563 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2565 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2566 cmd->seid = CPU_TO_LE16(seid);
2567 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2573 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2574 * @hw: pointer to the hw struct
2576 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2577 * @cmd_details: pointer to command details structure or NULL
2579 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2580 u16 seid, bool enable,
2581 struct i40e_asq_cmd_details *cmd_details)
2583 struct i40e_aq_desc desc;
2584 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2585 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2586 enum i40e_status_code status;
2589 i40e_fill_default_direct_cmd_desc(&desc,
2590 i40e_aqc_opc_set_vsi_promiscuous_modes);
2592 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2594 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2595 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2596 cmd->seid = CPU_TO_LE16(seid);
2598 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2604 * i40e_get_vsi_params - get VSI configuration info
2605 * @hw: pointer to the hw struct
2606 * @vsi_ctx: pointer to a vsi context struct
2607 * @cmd_details: pointer to command details structure or NULL
2609 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2610 struct i40e_vsi_context *vsi_ctx,
2611 struct i40e_asq_cmd_details *cmd_details)
2613 struct i40e_aq_desc desc;
2614 struct i40e_aqc_add_get_update_vsi *cmd =
2615 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2616 struct i40e_aqc_add_get_update_vsi_completion *resp =
2617 (struct i40e_aqc_add_get_update_vsi_completion *)
2619 enum i40e_status_code status;
2621 UNREFERENCED_1PARAMETER(cmd_details);
2622 i40e_fill_default_direct_cmd_desc(&desc,
2623 i40e_aqc_opc_get_vsi_parameters);
2625 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2627 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2629 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2630 sizeof(vsi_ctx->info), NULL);
2632 if (status != I40E_SUCCESS)
2633 goto aq_get_vsi_params_exit;
2635 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2636 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2637 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2638 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2640 aq_get_vsi_params_exit:
2645 * i40e_aq_update_vsi_params
2646 * @hw: pointer to the hw struct
2647 * @vsi_ctx: pointer to a vsi context struct
2648 * @cmd_details: pointer to command details structure or NULL
2650 * Update a VSI context.
2652 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2653 struct i40e_vsi_context *vsi_ctx,
2654 struct i40e_asq_cmd_details *cmd_details)
2656 struct i40e_aq_desc desc;
2657 struct i40e_aqc_add_get_update_vsi *cmd =
2658 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2659 struct i40e_aqc_add_get_update_vsi_completion *resp =
2660 (struct i40e_aqc_add_get_update_vsi_completion *)
2662 enum i40e_status_code status;
2664 i40e_fill_default_direct_cmd_desc(&desc,
2665 i40e_aqc_opc_update_vsi_parameters);
2666 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2668 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2670 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2671 sizeof(vsi_ctx->info), cmd_details);
2673 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2674 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2680 * i40e_aq_get_switch_config
2681 * @hw: pointer to the hardware structure
2682 * @buf: pointer to the result buffer
2683 * @buf_size: length of input buffer
2684 * @start_seid: seid to start for the report, 0 == beginning
2685 * @cmd_details: pointer to command details structure or NULL
2687 * Fill the buf with switch configuration returned from AdminQ command
2689 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2690 struct i40e_aqc_get_switch_config_resp *buf,
2691 u16 buf_size, u16 *start_seid,
2692 struct i40e_asq_cmd_details *cmd_details)
2694 struct i40e_aq_desc desc;
2695 struct i40e_aqc_switch_seid *scfg =
2696 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2697 enum i40e_status_code status;
2699 i40e_fill_default_direct_cmd_desc(&desc,
2700 i40e_aqc_opc_get_switch_config);
2701 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2702 if (buf_size > I40E_AQ_LARGE_BUF)
2703 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2704 scfg->seid = CPU_TO_LE16(*start_seid);
2706 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2707 *start_seid = LE16_TO_CPU(scfg->seid);
2713 * i40e_aq_set_switch_config
2714 * @hw: pointer to the hardware structure
2715 * @flags: bit flag values to set
2716 * @mode: cloud filter mode
2717 * @valid_flags: which bit flags to set
2718 * @cmd_details: pointer to command details structure or NULL
2720 * Set switch configuration bits
2722 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2723 u16 flags, u16 valid_flags, u8 mode,
2724 struct i40e_asq_cmd_details *cmd_details)
2726 struct i40e_aq_desc desc;
2727 struct i40e_aqc_set_switch_config *scfg =
2728 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2729 enum i40e_status_code status;
2731 i40e_fill_default_direct_cmd_desc(&desc,
2732 i40e_aqc_opc_set_switch_config);
2733 scfg->flags = CPU_TO_LE16(flags);
2734 scfg->valid_flags = CPU_TO_LE16(valid_flags);
2736 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
2737 scfg->switch_tag = CPU_TO_LE16(hw->switch_tag);
2738 scfg->first_tag = CPU_TO_LE16(hw->first_tag);
2739 scfg->second_tag = CPU_TO_LE16(hw->second_tag);
2741 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2747 * i40e_aq_get_firmware_version
2748 * @hw: pointer to the hw struct
2749 * @fw_major_version: firmware major version
2750 * @fw_minor_version: firmware minor version
2751 * @fw_build: firmware build number
2752 * @api_major_version: major queue version
2753 * @api_minor_version: minor queue version
2754 * @cmd_details: pointer to command details structure or NULL
2756 * Get the firmware version from the admin queue commands
2758 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2759 u16 *fw_major_version, u16 *fw_minor_version,
2761 u16 *api_major_version, u16 *api_minor_version,
2762 struct i40e_asq_cmd_details *cmd_details)
2764 struct i40e_aq_desc desc;
2765 struct i40e_aqc_get_version *resp =
2766 (struct i40e_aqc_get_version *)&desc.params.raw;
2767 enum i40e_status_code status;
2769 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2771 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2773 if (status == I40E_SUCCESS) {
2774 if (fw_major_version != NULL)
2775 *fw_major_version = LE16_TO_CPU(resp->fw_major);
2776 if (fw_minor_version != NULL)
2777 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2778 if (fw_build != NULL)
2779 *fw_build = LE32_TO_CPU(resp->fw_build);
2780 if (api_major_version != NULL)
2781 *api_major_version = LE16_TO_CPU(resp->api_major);
2782 if (api_minor_version != NULL)
2783 *api_minor_version = LE16_TO_CPU(resp->api_minor);
2785 /* A workaround to fix the API version in SW */
2786 if (api_major_version && api_minor_version &&
2787 fw_major_version && fw_minor_version &&
2788 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2789 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2790 (*fw_major_version > 4)))
2791 *api_minor_version = 2;
2798 * i40e_aq_send_driver_version
2799 * @hw: pointer to the hw struct
2800 * @dv: driver's major, minor version
2801 * @cmd_details: pointer to command details structure or NULL
2803 * Send the driver version to the firmware
2805 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2806 struct i40e_driver_version *dv,
2807 struct i40e_asq_cmd_details *cmd_details)
2809 struct i40e_aq_desc desc;
2810 struct i40e_aqc_driver_version *cmd =
2811 (struct i40e_aqc_driver_version *)&desc.params.raw;
2812 enum i40e_status_code status;
2816 return I40E_ERR_PARAM;
2818 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2820 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2821 cmd->driver_major_ver = dv->major_version;
2822 cmd->driver_minor_ver = dv->minor_version;
2823 cmd->driver_build_ver = dv->build_version;
2824 cmd->driver_subbuild_ver = dv->subbuild_version;
2827 while (len < sizeof(dv->driver_string) &&
2828 (dv->driver_string[len] < 0x80) &&
2829 dv->driver_string[len])
2831 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2838 * i40e_get_link_status - get status of the HW network link
2839 * @hw: pointer to the hw struct
2840 * @link_up: pointer to bool (true/false = linkup/linkdown)
2842 * Variable link_up true if link is up, false if link is down.
2843 * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2845 * Side effect: LinkStatusEvent reporting becomes enabled
2847 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2849 enum i40e_status_code status = I40E_SUCCESS;
2851 if (hw->phy.get_link_info) {
2852 status = i40e_update_link_info(hw);
2854 if (status != I40E_SUCCESS)
2855 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2859 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2865 * i40e_updatelink_status - update status of the HW network link
2866 * @hw: pointer to the hw struct
2868 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2870 struct i40e_aq_get_phy_abilities_resp abilities;
2871 enum i40e_status_code status = I40E_SUCCESS;
2873 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2877 /* extra checking needed to ensure link info to user is timely */
2878 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2879 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2880 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2881 status = i40e_aq_get_phy_capabilities(hw, false, false,
2886 hw->phy.link_info.req_fec_info =
2887 abilities.fec_cfg_curr_mod_ext_info &
2888 (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS);
2890 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2891 sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2898 * i40e_get_link_speed
2899 * @hw: pointer to the hw struct
2901 * Returns the link speed of the adapter.
2903 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2905 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2906 enum i40e_status_code status = I40E_SUCCESS;
2908 if (hw->phy.get_link_info) {
2909 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2911 if (status != I40E_SUCCESS)
2912 goto i40e_link_speed_exit;
2915 speed = hw->phy.link_info.link_speed;
2917 i40e_link_speed_exit:
2922 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2923 * @hw: pointer to the hw struct
2924 * @uplink_seid: the MAC or other gizmo SEID
2925 * @downlink_seid: the VSI SEID
2926 * @enabled_tc: bitmap of TCs to be enabled
2927 * @default_port: true for default port VSI, false for control port
2928 * @veb_seid: pointer to where to put the resulting VEB SEID
2929 * @enable_stats: true to turn on VEB stats
2930 * @cmd_details: pointer to command details structure or NULL
2932 * This asks the FW to add a VEB between the uplink and downlink
2933 * elements. If the uplink SEID is 0, this will be a floating VEB.
2935 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2936 u16 downlink_seid, u8 enabled_tc,
2937 bool default_port, u16 *veb_seid,
2939 struct i40e_asq_cmd_details *cmd_details)
2941 struct i40e_aq_desc desc;
2942 struct i40e_aqc_add_veb *cmd =
2943 (struct i40e_aqc_add_veb *)&desc.params.raw;
2944 struct i40e_aqc_add_veb_completion *resp =
2945 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2946 enum i40e_status_code status;
2949 /* SEIDs need to either both be set or both be 0 for floating VEB */
2950 if (!!uplink_seid != !!downlink_seid)
2951 return I40E_ERR_PARAM;
2953 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2955 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2956 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2957 cmd->enable_tcs = enabled_tc;
2959 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2961 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2963 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2965 /* reverse logic here: set the bitflag to disable the stats */
2967 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2969 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2971 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2973 if (!status && veb_seid)
2974 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2980 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2981 * @hw: pointer to the hw struct
2982 * @veb_seid: the SEID of the VEB to query
2983 * @switch_id: the uplink switch id
2984 * @floating: set to true if the VEB is floating
2985 * @statistic_index: index of the stats counter block for this VEB
2986 * @vebs_used: number of VEB's used by function
2987 * @vebs_free: total VEB's not reserved by any function
2988 * @cmd_details: pointer to command details structure or NULL
2990 * This retrieves the parameters for a particular VEB, specified by
2991 * uplink_seid, and returns them to the caller.
2993 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2994 u16 veb_seid, u16 *switch_id,
2995 bool *floating, u16 *statistic_index,
2996 u16 *vebs_used, u16 *vebs_free,
2997 struct i40e_asq_cmd_details *cmd_details)
2999 struct i40e_aq_desc desc;
3000 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
3001 (struct i40e_aqc_get_veb_parameters_completion *)
3003 enum i40e_status_code status;
3006 return I40E_ERR_PARAM;
3008 i40e_fill_default_direct_cmd_desc(&desc,
3009 i40e_aqc_opc_get_veb_parameters);
3010 cmd_resp->seid = CPU_TO_LE16(veb_seid);
3012 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3017 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
3018 if (statistic_index)
3019 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
3021 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
3023 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
3025 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
3027 if (flags & I40E_AQC_ADD_VEB_FLOATING)
3038 * i40e_aq_add_macvlan
3039 * @hw: pointer to the hw struct
3040 * @seid: VSI for the mac address
3041 * @mv_list: list of macvlans to be added
3042 * @count: length of the list
3043 * @cmd_details: pointer to command details structure or NULL
3045 * Add MAC/VLAN addresses to the HW filtering
3047 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
3048 struct i40e_aqc_add_macvlan_element_data *mv_list,
3049 u16 count, struct i40e_asq_cmd_details *cmd_details)
3051 struct i40e_aq_desc desc;
3052 struct i40e_aqc_macvlan *cmd =
3053 (struct i40e_aqc_macvlan *)&desc.params.raw;
3054 enum i40e_status_code status;
3058 if (count == 0 || !mv_list || !hw)
3059 return I40E_ERR_PARAM;
3061 buf_size = count * sizeof(*mv_list);
3063 /* prep the rest of the request */
3064 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
3065 cmd->num_addresses = CPU_TO_LE16(count);
3066 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3070 for (i = 0; i < count; i++)
3071 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
3073 CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
3075 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3076 if (buf_size > I40E_AQ_LARGE_BUF)
3077 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3079 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3086 * i40e_aq_remove_macvlan
3087 * @hw: pointer to the hw struct
3088 * @seid: VSI for the mac address
3089 * @mv_list: list of macvlans to be removed
3090 * @count: length of the list
3091 * @cmd_details: pointer to command details structure or NULL
3093 * Remove MAC/VLAN addresses from the HW filtering
3095 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
3096 struct i40e_aqc_remove_macvlan_element_data *mv_list,
3097 u16 count, struct i40e_asq_cmd_details *cmd_details)
3099 struct i40e_aq_desc desc;
3100 struct i40e_aqc_macvlan *cmd =
3101 (struct i40e_aqc_macvlan *)&desc.params.raw;
3102 enum i40e_status_code status;
3105 if (count == 0 || !mv_list || !hw)
3106 return I40E_ERR_PARAM;
3108 buf_size = count * sizeof(*mv_list);
3110 /* prep the rest of the request */
3111 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
3112 cmd->num_addresses = CPU_TO_LE16(count);
3113 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3117 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3118 if (buf_size > I40E_AQ_LARGE_BUF)
3119 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3121 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3128 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3129 * @hw: pointer to the hw struct
3130 * @opcode: AQ opcode for add or delete mirror rule
3131 * @sw_seid: Switch SEID (to which rule refers)
3132 * @rule_type: Rule Type (ingress/egress/VLAN)
3133 * @id: Destination VSI SEID or Rule ID
3134 * @count: length of the list
3135 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3136 * @cmd_details: pointer to command details structure or NULL
3137 * @rule_id: Rule ID returned from FW
3138 * @rules_used: Number of rules used in internal switch
3139 * @rules_free: Number of rules free in internal switch
3141 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3142 * VEBs/VEPA elements only
3144 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3145 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3146 u16 count, __le16 *mr_list,
3147 struct i40e_asq_cmd_details *cmd_details,
3148 u16 *rule_id, u16 *rules_used, u16 *rules_free)
3150 struct i40e_aq_desc desc;
3151 struct i40e_aqc_add_delete_mirror_rule *cmd =
3152 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3153 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3154 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3155 enum i40e_status_code status;
3158 buf_size = count * sizeof(*mr_list);
3160 /* prep the rest of the request */
3161 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3162 cmd->seid = CPU_TO_LE16(sw_seid);
3163 cmd->rule_type = CPU_TO_LE16(rule_type &
3164 I40E_AQC_MIRROR_RULE_TYPE_MASK);
3165 cmd->num_entries = CPU_TO_LE16(count);
3166 /* Dest VSI for add, rule_id for delete */
3167 cmd->destination = CPU_TO_LE16(id);
3169 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3171 if (buf_size > I40E_AQ_LARGE_BUF)
3172 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3175 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3177 if (status == I40E_SUCCESS ||
3178 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3180 *rule_id = LE16_TO_CPU(resp->rule_id);
3182 *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3184 *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3190 * i40e_aq_add_mirrorrule - add a mirror rule
3191 * @hw: pointer to the hw struct
3192 * @sw_seid: Switch SEID (to which rule refers)
3193 * @rule_type: Rule Type (ingress/egress/VLAN)
3194 * @dest_vsi: SEID of VSI to which packets will be mirrored
3195 * @count: length of the list
3196 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3197 * @cmd_details: pointer to command details structure or NULL
3198 * @rule_id: Rule ID returned from FW
3199 * @rules_used: Number of rules used in internal switch
3200 * @rules_free: Number of rules free in internal switch
3202 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3204 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3205 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3206 struct i40e_asq_cmd_details *cmd_details,
3207 u16 *rule_id, u16 *rules_used, u16 *rules_free)
3209 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3210 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3211 if (count == 0 || !mr_list)
3212 return I40E_ERR_PARAM;
3215 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3216 rule_type, dest_vsi, count, mr_list,
3217 cmd_details, rule_id, rules_used, rules_free);
3221 * i40e_aq_delete_mirrorrule - delete a mirror rule
3222 * @hw: pointer to the hw struct
3223 * @sw_seid: Switch SEID (to which rule refers)
3224 * @rule_type: Rule Type (ingress/egress/VLAN)
3225 * @count: length of the list
3226 * @rule_id: Rule ID that is returned in the receive desc as part of
3228 * @mr_list: list of mirrored VLAN IDs to be removed
3229 * @cmd_details: pointer to command details structure or NULL
3230 * @rules_used: Number of rules used in internal switch
3231 * @rules_free: Number of rules free in internal switch
3233 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3235 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3236 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3237 struct i40e_asq_cmd_details *cmd_details,
3238 u16 *rules_used, u16 *rules_free)
3240 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3241 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3242 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3243 * mirroring. For other rule_type, count and rule_type should
3246 if (count == 0 || !mr_list)
3247 return I40E_ERR_PARAM;
3250 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3251 rule_type, rule_id, count, mr_list,
3252 cmd_details, NULL, rules_used, rules_free);
3256 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3257 * @hw: pointer to the hw struct
3258 * @seid: VSI for the vlan filters
3259 * @v_list: list of vlan filters to be added
3260 * @count: length of the list
3261 * @cmd_details: pointer to command details structure or NULL
3263 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3264 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3265 u8 count, struct i40e_asq_cmd_details *cmd_details)
3267 struct i40e_aq_desc desc;
3268 struct i40e_aqc_macvlan *cmd =
3269 (struct i40e_aqc_macvlan *)&desc.params.raw;
3270 enum i40e_status_code status;
3273 if (count == 0 || !v_list || !hw)
3274 return I40E_ERR_PARAM;
3276 buf_size = count * sizeof(*v_list);
3278 /* prep the rest of the request */
3279 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3280 cmd->num_addresses = CPU_TO_LE16(count);
3281 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3285 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3286 if (buf_size > I40E_AQ_LARGE_BUF)
3287 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3289 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3296 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3297 * @hw: pointer to the hw struct
3298 * @seid: VSI for the vlan filters
3299 * @v_list: list of macvlans to be removed
3300 * @count: length of the list
3301 * @cmd_details: pointer to command details structure or NULL
3303 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3304 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3305 u8 count, struct i40e_asq_cmd_details *cmd_details)
3307 struct i40e_aq_desc desc;
3308 struct i40e_aqc_macvlan *cmd =
3309 (struct i40e_aqc_macvlan *)&desc.params.raw;
3310 enum i40e_status_code status;
3313 if (count == 0 || !v_list || !hw)
3314 return I40E_ERR_PARAM;
3316 buf_size = count * sizeof(*v_list);
3318 /* prep the rest of the request */
3319 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3320 cmd->num_addresses = CPU_TO_LE16(count);
3321 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3325 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3326 if (buf_size > I40E_AQ_LARGE_BUF)
3327 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3329 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3336 * i40e_aq_send_msg_to_vf
3337 * @hw: pointer to the hardware structure
3338 * @vfid: vf id to send msg
3339 * @v_opcode: opcodes for VF-PF communication
3340 * @v_retval: return error code
3341 * @msg: pointer to the msg buffer
3342 * @msglen: msg length
3343 * @cmd_details: pointer to command details
3347 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3348 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3349 struct i40e_asq_cmd_details *cmd_details)
3351 struct i40e_aq_desc desc;
3352 struct i40e_aqc_pf_vf_message *cmd =
3353 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3354 enum i40e_status_code status;
3356 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3357 cmd->id = CPU_TO_LE32(vfid);
3358 desc.cookie_high = CPU_TO_LE32(v_opcode);
3359 desc.cookie_low = CPU_TO_LE32(v_retval);
3360 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3362 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3364 if (msglen > I40E_AQ_LARGE_BUF)
3365 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3366 desc.datalen = CPU_TO_LE16(msglen);
3368 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3374 * i40e_aq_debug_read_register
3375 * @hw: pointer to the hw struct
3376 * @reg_addr: register address
3377 * @reg_val: register value
3378 * @cmd_details: pointer to command details structure or NULL
3380 * Read the register using the admin queue commands
3382 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3383 u32 reg_addr, u64 *reg_val,
3384 struct i40e_asq_cmd_details *cmd_details)
3386 struct i40e_aq_desc desc;
3387 struct i40e_aqc_debug_reg_read_write *cmd_resp =
3388 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3389 enum i40e_status_code status;
3391 if (reg_val == NULL)
3392 return I40E_ERR_PARAM;
3394 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3396 cmd_resp->address = CPU_TO_LE32(reg_addr);
3398 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3400 if (status == I40E_SUCCESS) {
3401 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3402 (u64)LE32_TO_CPU(cmd_resp->value_low);
3409 * i40e_aq_debug_write_register
3410 * @hw: pointer to the hw struct
3411 * @reg_addr: register address
3412 * @reg_val: register value
3413 * @cmd_details: pointer to command details structure or NULL
3415 * Write to a register using the admin queue commands
3417 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3418 u32 reg_addr, u64 reg_val,
3419 struct i40e_asq_cmd_details *cmd_details)
3421 struct i40e_aq_desc desc;
3422 struct i40e_aqc_debug_reg_read_write *cmd =
3423 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3424 enum i40e_status_code status;
3426 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3428 cmd->address = CPU_TO_LE32(reg_addr);
3429 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3430 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3432 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3438 * i40e_aq_request_resource
3439 * @hw: pointer to the hw struct
3440 * @resource: resource id
3441 * @access: access type
3442 * @sdp_number: resource number
3443 * @timeout: the maximum time in ms that the driver may hold the resource
3444 * @cmd_details: pointer to command details structure or NULL
3446 * requests common resource using the admin queue commands
3448 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3449 enum i40e_aq_resources_ids resource,
3450 enum i40e_aq_resource_access_type access,
3451 u8 sdp_number, u64 *timeout,
3452 struct i40e_asq_cmd_details *cmd_details)
3454 struct i40e_aq_desc desc;
3455 struct i40e_aqc_request_resource *cmd_resp =
3456 (struct i40e_aqc_request_resource *)&desc.params.raw;
3457 enum i40e_status_code status;
3459 DEBUGFUNC("i40e_aq_request_resource");
3461 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3463 cmd_resp->resource_id = CPU_TO_LE16(resource);
3464 cmd_resp->access_type = CPU_TO_LE16(access);
3465 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3467 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3468 /* The completion specifies the maximum time in ms that the driver
3469 * may hold the resource in the Timeout field.
3470 * If the resource is held by someone else, the command completes with
3471 * busy return value and the timeout field indicates the maximum time
3472 * the current owner of the resource has to free it.
3474 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3475 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3481 * i40e_aq_release_resource
3482 * @hw: pointer to the hw struct
3483 * @resource: resource id
3484 * @sdp_number: resource number
3485 * @cmd_details: pointer to command details structure or NULL
3487 * release common resource using the admin queue commands
3489 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3490 enum i40e_aq_resources_ids resource,
3492 struct i40e_asq_cmd_details *cmd_details)
3494 struct i40e_aq_desc desc;
3495 struct i40e_aqc_request_resource *cmd =
3496 (struct i40e_aqc_request_resource *)&desc.params.raw;
3497 enum i40e_status_code status;
3499 DEBUGFUNC("i40e_aq_release_resource");
3501 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3503 cmd->resource_id = CPU_TO_LE16(resource);
3504 cmd->resource_number = CPU_TO_LE32(sdp_number);
3506 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3513 * @hw: pointer to the hw struct
3514 * @module_pointer: module pointer location in words from the NVM beginning
3515 * @offset: byte offset from the module beginning
3516 * @length: length of the section to be read (in bytes from the offset)
3517 * @data: command buffer (size [bytes] = length)
3518 * @last_command: tells if this is the last command in a series
3519 * @cmd_details: pointer to command details structure or NULL
3521 * Read the NVM using the admin queue commands
3523 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3524 u32 offset, u16 length, void *data,
3526 struct i40e_asq_cmd_details *cmd_details)
3528 struct i40e_aq_desc desc;
3529 struct i40e_aqc_nvm_update *cmd =
3530 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3531 enum i40e_status_code status;
3533 DEBUGFUNC("i40e_aq_read_nvm");
3535 /* In offset the highest byte must be zeroed. */
3536 if (offset & 0xFF000000) {
3537 status = I40E_ERR_PARAM;
3538 goto i40e_aq_read_nvm_exit;
3541 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3543 /* If this is the last command in a series, set the proper flag. */
3545 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3546 cmd->module_pointer = module_pointer;
3547 cmd->offset = CPU_TO_LE32(offset);
3548 cmd->length = CPU_TO_LE16(length);
3550 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3551 if (length > I40E_AQ_LARGE_BUF)
3552 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3554 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3556 i40e_aq_read_nvm_exit:
3561 * i40e_aq_read_nvm_config - read an nvm config block
3562 * @hw: pointer to the hw struct
3563 * @cmd_flags: NVM access admin command bits
3564 * @field_id: field or feature id
3565 * @data: buffer for result
3566 * @buf_size: buffer size
3567 * @element_count: pointer to count of elements read by FW
3568 * @cmd_details: pointer to command details structure or NULL
3570 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3571 u8 cmd_flags, u32 field_id, void *data,
3572 u16 buf_size, u16 *element_count,
3573 struct i40e_asq_cmd_details *cmd_details)
3575 struct i40e_aq_desc desc;
3576 struct i40e_aqc_nvm_config_read *cmd =
3577 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3578 enum i40e_status_code status;
3580 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3581 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3582 if (buf_size > I40E_AQ_LARGE_BUF)
3583 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3585 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3586 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3587 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3588 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3590 cmd->element_id_msw = 0;
3592 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3594 if (!status && element_count)
3595 *element_count = LE16_TO_CPU(cmd->element_count);
3601 * i40e_aq_write_nvm_config - write an nvm config block
3602 * @hw: pointer to the hw struct
3603 * @cmd_flags: NVM access admin command bits
3604 * @data: buffer for result
3605 * @buf_size: buffer size
3606 * @element_count: count of elements to be written
3607 * @cmd_details: pointer to command details structure or NULL
3609 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3610 u8 cmd_flags, void *data, u16 buf_size,
3612 struct i40e_asq_cmd_details *cmd_details)
3614 struct i40e_aq_desc desc;
3615 struct i40e_aqc_nvm_config_write *cmd =
3616 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3617 enum i40e_status_code status;
3619 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3620 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3621 if (buf_size > I40E_AQ_LARGE_BUF)
3622 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3624 cmd->element_count = CPU_TO_LE16(element_count);
3625 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3626 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3632 * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3633 * @hw: pointer to the hw struct
3634 * @buff: buffer for result
3635 * @buff_size: buffer size
3636 * @cmd_details: pointer to command details structure or NULL
3638 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3639 void *buff, u16 buff_size,
3640 struct i40e_asq_cmd_details *cmd_details)
3642 struct i40e_aq_desc desc;
3643 enum i40e_status_code status;
3645 UNREFERENCED_2PARAMETER(buff, buff_size);
3647 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3648 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3649 if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3650 status = I40E_ERR_NOT_IMPLEMENTED;
3657 * @hw: pointer to the hw struct
3658 * @module_pointer: module pointer location in words from the NVM beginning
3659 * @offset: offset in the module (expressed in 4 KB from module's beginning)
3660 * @length: length of the section to be erased (expressed in 4 KB)
3661 * @last_command: tells if this is the last command in a series
3662 * @cmd_details: pointer to command details structure or NULL
3664 * Erase the NVM sector using the admin queue commands
3666 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3667 u32 offset, u16 length, bool last_command,
3668 struct i40e_asq_cmd_details *cmd_details)
3670 struct i40e_aq_desc desc;
3671 struct i40e_aqc_nvm_update *cmd =
3672 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3673 enum i40e_status_code status;
3675 DEBUGFUNC("i40e_aq_erase_nvm");
3677 /* In offset the highest byte must be zeroed. */
3678 if (offset & 0xFF000000) {
3679 status = I40E_ERR_PARAM;
3680 goto i40e_aq_erase_nvm_exit;
3683 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3685 /* If this is the last command in a series, set the proper flag. */
3687 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3688 cmd->module_pointer = module_pointer;
3689 cmd->offset = CPU_TO_LE32(offset);
3690 cmd->length = CPU_TO_LE16(length);
3692 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3694 i40e_aq_erase_nvm_exit:
3699 * i40e_parse_discover_capabilities
3700 * @hw: pointer to the hw struct
3701 * @buff: pointer to a buffer containing device/function capability records
3702 * @cap_count: number of capability records in the list
3703 * @list_type_opc: type of capabilities list to parse
3705 * Parse the device/function capabilities list.
3707 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3709 enum i40e_admin_queue_opc list_type_opc)
3711 struct i40e_aqc_list_capabilities_element_resp *cap;
3712 u32 valid_functions, num_functions;
3713 u32 number, logical_id, phys_id;
3714 struct i40e_hw_capabilities *p;
3715 enum i40e_status_code status;
3716 u16 id, ocp_cfg_word0;
3720 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3722 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3723 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3724 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3725 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3729 for (i = 0; i < cap_count; i++, cap++) {
3730 id = LE16_TO_CPU(cap->id);
3731 number = LE32_TO_CPU(cap->number);
3732 logical_id = LE32_TO_CPU(cap->logical_id);
3733 phys_id = LE32_TO_CPU(cap->phys_id);
3734 major_rev = cap->major_rev;
3737 case I40E_AQ_CAP_ID_SWITCH_MODE:
3738 p->switch_mode = number;
3739 i40e_debug(hw, I40E_DEBUG_INIT,
3740 "HW Capability: Switch mode = %d\n",
3743 case I40E_AQ_CAP_ID_MNG_MODE:
3744 p->management_mode = number;
3745 if (major_rev > 1) {
3746 p->mng_protocols_over_mctp = logical_id;
3747 i40e_debug(hw, I40E_DEBUG_INIT,
3748 "HW Capability: Protocols over MCTP = %d\n",
3749 p->mng_protocols_over_mctp);
3751 p->mng_protocols_over_mctp = 0;
3753 i40e_debug(hw, I40E_DEBUG_INIT,
3754 "HW Capability: Management Mode = %d\n",
3755 p->management_mode);
3757 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3758 p->npar_enable = number;
3759 i40e_debug(hw, I40E_DEBUG_INIT,
3760 "HW Capability: NPAR enable = %d\n",
3763 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3765 i40e_debug(hw, I40E_DEBUG_INIT,
3766 "HW Capability: OS2BMC = %d\n", p->os2bmc);
3768 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3769 p->valid_functions = number;
3770 i40e_debug(hw, I40E_DEBUG_INIT,
3771 "HW Capability: Valid Functions = %d\n",
3772 p->valid_functions);
3774 case I40E_AQ_CAP_ID_SRIOV:
3776 p->sr_iov_1_1 = true;
3777 i40e_debug(hw, I40E_DEBUG_INIT,
3778 "HW Capability: SR-IOV = %d\n",
3781 case I40E_AQ_CAP_ID_VF:
3782 p->num_vfs = number;
3783 p->vf_base_id = logical_id;
3784 i40e_debug(hw, I40E_DEBUG_INIT,
3785 "HW Capability: VF count = %d\n",
3787 i40e_debug(hw, I40E_DEBUG_INIT,
3788 "HW Capability: VF base_id = %d\n",
3791 case I40E_AQ_CAP_ID_VMDQ:
3794 i40e_debug(hw, I40E_DEBUG_INIT,
3795 "HW Capability: VMDQ = %d\n", p->vmdq);
3797 case I40E_AQ_CAP_ID_8021QBG:
3799 p->evb_802_1_qbg = true;
3800 i40e_debug(hw, I40E_DEBUG_INIT,
3801 "HW Capability: 802.1Qbg = %d\n", number);
3803 case I40E_AQ_CAP_ID_8021QBR:
3805 p->evb_802_1_qbh = true;
3806 i40e_debug(hw, I40E_DEBUG_INIT,
3807 "HW Capability: 802.1Qbh = %d\n", number);
3809 case I40E_AQ_CAP_ID_VSI:
3810 p->num_vsis = number;
3811 i40e_debug(hw, I40E_DEBUG_INIT,
3812 "HW Capability: VSI count = %d\n",
3815 case I40E_AQ_CAP_ID_DCB:
3818 p->enabled_tcmap = logical_id;
3821 i40e_debug(hw, I40E_DEBUG_INIT,
3822 "HW Capability: DCB = %d\n", p->dcb);
3823 i40e_debug(hw, I40E_DEBUG_INIT,
3824 "HW Capability: TC Mapping = %d\n",
3826 i40e_debug(hw, I40E_DEBUG_INIT,
3827 "HW Capability: TC Max = %d\n", p->maxtc);
3829 case I40E_AQ_CAP_ID_FCOE:
3832 i40e_debug(hw, I40E_DEBUG_INIT,
3833 "HW Capability: FCOE = %d\n", p->fcoe);
3835 case I40E_AQ_CAP_ID_ISCSI:
3838 i40e_debug(hw, I40E_DEBUG_INIT,
3839 "HW Capability: iSCSI = %d\n", p->iscsi);
3841 case I40E_AQ_CAP_ID_RSS:
3843 p->rss_table_size = number;
3844 p->rss_table_entry_width = logical_id;
3845 i40e_debug(hw, I40E_DEBUG_INIT,
3846 "HW Capability: RSS = %d\n", p->rss);
3847 i40e_debug(hw, I40E_DEBUG_INIT,
3848 "HW Capability: RSS table size = %d\n",
3850 i40e_debug(hw, I40E_DEBUG_INIT,
3851 "HW Capability: RSS table width = %d\n",
3852 p->rss_table_entry_width);
3854 case I40E_AQ_CAP_ID_RXQ:
3855 p->num_rx_qp = number;
3856 p->base_queue = phys_id;
3857 i40e_debug(hw, I40E_DEBUG_INIT,
3858 "HW Capability: Rx QP = %d\n", number);
3859 i40e_debug(hw, I40E_DEBUG_INIT,
3860 "HW Capability: base_queue = %d\n",
3863 case I40E_AQ_CAP_ID_TXQ:
3864 p->num_tx_qp = number;
3865 p->base_queue = phys_id;
3866 i40e_debug(hw, I40E_DEBUG_INIT,
3867 "HW Capability: Tx QP = %d\n", number);
3868 i40e_debug(hw, I40E_DEBUG_INIT,
3869 "HW Capability: base_queue = %d\n",
3872 case I40E_AQ_CAP_ID_MSIX:
3873 p->num_msix_vectors = number;
3874 i40e_debug(hw, I40E_DEBUG_INIT,
3875 "HW Capability: MSIX vector count = %d\n",
3876 p->num_msix_vectors);
3878 case I40E_AQ_CAP_ID_VF_MSIX:
3879 p->num_msix_vectors_vf = number;
3880 i40e_debug(hw, I40E_DEBUG_INIT,
3881 "HW Capability: MSIX VF vector count = %d\n",
3882 p->num_msix_vectors_vf);
3884 case I40E_AQ_CAP_ID_FLEX10:
3885 if (major_rev == 1) {
3887 p->flex10_enable = true;
3888 p->flex10_capable = true;
3891 /* Capability revision >= 2 */
3893 p->flex10_enable = true;
3895 p->flex10_capable = true;
3897 p->flex10_mode = logical_id;
3898 p->flex10_status = phys_id;
3899 i40e_debug(hw, I40E_DEBUG_INIT,
3900 "HW Capability: Flex10 mode = %d\n",
3902 i40e_debug(hw, I40E_DEBUG_INIT,
3903 "HW Capability: Flex10 status = %d\n",
3906 case I40E_AQ_CAP_ID_CEM:
3909 i40e_debug(hw, I40E_DEBUG_INIT,
3910 "HW Capability: CEM = %d\n", p->mgmt_cem);
3912 case I40E_AQ_CAP_ID_IWARP:
3915 i40e_debug(hw, I40E_DEBUG_INIT,
3916 "HW Capability: iWARP = %d\n", p->iwarp);
3918 case I40E_AQ_CAP_ID_LED:
3919 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3920 p->led[phys_id] = true;
3921 i40e_debug(hw, I40E_DEBUG_INIT,
3922 "HW Capability: LED - PIN %d\n", phys_id);
3924 case I40E_AQ_CAP_ID_SDP:
3925 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3926 p->sdp[phys_id] = true;
3927 i40e_debug(hw, I40E_DEBUG_INIT,
3928 "HW Capability: SDP - PIN %d\n", phys_id);
3930 case I40E_AQ_CAP_ID_MDIO:
3932 p->mdio_port_num = phys_id;
3933 p->mdio_port_mode = logical_id;
3935 i40e_debug(hw, I40E_DEBUG_INIT,
3936 "HW Capability: MDIO port number = %d\n",
3938 i40e_debug(hw, I40E_DEBUG_INIT,
3939 "HW Capability: MDIO port mode = %d\n",
3942 case I40E_AQ_CAP_ID_1588:
3944 p->ieee_1588 = true;
3945 i40e_debug(hw, I40E_DEBUG_INIT,
3946 "HW Capability: IEEE 1588 = %d\n",
3949 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3951 p->fd_filters_guaranteed = number;
3952 p->fd_filters_best_effort = logical_id;
3953 i40e_debug(hw, I40E_DEBUG_INIT,
3954 "HW Capability: Flow Director = 1\n");
3955 i40e_debug(hw, I40E_DEBUG_INIT,
3956 "HW Capability: Guaranteed FD filters = %d\n",
3957 p->fd_filters_guaranteed);
3959 case I40E_AQ_CAP_ID_WSR_PROT:
3960 p->wr_csr_prot = (u64)number;
3961 p->wr_csr_prot |= (u64)logical_id << 32;
3962 i40e_debug(hw, I40E_DEBUG_INIT,
3963 "HW Capability: wr_csr_prot = 0x%llX\n\n",
3964 (p->wr_csr_prot & 0xffff));
3966 case I40E_AQ_CAP_ID_NVM_MGMT:
3967 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3968 p->sec_rev_disabled = true;
3969 if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3970 p->update_disabled = true;
3972 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3973 hw->num_wol_proxy_filters = (u16)number;
3974 hw->wol_proxy_vsi_seid = (u16)logical_id;
3975 p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3976 if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3977 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3979 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3980 p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3981 i40e_debug(hw, I40E_DEBUG_INIT,
3982 "HW Capability: WOL proxy filters = %d\n",
3983 hw->num_wol_proxy_filters);
3991 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3993 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3996 /* count the enabled ports (aka the "not disabled" ports) */
3998 for (i = 0; i < 4; i++) {
3999 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
4002 /* use AQ read to get the physical register offset instead
4003 * of the port relative offset
4005 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
4006 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
4010 /* OCP cards case: if a mezz is removed the ethernet port is at
4011 * disabled state in PRTGEN_CNF register. Additional NVM read is
4012 * needed in order to check if we are dealing with OCP card.
4013 * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting
4014 * physical ports results in wrong partition id calculation and thus
4015 * not supporting WoL.
4017 if (hw->mac.type == I40E_MAC_X722) {
4018 if (i40e_acquire_nvm(hw, I40E_RESOURCE_READ) == I40E_SUCCESS) {
4019 status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR,
4020 2 * I40E_SR_OCP_CFG_WORD0,
4021 sizeof(ocp_cfg_word0),
4022 &ocp_cfg_word0, true, NULL);
4023 if (status == I40E_SUCCESS &&
4024 (ocp_cfg_word0 & I40E_SR_OCP_ENABLED))
4026 i40e_release_nvm(hw);
4030 valid_functions = p->valid_functions;
4032 while (valid_functions) {
4033 if (valid_functions & 1)
4035 valid_functions >>= 1;
4038 /* partition id is 1-based, and functions are evenly spread
4039 * across the ports as partitions
4041 if (hw->num_ports != 0) {
4042 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
4043 hw->num_partitions = num_functions / hw->num_ports;
4046 /* additional HW specific goodies that might
4047 * someday be HW version specific
4049 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
4053 * i40e_aq_discover_capabilities
4054 * @hw: pointer to the hw struct
4055 * @buff: a virtual buffer to hold the capabilities
4056 * @buff_size: Size of the virtual buffer
4057 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
4058 * @list_type_opc: capabilities type to discover - pass in the command opcode
4059 * @cmd_details: pointer to command details structure or NULL
4061 * Get the device capabilities descriptions from the firmware
4063 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
4064 void *buff, u16 buff_size, u16 *data_size,
4065 enum i40e_admin_queue_opc list_type_opc,
4066 struct i40e_asq_cmd_details *cmd_details)
4068 struct i40e_aqc_list_capabilites *cmd;
4069 struct i40e_aq_desc desc;
4070 enum i40e_status_code status = I40E_SUCCESS;
4072 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
4074 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
4075 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
4076 status = I40E_ERR_PARAM;
4080 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
4082 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4083 if (buff_size > I40E_AQ_LARGE_BUF)
4084 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4086 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4087 *data_size = LE16_TO_CPU(desc.datalen);
4092 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
4100 * i40e_aq_update_nvm
4101 * @hw: pointer to the hw struct
4102 * @module_pointer: module pointer location in words from the NVM beginning
4103 * @offset: byte offset from the module beginning
4104 * @length: length of the section to be written (in bytes from the offset)
4105 * @data: command buffer (size [bytes] = length)
4106 * @last_command: tells if this is the last command in a series
4107 * @preservation_flags: Preservation mode flags
4108 * @cmd_details: pointer to command details structure or NULL
4110 * Update the NVM using the admin queue commands
4112 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
4113 u32 offset, u16 length, void *data,
4114 bool last_command, u8 preservation_flags,
4115 struct i40e_asq_cmd_details *cmd_details)
4117 struct i40e_aq_desc desc;
4118 struct i40e_aqc_nvm_update *cmd =
4119 (struct i40e_aqc_nvm_update *)&desc.params.raw;
4120 enum i40e_status_code status;
4122 DEBUGFUNC("i40e_aq_update_nvm");
4124 /* In offset the highest byte must be zeroed. */
4125 if (offset & 0xFF000000) {
4126 status = I40E_ERR_PARAM;
4127 goto i40e_aq_update_nvm_exit;
4130 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4132 /* If this is the last command in a series, set the proper flag. */
4134 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
4135 if (hw->mac.type == I40E_MAC_X722) {
4136 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED)
4137 cmd->command_flags |=
4138 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED <<
4139 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4140 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL)
4141 cmd->command_flags |=
4142 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL <<
4143 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4145 cmd->module_pointer = module_pointer;
4146 cmd->offset = CPU_TO_LE32(offset);
4147 cmd->length = CPU_TO_LE16(length);
4149 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4150 if (length > I40E_AQ_LARGE_BUF)
4151 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4153 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
4155 i40e_aq_update_nvm_exit:
4160 * i40e_aq_rearrange_nvm
4161 * @hw: pointer to the hw struct
4162 * @rearrange_nvm: defines direction of rearrangement
4163 * @cmd_details: pointer to command details structure or NULL
4165 * Rearrange NVM structure, available only for transition FW
4167 enum i40e_status_code i40e_aq_rearrange_nvm(struct i40e_hw *hw,
4169 struct i40e_asq_cmd_details *cmd_details)
4171 struct i40e_aqc_nvm_update *cmd;
4172 enum i40e_status_code status;
4173 struct i40e_aq_desc desc;
4175 DEBUGFUNC("i40e_aq_rearrange_nvm");
4177 cmd = (struct i40e_aqc_nvm_update *)&desc.params.raw;
4179 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4181 rearrange_nvm &= (I40E_AQ_NVM_REARRANGE_TO_FLAT |
4182 I40E_AQ_NVM_REARRANGE_TO_STRUCT);
4184 if (!rearrange_nvm) {
4185 status = I40E_ERR_PARAM;
4186 goto i40e_aq_rearrange_nvm_exit;
4189 cmd->command_flags |= rearrange_nvm;
4190 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4192 i40e_aq_rearrange_nvm_exit:
4197 * i40e_aq_nvm_progress
4198 * @hw: pointer to the hw struct
4199 * @progress: pointer to progress returned from AQ
4200 * @cmd_details: pointer to command details structure or NULL
4202 * Gets progress of flash rearrangement process
4204 enum i40e_status_code i40e_aq_nvm_progress(struct i40e_hw *hw, u8 *progress,
4205 struct i40e_asq_cmd_details *cmd_details)
4207 enum i40e_status_code status;
4208 struct i40e_aq_desc desc;
4210 DEBUGFUNC("i40e_aq_nvm_progress");
4212 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_progress);
4213 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4214 *progress = desc.params.raw[0];
4219 * i40e_aq_get_lldp_mib
4220 * @hw: pointer to the hw struct
4221 * @bridge_type: type of bridge requested
4222 * @mib_type: Local, Remote or both Local and Remote MIBs
4223 * @buff: pointer to a user supplied buffer to store the MIB block
4224 * @buff_size: size of the buffer (in bytes)
4225 * @local_len : length of the returned Local LLDP MIB
4226 * @remote_len: length of the returned Remote LLDP MIB
4227 * @cmd_details: pointer to command details structure or NULL
4229 * Requests the complete LLDP MIB (entire packet).
4231 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4232 u8 mib_type, void *buff, u16 buff_size,
4233 u16 *local_len, u16 *remote_len,
4234 struct i40e_asq_cmd_details *cmd_details)
4236 struct i40e_aq_desc desc;
4237 struct i40e_aqc_lldp_get_mib *cmd =
4238 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4239 struct i40e_aqc_lldp_get_mib *resp =
4240 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4241 enum i40e_status_code status;
4243 if (buff_size == 0 || !buff)
4244 return I40E_ERR_PARAM;
4246 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4247 /* Indirect Command */
4248 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4250 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4251 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4252 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4254 desc.datalen = CPU_TO_LE16(buff_size);
4256 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4257 if (buff_size > I40E_AQ_LARGE_BUF)
4258 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4260 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4262 if (local_len != NULL)
4263 *local_len = LE16_TO_CPU(resp->local_len);
4264 if (remote_len != NULL)
4265 *remote_len = LE16_TO_CPU(resp->remote_len);
4272 * i40e_aq_set_lldp_mib - Set the LLDP MIB
4273 * @hw: pointer to the hw struct
4274 * @mib_type: Local, Remote or both Local and Remote MIBs
4275 * @buff: pointer to a user supplied buffer to store the MIB block
4276 * @buff_size: size of the buffer (in bytes)
4277 * @cmd_details: pointer to command details structure or NULL
4281 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4282 u8 mib_type, void *buff, u16 buff_size,
4283 struct i40e_asq_cmd_details *cmd_details)
4285 struct i40e_aq_desc desc;
4286 struct i40e_aqc_lldp_set_local_mib *cmd =
4287 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4288 enum i40e_status_code status;
4290 if (buff_size == 0 || !buff)
4291 return I40E_ERR_PARAM;
4293 i40e_fill_default_direct_cmd_desc(&desc,
4294 i40e_aqc_opc_lldp_set_local_mib);
4295 /* Indirect Command */
4296 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4297 if (buff_size > I40E_AQ_LARGE_BUF)
4298 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4299 desc.datalen = CPU_TO_LE16(buff_size);
4301 cmd->type = mib_type;
4302 cmd->length = CPU_TO_LE16(buff_size);
4303 cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4304 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4306 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4311 * i40e_aq_cfg_lldp_mib_change_event
4312 * @hw: pointer to the hw struct
4313 * @enable_update: Enable or Disable event posting
4314 * @cmd_details: pointer to command details structure or NULL
4316 * Enable or Disable posting of an event on ARQ when LLDP MIB
4317 * associated with the interface changes
4319 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4321 struct i40e_asq_cmd_details *cmd_details)
4323 struct i40e_aq_desc desc;
4324 struct i40e_aqc_lldp_update_mib *cmd =
4325 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4326 enum i40e_status_code status;
4328 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4331 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4333 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4339 * i40e_aq_add_lldp_tlv
4340 * @hw: pointer to the hw struct
4341 * @bridge_type: type of bridge
4342 * @buff: buffer with TLV to add
4343 * @buff_size: length of the buffer
4344 * @tlv_len: length of the TLV to be added
4345 * @mib_len: length of the LLDP MIB returned in response
4346 * @cmd_details: pointer to command details structure or NULL
4348 * Add the specified TLV to LLDP Local MIB for the given bridge type,
4349 * it is responsibility of the caller to make sure that the TLV is not
4350 * already present in the LLDPDU.
4351 * In return firmware will write the complete LLDP MIB with the newly
4352 * added TLV in the response buffer.
4354 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4355 void *buff, u16 buff_size, u16 tlv_len,
4357 struct i40e_asq_cmd_details *cmd_details)
4359 struct i40e_aq_desc desc;
4360 struct i40e_aqc_lldp_add_tlv *cmd =
4361 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4362 enum i40e_status_code status;
4364 if (buff_size == 0 || !buff || tlv_len == 0)
4365 return I40E_ERR_PARAM;
4367 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4369 /* Indirect Command */
4370 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4371 if (buff_size > I40E_AQ_LARGE_BUF)
4372 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4373 desc.datalen = CPU_TO_LE16(buff_size);
4375 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4376 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4377 cmd->len = CPU_TO_LE16(tlv_len);
4379 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4381 if (mib_len != NULL)
4382 *mib_len = LE16_TO_CPU(desc.datalen);
4389 * i40e_aq_update_lldp_tlv
4390 * @hw: pointer to the hw struct
4391 * @bridge_type: type of bridge
4392 * @buff: buffer with TLV to update
4393 * @buff_size: size of the buffer holding original and updated TLVs
4394 * @old_len: Length of the Original TLV
4395 * @new_len: Length of the Updated TLV
4396 * @offset: offset of the updated TLV in the buff
4397 * @mib_len: length of the returned LLDP MIB
4398 * @cmd_details: pointer to command details structure or NULL
4400 * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4401 * Firmware will place the complete LLDP MIB in response buffer with the
4404 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4405 u8 bridge_type, void *buff, u16 buff_size,
4406 u16 old_len, u16 new_len, u16 offset,
4408 struct i40e_asq_cmd_details *cmd_details)
4410 struct i40e_aq_desc desc;
4411 struct i40e_aqc_lldp_update_tlv *cmd =
4412 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4413 enum i40e_status_code status;
4415 if (buff_size == 0 || !buff || offset == 0 ||
4416 old_len == 0 || new_len == 0)
4417 return I40E_ERR_PARAM;
4419 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4421 /* Indirect Command */
4422 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4423 if (buff_size > I40E_AQ_LARGE_BUF)
4424 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4425 desc.datalen = CPU_TO_LE16(buff_size);
4427 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4428 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4429 cmd->old_len = CPU_TO_LE16(old_len);
4430 cmd->new_offset = CPU_TO_LE16(offset);
4431 cmd->new_len = CPU_TO_LE16(new_len);
4433 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4435 if (mib_len != NULL)
4436 *mib_len = LE16_TO_CPU(desc.datalen);
4443 * i40e_aq_delete_lldp_tlv
4444 * @hw: pointer to the hw struct
4445 * @bridge_type: type of bridge
4446 * @buff: pointer to a user supplied buffer that has the TLV
4447 * @buff_size: length of the buffer
4448 * @tlv_len: length of the TLV to be deleted
4449 * @mib_len: length of the returned LLDP MIB
4450 * @cmd_details: pointer to command details structure or NULL
4452 * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4453 * The firmware places the entire LLDP MIB in the response buffer.
4455 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4456 u8 bridge_type, void *buff, u16 buff_size,
4457 u16 tlv_len, u16 *mib_len,
4458 struct i40e_asq_cmd_details *cmd_details)
4460 struct i40e_aq_desc desc;
4461 struct i40e_aqc_lldp_add_tlv *cmd =
4462 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4463 enum i40e_status_code status;
4465 if (buff_size == 0 || !buff)
4466 return I40E_ERR_PARAM;
4468 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4470 /* Indirect Command */
4471 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4472 if (buff_size > I40E_AQ_LARGE_BUF)
4473 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4474 desc.datalen = CPU_TO_LE16(buff_size);
4475 cmd->len = CPU_TO_LE16(tlv_len);
4476 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4477 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4479 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4481 if (mib_len != NULL)
4482 *mib_len = LE16_TO_CPU(desc.datalen);
4490 * @hw: pointer to the hw struct
4491 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4492 * @cmd_details: pointer to command details structure or NULL
4494 * Stop or Shutdown the embedded LLDP Agent
4496 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4497 struct i40e_asq_cmd_details *cmd_details)
4499 struct i40e_aq_desc desc;
4500 struct i40e_aqc_lldp_stop *cmd =
4501 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4502 enum i40e_status_code status;
4504 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4507 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4509 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4515 * i40e_aq_start_lldp
4516 * @hw: pointer to the hw struct
4517 * @cmd_details: pointer to command details structure or NULL
4519 * Start the embedded LLDP Agent on all ports.
4521 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4522 struct i40e_asq_cmd_details *cmd_details)
4524 struct i40e_aq_desc desc;
4525 struct i40e_aqc_lldp_start *cmd =
4526 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4527 enum i40e_status_code status;
4529 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4531 cmd->command = I40E_AQ_LLDP_AGENT_START;
4532 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4538 * i40e_aq_set_dcb_parameters
4539 * @hw: pointer to the hw struct
4540 * @cmd_details: pointer to command details structure or NULL
4541 * @dcb_enable: True if DCB configuration needs to be applied
4544 enum i40e_status_code
4545 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable,
4546 struct i40e_asq_cmd_details *cmd_details)
4548 struct i40e_aq_desc desc;
4549 struct i40e_aqc_set_dcb_parameters *cmd =
4550 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw;
4551 enum i40e_status_code status;
4553 if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_STOPPABLE))
4554 return I40E_ERR_DEVICE_NOT_SUPPORTED;
4556 i40e_fill_default_direct_cmd_desc(&desc,
4557 i40e_aqc_opc_set_dcb_parameters);
4560 cmd->valid_flags = I40E_DCB_VALID;
4561 cmd->command = I40E_AQ_DCB_SET_AGENT;
4563 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4569 * i40e_aq_get_cee_dcb_config
4570 * @hw: pointer to the hw struct
4571 * @buff: response buffer that stores CEE operational configuration
4572 * @buff_size: size of the buffer passed
4573 * @cmd_details: pointer to command details structure or NULL
4575 * Get CEE DCBX mode operational configuration from firmware
4577 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4578 void *buff, u16 buff_size,
4579 struct i40e_asq_cmd_details *cmd_details)
4581 struct i40e_aq_desc desc;
4582 enum i40e_status_code status;
4584 if (buff_size == 0 || !buff)
4585 return I40E_ERR_PARAM;
4587 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4589 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4590 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4597 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4598 * @hw: pointer to the hw struct
4599 * @start_agent: True if DCBx Agent needs to be Started
4600 * False if DCBx Agent needs to be Stopped
4601 * @cmd_details: pointer to command details structure or NULL
4603 * Start/Stop the embedded dcbx Agent
4605 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4607 struct i40e_asq_cmd_details *cmd_details)
4609 struct i40e_aq_desc desc;
4610 struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4611 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4613 enum i40e_status_code status;
4615 i40e_fill_default_direct_cmd_desc(&desc,
4616 i40e_aqc_opc_lldp_stop_start_spec_agent);
4619 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4621 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4627 * i40e_aq_add_udp_tunnel
4628 * @hw: pointer to the hw struct
4629 * @udp_port: the UDP port to add in Host byte order
4630 * @protocol_index: protocol index type
4631 * @filter_index: pointer to filter index
4632 * @cmd_details: pointer to command details structure or NULL
4634 * Note: Firmware expects the udp_port value to be in Little Endian format,
4635 * and this function will call CPU_TO_LE16 to convert from Host byte order to
4636 * Little Endian order.
4638 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4639 u16 udp_port, u8 protocol_index,
4641 struct i40e_asq_cmd_details *cmd_details)
4643 struct i40e_aq_desc desc;
4644 struct i40e_aqc_add_udp_tunnel *cmd =
4645 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4646 struct i40e_aqc_del_udp_tunnel_completion *resp =
4647 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4648 enum i40e_status_code status;
4650 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4652 cmd->udp_port = CPU_TO_LE16(udp_port);
4653 cmd->protocol_type = protocol_index;
4655 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4657 if (!status && filter_index)
4658 *filter_index = resp->index;
4664 * i40e_aq_del_udp_tunnel
4665 * @hw: pointer to the hw struct
4666 * @index: filter index
4667 * @cmd_details: pointer to command details structure or NULL
4669 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4670 struct i40e_asq_cmd_details *cmd_details)
4672 struct i40e_aq_desc desc;
4673 struct i40e_aqc_remove_udp_tunnel *cmd =
4674 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4675 enum i40e_status_code status;
4677 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4681 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4687 * i40e_aq_get_switch_resource_alloc (0x0204)
4688 * @hw: pointer to the hw struct
4689 * @num_entries: pointer to u8 to store the number of resource entries returned
4690 * @buf: pointer to a user supplied buffer. This buffer must be large enough
4691 * to store the resource information for all resource types. Each
4692 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
4693 * @count: size, in bytes, of the buffer provided
4694 * @cmd_details: pointer to command details structure or NULL
4696 * Query the resources allocated to a function.
4698 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4700 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4702 struct i40e_asq_cmd_details *cmd_details)
4704 struct i40e_aq_desc desc;
4705 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4706 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4707 enum i40e_status_code status;
4708 u16 length = count * sizeof(*buf);
4710 i40e_fill_default_direct_cmd_desc(&desc,
4711 i40e_aqc_opc_get_switch_resource_alloc);
4713 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4714 if (length > I40E_AQ_LARGE_BUF)
4715 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4717 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4719 if (!status && num_entries)
4720 *num_entries = cmd_resp->num_entries;
4726 * i40e_aq_delete_element - Delete switch element
4727 * @hw: pointer to the hw struct
4728 * @seid: the SEID to delete from the switch
4729 * @cmd_details: pointer to command details structure or NULL
4731 * This deletes a switch element from the switch.
4733 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4734 struct i40e_asq_cmd_details *cmd_details)
4736 struct i40e_aq_desc desc;
4737 struct i40e_aqc_switch_seid *cmd =
4738 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4739 enum i40e_status_code status;
4742 return I40E_ERR_PARAM;
4744 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4746 cmd->seid = CPU_TO_LE16(seid);
4748 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4754 * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4755 * @hw: pointer to the hw struct
4756 * @flags: component flags
4757 * @mac_seid: uplink seid (MAC SEID)
4758 * @vsi_seid: connected vsi seid
4759 * @ret_seid: seid of create pv component
4761 * This instantiates an i40e port virtualizer with specified flags.
4762 * Depending on specified flags the port virtualizer can act as a
4763 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4765 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4766 u16 mac_seid, u16 vsi_seid,
4769 struct i40e_aq_desc desc;
4770 struct i40e_aqc_add_update_pv *cmd =
4771 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4772 struct i40e_aqc_add_update_pv_completion *resp =
4773 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4774 enum i40e_status_code status;
4777 return I40E_ERR_PARAM;
4779 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4780 cmd->command_flags = CPU_TO_LE16(flags);
4781 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4782 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4784 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4785 if (!status && ret_seid)
4786 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4792 * i40e_aq_add_tag - Add an S/E-tag
4793 * @hw: pointer to the hw struct
4794 * @direct_to_queue: should s-tag direct flow to a specific queue
4795 * @vsi_seid: VSI SEID to use this tag
4796 * @tag: value of the tag
4797 * @queue_num: queue number, only valid is direct_to_queue is true
4798 * @tags_used: return value, number of tags in use by this PF
4799 * @tags_free: return value, number of unallocated tags
4800 * @cmd_details: pointer to command details structure or NULL
4802 * This associates an S- or E-tag to a VSI in the switch complex. It returns
4803 * the number of tags allocated by the PF, and the number of unallocated
4806 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4807 u16 vsi_seid, u16 tag, u16 queue_num,
4808 u16 *tags_used, u16 *tags_free,
4809 struct i40e_asq_cmd_details *cmd_details)
4811 struct i40e_aq_desc desc;
4812 struct i40e_aqc_add_tag *cmd =
4813 (struct i40e_aqc_add_tag *)&desc.params.raw;
4814 struct i40e_aqc_add_remove_tag_completion *resp =
4815 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4816 enum i40e_status_code status;
4819 return I40E_ERR_PARAM;
4821 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4823 cmd->seid = CPU_TO_LE16(vsi_seid);
4824 cmd->tag = CPU_TO_LE16(tag);
4825 if (direct_to_queue) {
4826 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4827 cmd->queue_number = CPU_TO_LE16(queue_num);
4830 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4833 if (tags_used != NULL)
4834 *tags_used = LE16_TO_CPU(resp->tags_used);
4835 if (tags_free != NULL)
4836 *tags_free = LE16_TO_CPU(resp->tags_free);
4843 * i40e_aq_remove_tag - Remove an S- or E-tag
4844 * @hw: pointer to the hw struct
4845 * @vsi_seid: VSI SEID this tag is associated with
4846 * @tag: value of the S-tag to delete
4847 * @tags_used: return value, number of tags in use by this PF
4848 * @tags_free: return value, number of unallocated tags
4849 * @cmd_details: pointer to command details structure or NULL
4851 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
4852 * the number of tags allocated by the PF, and the number of unallocated
4855 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4856 u16 tag, u16 *tags_used, u16 *tags_free,
4857 struct i40e_asq_cmd_details *cmd_details)
4859 struct i40e_aq_desc desc;
4860 struct i40e_aqc_remove_tag *cmd =
4861 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4862 struct i40e_aqc_add_remove_tag_completion *resp =
4863 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4864 enum i40e_status_code status;
4867 return I40E_ERR_PARAM;
4869 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4871 cmd->seid = CPU_TO_LE16(vsi_seid);
4872 cmd->tag = CPU_TO_LE16(tag);
4874 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4877 if (tags_used != NULL)
4878 *tags_used = LE16_TO_CPU(resp->tags_used);
4879 if (tags_free != NULL)
4880 *tags_free = LE16_TO_CPU(resp->tags_free);
4887 * i40e_aq_add_mcast_etag - Add a multicast E-tag
4888 * @hw: pointer to the hw struct
4889 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4890 * @etag: value of E-tag to add
4891 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4892 * @buf: address of indirect buffer
4893 * @tags_used: return value, number of E-tags in use by this port
4894 * @tags_free: return value, number of unallocated M-tags
4895 * @cmd_details: pointer to command details structure or NULL
4897 * This associates a multicast E-tag to a port virtualizer. It will return
4898 * the number of tags allocated by the PF, and the number of unallocated
4901 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4902 * num_tags_in_buf long.
4904 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4905 u16 etag, u8 num_tags_in_buf, void *buf,
4906 u16 *tags_used, u16 *tags_free,
4907 struct i40e_asq_cmd_details *cmd_details)
4909 struct i40e_aq_desc desc;
4910 struct i40e_aqc_add_remove_mcast_etag *cmd =
4911 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4912 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4913 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4914 enum i40e_status_code status;
4915 u16 length = sizeof(u16) * num_tags_in_buf;
4917 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4918 return I40E_ERR_PARAM;
4920 i40e_fill_default_direct_cmd_desc(&desc,
4921 i40e_aqc_opc_add_multicast_etag);
4923 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4924 cmd->etag = CPU_TO_LE16(etag);
4925 cmd->num_unicast_etags = num_tags_in_buf;
4927 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4928 if (length > I40E_AQ_LARGE_BUF)
4929 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4931 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4934 if (tags_used != NULL)
4935 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4936 if (tags_free != NULL)
4937 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4944 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4945 * @hw: pointer to the hw struct
4946 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4947 * @etag: value of the E-tag to remove
4948 * @tags_used: return value, number of tags in use by this port
4949 * @tags_free: return value, number of unallocated tags
4950 * @cmd_details: pointer to command details structure or NULL
4952 * This deletes an E-tag from the port virtualizer. It will return
4953 * the number of tags allocated by the port, and the number of unallocated
4956 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4957 u16 etag, u16 *tags_used, u16 *tags_free,
4958 struct i40e_asq_cmd_details *cmd_details)
4960 struct i40e_aq_desc desc;
4961 struct i40e_aqc_add_remove_mcast_etag *cmd =
4962 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4963 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4964 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4965 enum i40e_status_code status;
4969 return I40E_ERR_PARAM;
4971 i40e_fill_default_direct_cmd_desc(&desc,
4972 i40e_aqc_opc_remove_multicast_etag);
4974 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4975 cmd->etag = CPU_TO_LE16(etag);
4977 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4980 if (tags_used != NULL)
4981 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4982 if (tags_free != NULL)
4983 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4990 * i40e_aq_update_tag - Update an S/E-tag
4991 * @hw: pointer to the hw struct
4992 * @vsi_seid: VSI SEID using this S-tag
4993 * @old_tag: old tag value
4994 * @new_tag: new tag value
4995 * @tags_used: return value, number of tags in use by this PF
4996 * @tags_free: return value, number of unallocated tags
4997 * @cmd_details: pointer to command details structure or NULL
4999 * This updates the value of the tag currently attached to this VSI
5000 * in the switch complex. It will return the number of tags allocated
5001 * by the PF, and the number of unallocated tags available.
5003 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
5004 u16 old_tag, u16 new_tag, u16 *tags_used,
5006 struct i40e_asq_cmd_details *cmd_details)
5008 struct i40e_aq_desc desc;
5009 struct i40e_aqc_update_tag *cmd =
5010 (struct i40e_aqc_update_tag *)&desc.params.raw;
5011 struct i40e_aqc_update_tag_completion *resp =
5012 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
5013 enum i40e_status_code status;
5016 return I40E_ERR_PARAM;
5018 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
5020 cmd->seid = CPU_TO_LE16(vsi_seid);
5021 cmd->old_tag = CPU_TO_LE16(old_tag);
5022 cmd->new_tag = CPU_TO_LE16(new_tag);
5024 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5027 if (tags_used != NULL)
5028 *tags_used = LE16_TO_CPU(resp->tags_used);
5029 if (tags_free != NULL)
5030 *tags_free = LE16_TO_CPU(resp->tags_free);
5037 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
5038 * @hw: pointer to the hw struct
5039 * @tcmap: TC map for request/release any ignore PFC condition
5040 * @request: request or release ignore PFC condition
5041 * @tcmap_ret: return TCs for which PFC is currently ignored
5042 * @cmd_details: pointer to command details structure or NULL
5044 * This sends out request/release to ignore PFC condition for a TC.
5045 * It will return the TCs for which PFC is currently ignored.
5047 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
5048 bool request, u8 *tcmap_ret,
5049 struct i40e_asq_cmd_details *cmd_details)
5051 struct i40e_aq_desc desc;
5052 struct i40e_aqc_pfc_ignore *cmd_resp =
5053 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
5054 enum i40e_status_code status;
5056 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
5059 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
5061 cmd_resp->tc_bitmap = tcmap;
5063 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5066 if (tcmap_ret != NULL)
5067 *tcmap_ret = cmd_resp->tc_bitmap;
5074 * i40e_aq_dcb_updated - DCB Updated Command
5075 * @hw: pointer to the hw struct
5076 * @cmd_details: pointer to command details structure or NULL
5078 * When LLDP is handled in PF this command is used by the PF
5079 * to notify EMP that a DCB setting is modified.
5080 * When LLDP is handled in EMP this command is used by the PF
5081 * to notify EMP whenever one of the following parameters get
5083 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
5084 * - PCIRTT in PRTDCB_GENC.PCIRTT
5085 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
5086 * EMP will return when the shared RPB settings have been
5087 * recomputed and modified. The retval field in the descriptor
5088 * will be set to 0 when RPB is modified.
5090 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
5091 struct i40e_asq_cmd_details *cmd_details)
5093 struct i40e_aq_desc desc;
5094 enum i40e_status_code status;
5096 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
5098 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5104 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
5105 * @hw: pointer to the hw struct
5106 * @seid: defines the SEID of the switch for which the stats are requested
5107 * @vlan_id: the VLAN ID for which the statistics are requested
5108 * @stat_index: index of the statistics counters block assigned to this VLAN
5109 * @cmd_details: pointer to command details structure or NULL
5111 * XL710 supports 128 smonVlanStats counters.This command is used to
5112 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
5115 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
5116 u16 vlan_id, u16 *stat_index,
5117 struct i40e_asq_cmd_details *cmd_details)
5119 struct i40e_aq_desc desc;
5120 struct i40e_aqc_add_remove_statistics *cmd_resp =
5121 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5122 enum i40e_status_code status;
5124 if ((seid == 0) || (stat_index == NULL))
5125 return I40E_ERR_PARAM;
5127 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
5129 cmd_resp->seid = CPU_TO_LE16(seid);
5130 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
5132 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5134 if (!status && stat_index)
5135 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
5141 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
5142 * @hw: pointer to the hw struct
5143 * @seid: defines the SEID of the switch for which the stats are requested
5144 * @vlan_id: the VLAN ID for which the statistics are requested
5145 * @stat_index: index of the statistics counters block assigned to this VLAN
5146 * @cmd_details: pointer to command details structure or NULL
5148 * XL710 supports 128 smonVlanStats counters.This command is used to
5149 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
5152 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
5153 u16 vlan_id, u16 stat_index,
5154 struct i40e_asq_cmd_details *cmd_details)
5156 struct i40e_aq_desc desc;
5157 struct i40e_aqc_add_remove_statistics *cmd =
5158 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5159 enum i40e_status_code status;
5162 return I40E_ERR_PARAM;
5164 i40e_fill_default_direct_cmd_desc(&desc,
5165 i40e_aqc_opc_remove_statistics);
5167 cmd->seid = CPU_TO_LE16(seid);
5168 cmd->vlan = CPU_TO_LE16(vlan_id);
5169 cmd->stat_index = CPU_TO_LE16(stat_index);
5171 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5177 * i40e_aq_set_port_parameters - set physical port parameters.
5178 * @hw: pointer to the hw struct
5179 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
5180 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
5181 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
5182 * @double_vlan: if set double VLAN is enabled
5183 * @cmd_details: pointer to command details structure or NULL
5185 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
5186 u16 bad_frame_vsi, bool save_bad_pac,
5187 bool pad_short_pac, bool double_vlan,
5188 struct i40e_asq_cmd_details *cmd_details)
5190 struct i40e_aqc_set_port_parameters *cmd;
5191 enum i40e_status_code status;
5192 struct i40e_aq_desc desc;
5193 u16 command_flags = 0;
5195 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
5197 i40e_fill_default_direct_cmd_desc(&desc,
5198 i40e_aqc_opc_set_port_parameters);
5200 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
5202 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
5204 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
5206 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
5207 cmd->command_flags = CPU_TO_LE16(command_flags);
5209 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5215 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
5216 * @hw: pointer to the hw struct
5217 * @seid: seid for the physical port/switching component/vsi
5218 * @buff: Indirect buffer to hold data parameters and response
5219 * @buff_size: Indirect buffer size
5220 * @opcode: Tx scheduler AQ command opcode
5221 * @cmd_details: pointer to command details structure or NULL
5223 * Generic command handler for Tx scheduler AQ commands
5225 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
5226 void *buff, u16 buff_size,
5227 enum i40e_admin_queue_opc opcode,
5228 struct i40e_asq_cmd_details *cmd_details)
5230 struct i40e_aq_desc desc;
5231 struct i40e_aqc_tx_sched_ind *cmd =
5232 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
5233 enum i40e_status_code status;
5234 bool cmd_param_flag = false;
5237 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
5238 case i40e_aqc_opc_configure_vsi_tc_bw:
5239 case i40e_aqc_opc_enable_switching_comp_ets:
5240 case i40e_aqc_opc_modify_switching_comp_ets:
5241 case i40e_aqc_opc_disable_switching_comp_ets:
5242 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
5243 case i40e_aqc_opc_configure_switching_comp_bw_config:
5244 cmd_param_flag = true;
5246 case i40e_aqc_opc_query_vsi_bw_config:
5247 case i40e_aqc_opc_query_vsi_ets_sla_config:
5248 case i40e_aqc_opc_query_switching_comp_ets_config:
5249 case i40e_aqc_opc_query_port_ets_config:
5250 case i40e_aqc_opc_query_switching_comp_bw_config:
5251 cmd_param_flag = false;
5254 return I40E_ERR_PARAM;
5257 i40e_fill_default_direct_cmd_desc(&desc, opcode);
5259 /* Indirect command */
5260 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5262 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5263 if (buff_size > I40E_AQ_LARGE_BUF)
5264 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5266 desc.datalen = CPU_TO_LE16(buff_size);
5268 cmd->vsi_seid = CPU_TO_LE16(seid);
5270 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5276 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5277 * @hw: pointer to the hw struct
5279 * @credit: BW limit credits (0 = disabled)
5280 * @max_credit: Max BW limit credits
5281 * @cmd_details: pointer to command details structure or NULL
5283 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5284 u16 seid, u16 credit, u8 max_credit,
5285 struct i40e_asq_cmd_details *cmd_details)
5287 struct i40e_aq_desc desc;
5288 struct i40e_aqc_configure_vsi_bw_limit *cmd =
5289 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5290 enum i40e_status_code status;
5292 i40e_fill_default_direct_cmd_desc(&desc,
5293 i40e_aqc_opc_configure_vsi_bw_limit);
5295 cmd->vsi_seid = CPU_TO_LE16(seid);
5296 cmd->credit = CPU_TO_LE16(credit);
5297 cmd->max_credit = max_credit;
5299 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5305 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5306 * @hw: pointer to the hw struct
5307 * @seid: switching component seid
5308 * @credit: BW limit credits (0 = disabled)
5309 * @max_bw: Max BW limit credits
5310 * @cmd_details: pointer to command details structure or NULL
5312 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5313 u16 seid, u16 credit, u8 max_bw,
5314 struct i40e_asq_cmd_details *cmd_details)
5316 struct i40e_aq_desc desc;
5317 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5318 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5319 enum i40e_status_code status;
5321 i40e_fill_default_direct_cmd_desc(&desc,
5322 i40e_aqc_opc_configure_switching_comp_bw_limit);
5324 cmd->seid = CPU_TO_LE16(seid);
5325 cmd->credit = CPU_TO_LE16(credit);
5326 cmd->max_bw = max_bw;
5328 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5334 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5335 * @hw: pointer to the hw struct
5337 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5338 * @cmd_details: pointer to command details structure or NULL
5340 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5342 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5343 struct i40e_asq_cmd_details *cmd_details)
5345 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5346 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5351 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5352 * @hw: pointer to the hw struct
5354 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5355 * @cmd_details: pointer to command details structure or NULL
5357 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5359 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5360 struct i40e_asq_cmd_details *cmd_details)
5362 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5363 i40e_aqc_opc_configure_vsi_tc_bw,
5368 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5369 * @hw: pointer to the hw struct
5370 * @seid: seid of the switching component connected to Physical Port
5371 * @ets_data: Buffer holding ETS parameters
5372 * @opcode: Tx scheduler AQ command opcode
5373 * @cmd_details: pointer to command details structure or NULL
5375 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5377 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5378 enum i40e_admin_queue_opc opcode,
5379 struct i40e_asq_cmd_details *cmd_details)
5381 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5382 sizeof(*ets_data), opcode, cmd_details);
5386 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5387 * @hw: pointer to the hw struct
5388 * @seid: seid of the switching component
5389 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5390 * @cmd_details: pointer to command details structure or NULL
5392 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5394 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5395 struct i40e_asq_cmd_details *cmd_details)
5397 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5398 i40e_aqc_opc_configure_switching_comp_bw_config,
5403 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5404 * @hw: pointer to the hw struct
5405 * @seid: seid of the switching component
5406 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5407 * @cmd_details: pointer to command details structure or NULL
5409 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5410 struct i40e_hw *hw, u16 seid,
5411 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5412 struct i40e_asq_cmd_details *cmd_details)
5414 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5415 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5420 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5421 * @hw: pointer to the hw struct
5422 * @seid: seid of the VSI
5423 * @bw_data: Buffer to hold VSI BW configuration
5424 * @cmd_details: pointer to command details structure or NULL
5426 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5428 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5429 struct i40e_asq_cmd_details *cmd_details)
5431 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5432 i40e_aqc_opc_query_vsi_bw_config,
5437 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5438 * @hw: pointer to the hw struct
5439 * @seid: seid of the VSI
5440 * @bw_data: Buffer to hold VSI BW configuration per TC
5441 * @cmd_details: pointer to command details structure or NULL
5443 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5445 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5446 struct i40e_asq_cmd_details *cmd_details)
5448 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5449 i40e_aqc_opc_query_vsi_ets_sla_config,
5454 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5455 * @hw: pointer to the hw struct
5456 * @seid: seid of the switching component
5457 * @bw_data: Buffer to hold switching component's per TC BW config
5458 * @cmd_details: pointer to command details structure or NULL
5460 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5462 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5463 struct i40e_asq_cmd_details *cmd_details)
5465 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5466 i40e_aqc_opc_query_switching_comp_ets_config,
5471 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5472 * @hw: pointer to the hw struct
5473 * @seid: seid of the VSI or switching component connected to Physical Port
5474 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5475 * @cmd_details: pointer to command details structure or NULL
5477 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5479 struct i40e_aqc_query_port_ets_config_resp *bw_data,
5480 struct i40e_asq_cmd_details *cmd_details)
5482 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5483 i40e_aqc_opc_query_port_ets_config,
5488 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5489 * @hw: pointer to the hw struct
5490 * @seid: seid of the switching component
5491 * @bw_data: Buffer to hold switching component's BW configuration
5492 * @cmd_details: pointer to command details structure or NULL
5494 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5496 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5497 struct i40e_asq_cmd_details *cmd_details)
5499 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5500 i40e_aqc_opc_query_switching_comp_bw_config,
5505 * i40e_validate_filter_settings
5506 * @hw: pointer to the hardware structure
5507 * @settings: Filter control settings
5509 * Check and validate the filter control settings passed.
5510 * The function checks for the valid filter/context sizes being
5511 * passed for FCoE and PE.
5513 * Returns I40E_SUCCESS if the values passed are valid and within
5514 * range else returns an error.
5516 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5517 struct i40e_filter_control_settings *settings)
5519 u32 fcoe_cntx_size, fcoe_filt_size;
5520 u32 pe_cntx_size, pe_filt_size;
5525 /* Validate FCoE settings passed */
5526 switch (settings->fcoe_filt_num) {
5527 case I40E_HASH_FILTER_SIZE_1K:
5528 case I40E_HASH_FILTER_SIZE_2K:
5529 case I40E_HASH_FILTER_SIZE_4K:
5530 case I40E_HASH_FILTER_SIZE_8K:
5531 case I40E_HASH_FILTER_SIZE_16K:
5532 case I40E_HASH_FILTER_SIZE_32K:
5533 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5534 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5537 return I40E_ERR_PARAM;
5540 switch (settings->fcoe_cntx_num) {
5541 case I40E_DMA_CNTX_SIZE_512:
5542 case I40E_DMA_CNTX_SIZE_1K:
5543 case I40E_DMA_CNTX_SIZE_2K:
5544 case I40E_DMA_CNTX_SIZE_4K:
5545 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5546 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5549 return I40E_ERR_PARAM;
5552 /* Validate PE settings passed */
5553 switch (settings->pe_filt_num) {
5554 case I40E_HASH_FILTER_SIZE_1K:
5555 case I40E_HASH_FILTER_SIZE_2K:
5556 case I40E_HASH_FILTER_SIZE_4K:
5557 case I40E_HASH_FILTER_SIZE_8K:
5558 case I40E_HASH_FILTER_SIZE_16K:
5559 case I40E_HASH_FILTER_SIZE_32K:
5560 case I40E_HASH_FILTER_SIZE_64K:
5561 case I40E_HASH_FILTER_SIZE_128K:
5562 case I40E_HASH_FILTER_SIZE_256K:
5563 case I40E_HASH_FILTER_SIZE_512K:
5564 case I40E_HASH_FILTER_SIZE_1M:
5565 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5566 pe_filt_size <<= (u32)settings->pe_filt_num;
5569 return I40E_ERR_PARAM;
5572 switch (settings->pe_cntx_num) {
5573 case I40E_DMA_CNTX_SIZE_512:
5574 case I40E_DMA_CNTX_SIZE_1K:
5575 case I40E_DMA_CNTX_SIZE_2K:
5576 case I40E_DMA_CNTX_SIZE_4K:
5577 case I40E_DMA_CNTX_SIZE_8K:
5578 case I40E_DMA_CNTX_SIZE_16K:
5579 case I40E_DMA_CNTX_SIZE_32K:
5580 case I40E_DMA_CNTX_SIZE_64K:
5581 case I40E_DMA_CNTX_SIZE_128K:
5582 case I40E_DMA_CNTX_SIZE_256K:
5583 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5584 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5587 return I40E_ERR_PARAM;
5590 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5591 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5592 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5593 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5594 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
5595 return I40E_ERR_INVALID_SIZE;
5597 return I40E_SUCCESS;
5601 * i40e_set_filter_control
5602 * @hw: pointer to the hardware structure
5603 * @settings: Filter control settings
5605 * Set the Queue Filters for PE/FCoE and enable filters required
5606 * for a single PF. It is expected that these settings are programmed
5607 * at the driver initialization time.
5609 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5610 struct i40e_filter_control_settings *settings)
5612 enum i40e_status_code ret = I40E_SUCCESS;
5613 u32 hash_lut_size = 0;
5617 return I40E_ERR_PARAM;
5619 /* Validate the input settings */
5620 ret = i40e_validate_filter_settings(hw, settings);
5624 /* Read the PF Queue Filter control register */
5625 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5627 /* Program required PE hash buckets for the PF */
5628 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5629 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5630 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5631 /* Program required PE contexts for the PF */
5632 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5633 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5634 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5636 /* Program required FCoE hash buckets for the PF */
5637 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5638 val |= ((u32)settings->fcoe_filt_num <<
5639 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5640 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5641 /* Program required FCoE DDP contexts for the PF */
5642 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5643 val |= ((u32)settings->fcoe_cntx_num <<
5644 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5645 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5647 /* Program Hash LUT size for the PF */
5648 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5649 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5651 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5652 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5654 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5655 if (settings->enable_fdir)
5656 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5657 if (settings->enable_ethtype)
5658 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5659 if (settings->enable_macvlan)
5660 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5662 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5664 return I40E_SUCCESS;
5668 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5669 * @hw: pointer to the hw struct
5670 * @mac_addr: MAC address to use in the filter
5671 * @ethtype: Ethertype to use in the filter
5672 * @flags: Flags that needs to be applied to the filter
5673 * @vsi_seid: seid of the control VSI
5674 * @queue: VSI queue number to send the packet to
5675 * @is_add: Add control packet filter if True else remove
5676 * @stats: Structure to hold information on control filter counts
5677 * @cmd_details: pointer to command details structure or NULL
5679 * This command will Add or Remove control packet filter for a control VSI.
5680 * In return it will update the total number of perfect filter count in
5683 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5684 u8 *mac_addr, u16 ethtype, u16 flags,
5685 u16 vsi_seid, u16 queue, bool is_add,
5686 struct i40e_control_filter_stats *stats,
5687 struct i40e_asq_cmd_details *cmd_details)
5689 struct i40e_aq_desc desc;
5690 struct i40e_aqc_add_remove_control_packet_filter *cmd =
5691 (struct i40e_aqc_add_remove_control_packet_filter *)
5693 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5694 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5696 enum i40e_status_code status;
5699 return I40E_ERR_PARAM;
5702 i40e_fill_default_direct_cmd_desc(&desc,
5703 i40e_aqc_opc_add_control_packet_filter);
5704 cmd->queue = CPU_TO_LE16(queue);
5706 i40e_fill_default_direct_cmd_desc(&desc,
5707 i40e_aqc_opc_remove_control_packet_filter);
5711 i40e_memcpy(cmd->mac, mac_addr, ETH_ALEN,
5712 I40E_NONDMA_TO_NONDMA);
5714 cmd->etype = CPU_TO_LE16(ethtype);
5715 cmd->flags = CPU_TO_LE16(flags);
5716 cmd->seid = CPU_TO_LE16(vsi_seid);
5718 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5720 if (!status && stats) {
5721 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5722 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5723 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5724 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5731 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5732 * @hw: pointer to the hw struct
5733 * @seid: VSI seid to add ethertype filter from
5735 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5738 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5739 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5740 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5741 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5742 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5743 enum i40e_status_code status;
5745 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5746 seid, 0, true, NULL,
5749 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5753 * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5754 * @filters: list of cloud filters
5755 * @filter_count: length of list
5757 * There's an issue in the device where the Geneve VNI layout needs
5758 * to be shifted 1 byte over from the VxLAN VNI
5760 STATIC void i40e_fix_up_geneve_vni(
5761 struct i40e_aqc_cloud_filters_element_data *filters,
5764 struct i40e_aqc_cloud_filters_element_data *f = filters;
5767 for (i = 0; i < filter_count; i++) {
5771 tnl_type = (LE16_TO_CPU(f[i].flags) &
5772 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5773 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5774 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5775 ti = LE32_TO_CPU(f[i].tenant_id);
5776 f[i].tenant_id = CPU_TO_LE32(ti << 8);
5782 * i40e_aq_add_cloud_filters
5783 * @hw: pointer to the hardware structure
5784 * @seid: VSI seid to add cloud filters from
5785 * @filters: Buffer which contains the filters to be added
5786 * @filter_count: number of filters contained in the buffer
5788 * Set the cloud filters for a given VSI. The contents of the
5789 * i40e_aqc_cloud_filters_element_data are filled
5790 * in by the caller of the function.
5793 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5795 struct i40e_aqc_cloud_filters_element_data *filters,
5798 struct i40e_aq_desc desc;
5799 struct i40e_aqc_add_remove_cloud_filters *cmd =
5800 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5801 enum i40e_status_code status;
5804 i40e_fill_default_direct_cmd_desc(&desc,
5805 i40e_aqc_opc_add_cloud_filters);
5807 buff_len = filter_count * sizeof(*filters);
5808 desc.datalen = CPU_TO_LE16(buff_len);
5809 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5810 cmd->num_filters = filter_count;
5811 cmd->seid = CPU_TO_LE16(seid);
5813 i40e_fix_up_geneve_vni(filters, filter_count);
5815 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5821 * i40e_aq_add_cloud_filters_bb
5822 * @hw: pointer to the hardware structure
5823 * @seid: VSI seid to add cloud filters from
5824 * @filters: Buffer which contains the filters in big buffer to be added
5825 * @filter_count: number of filters contained in the buffer
5827 * Set the cloud filters for a given VSI. The contents of the
5828 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5832 enum i40e_status_code
5833 i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5834 struct i40e_aqc_cloud_filters_element_bb *filters,
5837 struct i40e_aq_desc desc;
5838 struct i40e_aqc_add_remove_cloud_filters *cmd =
5839 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5840 enum i40e_status_code status;
5844 i40e_fill_default_direct_cmd_desc(&desc,
5845 i40e_aqc_opc_add_cloud_filters);
5847 buff_len = filter_count * sizeof(*filters);
5848 desc.datalen = CPU_TO_LE16(buff_len);
5849 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5850 cmd->num_filters = filter_count;
5851 cmd->seid = CPU_TO_LE16(seid);
5852 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5854 for (i = 0; i < filter_count; i++) {
5858 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5859 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5860 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5862 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5863 * one more byte further than normally used for Tenant ID in
5864 * other tunnel types.
5866 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5867 ti = LE32_TO_CPU(filters[i].element.tenant_id);
5868 filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5872 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5878 * i40e_aq_rem_cloud_filters
5879 * @hw: pointer to the hardware structure
5880 * @seid: VSI seid to remove cloud filters from
5881 * @filters: Buffer which contains the filters to be removed
5882 * @filter_count: number of filters contained in the buffer
5884 * Remove the cloud filters for a given VSI. The contents of the
5885 * i40e_aqc_cloud_filters_element_data are filled in by the caller
5889 enum i40e_status_code
5890 i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid,
5891 struct i40e_aqc_cloud_filters_element_data *filters,
5894 struct i40e_aq_desc desc;
5895 struct i40e_aqc_add_remove_cloud_filters *cmd =
5896 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5897 enum i40e_status_code status;
5900 i40e_fill_default_direct_cmd_desc(&desc,
5901 i40e_aqc_opc_remove_cloud_filters);
5903 buff_len = filter_count * sizeof(*filters);
5904 desc.datalen = CPU_TO_LE16(buff_len);
5905 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5906 cmd->num_filters = filter_count;
5907 cmd->seid = CPU_TO_LE16(seid);
5909 i40e_fix_up_geneve_vni(filters, filter_count);
5911 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5917 * i40e_aq_rem_cloud_filters_bb
5918 * @hw: pointer to the hardware structure
5919 * @seid: VSI seid to remove cloud filters from
5920 * @filters: Buffer which contains the filters in big buffer to be removed
5921 * @filter_count: number of filters contained in the buffer
5923 * Remove the big buffer cloud filters for a given VSI. The contents of the
5924 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5928 enum i40e_status_code
5929 i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5930 struct i40e_aqc_cloud_filters_element_bb *filters,
5933 struct i40e_aq_desc desc;
5934 struct i40e_aqc_add_remove_cloud_filters *cmd =
5935 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5936 enum i40e_status_code status;
5940 i40e_fill_default_direct_cmd_desc(&desc,
5941 i40e_aqc_opc_remove_cloud_filters);
5943 buff_len = filter_count * sizeof(*filters);
5944 desc.datalen = CPU_TO_LE16(buff_len);
5945 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5946 cmd->num_filters = filter_count;
5947 cmd->seid = CPU_TO_LE16(seid);
5948 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5950 for (i = 0; i < filter_count; i++) {
5954 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5955 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5956 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5958 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5959 * one more byte further than normally used for Tenant ID in
5960 * other tunnel types.
5962 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5963 ti = LE32_TO_CPU(filters[i].element.tenant_id);
5964 filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5968 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5974 * i40e_aq_replace_cloud_filters - Replace cloud filter command
5975 * @hw: pointer to the hw struct
5976 * @filters: pointer to the i40e_aqc_replace_cloud_filter_cmd struct
5977 * @cmd_buf: pointer to the i40e_aqc_replace_cloud_filter_cmd_buf struct
5981 i40e_status_code i40e_aq_replace_cloud_filters(struct i40e_hw *hw,
5982 struct i40e_aqc_replace_cloud_filters_cmd *filters,
5983 struct i40e_aqc_replace_cloud_filters_cmd_buf *cmd_buf)
5985 struct i40e_aq_desc desc;
5986 struct i40e_aqc_replace_cloud_filters_cmd *cmd =
5987 (struct i40e_aqc_replace_cloud_filters_cmd *)&desc.params.raw;
5988 enum i40e_status_code status = I40E_SUCCESS;
5991 /* X722 doesn't support this command */
5992 if (hw->mac.type == I40E_MAC_X722)
5993 return I40E_ERR_DEVICE_NOT_SUPPORTED;
5995 /* need FW version greater than 6.00 */
5996 if (hw->aq.fw_maj_ver < 6)
5997 return I40E_NOT_SUPPORTED;
5999 i40e_fill_default_direct_cmd_desc(&desc,
6000 i40e_aqc_opc_replace_cloud_filters);
6002 desc.datalen = CPU_TO_LE16(32);
6003 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
6004 cmd->old_filter_type = filters->old_filter_type;
6005 cmd->new_filter_type = filters->new_filter_type;
6006 cmd->valid_flags = filters->valid_flags;
6007 cmd->tr_bit = filters->tr_bit;
6008 cmd->tr_bit2 = filters->tr_bit2;
6010 status = i40e_asq_send_command(hw, &desc, cmd_buf,
6011 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf), NULL);
6013 /* for get cloud filters command */
6014 for (i = 0; i < 32; i += 4) {
6015 cmd_buf->filters[i / 4].filter_type = cmd_buf->data[i];
6016 cmd_buf->filters[i / 4].input[0] = cmd_buf->data[i + 1];
6017 cmd_buf->filters[i / 4].input[1] = cmd_buf->data[i + 2];
6018 cmd_buf->filters[i / 4].input[2] = cmd_buf->data[i + 3];
6026 * i40e_aq_alternate_write
6027 * @hw: pointer to the hardware structure
6028 * @reg_addr0: address of first dword to be read
6029 * @reg_val0: value to be written under 'reg_addr0'
6030 * @reg_addr1: address of second dword to be read
6031 * @reg_val1: value to be written under 'reg_addr1'
6033 * Write one or two dwords to alternate structure. Fields are indicated
6034 * by 'reg_addr0' and 'reg_addr1' register numbers.
6037 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
6038 u32 reg_addr0, u32 reg_val0,
6039 u32 reg_addr1, u32 reg_val1)
6041 struct i40e_aq_desc desc;
6042 struct i40e_aqc_alternate_write *cmd_resp =
6043 (struct i40e_aqc_alternate_write *)&desc.params.raw;
6044 enum i40e_status_code status;
6046 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
6047 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
6048 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
6049 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
6050 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
6052 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6058 * i40e_aq_alternate_write_indirect
6059 * @hw: pointer to the hardware structure
6060 * @addr: address of a first register to be modified
6061 * @dw_count: number of alternate structure fields to write
6062 * @buffer: pointer to the command buffer
6064 * Write 'dw_count' dwords from 'buffer' to alternate structure
6065 * starting at 'addr'.
6068 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
6069 u32 addr, u32 dw_count, void *buffer)
6071 struct i40e_aq_desc desc;
6072 struct i40e_aqc_alternate_ind_write *cmd_resp =
6073 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
6074 enum i40e_status_code status;
6077 return I40E_ERR_PARAM;
6079 /* Indirect command */
6080 i40e_fill_default_direct_cmd_desc(&desc,
6081 i40e_aqc_opc_alternate_write_indirect);
6083 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6084 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6085 if (dw_count > (I40E_AQ_LARGE_BUF/4))
6086 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6088 cmd_resp->address = CPU_TO_LE32(addr);
6089 cmd_resp->length = CPU_TO_LE32(dw_count);
6091 status = i40e_asq_send_command(hw, &desc, buffer,
6092 I40E_LO_DWORD(4*dw_count), NULL);
6098 * i40e_aq_alternate_read
6099 * @hw: pointer to the hardware structure
6100 * @reg_addr0: address of first dword to be read
6101 * @reg_val0: pointer for data read from 'reg_addr0'
6102 * @reg_addr1: address of second dword to be read
6103 * @reg_val1: pointer for data read from 'reg_addr1'
6105 * Read one or two dwords from alternate structure. Fields are indicated
6106 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
6107 * is not passed then only register at 'reg_addr0' is read.
6110 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
6111 u32 reg_addr0, u32 *reg_val0,
6112 u32 reg_addr1, u32 *reg_val1)
6114 struct i40e_aq_desc desc;
6115 struct i40e_aqc_alternate_write *cmd_resp =
6116 (struct i40e_aqc_alternate_write *)&desc.params.raw;
6117 enum i40e_status_code status;
6119 if (reg_val0 == NULL)
6120 return I40E_ERR_PARAM;
6122 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
6123 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
6124 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
6126 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6128 if (status == I40E_SUCCESS) {
6129 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
6131 if (reg_val1 != NULL)
6132 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
6139 * i40e_aq_alternate_read_indirect
6140 * @hw: pointer to the hardware structure
6141 * @addr: address of the alternate structure field
6142 * @dw_count: number of alternate structure fields to read
6143 * @buffer: pointer to the command buffer
6145 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
6146 * place them in 'buffer'. The buffer should be allocated by caller.
6149 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
6150 u32 addr, u32 dw_count, void *buffer)
6152 struct i40e_aq_desc desc;
6153 struct i40e_aqc_alternate_ind_write *cmd_resp =
6154 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
6155 enum i40e_status_code status;
6158 return I40E_ERR_PARAM;
6160 /* Indirect command */
6161 i40e_fill_default_direct_cmd_desc(&desc,
6162 i40e_aqc_opc_alternate_read_indirect);
6164 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6165 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6166 if (dw_count > (I40E_AQ_LARGE_BUF/4))
6167 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6169 cmd_resp->address = CPU_TO_LE32(addr);
6170 cmd_resp->length = CPU_TO_LE32(dw_count);
6172 status = i40e_asq_send_command(hw, &desc, buffer,
6173 I40E_LO_DWORD(4*dw_count), NULL);
6179 * i40e_aq_alternate_clear
6180 * @hw: pointer to the HW structure.
6182 * Clear the alternate structures of the port from which the function
6186 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
6188 struct i40e_aq_desc desc;
6189 enum i40e_status_code status;
6191 i40e_fill_default_direct_cmd_desc(&desc,
6192 i40e_aqc_opc_alternate_clear_port);
6194 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6200 * i40e_aq_alternate_write_done
6201 * @hw: pointer to the HW structure.
6202 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
6203 * @reset_needed: indicates the SW should trigger GLOBAL reset
6205 * Indicates to the FW that alternate structures have been changed.
6208 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
6209 u8 bios_mode, bool *reset_needed)
6211 struct i40e_aq_desc desc;
6212 struct i40e_aqc_alternate_write_done *cmd =
6213 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6214 enum i40e_status_code status;
6216 if (reset_needed == NULL)
6217 return I40E_ERR_PARAM;
6219 i40e_fill_default_direct_cmd_desc(&desc,
6220 i40e_aqc_opc_alternate_write_done);
6222 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
6224 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6225 if (!status && reset_needed)
6226 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
6227 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
6233 * i40e_aq_set_oem_mode
6234 * @hw: pointer to the HW structure.
6235 * @oem_mode: the OEM mode to be used
6237 * Sets the device to a specific operating mode. Currently the only supported
6238 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
6241 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
6244 struct i40e_aq_desc desc;
6245 struct i40e_aqc_alternate_write_done *cmd =
6246 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6247 enum i40e_status_code status;
6249 i40e_fill_default_direct_cmd_desc(&desc,
6250 i40e_aqc_opc_alternate_set_mode);
6252 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
6254 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6260 * i40e_aq_resume_port_tx
6261 * @hw: pointer to the hardware structure
6262 * @cmd_details: pointer to command details structure or NULL
6264 * Resume port's Tx traffic
6266 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
6267 struct i40e_asq_cmd_details *cmd_details)
6269 struct i40e_aq_desc desc;
6270 enum i40e_status_code status;
6272 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
6274 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6280 * i40e_set_pci_config_data - store PCI bus info
6281 * @hw: pointer to hardware structure
6282 * @link_status: the link status word from PCI config space
6284 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
6286 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
6288 hw->bus.type = i40e_bus_type_pci_express;
6290 switch (link_status & I40E_PCI_LINK_WIDTH) {
6291 case I40E_PCI_LINK_WIDTH_1:
6292 hw->bus.width = i40e_bus_width_pcie_x1;
6294 case I40E_PCI_LINK_WIDTH_2:
6295 hw->bus.width = i40e_bus_width_pcie_x2;
6297 case I40E_PCI_LINK_WIDTH_4:
6298 hw->bus.width = i40e_bus_width_pcie_x4;
6300 case I40E_PCI_LINK_WIDTH_8:
6301 hw->bus.width = i40e_bus_width_pcie_x8;
6304 hw->bus.width = i40e_bus_width_unknown;
6308 switch (link_status & I40E_PCI_LINK_SPEED) {
6309 case I40E_PCI_LINK_SPEED_2500:
6310 hw->bus.speed = i40e_bus_speed_2500;
6312 case I40E_PCI_LINK_SPEED_5000:
6313 hw->bus.speed = i40e_bus_speed_5000;
6315 case I40E_PCI_LINK_SPEED_8000:
6316 hw->bus.speed = i40e_bus_speed_8000;
6319 hw->bus.speed = i40e_bus_speed_unknown;
6325 * i40e_aq_debug_dump
6326 * @hw: pointer to the hardware structure
6327 * @cluster_id: specific cluster to dump
6328 * @table_id: table id within cluster
6329 * @start_index: index of line in the block to read
6330 * @buff_size: dump buffer size
6331 * @buff: dump buffer
6332 * @ret_buff_size: actual buffer size returned
6333 * @ret_next_table: next block to read
6334 * @ret_next_index: next index to read
6335 * @cmd_details: pointer to command details structure or NULL
6337 * Dump internal FW/HW data for debug purposes.
6340 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
6341 u8 table_id, u32 start_index, u16 buff_size,
6342 void *buff, u16 *ret_buff_size,
6343 u8 *ret_next_table, u32 *ret_next_index,
6344 struct i40e_asq_cmd_details *cmd_details)
6346 struct i40e_aq_desc desc;
6347 struct i40e_aqc_debug_dump_internals *cmd =
6348 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6349 struct i40e_aqc_debug_dump_internals *resp =
6350 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6351 enum i40e_status_code status;
6353 if (buff_size == 0 || !buff)
6354 return I40E_ERR_PARAM;
6356 i40e_fill_default_direct_cmd_desc(&desc,
6357 i40e_aqc_opc_debug_dump_internals);
6358 /* Indirect Command */
6359 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6360 if (buff_size > I40E_AQ_LARGE_BUF)
6361 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6363 cmd->cluster_id = cluster_id;
6364 cmd->table_id = table_id;
6365 cmd->idx = CPU_TO_LE32(start_index);
6367 desc.datalen = CPU_TO_LE16(buff_size);
6369 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
6371 if (ret_buff_size != NULL)
6372 *ret_buff_size = LE16_TO_CPU(desc.datalen);
6373 if (ret_next_table != NULL)
6374 *ret_next_table = resp->table_id;
6375 if (ret_next_index != NULL)
6376 *ret_next_index = LE32_TO_CPU(resp->idx);
6383 * i40e_read_bw_from_alt_ram
6384 * @hw: pointer to the hardware structure
6385 * @max_bw: pointer for max_bw read
6386 * @min_bw: pointer for min_bw read
6387 * @min_valid: pointer for bool that is true if min_bw is a valid value
6388 * @max_valid: pointer for bool that is true if max_bw is a valid value
6390 * Read bw from the alternate ram for the given pf
6392 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
6393 u32 *max_bw, u32 *min_bw,
6394 bool *min_valid, bool *max_valid)
6396 enum i40e_status_code status;
6397 u32 max_bw_addr, min_bw_addr;
6399 /* Calculate the address of the min/max bw registers */
6400 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6401 I40E_ALT_STRUCT_MAX_BW_OFFSET +
6402 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6403 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6404 I40E_ALT_STRUCT_MIN_BW_OFFSET +
6405 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6407 /* Read the bandwidths from alt ram */
6408 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
6409 min_bw_addr, min_bw);
6411 if (*min_bw & I40E_ALT_BW_VALID_MASK)
6416 if (*max_bw & I40E_ALT_BW_VALID_MASK)
6425 * i40e_aq_configure_partition_bw
6426 * @hw: pointer to the hardware structure
6427 * @bw_data: Buffer holding valid pfs and bw limits
6428 * @cmd_details: pointer to command details
6430 * Configure partitions guaranteed/max bw
6432 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6433 struct i40e_aqc_configure_partition_bw_data *bw_data,
6434 struct i40e_asq_cmd_details *cmd_details)
6436 enum i40e_status_code status;
6437 struct i40e_aq_desc desc;
6438 u16 bwd_size = sizeof(*bw_data);
6440 i40e_fill_default_direct_cmd_desc(&desc,
6441 i40e_aqc_opc_configure_partition_bw);
6443 /* Indirect command */
6444 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6445 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6447 desc.datalen = CPU_TO_LE16(bwd_size);
6449 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6455 * i40e_read_phy_register_clause22
6456 * @hw: pointer to the HW structure
6457 * @reg: register address in the page
6458 * @phy_addr: PHY address on MDIO interface
6459 * @value: PHY register value
6461 * Reads specified PHY register value
6463 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
6464 u16 reg, u8 phy_addr, u16 *value)
6466 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6467 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6471 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6472 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6473 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
6474 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6475 (I40E_GLGEN_MSCA_MDICMD_MASK);
6476 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6478 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6479 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6480 status = I40E_SUCCESS;
6483 i40e_usec_delay(10);
6488 i40e_debug(hw, I40E_DEBUG_PHY,
6489 "PHY: Can't write command to external PHY.\n");
6491 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6492 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6493 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6500 * i40e_write_phy_register_clause22
6501 * @hw: pointer to the HW structure
6502 * @reg: register address in the page
6503 * @phy_addr: PHY address on MDIO interface
6504 * @value: PHY register value
6506 * Writes specified PHY register value
6508 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6509 u16 reg, u8 phy_addr, u16 value)
6511 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6512 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6516 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6517 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6519 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6520 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6521 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6522 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6523 (I40E_GLGEN_MSCA_MDICMD_MASK);
6525 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6527 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6528 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6529 status = I40E_SUCCESS;
6532 i40e_usec_delay(10);
6540 * i40e_read_phy_register_clause45
6541 * @hw: pointer to the HW structure
6542 * @page: registers page number
6543 * @reg: register address in the page
6544 * @phy_addr: PHY address on MDIO interface
6545 * @value: PHY register value
6547 * Reads specified PHY register value
6549 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6550 u8 page, u16 reg, u8 phy_addr, u16 *value)
6552 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6555 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6557 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6558 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6559 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6560 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6561 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6562 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6563 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6564 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6566 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6567 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6568 status = I40E_SUCCESS;
6571 i40e_usec_delay(10);
6576 i40e_debug(hw, I40E_DEBUG_PHY,
6577 "PHY: Can't write command to external PHY.\n");
6581 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6582 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6583 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6584 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6585 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6586 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6587 status = I40E_ERR_TIMEOUT;
6589 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6591 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6592 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6593 status = I40E_SUCCESS;
6596 i40e_usec_delay(10);
6601 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6602 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6603 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6605 i40e_debug(hw, I40E_DEBUG_PHY,
6606 "PHY: Can't read register value from external PHY.\n");
6614 * i40e_write_phy_register_clause45
6615 * @hw: pointer to the HW structure
6616 * @page: registers page number
6617 * @reg: register address in the page
6618 * @phy_addr: PHY address on MDIO interface
6619 * @value: PHY register value
6621 * Writes value to specified PHY register
6623 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6624 u8 page, u16 reg, u8 phy_addr, u16 value)
6626 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6629 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6631 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6632 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6633 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6634 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6635 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6636 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6637 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6638 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6640 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6641 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6642 status = I40E_SUCCESS;
6645 i40e_usec_delay(10);
6649 i40e_debug(hw, I40E_DEBUG_PHY,
6650 "PHY: Can't write command to external PHY.\n");
6654 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6655 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6657 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6658 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6659 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6660 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6661 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6662 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6663 status = I40E_ERR_TIMEOUT;
6665 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6667 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6668 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6669 status = I40E_SUCCESS;
6672 i40e_usec_delay(10);
6681 * i40e_write_phy_register
6682 * @hw: pointer to the HW structure
6683 * @page: registers page number
6684 * @reg: register address in the page
6685 * @phy_addr: PHY address on MDIO interface
6686 * @value: PHY register value
6688 * Writes value to specified PHY register
6690 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6691 u8 page, u16 reg, u8 phy_addr, u16 value)
6693 enum i40e_status_code status;
6695 switch (hw->device_id) {
6696 case I40E_DEV_ID_1G_BASE_T_X722:
6697 status = i40e_write_phy_register_clause22(hw,
6698 reg, phy_addr, value);
6700 case I40E_DEV_ID_10G_BASE_T:
6701 case I40E_DEV_ID_10G_BASE_T4:
6702 case I40E_DEV_ID_10G_BASE_T_BC:
6703 case I40E_DEV_ID_10G_BASE_T_X722:
6704 case I40E_DEV_ID_25G_B:
6705 case I40E_DEV_ID_25G_SFP28:
6706 status = i40e_write_phy_register_clause45(hw,
6707 page, reg, phy_addr, value);
6710 status = I40E_ERR_UNKNOWN_PHY;
6718 * i40e_read_phy_register
6719 * @hw: pointer to the HW structure
6720 * @page: registers page number
6721 * @reg: register address in the page
6722 * @phy_addr: PHY address on MDIO interface
6723 * @value: PHY register value
6725 * Reads specified PHY register value
6727 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6728 u8 page, u16 reg, u8 phy_addr, u16 *value)
6730 enum i40e_status_code status;
6732 switch (hw->device_id) {
6733 case I40E_DEV_ID_1G_BASE_T_X722:
6734 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6737 case I40E_DEV_ID_10G_BASE_T:
6738 case I40E_DEV_ID_10G_BASE_T4:
6739 case I40E_DEV_ID_10G_BASE_T_X722:
6740 case I40E_DEV_ID_25G_B:
6741 case I40E_DEV_ID_25G_SFP28:
6742 status = i40e_read_phy_register_clause45(hw, page, reg,
6746 status = I40E_ERR_UNKNOWN_PHY;
6754 * i40e_get_phy_address
6755 * @hw: pointer to the HW structure
6756 * @dev_num: PHY port num that address we want
6758 * Gets PHY address for current port
6760 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6762 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6763 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6765 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6769 * i40e_blink_phy_led
6770 * @hw: pointer to the HW structure
6771 * @time: time how long led will blinks in secs
6772 * @interval: gap between LED on and off in msecs
6774 * Blinks PHY link LED
6776 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6777 u32 time, u32 interval)
6779 enum i40e_status_code status = I40E_SUCCESS;
6784 u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6788 i = rd32(hw, I40E_PFGEN_PORTNUM);
6789 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6790 phy_addr = i40e_get_phy_address(hw, port_num);
6792 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6794 status = i40e_read_phy_register_clause45(hw,
6795 I40E_PHY_COM_REG_PAGE,
6799 goto phy_blinking_end;
6801 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6803 status = i40e_write_phy_register_clause45(hw,
6804 I40E_PHY_COM_REG_PAGE,
6808 goto phy_blinking_end;
6813 if (time > 0 && interval > 0) {
6814 for (i = 0; i < time * 1000; i += interval) {
6815 status = i40e_read_phy_register_clause45(hw,
6816 I40E_PHY_COM_REG_PAGE,
6817 led_addr, phy_addr, &led_reg);
6819 goto restore_config;
6820 if (led_reg & I40E_PHY_LED_MANUAL_ON)
6823 led_reg = I40E_PHY_LED_MANUAL_ON;
6824 status = i40e_write_phy_register_clause45(hw,
6825 I40E_PHY_COM_REG_PAGE,
6826 led_addr, phy_addr, led_reg);
6828 goto restore_config;
6829 i40e_msec_delay(interval);
6834 status = i40e_write_phy_register_clause45(hw,
6835 I40E_PHY_COM_REG_PAGE,
6836 led_addr, phy_addr, led_ctl);
6843 * i40e_led_get_reg - read LED register
6844 * @hw: pointer to the HW structure
6845 * @led_addr: LED register address
6846 * @reg_val: read register value
6848 static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr,
6851 enum i40e_status_code status;
6855 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6856 status = i40e_aq_get_phy_register(hw,
6857 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6858 I40E_PHY_COM_REG_PAGE, true,
6859 I40E_PHY_LED_PROV_REG_1,
6862 phy_addr = i40e_get_phy_address(hw, hw->port);
6863 status = i40e_read_phy_register_clause45(hw,
6864 I40E_PHY_COM_REG_PAGE,
6872 * i40e_led_set_reg - write LED register
6873 * @hw: pointer to the HW structure
6874 * @led_addr: LED register address
6875 * @reg_val: register value to write
6877 static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr,
6880 enum i40e_status_code status;
6883 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6884 status = i40e_aq_set_phy_register(hw,
6885 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6886 I40E_PHY_COM_REG_PAGE, true,
6887 I40E_PHY_LED_PROV_REG_1,
6890 phy_addr = i40e_get_phy_address(hw, hw->port);
6891 status = i40e_write_phy_register_clause45(hw,
6892 I40E_PHY_COM_REG_PAGE,
6901 * i40e_led_get_phy - return current on/off mode
6902 * @hw: pointer to the hw struct
6903 * @led_addr: address of led register to use
6904 * @val: original value of register to use
6907 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6910 enum i40e_status_code status = I40E_SUCCESS;
6917 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6918 status = i40e_aq_get_phy_register(hw,
6919 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6920 I40E_PHY_COM_REG_PAGE, true,
6921 I40E_PHY_LED_PROV_REG_1,
6923 if (status == I40E_SUCCESS)
6924 *val = (u16)reg_val_aq;
6927 temp_addr = I40E_PHY_LED_PROV_REG_1;
6928 phy_addr = i40e_get_phy_address(hw, hw->port);
6929 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6931 status = i40e_read_phy_register_clause45(hw,
6932 I40E_PHY_COM_REG_PAGE,
6933 temp_addr, phy_addr,
6938 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6939 *led_addr = temp_addr;
6948 * @hw: pointer to the HW structure
6949 * @on: true or false
6950 * @led_addr: address of led register to use
6951 * @mode: original val plus bit for set or ignore
6953 * Set led's on or off when controlled by the PHY
6956 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6957 u16 led_addr, u32 mode)
6959 enum i40e_status_code status = I40E_SUCCESS;
6963 status = i40e_led_get_reg(hw, led_addr, &led_reg);
6967 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6969 status = i40e_led_set_reg(hw, led_addr, led_reg);
6973 status = i40e_led_get_reg(hw, led_addr, &led_reg);
6975 goto restore_config;
6977 led_reg = I40E_PHY_LED_MANUAL_ON;
6980 status = i40e_led_set_reg(hw, led_addr, led_reg);
6982 goto restore_config;
6983 if (mode & I40E_PHY_LED_MODE_ORIG) {
6984 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6985 status = i40e_led_set_reg(hw, led_addr, led_ctl);
6990 status = i40e_led_set_reg(hw, led_addr, led_ctl);
6993 #endif /* PF_DRIVER */
6996 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6997 * @hw: pointer to the hw struct
6998 * @reg_addr: register address
6999 * @reg_val: ptr to register value
7000 * @cmd_details: pointer to command details structure or NULL
7002 * Use the firmware to read the Rx control register,
7003 * especially useful if the Rx unit is under heavy pressure
7005 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
7006 u32 reg_addr, u32 *reg_val,
7007 struct i40e_asq_cmd_details *cmd_details)
7009 struct i40e_aq_desc desc;
7010 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
7011 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
7012 enum i40e_status_code status;
7014 if (reg_val == NULL)
7015 return I40E_ERR_PARAM;
7017 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
7019 cmd_resp->address = CPU_TO_LE32(reg_addr);
7021 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7023 if (status == I40E_SUCCESS)
7024 *reg_val = LE32_TO_CPU(cmd_resp->value);
7030 * i40e_read_rx_ctl - read from an Rx control register
7031 * @hw: pointer to the hw struct
7032 * @reg_addr: register address
7034 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
7036 enum i40e_status_code status = I40E_SUCCESS;
7041 use_register = (((hw->aq.api_maj_ver == 1) &&
7042 (hw->aq.api_min_ver < 5)) ||
7043 (hw->mac.type == I40E_MAC_X722));
7044 if (!use_register) {
7046 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
7047 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
7054 /* if the AQ access failed, try the old-fashioned way */
7055 if (status || use_register)
7056 val = rd32(hw, reg_addr);
7062 * i40e_aq_rx_ctl_write_register
7063 * @hw: pointer to the hw struct
7064 * @reg_addr: register address
7065 * @reg_val: register value
7066 * @cmd_details: pointer to command details structure or NULL
7068 * Use the firmware to write to an Rx control register,
7069 * especially useful if the Rx unit is under heavy pressure
7071 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
7072 u32 reg_addr, u32 reg_val,
7073 struct i40e_asq_cmd_details *cmd_details)
7075 struct i40e_aq_desc desc;
7076 struct i40e_aqc_rx_ctl_reg_read_write *cmd =
7077 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
7078 enum i40e_status_code status;
7080 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
7082 cmd->address = CPU_TO_LE32(reg_addr);
7083 cmd->value = CPU_TO_LE32(reg_val);
7085 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7091 * i40e_write_rx_ctl - write to an Rx control register
7092 * @hw: pointer to the hw struct
7093 * @reg_addr: register address
7094 * @reg_val: register value
7096 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
7098 enum i40e_status_code status = I40E_SUCCESS;
7102 use_register = (((hw->aq.api_maj_ver == 1) &&
7103 (hw->aq.api_min_ver < 5)) ||
7104 (hw->mac.type == I40E_MAC_X722));
7105 if (!use_register) {
7107 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
7109 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
7116 /* if the AQ access failed, try the old-fashioned way */
7117 if (status || use_register)
7118 wr32(hw, reg_addr, reg_val);
7123 * i40e_aq_set_phy_register
7124 * @hw: pointer to the hw struct
7125 * @phy_select: select which phy should be accessed
7126 * @dev_addr: PHY device address
7127 * @page_change: enable auto page change
7128 * @reg_addr: PHY register address
7129 * @reg_val: new register value
7130 * @cmd_details: pointer to command details structure or NULL
7132 * Write the external PHY register.
7134 enum i40e_status_code i40e_aq_set_phy_register(struct i40e_hw *hw,
7135 u8 phy_select, u8 dev_addr, bool page_change,
7136 u32 reg_addr, u32 reg_val,
7137 struct i40e_asq_cmd_details *cmd_details)
7139 struct i40e_aq_desc desc;
7140 struct i40e_aqc_phy_register_access *cmd =
7141 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7142 enum i40e_status_code status;
7144 i40e_fill_default_direct_cmd_desc(&desc,
7145 i40e_aqc_opc_set_phy_register);
7147 cmd->phy_interface = phy_select;
7148 cmd->dev_addres = dev_addr;
7149 cmd->reg_address = CPU_TO_LE32(reg_addr);
7150 cmd->reg_value = CPU_TO_LE32(reg_val);
7153 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
7155 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7161 * i40e_aq_get_phy_register
7162 * @hw: pointer to the hw struct
7163 * @phy_select: select which phy should be accessed
7164 * @dev_addr: PHY device address
7165 * @page_change: enable auto page change
7166 * @reg_addr: PHY register address
7167 * @reg_val: read register value
7168 * @cmd_details: pointer to command details structure or NULL
7170 * Read the external PHY register.
7172 enum i40e_status_code i40e_aq_get_phy_register(struct i40e_hw *hw,
7173 u8 phy_select, u8 dev_addr, bool page_change,
7174 u32 reg_addr, u32 *reg_val,
7175 struct i40e_asq_cmd_details *cmd_details)
7177 struct i40e_aq_desc desc;
7178 struct i40e_aqc_phy_register_access *cmd =
7179 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7180 enum i40e_status_code status;
7182 i40e_fill_default_direct_cmd_desc(&desc,
7183 i40e_aqc_opc_get_phy_register);
7185 cmd->phy_interface = phy_select;
7186 cmd->dev_addres = dev_addr;
7187 cmd->reg_address = CPU_TO_LE32(reg_addr);
7190 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
7192 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7194 *reg_val = LE32_TO_CPU(cmd->reg_value);
7199 #endif /* PF_DRIVER */
7203 * i40e_aq_send_msg_to_pf
7204 * @hw: pointer to the hardware structure
7205 * @v_opcode: opcodes for VF-PF communication
7206 * @v_retval: return error code
7207 * @msg: pointer to the msg buffer
7208 * @msglen: msg length
7209 * @cmd_details: pointer to command details
7211 * Send message to PF driver using admin queue. By default, this message
7212 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
7213 * completion before returning.
7215 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
7216 enum virtchnl_ops v_opcode,
7217 enum i40e_status_code v_retval,
7218 u8 *msg, u16 msglen,
7219 struct i40e_asq_cmd_details *cmd_details)
7221 struct i40e_aq_desc desc;
7222 struct i40e_asq_cmd_details details;
7223 enum i40e_status_code status;
7225 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
7226 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
7227 desc.cookie_high = CPU_TO_LE32(v_opcode);
7228 desc.cookie_low = CPU_TO_LE32(v_retval);
7230 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
7231 | I40E_AQ_FLAG_RD));
7232 if (msglen > I40E_AQ_LARGE_BUF)
7233 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7234 desc.datalen = CPU_TO_LE16(msglen);
7237 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
7238 details.async = true;
7239 cmd_details = &details;
7241 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
7242 msglen, cmd_details);
7247 * i40e_vf_parse_hw_config
7248 * @hw: pointer to the hardware structure
7249 * @msg: pointer to the virtual channel VF resource structure
7251 * Given a VF resource message from the PF, populate the hw struct
7252 * with appropriate information.
7254 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
7255 struct virtchnl_vf_resource *msg)
7257 struct virtchnl_vsi_resource *vsi_res;
7260 vsi_res = &msg->vsi_res[0];
7262 hw->dev_caps.num_vsis = msg->num_vsis;
7263 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
7264 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
7265 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
7266 hw->dev_caps.dcb = msg->vf_cap_flags &
7267 VIRTCHNL_VF_OFFLOAD_L2;
7268 hw->dev_caps.iwarp = (msg->vf_cap_flags &
7269 VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
7270 for (i = 0; i < msg->num_vsis; i++) {
7271 if (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) {
7272 i40e_memcpy(hw->mac.perm_addr,
7273 vsi_res->default_mac_addr,
7275 I40E_NONDMA_TO_NONDMA);
7276 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
7278 I40E_NONDMA_TO_NONDMA);
7286 * @hw: pointer to the hardware structure
7288 * Send a VF_RESET message to the PF. Does not wait for response from PF
7289 * as none will be forthcoming. Immediately after calling this function,
7290 * the admin queue should be shut down and (optionally) reinitialized.
7292 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
7294 return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF,
7295 I40E_SUCCESS, NULL, 0, NULL);
7297 #endif /* VF_DRIVER */
7300 * i40e_aq_set_arp_proxy_config
7301 * @hw: pointer to the HW structure
7302 * @proxy_config: pointer to proxy config command table struct
7303 * @cmd_details: pointer to command details
7305 * Set ARP offload parameters from pre-populated
7306 * i40e_aqc_arp_proxy_data struct
7308 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
7309 struct i40e_aqc_arp_proxy_data *proxy_config,
7310 struct i40e_asq_cmd_details *cmd_details)
7312 struct i40e_aq_desc desc;
7313 enum i40e_status_code status;
7316 return I40E_ERR_PARAM;
7318 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
7320 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7321 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7322 desc.params.external.addr_high =
7323 CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
7324 desc.params.external.addr_low =
7325 CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
7326 desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_arp_proxy_data));
7328 status = i40e_asq_send_command(hw, &desc, proxy_config,
7329 sizeof(struct i40e_aqc_arp_proxy_data),
7336 * i40e_aq_opc_set_ns_proxy_table_entry
7337 * @hw: pointer to the HW structure
7338 * @ns_proxy_table_entry: pointer to NS table entry command struct
7339 * @cmd_details: pointer to command details
7341 * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
7342 * from pre-populated i40e_aqc_ns_proxy_data struct
7344 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
7345 struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
7346 struct i40e_asq_cmd_details *cmd_details)
7348 struct i40e_aq_desc desc;
7349 enum i40e_status_code status;
7351 if (!ns_proxy_table_entry)
7352 return I40E_ERR_PARAM;
7354 i40e_fill_default_direct_cmd_desc(&desc,
7355 i40e_aqc_opc_set_ns_proxy_table_entry);
7357 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7358 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7359 desc.params.external.addr_high =
7360 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
7361 desc.params.external.addr_low =
7362 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
7363 desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_ns_proxy_data));
7365 status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
7366 sizeof(struct i40e_aqc_ns_proxy_data),
7373 * i40e_aq_set_clear_wol_filter
7374 * @hw: pointer to the hw struct
7375 * @filter_index: index of filter to modify (0-7)
7376 * @filter: buffer containing filter to be set
7377 * @set_filter: true to set filter, false to clear filter
7378 * @no_wol_tco: if true, pass through packets cannot cause wake-up
7379 * if false, pass through packets may cause wake-up
7380 * @filter_valid: true if filter action is valid
7381 * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
7382 * @cmd_details: pointer to command details structure or NULL
7384 * Set or clear WoL filter for port attached to the PF
7386 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
7388 struct i40e_aqc_set_wol_filter_data *filter,
7389 bool set_filter, bool no_wol_tco,
7390 bool filter_valid, bool no_wol_tco_valid,
7391 struct i40e_asq_cmd_details *cmd_details)
7393 struct i40e_aq_desc desc;
7394 struct i40e_aqc_set_wol_filter *cmd =
7395 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
7396 enum i40e_status_code status;
7398 u16 valid_flags = 0;
7401 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
7403 if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
7404 return I40E_ERR_PARAM;
7405 cmd->filter_index = CPU_TO_LE16(filter_index);
7409 return I40E_ERR_PARAM;
7411 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
7412 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR;
7416 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
7417 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
7420 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
7421 if (no_wol_tco_valid)
7422 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
7423 cmd->valid_flags = CPU_TO_LE16(valid_flags);
7425 buff_len = sizeof(*filter);
7426 desc.datalen = CPU_TO_LE16(buff_len);
7428 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7429 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7431 cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
7432 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
7434 status = i40e_asq_send_command(hw, &desc, filter,
7435 buff_len, cmd_details);
7441 * i40e_aq_get_wake_event_reason
7442 * @hw: pointer to the hw struct
7443 * @wake_reason: return value, index of matching filter
7444 * @cmd_details: pointer to command details structure or NULL
7446 * Get information for the reason of a Wake Up event
7448 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
7450 struct i40e_asq_cmd_details *cmd_details)
7452 struct i40e_aq_desc desc;
7453 struct i40e_aqc_get_wake_reason_completion *resp =
7454 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
7455 enum i40e_status_code status;
7457 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
7459 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7461 if (status == I40E_SUCCESS)
7462 *wake_reason = LE16_TO_CPU(resp->wake_reason);
7468 * i40e_aq_clear_all_wol_filters
7469 * @hw: pointer to the hw struct
7470 * @cmd_details: pointer to command details structure or NULL
7472 * Get information for the reason of a Wake Up event
7474 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw,
7475 struct i40e_asq_cmd_details *cmd_details)
7477 struct i40e_aq_desc desc;
7478 enum i40e_status_code status;
7480 i40e_fill_default_direct_cmd_desc(&desc,
7481 i40e_aqc_opc_clear_all_wol_filters);
7483 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7489 * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
7490 * @hw: pointer to the hw struct
7491 * @buff: command buffer (size in bytes = buff_size)
7492 * @buff_size: buffer size in bytes
7493 * @track_id: package tracking id
7494 * @error_offset: returns error offset
7495 * @error_info: returns error information
7496 * @cmd_details: pointer to command details structure or NULL
7499 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
7500 u16 buff_size, u32 track_id,
7501 u32 *error_offset, u32 *error_info,
7502 struct i40e_asq_cmd_details *cmd_details)
7504 struct i40e_aq_desc desc;
7505 struct i40e_aqc_write_personalization_profile *cmd =
7506 (struct i40e_aqc_write_personalization_profile *)
7508 struct i40e_aqc_write_ddp_resp *resp;
7509 enum i40e_status_code status;
7511 i40e_fill_default_direct_cmd_desc(&desc,
7512 i40e_aqc_opc_write_personalization_profile);
7514 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
7515 if (buff_size > I40E_AQ_LARGE_BUF)
7516 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7518 desc.datalen = CPU_TO_LE16(buff_size);
7520 cmd->profile_track_id = CPU_TO_LE32(track_id);
7522 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7524 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
7526 *error_offset = LE32_TO_CPU(resp->error_offset);
7528 *error_info = LE32_TO_CPU(resp->error_info);
7535 * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
7536 * @hw: pointer to the hw struct
7537 * @buff: command buffer (size in bytes = buff_size)
7538 * @buff_size: buffer size in bytes
7539 * @flags: AdminQ command flags
7540 * @cmd_details: pointer to command details structure or NULL
7543 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
7544 u16 buff_size, u8 flags,
7545 struct i40e_asq_cmd_details *cmd_details)
7547 struct i40e_aq_desc desc;
7548 struct i40e_aqc_get_applied_profiles *cmd =
7549 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
7550 enum i40e_status_code status;
7552 i40e_fill_default_direct_cmd_desc(&desc,
7553 i40e_aqc_opc_get_personalization_profile_list);
7555 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7556 if (buff_size > I40E_AQ_LARGE_BUF)
7557 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7558 desc.datalen = CPU_TO_LE16(buff_size);
7562 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7568 * i40e_find_segment_in_package
7569 * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
7570 * @pkg_hdr: pointer to the package header to be searched
7572 * This function searches a package file for a particular segment type. On
7573 * success it returns a pointer to the segment header, otherwise it will
7576 struct i40e_generic_seg_header *
7577 i40e_find_segment_in_package(u32 segment_type,
7578 struct i40e_package_header *pkg_hdr)
7580 struct i40e_generic_seg_header *segment;
7583 /* Search all package segments for the requested segment type */
7584 for (i = 0; i < pkg_hdr->segment_count; i++) {
7586 (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
7587 pkg_hdr->segment_offset[i]);
7589 if (segment->type == segment_type)
7596 /* Get section table in profile */
7597 #define I40E_SECTION_TABLE(profile, sec_tbl) \
7599 struct i40e_profile_segment *p = (profile); \
7602 count = p->device_table_count; \
7603 nvm = (u32 *)&p->device_table[count]; \
7604 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \
7607 /* Get section header in profile */
7608 #define I40E_SECTION_HEADER(profile, offset) \
7609 (struct i40e_profile_section_header *)((u8 *)(profile) + (offset))
7612 * i40e_find_section_in_profile
7613 * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE)
7614 * @profile: pointer to the i40e segment header to be searched
7616 * This function searches i40e segment for a particular section type. On
7617 * success it returns a pointer to the section header, otherwise it will
7620 struct i40e_profile_section_header *
7621 i40e_find_section_in_profile(u32 section_type,
7622 struct i40e_profile_segment *profile)
7624 struct i40e_profile_section_header *sec;
7625 struct i40e_section_table *sec_tbl;
7629 if (profile->header.type != SEGMENT_TYPE_I40E)
7632 I40E_SECTION_TABLE(profile, sec_tbl);
7634 for (i = 0; i < sec_tbl->section_count; i++) {
7635 sec_off = sec_tbl->section_offset[i];
7636 sec = I40E_SECTION_HEADER(profile, sec_off);
7637 if (sec->section.type == section_type)
7645 * i40e_ddp_exec_aq_section - Execute generic AQ for DDP
7646 * @hw: pointer to the hw struct
7647 * @aq: command buffer containing all data to execute AQ
7650 i40e_status_code i40e_ddp_exec_aq_section(struct i40e_hw *hw,
7651 struct i40e_profile_aq_section *aq)
7653 enum i40e_status_code status;
7654 struct i40e_aq_desc desc;
7658 i40e_fill_default_direct_cmd_desc(&desc, aq->opcode);
7659 desc.flags |= CPU_TO_LE16(aq->flags);
7660 i40e_memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw),
7661 I40E_NONDMA_TO_NONDMA);
7663 msglen = aq->datalen;
7665 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
7667 if (msglen > I40E_AQ_LARGE_BUF)
7668 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7669 desc.datalen = CPU_TO_LE16(msglen);
7673 status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL);
7675 if (status != I40E_SUCCESS) {
7676 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7677 "unable to exec DDP AQ opcode %u, error %d\n",
7678 aq->opcode, status);
7682 /* copy returned desc to aq_buf */
7683 i40e_memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw),
7684 I40E_NONDMA_TO_NONDMA);
7686 return I40E_SUCCESS;
7690 * i40e_validate_profile
7691 * @hw: pointer to the hardware structure
7692 * @profile: pointer to the profile segment of the package to be validated
7693 * @track_id: package tracking id
7694 * @rollback: flag if the profile is for rollback.
7696 * Validates supported devices and profile's sections.
7698 STATIC enum i40e_status_code
7699 i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7700 u32 track_id, bool rollback)
7702 struct i40e_profile_section_header *sec = NULL;
7703 enum i40e_status_code status = I40E_SUCCESS;
7704 struct i40e_section_table *sec_tbl;
7710 if (track_id == I40E_DDP_TRACKID_INVALID) {
7711 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n");
7712 return I40E_NOT_SUPPORTED;
7715 dev_cnt = profile->device_table_count;
7716 for (i = 0; i < dev_cnt; i++) {
7717 vendor_dev_id = profile->device_table[i].vendor_dev_id;
7718 if ((vendor_dev_id >> 16) == I40E_INTEL_VENDOR_ID &&
7719 hw->device_id == (vendor_dev_id & 0xFFFF))
7722 if (dev_cnt && (i == dev_cnt)) {
7723 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7724 "Device doesn't support DDP\n");
7725 return I40E_ERR_DEVICE_NOT_SUPPORTED;
7728 I40E_SECTION_TABLE(profile, sec_tbl);
7730 /* Validate sections types */
7731 for (i = 0; i < sec_tbl->section_count; i++) {
7732 sec_off = sec_tbl->section_offset[i];
7733 sec = I40E_SECTION_HEADER(profile, sec_off);
7735 if (sec->section.type == SECTION_TYPE_MMIO ||
7736 sec->section.type == SECTION_TYPE_AQ ||
7737 sec->section.type == SECTION_TYPE_RB_AQ) {
7738 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7739 "Not a roll-back package\n");
7740 return I40E_NOT_SUPPORTED;
7743 if (sec->section.type == SECTION_TYPE_RB_AQ ||
7744 sec->section.type == SECTION_TYPE_RB_MMIO) {
7745 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7746 "Not an original package\n");
7747 return I40E_NOT_SUPPORTED;
7756 * i40e_write_profile
7757 * @hw: pointer to the hardware structure
7758 * @profile: pointer to the profile segment of the package to be downloaded
7759 * @track_id: package tracking id
7761 * Handles the download of a complete package.
7763 enum i40e_status_code
7764 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7767 enum i40e_status_code status = I40E_SUCCESS;
7768 struct i40e_section_table *sec_tbl;
7769 struct i40e_profile_section_header *sec = NULL;
7770 struct i40e_profile_aq_section *ddp_aq;
7771 u32 section_size = 0;
7772 u32 offset = 0, info = 0;
7776 status = i40e_validate_profile(hw, profile, track_id, false);
7780 I40E_SECTION_TABLE(profile, sec_tbl);
7782 for (i = 0; i < sec_tbl->section_count; i++) {
7783 sec_off = sec_tbl->section_offset[i];
7784 sec = I40E_SECTION_HEADER(profile, sec_off);
7785 /* Process generic admin command */
7786 if (sec->section.type == SECTION_TYPE_AQ) {
7787 ddp_aq = (struct i40e_profile_aq_section *)&sec[1];
7788 status = i40e_ddp_exec_aq_section(hw, ddp_aq);
7790 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7791 "Failed to execute aq: section %d, opcode %u\n",
7795 sec->section.type = SECTION_TYPE_RB_AQ;
7798 /* Skip any non-mmio sections */
7799 if (sec->section.type != SECTION_TYPE_MMIO)
7802 section_size = sec->section.size +
7803 sizeof(struct i40e_profile_section_header);
7805 /* Write MMIO section */
7806 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
7807 track_id, &offset, &info, NULL);
7809 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7810 "Failed to write profile: section %d, offset %d, info %d\n",
7819 * i40e_rollback_profile
7820 * @hw: pointer to the hardware structure
7821 * @profile: pointer to the profile segment of the package to be removed
7822 * @track_id: package tracking id
7824 * Rolls back previously loaded package.
7826 enum i40e_status_code
7827 i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7830 struct i40e_profile_section_header *sec = NULL;
7831 enum i40e_status_code status = I40E_SUCCESS;
7832 struct i40e_section_table *sec_tbl;
7833 u32 offset = 0, info = 0;
7834 u32 section_size = 0;
7838 status = i40e_validate_profile(hw, profile, track_id, true);
7842 I40E_SECTION_TABLE(profile, sec_tbl);
7844 /* For rollback write sections in reverse */
7845 for (i = sec_tbl->section_count - 1; i >= 0; i--) {
7846 sec_off = sec_tbl->section_offset[i];
7847 sec = I40E_SECTION_HEADER(profile, sec_off);
7849 /* Skip any non-rollback sections */
7850 if (sec->section.type != SECTION_TYPE_RB_MMIO)
7853 section_size = sec->section.size +
7854 sizeof(struct i40e_profile_section_header);
7856 /* Write roll-back MMIO section */
7857 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
7858 track_id, &offset, &info, NULL);
7860 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7861 "Failed to write profile: section %d, offset %d, info %d\n",
7870 * i40e_add_pinfo_to_list
7871 * @hw: pointer to the hardware structure
7872 * @profile: pointer to the profile segment of the package
7873 * @profile_info_sec: buffer for information section
7874 * @track_id: package tracking id
7876 * Register a profile to the list of loaded profiles.
7878 enum i40e_status_code
7879 i40e_add_pinfo_to_list(struct i40e_hw *hw,
7880 struct i40e_profile_segment *profile,
7881 u8 *profile_info_sec, u32 track_id)
7883 enum i40e_status_code status = I40E_SUCCESS;
7884 struct i40e_profile_section_header *sec = NULL;
7885 struct i40e_profile_info *pinfo;
7886 u32 offset = 0, info = 0;
7888 sec = (struct i40e_profile_section_header *)profile_info_sec;
7890 sec->data_end = sizeof(struct i40e_profile_section_header) +
7891 sizeof(struct i40e_profile_info);
7892 sec->section.type = SECTION_TYPE_INFO;
7893 sec->section.offset = sizeof(struct i40e_profile_section_header);
7894 sec->section.size = sizeof(struct i40e_profile_info);
7895 pinfo = (struct i40e_profile_info *)(profile_info_sec +
7896 sec->section.offset);
7897 pinfo->track_id = track_id;
7898 pinfo->version = profile->version;
7899 pinfo->op = I40E_DDP_ADD_TRACKID;
7900 i40e_memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE,
7901 I40E_NONDMA_TO_NONDMA);
7903 status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
7904 track_id, &offset, &info, NULL);