drivers/net/i40e/base/i40e_common.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "i40e_type.h"
  35 #include "i40e_adminq.h"
  36 #include "i40e_prototype.h"
  37 #include "virtchnl.h"
  38
  39
  40 /**
  41  * i40e_set_mac_type - Sets MAC type
  42  * @hw: pointer to the HW structure
  43  *
  44  * This function sets the mac type of the adapter based on the
  45  * vendor ID and device ID stored in the hw structure.
  46  **/
  47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  49 #else
  50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  51 #endif
  52 {
  53         enum i40e_status_code status = I40E_SUCCESS;
  54
  55         DEBUGFUNC("i40e_set_mac_type\n");
  56
  57         if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
  58                 switch (hw->device_id) {
  59                 case I40E_DEV_ID_SFP_XL710:
  60                 case I40E_DEV_ID_QEMU:
  61                 case I40E_DEV_ID_KX_B:
  62                 case I40E_DEV_ID_KX_C:
  63                 case I40E_DEV_ID_QSFP_A:
  64                 case I40E_DEV_ID_QSFP_B:
  65                 case I40E_DEV_ID_QSFP_C:
  66                 case I40E_DEV_ID_10G_BASE_T:
  67                 case I40E_DEV_ID_10G_BASE_T4:
  68                 case I40E_DEV_ID_20G_KR2:
  69                 case I40E_DEV_ID_20G_KR2_A:
  70                 case I40E_DEV_ID_25G_B:
  71                 case I40E_DEV_ID_25G_SFP28:
  72                         hw->mac.type = I40E_MAC_XL710;
  73                         break;
  74 #ifdef X722_A0_SUPPORT
  75                 case I40E_DEV_ID_X722_A0:
  76 #endif
  77                 case I40E_DEV_ID_KX_X722:
  78                 case I40E_DEV_ID_QSFP_X722:
  79                 case I40E_DEV_ID_SFP_X722:
  80                 case I40E_DEV_ID_1G_BASE_T_X722:
  81                 case I40E_DEV_ID_10G_BASE_T_X722:
  82                 case I40E_DEV_ID_SFP_I_X722:
  83                         hw->mac.type = I40E_MAC_X722;
  84                         break;
  85 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  86                 case I40E_DEV_ID_X722_VF:
  87 #ifdef X722_A0_SUPPORT
  88                 case I40E_DEV_ID_X722_A0_VF:
  89 #endif
  90                         hw->mac.type = I40E_MAC_X722_VF;
  91                         break;
  92 #endif /* INTEGRATED_VF || VF_DRIVER */
  93 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  94                 case I40E_DEV_ID_VF:
  95                 case I40E_DEV_ID_VF_HV:
  96                 case I40E_DEV_ID_ADAPTIVE_VF:
  97                         hw->mac.type = I40E_MAC_VF;
  98                         break;
  99 #endif
 100                 default:
 101                         hw->mac.type = I40E_MAC_GENERIC;
 102                         break;
 103                 }
 104         } else {
 105                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
 106         }
 107
 108         DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
 109                   hw->mac.type, status);
 110         return status;
 111 }
 112
 113 /**
 114  * i40e_aq_str - convert AQ err code to a string
 115  * @hw: pointer to the HW structure
 116  * @aq_err: the AQ error code to convert
 117  **/
 118 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
 119 {
 120         switch (aq_err) {
 121         case I40E_AQ_RC_OK:
 122                 return "OK";
 123         case I40E_AQ_RC_EPERM:
 124                 return "I40E_AQ_RC_EPERM";
 125         case I40E_AQ_RC_ENOENT:
 126                 return "I40E_AQ_RC_ENOENT";
 127         case I40E_AQ_RC_ESRCH:
 128                 return "I40E_AQ_RC_ESRCH";
 129         case I40E_AQ_RC_EINTR:
 130                 return "I40E_AQ_RC_EINTR";
 131         case I40E_AQ_RC_EIO:
 132                 return "I40E_AQ_RC_EIO";
 133         case I40E_AQ_RC_ENXIO:
 134                 return "I40E_AQ_RC_ENXIO";
 135         case I40E_AQ_RC_E2BIG:
 136                 return "I40E_AQ_RC_E2BIG";
 137         case I40E_AQ_RC_EAGAIN:
 138                 return "I40E_AQ_RC_EAGAIN";
 139         case I40E_AQ_RC_ENOMEM:
 140                 return "I40E_AQ_RC_ENOMEM";
 141         case I40E_AQ_RC_EACCES:
 142                 return "I40E_AQ_RC_EACCES";
 143         case I40E_AQ_RC_EFAULT:
 144                 return "I40E_AQ_RC_EFAULT";
 145         case I40E_AQ_RC_EBUSY:
 146                 return "I40E_AQ_RC_EBUSY";
 147         case I40E_AQ_RC_EEXIST:
 148                 return "I40E_AQ_RC_EEXIST";
 149         case I40E_AQ_RC_EINVAL:
 150                 return "I40E_AQ_RC_EINVAL";
 151         case I40E_AQ_RC_ENOTTY:
 152                 return "I40E_AQ_RC_ENOTTY";
 153         case I40E_AQ_RC_ENOSPC:
 154                 return "I40E_AQ_RC_ENOSPC";
 155         case I40E_AQ_RC_ENOSYS:
 156                 return "I40E_AQ_RC_ENOSYS";
 157         case I40E_AQ_RC_ERANGE:
 158                 return "I40E_AQ_RC_ERANGE";
 159         case I40E_AQ_RC_EFLUSHED:
 160                 return "I40E_AQ_RC_EFLUSHED";
 161         case I40E_AQ_RC_BAD_ADDR:
 162                 return "I40E_AQ_RC_BAD_ADDR";
 163         case I40E_AQ_RC_EMODE:
 164                 return "I40E_AQ_RC_EMODE";
 165         case I40E_AQ_RC_EFBIG:
 166                 return "I40E_AQ_RC_EFBIG";
 167         }
 168
 169         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 170         return hw->err_str;
 171 }
 172
 173 /**
 174  * i40e_stat_str - convert status err code to a string
 175  * @hw: pointer to the HW structure
 176  * @stat_err: the status error code to convert
 177  **/
 178 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
 179 {
 180         switch (stat_err) {
 181         case I40E_SUCCESS:
 182                 return "OK";
 183         case I40E_ERR_NVM:
 184                 return "I40E_ERR_NVM";
 185         case I40E_ERR_NVM_CHECKSUM:
 186                 return "I40E_ERR_NVM_CHECKSUM";
 187         case I40E_ERR_PHY:
 188                 return "I40E_ERR_PHY";
 189         case I40E_ERR_CONFIG:
 190                 return "I40E_ERR_CONFIG";
 191         case I40E_ERR_PARAM:
 192                 return "I40E_ERR_PARAM";
 193         case I40E_ERR_MAC_TYPE:
 194                 return "I40E_ERR_MAC_TYPE";
 195         case I40E_ERR_UNKNOWN_PHY:
 196                 return "I40E_ERR_UNKNOWN_PHY";
 197         case I40E_ERR_LINK_SETUP:
 198                 return "I40E_ERR_LINK_SETUP";
 199         case I40E_ERR_ADAPTER_STOPPED:
 200                 return "I40E_ERR_ADAPTER_STOPPED";
 201         case I40E_ERR_INVALID_MAC_ADDR:
 202                 return "I40E_ERR_INVALID_MAC_ADDR";
 203         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 204                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 205         case I40E_ERR_MASTER_REQUESTS_PENDING:
 206                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 207         case I40E_ERR_INVALID_LINK_SETTINGS:
 208                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 209         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 210                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 211         case I40E_ERR_RESET_FAILED:
 212                 return "I40E_ERR_RESET_FAILED";
 213         case I40E_ERR_SWFW_SYNC:
 214                 return "I40E_ERR_SWFW_SYNC";
 215         case I40E_ERR_NO_AVAILABLE_VSI:
 216                 return "I40E_ERR_NO_AVAILABLE_VSI";
 217         case I40E_ERR_NO_MEMORY:
 218                 return "I40E_ERR_NO_MEMORY";
 219         case I40E_ERR_BAD_PTR:
 220                 return "I40E_ERR_BAD_PTR";
 221         case I40E_ERR_RING_FULL:
 222                 return "I40E_ERR_RING_FULL";
 223         case I40E_ERR_INVALID_PD_ID:
 224                 return "I40E_ERR_INVALID_PD_ID";
 225         case I40E_ERR_INVALID_QP_ID:
 226                 return "I40E_ERR_INVALID_QP_ID";
 227         case I40E_ERR_INVALID_CQ_ID:
 228                 return "I40E_ERR_INVALID_CQ_ID";
 229         case I40E_ERR_INVALID_CEQ_ID:
 230                 return "I40E_ERR_INVALID_CEQ_ID";
 231         case I40E_ERR_INVALID_AEQ_ID:
 232                 return "I40E_ERR_INVALID_AEQ_ID";
 233         case I40E_ERR_INVALID_SIZE:
 234                 return "I40E_ERR_INVALID_SIZE";
 235         case I40E_ERR_INVALID_ARP_INDEX:
 236                 return "I40E_ERR_INVALID_ARP_INDEX";
 237         case I40E_ERR_INVALID_FPM_FUNC_ID:
 238                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 239         case I40E_ERR_QP_INVALID_MSG_SIZE:
 240                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 241         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 242                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 243         case I40E_ERR_INVALID_FRAG_COUNT:
 244                 return "I40E_ERR_INVALID_FRAG_COUNT";
 245         case I40E_ERR_QUEUE_EMPTY:
 246                 return "I40E_ERR_QUEUE_EMPTY";
 247         case I40E_ERR_INVALID_ALIGNMENT:
 248                 return "I40E_ERR_INVALID_ALIGNMENT";
 249         case I40E_ERR_FLUSHED_QUEUE:
 250                 return "I40E_ERR_FLUSHED_QUEUE";
 251         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 252                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 253         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 254                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 255         case I40E_ERR_TIMEOUT:
 256                 return "I40E_ERR_TIMEOUT";
 257         case I40E_ERR_OPCODE_MISMATCH:
 258                 return "I40E_ERR_OPCODE_MISMATCH";
 259         case I40E_ERR_CQP_COMPL_ERROR:
 260                 return "I40E_ERR_CQP_COMPL_ERROR";
 261         case I40E_ERR_INVALID_VF_ID:
 262                 return "I40E_ERR_INVALID_VF_ID";
 263         case I40E_ERR_INVALID_HMCFN_ID:
 264                 return "I40E_ERR_INVALID_HMCFN_ID";
 265         case I40E_ERR_BACKING_PAGE_ERROR:
 266                 return "I40E_ERR_BACKING_PAGE_ERROR";
 267         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 268                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 269         case I40E_ERR_INVALID_PBLE_INDEX:
 270                 return "I40E_ERR_INVALID_PBLE_INDEX";
 271         case I40E_ERR_INVALID_SD_INDEX:
 272                 return "I40E_ERR_INVALID_SD_INDEX";
 273         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 274                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 275         case I40E_ERR_INVALID_SD_TYPE:
 276                 return "I40E_ERR_INVALID_SD_TYPE";
 277         case I40E_ERR_MEMCPY_FAILED:
 278                 return "I40E_ERR_MEMCPY_FAILED";
 279         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 280                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 281         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 282                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 283         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 284                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 285         case I40E_ERR_SRQ_ENABLED:
 286                 return "I40E_ERR_SRQ_ENABLED";
 287         case I40E_ERR_ADMIN_QUEUE_ERROR:
 288                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 289         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 290                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 291         case I40E_ERR_BUF_TOO_SHORT:
 292                 return "I40E_ERR_BUF_TOO_SHORT";
 293         case I40E_ERR_ADMIN_QUEUE_FULL:
 294                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 295         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 296                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 297         case I40E_ERR_BAD_IWARP_CQE:
 298                 return "I40E_ERR_BAD_IWARP_CQE";
 299         case I40E_ERR_NVM_BLANK_MODE:
 300                 return "I40E_ERR_NVM_BLANK_MODE";
 301         case I40E_ERR_NOT_IMPLEMENTED:
 302                 return "I40E_ERR_NOT_IMPLEMENTED";
 303         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 304                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 305         case I40E_ERR_DIAG_TEST_FAILED:
 306                 return "I40E_ERR_DIAG_TEST_FAILED";
 307         case I40E_ERR_NOT_READY:
 308                 return "I40E_ERR_NOT_READY";
 309         case I40E_NOT_SUPPORTED:
 310                 return "I40E_NOT_SUPPORTED";
 311         case I40E_ERR_FIRMWARE_API_VERSION:
 312                 return "I40E_ERR_FIRMWARE_API_VERSION";
 313         }
 314
 315         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 316         return hw->err_str;
 317 }
 318
 319 /**
 320  * i40e_debug_aq
 321  * @hw: debug mask related to admin queue
 322  * @mask: debug mask
 323  * @desc: pointer to admin queue descriptor
 324  * @buffer: pointer to command buffer
 325  * @buf_len: max length of buffer
 326  *
 327  * Dumps debug log about adminq command with descriptor contents.
 328  **/
 329 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 330                    void *buffer, u16 buf_len)
 331 {
 332         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 333         u16 len = LE16_TO_CPU(aq_desc->datalen);
 334         u8 *buf = (u8 *)buffer;
 335         u16 i = 0;
 336
 337         if ((!(mask & hw->debug_mask)) || (desc == NULL))
 338                 return;
 339
 340         i40e_debug(hw, mask,
 341                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 342                    LE16_TO_CPU(aq_desc->opcode),
 343                    LE16_TO_CPU(aq_desc->flags),
 344                    LE16_TO_CPU(aq_desc->datalen),
 345                    LE16_TO_CPU(aq_desc->retval));
 346         i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
 347                    LE32_TO_CPU(aq_desc->cookie_high),
 348                    LE32_TO_CPU(aq_desc->cookie_low));
 349         i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
 350                    LE32_TO_CPU(aq_desc->params.internal.param0),
 351                    LE32_TO_CPU(aq_desc->params.internal.param1));
 352         i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
 353                    LE32_TO_CPU(aq_desc->params.external.addr_high),
 354                    LE32_TO_CPU(aq_desc->params.external.addr_low));
 355
 356         if ((buffer != NULL) && (aq_desc->datalen != 0)) {
 357                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 358                 if (buf_len < len)
 359                         len = buf_len;
 360                 /* write the full 16-byte chunks */
 361                 for (i = 0; i < (len - 16); i += 16)
 362                         i40e_debug(hw, mask,
 363                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 364                                    i, buf[i], buf[i+1], buf[i+2], buf[i+3],
 365                                    buf[i+4], buf[i+5], buf[i+6], buf[i+7],
 366                                    buf[i+8], buf[i+9], buf[i+10], buf[i+11],
 367                                    buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
 368                 /* the most we could have left is 16 bytes, pad with zeros */
 369                 if (i < len) {
 370                         char d_buf[16];
 371                         int j, i_sav;
 372
 373                         i_sav = i;
 374                         memset(d_buf, 0, sizeof(d_buf));
 375                         for (j = 0; i < len; j++, i++)
 376                                 d_buf[j] = buf[i];
 377                         i40e_debug(hw, mask,
 378                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 379                                    i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
 380                                    d_buf[4], d_buf[5], d_buf[6], d_buf[7],
 381                                    d_buf[8], d_buf[9], d_buf[10], d_buf[11],
 382                                    d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
 383                 }
 384         }
 385 }
 386
 387 /**
 388  * i40e_check_asq_alive
 389  * @hw: pointer to the hw struct
 390  *
 391  * Returns true if Queue is enabled else false.
 392  **/
 393 bool i40e_check_asq_alive(struct i40e_hw *hw)
 394 {
 395         if (hw->aq.asq.len)
 396 #ifdef PF_DRIVER
 397 #ifdef INTEGRATED_VF
 398                 if (!i40e_is_vf(hw))
 399                         return !!(rd32(hw, hw->aq.asq.len) &
 400                                 I40E_PF_ATQLEN_ATQENABLE_MASK);
 401 #else
 402                 return !!(rd32(hw, hw->aq.asq.len) &
 403                         I40E_PF_ATQLEN_ATQENABLE_MASK);
 404 #endif /* INTEGRATED_VF */
 405 #endif /* PF_DRIVER */
 406 #ifdef VF_DRIVER
 407 #ifdef INTEGRATED_VF
 408                 if (i40e_is_vf(hw))
 409                         return !!(rd32(hw, hw->aq.asq.len) &
 410                                 I40E_VF_ATQLEN1_ATQENABLE_MASK);
 411 #else
 412                 return !!(rd32(hw, hw->aq.asq.len) &
 413                         I40E_VF_ATQLEN1_ATQENABLE_MASK);
 414 #endif /* INTEGRATED_VF */
 415 #endif /* VF_DRIVER */
 416         return false;
 417 }
 418
 419 /**
 420  * i40e_aq_queue_shutdown
 421  * @hw: pointer to the hw struct
 422  * @unloading: is the driver unloading itself
 423  *
 424  * Tell the Firmware that we're shutting down the AdminQ and whether
 425  * or not the driver is unloading as well.
 426  **/
 427 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
 428                                              bool unloading)
 429 {
 430         struct i40e_aq_desc desc;
 431         struct i40e_aqc_queue_shutdown *cmd =
 432                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 433         enum i40e_status_code status;
 434
 435         i40e_fill_default_direct_cmd_desc(&desc,
 436                                           i40e_aqc_opc_queue_shutdown);
 437
 438         if (unloading)
 439                 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
 440         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 441
 442         return status;
 443 }
 444
 445 /**
 446  * i40e_aq_get_set_rss_lut
 447  * @hw: pointer to the hardware structure
 448  * @vsi_id: vsi fw index
 449  * @pf_lut: for PF table set true, for VSI table set false
 450  * @lut: pointer to the lut buffer provided by the caller
 451  * @lut_size: size of the lut buffer
 452  * @set: set true to set the table, false to get the table
 453  *
 454  * Internal function to get or set RSS look up table
 455  **/
 456 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 457                                                      u16 vsi_id, bool pf_lut,
 458                                                      u8 *lut, u16 lut_size,
 459                                                      bool set)
 460 {
 461         enum i40e_status_code status;
 462         struct i40e_aq_desc desc;
 463         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 464                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 465
 466         if (set)
 467                 i40e_fill_default_direct_cmd_desc(&desc,
 468                                                   i40e_aqc_opc_set_rss_lut);
 469         else
 470                 i40e_fill_default_direct_cmd_desc(&desc,
 471                                                   i40e_aqc_opc_get_rss_lut);
 472
 473         /* Indirect command */
 474         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 475         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 476
 477         cmd_resp->vsi_id =
 478                         CPU_TO_LE16((u16)((vsi_id <<
 479                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 480                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 481         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 482
 483         if (pf_lut)
 484                 cmd_resp->flags |= CPU_TO_LE16((u16)
 485                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 486                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 487                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 488         else
 489                 cmd_resp->flags |= CPU_TO_LE16((u16)
 490                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 491                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 492                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 493
 494         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 495
 496         return status;
 497 }
 498
 499 /**
 500  * i40e_aq_get_rss_lut
 501  * @hw: pointer to the hardware structure
 502  * @vsi_id: vsi fw index
 503  * @pf_lut: for PF table set true, for VSI table set false
 504  * @lut: pointer to the lut buffer provided by the caller
 505  * @lut_size: size of the lut buffer
 506  *
 507  * get the RSS lookup table, PF or VSI type
 508  **/
 509 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 510                                           bool pf_lut, u8 *lut, u16 lut_size)
 511 {
 512         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 513                                        false);
 514 }
 515
 516 /**
 517  * i40e_aq_set_rss_lut
 518  * @hw: pointer to the hardware structure
 519  * @vsi_id: vsi fw index
 520  * @pf_lut: for PF table set true, for VSI table set false
 521  * @lut: pointer to the lut buffer provided by the caller
 522  * @lut_size: size of the lut buffer
 523  *
 524  * set the RSS lookup table, PF or VSI type
 525  **/
 526 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 527                                           bool pf_lut, u8 *lut, u16 lut_size)
 528 {
 529         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
 530 }
 531
 532 /**
 533  * i40e_aq_get_set_rss_key
 534  * @hw: pointer to the hw struct
 535  * @vsi_id: vsi fw index
 536  * @key: pointer to key info struct
 537  * @set: set true to set the key, false to get the key
 538  *
 539  * get the RSS key per VSI
 540  **/
 541 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 542                                       u16 vsi_id,
 543                                       struct i40e_aqc_get_set_rss_key_data *key,
 544                                       bool set)
 545 {
 546         enum i40e_status_code status;
 547         struct i40e_aq_desc desc;
 548         struct i40e_aqc_get_set_rss_key *cmd_resp =
 549                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 550         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 551
 552         if (set)
 553                 i40e_fill_default_direct_cmd_desc(&desc,
 554                                                   i40e_aqc_opc_set_rss_key);
 555         else
 556                 i40e_fill_default_direct_cmd_desc(&desc,
 557                                                   i40e_aqc_opc_get_rss_key);
 558
 559         /* Indirect command */
 560         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 561         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 562
 563         cmd_resp->vsi_id =
 564                         CPU_TO_LE16((u16)((vsi_id <<
 565                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 566                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 567         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 568
 569         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 570
 571         return status;
 572 }
 573
 574 /**
 575  * i40e_aq_get_rss_key
 576  * @hw: pointer to the hw struct
 577  * @vsi_id: vsi fw index
 578  * @key: pointer to key info struct
 579  *
 580  **/
 581 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
 582                                       u16 vsi_id,
 583                                       struct i40e_aqc_get_set_rss_key_data *key)
 584 {
 585         return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
 586 }
 587
 588 /**
 589  * i40e_aq_set_rss_key
 590  * @hw: pointer to the hw struct
 591  * @vsi_id: vsi fw index
 592  * @key: pointer to key info struct
 593  *
 594  * set the RSS key per VSI
 595  **/
 596 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
 597                                       u16 vsi_id,
 598                                       struct i40e_aqc_get_set_rss_key_data *key)
 599 {
 600         return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
 601 }
 602
 603 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 604  * hardware to a bit-field that can be used by SW to more easily determine the
 605  * packet type.
 606  *
 607  * Macros are used to shorten the table lines and make this table human
 608  * readable.
 609  *
 610  * We store the PTYPE in the top byte of the bit field - this is just so that
 611  * we can check that the table doesn't have a row missing, as the index into
 612  * the table should be the PTYPE.
 613  *
 614  * Typical work flow:
 615  *
 616  * IF NOT i40e_ptype_lookup[ptype].known
 617  * THEN
 618  *      Packet is unknown
 619  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 620  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 621  * ELSE
 622  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 623  * ENDIF
 624  */
 625
 626 /* macro to make the table lines short */
 627 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 628         {       PTYPE, \
 629                 1, \
 630                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 631                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 632                 I40E_RX_PTYPE_##OUTER_FRAG, \
 633                 I40E_RX_PTYPE_TUNNEL_##T, \
 634                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 635                 I40E_RX_PTYPE_##TEF, \
 636                 I40E_RX_PTYPE_INNER_PROT_##I, \
 637                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 638
 639 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 640                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 641
 642 /* shorter macros makes the table fit but are terse */
 643 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 644 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 645 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 646
 647 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 648 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 649         /* L2 Packet types */
 650         I40E_PTT_UNUSED_ENTRY(0),
 651         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 652         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 653         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 654         I40E_PTT_UNUSED_ENTRY(4),
 655         I40E_PTT_UNUSED_ENTRY(5),
 656         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 657         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 658         I40E_PTT_UNUSED_ENTRY(8),
 659         I40E_PTT_UNUSED_ENTRY(9),
 660         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 661         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 662         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 663         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 664         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 665         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 666         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 667         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 668         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 669         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 670         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 671         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 672
 673         /* Non Tunneled IPv4 */
 674         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 675         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 676         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 677         I40E_PTT_UNUSED_ENTRY(25),
 678         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 679         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 680         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 681
 682         /* IPv4 --> IPv4 */
 683         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 684         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 685         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 686         I40E_PTT_UNUSED_ENTRY(32),
 687         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 688         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 689         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 690
 691         /* IPv4 --> IPv6 */
 692         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 693         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 694         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 695         I40E_PTT_UNUSED_ENTRY(39),
 696         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 697         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 698         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 699
 700         /* IPv4 --> GRE/NAT */
 701         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 702
 703         /* IPv4 --> GRE/NAT --> IPv4 */
 704         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 705         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 706         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 707         I40E_PTT_UNUSED_ENTRY(47),
 708         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 709         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 710         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 711
 712         /* IPv4 --> GRE/NAT --> IPv6 */
 713         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 714         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 715         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 716         I40E_PTT_UNUSED_ENTRY(54),
 717         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 718         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 719         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 720
 721         /* IPv4 --> GRE/NAT --> MAC */
 722         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 723
 724         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 725         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 726         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 727         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 728         I40E_PTT_UNUSED_ENTRY(62),
 729         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 730         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 731         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 732
 733         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 734         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 735         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 736         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 737         I40E_PTT_UNUSED_ENTRY(69),
 738         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 739         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 740         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 741
 742         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 743         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 744
 745         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 746         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 747         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 748         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 749         I40E_PTT_UNUSED_ENTRY(77),
 750         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 751         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 752         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 753
 754         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 755         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 756         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 757         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 758         I40E_PTT_UNUSED_ENTRY(84),
 759         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 760         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 761         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 762
 763         /* Non Tunneled IPv6 */
 764         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 765         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 766         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
 767         I40E_PTT_UNUSED_ENTRY(91),
 768         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 769         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 770         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 771
 772         /* IPv6 --> IPv4 */
 773         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 774         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 775         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 776         I40E_PTT_UNUSED_ENTRY(98),
 777         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 778         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 779         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 780
 781         /* IPv6 --> IPv6 */
 782         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 783         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 784         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 785         I40E_PTT_UNUSED_ENTRY(105),
 786         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 787         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 788         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 789
 790         /* IPv6 --> GRE/NAT */
 791         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 792
 793         /* IPv6 --> GRE/NAT -> IPv4 */
 794         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 795         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 796         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 797         I40E_PTT_UNUSED_ENTRY(113),
 798         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 799         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 800         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 801
 802         /* IPv6 --> GRE/NAT -> IPv6 */
 803         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 804         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 805         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 806         I40E_PTT_UNUSED_ENTRY(120),
 807         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 808         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 809         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 810
 811         /* IPv6 --> GRE/NAT -> MAC */
 812         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 813
 814         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 815         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 816         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 817         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 818         I40E_PTT_UNUSED_ENTRY(128),
 819         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 820         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 821         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 822
 823         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 824         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 825         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 826         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 827         I40E_PTT_UNUSED_ENTRY(135),
 828         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 829         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 830         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 831
 832         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 833         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 834
 835         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 836         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 837         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 838         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 839         I40E_PTT_UNUSED_ENTRY(143),
 840         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 841         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 842         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 843
 844         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 845         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 846         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 847         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 848         I40E_PTT_UNUSED_ENTRY(150),
 849         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 850         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 851         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 852
 853         /* unused entries */
 854         I40E_PTT_UNUSED_ENTRY(154),
 855         I40E_PTT_UNUSED_ENTRY(155),
 856         I40E_PTT_UNUSED_ENTRY(156),
 857         I40E_PTT_UNUSED_ENTRY(157),
 858         I40E_PTT_UNUSED_ENTRY(158),
 859         I40E_PTT_UNUSED_ENTRY(159),
 860
 861         I40E_PTT_UNUSED_ENTRY(160),
 862         I40E_PTT_UNUSED_ENTRY(161),
 863         I40E_PTT_UNUSED_ENTRY(162),
 864         I40E_PTT_UNUSED_ENTRY(163),
 865         I40E_PTT_UNUSED_ENTRY(164),
 866         I40E_PTT_UNUSED_ENTRY(165),
 867         I40E_PTT_UNUSED_ENTRY(166),
 868         I40E_PTT_UNUSED_ENTRY(167),
 869         I40E_PTT_UNUSED_ENTRY(168),
 870         I40E_PTT_UNUSED_ENTRY(169),
 871
 872         I40E_PTT_UNUSED_ENTRY(170),
 873         I40E_PTT_UNUSED_ENTRY(171),
 874         I40E_PTT_UNUSED_ENTRY(172),
 875         I40E_PTT_UNUSED_ENTRY(173),
 876         I40E_PTT_UNUSED_ENTRY(174),
 877         I40E_PTT_UNUSED_ENTRY(175),
 878         I40E_PTT_UNUSED_ENTRY(176),
 879         I40E_PTT_UNUSED_ENTRY(177),
 880         I40E_PTT_UNUSED_ENTRY(178),
 881         I40E_PTT_UNUSED_ENTRY(179),
 882
 883         I40E_PTT_UNUSED_ENTRY(180),
 884         I40E_PTT_UNUSED_ENTRY(181),
 885         I40E_PTT_UNUSED_ENTRY(182),
 886         I40E_PTT_UNUSED_ENTRY(183),
 887         I40E_PTT_UNUSED_ENTRY(184),
 888         I40E_PTT_UNUSED_ENTRY(185),
 889         I40E_PTT_UNUSED_ENTRY(186),
 890         I40E_PTT_UNUSED_ENTRY(187),
 891         I40E_PTT_UNUSED_ENTRY(188),
 892         I40E_PTT_UNUSED_ENTRY(189),
 893
 894         I40E_PTT_UNUSED_ENTRY(190),
 895         I40E_PTT_UNUSED_ENTRY(191),
 896         I40E_PTT_UNUSED_ENTRY(192),
 897         I40E_PTT_UNUSED_ENTRY(193),
 898         I40E_PTT_UNUSED_ENTRY(194),
 899         I40E_PTT_UNUSED_ENTRY(195),
 900         I40E_PTT_UNUSED_ENTRY(196),
 901         I40E_PTT_UNUSED_ENTRY(197),
 902         I40E_PTT_UNUSED_ENTRY(198),
 903         I40E_PTT_UNUSED_ENTRY(199),
 904
 905         I40E_PTT_UNUSED_ENTRY(200),
 906         I40E_PTT_UNUSED_ENTRY(201),
 907         I40E_PTT_UNUSED_ENTRY(202),
 908         I40E_PTT_UNUSED_ENTRY(203),
 909         I40E_PTT_UNUSED_ENTRY(204),
 910         I40E_PTT_UNUSED_ENTRY(205),
 911         I40E_PTT_UNUSED_ENTRY(206),
 912         I40E_PTT_UNUSED_ENTRY(207),
 913         I40E_PTT_UNUSED_ENTRY(208),
 914         I40E_PTT_UNUSED_ENTRY(209),
 915
 916         I40E_PTT_UNUSED_ENTRY(210),
 917         I40E_PTT_UNUSED_ENTRY(211),
 918         I40E_PTT_UNUSED_ENTRY(212),
 919         I40E_PTT_UNUSED_ENTRY(213),
 920         I40E_PTT_UNUSED_ENTRY(214),
 921         I40E_PTT_UNUSED_ENTRY(215),
 922         I40E_PTT_UNUSED_ENTRY(216),
 923         I40E_PTT_UNUSED_ENTRY(217),
 924         I40E_PTT_UNUSED_ENTRY(218),
 925         I40E_PTT_UNUSED_ENTRY(219),
 926
 927         I40E_PTT_UNUSED_ENTRY(220),
 928         I40E_PTT_UNUSED_ENTRY(221),
 929         I40E_PTT_UNUSED_ENTRY(222),
 930         I40E_PTT_UNUSED_ENTRY(223),
 931         I40E_PTT_UNUSED_ENTRY(224),
 932         I40E_PTT_UNUSED_ENTRY(225),
 933         I40E_PTT_UNUSED_ENTRY(226),
 934         I40E_PTT_UNUSED_ENTRY(227),
 935         I40E_PTT_UNUSED_ENTRY(228),
 936         I40E_PTT_UNUSED_ENTRY(229),
 937
 938         I40E_PTT_UNUSED_ENTRY(230),
 939         I40E_PTT_UNUSED_ENTRY(231),
 940         I40E_PTT_UNUSED_ENTRY(232),
 941         I40E_PTT_UNUSED_ENTRY(233),
 942         I40E_PTT_UNUSED_ENTRY(234),
 943         I40E_PTT_UNUSED_ENTRY(235),
 944         I40E_PTT_UNUSED_ENTRY(236),
 945         I40E_PTT_UNUSED_ENTRY(237),
 946         I40E_PTT_UNUSED_ENTRY(238),
 947         I40E_PTT_UNUSED_ENTRY(239),
 948
 949         I40E_PTT_UNUSED_ENTRY(240),
 950         I40E_PTT_UNUSED_ENTRY(241),
 951         I40E_PTT_UNUSED_ENTRY(242),
 952         I40E_PTT_UNUSED_ENTRY(243),
 953         I40E_PTT_UNUSED_ENTRY(244),
 954         I40E_PTT_UNUSED_ENTRY(245),
 955         I40E_PTT_UNUSED_ENTRY(246),
 956         I40E_PTT_UNUSED_ENTRY(247),
 957         I40E_PTT_UNUSED_ENTRY(248),
 958         I40E_PTT_UNUSED_ENTRY(249),
 959
 960         I40E_PTT_UNUSED_ENTRY(250),
 961         I40E_PTT_UNUSED_ENTRY(251),
 962         I40E_PTT_UNUSED_ENTRY(252),
 963         I40E_PTT_UNUSED_ENTRY(253),
 964         I40E_PTT_UNUSED_ENTRY(254),
 965         I40E_PTT_UNUSED_ENTRY(255)
 966 };
 967
 968
 969 /**
 970  * i40e_validate_mac_addr - Validate unicast MAC address
 971  * @mac_addr: pointer to MAC address
 972  *
 973  * Tests a MAC address to ensure it is a valid Individual Address
 974  **/
 975 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
 976 {
 977         enum i40e_status_code status = I40E_SUCCESS;
 978
 979         DEBUGFUNC("i40e_validate_mac_addr");
 980
 981         /* Broadcast addresses ARE multicast addresses
 982          * Make sure it is not a multicast address
 983          * Reject the zero address
 984          */
 985         if (I40E_IS_MULTICAST(mac_addr) ||
 986             (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
 987               mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
 988                 status = I40E_ERR_INVALID_MAC_ADDR;
 989
 990         return status;
 991 }
 992 #ifdef PF_DRIVER
 993
 994 /**
 995  * i40e_init_shared_code - Initialize the shared code
 996  * @hw: pointer to hardware structure
 997  *
 998  * This assigns the MAC type and PHY code and inits the NVM.
 999  * Does not touch the hardware. This function must be called prior to any
1000  * other function in the shared code. The i40e_hw structure should be
1001  * memset to 0 prior to calling this function.  The following fields in
1002  * hw structure should be filled in prior to calling this function:
1003  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1004  * subsystem_vendor_id, and revision_id
1005  **/
1006 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
1007 {
1008         enum i40e_status_code status = I40E_SUCCESS;
1009         u32 port, ari, func_rid;
1010
1011         DEBUGFUNC("i40e_init_shared_code");
1012
1013         i40e_set_mac_type(hw);
1014
1015         switch (hw->mac.type) {
1016         case I40E_MAC_XL710:
1017         case I40E_MAC_X722:
1018                 break;
1019         default:
1020                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1021         }
1022
1023         hw->phy.get_link_info = true;
1024
1025         /* Determine port number and PF number*/
1026         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1027                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1028         hw->port = (u8)port;
1029         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1030                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1031         func_rid = rd32(hw, I40E_PF_FUNC_RID);
1032         if (ari)
1033                 hw->pf_id = (u8)(func_rid & 0xff);
1034         else
1035                 hw->pf_id = (u8)(func_rid & 0x7);
1036
1037         if (hw->mac.type == I40E_MAC_X722)
1038                 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
1039
1040         status = i40e_init_nvm(hw);
1041         return status;
1042 }
1043
1044 /**
1045  * i40e_aq_mac_address_read - Retrieve the MAC addresses
1046  * @hw: pointer to the hw struct
1047  * @flags: a return indicator of what addresses were added to the addr store
1048  * @addrs: the requestor's mac addr store
1049  * @cmd_details: pointer to command details structure or NULL
1050  **/
1051 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1052                                    u16 *flags,
1053                                    struct i40e_aqc_mac_address_read_data *addrs,
1054                                    struct i40e_asq_cmd_details *cmd_details)
1055 {
1056         struct i40e_aq_desc desc;
1057         struct i40e_aqc_mac_address_read *cmd_data =
1058                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1059         enum i40e_status_code status;
1060
1061         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1062         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1063
1064         status = i40e_asq_send_command(hw, &desc, addrs,
1065                                        sizeof(*addrs), cmd_details);
1066         *flags = LE16_TO_CPU(cmd_data->command_flags);
1067
1068         return status;
1069 }
1070
1071 /**
1072  * i40e_aq_mac_address_write - Change the MAC addresses
1073  * @hw: pointer to the hw struct
1074  * @flags: indicates which MAC to be written
1075  * @mac_addr: address to write
1076  * @cmd_details: pointer to command details structure or NULL
1077  **/
1078 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1079                                     u16 flags, u8 *mac_addr,
1080                                     struct i40e_asq_cmd_details *cmd_details)
1081 {
1082         struct i40e_aq_desc desc;
1083         struct i40e_aqc_mac_address_write *cmd_data =
1084                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1085         enum i40e_status_code status;
1086
1087         i40e_fill_default_direct_cmd_desc(&desc,
1088                                           i40e_aqc_opc_mac_address_write);
1089         cmd_data->command_flags = CPU_TO_LE16(flags);
1090         cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1091         cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1092                                         ((u32)mac_addr[3] << 16) |
1093                                         ((u32)mac_addr[4] << 8) |
1094                                         mac_addr[5]);
1095
1096         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1097
1098         return status;
1099 }
1100
1101 /**
1102  * i40e_get_mac_addr - get MAC address
1103  * @hw: pointer to the HW structure
1104  * @mac_addr: pointer to MAC address
1105  *
1106  * Reads the adapter's MAC address from register
1107  **/
1108 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1109 {
1110         struct i40e_aqc_mac_address_read_data addrs;
1111         enum i40e_status_code status;
1112         u16 flags = 0;
1113
1114         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1115
1116         if (flags & I40E_AQC_LAN_ADDR_VALID)
1117                 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1118                         I40E_NONDMA_TO_NONDMA);
1119
1120         return status;
1121 }
1122
1123 /**
1124  * i40e_get_port_mac_addr - get Port MAC address
1125  * @hw: pointer to the HW structure
1126  * @mac_addr: pointer to Port MAC address
1127  *
1128  * Reads the adapter's Port MAC address
1129  **/
1130 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1131 {
1132         struct i40e_aqc_mac_address_read_data addrs;
1133         enum i40e_status_code status;
1134         u16 flags = 0;
1135
1136         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1137         if (status)
1138                 return status;
1139
1140         if (flags & I40E_AQC_PORT_ADDR_VALID)
1141                 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1142                         I40E_NONDMA_TO_NONDMA);
1143         else
1144                 status = I40E_ERR_INVALID_MAC_ADDR;
1145
1146         return status;
1147 }
1148
1149 /**
1150  * i40e_pre_tx_queue_cfg - pre tx queue configure
1151  * @hw: pointer to the HW structure
1152  * @queue: target pf queue index
1153  * @enable: state change request
1154  *
1155  * Handles hw requirement to indicate intention to enable
1156  * or disable target queue.
1157  **/
1158 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1159 {
1160         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1161         u32 reg_block = 0;
1162         u32 reg_val;
1163
1164         if (abs_queue_idx >= 128) {
1165                 reg_block = abs_queue_idx / 128;
1166                 abs_queue_idx %= 128;
1167         }
1168
1169         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1170         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1171         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1172
1173         if (enable)
1174                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1175         else
1176                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1177
1178         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1179 }
1180
1181 /**
1182  * i40e_get_san_mac_addr - get SAN MAC address
1183  * @hw: pointer to the HW structure
1184  * @mac_addr: pointer to SAN MAC address
1185  *
1186  * Reads the adapter's SAN MAC address from NVM
1187  **/
1188 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1189                                             u8 *mac_addr)
1190 {
1191         struct i40e_aqc_mac_address_read_data addrs;
1192         enum i40e_status_code status;
1193         u16 flags = 0;
1194
1195         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1196         if (status)
1197                 return status;
1198
1199         if (flags & I40E_AQC_SAN_ADDR_VALID)
1200                 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac),
1201                         I40E_NONDMA_TO_NONDMA);
1202         else
1203                 status = I40E_ERR_INVALID_MAC_ADDR;
1204
1205         return status;
1206 }
1207
1208 /**
1209  *  i40e_read_pba_string - Reads part number string from EEPROM
1210  *  @hw: pointer to hardware structure
1211  *  @pba_num: stores the part number string from the EEPROM
1212  *  @pba_num_size: part number string buffer length
1213  *
1214  *  Reads the part number string from the EEPROM.
1215  **/
1216 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1217                                             u32 pba_num_size)
1218 {
1219         enum i40e_status_code status = I40E_SUCCESS;
1220         u16 pba_word = 0;
1221         u16 pba_size = 0;
1222         u16 pba_ptr = 0;
1223         u16 i = 0;
1224
1225         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1226         if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1227                 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1228                 return status;
1229         }
1230
1231         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1232         if (status != I40E_SUCCESS) {
1233                 DEBUGOUT("Failed to read PBA Block pointer.\n");
1234                 return status;
1235         }
1236
1237         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1238         if (status != I40E_SUCCESS) {
1239                 DEBUGOUT("Failed to read PBA Block size.\n");
1240                 return status;
1241         }
1242
1243         /* Subtract one to get PBA word count (PBA Size word is included in
1244          * total size)
1245          */
1246         pba_size--;
1247         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1248                 DEBUGOUT("Buffer to small for PBA data.\n");
1249                 return I40E_ERR_PARAM;
1250         }
1251
1252         for (i = 0; i < pba_size; i++) {
1253                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1254                 if (status != I40E_SUCCESS) {
1255                         DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1256                         return status;
1257                 }
1258
1259                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1260                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1261         }
1262         pba_num[(pba_size * 2)] = '\0';
1263
1264         return status;
1265 }
1266
1267 /**
1268  * i40e_get_media_type - Gets media type
1269  * @hw: pointer to the hardware structure
1270  **/
1271 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1272 {
1273         enum i40e_media_type media;
1274
1275         switch (hw->phy.link_info.phy_type) {
1276         case I40E_PHY_TYPE_10GBASE_SR:
1277         case I40E_PHY_TYPE_10GBASE_LR:
1278         case I40E_PHY_TYPE_1000BASE_SX:
1279         case I40E_PHY_TYPE_1000BASE_LX:
1280         case I40E_PHY_TYPE_40GBASE_SR4:
1281         case I40E_PHY_TYPE_40GBASE_LR4:
1282         case I40E_PHY_TYPE_25GBASE_LR:
1283         case I40E_PHY_TYPE_25GBASE_SR:
1284                 media = I40E_MEDIA_TYPE_FIBER;
1285                 break;
1286         case I40E_PHY_TYPE_100BASE_TX:
1287         case I40E_PHY_TYPE_1000BASE_T:
1288         case I40E_PHY_TYPE_10GBASE_T:
1289                 media = I40E_MEDIA_TYPE_BASET;
1290                 break;
1291         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1292         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1293         case I40E_PHY_TYPE_10GBASE_CR1:
1294         case I40E_PHY_TYPE_40GBASE_CR4:
1295         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1296         case I40E_PHY_TYPE_40GBASE_AOC:
1297         case I40E_PHY_TYPE_10GBASE_AOC:
1298         case I40E_PHY_TYPE_25GBASE_CR:
1299         case I40E_PHY_TYPE_25GBASE_AOC:
1300         case I40E_PHY_TYPE_25GBASE_ACC:
1301                 media = I40E_MEDIA_TYPE_DA;
1302                 break;
1303         case I40E_PHY_TYPE_1000BASE_KX:
1304         case I40E_PHY_TYPE_10GBASE_KX4:
1305         case I40E_PHY_TYPE_10GBASE_KR:
1306         case I40E_PHY_TYPE_40GBASE_KR4:
1307         case I40E_PHY_TYPE_20GBASE_KR2:
1308         case I40E_PHY_TYPE_25GBASE_KR:
1309                 media = I40E_MEDIA_TYPE_BACKPLANE;
1310                 break;
1311         case I40E_PHY_TYPE_SGMII:
1312         case I40E_PHY_TYPE_XAUI:
1313         case I40E_PHY_TYPE_XFI:
1314         case I40E_PHY_TYPE_XLAUI:
1315         case I40E_PHY_TYPE_XLPPI:
1316         default:
1317                 media = I40E_MEDIA_TYPE_UNKNOWN;
1318                 break;
1319         }
1320
1321         return media;
1322 }
1323
1324 #define I40E_PF_RESET_WAIT_COUNT        200
1325 /**
1326  * i40e_pf_reset - Reset the PF
1327  * @hw: pointer to the hardware structure
1328  *
1329  * Assuming someone else has triggered a global reset,
1330  * assure the global reset is complete and then reset the PF
1331  **/
1332 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1333 {
1334         u32 cnt = 0;
1335         u32 cnt1 = 0;
1336         u32 reg = 0;
1337         u32 grst_del;
1338
1339         /* Poll for Global Reset steady state in case of recent GRST.
1340          * The grst delay value is in 100ms units, and we'll wait a
1341          * couple counts longer to be sure we don't just miss the end.
1342          */
1343         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1344                         I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1345                         I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1346
1347         grst_del = grst_del * 20;
1348
1349         for (cnt = 0; cnt < grst_del; cnt++) {
1350                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1351                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1352                         break;
1353                 i40e_msec_delay(100);
1354         }
1355         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1356                 DEBUGOUT("Global reset polling failed to complete.\n");
1357                 return I40E_ERR_RESET_FAILED;
1358         }
1359
1360         /* Now Wait for the FW to be ready */
1361         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1362                 reg = rd32(hw, I40E_GLNVM_ULD);
1363                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1364                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1365                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1366                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1367                         DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1368                         break;
1369                 }
1370                 i40e_msec_delay(10);
1371         }
1372         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1373                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1374                 DEBUGOUT("wait for FW Reset complete timedout\n");
1375                 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1376                 return I40E_ERR_RESET_FAILED;
1377         }
1378
1379         /* If there was a Global Reset in progress when we got here,
1380          * we don't need to do the PF Reset
1381          */
1382         if (!cnt) {
1383                 reg = rd32(hw, I40E_PFGEN_CTRL);
1384                 wr32(hw, I40E_PFGEN_CTRL,
1385                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1386                 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1387                         reg = rd32(hw, I40E_PFGEN_CTRL);
1388                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1389                                 break;
1390                         i40e_msec_delay(1);
1391                 }
1392                 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1393                         DEBUGOUT("PF reset polling failed to complete.\n");
1394                         return I40E_ERR_RESET_FAILED;
1395                 }
1396         }
1397
1398         i40e_clear_pxe_mode(hw);
1399
1400
1401         return I40E_SUCCESS;
1402 }
1403
1404 /**
1405  * i40e_clear_hw - clear out any left over hw state
1406  * @hw: pointer to the hw struct
1407  *
1408  * Clear queues and interrupts, typically called at init time,
1409  * but after the capabilities have been found so we know how many
1410  * queues and msix vectors have been allocated.
1411  **/
1412 void i40e_clear_hw(struct i40e_hw *hw)
1413 {
1414         u32 num_queues, base_queue;
1415         u32 num_pf_int;
1416         u32 num_vf_int;
1417         u32 num_vfs;
1418         u32 i, j;
1419         u32 val;
1420         u32 eol = 0x7ff;
1421
1422         /* get number of interrupts, queues, and vfs */
1423         val = rd32(hw, I40E_GLPCI_CNF2);
1424         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1425                         I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1426         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1427                         I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1428
1429         val = rd32(hw, I40E_PFLAN_QALLOC);
1430         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1431                         I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1432         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1433                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1434         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1435                 num_queues = (j - base_queue) + 1;
1436         else
1437                 num_queues = 0;
1438
1439         val = rd32(hw, I40E_PF_VT_PFALLOC);
1440         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1441                         I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1442         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1443                         I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1444         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1445                 num_vfs = (j - i) + 1;
1446         else
1447                 num_vfs = 0;
1448
1449         /* stop all the interrupts */
1450         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1451         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1452         for (i = 0; i < num_pf_int - 2; i++)
1453                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1454
1455         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1456         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1457         wr32(hw, I40E_PFINT_LNKLST0, val);
1458         for (i = 0; i < num_pf_int - 2; i++)
1459                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1460         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1461         for (i = 0; i < num_vfs; i++)
1462                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1463         for (i = 0; i < num_vf_int - 2; i++)
1464                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1465
1466         /* warn the HW of the coming Tx disables */
1467         for (i = 0; i < num_queues; i++) {
1468                 u32 abs_queue_idx = base_queue + i;
1469                 u32 reg_block = 0;
1470
1471                 if (abs_queue_idx >= 128) {
1472                         reg_block = abs_queue_idx / 128;
1473                         abs_queue_idx %= 128;
1474                 }
1475
1476                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1477                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1478                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1479                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1480
1481                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1482         }
1483         i40e_usec_delay(400);
1484
1485         /* stop all the queues */
1486         for (i = 0; i < num_queues; i++) {
1487                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1488                 wr32(hw, I40E_QTX_ENA(i), 0);
1489                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1490                 wr32(hw, I40E_QRX_ENA(i), 0);
1491         }
1492
1493         /* short wait for all queue disables to settle */
1494         i40e_usec_delay(50);
1495 }
1496
1497 /**
1498  * i40e_clear_pxe_mode - clear pxe operations mode
1499  * @hw: pointer to the hw struct
1500  *
1501  * Make sure all PXE mode settings are cleared, including things
1502  * like descriptor fetch/write-back mode.
1503  **/
1504 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1505 {
1506         if (i40e_check_asq_alive(hw))
1507                 i40e_aq_clear_pxe_mode(hw, NULL);
1508 }
1509
1510 /**
1511  * i40e_led_is_mine - helper to find matching led
1512  * @hw: pointer to the hw struct
1513  * @idx: index into GPIO registers
1514  *
1515  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1516  */
1517 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1518 {
1519         u32 gpio_val = 0;
1520         u32 port;
1521
1522         if (!hw->func_caps.led[idx])
1523                 return 0;
1524
1525         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1526         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1527                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1528
1529         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1530          * if it is not our port then ignore
1531          */
1532         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1533             (port != hw->port))
1534                 return 0;
1535
1536         return gpio_val;
1537 }
1538
1539 #define I40E_COMBINED_ACTIVITY 0xA
1540 #define I40E_FILTER_ACTIVITY 0xE
1541 #define I40E_LINK_ACTIVITY 0xC
1542 #define I40E_MAC_ACTIVITY 0xD
1543 #define I40E_LED0 22
1544
1545 /**
1546  * i40e_led_get - return current on/off mode
1547  * @hw: pointer to the hw struct
1548  *
1549  * The value returned is the 'mode' field as defined in the
1550  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1551  * values are variations of possible behaviors relating to
1552  * blink, link, and wire.
1553  **/
1554 u32 i40e_led_get(struct i40e_hw *hw)
1555 {
1556         u32 current_mode = 0;
1557         u32 mode = 0;
1558         int i;
1559
1560         /* as per the documentation GPIO 22-29 are the LED
1561          * GPIO pins named LED0..LED7
1562          */
1563         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1564                 u32 gpio_val = i40e_led_is_mine(hw, i);
1565
1566                 if (!gpio_val)
1567                         continue;
1568
1569                 /* ignore gpio LED src mode entries related to the activity
1570                  *  LEDs
1571                  */
1572                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1573                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1574                 switch (current_mode) {
1575                 case I40E_COMBINED_ACTIVITY:
1576                 case I40E_FILTER_ACTIVITY:
1577                 case I40E_MAC_ACTIVITY:
1578                         continue;
1579                 default:
1580                         break;
1581                 }
1582
1583                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1584                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1585                 break;
1586         }
1587
1588         return mode;
1589 }
1590
1591 /**
1592  * i40e_led_set - set new on/off mode
1593  * @hw: pointer to the hw struct
1594  * @mode: 0=off, 0xf=on (else see manual for mode details)
1595  * @blink: true if the LED should blink when on, false if steady
1596  *
1597  * if this function is used to turn on the blink it should
1598  * be used to disable the blink when restoring the original state.
1599  **/
1600 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1601 {
1602         u32 current_mode = 0;
1603         int i;
1604
1605         if (mode & 0xfffffff0)
1606                 DEBUGOUT1("invalid mode passed in %X\n", mode);
1607
1608         /* as per the documentation GPIO 22-29 are the LED
1609          * GPIO pins named LED0..LED7
1610          */
1611         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1612                 u32 gpio_val = i40e_led_is_mine(hw, i);
1613
1614                 if (!gpio_val)
1615                         continue;
1616
1617                 /* ignore gpio LED src mode entries related to the activity
1618                  * LEDs
1619                  */
1620                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1621                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1622                 switch (current_mode) {
1623                 case I40E_COMBINED_ACTIVITY:
1624                 case I40E_FILTER_ACTIVITY:
1625                 case I40E_MAC_ACTIVITY:
1626                         continue;
1627                 default:
1628                         break;
1629                 }
1630
1631                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1632                 /* this & is a bit of paranoia, but serves as a range check */
1633                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1634                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1635
1636                 if (mode == I40E_LINK_ACTIVITY)
1637                         blink = false;
1638
1639                 if (blink)
1640                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1641                 else
1642                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1643
1644                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1645                 break;
1646         }
1647 }
1648
1649 /* Admin command wrappers */
1650
1651 /**
1652  * i40e_aq_get_phy_capabilities
1653  * @hw: pointer to the hw struct
1654  * @abilities: structure for PHY capabilities to be filled
1655  * @qualified_modules: report Qualified Modules
1656  * @report_init: report init capabilities (active are default)
1657  * @cmd_details: pointer to command details structure or NULL
1658  *
1659  * Returns the various PHY abilities supported on the Port.
1660  **/
1661 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1662                         bool qualified_modules, bool report_init,
1663                         struct i40e_aq_get_phy_abilities_resp *abilities,
1664                         struct i40e_asq_cmd_details *cmd_details)
1665 {
1666         struct i40e_aq_desc desc;
1667         enum i40e_status_code status;
1668         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1669
1670         if (!abilities)
1671                 return I40E_ERR_PARAM;
1672
1673         i40e_fill_default_direct_cmd_desc(&desc,
1674                                           i40e_aqc_opc_get_phy_abilities);
1675
1676         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1677         if (abilities_size > I40E_AQ_LARGE_BUF)
1678                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1679
1680         if (qualified_modules)
1681                 desc.params.external.param0 |=
1682                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1683
1684         if (report_init)
1685                 desc.params.external.param0 |=
1686                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1687
1688         status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1689                                     cmd_details);
1690
1691         if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1692                 status = I40E_ERR_UNKNOWN_PHY;
1693
1694         if (report_init) {
1695                 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1696                     hw->aq.api_min_ver >= 7) {
1697                         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1698                 } else {
1699                         hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1700                         hw->phy.phy_types |=
1701                                         ((u64)abilities->phy_type_ext << 32);
1702                 }
1703         }
1704
1705         return status;
1706 }
1707
1708 /**
1709  * i40e_aq_set_phy_config
1710  * @hw: pointer to the hw struct
1711  * @config: structure with PHY configuration to be set
1712  * @cmd_details: pointer to command details structure or NULL
1713  *
1714  * Set the various PHY configuration parameters
1715  * supported on the Port.One or more of the Set PHY config parameters may be
1716  * ignored in an MFP mode as the PF may not have the privilege to set some
1717  * of the PHY Config parameters. This status will be indicated by the
1718  * command response.
1719  **/
1720 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1721                                 struct i40e_aq_set_phy_config *config,
1722                                 struct i40e_asq_cmd_details *cmd_details)
1723 {
1724         struct i40e_aq_desc desc;
1725         struct i40e_aq_set_phy_config *cmd =
1726                 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1727         enum i40e_status_code status;
1728
1729         if (!config)
1730                 return I40E_ERR_PARAM;
1731
1732         i40e_fill_default_direct_cmd_desc(&desc,
1733                                           i40e_aqc_opc_set_phy_config);
1734
1735         *cmd = *config;
1736
1737         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1738
1739         return status;
1740 }
1741
1742 /**
1743  * i40e_set_fc
1744  * @hw: pointer to the hw struct
1745  *
1746  * Set the requested flow control mode using set_phy_config.
1747  **/
1748 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1749                                   bool atomic_restart)
1750 {
1751         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1752         struct i40e_aq_get_phy_abilities_resp abilities;
1753         struct i40e_aq_set_phy_config config;
1754         enum i40e_status_code status;
1755         u8 pause_mask = 0x0;
1756
1757         *aq_failures = 0x0;
1758
1759         switch (fc_mode) {
1760         case I40E_FC_FULL:
1761                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1762                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1763                 break;
1764         case I40E_FC_RX_PAUSE:
1765                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1766                 break;
1767         case I40E_FC_TX_PAUSE:
1768                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1769                 break;
1770         default:
1771                 break;
1772         }
1773
1774         /* Get the current phy config */
1775         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1776                                               NULL);
1777         if (status) {
1778                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1779                 return status;
1780         }
1781
1782         memset(&config, 0, sizeof(config));
1783         /* clear the old pause settings */
1784         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1785                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1786         /* set the new abilities */
1787         config.abilities |= pause_mask;
1788         /* If the abilities have changed, then set the new config */
1789         if (config.abilities != abilities.abilities) {
1790                 /* Auto restart link so settings take effect */
1791                 if (atomic_restart)
1792                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1793                 /* Copy over all the old settings */
1794                 config.phy_type = abilities.phy_type;
1795                 config.phy_type_ext = abilities.phy_type_ext;
1796                 config.link_speed = abilities.link_speed;
1797                 config.eee_capability = abilities.eee_capability;
1798                 config.eeer = abilities.eeer_val;
1799                 config.low_power_ctrl = abilities.d3_lpan;
1800                 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1801                                     I40E_AQ_PHY_FEC_CONFIG_MASK;
1802                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1803
1804                 if (status)
1805                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1806         }
1807         /* Update the link info */
1808         status = i40e_update_link_info(hw);
1809         if (status) {
1810                 /* Wait a little bit (on 40G cards it sometimes takes a really
1811                  * long time for link to come back from the atomic reset)
1812                  * and try once more
1813                  */
1814                 i40e_msec_delay(1000);
1815                 status = i40e_update_link_info(hw);
1816         }
1817         if (status)
1818                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1819
1820         return status;
1821 }
1822
1823 /**
1824  * i40e_aq_set_mac_config
1825  * @hw: pointer to the hw struct
1826  * @max_frame_size: Maximum Frame Size to be supported by the port
1827  * @crc_en: Tell HW to append a CRC to outgoing frames
1828  * @pacing: Pacing configurations
1829  * @cmd_details: pointer to command details structure or NULL
1830  *
1831  * Configure MAC settings for frame size, jumbo frame support and the
1832  * addition of a CRC by the hardware.
1833  **/
1834 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1835                                 u16 max_frame_size,
1836                                 bool crc_en, u16 pacing,
1837                                 struct i40e_asq_cmd_details *cmd_details)
1838 {
1839         struct i40e_aq_desc desc;
1840         struct i40e_aq_set_mac_config *cmd =
1841                 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1842         enum i40e_status_code status;
1843
1844         if (max_frame_size == 0)
1845                 return I40E_ERR_PARAM;
1846
1847         i40e_fill_default_direct_cmd_desc(&desc,
1848                                           i40e_aqc_opc_set_mac_config);
1849
1850         cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1851         cmd->params = ((u8)pacing & 0x0F) << 3;
1852         if (crc_en)
1853                 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1854
1855         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1856
1857         return status;
1858 }
1859
1860 /**
1861  * i40e_aq_clear_pxe_mode
1862  * @hw: pointer to the hw struct
1863  * @cmd_details: pointer to command details structure or NULL
1864  *
1865  * Tell the firmware that the driver is taking over from PXE
1866  **/
1867 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1868                         struct i40e_asq_cmd_details *cmd_details)
1869 {
1870         enum i40e_status_code status;
1871         struct i40e_aq_desc desc;
1872         struct i40e_aqc_clear_pxe *cmd =
1873                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1874
1875         i40e_fill_default_direct_cmd_desc(&desc,
1876                                           i40e_aqc_opc_clear_pxe_mode);
1877
1878         cmd->rx_cnt = 0x2;
1879
1880         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1881
1882         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1883
1884         return status;
1885 }
1886
1887 /**
1888  * i40e_aq_set_link_restart_an
1889  * @hw: pointer to the hw struct
1890  * @enable_link: if true: enable link, if false: disable link
1891  * @cmd_details: pointer to command details structure or NULL
1892  *
1893  * Sets up the link and restarts the Auto-Negotiation over the link.
1894  **/
1895 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1896                 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1897 {
1898         struct i40e_aq_desc desc;
1899         struct i40e_aqc_set_link_restart_an *cmd =
1900                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1901         enum i40e_status_code status;
1902
1903         i40e_fill_default_direct_cmd_desc(&desc,
1904                                           i40e_aqc_opc_set_link_restart_an);
1905
1906         cmd->command = I40E_AQ_PHY_RESTART_AN;
1907         if (enable_link)
1908                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1909         else
1910                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1911
1912         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1913
1914         return status;
1915 }
1916
1917 /**
1918  * i40e_aq_get_link_info
1919  * @hw: pointer to the hw struct
1920  * @enable_lse: enable/disable LinkStatusEvent reporting
1921  * @link: pointer to link status structure - optional
1922  * @cmd_details: pointer to command details structure or NULL
1923  *
1924  * Returns the link status of the adapter.
1925  **/
1926 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1927                                 bool enable_lse, struct i40e_link_status *link,
1928                                 struct i40e_asq_cmd_details *cmd_details)
1929 {
1930         struct i40e_aq_desc desc;
1931         struct i40e_aqc_get_link_status *resp =
1932                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1933         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1934         enum i40e_status_code status;
1935         bool tx_pause, rx_pause;
1936         u16 command_flags;
1937
1938         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1939
1940         if (enable_lse)
1941                 command_flags = I40E_AQ_LSE_ENABLE;
1942         else
1943                 command_flags = I40E_AQ_LSE_DISABLE;
1944         resp->command_flags = CPU_TO_LE16(command_flags);
1945
1946         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1947
1948         if (status != I40E_SUCCESS)
1949                 goto aq_get_link_info_exit;
1950
1951         /* save off old link status information */
1952         i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1953                     sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1954
1955         /* update link status */
1956         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1957         hw->phy.media_type = i40e_get_media_type(hw);
1958         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1959         hw_link_info->link_info = resp->link_info;
1960         hw_link_info->an_info = resp->an_info;
1961         hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
1962                                                  I40E_AQ_CONFIG_FEC_RS_ENA);
1963         hw_link_info->ext_info = resp->ext_info;
1964         hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
1965         hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1966         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1967
1968         /* update fc info */
1969         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1970         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1971         if (tx_pause & rx_pause)
1972                 hw->fc.current_mode = I40E_FC_FULL;
1973         else if (tx_pause)
1974                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1975         else if (rx_pause)
1976                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1977         else
1978                 hw->fc.current_mode = I40E_FC_NONE;
1979
1980         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1981                 hw_link_info->crc_enable = true;
1982         else
1983                 hw_link_info->crc_enable = false;
1984
1985         if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
1986                 hw_link_info->lse_enable = true;
1987         else
1988                 hw_link_info->lse_enable = false;
1989
1990         if ((hw->mac.type == I40E_MAC_XL710) &&
1991             (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1992              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1993                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1994
1995         if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1996             hw->aq.api_min_ver >= 7) {
1997                 hw->phy.phy_types = LE32_TO_CPU(*(__le32 *)resp->link_type);
1998                 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
1999         }
2000
2001         /* save link status information */
2002         if (link)
2003                 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
2004                             I40E_NONDMA_TO_NONDMA);
2005
2006         /* flag cleared so helper functions don't call AQ again */
2007         hw->phy.get_link_info = false;
2008
2009 aq_get_link_info_exit:
2010         return status;
2011 }
2012
2013 /**
2014  * i40e_aq_set_phy_int_mask
2015  * @hw: pointer to the hw struct
2016  * @mask: interrupt mask to be set
2017  * @cmd_details: pointer to command details structure or NULL
2018  *
2019  * Set link interrupt mask.
2020  **/
2021 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2022                                 u16 mask,
2023                                 struct i40e_asq_cmd_details *cmd_details)
2024 {
2025         struct i40e_aq_desc desc;
2026         struct i40e_aqc_set_phy_int_mask *cmd =
2027                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2028         enum i40e_status_code status;
2029
2030         i40e_fill_default_direct_cmd_desc(&desc,
2031                                           i40e_aqc_opc_set_phy_int_mask);
2032
2033         cmd->event_mask = CPU_TO_LE16(mask);
2034
2035         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2036
2037         return status;
2038 }
2039
2040 /**
2041  * i40e_aq_get_local_advt_reg
2042  * @hw: pointer to the hw struct
2043  * @advt_reg: local AN advertisement register value
2044  * @cmd_details: pointer to command details structure or NULL
2045  *
2046  * Get the Local AN advertisement register value.
2047  **/
2048 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2049                                 u64 *advt_reg,
2050                                 struct i40e_asq_cmd_details *cmd_details)
2051 {
2052         struct i40e_aq_desc desc;
2053         struct i40e_aqc_an_advt_reg *resp =
2054                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2055         enum i40e_status_code status;
2056
2057         i40e_fill_default_direct_cmd_desc(&desc,
2058                                           i40e_aqc_opc_get_local_advt_reg);
2059
2060         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2061
2062         if (status != I40E_SUCCESS)
2063                 goto aq_get_local_advt_reg_exit;
2064
2065         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2066         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2067
2068 aq_get_local_advt_reg_exit:
2069         return status;
2070 }
2071
2072 /**
2073  * i40e_aq_set_local_advt_reg
2074  * @hw: pointer to the hw struct
2075  * @advt_reg: local AN advertisement register value
2076  * @cmd_details: pointer to command details structure or NULL
2077  *
2078  * Get the Local AN advertisement register value.
2079  **/
2080 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2081                                 u64 advt_reg,
2082                                 struct i40e_asq_cmd_details *cmd_details)
2083 {
2084         struct i40e_aq_desc desc;
2085         struct i40e_aqc_an_advt_reg *cmd =
2086                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2087         enum i40e_status_code status;
2088
2089         i40e_fill_default_direct_cmd_desc(&desc,
2090                                           i40e_aqc_opc_get_local_advt_reg);
2091
2092         cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2093         cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2094
2095         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2096
2097         return status;
2098 }
2099
2100 /**
2101  * i40e_aq_get_partner_advt
2102  * @hw: pointer to the hw struct
2103  * @advt_reg: AN partner advertisement register value
2104  * @cmd_details: pointer to command details structure or NULL
2105  *
2106  * Get the link partner AN advertisement register value.
2107  **/
2108 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2109                                 u64 *advt_reg,
2110                                 struct i40e_asq_cmd_details *cmd_details)
2111 {
2112         struct i40e_aq_desc desc;
2113         struct i40e_aqc_an_advt_reg *resp =
2114                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2115         enum i40e_status_code status;
2116
2117         i40e_fill_default_direct_cmd_desc(&desc,
2118                                           i40e_aqc_opc_get_partner_advt);
2119
2120         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2121
2122         if (status != I40E_SUCCESS)
2123                 goto aq_get_partner_advt_exit;
2124
2125         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2126         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2127
2128 aq_get_partner_advt_exit:
2129         return status;
2130 }
2131
2132 /**
2133  * i40e_aq_set_lb_modes
2134  * @hw: pointer to the hw struct
2135  * @lb_modes: loopback mode to be set
2136  * @cmd_details: pointer to command details structure or NULL
2137  *
2138  * Sets loopback modes.
2139  **/
2140 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2141                                 u16 lb_modes,
2142                                 struct i40e_asq_cmd_details *cmd_details)
2143 {
2144         struct i40e_aq_desc desc;
2145         struct i40e_aqc_set_lb_mode *cmd =
2146                 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2147         enum i40e_status_code status;
2148
2149         i40e_fill_default_direct_cmd_desc(&desc,
2150                                           i40e_aqc_opc_set_lb_modes);
2151
2152         cmd->lb_mode = CPU_TO_LE16(lb_modes);
2153
2154         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2155
2156         return status;
2157 }
2158
2159 /**
2160  * i40e_aq_set_phy_debug
2161  * @hw: pointer to the hw struct
2162  * @cmd_flags: debug command flags
2163  * @cmd_details: pointer to command details structure or NULL
2164  *
2165  * Reset the external PHY.
2166  **/
2167 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2168                                 struct i40e_asq_cmd_details *cmd_details)
2169 {
2170         struct i40e_aq_desc desc;
2171         struct i40e_aqc_set_phy_debug *cmd =
2172                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2173         enum i40e_status_code status;
2174
2175         i40e_fill_default_direct_cmd_desc(&desc,
2176                                           i40e_aqc_opc_set_phy_debug);
2177
2178         cmd->command_flags = cmd_flags;
2179
2180         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2181
2182         return status;
2183 }
2184
2185 /**
2186  * i40e_aq_add_vsi
2187  * @hw: pointer to the hw struct
2188  * @vsi_ctx: pointer to a vsi context struct
2189  * @cmd_details: pointer to command details structure or NULL
2190  *
2191  * Add a VSI context to the hardware.
2192 **/
2193 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2194                                 struct i40e_vsi_context *vsi_ctx,
2195                                 struct i40e_asq_cmd_details *cmd_details)
2196 {
2197         struct i40e_aq_desc desc;
2198         struct i40e_aqc_add_get_update_vsi *cmd =
2199                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2200         struct i40e_aqc_add_get_update_vsi_completion *resp =
2201                 (struct i40e_aqc_add_get_update_vsi_completion *)
2202                 &desc.params.raw;
2203         enum i40e_status_code status;
2204
2205         i40e_fill_default_direct_cmd_desc(&desc,
2206                                           i40e_aqc_opc_add_vsi);
2207
2208         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2209         cmd->connection_type = vsi_ctx->connection_type;
2210         cmd->vf_id = vsi_ctx->vf_num;
2211         cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2212
2213         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2214
2215         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2216                                     sizeof(vsi_ctx->info), cmd_details);
2217
2218         if (status != I40E_SUCCESS)
2219                 goto aq_add_vsi_exit;
2220
2221         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2222         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2223         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2224         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2225
2226 aq_add_vsi_exit:
2227         return status;
2228 }
2229
2230 /**
2231  * i40e_aq_set_default_vsi
2232  * @hw: pointer to the hw struct
2233  * @seid: vsi number
2234  * @cmd_details: pointer to command details structure or NULL
2235  **/
2236 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2237                                 u16 seid,
2238                                 struct i40e_asq_cmd_details *cmd_details)
2239 {
2240         struct i40e_aq_desc desc;
2241         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2242                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2243                 &desc.params.raw;
2244         enum i40e_status_code status;
2245
2246         i40e_fill_default_direct_cmd_desc(&desc,
2247                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2248
2249         cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2250         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2251         cmd->seid = CPU_TO_LE16(seid);
2252
2253         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2254
2255         return status;
2256 }
2257
2258 /**
2259  * i40e_aq_clear_default_vsi
2260  * @hw: pointer to the hw struct
2261  * @seid: vsi number
2262  * @cmd_details: pointer to command details structure or NULL
2263  **/
2264 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2265                                 u16 seid,
2266                                 struct i40e_asq_cmd_details *cmd_details)
2267 {
2268         struct i40e_aq_desc desc;
2269         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2270                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2271                 &desc.params.raw;
2272         enum i40e_status_code status;
2273
2274         i40e_fill_default_direct_cmd_desc(&desc,
2275                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2276
2277         cmd->promiscuous_flags = CPU_TO_LE16(0);
2278         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2279         cmd->seid = CPU_TO_LE16(seid);
2280
2281         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2282
2283         return status;
2284 }
2285
2286 /**
2287  * i40e_aq_set_vsi_unicast_promiscuous
2288  * @hw: pointer to the hw struct
2289  * @seid: vsi number
2290  * @set: set unicast promiscuous enable/disable
2291  * @cmd_details: pointer to command details structure or NULL
2292  * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2293  **/
2294 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2295                                 u16 seid, bool set,
2296                                 struct i40e_asq_cmd_details *cmd_details,
2297                                 bool rx_only_promisc)
2298 {
2299         struct i40e_aq_desc desc;
2300         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2301                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2302         enum i40e_status_code status;
2303         u16 flags = 0;
2304
2305         i40e_fill_default_direct_cmd_desc(&desc,
2306                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2307
2308         if (set) {
2309                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2310                 if (rx_only_promisc &&
2311                     (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2312                      (hw->aq.api_maj_ver > 1)))
2313                         flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2314         }
2315
2316         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2317
2318         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2319         if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2320              (hw->aq.api_maj_ver > 1))
2321                 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2322
2323         cmd->seid = CPU_TO_LE16(seid);
2324         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2325
2326         return status;
2327 }
2328
2329 /**
2330  * i40e_aq_set_vsi_multicast_promiscuous
2331  * @hw: pointer to the hw struct
2332  * @seid: vsi number
2333  * @set: set multicast promiscuous enable/disable
2334  * @cmd_details: pointer to command details structure or NULL
2335  **/
2336 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2337                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2338 {
2339         struct i40e_aq_desc desc;
2340         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2341                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2342         enum i40e_status_code status;
2343         u16 flags = 0;
2344
2345         i40e_fill_default_direct_cmd_desc(&desc,
2346                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2347
2348         if (set)
2349                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2350
2351         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2352
2353         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2354
2355         cmd->seid = CPU_TO_LE16(seid);
2356         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2357
2358         return status;
2359 }
2360
2361 /**
2362 * i40e_aq_set_vsi_full_promiscuous
2363 * @hw: pointer to the hw struct
2364 * @seid: VSI number
2365 * @set: set promiscuous enable/disable
2366 * @cmd_details: pointer to command details structure or NULL
2367 **/
2368 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw,
2369                                 u16 seid, bool set,
2370                                 struct i40e_asq_cmd_details *cmd_details)
2371 {
2372         struct i40e_aq_desc desc;
2373         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2374                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2375         enum i40e_status_code status;
2376         u16 flags = 0;
2377
2378         i40e_fill_default_direct_cmd_desc(&desc,
2379                 i40e_aqc_opc_set_vsi_promiscuous_modes);
2380
2381         if (set)
2382                 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2383                         I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2384                         I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2385
2386         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2387
2388         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2389                                        I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2390                                        I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2391
2392         cmd->seid = CPU_TO_LE16(seid);
2393         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2394
2395         return status;
2396 }
2397
2398 /**
2399  * i40e_aq_set_vsi_mc_promisc_on_vlan
2400  * @hw: pointer to the hw struct
2401  * @seid: vsi number
2402  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2403  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2404  * @cmd_details: pointer to command details structure or NULL
2405  **/
2406 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2407                                 u16 seid, bool enable, u16 vid,
2408                                 struct i40e_asq_cmd_details *cmd_details)
2409 {
2410         struct i40e_aq_desc desc;
2411         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2412                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2413         enum i40e_status_code status;
2414         u16 flags = 0;
2415
2416         i40e_fill_default_direct_cmd_desc(&desc,
2417                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2418
2419         if (enable)
2420                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2421
2422         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2423         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2424         cmd->seid = CPU_TO_LE16(seid);
2425         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2426
2427         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2428
2429         return status;
2430 }
2431
2432 /**
2433  * i40e_aq_set_vsi_uc_promisc_on_vlan
2434  * @hw: pointer to the hw struct
2435  * @seid: vsi number
2436  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2437  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2438  * @cmd_details: pointer to command details structure or NULL
2439  **/
2440 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2441                                 u16 seid, bool enable, u16 vid,
2442                                 struct i40e_asq_cmd_details *cmd_details)
2443 {
2444         struct i40e_aq_desc desc;
2445         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2446                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2447         enum i40e_status_code status;
2448         u16 flags = 0;
2449
2450         i40e_fill_default_direct_cmd_desc(&desc,
2451                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2452
2453         if (enable)
2454                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2455
2456         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2457         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2458         cmd->seid = CPU_TO_LE16(seid);
2459         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2460
2461         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2462
2463         return status;
2464 }
2465
2466 /**
2467  * i40e_aq_set_vsi_bc_promisc_on_vlan
2468  * @hw: pointer to the hw struct
2469  * @seid: vsi number
2470  * @enable: set broadcast promiscuous enable/disable for a given VLAN
2471  * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2472  * @cmd_details: pointer to command details structure or NULL
2473  **/
2474 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2475                                 u16 seid, bool enable, u16 vid,
2476                                 struct i40e_asq_cmd_details *cmd_details)
2477 {
2478         struct i40e_aq_desc desc;
2479         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2480                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2481         enum i40e_status_code status;
2482         u16 flags = 0;
2483
2484         i40e_fill_default_direct_cmd_desc(&desc,
2485                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2486
2487         if (enable)
2488                 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2489
2490         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2491         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2492         cmd->seid = CPU_TO_LE16(seid);
2493         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2494
2495         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2496
2497         return status;
2498 }
2499
2500 /**
2501  * i40e_aq_set_vsi_broadcast
2502  * @hw: pointer to the hw struct
2503  * @seid: vsi number
2504  * @set_filter: true to set filter, false to clear filter
2505  * @cmd_details: pointer to command details structure or NULL
2506  *
2507  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2508  **/
2509 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2510                                 u16 seid, bool set_filter,
2511                                 struct i40e_asq_cmd_details *cmd_details)
2512 {
2513         struct i40e_aq_desc desc;
2514         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2515                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2516         enum i40e_status_code status;
2517
2518         i40e_fill_default_direct_cmd_desc(&desc,
2519                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2520
2521         if (set_filter)
2522                 cmd->promiscuous_flags
2523                             |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2524         else
2525                 cmd->promiscuous_flags
2526                             &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2527
2528         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2529         cmd->seid = CPU_TO_LE16(seid);
2530         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2531
2532         return status;
2533 }
2534
2535 /**
2536  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2537  * @hw: pointer to the hw struct
2538  * @seid: vsi number
2539  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2540  * @cmd_details: pointer to command details structure or NULL
2541  **/
2542 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2543                                 u16 seid, bool enable,
2544                                 struct i40e_asq_cmd_details *cmd_details)
2545 {
2546         struct i40e_aq_desc desc;
2547         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2548                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2549         enum i40e_status_code status;
2550         u16 flags = 0;
2551
2552         i40e_fill_default_direct_cmd_desc(&desc,
2553                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2554         if (enable)
2555                 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2556
2557         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2558         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2559         cmd->seid = CPU_TO_LE16(seid);
2560
2561         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2562
2563         return status;
2564 }
2565
2566 /**
2567  * i40e_get_vsi_params - get VSI configuration info
2568  * @hw: pointer to the hw struct
2569  * @vsi_ctx: pointer to a vsi context struct
2570  * @cmd_details: pointer to command details structure or NULL
2571  **/
2572 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2573                                 struct i40e_vsi_context *vsi_ctx,
2574                                 struct i40e_asq_cmd_details *cmd_details)
2575 {
2576         struct i40e_aq_desc desc;
2577         struct i40e_aqc_add_get_update_vsi *cmd =
2578                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2579         struct i40e_aqc_add_get_update_vsi_completion *resp =
2580                 (struct i40e_aqc_add_get_update_vsi_completion *)
2581                 &desc.params.raw;
2582         enum i40e_status_code status;
2583
2584         UNREFERENCED_1PARAMETER(cmd_details);
2585         i40e_fill_default_direct_cmd_desc(&desc,
2586                                           i40e_aqc_opc_get_vsi_parameters);
2587
2588         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2589
2590         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2591
2592         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2593                                     sizeof(vsi_ctx->info), NULL);
2594
2595         if (status != I40E_SUCCESS)
2596                 goto aq_get_vsi_params_exit;
2597
2598         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2599         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2600         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2601         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2602
2603 aq_get_vsi_params_exit:
2604         return status;
2605 }
2606
2607 /**
2608  * i40e_aq_update_vsi_params
2609  * @hw: pointer to the hw struct
2610  * @vsi_ctx: pointer to a vsi context struct
2611  * @cmd_details: pointer to command details structure or NULL
2612  *
2613  * Update a VSI context.
2614  **/
2615 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2616                                 struct i40e_vsi_context *vsi_ctx,
2617                                 struct i40e_asq_cmd_details *cmd_details)
2618 {
2619         struct i40e_aq_desc desc;
2620         struct i40e_aqc_add_get_update_vsi *cmd =
2621                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2622         struct i40e_aqc_add_get_update_vsi_completion *resp =
2623                 (struct i40e_aqc_add_get_update_vsi_completion *)
2624                 &desc.params.raw;
2625         enum i40e_status_code status;
2626
2627         i40e_fill_default_direct_cmd_desc(&desc,
2628                                           i40e_aqc_opc_update_vsi_parameters);
2629         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2630
2631         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2632
2633         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2634                                     sizeof(vsi_ctx->info), cmd_details);
2635
2636         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2637         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2638
2639         return status;
2640 }
2641
2642 /**
2643  * i40e_aq_get_switch_config
2644  * @hw: pointer to the hardware structure
2645  * @buf: pointer to the result buffer
2646  * @buf_size: length of input buffer
2647  * @start_seid: seid to start for the report, 0 == beginning
2648  * @cmd_details: pointer to command details structure or NULL
2649  *
2650  * Fill the buf with switch configuration returned from AdminQ command
2651  **/
2652 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2653                                 struct i40e_aqc_get_switch_config_resp *buf,
2654                                 u16 buf_size, u16 *start_seid,
2655                                 struct i40e_asq_cmd_details *cmd_details)
2656 {
2657         struct i40e_aq_desc desc;
2658         struct i40e_aqc_switch_seid *scfg =
2659                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2660         enum i40e_status_code status;
2661
2662         i40e_fill_default_direct_cmd_desc(&desc,
2663                                           i40e_aqc_opc_get_switch_config);
2664         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2665         if (buf_size > I40E_AQ_LARGE_BUF)
2666                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2667         scfg->seid = CPU_TO_LE16(*start_seid);
2668
2669         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2670         *start_seid = LE16_TO_CPU(scfg->seid);
2671
2672         return status;
2673 }
2674
2675 /**
2676  * i40e_aq_set_switch_config
2677  * @hw: pointer to the hardware structure
2678  * @flags: bit flag values to set
2679  * @valid_flags: which bit flags to set
2680  * @cmd_details: pointer to command details structure or NULL
2681  *
2682  * Set switch configuration bits
2683  **/
2684 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2685                                 u16 flags, u16 valid_flags,
2686                                 struct i40e_asq_cmd_details *cmd_details)
2687 {
2688         struct i40e_aq_desc desc;
2689         struct i40e_aqc_set_switch_config *scfg =
2690                 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2691         enum i40e_status_code status;
2692
2693         i40e_fill_default_direct_cmd_desc(&desc,
2694                                           i40e_aqc_opc_set_switch_config);
2695         scfg->flags = CPU_TO_LE16(flags);
2696         scfg->valid_flags = CPU_TO_LE16(valid_flags);
2697
2698         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2699
2700         return status;
2701 }
2702
2703 /**
2704  * i40e_aq_get_firmware_version
2705  * @hw: pointer to the hw struct
2706  * @fw_major_version: firmware major version
2707  * @fw_minor_version: firmware minor version
2708  * @fw_build: firmware build number
2709  * @api_major_version: major queue version
2710  * @api_minor_version: minor queue version
2711  * @cmd_details: pointer to command details structure or NULL
2712  *
2713  * Get the firmware version from the admin queue commands
2714  **/
2715 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2716                                 u16 *fw_major_version, u16 *fw_minor_version,
2717                                 u32 *fw_build,
2718                                 u16 *api_major_version, u16 *api_minor_version,
2719                                 struct i40e_asq_cmd_details *cmd_details)
2720 {
2721         struct i40e_aq_desc desc;
2722         struct i40e_aqc_get_version *resp =
2723                 (struct i40e_aqc_get_version *)&desc.params.raw;
2724         enum i40e_status_code status;
2725
2726         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2727
2728         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2729
2730         if (status == I40E_SUCCESS) {
2731                 if (fw_major_version != NULL)
2732                         *fw_major_version = LE16_TO_CPU(resp->fw_major);
2733                 if (fw_minor_version != NULL)
2734                         *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2735                 if (fw_build != NULL)
2736                         *fw_build = LE32_TO_CPU(resp->fw_build);
2737                 if (api_major_version != NULL)
2738                         *api_major_version = LE16_TO_CPU(resp->api_major);
2739                 if (api_minor_version != NULL)
2740                         *api_minor_version = LE16_TO_CPU(resp->api_minor);
2741
2742                 /* A workaround to fix the API version in SW */
2743                 if (api_major_version && api_minor_version &&
2744                     fw_major_version && fw_minor_version &&
2745                     ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2746                     (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2747                      (*fw_major_version > 4)))
2748                         *api_minor_version = 2;
2749         }
2750
2751         return status;
2752 }
2753
2754 /**
2755  * i40e_aq_send_driver_version
2756  * @hw: pointer to the hw struct
2757  * @dv: driver's major, minor version
2758  * @cmd_details: pointer to command details structure or NULL
2759  *
2760  * Send the driver version to the firmware
2761  **/
2762 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2763                                 struct i40e_driver_version *dv,
2764                                 struct i40e_asq_cmd_details *cmd_details)
2765 {
2766         struct i40e_aq_desc desc;
2767         struct i40e_aqc_driver_version *cmd =
2768                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2769         enum i40e_status_code status;
2770         u16 len;
2771
2772         if (dv == NULL)
2773                 return I40E_ERR_PARAM;
2774
2775         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2776
2777         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2778         cmd->driver_major_ver = dv->major_version;
2779         cmd->driver_minor_ver = dv->minor_version;
2780         cmd->driver_build_ver = dv->build_version;
2781         cmd->driver_subbuild_ver = dv->subbuild_version;
2782
2783         len = 0;
2784         while (len < sizeof(dv->driver_string) &&
2785                (dv->driver_string[len] < 0x80) &&
2786                dv->driver_string[len])
2787                 len++;
2788         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2789                                        len, cmd_details);
2790
2791         return status;
2792 }
2793
2794 /**
2795  * i40e_get_link_status - get status of the HW network link
2796  * @hw: pointer to the hw struct
2797  * @link_up: pointer to bool (true/false = linkup/linkdown)
2798  *
2799  * Variable link_up true if link is up, false if link is down.
2800  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2801  *
2802  * Side effect: LinkStatusEvent reporting becomes enabled
2803  **/
2804 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2805 {
2806         enum i40e_status_code status = I40E_SUCCESS;
2807
2808         if (hw->phy.get_link_info) {
2809                 status = i40e_update_link_info(hw);
2810
2811                 if (status != I40E_SUCCESS)
2812                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2813                                    status);
2814         }
2815
2816         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2817
2818         return status;
2819 }
2820
2821 /**
2822  * i40e_updatelink_status - update status of the HW network link
2823  * @hw: pointer to the hw struct
2824  **/
2825 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2826 {
2827         struct i40e_aq_get_phy_abilities_resp abilities;
2828         enum i40e_status_code status = I40E_SUCCESS;
2829
2830         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2831         if (status)
2832                 return status;
2833
2834         /* extra checking needed to ensure link info to user is timely */
2835         if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2836             ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2837              !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2838                 status = i40e_aq_get_phy_capabilities(hw, false, false,
2839                                                       &abilities, NULL);
2840                 if (status)
2841                         return status;
2842
2843                 hw->phy.link_info.req_fec_info =
2844                         abilities.fec_cfg_curr_mod_ext_info &
2845                         (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS);
2846
2847                 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2848                         sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2849         }
2850         return status;
2851 }
2852
2853
2854 /**
2855  * i40e_get_link_speed
2856  * @hw: pointer to the hw struct
2857  *
2858  * Returns the link speed of the adapter.
2859  **/
2860 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2861 {
2862         enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2863         enum i40e_status_code status = I40E_SUCCESS;
2864
2865         if (hw->phy.get_link_info) {
2866                 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2867
2868                 if (status != I40E_SUCCESS)
2869                         goto i40e_link_speed_exit;
2870         }
2871
2872         speed = hw->phy.link_info.link_speed;
2873
2874 i40e_link_speed_exit:
2875         return speed;
2876 }
2877
2878 /**
2879  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2880  * @hw: pointer to the hw struct
2881  * @uplink_seid: the MAC or other gizmo SEID
2882  * @downlink_seid: the VSI SEID
2883  * @enabled_tc: bitmap of TCs to be enabled
2884  * @default_port: true for default port VSI, false for control port
2885  * @veb_seid: pointer to where to put the resulting VEB SEID
2886  * @enable_stats: true to turn on VEB stats
2887  * @cmd_details: pointer to command details structure or NULL
2888  *
2889  * This asks the FW to add a VEB between the uplink and downlink
2890  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2891  **/
2892 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2893                                 u16 downlink_seid, u8 enabled_tc,
2894                                 bool default_port, u16 *veb_seid,
2895                                 bool enable_stats,
2896                                 struct i40e_asq_cmd_details *cmd_details)
2897 {
2898         struct i40e_aq_desc desc;
2899         struct i40e_aqc_add_veb *cmd =
2900                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2901         struct i40e_aqc_add_veb_completion *resp =
2902                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2903         enum i40e_status_code status;
2904         u16 veb_flags = 0;
2905
2906         /* SEIDs need to either both be set or both be 0 for floating VEB */
2907         if (!!uplink_seid != !!downlink_seid)
2908                 return I40E_ERR_PARAM;
2909
2910         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2911
2912         cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2913         cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2914         cmd->enable_tcs = enabled_tc;
2915         if (!uplink_seid)
2916                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2917         if (default_port)
2918                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2919         else
2920                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2921
2922         /* reverse logic here: set the bitflag to disable the stats */
2923         if (!enable_stats)
2924                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2925
2926         cmd->veb_flags = CPU_TO_LE16(veb_flags);
2927
2928         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2929
2930         if (!status && veb_seid)
2931                 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2932
2933         return status;
2934 }
2935
2936 /**
2937  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2938  * @hw: pointer to the hw struct
2939  * @veb_seid: the SEID of the VEB to query
2940  * @switch_id: the uplink switch id
2941  * @floating: set to true if the VEB is floating
2942  * @statistic_index: index of the stats counter block for this VEB
2943  * @vebs_used: number of VEB's used by function
2944  * @vebs_free: total VEB's not reserved by any function
2945  * @cmd_details: pointer to command details structure or NULL
2946  *
2947  * This retrieves the parameters for a particular VEB, specified by
2948  * uplink_seid, and returns them to the caller.
2949  **/
2950 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2951                                 u16 veb_seid, u16 *switch_id,
2952                                 bool *floating, u16 *statistic_index,
2953                                 u16 *vebs_used, u16 *vebs_free,
2954                                 struct i40e_asq_cmd_details *cmd_details)
2955 {
2956         struct i40e_aq_desc desc;
2957         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2958                 (struct i40e_aqc_get_veb_parameters_completion *)
2959                 &desc.params.raw;
2960         enum i40e_status_code status;
2961
2962         if (veb_seid == 0)
2963                 return I40E_ERR_PARAM;
2964
2965         i40e_fill_default_direct_cmd_desc(&desc,
2966                                           i40e_aqc_opc_get_veb_parameters);
2967         cmd_resp->seid = CPU_TO_LE16(veb_seid);
2968
2969         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2970         if (status)
2971                 goto get_veb_exit;
2972
2973         if (switch_id)
2974                 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2975         if (statistic_index)
2976                 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2977         if (vebs_used)
2978                 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2979         if (vebs_free)
2980                 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2981         if (floating) {
2982                 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2983
2984                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2985                         *floating = true;
2986                 else
2987                         *floating = false;
2988         }
2989
2990 get_veb_exit:
2991         return status;
2992 }
2993
2994 /**
2995  * i40e_aq_add_macvlan
2996  * @hw: pointer to the hw struct
2997  * @seid: VSI for the mac address
2998  * @mv_list: list of macvlans to be added
2999  * @count: length of the list
3000  * @cmd_details: pointer to command details structure or NULL
3001  *
3002  * Add MAC/VLAN addresses to the HW filtering
3003  **/
3004 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
3005                         struct i40e_aqc_add_macvlan_element_data *mv_list,
3006                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3007 {
3008         struct i40e_aq_desc desc;
3009         struct i40e_aqc_macvlan *cmd =
3010                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3011         enum i40e_status_code status;
3012         u16 buf_size;
3013         int i;
3014
3015         if (count == 0 || !mv_list || !hw)
3016                 return I40E_ERR_PARAM;
3017
3018         buf_size = count * sizeof(*mv_list);
3019
3020         /* prep the rest of the request */
3021         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
3022         cmd->num_addresses = CPU_TO_LE16(count);
3023         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3024         cmd->seid[1] = 0;
3025         cmd->seid[2] = 0;
3026
3027         for (i = 0; i < count; i++)
3028                 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
3029                         mv_list[i].flags |=
3030                             CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
3031
3032         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3033         if (buf_size > I40E_AQ_LARGE_BUF)
3034                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3035
3036         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3037                                        cmd_details);
3038
3039         return status;
3040 }
3041
3042 /**
3043  * i40e_aq_remove_macvlan
3044  * @hw: pointer to the hw struct
3045  * @seid: VSI for the mac address
3046  * @mv_list: list of macvlans to be removed
3047  * @count: length of the list
3048  * @cmd_details: pointer to command details structure or NULL
3049  *
3050  * Remove MAC/VLAN addresses from the HW filtering
3051  **/
3052 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
3053                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
3054                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3055 {
3056         struct i40e_aq_desc desc;
3057         struct i40e_aqc_macvlan *cmd =
3058                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3059         enum i40e_status_code status;
3060         u16 buf_size;
3061
3062         if (count == 0 || !mv_list || !hw)
3063                 return I40E_ERR_PARAM;
3064
3065         buf_size = count * sizeof(*mv_list);
3066
3067         /* prep the rest of the request */
3068         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
3069         cmd->num_addresses = CPU_TO_LE16(count);
3070         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3071         cmd->seid[1] = 0;
3072         cmd->seid[2] = 0;
3073
3074         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3075         if (buf_size > I40E_AQ_LARGE_BUF)
3076                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3077
3078         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3079                                        cmd_details);
3080
3081         return status;
3082 }
3083
3084 /**
3085  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3086  * @hw: pointer to the hw struct
3087  * @opcode: AQ opcode for add or delete mirror rule
3088  * @sw_seid: Switch SEID (to which rule refers)
3089  * @rule_type: Rule Type (ingress/egress/VLAN)
3090  * @id: Destination VSI SEID or Rule ID
3091  * @count: length of the list
3092  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3093  * @cmd_details: pointer to command details structure or NULL
3094  * @rule_id: Rule ID returned from FW
3095  * @rule_used: Number of rules used in internal switch
3096  * @rule_free: Number of rules free in internal switch
3097  *
3098  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3099  * VEBs/VEPA elements only
3100  **/
3101 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3102                         u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3103                         u16 count, __le16 *mr_list,
3104                         struct i40e_asq_cmd_details *cmd_details,
3105                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3106 {
3107         struct i40e_aq_desc desc;
3108         struct i40e_aqc_add_delete_mirror_rule *cmd =
3109                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3110         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3111         (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3112         enum i40e_status_code status;
3113         u16 buf_size;
3114
3115         buf_size = count * sizeof(*mr_list);
3116
3117         /* prep the rest of the request */
3118         i40e_fill_default_direct_cmd_desc(&desc, opcode);
3119         cmd->seid = CPU_TO_LE16(sw_seid);
3120         cmd->rule_type = CPU_TO_LE16(rule_type &
3121                                      I40E_AQC_MIRROR_RULE_TYPE_MASK);
3122         cmd->num_entries = CPU_TO_LE16(count);
3123         /* Dest VSI for add, rule_id for delete */
3124         cmd->destination = CPU_TO_LE16(id);
3125         if (mr_list) {
3126                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3127                                                 I40E_AQ_FLAG_RD));
3128                 if (buf_size > I40E_AQ_LARGE_BUF)
3129                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3130         }
3131
3132         status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3133                                        cmd_details);
3134         if (status == I40E_SUCCESS ||
3135             hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3136                 if (rule_id)
3137                         *rule_id = LE16_TO_CPU(resp->rule_id);
3138                 if (rules_used)
3139                         *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3140                 if (rules_free)
3141                         *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3142         }
3143         return status;
3144 }
3145
3146 /**
3147  * i40e_aq_add_mirrorrule - add a mirror rule
3148  * @hw: pointer to the hw struct
3149  * @sw_seid: Switch SEID (to which rule refers)
3150  * @rule_type: Rule Type (ingress/egress/VLAN)
3151  * @dest_vsi: SEID of VSI to which packets will be mirrored
3152  * @count: length of the list
3153  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3154  * @cmd_details: pointer to command details structure or NULL
3155  * @rule_id: Rule ID returned from FW
3156  * @rule_used: Number of rules used in internal switch
3157  * @rule_free: Number of rules free in internal switch
3158  *
3159  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3160  **/
3161 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3162                         u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3163                         struct i40e_asq_cmd_details *cmd_details,
3164                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3165 {
3166         if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3167             rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3168                 if (count == 0 || !mr_list)
3169                         return I40E_ERR_PARAM;
3170         }
3171
3172         return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3173                                   rule_type, dest_vsi, count, mr_list,
3174                                   cmd_details, rule_id, rules_used, rules_free);
3175 }
3176
3177 /**
3178  * i40e_aq_delete_mirrorrule - delete a mirror rule
3179  * @hw: pointer to the hw struct
3180  * @sw_seid: Switch SEID (to which rule refers)
3181  * @rule_type: Rule Type (ingress/egress/VLAN)
3182  * @count: length of the list
3183  * @rule_id: Rule ID that is returned in the receive desc as part of
3184  *              add_mirrorrule.
3185  * @mr_list: list of mirrored VLAN IDs to be removed
3186  * @cmd_details: pointer to command details structure or NULL
3187  * @rule_used: Number of rules used in internal switch
3188  * @rule_free: Number of rules free in internal switch
3189  *
3190  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3191  **/
3192 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3193                         u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3194                         struct i40e_asq_cmd_details *cmd_details,
3195                         u16 *rules_used, u16 *rules_free)
3196 {
3197         /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3198         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3199                 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3200                  * mirroring. For other rule_type, count and rule_type should
3201                  * not matter.
3202                  */
3203                 if (count == 0 || !mr_list)
3204                         return I40E_ERR_PARAM;
3205         }
3206
3207         return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3208                                   rule_type, rule_id, count, mr_list,
3209                                   cmd_details, NULL, rules_used, rules_free);
3210 }
3211
3212 /**
3213  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3214  * @hw: pointer to the hw struct
3215  * @seid: VSI for the vlan filters
3216  * @v_list: list of vlan filters to be added
3217  * @count: length of the list
3218  * @cmd_details: pointer to command details structure or NULL
3219  **/
3220 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3221                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3222                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3223 {
3224         struct i40e_aq_desc desc;
3225         struct i40e_aqc_macvlan *cmd =
3226                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3227         enum i40e_status_code status;
3228         u16 buf_size;
3229
3230         if (count == 0 || !v_list || !hw)
3231                 return I40E_ERR_PARAM;
3232
3233         buf_size = count * sizeof(*v_list);
3234
3235         /* prep the rest of the request */
3236         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3237         cmd->num_addresses = CPU_TO_LE16(count);
3238         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3239         cmd->seid[1] = 0;
3240         cmd->seid[2] = 0;
3241
3242         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3243         if (buf_size > I40E_AQ_LARGE_BUF)
3244                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3245
3246         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3247                                        cmd_details);
3248
3249         return status;
3250 }
3251
3252 /**
3253  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3254  * @hw: pointer to the hw struct
3255  * @seid: VSI for the vlan filters
3256  * @v_list: list of macvlans to be removed
3257  * @count: length of the list
3258  * @cmd_details: pointer to command details structure or NULL
3259  **/
3260 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3261                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3262                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3263 {
3264         struct i40e_aq_desc desc;
3265         struct i40e_aqc_macvlan *cmd =
3266                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3267         enum i40e_status_code status;
3268         u16 buf_size;
3269
3270         if (count == 0 || !v_list || !hw)
3271                 return I40E_ERR_PARAM;
3272
3273         buf_size = count * sizeof(*v_list);
3274
3275         /* prep the rest of the request */
3276         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3277         cmd->num_addresses = CPU_TO_LE16(count);
3278         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3279         cmd->seid[1] = 0;
3280         cmd->seid[2] = 0;
3281
3282         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3283         if (buf_size > I40E_AQ_LARGE_BUF)
3284                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3285
3286         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3287                                        cmd_details);
3288
3289         return status;
3290 }
3291
3292 /**
3293  * i40e_aq_send_msg_to_vf
3294  * @hw: pointer to the hardware structure
3295  * @vfid: vf id to send msg
3296  * @v_opcode: opcodes for VF-PF communication
3297  * @v_retval: return error code
3298  * @msg: pointer to the msg buffer
3299  * @msglen: msg length
3300  * @cmd_details: pointer to command details
3301  *
3302  * send msg to vf
3303  **/
3304 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3305                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3306                                 struct i40e_asq_cmd_details *cmd_details)
3307 {
3308         struct i40e_aq_desc desc;
3309         struct i40e_aqc_pf_vf_message *cmd =
3310                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3311         enum i40e_status_code status;
3312
3313         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3314         cmd->id = CPU_TO_LE32(vfid);
3315         desc.cookie_high = CPU_TO_LE32(v_opcode);
3316         desc.cookie_low = CPU_TO_LE32(v_retval);
3317         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3318         if (msglen) {
3319                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3320                                                 I40E_AQ_FLAG_RD));
3321                 if (msglen > I40E_AQ_LARGE_BUF)
3322                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3323                 desc.datalen = CPU_TO_LE16(msglen);
3324         }
3325         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3326
3327         return status;
3328 }
3329
3330 /**
3331  * i40e_aq_debug_read_register
3332  * @hw: pointer to the hw struct
3333  * @reg_addr: register address
3334  * @reg_val: register value
3335  * @cmd_details: pointer to command details structure or NULL
3336  *
3337  * Read the register using the admin queue commands
3338  **/
3339 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3340                                 u32 reg_addr, u64 *reg_val,
3341                                 struct i40e_asq_cmd_details *cmd_details)
3342 {
3343         struct i40e_aq_desc desc;
3344         struct i40e_aqc_debug_reg_read_write *cmd_resp =
3345                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3346         enum i40e_status_code status;
3347
3348         if (reg_val == NULL)
3349                 return I40E_ERR_PARAM;
3350
3351         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3352
3353         cmd_resp->address = CPU_TO_LE32(reg_addr);
3354
3355         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3356
3357         if (status == I40E_SUCCESS) {
3358                 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3359                            (u64)LE32_TO_CPU(cmd_resp->value_low);
3360         }
3361
3362         return status;
3363 }
3364
3365 /**
3366  * i40e_aq_debug_write_register
3367  * @hw: pointer to the hw struct
3368  * @reg_addr: register address
3369  * @reg_val: register value
3370  * @cmd_details: pointer to command details structure or NULL
3371  *
3372  * Write to a register using the admin queue commands
3373  **/
3374 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3375                                 u32 reg_addr, u64 reg_val,
3376                                 struct i40e_asq_cmd_details *cmd_details)
3377 {
3378         struct i40e_aq_desc desc;
3379         struct i40e_aqc_debug_reg_read_write *cmd =
3380                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3381         enum i40e_status_code status;
3382
3383         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3384
3385         cmd->address = CPU_TO_LE32(reg_addr);
3386         cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3387         cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3388
3389         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3390
3391         return status;
3392 }
3393
3394 /**
3395  * i40e_aq_request_resource
3396  * @hw: pointer to the hw struct
3397  * @resource: resource id
3398  * @access: access type
3399  * @sdp_number: resource number
3400  * @timeout: the maximum time in ms that the driver may hold the resource
3401  * @cmd_details: pointer to command details structure or NULL
3402  *
3403  * requests common resource using the admin queue commands
3404  **/
3405 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3406                                 enum i40e_aq_resources_ids resource,
3407                                 enum i40e_aq_resource_access_type access,
3408                                 u8 sdp_number, u64 *timeout,
3409                                 struct i40e_asq_cmd_details *cmd_details)
3410 {
3411         struct i40e_aq_desc desc;
3412         struct i40e_aqc_request_resource *cmd_resp =
3413                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3414         enum i40e_status_code status;
3415
3416         DEBUGFUNC("i40e_aq_request_resource");
3417
3418         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3419
3420         cmd_resp->resource_id = CPU_TO_LE16(resource);
3421         cmd_resp->access_type = CPU_TO_LE16(access);
3422         cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3423
3424         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3425         /* The completion specifies the maximum time in ms that the driver
3426          * may hold the resource in the Timeout field.
3427          * If the resource is held by someone else, the command completes with
3428          * busy return value and the timeout field indicates the maximum time
3429          * the current owner of the resource has to free it.
3430          */
3431         if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3432                 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3433
3434         return status;
3435 }
3436
3437 /**
3438  * i40e_aq_release_resource
3439  * @hw: pointer to the hw struct
3440  * @resource: resource id
3441  * @sdp_number: resource number
3442  * @cmd_details: pointer to command details structure or NULL
3443  *
3444  * release common resource using the admin queue commands
3445  **/
3446 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3447                                 enum i40e_aq_resources_ids resource,
3448                                 u8 sdp_number,
3449                                 struct i40e_asq_cmd_details *cmd_details)
3450 {
3451         struct i40e_aq_desc desc;
3452         struct i40e_aqc_request_resource *cmd =
3453                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3454         enum i40e_status_code status;
3455
3456         DEBUGFUNC("i40e_aq_release_resource");
3457
3458         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3459
3460         cmd->resource_id = CPU_TO_LE16(resource);
3461         cmd->resource_number = CPU_TO_LE32(sdp_number);
3462
3463         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3464
3465         return status;
3466 }
3467
3468 /**
3469  * i40e_aq_read_nvm
3470  * @hw: pointer to the hw struct
3471  * @module_pointer: module pointer location in words from the NVM beginning
3472  * @offset: byte offset from the module beginning
3473  * @length: length of the section to be read (in bytes from the offset)
3474  * @data: command buffer (size [bytes] = length)
3475  * @last_command: tells if this is the last command in a series
3476  * @cmd_details: pointer to command details structure or NULL
3477  *
3478  * Read the NVM using the admin queue commands
3479  **/
3480 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3481                                 u32 offset, u16 length, void *data,
3482                                 bool last_command,
3483                                 struct i40e_asq_cmd_details *cmd_details)
3484 {
3485         struct i40e_aq_desc desc;
3486         struct i40e_aqc_nvm_update *cmd =
3487                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3488         enum i40e_status_code status;
3489
3490         DEBUGFUNC("i40e_aq_read_nvm");
3491
3492         /* In offset the highest byte must be zeroed. */
3493         if (offset & 0xFF000000) {
3494                 status = I40E_ERR_PARAM;
3495                 goto i40e_aq_read_nvm_exit;
3496         }
3497
3498         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3499
3500         /* If this is the last command in a series, set the proper flag. */
3501         if (last_command)
3502                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3503         cmd->module_pointer = module_pointer;
3504         cmd->offset = CPU_TO_LE32(offset);
3505         cmd->length = CPU_TO_LE16(length);
3506
3507         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3508         if (length > I40E_AQ_LARGE_BUF)
3509                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3510
3511         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3512
3513 i40e_aq_read_nvm_exit:
3514         return status;
3515 }
3516
3517 /**
3518  * i40e_aq_read_nvm_config - read an nvm config block
3519  * @hw: pointer to the hw struct
3520  * @cmd_flags: NVM access admin command bits
3521  * @field_id: field or feature id
3522  * @data: buffer for result
3523  * @buf_size: buffer size
3524  * @element_count: pointer to count of elements read by FW
3525  * @cmd_details: pointer to command details structure or NULL
3526  **/
3527 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3528                                 u8 cmd_flags, u32 field_id, void *data,
3529                                 u16 buf_size, u16 *element_count,
3530                                 struct i40e_asq_cmd_details *cmd_details)
3531 {
3532         struct i40e_aq_desc desc;
3533         struct i40e_aqc_nvm_config_read *cmd =
3534                 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3535         enum i40e_status_code status;
3536
3537         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3538         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3539         if (buf_size > I40E_AQ_LARGE_BUF)
3540                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3541
3542         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3543         cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3544         if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3545                 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3546         else
3547                 cmd->element_id_msw = 0;
3548
3549         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3550
3551         if (!status && element_count)
3552                 *element_count = LE16_TO_CPU(cmd->element_count);
3553
3554         return status;
3555 }
3556
3557 /**
3558  * i40e_aq_write_nvm_config - write an nvm config block
3559  * @hw: pointer to the hw struct
3560  * @cmd_flags: NVM access admin command bits
3561  * @data: buffer for result
3562  * @buf_size: buffer size
3563  * @element_count: count of elements to be written
3564  * @cmd_details: pointer to command details structure or NULL
3565  **/
3566 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3567                                 u8 cmd_flags, void *data, u16 buf_size,
3568                                 u16 element_count,
3569                                 struct i40e_asq_cmd_details *cmd_details)
3570 {
3571         struct i40e_aq_desc desc;
3572         struct i40e_aqc_nvm_config_write *cmd =
3573                 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3574         enum i40e_status_code status;
3575
3576         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3577         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3578         if (buf_size > I40E_AQ_LARGE_BUF)
3579                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3580
3581         cmd->element_count = CPU_TO_LE16(element_count);
3582         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3583         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3584
3585         return status;
3586 }
3587
3588 /**
3589  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3590  * @hw: pointer to the hw struct
3591  * @cmd_details: pointer to command details structure or NULL
3592  **/
3593 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3594                                 void *buff, u16 buff_size,
3595                                 struct i40e_asq_cmd_details *cmd_details)
3596 {
3597         struct i40e_aq_desc desc;
3598         enum i40e_status_code status;
3599
3600         UNREFERENCED_2PARAMETER(buff, buff_size);
3601
3602         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3603         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3604         if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3605                 status = I40E_ERR_NOT_IMPLEMENTED;
3606
3607         return status;
3608 }
3609
3610 /**
3611  * i40e_aq_erase_nvm
3612  * @hw: pointer to the hw struct
3613  * @module_pointer: module pointer location in words from the NVM beginning
3614  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3615  * @length: length of the section to be erased (expressed in 4 KB)
3616  * @last_command: tells if this is the last command in a series
3617  * @cmd_details: pointer to command details structure or NULL
3618  *
3619  * Erase the NVM sector using the admin queue commands
3620  **/
3621 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3622                                 u32 offset, u16 length, bool last_command,
3623                                 struct i40e_asq_cmd_details *cmd_details)
3624 {
3625         struct i40e_aq_desc desc;
3626         struct i40e_aqc_nvm_update *cmd =
3627                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3628         enum i40e_status_code status;
3629
3630         DEBUGFUNC("i40e_aq_erase_nvm");
3631
3632         /* In offset the highest byte must be zeroed. */
3633         if (offset & 0xFF000000) {
3634                 status = I40E_ERR_PARAM;
3635                 goto i40e_aq_erase_nvm_exit;
3636         }
3637
3638         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3639
3640         /* If this is the last command in a series, set the proper flag. */
3641         if (last_command)
3642                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3643         cmd->module_pointer = module_pointer;
3644         cmd->offset = CPU_TO_LE32(offset);
3645         cmd->length = CPU_TO_LE16(length);
3646
3647         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3648
3649 i40e_aq_erase_nvm_exit:
3650         return status;
3651 }
3652
3653 /**
3654  * i40e_parse_discover_capabilities
3655  * @hw: pointer to the hw struct
3656  * @buff: pointer to a buffer containing device/function capability records
3657  * @cap_count: number of capability records in the list
3658  * @list_type_opc: type of capabilities list to parse
3659  *
3660  * Parse the device/function capabilities list.
3661  **/
3662 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3663                                      u32 cap_count,
3664                                      enum i40e_admin_queue_opc list_type_opc)
3665 {
3666         struct i40e_aqc_list_capabilities_element_resp *cap;
3667         u32 valid_functions, num_functions;
3668         u32 number, logical_id, phys_id;
3669         struct i40e_hw_capabilities *p;
3670         u8 major_rev;
3671         u32 i = 0;
3672         u16 id;
3673
3674         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3675
3676         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3677                 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3678         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3679                 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3680         else
3681                 return;
3682
3683         for (i = 0; i < cap_count; i++, cap++) {
3684                 id = LE16_TO_CPU(cap->id);
3685                 number = LE32_TO_CPU(cap->number);
3686                 logical_id = LE32_TO_CPU(cap->logical_id);
3687                 phys_id = LE32_TO_CPU(cap->phys_id);
3688                 major_rev = cap->major_rev;
3689
3690                 switch (id) {
3691                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3692                         p->switch_mode = number;
3693                         i40e_debug(hw, I40E_DEBUG_INIT,
3694                                    "HW Capability: Switch mode = %d\n",
3695                                    p->switch_mode);
3696                         break;
3697                 case I40E_AQ_CAP_ID_MNG_MODE:
3698                         p->management_mode = number;
3699                         if (major_rev > 1) {
3700                                 p->mng_protocols_over_mctp = logical_id;
3701                                 i40e_debug(hw, I40E_DEBUG_INIT,
3702                                            "HW Capability: Protocols over MCTP = %d\n",
3703                                            p->mng_protocols_over_mctp);
3704                         } else {
3705                                 p->mng_protocols_over_mctp = 0;
3706                         }
3707                         i40e_debug(hw, I40E_DEBUG_INIT,
3708                                    "HW Capability: Management Mode = %d\n",
3709                                    p->management_mode);
3710                         break;
3711                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3712                         p->npar_enable = number;
3713                         i40e_debug(hw, I40E_DEBUG_INIT,
3714                                    "HW Capability: NPAR enable = %d\n",
3715                                    p->npar_enable);
3716                         break;
3717                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3718                         p->os2bmc = number;
3719                         i40e_debug(hw, I40E_DEBUG_INIT,
3720                                    "HW Capability: OS2BMC = %d\n", p->os2bmc);
3721                         break;
3722                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3723                         p->valid_functions = number;
3724                         i40e_debug(hw, I40E_DEBUG_INIT,
3725                                    "HW Capability: Valid Functions = %d\n",
3726                                    p->valid_functions);
3727                         break;
3728                 case I40E_AQ_CAP_ID_SRIOV:
3729                         if (number == 1)
3730                                 p->sr_iov_1_1 = true;
3731                         i40e_debug(hw, I40E_DEBUG_INIT,
3732                                    "HW Capability: SR-IOV = %d\n",
3733                                    p->sr_iov_1_1);
3734                         break;
3735                 case I40E_AQ_CAP_ID_VF:
3736                         p->num_vfs = number;
3737                         p->vf_base_id = logical_id;
3738                         i40e_debug(hw, I40E_DEBUG_INIT,
3739                                    "HW Capability: VF count = %d\n",
3740                                    p->num_vfs);
3741                         i40e_debug(hw, I40E_DEBUG_INIT,
3742                                    "HW Capability: VF base_id = %d\n",
3743                                    p->vf_base_id);
3744                         break;
3745                 case I40E_AQ_CAP_ID_VMDQ:
3746                         if (number == 1)
3747                                 p->vmdq = true;
3748                         i40e_debug(hw, I40E_DEBUG_INIT,
3749                                    "HW Capability: VMDQ = %d\n", p->vmdq);
3750                         break;
3751                 case I40E_AQ_CAP_ID_8021QBG:
3752                         if (number == 1)
3753                                 p->evb_802_1_qbg = true;
3754                         i40e_debug(hw, I40E_DEBUG_INIT,
3755                                    "HW Capability: 802.1Qbg = %d\n", number);
3756                         break;
3757                 case I40E_AQ_CAP_ID_8021QBR:
3758                         if (number == 1)
3759                                 p->evb_802_1_qbh = true;
3760                         i40e_debug(hw, I40E_DEBUG_INIT,
3761                                    "HW Capability: 802.1Qbh = %d\n", number);
3762                         break;
3763                 case I40E_AQ_CAP_ID_VSI:
3764                         p->num_vsis = number;
3765                         i40e_debug(hw, I40E_DEBUG_INIT,
3766                                    "HW Capability: VSI count = %d\n",
3767                                    p->num_vsis);
3768                         break;
3769                 case I40E_AQ_CAP_ID_DCB:
3770                         if (number == 1) {
3771                                 p->dcb = true;
3772                                 p->enabled_tcmap = logical_id;
3773                                 p->maxtc = phys_id;
3774                         }
3775                         i40e_debug(hw, I40E_DEBUG_INIT,
3776                                    "HW Capability: DCB = %d\n", p->dcb);
3777                         i40e_debug(hw, I40E_DEBUG_INIT,
3778                                    "HW Capability: TC Mapping = %d\n",
3779                                    logical_id);
3780                         i40e_debug(hw, I40E_DEBUG_INIT,
3781                                    "HW Capability: TC Max = %d\n", p->maxtc);
3782                         break;
3783                 case I40E_AQ_CAP_ID_FCOE:
3784                         if (number == 1)
3785                                 p->fcoe = true;
3786                         i40e_debug(hw, I40E_DEBUG_INIT,
3787                                    "HW Capability: FCOE = %d\n", p->fcoe);
3788                         break;
3789                 case I40E_AQ_CAP_ID_ISCSI:
3790                         if (number == 1)
3791                                 p->iscsi = true;
3792                         i40e_debug(hw, I40E_DEBUG_INIT,
3793                                    "HW Capability: iSCSI = %d\n", p->iscsi);
3794                         break;
3795                 case I40E_AQ_CAP_ID_RSS:
3796                         p->rss = true;
3797                         p->rss_table_size = number;
3798                         p->rss_table_entry_width = logical_id;
3799                         i40e_debug(hw, I40E_DEBUG_INIT,
3800                                    "HW Capability: RSS = %d\n", p->rss);
3801                         i40e_debug(hw, I40E_DEBUG_INIT,
3802                                    "HW Capability: RSS table size = %d\n",
3803                                    p->rss_table_size);
3804                         i40e_debug(hw, I40E_DEBUG_INIT,
3805                                    "HW Capability: RSS table width = %d\n",
3806                                    p->rss_table_entry_width);
3807                         break;
3808                 case I40E_AQ_CAP_ID_RXQ:
3809                         p->num_rx_qp = number;
3810                         p->base_queue = phys_id;
3811                         i40e_debug(hw, I40E_DEBUG_INIT,
3812                                    "HW Capability: Rx QP = %d\n", number);
3813                         i40e_debug(hw, I40E_DEBUG_INIT,
3814                                    "HW Capability: base_queue = %d\n",
3815                                    p->base_queue);
3816                         break;
3817                 case I40E_AQ_CAP_ID_TXQ:
3818                         p->num_tx_qp = number;
3819                         p->base_queue = phys_id;
3820                         i40e_debug(hw, I40E_DEBUG_INIT,
3821                                    "HW Capability: Tx QP = %d\n", number);
3822                         i40e_debug(hw, I40E_DEBUG_INIT,
3823                                    "HW Capability: base_queue = %d\n",
3824                                    p->base_queue);
3825                         break;
3826                 case I40E_AQ_CAP_ID_MSIX:
3827                         p->num_msix_vectors = number;
3828                         i40e_debug(hw, I40E_DEBUG_INIT,
3829                                    "HW Capability: MSIX vector count = %d\n",
3830                                    p->num_msix_vectors);
3831                         break;
3832                 case I40E_AQ_CAP_ID_VF_MSIX:
3833                         p->num_msix_vectors_vf = number;
3834                         i40e_debug(hw, I40E_DEBUG_INIT,
3835                                    "HW Capability: MSIX VF vector count = %d\n",
3836                                    p->num_msix_vectors_vf);
3837                         break;
3838                 case I40E_AQ_CAP_ID_FLEX10:
3839                         if (major_rev == 1) {
3840                                 if (number == 1) {
3841                                         p->flex10_enable = true;
3842                                         p->flex10_capable = true;
3843                                 }
3844                         } else {
3845                                 /* Capability revision >= 2 */
3846                                 if (number & 1)
3847                                         p->flex10_enable = true;
3848                                 if (number & 2)
3849                                         p->flex10_capable = true;
3850                         }
3851                         p->flex10_mode = logical_id;
3852                         p->flex10_status = phys_id;
3853                         i40e_debug(hw, I40E_DEBUG_INIT,
3854                                    "HW Capability: Flex10 mode = %d\n",
3855                                    p->flex10_mode);
3856                         i40e_debug(hw, I40E_DEBUG_INIT,
3857                                    "HW Capability: Flex10 status = %d\n",
3858                                    p->flex10_status);
3859                         break;
3860                 case I40E_AQ_CAP_ID_CEM:
3861                         if (number == 1)
3862                                 p->mgmt_cem = true;
3863                         i40e_debug(hw, I40E_DEBUG_INIT,
3864                                    "HW Capability: CEM = %d\n", p->mgmt_cem);
3865                         break;
3866                 case I40E_AQ_CAP_ID_IWARP:
3867                         if (number == 1)
3868                                 p->iwarp = true;
3869                         i40e_debug(hw, I40E_DEBUG_INIT,
3870                                    "HW Capability: iWARP = %d\n", p->iwarp);
3871                         break;
3872                 case I40E_AQ_CAP_ID_LED:
3873                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3874                                 p->led[phys_id] = true;
3875                         i40e_debug(hw, I40E_DEBUG_INIT,
3876                                    "HW Capability: LED - PIN %d\n", phys_id);
3877                         break;
3878                 case I40E_AQ_CAP_ID_SDP:
3879                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3880                                 p->sdp[phys_id] = true;
3881                         i40e_debug(hw, I40E_DEBUG_INIT,
3882                                    "HW Capability: SDP - PIN %d\n", phys_id);
3883                         break;
3884                 case I40E_AQ_CAP_ID_MDIO:
3885                         if (number == 1) {
3886                                 p->mdio_port_num = phys_id;
3887                                 p->mdio_port_mode = logical_id;
3888                         }
3889                         i40e_debug(hw, I40E_DEBUG_INIT,
3890                                    "HW Capability: MDIO port number = %d\n",
3891                                    p->mdio_port_num);
3892                         i40e_debug(hw, I40E_DEBUG_INIT,
3893                                    "HW Capability: MDIO port mode = %d\n",
3894                                    p->mdio_port_mode);
3895                         break;
3896                 case I40E_AQ_CAP_ID_1588:
3897                         if (number == 1)
3898                                 p->ieee_1588 = true;
3899                         i40e_debug(hw, I40E_DEBUG_INIT,
3900                                    "HW Capability: IEEE 1588 = %d\n",
3901                                    p->ieee_1588);
3902                         break;
3903                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3904                         p->fd = true;
3905                         p->fd_filters_guaranteed = number;
3906                         p->fd_filters_best_effort = logical_id;
3907                         i40e_debug(hw, I40E_DEBUG_INIT,
3908                                    "HW Capability: Flow Director = 1\n");
3909                         i40e_debug(hw, I40E_DEBUG_INIT,
3910                                    "HW Capability: Guaranteed FD filters = %d\n",
3911                                    p->fd_filters_guaranteed);
3912                         break;
3913                 case I40E_AQ_CAP_ID_WSR_PROT:
3914                         p->wr_csr_prot = (u64)number;
3915                         p->wr_csr_prot |= (u64)logical_id << 32;
3916                         i40e_debug(hw, I40E_DEBUG_INIT,
3917                                    "HW Capability: wr_csr_prot = 0x%llX\n\n",
3918                                    (p->wr_csr_prot & 0xffff));
3919                         break;
3920                 case I40E_AQ_CAP_ID_NVM_MGMT:
3921                         if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3922                                 p->sec_rev_disabled = true;
3923                         if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3924                                 p->update_disabled = true;
3925                         break;
3926                 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3927                         hw->num_wol_proxy_filters = (u16)number;
3928                         hw->wol_proxy_vsi_seid = (u16)logical_id;
3929                         p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3930                         if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3931                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3932                         else
3933                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3934                         p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3935                         i40e_debug(hw, I40E_DEBUG_INIT,
3936                                    "HW Capability: WOL proxy filters = %d\n",
3937                                    hw->num_wol_proxy_filters);
3938                         break;
3939                 default:
3940                         break;
3941                 }
3942         }
3943
3944         if (p->fcoe)
3945                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3946
3947         /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3948         p->fcoe = false;
3949
3950         /* count the enabled ports (aka the "not disabled" ports) */
3951         hw->num_ports = 0;
3952         for (i = 0; i < 4; i++) {
3953                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3954                 u64 port_cfg = 0;
3955
3956                 /* use AQ read to get the physical register offset instead
3957                  * of the port relative offset
3958                  */
3959                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3960                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3961                         hw->num_ports++;
3962         }
3963
3964         valid_functions = p->valid_functions;
3965         num_functions = 0;
3966         while (valid_functions) {
3967                 if (valid_functions & 1)
3968                         num_functions++;
3969                 valid_functions >>= 1;
3970         }
3971
3972         /* partition id is 1-based, and functions are evenly spread
3973          * across the ports as partitions
3974          */
3975         if (hw->num_ports != 0) {
3976                 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3977                 hw->num_partitions = num_functions / hw->num_ports;
3978         }
3979
3980         /* additional HW specific goodies that might
3981          * someday be HW version specific
3982          */
3983         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3984 }
3985
3986 /**
3987  * i40e_aq_discover_capabilities
3988  * @hw: pointer to the hw struct
3989  * @buff: a virtual buffer to hold the capabilities
3990  * @buff_size: Size of the virtual buffer
3991  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3992  * @list_type_opc: capabilities type to discover - pass in the command opcode
3993  * @cmd_details: pointer to command details structure or NULL
3994  *
3995  * Get the device capabilities descriptions from the firmware
3996  **/
3997 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3998                                 void *buff, u16 buff_size, u16 *data_size,
3999                                 enum i40e_admin_queue_opc list_type_opc,
4000                                 struct i40e_asq_cmd_details *cmd_details)
4001 {
4002         struct i40e_aqc_list_capabilites *cmd;
4003         struct i40e_aq_desc desc;
4004         enum i40e_status_code status = I40E_SUCCESS;
4005
4006         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
4007
4008         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
4009                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
4010                 status = I40E_ERR_PARAM;
4011                 goto exit;
4012         }
4013
4014         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
4015
4016         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4017         if (buff_size > I40E_AQ_LARGE_BUF)
4018                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4019
4020         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4021         *data_size = LE16_TO_CPU(desc.datalen);
4022
4023         if (status)
4024                 goto exit;
4025
4026         i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
4027                                          list_type_opc);
4028
4029 exit:
4030         return status;
4031 }
4032
4033 /**
4034  * i40e_aq_update_nvm
4035  * @hw: pointer to the hw struct
4036  * @module_pointer: module pointer location in words from the NVM beginning
4037  * @offset: byte offset from the module beginning
4038  * @length: length of the section to be written (in bytes from the offset)
4039  * @data: command buffer (size [bytes] = length)
4040  * @last_command: tells if this is the last command in a series
4041  * @cmd_details: pointer to command details structure or NULL
4042  *
4043  * Update the NVM using the admin queue commands
4044  **/
4045 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
4046                                 u32 offset, u16 length, void *data,
4047                                 bool last_command,
4048                                 struct i40e_asq_cmd_details *cmd_details)
4049 {
4050         struct i40e_aq_desc desc;
4051         struct i40e_aqc_nvm_update *cmd =
4052                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
4053         enum i40e_status_code status;
4054
4055         DEBUGFUNC("i40e_aq_update_nvm");
4056
4057         /* In offset the highest byte must be zeroed. */
4058         if (offset & 0xFF000000) {
4059                 status = I40E_ERR_PARAM;
4060                 goto i40e_aq_update_nvm_exit;
4061         }
4062
4063         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4064
4065         /* If this is the last command in a series, set the proper flag. */
4066         if (last_command)
4067                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
4068         cmd->module_pointer = module_pointer;
4069         cmd->offset = CPU_TO_LE32(offset);
4070         cmd->length = CPU_TO_LE16(length);
4071
4072         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4073         if (length > I40E_AQ_LARGE_BUF)
4074                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4075
4076         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
4077
4078 i40e_aq_update_nvm_exit:
4079         return status;
4080 }
4081
4082 /**
4083  * i40e_aq_get_lldp_mib
4084  * @hw: pointer to the hw struct
4085  * @bridge_type: type of bridge requested
4086  * @mib_type: Local, Remote or both Local and Remote MIBs
4087  * @buff: pointer to a user supplied buffer to store the MIB block
4088  * @buff_size: size of the buffer (in bytes)
4089  * @local_len : length of the returned Local LLDP MIB
4090  * @remote_len: length of the returned Remote LLDP MIB
4091  * @cmd_details: pointer to command details structure or NULL
4092  *
4093  * Requests the complete LLDP MIB (entire packet).
4094  **/
4095 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4096                                 u8 mib_type, void *buff, u16 buff_size,
4097                                 u16 *local_len, u16 *remote_len,
4098                                 struct i40e_asq_cmd_details *cmd_details)
4099 {
4100         struct i40e_aq_desc desc;
4101         struct i40e_aqc_lldp_get_mib *cmd =
4102                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4103         struct i40e_aqc_lldp_get_mib *resp =
4104                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4105         enum i40e_status_code status;
4106
4107         if (buff_size == 0 || !buff)
4108                 return I40E_ERR_PARAM;
4109
4110         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4111         /* Indirect Command */
4112         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4113
4114         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4115         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4116                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4117
4118         desc.datalen = CPU_TO_LE16(buff_size);
4119
4120         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4121         if (buff_size > I40E_AQ_LARGE_BUF)
4122                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4123
4124         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4125         if (!status) {
4126                 if (local_len != NULL)
4127                         *local_len = LE16_TO_CPU(resp->local_len);
4128                 if (remote_len != NULL)
4129                         *remote_len = LE16_TO_CPU(resp->remote_len);
4130         }
4131
4132         return status;
4133 }
4134
4135  /**
4136  * i40e_aq_set_lldp_mib - Set the LLDP MIB
4137  * @hw: pointer to the hw struct
4138  * @mib_type: Local, Remote or both Local and Remote MIBs
4139  * @buff: pointer to a user supplied buffer to store the MIB block
4140  * @buff_size: size of the buffer (in bytes)
4141  * @cmd_details: pointer to command details structure or NULL
4142  *
4143  * Set the LLDP MIB.
4144  **/
4145 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4146                                 u8 mib_type, void *buff, u16 buff_size,
4147                                 struct i40e_asq_cmd_details *cmd_details)
4148 {
4149         struct i40e_aq_desc desc;
4150         struct i40e_aqc_lldp_set_local_mib *cmd =
4151                 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4152         enum i40e_status_code status;
4153
4154         if (buff_size == 0 || !buff)
4155                 return I40E_ERR_PARAM;
4156
4157         i40e_fill_default_direct_cmd_desc(&desc,
4158                                 i40e_aqc_opc_lldp_set_local_mib);
4159         /* Indirect Command */
4160         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4161         if (buff_size > I40E_AQ_LARGE_BUF)
4162                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4163         desc.datalen = CPU_TO_LE16(buff_size);
4164
4165         cmd->type = mib_type;
4166         cmd->length = CPU_TO_LE16(buff_size);
4167         cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4168         cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4169
4170         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4171         return status;
4172 }
4173
4174 /**
4175  * i40e_aq_cfg_lldp_mib_change_event
4176  * @hw: pointer to the hw struct
4177  * @enable_update: Enable or Disable event posting
4178  * @cmd_details: pointer to command details structure or NULL
4179  *
4180  * Enable or Disable posting of an event on ARQ when LLDP MIB
4181  * associated with the interface changes
4182  **/
4183 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4184                                 bool enable_update,
4185                                 struct i40e_asq_cmd_details *cmd_details)
4186 {
4187         struct i40e_aq_desc desc;
4188         struct i40e_aqc_lldp_update_mib *cmd =
4189                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4190         enum i40e_status_code status;
4191
4192         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4193
4194         if (!enable_update)
4195                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4196
4197         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4198
4199         return status;
4200 }
4201
4202 /**
4203  * i40e_aq_add_lldp_tlv
4204  * @hw: pointer to the hw struct
4205  * @bridge_type: type of bridge
4206  * @buff: buffer with TLV to add
4207  * @buff_size: length of the buffer
4208  * @tlv_len: length of the TLV to be added
4209  * @mib_len: length of the LLDP MIB returned in response
4210  * @cmd_details: pointer to command details structure or NULL
4211  *
4212  * Add the specified TLV to LLDP Local MIB for the given bridge type,
4213  * it is responsibility of the caller to make sure that the TLV is not
4214  * already present in the LLDPDU.
4215  * In return firmware will write the complete LLDP MIB with the newly
4216  * added TLV in the response buffer.
4217  **/
4218 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4219                                 void *buff, u16 buff_size, u16 tlv_len,
4220                                 u16 *mib_len,
4221                                 struct i40e_asq_cmd_details *cmd_details)
4222 {
4223         struct i40e_aq_desc desc;
4224         struct i40e_aqc_lldp_add_tlv *cmd =
4225                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4226         enum i40e_status_code status;
4227
4228         if (buff_size == 0 || !buff || tlv_len == 0)
4229                 return I40E_ERR_PARAM;
4230
4231         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4232
4233         /* Indirect Command */
4234         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4235         if (buff_size > I40E_AQ_LARGE_BUF)
4236                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4237         desc.datalen = CPU_TO_LE16(buff_size);
4238
4239         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4240                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4241         cmd->len = CPU_TO_LE16(tlv_len);
4242
4243         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4244         if (!status) {
4245                 if (mib_len != NULL)
4246                         *mib_len = LE16_TO_CPU(desc.datalen);
4247         }
4248
4249         return status;
4250 }
4251
4252 /**
4253  * i40e_aq_update_lldp_tlv
4254  * @hw: pointer to the hw struct
4255  * @bridge_type: type of bridge
4256  * @buff: buffer with TLV to update
4257  * @buff_size: size of the buffer holding original and updated TLVs
4258  * @old_len: Length of the Original TLV
4259  * @new_len: Length of the Updated TLV
4260  * @offset: offset of the updated TLV in the buff
4261  * @mib_len: length of the returned LLDP MIB
4262  * @cmd_details: pointer to command details structure or NULL
4263  *
4264  * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4265  * Firmware will place the complete LLDP MIB in response buffer with the
4266  * updated TLV.
4267  **/
4268 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4269                                 u8 bridge_type, void *buff, u16 buff_size,
4270                                 u16 old_len, u16 new_len, u16 offset,
4271                                 u16 *mib_len,
4272                                 struct i40e_asq_cmd_details *cmd_details)
4273 {
4274         struct i40e_aq_desc desc;
4275         struct i40e_aqc_lldp_update_tlv *cmd =
4276                 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4277         enum i40e_status_code status;
4278
4279         if (buff_size == 0 || !buff || offset == 0 ||
4280             old_len == 0 || new_len == 0)
4281                 return I40E_ERR_PARAM;
4282
4283         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4284
4285         /* Indirect Command */
4286         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4287         if (buff_size > I40E_AQ_LARGE_BUF)
4288                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4289         desc.datalen = CPU_TO_LE16(buff_size);
4290
4291         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4292                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4293         cmd->old_len = CPU_TO_LE16(old_len);
4294         cmd->new_offset = CPU_TO_LE16(offset);
4295         cmd->new_len = CPU_TO_LE16(new_len);
4296
4297         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4298         if (!status) {
4299                 if (mib_len != NULL)
4300                         *mib_len = LE16_TO_CPU(desc.datalen);
4301         }
4302
4303         return status;
4304 }
4305
4306 /**
4307  * i40e_aq_delete_lldp_tlv
4308  * @hw: pointer to the hw struct
4309  * @bridge_type: type of bridge
4310  * @buff: pointer to a user supplied buffer that has the TLV
4311  * @buff_size: length of the buffer
4312  * @tlv_len: length of the TLV to be deleted
4313  * @mib_len: length of the returned LLDP MIB
4314  * @cmd_details: pointer to command details structure or NULL
4315  *
4316  * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4317  * The firmware places the entire LLDP MIB in the response buffer.
4318  **/
4319 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4320                                 u8 bridge_type, void *buff, u16 buff_size,
4321                                 u16 tlv_len, u16 *mib_len,
4322                                 struct i40e_asq_cmd_details *cmd_details)
4323 {
4324         struct i40e_aq_desc desc;
4325         struct i40e_aqc_lldp_add_tlv *cmd =
4326                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4327         enum i40e_status_code status;
4328
4329         if (buff_size == 0 || !buff)
4330                 return I40E_ERR_PARAM;
4331
4332         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4333
4334         /* Indirect Command */
4335         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4336         if (buff_size > I40E_AQ_LARGE_BUF)
4337                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4338         desc.datalen = CPU_TO_LE16(buff_size);
4339         cmd->len = CPU_TO_LE16(tlv_len);
4340         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4341                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4342
4343         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4344         if (!status) {
4345                 if (mib_len != NULL)
4346                         *mib_len = LE16_TO_CPU(desc.datalen);
4347         }
4348
4349         return status;
4350 }
4351
4352 /**
4353  * i40e_aq_stop_lldp
4354  * @hw: pointer to the hw struct
4355  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4356  * @cmd_details: pointer to command details structure or NULL
4357  *
4358  * Stop or Shutdown the embedded LLDP Agent
4359  **/
4360 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4361                                 struct i40e_asq_cmd_details *cmd_details)
4362 {
4363         struct i40e_aq_desc desc;
4364         struct i40e_aqc_lldp_stop *cmd =
4365                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4366         enum i40e_status_code status;
4367
4368         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4369
4370         if (shutdown_agent)
4371                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4372
4373         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4374
4375         return status;
4376 }
4377
4378 /**
4379  * i40e_aq_start_lldp
4380  * @hw: pointer to the hw struct
4381  * @cmd_details: pointer to command details structure or NULL
4382  *
4383  * Start the embedded LLDP Agent on all ports.
4384  **/
4385 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4386                                 struct i40e_asq_cmd_details *cmd_details)
4387 {
4388         struct i40e_aq_desc desc;
4389         struct i40e_aqc_lldp_start *cmd =
4390                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4391         enum i40e_status_code status;
4392
4393         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4394
4395         cmd->command = I40E_AQ_LLDP_AGENT_START;
4396
4397         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4398
4399         return status;
4400 }
4401
4402 /**
4403  * i40e_aq_get_cee_dcb_config
4404  * @hw: pointer to the hw struct
4405  * @buff: response buffer that stores CEE operational configuration
4406  * @buff_size: size of the buffer passed
4407  * @cmd_details: pointer to command details structure or NULL
4408  *
4409  * Get CEE DCBX mode operational configuration from firmware
4410  **/
4411 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4412                                 void *buff, u16 buff_size,
4413                                 struct i40e_asq_cmd_details *cmd_details)
4414 {
4415         struct i40e_aq_desc desc;
4416         enum i40e_status_code status;
4417
4418         if (buff_size == 0 || !buff)
4419                 return I40E_ERR_PARAM;
4420
4421         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4422
4423         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4424         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4425                                        cmd_details);
4426
4427         return status;
4428 }
4429
4430 /**
4431  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4432  * @hw: pointer to the hw struct
4433  * @start_agent: True if DCBx Agent needs to be Started
4434  *                              False if DCBx Agent needs to be Stopped
4435  * @cmd_details: pointer to command details structure or NULL
4436  *
4437  * Start/Stop the embedded dcbx Agent
4438  **/
4439 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4440                                 bool start_agent,
4441                                 struct i40e_asq_cmd_details *cmd_details)
4442 {
4443         struct i40e_aq_desc desc;
4444         struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4445                 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4446                                 &desc.params.raw;
4447         enum i40e_status_code status;
4448
4449         i40e_fill_default_direct_cmd_desc(&desc,
4450                                 i40e_aqc_opc_lldp_stop_start_spec_agent);
4451
4452         if (start_agent)
4453                 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4454
4455         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4456
4457         return status;
4458 }
4459
4460 /**
4461  * i40e_aq_add_udp_tunnel
4462  * @hw: pointer to the hw struct
4463  * @udp_port: the UDP port to add in Host byte order
4464  * @header_len: length of the tunneling header length in DWords
4465  * @protocol_index: protocol index type
4466  * @filter_index: pointer to filter index
4467  * @cmd_details: pointer to command details structure or NULL
4468  *
4469  * Note: Firmware expects the udp_port value to be in Little Endian format,
4470  * and this function will call CPU_TO_LE16 to convert from Host byte order to
4471  * Little Endian order.
4472  **/
4473 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4474                                 u16 udp_port, u8 protocol_index,
4475                                 u8 *filter_index,
4476                                 struct i40e_asq_cmd_details *cmd_details)
4477 {
4478         struct i40e_aq_desc desc;
4479         struct i40e_aqc_add_udp_tunnel *cmd =
4480                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4481         struct i40e_aqc_del_udp_tunnel_completion *resp =
4482                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4483         enum i40e_status_code status;
4484
4485         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4486
4487         cmd->udp_port = CPU_TO_LE16(udp_port);
4488         cmd->protocol_type = protocol_index;
4489
4490         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4491
4492         if (!status && filter_index)
4493                 *filter_index = resp->index;
4494
4495         return status;
4496 }
4497
4498 /**
4499  * i40e_aq_del_udp_tunnel
4500  * @hw: pointer to the hw struct
4501  * @index: filter index
4502  * @cmd_details: pointer to command details structure or NULL
4503  **/
4504 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4505                                 struct i40e_asq_cmd_details *cmd_details)
4506 {
4507         struct i40e_aq_desc desc;
4508         struct i40e_aqc_remove_udp_tunnel *cmd =
4509                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4510         enum i40e_status_code status;
4511
4512         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4513
4514         cmd->index = index;
4515
4516         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4517
4518         return status;
4519 }
4520
4521 /**
4522  * i40e_aq_get_switch_resource_alloc (0x0204)
4523  * @hw: pointer to the hw struct
4524  * @num_entries: pointer to u8 to store the number of resource entries returned
4525  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
4526  *        to store the resource information for all resource types.  Each
4527  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
4528  * @count: size, in bytes, of the buffer provided
4529  * @cmd_details: pointer to command details structure or NULL
4530  *
4531  * Query the resources allocated to a function.
4532  **/
4533 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4534                         u8 *num_entries,
4535                         struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4536                         u16 count,
4537                         struct i40e_asq_cmd_details *cmd_details)
4538 {
4539         struct i40e_aq_desc desc;
4540         struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4541                 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4542         enum i40e_status_code status;
4543         u16 length = count * sizeof(*buf);
4544
4545         i40e_fill_default_direct_cmd_desc(&desc,
4546                                         i40e_aqc_opc_get_switch_resource_alloc);
4547
4548         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4549         if (length > I40E_AQ_LARGE_BUF)
4550                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4551
4552         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4553
4554         if (!status && num_entries)
4555                 *num_entries = cmd_resp->num_entries;
4556
4557         return status;
4558 }
4559
4560 /**
4561  * i40e_aq_delete_element - Delete switch element
4562  * @hw: pointer to the hw struct
4563  * @seid: the SEID to delete from the switch
4564  * @cmd_details: pointer to command details structure or NULL
4565  *
4566  * This deletes a switch element from the switch.
4567  **/
4568 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4569                                 struct i40e_asq_cmd_details *cmd_details)
4570 {
4571         struct i40e_aq_desc desc;
4572         struct i40e_aqc_switch_seid *cmd =
4573                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4574         enum i40e_status_code status;
4575
4576         if (seid == 0)
4577                 return I40E_ERR_PARAM;
4578
4579         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4580
4581         cmd->seid = CPU_TO_LE16(seid);
4582
4583         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4584
4585         return status;
4586 }
4587
4588 /**
4589  * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4590  * @hw: pointer to the hw struct
4591  * @flags: component flags
4592  * @mac_seid: uplink seid (MAC SEID)
4593  * @vsi_seid: connected vsi seid
4594  * @ret_seid: seid of create pv component
4595  *
4596  * This instantiates an i40e port virtualizer with specified flags.
4597  * Depending on specified flags the port virtualizer can act as a
4598  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4599  */
4600 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4601                                        u16 mac_seid, u16 vsi_seid,
4602                                        u16 *ret_seid)
4603 {
4604         struct i40e_aq_desc desc;
4605         struct i40e_aqc_add_update_pv *cmd =
4606                 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4607         struct i40e_aqc_add_update_pv_completion *resp =
4608                 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4609         enum i40e_status_code status;
4610
4611         if (vsi_seid == 0)
4612                 return I40E_ERR_PARAM;
4613
4614         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4615         cmd->command_flags = CPU_TO_LE16(flags);
4616         cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4617         cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4618
4619         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4620         if (!status && ret_seid)
4621                 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4622
4623         return status;
4624 }
4625
4626 /**
4627  * i40e_aq_add_tag - Add an S/E-tag
4628  * @hw: pointer to the hw struct
4629  * @direct_to_queue: should s-tag direct flow to a specific queue
4630  * @vsi_seid: VSI SEID to use this tag
4631  * @tag: value of the tag
4632  * @queue_num: queue number, only valid is direct_to_queue is true
4633  * @tags_used: return value, number of tags in use by this PF
4634  * @tags_free: return value, number of unallocated tags
4635  * @cmd_details: pointer to command details structure or NULL
4636  *
4637  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4638  * the number of tags allocated by the PF, and the number of unallocated
4639  * tags available.
4640  **/
4641 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4642                                 u16 vsi_seid, u16 tag, u16 queue_num,
4643                                 u16 *tags_used, u16 *tags_free,
4644                                 struct i40e_asq_cmd_details *cmd_details)
4645 {
4646         struct i40e_aq_desc desc;
4647         struct i40e_aqc_add_tag *cmd =
4648                 (struct i40e_aqc_add_tag *)&desc.params.raw;
4649         struct i40e_aqc_add_remove_tag_completion *resp =
4650                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4651         enum i40e_status_code status;
4652
4653         if (vsi_seid == 0)
4654                 return I40E_ERR_PARAM;
4655
4656         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4657
4658         cmd->seid = CPU_TO_LE16(vsi_seid);
4659         cmd->tag = CPU_TO_LE16(tag);
4660         if (direct_to_queue) {
4661                 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4662                 cmd->queue_number = CPU_TO_LE16(queue_num);
4663         }
4664
4665         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4666
4667         if (!status) {
4668                 if (tags_used != NULL)
4669                         *tags_used = LE16_TO_CPU(resp->tags_used);
4670                 if (tags_free != NULL)
4671                         *tags_free = LE16_TO_CPU(resp->tags_free);
4672         }
4673
4674         return status;
4675 }
4676
4677 /**
4678  * i40e_aq_remove_tag - Remove an S- or E-tag
4679  * @hw: pointer to the hw struct
4680  * @vsi_seid: VSI SEID this tag is associated with
4681  * @tag: value of the S-tag to delete
4682  * @tags_used: return value, number of tags in use by this PF
4683  * @tags_free: return value, number of unallocated tags
4684  * @cmd_details: pointer to command details structure or NULL
4685  *
4686  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4687  * the number of tags allocated by the PF, and the number of unallocated
4688  * tags available.
4689  **/
4690 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4691                                 u16 tag, u16 *tags_used, u16 *tags_free,
4692                                 struct i40e_asq_cmd_details *cmd_details)
4693 {
4694         struct i40e_aq_desc desc;
4695         struct i40e_aqc_remove_tag *cmd =
4696                 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4697         struct i40e_aqc_add_remove_tag_completion *resp =
4698                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4699         enum i40e_status_code status;
4700
4701         if (vsi_seid == 0)
4702                 return I40E_ERR_PARAM;
4703
4704         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4705
4706         cmd->seid = CPU_TO_LE16(vsi_seid);
4707         cmd->tag = CPU_TO_LE16(tag);
4708
4709         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4710
4711         if (!status) {
4712                 if (tags_used != NULL)
4713                         *tags_used = LE16_TO_CPU(resp->tags_used);
4714                 if (tags_free != NULL)
4715                         *tags_free = LE16_TO_CPU(resp->tags_free);
4716         }
4717
4718         return status;
4719 }
4720
4721 /**
4722  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4723  * @hw: pointer to the hw struct
4724  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4725  * @etag: value of E-tag to add
4726  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4727  * @buf: address of indirect buffer
4728  * @tags_used: return value, number of E-tags in use by this port
4729  * @tags_free: return value, number of unallocated M-tags
4730  * @cmd_details: pointer to command details structure or NULL
4731  *
4732  * This associates a multicast E-tag to a port virtualizer.  It will return
4733  * the number of tags allocated by the PF, and the number of unallocated
4734  * tags available.
4735  *
4736  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4737  * num_tags_in_buf long.
4738  **/
4739 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4740                                 u16 etag, u8 num_tags_in_buf, void *buf,
4741                                 u16 *tags_used, u16 *tags_free,
4742                                 struct i40e_asq_cmd_details *cmd_details)
4743 {
4744         struct i40e_aq_desc desc;
4745         struct i40e_aqc_add_remove_mcast_etag *cmd =
4746                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4747         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4748            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4749         enum i40e_status_code status;
4750         u16 length = sizeof(u16) * num_tags_in_buf;
4751
4752         if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4753                 return I40E_ERR_PARAM;
4754
4755         i40e_fill_default_direct_cmd_desc(&desc,
4756                                           i40e_aqc_opc_add_multicast_etag);
4757
4758         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4759         cmd->etag = CPU_TO_LE16(etag);
4760         cmd->num_unicast_etags = num_tags_in_buf;
4761
4762         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4763         if (length > I40E_AQ_LARGE_BUF)
4764                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4765
4766         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4767
4768         if (!status) {
4769                 if (tags_used != NULL)
4770                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4771                 if (tags_free != NULL)
4772                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4773         }
4774
4775         return status;
4776 }
4777
4778 /**
4779  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4780  * @hw: pointer to the hw struct
4781  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4782  * @etag: value of the E-tag to remove
4783  * @tags_used: return value, number of tags in use by this port
4784  * @tags_free: return value, number of unallocated tags
4785  * @cmd_details: pointer to command details structure or NULL
4786  *
4787  * This deletes an E-tag from the port virtualizer.  It will return
4788  * the number of tags allocated by the port, and the number of unallocated
4789  * tags available.
4790  **/
4791 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4792                                 u16 etag, u16 *tags_used, u16 *tags_free,
4793                                 struct i40e_asq_cmd_details *cmd_details)
4794 {
4795         struct i40e_aq_desc desc;
4796         struct i40e_aqc_add_remove_mcast_etag *cmd =
4797                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4798         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4799            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4800         enum i40e_status_code status;
4801
4802
4803         if (pv_seid == 0)
4804                 return I40E_ERR_PARAM;
4805
4806         i40e_fill_default_direct_cmd_desc(&desc,
4807                                           i40e_aqc_opc_remove_multicast_etag);
4808
4809         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4810         cmd->etag = CPU_TO_LE16(etag);
4811
4812         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4813
4814         if (!status) {
4815                 if (tags_used != NULL)
4816                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4817                 if (tags_free != NULL)
4818                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4819         }
4820
4821         return status;
4822 }
4823
4824 /**
4825  * i40e_aq_update_tag - Update an S/E-tag
4826  * @hw: pointer to the hw struct
4827  * @vsi_seid: VSI SEID using this S-tag
4828  * @old_tag: old tag value
4829  * @new_tag: new tag value
4830  * @tags_used: return value, number of tags in use by this PF
4831  * @tags_free: return value, number of unallocated tags
4832  * @cmd_details: pointer to command details structure or NULL
4833  *
4834  * This updates the value of the tag currently attached to this VSI
4835  * in the switch complex.  It will return the number of tags allocated
4836  * by the PF, and the number of unallocated tags available.
4837  **/
4838 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4839                                 u16 old_tag, u16 new_tag, u16 *tags_used,
4840                                 u16 *tags_free,
4841                                 struct i40e_asq_cmd_details *cmd_details)
4842 {
4843         struct i40e_aq_desc desc;
4844         struct i40e_aqc_update_tag *cmd =
4845                 (struct i40e_aqc_update_tag *)&desc.params.raw;
4846         struct i40e_aqc_update_tag_completion *resp =
4847                 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4848         enum i40e_status_code status;
4849
4850         if (vsi_seid == 0)
4851                 return I40E_ERR_PARAM;
4852
4853         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4854
4855         cmd->seid = CPU_TO_LE16(vsi_seid);
4856         cmd->old_tag = CPU_TO_LE16(old_tag);
4857         cmd->new_tag = CPU_TO_LE16(new_tag);
4858
4859         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4860
4861         if (!status) {
4862                 if (tags_used != NULL)
4863                         *tags_used = LE16_TO_CPU(resp->tags_used);
4864                 if (tags_free != NULL)
4865                         *tags_free = LE16_TO_CPU(resp->tags_free);
4866         }
4867
4868         return status;
4869 }
4870
4871 /**
4872  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4873  * @hw: pointer to the hw struct
4874  * @tcmap: TC map for request/release any ignore PFC condition
4875  * @request: request or release ignore PFC condition
4876  * @tcmap_ret: return TCs for which PFC is currently ignored
4877  * @cmd_details: pointer to command details structure or NULL
4878  *
4879  * This sends out request/release to ignore PFC condition for a TC.
4880  * It will return the TCs for which PFC is currently ignored.
4881  **/
4882 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4883                                 bool request, u8 *tcmap_ret,
4884                                 struct i40e_asq_cmd_details *cmd_details)
4885 {
4886         struct i40e_aq_desc desc;
4887         struct i40e_aqc_pfc_ignore *cmd_resp =
4888                 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4889         enum i40e_status_code status;
4890
4891         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4892
4893         if (request)
4894                 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4895
4896         cmd_resp->tc_bitmap = tcmap;
4897
4898         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4899
4900         if (!status) {
4901                 if (tcmap_ret != NULL)
4902                         *tcmap_ret = cmd_resp->tc_bitmap;
4903         }
4904
4905         return status;
4906 }
4907
4908 /**
4909  * i40e_aq_dcb_updated - DCB Updated Command
4910  * @hw: pointer to the hw struct
4911  * @cmd_details: pointer to command details structure or NULL
4912  *
4913  * When LLDP is handled in PF this command is used by the PF
4914  * to notify EMP that a DCB setting is modified.
4915  * When LLDP is handled in EMP this command is used by the PF
4916  * to notify EMP whenever one of the following parameters get
4917  * modified:
4918  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4919  *   - PCIRTT in PRTDCB_GENC.PCIRTT
4920  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4921  * EMP will return when the shared RPB settings have been
4922  * recomputed and modified. The retval field in the descriptor
4923  * will be set to 0 when RPB is modified.
4924  **/
4925 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4926                                 struct i40e_asq_cmd_details *cmd_details)
4927 {
4928         struct i40e_aq_desc desc;
4929         enum i40e_status_code status;
4930
4931         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4932
4933         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4934
4935         return status;
4936 }
4937
4938 /**
4939  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4940  * @hw: pointer to the hw struct
4941  * @seid: defines the SEID of the switch for which the stats are requested
4942  * @vlan_id: the VLAN ID for which the statistics are requested
4943  * @stat_index: index of the statistics counters block assigned to this VLAN
4944  * @cmd_details: pointer to command details structure or NULL
4945  *
4946  * XL710 supports 128 smonVlanStats counters.This command is used to
4947  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4948  * switch.
4949  **/
4950 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4951                                 u16 vlan_id, u16 *stat_index,
4952                                 struct i40e_asq_cmd_details *cmd_details)
4953 {
4954         struct i40e_aq_desc desc;
4955         struct i40e_aqc_add_remove_statistics *cmd_resp =
4956                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4957         enum i40e_status_code status;
4958
4959         if ((seid == 0) || (stat_index == NULL))
4960                 return I40E_ERR_PARAM;
4961
4962         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4963
4964         cmd_resp->seid = CPU_TO_LE16(seid);
4965         cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4966
4967         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4968
4969         if (!status && stat_index)
4970                 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4971
4972         return status;
4973 }
4974
4975 /**
4976  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4977  * @hw: pointer to the hw struct
4978  * @seid: defines the SEID of the switch for which the stats are requested
4979  * @vlan_id: the VLAN ID for which the statistics are requested
4980  * @stat_index: index of the statistics counters block assigned to this VLAN
4981  * @cmd_details: pointer to command details structure or NULL
4982  *
4983  * XL710 supports 128 smonVlanStats counters.This command is used to
4984  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4985  * switch.
4986  **/
4987 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4988                                 u16 vlan_id, u16 stat_index,
4989                                 struct i40e_asq_cmd_details *cmd_details)
4990 {
4991         struct i40e_aq_desc desc;
4992         struct i40e_aqc_add_remove_statistics *cmd =
4993                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4994         enum i40e_status_code status;
4995
4996         if (seid == 0)
4997                 return I40E_ERR_PARAM;
4998
4999         i40e_fill_default_direct_cmd_desc(&desc,
5000                                           i40e_aqc_opc_remove_statistics);
5001
5002         cmd->seid = CPU_TO_LE16(seid);
5003         cmd->vlan  = CPU_TO_LE16(vlan_id);
5004         cmd->stat_index = CPU_TO_LE16(stat_index);
5005
5006         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5007
5008         return status;
5009 }
5010
5011 /**
5012  * i40e_aq_set_port_parameters - set physical port parameters.
5013  * @hw: pointer to the hw struct
5014  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
5015  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
5016  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
5017  * @double_vlan: if set double VLAN is enabled
5018  * @cmd_details: pointer to command details structure or NULL
5019  **/
5020 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
5021                                 u16 bad_frame_vsi, bool save_bad_pac,
5022                                 bool pad_short_pac, bool double_vlan,
5023                                 struct i40e_asq_cmd_details *cmd_details)
5024 {
5025         struct i40e_aqc_set_port_parameters *cmd;
5026         enum i40e_status_code status;
5027         struct i40e_aq_desc desc;
5028         u16 command_flags = 0;
5029
5030         cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
5031
5032         i40e_fill_default_direct_cmd_desc(&desc,
5033                                           i40e_aqc_opc_set_port_parameters);
5034
5035         cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
5036         if (save_bad_pac)
5037                 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
5038         if (pad_short_pac)
5039                 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
5040         if (double_vlan)
5041                 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
5042         cmd->command_flags = CPU_TO_LE16(command_flags);
5043
5044         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5045
5046         return status;
5047 }
5048
5049 /**
5050  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
5051  * @hw: pointer to the hw struct
5052  * @seid: seid for the physical port/switching component/vsi
5053  * @buff: Indirect buffer to hold data parameters and response
5054  * @buff_size: Indirect buffer size
5055  * @opcode: Tx scheduler AQ command opcode
5056  * @cmd_details: pointer to command details structure or NULL
5057  *
5058  * Generic command handler for Tx scheduler AQ commands
5059  **/
5060 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
5061                                 void *buff, u16 buff_size,
5062                                  enum i40e_admin_queue_opc opcode,
5063                                 struct i40e_asq_cmd_details *cmd_details)
5064 {
5065         struct i40e_aq_desc desc;
5066         struct i40e_aqc_tx_sched_ind *cmd =
5067                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
5068         enum i40e_status_code status;
5069         bool cmd_param_flag = false;
5070
5071         switch (opcode) {
5072         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
5073         case i40e_aqc_opc_configure_vsi_tc_bw:
5074         case i40e_aqc_opc_enable_switching_comp_ets:
5075         case i40e_aqc_opc_modify_switching_comp_ets:
5076         case i40e_aqc_opc_disable_switching_comp_ets:
5077         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
5078         case i40e_aqc_opc_configure_switching_comp_bw_config:
5079                 cmd_param_flag = true;
5080                 break;
5081         case i40e_aqc_opc_query_vsi_bw_config:
5082         case i40e_aqc_opc_query_vsi_ets_sla_config:
5083         case i40e_aqc_opc_query_switching_comp_ets_config:
5084         case i40e_aqc_opc_query_port_ets_config:
5085         case i40e_aqc_opc_query_switching_comp_bw_config:
5086                 cmd_param_flag = false;
5087                 break;
5088         default:
5089                 return I40E_ERR_PARAM;
5090         }
5091
5092         i40e_fill_default_direct_cmd_desc(&desc, opcode);
5093
5094         /* Indirect command */
5095         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5096         if (cmd_param_flag)
5097                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5098         if (buff_size > I40E_AQ_LARGE_BUF)
5099                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5100
5101         desc.datalen = CPU_TO_LE16(buff_size);
5102
5103         cmd->vsi_seid = CPU_TO_LE16(seid);
5104
5105         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5106
5107         return status;
5108 }
5109
5110 /**
5111  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5112  * @hw: pointer to the hw struct
5113  * @seid: VSI seid
5114  * @credit: BW limit credits (0 = disabled)
5115  * @max_credit: Max BW limit credits
5116  * @cmd_details: pointer to command details structure or NULL
5117  **/
5118 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5119                                 u16 seid, u16 credit, u8 max_credit,
5120                                 struct i40e_asq_cmd_details *cmd_details)
5121 {
5122         struct i40e_aq_desc desc;
5123         struct i40e_aqc_configure_vsi_bw_limit *cmd =
5124                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5125         enum i40e_status_code status;
5126
5127         i40e_fill_default_direct_cmd_desc(&desc,
5128                                           i40e_aqc_opc_configure_vsi_bw_limit);
5129
5130         cmd->vsi_seid = CPU_TO_LE16(seid);
5131         cmd->credit = CPU_TO_LE16(credit);
5132         cmd->max_credit = max_credit;
5133
5134         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5135
5136         return status;
5137 }
5138
5139 /**
5140  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5141  * @hw: pointer to the hw struct
5142  * @seid: switching component seid
5143  * @credit: BW limit credits (0 = disabled)
5144  * @max_bw: Max BW limit credits
5145  * @cmd_details: pointer to command details structure or NULL
5146  **/
5147 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5148                                 u16 seid, u16 credit, u8 max_bw,
5149                                 struct i40e_asq_cmd_details *cmd_details)
5150 {
5151         struct i40e_aq_desc desc;
5152         struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5153           (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5154         enum i40e_status_code status;
5155
5156         i40e_fill_default_direct_cmd_desc(&desc,
5157                                 i40e_aqc_opc_configure_switching_comp_bw_limit);
5158
5159         cmd->seid = CPU_TO_LE16(seid);
5160         cmd->credit = CPU_TO_LE16(credit);
5161         cmd->max_bw = max_bw;
5162
5163         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5164
5165         return status;
5166 }
5167
5168 /**
5169  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5170  * @hw: pointer to the hw struct
5171  * @seid: VSI seid
5172  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5173  * @cmd_details: pointer to command details structure or NULL
5174  **/
5175 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5176                         u16 seid,
5177                         struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5178                         struct i40e_asq_cmd_details *cmd_details)
5179 {
5180         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5181                                     i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5182                                     cmd_details);
5183 }
5184
5185 /**
5186  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5187  * @hw: pointer to the hw struct
5188  * @seid: VSI seid
5189  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5190  * @cmd_details: pointer to command details structure or NULL
5191  **/
5192 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5193                         u16 seid,
5194                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5195                         struct i40e_asq_cmd_details *cmd_details)
5196 {
5197         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5198                                     i40e_aqc_opc_configure_vsi_tc_bw,
5199                                     cmd_details);
5200 }
5201
5202 /**
5203  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5204  * @hw: pointer to the hw struct
5205  * @seid: seid of the switching component connected to Physical Port
5206  * @ets_data: Buffer holding ETS parameters
5207  * @cmd_details: pointer to command details structure or NULL
5208  **/
5209 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5210                 u16 seid,
5211                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5212                 enum i40e_admin_queue_opc opcode,
5213                 struct i40e_asq_cmd_details *cmd_details)
5214 {
5215         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5216                                     sizeof(*ets_data), opcode, cmd_details);
5217 }
5218
5219 /**
5220  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5221  * @hw: pointer to the hw struct
5222  * @seid: seid of the switching component
5223  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5224  * @cmd_details: pointer to command details structure or NULL
5225  **/
5226 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5227         u16 seid,
5228         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5229         struct i40e_asq_cmd_details *cmd_details)
5230 {
5231         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5232                             i40e_aqc_opc_configure_switching_comp_bw_config,
5233                             cmd_details);
5234 }
5235
5236 /**
5237  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5238  * @hw: pointer to the hw struct
5239  * @seid: seid of the switching component
5240  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5241  * @cmd_details: pointer to command details structure or NULL
5242  **/
5243 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5244         struct i40e_hw *hw, u16 seid,
5245         struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5246         struct i40e_asq_cmd_details *cmd_details)
5247 {
5248         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5249                             i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5250                             cmd_details);
5251 }
5252
5253 /**
5254  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5255  * @hw: pointer to the hw struct
5256  * @seid: seid of the VSI
5257  * @bw_data: Buffer to hold VSI BW configuration
5258  * @cmd_details: pointer to command details structure or NULL
5259  **/
5260 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5261                         u16 seid,
5262                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5263                         struct i40e_asq_cmd_details *cmd_details)
5264 {
5265         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5266                                     i40e_aqc_opc_query_vsi_bw_config,
5267                                     cmd_details);
5268 }
5269
5270 /**
5271  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5272  * @hw: pointer to the hw struct
5273  * @seid: seid of the VSI
5274  * @bw_data: Buffer to hold VSI BW configuration per TC
5275  * @cmd_details: pointer to command details structure or NULL
5276  **/
5277 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5278                         u16 seid,
5279                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5280                         struct i40e_asq_cmd_details *cmd_details)
5281 {
5282         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5283                                     i40e_aqc_opc_query_vsi_ets_sla_config,
5284                                     cmd_details);
5285 }
5286
5287 /**
5288  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5289  * @hw: pointer to the hw struct
5290  * @seid: seid of the switching component
5291  * @bw_data: Buffer to hold switching component's per TC BW config
5292  * @cmd_details: pointer to command details structure or NULL
5293  **/
5294 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5295                 u16 seid,
5296                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5297                 struct i40e_asq_cmd_details *cmd_details)
5298 {
5299         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5300                                    i40e_aqc_opc_query_switching_comp_ets_config,
5301                                    cmd_details);
5302 }
5303
5304 /**
5305  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5306  * @hw: pointer to the hw struct
5307  * @seid: seid of the VSI or switching component connected to Physical Port
5308  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5309  * @cmd_details: pointer to command details structure or NULL
5310  **/
5311 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5312                         u16 seid,
5313                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
5314                         struct i40e_asq_cmd_details *cmd_details)
5315 {
5316         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5317                                     i40e_aqc_opc_query_port_ets_config,
5318                                     cmd_details);
5319 }
5320
5321 /**
5322  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5323  * @hw: pointer to the hw struct
5324  * @seid: seid of the switching component
5325  * @bw_data: Buffer to hold switching component's BW configuration
5326  * @cmd_details: pointer to command details structure or NULL
5327  **/
5328 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5329                 u16 seid,
5330                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5331                 struct i40e_asq_cmd_details *cmd_details)
5332 {
5333         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5334                                     i40e_aqc_opc_query_switching_comp_bw_config,
5335                                     cmd_details);
5336 }
5337
5338 /**
5339  * i40e_validate_filter_settings
5340  * @hw: pointer to the hardware structure
5341  * @settings: Filter control settings
5342  *
5343  * Check and validate the filter control settings passed.
5344  * The function checks for the valid filter/context sizes being
5345  * passed for FCoE and PE.
5346  *
5347  * Returns I40E_SUCCESS if the values passed are valid and within
5348  * range else returns an error.
5349  **/
5350 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5351                                 struct i40e_filter_control_settings *settings)
5352 {
5353         u32 fcoe_cntx_size, fcoe_filt_size;
5354         u32 pe_cntx_size, pe_filt_size;
5355         u32 fcoe_fmax;
5356
5357         u32 val;
5358
5359         /* Validate FCoE settings passed */
5360         switch (settings->fcoe_filt_num) {
5361         case I40E_HASH_FILTER_SIZE_1K:
5362         case I40E_HASH_FILTER_SIZE_2K:
5363         case I40E_HASH_FILTER_SIZE_4K:
5364         case I40E_HASH_FILTER_SIZE_8K:
5365         case I40E_HASH_FILTER_SIZE_16K:
5366         case I40E_HASH_FILTER_SIZE_32K:
5367                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5368                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5369                 break;
5370         default:
5371                 return I40E_ERR_PARAM;
5372         }
5373
5374         switch (settings->fcoe_cntx_num) {
5375         case I40E_DMA_CNTX_SIZE_512:
5376         case I40E_DMA_CNTX_SIZE_1K:
5377         case I40E_DMA_CNTX_SIZE_2K:
5378         case I40E_DMA_CNTX_SIZE_4K:
5379                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5380                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5381                 break;
5382         default:
5383                 return I40E_ERR_PARAM;
5384         }
5385
5386         /* Validate PE settings passed */
5387         switch (settings->pe_filt_num) {
5388         case I40E_HASH_FILTER_SIZE_1K:
5389         case I40E_HASH_FILTER_SIZE_2K:
5390         case I40E_HASH_FILTER_SIZE_4K:
5391         case I40E_HASH_FILTER_SIZE_8K:
5392         case I40E_HASH_FILTER_SIZE_16K:
5393         case I40E_HASH_FILTER_SIZE_32K:
5394         case I40E_HASH_FILTER_SIZE_64K:
5395         case I40E_HASH_FILTER_SIZE_128K:
5396         case I40E_HASH_FILTER_SIZE_256K:
5397         case I40E_HASH_FILTER_SIZE_512K:
5398         case I40E_HASH_FILTER_SIZE_1M:
5399                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5400                 pe_filt_size <<= (u32)settings->pe_filt_num;
5401                 break;
5402         default:
5403                 return I40E_ERR_PARAM;
5404         }
5405
5406         switch (settings->pe_cntx_num) {
5407         case I40E_DMA_CNTX_SIZE_512:
5408         case I40E_DMA_CNTX_SIZE_1K:
5409         case I40E_DMA_CNTX_SIZE_2K:
5410         case I40E_DMA_CNTX_SIZE_4K:
5411         case I40E_DMA_CNTX_SIZE_8K:
5412         case I40E_DMA_CNTX_SIZE_16K:
5413         case I40E_DMA_CNTX_SIZE_32K:
5414         case I40E_DMA_CNTX_SIZE_64K:
5415         case I40E_DMA_CNTX_SIZE_128K:
5416         case I40E_DMA_CNTX_SIZE_256K:
5417                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5418                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5419                 break;
5420         default:
5421                 return I40E_ERR_PARAM;
5422         }
5423
5424         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5425         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5426         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5427                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5428         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
5429                 return I40E_ERR_INVALID_SIZE;
5430
5431         return I40E_SUCCESS;
5432 }
5433
5434 /**
5435  * i40e_set_filter_control
5436  * @hw: pointer to the hardware structure
5437  * @settings: Filter control settings
5438  *
5439  * Set the Queue Filters for PE/FCoE and enable filters required
5440  * for a single PF. It is expected that these settings are programmed
5441  * at the driver initialization time.
5442  **/
5443 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5444                                 struct i40e_filter_control_settings *settings)
5445 {
5446         enum i40e_status_code ret = I40E_SUCCESS;
5447         u32 hash_lut_size = 0;
5448         u32 val;
5449
5450         if (!settings)
5451                 return I40E_ERR_PARAM;
5452
5453         /* Validate the input settings */
5454         ret = i40e_validate_filter_settings(hw, settings);
5455         if (ret)
5456                 return ret;
5457
5458         /* Read the PF Queue Filter control register */
5459         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5460
5461         /* Program required PE hash buckets for the PF */
5462         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5463         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5464                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5465         /* Program required PE contexts for the PF */
5466         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5467         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5468                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5469
5470         /* Program required FCoE hash buckets for the PF */
5471         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5472         val |= ((u32)settings->fcoe_filt_num <<
5473                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5474                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5475         /* Program required FCoE DDP contexts for the PF */
5476         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5477         val |= ((u32)settings->fcoe_cntx_num <<
5478                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5479                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5480
5481         /* Program Hash LUT size for the PF */
5482         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5483         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5484                 hash_lut_size = 1;
5485         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5486                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5487
5488         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5489         if (settings->enable_fdir)
5490                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5491         if (settings->enable_ethtype)
5492                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5493         if (settings->enable_macvlan)
5494                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5495
5496         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5497
5498         return I40E_SUCCESS;
5499 }
5500
5501 /**
5502  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5503  * @hw: pointer to the hw struct
5504  * @mac_addr: MAC address to use in the filter
5505  * @ethtype: Ethertype to use in the filter
5506  * @flags: Flags that needs to be applied to the filter
5507  * @vsi_seid: seid of the control VSI
5508  * @queue: VSI queue number to send the packet to
5509  * @is_add: Add control packet filter if True else remove
5510  * @stats: Structure to hold information on control filter counts
5511  * @cmd_details: pointer to command details structure or NULL
5512  *
5513  * This command will Add or Remove control packet filter for a control VSI.
5514  * In return it will update the total number of perfect filter count in
5515  * the stats member.
5516  **/
5517 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5518                                 u8 *mac_addr, u16 ethtype, u16 flags,
5519                                 u16 vsi_seid, u16 queue, bool is_add,
5520                                 struct i40e_control_filter_stats *stats,
5521                                 struct i40e_asq_cmd_details *cmd_details)
5522 {
5523         struct i40e_aq_desc desc;
5524         struct i40e_aqc_add_remove_control_packet_filter *cmd =
5525                 (struct i40e_aqc_add_remove_control_packet_filter *)
5526                 &desc.params.raw;
5527         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5528                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5529                 &desc.params.raw;
5530         enum i40e_status_code status;
5531
5532         if (vsi_seid == 0)
5533                 return I40E_ERR_PARAM;
5534
5535         if (is_add) {
5536                 i40e_fill_default_direct_cmd_desc(&desc,
5537                                 i40e_aqc_opc_add_control_packet_filter);
5538                 cmd->queue = CPU_TO_LE16(queue);
5539         } else {
5540                 i40e_fill_default_direct_cmd_desc(&desc,
5541                                 i40e_aqc_opc_remove_control_packet_filter);
5542         }
5543
5544         if (mac_addr)
5545                 i40e_memcpy(cmd->mac, mac_addr, ETH_ALEN,
5546                             I40E_NONDMA_TO_NONDMA);
5547
5548         cmd->etype = CPU_TO_LE16(ethtype);
5549         cmd->flags = CPU_TO_LE16(flags);
5550         cmd->seid = CPU_TO_LE16(vsi_seid);
5551
5552         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5553
5554         if (!status && stats) {
5555                 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5556                 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5557                 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5558                 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5559         }
5560
5561         return status;
5562 }
5563
5564 /**
5565  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5566  * @hw: pointer to the hw struct
5567  * @seid: VSI seid to add ethertype filter from
5568  **/
5569 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5570 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5571                                                     u16 seid)
5572 {
5573         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5574                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5575                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5576         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5577         enum i40e_status_code status;
5578
5579         status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5580                                                        seid, 0, true, NULL,
5581                                                        NULL);
5582         if (status)
5583                 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5584 }
5585
5586 /**
5587  * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5588  * @filters: list of cloud filters
5589  * @filter_count: length of list
5590  *
5591  * There's an issue in the device where the Geneve VNI layout needs
5592  * to be shifted 1 byte over from the VxLAN VNI
5593  **/
5594 STATIC void i40e_fix_up_geneve_vni(
5595         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5596         u8 filter_count)
5597 {
5598         struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters;
5599         int i;
5600
5601         for (i = 0; i < filter_count; i++) {
5602                 u16 tnl_type;
5603                 u32 ti;
5604
5605                 tnl_type = (LE16_TO_CPU(f[i].flags) &
5606                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5607                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5608                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5609                         ti = LE32_TO_CPU(f[i].tenant_id);
5610                         f[i].tenant_id = CPU_TO_LE32(ti << 8);
5611                 }
5612         }
5613 }
5614
5615 /**
5616  * i40e_aq_add_cloud_filters
5617  * @hw: pointer to the hardware structure
5618  * @seid: VSI seid to add cloud filters from
5619  * @filters: Buffer which contains the filters to be added
5620  * @filter_count: number of filters contained in the buffer
5621  *
5622  * Set the cloud filters for a given VSI.  The contents of the
5623  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5624  * in by the caller of the function.
5625  *
5626  **/
5627 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5628         u16 seid,
5629         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5630         u8 filter_count)
5631 {
5632         struct i40e_aq_desc desc;
5633         struct i40e_aqc_add_remove_cloud_filters *cmd =
5634         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5635         enum i40e_status_code status;
5636         u16 buff_len;
5637
5638         i40e_fill_default_direct_cmd_desc(&desc,
5639                                           i40e_aqc_opc_add_cloud_filters);
5640
5641         buff_len = filter_count * sizeof(*filters);
5642         desc.datalen = CPU_TO_LE16(buff_len);
5643         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5644         cmd->num_filters = filter_count;
5645         cmd->seid = CPU_TO_LE16(seid);
5646
5647         i40e_fix_up_geneve_vni(filters, filter_count);
5648
5649         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5650
5651         return status;
5652 }
5653
5654 /**
5655  * i40e_aq_add_cloud_filters_big_buffer
5656  * @hw: pointer to the hardware structure
5657  * @seid: VSI seid to add cloud filters from
5658  * @filters: Buffer which contains the filters in big buffer to be added
5659  * @filter_count: number of filters contained in the buffer
5660  *
5661  * Set the cloud filters for a given VSI.  The contents of the
5662  * i40e_aqc_add_rm_cloud_filt_elem_ext are filled in by the caller of
5663  * the function.
5664  *
5665  **/
5666 enum i40e_status_code i40e_aq_add_cloud_filters_big_buffer(struct i40e_hw *hw,
5667         u16 seid,
5668         struct i40e_aqc_add_rm_cloud_filt_elem_ext *filters,
5669         u8 filter_count)
5670 {
5671         struct i40e_aq_desc desc;
5672         struct i40e_aqc_add_remove_cloud_filters *cmd =
5673         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5674         enum i40e_status_code status;
5675         u16 buff_len;
5676         int i;
5677
5678         i40e_fill_default_direct_cmd_desc(&desc,
5679                                           i40e_aqc_opc_add_cloud_filters);
5680
5681         buff_len = filter_count * sizeof(*filters);
5682         desc.datalen = CPU_TO_LE16(buff_len);
5683         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5684         cmd->num_filters = filter_count;
5685         cmd->seid = CPU_TO_LE16(seid);
5686         cmd->big_buffer_flag = I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER;
5687
5688         /* adjust Geneve VNI for HW issue */
5689         for (i = 0; i < filter_count; i++) {
5690                 u16 tnl_type;
5691                 u32 ti;
5692
5693                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5694                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5695                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5696                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5697                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5698                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5699                 }
5700         }
5701
5702         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5703
5704         return status;
5705 }
5706
5707 /**
5708  * i40e_aq_remove_cloud_filters
5709  * @hw: pointer to the hardware structure
5710  * @seid: VSI seid to remove cloud filters from
5711  * @filters: Buffer which contains the filters to be removed
5712  * @filter_count: number of filters contained in the buffer
5713  *
5714  * Remove the cloud filters for a given VSI.  The contents of the
5715  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5716  * in by the caller of the function.
5717  *
5718  **/
5719 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5720         u16 seid,
5721         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5722         u8 filter_count)
5723 {
5724         struct i40e_aq_desc desc;
5725         struct i40e_aqc_add_remove_cloud_filters *cmd =
5726         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5727         enum i40e_status_code status;
5728         u16 buff_len;
5729
5730         i40e_fill_default_direct_cmd_desc(&desc,
5731                                           i40e_aqc_opc_remove_cloud_filters);
5732
5733         buff_len = filter_count * sizeof(*filters);
5734         desc.datalen = CPU_TO_LE16(buff_len);
5735         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5736         cmd->num_filters = filter_count;
5737         cmd->seid = CPU_TO_LE16(seid);
5738
5739         i40e_fix_up_geneve_vni(filters, filter_count);
5740
5741         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5742
5743         return status;
5744 }
5745
5746 /**
5747  * i40e_aq_remove_cloud_filters_big_buffer
5748  * @hw: pointer to the hardware structure
5749  * @seid: VSI seid to remove cloud filters from
5750  * @filters: Buffer which contains the filters in big buffer to be removed
5751  * @filter_count: number of filters contained in the buffer
5752  *
5753  * Remove the cloud filters for a given VSI.  The contents of the
5754  * i40e_aqc_add_rm_cloud_filt_elem_ext are filled in by the caller of
5755  * the function.
5756  *
5757  **/
5758 enum i40e_status_code i40e_aq_remove_cloud_filters_big_buffer(
5759         struct i40e_hw *hw,
5760         u16 seid,
5761         struct i40e_aqc_add_rm_cloud_filt_elem_ext *filters,
5762         u8 filter_count)
5763 {
5764         struct i40e_aq_desc desc;
5765         struct i40e_aqc_add_remove_cloud_filters *cmd =
5766         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5767         enum i40e_status_code status;
5768         u16 buff_len;
5769         int i;
5770
5771         i40e_fill_default_direct_cmd_desc(&desc,
5772                                           i40e_aqc_opc_remove_cloud_filters);
5773
5774         buff_len = filter_count * sizeof(*filters);
5775         desc.datalen = CPU_TO_LE16(buff_len);
5776         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5777         cmd->num_filters = filter_count;
5778         cmd->seid = CPU_TO_LE16(seid);
5779         cmd->big_buffer_flag = I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER;
5780
5781         /* adjust Geneve VNI for HW issue */
5782         for (i = 0; i < filter_count; i++) {
5783                 u16 tnl_type;
5784                 u32 ti;
5785
5786                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5787                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5788                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5789                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5790                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5791                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5792                 }
5793         }
5794
5795         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5796
5797         return status;
5798 }
5799
5800 /**
5801  * i40e_aq_replace_cloud_filters - Replace cloud filter command
5802  * @hw: pointer to the hw struct
5803  * @filters: pointer to the i40e_aqc_replace_cloud_filter_cmd struct
5804  * @cmd_buf: pointer to the i40e_aqc_replace_cloud_filter_cmd_buf struct
5805  *
5806  **/
5807 enum
5808 i40e_status_code i40e_aq_replace_cloud_filters(struct i40e_hw *hw,
5809         struct i40e_aqc_replace_cloud_filters_cmd *filters,
5810         struct i40e_aqc_replace_cloud_filters_cmd_buf *cmd_buf)
5811 {
5812         struct i40e_aq_desc desc;
5813         struct i40e_aqc_replace_cloud_filters_cmd *cmd =
5814                 (struct i40e_aqc_replace_cloud_filters_cmd *)&desc.params.raw;
5815         enum i40e_status_code status = I40E_SUCCESS;
5816         int i = 0;
5817
5818         i40e_fill_default_direct_cmd_desc(&desc,
5819                                           i40e_aqc_opc_replace_cloud_filters);
5820
5821         desc.datalen = CPU_TO_LE16(32);
5822         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5823         cmd->old_filter_type = filters->old_filter_type;
5824         cmd->new_filter_type = filters->new_filter_type;
5825         cmd->valid_flags = filters->valid_flags;
5826         cmd->tr_bit = filters->tr_bit;
5827
5828         status = i40e_asq_send_command(hw, &desc, cmd_buf,
5829                 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf),  NULL);
5830
5831         /* for get cloud filters command */
5832         for (i = 0; i < 32; i += 4) {
5833                 cmd_buf->filters[i / 4].filter_type = cmd_buf->data[i];
5834                 cmd_buf->filters[i / 4].input[0] = cmd_buf->data[i + 1];
5835                 cmd_buf->filters[i / 4].input[1] = cmd_buf->data[i + 2];
5836                 cmd_buf->filters[i / 4].input[2] = cmd_buf->data[i + 3];
5837         }
5838
5839         return status;
5840 }
5841
5842
5843 /**
5844  * i40e_aq_alternate_write
5845  * @hw: pointer to the hardware structure
5846  * @reg_addr0: address of first dword to be read
5847  * @reg_val0: value to be written under 'reg_addr0'
5848  * @reg_addr1: address of second dword to be read
5849  * @reg_val1: value to be written under 'reg_addr1'
5850  *
5851  * Write one or two dwords to alternate structure. Fields are indicated
5852  * by 'reg_addr0' and 'reg_addr1' register numbers.
5853  *
5854  **/
5855 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5856                                 u32 reg_addr0, u32 reg_val0,
5857                                 u32 reg_addr1, u32 reg_val1)
5858 {
5859         struct i40e_aq_desc desc;
5860         struct i40e_aqc_alternate_write *cmd_resp =
5861                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5862         enum i40e_status_code status;
5863
5864         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5865         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5866         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5867         cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5868         cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5869
5870         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5871
5872         return status;
5873 }
5874
5875 /**
5876  * i40e_aq_alternate_write_indirect
5877  * @hw: pointer to the hardware structure
5878  * @addr: address of a first register to be modified
5879  * @dw_count: number of alternate structure fields to write
5880  * @buffer: pointer to the command buffer
5881  *
5882  * Write 'dw_count' dwords from 'buffer' to alternate structure
5883  * starting at 'addr'.
5884  *
5885  **/
5886 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5887                                 u32 addr, u32 dw_count, void *buffer)
5888 {
5889         struct i40e_aq_desc desc;
5890         struct i40e_aqc_alternate_ind_write *cmd_resp =
5891                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5892         enum i40e_status_code status;
5893
5894         if (buffer == NULL)
5895                 return I40E_ERR_PARAM;
5896
5897         /* Indirect command */
5898         i40e_fill_default_direct_cmd_desc(&desc,
5899                                          i40e_aqc_opc_alternate_write_indirect);
5900
5901         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5902         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5903         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5904                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5905
5906         cmd_resp->address = CPU_TO_LE32(addr);
5907         cmd_resp->length = CPU_TO_LE32(dw_count);
5908
5909         status = i40e_asq_send_command(hw, &desc, buffer,
5910                                        I40E_LO_DWORD(4*dw_count), NULL);
5911
5912         return status;
5913 }
5914
5915 /**
5916  * i40e_aq_alternate_read
5917  * @hw: pointer to the hardware structure
5918  * @reg_addr0: address of first dword to be read
5919  * @reg_val0: pointer for data read from 'reg_addr0'
5920  * @reg_addr1: address of second dword to be read
5921  * @reg_val1: pointer for data read from 'reg_addr1'
5922  *
5923  * Read one or two dwords from alternate structure. Fields are indicated
5924  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5925  * is not passed then only register at 'reg_addr0' is read.
5926  *
5927  **/
5928 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5929                                 u32 reg_addr0, u32 *reg_val0,
5930                                 u32 reg_addr1, u32 *reg_val1)
5931 {
5932         struct i40e_aq_desc desc;
5933         struct i40e_aqc_alternate_write *cmd_resp =
5934                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5935         enum i40e_status_code status;
5936
5937         if (reg_val0 == NULL)
5938                 return I40E_ERR_PARAM;
5939
5940         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5941         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5942         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5943
5944         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5945
5946         if (status == I40E_SUCCESS) {
5947                 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5948
5949                 if (reg_val1 != NULL)
5950                         *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5951         }
5952
5953         return status;
5954 }
5955
5956 /**
5957  * i40e_aq_alternate_read_indirect
5958  * @hw: pointer to the hardware structure
5959  * @addr: address of the alternate structure field
5960  * @dw_count: number of alternate structure fields to read
5961  * @buffer: pointer to the command buffer
5962  *
5963  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5964  * place them in 'buffer'. The buffer should be allocated by caller.
5965  *
5966  **/
5967 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5968                                 u32 addr, u32 dw_count, void *buffer)
5969 {
5970         struct i40e_aq_desc desc;
5971         struct i40e_aqc_alternate_ind_write *cmd_resp =
5972                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5973         enum i40e_status_code status;
5974
5975         if (buffer == NULL)
5976                 return I40E_ERR_PARAM;
5977
5978         /* Indirect command */
5979         i40e_fill_default_direct_cmd_desc(&desc,
5980                 i40e_aqc_opc_alternate_read_indirect);
5981
5982         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5983         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5984         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5985                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5986
5987         cmd_resp->address = CPU_TO_LE32(addr);
5988         cmd_resp->length = CPU_TO_LE32(dw_count);
5989
5990         status = i40e_asq_send_command(hw, &desc, buffer,
5991                                        I40E_LO_DWORD(4*dw_count), NULL);
5992
5993         return status;
5994 }
5995
5996 /**
5997  *  i40e_aq_alternate_clear
5998  *  @hw: pointer to the HW structure.
5999  *
6000  *  Clear the alternate structures of the port from which the function
6001  *  is called.
6002  *
6003  **/
6004 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
6005 {
6006         struct i40e_aq_desc desc;
6007         enum i40e_status_code status;
6008
6009         i40e_fill_default_direct_cmd_desc(&desc,
6010                                           i40e_aqc_opc_alternate_clear_port);
6011
6012         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6013
6014         return status;
6015 }
6016
6017 /**
6018  *  i40e_aq_alternate_write_done
6019  *  @hw: pointer to the HW structure.
6020  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
6021  *  @reset_needed: indicates the SW should trigger GLOBAL reset
6022  *
6023  *  Indicates to the FW that alternate structures have been changed.
6024  *
6025  **/
6026 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
6027                 u8 bios_mode, bool *reset_needed)
6028 {
6029         struct i40e_aq_desc desc;
6030         struct i40e_aqc_alternate_write_done *cmd =
6031                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6032         enum i40e_status_code status;
6033
6034         if (reset_needed == NULL)
6035                 return I40E_ERR_PARAM;
6036
6037         i40e_fill_default_direct_cmd_desc(&desc,
6038                                           i40e_aqc_opc_alternate_write_done);
6039
6040         cmd->cmd_flags = CPU_TO_LE16(bios_mode);
6041
6042         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6043         if (!status && reset_needed)
6044                 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
6045                                  I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
6046
6047         return status;
6048 }
6049
6050 /**
6051  *  i40e_aq_set_oem_mode
6052  *  @hw: pointer to the HW structure.
6053  *  @oem_mode: the OEM mode to be used
6054  *
6055  *  Sets the device to a specific operating mode. Currently the only supported
6056  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
6057  *
6058  **/
6059 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
6060                 u8 oem_mode)
6061 {
6062         struct i40e_aq_desc desc;
6063         struct i40e_aqc_alternate_write_done *cmd =
6064                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6065         enum i40e_status_code status;
6066
6067         i40e_fill_default_direct_cmd_desc(&desc,
6068                                           i40e_aqc_opc_alternate_set_mode);
6069
6070         cmd->cmd_flags = CPU_TO_LE16(oem_mode);
6071
6072         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6073
6074         return status;
6075 }
6076
6077 /**
6078  * i40e_aq_resume_port_tx
6079  * @hw: pointer to the hardware structure
6080  * @cmd_details: pointer to command details structure or NULL
6081  *
6082  * Resume port's Tx traffic
6083  **/
6084 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
6085                                 struct i40e_asq_cmd_details *cmd_details)
6086 {
6087         struct i40e_aq_desc desc;
6088         enum i40e_status_code status;
6089
6090         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
6091
6092         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6093
6094         return status;
6095 }
6096
6097 /**
6098  * i40e_set_pci_config_data - store PCI bus info
6099  * @hw: pointer to hardware structure
6100  * @link_status: the link status word from PCI config space
6101  *
6102  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
6103  **/
6104 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
6105 {
6106         hw->bus.type = i40e_bus_type_pci_express;
6107
6108         switch (link_status & I40E_PCI_LINK_WIDTH) {
6109         case I40E_PCI_LINK_WIDTH_1:
6110                 hw->bus.width = i40e_bus_width_pcie_x1;
6111                 break;
6112         case I40E_PCI_LINK_WIDTH_2:
6113                 hw->bus.width = i40e_bus_width_pcie_x2;
6114                 break;
6115         case I40E_PCI_LINK_WIDTH_4:
6116                 hw->bus.width = i40e_bus_width_pcie_x4;
6117                 break;
6118         case I40E_PCI_LINK_WIDTH_8:
6119                 hw->bus.width = i40e_bus_width_pcie_x8;
6120                 break;
6121         default:
6122                 hw->bus.width = i40e_bus_width_unknown;
6123                 break;
6124         }
6125
6126         switch (link_status & I40E_PCI_LINK_SPEED) {
6127         case I40E_PCI_LINK_SPEED_2500:
6128                 hw->bus.speed = i40e_bus_speed_2500;
6129                 break;
6130         case I40E_PCI_LINK_SPEED_5000:
6131                 hw->bus.speed = i40e_bus_speed_5000;
6132                 break;
6133         case I40E_PCI_LINK_SPEED_8000:
6134                 hw->bus.speed = i40e_bus_speed_8000;
6135                 break;
6136         default:
6137                 hw->bus.speed = i40e_bus_speed_unknown;
6138                 break;
6139         }
6140 }
6141
6142 /**
6143  * i40e_aq_debug_dump
6144  * @hw: pointer to the hardware structure
6145  * @cluster_id: specific cluster to dump
6146  * @table_id: table id within cluster
6147  * @start_index: index of line in the block to read
6148  * @buff_size: dump buffer size
6149  * @buff: dump buffer
6150  * @ret_buff_size: actual buffer size returned
6151  * @ret_next_table: next block to read
6152  * @ret_next_index: next index to read
6153  *
6154  * Dump internal FW/HW data for debug purposes.
6155  *
6156  **/
6157 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
6158                                 u8 table_id, u32 start_index, u16 buff_size,
6159                                 void *buff, u16 *ret_buff_size,
6160                                 u8 *ret_next_table, u32 *ret_next_index,
6161                                 struct i40e_asq_cmd_details *cmd_details)
6162 {
6163         struct i40e_aq_desc desc;
6164         struct i40e_aqc_debug_dump_internals *cmd =
6165                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6166         struct i40e_aqc_debug_dump_internals *resp =
6167                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6168         enum i40e_status_code status;
6169
6170         if (buff_size == 0 || !buff)
6171                 return I40E_ERR_PARAM;
6172
6173         i40e_fill_default_direct_cmd_desc(&desc,
6174                                           i40e_aqc_opc_debug_dump_internals);
6175         /* Indirect Command */
6176         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6177         if (buff_size > I40E_AQ_LARGE_BUF)
6178                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6179
6180         cmd->cluster_id = cluster_id;
6181         cmd->table_id = table_id;
6182         cmd->idx = CPU_TO_LE32(start_index);
6183
6184         desc.datalen = CPU_TO_LE16(buff_size);
6185
6186         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
6187         if (!status) {
6188                 if (ret_buff_size != NULL)
6189                         *ret_buff_size = LE16_TO_CPU(desc.datalen);
6190                 if (ret_next_table != NULL)
6191                         *ret_next_table = resp->table_id;
6192                 if (ret_next_index != NULL)
6193                         *ret_next_index = LE32_TO_CPU(resp->idx);
6194         }
6195
6196         return status;
6197 }
6198
6199 /**
6200  * i40e_read_bw_from_alt_ram
6201  * @hw: pointer to the hardware structure
6202  * @max_bw: pointer for max_bw read
6203  * @min_bw: pointer for min_bw read
6204  * @min_valid: pointer for bool that is true if min_bw is a valid value
6205  * @max_valid: pointer for bool that is true if max_bw is a valid value
6206  *
6207  * Read bw from the alternate ram for the given pf
6208  **/
6209 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
6210                                         u32 *max_bw, u32 *min_bw,
6211                                         bool *min_valid, bool *max_valid)
6212 {
6213         enum i40e_status_code status;
6214         u32 max_bw_addr, min_bw_addr;
6215
6216         /* Calculate the address of the min/max bw registers */
6217         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6218                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
6219                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6220         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6221                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
6222                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6223
6224         /* Read the bandwidths from alt ram */
6225         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
6226                                         min_bw_addr, min_bw);
6227
6228         if (*min_bw & I40E_ALT_BW_VALID_MASK)
6229                 *min_valid = true;
6230         else
6231                 *min_valid = false;
6232
6233         if (*max_bw & I40E_ALT_BW_VALID_MASK)
6234                 *max_valid = true;
6235         else
6236                 *max_valid = false;
6237
6238         return status;
6239 }
6240
6241 /**
6242  * i40e_aq_configure_partition_bw
6243  * @hw: pointer to the hardware structure
6244  * @bw_data: Buffer holding valid pfs and bw limits
6245  * @cmd_details: pointer to command details
6246  *
6247  * Configure partitions guaranteed/max bw
6248  **/
6249 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6250                         struct i40e_aqc_configure_partition_bw_data *bw_data,
6251                         struct i40e_asq_cmd_details *cmd_details)
6252 {
6253         enum i40e_status_code status;
6254         struct i40e_aq_desc desc;
6255         u16 bwd_size = sizeof(*bw_data);
6256
6257         i40e_fill_default_direct_cmd_desc(&desc,
6258                                 i40e_aqc_opc_configure_partition_bw);
6259
6260         /* Indirect command */
6261         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6262         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6263
6264         desc.datalen = CPU_TO_LE16(bwd_size);
6265
6266         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6267
6268         return status;
6269 }
6270
6271 /**
6272  * i40e_read_phy_register_clause22
6273  * @hw: pointer to the HW structure
6274  * @reg: register address in the page
6275  * @phy_adr: PHY address on MDIO interface
6276  * @value: PHY register value
6277  *
6278  * Reads specified PHY register value
6279  **/
6280 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
6281                                         u16 reg, u8 phy_addr, u16 *value)
6282 {
6283         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6284         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6285         u32 command = 0;
6286         u16 retry = 1000;
6287
6288         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6289                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6290                   (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
6291                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6292                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6293         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6294         do {
6295                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6296                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6297                         status = I40E_SUCCESS;
6298                         break;
6299                 }
6300                 i40e_usec_delay(10);
6301                 retry--;
6302         } while (retry);
6303
6304         if (status) {
6305                 i40e_debug(hw, I40E_DEBUG_PHY,
6306                            "PHY: Can't write command to external PHY.\n");
6307         } else {
6308                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6309                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6310                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6311         }
6312
6313         return status;
6314 }
6315
6316 /**
6317  * i40e_write_phy_register_clause22
6318  * @hw: pointer to the HW structure
6319  * @reg: register address in the page
6320  * @phy_adr: PHY address on MDIO interface
6321  * @value: PHY register value
6322  *
6323  * Writes specified PHY register value
6324  **/
6325 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6326                                         u16 reg, u8 phy_addr, u16 value)
6327 {
6328         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6329         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6330         u32 command  = 0;
6331         u16 retry = 1000;
6332
6333         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6334         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6335
6336         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6337                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6338                   (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6339                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6340                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6341
6342         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6343         do {
6344                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6345                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6346                         status = I40E_SUCCESS;
6347                         break;
6348                 }
6349                 i40e_usec_delay(10);
6350                 retry--;
6351         } while (retry);
6352
6353         return status;
6354 }
6355
6356 /**
6357  * i40e_read_phy_register_clause45
6358  * @hw: pointer to the HW structure
6359  * @page: registers page number
6360  * @reg: register address in the page
6361  * @phy_adr: PHY address on MDIO interface
6362  * @value: PHY register value
6363  *
6364  * Reads specified PHY register value
6365  **/
6366 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6367                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6368 {
6369         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6370         u32 command  = 0;
6371         u16 retry = 1000;
6372         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6373
6374         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6375                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6376                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6377                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6378                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6379                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6380                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6381         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6382         do {
6383                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6384                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6385                         status = I40E_SUCCESS;
6386                         break;
6387                 }
6388                 i40e_usec_delay(10);
6389                 retry--;
6390         } while (retry);
6391
6392         if (status) {
6393                 i40e_debug(hw, I40E_DEBUG_PHY,
6394                            "PHY: Can't write command to external PHY.\n");
6395                 goto phy_read_end;
6396         }
6397
6398         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6399                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6400                   (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6401                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6402                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6403                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6404         status = I40E_ERR_TIMEOUT;
6405         retry = 1000;
6406         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6407         do {
6408                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6409                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6410                         status = I40E_SUCCESS;
6411                         break;
6412                 }
6413                 i40e_usec_delay(10);
6414                 retry--;
6415         } while (retry);
6416
6417         if (!status) {
6418                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6419                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6420                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6421         } else {
6422                 i40e_debug(hw, I40E_DEBUG_PHY,
6423                            "PHY: Can't read register value from external PHY.\n");
6424         }
6425
6426 phy_read_end:
6427         return status;
6428 }
6429
6430 /**
6431  * i40e_write_phy_register_clause45
6432  * @hw: pointer to the HW structure
6433  * @page: registers page number
6434  * @reg: register address in the page
6435  * @phy_adr: PHY address on MDIO interface
6436  * @value: PHY register value
6437  *
6438  * Writes value to specified PHY register
6439  **/
6440 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6441                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6442 {
6443         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6444         u32 command  = 0;
6445         u16 retry = 1000;
6446         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6447
6448         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6449                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6450                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6451                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6452                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6453                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6454                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6455         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6456         do {
6457                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6458                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6459                         status = I40E_SUCCESS;
6460                         break;
6461                 }
6462                 i40e_usec_delay(10);
6463                 retry--;
6464         } while (retry);
6465         if (status) {
6466                 i40e_debug(hw, I40E_DEBUG_PHY,
6467                            "PHY: Can't write command to external PHY.\n");
6468                 goto phy_write_end;
6469         }
6470
6471         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6472         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6473
6474         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6475                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6476                   (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6477                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6478                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6479                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6480         status = I40E_ERR_TIMEOUT;
6481         retry = 1000;
6482         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6483         do {
6484                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6485                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6486                         status = I40E_SUCCESS;
6487                         break;
6488                 }
6489                 i40e_usec_delay(10);
6490                 retry--;
6491         } while (retry);
6492
6493 phy_write_end:
6494         return status;
6495 }
6496
6497 /**
6498  * i40e_write_phy_register
6499  * @hw: pointer to the HW structure
6500  * @page: registers page number
6501  * @reg: register address in the page
6502  * @phy_adr: PHY address on MDIO interface
6503  * @value: PHY register value
6504  *
6505  * Writes value to specified PHY register
6506  **/
6507 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6508                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6509 {
6510         enum i40e_status_code status;
6511
6512         switch (hw->device_id) {
6513         case I40E_DEV_ID_1G_BASE_T_X722:
6514                 status = i40e_write_phy_register_clause22(hw,
6515                         reg, phy_addr, value);
6516                 break;
6517         case I40E_DEV_ID_10G_BASE_T:
6518         case I40E_DEV_ID_10G_BASE_T4:
6519         case I40E_DEV_ID_10G_BASE_T_X722:
6520         case I40E_DEV_ID_25G_B:
6521         case I40E_DEV_ID_25G_SFP28:
6522                 status = i40e_write_phy_register_clause45(hw,
6523                         page, reg, phy_addr, value);
6524                 break;
6525         default:
6526                 status = I40E_ERR_UNKNOWN_PHY;
6527                 break;
6528         }
6529
6530         return status;
6531 }
6532
6533 /**
6534  * i40e_read_phy_register
6535  * @hw: pointer to the HW structure
6536  * @page: registers page number
6537  * @reg: register address in the page
6538  * @phy_adr: PHY address on MDIO interface
6539  * @value: PHY register value
6540  *
6541  * Reads specified PHY register value
6542  **/
6543 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6544                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6545 {
6546         enum i40e_status_code status;
6547
6548         switch (hw->device_id) {
6549         case I40E_DEV_ID_1G_BASE_T_X722:
6550                 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6551                                                          value);
6552                 break;
6553         case I40E_DEV_ID_10G_BASE_T:
6554         case I40E_DEV_ID_10G_BASE_T4:
6555         case I40E_DEV_ID_10G_BASE_T_X722:
6556         case I40E_DEV_ID_25G_B:
6557         case I40E_DEV_ID_25G_SFP28:
6558                 status = i40e_read_phy_register_clause45(hw, page, reg,
6559                                                          phy_addr, value);
6560                 break;
6561         default:
6562                 status = I40E_ERR_UNKNOWN_PHY;
6563                 break;
6564         }
6565
6566         return status;
6567 }
6568
6569 /**
6570  * i40e_get_phy_address
6571  * @hw: pointer to the HW structure
6572  * @dev_num: PHY port num that address we want
6573  * @phy_addr: Returned PHY address
6574  *
6575  * Gets PHY address for current port
6576  **/
6577 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6578 {
6579         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6580         u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6581
6582         return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6583 }
6584
6585 /**
6586  * i40e_blink_phy_led
6587  * @hw: pointer to the HW structure
6588  * @time: time how long led will blinks in secs
6589  * @interval: gap between LED on and off in msecs
6590  *
6591  * Blinks PHY link LED
6592  **/
6593 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6594                                               u32 time, u32 interval)
6595 {
6596         enum i40e_status_code status = I40E_SUCCESS;
6597         u32 i;
6598         u16 led_ctl = 0;
6599         u16 gpio_led_port;
6600         u16 led_reg;
6601         u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6602         u8 phy_addr = 0;
6603         u8 port_num;
6604
6605         i = rd32(hw, I40E_PFGEN_PORTNUM);
6606         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6607         phy_addr = i40e_get_phy_address(hw, port_num);
6608
6609         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6610              led_addr++) {
6611                 status = i40e_read_phy_register_clause45(hw,
6612                                                          I40E_PHY_COM_REG_PAGE,
6613                                                          led_addr, phy_addr,
6614                                                          &led_reg);
6615                 if (status)
6616                         goto phy_blinking_end;
6617                 led_ctl = led_reg;
6618                 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6619                         led_reg = 0;
6620                         status = i40e_write_phy_register_clause45(hw,
6621                                                          I40E_PHY_COM_REG_PAGE,
6622                                                          led_addr, phy_addr,
6623                                                          led_reg);
6624                         if (status)
6625                                 goto phy_blinking_end;
6626                         break;
6627                 }
6628         }
6629
6630         if (time > 0 && interval > 0) {
6631                 for (i = 0; i < time * 1000; i += interval) {
6632                         status = i40e_read_phy_register_clause45(hw,
6633                                                 I40E_PHY_COM_REG_PAGE,
6634                                                 led_addr, phy_addr, &led_reg);
6635                         if (status)
6636                                 goto restore_config;
6637                         if (led_reg & I40E_PHY_LED_MANUAL_ON)
6638                                 led_reg = 0;
6639                         else
6640                                 led_reg = I40E_PHY_LED_MANUAL_ON;
6641                         status = i40e_write_phy_register_clause45(hw,
6642                                                 I40E_PHY_COM_REG_PAGE,
6643                                                 led_addr, phy_addr, led_reg);
6644                         if (status)
6645                                 goto restore_config;
6646                         i40e_msec_delay(interval);
6647                 }
6648         }
6649
6650 restore_config:
6651         status = i40e_write_phy_register_clause45(hw,
6652                                                   I40E_PHY_COM_REG_PAGE,
6653                                                   led_addr, phy_addr, led_ctl);
6654
6655 phy_blinking_end:
6656         return status;
6657 }
6658
6659 /**
6660  * i40e_led_get_phy - return current on/off mode
6661  * @hw: pointer to the hw struct
6662  * @led_addr: address of led register to use
6663  * @val: original value of register to use
6664  *
6665  **/
6666 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6667                                        u16 *val)
6668 {
6669         enum i40e_status_code status = I40E_SUCCESS;
6670         u16 gpio_led_port;
6671         u8 phy_addr = 0;
6672         u16 reg_val;
6673         u16 temp_addr;
6674         u8 port_num;
6675         u32 i;
6676
6677         temp_addr = I40E_PHY_LED_PROV_REG_1;
6678         i = rd32(hw, I40E_PFGEN_PORTNUM);
6679         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6680         phy_addr = i40e_get_phy_address(hw, port_num);
6681
6682         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6683              temp_addr++) {
6684                 status = i40e_read_phy_register_clause45(hw,
6685                                                          I40E_PHY_COM_REG_PAGE,
6686                                                          temp_addr, phy_addr,
6687                                                          &reg_val);
6688                 if (status)
6689                         return status;
6690                 *val = reg_val;
6691                 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6692                         *led_addr = temp_addr;
6693                         break;
6694                 }
6695         }
6696         return status;
6697 }
6698
6699 /**
6700  * i40e_led_set_phy
6701  * @hw: pointer to the HW structure
6702  * @on: true or false
6703  * @mode: original val plus bit for set or ignore
6704  * Set led's on or off when controlled by the PHY
6705  *
6706  **/
6707 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6708                                        u16 led_addr, u32 mode)
6709 {
6710         enum i40e_status_code status = I40E_SUCCESS;
6711         u16 led_ctl = 0;
6712         u16 led_reg = 0;
6713         u8 phy_addr = 0;
6714         u8 port_num;
6715         u32 i;
6716
6717         i = rd32(hw, I40E_PFGEN_PORTNUM);
6718         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6719         phy_addr = i40e_get_phy_address(hw, port_num);
6720         status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6721                                                  led_addr, phy_addr, &led_reg);
6722         if (status)
6723                 return status;
6724         led_ctl = led_reg;
6725         if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6726                 led_reg = 0;
6727                 status = i40e_write_phy_register_clause45(hw,
6728                                                           I40E_PHY_COM_REG_PAGE,
6729                                                           led_addr, phy_addr,
6730                                                           led_reg);
6731                 if (status)
6732                         return status;
6733         }
6734         status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6735                                                  led_addr, phy_addr, &led_reg);
6736         if (status)
6737                 goto restore_config;
6738         if (on)
6739                 led_reg = I40E_PHY_LED_MANUAL_ON;
6740         else
6741                 led_reg = 0;
6742         status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6743                                                   led_addr, phy_addr, led_reg);
6744         if (status)
6745                 goto restore_config;
6746         if (mode & I40E_PHY_LED_MODE_ORIG) {
6747                 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6748                 status = i40e_write_phy_register_clause45(hw,
6749                                                  I40E_PHY_COM_REG_PAGE,
6750                                                  led_addr, phy_addr, led_ctl);
6751         }
6752         return status;
6753 restore_config:
6754         status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6755                                                   led_addr, phy_addr, led_ctl);
6756         return status;
6757 }
6758 #endif /* PF_DRIVER */
6759
6760 /**
6761  * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6762  * @hw: pointer to the hw struct
6763  * @reg_addr: register address
6764  * @reg_val: ptr to register value
6765  * @cmd_details: pointer to command details structure or NULL
6766  *
6767  * Use the firmware to read the Rx control register,
6768  * especially useful if the Rx unit is under heavy pressure
6769  **/
6770 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6771                                 u32 reg_addr, u32 *reg_val,
6772                                 struct i40e_asq_cmd_details *cmd_details)
6773 {
6774         struct i40e_aq_desc desc;
6775         struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
6776                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6777         enum i40e_status_code status;
6778
6779         if (reg_val == NULL)
6780                 return I40E_ERR_PARAM;
6781
6782         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
6783
6784         cmd_resp->address = CPU_TO_LE32(reg_addr);
6785
6786         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6787
6788         if (status == I40E_SUCCESS)
6789                 *reg_val = LE32_TO_CPU(cmd_resp->value);
6790
6791         return status;
6792 }
6793
6794 /**
6795  * i40e_read_rx_ctl - read from an Rx control register
6796  * @hw: pointer to the hw struct
6797  * @reg_addr: register address
6798  **/
6799 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
6800 {
6801         enum i40e_status_code status = I40E_SUCCESS;
6802         bool use_register;
6803         int retry = 5;
6804         u32 val = 0;
6805
6806         use_register = (((hw->aq.api_maj_ver == 1) &&
6807                         (hw->aq.api_min_ver < 5)) ||
6808                         (hw->mac.type == I40E_MAC_X722));
6809         if (!use_register) {
6810 do_retry:
6811                 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
6812                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6813                         i40e_msec_delay(1);
6814                         retry--;
6815                         goto do_retry;
6816                 }
6817         }
6818
6819         /* if the AQ access failed, try the old-fashioned way */
6820         if (status || use_register)
6821                 val = rd32(hw, reg_addr);
6822
6823         return val;
6824 }
6825
6826 /**
6827  * i40e_aq_rx_ctl_write_register
6828  * @hw: pointer to the hw struct
6829  * @reg_addr: register address
6830  * @reg_val: register value
6831  * @cmd_details: pointer to command details structure or NULL
6832  *
6833  * Use the firmware to write to an Rx control register,
6834  * especially useful if the Rx unit is under heavy pressure
6835  **/
6836 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
6837                                 u32 reg_addr, u32 reg_val,
6838                                 struct i40e_asq_cmd_details *cmd_details)
6839 {
6840         struct i40e_aq_desc desc;
6841         struct i40e_aqc_rx_ctl_reg_read_write *cmd =
6842                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6843         enum i40e_status_code status;
6844
6845         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
6846
6847         cmd->address = CPU_TO_LE32(reg_addr);
6848         cmd->value = CPU_TO_LE32(reg_val);
6849
6850         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6851
6852         return status;
6853 }
6854
6855 /**
6856  * i40e_write_rx_ctl - write to an Rx control register
6857  * @hw: pointer to the hw struct
6858  * @reg_addr: register address
6859  * @reg_val: register value
6860  **/
6861 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
6862 {
6863         enum i40e_status_code status = I40E_SUCCESS;
6864         bool use_register;
6865         int retry = 5;
6866
6867         use_register = (((hw->aq.api_maj_ver == 1) &&
6868                         (hw->aq.api_min_ver < 5)) ||
6869                         (hw->mac.type == I40E_MAC_X722));
6870         if (!use_register) {
6871 do_retry:
6872                 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
6873                                                        reg_val, NULL);
6874                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6875                         i40e_msec_delay(1);
6876                         retry--;
6877                         goto do_retry;
6878                 }
6879         }
6880
6881         /* if the AQ access failed, try the old-fashioned way */
6882         if (status || use_register)
6883                 wr32(hw, reg_addr, reg_val);
6884 }
6885
6886 /**
6887  * i40e_aq_set_phy_register
6888  * @hw: pointer to the hw struct
6889  * @phy_select: select which phy should be accessed
6890  * @dev_addr: PHY device address
6891  * @reg_addr: PHY register address
6892  * @reg_val: new register value
6893  * @cmd_details: pointer to command details structure or NULL
6894  *
6895  * Write the external PHY register.
6896  **/
6897 enum i40e_status_code i40e_aq_set_phy_register(struct i40e_hw *hw,
6898                                 u8 phy_select, u8 dev_addr,
6899                                 u32 reg_addr, u32 reg_val,
6900                                 struct i40e_asq_cmd_details *cmd_details)
6901 {
6902         struct i40e_aq_desc desc;
6903         struct i40e_aqc_phy_register_access *cmd =
6904                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
6905         enum i40e_status_code status;
6906
6907         i40e_fill_default_direct_cmd_desc(&desc,
6908                                           i40e_aqc_opc_set_phy_register);
6909
6910         cmd->phy_interface = phy_select;
6911         cmd->dev_addres = dev_addr;
6912         cmd->reg_address = reg_addr;
6913         cmd->reg_value = reg_val;
6914
6915         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6916
6917         return status;
6918 }
6919
6920 /**
6921  * i40e_aq_get_phy_register
6922  * @hw: pointer to the hw struct
6923  * @phy_select: select which phy should be accessed
6924  * @dev_addr: PHY device address
6925  * @reg_addr: PHY register address
6926  * @reg_val: read register value
6927  * @cmd_details: pointer to command details structure or NULL
6928  *
6929  * Read the external PHY register.
6930  **/
6931 enum i40e_status_code i40e_aq_get_phy_register(struct i40e_hw *hw,
6932                                 u8 phy_select, u8 dev_addr,
6933                                 u32 reg_addr, u32 *reg_val,
6934                                 struct i40e_asq_cmd_details *cmd_details)
6935 {
6936         struct i40e_aq_desc desc;
6937         struct i40e_aqc_phy_register_access *cmd =
6938                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
6939         enum i40e_status_code status;
6940
6941         i40e_fill_default_direct_cmd_desc(&desc,
6942                                           i40e_aqc_opc_get_phy_register);
6943
6944         cmd->phy_interface = phy_select;
6945         cmd->dev_addres = dev_addr;
6946         cmd->reg_address = reg_addr;
6947
6948         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6949         if (!status)
6950                 *reg_val = cmd->reg_value;
6951
6952         return status;
6953 }
6954
6955 #ifdef VF_DRIVER
6956
6957 /**
6958  * i40e_aq_send_msg_to_pf
6959  * @hw: pointer to the hardware structure
6960  * @v_opcode: opcodes for VF-PF communication
6961  * @v_retval: return error code
6962  * @msg: pointer to the msg buffer
6963  * @msglen: msg length
6964  * @cmd_details: pointer to command details
6965  *
6966  * Send message to PF driver using admin queue. By default, this message
6967  * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
6968  * completion before returning.
6969  **/
6970 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
6971                                 enum virtchnl_ops v_opcode,
6972                                 enum i40e_status_code v_retval,
6973                                 u8 *msg, u16 msglen,
6974                                 struct i40e_asq_cmd_details *cmd_details)
6975 {
6976         struct i40e_aq_desc desc;
6977         struct i40e_asq_cmd_details details;
6978         enum i40e_status_code status;
6979
6980         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
6981         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
6982         desc.cookie_high = CPU_TO_LE32(v_opcode);
6983         desc.cookie_low = CPU_TO_LE32(v_retval);
6984         if (msglen) {
6985                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
6986                                                 | I40E_AQ_FLAG_RD));
6987                 if (msglen > I40E_AQ_LARGE_BUF)
6988                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6989                 desc.datalen = CPU_TO_LE16(msglen);
6990         }
6991         if (!cmd_details) {
6992                 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
6993                 details.async = true;
6994                 cmd_details = &details;
6995         }
6996         status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
6997                                        msglen, cmd_details);
6998         return status;
6999 }
7000
7001 /**
7002  * i40e_vf_parse_hw_config
7003  * @hw: pointer to the hardware structure
7004  * @msg: pointer to the virtual channel VF resource structure
7005  *
7006  * Given a VF resource message from the PF, populate the hw struct
7007  * with appropriate information.
7008  **/
7009 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
7010                              struct virtchnl_vf_resource *msg)
7011 {
7012         struct virtchnl_vsi_resource *vsi_res;
7013         int i;
7014
7015         vsi_res = &msg->vsi_res[0];
7016
7017         hw->dev_caps.num_vsis = msg->num_vsis;
7018         hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
7019         hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
7020         hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
7021         hw->dev_caps.dcb = msg->vf_offload_flags &
7022                            VIRTCHNL_VF_OFFLOAD_L2;
7023         hw->dev_caps.iwarp = (msg->vf_offload_flags &
7024                               VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
7025         for (i = 0; i < msg->num_vsis; i++) {
7026                 if (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) {
7027                         i40e_memcpy(hw->mac.perm_addr,
7028                                     vsi_res->default_mac_addr,
7029                                     ETH_ALEN,
7030                                     I40E_NONDMA_TO_NONDMA);
7031                         i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
7032                                     ETH_ALEN,
7033                                     I40E_NONDMA_TO_NONDMA);
7034                 }
7035                 vsi_res++;
7036         }
7037 }
7038
7039 /**
7040  * i40e_vf_reset
7041  * @hw: pointer to the hardware structure
7042  *
7043  * Send a VF_RESET message to the PF. Does not wait for response from PF
7044  * as none will be forthcoming. Immediately after calling this function,
7045  * the admin queue should be shut down and (optionally) reinitialized.
7046  **/
7047 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
7048 {
7049         return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF,
7050                                       I40E_SUCCESS, NULL, 0, NULL);
7051 }
7052 #endif /* VF_DRIVER */
7053
7054 /**
7055  * i40e_aq_set_arp_proxy_config
7056  * @hw: pointer to the HW structure
7057  * @proxy_config - pointer to proxy config command table struct
7058  * @cmd_details: pointer to command details
7059  *
7060  * Set ARP offload parameters from pre-populated
7061  * i40e_aqc_arp_proxy_data struct
7062  **/
7063 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
7064                                 struct i40e_aqc_arp_proxy_data *proxy_config,
7065                                 struct i40e_asq_cmd_details *cmd_details)
7066 {
7067         struct i40e_aq_desc desc;
7068         enum i40e_status_code status;
7069
7070         if (!proxy_config)
7071                 return I40E_ERR_PARAM;
7072
7073         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
7074
7075         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7076         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7077         desc.params.external.addr_high =
7078                                   CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
7079         desc.params.external.addr_low =
7080                                   CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
7081         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_arp_proxy_data));
7082
7083         status = i40e_asq_send_command(hw, &desc, proxy_config,
7084                                        sizeof(struct i40e_aqc_arp_proxy_data),
7085                                        cmd_details);
7086
7087         return status;
7088 }
7089
7090 /**
7091  * i40e_aq_opc_set_ns_proxy_table_entry
7092  * @hw: pointer to the HW structure
7093  * @ns_proxy_table_entry: pointer to NS table entry command struct
7094  * @cmd_details: pointer to command details
7095  *
7096  * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
7097  * from pre-populated i40e_aqc_ns_proxy_data struct
7098  **/
7099 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
7100                         struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
7101                         struct i40e_asq_cmd_details *cmd_details)
7102 {
7103         struct i40e_aq_desc desc;
7104         enum i40e_status_code status;
7105
7106         if (!ns_proxy_table_entry)
7107                 return I40E_ERR_PARAM;
7108
7109         i40e_fill_default_direct_cmd_desc(&desc,
7110                                 i40e_aqc_opc_set_ns_proxy_table_entry);
7111
7112         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7113         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7114         desc.params.external.addr_high =
7115                 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
7116         desc.params.external.addr_low =
7117                 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
7118         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_ns_proxy_data));
7119
7120         status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
7121                                        sizeof(struct i40e_aqc_ns_proxy_data),
7122                                        cmd_details);
7123
7124         return status;
7125 }
7126
7127 /**
7128  * i40e_aq_set_clear_wol_filter
7129  * @hw: pointer to the hw struct
7130  * @filter_index: index of filter to modify (0-7)
7131  * @filter: buffer containing filter to be set
7132  * @set_filter: true to set filter, false to clear filter
7133  * @no_wol_tco: if true, pass through packets cannot cause wake-up
7134  *              if false, pass through packets may cause wake-up
7135  * @filter_valid: true if filter action is valid
7136  * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
7137  * @cmd_details: pointer to command details structure or NULL
7138  *
7139  * Set or clear WoL filter for port attached to the PF
7140  **/
7141 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
7142                                 u8 filter_index,
7143                                 struct i40e_aqc_set_wol_filter_data *filter,
7144                                 bool set_filter, bool no_wol_tco,
7145                                 bool filter_valid, bool no_wol_tco_valid,
7146                                 struct i40e_asq_cmd_details *cmd_details)
7147 {
7148         struct i40e_aq_desc desc;
7149         struct i40e_aqc_set_wol_filter *cmd =
7150                 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
7151         enum i40e_status_code status;
7152         u16 cmd_flags = 0;
7153         u16 valid_flags = 0;
7154         u16 buff_len = 0;
7155
7156         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
7157
7158         if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
7159                 return  I40E_ERR_PARAM;
7160         cmd->filter_index = CPU_TO_LE16(filter_index);
7161
7162         if (set_filter) {
7163                 if (!filter)
7164                         return  I40E_ERR_PARAM;
7165
7166                 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
7167                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR;
7168         }
7169
7170         if (no_wol_tco)
7171                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
7172         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
7173
7174         if (filter_valid)
7175                 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
7176         if (no_wol_tco_valid)
7177                 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
7178         cmd->valid_flags = CPU_TO_LE16(valid_flags);
7179
7180         buff_len = sizeof(*filter);
7181         desc.datalen = CPU_TO_LE16(buff_len);
7182
7183         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7184         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7185
7186         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
7187         cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
7188
7189         status = i40e_asq_send_command(hw, &desc, filter,
7190                                        buff_len, cmd_details);
7191
7192         return status;
7193 }
7194
7195 /**
7196  * i40e_aq_get_wake_event_reason
7197  * @hw: pointer to the hw struct
7198  * @wake_reason: return value, index of matching filter
7199  * @cmd_details: pointer to command details structure or NULL
7200  *
7201  * Get information for the reason of a Wake Up event
7202  **/
7203 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
7204                                 u16 *wake_reason,
7205                                 struct i40e_asq_cmd_details *cmd_details)
7206 {
7207         struct i40e_aq_desc desc;
7208         struct i40e_aqc_get_wake_reason_completion *resp =
7209                 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
7210         enum i40e_status_code status;
7211
7212         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
7213
7214         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7215
7216         if (status == I40E_SUCCESS)
7217                 *wake_reason = LE16_TO_CPU(resp->wake_reason);
7218
7219         return status;
7220 }
7221
7222 /**
7223 * i40e_aq_clear_all_wol_filters
7224 * @hw: pointer to the hw struct
7225 * @cmd_details: pointer to command details structure or NULL
7226 *
7227 * Get information for the reason of a Wake Up event
7228 **/
7229 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw,
7230         struct i40e_asq_cmd_details *cmd_details)
7231 {
7232         struct i40e_aq_desc desc;
7233         enum i40e_status_code status;
7234
7235         i40e_fill_default_direct_cmd_desc(&desc,
7236                                           i40e_aqc_opc_clear_all_wol_filters);
7237
7238         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7239
7240         return status;
7241 }
7242
7243
7244 /**
7245  * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
7246  * @hw: pointer to the hw struct
7247  * @buff: command buffer (size in bytes = buff_size)
7248  * @buff_size: buffer size in bytes
7249  * @track_id: package tracking id
7250  * @error_offset: returns error offset
7251  * @error_info: returns error information
7252  * @cmd_details: pointer to command details structure or NULL
7253  **/
7254 enum
7255 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
7256                                    u16 buff_size, u32 track_id,
7257                                    u32 *error_offset, u32 *error_info,
7258                                    struct i40e_asq_cmd_details *cmd_details)
7259 {
7260         struct i40e_aq_desc desc;
7261         struct i40e_aqc_write_personalization_profile *cmd =
7262                 (struct i40e_aqc_write_personalization_profile *)
7263                 &desc.params.raw;
7264         struct i40e_aqc_write_ddp_resp *resp;
7265         enum i40e_status_code status;
7266
7267         i40e_fill_default_direct_cmd_desc(&desc,
7268                                   i40e_aqc_opc_write_personalization_profile);
7269
7270         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
7271         if (buff_size > I40E_AQ_LARGE_BUF)
7272                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7273
7274         desc.datalen = CPU_TO_LE16(buff_size);
7275
7276         cmd->profile_track_id = CPU_TO_LE32(track_id);
7277
7278         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7279         if (!status) {
7280                 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
7281                 if (error_offset)
7282                         *error_offset = LE32_TO_CPU(resp->error_offset);
7283                 if (error_info)
7284                         *error_info = LE32_TO_CPU(resp->error_info);
7285         }
7286
7287         return status;
7288 }
7289
7290 /**
7291  * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
7292  * @hw: pointer to the hw struct
7293  * @buff: command buffer (size in bytes = buff_size)
7294  * @buff_size: buffer size in bytes
7295  * @cmd_details: pointer to command details structure or NULL
7296  **/
7297 enum
7298 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
7299                                       u16 buff_size, u8 flags,
7300                                       struct i40e_asq_cmd_details *cmd_details)
7301 {
7302         struct i40e_aq_desc desc;
7303         struct i40e_aqc_get_applied_profiles *cmd =
7304                 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
7305         enum i40e_status_code status;
7306
7307         i40e_fill_default_direct_cmd_desc(&desc,
7308                           i40e_aqc_opc_get_personalization_profile_list);
7309
7310         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7311         if (buff_size > I40E_AQ_LARGE_BUF)
7312                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7313         desc.datalen = CPU_TO_LE16(buff_size);
7314
7315         cmd->flags = flags;
7316
7317         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7318
7319         return status;
7320 }
7321
7322 /**
7323  * i40e_find_segment_in_package
7324  * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
7325  * @pkg_hdr: pointer to the package header to be searched
7326  *
7327  * This function searches a package file for a particular segment type. On
7328  * success it returns a pointer to the segment header, otherwise it will
7329  * return NULL.
7330  **/
7331 struct i40e_generic_seg_header *
7332 i40e_find_segment_in_package(u32 segment_type,
7333                              struct i40e_package_header *pkg_hdr)
7334 {
7335         struct i40e_generic_seg_header *segment;
7336         u32 i;
7337
7338         /* Search all package segments for the requested segment type */
7339         for (i = 0; i < pkg_hdr->segment_count; i++) {
7340                 segment =
7341                         (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
7342                          pkg_hdr->segment_offset[i]);
7343
7344                 if (segment->type == segment_type)
7345                         return segment;
7346         }
7347
7348         return NULL;
7349 }
7350
7351 /**
7352  * i40e_write_profile
7353  * @hw: pointer to the hardware structure
7354  * @profile: pointer to the profile segment of the package to be downloaded
7355  * @track_id: package tracking id
7356  *
7357  * Handles the download of a complete package.
7358  */
7359 enum i40e_status_code
7360 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7361                    u32 track_id)
7362 {
7363         enum i40e_status_code status = I40E_SUCCESS;
7364         struct i40e_section_table *sec_tbl;
7365         struct i40e_profile_section_header *sec = NULL;
7366         u32 dev_cnt;
7367         u32 vendor_dev_id;
7368         u32 *nvm;
7369         u32 section_size = 0;
7370         u32 offset = 0, info = 0;
7371         u32 i;
7372
7373         dev_cnt = profile->device_table_count;
7374
7375         for (i = 0; i < dev_cnt; i++) {
7376                 vendor_dev_id = profile->device_table[i].vendor_dev_id;
7377                 if ((vendor_dev_id >> 16) == I40E_INTEL_VENDOR_ID)
7378                         if (hw->device_id == (vendor_dev_id & 0xFFFF))
7379                                 break;
7380         }
7381         if (i == dev_cnt) {
7382                 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Device doesn't support DDP");
7383                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
7384         }
7385
7386         nvm = (u32 *)&profile->device_table[dev_cnt];
7387         sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1];
7388
7389         for (i = 0; i < sec_tbl->section_count; i++) {
7390                 sec = (struct i40e_profile_section_header *)((u8 *)profile +
7391                                              sec_tbl->section_offset[i]);
7392
7393                 /* Skip 'AQ', 'note' and 'name' sections */
7394                 if (sec->section.type != SECTION_TYPE_MMIO)
7395                         continue;
7396
7397                 section_size = sec->section.size +
7398                         sizeof(struct i40e_profile_section_header);
7399
7400                 /* Write profile */
7401                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
7402                                            track_id, &offset, &info, NULL);
7403                 if (status) {
7404                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
7405                                    "Failed to write profile: offset %d, info %d",
7406                                    offset, info);
7407                         break;
7408                 }
7409         }
7410         return status;
7411 }
7412
7413 /**
7414  * i40e_add_pinfo_to_list
7415  * @hw: pointer to the hardware structure
7416  * @profile: pointer to the profile segment of the package
7417  * @profile_info_sec: buffer for information section
7418  * @track_id: package tracking id
7419  *
7420  * Register a profile to the list of loaded profiles.
7421  */
7422 enum i40e_status_code
7423 i40e_add_pinfo_to_list(struct i40e_hw *hw,
7424                        struct i40e_profile_segment *profile,
7425                        u8 *profile_info_sec, u32 track_id)
7426 {
7427         enum i40e_status_code status = I40E_SUCCESS;
7428         struct i40e_profile_section_header *sec = NULL;
7429         struct i40e_profile_info *pinfo;
7430         u32 offset = 0, info = 0;
7431
7432         sec = (struct i40e_profile_section_header *)profile_info_sec;
7433         sec->tbl_size = 1;
7434         sec->data_end = sizeof(struct i40e_profile_section_header) +
7435                         sizeof(struct i40e_profile_info);
7436         sec->section.type = SECTION_TYPE_INFO;
7437         sec->section.offset = sizeof(struct i40e_profile_section_header);
7438         sec->section.size = sizeof(struct i40e_profile_info);
7439         pinfo = (struct i40e_profile_info *)(profile_info_sec +
7440                                              sec->section.offset);
7441         pinfo->track_id = track_id;
7442         pinfo->version = profile->version;
7443         pinfo->op = I40E_DDP_ADD_TRACKID;
7444         memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE);
7445
7446         status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
7447                                    track_id, &offset, &info, NULL);
7448         return status;
7449 }