1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "i40e_type.h"
35 #include "i40e_adminq.h"
36 #include "i40e_prototype.h"
37 #include "i40e_virtchnl.h"
41 * i40e_set_mac_type - Sets MAC type
42 * @hw: pointer to the HW structure
44 * This function sets the mac type of the adapter based on the
45 * vendor ID and device ID stored in the hw structure.
47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
53 enum i40e_status_code status = I40E_SUCCESS;
55 DEBUGFUNC("i40e_set_mac_type\n");
57 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
58 switch (hw->device_id) {
59 case I40E_DEV_ID_SFP_XL710:
60 case I40E_DEV_ID_QEMU:
61 case I40E_DEV_ID_KX_B:
62 case I40E_DEV_ID_KX_C:
63 case I40E_DEV_ID_QSFP_A:
64 case I40E_DEV_ID_QSFP_B:
65 case I40E_DEV_ID_QSFP_C:
66 case I40E_DEV_ID_10G_BASE_T:
67 case I40E_DEV_ID_10G_BASE_T4:
68 case I40E_DEV_ID_20G_KR2:
69 case I40E_DEV_ID_20G_KR2_A:
70 case I40E_DEV_ID_25G_B:
71 case I40E_DEV_ID_25G_SFP28:
72 hw->mac.type = I40E_MAC_XL710;
75 #ifdef X722_A0_SUPPORT
76 case I40E_DEV_ID_X722_A0:
78 case I40E_DEV_ID_KX_X722:
79 case I40E_DEV_ID_QSFP_X722:
80 case I40E_DEV_ID_SFP_X722:
81 case I40E_DEV_ID_1G_BASE_T_X722:
82 case I40E_DEV_ID_10G_BASE_T_X722:
83 case I40E_DEV_ID_SFP_I_X722:
84 hw->mac.type = I40E_MAC_X722;
88 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
89 case I40E_DEV_ID_X722_VF:
90 #ifdef X722_A0_SUPPORT
91 case I40E_DEV_ID_X722_A0_VF:
93 hw->mac.type = I40E_MAC_X722_VF;
95 #endif /* INTEGRATED_VF || VF_DRIVER */
96 #endif /* X722_SUPPORT */
97 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
99 case I40E_DEV_ID_VF_HV:
100 hw->mac.type = I40E_MAC_VF;
104 hw->mac.type = I40E_MAC_GENERIC;
108 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
111 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
112 hw->mac.type, status);
116 #ifndef I40E_NDIS_SUPPORT
118 * i40e_aq_str - convert AQ err code to a string
119 * @hw: pointer to the HW structure
120 * @aq_err: the AQ error code to convert
122 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
127 case I40E_AQ_RC_EPERM:
128 return "I40E_AQ_RC_EPERM";
129 case I40E_AQ_RC_ENOENT:
130 return "I40E_AQ_RC_ENOENT";
131 case I40E_AQ_RC_ESRCH:
132 return "I40E_AQ_RC_ESRCH";
133 case I40E_AQ_RC_EINTR:
134 return "I40E_AQ_RC_EINTR";
136 return "I40E_AQ_RC_EIO";
137 case I40E_AQ_RC_ENXIO:
138 return "I40E_AQ_RC_ENXIO";
139 case I40E_AQ_RC_E2BIG:
140 return "I40E_AQ_RC_E2BIG";
141 case I40E_AQ_RC_EAGAIN:
142 return "I40E_AQ_RC_EAGAIN";
143 case I40E_AQ_RC_ENOMEM:
144 return "I40E_AQ_RC_ENOMEM";
145 case I40E_AQ_RC_EACCES:
146 return "I40E_AQ_RC_EACCES";
147 case I40E_AQ_RC_EFAULT:
148 return "I40E_AQ_RC_EFAULT";
149 case I40E_AQ_RC_EBUSY:
150 return "I40E_AQ_RC_EBUSY";
151 case I40E_AQ_RC_EEXIST:
152 return "I40E_AQ_RC_EEXIST";
153 case I40E_AQ_RC_EINVAL:
154 return "I40E_AQ_RC_EINVAL";
155 case I40E_AQ_RC_ENOTTY:
156 return "I40E_AQ_RC_ENOTTY";
157 case I40E_AQ_RC_ENOSPC:
158 return "I40E_AQ_RC_ENOSPC";
159 case I40E_AQ_RC_ENOSYS:
160 return "I40E_AQ_RC_ENOSYS";
161 case I40E_AQ_RC_ERANGE:
162 return "I40E_AQ_RC_ERANGE";
163 case I40E_AQ_RC_EFLUSHED:
164 return "I40E_AQ_RC_EFLUSHED";
165 case I40E_AQ_RC_BAD_ADDR:
166 return "I40E_AQ_RC_BAD_ADDR";
167 case I40E_AQ_RC_EMODE:
168 return "I40E_AQ_RC_EMODE";
169 case I40E_AQ_RC_EFBIG:
170 return "I40E_AQ_RC_EFBIG";
173 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
178 * i40e_stat_str - convert status err code to a string
179 * @hw: pointer to the HW structure
180 * @stat_err: the status error code to convert
182 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
188 return "I40E_ERR_NVM";
189 case I40E_ERR_NVM_CHECKSUM:
190 return "I40E_ERR_NVM_CHECKSUM";
192 return "I40E_ERR_PHY";
193 case I40E_ERR_CONFIG:
194 return "I40E_ERR_CONFIG";
196 return "I40E_ERR_PARAM";
197 case I40E_ERR_MAC_TYPE:
198 return "I40E_ERR_MAC_TYPE";
199 case I40E_ERR_UNKNOWN_PHY:
200 return "I40E_ERR_UNKNOWN_PHY";
201 case I40E_ERR_LINK_SETUP:
202 return "I40E_ERR_LINK_SETUP";
203 case I40E_ERR_ADAPTER_STOPPED:
204 return "I40E_ERR_ADAPTER_STOPPED";
205 case I40E_ERR_INVALID_MAC_ADDR:
206 return "I40E_ERR_INVALID_MAC_ADDR";
207 case I40E_ERR_DEVICE_NOT_SUPPORTED:
208 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
209 case I40E_ERR_MASTER_REQUESTS_PENDING:
210 return "I40E_ERR_MASTER_REQUESTS_PENDING";
211 case I40E_ERR_INVALID_LINK_SETTINGS:
212 return "I40E_ERR_INVALID_LINK_SETTINGS";
213 case I40E_ERR_AUTONEG_NOT_COMPLETE:
214 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
215 case I40E_ERR_RESET_FAILED:
216 return "I40E_ERR_RESET_FAILED";
217 case I40E_ERR_SWFW_SYNC:
218 return "I40E_ERR_SWFW_SYNC";
219 case I40E_ERR_NO_AVAILABLE_VSI:
220 return "I40E_ERR_NO_AVAILABLE_VSI";
221 case I40E_ERR_NO_MEMORY:
222 return "I40E_ERR_NO_MEMORY";
223 case I40E_ERR_BAD_PTR:
224 return "I40E_ERR_BAD_PTR";
225 case I40E_ERR_RING_FULL:
226 return "I40E_ERR_RING_FULL";
227 case I40E_ERR_INVALID_PD_ID:
228 return "I40E_ERR_INVALID_PD_ID";
229 case I40E_ERR_INVALID_QP_ID:
230 return "I40E_ERR_INVALID_QP_ID";
231 case I40E_ERR_INVALID_CQ_ID:
232 return "I40E_ERR_INVALID_CQ_ID";
233 case I40E_ERR_INVALID_CEQ_ID:
234 return "I40E_ERR_INVALID_CEQ_ID";
235 case I40E_ERR_INVALID_AEQ_ID:
236 return "I40E_ERR_INVALID_AEQ_ID";
237 case I40E_ERR_INVALID_SIZE:
238 return "I40E_ERR_INVALID_SIZE";
239 case I40E_ERR_INVALID_ARP_INDEX:
240 return "I40E_ERR_INVALID_ARP_INDEX";
241 case I40E_ERR_INVALID_FPM_FUNC_ID:
242 return "I40E_ERR_INVALID_FPM_FUNC_ID";
243 case I40E_ERR_QP_INVALID_MSG_SIZE:
244 return "I40E_ERR_QP_INVALID_MSG_SIZE";
245 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
246 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
247 case I40E_ERR_INVALID_FRAG_COUNT:
248 return "I40E_ERR_INVALID_FRAG_COUNT";
249 case I40E_ERR_QUEUE_EMPTY:
250 return "I40E_ERR_QUEUE_EMPTY";
251 case I40E_ERR_INVALID_ALIGNMENT:
252 return "I40E_ERR_INVALID_ALIGNMENT";
253 case I40E_ERR_FLUSHED_QUEUE:
254 return "I40E_ERR_FLUSHED_QUEUE";
255 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
256 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
257 case I40E_ERR_INVALID_IMM_DATA_SIZE:
258 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
259 case I40E_ERR_TIMEOUT:
260 return "I40E_ERR_TIMEOUT";
261 case I40E_ERR_OPCODE_MISMATCH:
262 return "I40E_ERR_OPCODE_MISMATCH";
263 case I40E_ERR_CQP_COMPL_ERROR:
264 return "I40E_ERR_CQP_COMPL_ERROR";
265 case I40E_ERR_INVALID_VF_ID:
266 return "I40E_ERR_INVALID_VF_ID";
267 case I40E_ERR_INVALID_HMCFN_ID:
268 return "I40E_ERR_INVALID_HMCFN_ID";
269 case I40E_ERR_BACKING_PAGE_ERROR:
270 return "I40E_ERR_BACKING_PAGE_ERROR";
271 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
272 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
273 case I40E_ERR_INVALID_PBLE_INDEX:
274 return "I40E_ERR_INVALID_PBLE_INDEX";
275 case I40E_ERR_INVALID_SD_INDEX:
276 return "I40E_ERR_INVALID_SD_INDEX";
277 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
278 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
279 case I40E_ERR_INVALID_SD_TYPE:
280 return "I40E_ERR_INVALID_SD_TYPE";
281 case I40E_ERR_MEMCPY_FAILED:
282 return "I40E_ERR_MEMCPY_FAILED";
283 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
284 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
285 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
286 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
287 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
288 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
289 case I40E_ERR_SRQ_ENABLED:
290 return "I40E_ERR_SRQ_ENABLED";
291 case I40E_ERR_ADMIN_QUEUE_ERROR:
292 return "I40E_ERR_ADMIN_QUEUE_ERROR";
293 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
294 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
295 case I40E_ERR_BUF_TOO_SHORT:
296 return "I40E_ERR_BUF_TOO_SHORT";
297 case I40E_ERR_ADMIN_QUEUE_FULL:
298 return "I40E_ERR_ADMIN_QUEUE_FULL";
299 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
300 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
301 case I40E_ERR_BAD_IWARP_CQE:
302 return "I40E_ERR_BAD_IWARP_CQE";
303 case I40E_ERR_NVM_BLANK_MODE:
304 return "I40E_ERR_NVM_BLANK_MODE";
305 case I40E_ERR_NOT_IMPLEMENTED:
306 return "I40E_ERR_NOT_IMPLEMENTED";
307 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
308 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
309 case I40E_ERR_DIAG_TEST_FAILED:
310 return "I40E_ERR_DIAG_TEST_FAILED";
311 case I40E_ERR_NOT_READY:
312 return "I40E_ERR_NOT_READY";
313 case I40E_NOT_SUPPORTED:
314 return "I40E_NOT_SUPPORTED";
315 case I40E_ERR_FIRMWARE_API_VERSION:
316 return "I40E_ERR_FIRMWARE_API_VERSION";
319 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
323 #endif /* I40E_NDIS_SUPPORT */
326 * @hw: debug mask related to admin queue
328 * @desc: pointer to admin queue descriptor
329 * @buffer: pointer to command buffer
330 * @buf_len: max length of buffer
332 * Dumps debug log about adminq command with descriptor contents.
334 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
335 void *buffer, u16 buf_len)
337 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
338 u16 len = LE16_TO_CPU(aq_desc->datalen);
339 u8 *buf = (u8 *)buffer;
342 if ((!(mask & hw->debug_mask)) || (desc == NULL))
346 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
347 LE16_TO_CPU(aq_desc->opcode),
348 LE16_TO_CPU(aq_desc->flags),
349 LE16_TO_CPU(aq_desc->datalen),
350 LE16_TO_CPU(aq_desc->retval));
351 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
352 LE32_TO_CPU(aq_desc->cookie_high),
353 LE32_TO_CPU(aq_desc->cookie_low));
354 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
355 LE32_TO_CPU(aq_desc->params.internal.param0),
356 LE32_TO_CPU(aq_desc->params.internal.param1));
357 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
358 LE32_TO_CPU(aq_desc->params.external.addr_high),
359 LE32_TO_CPU(aq_desc->params.external.addr_low));
361 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
362 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
365 /* write the full 16-byte chunks */
366 for (i = 0; i < (len - 16); i += 16)
368 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
369 i, buf[i], buf[i+1], buf[i+2], buf[i+3],
370 buf[i+4], buf[i+5], buf[i+6], buf[i+7],
371 buf[i+8], buf[i+9], buf[i+10], buf[i+11],
372 buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
373 /* the most we could have left is 16 bytes, pad with zeros */
379 memset(d_buf, 0, sizeof(d_buf));
380 for (j = 0; i < len; j++, i++)
383 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
384 i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
385 d_buf[4], d_buf[5], d_buf[6], d_buf[7],
386 d_buf[8], d_buf[9], d_buf[10], d_buf[11],
387 d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
393 * i40e_check_asq_alive
394 * @hw: pointer to the hw struct
396 * Returns true if Queue is enabled else false.
398 bool i40e_check_asq_alive(struct i40e_hw *hw)
404 return !!(rd32(hw, hw->aq.asq.len) &
405 I40E_PF_ATQLEN_ATQENABLE_MASK);
407 return !!(rd32(hw, hw->aq.asq.len) &
408 I40E_PF_ATQLEN_ATQENABLE_MASK);
409 #endif /* INTEGRATED_VF */
410 #endif /* PF_DRIVER */
414 return !!(rd32(hw, hw->aq.asq.len) &
415 I40E_VF_ATQLEN1_ATQENABLE_MASK);
417 return !!(rd32(hw, hw->aq.asq.len) &
418 I40E_VF_ATQLEN1_ATQENABLE_MASK);
419 #endif /* INTEGRATED_VF */
420 #endif /* VF_DRIVER */
425 * i40e_aq_queue_shutdown
426 * @hw: pointer to the hw struct
427 * @unloading: is the driver unloading itself
429 * Tell the Firmware that we're shutting down the AdminQ and whether
430 * or not the driver is unloading as well.
432 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
435 struct i40e_aq_desc desc;
436 struct i40e_aqc_queue_shutdown *cmd =
437 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
438 enum i40e_status_code status;
440 i40e_fill_default_direct_cmd_desc(&desc,
441 i40e_aqc_opc_queue_shutdown);
444 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
445 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
452 * i40e_aq_get_set_rss_lut
453 * @hw: pointer to the hardware structure
454 * @vsi_id: vsi fw index
455 * @pf_lut: for PF table set true, for VSI table set false
456 * @lut: pointer to the lut buffer provided by the caller
457 * @lut_size: size of the lut buffer
458 * @set: set true to set the table, false to get the table
460 * Internal function to get or set RSS look up table
462 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
463 u16 vsi_id, bool pf_lut,
464 u8 *lut, u16 lut_size,
467 enum i40e_status_code status;
468 struct i40e_aq_desc desc;
469 struct i40e_aqc_get_set_rss_lut *cmd_resp =
470 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
473 i40e_fill_default_direct_cmd_desc(&desc,
474 i40e_aqc_opc_set_rss_lut);
476 i40e_fill_default_direct_cmd_desc(&desc,
477 i40e_aqc_opc_get_rss_lut);
479 /* Indirect command */
480 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
481 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
484 CPU_TO_LE16((u16)((vsi_id <<
485 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
486 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
487 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
490 cmd_resp->flags |= CPU_TO_LE16((u16)
491 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
492 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
493 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
495 cmd_resp->flags |= CPU_TO_LE16((u16)
496 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
497 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
498 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
500 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
506 * i40e_aq_get_rss_lut
507 * @hw: pointer to the hardware structure
508 * @vsi_id: vsi fw index
509 * @pf_lut: for PF table set true, for VSI table set false
510 * @lut: pointer to the lut buffer provided by the caller
511 * @lut_size: size of the lut buffer
513 * get the RSS lookup table, PF or VSI type
515 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
516 bool pf_lut, u8 *lut, u16 lut_size)
518 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
523 * i40e_aq_set_rss_lut
524 * @hw: pointer to the hardware structure
525 * @vsi_id: vsi fw index
526 * @pf_lut: for PF table set true, for VSI table set false
527 * @lut: pointer to the lut buffer provided by the caller
528 * @lut_size: size of the lut buffer
530 * set the RSS lookup table, PF or VSI type
532 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
533 bool pf_lut, u8 *lut, u16 lut_size)
535 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
539 * i40e_aq_get_set_rss_key
540 * @hw: pointer to the hw struct
541 * @vsi_id: vsi fw index
542 * @key: pointer to key info struct
543 * @set: set true to set the key, false to get the key
545 * get the RSS key per VSI
547 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
549 struct i40e_aqc_get_set_rss_key_data *key,
552 enum i40e_status_code status;
553 struct i40e_aq_desc desc;
554 struct i40e_aqc_get_set_rss_key *cmd_resp =
555 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
556 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
559 i40e_fill_default_direct_cmd_desc(&desc,
560 i40e_aqc_opc_set_rss_key);
562 i40e_fill_default_direct_cmd_desc(&desc,
563 i40e_aqc_opc_get_rss_key);
565 /* Indirect command */
566 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
567 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
570 CPU_TO_LE16((u16)((vsi_id <<
571 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
572 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
573 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
575 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
581 * i40e_aq_get_rss_key
582 * @hw: pointer to the hw struct
583 * @vsi_id: vsi fw index
584 * @key: pointer to key info struct
587 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
589 struct i40e_aqc_get_set_rss_key_data *key)
591 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
595 * i40e_aq_set_rss_key
596 * @hw: pointer to the hw struct
597 * @vsi_id: vsi fw index
598 * @key: pointer to key info struct
600 * set the RSS key per VSI
602 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
604 struct i40e_aqc_get_set_rss_key_data *key)
606 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
608 #endif /* X722_SUPPORT */
610 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
611 * hardware to a bit-field that can be used by SW to more easily determine the
614 * Macros are used to shorten the table lines and make this table human
617 * We store the PTYPE in the top byte of the bit field - this is just so that
618 * we can check that the table doesn't have a row missing, as the index into
619 * the table should be the PTYPE.
623 * IF NOT i40e_ptype_lookup[ptype].known
626 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
627 * Use the rest of the fields to look at the tunnels, inner protocols, etc
629 * Use the enum i40e_rx_l2_ptype to decode the packet type
633 /* macro to make the table lines short */
634 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
637 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
638 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
639 I40E_RX_PTYPE_##OUTER_FRAG, \
640 I40E_RX_PTYPE_TUNNEL_##T, \
641 I40E_RX_PTYPE_TUNNEL_END_##TE, \
642 I40E_RX_PTYPE_##TEF, \
643 I40E_RX_PTYPE_INNER_PROT_##I, \
644 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
646 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
647 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
649 /* shorter macros makes the table fit but are terse */
650 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
651 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
652 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
654 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
655 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
656 /* L2 Packet types */
657 I40E_PTT_UNUSED_ENTRY(0),
658 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
659 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
660 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
661 I40E_PTT_UNUSED_ENTRY(4),
662 I40E_PTT_UNUSED_ENTRY(5),
663 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
664 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
665 I40E_PTT_UNUSED_ENTRY(8),
666 I40E_PTT_UNUSED_ENTRY(9),
667 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
668 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
669 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
670 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
671 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
672 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
673 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
674 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
675 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
676 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
677 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
678 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
680 /* Non Tunneled IPv4 */
681 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
682 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
683 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
684 I40E_PTT_UNUSED_ENTRY(25),
685 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
686 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
687 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
690 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
691 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
692 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
693 I40E_PTT_UNUSED_ENTRY(32),
694 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
695 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
696 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
699 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
700 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
701 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
702 I40E_PTT_UNUSED_ENTRY(39),
703 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
704 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
705 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
707 /* IPv4 --> GRE/NAT */
708 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
710 /* IPv4 --> GRE/NAT --> IPv4 */
711 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
712 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
713 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
714 I40E_PTT_UNUSED_ENTRY(47),
715 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
716 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
717 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
719 /* IPv4 --> GRE/NAT --> IPv6 */
720 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
721 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
722 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
723 I40E_PTT_UNUSED_ENTRY(54),
724 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
725 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
726 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
728 /* IPv4 --> GRE/NAT --> MAC */
729 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
731 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
732 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
733 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
734 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
735 I40E_PTT_UNUSED_ENTRY(62),
736 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
737 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
738 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
740 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
741 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
742 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
743 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
744 I40E_PTT_UNUSED_ENTRY(69),
745 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
746 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
747 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
749 /* IPv4 --> GRE/NAT --> MAC/VLAN */
750 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
752 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
753 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
754 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
755 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
756 I40E_PTT_UNUSED_ENTRY(77),
757 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
758 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
759 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
761 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
762 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
763 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
764 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
765 I40E_PTT_UNUSED_ENTRY(84),
766 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
767 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
768 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
770 /* Non Tunneled IPv6 */
771 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
772 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
773 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4),
774 I40E_PTT_UNUSED_ENTRY(91),
775 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
776 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
777 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
780 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
781 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
782 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
783 I40E_PTT_UNUSED_ENTRY(98),
784 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
785 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
786 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
789 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
790 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
791 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
792 I40E_PTT_UNUSED_ENTRY(105),
793 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
794 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
795 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
797 /* IPv6 --> GRE/NAT */
798 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
800 /* IPv6 --> GRE/NAT -> IPv4 */
801 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
802 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
803 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
804 I40E_PTT_UNUSED_ENTRY(113),
805 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
806 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
807 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
809 /* IPv6 --> GRE/NAT -> IPv6 */
810 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
811 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
812 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
813 I40E_PTT_UNUSED_ENTRY(120),
814 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
815 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
816 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
818 /* IPv6 --> GRE/NAT -> MAC */
819 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
821 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
822 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
823 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
824 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
825 I40E_PTT_UNUSED_ENTRY(128),
826 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
827 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
828 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
830 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
831 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
832 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
833 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
834 I40E_PTT_UNUSED_ENTRY(135),
835 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
836 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
837 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
839 /* IPv6 --> GRE/NAT -> MAC/VLAN */
840 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
842 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
843 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
844 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
845 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
846 I40E_PTT_UNUSED_ENTRY(143),
847 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
848 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
849 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
851 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
852 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
853 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
854 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
855 I40E_PTT_UNUSED_ENTRY(150),
856 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
857 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
858 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
861 I40E_PTT_UNUSED_ENTRY(154),
862 I40E_PTT_UNUSED_ENTRY(155),
863 I40E_PTT_UNUSED_ENTRY(156),
864 I40E_PTT_UNUSED_ENTRY(157),
865 I40E_PTT_UNUSED_ENTRY(158),
866 I40E_PTT_UNUSED_ENTRY(159),
868 I40E_PTT_UNUSED_ENTRY(160),
869 I40E_PTT_UNUSED_ENTRY(161),
870 I40E_PTT_UNUSED_ENTRY(162),
871 I40E_PTT_UNUSED_ENTRY(163),
872 I40E_PTT_UNUSED_ENTRY(164),
873 I40E_PTT_UNUSED_ENTRY(165),
874 I40E_PTT_UNUSED_ENTRY(166),
875 I40E_PTT_UNUSED_ENTRY(167),
876 I40E_PTT_UNUSED_ENTRY(168),
877 I40E_PTT_UNUSED_ENTRY(169),
879 I40E_PTT_UNUSED_ENTRY(170),
880 I40E_PTT_UNUSED_ENTRY(171),
881 I40E_PTT_UNUSED_ENTRY(172),
882 I40E_PTT_UNUSED_ENTRY(173),
883 I40E_PTT_UNUSED_ENTRY(174),
884 I40E_PTT_UNUSED_ENTRY(175),
885 I40E_PTT_UNUSED_ENTRY(176),
886 I40E_PTT_UNUSED_ENTRY(177),
887 I40E_PTT_UNUSED_ENTRY(178),
888 I40E_PTT_UNUSED_ENTRY(179),
890 I40E_PTT_UNUSED_ENTRY(180),
891 I40E_PTT_UNUSED_ENTRY(181),
892 I40E_PTT_UNUSED_ENTRY(182),
893 I40E_PTT_UNUSED_ENTRY(183),
894 I40E_PTT_UNUSED_ENTRY(184),
895 I40E_PTT_UNUSED_ENTRY(185),
896 I40E_PTT_UNUSED_ENTRY(186),
897 I40E_PTT_UNUSED_ENTRY(187),
898 I40E_PTT_UNUSED_ENTRY(188),
899 I40E_PTT_UNUSED_ENTRY(189),
901 I40E_PTT_UNUSED_ENTRY(190),
902 I40E_PTT_UNUSED_ENTRY(191),
903 I40E_PTT_UNUSED_ENTRY(192),
904 I40E_PTT_UNUSED_ENTRY(193),
905 I40E_PTT_UNUSED_ENTRY(194),
906 I40E_PTT_UNUSED_ENTRY(195),
907 I40E_PTT_UNUSED_ENTRY(196),
908 I40E_PTT_UNUSED_ENTRY(197),
909 I40E_PTT_UNUSED_ENTRY(198),
910 I40E_PTT_UNUSED_ENTRY(199),
912 I40E_PTT_UNUSED_ENTRY(200),
913 I40E_PTT_UNUSED_ENTRY(201),
914 I40E_PTT_UNUSED_ENTRY(202),
915 I40E_PTT_UNUSED_ENTRY(203),
916 I40E_PTT_UNUSED_ENTRY(204),
917 I40E_PTT_UNUSED_ENTRY(205),
918 I40E_PTT_UNUSED_ENTRY(206),
919 I40E_PTT_UNUSED_ENTRY(207),
920 I40E_PTT_UNUSED_ENTRY(208),
921 I40E_PTT_UNUSED_ENTRY(209),
923 I40E_PTT_UNUSED_ENTRY(210),
924 I40E_PTT_UNUSED_ENTRY(211),
925 I40E_PTT_UNUSED_ENTRY(212),
926 I40E_PTT_UNUSED_ENTRY(213),
927 I40E_PTT_UNUSED_ENTRY(214),
928 I40E_PTT_UNUSED_ENTRY(215),
929 I40E_PTT_UNUSED_ENTRY(216),
930 I40E_PTT_UNUSED_ENTRY(217),
931 I40E_PTT_UNUSED_ENTRY(218),
932 I40E_PTT_UNUSED_ENTRY(219),
934 I40E_PTT_UNUSED_ENTRY(220),
935 I40E_PTT_UNUSED_ENTRY(221),
936 I40E_PTT_UNUSED_ENTRY(222),
937 I40E_PTT_UNUSED_ENTRY(223),
938 I40E_PTT_UNUSED_ENTRY(224),
939 I40E_PTT_UNUSED_ENTRY(225),
940 I40E_PTT_UNUSED_ENTRY(226),
941 I40E_PTT_UNUSED_ENTRY(227),
942 I40E_PTT_UNUSED_ENTRY(228),
943 I40E_PTT_UNUSED_ENTRY(229),
945 I40E_PTT_UNUSED_ENTRY(230),
946 I40E_PTT_UNUSED_ENTRY(231),
947 I40E_PTT_UNUSED_ENTRY(232),
948 I40E_PTT_UNUSED_ENTRY(233),
949 I40E_PTT_UNUSED_ENTRY(234),
950 I40E_PTT_UNUSED_ENTRY(235),
951 I40E_PTT_UNUSED_ENTRY(236),
952 I40E_PTT_UNUSED_ENTRY(237),
953 I40E_PTT_UNUSED_ENTRY(238),
954 I40E_PTT_UNUSED_ENTRY(239),
956 I40E_PTT_UNUSED_ENTRY(240),
957 I40E_PTT_UNUSED_ENTRY(241),
958 I40E_PTT_UNUSED_ENTRY(242),
959 I40E_PTT_UNUSED_ENTRY(243),
960 I40E_PTT_UNUSED_ENTRY(244),
961 I40E_PTT_UNUSED_ENTRY(245),
962 I40E_PTT_UNUSED_ENTRY(246),
963 I40E_PTT_UNUSED_ENTRY(247),
964 I40E_PTT_UNUSED_ENTRY(248),
965 I40E_PTT_UNUSED_ENTRY(249),
967 I40E_PTT_UNUSED_ENTRY(250),
968 I40E_PTT_UNUSED_ENTRY(251),
969 I40E_PTT_UNUSED_ENTRY(252),
970 I40E_PTT_UNUSED_ENTRY(253),
971 I40E_PTT_UNUSED_ENTRY(254),
972 I40E_PTT_UNUSED_ENTRY(255)
977 * i40e_validate_mac_addr - Validate unicast MAC address
978 * @mac_addr: pointer to MAC address
980 * Tests a MAC address to ensure it is a valid Individual Address
982 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
984 enum i40e_status_code status = I40E_SUCCESS;
986 DEBUGFUNC("i40e_validate_mac_addr");
988 /* Broadcast addresses ARE multicast addresses
989 * Make sure it is not a multicast address
990 * Reject the zero address
992 if (I40E_IS_MULTICAST(mac_addr) ||
993 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
994 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
995 status = I40E_ERR_INVALID_MAC_ADDR;
1002 * i40e_init_shared_code - Initialize the shared code
1003 * @hw: pointer to hardware structure
1005 * This assigns the MAC type and PHY code and inits the NVM.
1006 * Does not touch the hardware. This function must be called prior to any
1007 * other function in the shared code. The i40e_hw structure should be
1008 * memset to 0 prior to calling this function. The following fields in
1009 * hw structure should be filled in prior to calling this function:
1010 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1011 * subsystem_vendor_id, and revision_id
1013 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
1015 enum i40e_status_code status = I40E_SUCCESS;
1016 u32 port, ari, func_rid;
1018 DEBUGFUNC("i40e_init_shared_code");
1020 i40e_set_mac_type(hw);
1022 switch (hw->mac.type) {
1023 case I40E_MAC_XL710:
1029 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1032 hw->phy.get_link_info = true;
1034 /* Determine port number and PF number*/
1035 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1036 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1037 hw->port = (u8)port;
1038 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1039 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1040 func_rid = rd32(hw, I40E_PF_FUNC_RID);
1042 hw->pf_id = (u8)(func_rid & 0xff);
1044 hw->pf_id = (u8)(func_rid & 0x7);
1047 if (hw->mac.type == I40E_MAC_X722)
1048 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
1051 status = i40e_init_nvm(hw);
1056 * i40e_aq_mac_address_read - Retrieve the MAC addresses
1057 * @hw: pointer to the hw struct
1058 * @flags: a return indicator of what addresses were added to the addr store
1059 * @addrs: the requestor's mac addr store
1060 * @cmd_details: pointer to command details structure or NULL
1062 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1064 struct i40e_aqc_mac_address_read_data *addrs,
1065 struct i40e_asq_cmd_details *cmd_details)
1067 struct i40e_aq_desc desc;
1068 struct i40e_aqc_mac_address_read *cmd_data =
1069 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1070 enum i40e_status_code status;
1072 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1073 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1075 status = i40e_asq_send_command(hw, &desc, addrs,
1076 sizeof(*addrs), cmd_details);
1077 *flags = LE16_TO_CPU(cmd_data->command_flags);
1083 * i40e_aq_mac_address_write - Change the MAC addresses
1084 * @hw: pointer to the hw struct
1085 * @flags: indicates which MAC to be written
1086 * @mac_addr: address to write
1087 * @cmd_details: pointer to command details structure or NULL
1089 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1090 u16 flags, u8 *mac_addr,
1091 struct i40e_asq_cmd_details *cmd_details)
1093 struct i40e_aq_desc desc;
1094 struct i40e_aqc_mac_address_write *cmd_data =
1095 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1096 enum i40e_status_code status;
1098 i40e_fill_default_direct_cmd_desc(&desc,
1099 i40e_aqc_opc_mac_address_write);
1100 cmd_data->command_flags = CPU_TO_LE16(flags);
1101 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1102 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1103 ((u32)mac_addr[3] << 16) |
1104 ((u32)mac_addr[4] << 8) |
1107 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1113 * i40e_get_mac_addr - get MAC address
1114 * @hw: pointer to the HW structure
1115 * @mac_addr: pointer to MAC address
1117 * Reads the adapter's MAC address from register
1119 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1121 struct i40e_aqc_mac_address_read_data addrs;
1122 enum i40e_status_code status;
1125 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1127 if (flags & I40E_AQC_LAN_ADDR_VALID)
1128 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1129 I40E_NONDMA_TO_NONDMA);
1135 * i40e_get_port_mac_addr - get Port MAC address
1136 * @hw: pointer to the HW structure
1137 * @mac_addr: pointer to Port MAC address
1139 * Reads the adapter's Port MAC address
1141 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1143 struct i40e_aqc_mac_address_read_data addrs;
1144 enum i40e_status_code status;
1147 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1151 if (flags & I40E_AQC_PORT_ADDR_VALID)
1152 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1153 I40E_NONDMA_TO_NONDMA);
1155 status = I40E_ERR_INVALID_MAC_ADDR;
1161 * i40e_pre_tx_queue_cfg - pre tx queue configure
1162 * @hw: pointer to the HW structure
1163 * @queue: target pf queue index
1164 * @enable: state change request
1166 * Handles hw requirement to indicate intention to enable
1167 * or disable target queue.
1169 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1171 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1175 if (abs_queue_idx >= 128) {
1176 reg_block = abs_queue_idx / 128;
1177 abs_queue_idx %= 128;
1180 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1181 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1182 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1185 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1187 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1189 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1193 * i40e_get_san_mac_addr - get SAN MAC address
1194 * @hw: pointer to the HW structure
1195 * @mac_addr: pointer to SAN MAC address
1197 * Reads the adapter's SAN MAC address from NVM
1199 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1202 struct i40e_aqc_mac_address_read_data addrs;
1203 enum i40e_status_code status;
1206 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1210 if (flags & I40E_AQC_SAN_ADDR_VALID)
1211 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac),
1212 I40E_NONDMA_TO_NONDMA);
1214 status = I40E_ERR_INVALID_MAC_ADDR;
1220 * i40e_read_pba_string - Reads part number string from EEPROM
1221 * @hw: pointer to hardware structure
1222 * @pba_num: stores the part number string from the EEPROM
1223 * @pba_num_size: part number string buffer length
1225 * Reads the part number string from the EEPROM.
1227 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1230 enum i40e_status_code status = I40E_SUCCESS;
1236 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1237 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1238 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1242 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1243 if (status != I40E_SUCCESS) {
1244 DEBUGOUT("Failed to read PBA Block pointer.\n");
1248 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1249 if (status != I40E_SUCCESS) {
1250 DEBUGOUT("Failed to read PBA Block size.\n");
1254 /* Subtract one to get PBA word count (PBA Size word is included in
1258 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1259 DEBUGOUT("Buffer to small for PBA data.\n");
1260 return I40E_ERR_PARAM;
1263 for (i = 0; i < pba_size; i++) {
1264 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1265 if (status != I40E_SUCCESS) {
1266 DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1270 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1271 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1273 pba_num[(pba_size * 2)] = '\0';
1279 * i40e_get_media_type - Gets media type
1280 * @hw: pointer to the hardware structure
1282 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1284 enum i40e_media_type media;
1286 switch (hw->phy.link_info.phy_type) {
1287 case I40E_PHY_TYPE_10GBASE_SR:
1288 case I40E_PHY_TYPE_10GBASE_LR:
1289 case I40E_PHY_TYPE_1000BASE_SX:
1290 case I40E_PHY_TYPE_1000BASE_LX:
1291 case I40E_PHY_TYPE_40GBASE_SR4:
1292 case I40E_PHY_TYPE_40GBASE_LR4:
1293 case I40E_PHY_TYPE_25GBASE_LR:
1294 case I40E_PHY_TYPE_25GBASE_SR:
1295 media = I40E_MEDIA_TYPE_FIBER;
1297 case I40E_PHY_TYPE_100BASE_TX:
1298 case I40E_PHY_TYPE_1000BASE_T:
1299 case I40E_PHY_TYPE_10GBASE_T:
1300 media = I40E_MEDIA_TYPE_BASET;
1302 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1303 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1304 case I40E_PHY_TYPE_10GBASE_CR1:
1305 case I40E_PHY_TYPE_40GBASE_CR4:
1306 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1307 case I40E_PHY_TYPE_40GBASE_AOC:
1308 case I40E_PHY_TYPE_10GBASE_AOC:
1309 case I40E_PHY_TYPE_25GBASE_CR:
1310 media = I40E_MEDIA_TYPE_DA;
1312 case I40E_PHY_TYPE_1000BASE_KX:
1313 case I40E_PHY_TYPE_10GBASE_KX4:
1314 case I40E_PHY_TYPE_10GBASE_KR:
1315 case I40E_PHY_TYPE_40GBASE_KR4:
1316 case I40E_PHY_TYPE_20GBASE_KR2:
1317 case I40E_PHY_TYPE_25GBASE_KR:
1318 media = I40E_MEDIA_TYPE_BACKPLANE;
1320 case I40E_PHY_TYPE_SGMII:
1321 case I40E_PHY_TYPE_XAUI:
1322 case I40E_PHY_TYPE_XFI:
1323 case I40E_PHY_TYPE_XLAUI:
1324 case I40E_PHY_TYPE_XLPPI:
1326 media = I40E_MEDIA_TYPE_UNKNOWN;
1333 #define I40E_PF_RESET_WAIT_COUNT 200
1335 * i40e_pf_reset - Reset the PF
1336 * @hw: pointer to the hardware structure
1338 * Assuming someone else has triggered a global reset,
1339 * assure the global reset is complete and then reset the PF
1341 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1348 /* Poll for Global Reset steady state in case of recent GRST.
1349 * The grst delay value is in 100ms units, and we'll wait a
1350 * couple counts longer to be sure we don't just miss the end.
1352 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1353 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1354 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1356 grst_del = grst_del * 20;
1358 for (cnt = 0; cnt < grst_del; cnt++) {
1359 reg = rd32(hw, I40E_GLGEN_RSTAT);
1360 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1362 i40e_msec_delay(100);
1364 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1365 DEBUGOUT("Global reset polling failed to complete.\n");
1366 return I40E_ERR_RESET_FAILED;
1369 /* Now Wait for the FW to be ready */
1370 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1371 reg = rd32(hw, I40E_GLNVM_ULD);
1372 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1373 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1374 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1375 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1376 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1379 i40e_msec_delay(10);
1381 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1382 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1383 DEBUGOUT("wait for FW Reset complete timedout\n");
1384 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1385 return I40E_ERR_RESET_FAILED;
1388 /* If there was a Global Reset in progress when we got here,
1389 * we don't need to do the PF Reset
1392 reg = rd32(hw, I40E_PFGEN_CTRL);
1393 wr32(hw, I40E_PFGEN_CTRL,
1394 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1395 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1396 reg = rd32(hw, I40E_PFGEN_CTRL);
1397 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1401 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1402 DEBUGOUT("PF reset polling failed to complete.\n");
1403 return I40E_ERR_RESET_FAILED;
1407 i40e_clear_pxe_mode(hw);
1410 return I40E_SUCCESS;
1414 * i40e_clear_hw - clear out any left over hw state
1415 * @hw: pointer to the hw struct
1417 * Clear queues and interrupts, typically called at init time,
1418 * but after the capabilities have been found so we know how many
1419 * queues and msix vectors have been allocated.
1421 void i40e_clear_hw(struct i40e_hw *hw)
1423 u32 num_queues, base_queue;
1431 /* get number of interrupts, queues, and vfs */
1432 val = rd32(hw, I40E_GLPCI_CNF2);
1433 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1434 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1435 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1436 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1438 val = rd32(hw, I40E_PFLAN_QALLOC);
1439 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1440 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1441 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1442 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1443 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1444 num_queues = (j - base_queue) + 1;
1448 val = rd32(hw, I40E_PF_VT_PFALLOC);
1449 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1450 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1451 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1452 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1453 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1454 num_vfs = (j - i) + 1;
1458 /* stop all the interrupts */
1459 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1460 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1461 for (i = 0; i < num_pf_int - 2; i++)
1462 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1464 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1465 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1466 wr32(hw, I40E_PFINT_LNKLST0, val);
1467 for (i = 0; i < num_pf_int - 2; i++)
1468 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1469 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1470 for (i = 0; i < num_vfs; i++)
1471 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1472 for (i = 0; i < num_vf_int - 2; i++)
1473 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1475 /* warn the HW of the coming Tx disables */
1476 for (i = 0; i < num_queues; i++) {
1477 u32 abs_queue_idx = base_queue + i;
1480 if (abs_queue_idx >= 128) {
1481 reg_block = abs_queue_idx / 128;
1482 abs_queue_idx %= 128;
1485 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1486 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1487 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1488 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1490 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1492 i40e_usec_delay(400);
1494 /* stop all the queues */
1495 for (i = 0; i < num_queues; i++) {
1496 wr32(hw, I40E_QINT_TQCTL(i), 0);
1497 wr32(hw, I40E_QTX_ENA(i), 0);
1498 wr32(hw, I40E_QINT_RQCTL(i), 0);
1499 wr32(hw, I40E_QRX_ENA(i), 0);
1502 /* short wait for all queue disables to settle */
1503 i40e_usec_delay(50);
1507 * i40e_clear_pxe_mode - clear pxe operations mode
1508 * @hw: pointer to the hw struct
1510 * Make sure all PXE mode settings are cleared, including things
1511 * like descriptor fetch/write-back mode.
1513 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1515 if (i40e_check_asq_alive(hw))
1516 i40e_aq_clear_pxe_mode(hw, NULL);
1520 * i40e_led_is_mine - helper to find matching led
1521 * @hw: pointer to the hw struct
1522 * @idx: index into GPIO registers
1524 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1526 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1531 if (!hw->func_caps.led[idx])
1534 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1535 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1536 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1538 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1539 * if it is not our port then ignore
1541 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1548 #define I40E_COMBINED_ACTIVITY 0xA
1549 #define I40E_FILTER_ACTIVITY 0xE
1550 #define I40E_LINK_ACTIVITY 0xC
1551 #define I40E_MAC_ACTIVITY 0xD
1552 #define I40E_LED0 22
1555 * i40e_led_get - return current on/off mode
1556 * @hw: pointer to the hw struct
1558 * The value returned is the 'mode' field as defined in the
1559 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1560 * values are variations of possible behaviors relating to
1561 * blink, link, and wire.
1563 u32 i40e_led_get(struct i40e_hw *hw)
1565 u32 current_mode = 0;
1569 /* as per the documentation GPIO 22-29 are the LED
1570 * GPIO pins named LED0..LED7
1572 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1573 u32 gpio_val = i40e_led_is_mine(hw, i);
1578 /* ignore gpio LED src mode entries related to the activity
1581 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1582 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1583 switch (current_mode) {
1584 case I40E_COMBINED_ACTIVITY:
1585 case I40E_FILTER_ACTIVITY:
1586 case I40E_MAC_ACTIVITY:
1592 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1593 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1601 * i40e_led_set - set new on/off mode
1602 * @hw: pointer to the hw struct
1603 * @mode: 0=off, 0xf=on (else see manual for mode details)
1604 * @blink: true if the LED should blink when on, false if steady
1606 * if this function is used to turn on the blink it should
1607 * be used to disable the blink when restoring the original state.
1609 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1611 u32 current_mode = 0;
1614 if (mode & 0xfffffff0)
1615 DEBUGOUT1("invalid mode passed in %X\n", mode);
1617 /* as per the documentation GPIO 22-29 are the LED
1618 * GPIO pins named LED0..LED7
1620 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1621 u32 gpio_val = i40e_led_is_mine(hw, i);
1626 /* ignore gpio LED src mode entries related to the activity
1629 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1630 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1631 switch (current_mode) {
1632 case I40E_COMBINED_ACTIVITY:
1633 case I40E_FILTER_ACTIVITY:
1634 case I40E_MAC_ACTIVITY:
1640 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1641 /* this & is a bit of paranoia, but serves as a range check */
1642 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1643 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1645 if (mode == I40E_LINK_ACTIVITY)
1649 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1651 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1653 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1658 /* Admin command wrappers */
1661 * i40e_aq_get_phy_capabilities
1662 * @hw: pointer to the hw struct
1663 * @abilities: structure for PHY capabilities to be filled
1664 * @qualified_modules: report Qualified Modules
1665 * @report_init: report init capabilities (active are default)
1666 * @cmd_details: pointer to command details structure or NULL
1668 * Returns the various PHY abilities supported on the Port.
1670 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1671 bool qualified_modules, bool report_init,
1672 struct i40e_aq_get_phy_abilities_resp *abilities,
1673 struct i40e_asq_cmd_details *cmd_details)
1675 struct i40e_aq_desc desc;
1676 enum i40e_status_code status;
1677 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1680 return I40E_ERR_PARAM;
1682 i40e_fill_default_direct_cmd_desc(&desc,
1683 i40e_aqc_opc_get_phy_abilities);
1685 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1686 if (abilities_size > I40E_AQ_LARGE_BUF)
1687 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1689 if (qualified_modules)
1690 desc.params.external.param0 |=
1691 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1694 desc.params.external.param0 |=
1695 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1697 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1700 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1701 status = I40E_ERR_UNKNOWN_PHY;
1704 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1705 hw->phy.phy_types |= ((u64)abilities->phy_type_ext << 32);
1712 * i40e_aq_set_phy_config
1713 * @hw: pointer to the hw struct
1714 * @config: structure with PHY configuration to be set
1715 * @cmd_details: pointer to command details structure or NULL
1717 * Set the various PHY configuration parameters
1718 * supported on the Port.One or more of the Set PHY config parameters may be
1719 * ignored in an MFP mode as the PF may not have the privilege to set some
1720 * of the PHY Config parameters. This status will be indicated by the
1723 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1724 struct i40e_aq_set_phy_config *config,
1725 struct i40e_asq_cmd_details *cmd_details)
1727 struct i40e_aq_desc desc;
1728 struct i40e_aq_set_phy_config *cmd =
1729 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1730 enum i40e_status_code status;
1733 return I40E_ERR_PARAM;
1735 i40e_fill_default_direct_cmd_desc(&desc,
1736 i40e_aqc_opc_set_phy_config);
1740 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1747 * @hw: pointer to the hw struct
1749 * Set the requested flow control mode using set_phy_config.
1751 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1752 bool atomic_restart)
1754 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1755 struct i40e_aq_get_phy_abilities_resp abilities;
1756 struct i40e_aq_set_phy_config config;
1757 enum i40e_status_code status;
1758 u8 pause_mask = 0x0;
1764 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1765 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1767 case I40E_FC_RX_PAUSE:
1768 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1770 case I40E_FC_TX_PAUSE:
1771 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1777 /* Get the current phy config */
1778 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1781 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1785 memset(&config, 0, sizeof(config));
1786 /* clear the old pause settings */
1787 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1788 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1789 /* set the new abilities */
1790 config.abilities |= pause_mask;
1791 /* If the abilities have changed, then set the new config */
1792 if (config.abilities != abilities.abilities) {
1793 /* Auto restart link so settings take effect */
1795 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1796 /* Copy over all the old settings */
1797 config.phy_type = abilities.phy_type;
1798 config.phy_type_ext = abilities.phy_type_ext;
1799 config.link_speed = abilities.link_speed;
1800 config.eee_capability = abilities.eee_capability;
1801 config.eeer = abilities.eeer_val;
1802 config.low_power_ctrl = abilities.d3_lpan;
1803 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1804 I40E_AQ_PHY_FEC_CONFIG_MASK;
1805 status = i40e_aq_set_phy_config(hw, &config, NULL);
1808 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1810 /* Update the link info */
1811 status = i40e_update_link_info(hw);
1813 /* Wait a little bit (on 40G cards it sometimes takes a really
1814 * long time for link to come back from the atomic reset)
1817 i40e_msec_delay(1000);
1818 status = i40e_update_link_info(hw);
1821 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1827 * i40e_aq_set_mac_config
1828 * @hw: pointer to the hw struct
1829 * @max_frame_size: Maximum Frame Size to be supported by the port
1830 * @crc_en: Tell HW to append a CRC to outgoing frames
1831 * @pacing: Pacing configurations
1832 * @cmd_details: pointer to command details structure or NULL
1834 * Configure MAC settings for frame size, jumbo frame support and the
1835 * addition of a CRC by the hardware.
1837 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1839 bool crc_en, u16 pacing,
1840 struct i40e_asq_cmd_details *cmd_details)
1842 struct i40e_aq_desc desc;
1843 struct i40e_aq_set_mac_config *cmd =
1844 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1845 enum i40e_status_code status;
1847 if (max_frame_size == 0)
1848 return I40E_ERR_PARAM;
1850 i40e_fill_default_direct_cmd_desc(&desc,
1851 i40e_aqc_opc_set_mac_config);
1853 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1854 cmd->params = ((u8)pacing & 0x0F) << 3;
1856 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1858 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1864 * i40e_aq_clear_pxe_mode
1865 * @hw: pointer to the hw struct
1866 * @cmd_details: pointer to command details structure or NULL
1868 * Tell the firmware that the driver is taking over from PXE
1870 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1871 struct i40e_asq_cmd_details *cmd_details)
1873 enum i40e_status_code status;
1874 struct i40e_aq_desc desc;
1875 struct i40e_aqc_clear_pxe *cmd =
1876 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1878 i40e_fill_default_direct_cmd_desc(&desc,
1879 i40e_aqc_opc_clear_pxe_mode);
1883 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1885 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1891 * i40e_aq_set_link_restart_an
1892 * @hw: pointer to the hw struct
1893 * @enable_link: if true: enable link, if false: disable link
1894 * @cmd_details: pointer to command details structure or NULL
1896 * Sets up the link and restarts the Auto-Negotiation over the link.
1898 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1899 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1901 struct i40e_aq_desc desc;
1902 struct i40e_aqc_set_link_restart_an *cmd =
1903 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1904 enum i40e_status_code status;
1906 i40e_fill_default_direct_cmd_desc(&desc,
1907 i40e_aqc_opc_set_link_restart_an);
1909 cmd->command = I40E_AQ_PHY_RESTART_AN;
1911 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1913 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1915 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1921 * i40e_aq_get_link_info
1922 * @hw: pointer to the hw struct
1923 * @enable_lse: enable/disable LinkStatusEvent reporting
1924 * @link: pointer to link status structure - optional
1925 * @cmd_details: pointer to command details structure or NULL
1927 * Returns the link status of the adapter.
1929 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1930 bool enable_lse, struct i40e_link_status *link,
1931 struct i40e_asq_cmd_details *cmd_details)
1933 struct i40e_aq_desc desc;
1934 struct i40e_aqc_get_link_status *resp =
1935 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1936 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1937 enum i40e_status_code status;
1938 bool tx_pause, rx_pause;
1941 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1944 command_flags = I40E_AQ_LSE_ENABLE;
1946 command_flags = I40E_AQ_LSE_DISABLE;
1947 resp->command_flags = CPU_TO_LE16(command_flags);
1949 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1951 if (status != I40E_SUCCESS)
1952 goto aq_get_link_info_exit;
1954 /* save off old link status information */
1955 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1956 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1958 /* update link status */
1959 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1960 hw->phy.media_type = i40e_get_media_type(hw);
1961 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1962 hw_link_info->link_info = resp->link_info;
1963 hw_link_info->an_info = resp->an_info;
1964 hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
1965 I40E_AQ_CONFIG_FEC_RS_ENA);
1966 hw_link_info->ext_info = resp->ext_info;
1967 hw_link_info->loopback = resp->loopback;
1968 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1969 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1971 /* update fc info */
1972 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1973 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1974 if (tx_pause & rx_pause)
1975 hw->fc.current_mode = I40E_FC_FULL;
1977 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1979 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1981 hw->fc.current_mode = I40E_FC_NONE;
1983 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1984 hw_link_info->crc_enable = true;
1986 hw_link_info->crc_enable = false;
1988 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
1989 hw_link_info->lse_enable = true;
1991 hw_link_info->lse_enable = false;
1993 if ((hw->mac.type == I40E_MAC_XL710) &&
1994 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1995 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1996 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1998 /* save link status information */
2000 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
2001 I40E_NONDMA_TO_NONDMA);
2003 /* flag cleared so helper functions don't call AQ again */
2004 hw->phy.get_link_info = false;
2006 aq_get_link_info_exit:
2011 * i40e_aq_set_phy_int_mask
2012 * @hw: pointer to the hw struct
2013 * @mask: interrupt mask to be set
2014 * @cmd_details: pointer to command details structure or NULL
2016 * Set link interrupt mask.
2018 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2020 struct i40e_asq_cmd_details *cmd_details)
2022 struct i40e_aq_desc desc;
2023 struct i40e_aqc_set_phy_int_mask *cmd =
2024 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2025 enum i40e_status_code status;
2027 i40e_fill_default_direct_cmd_desc(&desc,
2028 i40e_aqc_opc_set_phy_int_mask);
2030 cmd->event_mask = CPU_TO_LE16(mask);
2032 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2038 * i40e_aq_get_local_advt_reg
2039 * @hw: pointer to the hw struct
2040 * @advt_reg: local AN advertisement register value
2041 * @cmd_details: pointer to command details structure or NULL
2043 * Get the Local AN advertisement register value.
2045 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2047 struct i40e_asq_cmd_details *cmd_details)
2049 struct i40e_aq_desc desc;
2050 struct i40e_aqc_an_advt_reg *resp =
2051 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2052 enum i40e_status_code status;
2054 i40e_fill_default_direct_cmd_desc(&desc,
2055 i40e_aqc_opc_get_local_advt_reg);
2057 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2059 if (status != I40E_SUCCESS)
2060 goto aq_get_local_advt_reg_exit;
2062 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2063 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2065 aq_get_local_advt_reg_exit:
2070 * i40e_aq_set_local_advt_reg
2071 * @hw: pointer to the hw struct
2072 * @advt_reg: local AN advertisement register value
2073 * @cmd_details: pointer to command details structure or NULL
2075 * Get the Local AN advertisement register value.
2077 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2079 struct i40e_asq_cmd_details *cmd_details)
2081 struct i40e_aq_desc desc;
2082 struct i40e_aqc_an_advt_reg *cmd =
2083 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2084 enum i40e_status_code status;
2086 i40e_fill_default_direct_cmd_desc(&desc,
2087 i40e_aqc_opc_get_local_advt_reg);
2089 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2090 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2092 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2098 * i40e_aq_get_partner_advt
2099 * @hw: pointer to the hw struct
2100 * @advt_reg: AN partner advertisement register value
2101 * @cmd_details: pointer to command details structure or NULL
2103 * Get the link partner AN advertisement register value.
2105 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2107 struct i40e_asq_cmd_details *cmd_details)
2109 struct i40e_aq_desc desc;
2110 struct i40e_aqc_an_advt_reg *resp =
2111 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2112 enum i40e_status_code status;
2114 i40e_fill_default_direct_cmd_desc(&desc,
2115 i40e_aqc_opc_get_partner_advt);
2117 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2119 if (status != I40E_SUCCESS)
2120 goto aq_get_partner_advt_exit;
2122 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2123 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2125 aq_get_partner_advt_exit:
2130 * i40e_aq_set_lb_modes
2131 * @hw: pointer to the hw struct
2132 * @lb_modes: loopback mode to be set
2133 * @cmd_details: pointer to command details structure or NULL
2135 * Sets loopback modes.
2137 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2139 struct i40e_asq_cmd_details *cmd_details)
2141 struct i40e_aq_desc desc;
2142 struct i40e_aqc_set_lb_mode *cmd =
2143 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2144 enum i40e_status_code status;
2146 i40e_fill_default_direct_cmd_desc(&desc,
2147 i40e_aqc_opc_set_lb_modes);
2149 cmd->lb_mode = CPU_TO_LE16(lb_modes);
2151 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2157 * i40e_aq_set_phy_debug
2158 * @hw: pointer to the hw struct
2159 * @cmd_flags: debug command flags
2160 * @cmd_details: pointer to command details structure or NULL
2162 * Reset the external PHY.
2164 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2165 struct i40e_asq_cmd_details *cmd_details)
2167 struct i40e_aq_desc desc;
2168 struct i40e_aqc_set_phy_debug *cmd =
2169 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2170 enum i40e_status_code status;
2172 i40e_fill_default_direct_cmd_desc(&desc,
2173 i40e_aqc_opc_set_phy_debug);
2175 cmd->command_flags = cmd_flags;
2177 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2184 * @hw: pointer to the hw struct
2185 * @vsi_ctx: pointer to a vsi context struct
2186 * @cmd_details: pointer to command details structure or NULL
2188 * Add a VSI context to the hardware.
2190 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2191 struct i40e_vsi_context *vsi_ctx,
2192 struct i40e_asq_cmd_details *cmd_details)
2194 struct i40e_aq_desc desc;
2195 struct i40e_aqc_add_get_update_vsi *cmd =
2196 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2197 struct i40e_aqc_add_get_update_vsi_completion *resp =
2198 (struct i40e_aqc_add_get_update_vsi_completion *)
2200 enum i40e_status_code status;
2202 i40e_fill_default_direct_cmd_desc(&desc,
2203 i40e_aqc_opc_add_vsi);
2205 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2206 cmd->connection_type = vsi_ctx->connection_type;
2207 cmd->vf_id = vsi_ctx->vf_num;
2208 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2210 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2212 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2213 sizeof(vsi_ctx->info), cmd_details);
2215 if (status != I40E_SUCCESS)
2216 goto aq_add_vsi_exit;
2218 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2219 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2220 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2221 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2228 * i40e_aq_set_default_vsi
2229 * @hw: pointer to the hw struct
2231 * @cmd_details: pointer to command details structure or NULL
2233 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2235 struct i40e_asq_cmd_details *cmd_details)
2237 struct i40e_aq_desc desc;
2238 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2239 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2241 enum i40e_status_code status;
2243 i40e_fill_default_direct_cmd_desc(&desc,
2244 i40e_aqc_opc_set_vsi_promiscuous_modes);
2246 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2247 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2248 cmd->seid = CPU_TO_LE16(seid);
2250 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2256 * i40e_aq_clear_default_vsi
2257 * @hw: pointer to the hw struct
2259 * @cmd_details: pointer to command details structure or NULL
2261 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2263 struct i40e_asq_cmd_details *cmd_details)
2265 struct i40e_aq_desc desc;
2266 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2267 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2269 enum i40e_status_code status;
2271 i40e_fill_default_direct_cmd_desc(&desc,
2272 i40e_aqc_opc_set_vsi_promiscuous_modes);
2274 cmd->promiscuous_flags = CPU_TO_LE16(0);
2275 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2276 cmd->seid = CPU_TO_LE16(seid);
2278 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2284 * i40e_aq_set_vsi_unicast_promiscuous
2285 * @hw: pointer to the hw struct
2287 * @set: set unicast promiscuous enable/disable
2288 * @cmd_details: pointer to command details structure or NULL
2289 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2291 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2293 struct i40e_asq_cmd_details *cmd_details,
2294 bool rx_only_promisc)
2296 struct i40e_aq_desc desc;
2297 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2298 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2299 enum i40e_status_code status;
2302 i40e_fill_default_direct_cmd_desc(&desc,
2303 i40e_aqc_opc_set_vsi_promiscuous_modes);
2306 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2307 if (rx_only_promisc &&
2308 (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2309 (hw->aq.api_maj_ver > 1)))
2310 flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2313 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2315 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2316 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2317 (hw->aq.api_maj_ver > 1))
2318 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2320 cmd->seid = CPU_TO_LE16(seid);
2321 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2327 * i40e_aq_set_vsi_multicast_promiscuous
2328 * @hw: pointer to the hw struct
2330 * @set: set multicast promiscuous enable/disable
2331 * @cmd_details: pointer to command details structure or NULL
2333 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2334 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2336 struct i40e_aq_desc desc;
2337 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2338 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2339 enum i40e_status_code status;
2342 i40e_fill_default_direct_cmd_desc(&desc,
2343 i40e_aqc_opc_set_vsi_promiscuous_modes);
2346 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2348 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2350 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2352 cmd->seid = CPU_TO_LE16(seid);
2353 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2359 * i40e_aq_set_vsi_full_promiscuous
2360 * @hw: pointer to the hw struct
2362 * @set: set promiscuous enable/disable
2363 * @cmd_details: pointer to command details structure or NULL
2365 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw,
2367 struct i40e_asq_cmd_details *cmd_details)
2369 struct i40e_aq_desc desc;
2370 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2371 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2372 enum i40e_status_code status;
2375 i40e_fill_default_direct_cmd_desc(&desc,
2376 i40e_aqc_opc_set_vsi_promiscuous_modes);
2379 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST |
2380 I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2381 I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2383 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2385 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST |
2386 I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2387 I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2389 cmd->seid = CPU_TO_LE16(seid);
2390 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2396 * i40e_aq_set_vsi_mc_promisc_on_vlan
2397 * @hw: pointer to the hw struct
2399 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2400 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2401 * @cmd_details: pointer to command details structure or NULL
2403 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2404 u16 seid, bool enable, u16 vid,
2405 struct i40e_asq_cmd_details *cmd_details)
2407 struct i40e_aq_desc desc;
2408 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2409 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2410 enum i40e_status_code status;
2413 i40e_fill_default_direct_cmd_desc(&desc,
2414 i40e_aqc_opc_set_vsi_promiscuous_modes);
2417 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2419 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2420 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2421 cmd->seid = CPU_TO_LE16(seid);
2422 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2424 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2430 * i40e_aq_set_vsi_uc_promisc_on_vlan
2431 * @hw: pointer to the hw struct
2433 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2434 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2435 * @cmd_details: pointer to command details structure or NULL
2437 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2438 u16 seid, bool enable, u16 vid,
2439 struct i40e_asq_cmd_details *cmd_details)
2441 struct i40e_aq_desc desc;
2442 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2443 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2444 enum i40e_status_code status;
2447 i40e_fill_default_direct_cmd_desc(&desc,
2448 i40e_aqc_opc_set_vsi_promiscuous_modes);
2451 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2453 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2454 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2455 cmd->seid = CPU_TO_LE16(seid);
2456 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2458 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2464 * i40e_aq_set_vsi_bc_promisc_on_vlan
2465 * @hw: pointer to the hw struct
2467 * @enable: set broadcast promiscuous enable/disable for a given VLAN
2468 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2469 * @cmd_details: pointer to command details structure or NULL
2471 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2472 u16 seid, bool enable, u16 vid,
2473 struct i40e_asq_cmd_details *cmd_details)
2475 struct i40e_aq_desc desc;
2476 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2477 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2478 enum i40e_status_code status;
2481 i40e_fill_default_direct_cmd_desc(&desc,
2482 i40e_aqc_opc_set_vsi_promiscuous_modes);
2485 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2487 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2488 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2489 cmd->seid = CPU_TO_LE16(seid);
2490 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2492 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2498 * i40e_aq_set_vsi_broadcast
2499 * @hw: pointer to the hw struct
2501 * @set_filter: true to set filter, false to clear filter
2502 * @cmd_details: pointer to command details structure or NULL
2504 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2506 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2507 u16 seid, bool set_filter,
2508 struct i40e_asq_cmd_details *cmd_details)
2510 struct i40e_aq_desc desc;
2511 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2512 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2513 enum i40e_status_code status;
2515 i40e_fill_default_direct_cmd_desc(&desc,
2516 i40e_aqc_opc_set_vsi_promiscuous_modes);
2519 cmd->promiscuous_flags
2520 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2522 cmd->promiscuous_flags
2523 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2525 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2526 cmd->seid = CPU_TO_LE16(seid);
2527 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2533 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2534 * @hw: pointer to the hw struct
2536 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2537 * @cmd_details: pointer to command details structure or NULL
2539 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2540 u16 seid, bool enable,
2541 struct i40e_asq_cmd_details *cmd_details)
2543 struct i40e_aq_desc desc;
2544 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2545 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2546 enum i40e_status_code status;
2549 i40e_fill_default_direct_cmd_desc(&desc,
2550 i40e_aqc_opc_set_vsi_promiscuous_modes);
2552 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2554 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2555 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2556 cmd->seid = CPU_TO_LE16(seid);
2558 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2564 * i40e_get_vsi_params - get VSI configuration info
2565 * @hw: pointer to the hw struct
2566 * @vsi_ctx: pointer to a vsi context struct
2567 * @cmd_details: pointer to command details structure or NULL
2569 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2570 struct i40e_vsi_context *vsi_ctx,
2571 struct i40e_asq_cmd_details *cmd_details)
2573 struct i40e_aq_desc desc;
2574 struct i40e_aqc_add_get_update_vsi *cmd =
2575 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2576 struct i40e_aqc_add_get_update_vsi_completion *resp =
2577 (struct i40e_aqc_add_get_update_vsi_completion *)
2579 enum i40e_status_code status;
2581 UNREFERENCED_1PARAMETER(cmd_details);
2582 i40e_fill_default_direct_cmd_desc(&desc,
2583 i40e_aqc_opc_get_vsi_parameters);
2585 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2587 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2589 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2590 sizeof(vsi_ctx->info), NULL);
2592 if (status != I40E_SUCCESS)
2593 goto aq_get_vsi_params_exit;
2595 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2596 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2597 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2598 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2600 aq_get_vsi_params_exit:
2605 * i40e_aq_update_vsi_params
2606 * @hw: pointer to the hw struct
2607 * @vsi_ctx: pointer to a vsi context struct
2608 * @cmd_details: pointer to command details structure or NULL
2610 * Update a VSI context.
2612 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2613 struct i40e_vsi_context *vsi_ctx,
2614 struct i40e_asq_cmd_details *cmd_details)
2616 struct i40e_aq_desc desc;
2617 struct i40e_aqc_add_get_update_vsi *cmd =
2618 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2619 struct i40e_aqc_add_get_update_vsi_completion *resp =
2620 (struct i40e_aqc_add_get_update_vsi_completion *)
2622 enum i40e_status_code status;
2624 i40e_fill_default_direct_cmd_desc(&desc,
2625 i40e_aqc_opc_update_vsi_parameters);
2626 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2628 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2630 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2631 sizeof(vsi_ctx->info), cmd_details);
2633 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2634 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2640 * i40e_aq_get_switch_config
2641 * @hw: pointer to the hardware structure
2642 * @buf: pointer to the result buffer
2643 * @buf_size: length of input buffer
2644 * @start_seid: seid to start for the report, 0 == beginning
2645 * @cmd_details: pointer to command details structure or NULL
2647 * Fill the buf with switch configuration returned from AdminQ command
2649 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2650 struct i40e_aqc_get_switch_config_resp *buf,
2651 u16 buf_size, u16 *start_seid,
2652 struct i40e_asq_cmd_details *cmd_details)
2654 struct i40e_aq_desc desc;
2655 struct i40e_aqc_switch_seid *scfg =
2656 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2657 enum i40e_status_code status;
2659 i40e_fill_default_direct_cmd_desc(&desc,
2660 i40e_aqc_opc_get_switch_config);
2661 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2662 if (buf_size > I40E_AQ_LARGE_BUF)
2663 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2664 scfg->seid = CPU_TO_LE16(*start_seid);
2666 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2667 *start_seid = LE16_TO_CPU(scfg->seid);
2673 * i40e_aq_set_switch_config
2674 * @hw: pointer to the hardware structure
2675 * @flags: bit flag values to set
2676 * @valid_flags: which bit flags to set
2677 * @cmd_details: pointer to command details structure or NULL
2679 * Set switch configuration bits
2681 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2682 u16 flags, u16 valid_flags,
2683 struct i40e_asq_cmd_details *cmd_details)
2685 struct i40e_aq_desc desc;
2686 struct i40e_aqc_set_switch_config *scfg =
2687 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2688 enum i40e_status_code status;
2690 i40e_fill_default_direct_cmd_desc(&desc,
2691 i40e_aqc_opc_set_switch_config);
2692 scfg->flags = CPU_TO_LE16(flags);
2693 scfg->valid_flags = CPU_TO_LE16(valid_flags);
2695 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2701 * i40e_aq_get_firmware_version
2702 * @hw: pointer to the hw struct
2703 * @fw_major_version: firmware major version
2704 * @fw_minor_version: firmware minor version
2705 * @fw_build: firmware build number
2706 * @api_major_version: major queue version
2707 * @api_minor_version: minor queue version
2708 * @cmd_details: pointer to command details structure or NULL
2710 * Get the firmware version from the admin queue commands
2712 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2713 u16 *fw_major_version, u16 *fw_minor_version,
2715 u16 *api_major_version, u16 *api_minor_version,
2716 struct i40e_asq_cmd_details *cmd_details)
2718 struct i40e_aq_desc desc;
2719 struct i40e_aqc_get_version *resp =
2720 (struct i40e_aqc_get_version *)&desc.params.raw;
2721 enum i40e_status_code status;
2723 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2725 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2727 if (status == I40E_SUCCESS) {
2728 if (fw_major_version != NULL)
2729 *fw_major_version = LE16_TO_CPU(resp->fw_major);
2730 if (fw_minor_version != NULL)
2731 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2732 if (fw_build != NULL)
2733 *fw_build = LE32_TO_CPU(resp->fw_build);
2734 if (api_major_version != NULL)
2735 *api_major_version = LE16_TO_CPU(resp->api_major);
2736 if (api_minor_version != NULL)
2737 *api_minor_version = LE16_TO_CPU(resp->api_minor);
2739 /* A workaround to fix the API version in SW */
2740 if (api_major_version && api_minor_version &&
2741 fw_major_version && fw_minor_version &&
2742 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2743 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2744 (*fw_major_version > 4)))
2745 *api_minor_version = 2;
2752 * i40e_aq_send_driver_version
2753 * @hw: pointer to the hw struct
2754 * @dv: driver's major, minor version
2755 * @cmd_details: pointer to command details structure or NULL
2757 * Send the driver version to the firmware
2759 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2760 struct i40e_driver_version *dv,
2761 struct i40e_asq_cmd_details *cmd_details)
2763 struct i40e_aq_desc desc;
2764 struct i40e_aqc_driver_version *cmd =
2765 (struct i40e_aqc_driver_version *)&desc.params.raw;
2766 enum i40e_status_code status;
2770 return I40E_ERR_PARAM;
2772 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2774 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2775 cmd->driver_major_ver = dv->major_version;
2776 cmd->driver_minor_ver = dv->minor_version;
2777 cmd->driver_build_ver = dv->build_version;
2778 cmd->driver_subbuild_ver = dv->subbuild_version;
2781 while (len < sizeof(dv->driver_string) &&
2782 (dv->driver_string[len] < 0x80) &&
2783 dv->driver_string[len])
2785 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2792 * i40e_get_link_status - get status of the HW network link
2793 * @hw: pointer to the hw struct
2794 * @link_up: pointer to bool (true/false = linkup/linkdown)
2796 * Variable link_up true if link is up, false if link is down.
2797 * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2799 * Side effect: LinkStatusEvent reporting becomes enabled
2801 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2803 enum i40e_status_code status = I40E_SUCCESS;
2805 if (hw->phy.get_link_info) {
2806 status = i40e_update_link_info(hw);
2808 if (status != I40E_SUCCESS)
2809 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2813 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2819 * i40e_updatelink_status - update status of the HW network link
2820 * @hw: pointer to the hw struct
2822 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2824 struct i40e_aq_get_phy_abilities_resp abilities;
2825 enum i40e_status_code status = I40E_SUCCESS;
2827 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2831 /* extra checking needed to ensure link info to user is timely */
2832 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2833 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2834 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2835 status = i40e_aq_get_phy_capabilities(hw, false, false,
2840 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2841 sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2848 * i40e_get_link_speed
2849 * @hw: pointer to the hw struct
2851 * Returns the link speed of the adapter.
2853 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2855 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2856 enum i40e_status_code status = I40E_SUCCESS;
2858 if (hw->phy.get_link_info) {
2859 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2861 if (status != I40E_SUCCESS)
2862 goto i40e_link_speed_exit;
2865 speed = hw->phy.link_info.link_speed;
2867 i40e_link_speed_exit:
2872 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2873 * @hw: pointer to the hw struct
2874 * @uplink_seid: the MAC or other gizmo SEID
2875 * @downlink_seid: the VSI SEID
2876 * @enabled_tc: bitmap of TCs to be enabled
2877 * @default_port: true for default port VSI, false for control port
2878 * @veb_seid: pointer to where to put the resulting VEB SEID
2879 * @enable_stats: true to turn on VEB stats
2880 * @cmd_details: pointer to command details structure or NULL
2882 * This asks the FW to add a VEB between the uplink and downlink
2883 * elements. If the uplink SEID is 0, this will be a floating VEB.
2885 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2886 u16 downlink_seid, u8 enabled_tc,
2887 bool default_port, u16 *veb_seid,
2889 struct i40e_asq_cmd_details *cmd_details)
2891 struct i40e_aq_desc desc;
2892 struct i40e_aqc_add_veb *cmd =
2893 (struct i40e_aqc_add_veb *)&desc.params.raw;
2894 struct i40e_aqc_add_veb_completion *resp =
2895 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2896 enum i40e_status_code status;
2899 /* SEIDs need to either both be set or both be 0 for floating VEB */
2900 if (!!uplink_seid != !!downlink_seid)
2901 return I40E_ERR_PARAM;
2903 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2905 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2906 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2907 cmd->enable_tcs = enabled_tc;
2909 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2911 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2913 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2915 /* reverse logic here: set the bitflag to disable the stats */
2917 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2919 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2921 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2923 if (!status && veb_seid)
2924 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2930 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2931 * @hw: pointer to the hw struct
2932 * @veb_seid: the SEID of the VEB to query
2933 * @switch_id: the uplink switch id
2934 * @floating: set to true if the VEB is floating
2935 * @statistic_index: index of the stats counter block for this VEB
2936 * @vebs_used: number of VEB's used by function
2937 * @vebs_free: total VEB's not reserved by any function
2938 * @cmd_details: pointer to command details structure or NULL
2940 * This retrieves the parameters for a particular VEB, specified by
2941 * uplink_seid, and returns them to the caller.
2943 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2944 u16 veb_seid, u16 *switch_id,
2945 bool *floating, u16 *statistic_index,
2946 u16 *vebs_used, u16 *vebs_free,
2947 struct i40e_asq_cmd_details *cmd_details)
2949 struct i40e_aq_desc desc;
2950 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2951 (struct i40e_aqc_get_veb_parameters_completion *)
2953 enum i40e_status_code status;
2956 return I40E_ERR_PARAM;
2958 i40e_fill_default_direct_cmd_desc(&desc,
2959 i40e_aqc_opc_get_veb_parameters);
2960 cmd_resp->seid = CPU_TO_LE16(veb_seid);
2962 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2967 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2968 if (statistic_index)
2969 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2971 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2973 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2975 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2977 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2988 * i40e_aq_add_macvlan
2989 * @hw: pointer to the hw struct
2990 * @seid: VSI for the mac address
2991 * @mv_list: list of macvlans to be added
2992 * @count: length of the list
2993 * @cmd_details: pointer to command details structure or NULL
2995 * Add MAC/VLAN addresses to the HW filtering
2997 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2998 struct i40e_aqc_add_macvlan_element_data *mv_list,
2999 u16 count, struct i40e_asq_cmd_details *cmd_details)
3001 struct i40e_aq_desc desc;
3002 struct i40e_aqc_macvlan *cmd =
3003 (struct i40e_aqc_macvlan *)&desc.params.raw;
3004 enum i40e_status_code status;
3008 if (count == 0 || !mv_list || !hw)
3009 return I40E_ERR_PARAM;
3011 buf_size = count * sizeof(*mv_list);
3013 /* prep the rest of the request */
3014 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
3015 cmd->num_addresses = CPU_TO_LE16(count);
3016 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3020 for (i = 0; i < count; i++)
3021 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
3023 CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
3025 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3026 if (buf_size > I40E_AQ_LARGE_BUF)
3027 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3029 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3036 * i40e_aq_remove_macvlan
3037 * @hw: pointer to the hw struct
3038 * @seid: VSI for the mac address
3039 * @mv_list: list of macvlans to be removed
3040 * @count: length of the list
3041 * @cmd_details: pointer to command details structure or NULL
3043 * Remove MAC/VLAN addresses from the HW filtering
3045 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
3046 struct i40e_aqc_remove_macvlan_element_data *mv_list,
3047 u16 count, struct i40e_asq_cmd_details *cmd_details)
3049 struct i40e_aq_desc desc;
3050 struct i40e_aqc_macvlan *cmd =
3051 (struct i40e_aqc_macvlan *)&desc.params.raw;
3052 enum i40e_status_code status;
3055 if (count == 0 || !mv_list || !hw)
3056 return I40E_ERR_PARAM;
3058 buf_size = count * sizeof(*mv_list);
3060 /* prep the rest of the request */
3061 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
3062 cmd->num_addresses = CPU_TO_LE16(count);
3063 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3067 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3068 if (buf_size > I40E_AQ_LARGE_BUF)
3069 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3071 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3078 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3079 * @hw: pointer to the hw struct
3080 * @opcode: AQ opcode for add or delete mirror rule
3081 * @sw_seid: Switch SEID (to which rule refers)
3082 * @rule_type: Rule Type (ingress/egress/VLAN)
3083 * @id: Destination VSI SEID or Rule ID
3084 * @count: length of the list
3085 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3086 * @cmd_details: pointer to command details structure or NULL
3087 * @rule_id: Rule ID returned from FW
3088 * @rule_used: Number of rules used in internal switch
3089 * @rule_free: Number of rules free in internal switch
3091 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3092 * VEBs/VEPA elements only
3094 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3095 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3096 u16 count, __le16 *mr_list,
3097 struct i40e_asq_cmd_details *cmd_details,
3098 u16 *rule_id, u16 *rules_used, u16 *rules_free)
3100 struct i40e_aq_desc desc;
3101 struct i40e_aqc_add_delete_mirror_rule *cmd =
3102 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3103 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3104 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3105 enum i40e_status_code status;
3108 buf_size = count * sizeof(*mr_list);
3110 /* prep the rest of the request */
3111 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3112 cmd->seid = CPU_TO_LE16(sw_seid);
3113 cmd->rule_type = CPU_TO_LE16(rule_type &
3114 I40E_AQC_MIRROR_RULE_TYPE_MASK);
3115 cmd->num_entries = CPU_TO_LE16(count);
3116 /* Dest VSI for add, rule_id for delete */
3117 cmd->destination = CPU_TO_LE16(id);
3119 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3121 if (buf_size > I40E_AQ_LARGE_BUF)
3122 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3125 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3127 if (status == I40E_SUCCESS ||
3128 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3130 *rule_id = LE16_TO_CPU(resp->rule_id);
3132 *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3134 *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3140 * i40e_aq_add_mirrorrule - add a mirror rule
3141 * @hw: pointer to the hw struct
3142 * @sw_seid: Switch SEID (to which rule refers)
3143 * @rule_type: Rule Type (ingress/egress/VLAN)
3144 * @dest_vsi: SEID of VSI to which packets will be mirrored
3145 * @count: length of the list
3146 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3147 * @cmd_details: pointer to command details structure or NULL
3148 * @rule_id: Rule ID returned from FW
3149 * @rule_used: Number of rules used in internal switch
3150 * @rule_free: Number of rules free in internal switch
3152 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3154 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3155 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3156 struct i40e_asq_cmd_details *cmd_details,
3157 u16 *rule_id, u16 *rules_used, u16 *rules_free)
3159 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3160 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3161 if (count == 0 || !mr_list)
3162 return I40E_ERR_PARAM;
3165 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3166 rule_type, dest_vsi, count, mr_list,
3167 cmd_details, rule_id, rules_used, rules_free);
3171 * i40e_aq_delete_mirrorrule - delete a mirror rule
3172 * @hw: pointer to the hw struct
3173 * @sw_seid: Switch SEID (to which rule refers)
3174 * @rule_type: Rule Type (ingress/egress/VLAN)
3175 * @count: length of the list
3176 * @rule_id: Rule ID that is returned in the receive desc as part of
3178 * @mr_list: list of mirrored VLAN IDs to be removed
3179 * @cmd_details: pointer to command details structure or NULL
3180 * @rule_used: Number of rules used in internal switch
3181 * @rule_free: Number of rules free in internal switch
3183 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3185 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3186 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3187 struct i40e_asq_cmd_details *cmd_details,
3188 u16 *rules_used, u16 *rules_free)
3190 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3191 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3192 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3193 * mirroring. For other rule_type, count and rule_type should
3196 if (count == 0 || !mr_list)
3197 return I40E_ERR_PARAM;
3200 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3201 rule_type, rule_id, count, mr_list,
3202 cmd_details, NULL, rules_used, rules_free);
3206 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3207 * @hw: pointer to the hw struct
3208 * @seid: VSI for the vlan filters
3209 * @v_list: list of vlan filters to be added
3210 * @count: length of the list
3211 * @cmd_details: pointer to command details structure or NULL
3213 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3214 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3215 u8 count, struct i40e_asq_cmd_details *cmd_details)
3217 struct i40e_aq_desc desc;
3218 struct i40e_aqc_macvlan *cmd =
3219 (struct i40e_aqc_macvlan *)&desc.params.raw;
3220 enum i40e_status_code status;
3223 if (count == 0 || !v_list || !hw)
3224 return I40E_ERR_PARAM;
3226 buf_size = count * sizeof(*v_list);
3228 /* prep the rest of the request */
3229 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3230 cmd->num_addresses = CPU_TO_LE16(count);
3231 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3235 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3236 if (buf_size > I40E_AQ_LARGE_BUF)
3237 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3239 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3246 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3247 * @hw: pointer to the hw struct
3248 * @seid: VSI for the vlan filters
3249 * @v_list: list of macvlans to be removed
3250 * @count: length of the list
3251 * @cmd_details: pointer to command details structure or NULL
3253 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3254 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3255 u8 count, struct i40e_asq_cmd_details *cmd_details)
3257 struct i40e_aq_desc desc;
3258 struct i40e_aqc_macvlan *cmd =
3259 (struct i40e_aqc_macvlan *)&desc.params.raw;
3260 enum i40e_status_code status;
3263 if (count == 0 || !v_list || !hw)
3264 return I40E_ERR_PARAM;
3266 buf_size = count * sizeof(*v_list);
3268 /* prep the rest of the request */
3269 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3270 cmd->num_addresses = CPU_TO_LE16(count);
3271 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3275 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3276 if (buf_size > I40E_AQ_LARGE_BUF)
3277 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3279 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3286 * i40e_aq_send_msg_to_vf
3287 * @hw: pointer to the hardware structure
3288 * @vfid: vf id to send msg
3289 * @v_opcode: opcodes for VF-PF communication
3290 * @v_retval: return error code
3291 * @msg: pointer to the msg buffer
3292 * @msglen: msg length
3293 * @cmd_details: pointer to command details
3297 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3298 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3299 struct i40e_asq_cmd_details *cmd_details)
3301 struct i40e_aq_desc desc;
3302 struct i40e_aqc_pf_vf_message *cmd =
3303 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3304 enum i40e_status_code status;
3306 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3307 cmd->id = CPU_TO_LE32(vfid);
3308 desc.cookie_high = CPU_TO_LE32(v_opcode);
3309 desc.cookie_low = CPU_TO_LE32(v_retval);
3310 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3312 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3314 if (msglen > I40E_AQ_LARGE_BUF)
3315 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3316 desc.datalen = CPU_TO_LE16(msglen);
3318 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3324 * i40e_aq_debug_read_register
3325 * @hw: pointer to the hw struct
3326 * @reg_addr: register address
3327 * @reg_val: register value
3328 * @cmd_details: pointer to command details structure or NULL
3330 * Read the register using the admin queue commands
3332 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3333 u32 reg_addr, u64 *reg_val,
3334 struct i40e_asq_cmd_details *cmd_details)
3336 struct i40e_aq_desc desc;
3337 struct i40e_aqc_debug_reg_read_write *cmd_resp =
3338 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3339 enum i40e_status_code status;
3341 if (reg_val == NULL)
3342 return I40E_ERR_PARAM;
3344 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3346 cmd_resp->address = CPU_TO_LE32(reg_addr);
3348 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3350 if (status == I40E_SUCCESS) {
3351 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3352 (u64)LE32_TO_CPU(cmd_resp->value_low);
3359 * i40e_aq_debug_write_register
3360 * @hw: pointer to the hw struct
3361 * @reg_addr: register address
3362 * @reg_val: register value
3363 * @cmd_details: pointer to command details structure or NULL
3365 * Write to a register using the admin queue commands
3367 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3368 u32 reg_addr, u64 reg_val,
3369 struct i40e_asq_cmd_details *cmd_details)
3371 struct i40e_aq_desc desc;
3372 struct i40e_aqc_debug_reg_read_write *cmd =
3373 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3374 enum i40e_status_code status;
3376 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3378 cmd->address = CPU_TO_LE32(reg_addr);
3379 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3380 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3382 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3388 * i40e_aq_request_resource
3389 * @hw: pointer to the hw struct
3390 * @resource: resource id
3391 * @access: access type
3392 * @sdp_number: resource number
3393 * @timeout: the maximum time in ms that the driver may hold the resource
3394 * @cmd_details: pointer to command details structure or NULL
3396 * requests common resource using the admin queue commands
3398 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3399 enum i40e_aq_resources_ids resource,
3400 enum i40e_aq_resource_access_type access,
3401 u8 sdp_number, u64 *timeout,
3402 struct i40e_asq_cmd_details *cmd_details)
3404 struct i40e_aq_desc desc;
3405 struct i40e_aqc_request_resource *cmd_resp =
3406 (struct i40e_aqc_request_resource *)&desc.params.raw;
3407 enum i40e_status_code status;
3409 DEBUGFUNC("i40e_aq_request_resource");
3411 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3413 cmd_resp->resource_id = CPU_TO_LE16(resource);
3414 cmd_resp->access_type = CPU_TO_LE16(access);
3415 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3417 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3418 /* The completion specifies the maximum time in ms that the driver
3419 * may hold the resource in the Timeout field.
3420 * If the resource is held by someone else, the command completes with
3421 * busy return value and the timeout field indicates the maximum time
3422 * the current owner of the resource has to free it.
3424 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3425 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3431 * i40e_aq_release_resource
3432 * @hw: pointer to the hw struct
3433 * @resource: resource id
3434 * @sdp_number: resource number
3435 * @cmd_details: pointer to command details structure or NULL
3437 * release common resource using the admin queue commands
3439 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3440 enum i40e_aq_resources_ids resource,
3442 struct i40e_asq_cmd_details *cmd_details)
3444 struct i40e_aq_desc desc;
3445 struct i40e_aqc_request_resource *cmd =
3446 (struct i40e_aqc_request_resource *)&desc.params.raw;
3447 enum i40e_status_code status;
3449 DEBUGFUNC("i40e_aq_release_resource");
3451 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3453 cmd->resource_id = CPU_TO_LE16(resource);
3454 cmd->resource_number = CPU_TO_LE32(sdp_number);
3456 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3463 * @hw: pointer to the hw struct
3464 * @module_pointer: module pointer location in words from the NVM beginning
3465 * @offset: byte offset from the module beginning
3466 * @length: length of the section to be read (in bytes from the offset)
3467 * @data: command buffer (size [bytes] = length)
3468 * @last_command: tells if this is the last command in a series
3469 * @cmd_details: pointer to command details structure or NULL
3471 * Read the NVM using the admin queue commands
3473 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3474 u32 offset, u16 length, void *data,
3476 struct i40e_asq_cmd_details *cmd_details)
3478 struct i40e_aq_desc desc;
3479 struct i40e_aqc_nvm_update *cmd =
3480 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3481 enum i40e_status_code status;
3483 DEBUGFUNC("i40e_aq_read_nvm");
3485 /* In offset the highest byte must be zeroed. */
3486 if (offset & 0xFF000000) {
3487 status = I40E_ERR_PARAM;
3488 goto i40e_aq_read_nvm_exit;
3491 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3493 /* If this is the last command in a series, set the proper flag. */
3495 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3496 cmd->module_pointer = module_pointer;
3497 cmd->offset = CPU_TO_LE32(offset);
3498 cmd->length = CPU_TO_LE16(length);
3500 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3501 if (length > I40E_AQ_LARGE_BUF)
3502 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3504 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3506 i40e_aq_read_nvm_exit:
3511 * i40e_aq_read_nvm_config - read an nvm config block
3512 * @hw: pointer to the hw struct
3513 * @cmd_flags: NVM access admin command bits
3514 * @field_id: field or feature id
3515 * @data: buffer for result
3516 * @buf_size: buffer size
3517 * @element_count: pointer to count of elements read by FW
3518 * @cmd_details: pointer to command details structure or NULL
3520 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3521 u8 cmd_flags, u32 field_id, void *data,
3522 u16 buf_size, u16 *element_count,
3523 struct i40e_asq_cmd_details *cmd_details)
3525 struct i40e_aq_desc desc;
3526 struct i40e_aqc_nvm_config_read *cmd =
3527 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3528 enum i40e_status_code status;
3530 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3531 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3532 if (buf_size > I40E_AQ_LARGE_BUF)
3533 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3535 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3536 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3537 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3538 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3540 cmd->element_id_msw = 0;
3542 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3544 if (!status && element_count)
3545 *element_count = LE16_TO_CPU(cmd->element_count);
3551 * i40e_aq_write_nvm_config - write an nvm config block
3552 * @hw: pointer to the hw struct
3553 * @cmd_flags: NVM access admin command bits
3554 * @data: buffer for result
3555 * @buf_size: buffer size
3556 * @element_count: count of elements to be written
3557 * @cmd_details: pointer to command details structure or NULL
3559 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3560 u8 cmd_flags, void *data, u16 buf_size,
3562 struct i40e_asq_cmd_details *cmd_details)
3564 struct i40e_aq_desc desc;
3565 struct i40e_aqc_nvm_config_write *cmd =
3566 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3567 enum i40e_status_code status;
3569 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3570 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3571 if (buf_size > I40E_AQ_LARGE_BUF)
3572 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3574 cmd->element_count = CPU_TO_LE16(element_count);
3575 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3576 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3582 * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3583 * @hw: pointer to the hw struct
3584 * @cmd_details: pointer to command details structure or NULL
3586 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3587 void *buff, u16 buff_size,
3588 struct i40e_asq_cmd_details *cmd_details)
3590 struct i40e_aq_desc desc;
3591 enum i40e_status_code status;
3593 UNREFERENCED_2PARAMETER(buff, buff_size);
3595 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3596 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3597 if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3598 status = I40E_ERR_NOT_IMPLEMENTED;
3605 * @hw: pointer to the hw struct
3606 * @module_pointer: module pointer location in words from the NVM beginning
3607 * @offset: offset in the module (expressed in 4 KB from module's beginning)
3608 * @length: length of the section to be erased (expressed in 4 KB)
3609 * @last_command: tells if this is the last command in a series
3610 * @cmd_details: pointer to command details structure or NULL
3612 * Erase the NVM sector using the admin queue commands
3614 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3615 u32 offset, u16 length, bool last_command,
3616 struct i40e_asq_cmd_details *cmd_details)
3618 struct i40e_aq_desc desc;
3619 struct i40e_aqc_nvm_update *cmd =
3620 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3621 enum i40e_status_code status;
3623 DEBUGFUNC("i40e_aq_erase_nvm");
3625 /* In offset the highest byte must be zeroed. */
3626 if (offset & 0xFF000000) {
3627 status = I40E_ERR_PARAM;
3628 goto i40e_aq_erase_nvm_exit;
3631 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3633 /* If this is the last command in a series, set the proper flag. */
3635 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3636 cmd->module_pointer = module_pointer;
3637 cmd->offset = CPU_TO_LE32(offset);
3638 cmd->length = CPU_TO_LE16(length);
3640 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3642 i40e_aq_erase_nvm_exit:
3647 * i40e_parse_discover_capabilities
3648 * @hw: pointer to the hw struct
3649 * @buff: pointer to a buffer containing device/function capability records
3650 * @cap_count: number of capability records in the list
3651 * @list_type_opc: type of capabilities list to parse
3653 * Parse the device/function capabilities list.
3655 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3657 enum i40e_admin_queue_opc list_type_opc)
3659 struct i40e_aqc_list_capabilities_element_resp *cap;
3660 u32 valid_functions, num_functions;
3661 u32 number, logical_id, phys_id;
3662 struct i40e_hw_capabilities *p;
3667 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3669 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3670 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3671 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3672 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3676 for (i = 0; i < cap_count; i++, cap++) {
3677 id = LE16_TO_CPU(cap->id);
3678 number = LE32_TO_CPU(cap->number);
3679 logical_id = LE32_TO_CPU(cap->logical_id);
3680 phys_id = LE32_TO_CPU(cap->phys_id);
3681 major_rev = cap->major_rev;
3684 case I40E_AQ_CAP_ID_SWITCH_MODE:
3685 p->switch_mode = number;
3686 i40e_debug(hw, I40E_DEBUG_INIT,
3687 "HW Capability: Switch mode = %d\n",
3690 case I40E_AQ_CAP_ID_MNG_MODE:
3691 p->management_mode = number;
3692 if (major_rev > 1) {
3693 p->mng_protocols_over_mctp = logical_id;
3694 i40e_debug(hw, I40E_DEBUG_INIT,
3695 "HW Capability: Protocols over MCTP = %d\n",
3696 p->mng_protocols_over_mctp);
3698 p->mng_protocols_over_mctp = 0;
3700 i40e_debug(hw, I40E_DEBUG_INIT,
3701 "HW Capability: Management Mode = %d\n",
3702 p->management_mode);
3704 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3705 p->npar_enable = number;
3706 i40e_debug(hw, I40E_DEBUG_INIT,
3707 "HW Capability: NPAR enable = %d\n",
3710 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3712 i40e_debug(hw, I40E_DEBUG_INIT,
3713 "HW Capability: OS2BMC = %d\n", p->os2bmc);
3715 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3716 p->valid_functions = number;
3717 i40e_debug(hw, I40E_DEBUG_INIT,
3718 "HW Capability: Valid Functions = %d\n",
3719 p->valid_functions);
3721 case I40E_AQ_CAP_ID_SRIOV:
3723 p->sr_iov_1_1 = true;
3724 i40e_debug(hw, I40E_DEBUG_INIT,
3725 "HW Capability: SR-IOV = %d\n",
3728 case I40E_AQ_CAP_ID_VF:
3729 p->num_vfs = number;
3730 p->vf_base_id = logical_id;
3731 i40e_debug(hw, I40E_DEBUG_INIT,
3732 "HW Capability: VF count = %d\n",
3734 i40e_debug(hw, I40E_DEBUG_INIT,
3735 "HW Capability: VF base_id = %d\n",
3738 case I40E_AQ_CAP_ID_VMDQ:
3741 i40e_debug(hw, I40E_DEBUG_INIT,
3742 "HW Capability: VMDQ = %d\n", p->vmdq);
3744 case I40E_AQ_CAP_ID_8021QBG:
3746 p->evb_802_1_qbg = true;
3747 i40e_debug(hw, I40E_DEBUG_INIT,
3748 "HW Capability: 802.1Qbg = %d\n", number);
3750 case I40E_AQ_CAP_ID_8021QBR:
3752 p->evb_802_1_qbh = true;
3753 i40e_debug(hw, I40E_DEBUG_INIT,
3754 "HW Capability: 802.1Qbh = %d\n", number);
3756 case I40E_AQ_CAP_ID_VSI:
3757 p->num_vsis = number;
3758 i40e_debug(hw, I40E_DEBUG_INIT,
3759 "HW Capability: VSI count = %d\n",
3762 case I40E_AQ_CAP_ID_DCB:
3765 p->enabled_tcmap = logical_id;
3768 i40e_debug(hw, I40E_DEBUG_INIT,
3769 "HW Capability: DCB = %d\n", p->dcb);
3770 i40e_debug(hw, I40E_DEBUG_INIT,
3771 "HW Capability: TC Mapping = %d\n",
3773 i40e_debug(hw, I40E_DEBUG_INIT,
3774 "HW Capability: TC Max = %d\n", p->maxtc);
3776 case I40E_AQ_CAP_ID_FCOE:
3779 i40e_debug(hw, I40E_DEBUG_INIT,
3780 "HW Capability: FCOE = %d\n", p->fcoe);
3782 case I40E_AQ_CAP_ID_ISCSI:
3785 i40e_debug(hw, I40E_DEBUG_INIT,
3786 "HW Capability: iSCSI = %d\n", p->iscsi);
3788 case I40E_AQ_CAP_ID_RSS:
3790 p->rss_table_size = number;
3791 p->rss_table_entry_width = logical_id;
3792 i40e_debug(hw, I40E_DEBUG_INIT,
3793 "HW Capability: RSS = %d\n", p->rss);
3794 i40e_debug(hw, I40E_DEBUG_INIT,
3795 "HW Capability: RSS table size = %d\n",
3797 i40e_debug(hw, I40E_DEBUG_INIT,
3798 "HW Capability: RSS table width = %d\n",
3799 p->rss_table_entry_width);
3801 case I40E_AQ_CAP_ID_RXQ:
3802 p->num_rx_qp = number;
3803 p->base_queue = phys_id;
3804 i40e_debug(hw, I40E_DEBUG_INIT,
3805 "HW Capability: Rx QP = %d\n", number);
3806 i40e_debug(hw, I40E_DEBUG_INIT,
3807 "HW Capability: base_queue = %d\n",
3810 case I40E_AQ_CAP_ID_TXQ:
3811 p->num_tx_qp = number;
3812 p->base_queue = phys_id;
3813 i40e_debug(hw, I40E_DEBUG_INIT,
3814 "HW Capability: Tx QP = %d\n", number);
3815 i40e_debug(hw, I40E_DEBUG_INIT,
3816 "HW Capability: base_queue = %d\n",
3819 case I40E_AQ_CAP_ID_MSIX:
3820 p->num_msix_vectors = number;
3821 i40e_debug(hw, I40E_DEBUG_INIT,
3822 "HW Capability: MSIX vector count = %d\n",
3823 p->num_msix_vectors);
3825 case I40E_AQ_CAP_ID_VF_MSIX:
3826 p->num_msix_vectors_vf = number;
3827 i40e_debug(hw, I40E_DEBUG_INIT,
3828 "HW Capability: MSIX VF vector count = %d\n",
3829 p->num_msix_vectors_vf);
3831 case I40E_AQ_CAP_ID_FLEX10:
3832 if (major_rev == 1) {
3834 p->flex10_enable = true;
3835 p->flex10_capable = true;
3838 /* Capability revision >= 2 */
3840 p->flex10_enable = true;
3842 p->flex10_capable = true;
3844 p->flex10_mode = logical_id;
3845 p->flex10_status = phys_id;
3846 i40e_debug(hw, I40E_DEBUG_INIT,
3847 "HW Capability: Flex10 mode = %d\n",
3849 i40e_debug(hw, I40E_DEBUG_INIT,
3850 "HW Capability: Flex10 status = %d\n",
3853 case I40E_AQ_CAP_ID_CEM:
3856 i40e_debug(hw, I40E_DEBUG_INIT,
3857 "HW Capability: CEM = %d\n", p->mgmt_cem);
3859 case I40E_AQ_CAP_ID_IWARP:
3862 i40e_debug(hw, I40E_DEBUG_INIT,
3863 "HW Capability: iWARP = %d\n", p->iwarp);
3865 case I40E_AQ_CAP_ID_LED:
3866 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3867 p->led[phys_id] = true;
3868 i40e_debug(hw, I40E_DEBUG_INIT,
3869 "HW Capability: LED - PIN %d\n", phys_id);
3871 case I40E_AQ_CAP_ID_SDP:
3872 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3873 p->sdp[phys_id] = true;
3874 i40e_debug(hw, I40E_DEBUG_INIT,
3875 "HW Capability: SDP - PIN %d\n", phys_id);
3877 case I40E_AQ_CAP_ID_MDIO:
3879 p->mdio_port_num = phys_id;
3880 p->mdio_port_mode = logical_id;
3882 i40e_debug(hw, I40E_DEBUG_INIT,
3883 "HW Capability: MDIO port number = %d\n",
3885 i40e_debug(hw, I40E_DEBUG_INIT,
3886 "HW Capability: MDIO port mode = %d\n",
3889 case I40E_AQ_CAP_ID_1588:
3891 p->ieee_1588 = true;
3892 i40e_debug(hw, I40E_DEBUG_INIT,
3893 "HW Capability: IEEE 1588 = %d\n",
3896 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3898 p->fd_filters_guaranteed = number;
3899 p->fd_filters_best_effort = logical_id;
3900 i40e_debug(hw, I40E_DEBUG_INIT,
3901 "HW Capability: Flow Director = 1\n");
3902 i40e_debug(hw, I40E_DEBUG_INIT,
3903 "HW Capability: Guaranteed FD filters = %d\n",
3904 p->fd_filters_guaranteed);
3906 case I40E_AQ_CAP_ID_WSR_PROT:
3907 p->wr_csr_prot = (u64)number;
3908 p->wr_csr_prot |= (u64)logical_id << 32;
3909 i40e_debug(hw, I40E_DEBUG_INIT,
3910 "HW Capability: wr_csr_prot = 0x%llX\n\n",
3911 (p->wr_csr_prot & 0xffff));
3913 case I40E_AQ_CAP_ID_NVM_MGMT:
3914 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3915 p->sec_rev_disabled = true;
3916 if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3917 p->update_disabled = true;
3920 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3921 hw->num_wol_proxy_filters = (u16)number;
3922 hw->wol_proxy_vsi_seid = (u16)logical_id;
3923 p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3924 if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3925 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3927 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3928 p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3929 i40e_debug(hw, I40E_DEBUG_INIT,
3930 "HW Capability: WOL proxy filters = %d\n",
3931 hw->num_wol_proxy_filters);
3940 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3942 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3945 /* count the enabled ports (aka the "not disabled" ports) */
3947 for (i = 0; i < 4; i++) {
3948 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3951 /* use AQ read to get the physical register offset instead
3952 * of the port relative offset
3954 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3955 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3959 valid_functions = p->valid_functions;
3961 while (valid_functions) {
3962 if (valid_functions & 1)
3964 valid_functions >>= 1;
3967 /* partition id is 1-based, and functions are evenly spread
3968 * across the ports as partitions
3970 if (hw->num_ports != 0) {
3971 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3972 hw->num_partitions = num_functions / hw->num_ports;
3975 /* additional HW specific goodies that might
3976 * someday be HW version specific
3978 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3982 * i40e_aq_discover_capabilities
3983 * @hw: pointer to the hw struct
3984 * @buff: a virtual buffer to hold the capabilities
3985 * @buff_size: Size of the virtual buffer
3986 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3987 * @list_type_opc: capabilities type to discover - pass in the command opcode
3988 * @cmd_details: pointer to command details structure or NULL
3990 * Get the device capabilities descriptions from the firmware
3992 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3993 void *buff, u16 buff_size, u16 *data_size,
3994 enum i40e_admin_queue_opc list_type_opc,
3995 struct i40e_asq_cmd_details *cmd_details)
3997 struct i40e_aqc_list_capabilites *cmd;
3998 struct i40e_aq_desc desc;
3999 enum i40e_status_code status = I40E_SUCCESS;
4001 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
4003 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
4004 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
4005 status = I40E_ERR_PARAM;
4009 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
4011 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4012 if (buff_size > I40E_AQ_LARGE_BUF)
4013 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4015 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4016 *data_size = LE16_TO_CPU(desc.datalen);
4021 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
4029 * i40e_aq_update_nvm
4030 * @hw: pointer to the hw struct
4031 * @module_pointer: module pointer location in words from the NVM beginning
4032 * @offset: byte offset from the module beginning
4033 * @length: length of the section to be written (in bytes from the offset)
4034 * @data: command buffer (size [bytes] = length)
4035 * @last_command: tells if this is the last command in a series
4036 * @cmd_details: pointer to command details structure or NULL
4038 * Update the NVM using the admin queue commands
4040 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
4041 u32 offset, u16 length, void *data,
4043 struct i40e_asq_cmd_details *cmd_details)
4045 struct i40e_aq_desc desc;
4046 struct i40e_aqc_nvm_update *cmd =
4047 (struct i40e_aqc_nvm_update *)&desc.params.raw;
4048 enum i40e_status_code status;
4050 DEBUGFUNC("i40e_aq_update_nvm");
4052 /* In offset the highest byte must be zeroed. */
4053 if (offset & 0xFF000000) {
4054 status = I40E_ERR_PARAM;
4055 goto i40e_aq_update_nvm_exit;
4058 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4060 /* If this is the last command in a series, set the proper flag. */
4062 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
4063 cmd->module_pointer = module_pointer;
4064 cmd->offset = CPU_TO_LE32(offset);
4065 cmd->length = CPU_TO_LE16(length);
4067 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4068 if (length > I40E_AQ_LARGE_BUF)
4069 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4071 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
4073 i40e_aq_update_nvm_exit:
4078 * i40e_aq_get_lldp_mib
4079 * @hw: pointer to the hw struct
4080 * @bridge_type: type of bridge requested
4081 * @mib_type: Local, Remote or both Local and Remote MIBs
4082 * @buff: pointer to a user supplied buffer to store the MIB block
4083 * @buff_size: size of the buffer (in bytes)
4084 * @local_len : length of the returned Local LLDP MIB
4085 * @remote_len: length of the returned Remote LLDP MIB
4086 * @cmd_details: pointer to command details structure or NULL
4088 * Requests the complete LLDP MIB (entire packet).
4090 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4091 u8 mib_type, void *buff, u16 buff_size,
4092 u16 *local_len, u16 *remote_len,
4093 struct i40e_asq_cmd_details *cmd_details)
4095 struct i40e_aq_desc desc;
4096 struct i40e_aqc_lldp_get_mib *cmd =
4097 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4098 struct i40e_aqc_lldp_get_mib *resp =
4099 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4100 enum i40e_status_code status;
4102 if (buff_size == 0 || !buff)
4103 return I40E_ERR_PARAM;
4105 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4106 /* Indirect Command */
4107 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4109 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4110 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4111 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4113 desc.datalen = CPU_TO_LE16(buff_size);
4115 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4116 if (buff_size > I40E_AQ_LARGE_BUF)
4117 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4119 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4121 if (local_len != NULL)
4122 *local_len = LE16_TO_CPU(resp->local_len);
4123 if (remote_len != NULL)
4124 *remote_len = LE16_TO_CPU(resp->remote_len);
4131 * i40e_aq_set_lldp_mib - Set the LLDP MIB
4132 * @hw: pointer to the hw struct
4133 * @mib_type: Local, Remote or both Local and Remote MIBs
4134 * @buff: pointer to a user supplied buffer to store the MIB block
4135 * @buff_size: size of the buffer (in bytes)
4136 * @cmd_details: pointer to command details structure or NULL
4140 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4141 u8 mib_type, void *buff, u16 buff_size,
4142 struct i40e_asq_cmd_details *cmd_details)
4144 struct i40e_aq_desc desc;
4145 struct i40e_aqc_lldp_set_local_mib *cmd =
4146 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4147 enum i40e_status_code status;
4149 if (buff_size == 0 || !buff)
4150 return I40E_ERR_PARAM;
4152 i40e_fill_default_direct_cmd_desc(&desc,
4153 i40e_aqc_opc_lldp_set_local_mib);
4154 /* Indirect Command */
4155 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4156 if (buff_size > I40E_AQ_LARGE_BUF)
4157 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4158 desc.datalen = CPU_TO_LE16(buff_size);
4160 cmd->type = mib_type;
4161 cmd->length = CPU_TO_LE16(buff_size);
4162 cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4163 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4165 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4170 * i40e_aq_cfg_lldp_mib_change_event
4171 * @hw: pointer to the hw struct
4172 * @enable_update: Enable or Disable event posting
4173 * @cmd_details: pointer to command details structure or NULL
4175 * Enable or Disable posting of an event on ARQ when LLDP MIB
4176 * associated with the interface changes
4178 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4180 struct i40e_asq_cmd_details *cmd_details)
4182 struct i40e_aq_desc desc;
4183 struct i40e_aqc_lldp_update_mib *cmd =
4184 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4185 enum i40e_status_code status;
4187 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4190 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4192 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4198 * i40e_aq_add_lldp_tlv
4199 * @hw: pointer to the hw struct
4200 * @bridge_type: type of bridge
4201 * @buff: buffer with TLV to add
4202 * @buff_size: length of the buffer
4203 * @tlv_len: length of the TLV to be added
4204 * @mib_len: length of the LLDP MIB returned in response
4205 * @cmd_details: pointer to command details structure or NULL
4207 * Add the specified TLV to LLDP Local MIB for the given bridge type,
4208 * it is responsibility of the caller to make sure that the TLV is not
4209 * already present in the LLDPDU.
4210 * In return firmware will write the complete LLDP MIB with the newly
4211 * added TLV in the response buffer.
4213 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4214 void *buff, u16 buff_size, u16 tlv_len,
4216 struct i40e_asq_cmd_details *cmd_details)
4218 struct i40e_aq_desc desc;
4219 struct i40e_aqc_lldp_add_tlv *cmd =
4220 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4221 enum i40e_status_code status;
4223 if (buff_size == 0 || !buff || tlv_len == 0)
4224 return I40E_ERR_PARAM;
4226 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4228 /* Indirect Command */
4229 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4230 if (buff_size > I40E_AQ_LARGE_BUF)
4231 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4232 desc.datalen = CPU_TO_LE16(buff_size);
4234 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4235 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4236 cmd->len = CPU_TO_LE16(tlv_len);
4238 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4240 if (mib_len != NULL)
4241 *mib_len = LE16_TO_CPU(desc.datalen);
4248 * i40e_aq_update_lldp_tlv
4249 * @hw: pointer to the hw struct
4250 * @bridge_type: type of bridge
4251 * @buff: buffer with TLV to update
4252 * @buff_size: size of the buffer holding original and updated TLVs
4253 * @old_len: Length of the Original TLV
4254 * @new_len: Length of the Updated TLV
4255 * @offset: offset of the updated TLV in the buff
4256 * @mib_len: length of the returned LLDP MIB
4257 * @cmd_details: pointer to command details structure or NULL
4259 * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4260 * Firmware will place the complete LLDP MIB in response buffer with the
4263 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4264 u8 bridge_type, void *buff, u16 buff_size,
4265 u16 old_len, u16 new_len, u16 offset,
4267 struct i40e_asq_cmd_details *cmd_details)
4269 struct i40e_aq_desc desc;
4270 struct i40e_aqc_lldp_update_tlv *cmd =
4271 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4272 enum i40e_status_code status;
4274 if (buff_size == 0 || !buff || offset == 0 ||
4275 old_len == 0 || new_len == 0)
4276 return I40E_ERR_PARAM;
4278 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4280 /* Indirect Command */
4281 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4282 if (buff_size > I40E_AQ_LARGE_BUF)
4283 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4284 desc.datalen = CPU_TO_LE16(buff_size);
4286 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4287 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4288 cmd->old_len = CPU_TO_LE16(old_len);
4289 cmd->new_offset = CPU_TO_LE16(offset);
4290 cmd->new_len = CPU_TO_LE16(new_len);
4292 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4294 if (mib_len != NULL)
4295 *mib_len = LE16_TO_CPU(desc.datalen);
4302 * i40e_aq_delete_lldp_tlv
4303 * @hw: pointer to the hw struct
4304 * @bridge_type: type of bridge
4305 * @buff: pointer to a user supplied buffer that has the TLV
4306 * @buff_size: length of the buffer
4307 * @tlv_len: length of the TLV to be deleted
4308 * @mib_len: length of the returned LLDP MIB
4309 * @cmd_details: pointer to command details structure or NULL
4311 * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4312 * The firmware places the entire LLDP MIB in the response buffer.
4314 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4315 u8 bridge_type, void *buff, u16 buff_size,
4316 u16 tlv_len, u16 *mib_len,
4317 struct i40e_asq_cmd_details *cmd_details)
4319 struct i40e_aq_desc desc;
4320 struct i40e_aqc_lldp_add_tlv *cmd =
4321 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4322 enum i40e_status_code status;
4324 if (buff_size == 0 || !buff)
4325 return I40E_ERR_PARAM;
4327 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4329 /* Indirect Command */
4330 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4331 if (buff_size > I40E_AQ_LARGE_BUF)
4332 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4333 desc.datalen = CPU_TO_LE16(buff_size);
4334 cmd->len = CPU_TO_LE16(tlv_len);
4335 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4336 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4338 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4340 if (mib_len != NULL)
4341 *mib_len = LE16_TO_CPU(desc.datalen);
4349 * @hw: pointer to the hw struct
4350 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4351 * @cmd_details: pointer to command details structure or NULL
4353 * Stop or Shutdown the embedded LLDP Agent
4355 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4356 struct i40e_asq_cmd_details *cmd_details)
4358 struct i40e_aq_desc desc;
4359 struct i40e_aqc_lldp_stop *cmd =
4360 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4361 enum i40e_status_code status;
4363 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4366 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4368 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4374 * i40e_aq_start_lldp
4375 * @hw: pointer to the hw struct
4376 * @cmd_details: pointer to command details structure or NULL
4378 * Start the embedded LLDP Agent on all ports.
4380 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4381 struct i40e_asq_cmd_details *cmd_details)
4383 struct i40e_aq_desc desc;
4384 struct i40e_aqc_lldp_start *cmd =
4385 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4386 enum i40e_status_code status;
4388 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4390 cmd->command = I40E_AQ_LLDP_AGENT_START;
4392 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4398 * i40e_aq_get_cee_dcb_config
4399 * @hw: pointer to the hw struct
4400 * @buff: response buffer that stores CEE operational configuration
4401 * @buff_size: size of the buffer passed
4402 * @cmd_details: pointer to command details structure or NULL
4404 * Get CEE DCBX mode operational configuration from firmware
4406 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4407 void *buff, u16 buff_size,
4408 struct i40e_asq_cmd_details *cmd_details)
4410 struct i40e_aq_desc desc;
4411 enum i40e_status_code status;
4413 if (buff_size == 0 || !buff)
4414 return I40E_ERR_PARAM;
4416 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4418 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4419 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4426 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4427 * @hw: pointer to the hw struct
4428 * @start_agent: True if DCBx Agent needs to be Started
4429 * False if DCBx Agent needs to be Stopped
4430 * @cmd_details: pointer to command details structure or NULL
4432 * Start/Stop the embedded dcbx Agent
4434 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4436 struct i40e_asq_cmd_details *cmd_details)
4438 struct i40e_aq_desc desc;
4439 struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4440 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4442 enum i40e_status_code status;
4444 i40e_fill_default_direct_cmd_desc(&desc,
4445 i40e_aqc_opc_lldp_stop_start_spec_agent);
4448 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4450 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4456 * i40e_aq_add_udp_tunnel
4457 * @hw: pointer to the hw struct
4458 * @udp_port: the UDP port to add in Host byte order
4459 * @header_len: length of the tunneling header length in DWords
4460 * @protocol_index: protocol index type
4461 * @filter_index: pointer to filter index
4462 * @cmd_details: pointer to command details structure or NULL
4464 * Note: Firmware expects the udp_port value to be in Little Endian format,
4465 * and this function will call CPU_TO_LE16 to convert from Host byte order to
4466 * Little Endian order.
4468 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4469 u16 udp_port, u8 protocol_index,
4471 struct i40e_asq_cmd_details *cmd_details)
4473 struct i40e_aq_desc desc;
4474 struct i40e_aqc_add_udp_tunnel *cmd =
4475 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4476 struct i40e_aqc_del_udp_tunnel_completion *resp =
4477 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4478 enum i40e_status_code status;
4480 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4482 cmd->udp_port = CPU_TO_LE16(udp_port);
4483 cmd->protocol_type = protocol_index;
4485 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4487 if (!status && filter_index)
4488 *filter_index = resp->index;
4494 * i40e_aq_del_udp_tunnel
4495 * @hw: pointer to the hw struct
4496 * @index: filter index
4497 * @cmd_details: pointer to command details structure or NULL
4499 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4500 struct i40e_asq_cmd_details *cmd_details)
4502 struct i40e_aq_desc desc;
4503 struct i40e_aqc_remove_udp_tunnel *cmd =
4504 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4505 enum i40e_status_code status;
4507 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4511 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4517 * i40e_aq_get_switch_resource_alloc (0x0204)
4518 * @hw: pointer to the hw struct
4519 * @num_entries: pointer to u8 to store the number of resource entries returned
4520 * @buf: pointer to a user supplied buffer. This buffer must be large enough
4521 * to store the resource information for all resource types. Each
4522 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
4523 * @count: size, in bytes, of the buffer provided
4524 * @cmd_details: pointer to command details structure or NULL
4526 * Query the resources allocated to a function.
4528 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4530 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4532 struct i40e_asq_cmd_details *cmd_details)
4534 struct i40e_aq_desc desc;
4535 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4536 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4537 enum i40e_status_code status;
4538 u16 length = count * sizeof(*buf);
4540 i40e_fill_default_direct_cmd_desc(&desc,
4541 i40e_aqc_opc_get_switch_resource_alloc);
4543 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4544 if (length > I40E_AQ_LARGE_BUF)
4545 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4547 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4549 if (!status && num_entries)
4550 *num_entries = cmd_resp->num_entries;
4556 * i40e_aq_delete_element - Delete switch element
4557 * @hw: pointer to the hw struct
4558 * @seid: the SEID to delete from the switch
4559 * @cmd_details: pointer to command details structure or NULL
4561 * This deletes a switch element from the switch.
4563 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4564 struct i40e_asq_cmd_details *cmd_details)
4566 struct i40e_aq_desc desc;
4567 struct i40e_aqc_switch_seid *cmd =
4568 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4569 enum i40e_status_code status;
4572 return I40E_ERR_PARAM;
4574 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4576 cmd->seid = CPU_TO_LE16(seid);
4578 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4584 * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4585 * @hw: pointer to the hw struct
4586 * @flags: component flags
4587 * @mac_seid: uplink seid (MAC SEID)
4588 * @vsi_seid: connected vsi seid
4589 * @ret_seid: seid of create pv component
4591 * This instantiates an i40e port virtualizer with specified flags.
4592 * Depending on specified flags the port virtualizer can act as a
4593 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4595 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4596 u16 mac_seid, u16 vsi_seid,
4599 struct i40e_aq_desc desc;
4600 struct i40e_aqc_add_update_pv *cmd =
4601 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4602 struct i40e_aqc_add_update_pv_completion *resp =
4603 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4604 enum i40e_status_code status;
4607 return I40E_ERR_PARAM;
4609 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4610 cmd->command_flags = CPU_TO_LE16(flags);
4611 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4612 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4614 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4615 if (!status && ret_seid)
4616 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4622 * i40e_aq_add_tag - Add an S/E-tag
4623 * @hw: pointer to the hw struct
4624 * @direct_to_queue: should s-tag direct flow to a specific queue
4625 * @vsi_seid: VSI SEID to use this tag
4626 * @tag: value of the tag
4627 * @queue_num: queue number, only valid is direct_to_queue is true
4628 * @tags_used: return value, number of tags in use by this PF
4629 * @tags_free: return value, number of unallocated tags
4630 * @cmd_details: pointer to command details structure or NULL
4632 * This associates an S- or E-tag to a VSI in the switch complex. It returns
4633 * the number of tags allocated by the PF, and the number of unallocated
4636 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4637 u16 vsi_seid, u16 tag, u16 queue_num,
4638 u16 *tags_used, u16 *tags_free,
4639 struct i40e_asq_cmd_details *cmd_details)
4641 struct i40e_aq_desc desc;
4642 struct i40e_aqc_add_tag *cmd =
4643 (struct i40e_aqc_add_tag *)&desc.params.raw;
4644 struct i40e_aqc_add_remove_tag_completion *resp =
4645 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4646 enum i40e_status_code status;
4649 return I40E_ERR_PARAM;
4651 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4653 cmd->seid = CPU_TO_LE16(vsi_seid);
4654 cmd->tag = CPU_TO_LE16(tag);
4655 if (direct_to_queue) {
4656 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4657 cmd->queue_number = CPU_TO_LE16(queue_num);
4660 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4663 if (tags_used != NULL)
4664 *tags_used = LE16_TO_CPU(resp->tags_used);
4665 if (tags_free != NULL)
4666 *tags_free = LE16_TO_CPU(resp->tags_free);
4673 * i40e_aq_remove_tag - Remove an S- or E-tag
4674 * @hw: pointer to the hw struct
4675 * @vsi_seid: VSI SEID this tag is associated with
4676 * @tag: value of the S-tag to delete
4677 * @tags_used: return value, number of tags in use by this PF
4678 * @tags_free: return value, number of unallocated tags
4679 * @cmd_details: pointer to command details structure or NULL
4681 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
4682 * the number of tags allocated by the PF, and the number of unallocated
4685 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4686 u16 tag, u16 *tags_used, u16 *tags_free,
4687 struct i40e_asq_cmd_details *cmd_details)
4689 struct i40e_aq_desc desc;
4690 struct i40e_aqc_remove_tag *cmd =
4691 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4692 struct i40e_aqc_add_remove_tag_completion *resp =
4693 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4694 enum i40e_status_code status;
4697 return I40E_ERR_PARAM;
4699 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4701 cmd->seid = CPU_TO_LE16(vsi_seid);
4702 cmd->tag = CPU_TO_LE16(tag);
4704 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4707 if (tags_used != NULL)
4708 *tags_used = LE16_TO_CPU(resp->tags_used);
4709 if (tags_free != NULL)
4710 *tags_free = LE16_TO_CPU(resp->tags_free);
4717 * i40e_aq_add_mcast_etag - Add a multicast E-tag
4718 * @hw: pointer to the hw struct
4719 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4720 * @etag: value of E-tag to add
4721 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4722 * @buf: address of indirect buffer
4723 * @tags_used: return value, number of E-tags in use by this port
4724 * @tags_free: return value, number of unallocated M-tags
4725 * @cmd_details: pointer to command details structure or NULL
4727 * This associates a multicast E-tag to a port virtualizer. It will return
4728 * the number of tags allocated by the PF, and the number of unallocated
4731 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4732 * num_tags_in_buf long.
4734 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4735 u16 etag, u8 num_tags_in_buf, void *buf,
4736 u16 *tags_used, u16 *tags_free,
4737 struct i40e_asq_cmd_details *cmd_details)
4739 struct i40e_aq_desc desc;
4740 struct i40e_aqc_add_remove_mcast_etag *cmd =
4741 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4742 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4743 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4744 enum i40e_status_code status;
4745 u16 length = sizeof(u16) * num_tags_in_buf;
4747 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4748 return I40E_ERR_PARAM;
4750 i40e_fill_default_direct_cmd_desc(&desc,
4751 i40e_aqc_opc_add_multicast_etag);
4753 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4754 cmd->etag = CPU_TO_LE16(etag);
4755 cmd->num_unicast_etags = num_tags_in_buf;
4757 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4758 if (length > I40E_AQ_LARGE_BUF)
4759 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4761 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4764 if (tags_used != NULL)
4765 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4766 if (tags_free != NULL)
4767 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4774 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4775 * @hw: pointer to the hw struct
4776 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4777 * @etag: value of the E-tag to remove
4778 * @tags_used: return value, number of tags in use by this port
4779 * @tags_free: return value, number of unallocated tags
4780 * @cmd_details: pointer to command details structure or NULL
4782 * This deletes an E-tag from the port virtualizer. It will return
4783 * the number of tags allocated by the port, and the number of unallocated
4786 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4787 u16 etag, u16 *tags_used, u16 *tags_free,
4788 struct i40e_asq_cmd_details *cmd_details)
4790 struct i40e_aq_desc desc;
4791 struct i40e_aqc_add_remove_mcast_etag *cmd =
4792 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4793 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4794 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4795 enum i40e_status_code status;
4799 return I40E_ERR_PARAM;
4801 i40e_fill_default_direct_cmd_desc(&desc,
4802 i40e_aqc_opc_remove_multicast_etag);
4804 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4805 cmd->etag = CPU_TO_LE16(etag);
4807 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4810 if (tags_used != NULL)
4811 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4812 if (tags_free != NULL)
4813 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4820 * i40e_aq_update_tag - Update an S/E-tag
4821 * @hw: pointer to the hw struct
4822 * @vsi_seid: VSI SEID using this S-tag
4823 * @old_tag: old tag value
4824 * @new_tag: new tag value
4825 * @tags_used: return value, number of tags in use by this PF
4826 * @tags_free: return value, number of unallocated tags
4827 * @cmd_details: pointer to command details structure or NULL
4829 * This updates the value of the tag currently attached to this VSI
4830 * in the switch complex. It will return the number of tags allocated
4831 * by the PF, and the number of unallocated tags available.
4833 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4834 u16 old_tag, u16 new_tag, u16 *tags_used,
4836 struct i40e_asq_cmd_details *cmd_details)
4838 struct i40e_aq_desc desc;
4839 struct i40e_aqc_update_tag *cmd =
4840 (struct i40e_aqc_update_tag *)&desc.params.raw;
4841 struct i40e_aqc_update_tag_completion *resp =
4842 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4843 enum i40e_status_code status;
4846 return I40E_ERR_PARAM;
4848 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4850 cmd->seid = CPU_TO_LE16(vsi_seid);
4851 cmd->old_tag = CPU_TO_LE16(old_tag);
4852 cmd->new_tag = CPU_TO_LE16(new_tag);
4854 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4857 if (tags_used != NULL)
4858 *tags_used = LE16_TO_CPU(resp->tags_used);
4859 if (tags_free != NULL)
4860 *tags_free = LE16_TO_CPU(resp->tags_free);
4867 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4868 * @hw: pointer to the hw struct
4869 * @tcmap: TC map for request/release any ignore PFC condition
4870 * @request: request or release ignore PFC condition
4871 * @tcmap_ret: return TCs for which PFC is currently ignored
4872 * @cmd_details: pointer to command details structure or NULL
4874 * This sends out request/release to ignore PFC condition for a TC.
4875 * It will return the TCs for which PFC is currently ignored.
4877 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4878 bool request, u8 *tcmap_ret,
4879 struct i40e_asq_cmd_details *cmd_details)
4881 struct i40e_aq_desc desc;
4882 struct i40e_aqc_pfc_ignore *cmd_resp =
4883 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4884 enum i40e_status_code status;
4886 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4889 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4891 cmd_resp->tc_bitmap = tcmap;
4893 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4896 if (tcmap_ret != NULL)
4897 *tcmap_ret = cmd_resp->tc_bitmap;
4904 * i40e_aq_dcb_updated - DCB Updated Command
4905 * @hw: pointer to the hw struct
4906 * @cmd_details: pointer to command details structure or NULL
4908 * When LLDP is handled in PF this command is used by the PF
4909 * to notify EMP that a DCB setting is modified.
4910 * When LLDP is handled in EMP this command is used by the PF
4911 * to notify EMP whenever one of the following parameters get
4913 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4914 * - PCIRTT in PRTDCB_GENC.PCIRTT
4915 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4916 * EMP will return when the shared RPB settings have been
4917 * recomputed and modified. The retval field in the descriptor
4918 * will be set to 0 when RPB is modified.
4920 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4921 struct i40e_asq_cmd_details *cmd_details)
4923 struct i40e_aq_desc desc;
4924 enum i40e_status_code status;
4926 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4928 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4934 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4935 * @hw: pointer to the hw struct
4936 * @seid: defines the SEID of the switch for which the stats are requested
4937 * @vlan_id: the VLAN ID for which the statistics are requested
4938 * @stat_index: index of the statistics counters block assigned to this VLAN
4939 * @cmd_details: pointer to command details structure or NULL
4941 * XL710 supports 128 smonVlanStats counters.This command is used to
4942 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4945 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4946 u16 vlan_id, u16 *stat_index,
4947 struct i40e_asq_cmd_details *cmd_details)
4949 struct i40e_aq_desc desc;
4950 struct i40e_aqc_add_remove_statistics *cmd_resp =
4951 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4952 enum i40e_status_code status;
4954 if ((seid == 0) || (stat_index == NULL))
4955 return I40E_ERR_PARAM;
4957 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4959 cmd_resp->seid = CPU_TO_LE16(seid);
4960 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4962 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4964 if (!status && stat_index)
4965 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4971 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4972 * @hw: pointer to the hw struct
4973 * @seid: defines the SEID of the switch for which the stats are requested
4974 * @vlan_id: the VLAN ID for which the statistics are requested
4975 * @stat_index: index of the statistics counters block assigned to this VLAN
4976 * @cmd_details: pointer to command details structure or NULL
4978 * XL710 supports 128 smonVlanStats counters.This command is used to
4979 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4982 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4983 u16 vlan_id, u16 stat_index,
4984 struct i40e_asq_cmd_details *cmd_details)
4986 struct i40e_aq_desc desc;
4987 struct i40e_aqc_add_remove_statistics *cmd =
4988 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4989 enum i40e_status_code status;
4992 return I40E_ERR_PARAM;
4994 i40e_fill_default_direct_cmd_desc(&desc,
4995 i40e_aqc_opc_remove_statistics);
4997 cmd->seid = CPU_TO_LE16(seid);
4998 cmd->vlan = CPU_TO_LE16(vlan_id);
4999 cmd->stat_index = CPU_TO_LE16(stat_index);
5001 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5007 * i40e_aq_set_port_parameters - set physical port parameters.
5008 * @hw: pointer to the hw struct
5009 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
5010 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
5011 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
5012 * @double_vlan: if set double VLAN is enabled
5013 * @cmd_details: pointer to command details structure or NULL
5015 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
5016 u16 bad_frame_vsi, bool save_bad_pac,
5017 bool pad_short_pac, bool double_vlan,
5018 struct i40e_asq_cmd_details *cmd_details)
5020 struct i40e_aqc_set_port_parameters *cmd;
5021 enum i40e_status_code status;
5022 struct i40e_aq_desc desc;
5023 u16 command_flags = 0;
5025 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
5027 i40e_fill_default_direct_cmd_desc(&desc,
5028 i40e_aqc_opc_set_port_parameters);
5030 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
5032 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
5034 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
5036 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
5037 cmd->command_flags = CPU_TO_LE16(command_flags);
5039 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5045 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
5046 * @hw: pointer to the hw struct
5047 * @seid: seid for the physical port/switching component/vsi
5048 * @buff: Indirect buffer to hold data parameters and response
5049 * @buff_size: Indirect buffer size
5050 * @opcode: Tx scheduler AQ command opcode
5051 * @cmd_details: pointer to command details structure or NULL
5053 * Generic command handler for Tx scheduler AQ commands
5055 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
5056 void *buff, u16 buff_size,
5057 enum i40e_admin_queue_opc opcode,
5058 struct i40e_asq_cmd_details *cmd_details)
5060 struct i40e_aq_desc desc;
5061 struct i40e_aqc_tx_sched_ind *cmd =
5062 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
5063 enum i40e_status_code status;
5064 bool cmd_param_flag = false;
5067 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
5068 case i40e_aqc_opc_configure_vsi_tc_bw:
5069 case i40e_aqc_opc_enable_switching_comp_ets:
5070 case i40e_aqc_opc_modify_switching_comp_ets:
5071 case i40e_aqc_opc_disable_switching_comp_ets:
5072 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
5073 case i40e_aqc_opc_configure_switching_comp_bw_config:
5074 cmd_param_flag = true;
5076 case i40e_aqc_opc_query_vsi_bw_config:
5077 case i40e_aqc_opc_query_vsi_ets_sla_config:
5078 case i40e_aqc_opc_query_switching_comp_ets_config:
5079 case i40e_aqc_opc_query_port_ets_config:
5080 case i40e_aqc_opc_query_switching_comp_bw_config:
5081 cmd_param_flag = false;
5084 return I40E_ERR_PARAM;
5087 i40e_fill_default_direct_cmd_desc(&desc, opcode);
5089 /* Indirect command */
5090 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5092 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5093 if (buff_size > I40E_AQ_LARGE_BUF)
5094 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5096 desc.datalen = CPU_TO_LE16(buff_size);
5098 cmd->vsi_seid = CPU_TO_LE16(seid);
5100 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5106 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5107 * @hw: pointer to the hw struct
5109 * @credit: BW limit credits (0 = disabled)
5110 * @max_credit: Max BW limit credits
5111 * @cmd_details: pointer to command details structure or NULL
5113 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5114 u16 seid, u16 credit, u8 max_credit,
5115 struct i40e_asq_cmd_details *cmd_details)
5117 struct i40e_aq_desc desc;
5118 struct i40e_aqc_configure_vsi_bw_limit *cmd =
5119 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5120 enum i40e_status_code status;
5122 i40e_fill_default_direct_cmd_desc(&desc,
5123 i40e_aqc_opc_configure_vsi_bw_limit);
5125 cmd->vsi_seid = CPU_TO_LE16(seid);
5126 cmd->credit = CPU_TO_LE16(credit);
5127 cmd->max_credit = max_credit;
5129 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5135 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5136 * @hw: pointer to the hw struct
5137 * @seid: switching component seid
5138 * @credit: BW limit credits (0 = disabled)
5139 * @max_bw: Max BW limit credits
5140 * @cmd_details: pointer to command details structure or NULL
5142 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5143 u16 seid, u16 credit, u8 max_bw,
5144 struct i40e_asq_cmd_details *cmd_details)
5146 struct i40e_aq_desc desc;
5147 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5148 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5149 enum i40e_status_code status;
5151 i40e_fill_default_direct_cmd_desc(&desc,
5152 i40e_aqc_opc_configure_switching_comp_bw_limit);
5154 cmd->seid = CPU_TO_LE16(seid);
5155 cmd->credit = CPU_TO_LE16(credit);
5156 cmd->max_bw = max_bw;
5158 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5164 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5165 * @hw: pointer to the hw struct
5167 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5168 * @cmd_details: pointer to command details structure or NULL
5170 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5172 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5173 struct i40e_asq_cmd_details *cmd_details)
5175 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5176 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5181 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5182 * @hw: pointer to the hw struct
5184 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5185 * @cmd_details: pointer to command details structure or NULL
5187 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5189 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5190 struct i40e_asq_cmd_details *cmd_details)
5192 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5193 i40e_aqc_opc_configure_vsi_tc_bw,
5198 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5199 * @hw: pointer to the hw struct
5200 * @seid: seid of the switching component connected to Physical Port
5201 * @ets_data: Buffer holding ETS parameters
5202 * @cmd_details: pointer to command details structure or NULL
5204 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5206 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5207 enum i40e_admin_queue_opc opcode,
5208 struct i40e_asq_cmd_details *cmd_details)
5210 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5211 sizeof(*ets_data), opcode, cmd_details);
5215 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5216 * @hw: pointer to the hw struct
5217 * @seid: seid of the switching component
5218 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5219 * @cmd_details: pointer to command details structure or NULL
5221 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5223 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5224 struct i40e_asq_cmd_details *cmd_details)
5226 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5227 i40e_aqc_opc_configure_switching_comp_bw_config,
5232 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5233 * @hw: pointer to the hw struct
5234 * @seid: seid of the switching component
5235 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5236 * @cmd_details: pointer to command details structure or NULL
5238 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5239 struct i40e_hw *hw, u16 seid,
5240 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5241 struct i40e_asq_cmd_details *cmd_details)
5243 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5244 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5249 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5250 * @hw: pointer to the hw struct
5251 * @seid: seid of the VSI
5252 * @bw_data: Buffer to hold VSI BW configuration
5253 * @cmd_details: pointer to command details structure or NULL
5255 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5257 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5258 struct i40e_asq_cmd_details *cmd_details)
5260 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5261 i40e_aqc_opc_query_vsi_bw_config,
5266 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5267 * @hw: pointer to the hw struct
5268 * @seid: seid of the VSI
5269 * @bw_data: Buffer to hold VSI BW configuration per TC
5270 * @cmd_details: pointer to command details structure or NULL
5272 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5274 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5275 struct i40e_asq_cmd_details *cmd_details)
5277 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5278 i40e_aqc_opc_query_vsi_ets_sla_config,
5283 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5284 * @hw: pointer to the hw struct
5285 * @seid: seid of the switching component
5286 * @bw_data: Buffer to hold switching component's per TC BW config
5287 * @cmd_details: pointer to command details structure or NULL
5289 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5291 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5292 struct i40e_asq_cmd_details *cmd_details)
5294 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5295 i40e_aqc_opc_query_switching_comp_ets_config,
5300 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5301 * @hw: pointer to the hw struct
5302 * @seid: seid of the VSI or switching component connected to Physical Port
5303 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5304 * @cmd_details: pointer to command details structure or NULL
5306 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5308 struct i40e_aqc_query_port_ets_config_resp *bw_data,
5309 struct i40e_asq_cmd_details *cmd_details)
5311 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5312 i40e_aqc_opc_query_port_ets_config,
5317 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5318 * @hw: pointer to the hw struct
5319 * @seid: seid of the switching component
5320 * @bw_data: Buffer to hold switching component's BW configuration
5321 * @cmd_details: pointer to command details structure or NULL
5323 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5325 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5326 struct i40e_asq_cmd_details *cmd_details)
5328 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5329 i40e_aqc_opc_query_switching_comp_bw_config,
5334 * i40e_validate_filter_settings
5335 * @hw: pointer to the hardware structure
5336 * @settings: Filter control settings
5338 * Check and validate the filter control settings passed.
5339 * The function checks for the valid filter/context sizes being
5340 * passed for FCoE and PE.
5342 * Returns I40E_SUCCESS if the values passed are valid and within
5343 * range else returns an error.
5345 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5346 struct i40e_filter_control_settings *settings)
5348 u32 fcoe_cntx_size, fcoe_filt_size;
5349 u32 pe_cntx_size, pe_filt_size;
5354 /* Validate FCoE settings passed */
5355 switch (settings->fcoe_filt_num) {
5356 case I40E_HASH_FILTER_SIZE_1K:
5357 case I40E_HASH_FILTER_SIZE_2K:
5358 case I40E_HASH_FILTER_SIZE_4K:
5359 case I40E_HASH_FILTER_SIZE_8K:
5360 case I40E_HASH_FILTER_SIZE_16K:
5361 case I40E_HASH_FILTER_SIZE_32K:
5362 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5363 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5366 return I40E_ERR_PARAM;
5369 switch (settings->fcoe_cntx_num) {
5370 case I40E_DMA_CNTX_SIZE_512:
5371 case I40E_DMA_CNTX_SIZE_1K:
5372 case I40E_DMA_CNTX_SIZE_2K:
5373 case I40E_DMA_CNTX_SIZE_4K:
5374 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5375 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5378 return I40E_ERR_PARAM;
5381 /* Validate PE settings passed */
5382 switch (settings->pe_filt_num) {
5383 case I40E_HASH_FILTER_SIZE_1K:
5384 case I40E_HASH_FILTER_SIZE_2K:
5385 case I40E_HASH_FILTER_SIZE_4K:
5386 case I40E_HASH_FILTER_SIZE_8K:
5387 case I40E_HASH_FILTER_SIZE_16K:
5388 case I40E_HASH_FILTER_SIZE_32K:
5389 case I40E_HASH_FILTER_SIZE_64K:
5390 case I40E_HASH_FILTER_SIZE_128K:
5391 case I40E_HASH_FILTER_SIZE_256K:
5392 case I40E_HASH_FILTER_SIZE_512K:
5393 case I40E_HASH_FILTER_SIZE_1M:
5394 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5395 pe_filt_size <<= (u32)settings->pe_filt_num;
5398 return I40E_ERR_PARAM;
5401 switch (settings->pe_cntx_num) {
5402 case I40E_DMA_CNTX_SIZE_512:
5403 case I40E_DMA_CNTX_SIZE_1K:
5404 case I40E_DMA_CNTX_SIZE_2K:
5405 case I40E_DMA_CNTX_SIZE_4K:
5406 case I40E_DMA_CNTX_SIZE_8K:
5407 case I40E_DMA_CNTX_SIZE_16K:
5408 case I40E_DMA_CNTX_SIZE_32K:
5409 case I40E_DMA_CNTX_SIZE_64K:
5410 case I40E_DMA_CNTX_SIZE_128K:
5411 case I40E_DMA_CNTX_SIZE_256K:
5412 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5413 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5416 return I40E_ERR_PARAM;
5419 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5420 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5421 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5422 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5423 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
5424 return I40E_ERR_INVALID_SIZE;
5426 return I40E_SUCCESS;
5430 * i40e_set_filter_control
5431 * @hw: pointer to the hardware structure
5432 * @settings: Filter control settings
5434 * Set the Queue Filters for PE/FCoE and enable filters required
5435 * for a single PF. It is expected that these settings are programmed
5436 * at the driver initialization time.
5438 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5439 struct i40e_filter_control_settings *settings)
5441 enum i40e_status_code ret = I40E_SUCCESS;
5442 u32 hash_lut_size = 0;
5446 return I40E_ERR_PARAM;
5448 /* Validate the input settings */
5449 ret = i40e_validate_filter_settings(hw, settings);
5453 /* Read the PF Queue Filter control register */
5454 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5456 /* Program required PE hash buckets for the PF */
5457 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5458 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5459 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5460 /* Program required PE contexts for the PF */
5461 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5462 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5463 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5465 /* Program required FCoE hash buckets for the PF */
5466 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5467 val |= ((u32)settings->fcoe_filt_num <<
5468 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5469 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5470 /* Program required FCoE DDP contexts for the PF */
5471 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5472 val |= ((u32)settings->fcoe_cntx_num <<
5473 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5474 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5476 /* Program Hash LUT size for the PF */
5477 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5478 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5480 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5481 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5483 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5484 if (settings->enable_fdir)
5485 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5486 if (settings->enable_ethtype)
5487 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5488 if (settings->enable_macvlan)
5489 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5491 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5493 return I40E_SUCCESS;
5497 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5498 * @hw: pointer to the hw struct
5499 * @mac_addr: MAC address to use in the filter
5500 * @ethtype: Ethertype to use in the filter
5501 * @flags: Flags that needs to be applied to the filter
5502 * @vsi_seid: seid of the control VSI
5503 * @queue: VSI queue number to send the packet to
5504 * @is_add: Add control packet filter if True else remove
5505 * @stats: Structure to hold information on control filter counts
5506 * @cmd_details: pointer to command details structure or NULL
5508 * This command will Add or Remove control packet filter for a control VSI.
5509 * In return it will update the total number of perfect filter count in
5512 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5513 u8 *mac_addr, u16 ethtype, u16 flags,
5514 u16 vsi_seid, u16 queue, bool is_add,
5515 struct i40e_control_filter_stats *stats,
5516 struct i40e_asq_cmd_details *cmd_details)
5518 struct i40e_aq_desc desc;
5519 struct i40e_aqc_add_remove_control_packet_filter *cmd =
5520 (struct i40e_aqc_add_remove_control_packet_filter *)
5522 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5523 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5525 enum i40e_status_code status;
5528 return I40E_ERR_PARAM;
5531 i40e_fill_default_direct_cmd_desc(&desc,
5532 i40e_aqc_opc_add_control_packet_filter);
5533 cmd->queue = CPU_TO_LE16(queue);
5535 i40e_fill_default_direct_cmd_desc(&desc,
5536 i40e_aqc_opc_remove_control_packet_filter);
5540 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
5541 I40E_NONDMA_TO_NONDMA);
5543 cmd->etype = CPU_TO_LE16(ethtype);
5544 cmd->flags = CPU_TO_LE16(flags);
5545 cmd->seid = CPU_TO_LE16(vsi_seid);
5547 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5549 if (!status && stats) {
5550 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5551 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5552 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5553 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5560 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5561 * @hw: pointer to the hw struct
5562 * @seid: VSI seid to add ethertype filter from
5564 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5565 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5568 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5569 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5570 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5571 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5572 enum i40e_status_code status;
5574 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5575 seid, 0, true, NULL,
5578 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5582 * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5583 * @filters: list of cloud filters
5584 * @filter_count: length of list
5586 * There's an issue in the device where the Geneve VNI layout needs
5587 * to be shifted 1 byte over from the VxLAN VNI
5589 STATIC void i40e_fix_up_geneve_vni(
5590 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5593 struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters;
5596 for (i = 0; i < filter_count; i++) {
5600 tnl_type = (LE16_TO_CPU(f[i].flags) &
5601 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5602 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5603 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5604 ti = LE32_TO_CPU(f[i].tenant_id);
5605 f[i].tenant_id = CPU_TO_LE32(ti << 8);
5611 * i40e_aq_add_cloud_filters
5612 * @hw: pointer to the hardware structure
5613 * @seid: VSI seid to add cloud filters from
5614 * @filters: Buffer which contains the filters to be added
5615 * @filter_count: number of filters contained in the buffer
5617 * Set the cloud filters for a given VSI. The contents of the
5618 * i40e_aqc_add_remove_cloud_filters_element_data are filled
5619 * in by the caller of the function.
5622 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5624 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5627 struct i40e_aq_desc desc;
5628 struct i40e_aqc_add_remove_cloud_filters *cmd =
5629 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5630 enum i40e_status_code status;
5633 i40e_fill_default_direct_cmd_desc(&desc,
5634 i40e_aqc_opc_add_cloud_filters);
5636 buff_len = filter_count * sizeof(*filters);
5637 desc.datalen = CPU_TO_LE16(buff_len);
5638 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5639 cmd->num_filters = filter_count;
5640 cmd->seid = CPU_TO_LE16(seid);
5642 i40e_fix_up_geneve_vni(filters, filter_count);
5644 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5650 * i40e_aq_remove_cloud_filters
5651 * @hw: pointer to the hardware structure
5652 * @seid: VSI seid to remove cloud filters from
5653 * @filters: Buffer which contains the filters to be removed
5654 * @filter_count: number of filters contained in the buffer
5656 * Remove the cloud filters for a given VSI. The contents of the
5657 * i40e_aqc_add_remove_cloud_filters_element_data are filled
5658 * in by the caller of the function.
5661 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5663 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5666 struct i40e_aq_desc desc;
5667 struct i40e_aqc_add_remove_cloud_filters *cmd =
5668 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5669 enum i40e_status_code status;
5672 i40e_fill_default_direct_cmd_desc(&desc,
5673 i40e_aqc_opc_remove_cloud_filters);
5675 buff_len = filter_count * sizeof(*filters);
5676 desc.datalen = CPU_TO_LE16(buff_len);
5677 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5678 cmd->num_filters = filter_count;
5679 cmd->seid = CPU_TO_LE16(seid);
5681 i40e_fix_up_geneve_vni(filters, filter_count);
5683 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5689 * i40e_aq_alternate_write
5690 * @hw: pointer to the hardware structure
5691 * @reg_addr0: address of first dword to be read
5692 * @reg_val0: value to be written under 'reg_addr0'
5693 * @reg_addr1: address of second dword to be read
5694 * @reg_val1: value to be written under 'reg_addr1'
5696 * Write one or two dwords to alternate structure. Fields are indicated
5697 * by 'reg_addr0' and 'reg_addr1' register numbers.
5700 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5701 u32 reg_addr0, u32 reg_val0,
5702 u32 reg_addr1, u32 reg_val1)
5704 struct i40e_aq_desc desc;
5705 struct i40e_aqc_alternate_write *cmd_resp =
5706 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5707 enum i40e_status_code status;
5709 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5710 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5711 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5712 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5713 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5715 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5721 * i40e_aq_alternate_write_indirect
5722 * @hw: pointer to the hardware structure
5723 * @addr: address of a first register to be modified
5724 * @dw_count: number of alternate structure fields to write
5725 * @buffer: pointer to the command buffer
5727 * Write 'dw_count' dwords from 'buffer' to alternate structure
5728 * starting at 'addr'.
5731 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5732 u32 addr, u32 dw_count, void *buffer)
5734 struct i40e_aq_desc desc;
5735 struct i40e_aqc_alternate_ind_write *cmd_resp =
5736 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5737 enum i40e_status_code status;
5740 return I40E_ERR_PARAM;
5742 /* Indirect command */
5743 i40e_fill_default_direct_cmd_desc(&desc,
5744 i40e_aqc_opc_alternate_write_indirect);
5746 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5747 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5748 if (dw_count > (I40E_AQ_LARGE_BUF/4))
5749 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5751 cmd_resp->address = CPU_TO_LE32(addr);
5752 cmd_resp->length = CPU_TO_LE32(dw_count);
5754 status = i40e_asq_send_command(hw, &desc, buffer,
5755 I40E_LO_DWORD(4*dw_count), NULL);
5761 * i40e_aq_alternate_read
5762 * @hw: pointer to the hardware structure
5763 * @reg_addr0: address of first dword to be read
5764 * @reg_val0: pointer for data read from 'reg_addr0'
5765 * @reg_addr1: address of second dword to be read
5766 * @reg_val1: pointer for data read from 'reg_addr1'
5768 * Read one or two dwords from alternate structure. Fields are indicated
5769 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5770 * is not passed then only register at 'reg_addr0' is read.
5773 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5774 u32 reg_addr0, u32 *reg_val0,
5775 u32 reg_addr1, u32 *reg_val1)
5777 struct i40e_aq_desc desc;
5778 struct i40e_aqc_alternate_write *cmd_resp =
5779 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5780 enum i40e_status_code status;
5782 if (reg_val0 == NULL)
5783 return I40E_ERR_PARAM;
5785 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5786 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5787 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5789 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5791 if (status == I40E_SUCCESS) {
5792 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5794 if (reg_val1 != NULL)
5795 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5802 * i40e_aq_alternate_read_indirect
5803 * @hw: pointer to the hardware structure
5804 * @addr: address of the alternate structure field
5805 * @dw_count: number of alternate structure fields to read
5806 * @buffer: pointer to the command buffer
5808 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5809 * place them in 'buffer'. The buffer should be allocated by caller.
5812 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5813 u32 addr, u32 dw_count, void *buffer)
5815 struct i40e_aq_desc desc;
5816 struct i40e_aqc_alternate_ind_write *cmd_resp =
5817 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5818 enum i40e_status_code status;
5821 return I40E_ERR_PARAM;
5823 /* Indirect command */
5824 i40e_fill_default_direct_cmd_desc(&desc,
5825 i40e_aqc_opc_alternate_read_indirect);
5827 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5828 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5829 if (dw_count > (I40E_AQ_LARGE_BUF/4))
5830 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5832 cmd_resp->address = CPU_TO_LE32(addr);
5833 cmd_resp->length = CPU_TO_LE32(dw_count);
5835 status = i40e_asq_send_command(hw, &desc, buffer,
5836 I40E_LO_DWORD(4*dw_count), NULL);
5842 * i40e_aq_alternate_clear
5843 * @hw: pointer to the HW structure.
5845 * Clear the alternate structures of the port from which the function
5849 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5851 struct i40e_aq_desc desc;
5852 enum i40e_status_code status;
5854 i40e_fill_default_direct_cmd_desc(&desc,
5855 i40e_aqc_opc_alternate_clear_port);
5857 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5863 * i40e_aq_alternate_write_done
5864 * @hw: pointer to the HW structure.
5865 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
5866 * @reset_needed: indicates the SW should trigger GLOBAL reset
5868 * Indicates to the FW that alternate structures have been changed.
5871 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
5872 u8 bios_mode, bool *reset_needed)
5874 struct i40e_aq_desc desc;
5875 struct i40e_aqc_alternate_write_done *cmd =
5876 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5877 enum i40e_status_code status;
5879 if (reset_needed == NULL)
5880 return I40E_ERR_PARAM;
5882 i40e_fill_default_direct_cmd_desc(&desc,
5883 i40e_aqc_opc_alternate_write_done);
5885 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
5887 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5888 if (!status && reset_needed)
5889 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
5890 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
5896 * i40e_aq_set_oem_mode
5897 * @hw: pointer to the HW structure.
5898 * @oem_mode: the OEM mode to be used
5900 * Sets the device to a specific operating mode. Currently the only supported
5901 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
5904 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
5907 struct i40e_aq_desc desc;
5908 struct i40e_aqc_alternate_write_done *cmd =
5909 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5910 enum i40e_status_code status;
5912 i40e_fill_default_direct_cmd_desc(&desc,
5913 i40e_aqc_opc_alternate_set_mode);
5915 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
5917 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5923 * i40e_aq_resume_port_tx
5924 * @hw: pointer to the hardware structure
5925 * @cmd_details: pointer to command details structure or NULL
5927 * Resume port's Tx traffic
5929 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
5930 struct i40e_asq_cmd_details *cmd_details)
5932 struct i40e_aq_desc desc;
5933 enum i40e_status_code status;
5935 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
5937 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5943 * i40e_set_pci_config_data - store PCI bus info
5944 * @hw: pointer to hardware structure
5945 * @link_status: the link status word from PCI config space
5947 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
5949 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
5951 hw->bus.type = i40e_bus_type_pci_express;
5953 switch (link_status & I40E_PCI_LINK_WIDTH) {
5954 case I40E_PCI_LINK_WIDTH_1:
5955 hw->bus.width = i40e_bus_width_pcie_x1;
5957 case I40E_PCI_LINK_WIDTH_2:
5958 hw->bus.width = i40e_bus_width_pcie_x2;
5960 case I40E_PCI_LINK_WIDTH_4:
5961 hw->bus.width = i40e_bus_width_pcie_x4;
5963 case I40E_PCI_LINK_WIDTH_8:
5964 hw->bus.width = i40e_bus_width_pcie_x8;
5967 hw->bus.width = i40e_bus_width_unknown;
5971 switch (link_status & I40E_PCI_LINK_SPEED) {
5972 case I40E_PCI_LINK_SPEED_2500:
5973 hw->bus.speed = i40e_bus_speed_2500;
5975 case I40E_PCI_LINK_SPEED_5000:
5976 hw->bus.speed = i40e_bus_speed_5000;
5978 case I40E_PCI_LINK_SPEED_8000:
5979 hw->bus.speed = i40e_bus_speed_8000;
5982 hw->bus.speed = i40e_bus_speed_unknown;
5988 * i40e_aq_debug_dump
5989 * @hw: pointer to the hardware structure
5990 * @cluster_id: specific cluster to dump
5991 * @table_id: table id within cluster
5992 * @start_index: index of line in the block to read
5993 * @buff_size: dump buffer size
5994 * @buff: dump buffer
5995 * @ret_buff_size: actual buffer size returned
5996 * @ret_next_table: next block to read
5997 * @ret_next_index: next index to read
5999 * Dump internal FW/HW data for debug purposes.
6002 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
6003 u8 table_id, u32 start_index, u16 buff_size,
6004 void *buff, u16 *ret_buff_size,
6005 u8 *ret_next_table, u32 *ret_next_index,
6006 struct i40e_asq_cmd_details *cmd_details)
6008 struct i40e_aq_desc desc;
6009 struct i40e_aqc_debug_dump_internals *cmd =
6010 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6011 struct i40e_aqc_debug_dump_internals *resp =
6012 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6013 enum i40e_status_code status;
6015 if (buff_size == 0 || !buff)
6016 return I40E_ERR_PARAM;
6018 i40e_fill_default_direct_cmd_desc(&desc,
6019 i40e_aqc_opc_debug_dump_internals);
6020 /* Indirect Command */
6021 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6022 if (buff_size > I40E_AQ_LARGE_BUF)
6023 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6025 cmd->cluster_id = cluster_id;
6026 cmd->table_id = table_id;
6027 cmd->idx = CPU_TO_LE32(start_index);
6029 desc.datalen = CPU_TO_LE16(buff_size);
6031 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
6033 if (ret_buff_size != NULL)
6034 *ret_buff_size = LE16_TO_CPU(desc.datalen);
6035 if (ret_next_table != NULL)
6036 *ret_next_table = resp->table_id;
6037 if (ret_next_index != NULL)
6038 *ret_next_index = LE32_TO_CPU(resp->idx);
6045 * i40e_read_bw_from_alt_ram
6046 * @hw: pointer to the hardware structure
6047 * @max_bw: pointer for max_bw read
6048 * @min_bw: pointer for min_bw read
6049 * @min_valid: pointer for bool that is true if min_bw is a valid value
6050 * @max_valid: pointer for bool that is true if max_bw is a valid value
6052 * Read bw from the alternate ram for the given pf
6054 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
6055 u32 *max_bw, u32 *min_bw,
6056 bool *min_valid, bool *max_valid)
6058 enum i40e_status_code status;
6059 u32 max_bw_addr, min_bw_addr;
6061 /* Calculate the address of the min/max bw registers */
6062 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6063 I40E_ALT_STRUCT_MAX_BW_OFFSET +
6064 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6065 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6066 I40E_ALT_STRUCT_MIN_BW_OFFSET +
6067 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6069 /* Read the bandwidths from alt ram */
6070 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
6071 min_bw_addr, min_bw);
6073 if (*min_bw & I40E_ALT_BW_VALID_MASK)
6078 if (*max_bw & I40E_ALT_BW_VALID_MASK)
6087 * i40e_aq_configure_partition_bw
6088 * @hw: pointer to the hardware structure
6089 * @bw_data: Buffer holding valid pfs and bw limits
6090 * @cmd_details: pointer to command details
6092 * Configure partitions guaranteed/max bw
6094 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6095 struct i40e_aqc_configure_partition_bw_data *bw_data,
6096 struct i40e_asq_cmd_details *cmd_details)
6098 enum i40e_status_code status;
6099 struct i40e_aq_desc desc;
6100 u16 bwd_size = sizeof(*bw_data);
6102 i40e_fill_default_direct_cmd_desc(&desc,
6103 i40e_aqc_opc_configure_partition_bw);
6105 /* Indirect command */
6106 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6107 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6109 desc.datalen = CPU_TO_LE16(bwd_size);
6111 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6117 * i40e_read_phy_register_clause22
6118 * @hw: pointer to the HW structure
6119 * @reg: register address in the page
6120 * @phy_adr: PHY address on MDIO interface
6121 * @value: PHY register value
6123 * Reads specified PHY register value
6125 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
6126 u16 reg, u8 phy_addr, u16 *value)
6128 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6129 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6133 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6134 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6135 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
6136 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6137 (I40E_GLGEN_MSCA_MDICMD_MASK);
6138 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6140 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6141 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6142 status = I40E_SUCCESS;
6145 i40e_usec_delay(10);
6150 i40e_debug(hw, I40E_DEBUG_PHY,
6151 "PHY: Can't write command to external PHY.\n");
6153 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6154 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6155 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6162 * i40e_write_phy_register_clause22
6163 * @hw: pointer to the HW structure
6164 * @reg: register address in the page
6165 * @phy_adr: PHY address on MDIO interface
6166 * @value: PHY register value
6168 * Writes specified PHY register value
6170 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6171 u16 reg, u8 phy_addr, u16 value)
6173 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6174 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6178 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6179 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6181 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6182 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6183 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6184 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6185 (I40E_GLGEN_MSCA_MDICMD_MASK);
6187 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6189 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6190 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6191 status = I40E_SUCCESS;
6194 i40e_usec_delay(10);
6202 * i40e_read_phy_register_clause45
6203 * @hw: pointer to the HW structure
6204 * @page: registers page number
6205 * @reg: register address in the page
6206 * @phy_adr: PHY address on MDIO interface
6207 * @value: PHY register value
6209 * Reads specified PHY register value
6211 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6212 u8 page, u16 reg, u8 phy_addr, u16 *value)
6214 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6217 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6219 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6220 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6221 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6222 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6223 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6224 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6225 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6226 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6228 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6229 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6230 status = I40E_SUCCESS;
6233 i40e_usec_delay(10);
6238 i40e_debug(hw, I40E_DEBUG_PHY,
6239 "PHY: Can't write command to external PHY.\n");
6243 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6244 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6245 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6246 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6247 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6248 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6249 status = I40E_ERR_TIMEOUT;
6251 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6253 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6254 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6255 status = I40E_SUCCESS;
6258 i40e_usec_delay(10);
6263 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6264 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6265 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6267 i40e_debug(hw, I40E_DEBUG_PHY,
6268 "PHY: Can't read register value from external PHY.\n");
6276 * i40e_write_phy_register_clause45
6277 * @hw: pointer to the HW structure
6278 * @page: registers page number
6279 * @reg: register address in the page
6280 * @phy_adr: PHY address on MDIO interface
6281 * @value: PHY register value
6283 * Writes value to specified PHY register
6285 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6286 u8 page, u16 reg, u8 phy_addr, u16 value)
6288 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6291 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6293 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6294 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6295 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6296 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6297 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6298 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6299 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6300 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6302 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6303 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6304 status = I40E_SUCCESS;
6307 i40e_usec_delay(10);
6311 i40e_debug(hw, I40E_DEBUG_PHY,
6312 "PHY: Can't write command to external PHY.\n");
6316 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6317 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6319 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6320 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6321 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6322 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6323 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6324 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6325 status = I40E_ERR_TIMEOUT;
6327 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6329 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6330 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6331 status = I40E_SUCCESS;
6334 i40e_usec_delay(10);
6343 * i40e_write_phy_register
6344 * @hw: pointer to the HW structure
6345 * @page: registers page number
6346 * @reg: register address in the page
6347 * @phy_adr: PHY address on MDIO interface
6348 * @value: PHY register value
6350 * Writes value to specified PHY register
6352 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6353 u8 page, u16 reg, u8 phy_addr, u16 value)
6355 enum i40e_status_code status;
6357 switch (hw->device_id) {
6358 case I40E_DEV_ID_1G_BASE_T_X722:
6359 status = i40e_write_phy_register_clause22(hw,
6360 reg, phy_addr, value);
6362 case I40E_DEV_ID_10G_BASE_T:
6363 case I40E_DEV_ID_10G_BASE_T4:
6364 case I40E_DEV_ID_10G_BASE_T_X722:
6365 case I40E_DEV_ID_25G_B:
6366 case I40E_DEV_ID_25G_SFP28:
6367 status = i40e_write_phy_register_clause45(hw,
6368 page, reg, phy_addr, value);
6371 status = I40E_ERR_UNKNOWN_PHY;
6379 * i40e_read_phy_register
6380 * @hw: pointer to the HW structure
6381 * @page: registers page number
6382 * @reg: register address in the page
6383 * @phy_adr: PHY address on MDIO interface
6384 * @value: PHY register value
6386 * Reads specified PHY register value
6388 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6389 u8 page, u16 reg, u8 phy_addr, u16 *value)
6391 enum i40e_status_code status;
6393 switch (hw->device_id) {
6394 case I40E_DEV_ID_1G_BASE_T_X722:
6395 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6398 case I40E_DEV_ID_10G_BASE_T:
6399 case I40E_DEV_ID_10G_BASE_T4:
6400 case I40E_DEV_ID_10G_BASE_T_X722:
6401 case I40E_DEV_ID_25G_B:
6402 case I40E_DEV_ID_25G_SFP28:
6403 status = i40e_read_phy_register_clause45(hw, page, reg,
6407 status = I40E_ERR_UNKNOWN_PHY;
6415 * i40e_get_phy_address
6416 * @hw: pointer to the HW structure
6417 * @dev_num: PHY port num that address we want
6418 * @phy_addr: Returned PHY address
6420 * Gets PHY address for current port
6422 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6424 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6425 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6427 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6431 * i40e_blink_phy_led
6432 * @hw: pointer to the HW structure
6433 * @time: time how long led will blinks in secs
6434 * @interval: gap between LED on and off in msecs
6436 * Blinks PHY link LED
6438 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6439 u32 time, u32 interval)
6441 enum i40e_status_code status = I40E_SUCCESS;
6446 u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6450 i = rd32(hw, I40E_PFGEN_PORTNUM);
6451 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6452 phy_addr = i40e_get_phy_address(hw, port_num);
6454 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6456 status = i40e_read_phy_register_clause45(hw,
6457 I40E_PHY_COM_REG_PAGE,
6461 goto phy_blinking_end;
6463 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6465 status = i40e_write_phy_register_clause45(hw,
6466 I40E_PHY_COM_REG_PAGE,
6470 goto phy_blinking_end;
6475 if (time > 0 && interval > 0) {
6476 for (i = 0; i < time * 1000; i += interval) {
6477 status = i40e_read_phy_register_clause45(hw,
6478 I40E_PHY_COM_REG_PAGE,
6479 led_addr, phy_addr, &led_reg);
6481 goto restore_config;
6482 if (led_reg & I40E_PHY_LED_MANUAL_ON)
6485 led_reg = I40E_PHY_LED_MANUAL_ON;
6486 status = i40e_write_phy_register_clause45(hw,
6487 I40E_PHY_COM_REG_PAGE,
6488 led_addr, phy_addr, led_reg);
6490 goto restore_config;
6491 i40e_msec_delay(interval);
6496 status = i40e_write_phy_register_clause45(hw,
6497 I40E_PHY_COM_REG_PAGE,
6498 led_addr, phy_addr, led_ctl);
6505 * i40e_led_get_phy - return current on/off mode
6506 * @hw: pointer to the hw struct
6507 * @led_addr: address of led register to use
6508 * @val: original value of register to use
6511 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6514 enum i40e_status_code status = I40E_SUCCESS;
6522 temp_addr = I40E_PHY_LED_PROV_REG_1;
6523 i = rd32(hw, I40E_PFGEN_PORTNUM);
6524 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6525 phy_addr = i40e_get_phy_address(hw, port_num);
6527 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6529 status = i40e_read_phy_register_clause45(hw,
6530 I40E_PHY_COM_REG_PAGE,
6531 temp_addr, phy_addr,
6536 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6537 *led_addr = temp_addr;
6546 * @hw: pointer to the HW structure
6547 * @on: true or false
6548 * @mode: original val plus bit for set or ignore
6549 * Set led's on or off when controlled by the PHY
6552 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6553 u16 led_addr, u32 mode)
6555 enum i40e_status_code status = I40E_SUCCESS;
6562 i = rd32(hw, I40E_PFGEN_PORTNUM);
6563 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6564 phy_addr = i40e_get_phy_address(hw, port_num);
6565 status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6566 led_addr, phy_addr, &led_reg);
6570 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6572 status = i40e_write_phy_register_clause45(hw,
6573 I40E_PHY_COM_REG_PAGE,
6579 status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6580 led_addr, phy_addr, &led_reg);
6582 goto restore_config;
6584 led_reg = I40E_PHY_LED_MANUAL_ON;
6587 status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6588 led_addr, phy_addr, led_reg);
6590 goto restore_config;
6591 if (mode & I40E_PHY_LED_MODE_ORIG) {
6592 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6593 status = i40e_write_phy_register_clause45(hw,
6594 I40E_PHY_COM_REG_PAGE,
6595 led_addr, phy_addr, led_ctl);
6599 status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6600 led_addr, phy_addr, led_ctl);
6603 #endif /* PF_DRIVER */
6606 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6607 * @hw: pointer to the hw struct
6608 * @reg_addr: register address
6609 * @reg_val: ptr to register value
6610 * @cmd_details: pointer to command details structure or NULL
6612 * Use the firmware to read the Rx control register,
6613 * especially useful if the Rx unit is under heavy pressure
6615 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6616 u32 reg_addr, u32 *reg_val,
6617 struct i40e_asq_cmd_details *cmd_details)
6619 struct i40e_aq_desc desc;
6620 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
6621 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6622 enum i40e_status_code status;
6624 if (reg_val == NULL)
6625 return I40E_ERR_PARAM;
6627 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
6629 cmd_resp->address = CPU_TO_LE32(reg_addr);
6631 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6633 if (status == I40E_SUCCESS)
6634 *reg_val = LE32_TO_CPU(cmd_resp->value);
6640 * i40e_read_rx_ctl - read from an Rx control register
6641 * @hw: pointer to the hw struct
6642 * @reg_addr: register address
6644 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
6646 enum i40e_status_code status = I40E_SUCCESS;
6651 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6652 if (!use_register) {
6654 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
6655 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6662 /* if the AQ access failed, try the old-fashioned way */
6663 if (status || use_register)
6664 val = rd32(hw, reg_addr);
6670 * i40e_aq_rx_ctl_write_register
6671 * @hw: pointer to the hw struct
6672 * @reg_addr: register address
6673 * @reg_val: register value
6674 * @cmd_details: pointer to command details structure or NULL
6676 * Use the firmware to write to an Rx control register,
6677 * especially useful if the Rx unit is under heavy pressure
6679 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
6680 u32 reg_addr, u32 reg_val,
6681 struct i40e_asq_cmd_details *cmd_details)
6683 struct i40e_aq_desc desc;
6684 struct i40e_aqc_rx_ctl_reg_read_write *cmd =
6685 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6686 enum i40e_status_code status;
6688 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
6690 cmd->address = CPU_TO_LE32(reg_addr);
6691 cmd->value = CPU_TO_LE32(reg_val);
6693 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6699 * i40e_write_rx_ctl - write to an Rx control register
6700 * @hw: pointer to the hw struct
6701 * @reg_addr: register address
6702 * @reg_val: register value
6704 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
6706 enum i40e_status_code status = I40E_SUCCESS;
6710 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6711 if (!use_register) {
6713 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
6715 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6722 /* if the AQ access failed, try the old-fashioned way */
6723 if (status || use_register)
6724 wr32(hw, reg_addr, reg_val);
6729 * i40e_aq_send_msg_to_pf
6730 * @hw: pointer to the hardware structure
6731 * @v_opcode: opcodes for VF-PF communication
6732 * @v_retval: return error code
6733 * @msg: pointer to the msg buffer
6734 * @msglen: msg length
6735 * @cmd_details: pointer to command details
6737 * Send message to PF driver using admin queue. By default, this message
6738 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
6739 * completion before returning.
6741 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
6742 enum i40e_virtchnl_ops v_opcode,
6743 enum i40e_status_code v_retval,
6744 u8 *msg, u16 msglen,
6745 struct i40e_asq_cmd_details *cmd_details)
6747 struct i40e_aq_desc desc;
6748 struct i40e_asq_cmd_details details;
6749 enum i40e_status_code status;
6751 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
6752 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
6753 desc.cookie_high = CPU_TO_LE32(v_opcode);
6754 desc.cookie_low = CPU_TO_LE32(v_retval);
6756 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
6757 | I40E_AQ_FLAG_RD));
6758 if (msglen > I40E_AQ_LARGE_BUF)
6759 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6760 desc.datalen = CPU_TO_LE16(msglen);
6763 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
6764 details.async = true;
6765 cmd_details = &details;
6767 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
6768 msglen, cmd_details);
6773 * i40e_vf_parse_hw_config
6774 * @hw: pointer to the hardware structure
6775 * @msg: pointer to the virtual channel VF resource structure
6777 * Given a VF resource message from the PF, populate the hw struct
6778 * with appropriate information.
6780 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
6781 struct i40e_virtchnl_vf_resource *msg)
6783 struct i40e_virtchnl_vsi_resource *vsi_res;
6786 vsi_res = &msg->vsi_res[0];
6788 hw->dev_caps.num_vsis = msg->num_vsis;
6789 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
6790 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
6791 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
6792 hw->dev_caps.dcb = msg->vf_offload_flags &
6793 I40E_VIRTCHNL_VF_OFFLOAD_L2;
6794 hw->dev_caps.fcoe = (msg->vf_offload_flags &
6795 I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
6796 hw->dev_caps.iwarp = (msg->vf_offload_flags &
6797 I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
6798 for (i = 0; i < msg->num_vsis; i++) {
6799 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
6800 i40e_memcpy(hw->mac.perm_addr,
6801 vsi_res->default_mac_addr,
6802 I40E_ETH_LENGTH_OF_ADDRESS,
6803 I40E_NONDMA_TO_NONDMA);
6804 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
6805 I40E_ETH_LENGTH_OF_ADDRESS,
6806 I40E_NONDMA_TO_NONDMA);
6814 * @hw: pointer to the hardware structure
6816 * Send a VF_RESET message to the PF. Does not wait for response from PF
6817 * as none will be forthcoming. Immediately after calling this function,
6818 * the admin queue should be shut down and (optionally) reinitialized.
6820 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
6822 return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
6823 I40E_SUCCESS, NULL, 0, NULL);
6825 #endif /* VF_DRIVER */
6829 * i40e_aq_set_arp_proxy_config
6830 * @hw: pointer to the HW structure
6831 * @proxy_config - pointer to proxy config command table struct
6832 * @cmd_details: pointer to command details
6834 * Set ARP offload parameters from pre-populated
6835 * i40e_aqc_arp_proxy_data struct
6837 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
6838 struct i40e_aqc_arp_proxy_data *proxy_config,
6839 struct i40e_asq_cmd_details *cmd_details)
6841 struct i40e_aq_desc desc;
6842 enum i40e_status_code status;
6845 return I40E_ERR_PARAM;
6847 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
6849 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6850 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6851 desc.params.external.addr_high =
6852 CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
6853 desc.params.external.addr_low =
6854 CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
6855 desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_arp_proxy_data));
6857 status = i40e_asq_send_command(hw, &desc, proxy_config,
6858 sizeof(struct i40e_aqc_arp_proxy_data),
6865 * i40e_aq_opc_set_ns_proxy_table_entry
6866 * @hw: pointer to the HW structure
6867 * @ns_proxy_table_entry: pointer to NS table entry command struct
6868 * @cmd_details: pointer to command details
6870 * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
6871 * from pre-populated i40e_aqc_ns_proxy_data struct
6873 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
6874 struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
6875 struct i40e_asq_cmd_details *cmd_details)
6877 struct i40e_aq_desc desc;
6878 enum i40e_status_code status;
6880 if (!ns_proxy_table_entry)
6881 return I40E_ERR_PARAM;
6883 i40e_fill_default_direct_cmd_desc(&desc,
6884 i40e_aqc_opc_set_ns_proxy_table_entry);
6886 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6887 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6888 desc.params.external.addr_high =
6889 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
6890 desc.params.external.addr_low =
6891 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
6892 desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_ns_proxy_data));
6894 status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
6895 sizeof(struct i40e_aqc_ns_proxy_data),
6902 * i40e_aq_set_clear_wol_filter
6903 * @hw: pointer to the hw struct
6904 * @filter_index: index of filter to modify (0-7)
6905 * @filter: buffer containing filter to be set
6906 * @set_filter: true to set filter, false to clear filter
6907 * @no_wol_tco: if true, pass through packets cannot cause wake-up
6908 * if false, pass through packets may cause wake-up
6909 * @filter_valid: true if filter action is valid
6910 * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
6911 * @cmd_details: pointer to command details structure or NULL
6913 * Set or clear WoL filter for port attached to the PF
6915 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
6917 struct i40e_aqc_set_wol_filter_data *filter,
6918 bool set_filter, bool no_wol_tco,
6919 bool filter_valid, bool no_wol_tco_valid,
6920 struct i40e_asq_cmd_details *cmd_details)
6922 struct i40e_aq_desc desc;
6923 struct i40e_aqc_set_wol_filter *cmd =
6924 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
6925 enum i40e_status_code status;
6927 u16 valid_flags = 0;
6930 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
6932 if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
6933 return I40E_ERR_PARAM;
6934 cmd->filter_index = CPU_TO_LE16(filter_index);
6938 return I40E_ERR_PARAM;
6940 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
6941 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR;
6945 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
6946 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
6949 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
6950 if (no_wol_tco_valid)
6951 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
6952 cmd->valid_flags = CPU_TO_LE16(valid_flags);
6954 buff_len = sizeof(*filter);
6955 desc.datalen = CPU_TO_LE16(buff_len);
6957 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6958 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6960 cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
6961 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
6963 status = i40e_asq_send_command(hw, &desc, filter,
6964 buff_len, cmd_details);
6970 * i40e_aq_get_wake_event_reason
6971 * @hw: pointer to the hw struct
6972 * @wake_reason: return value, index of matching filter
6973 * @cmd_details: pointer to command details structure or NULL
6975 * Get information for the reason of a Wake Up event
6977 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
6979 struct i40e_asq_cmd_details *cmd_details)
6981 struct i40e_aq_desc desc;
6982 struct i40e_aqc_get_wake_reason_completion *resp =
6983 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
6984 enum i40e_status_code status;
6986 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
6988 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6990 if (status == I40E_SUCCESS)
6991 *wake_reason = LE16_TO_CPU(resp->wake_reason);
6997 * i40e_aq_clear_all_wol_filters
6998 * @hw: pointer to the hw struct
6999 * @cmd_details: pointer to command details structure or NULL
7001 * Get information for the reason of a Wake Up event
7003 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw,
7004 struct i40e_asq_cmd_details *cmd_details)
7006 struct i40e_aq_desc desc;
7007 enum i40e_status_code status;
7009 i40e_fill_default_direct_cmd_desc(&desc,
7010 i40e_aqc_opc_clear_all_wol_filters);
7012 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7016 #endif /* X722_SUPPORT */