1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2018
6 #include "i40e_adminq.h"
7 #include "i40e_prototype.h"
11 * i40e_set_mac_type - Sets MAC type
12 * @hw: pointer to the HW structure
14 * This function sets the mac type of the adapter based on the
15 * vendor ID and device ID stored in the hw structure.
17 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
18 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
20 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
23 enum i40e_status_code status = I40E_SUCCESS;
25 DEBUGFUNC("i40e_set_mac_type\n");
27 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
28 switch (hw->device_id) {
29 case I40E_DEV_ID_SFP_XL710:
30 case I40E_DEV_ID_QEMU:
31 case I40E_DEV_ID_KX_B:
32 case I40E_DEV_ID_KX_C:
33 case I40E_DEV_ID_QSFP_A:
34 case I40E_DEV_ID_QSFP_B:
35 case I40E_DEV_ID_QSFP_C:
36 case I40E_DEV_ID_10G_BASE_T:
37 case I40E_DEV_ID_10G_BASE_T4:
39 case I40E_DEV_ID_10G_BASE_T_BC:
41 case I40E_DEV_ID_20G_KR2:
42 case I40E_DEV_ID_20G_KR2_A:
43 case I40E_DEV_ID_25G_B:
44 case I40E_DEV_ID_25G_SFP28:
45 hw->mac.type = I40E_MAC_XL710;
47 #ifdef X722_A0_SUPPORT
48 case I40E_DEV_ID_X722_A0:
50 case I40E_DEV_ID_KX_X722:
51 case I40E_DEV_ID_QSFP_X722:
52 case I40E_DEV_ID_SFP_X722:
53 case I40E_DEV_ID_1G_BASE_T_X722:
54 case I40E_DEV_ID_10G_BASE_T_X722:
55 case I40E_DEV_ID_SFP_I_X722:
56 hw->mac.type = I40E_MAC_X722;
58 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
59 case I40E_DEV_ID_X722_VF:
60 #ifdef X722_A0_SUPPORT
61 case I40E_DEV_ID_X722_A0_VF:
63 hw->mac.type = I40E_MAC_X722_VF;
65 #endif /* INTEGRATED_VF || VF_DRIVER */
66 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
68 case I40E_DEV_ID_VF_HV:
69 case I40E_DEV_ID_ADAPTIVE_VF:
70 hw->mac.type = I40E_MAC_VF;
74 hw->mac.type = I40E_MAC_GENERIC;
78 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
81 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
82 hw->mac.type, status);
87 * i40e_aq_str - convert AQ err code to a string
88 * @hw: pointer to the HW structure
89 * @aq_err: the AQ error code to convert
91 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
96 case I40E_AQ_RC_EPERM:
97 return "I40E_AQ_RC_EPERM";
98 case I40E_AQ_RC_ENOENT:
99 return "I40E_AQ_RC_ENOENT";
100 case I40E_AQ_RC_ESRCH:
101 return "I40E_AQ_RC_ESRCH";
102 case I40E_AQ_RC_EINTR:
103 return "I40E_AQ_RC_EINTR";
105 return "I40E_AQ_RC_EIO";
106 case I40E_AQ_RC_ENXIO:
107 return "I40E_AQ_RC_ENXIO";
108 case I40E_AQ_RC_E2BIG:
109 return "I40E_AQ_RC_E2BIG";
110 case I40E_AQ_RC_EAGAIN:
111 return "I40E_AQ_RC_EAGAIN";
112 case I40E_AQ_RC_ENOMEM:
113 return "I40E_AQ_RC_ENOMEM";
114 case I40E_AQ_RC_EACCES:
115 return "I40E_AQ_RC_EACCES";
116 case I40E_AQ_RC_EFAULT:
117 return "I40E_AQ_RC_EFAULT";
118 case I40E_AQ_RC_EBUSY:
119 return "I40E_AQ_RC_EBUSY";
120 case I40E_AQ_RC_EEXIST:
121 return "I40E_AQ_RC_EEXIST";
122 case I40E_AQ_RC_EINVAL:
123 return "I40E_AQ_RC_EINVAL";
124 case I40E_AQ_RC_ENOTTY:
125 return "I40E_AQ_RC_ENOTTY";
126 case I40E_AQ_RC_ENOSPC:
127 return "I40E_AQ_RC_ENOSPC";
128 case I40E_AQ_RC_ENOSYS:
129 return "I40E_AQ_RC_ENOSYS";
130 case I40E_AQ_RC_ERANGE:
131 return "I40E_AQ_RC_ERANGE";
132 case I40E_AQ_RC_EFLUSHED:
133 return "I40E_AQ_RC_EFLUSHED";
134 case I40E_AQ_RC_BAD_ADDR:
135 return "I40E_AQ_RC_BAD_ADDR";
136 case I40E_AQ_RC_EMODE:
137 return "I40E_AQ_RC_EMODE";
138 case I40E_AQ_RC_EFBIG:
139 return "I40E_AQ_RC_EFBIG";
142 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
147 * i40e_stat_str - convert status err code to a string
148 * @hw: pointer to the HW structure
149 * @stat_err: the status error code to convert
151 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
157 return "I40E_ERR_NVM";
158 case I40E_ERR_NVM_CHECKSUM:
159 return "I40E_ERR_NVM_CHECKSUM";
161 return "I40E_ERR_PHY";
162 case I40E_ERR_CONFIG:
163 return "I40E_ERR_CONFIG";
165 return "I40E_ERR_PARAM";
166 case I40E_ERR_MAC_TYPE:
167 return "I40E_ERR_MAC_TYPE";
168 case I40E_ERR_UNKNOWN_PHY:
169 return "I40E_ERR_UNKNOWN_PHY";
170 case I40E_ERR_LINK_SETUP:
171 return "I40E_ERR_LINK_SETUP";
172 case I40E_ERR_ADAPTER_STOPPED:
173 return "I40E_ERR_ADAPTER_STOPPED";
174 case I40E_ERR_INVALID_MAC_ADDR:
175 return "I40E_ERR_INVALID_MAC_ADDR";
176 case I40E_ERR_DEVICE_NOT_SUPPORTED:
177 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
178 case I40E_ERR_MASTER_REQUESTS_PENDING:
179 return "I40E_ERR_MASTER_REQUESTS_PENDING";
180 case I40E_ERR_INVALID_LINK_SETTINGS:
181 return "I40E_ERR_INVALID_LINK_SETTINGS";
182 case I40E_ERR_AUTONEG_NOT_COMPLETE:
183 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
184 case I40E_ERR_RESET_FAILED:
185 return "I40E_ERR_RESET_FAILED";
186 case I40E_ERR_SWFW_SYNC:
187 return "I40E_ERR_SWFW_SYNC";
188 case I40E_ERR_NO_AVAILABLE_VSI:
189 return "I40E_ERR_NO_AVAILABLE_VSI";
190 case I40E_ERR_NO_MEMORY:
191 return "I40E_ERR_NO_MEMORY";
192 case I40E_ERR_BAD_PTR:
193 return "I40E_ERR_BAD_PTR";
194 case I40E_ERR_RING_FULL:
195 return "I40E_ERR_RING_FULL";
196 case I40E_ERR_INVALID_PD_ID:
197 return "I40E_ERR_INVALID_PD_ID";
198 case I40E_ERR_INVALID_QP_ID:
199 return "I40E_ERR_INVALID_QP_ID";
200 case I40E_ERR_INVALID_CQ_ID:
201 return "I40E_ERR_INVALID_CQ_ID";
202 case I40E_ERR_INVALID_CEQ_ID:
203 return "I40E_ERR_INVALID_CEQ_ID";
204 case I40E_ERR_INVALID_AEQ_ID:
205 return "I40E_ERR_INVALID_AEQ_ID";
206 case I40E_ERR_INVALID_SIZE:
207 return "I40E_ERR_INVALID_SIZE";
208 case I40E_ERR_INVALID_ARP_INDEX:
209 return "I40E_ERR_INVALID_ARP_INDEX";
210 case I40E_ERR_INVALID_FPM_FUNC_ID:
211 return "I40E_ERR_INVALID_FPM_FUNC_ID";
212 case I40E_ERR_QP_INVALID_MSG_SIZE:
213 return "I40E_ERR_QP_INVALID_MSG_SIZE";
214 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
215 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
216 case I40E_ERR_INVALID_FRAG_COUNT:
217 return "I40E_ERR_INVALID_FRAG_COUNT";
218 case I40E_ERR_QUEUE_EMPTY:
219 return "I40E_ERR_QUEUE_EMPTY";
220 case I40E_ERR_INVALID_ALIGNMENT:
221 return "I40E_ERR_INVALID_ALIGNMENT";
222 case I40E_ERR_FLUSHED_QUEUE:
223 return "I40E_ERR_FLUSHED_QUEUE";
224 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
225 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
226 case I40E_ERR_INVALID_IMM_DATA_SIZE:
227 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
228 case I40E_ERR_TIMEOUT:
229 return "I40E_ERR_TIMEOUT";
230 case I40E_ERR_OPCODE_MISMATCH:
231 return "I40E_ERR_OPCODE_MISMATCH";
232 case I40E_ERR_CQP_COMPL_ERROR:
233 return "I40E_ERR_CQP_COMPL_ERROR";
234 case I40E_ERR_INVALID_VF_ID:
235 return "I40E_ERR_INVALID_VF_ID";
236 case I40E_ERR_INVALID_HMCFN_ID:
237 return "I40E_ERR_INVALID_HMCFN_ID";
238 case I40E_ERR_BACKING_PAGE_ERROR:
239 return "I40E_ERR_BACKING_PAGE_ERROR";
240 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
241 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
242 case I40E_ERR_INVALID_PBLE_INDEX:
243 return "I40E_ERR_INVALID_PBLE_INDEX";
244 case I40E_ERR_INVALID_SD_INDEX:
245 return "I40E_ERR_INVALID_SD_INDEX";
246 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
247 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
248 case I40E_ERR_INVALID_SD_TYPE:
249 return "I40E_ERR_INVALID_SD_TYPE";
250 case I40E_ERR_MEMCPY_FAILED:
251 return "I40E_ERR_MEMCPY_FAILED";
252 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
253 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
254 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
255 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
256 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
257 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
258 case I40E_ERR_SRQ_ENABLED:
259 return "I40E_ERR_SRQ_ENABLED";
260 case I40E_ERR_ADMIN_QUEUE_ERROR:
261 return "I40E_ERR_ADMIN_QUEUE_ERROR";
262 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
263 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
264 case I40E_ERR_BUF_TOO_SHORT:
265 return "I40E_ERR_BUF_TOO_SHORT";
266 case I40E_ERR_ADMIN_QUEUE_FULL:
267 return "I40E_ERR_ADMIN_QUEUE_FULL";
268 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
269 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
270 case I40E_ERR_BAD_IWARP_CQE:
271 return "I40E_ERR_BAD_IWARP_CQE";
272 case I40E_ERR_NVM_BLANK_MODE:
273 return "I40E_ERR_NVM_BLANK_MODE";
274 case I40E_ERR_NOT_IMPLEMENTED:
275 return "I40E_ERR_NOT_IMPLEMENTED";
276 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
277 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
278 case I40E_ERR_DIAG_TEST_FAILED:
279 return "I40E_ERR_DIAG_TEST_FAILED";
280 case I40E_ERR_NOT_READY:
281 return "I40E_ERR_NOT_READY";
282 case I40E_NOT_SUPPORTED:
283 return "I40E_NOT_SUPPORTED";
284 case I40E_ERR_FIRMWARE_API_VERSION:
285 return "I40E_ERR_FIRMWARE_API_VERSION";
286 case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR:
287 return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR";
290 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
296 * @hw: debug mask related to admin queue
298 * @desc: pointer to admin queue descriptor
299 * @buffer: pointer to command buffer
300 * @buf_len: max length of buffer
302 * Dumps debug log about adminq command with descriptor contents.
304 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
305 void *buffer, u16 buf_len)
307 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
308 u8 *buf = (u8 *)buffer;
312 if ((!(mask & hw->debug_mask)) || (desc == NULL))
315 len = LE16_TO_CPU(aq_desc->datalen);
318 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
319 LE16_TO_CPU(aq_desc->opcode),
320 LE16_TO_CPU(aq_desc->flags),
321 LE16_TO_CPU(aq_desc->datalen),
322 LE16_TO_CPU(aq_desc->retval));
323 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
324 LE32_TO_CPU(aq_desc->cookie_high),
325 LE32_TO_CPU(aq_desc->cookie_low));
326 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
327 LE32_TO_CPU(aq_desc->params.internal.param0),
328 LE32_TO_CPU(aq_desc->params.internal.param1));
329 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
330 LE32_TO_CPU(aq_desc->params.external.addr_high),
331 LE32_TO_CPU(aq_desc->params.external.addr_low));
333 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
334 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
337 /* write the full 16-byte chunks */
338 for (i = 0; i < (len - 16); i += 16)
340 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
341 i, buf[i], buf[i+1], buf[i+2], buf[i+3],
342 buf[i+4], buf[i+5], buf[i+6], buf[i+7],
343 buf[i+8], buf[i+9], buf[i+10], buf[i+11],
344 buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
345 /* the most we could have left is 16 bytes, pad with zeros */
351 memset(d_buf, 0, sizeof(d_buf));
352 for (j = 0; i < len; j++, i++)
355 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
356 i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
357 d_buf[4], d_buf[5], d_buf[6], d_buf[7],
358 d_buf[8], d_buf[9], d_buf[10], d_buf[11],
359 d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
365 * i40e_check_asq_alive
366 * @hw: pointer to the hw struct
368 * Returns true if Queue is enabled else false.
370 bool i40e_check_asq_alive(struct i40e_hw *hw)
376 return !!(rd32(hw, hw->aq.asq.len) &
377 I40E_PF_ATQLEN_ATQENABLE_MASK);
379 return !!(rd32(hw, hw->aq.asq.len) &
380 I40E_PF_ATQLEN_ATQENABLE_MASK);
381 #endif /* INTEGRATED_VF */
382 #endif /* PF_DRIVER */
386 return !!(rd32(hw, hw->aq.asq.len) &
387 I40E_VF_ATQLEN1_ATQENABLE_MASK);
389 return !!(rd32(hw, hw->aq.asq.len) &
390 I40E_VF_ATQLEN1_ATQENABLE_MASK);
391 #endif /* INTEGRATED_VF */
392 #endif /* VF_DRIVER */
397 * i40e_aq_queue_shutdown
398 * @hw: pointer to the hw struct
399 * @unloading: is the driver unloading itself
401 * Tell the Firmware that we're shutting down the AdminQ and whether
402 * or not the driver is unloading as well.
404 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
407 struct i40e_aq_desc desc;
408 struct i40e_aqc_queue_shutdown *cmd =
409 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
410 enum i40e_status_code status;
412 i40e_fill_default_direct_cmd_desc(&desc,
413 i40e_aqc_opc_queue_shutdown);
416 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
417 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
423 * i40e_aq_get_set_rss_lut
424 * @hw: pointer to the hardware structure
425 * @vsi_id: vsi fw index
426 * @pf_lut: for PF table set true, for VSI table set false
427 * @lut: pointer to the lut buffer provided by the caller
428 * @lut_size: size of the lut buffer
429 * @set: set true to set the table, false to get the table
431 * Internal function to get or set RSS look up table
433 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
434 u16 vsi_id, bool pf_lut,
435 u8 *lut, u16 lut_size,
438 enum i40e_status_code status;
439 struct i40e_aq_desc desc;
440 struct i40e_aqc_get_set_rss_lut *cmd_resp =
441 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
444 i40e_fill_default_direct_cmd_desc(&desc,
445 i40e_aqc_opc_set_rss_lut);
447 i40e_fill_default_direct_cmd_desc(&desc,
448 i40e_aqc_opc_get_rss_lut);
450 /* Indirect command */
451 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
452 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
455 CPU_TO_LE16((u16)((vsi_id <<
456 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
457 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
458 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
461 cmd_resp->flags |= CPU_TO_LE16((u16)
462 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
463 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
464 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
466 cmd_resp->flags |= CPU_TO_LE16((u16)
467 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
468 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
469 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
471 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
477 * i40e_aq_get_rss_lut
478 * @hw: pointer to the hardware structure
479 * @vsi_id: vsi fw index
480 * @pf_lut: for PF table set true, for VSI table set false
481 * @lut: pointer to the lut buffer provided by the caller
482 * @lut_size: size of the lut buffer
484 * get the RSS lookup table, PF or VSI type
486 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
487 bool pf_lut, u8 *lut, u16 lut_size)
489 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
494 * i40e_aq_set_rss_lut
495 * @hw: pointer to the hardware structure
496 * @vsi_id: vsi fw index
497 * @pf_lut: for PF table set true, for VSI table set false
498 * @lut: pointer to the lut buffer provided by the caller
499 * @lut_size: size of the lut buffer
501 * set the RSS lookup table, PF or VSI type
503 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
504 bool pf_lut, u8 *lut, u16 lut_size)
506 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
510 * i40e_aq_get_set_rss_key
511 * @hw: pointer to the hw struct
512 * @vsi_id: vsi fw index
513 * @key: pointer to key info struct
514 * @set: set true to set the key, false to get the key
516 * get the RSS key per VSI
518 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
520 struct i40e_aqc_get_set_rss_key_data *key,
523 enum i40e_status_code status;
524 struct i40e_aq_desc desc;
525 struct i40e_aqc_get_set_rss_key *cmd_resp =
526 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
527 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
530 i40e_fill_default_direct_cmd_desc(&desc,
531 i40e_aqc_opc_set_rss_key);
533 i40e_fill_default_direct_cmd_desc(&desc,
534 i40e_aqc_opc_get_rss_key);
536 /* Indirect command */
537 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
538 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
541 CPU_TO_LE16((u16)((vsi_id <<
542 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
543 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
544 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
546 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
552 * i40e_aq_get_rss_key
553 * @hw: pointer to the hw struct
554 * @vsi_id: vsi fw index
555 * @key: pointer to key info struct
558 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
560 struct i40e_aqc_get_set_rss_key_data *key)
562 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
566 * i40e_aq_set_rss_key
567 * @hw: pointer to the hw struct
568 * @vsi_id: vsi fw index
569 * @key: pointer to key info struct
571 * set the RSS key per VSI
573 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
575 struct i40e_aqc_get_set_rss_key_data *key)
577 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
580 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
581 * hardware to a bit-field that can be used by SW to more easily determine the
584 * Macros are used to shorten the table lines and make this table human
587 * We store the PTYPE in the top byte of the bit field - this is just so that
588 * we can check that the table doesn't have a row missing, as the index into
589 * the table should be the PTYPE.
593 * IF NOT i40e_ptype_lookup[ptype].known
596 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
597 * Use the rest of the fields to look at the tunnels, inner protocols, etc
599 * Use the enum i40e_rx_l2_ptype to decode the packet type
603 /* macro to make the table lines short */
604 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
607 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
608 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
609 I40E_RX_PTYPE_##OUTER_FRAG, \
610 I40E_RX_PTYPE_TUNNEL_##T, \
611 I40E_RX_PTYPE_TUNNEL_END_##TE, \
612 I40E_RX_PTYPE_##TEF, \
613 I40E_RX_PTYPE_INNER_PROT_##I, \
614 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
616 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
617 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
619 /* shorter macros makes the table fit but are terse */
620 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
621 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
622 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
624 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
625 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
626 /* L2 Packet types */
627 I40E_PTT_UNUSED_ENTRY(0),
628 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
629 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
630 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
631 I40E_PTT_UNUSED_ENTRY(4),
632 I40E_PTT_UNUSED_ENTRY(5),
633 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
634 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
635 I40E_PTT_UNUSED_ENTRY(8),
636 I40E_PTT_UNUSED_ENTRY(9),
637 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
638 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
639 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
640 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
641 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
642 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
643 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
644 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
645 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
646 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
647 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
648 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
650 /* Non Tunneled IPv4 */
651 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
652 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
653 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
654 I40E_PTT_UNUSED_ENTRY(25),
655 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
656 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
657 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
660 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
661 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
662 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
663 I40E_PTT_UNUSED_ENTRY(32),
664 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
665 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
666 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
669 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
670 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
671 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
672 I40E_PTT_UNUSED_ENTRY(39),
673 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
674 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
675 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
677 /* IPv4 --> GRE/NAT */
678 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
680 /* IPv4 --> GRE/NAT --> IPv4 */
681 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
682 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
683 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
684 I40E_PTT_UNUSED_ENTRY(47),
685 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
686 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
687 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
689 /* IPv4 --> GRE/NAT --> IPv6 */
690 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
691 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
692 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
693 I40E_PTT_UNUSED_ENTRY(54),
694 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
695 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
696 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
698 /* IPv4 --> GRE/NAT --> MAC */
699 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
701 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
702 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
703 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
704 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
705 I40E_PTT_UNUSED_ENTRY(62),
706 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
707 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
708 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
710 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
711 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
712 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
713 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
714 I40E_PTT_UNUSED_ENTRY(69),
715 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
716 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
717 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
719 /* IPv4 --> GRE/NAT --> MAC/VLAN */
720 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
722 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
723 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
724 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
725 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
726 I40E_PTT_UNUSED_ENTRY(77),
727 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
728 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
729 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
731 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
732 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
733 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
734 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
735 I40E_PTT_UNUSED_ENTRY(84),
736 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
737 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
738 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
740 /* Non Tunneled IPv6 */
741 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
742 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
743 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4),
744 I40E_PTT_UNUSED_ENTRY(91),
745 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
746 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
747 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
750 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
751 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
752 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
753 I40E_PTT_UNUSED_ENTRY(98),
754 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
755 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
756 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
759 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
760 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
761 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
762 I40E_PTT_UNUSED_ENTRY(105),
763 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
764 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
765 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
767 /* IPv6 --> GRE/NAT */
768 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
770 /* IPv6 --> GRE/NAT -> IPv4 */
771 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
772 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
773 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
774 I40E_PTT_UNUSED_ENTRY(113),
775 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
776 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
777 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
779 /* IPv6 --> GRE/NAT -> IPv6 */
780 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
781 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
782 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
783 I40E_PTT_UNUSED_ENTRY(120),
784 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
785 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
786 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
788 /* IPv6 --> GRE/NAT -> MAC */
789 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
791 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
792 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
793 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
794 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
795 I40E_PTT_UNUSED_ENTRY(128),
796 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
797 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
798 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
800 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
801 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
802 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
803 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
804 I40E_PTT_UNUSED_ENTRY(135),
805 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
806 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
807 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
809 /* IPv6 --> GRE/NAT -> MAC/VLAN */
810 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
812 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
813 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
814 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
815 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
816 I40E_PTT_UNUSED_ENTRY(143),
817 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
818 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
819 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
821 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
822 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
823 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
824 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
825 I40E_PTT_UNUSED_ENTRY(150),
826 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
827 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
828 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
831 I40E_PTT_UNUSED_ENTRY(154),
832 I40E_PTT_UNUSED_ENTRY(155),
833 I40E_PTT_UNUSED_ENTRY(156),
834 I40E_PTT_UNUSED_ENTRY(157),
835 I40E_PTT_UNUSED_ENTRY(158),
836 I40E_PTT_UNUSED_ENTRY(159),
838 I40E_PTT_UNUSED_ENTRY(160),
839 I40E_PTT_UNUSED_ENTRY(161),
840 I40E_PTT_UNUSED_ENTRY(162),
841 I40E_PTT_UNUSED_ENTRY(163),
842 I40E_PTT_UNUSED_ENTRY(164),
843 I40E_PTT_UNUSED_ENTRY(165),
844 I40E_PTT_UNUSED_ENTRY(166),
845 I40E_PTT_UNUSED_ENTRY(167),
846 I40E_PTT_UNUSED_ENTRY(168),
847 I40E_PTT_UNUSED_ENTRY(169),
849 I40E_PTT_UNUSED_ENTRY(170),
850 I40E_PTT_UNUSED_ENTRY(171),
851 I40E_PTT_UNUSED_ENTRY(172),
852 I40E_PTT_UNUSED_ENTRY(173),
853 I40E_PTT_UNUSED_ENTRY(174),
854 I40E_PTT_UNUSED_ENTRY(175),
855 I40E_PTT_UNUSED_ENTRY(176),
856 I40E_PTT_UNUSED_ENTRY(177),
857 I40E_PTT_UNUSED_ENTRY(178),
858 I40E_PTT_UNUSED_ENTRY(179),
860 I40E_PTT_UNUSED_ENTRY(180),
861 I40E_PTT_UNUSED_ENTRY(181),
862 I40E_PTT_UNUSED_ENTRY(182),
863 I40E_PTT_UNUSED_ENTRY(183),
864 I40E_PTT_UNUSED_ENTRY(184),
865 I40E_PTT_UNUSED_ENTRY(185),
866 I40E_PTT_UNUSED_ENTRY(186),
867 I40E_PTT_UNUSED_ENTRY(187),
868 I40E_PTT_UNUSED_ENTRY(188),
869 I40E_PTT_UNUSED_ENTRY(189),
871 I40E_PTT_UNUSED_ENTRY(190),
872 I40E_PTT_UNUSED_ENTRY(191),
873 I40E_PTT_UNUSED_ENTRY(192),
874 I40E_PTT_UNUSED_ENTRY(193),
875 I40E_PTT_UNUSED_ENTRY(194),
876 I40E_PTT_UNUSED_ENTRY(195),
877 I40E_PTT_UNUSED_ENTRY(196),
878 I40E_PTT_UNUSED_ENTRY(197),
879 I40E_PTT_UNUSED_ENTRY(198),
880 I40E_PTT_UNUSED_ENTRY(199),
882 I40E_PTT_UNUSED_ENTRY(200),
883 I40E_PTT_UNUSED_ENTRY(201),
884 I40E_PTT_UNUSED_ENTRY(202),
885 I40E_PTT_UNUSED_ENTRY(203),
886 I40E_PTT_UNUSED_ENTRY(204),
887 I40E_PTT_UNUSED_ENTRY(205),
888 I40E_PTT_UNUSED_ENTRY(206),
889 I40E_PTT_UNUSED_ENTRY(207),
890 I40E_PTT_UNUSED_ENTRY(208),
891 I40E_PTT_UNUSED_ENTRY(209),
893 I40E_PTT_UNUSED_ENTRY(210),
894 I40E_PTT_UNUSED_ENTRY(211),
895 I40E_PTT_UNUSED_ENTRY(212),
896 I40E_PTT_UNUSED_ENTRY(213),
897 I40E_PTT_UNUSED_ENTRY(214),
898 I40E_PTT_UNUSED_ENTRY(215),
899 I40E_PTT_UNUSED_ENTRY(216),
900 I40E_PTT_UNUSED_ENTRY(217),
901 I40E_PTT_UNUSED_ENTRY(218),
902 I40E_PTT_UNUSED_ENTRY(219),
904 I40E_PTT_UNUSED_ENTRY(220),
905 I40E_PTT_UNUSED_ENTRY(221),
906 I40E_PTT_UNUSED_ENTRY(222),
907 I40E_PTT_UNUSED_ENTRY(223),
908 I40E_PTT_UNUSED_ENTRY(224),
909 I40E_PTT_UNUSED_ENTRY(225),
910 I40E_PTT_UNUSED_ENTRY(226),
911 I40E_PTT_UNUSED_ENTRY(227),
912 I40E_PTT_UNUSED_ENTRY(228),
913 I40E_PTT_UNUSED_ENTRY(229),
915 I40E_PTT_UNUSED_ENTRY(230),
916 I40E_PTT_UNUSED_ENTRY(231),
917 I40E_PTT_UNUSED_ENTRY(232),
918 I40E_PTT_UNUSED_ENTRY(233),
919 I40E_PTT_UNUSED_ENTRY(234),
920 I40E_PTT_UNUSED_ENTRY(235),
921 I40E_PTT_UNUSED_ENTRY(236),
922 I40E_PTT_UNUSED_ENTRY(237),
923 I40E_PTT_UNUSED_ENTRY(238),
924 I40E_PTT_UNUSED_ENTRY(239),
926 I40E_PTT_UNUSED_ENTRY(240),
927 I40E_PTT_UNUSED_ENTRY(241),
928 I40E_PTT_UNUSED_ENTRY(242),
929 I40E_PTT_UNUSED_ENTRY(243),
930 I40E_PTT_UNUSED_ENTRY(244),
931 I40E_PTT_UNUSED_ENTRY(245),
932 I40E_PTT_UNUSED_ENTRY(246),
933 I40E_PTT_UNUSED_ENTRY(247),
934 I40E_PTT_UNUSED_ENTRY(248),
935 I40E_PTT_UNUSED_ENTRY(249),
937 I40E_PTT_UNUSED_ENTRY(250),
938 I40E_PTT_UNUSED_ENTRY(251),
939 I40E_PTT_UNUSED_ENTRY(252),
940 I40E_PTT_UNUSED_ENTRY(253),
941 I40E_PTT_UNUSED_ENTRY(254),
942 I40E_PTT_UNUSED_ENTRY(255)
947 * i40e_validate_mac_addr - Validate unicast MAC address
948 * @mac_addr: pointer to MAC address
950 * Tests a MAC address to ensure it is a valid Individual Address
952 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
954 enum i40e_status_code status = I40E_SUCCESS;
956 DEBUGFUNC("i40e_validate_mac_addr");
958 /* Broadcast addresses ARE multicast addresses
959 * Make sure it is not a multicast address
960 * Reject the zero address
962 if (I40E_IS_MULTICAST(mac_addr) ||
963 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
964 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
965 status = I40E_ERR_INVALID_MAC_ADDR;
972 * i40e_init_shared_code - Initialize the shared code
973 * @hw: pointer to hardware structure
975 * This assigns the MAC type and PHY code and inits the NVM.
976 * Does not touch the hardware. This function must be called prior to any
977 * other function in the shared code. The i40e_hw structure should be
978 * memset to 0 prior to calling this function. The following fields in
979 * hw structure should be filled in prior to calling this function:
980 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
981 * subsystem_vendor_id, and revision_id
983 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
985 enum i40e_status_code status = I40E_SUCCESS;
986 u32 port, ari, func_rid;
988 DEBUGFUNC("i40e_init_shared_code");
990 i40e_set_mac_type(hw);
992 switch (hw->mac.type) {
997 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1000 hw->phy.get_link_info = true;
1002 /* Determine port number and PF number*/
1003 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1004 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1005 hw->port = (u8)port;
1006 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1007 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1008 func_rid = rd32(hw, I40E_PF_FUNC_RID);
1010 hw->pf_id = (u8)(func_rid & 0xff);
1012 hw->pf_id = (u8)(func_rid & 0x7);
1014 if (hw->mac.type == I40E_MAC_X722)
1015 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE |
1016 I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK;
1018 status = i40e_init_nvm(hw);
1023 * i40e_aq_mac_address_read - Retrieve the MAC addresses
1024 * @hw: pointer to the hw struct
1025 * @flags: a return indicator of what addresses were added to the addr store
1026 * @addrs: the requestor's mac addr store
1027 * @cmd_details: pointer to command details structure or NULL
1029 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1031 struct i40e_aqc_mac_address_read_data *addrs,
1032 struct i40e_asq_cmd_details *cmd_details)
1034 struct i40e_aq_desc desc;
1035 struct i40e_aqc_mac_address_read *cmd_data =
1036 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1037 enum i40e_status_code status;
1039 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1040 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1042 status = i40e_asq_send_command(hw, &desc, addrs,
1043 sizeof(*addrs), cmd_details);
1044 *flags = LE16_TO_CPU(cmd_data->command_flags);
1050 * i40e_aq_mac_address_write - Change the MAC addresses
1051 * @hw: pointer to the hw struct
1052 * @flags: indicates which MAC to be written
1053 * @mac_addr: address to write
1054 * @cmd_details: pointer to command details structure or NULL
1056 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1057 u16 flags, u8 *mac_addr,
1058 struct i40e_asq_cmd_details *cmd_details)
1060 struct i40e_aq_desc desc;
1061 struct i40e_aqc_mac_address_write *cmd_data =
1062 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1063 enum i40e_status_code status;
1065 i40e_fill_default_direct_cmd_desc(&desc,
1066 i40e_aqc_opc_mac_address_write);
1067 cmd_data->command_flags = CPU_TO_LE16(flags);
1068 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1069 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1070 ((u32)mac_addr[3] << 16) |
1071 ((u32)mac_addr[4] << 8) |
1074 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1080 * i40e_get_mac_addr - get MAC address
1081 * @hw: pointer to the HW structure
1082 * @mac_addr: pointer to MAC address
1084 * Reads the adapter's MAC address from register
1086 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1088 struct i40e_aqc_mac_address_read_data addrs;
1089 enum i40e_status_code status;
1092 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1094 if (flags & I40E_AQC_LAN_ADDR_VALID)
1095 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1096 I40E_NONDMA_TO_NONDMA);
1102 * i40e_get_port_mac_addr - get Port MAC address
1103 * @hw: pointer to the HW structure
1104 * @mac_addr: pointer to Port MAC address
1106 * Reads the adapter's Port MAC address
1108 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1110 struct i40e_aqc_mac_address_read_data addrs;
1111 enum i40e_status_code status;
1114 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1118 if (flags & I40E_AQC_PORT_ADDR_VALID)
1119 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1120 I40E_NONDMA_TO_NONDMA);
1122 status = I40E_ERR_INVALID_MAC_ADDR;
1128 * i40e_pre_tx_queue_cfg - pre tx queue configure
1129 * @hw: pointer to the HW structure
1130 * @queue: target pf queue index
1131 * @enable: state change request
1133 * Handles hw requirement to indicate intention to enable
1134 * or disable target queue.
1136 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1138 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1142 if (abs_queue_idx >= 128) {
1143 reg_block = abs_queue_idx / 128;
1144 abs_queue_idx %= 128;
1147 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1148 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1149 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1152 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1154 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1156 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1160 * i40e_get_san_mac_addr - get SAN MAC address
1161 * @hw: pointer to the HW structure
1162 * @mac_addr: pointer to SAN MAC address
1164 * Reads the adapter's SAN MAC address from NVM
1166 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1169 struct i40e_aqc_mac_address_read_data addrs;
1170 enum i40e_status_code status;
1173 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1177 if (flags & I40E_AQC_SAN_ADDR_VALID)
1178 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac),
1179 I40E_NONDMA_TO_NONDMA);
1181 status = I40E_ERR_INVALID_MAC_ADDR;
1187 * i40e_read_pba_string - Reads part number string from EEPROM
1188 * @hw: pointer to hardware structure
1189 * @pba_num: stores the part number string from the EEPROM
1190 * @pba_num_size: part number string buffer length
1192 * Reads the part number string from the EEPROM.
1194 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1197 enum i40e_status_code status = I40E_SUCCESS;
1203 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1204 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1205 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1209 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1210 if (status != I40E_SUCCESS) {
1211 DEBUGOUT("Failed to read PBA Block pointer.\n");
1215 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1216 if (status != I40E_SUCCESS) {
1217 DEBUGOUT("Failed to read PBA Block size.\n");
1221 /* Subtract one to get PBA word count (PBA Size word is included in
1225 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1226 DEBUGOUT("Buffer to small for PBA data.\n");
1227 return I40E_ERR_PARAM;
1230 for (i = 0; i < pba_size; i++) {
1231 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1232 if (status != I40E_SUCCESS) {
1233 DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1237 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1238 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1240 pba_num[(pba_size * 2)] = '\0';
1246 * i40e_get_media_type - Gets media type
1247 * @hw: pointer to the hardware structure
1249 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1251 enum i40e_media_type media;
1253 switch (hw->phy.link_info.phy_type) {
1254 case I40E_PHY_TYPE_10GBASE_SR:
1255 case I40E_PHY_TYPE_10GBASE_LR:
1256 case I40E_PHY_TYPE_1000BASE_SX:
1257 case I40E_PHY_TYPE_1000BASE_LX:
1258 case I40E_PHY_TYPE_40GBASE_SR4:
1259 case I40E_PHY_TYPE_40GBASE_LR4:
1260 case I40E_PHY_TYPE_25GBASE_LR:
1261 case I40E_PHY_TYPE_25GBASE_SR:
1262 media = I40E_MEDIA_TYPE_FIBER;
1264 case I40E_PHY_TYPE_100BASE_TX:
1265 case I40E_PHY_TYPE_1000BASE_T:
1266 #ifdef CARLSVILLE_HW
1267 case I40E_PHY_TYPE_2_5GBASE_T:
1268 case I40E_PHY_TYPE_5GBASE_T:
1270 case I40E_PHY_TYPE_10GBASE_T:
1271 media = I40E_MEDIA_TYPE_BASET;
1273 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1274 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1275 case I40E_PHY_TYPE_10GBASE_CR1:
1276 case I40E_PHY_TYPE_40GBASE_CR4:
1277 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1278 case I40E_PHY_TYPE_40GBASE_AOC:
1279 case I40E_PHY_TYPE_10GBASE_AOC:
1280 case I40E_PHY_TYPE_25GBASE_CR:
1281 case I40E_PHY_TYPE_25GBASE_AOC:
1282 case I40E_PHY_TYPE_25GBASE_ACC:
1283 media = I40E_MEDIA_TYPE_DA;
1285 case I40E_PHY_TYPE_1000BASE_KX:
1286 case I40E_PHY_TYPE_10GBASE_KX4:
1287 case I40E_PHY_TYPE_10GBASE_KR:
1288 case I40E_PHY_TYPE_40GBASE_KR4:
1289 case I40E_PHY_TYPE_20GBASE_KR2:
1290 case I40E_PHY_TYPE_25GBASE_KR:
1291 media = I40E_MEDIA_TYPE_BACKPLANE;
1293 case I40E_PHY_TYPE_SGMII:
1294 case I40E_PHY_TYPE_XAUI:
1295 case I40E_PHY_TYPE_XFI:
1296 case I40E_PHY_TYPE_XLAUI:
1297 case I40E_PHY_TYPE_XLPPI:
1299 media = I40E_MEDIA_TYPE_UNKNOWN;
1307 * i40e_poll_globr - Poll for Global Reset completion
1308 * @hw: pointer to the hardware structure
1309 * @retry_limit: how many times to retry before failure
1311 STATIC enum i40e_status_code i40e_poll_globr(struct i40e_hw *hw,
1316 for (cnt = 0; cnt < retry_limit; cnt++) {
1317 reg = rd32(hw, I40E_GLGEN_RSTAT);
1318 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1319 return I40E_SUCCESS;
1320 i40e_msec_delay(100);
1323 DEBUGOUT("Global reset failed.\n");
1324 DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg);
1326 return I40E_ERR_RESET_FAILED;
1329 #define I40E_PF_RESET_WAIT_COUNT 200
1331 * i40e_pf_reset - Reset the PF
1332 * @hw: pointer to the hardware structure
1334 * Assuming someone else has triggered a global reset,
1335 * assure the global reset is complete and then reset the PF
1337 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1344 /* Poll for Global Reset steady state in case of recent GRST.
1345 * The grst delay value is in 100ms units, and we'll wait a
1346 * couple counts longer to be sure we don't just miss the end.
1348 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1349 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1350 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1352 grst_del = min(grst_del * 20, 160U);
1354 for (cnt = 0; cnt < grst_del; cnt++) {
1355 reg = rd32(hw, I40E_GLGEN_RSTAT);
1356 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1358 i40e_msec_delay(100);
1360 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1361 DEBUGOUT("Global reset polling failed to complete.\n");
1362 return I40E_ERR_RESET_FAILED;
1365 /* Now Wait for the FW to be ready */
1366 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1367 reg = rd32(hw, I40E_GLNVM_ULD);
1368 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1369 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1370 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1371 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1372 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1375 i40e_msec_delay(10);
1377 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1378 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1379 DEBUGOUT("wait for FW Reset complete timedout\n");
1380 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1381 return I40E_ERR_RESET_FAILED;
1384 /* If there was a Global Reset in progress when we got here,
1385 * we don't need to do the PF Reset
1390 reg = rd32(hw, I40E_PFGEN_CTRL);
1391 wr32(hw, I40E_PFGEN_CTRL,
1392 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1393 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1394 reg = rd32(hw, I40E_PFGEN_CTRL);
1395 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1397 reg2 = rd32(hw, I40E_GLGEN_RSTAT);
1398 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK)
1402 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1403 if (i40e_poll_globr(hw, grst_del) != I40E_SUCCESS)
1404 return I40E_ERR_RESET_FAILED;
1405 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1406 DEBUGOUT("PF reset polling failed to complete.\n");
1407 return I40E_ERR_RESET_FAILED;
1411 i40e_clear_pxe_mode(hw);
1414 return I40E_SUCCESS;
1418 * i40e_clear_hw - clear out any left over hw state
1419 * @hw: pointer to the hw struct
1421 * Clear queues and interrupts, typically called at init time,
1422 * but after the capabilities have been found so we know how many
1423 * queues and msix vectors have been allocated.
1425 void i40e_clear_hw(struct i40e_hw *hw)
1427 u32 num_queues, base_queue;
1435 /* get number of interrupts, queues, and vfs */
1436 val = rd32(hw, I40E_GLPCI_CNF2);
1437 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1438 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1439 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1440 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1442 val = rd32(hw, I40E_PFLAN_QALLOC);
1443 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1444 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1445 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1446 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1447 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1448 num_queues = (j - base_queue) + 1;
1452 val = rd32(hw, I40E_PF_VT_PFALLOC);
1453 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1454 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1455 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1456 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1457 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1458 num_vfs = (j - i) + 1;
1462 /* stop all the interrupts */
1463 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1464 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1465 for (i = 0; i < num_pf_int - 2; i++)
1466 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1468 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1469 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1470 wr32(hw, I40E_PFINT_LNKLST0, val);
1471 for (i = 0; i < num_pf_int - 2; i++)
1472 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1473 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1474 for (i = 0; i < num_vfs; i++)
1475 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1476 for (i = 0; i < num_vf_int - 2; i++)
1477 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1479 /* warn the HW of the coming Tx disables */
1480 for (i = 0; i < num_queues; i++) {
1481 u32 abs_queue_idx = base_queue + i;
1484 if (abs_queue_idx >= 128) {
1485 reg_block = abs_queue_idx / 128;
1486 abs_queue_idx %= 128;
1489 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1490 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1491 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1492 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1494 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1496 i40e_usec_delay(400);
1498 /* stop all the queues */
1499 for (i = 0; i < num_queues; i++) {
1500 wr32(hw, I40E_QINT_TQCTL(i), 0);
1501 wr32(hw, I40E_QTX_ENA(i), 0);
1502 wr32(hw, I40E_QINT_RQCTL(i), 0);
1503 wr32(hw, I40E_QRX_ENA(i), 0);
1506 /* short wait for all queue disables to settle */
1507 i40e_usec_delay(50);
1511 * i40e_clear_pxe_mode - clear pxe operations mode
1512 * @hw: pointer to the hw struct
1514 * Make sure all PXE mode settings are cleared, including things
1515 * like descriptor fetch/write-back mode.
1517 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1519 if (i40e_check_asq_alive(hw))
1520 i40e_aq_clear_pxe_mode(hw, NULL);
1524 * i40e_led_is_mine - helper to find matching led
1525 * @hw: pointer to the hw struct
1526 * @idx: index into GPIO registers
1528 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1530 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1535 if (!hw->func_caps.led[idx])
1538 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1539 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1540 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1542 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1543 * if it is not our port then ignore
1545 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1552 #define I40E_COMBINED_ACTIVITY 0xA
1553 #define I40E_FILTER_ACTIVITY 0xE
1554 #define I40E_LINK_ACTIVITY 0xC
1555 #define I40E_MAC_ACTIVITY 0xD
1556 #define I40E_LED0 22
1559 * i40e_led_get - return current on/off mode
1560 * @hw: pointer to the hw struct
1562 * The value returned is the 'mode' field as defined in the
1563 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1564 * values are variations of possible behaviors relating to
1565 * blink, link, and wire.
1567 u32 i40e_led_get(struct i40e_hw *hw)
1569 u32 current_mode = 0;
1573 /* as per the documentation GPIO 22-29 are the LED
1574 * GPIO pins named LED0..LED7
1576 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1577 u32 gpio_val = i40e_led_is_mine(hw, i);
1582 /* ignore gpio LED src mode entries related to the activity
1585 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1586 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1587 switch (current_mode) {
1588 case I40E_COMBINED_ACTIVITY:
1589 case I40E_FILTER_ACTIVITY:
1590 case I40E_MAC_ACTIVITY:
1591 case I40E_LINK_ACTIVITY:
1597 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1598 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1606 * i40e_led_set - set new on/off mode
1607 * @hw: pointer to the hw struct
1608 * @mode: 0=off, 0xf=on (else see manual for mode details)
1609 * @blink: true if the LED should blink when on, false if steady
1611 * if this function is used to turn on the blink it should
1612 * be used to disable the blink when restoring the original state.
1614 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1616 u32 current_mode = 0;
1619 if (mode & 0xfffffff0)
1620 DEBUGOUT1("invalid mode passed in %X\n", mode);
1622 /* as per the documentation GPIO 22-29 are the LED
1623 * GPIO pins named LED0..LED7
1625 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1626 u32 gpio_val = i40e_led_is_mine(hw, i);
1631 /* ignore gpio LED src mode entries related to the activity
1634 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1635 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1636 switch (current_mode) {
1637 case I40E_COMBINED_ACTIVITY:
1638 case I40E_FILTER_ACTIVITY:
1639 case I40E_MAC_ACTIVITY:
1640 case I40E_LINK_ACTIVITY:
1646 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1647 /* this & is a bit of paranoia, but serves as a range check */
1648 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1649 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1652 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1654 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1656 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1661 /* Admin command wrappers */
1664 * i40e_aq_get_phy_capabilities
1665 * @hw: pointer to the hw struct
1666 * @abilities: structure for PHY capabilities to be filled
1667 * @qualified_modules: report Qualified Modules
1668 * @report_init: report init capabilities (active are default)
1669 * @cmd_details: pointer to command details structure or NULL
1671 * Returns the various PHY abilities supported on the Port.
1673 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1674 bool qualified_modules, bool report_init,
1675 struct i40e_aq_get_phy_abilities_resp *abilities,
1676 struct i40e_asq_cmd_details *cmd_details)
1678 struct i40e_aq_desc desc;
1679 enum i40e_status_code status;
1680 u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0;
1681 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1684 return I40E_ERR_PARAM;
1687 i40e_fill_default_direct_cmd_desc(&desc,
1688 i40e_aqc_opc_get_phy_abilities);
1690 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1691 if (abilities_size > I40E_AQ_LARGE_BUF)
1692 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1694 if (qualified_modules)
1695 desc.params.external.param0 |=
1696 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1699 desc.params.external.param0 |=
1700 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1702 status = i40e_asq_send_command(hw, &desc, abilities,
1703 abilities_size, cmd_details);
1705 if (status != I40E_SUCCESS)
1708 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) {
1709 status = I40E_ERR_UNKNOWN_PHY;
1711 } else if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) {
1714 status = I40E_ERR_TIMEOUT;
1716 } while ((hw->aq.asq_last_status != I40E_AQ_RC_OK) &&
1717 (total_delay < max_delay));
1719 if (status != I40E_SUCCESS)
1723 if (hw->mac.type == I40E_MAC_XL710 &&
1724 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1725 hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
1726 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1728 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1729 hw->phy.phy_types |=
1730 ((u64)abilities->phy_type_ext << 32);
1738 * i40e_aq_set_phy_config
1739 * @hw: pointer to the hw struct
1740 * @config: structure with PHY configuration to be set
1741 * @cmd_details: pointer to command details structure or NULL
1743 * Set the various PHY configuration parameters
1744 * supported on the Port.One or more of the Set PHY config parameters may be
1745 * ignored in an MFP mode as the PF may not have the privilege to set some
1746 * of the PHY Config parameters. This status will be indicated by the
1749 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1750 struct i40e_aq_set_phy_config *config,
1751 struct i40e_asq_cmd_details *cmd_details)
1753 struct i40e_aq_desc desc;
1754 struct i40e_aq_set_phy_config *cmd =
1755 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1756 enum i40e_status_code status;
1759 return I40E_ERR_PARAM;
1761 i40e_fill_default_direct_cmd_desc(&desc,
1762 i40e_aqc_opc_set_phy_config);
1766 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1773 * @hw: pointer to the hw struct
1774 * @aq_failures: buffer to return AdminQ failure information
1775 * @atomic_restart: whether to enable atomic link restart
1777 * Set the requested flow control mode using set_phy_config.
1779 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1780 bool atomic_restart)
1782 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1783 struct i40e_aq_get_phy_abilities_resp abilities;
1784 struct i40e_aq_set_phy_config config;
1785 enum i40e_status_code status;
1786 u8 pause_mask = 0x0;
1792 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1793 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1795 case I40E_FC_RX_PAUSE:
1796 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1798 case I40E_FC_TX_PAUSE:
1799 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1805 /* Get the current phy config */
1806 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1809 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1813 memset(&config, 0, sizeof(config));
1814 /* clear the old pause settings */
1815 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1816 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1817 /* set the new abilities */
1818 config.abilities |= pause_mask;
1819 /* If the abilities have changed, then set the new config */
1820 if (config.abilities != abilities.abilities) {
1821 /* Auto restart link so settings take effect */
1823 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1824 /* Copy over all the old settings */
1825 config.phy_type = abilities.phy_type;
1826 config.phy_type_ext = abilities.phy_type_ext;
1827 config.link_speed = abilities.link_speed;
1828 config.eee_capability = abilities.eee_capability;
1829 config.eeer = abilities.eeer_val;
1830 config.low_power_ctrl = abilities.d3_lpan;
1831 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1832 I40E_AQ_PHY_FEC_CONFIG_MASK;
1833 status = i40e_aq_set_phy_config(hw, &config, NULL);
1836 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1838 /* Update the link info */
1839 status = i40e_update_link_info(hw);
1841 /* Wait a little bit (on 40G cards it sometimes takes a really
1842 * long time for link to come back from the atomic reset)
1845 i40e_msec_delay(1000);
1846 status = i40e_update_link_info(hw);
1849 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1855 * i40e_aq_set_mac_config
1856 * @hw: pointer to the hw struct
1857 * @max_frame_size: Maximum Frame Size to be supported by the port
1858 * @crc_en: Tell HW to append a CRC to outgoing frames
1859 * @pacing: Pacing configurations
1860 * @cmd_details: pointer to command details structure or NULL
1862 * Configure MAC settings for frame size, jumbo frame support and the
1863 * addition of a CRC by the hardware.
1865 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1867 bool crc_en, u16 pacing,
1868 struct i40e_asq_cmd_details *cmd_details)
1870 struct i40e_aq_desc desc;
1871 struct i40e_aq_set_mac_config *cmd =
1872 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1873 enum i40e_status_code status;
1875 if (max_frame_size == 0)
1876 return I40E_ERR_PARAM;
1878 i40e_fill_default_direct_cmd_desc(&desc,
1879 i40e_aqc_opc_set_mac_config);
1881 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1882 cmd->params = ((u8)pacing & 0x0F) << 3;
1884 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1886 #define I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD 0x7FFF
1887 cmd->fc_refresh_threshold =
1888 CPU_TO_LE16(I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD);
1890 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1896 * i40e_aq_clear_pxe_mode
1897 * @hw: pointer to the hw struct
1898 * @cmd_details: pointer to command details structure or NULL
1900 * Tell the firmware that the driver is taking over from PXE
1902 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1903 struct i40e_asq_cmd_details *cmd_details)
1905 enum i40e_status_code status;
1906 struct i40e_aq_desc desc;
1907 struct i40e_aqc_clear_pxe *cmd =
1908 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1910 i40e_fill_default_direct_cmd_desc(&desc,
1911 i40e_aqc_opc_clear_pxe_mode);
1915 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1917 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1923 * i40e_aq_set_link_restart_an
1924 * @hw: pointer to the hw struct
1925 * @enable_link: if true: enable link, if false: disable link
1926 * @cmd_details: pointer to command details structure or NULL
1928 * Sets up the link and restarts the Auto-Negotiation over the link.
1930 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1931 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1933 struct i40e_aq_desc desc;
1934 struct i40e_aqc_set_link_restart_an *cmd =
1935 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1936 enum i40e_status_code status;
1938 i40e_fill_default_direct_cmd_desc(&desc,
1939 i40e_aqc_opc_set_link_restart_an);
1941 cmd->command = I40E_AQ_PHY_RESTART_AN;
1943 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1945 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1947 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1953 * i40e_aq_get_link_info
1954 * @hw: pointer to the hw struct
1955 * @enable_lse: enable/disable LinkStatusEvent reporting
1956 * @link: pointer to link status structure - optional
1957 * @cmd_details: pointer to command details structure or NULL
1959 * Returns the link status of the adapter.
1961 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1962 bool enable_lse, struct i40e_link_status *link,
1963 struct i40e_asq_cmd_details *cmd_details)
1965 struct i40e_aq_desc desc;
1966 struct i40e_aqc_get_link_status *resp =
1967 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1968 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1969 enum i40e_status_code status;
1970 bool tx_pause, rx_pause;
1973 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1976 command_flags = I40E_AQ_LSE_ENABLE;
1978 command_flags = I40E_AQ_LSE_DISABLE;
1979 resp->command_flags = CPU_TO_LE16(command_flags);
1981 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1983 if (status != I40E_SUCCESS)
1984 goto aq_get_link_info_exit;
1986 /* save off old link status information */
1987 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1988 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1990 /* update link status */
1991 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1992 hw->phy.media_type = i40e_get_media_type(hw);
1993 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1994 hw_link_info->link_info = resp->link_info;
1995 hw_link_info->an_info = resp->an_info;
1996 hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
1997 I40E_AQ_CONFIG_FEC_RS_ENA);
1998 hw_link_info->ext_info = resp->ext_info;
1999 hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
2000 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
2001 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
2003 /* update fc info */
2004 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
2005 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
2006 if (tx_pause & rx_pause)
2007 hw->fc.current_mode = I40E_FC_FULL;
2009 hw->fc.current_mode = I40E_FC_TX_PAUSE;
2011 hw->fc.current_mode = I40E_FC_RX_PAUSE;
2013 hw->fc.current_mode = I40E_FC_NONE;
2015 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
2016 hw_link_info->crc_enable = true;
2018 hw_link_info->crc_enable = false;
2020 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
2021 hw_link_info->lse_enable = true;
2023 hw_link_info->lse_enable = false;
2025 if ((hw->mac.type == I40E_MAC_XL710) &&
2026 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
2027 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
2028 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
2030 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
2031 hw->aq.api_min_ver >= 7) {
2034 i40e_memcpy(&tmp, resp->link_type, sizeof(tmp),
2035 I40E_NONDMA_TO_NONDMA);
2036 hw->phy.phy_types = LE32_TO_CPU(tmp);
2037 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
2040 /* save link status information */
2042 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
2043 I40E_NONDMA_TO_NONDMA);
2045 /* flag cleared so helper functions don't call AQ again */
2046 hw->phy.get_link_info = false;
2048 aq_get_link_info_exit:
2053 * i40e_aq_set_phy_int_mask
2054 * @hw: pointer to the hw struct
2055 * @mask: interrupt mask to be set
2056 * @cmd_details: pointer to command details structure or NULL
2058 * Set link interrupt mask.
2060 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2062 struct i40e_asq_cmd_details *cmd_details)
2064 struct i40e_aq_desc desc;
2065 struct i40e_aqc_set_phy_int_mask *cmd =
2066 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2067 enum i40e_status_code status;
2069 i40e_fill_default_direct_cmd_desc(&desc,
2070 i40e_aqc_opc_set_phy_int_mask);
2072 cmd->event_mask = CPU_TO_LE16(mask);
2074 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2080 * i40e_aq_get_local_advt_reg
2081 * @hw: pointer to the hw struct
2082 * @advt_reg: local AN advertisement register value
2083 * @cmd_details: pointer to command details structure or NULL
2085 * Get the Local AN advertisement register value.
2087 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2089 struct i40e_asq_cmd_details *cmd_details)
2091 struct i40e_aq_desc desc;
2092 struct i40e_aqc_an_advt_reg *resp =
2093 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2094 enum i40e_status_code status;
2096 i40e_fill_default_direct_cmd_desc(&desc,
2097 i40e_aqc_opc_get_local_advt_reg);
2099 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2101 if (status != I40E_SUCCESS)
2102 goto aq_get_local_advt_reg_exit;
2104 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2105 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2107 aq_get_local_advt_reg_exit:
2112 * i40e_aq_set_local_advt_reg
2113 * @hw: pointer to the hw struct
2114 * @advt_reg: local AN advertisement register value
2115 * @cmd_details: pointer to command details structure or NULL
2117 * Get the Local AN advertisement register value.
2119 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2121 struct i40e_asq_cmd_details *cmd_details)
2123 struct i40e_aq_desc desc;
2124 struct i40e_aqc_an_advt_reg *cmd =
2125 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2126 enum i40e_status_code status;
2128 i40e_fill_default_direct_cmd_desc(&desc,
2129 i40e_aqc_opc_get_local_advt_reg);
2131 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2132 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2134 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2140 * i40e_aq_get_partner_advt
2141 * @hw: pointer to the hw struct
2142 * @advt_reg: AN partner advertisement register value
2143 * @cmd_details: pointer to command details structure or NULL
2145 * Get the link partner AN advertisement register value.
2147 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2149 struct i40e_asq_cmd_details *cmd_details)
2151 struct i40e_aq_desc desc;
2152 struct i40e_aqc_an_advt_reg *resp =
2153 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2154 enum i40e_status_code status;
2156 i40e_fill_default_direct_cmd_desc(&desc,
2157 i40e_aqc_opc_get_partner_advt);
2159 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2161 if (status != I40E_SUCCESS)
2162 goto aq_get_partner_advt_exit;
2164 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2165 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2167 aq_get_partner_advt_exit:
2172 * i40e_aq_set_lb_modes
2173 * @hw: pointer to the hw struct
2174 * @lb_modes: loopback mode to be set
2175 * @cmd_details: pointer to command details structure or NULL
2177 * Sets loopback modes.
2179 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2181 struct i40e_asq_cmd_details *cmd_details)
2183 struct i40e_aq_desc desc;
2184 struct i40e_aqc_set_lb_mode *cmd =
2185 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2186 enum i40e_status_code status;
2188 i40e_fill_default_direct_cmd_desc(&desc,
2189 i40e_aqc_opc_set_lb_modes);
2191 cmd->lb_mode = CPU_TO_LE16(lb_modes);
2193 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2199 * i40e_aq_set_phy_debug
2200 * @hw: pointer to the hw struct
2201 * @cmd_flags: debug command flags
2202 * @cmd_details: pointer to command details structure or NULL
2204 * Reset the external PHY.
2206 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2207 struct i40e_asq_cmd_details *cmd_details)
2209 struct i40e_aq_desc desc;
2210 struct i40e_aqc_set_phy_debug *cmd =
2211 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2212 enum i40e_status_code status;
2214 i40e_fill_default_direct_cmd_desc(&desc,
2215 i40e_aqc_opc_set_phy_debug);
2217 cmd->command_flags = cmd_flags;
2219 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2226 * @hw: pointer to the hw struct
2227 * @vsi_ctx: pointer to a vsi context struct
2228 * @cmd_details: pointer to command details structure or NULL
2230 * Add a VSI context to the hardware.
2232 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2233 struct i40e_vsi_context *vsi_ctx,
2234 struct i40e_asq_cmd_details *cmd_details)
2236 struct i40e_aq_desc desc;
2237 struct i40e_aqc_add_get_update_vsi *cmd =
2238 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2239 struct i40e_aqc_add_get_update_vsi_completion *resp =
2240 (struct i40e_aqc_add_get_update_vsi_completion *)
2242 enum i40e_status_code status;
2244 i40e_fill_default_direct_cmd_desc(&desc,
2245 i40e_aqc_opc_add_vsi);
2247 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2248 cmd->connection_type = vsi_ctx->connection_type;
2249 cmd->vf_id = vsi_ctx->vf_num;
2250 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2252 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2254 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2255 sizeof(vsi_ctx->info), cmd_details);
2257 if (status != I40E_SUCCESS)
2258 goto aq_add_vsi_exit;
2260 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2261 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2262 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2263 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2270 * i40e_aq_set_default_vsi
2271 * @hw: pointer to the hw struct
2273 * @cmd_details: pointer to command details structure or NULL
2275 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2277 struct i40e_asq_cmd_details *cmd_details)
2279 struct i40e_aq_desc desc;
2280 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2281 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2283 enum i40e_status_code status;
2285 i40e_fill_default_direct_cmd_desc(&desc,
2286 i40e_aqc_opc_set_vsi_promiscuous_modes);
2288 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2289 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2290 cmd->seid = CPU_TO_LE16(seid);
2292 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2298 * i40e_aq_clear_default_vsi
2299 * @hw: pointer to the hw struct
2301 * @cmd_details: pointer to command details structure or NULL
2303 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2305 struct i40e_asq_cmd_details *cmd_details)
2307 struct i40e_aq_desc desc;
2308 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2309 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2311 enum i40e_status_code status;
2313 i40e_fill_default_direct_cmd_desc(&desc,
2314 i40e_aqc_opc_set_vsi_promiscuous_modes);
2316 cmd->promiscuous_flags = CPU_TO_LE16(0);
2317 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2318 cmd->seid = CPU_TO_LE16(seid);
2320 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2326 * i40e_aq_set_vsi_unicast_promiscuous
2327 * @hw: pointer to the hw struct
2329 * @set: set unicast promiscuous enable/disable
2330 * @cmd_details: pointer to command details structure or NULL
2331 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2333 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2335 struct i40e_asq_cmd_details *cmd_details,
2336 bool rx_only_promisc)
2338 struct i40e_aq_desc desc;
2339 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2340 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2341 enum i40e_status_code status;
2344 i40e_fill_default_direct_cmd_desc(&desc,
2345 i40e_aqc_opc_set_vsi_promiscuous_modes);
2348 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2349 if (rx_only_promisc &&
2350 (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2351 (hw->aq.api_maj_ver > 1)))
2352 flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2355 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2357 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2358 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2359 (hw->aq.api_maj_ver > 1))
2360 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2362 cmd->seid = CPU_TO_LE16(seid);
2363 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2369 * i40e_aq_set_vsi_multicast_promiscuous
2370 * @hw: pointer to the hw struct
2372 * @set: set multicast promiscuous enable/disable
2373 * @cmd_details: pointer to command details structure or NULL
2375 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2376 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2378 struct i40e_aq_desc desc;
2379 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2380 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2381 enum i40e_status_code status;
2384 i40e_fill_default_direct_cmd_desc(&desc,
2385 i40e_aqc_opc_set_vsi_promiscuous_modes);
2388 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2390 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2392 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2394 cmd->seid = CPU_TO_LE16(seid);
2395 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2401 * i40e_aq_set_vsi_full_promiscuous
2402 * @hw: pointer to the hw struct
2404 * @set: set promiscuous enable/disable
2405 * @cmd_details: pointer to command details structure or NULL
2407 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw,
2409 struct i40e_asq_cmd_details *cmd_details)
2411 struct i40e_aq_desc desc;
2412 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2413 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2414 enum i40e_status_code status;
2417 i40e_fill_default_direct_cmd_desc(&desc,
2418 i40e_aqc_opc_set_vsi_promiscuous_modes);
2421 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST |
2422 I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2423 I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2425 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2427 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST |
2428 I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2429 I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2431 cmd->seid = CPU_TO_LE16(seid);
2432 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2438 * i40e_aq_set_vsi_mc_promisc_on_vlan
2439 * @hw: pointer to the hw struct
2441 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2442 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2443 * @cmd_details: pointer to command details structure or NULL
2445 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2446 u16 seid, bool enable, u16 vid,
2447 struct i40e_asq_cmd_details *cmd_details)
2449 struct i40e_aq_desc desc;
2450 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2451 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2452 enum i40e_status_code status;
2455 i40e_fill_default_direct_cmd_desc(&desc,
2456 i40e_aqc_opc_set_vsi_promiscuous_modes);
2459 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2461 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2462 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2463 cmd->seid = CPU_TO_LE16(seid);
2464 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2466 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2472 * i40e_aq_set_vsi_uc_promisc_on_vlan
2473 * @hw: pointer to the hw struct
2475 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2476 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2477 * @cmd_details: pointer to command details structure or NULL
2479 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2480 u16 seid, bool enable, u16 vid,
2481 struct i40e_asq_cmd_details *cmd_details)
2483 struct i40e_aq_desc desc;
2484 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2485 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2486 enum i40e_status_code status;
2489 i40e_fill_default_direct_cmd_desc(&desc,
2490 i40e_aqc_opc_set_vsi_promiscuous_modes);
2493 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2495 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2496 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2497 cmd->seid = CPU_TO_LE16(seid);
2498 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2500 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2506 * i40e_aq_set_vsi_bc_promisc_on_vlan
2507 * @hw: pointer to the hw struct
2509 * @enable: set broadcast promiscuous enable/disable for a given VLAN
2510 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2511 * @cmd_details: pointer to command details structure or NULL
2513 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2514 u16 seid, bool enable, u16 vid,
2515 struct i40e_asq_cmd_details *cmd_details)
2517 struct i40e_aq_desc desc;
2518 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2519 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2520 enum i40e_status_code status;
2523 i40e_fill_default_direct_cmd_desc(&desc,
2524 i40e_aqc_opc_set_vsi_promiscuous_modes);
2527 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2529 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2530 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2531 cmd->seid = CPU_TO_LE16(seid);
2532 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2534 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2540 * i40e_aq_set_vsi_broadcast
2541 * @hw: pointer to the hw struct
2543 * @set_filter: true to set filter, false to clear filter
2544 * @cmd_details: pointer to command details structure or NULL
2546 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2548 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2549 u16 seid, bool set_filter,
2550 struct i40e_asq_cmd_details *cmd_details)
2552 struct i40e_aq_desc desc;
2553 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2554 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2555 enum i40e_status_code status;
2557 i40e_fill_default_direct_cmd_desc(&desc,
2558 i40e_aqc_opc_set_vsi_promiscuous_modes);
2561 cmd->promiscuous_flags
2562 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2564 cmd->promiscuous_flags
2565 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2567 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2568 cmd->seid = CPU_TO_LE16(seid);
2569 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2575 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2576 * @hw: pointer to the hw struct
2578 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2579 * @cmd_details: pointer to command details structure or NULL
2581 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2582 u16 seid, bool enable,
2583 struct i40e_asq_cmd_details *cmd_details)
2585 struct i40e_aq_desc desc;
2586 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2587 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2588 enum i40e_status_code status;
2591 i40e_fill_default_direct_cmd_desc(&desc,
2592 i40e_aqc_opc_set_vsi_promiscuous_modes);
2594 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2596 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2597 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2598 cmd->seid = CPU_TO_LE16(seid);
2600 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2606 * i40e_get_vsi_params - get VSI configuration info
2607 * @hw: pointer to the hw struct
2608 * @vsi_ctx: pointer to a vsi context struct
2609 * @cmd_details: pointer to command details structure or NULL
2611 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2612 struct i40e_vsi_context *vsi_ctx,
2613 struct i40e_asq_cmd_details *cmd_details)
2615 struct i40e_aq_desc desc;
2616 struct i40e_aqc_add_get_update_vsi *cmd =
2617 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2618 struct i40e_aqc_add_get_update_vsi_completion *resp =
2619 (struct i40e_aqc_add_get_update_vsi_completion *)
2621 enum i40e_status_code status;
2623 UNREFERENCED_1PARAMETER(cmd_details);
2624 i40e_fill_default_direct_cmd_desc(&desc,
2625 i40e_aqc_opc_get_vsi_parameters);
2627 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2629 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2631 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2632 sizeof(vsi_ctx->info), NULL);
2634 if (status != I40E_SUCCESS)
2635 goto aq_get_vsi_params_exit;
2637 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2638 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2639 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2640 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2642 aq_get_vsi_params_exit:
2647 * i40e_aq_update_vsi_params
2648 * @hw: pointer to the hw struct
2649 * @vsi_ctx: pointer to a vsi context struct
2650 * @cmd_details: pointer to command details structure or NULL
2652 * Update a VSI context.
2654 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2655 struct i40e_vsi_context *vsi_ctx,
2656 struct i40e_asq_cmd_details *cmd_details)
2658 struct i40e_aq_desc desc;
2659 struct i40e_aqc_add_get_update_vsi *cmd =
2660 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2661 struct i40e_aqc_add_get_update_vsi_completion *resp =
2662 (struct i40e_aqc_add_get_update_vsi_completion *)
2664 enum i40e_status_code status;
2666 i40e_fill_default_direct_cmd_desc(&desc,
2667 i40e_aqc_opc_update_vsi_parameters);
2668 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2670 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2672 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2673 sizeof(vsi_ctx->info), cmd_details);
2675 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2676 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2682 * i40e_aq_get_switch_config
2683 * @hw: pointer to the hardware structure
2684 * @buf: pointer to the result buffer
2685 * @buf_size: length of input buffer
2686 * @start_seid: seid to start for the report, 0 == beginning
2687 * @cmd_details: pointer to command details structure or NULL
2689 * Fill the buf with switch configuration returned from AdminQ command
2691 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2692 struct i40e_aqc_get_switch_config_resp *buf,
2693 u16 buf_size, u16 *start_seid,
2694 struct i40e_asq_cmd_details *cmd_details)
2696 struct i40e_aq_desc desc;
2697 struct i40e_aqc_switch_seid *scfg =
2698 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2699 enum i40e_status_code status;
2701 i40e_fill_default_direct_cmd_desc(&desc,
2702 i40e_aqc_opc_get_switch_config);
2703 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2704 if (buf_size > I40E_AQ_LARGE_BUF)
2705 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2706 scfg->seid = CPU_TO_LE16(*start_seid);
2708 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2709 *start_seid = LE16_TO_CPU(scfg->seid);
2715 * i40e_aq_set_switch_config
2716 * @hw: pointer to the hardware structure
2717 * @flags: bit flag values to set
2718 * @mode: cloud filter mode
2719 * @valid_flags: which bit flags to set
2720 * @cmd_details: pointer to command details structure or NULL
2722 * Set switch configuration bits
2724 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2725 u16 flags, u16 valid_flags, u8 mode,
2726 struct i40e_asq_cmd_details *cmd_details)
2728 struct i40e_aq_desc desc;
2729 struct i40e_aqc_set_switch_config *scfg =
2730 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2731 enum i40e_status_code status;
2733 i40e_fill_default_direct_cmd_desc(&desc,
2734 i40e_aqc_opc_set_switch_config);
2735 scfg->flags = CPU_TO_LE16(flags);
2736 scfg->valid_flags = CPU_TO_LE16(valid_flags);
2738 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
2739 scfg->switch_tag = CPU_TO_LE16(hw->switch_tag);
2740 scfg->first_tag = CPU_TO_LE16(hw->first_tag);
2741 scfg->second_tag = CPU_TO_LE16(hw->second_tag);
2743 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2749 * i40e_aq_get_firmware_version
2750 * @hw: pointer to the hw struct
2751 * @fw_major_version: firmware major version
2752 * @fw_minor_version: firmware minor version
2753 * @fw_build: firmware build number
2754 * @api_major_version: major queue version
2755 * @api_minor_version: minor queue version
2756 * @cmd_details: pointer to command details structure or NULL
2758 * Get the firmware version from the admin queue commands
2760 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2761 u16 *fw_major_version, u16 *fw_minor_version,
2763 u16 *api_major_version, u16 *api_minor_version,
2764 struct i40e_asq_cmd_details *cmd_details)
2766 struct i40e_aq_desc desc;
2767 struct i40e_aqc_get_version *resp =
2768 (struct i40e_aqc_get_version *)&desc.params.raw;
2769 enum i40e_status_code status;
2771 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2773 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2775 if (status == I40E_SUCCESS) {
2776 if (fw_major_version != NULL)
2777 *fw_major_version = LE16_TO_CPU(resp->fw_major);
2778 if (fw_minor_version != NULL)
2779 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2780 if (fw_build != NULL)
2781 *fw_build = LE32_TO_CPU(resp->fw_build);
2782 if (api_major_version != NULL)
2783 *api_major_version = LE16_TO_CPU(resp->api_major);
2784 if (api_minor_version != NULL)
2785 *api_minor_version = LE16_TO_CPU(resp->api_minor);
2787 /* A workaround to fix the API version in SW */
2788 if (api_major_version && api_minor_version &&
2789 fw_major_version && fw_minor_version &&
2790 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2791 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2792 (*fw_major_version > 4)))
2793 *api_minor_version = 2;
2800 * i40e_aq_send_driver_version
2801 * @hw: pointer to the hw struct
2802 * @dv: driver's major, minor version
2803 * @cmd_details: pointer to command details structure or NULL
2805 * Send the driver version to the firmware
2807 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2808 struct i40e_driver_version *dv,
2809 struct i40e_asq_cmd_details *cmd_details)
2811 struct i40e_aq_desc desc;
2812 struct i40e_aqc_driver_version *cmd =
2813 (struct i40e_aqc_driver_version *)&desc.params.raw;
2814 enum i40e_status_code status;
2818 return I40E_ERR_PARAM;
2820 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2822 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2823 cmd->driver_major_ver = dv->major_version;
2824 cmd->driver_minor_ver = dv->minor_version;
2825 cmd->driver_build_ver = dv->build_version;
2826 cmd->driver_subbuild_ver = dv->subbuild_version;
2829 while (len < sizeof(dv->driver_string) &&
2830 (dv->driver_string[len] < 0x80) &&
2831 dv->driver_string[len])
2833 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2840 * i40e_get_link_status - get status of the HW network link
2841 * @hw: pointer to the hw struct
2842 * @link_up: pointer to bool (true/false = linkup/linkdown)
2844 * Variable link_up true if link is up, false if link is down.
2845 * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2847 * Side effect: LinkStatusEvent reporting becomes enabled
2849 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2851 enum i40e_status_code status = I40E_SUCCESS;
2853 if (hw->phy.get_link_info) {
2854 status = i40e_update_link_info(hw);
2856 if (status != I40E_SUCCESS)
2857 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2861 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2867 * i40e_updatelink_status - update status of the HW network link
2868 * @hw: pointer to the hw struct
2870 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2872 struct i40e_aq_get_phy_abilities_resp abilities;
2873 enum i40e_status_code status = I40E_SUCCESS;
2875 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2879 /* extra checking needed to ensure link info to user is timely */
2880 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2881 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2882 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2883 status = i40e_aq_get_phy_capabilities(hw, false, false,
2888 hw->phy.link_info.req_fec_info =
2889 abilities.fec_cfg_curr_mod_ext_info &
2890 (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS);
2892 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2893 sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2900 * i40e_get_link_speed
2901 * @hw: pointer to the hw struct
2903 * Returns the link speed of the adapter.
2905 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2907 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2908 enum i40e_status_code status = I40E_SUCCESS;
2910 if (hw->phy.get_link_info) {
2911 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2913 if (status != I40E_SUCCESS)
2914 goto i40e_link_speed_exit;
2917 speed = hw->phy.link_info.link_speed;
2919 i40e_link_speed_exit:
2924 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2925 * @hw: pointer to the hw struct
2926 * @uplink_seid: the MAC or other gizmo SEID
2927 * @downlink_seid: the VSI SEID
2928 * @enabled_tc: bitmap of TCs to be enabled
2929 * @default_port: true for default port VSI, false for control port
2930 * @veb_seid: pointer to where to put the resulting VEB SEID
2931 * @enable_stats: true to turn on VEB stats
2932 * @cmd_details: pointer to command details structure or NULL
2934 * This asks the FW to add a VEB between the uplink and downlink
2935 * elements. If the uplink SEID is 0, this will be a floating VEB.
2937 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2938 u16 downlink_seid, u8 enabled_tc,
2939 bool default_port, u16 *veb_seid,
2941 struct i40e_asq_cmd_details *cmd_details)
2943 struct i40e_aq_desc desc;
2944 struct i40e_aqc_add_veb *cmd =
2945 (struct i40e_aqc_add_veb *)&desc.params.raw;
2946 struct i40e_aqc_add_veb_completion *resp =
2947 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2948 enum i40e_status_code status;
2951 /* SEIDs need to either both be set or both be 0 for floating VEB */
2952 if (!!uplink_seid != !!downlink_seid)
2953 return I40E_ERR_PARAM;
2955 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2957 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2958 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2959 cmd->enable_tcs = enabled_tc;
2961 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2963 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2965 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2967 /* reverse logic here: set the bitflag to disable the stats */
2969 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2971 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2973 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2975 if (!status && veb_seid)
2976 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2982 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2983 * @hw: pointer to the hw struct
2984 * @veb_seid: the SEID of the VEB to query
2985 * @switch_id: the uplink switch id
2986 * @floating: set to true if the VEB is floating
2987 * @statistic_index: index of the stats counter block for this VEB
2988 * @vebs_used: number of VEB's used by function
2989 * @vebs_free: total VEB's not reserved by any function
2990 * @cmd_details: pointer to command details structure or NULL
2992 * This retrieves the parameters for a particular VEB, specified by
2993 * uplink_seid, and returns them to the caller.
2995 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2996 u16 veb_seid, u16 *switch_id,
2997 bool *floating, u16 *statistic_index,
2998 u16 *vebs_used, u16 *vebs_free,
2999 struct i40e_asq_cmd_details *cmd_details)
3001 struct i40e_aq_desc desc;
3002 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
3003 (struct i40e_aqc_get_veb_parameters_completion *)
3005 enum i40e_status_code status;
3008 return I40E_ERR_PARAM;
3010 i40e_fill_default_direct_cmd_desc(&desc,
3011 i40e_aqc_opc_get_veb_parameters);
3012 cmd_resp->seid = CPU_TO_LE16(veb_seid);
3014 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3019 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
3020 if (statistic_index)
3021 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
3023 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
3025 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
3027 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
3029 if (flags & I40E_AQC_ADD_VEB_FLOATING)
3040 * i40e_aq_add_macvlan
3041 * @hw: pointer to the hw struct
3042 * @seid: VSI for the mac address
3043 * @mv_list: list of macvlans to be added
3044 * @count: length of the list
3045 * @cmd_details: pointer to command details structure or NULL
3047 * Add MAC/VLAN addresses to the HW filtering
3049 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
3050 struct i40e_aqc_add_macvlan_element_data *mv_list,
3051 u16 count, struct i40e_asq_cmd_details *cmd_details)
3053 struct i40e_aq_desc desc;
3054 struct i40e_aqc_macvlan *cmd =
3055 (struct i40e_aqc_macvlan *)&desc.params.raw;
3056 enum i40e_status_code status;
3060 if (count == 0 || !mv_list || !hw)
3061 return I40E_ERR_PARAM;
3063 buf_size = count * sizeof(*mv_list);
3065 /* prep the rest of the request */
3066 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
3067 cmd->num_addresses = CPU_TO_LE16(count);
3068 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3072 for (i = 0; i < count; i++)
3073 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
3075 CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
3077 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3078 if (buf_size > I40E_AQ_LARGE_BUF)
3079 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3081 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3088 * i40e_aq_remove_macvlan
3089 * @hw: pointer to the hw struct
3090 * @seid: VSI for the mac address
3091 * @mv_list: list of macvlans to be removed
3092 * @count: length of the list
3093 * @cmd_details: pointer to command details structure or NULL
3095 * Remove MAC/VLAN addresses from the HW filtering
3097 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
3098 struct i40e_aqc_remove_macvlan_element_data *mv_list,
3099 u16 count, struct i40e_asq_cmd_details *cmd_details)
3101 struct i40e_aq_desc desc;
3102 struct i40e_aqc_macvlan *cmd =
3103 (struct i40e_aqc_macvlan *)&desc.params.raw;
3104 enum i40e_status_code status;
3107 if (count == 0 || !mv_list || !hw)
3108 return I40E_ERR_PARAM;
3110 buf_size = count * sizeof(*mv_list);
3112 /* prep the rest of the request */
3113 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
3114 cmd->num_addresses = CPU_TO_LE16(count);
3115 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3119 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3120 if (buf_size > I40E_AQ_LARGE_BUF)
3121 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3123 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3130 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3131 * @hw: pointer to the hw struct
3132 * @opcode: AQ opcode for add or delete mirror rule
3133 * @sw_seid: Switch SEID (to which rule refers)
3134 * @rule_type: Rule Type (ingress/egress/VLAN)
3135 * @id: Destination VSI SEID or Rule ID
3136 * @count: length of the list
3137 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3138 * @cmd_details: pointer to command details structure or NULL
3139 * @rule_id: Rule ID returned from FW
3140 * @rules_used: Number of rules used in internal switch
3141 * @rules_free: Number of rules free in internal switch
3143 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3144 * VEBs/VEPA elements only
3146 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3147 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3148 u16 count, __le16 *mr_list,
3149 struct i40e_asq_cmd_details *cmd_details,
3150 u16 *rule_id, u16 *rules_used, u16 *rules_free)
3152 struct i40e_aq_desc desc;
3153 struct i40e_aqc_add_delete_mirror_rule *cmd =
3154 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3155 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3156 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3157 enum i40e_status_code status;
3160 buf_size = count * sizeof(*mr_list);
3162 /* prep the rest of the request */
3163 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3164 cmd->seid = CPU_TO_LE16(sw_seid);
3165 cmd->rule_type = CPU_TO_LE16(rule_type &
3166 I40E_AQC_MIRROR_RULE_TYPE_MASK);
3167 cmd->num_entries = CPU_TO_LE16(count);
3168 /* Dest VSI for add, rule_id for delete */
3169 cmd->destination = CPU_TO_LE16(id);
3171 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3173 if (buf_size > I40E_AQ_LARGE_BUF)
3174 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3177 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3179 if (status == I40E_SUCCESS ||
3180 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3182 *rule_id = LE16_TO_CPU(resp->rule_id);
3184 *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3186 *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3192 * i40e_aq_add_mirrorrule - add a mirror rule
3193 * @hw: pointer to the hw struct
3194 * @sw_seid: Switch SEID (to which rule refers)
3195 * @rule_type: Rule Type (ingress/egress/VLAN)
3196 * @dest_vsi: SEID of VSI to which packets will be mirrored
3197 * @count: length of the list
3198 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3199 * @cmd_details: pointer to command details structure or NULL
3200 * @rule_id: Rule ID returned from FW
3201 * @rules_used: Number of rules used in internal switch
3202 * @rules_free: Number of rules free in internal switch
3204 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3206 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3207 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3208 struct i40e_asq_cmd_details *cmd_details,
3209 u16 *rule_id, u16 *rules_used, u16 *rules_free)
3211 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3212 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3213 if (count == 0 || !mr_list)
3214 return I40E_ERR_PARAM;
3217 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3218 rule_type, dest_vsi, count, mr_list,
3219 cmd_details, rule_id, rules_used, rules_free);
3223 * i40e_aq_delete_mirrorrule - delete a mirror rule
3224 * @hw: pointer to the hw struct
3225 * @sw_seid: Switch SEID (to which rule refers)
3226 * @rule_type: Rule Type (ingress/egress/VLAN)
3227 * @count: length of the list
3228 * @rule_id: Rule ID that is returned in the receive desc as part of
3230 * @mr_list: list of mirrored VLAN IDs to be removed
3231 * @cmd_details: pointer to command details structure or NULL
3232 * @rules_used: Number of rules used in internal switch
3233 * @rules_free: Number of rules free in internal switch
3235 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3237 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3238 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3239 struct i40e_asq_cmd_details *cmd_details,
3240 u16 *rules_used, u16 *rules_free)
3242 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3243 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3244 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3245 * mirroring. For other rule_type, count and rule_type should
3248 if (count == 0 || !mr_list)
3249 return I40E_ERR_PARAM;
3252 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3253 rule_type, rule_id, count, mr_list,
3254 cmd_details, NULL, rules_used, rules_free);
3258 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3259 * @hw: pointer to the hw struct
3260 * @seid: VSI for the vlan filters
3261 * @v_list: list of vlan filters to be added
3262 * @count: length of the list
3263 * @cmd_details: pointer to command details structure or NULL
3265 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3266 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3267 u8 count, struct i40e_asq_cmd_details *cmd_details)
3269 struct i40e_aq_desc desc;
3270 struct i40e_aqc_macvlan *cmd =
3271 (struct i40e_aqc_macvlan *)&desc.params.raw;
3272 enum i40e_status_code status;
3275 if (count == 0 || !v_list || !hw)
3276 return I40E_ERR_PARAM;
3278 buf_size = count * sizeof(*v_list);
3280 /* prep the rest of the request */
3281 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3282 cmd->num_addresses = CPU_TO_LE16(count);
3283 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3287 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3288 if (buf_size > I40E_AQ_LARGE_BUF)
3289 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3291 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3298 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3299 * @hw: pointer to the hw struct
3300 * @seid: VSI for the vlan filters
3301 * @v_list: list of macvlans to be removed
3302 * @count: length of the list
3303 * @cmd_details: pointer to command details structure or NULL
3305 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3306 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3307 u8 count, struct i40e_asq_cmd_details *cmd_details)
3309 struct i40e_aq_desc desc;
3310 struct i40e_aqc_macvlan *cmd =
3311 (struct i40e_aqc_macvlan *)&desc.params.raw;
3312 enum i40e_status_code status;
3315 if (count == 0 || !v_list || !hw)
3316 return I40E_ERR_PARAM;
3318 buf_size = count * sizeof(*v_list);
3320 /* prep the rest of the request */
3321 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3322 cmd->num_addresses = CPU_TO_LE16(count);
3323 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3327 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3328 if (buf_size > I40E_AQ_LARGE_BUF)
3329 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3331 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3338 * i40e_aq_send_msg_to_vf
3339 * @hw: pointer to the hardware structure
3340 * @vfid: vf id to send msg
3341 * @v_opcode: opcodes for VF-PF communication
3342 * @v_retval: return error code
3343 * @msg: pointer to the msg buffer
3344 * @msglen: msg length
3345 * @cmd_details: pointer to command details
3349 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3350 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3351 struct i40e_asq_cmd_details *cmd_details)
3353 struct i40e_aq_desc desc;
3354 struct i40e_aqc_pf_vf_message *cmd =
3355 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3356 enum i40e_status_code status;
3358 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3359 cmd->id = CPU_TO_LE32(vfid);
3360 desc.cookie_high = CPU_TO_LE32(v_opcode);
3361 desc.cookie_low = CPU_TO_LE32(v_retval);
3362 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3364 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3366 if (msglen > I40E_AQ_LARGE_BUF)
3367 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3368 desc.datalen = CPU_TO_LE16(msglen);
3370 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3376 * i40e_aq_debug_read_register
3377 * @hw: pointer to the hw struct
3378 * @reg_addr: register address
3379 * @reg_val: register value
3380 * @cmd_details: pointer to command details structure or NULL
3382 * Read the register using the admin queue commands
3384 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3385 u32 reg_addr, u64 *reg_val,
3386 struct i40e_asq_cmd_details *cmd_details)
3388 struct i40e_aq_desc desc;
3389 struct i40e_aqc_debug_reg_read_write *cmd_resp =
3390 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3391 enum i40e_status_code status;
3393 if (reg_val == NULL)
3394 return I40E_ERR_PARAM;
3396 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3398 cmd_resp->address = CPU_TO_LE32(reg_addr);
3400 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3402 if (status == I40E_SUCCESS) {
3403 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3404 (u64)LE32_TO_CPU(cmd_resp->value_low);
3411 * i40e_aq_debug_write_register
3412 * @hw: pointer to the hw struct
3413 * @reg_addr: register address
3414 * @reg_val: register value
3415 * @cmd_details: pointer to command details structure or NULL
3417 * Write to a register using the admin queue commands
3419 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3420 u32 reg_addr, u64 reg_val,
3421 struct i40e_asq_cmd_details *cmd_details)
3423 struct i40e_aq_desc desc;
3424 struct i40e_aqc_debug_reg_read_write *cmd =
3425 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3426 enum i40e_status_code status;
3428 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3430 cmd->address = CPU_TO_LE32(reg_addr);
3431 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3432 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3434 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3440 * i40e_aq_request_resource
3441 * @hw: pointer to the hw struct
3442 * @resource: resource id
3443 * @access: access type
3444 * @sdp_number: resource number
3445 * @timeout: the maximum time in ms that the driver may hold the resource
3446 * @cmd_details: pointer to command details structure or NULL
3448 * requests common resource using the admin queue commands
3450 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3451 enum i40e_aq_resources_ids resource,
3452 enum i40e_aq_resource_access_type access,
3453 u8 sdp_number, u64 *timeout,
3454 struct i40e_asq_cmd_details *cmd_details)
3456 struct i40e_aq_desc desc;
3457 struct i40e_aqc_request_resource *cmd_resp =
3458 (struct i40e_aqc_request_resource *)&desc.params.raw;
3459 enum i40e_status_code status;
3461 DEBUGFUNC("i40e_aq_request_resource");
3463 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3465 cmd_resp->resource_id = CPU_TO_LE16(resource);
3466 cmd_resp->access_type = CPU_TO_LE16(access);
3467 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3469 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3470 /* The completion specifies the maximum time in ms that the driver
3471 * may hold the resource in the Timeout field.
3472 * If the resource is held by someone else, the command completes with
3473 * busy return value and the timeout field indicates the maximum time
3474 * the current owner of the resource has to free it.
3476 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3477 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3483 * i40e_aq_release_resource
3484 * @hw: pointer to the hw struct
3485 * @resource: resource id
3486 * @sdp_number: resource number
3487 * @cmd_details: pointer to command details structure or NULL
3489 * release common resource using the admin queue commands
3491 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3492 enum i40e_aq_resources_ids resource,
3494 struct i40e_asq_cmd_details *cmd_details)
3496 struct i40e_aq_desc desc;
3497 struct i40e_aqc_request_resource *cmd =
3498 (struct i40e_aqc_request_resource *)&desc.params.raw;
3499 enum i40e_status_code status;
3501 DEBUGFUNC("i40e_aq_release_resource");
3503 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3505 cmd->resource_id = CPU_TO_LE16(resource);
3506 cmd->resource_number = CPU_TO_LE32(sdp_number);
3508 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3515 * @hw: pointer to the hw struct
3516 * @module_pointer: module pointer location in words from the NVM beginning
3517 * @offset: byte offset from the module beginning
3518 * @length: length of the section to be read (in bytes from the offset)
3519 * @data: command buffer (size [bytes] = length)
3520 * @last_command: tells if this is the last command in a series
3521 * @cmd_details: pointer to command details structure or NULL
3523 * Read the NVM using the admin queue commands
3525 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3526 u32 offset, u16 length, void *data,
3528 struct i40e_asq_cmd_details *cmd_details)
3530 struct i40e_aq_desc desc;
3531 struct i40e_aqc_nvm_update *cmd =
3532 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3533 enum i40e_status_code status;
3535 DEBUGFUNC("i40e_aq_read_nvm");
3537 /* In offset the highest byte must be zeroed. */
3538 if (offset & 0xFF000000) {
3539 status = I40E_ERR_PARAM;
3540 goto i40e_aq_read_nvm_exit;
3543 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3545 /* If this is the last command in a series, set the proper flag. */
3547 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3548 cmd->module_pointer = module_pointer;
3549 cmd->offset = CPU_TO_LE32(offset);
3550 cmd->length = CPU_TO_LE16(length);
3552 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3553 if (length > I40E_AQ_LARGE_BUF)
3554 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3556 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3558 i40e_aq_read_nvm_exit:
3563 * i40e_aq_read_nvm_config - read an nvm config block
3564 * @hw: pointer to the hw struct
3565 * @cmd_flags: NVM access admin command bits
3566 * @field_id: field or feature id
3567 * @data: buffer for result
3568 * @buf_size: buffer size
3569 * @element_count: pointer to count of elements read by FW
3570 * @cmd_details: pointer to command details structure or NULL
3572 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3573 u8 cmd_flags, u32 field_id, void *data,
3574 u16 buf_size, u16 *element_count,
3575 struct i40e_asq_cmd_details *cmd_details)
3577 struct i40e_aq_desc desc;
3578 struct i40e_aqc_nvm_config_read *cmd =
3579 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3580 enum i40e_status_code status;
3582 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3583 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3584 if (buf_size > I40E_AQ_LARGE_BUF)
3585 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3587 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3588 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3589 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3590 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3592 cmd->element_id_msw = 0;
3594 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3596 if (!status && element_count)
3597 *element_count = LE16_TO_CPU(cmd->element_count);
3603 * i40e_aq_write_nvm_config - write an nvm config block
3604 * @hw: pointer to the hw struct
3605 * @cmd_flags: NVM access admin command bits
3606 * @data: buffer for result
3607 * @buf_size: buffer size
3608 * @element_count: count of elements to be written
3609 * @cmd_details: pointer to command details structure or NULL
3611 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3612 u8 cmd_flags, void *data, u16 buf_size,
3614 struct i40e_asq_cmd_details *cmd_details)
3616 struct i40e_aq_desc desc;
3617 struct i40e_aqc_nvm_config_write *cmd =
3618 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3619 enum i40e_status_code status;
3621 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3622 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3623 if (buf_size > I40E_AQ_LARGE_BUF)
3624 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3626 cmd->element_count = CPU_TO_LE16(element_count);
3627 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3628 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3634 * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3635 * @hw: pointer to the hw struct
3636 * @buff: buffer for result
3637 * @buff_size: buffer size
3638 * @cmd_details: pointer to command details structure or NULL
3640 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3641 void *buff, u16 buff_size,
3642 struct i40e_asq_cmd_details *cmd_details)
3644 struct i40e_aq_desc desc;
3645 enum i40e_status_code status;
3647 UNREFERENCED_2PARAMETER(buff, buff_size);
3649 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3650 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3651 if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3652 status = I40E_ERR_NOT_IMPLEMENTED;
3659 * @hw: pointer to the hw struct
3660 * @module_pointer: module pointer location in words from the NVM beginning
3661 * @offset: offset in the module (expressed in 4 KB from module's beginning)
3662 * @length: length of the section to be erased (expressed in 4 KB)
3663 * @last_command: tells if this is the last command in a series
3664 * @cmd_details: pointer to command details structure or NULL
3666 * Erase the NVM sector using the admin queue commands
3668 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3669 u32 offset, u16 length, bool last_command,
3670 struct i40e_asq_cmd_details *cmd_details)
3672 struct i40e_aq_desc desc;
3673 struct i40e_aqc_nvm_update *cmd =
3674 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3675 enum i40e_status_code status;
3677 DEBUGFUNC("i40e_aq_erase_nvm");
3679 /* In offset the highest byte must be zeroed. */
3680 if (offset & 0xFF000000) {
3681 status = I40E_ERR_PARAM;
3682 goto i40e_aq_erase_nvm_exit;
3685 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3687 /* If this is the last command in a series, set the proper flag. */
3689 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3690 cmd->module_pointer = module_pointer;
3691 cmd->offset = CPU_TO_LE32(offset);
3692 cmd->length = CPU_TO_LE16(length);
3694 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3696 i40e_aq_erase_nvm_exit:
3701 * i40e_parse_discover_capabilities
3702 * @hw: pointer to the hw struct
3703 * @buff: pointer to a buffer containing device/function capability records
3704 * @cap_count: number of capability records in the list
3705 * @list_type_opc: type of capabilities list to parse
3707 * Parse the device/function capabilities list.
3709 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3711 enum i40e_admin_queue_opc list_type_opc)
3713 struct i40e_aqc_list_capabilities_element_resp *cap;
3714 u32 valid_functions, num_functions;
3715 u32 number, logical_id, phys_id;
3716 struct i40e_hw_capabilities *p;
3717 enum i40e_status_code status;
3718 u16 id, ocp_cfg_word0;
3722 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3724 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3725 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3726 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3727 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3731 for (i = 0; i < cap_count; i++, cap++) {
3732 id = LE16_TO_CPU(cap->id);
3733 number = LE32_TO_CPU(cap->number);
3734 logical_id = LE32_TO_CPU(cap->logical_id);
3735 phys_id = LE32_TO_CPU(cap->phys_id);
3736 major_rev = cap->major_rev;
3739 case I40E_AQ_CAP_ID_SWITCH_MODE:
3740 p->switch_mode = number;
3741 i40e_debug(hw, I40E_DEBUG_INIT,
3742 "HW Capability: Switch mode = %d\n",
3745 case I40E_AQ_CAP_ID_MNG_MODE:
3746 p->management_mode = number;
3747 if (major_rev > 1) {
3748 p->mng_protocols_over_mctp = logical_id;
3749 i40e_debug(hw, I40E_DEBUG_INIT,
3750 "HW Capability: Protocols over MCTP = %d\n",
3751 p->mng_protocols_over_mctp);
3753 p->mng_protocols_over_mctp = 0;
3755 i40e_debug(hw, I40E_DEBUG_INIT,
3756 "HW Capability: Management Mode = %d\n",
3757 p->management_mode);
3759 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3760 p->npar_enable = number;
3761 i40e_debug(hw, I40E_DEBUG_INIT,
3762 "HW Capability: NPAR enable = %d\n",
3765 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3767 i40e_debug(hw, I40E_DEBUG_INIT,
3768 "HW Capability: OS2BMC = %d\n", p->os2bmc);
3770 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3771 p->valid_functions = number;
3772 i40e_debug(hw, I40E_DEBUG_INIT,
3773 "HW Capability: Valid Functions = %d\n",
3774 p->valid_functions);
3776 case I40E_AQ_CAP_ID_SRIOV:
3778 p->sr_iov_1_1 = true;
3779 i40e_debug(hw, I40E_DEBUG_INIT,
3780 "HW Capability: SR-IOV = %d\n",
3783 case I40E_AQ_CAP_ID_VF:
3784 p->num_vfs = number;
3785 p->vf_base_id = logical_id;
3786 i40e_debug(hw, I40E_DEBUG_INIT,
3787 "HW Capability: VF count = %d\n",
3789 i40e_debug(hw, I40E_DEBUG_INIT,
3790 "HW Capability: VF base_id = %d\n",
3793 case I40E_AQ_CAP_ID_VMDQ:
3796 i40e_debug(hw, I40E_DEBUG_INIT,
3797 "HW Capability: VMDQ = %d\n", p->vmdq);
3799 case I40E_AQ_CAP_ID_8021QBG:
3801 p->evb_802_1_qbg = true;
3802 i40e_debug(hw, I40E_DEBUG_INIT,
3803 "HW Capability: 802.1Qbg = %d\n", number);
3805 case I40E_AQ_CAP_ID_8021QBR:
3807 p->evb_802_1_qbh = true;
3808 i40e_debug(hw, I40E_DEBUG_INIT,
3809 "HW Capability: 802.1Qbh = %d\n", number);
3811 case I40E_AQ_CAP_ID_VSI:
3812 p->num_vsis = number;
3813 i40e_debug(hw, I40E_DEBUG_INIT,
3814 "HW Capability: VSI count = %d\n",
3817 case I40E_AQ_CAP_ID_DCB:
3820 p->enabled_tcmap = logical_id;
3823 i40e_debug(hw, I40E_DEBUG_INIT,
3824 "HW Capability: DCB = %d\n", p->dcb);
3825 i40e_debug(hw, I40E_DEBUG_INIT,
3826 "HW Capability: TC Mapping = %d\n",
3828 i40e_debug(hw, I40E_DEBUG_INIT,
3829 "HW Capability: TC Max = %d\n", p->maxtc);
3831 case I40E_AQ_CAP_ID_FCOE:
3834 i40e_debug(hw, I40E_DEBUG_INIT,
3835 "HW Capability: FCOE = %d\n", p->fcoe);
3837 case I40E_AQ_CAP_ID_ISCSI:
3840 i40e_debug(hw, I40E_DEBUG_INIT,
3841 "HW Capability: iSCSI = %d\n", p->iscsi);
3843 case I40E_AQ_CAP_ID_RSS:
3845 p->rss_table_size = number;
3846 p->rss_table_entry_width = logical_id;
3847 i40e_debug(hw, I40E_DEBUG_INIT,
3848 "HW Capability: RSS = %d\n", p->rss);
3849 i40e_debug(hw, I40E_DEBUG_INIT,
3850 "HW Capability: RSS table size = %d\n",
3852 i40e_debug(hw, I40E_DEBUG_INIT,
3853 "HW Capability: RSS table width = %d\n",
3854 p->rss_table_entry_width);
3856 case I40E_AQ_CAP_ID_RXQ:
3857 p->num_rx_qp = number;
3858 p->base_queue = phys_id;
3859 i40e_debug(hw, I40E_DEBUG_INIT,
3860 "HW Capability: Rx QP = %d\n", number);
3861 i40e_debug(hw, I40E_DEBUG_INIT,
3862 "HW Capability: base_queue = %d\n",
3865 case I40E_AQ_CAP_ID_TXQ:
3866 p->num_tx_qp = number;
3867 p->base_queue = phys_id;
3868 i40e_debug(hw, I40E_DEBUG_INIT,
3869 "HW Capability: Tx QP = %d\n", number);
3870 i40e_debug(hw, I40E_DEBUG_INIT,
3871 "HW Capability: base_queue = %d\n",
3874 case I40E_AQ_CAP_ID_MSIX:
3875 p->num_msix_vectors = number;
3876 i40e_debug(hw, I40E_DEBUG_INIT,
3877 "HW Capability: MSIX vector count = %d\n",
3878 p->num_msix_vectors);
3880 case I40E_AQ_CAP_ID_VF_MSIX:
3881 p->num_msix_vectors_vf = number;
3882 i40e_debug(hw, I40E_DEBUG_INIT,
3883 "HW Capability: MSIX VF vector count = %d\n",
3884 p->num_msix_vectors_vf);
3886 case I40E_AQ_CAP_ID_FLEX10:
3887 if (major_rev == 1) {
3889 p->flex10_enable = true;
3890 p->flex10_capable = true;
3893 /* Capability revision >= 2 */
3895 p->flex10_enable = true;
3897 p->flex10_capable = true;
3899 p->flex10_mode = logical_id;
3900 p->flex10_status = phys_id;
3901 i40e_debug(hw, I40E_DEBUG_INIT,
3902 "HW Capability: Flex10 mode = %d\n",
3904 i40e_debug(hw, I40E_DEBUG_INIT,
3905 "HW Capability: Flex10 status = %d\n",
3908 case I40E_AQ_CAP_ID_CEM:
3911 i40e_debug(hw, I40E_DEBUG_INIT,
3912 "HW Capability: CEM = %d\n", p->mgmt_cem);
3914 case I40E_AQ_CAP_ID_IWARP:
3917 i40e_debug(hw, I40E_DEBUG_INIT,
3918 "HW Capability: iWARP = %d\n", p->iwarp);
3920 case I40E_AQ_CAP_ID_LED:
3921 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3922 p->led[phys_id] = true;
3923 i40e_debug(hw, I40E_DEBUG_INIT,
3924 "HW Capability: LED - PIN %d\n", phys_id);
3926 case I40E_AQ_CAP_ID_SDP:
3927 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3928 p->sdp[phys_id] = true;
3929 i40e_debug(hw, I40E_DEBUG_INIT,
3930 "HW Capability: SDP - PIN %d\n", phys_id);
3932 case I40E_AQ_CAP_ID_MDIO:
3934 p->mdio_port_num = phys_id;
3935 p->mdio_port_mode = logical_id;
3937 i40e_debug(hw, I40E_DEBUG_INIT,
3938 "HW Capability: MDIO port number = %d\n",
3940 i40e_debug(hw, I40E_DEBUG_INIT,
3941 "HW Capability: MDIO port mode = %d\n",
3944 case I40E_AQ_CAP_ID_1588:
3946 p->ieee_1588 = true;
3947 i40e_debug(hw, I40E_DEBUG_INIT,
3948 "HW Capability: IEEE 1588 = %d\n",
3951 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3953 p->fd_filters_guaranteed = number;
3954 p->fd_filters_best_effort = logical_id;
3955 i40e_debug(hw, I40E_DEBUG_INIT,
3956 "HW Capability: Flow Director = 1\n");
3957 i40e_debug(hw, I40E_DEBUG_INIT,
3958 "HW Capability: Guaranteed FD filters = %d\n",
3959 p->fd_filters_guaranteed);
3961 case I40E_AQ_CAP_ID_WSR_PROT:
3962 p->wr_csr_prot = (u64)number;
3963 p->wr_csr_prot |= (u64)logical_id << 32;
3964 i40e_debug(hw, I40E_DEBUG_INIT,
3965 "HW Capability: wr_csr_prot = 0x%llX\n\n",
3966 (p->wr_csr_prot & 0xffff));
3968 case I40E_AQ_CAP_ID_NVM_MGMT:
3969 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3970 p->sec_rev_disabled = true;
3971 if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3972 p->update_disabled = true;
3974 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3975 hw->num_wol_proxy_filters = (u16)number;
3976 hw->wol_proxy_vsi_seid = (u16)logical_id;
3977 p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3978 if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3979 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3981 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3982 p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3983 i40e_debug(hw, I40E_DEBUG_INIT,
3984 "HW Capability: WOL proxy filters = %d\n",
3985 hw->num_wol_proxy_filters);
3993 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3995 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3998 /* count the enabled ports (aka the "not disabled" ports) */
4000 for (i = 0; i < 4; i++) {
4001 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
4004 /* use AQ read to get the physical register offset instead
4005 * of the port relative offset
4007 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
4008 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
4012 /* OCP cards case: if a mezz is removed the ethernet port is at
4013 * disabled state in PRTGEN_CNF register. Additional NVM read is
4014 * needed in order to check if we are dealing with OCP card.
4015 * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting
4016 * physical ports results in wrong partition id calculation and thus
4017 * not supporting WoL.
4019 if (hw->mac.type == I40E_MAC_X722) {
4020 if (i40e_acquire_nvm(hw, I40E_RESOURCE_READ) == I40E_SUCCESS) {
4021 status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR,
4022 2 * I40E_SR_OCP_CFG_WORD0,
4023 sizeof(ocp_cfg_word0),
4024 &ocp_cfg_word0, true, NULL);
4025 if (status == I40E_SUCCESS &&
4026 (ocp_cfg_word0 & I40E_SR_OCP_ENABLED))
4028 i40e_release_nvm(hw);
4032 valid_functions = p->valid_functions;
4034 while (valid_functions) {
4035 if (valid_functions & 1)
4037 valid_functions >>= 1;
4040 /* partition id is 1-based, and functions are evenly spread
4041 * across the ports as partitions
4043 if (hw->num_ports != 0) {
4044 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
4045 hw->num_partitions = num_functions / hw->num_ports;
4048 /* additional HW specific goodies that might
4049 * someday be HW version specific
4051 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
4055 * i40e_aq_discover_capabilities
4056 * @hw: pointer to the hw struct
4057 * @buff: a virtual buffer to hold the capabilities
4058 * @buff_size: Size of the virtual buffer
4059 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
4060 * @list_type_opc: capabilities type to discover - pass in the command opcode
4061 * @cmd_details: pointer to command details structure or NULL
4063 * Get the device capabilities descriptions from the firmware
4065 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
4066 void *buff, u16 buff_size, u16 *data_size,
4067 enum i40e_admin_queue_opc list_type_opc,
4068 struct i40e_asq_cmd_details *cmd_details)
4070 struct i40e_aqc_list_capabilites *cmd;
4071 struct i40e_aq_desc desc;
4072 enum i40e_status_code status = I40E_SUCCESS;
4074 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
4076 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
4077 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
4078 status = I40E_ERR_PARAM;
4082 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
4084 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4085 if (buff_size > I40E_AQ_LARGE_BUF)
4086 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4088 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4089 *data_size = LE16_TO_CPU(desc.datalen);
4094 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
4102 * i40e_aq_update_nvm
4103 * @hw: pointer to the hw struct
4104 * @module_pointer: module pointer location in words from the NVM beginning
4105 * @offset: byte offset from the module beginning
4106 * @length: length of the section to be written (in bytes from the offset)
4107 * @data: command buffer (size [bytes] = length)
4108 * @last_command: tells if this is the last command in a series
4109 * @preservation_flags: Preservation mode flags
4110 * @cmd_details: pointer to command details structure or NULL
4112 * Update the NVM using the admin queue commands
4114 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
4115 u32 offset, u16 length, void *data,
4116 bool last_command, u8 preservation_flags,
4117 struct i40e_asq_cmd_details *cmd_details)
4119 struct i40e_aq_desc desc;
4120 struct i40e_aqc_nvm_update *cmd =
4121 (struct i40e_aqc_nvm_update *)&desc.params.raw;
4122 enum i40e_status_code status;
4124 DEBUGFUNC("i40e_aq_update_nvm");
4126 /* In offset the highest byte must be zeroed. */
4127 if (offset & 0xFF000000) {
4128 status = I40E_ERR_PARAM;
4129 goto i40e_aq_update_nvm_exit;
4132 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4134 /* If this is the last command in a series, set the proper flag. */
4136 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
4137 if (hw->mac.type == I40E_MAC_X722) {
4138 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED)
4139 cmd->command_flags |=
4140 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED <<
4141 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4142 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL)
4143 cmd->command_flags |=
4144 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL <<
4145 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4147 cmd->module_pointer = module_pointer;
4148 cmd->offset = CPU_TO_LE32(offset);
4149 cmd->length = CPU_TO_LE16(length);
4151 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4152 if (length > I40E_AQ_LARGE_BUF)
4153 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4155 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
4157 i40e_aq_update_nvm_exit:
4162 * i40e_aq_rearrange_nvm
4163 * @hw: pointer to the hw struct
4164 * @rearrange_nvm: defines direction of rearrangement
4165 * @cmd_details: pointer to command details structure or NULL
4167 * Rearrange NVM structure, available only for transition FW
4169 enum i40e_status_code i40e_aq_rearrange_nvm(struct i40e_hw *hw,
4171 struct i40e_asq_cmd_details *cmd_details)
4173 struct i40e_aqc_nvm_update *cmd;
4174 enum i40e_status_code status;
4175 struct i40e_aq_desc desc;
4177 DEBUGFUNC("i40e_aq_rearrange_nvm");
4179 cmd = (struct i40e_aqc_nvm_update *)&desc.params.raw;
4181 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4183 rearrange_nvm &= (I40E_AQ_NVM_REARRANGE_TO_FLAT |
4184 I40E_AQ_NVM_REARRANGE_TO_STRUCT);
4186 if (!rearrange_nvm) {
4187 status = I40E_ERR_PARAM;
4188 goto i40e_aq_rearrange_nvm_exit;
4191 cmd->command_flags |= rearrange_nvm;
4192 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4194 i40e_aq_rearrange_nvm_exit:
4199 * i40e_aq_nvm_progress
4200 * @hw: pointer to the hw struct
4201 * @progress: pointer to progress returned from AQ
4202 * @cmd_details: pointer to command details structure or NULL
4204 * Gets progress of flash rearrangement process
4206 enum i40e_status_code i40e_aq_nvm_progress(struct i40e_hw *hw, u8 *progress,
4207 struct i40e_asq_cmd_details *cmd_details)
4209 enum i40e_status_code status;
4210 struct i40e_aq_desc desc;
4212 DEBUGFUNC("i40e_aq_nvm_progress");
4214 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_progress);
4215 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4216 *progress = desc.params.raw[0];
4221 * i40e_aq_get_lldp_mib
4222 * @hw: pointer to the hw struct
4223 * @bridge_type: type of bridge requested
4224 * @mib_type: Local, Remote or both Local and Remote MIBs
4225 * @buff: pointer to a user supplied buffer to store the MIB block
4226 * @buff_size: size of the buffer (in bytes)
4227 * @local_len : length of the returned Local LLDP MIB
4228 * @remote_len: length of the returned Remote LLDP MIB
4229 * @cmd_details: pointer to command details structure or NULL
4231 * Requests the complete LLDP MIB (entire packet).
4233 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4234 u8 mib_type, void *buff, u16 buff_size,
4235 u16 *local_len, u16 *remote_len,
4236 struct i40e_asq_cmd_details *cmd_details)
4238 struct i40e_aq_desc desc;
4239 struct i40e_aqc_lldp_get_mib *cmd =
4240 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4241 struct i40e_aqc_lldp_get_mib *resp =
4242 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4243 enum i40e_status_code status;
4245 if (buff_size == 0 || !buff)
4246 return I40E_ERR_PARAM;
4248 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4249 /* Indirect Command */
4250 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4252 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4253 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4254 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4256 desc.datalen = CPU_TO_LE16(buff_size);
4258 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4259 if (buff_size > I40E_AQ_LARGE_BUF)
4260 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4262 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4264 if (local_len != NULL)
4265 *local_len = LE16_TO_CPU(resp->local_len);
4266 if (remote_len != NULL)
4267 *remote_len = LE16_TO_CPU(resp->remote_len);
4274 * i40e_aq_set_lldp_mib - Set the LLDP MIB
4275 * @hw: pointer to the hw struct
4276 * @mib_type: Local, Remote or both Local and Remote MIBs
4277 * @buff: pointer to a user supplied buffer to store the MIB block
4278 * @buff_size: size of the buffer (in bytes)
4279 * @cmd_details: pointer to command details structure or NULL
4283 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4284 u8 mib_type, void *buff, u16 buff_size,
4285 struct i40e_asq_cmd_details *cmd_details)
4287 struct i40e_aq_desc desc;
4288 struct i40e_aqc_lldp_set_local_mib *cmd =
4289 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4290 enum i40e_status_code status;
4292 if (buff_size == 0 || !buff)
4293 return I40E_ERR_PARAM;
4295 i40e_fill_default_direct_cmd_desc(&desc,
4296 i40e_aqc_opc_lldp_set_local_mib);
4297 /* Indirect Command */
4298 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4299 if (buff_size > I40E_AQ_LARGE_BUF)
4300 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4301 desc.datalen = CPU_TO_LE16(buff_size);
4303 cmd->type = mib_type;
4304 cmd->length = CPU_TO_LE16(buff_size);
4305 cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4306 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4308 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4313 * i40e_aq_cfg_lldp_mib_change_event
4314 * @hw: pointer to the hw struct
4315 * @enable_update: Enable or Disable event posting
4316 * @cmd_details: pointer to command details structure or NULL
4318 * Enable or Disable posting of an event on ARQ when LLDP MIB
4319 * associated with the interface changes
4321 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4323 struct i40e_asq_cmd_details *cmd_details)
4325 struct i40e_aq_desc desc;
4326 struct i40e_aqc_lldp_update_mib *cmd =
4327 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4328 enum i40e_status_code status;
4330 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4333 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4335 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4341 * i40e_aq_add_lldp_tlv
4342 * @hw: pointer to the hw struct
4343 * @bridge_type: type of bridge
4344 * @buff: buffer with TLV to add
4345 * @buff_size: length of the buffer
4346 * @tlv_len: length of the TLV to be added
4347 * @mib_len: length of the LLDP MIB returned in response
4348 * @cmd_details: pointer to command details structure or NULL
4350 * Add the specified TLV to LLDP Local MIB for the given bridge type,
4351 * it is responsibility of the caller to make sure that the TLV is not
4352 * already present in the LLDPDU.
4353 * In return firmware will write the complete LLDP MIB with the newly
4354 * added TLV in the response buffer.
4356 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4357 void *buff, u16 buff_size, u16 tlv_len,
4359 struct i40e_asq_cmd_details *cmd_details)
4361 struct i40e_aq_desc desc;
4362 struct i40e_aqc_lldp_add_tlv *cmd =
4363 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4364 enum i40e_status_code status;
4366 if (buff_size == 0 || !buff || tlv_len == 0)
4367 return I40E_ERR_PARAM;
4369 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4371 /* Indirect Command */
4372 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4373 if (buff_size > I40E_AQ_LARGE_BUF)
4374 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4375 desc.datalen = CPU_TO_LE16(buff_size);
4377 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4378 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4379 cmd->len = CPU_TO_LE16(tlv_len);
4381 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4383 if (mib_len != NULL)
4384 *mib_len = LE16_TO_CPU(desc.datalen);
4391 * i40e_aq_update_lldp_tlv
4392 * @hw: pointer to the hw struct
4393 * @bridge_type: type of bridge
4394 * @buff: buffer with TLV to update
4395 * @buff_size: size of the buffer holding original and updated TLVs
4396 * @old_len: Length of the Original TLV
4397 * @new_len: Length of the Updated TLV
4398 * @offset: offset of the updated TLV in the buff
4399 * @mib_len: length of the returned LLDP MIB
4400 * @cmd_details: pointer to command details structure or NULL
4402 * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4403 * Firmware will place the complete LLDP MIB in response buffer with the
4406 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4407 u8 bridge_type, void *buff, u16 buff_size,
4408 u16 old_len, u16 new_len, u16 offset,
4410 struct i40e_asq_cmd_details *cmd_details)
4412 struct i40e_aq_desc desc;
4413 struct i40e_aqc_lldp_update_tlv *cmd =
4414 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4415 enum i40e_status_code status;
4417 if (buff_size == 0 || !buff || offset == 0 ||
4418 old_len == 0 || new_len == 0)
4419 return I40E_ERR_PARAM;
4421 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4423 /* Indirect Command */
4424 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4425 if (buff_size > I40E_AQ_LARGE_BUF)
4426 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4427 desc.datalen = CPU_TO_LE16(buff_size);
4429 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4430 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4431 cmd->old_len = CPU_TO_LE16(old_len);
4432 cmd->new_offset = CPU_TO_LE16(offset);
4433 cmd->new_len = CPU_TO_LE16(new_len);
4435 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4437 if (mib_len != NULL)
4438 *mib_len = LE16_TO_CPU(desc.datalen);
4445 * i40e_aq_delete_lldp_tlv
4446 * @hw: pointer to the hw struct
4447 * @bridge_type: type of bridge
4448 * @buff: pointer to a user supplied buffer that has the TLV
4449 * @buff_size: length of the buffer
4450 * @tlv_len: length of the TLV to be deleted
4451 * @mib_len: length of the returned LLDP MIB
4452 * @cmd_details: pointer to command details structure or NULL
4454 * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4455 * The firmware places the entire LLDP MIB in the response buffer.
4457 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4458 u8 bridge_type, void *buff, u16 buff_size,
4459 u16 tlv_len, u16 *mib_len,
4460 struct i40e_asq_cmd_details *cmd_details)
4462 struct i40e_aq_desc desc;
4463 struct i40e_aqc_lldp_add_tlv *cmd =
4464 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4465 enum i40e_status_code status;
4467 if (buff_size == 0 || !buff)
4468 return I40E_ERR_PARAM;
4470 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4472 /* Indirect Command */
4473 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4474 if (buff_size > I40E_AQ_LARGE_BUF)
4475 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4476 desc.datalen = CPU_TO_LE16(buff_size);
4477 cmd->len = CPU_TO_LE16(tlv_len);
4478 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4479 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4481 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4483 if (mib_len != NULL)
4484 *mib_len = LE16_TO_CPU(desc.datalen);
4492 * @hw: pointer to the hw struct
4493 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4494 * @cmd_details: pointer to command details structure or NULL
4496 * Stop or Shutdown the embedded LLDP Agent
4498 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4499 struct i40e_asq_cmd_details *cmd_details)
4501 struct i40e_aq_desc desc;
4502 struct i40e_aqc_lldp_stop *cmd =
4503 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4504 enum i40e_status_code status;
4506 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4509 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4511 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4517 * i40e_aq_start_lldp
4518 * @hw: pointer to the hw struct
4519 * @cmd_details: pointer to command details structure or NULL
4521 * Start the embedded LLDP Agent on all ports.
4523 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4524 struct i40e_asq_cmd_details *cmd_details)
4526 struct i40e_aq_desc desc;
4527 struct i40e_aqc_lldp_start *cmd =
4528 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4529 enum i40e_status_code status;
4531 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4533 cmd->command = I40E_AQ_LLDP_AGENT_START;
4534 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4540 * i40e_aq_set_dcb_parameters
4541 * @hw: pointer to the hw struct
4542 * @cmd_details: pointer to command details structure or NULL
4543 * @dcb_enable: True if DCB configuration needs to be applied
4546 enum i40e_status_code
4547 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable,
4548 struct i40e_asq_cmd_details *cmd_details)
4550 struct i40e_aq_desc desc;
4551 struct i40e_aqc_set_dcb_parameters *cmd =
4552 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw;
4553 enum i40e_status_code status;
4555 i40e_fill_default_direct_cmd_desc(&desc,
4556 i40e_aqc_opc_set_dcb_parameters);
4559 cmd->valid_flags = I40E_DCB_VALID;
4560 cmd->command = I40E_AQ_DCB_SET_AGENT;
4562 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4568 * i40e_aq_get_cee_dcb_config
4569 * @hw: pointer to the hw struct
4570 * @buff: response buffer that stores CEE operational configuration
4571 * @buff_size: size of the buffer passed
4572 * @cmd_details: pointer to command details structure or NULL
4574 * Get CEE DCBX mode operational configuration from firmware
4576 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4577 void *buff, u16 buff_size,
4578 struct i40e_asq_cmd_details *cmd_details)
4580 struct i40e_aq_desc desc;
4581 enum i40e_status_code status;
4583 if (buff_size == 0 || !buff)
4584 return I40E_ERR_PARAM;
4586 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4588 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4589 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4596 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4597 * @hw: pointer to the hw struct
4598 * @start_agent: True if DCBx Agent needs to be Started
4599 * False if DCBx Agent needs to be Stopped
4600 * @cmd_details: pointer to command details structure or NULL
4602 * Start/Stop the embedded dcbx Agent
4604 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4606 struct i40e_asq_cmd_details *cmd_details)
4608 struct i40e_aq_desc desc;
4609 struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4610 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4612 enum i40e_status_code status;
4614 i40e_fill_default_direct_cmd_desc(&desc,
4615 i40e_aqc_opc_lldp_stop_start_spec_agent);
4618 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4620 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4626 * i40e_aq_add_udp_tunnel
4627 * @hw: pointer to the hw struct
4628 * @udp_port: the UDP port to add in Host byte order
4629 * @protocol_index: protocol index type
4630 * @filter_index: pointer to filter index
4631 * @cmd_details: pointer to command details structure or NULL
4633 * Note: Firmware expects the udp_port value to be in Little Endian format,
4634 * and this function will call CPU_TO_LE16 to convert from Host byte order to
4635 * Little Endian order.
4637 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4638 u16 udp_port, u8 protocol_index,
4640 struct i40e_asq_cmd_details *cmd_details)
4642 struct i40e_aq_desc desc;
4643 struct i40e_aqc_add_udp_tunnel *cmd =
4644 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4645 struct i40e_aqc_del_udp_tunnel_completion *resp =
4646 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4647 enum i40e_status_code status;
4649 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4651 cmd->udp_port = CPU_TO_LE16(udp_port);
4652 cmd->protocol_type = protocol_index;
4654 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4656 if (!status && filter_index)
4657 *filter_index = resp->index;
4663 * i40e_aq_del_udp_tunnel
4664 * @hw: pointer to the hw struct
4665 * @index: filter index
4666 * @cmd_details: pointer to command details structure or NULL
4668 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4669 struct i40e_asq_cmd_details *cmd_details)
4671 struct i40e_aq_desc desc;
4672 struct i40e_aqc_remove_udp_tunnel *cmd =
4673 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4674 enum i40e_status_code status;
4676 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4680 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4686 * i40e_aq_get_switch_resource_alloc (0x0204)
4687 * @hw: pointer to the hw struct
4688 * @num_entries: pointer to u8 to store the number of resource entries returned
4689 * @buf: pointer to a user supplied buffer. This buffer must be large enough
4690 * to store the resource information for all resource types. Each
4691 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
4692 * @count: size, in bytes, of the buffer provided
4693 * @cmd_details: pointer to command details structure or NULL
4695 * Query the resources allocated to a function.
4697 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4699 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4701 struct i40e_asq_cmd_details *cmd_details)
4703 struct i40e_aq_desc desc;
4704 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4705 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4706 enum i40e_status_code status;
4707 u16 length = count * sizeof(*buf);
4709 i40e_fill_default_direct_cmd_desc(&desc,
4710 i40e_aqc_opc_get_switch_resource_alloc);
4712 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4713 if (length > I40E_AQ_LARGE_BUF)
4714 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4716 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4718 if (!status && num_entries)
4719 *num_entries = cmd_resp->num_entries;
4725 * i40e_aq_delete_element - Delete switch element
4726 * @hw: pointer to the hw struct
4727 * @seid: the SEID to delete from the switch
4728 * @cmd_details: pointer to command details structure or NULL
4730 * This deletes a switch element from the switch.
4732 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4733 struct i40e_asq_cmd_details *cmd_details)
4735 struct i40e_aq_desc desc;
4736 struct i40e_aqc_switch_seid *cmd =
4737 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4738 enum i40e_status_code status;
4741 return I40E_ERR_PARAM;
4743 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4745 cmd->seid = CPU_TO_LE16(seid);
4747 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4753 * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4754 * @hw: pointer to the hw struct
4755 * @flags: component flags
4756 * @mac_seid: uplink seid (MAC SEID)
4757 * @vsi_seid: connected vsi seid
4758 * @ret_seid: seid of create pv component
4760 * This instantiates an i40e port virtualizer with specified flags.
4761 * Depending on specified flags the port virtualizer can act as a
4762 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4764 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4765 u16 mac_seid, u16 vsi_seid,
4768 struct i40e_aq_desc desc;
4769 struct i40e_aqc_add_update_pv *cmd =
4770 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4771 struct i40e_aqc_add_update_pv_completion *resp =
4772 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4773 enum i40e_status_code status;
4776 return I40E_ERR_PARAM;
4778 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4779 cmd->command_flags = CPU_TO_LE16(flags);
4780 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4781 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4783 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4784 if (!status && ret_seid)
4785 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4791 * i40e_aq_add_tag - Add an S/E-tag
4792 * @hw: pointer to the hw struct
4793 * @direct_to_queue: should s-tag direct flow to a specific queue
4794 * @vsi_seid: VSI SEID to use this tag
4795 * @tag: value of the tag
4796 * @queue_num: queue number, only valid is direct_to_queue is true
4797 * @tags_used: return value, number of tags in use by this PF
4798 * @tags_free: return value, number of unallocated tags
4799 * @cmd_details: pointer to command details structure or NULL
4801 * This associates an S- or E-tag to a VSI in the switch complex. It returns
4802 * the number of tags allocated by the PF, and the number of unallocated
4805 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4806 u16 vsi_seid, u16 tag, u16 queue_num,
4807 u16 *tags_used, u16 *tags_free,
4808 struct i40e_asq_cmd_details *cmd_details)
4810 struct i40e_aq_desc desc;
4811 struct i40e_aqc_add_tag *cmd =
4812 (struct i40e_aqc_add_tag *)&desc.params.raw;
4813 struct i40e_aqc_add_remove_tag_completion *resp =
4814 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4815 enum i40e_status_code status;
4818 return I40E_ERR_PARAM;
4820 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4822 cmd->seid = CPU_TO_LE16(vsi_seid);
4823 cmd->tag = CPU_TO_LE16(tag);
4824 if (direct_to_queue) {
4825 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4826 cmd->queue_number = CPU_TO_LE16(queue_num);
4829 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4832 if (tags_used != NULL)
4833 *tags_used = LE16_TO_CPU(resp->tags_used);
4834 if (tags_free != NULL)
4835 *tags_free = LE16_TO_CPU(resp->tags_free);
4842 * i40e_aq_remove_tag - Remove an S- or E-tag
4843 * @hw: pointer to the hw struct
4844 * @vsi_seid: VSI SEID this tag is associated with
4845 * @tag: value of the S-tag to delete
4846 * @tags_used: return value, number of tags in use by this PF
4847 * @tags_free: return value, number of unallocated tags
4848 * @cmd_details: pointer to command details structure or NULL
4850 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
4851 * the number of tags allocated by the PF, and the number of unallocated
4854 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4855 u16 tag, u16 *tags_used, u16 *tags_free,
4856 struct i40e_asq_cmd_details *cmd_details)
4858 struct i40e_aq_desc desc;
4859 struct i40e_aqc_remove_tag *cmd =
4860 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4861 struct i40e_aqc_add_remove_tag_completion *resp =
4862 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4863 enum i40e_status_code status;
4866 return I40E_ERR_PARAM;
4868 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4870 cmd->seid = CPU_TO_LE16(vsi_seid);
4871 cmd->tag = CPU_TO_LE16(tag);
4873 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4876 if (tags_used != NULL)
4877 *tags_used = LE16_TO_CPU(resp->tags_used);
4878 if (tags_free != NULL)
4879 *tags_free = LE16_TO_CPU(resp->tags_free);
4886 * i40e_aq_add_mcast_etag - Add a multicast E-tag
4887 * @hw: pointer to the hw struct
4888 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4889 * @etag: value of E-tag to add
4890 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4891 * @buf: address of indirect buffer
4892 * @tags_used: return value, number of E-tags in use by this port
4893 * @tags_free: return value, number of unallocated M-tags
4894 * @cmd_details: pointer to command details structure or NULL
4896 * This associates a multicast E-tag to a port virtualizer. It will return
4897 * the number of tags allocated by the PF, and the number of unallocated
4900 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4901 * num_tags_in_buf long.
4903 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4904 u16 etag, u8 num_tags_in_buf, void *buf,
4905 u16 *tags_used, u16 *tags_free,
4906 struct i40e_asq_cmd_details *cmd_details)
4908 struct i40e_aq_desc desc;
4909 struct i40e_aqc_add_remove_mcast_etag *cmd =
4910 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4911 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4912 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4913 enum i40e_status_code status;
4914 u16 length = sizeof(u16) * num_tags_in_buf;
4916 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4917 return I40E_ERR_PARAM;
4919 i40e_fill_default_direct_cmd_desc(&desc,
4920 i40e_aqc_opc_add_multicast_etag);
4922 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4923 cmd->etag = CPU_TO_LE16(etag);
4924 cmd->num_unicast_etags = num_tags_in_buf;
4926 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4927 if (length > I40E_AQ_LARGE_BUF)
4928 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4930 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4933 if (tags_used != NULL)
4934 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4935 if (tags_free != NULL)
4936 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4943 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4944 * @hw: pointer to the hw struct
4945 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4946 * @etag: value of the E-tag to remove
4947 * @tags_used: return value, number of tags in use by this port
4948 * @tags_free: return value, number of unallocated tags
4949 * @cmd_details: pointer to command details structure or NULL
4951 * This deletes an E-tag from the port virtualizer. It will return
4952 * the number of tags allocated by the port, and the number of unallocated
4955 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4956 u16 etag, u16 *tags_used, u16 *tags_free,
4957 struct i40e_asq_cmd_details *cmd_details)
4959 struct i40e_aq_desc desc;
4960 struct i40e_aqc_add_remove_mcast_etag *cmd =
4961 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4962 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4963 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4964 enum i40e_status_code status;
4968 return I40E_ERR_PARAM;
4970 i40e_fill_default_direct_cmd_desc(&desc,
4971 i40e_aqc_opc_remove_multicast_etag);
4973 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4974 cmd->etag = CPU_TO_LE16(etag);
4976 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4979 if (tags_used != NULL)
4980 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4981 if (tags_free != NULL)
4982 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4989 * i40e_aq_update_tag - Update an S/E-tag
4990 * @hw: pointer to the hw struct
4991 * @vsi_seid: VSI SEID using this S-tag
4992 * @old_tag: old tag value
4993 * @new_tag: new tag value
4994 * @tags_used: return value, number of tags in use by this PF
4995 * @tags_free: return value, number of unallocated tags
4996 * @cmd_details: pointer to command details structure or NULL
4998 * This updates the value of the tag currently attached to this VSI
4999 * in the switch complex. It will return the number of tags allocated
5000 * by the PF, and the number of unallocated tags available.
5002 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
5003 u16 old_tag, u16 new_tag, u16 *tags_used,
5005 struct i40e_asq_cmd_details *cmd_details)
5007 struct i40e_aq_desc desc;
5008 struct i40e_aqc_update_tag *cmd =
5009 (struct i40e_aqc_update_tag *)&desc.params.raw;
5010 struct i40e_aqc_update_tag_completion *resp =
5011 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
5012 enum i40e_status_code status;
5015 return I40E_ERR_PARAM;
5017 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
5019 cmd->seid = CPU_TO_LE16(vsi_seid);
5020 cmd->old_tag = CPU_TO_LE16(old_tag);
5021 cmd->new_tag = CPU_TO_LE16(new_tag);
5023 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5026 if (tags_used != NULL)
5027 *tags_used = LE16_TO_CPU(resp->tags_used);
5028 if (tags_free != NULL)
5029 *tags_free = LE16_TO_CPU(resp->tags_free);
5036 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
5037 * @hw: pointer to the hw struct
5038 * @tcmap: TC map for request/release any ignore PFC condition
5039 * @request: request or release ignore PFC condition
5040 * @tcmap_ret: return TCs for which PFC is currently ignored
5041 * @cmd_details: pointer to command details structure or NULL
5043 * This sends out request/release to ignore PFC condition for a TC.
5044 * It will return the TCs for which PFC is currently ignored.
5046 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
5047 bool request, u8 *tcmap_ret,
5048 struct i40e_asq_cmd_details *cmd_details)
5050 struct i40e_aq_desc desc;
5051 struct i40e_aqc_pfc_ignore *cmd_resp =
5052 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
5053 enum i40e_status_code status;
5055 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
5058 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
5060 cmd_resp->tc_bitmap = tcmap;
5062 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5065 if (tcmap_ret != NULL)
5066 *tcmap_ret = cmd_resp->tc_bitmap;
5073 * i40e_aq_dcb_updated - DCB Updated Command
5074 * @hw: pointer to the hw struct
5075 * @cmd_details: pointer to command details structure or NULL
5077 * When LLDP is handled in PF this command is used by the PF
5078 * to notify EMP that a DCB setting is modified.
5079 * When LLDP is handled in EMP this command is used by the PF
5080 * to notify EMP whenever one of the following parameters get
5082 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
5083 * - PCIRTT in PRTDCB_GENC.PCIRTT
5084 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
5085 * EMP will return when the shared RPB settings have been
5086 * recomputed and modified. The retval field in the descriptor
5087 * will be set to 0 when RPB is modified.
5089 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
5090 struct i40e_asq_cmd_details *cmd_details)
5092 struct i40e_aq_desc desc;
5093 enum i40e_status_code status;
5095 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
5097 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5103 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
5104 * @hw: pointer to the hw struct
5105 * @seid: defines the SEID of the switch for which the stats are requested
5106 * @vlan_id: the VLAN ID for which the statistics are requested
5107 * @stat_index: index of the statistics counters block assigned to this VLAN
5108 * @cmd_details: pointer to command details structure or NULL
5110 * XL710 supports 128 smonVlanStats counters.This command is used to
5111 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
5114 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
5115 u16 vlan_id, u16 *stat_index,
5116 struct i40e_asq_cmd_details *cmd_details)
5118 struct i40e_aq_desc desc;
5119 struct i40e_aqc_add_remove_statistics *cmd_resp =
5120 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5121 enum i40e_status_code status;
5123 if ((seid == 0) || (stat_index == NULL))
5124 return I40E_ERR_PARAM;
5126 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
5128 cmd_resp->seid = CPU_TO_LE16(seid);
5129 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
5131 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5133 if (!status && stat_index)
5134 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
5140 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
5141 * @hw: pointer to the hw struct
5142 * @seid: defines the SEID of the switch for which the stats are requested
5143 * @vlan_id: the VLAN ID for which the statistics are requested
5144 * @stat_index: index of the statistics counters block assigned to this VLAN
5145 * @cmd_details: pointer to command details structure or NULL
5147 * XL710 supports 128 smonVlanStats counters.This command is used to
5148 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
5151 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
5152 u16 vlan_id, u16 stat_index,
5153 struct i40e_asq_cmd_details *cmd_details)
5155 struct i40e_aq_desc desc;
5156 struct i40e_aqc_add_remove_statistics *cmd =
5157 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5158 enum i40e_status_code status;
5161 return I40E_ERR_PARAM;
5163 i40e_fill_default_direct_cmd_desc(&desc,
5164 i40e_aqc_opc_remove_statistics);
5166 cmd->seid = CPU_TO_LE16(seid);
5167 cmd->vlan = CPU_TO_LE16(vlan_id);
5168 cmd->stat_index = CPU_TO_LE16(stat_index);
5170 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5176 * i40e_aq_set_port_parameters - set physical port parameters.
5177 * @hw: pointer to the hw struct
5178 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
5179 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
5180 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
5181 * @double_vlan: if set double VLAN is enabled
5182 * @cmd_details: pointer to command details structure or NULL
5184 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
5185 u16 bad_frame_vsi, bool save_bad_pac,
5186 bool pad_short_pac, bool double_vlan,
5187 struct i40e_asq_cmd_details *cmd_details)
5189 struct i40e_aqc_set_port_parameters *cmd;
5190 enum i40e_status_code status;
5191 struct i40e_aq_desc desc;
5192 u16 command_flags = 0;
5194 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
5196 i40e_fill_default_direct_cmd_desc(&desc,
5197 i40e_aqc_opc_set_port_parameters);
5199 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
5201 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
5203 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
5205 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
5206 cmd->command_flags = CPU_TO_LE16(command_flags);
5208 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5214 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
5215 * @hw: pointer to the hw struct
5216 * @seid: seid for the physical port/switching component/vsi
5217 * @buff: Indirect buffer to hold data parameters and response
5218 * @buff_size: Indirect buffer size
5219 * @opcode: Tx scheduler AQ command opcode
5220 * @cmd_details: pointer to command details structure or NULL
5222 * Generic command handler for Tx scheduler AQ commands
5224 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
5225 void *buff, u16 buff_size,
5226 enum i40e_admin_queue_opc opcode,
5227 struct i40e_asq_cmd_details *cmd_details)
5229 struct i40e_aq_desc desc;
5230 struct i40e_aqc_tx_sched_ind *cmd =
5231 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
5232 enum i40e_status_code status;
5233 bool cmd_param_flag = false;
5236 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
5237 case i40e_aqc_opc_configure_vsi_tc_bw:
5238 case i40e_aqc_opc_enable_switching_comp_ets:
5239 case i40e_aqc_opc_modify_switching_comp_ets:
5240 case i40e_aqc_opc_disable_switching_comp_ets:
5241 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
5242 case i40e_aqc_opc_configure_switching_comp_bw_config:
5243 cmd_param_flag = true;
5245 case i40e_aqc_opc_query_vsi_bw_config:
5246 case i40e_aqc_opc_query_vsi_ets_sla_config:
5247 case i40e_aqc_opc_query_switching_comp_ets_config:
5248 case i40e_aqc_opc_query_port_ets_config:
5249 case i40e_aqc_opc_query_switching_comp_bw_config:
5250 cmd_param_flag = false;
5253 return I40E_ERR_PARAM;
5256 i40e_fill_default_direct_cmd_desc(&desc, opcode);
5258 /* Indirect command */
5259 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5261 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5262 if (buff_size > I40E_AQ_LARGE_BUF)
5263 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5265 desc.datalen = CPU_TO_LE16(buff_size);
5267 cmd->vsi_seid = CPU_TO_LE16(seid);
5269 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5275 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5276 * @hw: pointer to the hw struct
5278 * @credit: BW limit credits (0 = disabled)
5279 * @max_credit: Max BW limit credits
5280 * @cmd_details: pointer to command details structure or NULL
5282 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5283 u16 seid, u16 credit, u8 max_credit,
5284 struct i40e_asq_cmd_details *cmd_details)
5286 struct i40e_aq_desc desc;
5287 struct i40e_aqc_configure_vsi_bw_limit *cmd =
5288 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5289 enum i40e_status_code status;
5291 i40e_fill_default_direct_cmd_desc(&desc,
5292 i40e_aqc_opc_configure_vsi_bw_limit);
5294 cmd->vsi_seid = CPU_TO_LE16(seid);
5295 cmd->credit = CPU_TO_LE16(credit);
5296 cmd->max_credit = max_credit;
5298 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5304 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5305 * @hw: pointer to the hw struct
5306 * @seid: switching component seid
5307 * @credit: BW limit credits (0 = disabled)
5308 * @max_bw: Max BW limit credits
5309 * @cmd_details: pointer to command details structure or NULL
5311 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5312 u16 seid, u16 credit, u8 max_bw,
5313 struct i40e_asq_cmd_details *cmd_details)
5315 struct i40e_aq_desc desc;
5316 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5317 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5318 enum i40e_status_code status;
5320 i40e_fill_default_direct_cmd_desc(&desc,
5321 i40e_aqc_opc_configure_switching_comp_bw_limit);
5323 cmd->seid = CPU_TO_LE16(seid);
5324 cmd->credit = CPU_TO_LE16(credit);
5325 cmd->max_bw = max_bw;
5327 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5333 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5334 * @hw: pointer to the hw struct
5336 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5337 * @cmd_details: pointer to command details structure or NULL
5339 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5341 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5342 struct i40e_asq_cmd_details *cmd_details)
5344 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5345 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5350 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5351 * @hw: pointer to the hw struct
5353 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5354 * @cmd_details: pointer to command details structure or NULL
5356 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5358 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5359 struct i40e_asq_cmd_details *cmd_details)
5361 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5362 i40e_aqc_opc_configure_vsi_tc_bw,
5367 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5368 * @hw: pointer to the hw struct
5369 * @seid: seid of the switching component connected to Physical Port
5370 * @ets_data: Buffer holding ETS parameters
5371 * @opcode: Tx scheduler AQ command opcode
5372 * @cmd_details: pointer to command details structure or NULL
5374 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5376 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5377 enum i40e_admin_queue_opc opcode,
5378 struct i40e_asq_cmd_details *cmd_details)
5380 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5381 sizeof(*ets_data), opcode, cmd_details);
5385 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5386 * @hw: pointer to the hw struct
5387 * @seid: seid of the switching component
5388 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5389 * @cmd_details: pointer to command details structure or NULL
5391 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5393 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5394 struct i40e_asq_cmd_details *cmd_details)
5396 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5397 i40e_aqc_opc_configure_switching_comp_bw_config,
5402 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5403 * @hw: pointer to the hw struct
5404 * @seid: seid of the switching component
5405 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5406 * @cmd_details: pointer to command details structure or NULL
5408 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5409 struct i40e_hw *hw, u16 seid,
5410 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5411 struct i40e_asq_cmd_details *cmd_details)
5413 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5414 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5419 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5420 * @hw: pointer to the hw struct
5421 * @seid: seid of the VSI
5422 * @bw_data: Buffer to hold VSI BW configuration
5423 * @cmd_details: pointer to command details structure or NULL
5425 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5427 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5428 struct i40e_asq_cmd_details *cmd_details)
5430 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5431 i40e_aqc_opc_query_vsi_bw_config,
5436 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5437 * @hw: pointer to the hw struct
5438 * @seid: seid of the VSI
5439 * @bw_data: Buffer to hold VSI BW configuration per TC
5440 * @cmd_details: pointer to command details structure or NULL
5442 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5444 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5445 struct i40e_asq_cmd_details *cmd_details)
5447 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5448 i40e_aqc_opc_query_vsi_ets_sla_config,
5453 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5454 * @hw: pointer to the hw struct
5455 * @seid: seid of the switching component
5456 * @bw_data: Buffer to hold switching component's per TC BW config
5457 * @cmd_details: pointer to command details structure or NULL
5459 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5461 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5462 struct i40e_asq_cmd_details *cmd_details)
5464 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5465 i40e_aqc_opc_query_switching_comp_ets_config,
5470 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5471 * @hw: pointer to the hw struct
5472 * @seid: seid of the VSI or switching component connected to Physical Port
5473 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5474 * @cmd_details: pointer to command details structure or NULL
5476 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5478 struct i40e_aqc_query_port_ets_config_resp *bw_data,
5479 struct i40e_asq_cmd_details *cmd_details)
5481 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5482 i40e_aqc_opc_query_port_ets_config,
5487 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5488 * @hw: pointer to the hw struct
5489 * @seid: seid of the switching component
5490 * @bw_data: Buffer to hold switching component's BW configuration
5491 * @cmd_details: pointer to command details structure or NULL
5493 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5495 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5496 struct i40e_asq_cmd_details *cmd_details)
5498 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5499 i40e_aqc_opc_query_switching_comp_bw_config,
5504 * i40e_validate_filter_settings
5505 * @hw: pointer to the hardware structure
5506 * @settings: Filter control settings
5508 * Check and validate the filter control settings passed.
5509 * The function checks for the valid filter/context sizes being
5510 * passed for FCoE and PE.
5512 * Returns I40E_SUCCESS if the values passed are valid and within
5513 * range else returns an error.
5515 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5516 struct i40e_filter_control_settings *settings)
5518 u32 fcoe_cntx_size, fcoe_filt_size;
5519 u32 pe_cntx_size, pe_filt_size;
5524 /* Validate FCoE settings passed */
5525 switch (settings->fcoe_filt_num) {
5526 case I40E_HASH_FILTER_SIZE_1K:
5527 case I40E_HASH_FILTER_SIZE_2K:
5528 case I40E_HASH_FILTER_SIZE_4K:
5529 case I40E_HASH_FILTER_SIZE_8K:
5530 case I40E_HASH_FILTER_SIZE_16K:
5531 case I40E_HASH_FILTER_SIZE_32K:
5532 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5533 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5536 return I40E_ERR_PARAM;
5539 switch (settings->fcoe_cntx_num) {
5540 case I40E_DMA_CNTX_SIZE_512:
5541 case I40E_DMA_CNTX_SIZE_1K:
5542 case I40E_DMA_CNTX_SIZE_2K:
5543 case I40E_DMA_CNTX_SIZE_4K:
5544 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5545 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5548 return I40E_ERR_PARAM;
5551 /* Validate PE settings passed */
5552 switch (settings->pe_filt_num) {
5553 case I40E_HASH_FILTER_SIZE_1K:
5554 case I40E_HASH_FILTER_SIZE_2K:
5555 case I40E_HASH_FILTER_SIZE_4K:
5556 case I40E_HASH_FILTER_SIZE_8K:
5557 case I40E_HASH_FILTER_SIZE_16K:
5558 case I40E_HASH_FILTER_SIZE_32K:
5559 case I40E_HASH_FILTER_SIZE_64K:
5560 case I40E_HASH_FILTER_SIZE_128K:
5561 case I40E_HASH_FILTER_SIZE_256K:
5562 case I40E_HASH_FILTER_SIZE_512K:
5563 case I40E_HASH_FILTER_SIZE_1M:
5564 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5565 pe_filt_size <<= (u32)settings->pe_filt_num;
5568 return I40E_ERR_PARAM;
5571 switch (settings->pe_cntx_num) {
5572 case I40E_DMA_CNTX_SIZE_512:
5573 case I40E_DMA_CNTX_SIZE_1K:
5574 case I40E_DMA_CNTX_SIZE_2K:
5575 case I40E_DMA_CNTX_SIZE_4K:
5576 case I40E_DMA_CNTX_SIZE_8K:
5577 case I40E_DMA_CNTX_SIZE_16K:
5578 case I40E_DMA_CNTX_SIZE_32K:
5579 case I40E_DMA_CNTX_SIZE_64K:
5580 case I40E_DMA_CNTX_SIZE_128K:
5581 case I40E_DMA_CNTX_SIZE_256K:
5582 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5583 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5586 return I40E_ERR_PARAM;
5589 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5590 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5591 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5592 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5593 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
5594 return I40E_ERR_INVALID_SIZE;
5596 return I40E_SUCCESS;
5600 * i40e_set_filter_control
5601 * @hw: pointer to the hardware structure
5602 * @settings: Filter control settings
5604 * Set the Queue Filters for PE/FCoE and enable filters required
5605 * for a single PF. It is expected that these settings are programmed
5606 * at the driver initialization time.
5608 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5609 struct i40e_filter_control_settings *settings)
5611 enum i40e_status_code ret = I40E_SUCCESS;
5612 u32 hash_lut_size = 0;
5616 return I40E_ERR_PARAM;
5618 /* Validate the input settings */
5619 ret = i40e_validate_filter_settings(hw, settings);
5623 /* Read the PF Queue Filter control register */
5624 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5626 /* Program required PE hash buckets for the PF */
5627 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5628 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5629 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5630 /* Program required PE contexts for the PF */
5631 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5632 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5633 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5635 /* Program required FCoE hash buckets for the PF */
5636 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5637 val |= ((u32)settings->fcoe_filt_num <<
5638 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5639 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5640 /* Program required FCoE DDP contexts for the PF */
5641 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5642 val |= ((u32)settings->fcoe_cntx_num <<
5643 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5644 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5646 /* Program Hash LUT size for the PF */
5647 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5648 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5650 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5651 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5653 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5654 if (settings->enable_fdir)
5655 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5656 if (settings->enable_ethtype)
5657 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5658 if (settings->enable_macvlan)
5659 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5661 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5663 return I40E_SUCCESS;
5667 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5668 * @hw: pointer to the hw struct
5669 * @mac_addr: MAC address to use in the filter
5670 * @ethtype: Ethertype to use in the filter
5671 * @flags: Flags that needs to be applied to the filter
5672 * @vsi_seid: seid of the control VSI
5673 * @queue: VSI queue number to send the packet to
5674 * @is_add: Add control packet filter if True else remove
5675 * @stats: Structure to hold information on control filter counts
5676 * @cmd_details: pointer to command details structure or NULL
5678 * This command will Add or Remove control packet filter for a control VSI.
5679 * In return it will update the total number of perfect filter count in
5682 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5683 u8 *mac_addr, u16 ethtype, u16 flags,
5684 u16 vsi_seid, u16 queue, bool is_add,
5685 struct i40e_control_filter_stats *stats,
5686 struct i40e_asq_cmd_details *cmd_details)
5688 struct i40e_aq_desc desc;
5689 struct i40e_aqc_add_remove_control_packet_filter *cmd =
5690 (struct i40e_aqc_add_remove_control_packet_filter *)
5692 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5693 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5695 enum i40e_status_code status;
5698 return I40E_ERR_PARAM;
5701 i40e_fill_default_direct_cmd_desc(&desc,
5702 i40e_aqc_opc_add_control_packet_filter);
5703 cmd->queue = CPU_TO_LE16(queue);
5705 i40e_fill_default_direct_cmd_desc(&desc,
5706 i40e_aqc_opc_remove_control_packet_filter);
5710 i40e_memcpy(cmd->mac, mac_addr, ETH_ALEN,
5711 I40E_NONDMA_TO_NONDMA);
5713 cmd->etype = CPU_TO_LE16(ethtype);
5714 cmd->flags = CPU_TO_LE16(flags);
5715 cmd->seid = CPU_TO_LE16(vsi_seid);
5717 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5719 if (!status && stats) {
5720 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5721 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5722 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5723 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5730 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5731 * @hw: pointer to the hw struct
5732 * @seid: VSI seid to add ethertype filter from
5734 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5737 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5738 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5739 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5740 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5741 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5742 enum i40e_status_code status;
5744 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5745 seid, 0, true, NULL,
5748 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5752 * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5753 * @filters: list of cloud filters
5754 * @filter_count: length of list
5756 * There's an issue in the device where the Geneve VNI layout needs
5757 * to be shifted 1 byte over from the VxLAN VNI
5759 STATIC void i40e_fix_up_geneve_vni(
5760 struct i40e_aqc_cloud_filters_element_data *filters,
5763 struct i40e_aqc_cloud_filters_element_data *f = filters;
5766 for (i = 0; i < filter_count; i++) {
5770 tnl_type = (LE16_TO_CPU(f[i].flags) &
5771 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5772 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5773 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5774 ti = LE32_TO_CPU(f[i].tenant_id);
5775 f[i].tenant_id = CPU_TO_LE32(ti << 8);
5781 * i40e_aq_add_cloud_filters
5782 * @hw: pointer to the hardware structure
5783 * @seid: VSI seid to add cloud filters from
5784 * @filters: Buffer which contains the filters to be added
5785 * @filter_count: number of filters contained in the buffer
5787 * Set the cloud filters for a given VSI. The contents of the
5788 * i40e_aqc_cloud_filters_element_data are filled
5789 * in by the caller of the function.
5792 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5794 struct i40e_aqc_cloud_filters_element_data *filters,
5797 struct i40e_aq_desc desc;
5798 struct i40e_aqc_add_remove_cloud_filters *cmd =
5799 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5800 enum i40e_status_code status;
5803 i40e_fill_default_direct_cmd_desc(&desc,
5804 i40e_aqc_opc_add_cloud_filters);
5806 buff_len = filter_count * sizeof(*filters);
5807 desc.datalen = CPU_TO_LE16(buff_len);
5808 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5809 cmd->num_filters = filter_count;
5810 cmd->seid = CPU_TO_LE16(seid);
5812 i40e_fix_up_geneve_vni(filters, filter_count);
5814 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5820 * i40e_aq_add_cloud_filters_bb
5821 * @hw: pointer to the hardware structure
5822 * @seid: VSI seid to add cloud filters from
5823 * @filters: Buffer which contains the filters in big buffer to be added
5824 * @filter_count: number of filters contained in the buffer
5826 * Set the cloud filters for a given VSI. The contents of the
5827 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5831 enum i40e_status_code
5832 i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5833 struct i40e_aqc_cloud_filters_element_bb *filters,
5836 struct i40e_aq_desc desc;
5837 struct i40e_aqc_add_remove_cloud_filters *cmd =
5838 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5839 enum i40e_status_code status;
5843 i40e_fill_default_direct_cmd_desc(&desc,
5844 i40e_aqc_opc_add_cloud_filters);
5846 buff_len = filter_count * sizeof(*filters);
5847 desc.datalen = CPU_TO_LE16(buff_len);
5848 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5849 cmd->num_filters = filter_count;
5850 cmd->seid = CPU_TO_LE16(seid);
5851 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5853 for (i = 0; i < filter_count; i++) {
5857 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5858 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5859 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5861 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5862 * one more byte further than normally used for Tenant ID in
5863 * other tunnel types.
5865 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5866 ti = LE32_TO_CPU(filters[i].element.tenant_id);
5867 filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5871 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5877 * i40e_aq_rem_cloud_filters
5878 * @hw: pointer to the hardware structure
5879 * @seid: VSI seid to remove cloud filters from
5880 * @filters: Buffer which contains the filters to be removed
5881 * @filter_count: number of filters contained in the buffer
5883 * Remove the cloud filters for a given VSI. The contents of the
5884 * i40e_aqc_cloud_filters_element_data are filled in by the caller
5888 enum i40e_status_code
5889 i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid,
5890 struct i40e_aqc_cloud_filters_element_data *filters,
5893 struct i40e_aq_desc desc;
5894 struct i40e_aqc_add_remove_cloud_filters *cmd =
5895 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5896 enum i40e_status_code status;
5899 i40e_fill_default_direct_cmd_desc(&desc,
5900 i40e_aqc_opc_remove_cloud_filters);
5902 buff_len = filter_count * sizeof(*filters);
5903 desc.datalen = CPU_TO_LE16(buff_len);
5904 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5905 cmd->num_filters = filter_count;
5906 cmd->seid = CPU_TO_LE16(seid);
5908 i40e_fix_up_geneve_vni(filters, filter_count);
5910 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5916 * i40e_aq_rem_cloud_filters_bb
5917 * @hw: pointer to the hardware structure
5918 * @seid: VSI seid to remove cloud filters from
5919 * @filters: Buffer which contains the filters in big buffer to be removed
5920 * @filter_count: number of filters contained in the buffer
5922 * Remove the big buffer cloud filters for a given VSI. The contents of the
5923 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5927 enum i40e_status_code
5928 i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5929 struct i40e_aqc_cloud_filters_element_bb *filters,
5932 struct i40e_aq_desc desc;
5933 struct i40e_aqc_add_remove_cloud_filters *cmd =
5934 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5935 enum i40e_status_code status;
5939 i40e_fill_default_direct_cmd_desc(&desc,
5940 i40e_aqc_opc_remove_cloud_filters);
5942 buff_len = filter_count * sizeof(*filters);
5943 desc.datalen = CPU_TO_LE16(buff_len);
5944 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5945 cmd->num_filters = filter_count;
5946 cmd->seid = CPU_TO_LE16(seid);
5947 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5949 for (i = 0; i < filter_count; i++) {
5953 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5954 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5955 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5957 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5958 * one more byte further than normally used for Tenant ID in
5959 * other tunnel types.
5961 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5962 ti = LE32_TO_CPU(filters[i].element.tenant_id);
5963 filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5967 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5973 * i40e_aq_replace_cloud_filters - Replace cloud filter command
5974 * @hw: pointer to the hw struct
5975 * @filters: pointer to the i40e_aqc_replace_cloud_filter_cmd struct
5976 * @cmd_buf: pointer to the i40e_aqc_replace_cloud_filter_cmd_buf struct
5980 i40e_status_code i40e_aq_replace_cloud_filters(struct i40e_hw *hw,
5981 struct i40e_aqc_replace_cloud_filters_cmd *filters,
5982 struct i40e_aqc_replace_cloud_filters_cmd_buf *cmd_buf)
5984 struct i40e_aq_desc desc;
5985 struct i40e_aqc_replace_cloud_filters_cmd *cmd =
5986 (struct i40e_aqc_replace_cloud_filters_cmd *)&desc.params.raw;
5987 enum i40e_status_code status = I40E_SUCCESS;
5990 i40e_fill_default_direct_cmd_desc(&desc,
5991 i40e_aqc_opc_replace_cloud_filters);
5993 desc.datalen = CPU_TO_LE16(32);
5994 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5995 cmd->old_filter_type = filters->old_filter_type;
5996 cmd->new_filter_type = filters->new_filter_type;
5997 cmd->valid_flags = filters->valid_flags;
5998 cmd->tr_bit = filters->tr_bit;
6000 status = i40e_asq_send_command(hw, &desc, cmd_buf,
6001 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf), NULL);
6003 /* for get cloud filters command */
6004 for (i = 0; i < 32; i += 4) {
6005 cmd_buf->filters[i / 4].filter_type = cmd_buf->data[i];
6006 cmd_buf->filters[i / 4].input[0] = cmd_buf->data[i + 1];
6007 cmd_buf->filters[i / 4].input[1] = cmd_buf->data[i + 2];
6008 cmd_buf->filters[i / 4].input[2] = cmd_buf->data[i + 3];
6016 * i40e_aq_alternate_write
6017 * @hw: pointer to the hardware structure
6018 * @reg_addr0: address of first dword to be read
6019 * @reg_val0: value to be written under 'reg_addr0'
6020 * @reg_addr1: address of second dword to be read
6021 * @reg_val1: value to be written under 'reg_addr1'
6023 * Write one or two dwords to alternate structure. Fields are indicated
6024 * by 'reg_addr0' and 'reg_addr1' register numbers.
6027 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
6028 u32 reg_addr0, u32 reg_val0,
6029 u32 reg_addr1, u32 reg_val1)
6031 struct i40e_aq_desc desc;
6032 struct i40e_aqc_alternate_write *cmd_resp =
6033 (struct i40e_aqc_alternate_write *)&desc.params.raw;
6034 enum i40e_status_code status;
6036 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
6037 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
6038 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
6039 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
6040 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
6042 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6048 * i40e_aq_alternate_write_indirect
6049 * @hw: pointer to the hardware structure
6050 * @addr: address of a first register to be modified
6051 * @dw_count: number of alternate structure fields to write
6052 * @buffer: pointer to the command buffer
6054 * Write 'dw_count' dwords from 'buffer' to alternate structure
6055 * starting at 'addr'.
6058 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
6059 u32 addr, u32 dw_count, void *buffer)
6061 struct i40e_aq_desc desc;
6062 struct i40e_aqc_alternate_ind_write *cmd_resp =
6063 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
6064 enum i40e_status_code status;
6067 return I40E_ERR_PARAM;
6069 /* Indirect command */
6070 i40e_fill_default_direct_cmd_desc(&desc,
6071 i40e_aqc_opc_alternate_write_indirect);
6073 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6074 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6075 if (dw_count > (I40E_AQ_LARGE_BUF/4))
6076 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6078 cmd_resp->address = CPU_TO_LE32(addr);
6079 cmd_resp->length = CPU_TO_LE32(dw_count);
6081 status = i40e_asq_send_command(hw, &desc, buffer,
6082 I40E_LO_DWORD(4*dw_count), NULL);
6088 * i40e_aq_alternate_read
6089 * @hw: pointer to the hardware structure
6090 * @reg_addr0: address of first dword to be read
6091 * @reg_val0: pointer for data read from 'reg_addr0'
6092 * @reg_addr1: address of second dword to be read
6093 * @reg_val1: pointer for data read from 'reg_addr1'
6095 * Read one or two dwords from alternate structure. Fields are indicated
6096 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
6097 * is not passed then only register at 'reg_addr0' is read.
6100 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
6101 u32 reg_addr0, u32 *reg_val0,
6102 u32 reg_addr1, u32 *reg_val1)
6104 struct i40e_aq_desc desc;
6105 struct i40e_aqc_alternate_write *cmd_resp =
6106 (struct i40e_aqc_alternate_write *)&desc.params.raw;
6107 enum i40e_status_code status;
6109 if (reg_val0 == NULL)
6110 return I40E_ERR_PARAM;
6112 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
6113 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
6114 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
6116 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6118 if (status == I40E_SUCCESS) {
6119 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
6121 if (reg_val1 != NULL)
6122 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
6129 * i40e_aq_alternate_read_indirect
6130 * @hw: pointer to the hardware structure
6131 * @addr: address of the alternate structure field
6132 * @dw_count: number of alternate structure fields to read
6133 * @buffer: pointer to the command buffer
6135 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
6136 * place them in 'buffer'. The buffer should be allocated by caller.
6139 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
6140 u32 addr, u32 dw_count, void *buffer)
6142 struct i40e_aq_desc desc;
6143 struct i40e_aqc_alternate_ind_write *cmd_resp =
6144 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
6145 enum i40e_status_code status;
6148 return I40E_ERR_PARAM;
6150 /* Indirect command */
6151 i40e_fill_default_direct_cmd_desc(&desc,
6152 i40e_aqc_opc_alternate_read_indirect);
6154 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6155 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6156 if (dw_count > (I40E_AQ_LARGE_BUF/4))
6157 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6159 cmd_resp->address = CPU_TO_LE32(addr);
6160 cmd_resp->length = CPU_TO_LE32(dw_count);
6162 status = i40e_asq_send_command(hw, &desc, buffer,
6163 I40E_LO_DWORD(4*dw_count), NULL);
6169 * i40e_aq_alternate_clear
6170 * @hw: pointer to the HW structure.
6172 * Clear the alternate structures of the port from which the function
6176 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
6178 struct i40e_aq_desc desc;
6179 enum i40e_status_code status;
6181 i40e_fill_default_direct_cmd_desc(&desc,
6182 i40e_aqc_opc_alternate_clear_port);
6184 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6190 * i40e_aq_alternate_write_done
6191 * @hw: pointer to the HW structure.
6192 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
6193 * @reset_needed: indicates the SW should trigger GLOBAL reset
6195 * Indicates to the FW that alternate structures have been changed.
6198 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
6199 u8 bios_mode, bool *reset_needed)
6201 struct i40e_aq_desc desc;
6202 struct i40e_aqc_alternate_write_done *cmd =
6203 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6204 enum i40e_status_code status;
6206 if (reset_needed == NULL)
6207 return I40E_ERR_PARAM;
6209 i40e_fill_default_direct_cmd_desc(&desc,
6210 i40e_aqc_opc_alternate_write_done);
6212 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
6214 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6215 if (!status && reset_needed)
6216 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
6217 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
6223 * i40e_aq_set_oem_mode
6224 * @hw: pointer to the HW structure.
6225 * @oem_mode: the OEM mode to be used
6227 * Sets the device to a specific operating mode. Currently the only supported
6228 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
6231 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
6234 struct i40e_aq_desc desc;
6235 struct i40e_aqc_alternate_write_done *cmd =
6236 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6237 enum i40e_status_code status;
6239 i40e_fill_default_direct_cmd_desc(&desc,
6240 i40e_aqc_opc_alternate_set_mode);
6242 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
6244 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6250 * i40e_aq_resume_port_tx
6251 * @hw: pointer to the hardware structure
6252 * @cmd_details: pointer to command details structure or NULL
6254 * Resume port's Tx traffic
6256 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
6257 struct i40e_asq_cmd_details *cmd_details)
6259 struct i40e_aq_desc desc;
6260 enum i40e_status_code status;
6262 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
6264 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6270 * i40e_set_pci_config_data - store PCI bus info
6271 * @hw: pointer to hardware structure
6272 * @link_status: the link status word from PCI config space
6274 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
6276 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
6278 hw->bus.type = i40e_bus_type_pci_express;
6280 switch (link_status & I40E_PCI_LINK_WIDTH) {
6281 case I40E_PCI_LINK_WIDTH_1:
6282 hw->bus.width = i40e_bus_width_pcie_x1;
6284 case I40E_PCI_LINK_WIDTH_2:
6285 hw->bus.width = i40e_bus_width_pcie_x2;
6287 case I40E_PCI_LINK_WIDTH_4:
6288 hw->bus.width = i40e_bus_width_pcie_x4;
6290 case I40E_PCI_LINK_WIDTH_8:
6291 hw->bus.width = i40e_bus_width_pcie_x8;
6294 hw->bus.width = i40e_bus_width_unknown;
6298 switch (link_status & I40E_PCI_LINK_SPEED) {
6299 case I40E_PCI_LINK_SPEED_2500:
6300 hw->bus.speed = i40e_bus_speed_2500;
6302 case I40E_PCI_LINK_SPEED_5000:
6303 hw->bus.speed = i40e_bus_speed_5000;
6305 case I40E_PCI_LINK_SPEED_8000:
6306 hw->bus.speed = i40e_bus_speed_8000;
6309 hw->bus.speed = i40e_bus_speed_unknown;
6315 * i40e_aq_debug_dump
6316 * @hw: pointer to the hardware structure
6317 * @cluster_id: specific cluster to dump
6318 * @table_id: table id within cluster
6319 * @start_index: index of line in the block to read
6320 * @buff_size: dump buffer size
6321 * @buff: dump buffer
6322 * @ret_buff_size: actual buffer size returned
6323 * @ret_next_table: next block to read
6324 * @ret_next_index: next index to read
6325 * @cmd_details: pointer to command details structure or NULL
6327 * Dump internal FW/HW data for debug purposes.
6330 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
6331 u8 table_id, u32 start_index, u16 buff_size,
6332 void *buff, u16 *ret_buff_size,
6333 u8 *ret_next_table, u32 *ret_next_index,
6334 struct i40e_asq_cmd_details *cmd_details)
6336 struct i40e_aq_desc desc;
6337 struct i40e_aqc_debug_dump_internals *cmd =
6338 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6339 struct i40e_aqc_debug_dump_internals *resp =
6340 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6341 enum i40e_status_code status;
6343 if (buff_size == 0 || !buff)
6344 return I40E_ERR_PARAM;
6346 i40e_fill_default_direct_cmd_desc(&desc,
6347 i40e_aqc_opc_debug_dump_internals);
6348 /* Indirect Command */
6349 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6350 if (buff_size > I40E_AQ_LARGE_BUF)
6351 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6353 cmd->cluster_id = cluster_id;
6354 cmd->table_id = table_id;
6355 cmd->idx = CPU_TO_LE32(start_index);
6357 desc.datalen = CPU_TO_LE16(buff_size);
6359 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
6361 if (ret_buff_size != NULL)
6362 *ret_buff_size = LE16_TO_CPU(desc.datalen);
6363 if (ret_next_table != NULL)
6364 *ret_next_table = resp->table_id;
6365 if (ret_next_index != NULL)
6366 *ret_next_index = LE32_TO_CPU(resp->idx);
6373 * i40e_read_bw_from_alt_ram
6374 * @hw: pointer to the hardware structure
6375 * @max_bw: pointer for max_bw read
6376 * @min_bw: pointer for min_bw read
6377 * @min_valid: pointer for bool that is true if min_bw is a valid value
6378 * @max_valid: pointer for bool that is true if max_bw is a valid value
6380 * Read bw from the alternate ram for the given pf
6382 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
6383 u32 *max_bw, u32 *min_bw,
6384 bool *min_valid, bool *max_valid)
6386 enum i40e_status_code status;
6387 u32 max_bw_addr, min_bw_addr;
6389 /* Calculate the address of the min/max bw registers */
6390 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6391 I40E_ALT_STRUCT_MAX_BW_OFFSET +
6392 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6393 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6394 I40E_ALT_STRUCT_MIN_BW_OFFSET +
6395 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6397 /* Read the bandwidths from alt ram */
6398 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
6399 min_bw_addr, min_bw);
6401 if (*min_bw & I40E_ALT_BW_VALID_MASK)
6406 if (*max_bw & I40E_ALT_BW_VALID_MASK)
6415 * i40e_aq_configure_partition_bw
6416 * @hw: pointer to the hardware structure
6417 * @bw_data: Buffer holding valid pfs and bw limits
6418 * @cmd_details: pointer to command details
6420 * Configure partitions guaranteed/max bw
6422 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6423 struct i40e_aqc_configure_partition_bw_data *bw_data,
6424 struct i40e_asq_cmd_details *cmd_details)
6426 enum i40e_status_code status;
6427 struct i40e_aq_desc desc;
6428 u16 bwd_size = sizeof(*bw_data);
6430 i40e_fill_default_direct_cmd_desc(&desc,
6431 i40e_aqc_opc_configure_partition_bw);
6433 /* Indirect command */
6434 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6435 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6437 desc.datalen = CPU_TO_LE16(bwd_size);
6439 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6445 * i40e_read_phy_register_clause22
6446 * @hw: pointer to the HW structure
6447 * @reg: register address in the page
6448 * @phy_addr: PHY address on MDIO interface
6449 * @value: PHY register value
6451 * Reads specified PHY register value
6453 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
6454 u16 reg, u8 phy_addr, u16 *value)
6456 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6457 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6461 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6462 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6463 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
6464 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6465 (I40E_GLGEN_MSCA_MDICMD_MASK);
6466 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6468 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6469 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6470 status = I40E_SUCCESS;
6473 i40e_usec_delay(10);
6478 i40e_debug(hw, I40E_DEBUG_PHY,
6479 "PHY: Can't write command to external PHY.\n");
6481 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6482 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6483 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6490 * i40e_write_phy_register_clause22
6491 * @hw: pointer to the HW structure
6492 * @reg: register address in the page
6493 * @phy_addr: PHY address on MDIO interface
6494 * @value: PHY register value
6496 * Writes specified PHY register value
6498 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6499 u16 reg, u8 phy_addr, u16 value)
6501 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6502 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6506 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6507 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6509 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6510 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6511 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6512 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6513 (I40E_GLGEN_MSCA_MDICMD_MASK);
6515 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6517 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6518 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6519 status = I40E_SUCCESS;
6522 i40e_usec_delay(10);
6530 * i40e_read_phy_register_clause45
6531 * @hw: pointer to the HW structure
6532 * @page: registers page number
6533 * @reg: register address in the page
6534 * @phy_addr: PHY address on MDIO interface
6535 * @value: PHY register value
6537 * Reads specified PHY register value
6539 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6540 u8 page, u16 reg, u8 phy_addr, u16 *value)
6542 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6545 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6547 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6548 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6549 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6550 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6551 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6552 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6553 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6554 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6556 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6557 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6558 status = I40E_SUCCESS;
6561 i40e_usec_delay(10);
6566 i40e_debug(hw, I40E_DEBUG_PHY,
6567 "PHY: Can't write command to external PHY.\n");
6571 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6572 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6573 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6574 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6575 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6576 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6577 status = I40E_ERR_TIMEOUT;
6579 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6581 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6582 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6583 status = I40E_SUCCESS;
6586 i40e_usec_delay(10);
6591 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6592 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6593 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6595 i40e_debug(hw, I40E_DEBUG_PHY,
6596 "PHY: Can't read register value from external PHY.\n");
6604 * i40e_write_phy_register_clause45
6605 * @hw: pointer to the HW structure
6606 * @page: registers page number
6607 * @reg: register address in the page
6608 * @phy_addr: PHY address on MDIO interface
6609 * @value: PHY register value
6611 * Writes value to specified PHY register
6613 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6614 u8 page, u16 reg, u8 phy_addr, u16 value)
6616 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6619 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6621 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6622 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6623 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6624 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6625 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6626 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6627 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6628 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6630 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6631 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6632 status = I40E_SUCCESS;
6635 i40e_usec_delay(10);
6639 i40e_debug(hw, I40E_DEBUG_PHY,
6640 "PHY: Can't write command to external PHY.\n");
6644 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6645 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6647 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6648 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6649 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6650 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6651 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6652 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6653 status = I40E_ERR_TIMEOUT;
6655 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6657 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6658 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6659 status = I40E_SUCCESS;
6662 i40e_usec_delay(10);
6671 * i40e_write_phy_register
6672 * @hw: pointer to the HW structure
6673 * @page: registers page number
6674 * @reg: register address in the page
6675 * @phy_addr: PHY address on MDIO interface
6676 * @value: PHY register value
6678 * Writes value to specified PHY register
6680 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6681 u8 page, u16 reg, u8 phy_addr, u16 value)
6683 enum i40e_status_code status;
6685 switch (hw->device_id) {
6686 case I40E_DEV_ID_1G_BASE_T_X722:
6687 status = i40e_write_phy_register_clause22(hw,
6688 reg, phy_addr, value);
6690 case I40E_DEV_ID_10G_BASE_T:
6691 case I40E_DEV_ID_10G_BASE_T4:
6692 #ifdef CARLSVILLE_HW
6693 case I40E_DEV_ID_10G_BASE_T_BC:
6695 case I40E_DEV_ID_10G_BASE_T_X722:
6696 case I40E_DEV_ID_25G_B:
6697 case I40E_DEV_ID_25G_SFP28:
6698 status = i40e_write_phy_register_clause45(hw,
6699 page, reg, phy_addr, value);
6702 status = I40E_ERR_UNKNOWN_PHY;
6710 * i40e_read_phy_register
6711 * @hw: pointer to the HW structure
6712 * @page: registers page number
6713 * @reg: register address in the page
6714 * @phy_addr: PHY address on MDIO interface
6715 * @value: PHY register value
6717 * Reads specified PHY register value
6719 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6720 u8 page, u16 reg, u8 phy_addr, u16 *value)
6722 enum i40e_status_code status;
6724 switch (hw->device_id) {
6725 case I40E_DEV_ID_1G_BASE_T_X722:
6726 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6729 case I40E_DEV_ID_10G_BASE_T:
6730 case I40E_DEV_ID_10G_BASE_T4:
6731 case I40E_DEV_ID_10G_BASE_T_X722:
6732 case I40E_DEV_ID_25G_B:
6733 case I40E_DEV_ID_25G_SFP28:
6734 status = i40e_read_phy_register_clause45(hw, page, reg,
6738 status = I40E_ERR_UNKNOWN_PHY;
6746 * i40e_get_phy_address
6747 * @hw: pointer to the HW structure
6748 * @dev_num: PHY port num that address we want
6750 * Gets PHY address for current port
6752 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6754 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6755 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6757 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6761 * i40e_blink_phy_led
6762 * @hw: pointer to the HW structure
6763 * @time: time how long led will blinks in secs
6764 * @interval: gap between LED on and off in msecs
6766 * Blinks PHY link LED
6768 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6769 u32 time, u32 interval)
6771 enum i40e_status_code status = I40E_SUCCESS;
6776 u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6780 i = rd32(hw, I40E_PFGEN_PORTNUM);
6781 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6782 phy_addr = i40e_get_phy_address(hw, port_num);
6784 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6786 status = i40e_read_phy_register_clause45(hw,
6787 I40E_PHY_COM_REG_PAGE,
6791 goto phy_blinking_end;
6793 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6795 status = i40e_write_phy_register_clause45(hw,
6796 I40E_PHY_COM_REG_PAGE,
6800 goto phy_blinking_end;
6805 if (time > 0 && interval > 0) {
6806 for (i = 0; i < time * 1000; i += interval) {
6807 status = i40e_read_phy_register_clause45(hw,
6808 I40E_PHY_COM_REG_PAGE,
6809 led_addr, phy_addr, &led_reg);
6811 goto restore_config;
6812 if (led_reg & I40E_PHY_LED_MANUAL_ON)
6815 led_reg = I40E_PHY_LED_MANUAL_ON;
6816 status = i40e_write_phy_register_clause45(hw,
6817 I40E_PHY_COM_REG_PAGE,
6818 led_addr, phy_addr, led_reg);
6820 goto restore_config;
6821 i40e_msec_delay(interval);
6826 status = i40e_write_phy_register_clause45(hw,
6827 I40E_PHY_COM_REG_PAGE,
6828 led_addr, phy_addr, led_ctl);
6835 * i40e_led_get_reg - read LED register
6836 * @hw: pointer to the HW structure
6837 * @led_addr: LED register address
6838 * @reg_val: read register value
6840 static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr,
6843 enum i40e_status_code status;
6847 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6848 status = i40e_aq_get_phy_register(hw,
6849 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6850 I40E_PHY_COM_REG_PAGE, true,
6851 I40E_PHY_LED_PROV_REG_1,
6854 phy_addr = i40e_get_phy_address(hw, hw->port);
6855 status = i40e_read_phy_register_clause45(hw,
6856 I40E_PHY_COM_REG_PAGE,
6864 * i40e_led_set_reg - write LED register
6865 * @hw: pointer to the HW structure
6866 * @led_addr: LED register address
6867 * @reg_val: register value to write
6869 static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr,
6872 enum i40e_status_code status;
6875 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6876 status = i40e_aq_set_phy_register(hw,
6877 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6878 I40E_PHY_COM_REG_PAGE, true,
6879 I40E_PHY_LED_PROV_REG_1,
6882 phy_addr = i40e_get_phy_address(hw, hw->port);
6883 status = i40e_write_phy_register_clause45(hw,
6884 I40E_PHY_COM_REG_PAGE,
6893 * i40e_led_get_phy - return current on/off mode
6894 * @hw: pointer to the hw struct
6895 * @led_addr: address of led register to use
6896 * @val: original value of register to use
6899 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6902 enum i40e_status_code status = I40E_SUCCESS;
6909 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6910 status = i40e_aq_get_phy_register(hw,
6911 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6912 I40E_PHY_COM_REG_PAGE, true,
6913 I40E_PHY_LED_PROV_REG_1,
6915 if (status == I40E_SUCCESS)
6916 *val = (u16)reg_val_aq;
6919 temp_addr = I40E_PHY_LED_PROV_REG_1;
6920 phy_addr = i40e_get_phy_address(hw, hw->port);
6921 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6923 status = i40e_read_phy_register_clause45(hw,
6924 I40E_PHY_COM_REG_PAGE,
6925 temp_addr, phy_addr,
6930 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6931 *led_addr = temp_addr;
6940 * @hw: pointer to the HW structure
6941 * @on: true or false
6942 * @led_addr: address of led register to use
6943 * @mode: original val plus bit for set or ignore
6945 * Set led's on or off when controlled by the PHY
6948 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6949 u16 led_addr, u32 mode)
6951 enum i40e_status_code status = I40E_SUCCESS;
6955 status = i40e_led_get_reg(hw, led_addr, &led_reg);
6959 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6961 status = i40e_led_set_reg(hw, led_addr, led_reg);
6965 status = i40e_led_get_reg(hw, led_addr, &led_reg);
6967 goto restore_config;
6969 led_reg = I40E_PHY_LED_MANUAL_ON;
6972 status = i40e_led_set_reg(hw, led_addr, led_reg);
6974 goto restore_config;
6975 if (mode & I40E_PHY_LED_MODE_ORIG) {
6976 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6977 status = i40e_led_set_reg(hw, led_addr, led_ctl);
6982 status = i40e_led_set_reg(hw, led_addr, led_ctl);
6985 #endif /* PF_DRIVER */
6988 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6989 * @hw: pointer to the hw struct
6990 * @reg_addr: register address
6991 * @reg_val: ptr to register value
6992 * @cmd_details: pointer to command details structure or NULL
6994 * Use the firmware to read the Rx control register,
6995 * especially useful if the Rx unit is under heavy pressure
6997 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6998 u32 reg_addr, u32 *reg_val,
6999 struct i40e_asq_cmd_details *cmd_details)
7001 struct i40e_aq_desc desc;
7002 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
7003 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
7004 enum i40e_status_code status;
7006 if (reg_val == NULL)
7007 return I40E_ERR_PARAM;
7009 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
7011 cmd_resp->address = CPU_TO_LE32(reg_addr);
7013 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7015 if (status == I40E_SUCCESS)
7016 *reg_val = LE32_TO_CPU(cmd_resp->value);
7022 * i40e_read_rx_ctl - read from an Rx control register
7023 * @hw: pointer to the hw struct
7024 * @reg_addr: register address
7026 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
7028 enum i40e_status_code status = I40E_SUCCESS;
7033 use_register = (((hw->aq.api_maj_ver == 1) &&
7034 (hw->aq.api_min_ver < 5)) ||
7035 (hw->mac.type == I40E_MAC_X722));
7036 if (!use_register) {
7038 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
7039 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
7046 /* if the AQ access failed, try the old-fashioned way */
7047 if (status || use_register)
7048 val = rd32(hw, reg_addr);
7054 * i40e_aq_rx_ctl_write_register
7055 * @hw: pointer to the hw struct
7056 * @reg_addr: register address
7057 * @reg_val: register value
7058 * @cmd_details: pointer to command details structure or NULL
7060 * Use the firmware to write to an Rx control register,
7061 * especially useful if the Rx unit is under heavy pressure
7063 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
7064 u32 reg_addr, u32 reg_val,
7065 struct i40e_asq_cmd_details *cmd_details)
7067 struct i40e_aq_desc desc;
7068 struct i40e_aqc_rx_ctl_reg_read_write *cmd =
7069 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
7070 enum i40e_status_code status;
7072 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
7074 cmd->address = CPU_TO_LE32(reg_addr);
7075 cmd->value = CPU_TO_LE32(reg_val);
7077 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7083 * i40e_write_rx_ctl - write to an Rx control register
7084 * @hw: pointer to the hw struct
7085 * @reg_addr: register address
7086 * @reg_val: register value
7088 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
7090 enum i40e_status_code status = I40E_SUCCESS;
7094 use_register = (((hw->aq.api_maj_ver == 1) &&
7095 (hw->aq.api_min_ver < 5)) ||
7096 (hw->mac.type == I40E_MAC_X722));
7097 if (!use_register) {
7099 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
7101 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
7108 /* if the AQ access failed, try the old-fashioned way */
7109 if (status || use_register)
7110 wr32(hw, reg_addr, reg_val);
7115 * i40e_aq_set_phy_register
7116 * @hw: pointer to the hw struct
7117 * @phy_select: select which phy should be accessed
7118 * @dev_addr: PHY device address
7119 * @page_change: enable auto page change
7120 * @reg_addr: PHY register address
7121 * @reg_val: new register value
7122 * @cmd_details: pointer to command details structure or NULL
7124 * Write the external PHY register.
7126 enum i40e_status_code i40e_aq_set_phy_register(struct i40e_hw *hw,
7127 u8 phy_select, u8 dev_addr, bool page_change,
7128 u32 reg_addr, u32 reg_val,
7129 struct i40e_asq_cmd_details *cmd_details)
7131 struct i40e_aq_desc desc;
7132 struct i40e_aqc_phy_register_access *cmd =
7133 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7134 enum i40e_status_code status;
7136 i40e_fill_default_direct_cmd_desc(&desc,
7137 i40e_aqc_opc_set_phy_register);
7139 cmd->phy_interface = phy_select;
7140 cmd->dev_addres = dev_addr;
7141 cmd->reg_address = CPU_TO_LE32(reg_addr);
7142 cmd->reg_value = CPU_TO_LE32(reg_val);
7145 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
7147 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7153 * i40e_aq_get_phy_register
7154 * @hw: pointer to the hw struct
7155 * @phy_select: select which phy should be accessed
7156 * @dev_addr: PHY device address
7157 * @page_change: enable auto page change
7158 * @reg_addr: PHY register address
7159 * @reg_val: read register value
7160 * @cmd_details: pointer to command details structure or NULL
7162 * Read the external PHY register.
7164 enum i40e_status_code i40e_aq_get_phy_register(struct i40e_hw *hw,
7165 u8 phy_select, u8 dev_addr, bool page_change,
7166 u32 reg_addr, u32 *reg_val,
7167 struct i40e_asq_cmd_details *cmd_details)
7169 struct i40e_aq_desc desc;
7170 struct i40e_aqc_phy_register_access *cmd =
7171 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7172 enum i40e_status_code status;
7174 i40e_fill_default_direct_cmd_desc(&desc,
7175 i40e_aqc_opc_get_phy_register);
7177 cmd->phy_interface = phy_select;
7178 cmd->dev_addres = dev_addr;
7179 cmd->reg_address = CPU_TO_LE32(reg_addr);
7182 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
7184 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7186 *reg_val = LE32_TO_CPU(cmd->reg_value);
7191 #endif /* PF_DRIVER */
7195 * i40e_aq_send_msg_to_pf
7196 * @hw: pointer to the hardware structure
7197 * @v_opcode: opcodes for VF-PF communication
7198 * @v_retval: return error code
7199 * @msg: pointer to the msg buffer
7200 * @msglen: msg length
7201 * @cmd_details: pointer to command details
7203 * Send message to PF driver using admin queue. By default, this message
7204 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
7205 * completion before returning.
7207 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
7208 enum virtchnl_ops v_opcode,
7209 enum i40e_status_code v_retval,
7210 u8 *msg, u16 msglen,
7211 struct i40e_asq_cmd_details *cmd_details)
7213 struct i40e_aq_desc desc;
7214 struct i40e_asq_cmd_details details;
7215 enum i40e_status_code status;
7217 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
7218 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
7219 desc.cookie_high = CPU_TO_LE32(v_opcode);
7220 desc.cookie_low = CPU_TO_LE32(v_retval);
7222 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
7223 | I40E_AQ_FLAG_RD));
7224 if (msglen > I40E_AQ_LARGE_BUF)
7225 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7226 desc.datalen = CPU_TO_LE16(msglen);
7229 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
7230 details.async = true;
7231 cmd_details = &details;
7233 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
7234 msglen, cmd_details);
7239 * i40e_vf_parse_hw_config
7240 * @hw: pointer to the hardware structure
7241 * @msg: pointer to the virtual channel VF resource structure
7243 * Given a VF resource message from the PF, populate the hw struct
7244 * with appropriate information.
7246 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
7247 struct virtchnl_vf_resource *msg)
7249 struct virtchnl_vsi_resource *vsi_res;
7252 vsi_res = &msg->vsi_res[0];
7254 hw->dev_caps.num_vsis = msg->num_vsis;
7255 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
7256 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
7257 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
7258 hw->dev_caps.dcb = msg->vf_cap_flags &
7259 VIRTCHNL_VF_OFFLOAD_L2;
7260 hw->dev_caps.iwarp = (msg->vf_cap_flags &
7261 VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
7262 for (i = 0; i < msg->num_vsis; i++) {
7263 if (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) {
7264 i40e_memcpy(hw->mac.perm_addr,
7265 vsi_res->default_mac_addr,
7267 I40E_NONDMA_TO_NONDMA);
7268 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
7270 I40E_NONDMA_TO_NONDMA);
7278 * @hw: pointer to the hardware structure
7280 * Send a VF_RESET message to the PF. Does not wait for response from PF
7281 * as none will be forthcoming. Immediately after calling this function,
7282 * the admin queue should be shut down and (optionally) reinitialized.
7284 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
7286 return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF,
7287 I40E_SUCCESS, NULL, 0, NULL);
7289 #endif /* VF_DRIVER */
7292 * i40e_aq_set_arp_proxy_config
7293 * @hw: pointer to the HW structure
7294 * @proxy_config: pointer to proxy config command table struct
7295 * @cmd_details: pointer to command details
7297 * Set ARP offload parameters from pre-populated
7298 * i40e_aqc_arp_proxy_data struct
7300 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
7301 struct i40e_aqc_arp_proxy_data *proxy_config,
7302 struct i40e_asq_cmd_details *cmd_details)
7304 struct i40e_aq_desc desc;
7305 enum i40e_status_code status;
7308 return I40E_ERR_PARAM;
7310 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
7312 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7313 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7314 desc.params.external.addr_high =
7315 CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
7316 desc.params.external.addr_low =
7317 CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
7318 desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_arp_proxy_data));
7320 status = i40e_asq_send_command(hw, &desc, proxy_config,
7321 sizeof(struct i40e_aqc_arp_proxy_data),
7328 * i40e_aq_opc_set_ns_proxy_table_entry
7329 * @hw: pointer to the HW structure
7330 * @ns_proxy_table_entry: pointer to NS table entry command struct
7331 * @cmd_details: pointer to command details
7333 * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
7334 * from pre-populated i40e_aqc_ns_proxy_data struct
7336 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
7337 struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
7338 struct i40e_asq_cmd_details *cmd_details)
7340 struct i40e_aq_desc desc;
7341 enum i40e_status_code status;
7343 if (!ns_proxy_table_entry)
7344 return I40E_ERR_PARAM;
7346 i40e_fill_default_direct_cmd_desc(&desc,
7347 i40e_aqc_opc_set_ns_proxy_table_entry);
7349 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7350 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7351 desc.params.external.addr_high =
7352 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
7353 desc.params.external.addr_low =
7354 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
7355 desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_ns_proxy_data));
7357 status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
7358 sizeof(struct i40e_aqc_ns_proxy_data),
7365 * i40e_aq_set_clear_wol_filter
7366 * @hw: pointer to the hw struct
7367 * @filter_index: index of filter to modify (0-7)
7368 * @filter: buffer containing filter to be set
7369 * @set_filter: true to set filter, false to clear filter
7370 * @no_wol_tco: if true, pass through packets cannot cause wake-up
7371 * if false, pass through packets may cause wake-up
7372 * @filter_valid: true if filter action is valid
7373 * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
7374 * @cmd_details: pointer to command details structure or NULL
7376 * Set or clear WoL filter for port attached to the PF
7378 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
7380 struct i40e_aqc_set_wol_filter_data *filter,
7381 bool set_filter, bool no_wol_tco,
7382 bool filter_valid, bool no_wol_tco_valid,
7383 struct i40e_asq_cmd_details *cmd_details)
7385 struct i40e_aq_desc desc;
7386 struct i40e_aqc_set_wol_filter *cmd =
7387 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
7388 enum i40e_status_code status;
7390 u16 valid_flags = 0;
7393 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
7395 if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
7396 return I40E_ERR_PARAM;
7397 cmd->filter_index = CPU_TO_LE16(filter_index);
7401 return I40E_ERR_PARAM;
7403 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
7404 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR;
7408 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
7409 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
7412 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
7413 if (no_wol_tco_valid)
7414 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
7415 cmd->valid_flags = CPU_TO_LE16(valid_flags);
7417 buff_len = sizeof(*filter);
7418 desc.datalen = CPU_TO_LE16(buff_len);
7420 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7421 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7423 cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
7424 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
7426 status = i40e_asq_send_command(hw, &desc, filter,
7427 buff_len, cmd_details);
7433 * i40e_aq_get_wake_event_reason
7434 * @hw: pointer to the hw struct
7435 * @wake_reason: return value, index of matching filter
7436 * @cmd_details: pointer to command details structure or NULL
7438 * Get information for the reason of a Wake Up event
7440 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
7442 struct i40e_asq_cmd_details *cmd_details)
7444 struct i40e_aq_desc desc;
7445 struct i40e_aqc_get_wake_reason_completion *resp =
7446 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
7447 enum i40e_status_code status;
7449 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
7451 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7453 if (status == I40E_SUCCESS)
7454 *wake_reason = LE16_TO_CPU(resp->wake_reason);
7460 * i40e_aq_clear_all_wol_filters
7461 * @hw: pointer to the hw struct
7462 * @cmd_details: pointer to command details structure or NULL
7464 * Get information for the reason of a Wake Up event
7466 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw,
7467 struct i40e_asq_cmd_details *cmd_details)
7469 struct i40e_aq_desc desc;
7470 enum i40e_status_code status;
7472 i40e_fill_default_direct_cmd_desc(&desc,
7473 i40e_aqc_opc_clear_all_wol_filters);
7475 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7481 * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
7482 * @hw: pointer to the hw struct
7483 * @buff: command buffer (size in bytes = buff_size)
7484 * @buff_size: buffer size in bytes
7485 * @track_id: package tracking id
7486 * @error_offset: returns error offset
7487 * @error_info: returns error information
7488 * @cmd_details: pointer to command details structure or NULL
7491 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
7492 u16 buff_size, u32 track_id,
7493 u32 *error_offset, u32 *error_info,
7494 struct i40e_asq_cmd_details *cmd_details)
7496 struct i40e_aq_desc desc;
7497 struct i40e_aqc_write_personalization_profile *cmd =
7498 (struct i40e_aqc_write_personalization_profile *)
7500 struct i40e_aqc_write_ddp_resp *resp;
7501 enum i40e_status_code status;
7503 i40e_fill_default_direct_cmd_desc(&desc,
7504 i40e_aqc_opc_write_personalization_profile);
7506 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
7507 if (buff_size > I40E_AQ_LARGE_BUF)
7508 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7510 desc.datalen = CPU_TO_LE16(buff_size);
7512 cmd->profile_track_id = CPU_TO_LE32(track_id);
7514 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7516 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
7518 *error_offset = LE32_TO_CPU(resp->error_offset);
7520 *error_info = LE32_TO_CPU(resp->error_info);
7527 * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
7528 * @hw: pointer to the hw struct
7529 * @buff: command buffer (size in bytes = buff_size)
7530 * @buff_size: buffer size in bytes
7531 * @flags: AdminQ command flags
7532 * @cmd_details: pointer to command details structure or NULL
7535 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
7536 u16 buff_size, u8 flags,
7537 struct i40e_asq_cmd_details *cmd_details)
7539 struct i40e_aq_desc desc;
7540 struct i40e_aqc_get_applied_profiles *cmd =
7541 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
7542 enum i40e_status_code status;
7544 i40e_fill_default_direct_cmd_desc(&desc,
7545 i40e_aqc_opc_get_personalization_profile_list);
7547 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7548 if (buff_size > I40E_AQ_LARGE_BUF)
7549 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7550 desc.datalen = CPU_TO_LE16(buff_size);
7554 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7560 * i40e_find_segment_in_package
7561 * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
7562 * @pkg_hdr: pointer to the package header to be searched
7564 * This function searches a package file for a particular segment type. On
7565 * success it returns a pointer to the segment header, otherwise it will
7568 struct i40e_generic_seg_header *
7569 i40e_find_segment_in_package(u32 segment_type,
7570 struct i40e_package_header *pkg_hdr)
7572 struct i40e_generic_seg_header *segment;
7575 /* Search all package segments for the requested segment type */
7576 for (i = 0; i < pkg_hdr->segment_count; i++) {
7578 (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
7579 pkg_hdr->segment_offset[i]);
7581 if (segment->type == segment_type)
7588 /* Get section table in profile */
7589 #define I40E_SECTION_TABLE(profile, sec_tbl) \
7591 struct i40e_profile_segment *p = (profile); \
7594 count = p->device_table_count; \
7595 nvm = (u32 *)&p->device_table[count]; \
7596 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \
7599 /* Get section header in profile */
7600 #define I40E_SECTION_HEADER(profile, offset) \
7601 (struct i40e_profile_section_header *)((u8 *)(profile) + (offset))
7604 * i40e_find_section_in_profile
7605 * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE)
7606 * @profile: pointer to the i40e segment header to be searched
7608 * This function searches i40e segment for a particular section type. On
7609 * success it returns a pointer to the section header, otherwise it will
7612 struct i40e_profile_section_header *
7613 i40e_find_section_in_profile(u32 section_type,
7614 struct i40e_profile_segment *profile)
7616 struct i40e_profile_section_header *sec;
7617 struct i40e_section_table *sec_tbl;
7621 if (profile->header.type != SEGMENT_TYPE_I40E)
7624 I40E_SECTION_TABLE(profile, sec_tbl);
7626 for (i = 0; i < sec_tbl->section_count; i++) {
7627 sec_off = sec_tbl->section_offset[i];
7628 sec = I40E_SECTION_HEADER(profile, sec_off);
7629 if (sec->section.type == section_type)
7637 * i40e_ddp_exec_aq_section - Execute generic AQ for DDP
7638 * @hw: pointer to the hw struct
7639 * @aq: command buffer containing all data to execute AQ
7642 i40e_status_code i40e_ddp_exec_aq_section(struct i40e_hw *hw,
7643 struct i40e_profile_aq_section *aq)
7645 enum i40e_status_code status;
7646 struct i40e_aq_desc desc;
7650 i40e_fill_default_direct_cmd_desc(&desc, aq->opcode);
7651 desc.flags |= CPU_TO_LE16(aq->flags);
7652 i40e_memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw),
7653 I40E_NONDMA_TO_NONDMA);
7655 msglen = aq->datalen;
7657 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
7659 if (msglen > I40E_AQ_LARGE_BUF)
7660 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7661 desc.datalen = CPU_TO_LE16(msglen);
7665 status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL);
7667 if (status != I40E_SUCCESS) {
7668 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7669 "unable to exec DDP AQ opcode %u, error %d\n",
7670 aq->opcode, status);
7674 /* copy returned desc to aq_buf */
7675 i40e_memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw),
7676 I40E_NONDMA_TO_NONDMA);
7678 return I40E_SUCCESS;
7682 * i40e_validate_profile
7683 * @hw: pointer to the hardware structure
7684 * @profile: pointer to the profile segment of the package to be validated
7685 * @track_id: package tracking id
7686 * @rollback: flag if the profile is for rollback.
7688 * Validates supported devices and profile's sections.
7690 STATIC enum i40e_status_code
7691 i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7692 u32 track_id, bool rollback)
7694 struct i40e_profile_section_header *sec = NULL;
7695 enum i40e_status_code status = I40E_SUCCESS;
7696 struct i40e_section_table *sec_tbl;
7702 if (track_id == I40E_DDP_TRACKID_INVALID) {
7703 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n");
7704 return I40E_NOT_SUPPORTED;
7707 dev_cnt = profile->device_table_count;
7708 for (i = 0; i < dev_cnt; i++) {
7709 vendor_dev_id = profile->device_table[i].vendor_dev_id;
7710 if ((vendor_dev_id >> 16) == I40E_INTEL_VENDOR_ID &&
7711 hw->device_id == (vendor_dev_id & 0xFFFF))
7714 if (dev_cnt && (i == dev_cnt)) {
7715 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7716 "Device doesn't support DDP\n");
7717 return I40E_ERR_DEVICE_NOT_SUPPORTED;
7720 I40E_SECTION_TABLE(profile, sec_tbl);
7722 /* Validate sections types */
7723 for (i = 0; i < sec_tbl->section_count; i++) {
7724 sec_off = sec_tbl->section_offset[i];
7725 sec = I40E_SECTION_HEADER(profile, sec_off);
7727 if (sec->section.type == SECTION_TYPE_MMIO ||
7728 sec->section.type == SECTION_TYPE_AQ ||
7729 sec->section.type == SECTION_TYPE_RB_AQ) {
7730 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7731 "Not a roll-back package\n");
7732 return I40E_NOT_SUPPORTED;
7735 if (sec->section.type == SECTION_TYPE_RB_AQ ||
7736 sec->section.type == SECTION_TYPE_RB_MMIO) {
7737 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7738 "Not an original package\n");
7739 return I40E_NOT_SUPPORTED;
7748 * i40e_write_profile
7749 * @hw: pointer to the hardware structure
7750 * @profile: pointer to the profile segment of the package to be downloaded
7751 * @track_id: package tracking id
7753 * Handles the download of a complete package.
7755 enum i40e_status_code
7756 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7759 enum i40e_status_code status = I40E_SUCCESS;
7760 struct i40e_section_table *sec_tbl;
7761 struct i40e_profile_section_header *sec = NULL;
7762 struct i40e_profile_aq_section *ddp_aq;
7763 u32 section_size = 0;
7764 u32 offset = 0, info = 0;
7768 status = i40e_validate_profile(hw, profile, track_id, false);
7772 I40E_SECTION_TABLE(profile, sec_tbl);
7774 for (i = 0; i < sec_tbl->section_count; i++) {
7775 sec_off = sec_tbl->section_offset[i];
7776 sec = I40E_SECTION_HEADER(profile, sec_off);
7777 /* Process generic admin command */
7778 if (sec->section.type == SECTION_TYPE_AQ) {
7779 ddp_aq = (struct i40e_profile_aq_section *)&sec[1];
7780 status = i40e_ddp_exec_aq_section(hw, ddp_aq);
7782 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7783 "Failed to execute aq: section %d, opcode %u\n",
7787 sec->section.type = SECTION_TYPE_RB_AQ;
7790 /* Skip any non-mmio sections */
7791 if (sec->section.type != SECTION_TYPE_MMIO)
7794 section_size = sec->section.size +
7795 sizeof(struct i40e_profile_section_header);
7797 /* Write MMIO section */
7798 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
7799 track_id, &offset, &info, NULL);
7801 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7802 "Failed to write profile: section %d, offset %d, info %d\n",
7811 * i40e_rollback_profile
7812 * @hw: pointer to the hardware structure
7813 * @profile: pointer to the profile segment of the package to be removed
7814 * @track_id: package tracking id
7816 * Rolls back previously loaded package.
7818 enum i40e_status_code
7819 i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7822 struct i40e_profile_section_header *sec = NULL;
7823 enum i40e_status_code status = I40E_SUCCESS;
7824 struct i40e_section_table *sec_tbl;
7825 u32 offset = 0, info = 0;
7826 u32 section_size = 0;
7830 status = i40e_validate_profile(hw, profile, track_id, true);
7834 I40E_SECTION_TABLE(profile, sec_tbl);
7836 /* For rollback write sections in reverse */
7837 for (i = sec_tbl->section_count - 1; i >= 0; i--) {
7838 sec_off = sec_tbl->section_offset[i];
7839 sec = I40E_SECTION_HEADER(profile, sec_off);
7841 /* Skip any non-rollback sections */
7842 if (sec->section.type != SECTION_TYPE_RB_MMIO)
7845 section_size = sec->section.size +
7846 sizeof(struct i40e_profile_section_header);
7848 /* Write roll-back MMIO section */
7849 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
7850 track_id, &offset, &info, NULL);
7852 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7853 "Failed to write profile: section %d, offset %d, info %d\n",
7862 * i40e_add_pinfo_to_list
7863 * @hw: pointer to the hardware structure
7864 * @profile: pointer to the profile segment of the package
7865 * @profile_info_sec: buffer for information section
7866 * @track_id: package tracking id
7868 * Register a profile to the list of loaded profiles.
7870 enum i40e_status_code
7871 i40e_add_pinfo_to_list(struct i40e_hw *hw,
7872 struct i40e_profile_segment *profile,
7873 u8 *profile_info_sec, u32 track_id)
7875 enum i40e_status_code status = I40E_SUCCESS;
7876 struct i40e_profile_section_header *sec = NULL;
7877 struct i40e_profile_info *pinfo;
7878 u32 offset = 0, info = 0;
7880 sec = (struct i40e_profile_section_header *)profile_info_sec;
7882 sec->data_end = sizeof(struct i40e_profile_section_header) +
7883 sizeof(struct i40e_profile_info);
7884 sec->section.type = SECTION_TYPE_INFO;
7885 sec->section.offset = sizeof(struct i40e_profile_section_header);
7886 sec->section.size = sizeof(struct i40e_profile_info);
7887 pinfo = (struct i40e_profile_info *)(profile_info_sec +
7888 sec->section.offset);
7889 pinfo->track_id = track_id;
7890 pinfo->version = profile->version;
7891 pinfo->op = I40E_DDP_ADD_TRACKID;
7892 i40e_memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE,
7893 I40E_NONDMA_TO_NONDMA);
7895 status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
7896 track_id, &offset, &info, NULL);