1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "i40e_type.h"
35 #include "i40e_adminq.h"
36 #include "i40e_prototype.h"
37 #include "i40e_virtchnl.h"
41 * i40e_set_mac_type - Sets MAC type
42 * @hw: pointer to the HW structure
44 * This function sets the mac type of the adapter based on the
45 * vendor ID and device ID stored in the hw structure.
47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
53 enum i40e_status_code status = I40E_SUCCESS;
55 DEBUGFUNC("i40e_set_mac_type\n");
57 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
58 switch (hw->device_id) {
59 case I40E_DEV_ID_SFP_XL710:
60 case I40E_DEV_ID_QEMU:
61 case I40E_DEV_ID_KX_A:
62 case I40E_DEV_ID_KX_B:
63 case I40E_DEV_ID_KX_C:
64 case I40E_DEV_ID_QSFP_A:
65 case I40E_DEV_ID_QSFP_B:
66 case I40E_DEV_ID_QSFP_C:
67 case I40E_DEV_ID_10G_BASE_T:
68 case I40E_DEV_ID_10G_BASE_T4:
69 case I40E_DEV_ID_20G_KR2:
70 case I40E_DEV_ID_20G_KR2_A:
71 hw->mac.type = I40E_MAC_XL710;
74 case I40E_DEV_ID_VF_HV:
75 hw->mac.type = I40E_MAC_VF;
78 hw->mac.type = I40E_MAC_GENERIC;
82 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
85 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
86 hw->mac.type, status);
90 #ifndef I40E_NDIS_SUPPORT
92 * i40e_aq_str - convert AQ err code to a string
93 * @hw: pointer to the HW structure
94 * @aq_err: the AQ error code to convert
96 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
101 case I40E_AQ_RC_EPERM:
102 return "I40E_AQ_RC_EPERM";
103 case I40E_AQ_RC_ENOENT:
104 return "I40E_AQ_RC_ENOENT";
105 case I40E_AQ_RC_ESRCH:
106 return "I40E_AQ_RC_ESRCH";
107 case I40E_AQ_RC_EINTR:
108 return "I40E_AQ_RC_EINTR";
110 return "I40E_AQ_RC_EIO";
111 case I40E_AQ_RC_ENXIO:
112 return "I40E_AQ_RC_ENXIO";
113 case I40E_AQ_RC_E2BIG:
114 return "I40E_AQ_RC_E2BIG";
115 case I40E_AQ_RC_EAGAIN:
116 return "I40E_AQ_RC_EAGAIN";
117 case I40E_AQ_RC_ENOMEM:
118 return "I40E_AQ_RC_ENOMEM";
119 case I40E_AQ_RC_EACCES:
120 return "I40E_AQ_RC_EACCES";
121 case I40E_AQ_RC_EFAULT:
122 return "I40E_AQ_RC_EFAULT";
123 case I40E_AQ_RC_EBUSY:
124 return "I40E_AQ_RC_EBUSY";
125 case I40E_AQ_RC_EEXIST:
126 return "I40E_AQ_RC_EEXIST";
127 case I40E_AQ_RC_EINVAL:
128 return "I40E_AQ_RC_EINVAL";
129 case I40E_AQ_RC_ENOTTY:
130 return "I40E_AQ_RC_ENOTTY";
131 case I40E_AQ_RC_ENOSPC:
132 return "I40E_AQ_RC_ENOSPC";
133 case I40E_AQ_RC_ENOSYS:
134 return "I40E_AQ_RC_ENOSYS";
135 case I40E_AQ_RC_ERANGE:
136 return "I40E_AQ_RC_ERANGE";
137 case I40E_AQ_RC_EFLUSHED:
138 return "I40E_AQ_RC_EFLUSHED";
139 case I40E_AQ_RC_BAD_ADDR:
140 return "I40E_AQ_RC_BAD_ADDR";
141 case I40E_AQ_RC_EMODE:
142 return "I40E_AQ_RC_EMODE";
143 case I40E_AQ_RC_EFBIG:
144 return "I40E_AQ_RC_EFBIG";
147 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
152 * i40e_stat_str - convert status err code to a string
153 * @hw: pointer to the HW structure
154 * @stat_err: the status error code to convert
156 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
162 return "I40E_ERR_NVM";
163 case I40E_ERR_NVM_CHECKSUM:
164 return "I40E_ERR_NVM_CHECKSUM";
166 return "I40E_ERR_PHY";
167 case I40E_ERR_CONFIG:
168 return "I40E_ERR_CONFIG";
170 return "I40E_ERR_PARAM";
171 case I40E_ERR_MAC_TYPE:
172 return "I40E_ERR_MAC_TYPE";
173 case I40E_ERR_UNKNOWN_PHY:
174 return "I40E_ERR_UNKNOWN_PHY";
175 case I40E_ERR_LINK_SETUP:
176 return "I40E_ERR_LINK_SETUP";
177 case I40E_ERR_ADAPTER_STOPPED:
178 return "I40E_ERR_ADAPTER_STOPPED";
179 case I40E_ERR_INVALID_MAC_ADDR:
180 return "I40E_ERR_INVALID_MAC_ADDR";
181 case I40E_ERR_DEVICE_NOT_SUPPORTED:
182 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
183 case I40E_ERR_MASTER_REQUESTS_PENDING:
184 return "I40E_ERR_MASTER_REQUESTS_PENDING";
185 case I40E_ERR_INVALID_LINK_SETTINGS:
186 return "I40E_ERR_INVALID_LINK_SETTINGS";
187 case I40E_ERR_AUTONEG_NOT_COMPLETE:
188 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
189 case I40E_ERR_RESET_FAILED:
190 return "I40E_ERR_RESET_FAILED";
191 case I40E_ERR_SWFW_SYNC:
192 return "I40E_ERR_SWFW_SYNC";
193 case I40E_ERR_NO_AVAILABLE_VSI:
194 return "I40E_ERR_NO_AVAILABLE_VSI";
195 case I40E_ERR_NO_MEMORY:
196 return "I40E_ERR_NO_MEMORY";
197 case I40E_ERR_BAD_PTR:
198 return "I40E_ERR_BAD_PTR";
199 case I40E_ERR_RING_FULL:
200 return "I40E_ERR_RING_FULL";
201 case I40E_ERR_INVALID_PD_ID:
202 return "I40E_ERR_INVALID_PD_ID";
203 case I40E_ERR_INVALID_QP_ID:
204 return "I40E_ERR_INVALID_QP_ID";
205 case I40E_ERR_INVALID_CQ_ID:
206 return "I40E_ERR_INVALID_CQ_ID";
207 case I40E_ERR_INVALID_CEQ_ID:
208 return "I40E_ERR_INVALID_CEQ_ID";
209 case I40E_ERR_INVALID_AEQ_ID:
210 return "I40E_ERR_INVALID_AEQ_ID";
211 case I40E_ERR_INVALID_SIZE:
212 return "I40E_ERR_INVALID_SIZE";
213 case I40E_ERR_INVALID_ARP_INDEX:
214 return "I40E_ERR_INVALID_ARP_INDEX";
215 case I40E_ERR_INVALID_FPM_FUNC_ID:
216 return "I40E_ERR_INVALID_FPM_FUNC_ID";
217 case I40E_ERR_QP_INVALID_MSG_SIZE:
218 return "I40E_ERR_QP_INVALID_MSG_SIZE";
219 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
220 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
221 case I40E_ERR_INVALID_FRAG_COUNT:
222 return "I40E_ERR_INVALID_FRAG_COUNT";
223 case I40E_ERR_QUEUE_EMPTY:
224 return "I40E_ERR_QUEUE_EMPTY";
225 case I40E_ERR_INVALID_ALIGNMENT:
226 return "I40E_ERR_INVALID_ALIGNMENT";
227 case I40E_ERR_FLUSHED_QUEUE:
228 return "I40E_ERR_FLUSHED_QUEUE";
229 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
230 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
231 case I40E_ERR_INVALID_IMM_DATA_SIZE:
232 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
233 case I40E_ERR_TIMEOUT:
234 return "I40E_ERR_TIMEOUT";
235 case I40E_ERR_OPCODE_MISMATCH:
236 return "I40E_ERR_OPCODE_MISMATCH";
237 case I40E_ERR_CQP_COMPL_ERROR:
238 return "I40E_ERR_CQP_COMPL_ERROR";
239 case I40E_ERR_INVALID_VF_ID:
240 return "I40E_ERR_INVALID_VF_ID";
241 case I40E_ERR_INVALID_HMCFN_ID:
242 return "I40E_ERR_INVALID_HMCFN_ID";
243 case I40E_ERR_BACKING_PAGE_ERROR:
244 return "I40E_ERR_BACKING_PAGE_ERROR";
245 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
246 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
247 case I40E_ERR_INVALID_PBLE_INDEX:
248 return "I40E_ERR_INVALID_PBLE_INDEX";
249 case I40E_ERR_INVALID_SD_INDEX:
250 return "I40E_ERR_INVALID_SD_INDEX";
251 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
252 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
253 case I40E_ERR_INVALID_SD_TYPE:
254 return "I40E_ERR_INVALID_SD_TYPE";
255 case I40E_ERR_MEMCPY_FAILED:
256 return "I40E_ERR_MEMCPY_FAILED";
257 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
258 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
259 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
260 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
261 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
262 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
263 case I40E_ERR_SRQ_ENABLED:
264 return "I40E_ERR_SRQ_ENABLED";
265 case I40E_ERR_ADMIN_QUEUE_ERROR:
266 return "I40E_ERR_ADMIN_QUEUE_ERROR";
267 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
268 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
269 case I40E_ERR_BUF_TOO_SHORT:
270 return "I40E_ERR_BUF_TOO_SHORT";
271 case I40E_ERR_ADMIN_QUEUE_FULL:
272 return "I40E_ERR_ADMIN_QUEUE_FULL";
273 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
274 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
275 case I40E_ERR_BAD_IWARP_CQE:
276 return "I40E_ERR_BAD_IWARP_CQE";
277 case I40E_ERR_NVM_BLANK_MODE:
278 return "I40E_ERR_NVM_BLANK_MODE";
279 case I40E_ERR_NOT_IMPLEMENTED:
280 return "I40E_ERR_NOT_IMPLEMENTED";
281 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
282 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
283 case I40E_ERR_DIAG_TEST_FAILED:
284 return "I40E_ERR_DIAG_TEST_FAILED";
285 case I40E_ERR_NOT_READY:
286 return "I40E_ERR_NOT_READY";
287 case I40E_NOT_SUPPORTED:
288 return "I40E_NOT_SUPPORTED";
289 case I40E_ERR_FIRMWARE_API_VERSION:
290 return "I40E_ERR_FIRMWARE_API_VERSION";
293 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
297 #endif /* I40E_NDIS_SUPPORT */
300 * @hw: debug mask related to admin queue
302 * @desc: pointer to admin queue descriptor
303 * @buffer: pointer to command buffer
304 * @buf_len: max length of buffer
306 * Dumps debug log about adminq command with descriptor contents.
308 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
309 void *buffer, u16 buf_len)
311 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
312 u16 len = LE16_TO_CPU(aq_desc->datalen);
313 u8 *buf = (u8 *)buffer;
316 if ((!(mask & hw->debug_mask)) || (desc == NULL))
320 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
321 LE16_TO_CPU(aq_desc->opcode),
322 LE16_TO_CPU(aq_desc->flags),
323 LE16_TO_CPU(aq_desc->datalen),
324 LE16_TO_CPU(aq_desc->retval));
325 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
326 LE32_TO_CPU(aq_desc->cookie_high),
327 LE32_TO_CPU(aq_desc->cookie_low));
328 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
329 LE32_TO_CPU(aq_desc->params.internal.param0),
330 LE32_TO_CPU(aq_desc->params.internal.param1));
331 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
332 LE32_TO_CPU(aq_desc->params.external.addr_high),
333 LE32_TO_CPU(aq_desc->params.external.addr_low));
335 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
336 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
339 /* write the full 16-byte chunks */
340 for (i = 0; i < (len - 16); i += 16)
342 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
343 i, buf[i], buf[i+1], buf[i+2], buf[i+3],
344 buf[i+4], buf[i+5], buf[i+6], buf[i+7],
345 buf[i+8], buf[i+9], buf[i+10], buf[i+11],
346 buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
347 /* the most we could have left is 16 bytes, pad with zeros */
352 memset(d_buf, 0, sizeof(d_buf));
353 for (j = 0; i < len; j++, i++)
356 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
357 i, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
358 d_buf[4], d_buf[5], d_buf[6], d_buf[7],
359 d_buf[8], d_buf[9], d_buf[10], d_buf[11],
360 d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
366 * i40e_check_asq_alive
367 * @hw: pointer to the hw struct
369 * Returns true if Queue is enabled else false.
371 bool i40e_check_asq_alive(struct i40e_hw *hw)
377 return !!(rd32(hw, hw->aq.asq.len) &
378 I40E_PF_ATQLEN_ATQENABLE_MASK);
380 return !!(rd32(hw, hw->aq.asq.len) &
381 I40E_PF_ATQLEN_ATQENABLE_MASK);
382 #endif /* INTEGRATED_VF */
383 #endif /* PF_DRIVER */
387 return !!(rd32(hw, hw->aq.asq.len) &
388 I40E_VF_ATQLEN1_ATQENABLE_MASK);
390 return !!(rd32(hw, hw->aq.asq.len) &
391 I40E_VF_ATQLEN1_ATQENABLE_MASK);
392 #endif /* INTEGRATED_VF */
393 #endif /* VF_DRIVER */
398 * i40e_aq_queue_shutdown
399 * @hw: pointer to the hw struct
400 * @unloading: is the driver unloading itself
402 * Tell the Firmware that we're shutting down the AdminQ and whether
403 * or not the driver is unloading as well.
405 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
408 struct i40e_aq_desc desc;
409 struct i40e_aqc_queue_shutdown *cmd =
410 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
411 enum i40e_status_code status;
413 i40e_fill_default_direct_cmd_desc(&desc,
414 i40e_aqc_opc_queue_shutdown);
417 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
418 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
423 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
424 * hardware to a bit-field that can be used by SW to more easily determine the
427 * Macros are used to shorten the table lines and make this table human
430 * We store the PTYPE in the top byte of the bit field - this is just so that
431 * we can check that the table doesn't have a row missing, as the index into
432 * the table should be the PTYPE.
436 * IF NOT i40e_ptype_lookup[ptype].known
439 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
440 * Use the rest of the fields to look at the tunnels, inner protocols, etc
442 * Use the enum i40e_rx_l2_ptype to decode the packet type
446 /* macro to make the table lines short */
447 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
450 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
451 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
452 I40E_RX_PTYPE_##OUTER_FRAG, \
453 I40E_RX_PTYPE_TUNNEL_##T, \
454 I40E_RX_PTYPE_TUNNEL_END_##TE, \
455 I40E_RX_PTYPE_##TEF, \
456 I40E_RX_PTYPE_INNER_PROT_##I, \
457 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
459 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
460 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
462 /* shorter macros makes the table fit but are terse */
463 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
464 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
465 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
467 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
468 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
469 /* L2 Packet types */
470 I40E_PTT_UNUSED_ENTRY(0),
471 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
472 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
473 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
474 I40E_PTT_UNUSED_ENTRY(4),
475 I40E_PTT_UNUSED_ENTRY(5),
476 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
477 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
478 I40E_PTT_UNUSED_ENTRY(8),
479 I40E_PTT_UNUSED_ENTRY(9),
480 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
481 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
482 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
483 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
484 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
485 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
486 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
487 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
488 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
489 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
490 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
491 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
493 /* Non Tunneled IPv4 */
494 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
495 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
496 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
497 I40E_PTT_UNUSED_ENTRY(25),
498 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
499 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
500 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
503 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
504 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
505 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
506 I40E_PTT_UNUSED_ENTRY(32),
507 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
508 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
509 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
512 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
513 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
514 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
515 I40E_PTT_UNUSED_ENTRY(39),
516 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
517 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
518 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
520 /* IPv4 --> GRE/NAT */
521 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
523 /* IPv4 --> GRE/NAT --> IPv4 */
524 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
525 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
526 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
527 I40E_PTT_UNUSED_ENTRY(47),
528 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
529 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
530 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
532 /* IPv4 --> GRE/NAT --> IPv6 */
533 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
534 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
535 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
536 I40E_PTT_UNUSED_ENTRY(54),
537 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
538 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
539 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
541 /* IPv4 --> GRE/NAT --> MAC */
542 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
544 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
545 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
546 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
547 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
548 I40E_PTT_UNUSED_ENTRY(62),
549 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
550 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
551 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
553 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
554 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
555 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
556 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
557 I40E_PTT_UNUSED_ENTRY(69),
558 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
559 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
560 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
562 /* IPv4 --> GRE/NAT --> MAC/VLAN */
563 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
565 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
566 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
567 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
568 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
569 I40E_PTT_UNUSED_ENTRY(77),
570 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
571 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
572 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
574 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
575 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
576 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
577 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
578 I40E_PTT_UNUSED_ENTRY(84),
579 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
580 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
581 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
583 /* Non Tunneled IPv6 */
584 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
585 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
586 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
587 I40E_PTT_UNUSED_ENTRY(91),
588 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
589 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
590 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
593 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
594 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
595 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
596 I40E_PTT_UNUSED_ENTRY(98),
597 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
598 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
599 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
602 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
603 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
604 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
605 I40E_PTT_UNUSED_ENTRY(105),
606 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
607 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
608 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
610 /* IPv6 --> GRE/NAT */
611 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
613 /* IPv6 --> GRE/NAT -> IPv4 */
614 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
615 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
616 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
617 I40E_PTT_UNUSED_ENTRY(113),
618 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
619 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
620 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
622 /* IPv6 --> GRE/NAT -> IPv6 */
623 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
624 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
625 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
626 I40E_PTT_UNUSED_ENTRY(120),
627 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
628 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
629 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
631 /* IPv6 --> GRE/NAT -> MAC */
632 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
634 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
635 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
636 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
637 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
638 I40E_PTT_UNUSED_ENTRY(128),
639 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
640 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
641 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
643 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
644 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
645 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
646 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
647 I40E_PTT_UNUSED_ENTRY(135),
648 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
649 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
650 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
652 /* IPv6 --> GRE/NAT -> MAC/VLAN */
653 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
655 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
656 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
657 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
658 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
659 I40E_PTT_UNUSED_ENTRY(143),
660 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
661 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
662 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
664 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
665 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
666 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
667 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
668 I40E_PTT_UNUSED_ENTRY(150),
669 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
670 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
671 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
674 I40E_PTT_UNUSED_ENTRY(154),
675 I40E_PTT_UNUSED_ENTRY(155),
676 I40E_PTT_UNUSED_ENTRY(156),
677 I40E_PTT_UNUSED_ENTRY(157),
678 I40E_PTT_UNUSED_ENTRY(158),
679 I40E_PTT_UNUSED_ENTRY(159),
681 I40E_PTT_UNUSED_ENTRY(160),
682 I40E_PTT_UNUSED_ENTRY(161),
683 I40E_PTT_UNUSED_ENTRY(162),
684 I40E_PTT_UNUSED_ENTRY(163),
685 I40E_PTT_UNUSED_ENTRY(164),
686 I40E_PTT_UNUSED_ENTRY(165),
687 I40E_PTT_UNUSED_ENTRY(166),
688 I40E_PTT_UNUSED_ENTRY(167),
689 I40E_PTT_UNUSED_ENTRY(168),
690 I40E_PTT_UNUSED_ENTRY(169),
692 I40E_PTT_UNUSED_ENTRY(170),
693 I40E_PTT_UNUSED_ENTRY(171),
694 I40E_PTT_UNUSED_ENTRY(172),
695 I40E_PTT_UNUSED_ENTRY(173),
696 I40E_PTT_UNUSED_ENTRY(174),
697 I40E_PTT_UNUSED_ENTRY(175),
698 I40E_PTT_UNUSED_ENTRY(176),
699 I40E_PTT_UNUSED_ENTRY(177),
700 I40E_PTT_UNUSED_ENTRY(178),
701 I40E_PTT_UNUSED_ENTRY(179),
703 I40E_PTT_UNUSED_ENTRY(180),
704 I40E_PTT_UNUSED_ENTRY(181),
705 I40E_PTT_UNUSED_ENTRY(182),
706 I40E_PTT_UNUSED_ENTRY(183),
707 I40E_PTT_UNUSED_ENTRY(184),
708 I40E_PTT_UNUSED_ENTRY(185),
709 I40E_PTT_UNUSED_ENTRY(186),
710 I40E_PTT_UNUSED_ENTRY(187),
711 I40E_PTT_UNUSED_ENTRY(188),
712 I40E_PTT_UNUSED_ENTRY(189),
714 I40E_PTT_UNUSED_ENTRY(190),
715 I40E_PTT_UNUSED_ENTRY(191),
716 I40E_PTT_UNUSED_ENTRY(192),
717 I40E_PTT_UNUSED_ENTRY(193),
718 I40E_PTT_UNUSED_ENTRY(194),
719 I40E_PTT_UNUSED_ENTRY(195),
720 I40E_PTT_UNUSED_ENTRY(196),
721 I40E_PTT_UNUSED_ENTRY(197),
722 I40E_PTT_UNUSED_ENTRY(198),
723 I40E_PTT_UNUSED_ENTRY(199),
725 I40E_PTT_UNUSED_ENTRY(200),
726 I40E_PTT_UNUSED_ENTRY(201),
727 I40E_PTT_UNUSED_ENTRY(202),
728 I40E_PTT_UNUSED_ENTRY(203),
729 I40E_PTT_UNUSED_ENTRY(204),
730 I40E_PTT_UNUSED_ENTRY(205),
731 I40E_PTT_UNUSED_ENTRY(206),
732 I40E_PTT_UNUSED_ENTRY(207),
733 I40E_PTT_UNUSED_ENTRY(208),
734 I40E_PTT_UNUSED_ENTRY(209),
736 I40E_PTT_UNUSED_ENTRY(210),
737 I40E_PTT_UNUSED_ENTRY(211),
738 I40E_PTT_UNUSED_ENTRY(212),
739 I40E_PTT_UNUSED_ENTRY(213),
740 I40E_PTT_UNUSED_ENTRY(214),
741 I40E_PTT_UNUSED_ENTRY(215),
742 I40E_PTT_UNUSED_ENTRY(216),
743 I40E_PTT_UNUSED_ENTRY(217),
744 I40E_PTT_UNUSED_ENTRY(218),
745 I40E_PTT_UNUSED_ENTRY(219),
747 I40E_PTT_UNUSED_ENTRY(220),
748 I40E_PTT_UNUSED_ENTRY(221),
749 I40E_PTT_UNUSED_ENTRY(222),
750 I40E_PTT_UNUSED_ENTRY(223),
751 I40E_PTT_UNUSED_ENTRY(224),
752 I40E_PTT_UNUSED_ENTRY(225),
753 I40E_PTT_UNUSED_ENTRY(226),
754 I40E_PTT_UNUSED_ENTRY(227),
755 I40E_PTT_UNUSED_ENTRY(228),
756 I40E_PTT_UNUSED_ENTRY(229),
758 I40E_PTT_UNUSED_ENTRY(230),
759 I40E_PTT_UNUSED_ENTRY(231),
760 I40E_PTT_UNUSED_ENTRY(232),
761 I40E_PTT_UNUSED_ENTRY(233),
762 I40E_PTT_UNUSED_ENTRY(234),
763 I40E_PTT_UNUSED_ENTRY(235),
764 I40E_PTT_UNUSED_ENTRY(236),
765 I40E_PTT_UNUSED_ENTRY(237),
766 I40E_PTT_UNUSED_ENTRY(238),
767 I40E_PTT_UNUSED_ENTRY(239),
769 I40E_PTT_UNUSED_ENTRY(240),
770 I40E_PTT_UNUSED_ENTRY(241),
771 I40E_PTT_UNUSED_ENTRY(242),
772 I40E_PTT_UNUSED_ENTRY(243),
773 I40E_PTT_UNUSED_ENTRY(244),
774 I40E_PTT_UNUSED_ENTRY(245),
775 I40E_PTT_UNUSED_ENTRY(246),
776 I40E_PTT_UNUSED_ENTRY(247),
777 I40E_PTT_UNUSED_ENTRY(248),
778 I40E_PTT_UNUSED_ENTRY(249),
780 I40E_PTT_UNUSED_ENTRY(250),
781 I40E_PTT_UNUSED_ENTRY(251),
782 I40E_PTT_UNUSED_ENTRY(252),
783 I40E_PTT_UNUSED_ENTRY(253),
784 I40E_PTT_UNUSED_ENTRY(254),
785 I40E_PTT_UNUSED_ENTRY(255)
790 * i40e_validate_mac_addr - Validate unicast MAC address
791 * @mac_addr: pointer to MAC address
793 * Tests a MAC address to ensure it is a valid Individual Address
795 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
797 enum i40e_status_code status = I40E_SUCCESS;
799 DEBUGFUNC("i40e_validate_mac_addr");
801 /* Broadcast addresses ARE multicast addresses
802 * Make sure it is not a multicast address
803 * Reject the zero address
805 if (I40E_IS_MULTICAST(mac_addr) ||
806 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
807 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
808 status = I40E_ERR_INVALID_MAC_ADDR;
815 * i40e_init_shared_code - Initialize the shared code
816 * @hw: pointer to hardware structure
818 * This assigns the MAC type and PHY code and inits the NVM.
819 * Does not touch the hardware. This function must be called prior to any
820 * other function in the shared code. The i40e_hw structure should be
821 * memset to 0 prior to calling this function. The following fields in
822 * hw structure should be filled in prior to calling this function:
823 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
824 * subsystem_vendor_id, and revision_id
826 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
828 enum i40e_status_code status = I40E_SUCCESS;
829 u32 port, ari, func_rid;
831 DEBUGFUNC("i40e_init_shared_code");
833 i40e_set_mac_type(hw);
835 switch (hw->mac.type) {
839 return I40E_ERR_DEVICE_NOT_SUPPORTED;
842 hw->phy.get_link_info = true;
844 /* Determine port number and PF number*/
845 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
846 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
848 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
849 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
850 func_rid = rd32(hw, I40E_PF_FUNC_RID);
852 hw->pf_id = (u8)(func_rid & 0xff);
854 hw->pf_id = (u8)(func_rid & 0x7);
856 status = i40e_init_nvm(hw);
861 * i40e_aq_mac_address_read - Retrieve the MAC addresses
862 * @hw: pointer to the hw struct
863 * @flags: a return indicator of what addresses were added to the addr store
864 * @addrs: the requestor's mac addr store
865 * @cmd_details: pointer to command details structure or NULL
867 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
869 struct i40e_aqc_mac_address_read_data *addrs,
870 struct i40e_asq_cmd_details *cmd_details)
872 struct i40e_aq_desc desc;
873 struct i40e_aqc_mac_address_read *cmd_data =
874 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
875 enum i40e_status_code status;
877 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
878 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
880 status = i40e_asq_send_command(hw, &desc, addrs,
881 sizeof(*addrs), cmd_details);
882 *flags = LE16_TO_CPU(cmd_data->command_flags);
888 * i40e_aq_mac_address_write - Change the MAC addresses
889 * @hw: pointer to the hw struct
890 * @flags: indicates which MAC to be written
891 * @mac_addr: address to write
892 * @cmd_details: pointer to command details structure or NULL
894 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
895 u16 flags, u8 *mac_addr,
896 struct i40e_asq_cmd_details *cmd_details)
898 struct i40e_aq_desc desc;
899 struct i40e_aqc_mac_address_write *cmd_data =
900 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
901 enum i40e_status_code status;
903 i40e_fill_default_direct_cmd_desc(&desc,
904 i40e_aqc_opc_mac_address_write);
905 cmd_data->command_flags = CPU_TO_LE16(flags);
906 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
907 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
908 ((u32)mac_addr[3] << 16) |
909 ((u32)mac_addr[4] << 8) |
912 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
918 * i40e_get_mac_addr - get MAC address
919 * @hw: pointer to the HW structure
920 * @mac_addr: pointer to MAC address
922 * Reads the adapter's MAC address from register
924 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
926 struct i40e_aqc_mac_address_read_data addrs;
927 enum i40e_status_code status;
930 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
932 if (flags & I40E_AQC_LAN_ADDR_VALID)
933 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
939 * i40e_get_port_mac_addr - get Port MAC address
940 * @hw: pointer to the HW structure
941 * @mac_addr: pointer to Port MAC address
943 * Reads the adapter's Port MAC address
945 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
947 struct i40e_aqc_mac_address_read_data addrs;
948 enum i40e_status_code status;
951 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
955 if (flags & I40E_AQC_PORT_ADDR_VALID)
956 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
958 status = I40E_ERR_INVALID_MAC_ADDR;
964 * i40e_pre_tx_queue_cfg - pre tx queue configure
965 * @hw: pointer to the HW structure
966 * @queue: target pf queue index
967 * @enable: state change request
969 * Handles hw requirement to indicate intention to enable
970 * or disable target queue.
972 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
974 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
978 if (abs_queue_idx >= 128) {
979 reg_block = abs_queue_idx / 128;
980 abs_queue_idx %= 128;
983 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
984 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
985 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
988 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
990 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
992 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
996 * i40e_read_pba_string - Reads part number string from EEPROM
997 * @hw: pointer to hardware structure
998 * @pba_num: stores the part number string from the EEPROM
999 * @pba_num_size: part number string buffer length
1001 * Reads the part number string from the EEPROM.
1003 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1006 enum i40e_status_code status = I40E_SUCCESS;
1012 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1013 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1014 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1018 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1019 if (status != I40E_SUCCESS) {
1020 DEBUGOUT("Failed to read PBA Block pointer.\n");
1024 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1025 if (status != I40E_SUCCESS) {
1026 DEBUGOUT("Failed to read PBA Block size.\n");
1030 /* Subtract one to get PBA word count (PBA Size word is included in
1034 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1035 DEBUGOUT("Buffer to small for PBA data.\n");
1036 return I40E_ERR_PARAM;
1039 for (i = 0; i < pba_size; i++) {
1040 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1041 if (status != I40E_SUCCESS) {
1042 DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1046 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1047 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1049 pba_num[(pba_size * 2)] = '\0';
1055 * i40e_get_media_type - Gets media type
1056 * @hw: pointer to the hardware structure
1058 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1060 enum i40e_media_type media;
1062 switch (hw->phy.link_info.phy_type) {
1063 case I40E_PHY_TYPE_10GBASE_SR:
1064 case I40E_PHY_TYPE_10GBASE_LR:
1065 case I40E_PHY_TYPE_1000BASE_SX:
1066 case I40E_PHY_TYPE_1000BASE_LX:
1067 case I40E_PHY_TYPE_40GBASE_SR4:
1068 case I40E_PHY_TYPE_40GBASE_LR4:
1069 media = I40E_MEDIA_TYPE_FIBER;
1071 case I40E_PHY_TYPE_100BASE_TX:
1072 case I40E_PHY_TYPE_1000BASE_T:
1073 case I40E_PHY_TYPE_10GBASE_T:
1074 media = I40E_MEDIA_TYPE_BASET;
1076 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1077 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1078 case I40E_PHY_TYPE_10GBASE_CR1:
1079 case I40E_PHY_TYPE_40GBASE_CR4:
1080 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1081 case I40E_PHY_TYPE_40GBASE_AOC:
1082 case I40E_PHY_TYPE_10GBASE_AOC:
1083 media = I40E_MEDIA_TYPE_DA;
1085 case I40E_PHY_TYPE_1000BASE_KX:
1086 case I40E_PHY_TYPE_10GBASE_KX4:
1087 case I40E_PHY_TYPE_10GBASE_KR:
1088 case I40E_PHY_TYPE_40GBASE_KR4:
1089 case I40E_PHY_TYPE_20GBASE_KR2:
1090 media = I40E_MEDIA_TYPE_BACKPLANE;
1092 case I40E_PHY_TYPE_SGMII:
1093 case I40E_PHY_TYPE_XAUI:
1094 case I40E_PHY_TYPE_XFI:
1095 case I40E_PHY_TYPE_XLAUI:
1096 case I40E_PHY_TYPE_XLPPI:
1098 media = I40E_MEDIA_TYPE_UNKNOWN;
1105 #define I40E_PF_RESET_WAIT_COUNT 200
1107 * i40e_pf_reset - Reset the PF
1108 * @hw: pointer to the hardware structure
1110 * Assuming someone else has triggered a global reset,
1111 * assure the global reset is complete and then reset the PF
1113 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1120 /* Poll for Global Reset steady state in case of recent GRST.
1121 * The grst delay value is in 100ms units, and we'll wait a
1122 * couple counts longer to be sure we don't just miss the end.
1124 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1125 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1126 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1127 for (cnt = 0; cnt < grst_del + 2; cnt++) {
1128 reg = rd32(hw, I40E_GLGEN_RSTAT);
1129 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1131 i40e_msec_delay(100);
1133 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1134 DEBUGOUT("Global reset polling failed to complete.\n");
1135 return I40E_ERR_RESET_FAILED;
1138 /* Now Wait for the FW to be ready */
1139 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1140 reg = rd32(hw, I40E_GLNVM_ULD);
1141 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1142 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1143 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1144 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1145 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1148 i40e_msec_delay(10);
1150 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1151 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1152 DEBUGOUT("wait for FW Reset complete timedout\n");
1153 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1154 return I40E_ERR_RESET_FAILED;
1157 /* If there was a Global Reset in progress when we got here,
1158 * we don't need to do the PF Reset
1161 reg = rd32(hw, I40E_PFGEN_CTRL);
1162 wr32(hw, I40E_PFGEN_CTRL,
1163 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1164 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1165 reg = rd32(hw, I40E_PFGEN_CTRL);
1166 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1170 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1171 DEBUGOUT("PF reset polling failed to complete.\n");
1172 return I40E_ERR_RESET_FAILED;
1176 i40e_clear_pxe_mode(hw);
1179 return I40E_SUCCESS;
1183 * i40e_clear_hw - clear out any left over hw state
1184 * @hw: pointer to the hw struct
1186 * Clear queues and interrupts, typically called at init time,
1187 * but after the capabilities have been found so we know how many
1188 * queues and msix vectors have been allocated.
1190 void i40e_clear_hw(struct i40e_hw *hw)
1192 u32 num_queues, base_queue;
1200 /* get number of interrupts, queues, and vfs */
1201 val = rd32(hw, I40E_GLPCI_CNF2);
1202 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1203 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1204 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1205 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1207 val = rd32(hw, I40E_PFLAN_QALLOC);
1208 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1209 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1210 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1211 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1212 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1213 num_queues = (j - base_queue) + 1;
1217 val = rd32(hw, I40E_PF_VT_PFALLOC);
1218 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1219 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1220 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1221 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1222 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1223 num_vfs = (j - i) + 1;
1227 /* stop all the interrupts */
1228 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1229 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1230 for (i = 0; i < num_pf_int - 2; i++)
1231 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1233 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1234 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1235 wr32(hw, I40E_PFINT_LNKLST0, val);
1236 for (i = 0; i < num_pf_int - 2; i++)
1237 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1238 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1239 for (i = 0; i < num_vfs; i++)
1240 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1241 for (i = 0; i < num_vf_int - 2; i++)
1242 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1244 /* warn the HW of the coming Tx disables */
1245 for (i = 0; i < num_queues; i++) {
1246 u32 abs_queue_idx = base_queue + i;
1249 if (abs_queue_idx >= 128) {
1250 reg_block = abs_queue_idx / 128;
1251 abs_queue_idx %= 128;
1254 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1255 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1256 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1257 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1259 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1261 i40e_usec_delay(400);
1263 /* stop all the queues */
1264 for (i = 0; i < num_queues; i++) {
1265 wr32(hw, I40E_QINT_TQCTL(i), 0);
1266 wr32(hw, I40E_QTX_ENA(i), 0);
1267 wr32(hw, I40E_QINT_RQCTL(i), 0);
1268 wr32(hw, I40E_QRX_ENA(i), 0);
1271 /* short wait for all queue disables to settle */
1272 i40e_usec_delay(50);
1276 * i40e_clear_pxe_mode - clear pxe operations mode
1277 * @hw: pointer to the hw struct
1279 * Make sure all PXE mode settings are cleared, including things
1280 * like descriptor fetch/write-back mode.
1282 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1284 if (i40e_check_asq_alive(hw))
1285 i40e_aq_clear_pxe_mode(hw, NULL);
1289 * i40e_led_is_mine - helper to find matching led
1290 * @hw: pointer to the hw struct
1291 * @idx: index into GPIO registers
1293 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1295 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1300 if (!hw->func_caps.led[idx])
1303 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1304 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1305 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1307 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1308 * if it is not our port then ignore
1310 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1317 #define I40E_COMBINED_ACTIVITY 0xA
1318 #define I40E_FILTER_ACTIVITY 0xE
1319 #define I40E_LINK_ACTIVITY 0xC
1320 #define I40E_MAC_ACTIVITY 0xD
1321 #define I40E_LED0 22
1324 * i40e_led_get - return current on/off mode
1325 * @hw: pointer to the hw struct
1327 * The value returned is the 'mode' field as defined in the
1328 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1329 * values are variations of possible behaviors relating to
1330 * blink, link, and wire.
1332 u32 i40e_led_get(struct i40e_hw *hw)
1334 u32 current_mode = 0;
1338 /* as per the documentation GPIO 22-29 are the LED
1339 * GPIO pins named LED0..LED7
1341 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1342 u32 gpio_val = i40e_led_is_mine(hw, i);
1347 /* ignore gpio LED src mode entries related to the activity LEDs */
1348 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1349 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1350 switch (current_mode) {
1351 case I40E_COMBINED_ACTIVITY:
1352 case I40E_FILTER_ACTIVITY:
1353 case I40E_MAC_ACTIVITY:
1359 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1360 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1368 * i40e_led_set - set new on/off mode
1369 * @hw: pointer to the hw struct
1370 * @mode: 0=off, 0xf=on (else see manual for mode details)
1371 * @blink: true if the LED should blink when on, false if steady
1373 * if this function is used to turn on the blink it should
1374 * be used to disable the blink when restoring the original state.
1376 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1378 u32 current_mode = 0;
1381 if (mode & 0xfffffff0)
1382 DEBUGOUT1("invalid mode passed in %X\n", mode);
1384 /* as per the documentation GPIO 22-29 are the LED
1385 * GPIO pins named LED0..LED7
1387 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1388 u32 gpio_val = i40e_led_is_mine(hw, i);
1393 /* ignore gpio LED src mode entries related to the activity LEDs */
1394 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1395 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1396 switch (current_mode) {
1397 case I40E_COMBINED_ACTIVITY:
1398 case I40E_FILTER_ACTIVITY:
1399 case I40E_MAC_ACTIVITY:
1405 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1406 /* this & is a bit of paranoia, but serves as a range check */
1407 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1408 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1410 if (mode == I40E_LINK_ACTIVITY)
1414 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1416 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1418 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1423 /* Admin command wrappers */
1426 * i40e_aq_get_phy_capabilities
1427 * @hw: pointer to the hw struct
1428 * @abilities: structure for PHY capabilities to be filled
1429 * @qualified_modules: report Qualified Modules
1430 * @report_init: report init capabilities (active are default)
1431 * @cmd_details: pointer to command details structure or NULL
1433 * Returns the various PHY abilities supported on the Port.
1435 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1436 bool qualified_modules, bool report_init,
1437 struct i40e_aq_get_phy_abilities_resp *abilities,
1438 struct i40e_asq_cmd_details *cmd_details)
1440 struct i40e_aq_desc desc;
1441 enum i40e_status_code status;
1442 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1445 return I40E_ERR_PARAM;
1447 i40e_fill_default_direct_cmd_desc(&desc,
1448 i40e_aqc_opc_get_phy_abilities);
1450 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1451 if (abilities_size > I40E_AQ_LARGE_BUF)
1452 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1454 if (qualified_modules)
1455 desc.params.external.param0 |=
1456 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1459 desc.params.external.param0 |=
1460 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1462 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1465 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1466 status = I40E_ERR_UNKNOWN_PHY;
1469 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1475 * i40e_aq_set_phy_config
1476 * @hw: pointer to the hw struct
1477 * @config: structure with PHY configuration to be set
1478 * @cmd_details: pointer to command details structure or NULL
1480 * Set the various PHY configuration parameters
1481 * supported on the Port.One or more of the Set PHY config parameters may be
1482 * ignored in an MFP mode as the PF may not have the privilege to set some
1483 * of the PHY Config parameters. This status will be indicated by the
1486 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1487 struct i40e_aq_set_phy_config *config,
1488 struct i40e_asq_cmd_details *cmd_details)
1490 struct i40e_aq_desc desc;
1491 struct i40e_aq_set_phy_config *cmd =
1492 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1493 enum i40e_status_code status;
1496 return I40E_ERR_PARAM;
1498 i40e_fill_default_direct_cmd_desc(&desc,
1499 i40e_aqc_opc_set_phy_config);
1503 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1510 * @hw: pointer to the hw struct
1512 * Set the requested flow control mode using set_phy_config.
1514 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1515 bool atomic_restart)
1517 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1518 struct i40e_aq_get_phy_abilities_resp abilities;
1519 struct i40e_aq_set_phy_config config;
1520 enum i40e_status_code status;
1521 u8 pause_mask = 0x0;
1527 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1528 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1530 case I40E_FC_RX_PAUSE:
1531 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1533 case I40E_FC_TX_PAUSE:
1534 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1540 /* Get the current phy config */
1541 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1544 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1548 memset(&config, 0, sizeof(config));
1549 /* clear the old pause settings */
1550 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1551 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1552 /* set the new abilities */
1553 config.abilities |= pause_mask;
1554 /* If the abilities have changed, then set the new config */
1555 if (config.abilities != abilities.abilities) {
1556 /* Auto restart link so settings take effect */
1558 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1559 /* Copy over all the old settings */
1560 config.phy_type = abilities.phy_type;
1561 config.link_speed = abilities.link_speed;
1562 config.eee_capability = abilities.eee_capability;
1563 config.eeer = abilities.eeer_val;
1564 config.low_power_ctrl = abilities.d3_lpan;
1565 status = i40e_aq_set_phy_config(hw, &config, NULL);
1568 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1570 /* Update the link info */
1571 status = i40e_update_link_info(hw);
1573 /* Wait a little bit (on 40G cards it sometimes takes a really
1574 * long time for link to come back from the atomic reset)
1577 i40e_msec_delay(1000);
1578 status = i40e_update_link_info(hw);
1581 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1587 * i40e_aq_set_mac_config
1588 * @hw: pointer to the hw struct
1589 * @max_frame_size: Maximum Frame Size to be supported by the port
1590 * @crc_en: Tell HW to append a CRC to outgoing frames
1591 * @pacing: Pacing configurations
1592 * @cmd_details: pointer to command details structure or NULL
1594 * Configure MAC settings for frame size, jumbo frame support and the
1595 * addition of a CRC by the hardware.
1597 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1599 bool crc_en, u16 pacing,
1600 struct i40e_asq_cmd_details *cmd_details)
1602 struct i40e_aq_desc desc;
1603 struct i40e_aq_set_mac_config *cmd =
1604 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1605 enum i40e_status_code status;
1607 if (max_frame_size == 0)
1608 return I40E_ERR_PARAM;
1610 i40e_fill_default_direct_cmd_desc(&desc,
1611 i40e_aqc_opc_set_mac_config);
1613 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1614 cmd->params = ((u8)pacing & 0x0F) << 3;
1616 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1618 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1624 * i40e_aq_clear_pxe_mode
1625 * @hw: pointer to the hw struct
1626 * @cmd_details: pointer to command details structure or NULL
1628 * Tell the firmware that the driver is taking over from PXE
1630 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1631 struct i40e_asq_cmd_details *cmd_details)
1633 enum i40e_status_code status;
1634 struct i40e_aq_desc desc;
1635 struct i40e_aqc_clear_pxe *cmd =
1636 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1638 i40e_fill_default_direct_cmd_desc(&desc,
1639 i40e_aqc_opc_clear_pxe_mode);
1643 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1645 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1651 * i40e_aq_set_link_restart_an
1652 * @hw: pointer to the hw struct
1653 * @enable_link: if true: enable link, if false: disable link
1654 * @cmd_details: pointer to command details structure or NULL
1656 * Sets up the link and restarts the Auto-Negotiation over the link.
1658 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1659 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1661 struct i40e_aq_desc desc;
1662 struct i40e_aqc_set_link_restart_an *cmd =
1663 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1664 enum i40e_status_code status;
1666 i40e_fill_default_direct_cmd_desc(&desc,
1667 i40e_aqc_opc_set_link_restart_an);
1669 cmd->command = I40E_AQ_PHY_RESTART_AN;
1671 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1673 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1675 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1681 * i40e_aq_get_link_info
1682 * @hw: pointer to the hw struct
1683 * @enable_lse: enable/disable LinkStatusEvent reporting
1684 * @link: pointer to link status structure - optional
1685 * @cmd_details: pointer to command details structure or NULL
1687 * Returns the link status of the adapter.
1689 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1690 bool enable_lse, struct i40e_link_status *link,
1691 struct i40e_asq_cmd_details *cmd_details)
1693 struct i40e_aq_desc desc;
1694 struct i40e_aqc_get_link_status *resp =
1695 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1696 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1697 enum i40e_status_code status;
1698 bool tx_pause, rx_pause;
1701 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1704 command_flags = I40E_AQ_LSE_ENABLE;
1706 command_flags = I40E_AQ_LSE_DISABLE;
1707 resp->command_flags = CPU_TO_LE16(command_flags);
1709 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1711 if (status != I40E_SUCCESS)
1712 goto aq_get_link_info_exit;
1714 /* save off old link status information */
1715 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1716 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1718 /* update link status */
1719 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1720 hw->phy.media_type = i40e_get_media_type(hw);
1721 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1722 hw_link_info->link_info = resp->link_info;
1723 hw_link_info->an_info = resp->an_info;
1724 hw_link_info->ext_info = resp->ext_info;
1725 hw_link_info->loopback = resp->loopback;
1726 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1727 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1729 /* update fc info */
1730 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1731 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1732 if (tx_pause & rx_pause)
1733 hw->fc.current_mode = I40E_FC_FULL;
1735 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1737 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1739 hw->fc.current_mode = I40E_FC_NONE;
1741 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1742 hw_link_info->crc_enable = true;
1744 hw_link_info->crc_enable = false;
1746 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1747 hw_link_info->lse_enable = true;
1749 hw_link_info->lse_enable = false;
1751 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1752 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1753 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1755 /* save link status information */
1757 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1758 I40E_NONDMA_TO_NONDMA);
1760 /* flag cleared so helper functions don't call AQ again */
1761 hw->phy.get_link_info = false;
1763 aq_get_link_info_exit:
1768 * i40e_aq_set_phy_int_mask
1769 * @hw: pointer to the hw struct
1770 * @mask: interrupt mask to be set
1771 * @cmd_details: pointer to command details structure or NULL
1773 * Set link interrupt mask.
1775 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1777 struct i40e_asq_cmd_details *cmd_details)
1779 struct i40e_aq_desc desc;
1780 struct i40e_aqc_set_phy_int_mask *cmd =
1781 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1782 enum i40e_status_code status;
1784 i40e_fill_default_direct_cmd_desc(&desc,
1785 i40e_aqc_opc_set_phy_int_mask);
1787 cmd->event_mask = CPU_TO_LE16(mask);
1789 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1795 * i40e_aq_get_local_advt_reg
1796 * @hw: pointer to the hw struct
1797 * @advt_reg: local AN advertisement register value
1798 * @cmd_details: pointer to command details structure or NULL
1800 * Get the Local AN advertisement register value.
1802 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
1804 struct i40e_asq_cmd_details *cmd_details)
1806 struct i40e_aq_desc desc;
1807 struct i40e_aqc_an_advt_reg *resp =
1808 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1809 enum i40e_status_code status;
1811 i40e_fill_default_direct_cmd_desc(&desc,
1812 i40e_aqc_opc_get_local_advt_reg);
1814 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1816 if (status != I40E_SUCCESS)
1817 goto aq_get_local_advt_reg_exit;
1819 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1820 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1822 aq_get_local_advt_reg_exit:
1827 * i40e_aq_set_local_advt_reg
1828 * @hw: pointer to the hw struct
1829 * @advt_reg: local AN advertisement register value
1830 * @cmd_details: pointer to command details structure or NULL
1832 * Get the Local AN advertisement register value.
1834 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
1836 struct i40e_asq_cmd_details *cmd_details)
1838 struct i40e_aq_desc desc;
1839 struct i40e_aqc_an_advt_reg *cmd =
1840 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1841 enum i40e_status_code status;
1843 i40e_fill_default_direct_cmd_desc(&desc,
1844 i40e_aqc_opc_get_local_advt_reg);
1846 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
1847 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
1849 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1855 * i40e_aq_get_partner_advt
1856 * @hw: pointer to the hw struct
1857 * @advt_reg: AN partner advertisement register value
1858 * @cmd_details: pointer to command details structure or NULL
1860 * Get the link partner AN advertisement register value.
1862 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
1864 struct i40e_asq_cmd_details *cmd_details)
1866 struct i40e_aq_desc desc;
1867 struct i40e_aqc_an_advt_reg *resp =
1868 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1869 enum i40e_status_code status;
1871 i40e_fill_default_direct_cmd_desc(&desc,
1872 i40e_aqc_opc_get_partner_advt);
1874 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1876 if (status != I40E_SUCCESS)
1877 goto aq_get_partner_advt_exit;
1879 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1880 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1882 aq_get_partner_advt_exit:
1887 * i40e_aq_set_lb_modes
1888 * @hw: pointer to the hw struct
1889 * @lb_modes: loopback mode to be set
1890 * @cmd_details: pointer to command details structure or NULL
1892 * Sets loopback modes.
1894 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
1896 struct i40e_asq_cmd_details *cmd_details)
1898 struct i40e_aq_desc desc;
1899 struct i40e_aqc_set_lb_mode *cmd =
1900 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
1901 enum i40e_status_code status;
1903 i40e_fill_default_direct_cmd_desc(&desc,
1904 i40e_aqc_opc_set_lb_modes);
1906 cmd->lb_mode = CPU_TO_LE16(lb_modes);
1908 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1914 * i40e_aq_set_phy_debug
1915 * @hw: pointer to the hw struct
1916 * @cmd_flags: debug command flags
1917 * @cmd_details: pointer to command details structure or NULL
1919 * Reset the external PHY.
1921 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1922 struct i40e_asq_cmd_details *cmd_details)
1924 struct i40e_aq_desc desc;
1925 struct i40e_aqc_set_phy_debug *cmd =
1926 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1927 enum i40e_status_code status;
1929 i40e_fill_default_direct_cmd_desc(&desc,
1930 i40e_aqc_opc_set_phy_debug);
1932 cmd->command_flags = cmd_flags;
1934 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1941 * @hw: pointer to the hw struct
1942 * @vsi_ctx: pointer to a vsi context struct
1943 * @cmd_details: pointer to command details structure or NULL
1945 * Add a VSI context to the hardware.
1947 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
1948 struct i40e_vsi_context *vsi_ctx,
1949 struct i40e_asq_cmd_details *cmd_details)
1951 struct i40e_aq_desc desc;
1952 struct i40e_aqc_add_get_update_vsi *cmd =
1953 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1954 struct i40e_aqc_add_get_update_vsi_completion *resp =
1955 (struct i40e_aqc_add_get_update_vsi_completion *)
1957 enum i40e_status_code status;
1959 i40e_fill_default_direct_cmd_desc(&desc,
1960 i40e_aqc_opc_add_vsi);
1962 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
1963 cmd->connection_type = vsi_ctx->connection_type;
1964 cmd->vf_id = vsi_ctx->vf_num;
1965 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
1967 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1969 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1970 sizeof(vsi_ctx->info), cmd_details);
1972 if (status != I40E_SUCCESS)
1973 goto aq_add_vsi_exit;
1975 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
1976 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
1977 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
1978 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
1985 * i40e_aq_set_default_vsi
1986 * @hw: pointer to the hw struct
1988 * @cmd_details: pointer to command details structure or NULL
1990 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
1992 struct i40e_asq_cmd_details *cmd_details)
1994 struct i40e_aq_desc desc;
1995 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1996 (struct i40e_aqc_set_vsi_promiscuous_modes *)
1998 enum i40e_status_code status;
2000 i40e_fill_default_direct_cmd_desc(&desc,
2001 i40e_aqc_opc_set_vsi_promiscuous_modes);
2003 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2004 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2005 cmd->seid = CPU_TO_LE16(seid);
2007 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2013 * i40e_aq_set_vsi_unicast_promiscuous
2014 * @hw: pointer to the hw struct
2016 * @set: set unicast promiscuous enable/disable
2017 * @cmd_details: pointer to command details structure or NULL
2019 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2021 struct i40e_asq_cmd_details *cmd_details)
2023 struct i40e_aq_desc desc;
2024 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2025 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2026 enum i40e_status_code status;
2029 i40e_fill_default_direct_cmd_desc(&desc,
2030 i40e_aqc_opc_set_vsi_promiscuous_modes);
2033 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2035 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2037 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2039 cmd->seid = CPU_TO_LE16(seid);
2040 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2046 * i40e_aq_set_vsi_multicast_promiscuous
2047 * @hw: pointer to the hw struct
2049 * @set: set multicast promiscuous enable/disable
2050 * @cmd_details: pointer to command details structure or NULL
2052 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2053 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2055 struct i40e_aq_desc desc;
2056 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2057 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2058 enum i40e_status_code status;
2061 i40e_fill_default_direct_cmd_desc(&desc,
2062 i40e_aqc_opc_set_vsi_promiscuous_modes);
2065 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2067 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2069 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2071 cmd->seid = CPU_TO_LE16(seid);
2072 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2078 * i40e_aq_set_vsi_mc_promisc_on_vlan
2079 * @hw: pointer to the hw struct
2081 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2082 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2083 * @cmd_details: pointer to command details structure or NULL
2085 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2086 u16 seid, bool enable, u16 vid,
2087 struct i40e_asq_cmd_details *cmd_details)
2089 struct i40e_aq_desc desc;
2090 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2091 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2092 enum i40e_status_code status;
2095 i40e_fill_default_direct_cmd_desc(&desc,
2096 i40e_aqc_opc_set_vsi_promiscuous_modes);
2099 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2101 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2102 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2103 cmd->seid = CPU_TO_LE16(seid);
2104 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2106 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2112 * i40e_aq_set_vsi_uc_promisc_on_vlan
2113 * @hw: pointer to the hw struct
2115 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2116 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2117 * @cmd_details: pointer to command details structure or NULL
2119 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2120 u16 seid, bool enable, u16 vid,
2121 struct i40e_asq_cmd_details *cmd_details)
2123 struct i40e_aq_desc desc;
2124 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2125 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2126 enum i40e_status_code status;
2129 i40e_fill_default_direct_cmd_desc(&desc,
2130 i40e_aqc_opc_set_vsi_promiscuous_modes);
2133 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2135 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2136 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2137 cmd->seid = CPU_TO_LE16(seid);
2138 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2140 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2146 * i40e_aq_set_vsi_broadcast
2147 * @hw: pointer to the hw struct
2149 * @set_filter: true to set filter, false to clear filter
2150 * @cmd_details: pointer to command details structure or NULL
2152 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2154 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2155 u16 seid, bool set_filter,
2156 struct i40e_asq_cmd_details *cmd_details)
2158 struct i40e_aq_desc desc;
2159 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2160 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2161 enum i40e_status_code status;
2163 i40e_fill_default_direct_cmd_desc(&desc,
2164 i40e_aqc_opc_set_vsi_promiscuous_modes);
2167 cmd->promiscuous_flags
2168 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2170 cmd->promiscuous_flags
2171 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2173 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2174 cmd->seid = CPU_TO_LE16(seid);
2175 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2181 * i40e_get_vsi_params - get VSI configuration info
2182 * @hw: pointer to the hw struct
2183 * @vsi_ctx: pointer to a vsi context struct
2184 * @cmd_details: pointer to command details structure or NULL
2186 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2187 struct i40e_vsi_context *vsi_ctx,
2188 struct i40e_asq_cmd_details *cmd_details)
2190 struct i40e_aq_desc desc;
2191 struct i40e_aqc_add_get_update_vsi *cmd =
2192 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2193 struct i40e_aqc_add_get_update_vsi_completion *resp =
2194 (struct i40e_aqc_add_get_update_vsi_completion *)
2196 enum i40e_status_code status;
2198 UNREFERENCED_1PARAMETER(cmd_details);
2199 i40e_fill_default_direct_cmd_desc(&desc,
2200 i40e_aqc_opc_get_vsi_parameters);
2202 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2204 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2206 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2207 sizeof(vsi_ctx->info), NULL);
2209 if (status != I40E_SUCCESS)
2210 goto aq_get_vsi_params_exit;
2212 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2213 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2214 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2215 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2217 aq_get_vsi_params_exit:
2222 * i40e_aq_update_vsi_params
2223 * @hw: pointer to the hw struct
2224 * @vsi_ctx: pointer to a vsi context struct
2225 * @cmd_details: pointer to command details structure or NULL
2227 * Update a VSI context.
2229 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2230 struct i40e_vsi_context *vsi_ctx,
2231 struct i40e_asq_cmd_details *cmd_details)
2233 struct i40e_aq_desc desc;
2234 struct i40e_aqc_add_get_update_vsi *cmd =
2235 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2236 enum i40e_status_code status;
2238 i40e_fill_default_direct_cmd_desc(&desc,
2239 i40e_aqc_opc_update_vsi_parameters);
2240 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2242 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2244 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2245 sizeof(vsi_ctx->info), cmd_details);
2251 * i40e_aq_get_switch_config
2252 * @hw: pointer to the hardware structure
2253 * @buf: pointer to the result buffer
2254 * @buf_size: length of input buffer
2255 * @start_seid: seid to start for the report, 0 == beginning
2256 * @cmd_details: pointer to command details structure or NULL
2258 * Fill the buf with switch configuration returned from AdminQ command
2260 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2261 struct i40e_aqc_get_switch_config_resp *buf,
2262 u16 buf_size, u16 *start_seid,
2263 struct i40e_asq_cmd_details *cmd_details)
2265 struct i40e_aq_desc desc;
2266 struct i40e_aqc_switch_seid *scfg =
2267 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2268 enum i40e_status_code status;
2270 i40e_fill_default_direct_cmd_desc(&desc,
2271 i40e_aqc_opc_get_switch_config);
2272 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2273 if (buf_size > I40E_AQ_LARGE_BUF)
2274 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2275 scfg->seid = CPU_TO_LE16(*start_seid);
2277 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2278 *start_seid = LE16_TO_CPU(scfg->seid);
2284 * i40e_aq_get_firmware_version
2285 * @hw: pointer to the hw struct
2286 * @fw_major_version: firmware major version
2287 * @fw_minor_version: firmware minor version
2288 * @fw_build: firmware build number
2289 * @api_major_version: major queue version
2290 * @api_minor_version: minor queue version
2291 * @cmd_details: pointer to command details structure or NULL
2293 * Get the firmware version from the admin queue commands
2295 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2296 u16 *fw_major_version, u16 *fw_minor_version,
2298 u16 *api_major_version, u16 *api_minor_version,
2299 struct i40e_asq_cmd_details *cmd_details)
2301 struct i40e_aq_desc desc;
2302 struct i40e_aqc_get_version *resp =
2303 (struct i40e_aqc_get_version *)&desc.params.raw;
2304 enum i40e_status_code status;
2306 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2308 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2310 if (status == I40E_SUCCESS) {
2311 if (fw_major_version != NULL)
2312 *fw_major_version = LE16_TO_CPU(resp->fw_major);
2313 if (fw_minor_version != NULL)
2314 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2315 if (fw_build != NULL)
2316 *fw_build = LE32_TO_CPU(resp->fw_build);
2317 if (api_major_version != NULL)
2318 *api_major_version = LE16_TO_CPU(resp->api_major);
2319 if (api_minor_version != NULL)
2320 *api_minor_version = LE16_TO_CPU(resp->api_minor);
2322 /* A workaround to fix the API version in SW */
2323 if (api_major_version && api_minor_version &&
2324 fw_major_version && fw_minor_version &&
2325 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2326 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2327 (*fw_major_version > 4)))
2328 *api_minor_version = 2;
2335 * i40e_aq_send_driver_version
2336 * @hw: pointer to the hw struct
2337 * @dv: driver's major, minor version
2338 * @cmd_details: pointer to command details structure or NULL
2340 * Send the driver version to the firmware
2342 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2343 struct i40e_driver_version *dv,
2344 struct i40e_asq_cmd_details *cmd_details)
2346 struct i40e_aq_desc desc;
2347 struct i40e_aqc_driver_version *cmd =
2348 (struct i40e_aqc_driver_version *)&desc.params.raw;
2349 enum i40e_status_code status;
2353 return I40E_ERR_PARAM;
2355 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2357 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2358 cmd->driver_major_ver = dv->major_version;
2359 cmd->driver_minor_ver = dv->minor_version;
2360 cmd->driver_build_ver = dv->build_version;
2361 cmd->driver_subbuild_ver = dv->subbuild_version;
2364 while (len < sizeof(dv->driver_string) &&
2365 (dv->driver_string[len] < 0x80) &&
2366 dv->driver_string[len])
2368 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2375 * i40e_get_link_status - get status of the HW network link
2376 * @hw: pointer to the hw struct
2377 * @link_up: pointer to bool (true/false = linkup/linkdown)
2379 * Variable link_up true if link is up, false if link is down.
2380 * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2382 * Side effect: LinkStatusEvent reporting becomes enabled
2384 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2386 enum i40e_status_code status = I40E_SUCCESS;
2388 if (hw->phy.get_link_info) {
2389 status = i40e_update_link_info(hw);
2391 if (status != I40E_SUCCESS)
2392 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2396 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2402 * i40e_updatelink_status - update status of the HW network link
2403 * @hw: pointer to the hw struct
2405 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2407 struct i40e_aq_get_phy_abilities_resp abilities;
2408 enum i40e_status_code status = I40E_SUCCESS;
2410 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2414 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
2419 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2420 sizeof(hw->phy.link_info.module_type));
2426 * i40e_get_link_speed
2427 * @hw: pointer to the hw struct
2429 * Returns the link speed of the adapter.
2431 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2433 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2434 enum i40e_status_code status = I40E_SUCCESS;
2436 if (hw->phy.get_link_info) {
2437 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2439 if (status != I40E_SUCCESS)
2440 goto i40e_link_speed_exit;
2443 speed = hw->phy.link_info.link_speed;
2445 i40e_link_speed_exit:
2450 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2451 * @hw: pointer to the hw struct
2452 * @uplink_seid: the MAC or other gizmo SEID
2453 * @downlink_seid: the VSI SEID
2454 * @enabled_tc: bitmap of TCs to be enabled
2455 * @default_port: true for default port VSI, false for control port
2456 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
2457 * @veb_seid: pointer to where to put the resulting VEB SEID
2458 * @cmd_details: pointer to command details structure or NULL
2460 * This asks the FW to add a VEB between the uplink and downlink
2461 * elements. If the uplink SEID is 0, this will be a floating VEB.
2463 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2464 u16 downlink_seid, u8 enabled_tc,
2465 bool default_port, bool enable_l2_filtering,
2467 struct i40e_asq_cmd_details *cmd_details)
2469 struct i40e_aq_desc desc;
2470 struct i40e_aqc_add_veb *cmd =
2471 (struct i40e_aqc_add_veb *)&desc.params.raw;
2472 struct i40e_aqc_add_veb_completion *resp =
2473 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2474 enum i40e_status_code status;
2477 /* SEIDs need to either both be set or both be 0 for floating VEB */
2478 if (!!uplink_seid != !!downlink_seid)
2479 return I40E_ERR_PARAM;
2481 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2483 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2484 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2485 cmd->enable_tcs = enabled_tc;
2487 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2489 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2491 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2493 if (enable_l2_filtering)
2494 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
2496 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2498 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2500 if (!status && veb_seid)
2501 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2507 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2508 * @hw: pointer to the hw struct
2509 * @veb_seid: the SEID of the VEB to query
2510 * @switch_id: the uplink switch id
2511 * @floating: set to true if the VEB is floating
2512 * @statistic_index: index of the stats counter block for this VEB
2513 * @vebs_used: number of VEB's used by function
2514 * @vebs_free: total VEB's not reserved by any function
2515 * @cmd_details: pointer to command details structure or NULL
2517 * This retrieves the parameters for a particular VEB, specified by
2518 * uplink_seid, and returns them to the caller.
2520 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2521 u16 veb_seid, u16 *switch_id,
2522 bool *floating, u16 *statistic_index,
2523 u16 *vebs_used, u16 *vebs_free,
2524 struct i40e_asq_cmd_details *cmd_details)
2526 struct i40e_aq_desc desc;
2527 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2528 (struct i40e_aqc_get_veb_parameters_completion *)
2530 enum i40e_status_code status;
2533 return I40E_ERR_PARAM;
2535 i40e_fill_default_direct_cmd_desc(&desc,
2536 i40e_aqc_opc_get_veb_parameters);
2537 cmd_resp->seid = CPU_TO_LE16(veb_seid);
2539 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2544 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2545 if (statistic_index)
2546 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2548 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2550 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2552 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2553 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2564 * i40e_aq_add_macvlan
2565 * @hw: pointer to the hw struct
2566 * @seid: VSI for the mac address
2567 * @mv_list: list of macvlans to be added
2568 * @count: length of the list
2569 * @cmd_details: pointer to command details structure or NULL
2571 * Add MAC/VLAN addresses to the HW filtering
2573 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2574 struct i40e_aqc_add_macvlan_element_data *mv_list,
2575 u16 count, struct i40e_asq_cmd_details *cmd_details)
2577 struct i40e_aq_desc desc;
2578 struct i40e_aqc_macvlan *cmd =
2579 (struct i40e_aqc_macvlan *)&desc.params.raw;
2580 enum i40e_status_code status;
2583 if (count == 0 || !mv_list || !hw)
2584 return I40E_ERR_PARAM;
2586 buf_size = count * sizeof(*mv_list);
2588 /* prep the rest of the request */
2589 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2590 cmd->num_addresses = CPU_TO_LE16(count);
2591 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2595 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2596 if (buf_size > I40E_AQ_LARGE_BUF)
2597 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2599 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2606 * i40e_aq_remove_macvlan
2607 * @hw: pointer to the hw struct
2608 * @seid: VSI for the mac address
2609 * @mv_list: list of macvlans to be removed
2610 * @count: length of the list
2611 * @cmd_details: pointer to command details structure or NULL
2613 * Remove MAC/VLAN addresses from the HW filtering
2615 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2616 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2617 u16 count, struct i40e_asq_cmd_details *cmd_details)
2619 struct i40e_aq_desc desc;
2620 struct i40e_aqc_macvlan *cmd =
2621 (struct i40e_aqc_macvlan *)&desc.params.raw;
2622 enum i40e_status_code status;
2625 if (count == 0 || !mv_list || !hw)
2626 return I40E_ERR_PARAM;
2628 buf_size = count * sizeof(*mv_list);
2630 /* prep the rest of the request */
2631 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2632 cmd->num_addresses = CPU_TO_LE16(count);
2633 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2637 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2638 if (buf_size > I40E_AQ_LARGE_BUF)
2639 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2641 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2648 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
2649 * @hw: pointer to the hw struct
2650 * @seid: VSI for the vlan filters
2651 * @v_list: list of vlan filters to be added
2652 * @count: length of the list
2653 * @cmd_details: pointer to command details structure or NULL
2655 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
2656 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2657 u8 count, struct i40e_asq_cmd_details *cmd_details)
2659 struct i40e_aq_desc desc;
2660 struct i40e_aqc_macvlan *cmd =
2661 (struct i40e_aqc_macvlan *)&desc.params.raw;
2662 enum i40e_status_code status;
2665 if (count == 0 || !v_list || !hw)
2666 return I40E_ERR_PARAM;
2668 buf_size = count * sizeof(*v_list);
2670 /* prep the rest of the request */
2671 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
2672 cmd->num_addresses = CPU_TO_LE16(count);
2673 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2677 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2678 if (buf_size > I40E_AQ_LARGE_BUF)
2679 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2681 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2688 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
2689 * @hw: pointer to the hw struct
2690 * @seid: VSI for the vlan filters
2691 * @v_list: list of macvlans to be removed
2692 * @count: length of the list
2693 * @cmd_details: pointer to command details structure or NULL
2695 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
2696 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2697 u8 count, struct i40e_asq_cmd_details *cmd_details)
2699 struct i40e_aq_desc desc;
2700 struct i40e_aqc_macvlan *cmd =
2701 (struct i40e_aqc_macvlan *)&desc.params.raw;
2702 enum i40e_status_code status;
2705 if (count == 0 || !v_list || !hw)
2706 return I40E_ERR_PARAM;
2708 buf_size = count * sizeof(*v_list);
2710 /* prep the rest of the request */
2711 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
2712 cmd->num_addresses = CPU_TO_LE16(count);
2713 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2717 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2718 if (buf_size > I40E_AQ_LARGE_BUF)
2719 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2721 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2728 * i40e_aq_send_msg_to_vf
2729 * @hw: pointer to the hardware structure
2730 * @vfid: vf id to send msg
2731 * @v_opcode: opcodes for VF-PF communication
2732 * @v_retval: return error code
2733 * @msg: pointer to the msg buffer
2734 * @msglen: msg length
2735 * @cmd_details: pointer to command details
2739 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2740 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2741 struct i40e_asq_cmd_details *cmd_details)
2743 struct i40e_aq_desc desc;
2744 struct i40e_aqc_pf_vf_message *cmd =
2745 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2746 enum i40e_status_code status;
2748 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2749 cmd->id = CPU_TO_LE32(vfid);
2750 desc.cookie_high = CPU_TO_LE32(v_opcode);
2751 desc.cookie_low = CPU_TO_LE32(v_retval);
2752 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
2754 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
2756 if (msglen > I40E_AQ_LARGE_BUF)
2757 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2758 desc.datalen = CPU_TO_LE16(msglen);
2760 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2766 * i40e_aq_debug_read_register
2767 * @hw: pointer to the hw struct
2768 * @reg_addr: register address
2769 * @reg_val: register value
2770 * @cmd_details: pointer to command details structure or NULL
2772 * Read the register using the admin queue commands
2774 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
2775 u32 reg_addr, u64 *reg_val,
2776 struct i40e_asq_cmd_details *cmd_details)
2778 struct i40e_aq_desc desc;
2779 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2780 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2781 enum i40e_status_code status;
2783 if (reg_val == NULL)
2784 return I40E_ERR_PARAM;
2786 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2788 cmd_resp->address = CPU_TO_LE32(reg_addr);
2790 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2792 if (status == I40E_SUCCESS) {
2793 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
2794 (u64)LE32_TO_CPU(cmd_resp->value_low);
2801 * i40e_aq_debug_write_register
2802 * @hw: pointer to the hw struct
2803 * @reg_addr: register address
2804 * @reg_val: register value
2805 * @cmd_details: pointer to command details structure or NULL
2807 * Write to a register using the admin queue commands
2809 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
2810 u32 reg_addr, u64 reg_val,
2811 struct i40e_asq_cmd_details *cmd_details)
2813 struct i40e_aq_desc desc;
2814 struct i40e_aqc_debug_reg_read_write *cmd =
2815 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2816 enum i40e_status_code status;
2818 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2820 cmd->address = CPU_TO_LE32(reg_addr);
2821 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
2822 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
2824 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2830 * i40e_aq_get_hmc_resource_profile
2831 * @hw: pointer to the hw struct
2832 * @profile: type of profile the HMC is to be set as
2833 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2834 * @cmd_details: pointer to command details structure or NULL
2836 * query the HMC profile of the device.
2838 enum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw,
2839 enum i40e_aq_hmc_profile *profile,
2840 u8 *pe_vf_enabled_count,
2841 struct i40e_asq_cmd_details *cmd_details)
2843 struct i40e_aq_desc desc;
2844 struct i40e_aq_get_set_hmc_resource_profile *resp =
2845 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2846 enum i40e_status_code status;
2848 i40e_fill_default_direct_cmd_desc(&desc,
2849 i40e_aqc_opc_query_hmc_resource_profile);
2850 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2852 *profile = (enum i40e_aq_hmc_profile)(resp->pm_profile &
2853 I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK);
2854 *pe_vf_enabled_count = resp->pe_vf_enabled &
2855 I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK;
2861 * i40e_aq_set_hmc_resource_profile
2862 * @hw: pointer to the hw struct
2863 * @profile: type of profile the HMC is to be set as
2864 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2865 * @cmd_details: pointer to command details structure or NULL
2867 * set the HMC profile of the device.
2869 enum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2870 enum i40e_aq_hmc_profile profile,
2871 u8 pe_vf_enabled_count,
2872 struct i40e_asq_cmd_details *cmd_details)
2874 struct i40e_aq_desc desc;
2875 struct i40e_aq_get_set_hmc_resource_profile *cmd =
2876 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2877 enum i40e_status_code status;
2879 i40e_fill_default_direct_cmd_desc(&desc,
2880 i40e_aqc_opc_set_hmc_resource_profile);
2882 cmd->pm_profile = (u8)profile;
2883 cmd->pe_vf_enabled = pe_vf_enabled_count;
2885 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2891 * i40e_aq_request_resource
2892 * @hw: pointer to the hw struct
2893 * @resource: resource id
2894 * @access: access type
2895 * @sdp_number: resource number
2896 * @timeout: the maximum time in ms that the driver may hold the resource
2897 * @cmd_details: pointer to command details structure or NULL
2899 * requests common resource using the admin queue commands
2901 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
2902 enum i40e_aq_resources_ids resource,
2903 enum i40e_aq_resource_access_type access,
2904 u8 sdp_number, u64 *timeout,
2905 struct i40e_asq_cmd_details *cmd_details)
2907 struct i40e_aq_desc desc;
2908 struct i40e_aqc_request_resource *cmd_resp =
2909 (struct i40e_aqc_request_resource *)&desc.params.raw;
2910 enum i40e_status_code status;
2912 DEBUGFUNC("i40e_aq_request_resource");
2914 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2916 cmd_resp->resource_id = CPU_TO_LE16(resource);
2917 cmd_resp->access_type = CPU_TO_LE16(access);
2918 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
2920 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2921 /* The completion specifies the maximum time in ms that the driver
2922 * may hold the resource in the Timeout field.
2923 * If the resource is held by someone else, the command completes with
2924 * busy return value and the timeout field indicates the maximum time
2925 * the current owner of the resource has to free it.
2927 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2928 *timeout = LE32_TO_CPU(cmd_resp->timeout);
2934 * i40e_aq_release_resource
2935 * @hw: pointer to the hw struct
2936 * @resource: resource id
2937 * @sdp_number: resource number
2938 * @cmd_details: pointer to command details structure or NULL
2940 * release common resource using the admin queue commands
2942 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
2943 enum i40e_aq_resources_ids resource,
2945 struct i40e_asq_cmd_details *cmd_details)
2947 struct i40e_aq_desc desc;
2948 struct i40e_aqc_request_resource *cmd =
2949 (struct i40e_aqc_request_resource *)&desc.params.raw;
2950 enum i40e_status_code status;
2952 DEBUGFUNC("i40e_aq_release_resource");
2954 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2956 cmd->resource_id = CPU_TO_LE16(resource);
2957 cmd->resource_number = CPU_TO_LE32(sdp_number);
2959 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2966 * @hw: pointer to the hw struct
2967 * @module_pointer: module pointer location in words from the NVM beginning
2968 * @offset: byte offset from the module beginning
2969 * @length: length of the section to be read (in bytes from the offset)
2970 * @data: command buffer (size [bytes] = length)
2971 * @last_command: tells if this is the last command in a series
2972 * @cmd_details: pointer to command details structure or NULL
2974 * Read the NVM using the admin queue commands
2976 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2977 u32 offset, u16 length, void *data,
2979 struct i40e_asq_cmd_details *cmd_details)
2981 struct i40e_aq_desc desc;
2982 struct i40e_aqc_nvm_update *cmd =
2983 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2984 enum i40e_status_code status;
2986 DEBUGFUNC("i40e_aq_read_nvm");
2988 /* In offset the highest byte must be zeroed. */
2989 if (offset & 0xFF000000) {
2990 status = I40E_ERR_PARAM;
2991 goto i40e_aq_read_nvm_exit;
2994 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2996 /* If this is the last command in a series, set the proper flag. */
2998 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2999 cmd->module_pointer = module_pointer;
3000 cmd->offset = CPU_TO_LE32(offset);
3001 cmd->length = CPU_TO_LE16(length);
3003 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3004 if (length > I40E_AQ_LARGE_BUF)
3005 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3007 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3009 i40e_aq_read_nvm_exit:
3014 * i40e_aq_read_nvm_config - read an nvm config block
3015 * @hw: pointer to the hw struct
3016 * @cmd_flags: NVM access admin command bits
3017 * @field_id: field or feature id
3018 * @data: buffer for result
3019 * @buf_size: buffer size
3020 * @element_count: pointer to count of elements read by FW
3021 * @cmd_details: pointer to command details structure or NULL
3023 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3024 u8 cmd_flags, u32 field_id, void *data,
3025 u16 buf_size, u16 *element_count,
3026 struct i40e_asq_cmd_details *cmd_details)
3028 struct i40e_aq_desc desc;
3029 struct i40e_aqc_nvm_config_read *cmd =
3030 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3031 enum i40e_status_code status;
3033 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3034 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3035 if (buf_size > I40E_AQ_LARGE_BUF)
3036 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3038 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3039 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3040 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3041 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3043 cmd->element_id_msw = 0;
3045 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3047 if (!status && element_count)
3048 *element_count = LE16_TO_CPU(cmd->element_count);
3054 * i40e_aq_write_nvm_config - write an nvm config block
3055 * @hw: pointer to the hw struct
3056 * @cmd_flags: NVM access admin command bits
3057 * @data: buffer for result
3058 * @buf_size: buffer size
3059 * @element_count: count of elements to be written
3060 * @cmd_details: pointer to command details structure or NULL
3062 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3063 u8 cmd_flags, void *data, u16 buf_size,
3065 struct i40e_asq_cmd_details *cmd_details)
3067 struct i40e_aq_desc desc;
3068 struct i40e_aqc_nvm_config_write *cmd =
3069 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3070 enum i40e_status_code status;
3072 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3073 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3074 if (buf_size > I40E_AQ_LARGE_BUF)
3075 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3077 cmd->element_count = CPU_TO_LE16(element_count);
3078 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3079 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3085 * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3086 * @hw: pointer to the hw struct
3087 * @cmd_details: pointer to command details structure or NULL
3089 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3090 void *buff, u16 buff_size,
3091 struct i40e_asq_cmd_details *cmd_details)
3093 struct i40e_aq_desc desc;
3094 enum i40e_status_code status;
3096 UNREFERENCED_2PARAMETER(buff, buff_size);
3098 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3099 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3100 if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3101 status = I40E_ERR_NOT_IMPLEMENTED;
3108 * @hw: pointer to the hw struct
3109 * @module_pointer: module pointer location in words from the NVM beginning
3110 * @offset: offset in the module (expressed in 4 KB from module's beginning)
3111 * @length: length of the section to be erased (expressed in 4 KB)
3112 * @last_command: tells if this is the last command in a series
3113 * @cmd_details: pointer to command details structure or NULL
3115 * Erase the NVM sector using the admin queue commands
3117 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3118 u32 offset, u16 length, bool last_command,
3119 struct i40e_asq_cmd_details *cmd_details)
3121 struct i40e_aq_desc desc;
3122 struct i40e_aqc_nvm_update *cmd =
3123 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3124 enum i40e_status_code status;
3126 DEBUGFUNC("i40e_aq_erase_nvm");
3128 /* In offset the highest byte must be zeroed. */
3129 if (offset & 0xFF000000) {
3130 status = I40E_ERR_PARAM;
3131 goto i40e_aq_erase_nvm_exit;
3134 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3136 /* If this is the last command in a series, set the proper flag. */
3138 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3139 cmd->module_pointer = module_pointer;
3140 cmd->offset = CPU_TO_LE32(offset);
3141 cmd->length = CPU_TO_LE16(length);
3143 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3145 i40e_aq_erase_nvm_exit:
3149 #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
3150 #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
3151 #define I40E_DEV_FUNC_CAP_NPAR 0x03
3152 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04
3153 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
3154 #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
3155 #define I40E_DEV_FUNC_CAP_VF 0x13
3156 #define I40E_DEV_FUNC_CAP_VMDQ 0x14
3157 #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
3158 #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
3159 #define I40E_DEV_FUNC_CAP_VSI 0x17
3160 #define I40E_DEV_FUNC_CAP_DCB 0x18
3161 #define I40E_DEV_FUNC_CAP_FCOE 0x21
3162 #define I40E_DEV_FUNC_CAP_ISCSI 0x22
3163 #define I40E_DEV_FUNC_CAP_RSS 0x40
3164 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
3165 #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
3166 #define I40E_DEV_FUNC_CAP_MSIX 0x43
3167 #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
3168 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
3169 #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
3170 #define I40E_DEV_FUNC_CAP_FLEX10 0xF1
3171 #define I40E_DEV_FUNC_CAP_CEM 0xF2
3172 #define I40E_DEV_FUNC_CAP_IWARP 0x51
3173 #define I40E_DEV_FUNC_CAP_LED 0x61
3174 #define I40E_DEV_FUNC_CAP_SDP 0x62
3175 #define I40E_DEV_FUNC_CAP_MDIO 0x63
3178 * i40e_parse_discover_capabilities
3179 * @hw: pointer to the hw struct
3180 * @buff: pointer to a buffer containing device/function capability records
3181 * @cap_count: number of capability records in the list
3182 * @list_type_opc: type of capabilities list to parse
3184 * Parse the device/function capabilities list.
3186 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3188 enum i40e_admin_queue_opc list_type_opc)
3190 struct i40e_aqc_list_capabilities_element_resp *cap;
3191 u32 valid_functions, num_functions;
3192 u32 number, logical_id, phys_id;
3193 struct i40e_hw_capabilities *p;
3198 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3200 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3201 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3202 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3203 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3207 for (i = 0; i < cap_count; i++, cap++) {
3208 id = LE16_TO_CPU(cap->id);
3209 number = LE32_TO_CPU(cap->number);
3210 logical_id = LE32_TO_CPU(cap->logical_id);
3211 phys_id = LE32_TO_CPU(cap->phys_id);
3212 major_rev = cap->major_rev;
3215 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
3216 p->switch_mode = number;
3218 case I40E_DEV_FUNC_CAP_MGMT_MODE:
3219 p->management_mode = number;
3221 case I40E_DEV_FUNC_CAP_NPAR:
3222 p->npar_enable = number;
3224 case I40E_DEV_FUNC_CAP_OS2BMC:
3227 case I40E_DEV_FUNC_CAP_VALID_FUNC:
3228 p->valid_functions = number;
3230 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
3232 p->sr_iov_1_1 = true;
3234 case I40E_DEV_FUNC_CAP_VF:
3235 p->num_vfs = number;
3236 p->vf_base_id = logical_id;
3238 case I40E_DEV_FUNC_CAP_VMDQ:
3242 case I40E_DEV_FUNC_CAP_802_1_QBG:
3244 p->evb_802_1_qbg = true;
3246 case I40E_DEV_FUNC_CAP_802_1_QBH:
3248 p->evb_802_1_qbh = true;
3250 case I40E_DEV_FUNC_CAP_VSI:
3251 p->num_vsis = number;
3253 case I40E_DEV_FUNC_CAP_DCB:
3256 p->enabled_tcmap = logical_id;
3260 case I40E_DEV_FUNC_CAP_FCOE:
3264 case I40E_DEV_FUNC_CAP_ISCSI:
3268 case I40E_DEV_FUNC_CAP_RSS:
3270 p->rss_table_size = number;
3271 p->rss_table_entry_width = logical_id;
3273 case I40E_DEV_FUNC_CAP_RX_QUEUES:
3274 p->num_rx_qp = number;
3275 p->base_queue = phys_id;
3277 case I40E_DEV_FUNC_CAP_TX_QUEUES:
3278 p->num_tx_qp = number;
3279 p->base_queue = phys_id;
3281 case I40E_DEV_FUNC_CAP_MSIX:
3282 p->num_msix_vectors = number;
3284 case I40E_DEV_FUNC_CAP_MSIX_VF:
3285 p->num_msix_vectors_vf = number;
3287 case I40E_DEV_FUNC_CAP_FLEX10:
3288 if (major_rev == 1) {
3290 p->flex10_enable = true;
3291 p->flex10_capable = true;
3294 /* Capability revision >= 2 */
3296 p->flex10_enable = true;
3298 p->flex10_capable = true;
3300 p->flex10_mode = logical_id;
3301 p->flex10_status = phys_id;
3303 case I40E_DEV_FUNC_CAP_CEM:
3307 case I40E_DEV_FUNC_CAP_IWARP:
3311 case I40E_DEV_FUNC_CAP_LED:
3312 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3313 p->led[phys_id] = true;
3315 case I40E_DEV_FUNC_CAP_SDP:
3316 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3317 p->sdp[phys_id] = true;
3319 case I40E_DEV_FUNC_CAP_MDIO:
3321 p->mdio_port_num = phys_id;
3322 p->mdio_port_mode = logical_id;
3325 case I40E_DEV_FUNC_CAP_IEEE_1588:
3327 p->ieee_1588 = true;
3329 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
3331 p->fd_filters_guaranteed = number;
3332 p->fd_filters_best_effort = logical_id;
3339 #ifdef I40E_FCOE_ENA
3340 /* Software override ensuring FCoE is disabled if npar or mfp
3341 * mode because it is not supported in these modes.
3343 if (p->npar_enable || p->flex10_enable)
3346 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3350 /* count the enabled ports (aka the "not disabled" ports) */
3352 for (i = 0; i < 4; i++) {
3353 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3356 /* use AQ read to get the physical register offset instead
3357 * of the port relative offset
3359 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3360 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3364 valid_functions = p->valid_functions;
3366 while (valid_functions) {
3367 if (valid_functions & 1)
3369 valid_functions >>= 1;
3372 /* partition id is 1-based, and functions are evenly spread
3373 * across the ports as partitions
3375 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3376 hw->num_partitions = num_functions / hw->num_ports;
3378 /* additional HW specific goodies that might
3379 * someday be HW version specific
3381 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3385 * i40e_aq_discover_capabilities
3386 * @hw: pointer to the hw struct
3387 * @buff: a virtual buffer to hold the capabilities
3388 * @buff_size: Size of the virtual buffer
3389 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3390 * @list_type_opc: capabilities type to discover - pass in the command opcode
3391 * @cmd_details: pointer to command details structure or NULL
3393 * Get the device capabilities descriptions from the firmware
3395 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3396 void *buff, u16 buff_size, u16 *data_size,
3397 enum i40e_admin_queue_opc list_type_opc,
3398 struct i40e_asq_cmd_details *cmd_details)
3400 struct i40e_aqc_list_capabilites *cmd;
3401 struct i40e_aq_desc desc;
3402 enum i40e_status_code status = I40E_SUCCESS;
3404 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3406 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3407 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3408 status = I40E_ERR_PARAM;
3412 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3414 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3415 if (buff_size > I40E_AQ_LARGE_BUF)
3416 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3418 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3419 *data_size = LE16_TO_CPU(desc.datalen);
3424 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3432 * i40e_aq_update_nvm
3433 * @hw: pointer to the hw struct
3434 * @module_pointer: module pointer location in words from the NVM beginning
3435 * @offset: byte offset from the module beginning
3436 * @length: length of the section to be written (in bytes from the offset)
3437 * @data: command buffer (size [bytes] = length)
3438 * @last_command: tells if this is the last command in a series
3439 * @cmd_details: pointer to command details structure or NULL
3441 * Update the NVM using the admin queue commands
3443 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3444 u32 offset, u16 length, void *data,
3446 struct i40e_asq_cmd_details *cmd_details)
3448 struct i40e_aq_desc desc;
3449 struct i40e_aqc_nvm_update *cmd =
3450 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3451 enum i40e_status_code status;
3453 DEBUGFUNC("i40e_aq_update_nvm");
3455 /* In offset the highest byte must be zeroed. */
3456 if (offset & 0xFF000000) {
3457 status = I40E_ERR_PARAM;
3458 goto i40e_aq_update_nvm_exit;
3461 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3463 /* If this is the last command in a series, set the proper flag. */
3465 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3466 cmd->module_pointer = module_pointer;
3467 cmd->offset = CPU_TO_LE32(offset);
3468 cmd->length = CPU_TO_LE16(length);
3470 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3471 if (length > I40E_AQ_LARGE_BUF)
3472 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3474 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3476 i40e_aq_update_nvm_exit:
3481 * i40e_aq_get_lldp_mib
3482 * @hw: pointer to the hw struct
3483 * @bridge_type: type of bridge requested
3484 * @mib_type: Local, Remote or both Local and Remote MIBs
3485 * @buff: pointer to a user supplied buffer to store the MIB block
3486 * @buff_size: size of the buffer (in bytes)
3487 * @local_len : length of the returned Local LLDP MIB
3488 * @remote_len: length of the returned Remote LLDP MIB
3489 * @cmd_details: pointer to command details structure or NULL
3491 * Requests the complete LLDP MIB (entire packet).
3493 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3494 u8 mib_type, void *buff, u16 buff_size,
3495 u16 *local_len, u16 *remote_len,
3496 struct i40e_asq_cmd_details *cmd_details)
3498 struct i40e_aq_desc desc;
3499 struct i40e_aqc_lldp_get_mib *cmd =
3500 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3501 struct i40e_aqc_lldp_get_mib *resp =
3502 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3503 enum i40e_status_code status;
3505 if (buff_size == 0 || !buff)
3506 return I40E_ERR_PARAM;
3508 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3509 /* Indirect Command */
3510 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3512 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3513 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3514 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3516 desc.datalen = CPU_TO_LE16(buff_size);
3518 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3519 if (buff_size > I40E_AQ_LARGE_BUF)
3520 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3522 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3524 if (local_len != NULL)
3525 *local_len = LE16_TO_CPU(resp->local_len);
3526 if (remote_len != NULL)
3527 *remote_len = LE16_TO_CPU(resp->remote_len);
3534 * i40e_aq_set_lldp_mib - Set the LLDP MIB
3535 * @hw: pointer to the hw struct
3536 * @mib_type: Local, Remote or both Local and Remote MIBs
3537 * @buff: pointer to a user supplied buffer to store the MIB block
3538 * @buff_size: size of the buffer (in bytes)
3539 * @cmd_details: pointer to command details structure or NULL
3543 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
3544 u8 mib_type, void *buff, u16 buff_size,
3545 struct i40e_asq_cmd_details *cmd_details)
3547 struct i40e_aq_desc desc;
3548 struct i40e_aqc_lldp_set_local_mib *cmd =
3549 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
3550 enum i40e_status_code status;
3552 if (buff_size == 0 || !buff)
3553 return I40E_ERR_PARAM;
3555 i40e_fill_default_direct_cmd_desc(&desc,
3556 i40e_aqc_opc_lldp_set_local_mib);
3557 /* Indirect Command */
3558 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3559 if (buff_size > I40E_AQ_LARGE_BUF)
3560 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3561 desc.datalen = CPU_TO_LE16(buff_size);
3563 cmd->type = mib_type;
3564 cmd->length = CPU_TO_LE16(buff_size);
3565 cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
3566 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
3568 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3573 * i40e_aq_cfg_lldp_mib_change_event
3574 * @hw: pointer to the hw struct
3575 * @enable_update: Enable or Disable event posting
3576 * @cmd_details: pointer to command details structure or NULL
3578 * Enable or Disable posting of an event on ARQ when LLDP MIB
3579 * associated with the interface changes
3581 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3583 struct i40e_asq_cmd_details *cmd_details)
3585 struct i40e_aq_desc desc;
3586 struct i40e_aqc_lldp_update_mib *cmd =
3587 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3588 enum i40e_status_code status;
3590 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3593 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3595 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3601 * i40e_aq_add_lldp_tlv
3602 * @hw: pointer to the hw struct
3603 * @bridge_type: type of bridge
3604 * @buff: buffer with TLV to add
3605 * @buff_size: length of the buffer
3606 * @tlv_len: length of the TLV to be added
3607 * @mib_len: length of the LLDP MIB returned in response
3608 * @cmd_details: pointer to command details structure or NULL
3610 * Add the specified TLV to LLDP Local MIB for the given bridge type,
3611 * it is responsibility of the caller to make sure that the TLV is not
3612 * already present in the LLDPDU.
3613 * In return firmware will write the complete LLDP MIB with the newly
3614 * added TLV in the response buffer.
3616 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
3617 void *buff, u16 buff_size, u16 tlv_len,
3619 struct i40e_asq_cmd_details *cmd_details)
3621 struct i40e_aq_desc desc;
3622 struct i40e_aqc_lldp_add_tlv *cmd =
3623 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3624 enum i40e_status_code status;
3626 if (buff_size == 0 || !buff || tlv_len == 0)
3627 return I40E_ERR_PARAM;
3629 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
3631 /* Indirect Command */
3632 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3633 if (buff_size > I40E_AQ_LARGE_BUF)
3634 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3635 desc.datalen = CPU_TO_LE16(buff_size);
3637 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3638 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3639 cmd->len = CPU_TO_LE16(tlv_len);
3641 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3643 if (mib_len != NULL)
3644 *mib_len = LE16_TO_CPU(desc.datalen);
3651 * i40e_aq_update_lldp_tlv
3652 * @hw: pointer to the hw struct
3653 * @bridge_type: type of bridge
3654 * @buff: buffer with TLV to update
3655 * @buff_size: size of the buffer holding original and updated TLVs
3656 * @old_len: Length of the Original TLV
3657 * @new_len: Length of the Updated TLV
3658 * @offset: offset of the updated TLV in the buff
3659 * @mib_len: length of the returned LLDP MIB
3660 * @cmd_details: pointer to command details structure or NULL
3662 * Update the specified TLV to the LLDP Local MIB for the given bridge type.
3663 * Firmware will place the complete LLDP MIB in response buffer with the
3666 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
3667 u8 bridge_type, void *buff, u16 buff_size,
3668 u16 old_len, u16 new_len, u16 offset,
3670 struct i40e_asq_cmd_details *cmd_details)
3672 struct i40e_aq_desc desc;
3673 struct i40e_aqc_lldp_update_tlv *cmd =
3674 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
3675 enum i40e_status_code status;
3677 if (buff_size == 0 || !buff || offset == 0 ||
3678 old_len == 0 || new_len == 0)
3679 return I40E_ERR_PARAM;
3681 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
3683 /* Indirect Command */
3684 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3685 if (buff_size > I40E_AQ_LARGE_BUF)
3686 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3687 desc.datalen = CPU_TO_LE16(buff_size);
3689 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3690 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3691 cmd->old_len = CPU_TO_LE16(old_len);
3692 cmd->new_offset = CPU_TO_LE16(offset);
3693 cmd->new_len = CPU_TO_LE16(new_len);
3695 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3697 if (mib_len != NULL)
3698 *mib_len = LE16_TO_CPU(desc.datalen);
3705 * i40e_aq_delete_lldp_tlv
3706 * @hw: pointer to the hw struct
3707 * @bridge_type: type of bridge
3708 * @buff: pointer to a user supplied buffer that has the TLV
3709 * @buff_size: length of the buffer
3710 * @tlv_len: length of the TLV to be deleted
3711 * @mib_len: length of the returned LLDP MIB
3712 * @cmd_details: pointer to command details structure or NULL
3714 * Delete the specified TLV from LLDP Local MIB for the given bridge type.
3715 * The firmware places the entire LLDP MIB in the response buffer.
3717 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
3718 u8 bridge_type, void *buff, u16 buff_size,
3719 u16 tlv_len, u16 *mib_len,
3720 struct i40e_asq_cmd_details *cmd_details)
3722 struct i40e_aq_desc desc;
3723 struct i40e_aqc_lldp_add_tlv *cmd =
3724 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3725 enum i40e_status_code status;
3727 if (buff_size == 0 || !buff)
3728 return I40E_ERR_PARAM;
3730 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
3732 /* Indirect Command */
3733 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3734 if (buff_size > I40E_AQ_LARGE_BUF)
3735 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3736 desc.datalen = CPU_TO_LE16(buff_size);
3737 cmd->len = CPU_TO_LE16(tlv_len);
3738 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3739 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3741 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3743 if (mib_len != NULL)
3744 *mib_len = LE16_TO_CPU(desc.datalen);
3752 * @hw: pointer to the hw struct
3753 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3754 * @cmd_details: pointer to command details structure or NULL
3756 * Stop or Shutdown the embedded LLDP Agent
3758 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3759 struct i40e_asq_cmd_details *cmd_details)
3761 struct i40e_aq_desc desc;
3762 struct i40e_aqc_lldp_stop *cmd =
3763 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3764 enum i40e_status_code status;
3766 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3769 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3771 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3777 * i40e_aq_start_lldp
3778 * @hw: pointer to the hw struct
3779 * @cmd_details: pointer to command details structure or NULL
3781 * Start the embedded LLDP Agent on all ports.
3783 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
3784 struct i40e_asq_cmd_details *cmd_details)
3786 struct i40e_aq_desc desc;
3787 struct i40e_aqc_lldp_start *cmd =
3788 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3789 enum i40e_status_code status;
3791 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3793 cmd->command = I40E_AQ_LLDP_AGENT_START;
3795 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3801 * i40e_aq_get_cee_dcb_config
3802 * @hw: pointer to the hw struct
3803 * @buff: response buffer that stores CEE operational configuration
3804 * @buff_size: size of the buffer passed
3805 * @cmd_details: pointer to command details structure or NULL
3807 * Get CEE DCBX mode operational configuration from firmware
3809 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3810 void *buff, u16 buff_size,
3811 struct i40e_asq_cmd_details *cmd_details)
3813 struct i40e_aq_desc desc;
3814 enum i40e_status_code status;
3816 if (buff_size == 0 || !buff)
3817 return I40E_ERR_PARAM;
3819 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3821 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3822 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3829 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
3830 * @hw: pointer to the hw struct
3831 * @start_agent: True if DCBx Agent needs to be Started
3832 * False if DCBx Agent needs to be Stopped
3833 * @cmd_details: pointer to command details structure or NULL
3835 * Start/Stop the embedded dcbx Agent
3837 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
3839 struct i40e_asq_cmd_details *cmd_details)
3841 struct i40e_aq_desc desc;
3842 struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
3843 (struct i40e_aqc_lldp_stop_start_specific_agent *)
3845 enum i40e_status_code status;
3847 i40e_fill_default_direct_cmd_desc(&desc,
3848 i40e_aqc_opc_lldp_stop_start_spec_agent);
3851 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
3853 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3859 * i40e_aq_add_udp_tunnel
3860 * @hw: pointer to the hw struct
3861 * @udp_port: the UDP port to add
3862 * @header_len: length of the tunneling header length in DWords
3863 * @protocol_index: protocol index type
3864 * @filter_index: pointer to filter index
3865 * @cmd_details: pointer to command details structure or NULL
3867 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3868 u16 udp_port, u8 protocol_index,
3870 struct i40e_asq_cmd_details *cmd_details)
3872 struct i40e_aq_desc desc;
3873 struct i40e_aqc_add_udp_tunnel *cmd =
3874 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3875 struct i40e_aqc_del_udp_tunnel_completion *resp =
3876 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3877 enum i40e_status_code status;
3879 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3881 cmd->udp_port = CPU_TO_LE16(udp_port);
3882 cmd->protocol_type = protocol_index;
3884 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3886 if (!status && filter_index)
3887 *filter_index = resp->index;
3893 * i40e_aq_del_udp_tunnel
3894 * @hw: pointer to the hw struct
3895 * @index: filter index
3896 * @cmd_details: pointer to command details structure or NULL
3898 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3899 struct i40e_asq_cmd_details *cmd_details)
3901 struct i40e_aq_desc desc;
3902 struct i40e_aqc_remove_udp_tunnel *cmd =
3903 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3904 enum i40e_status_code status;
3906 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3910 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3916 * i40e_aq_get_switch_resource_alloc (0x0204)
3917 * @hw: pointer to the hw struct
3918 * @num_entries: pointer to u8 to store the number of resource entries returned
3919 * @buf: pointer to a user supplied buffer. This buffer must be large enough
3920 * to store the resource information for all resource types. Each
3921 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
3922 * @count: size, in bytes, of the buffer provided
3923 * @cmd_details: pointer to command details structure or NULL
3925 * Query the resources allocated to a function.
3927 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
3929 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
3931 struct i40e_asq_cmd_details *cmd_details)
3933 struct i40e_aq_desc desc;
3934 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
3935 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
3936 enum i40e_status_code status;
3937 u16 length = count * sizeof(*buf);
3939 i40e_fill_default_direct_cmd_desc(&desc,
3940 i40e_aqc_opc_get_switch_resource_alloc);
3942 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3943 if (length > I40E_AQ_LARGE_BUF)
3944 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3946 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
3948 if (!status && num_entries)
3949 *num_entries = cmd_resp->num_entries;
3955 * i40e_aq_delete_element - Delete switch element
3956 * @hw: pointer to the hw struct
3957 * @seid: the SEID to delete from the switch
3958 * @cmd_details: pointer to command details structure or NULL
3960 * This deletes a switch element from the switch.
3962 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3963 struct i40e_asq_cmd_details *cmd_details)
3965 struct i40e_aq_desc desc;
3966 struct i40e_aqc_switch_seid *cmd =
3967 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3968 enum i40e_status_code status;
3971 return I40E_ERR_PARAM;
3973 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3975 cmd->seid = CPU_TO_LE16(seid);
3977 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3983 * i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port
3984 * @hw: pointer to the hw struct
3985 * @flags: component flags
3986 * @mac_seid: uplink seid (MAC SEID)
3987 * @vsi_seid: connected vsi seid
3988 * @ret_seid: seid of create pv component
3990 * This instantiates an i40e port virtualizer with specified flags.
3991 * Depending on specified flags the port virtualizer can act as a
3992 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
3994 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
3995 u16 mac_seid, u16 vsi_seid,
3998 struct i40e_aq_desc desc;
3999 struct i40e_aqc_add_update_pv *cmd =
4000 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4001 struct i40e_aqc_add_update_pv_completion *resp =
4002 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4003 enum i40e_status_code status;
4006 return I40E_ERR_PARAM;
4008 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4009 cmd->command_flags = CPU_TO_LE16(flags);
4010 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4011 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4013 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4014 if (!status && ret_seid)
4015 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4021 * i40e_aq_add_tag - Add an S/E-tag
4022 * @hw: pointer to the hw struct
4023 * @direct_to_queue: should s-tag direct flow to a specific queue
4024 * @vsi_seid: VSI SEID to use this tag
4025 * @tag: value of the tag
4026 * @queue_num: queue number, only valid is direct_to_queue is true
4027 * @tags_used: return value, number of tags in use by this PF
4028 * @tags_free: return value, number of unallocated tags
4029 * @cmd_details: pointer to command details structure or NULL
4031 * This associates an S- or E-tag to a VSI in the switch complex. It returns
4032 * the number of tags allocated by the PF, and the number of unallocated
4035 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4036 u16 vsi_seid, u16 tag, u16 queue_num,
4037 u16 *tags_used, u16 *tags_free,
4038 struct i40e_asq_cmd_details *cmd_details)
4040 struct i40e_aq_desc desc;
4041 struct i40e_aqc_add_tag *cmd =
4042 (struct i40e_aqc_add_tag *)&desc.params.raw;
4043 struct i40e_aqc_add_remove_tag_completion *resp =
4044 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4045 enum i40e_status_code status;
4048 return I40E_ERR_PARAM;
4050 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4052 cmd->seid = CPU_TO_LE16(vsi_seid);
4053 cmd->tag = CPU_TO_LE16(tag);
4054 if (direct_to_queue) {
4055 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4056 cmd->queue_number = CPU_TO_LE16(queue_num);
4059 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4062 if (tags_used != NULL)
4063 *tags_used = LE16_TO_CPU(resp->tags_used);
4064 if (tags_free != NULL)
4065 *tags_free = LE16_TO_CPU(resp->tags_free);
4072 * i40e_aq_remove_tag - Remove an S- or E-tag
4073 * @hw: pointer to the hw struct
4074 * @vsi_seid: VSI SEID this tag is associated with
4075 * @tag: value of the S-tag to delete
4076 * @tags_used: return value, number of tags in use by this PF
4077 * @tags_free: return value, number of unallocated tags
4078 * @cmd_details: pointer to command details structure or NULL
4080 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
4081 * the number of tags allocated by the PF, and the number of unallocated
4084 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4085 u16 tag, u16 *tags_used, u16 *tags_free,
4086 struct i40e_asq_cmd_details *cmd_details)
4088 struct i40e_aq_desc desc;
4089 struct i40e_aqc_remove_tag *cmd =
4090 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4091 struct i40e_aqc_add_remove_tag_completion *resp =
4092 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4093 enum i40e_status_code status;
4096 return I40E_ERR_PARAM;
4098 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4100 cmd->seid = CPU_TO_LE16(vsi_seid);
4101 cmd->tag = CPU_TO_LE16(tag);
4103 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4106 if (tags_used != NULL)
4107 *tags_used = LE16_TO_CPU(resp->tags_used);
4108 if (tags_free != NULL)
4109 *tags_free = LE16_TO_CPU(resp->tags_free);
4116 * i40e_aq_add_mcast_etag - Add a multicast E-tag
4117 * @hw: pointer to the hw struct
4118 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4119 * @etag: value of E-tag to add
4120 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4121 * @buf: address of indirect buffer
4122 * @tags_used: return value, number of E-tags in use by this port
4123 * @tags_free: return value, number of unallocated M-tags
4124 * @cmd_details: pointer to command details structure or NULL
4126 * This associates a multicast E-tag to a port virtualizer. It will return
4127 * the number of tags allocated by the PF, and the number of unallocated
4130 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4131 * num_tags_in_buf long.
4133 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4134 u16 etag, u8 num_tags_in_buf, void *buf,
4135 u16 *tags_used, u16 *tags_free,
4136 struct i40e_asq_cmd_details *cmd_details)
4138 struct i40e_aq_desc desc;
4139 struct i40e_aqc_add_remove_mcast_etag *cmd =
4140 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4141 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4142 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4143 enum i40e_status_code status;
4144 u16 length = sizeof(u16) * num_tags_in_buf;
4146 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4147 return I40E_ERR_PARAM;
4149 i40e_fill_default_direct_cmd_desc(&desc,
4150 i40e_aqc_opc_add_multicast_etag);
4152 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4153 cmd->etag = CPU_TO_LE16(etag);
4154 cmd->num_unicast_etags = num_tags_in_buf;
4156 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4157 if (length > I40E_AQ_LARGE_BUF)
4158 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4160 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4163 if (tags_used != NULL)
4164 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4165 if (tags_free != NULL)
4166 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4173 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4174 * @hw: pointer to the hw struct
4175 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4176 * @etag: value of the E-tag to remove
4177 * @tags_used: return value, number of tags in use by this port
4178 * @tags_free: return value, number of unallocated tags
4179 * @cmd_details: pointer to command details structure or NULL
4181 * This deletes an E-tag from the port virtualizer. It will return
4182 * the number of tags allocated by the port, and the number of unallocated
4185 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4186 u16 etag, u16 *tags_used, u16 *tags_free,
4187 struct i40e_asq_cmd_details *cmd_details)
4189 struct i40e_aq_desc desc;
4190 struct i40e_aqc_add_remove_mcast_etag *cmd =
4191 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4192 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4193 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4194 enum i40e_status_code status;
4198 return I40E_ERR_PARAM;
4200 i40e_fill_default_direct_cmd_desc(&desc,
4201 i40e_aqc_opc_remove_multicast_etag);
4203 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4204 cmd->etag = CPU_TO_LE16(etag);
4206 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4209 if (tags_used != NULL)
4210 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4211 if (tags_free != NULL)
4212 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4219 * i40e_aq_update_tag - Update an S/E-tag
4220 * @hw: pointer to the hw struct
4221 * @vsi_seid: VSI SEID using this S-tag
4222 * @old_tag: old tag value
4223 * @new_tag: new tag value
4224 * @tags_used: return value, number of tags in use by this PF
4225 * @tags_free: return value, number of unallocated tags
4226 * @cmd_details: pointer to command details structure or NULL
4228 * This updates the value of the tag currently attached to this VSI
4229 * in the switch complex. It will return the number of tags allocated
4230 * by the PF, and the number of unallocated tags available.
4232 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4233 u16 old_tag, u16 new_tag, u16 *tags_used,
4235 struct i40e_asq_cmd_details *cmd_details)
4237 struct i40e_aq_desc desc;
4238 struct i40e_aqc_update_tag *cmd =
4239 (struct i40e_aqc_update_tag *)&desc.params.raw;
4240 struct i40e_aqc_update_tag_completion *resp =
4241 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4242 enum i40e_status_code status;
4245 return I40E_ERR_PARAM;
4247 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4249 cmd->seid = CPU_TO_LE16(vsi_seid);
4250 cmd->old_tag = CPU_TO_LE16(old_tag);
4251 cmd->new_tag = CPU_TO_LE16(new_tag);
4253 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4256 if (tags_used != NULL)
4257 *tags_used = LE16_TO_CPU(resp->tags_used);
4258 if (tags_free != NULL)
4259 *tags_free = LE16_TO_CPU(resp->tags_free);
4266 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4267 * @hw: pointer to the hw struct
4268 * @tcmap: TC map for request/release any ignore PFC condition
4269 * @request: request or release ignore PFC condition
4270 * @tcmap_ret: return TCs for which PFC is currently ignored
4271 * @cmd_details: pointer to command details structure or NULL
4273 * This sends out request/release to ignore PFC condition for a TC.
4274 * It will return the TCs for which PFC is currently ignored.
4276 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4277 bool request, u8 *tcmap_ret,
4278 struct i40e_asq_cmd_details *cmd_details)
4280 struct i40e_aq_desc desc;
4281 struct i40e_aqc_pfc_ignore *cmd_resp =
4282 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4283 enum i40e_status_code status;
4285 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4288 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4290 cmd_resp->tc_bitmap = tcmap;
4292 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4295 if (tcmap_ret != NULL)
4296 *tcmap_ret = cmd_resp->tc_bitmap;
4303 * i40e_aq_dcb_updated - DCB Updated Command
4304 * @hw: pointer to the hw struct
4305 * @cmd_details: pointer to command details structure or NULL
4307 * When LLDP is handled in PF this command is used by the PF
4308 * to notify EMP that a DCB setting is modified.
4309 * When LLDP is handled in EMP this command is used by the PF
4310 * to notify EMP whenever one of the following parameters get
4312 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4313 * - PCIRTT in PRTDCB_GENC.PCIRTT
4314 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4315 * EMP will return when the shared RPB settings have been
4316 * recomputed and modified. The retval field in the descriptor
4317 * will be set to 0 when RPB is modified.
4319 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4320 struct i40e_asq_cmd_details *cmd_details)
4322 struct i40e_aq_desc desc;
4323 enum i40e_status_code status;
4325 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4327 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4333 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4334 * @hw: pointer to the hw struct
4335 * @seid: defines the SEID of the switch for which the stats are requested
4336 * @vlan_id: the VLAN ID for which the statistics are requested
4337 * @stat_index: index of the statistics counters block assigned to this VLAN
4338 * @cmd_details: pointer to command details structure or NULL
4340 * XL710 supports 128 smonVlanStats counters.This command is used to
4341 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4344 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4345 u16 vlan_id, u16 *stat_index,
4346 struct i40e_asq_cmd_details *cmd_details)
4348 struct i40e_aq_desc desc;
4349 struct i40e_aqc_add_remove_statistics *cmd_resp =
4350 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4351 enum i40e_status_code status;
4353 if ((seid == 0) || (stat_index == NULL))
4354 return I40E_ERR_PARAM;
4356 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4358 cmd_resp->seid = CPU_TO_LE16(seid);
4359 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4361 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4363 if (!status && stat_index)
4364 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4370 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4371 * @hw: pointer to the hw struct
4372 * @seid: defines the SEID of the switch for which the stats are requested
4373 * @vlan_id: the VLAN ID for which the statistics are requested
4374 * @stat_index: index of the statistics counters block assigned to this VLAN
4375 * @cmd_details: pointer to command details structure or NULL
4377 * XL710 supports 128 smonVlanStats counters.This command is used to
4378 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4381 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4382 u16 vlan_id, u16 stat_index,
4383 struct i40e_asq_cmd_details *cmd_details)
4385 struct i40e_aq_desc desc;
4386 struct i40e_aqc_add_remove_statistics *cmd =
4387 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4388 enum i40e_status_code status;
4391 return I40E_ERR_PARAM;
4393 i40e_fill_default_direct_cmd_desc(&desc,
4394 i40e_aqc_opc_remove_statistics);
4396 cmd->seid = CPU_TO_LE16(seid);
4397 cmd->vlan = CPU_TO_LE16(vlan_id);
4398 cmd->stat_index = CPU_TO_LE16(stat_index);
4400 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4406 * i40e_aq_set_port_parameters - set physical port parameters.
4407 * @hw: pointer to the hw struct
4408 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4409 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4410 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4411 * @double_vlan: if set double VLAN is enabled
4412 * @cmd_details: pointer to command details structure or NULL
4414 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4415 u16 bad_frame_vsi, bool save_bad_pac,
4416 bool pad_short_pac, bool double_vlan,
4417 struct i40e_asq_cmd_details *cmd_details)
4419 struct i40e_aqc_set_port_parameters *cmd;
4420 enum i40e_status_code status;
4421 struct i40e_aq_desc desc;
4422 u16 command_flags = 0;
4424 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4426 i40e_fill_default_direct_cmd_desc(&desc,
4427 i40e_aqc_opc_set_port_parameters);
4429 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4431 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4433 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4435 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4436 cmd->command_flags = CPU_TO_LE16(command_flags);
4438 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4444 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
4445 * @hw: pointer to the hw struct
4446 * @seid: seid for the physical port/switching component/vsi
4447 * @buff: Indirect buffer to hold data parameters and response
4448 * @buff_size: Indirect buffer size
4449 * @opcode: Tx scheduler AQ command opcode
4450 * @cmd_details: pointer to command details structure or NULL
4452 * Generic command handler for Tx scheduler AQ commands
4454 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
4455 void *buff, u16 buff_size,
4456 enum i40e_admin_queue_opc opcode,
4457 struct i40e_asq_cmd_details *cmd_details)
4459 struct i40e_aq_desc desc;
4460 struct i40e_aqc_tx_sched_ind *cmd =
4461 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4462 enum i40e_status_code status;
4463 bool cmd_param_flag = false;
4466 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
4467 case i40e_aqc_opc_configure_vsi_tc_bw:
4468 case i40e_aqc_opc_enable_switching_comp_ets:
4469 case i40e_aqc_opc_modify_switching_comp_ets:
4470 case i40e_aqc_opc_disable_switching_comp_ets:
4471 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
4472 case i40e_aqc_opc_configure_switching_comp_bw_config:
4473 cmd_param_flag = true;
4475 case i40e_aqc_opc_query_vsi_bw_config:
4476 case i40e_aqc_opc_query_vsi_ets_sla_config:
4477 case i40e_aqc_opc_query_switching_comp_ets_config:
4478 case i40e_aqc_opc_query_port_ets_config:
4479 case i40e_aqc_opc_query_switching_comp_bw_config:
4480 cmd_param_flag = false;
4483 return I40E_ERR_PARAM;
4486 i40e_fill_default_direct_cmd_desc(&desc, opcode);
4488 /* Indirect command */
4489 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4491 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4492 if (buff_size > I40E_AQ_LARGE_BUF)
4493 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4495 desc.datalen = CPU_TO_LE16(buff_size);
4497 cmd->vsi_seid = CPU_TO_LE16(seid);
4499 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4505 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
4506 * @hw: pointer to the hw struct
4508 * @credit: BW limit credits (0 = disabled)
4509 * @max_credit: Max BW limit credits
4510 * @cmd_details: pointer to command details structure or NULL
4512 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
4513 u16 seid, u16 credit, u8 max_credit,
4514 struct i40e_asq_cmd_details *cmd_details)
4516 struct i40e_aq_desc desc;
4517 struct i40e_aqc_configure_vsi_bw_limit *cmd =
4518 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
4519 enum i40e_status_code status;
4521 i40e_fill_default_direct_cmd_desc(&desc,
4522 i40e_aqc_opc_configure_vsi_bw_limit);
4524 cmd->vsi_seid = CPU_TO_LE16(seid);
4525 cmd->credit = CPU_TO_LE16(credit);
4526 cmd->max_credit = max_credit;
4528 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4534 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
4535 * @hw: pointer to the hw struct
4536 * @seid: switching component seid
4537 * @credit: BW limit credits (0 = disabled)
4538 * @max_bw: Max BW limit credits
4539 * @cmd_details: pointer to command details structure or NULL
4541 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
4542 u16 seid, u16 credit, u8 max_bw,
4543 struct i40e_asq_cmd_details *cmd_details)
4545 struct i40e_aq_desc desc;
4546 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
4547 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
4548 enum i40e_status_code status;
4550 i40e_fill_default_direct_cmd_desc(&desc,
4551 i40e_aqc_opc_configure_switching_comp_bw_limit);
4553 cmd->seid = CPU_TO_LE16(seid);
4554 cmd->credit = CPU_TO_LE16(credit);
4555 cmd->max_bw = max_bw;
4557 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4563 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
4564 * @hw: pointer to the hw struct
4566 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4567 * @cmd_details: pointer to command details structure or NULL
4569 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
4571 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
4572 struct i40e_asq_cmd_details *cmd_details)
4574 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4575 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
4580 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
4581 * @hw: pointer to the hw struct
4583 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
4584 * @cmd_details: pointer to command details structure or NULL
4586 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
4588 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
4589 struct i40e_asq_cmd_details *cmd_details)
4591 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4592 i40e_aqc_opc_configure_vsi_tc_bw,
4597 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
4598 * @hw: pointer to the hw struct
4599 * @seid: seid of the switching component connected to Physical Port
4600 * @ets_data: Buffer holding ETS parameters
4601 * @cmd_details: pointer to command details structure or NULL
4603 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
4605 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
4606 enum i40e_admin_queue_opc opcode,
4607 struct i40e_asq_cmd_details *cmd_details)
4609 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
4610 sizeof(*ets_data), opcode, cmd_details);
4614 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
4615 * @hw: pointer to the hw struct
4616 * @seid: seid of the switching component
4617 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
4618 * @cmd_details: pointer to command details structure or NULL
4620 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
4622 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
4623 struct i40e_asq_cmd_details *cmd_details)
4625 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4626 i40e_aqc_opc_configure_switching_comp_bw_config,
4631 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
4632 * @hw: pointer to the hw struct
4633 * @seid: seid of the switching component
4634 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4635 * @cmd_details: pointer to command details structure or NULL
4637 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
4638 struct i40e_hw *hw, u16 seid,
4639 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
4640 struct i40e_asq_cmd_details *cmd_details)
4642 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4643 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
4648 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
4649 * @hw: pointer to the hw struct
4650 * @seid: seid of the VSI
4651 * @bw_data: Buffer to hold VSI BW configuration
4652 * @cmd_details: pointer to command details structure or NULL
4654 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
4656 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
4657 struct i40e_asq_cmd_details *cmd_details)
4659 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4660 i40e_aqc_opc_query_vsi_bw_config,
4665 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
4666 * @hw: pointer to the hw struct
4667 * @seid: seid of the VSI
4668 * @bw_data: Buffer to hold VSI BW configuration per TC
4669 * @cmd_details: pointer to command details structure or NULL
4671 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
4673 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
4674 struct i40e_asq_cmd_details *cmd_details)
4676 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4677 i40e_aqc_opc_query_vsi_ets_sla_config,
4682 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
4683 * @hw: pointer to the hw struct
4684 * @seid: seid of the switching component
4685 * @bw_data: Buffer to hold switching component's per TC BW config
4686 * @cmd_details: pointer to command details structure or NULL
4688 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
4690 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
4691 struct i40e_asq_cmd_details *cmd_details)
4693 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4694 i40e_aqc_opc_query_switching_comp_ets_config,
4699 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
4700 * @hw: pointer to the hw struct
4701 * @seid: seid of the VSI or switching component connected to Physical Port
4702 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
4703 * @cmd_details: pointer to command details structure or NULL
4705 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
4707 struct i40e_aqc_query_port_ets_config_resp *bw_data,
4708 struct i40e_asq_cmd_details *cmd_details)
4710 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4711 i40e_aqc_opc_query_port_ets_config,
4716 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
4717 * @hw: pointer to the hw struct
4718 * @seid: seid of the switching component
4719 * @bw_data: Buffer to hold switching component's BW configuration
4720 * @cmd_details: pointer to command details structure or NULL
4722 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
4724 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
4725 struct i40e_asq_cmd_details *cmd_details)
4727 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4728 i40e_aqc_opc_query_switching_comp_bw_config,
4733 * i40e_validate_filter_settings
4734 * @hw: pointer to the hardware structure
4735 * @settings: Filter control settings
4737 * Check and validate the filter control settings passed.
4738 * The function checks for the valid filter/context sizes being
4739 * passed for FCoE and PE.
4741 * Returns I40E_SUCCESS if the values passed are valid and within
4742 * range else returns an error.
4744 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
4745 struct i40e_filter_control_settings *settings)
4747 u32 fcoe_cntx_size, fcoe_filt_size;
4748 u32 pe_cntx_size, pe_filt_size;
4753 /* Validate FCoE settings passed */
4754 switch (settings->fcoe_filt_num) {
4755 case I40E_HASH_FILTER_SIZE_1K:
4756 case I40E_HASH_FILTER_SIZE_2K:
4757 case I40E_HASH_FILTER_SIZE_4K:
4758 case I40E_HASH_FILTER_SIZE_8K:
4759 case I40E_HASH_FILTER_SIZE_16K:
4760 case I40E_HASH_FILTER_SIZE_32K:
4761 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4762 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
4765 return I40E_ERR_PARAM;
4768 switch (settings->fcoe_cntx_num) {
4769 case I40E_DMA_CNTX_SIZE_512:
4770 case I40E_DMA_CNTX_SIZE_1K:
4771 case I40E_DMA_CNTX_SIZE_2K:
4772 case I40E_DMA_CNTX_SIZE_4K:
4773 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4774 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
4777 return I40E_ERR_PARAM;
4780 /* Validate PE settings passed */
4781 switch (settings->pe_filt_num) {
4782 case I40E_HASH_FILTER_SIZE_1K:
4783 case I40E_HASH_FILTER_SIZE_2K:
4784 case I40E_HASH_FILTER_SIZE_4K:
4785 case I40E_HASH_FILTER_SIZE_8K:
4786 case I40E_HASH_FILTER_SIZE_16K:
4787 case I40E_HASH_FILTER_SIZE_32K:
4788 case I40E_HASH_FILTER_SIZE_64K:
4789 case I40E_HASH_FILTER_SIZE_128K:
4790 case I40E_HASH_FILTER_SIZE_256K:
4791 case I40E_HASH_FILTER_SIZE_512K:
4792 case I40E_HASH_FILTER_SIZE_1M:
4793 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4794 pe_filt_size <<= (u32)settings->pe_filt_num;
4797 return I40E_ERR_PARAM;
4800 switch (settings->pe_cntx_num) {
4801 case I40E_DMA_CNTX_SIZE_512:
4802 case I40E_DMA_CNTX_SIZE_1K:
4803 case I40E_DMA_CNTX_SIZE_2K:
4804 case I40E_DMA_CNTX_SIZE_4K:
4805 case I40E_DMA_CNTX_SIZE_8K:
4806 case I40E_DMA_CNTX_SIZE_16K:
4807 case I40E_DMA_CNTX_SIZE_32K:
4808 case I40E_DMA_CNTX_SIZE_64K:
4809 case I40E_DMA_CNTX_SIZE_128K:
4810 case I40E_DMA_CNTX_SIZE_256K:
4811 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4812 pe_cntx_size <<= (u32)settings->pe_cntx_num;
4815 return I40E_ERR_PARAM;
4818 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
4819 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
4820 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
4821 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
4822 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
4823 return I40E_ERR_INVALID_SIZE;
4825 return I40E_SUCCESS;
4829 * i40e_set_filter_control
4830 * @hw: pointer to the hardware structure
4831 * @settings: Filter control settings
4833 * Set the Queue Filters for PE/FCoE and enable filters required
4834 * for a single PF. It is expected that these settings are programmed
4835 * at the driver initialization time.
4837 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
4838 struct i40e_filter_control_settings *settings)
4840 enum i40e_status_code ret = I40E_SUCCESS;
4841 u32 hash_lut_size = 0;
4845 return I40E_ERR_PARAM;
4847 /* Validate the input settings */
4848 ret = i40e_validate_filter_settings(hw, settings);
4852 /* Read the PF Queue Filter control register */
4853 val = rd32(hw, I40E_PFQF_CTL_0);
4855 /* Program required PE hash buckets for the PF */
4856 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
4857 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
4858 I40E_PFQF_CTL_0_PEHSIZE_MASK;
4859 /* Program required PE contexts for the PF */
4860 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
4861 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
4862 I40E_PFQF_CTL_0_PEDSIZE_MASK;
4864 /* Program required FCoE hash buckets for the PF */
4865 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4866 val |= ((u32)settings->fcoe_filt_num <<
4867 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
4868 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4869 /* Program required FCoE DDP contexts for the PF */
4870 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4871 val |= ((u32)settings->fcoe_cntx_num <<
4872 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
4873 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4875 /* Program Hash LUT size for the PF */
4876 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4877 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
4879 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
4880 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4882 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
4883 if (settings->enable_fdir)
4884 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
4885 if (settings->enable_ethtype)
4886 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
4887 if (settings->enable_macvlan)
4888 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
4890 wr32(hw, I40E_PFQF_CTL_0, val);
4892 return I40E_SUCCESS;
4896 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
4897 * @hw: pointer to the hw struct
4898 * @mac_addr: MAC address to use in the filter
4899 * @ethtype: Ethertype to use in the filter
4900 * @flags: Flags that needs to be applied to the filter
4901 * @vsi_seid: seid of the control VSI
4902 * @queue: VSI queue number to send the packet to
4903 * @is_add: Add control packet filter if True else remove
4904 * @stats: Structure to hold information on control filter counts
4905 * @cmd_details: pointer to command details structure or NULL
4907 * This command will Add or Remove control packet filter for a control VSI.
4908 * In return it will update the total number of perfect filter count in
4911 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
4912 u8 *mac_addr, u16 ethtype, u16 flags,
4913 u16 vsi_seid, u16 queue, bool is_add,
4914 struct i40e_control_filter_stats *stats,
4915 struct i40e_asq_cmd_details *cmd_details)
4917 struct i40e_aq_desc desc;
4918 struct i40e_aqc_add_remove_control_packet_filter *cmd =
4919 (struct i40e_aqc_add_remove_control_packet_filter *)
4921 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
4922 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
4924 enum i40e_status_code status;
4927 return I40E_ERR_PARAM;
4930 i40e_fill_default_direct_cmd_desc(&desc,
4931 i40e_aqc_opc_add_control_packet_filter);
4932 cmd->queue = CPU_TO_LE16(queue);
4934 i40e_fill_default_direct_cmd_desc(&desc,
4935 i40e_aqc_opc_remove_control_packet_filter);
4939 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
4940 I40E_NONDMA_TO_NONDMA);
4942 cmd->etype = CPU_TO_LE16(ethtype);
4943 cmd->flags = CPU_TO_LE16(flags);
4944 cmd->seid = CPU_TO_LE16(vsi_seid);
4946 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4948 if (!status && stats) {
4949 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
4950 stats->etype_used = LE16_TO_CPU(resp->etype_used);
4951 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
4952 stats->etype_free = LE16_TO_CPU(resp->etype_free);
4959 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
4960 * @hw: pointer to the hw struct
4961 * @seid: VSI seid to add ethertype filter from
4963 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
4964 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
4967 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
4968 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
4969 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
4970 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
4971 enum i40e_status_code status;
4973 status = i40e_aq_add_rem_control_packet_filter(hw, 0, ethtype, flag,
4974 seid, 0, true, NULL,
4977 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
4981 * i40e_aq_add_cloud_filters
4982 * @hw: pointer to the hardware structure
4983 * @seid: VSI seid to add cloud filters from
4984 * @filters: Buffer which contains the filters to be added
4985 * @filter_count: number of filters contained in the buffer
4987 * Set the cloud filters for a given VSI. The contents of the
4988 * i40e_aqc_add_remove_cloud_filters_element_data are filled
4989 * in by the caller of the function.
4992 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
4994 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
4997 struct i40e_aq_desc desc;
4998 struct i40e_aqc_add_remove_cloud_filters *cmd =
4999 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5001 enum i40e_status_code status;
5003 i40e_fill_default_direct_cmd_desc(&desc,
5004 i40e_aqc_opc_add_cloud_filters);
5006 buff_len = filter_count * sizeof(*filters);
5007 desc.datalen = CPU_TO_LE16(buff_len);
5008 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5009 cmd->num_filters = filter_count;
5010 cmd->seid = CPU_TO_LE16(seid);
5012 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5018 * i40e_aq_remove_cloud_filters
5019 * @hw: pointer to the hardware structure
5020 * @seid: VSI seid to remove cloud filters from
5021 * @filters: Buffer which contains the filters to be removed
5022 * @filter_count: number of filters contained in the buffer
5024 * Remove the cloud filters for a given VSI. The contents of the
5025 * i40e_aqc_add_remove_cloud_filters_element_data are filled
5026 * in by the caller of the function.
5029 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5031 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5034 struct i40e_aq_desc desc;
5035 struct i40e_aqc_add_remove_cloud_filters *cmd =
5036 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5037 enum i40e_status_code status;
5040 i40e_fill_default_direct_cmd_desc(&desc,
5041 i40e_aqc_opc_remove_cloud_filters);
5043 buff_len = filter_count * sizeof(*filters);
5044 desc.datalen = CPU_TO_LE16(buff_len);
5045 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5046 cmd->num_filters = filter_count;
5047 cmd->seid = CPU_TO_LE16(seid);
5049 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5055 * i40e_aq_alternate_write
5056 * @hw: pointer to the hardware structure
5057 * @reg_addr0: address of first dword to be read
5058 * @reg_val0: value to be written under 'reg_addr0'
5059 * @reg_addr1: address of second dword to be read
5060 * @reg_val1: value to be written under 'reg_addr1'
5062 * Write one or two dwords to alternate structure. Fields are indicated
5063 * by 'reg_addr0' and 'reg_addr1' register numbers.
5066 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5067 u32 reg_addr0, u32 reg_val0,
5068 u32 reg_addr1, u32 reg_val1)
5070 struct i40e_aq_desc desc;
5071 struct i40e_aqc_alternate_write *cmd_resp =
5072 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5073 enum i40e_status_code status;
5075 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5076 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5077 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5078 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5079 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5081 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5087 * i40e_aq_alternate_write_indirect
5088 * @hw: pointer to the hardware structure
5089 * @addr: address of a first register to be modified
5090 * @dw_count: number of alternate structure fields to write
5091 * @buffer: pointer to the command buffer
5093 * Write 'dw_count' dwords from 'buffer' to alternate structure
5094 * starting at 'addr'.
5097 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5098 u32 addr, u32 dw_count, void *buffer)
5100 struct i40e_aq_desc desc;
5101 struct i40e_aqc_alternate_ind_write *cmd_resp =
5102 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5103 enum i40e_status_code status;
5106 return I40E_ERR_PARAM;
5108 /* Indirect command */
5109 i40e_fill_default_direct_cmd_desc(&desc,
5110 i40e_aqc_opc_alternate_write_indirect);
5112 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5113 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5114 if (dw_count > (I40E_AQ_LARGE_BUF/4))
5115 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5117 cmd_resp->address = CPU_TO_LE32(addr);
5118 cmd_resp->length = CPU_TO_LE32(dw_count);
5120 status = i40e_asq_send_command(hw, &desc, buffer,
5121 I40E_LO_DWORD(4*dw_count), NULL);
5127 * i40e_aq_alternate_read
5128 * @hw: pointer to the hardware structure
5129 * @reg_addr0: address of first dword to be read
5130 * @reg_val0: pointer for data read from 'reg_addr0'
5131 * @reg_addr1: address of second dword to be read
5132 * @reg_val1: pointer for data read from 'reg_addr1'
5134 * Read one or two dwords from alternate structure. Fields are indicated
5135 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5136 * is not passed then only register at 'reg_addr0' is read.
5139 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5140 u32 reg_addr0, u32 *reg_val0,
5141 u32 reg_addr1, u32 *reg_val1)
5143 struct i40e_aq_desc desc;
5144 struct i40e_aqc_alternate_write *cmd_resp =
5145 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5146 enum i40e_status_code status;
5148 if (reg_val0 == NULL)
5149 return I40E_ERR_PARAM;
5151 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5152 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5153 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5155 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5157 if (status == I40E_SUCCESS) {
5158 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5160 if (reg_val1 != NULL)
5161 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5168 * i40e_aq_alternate_read_indirect
5169 * @hw: pointer to the hardware structure
5170 * @addr: address of the alternate structure field
5171 * @dw_count: number of alternate structure fields to read
5172 * @buffer: pointer to the command buffer
5174 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5175 * place them in 'buffer'. The buffer should be allocated by caller.
5178 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5179 u32 addr, u32 dw_count, void *buffer)
5181 struct i40e_aq_desc desc;
5182 struct i40e_aqc_alternate_ind_write *cmd_resp =
5183 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5184 enum i40e_status_code status;
5187 return I40E_ERR_PARAM;
5189 /* Indirect command */
5190 i40e_fill_default_direct_cmd_desc(&desc,
5191 i40e_aqc_opc_alternate_read_indirect);
5193 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5194 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5195 if (dw_count > (I40E_AQ_LARGE_BUF/4))
5196 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5198 cmd_resp->address = CPU_TO_LE32(addr);
5199 cmd_resp->length = CPU_TO_LE32(dw_count);
5201 status = i40e_asq_send_command(hw, &desc, buffer,
5202 I40E_LO_DWORD(4*dw_count), NULL);
5208 * i40e_aq_alternate_clear
5209 * @hw: pointer to the HW structure.
5211 * Clear the alternate structures of the port from which the function
5215 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5217 struct i40e_aq_desc desc;
5218 enum i40e_status_code status;
5220 i40e_fill_default_direct_cmd_desc(&desc,
5221 i40e_aqc_opc_alternate_clear_port);
5223 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5229 * i40e_aq_alternate_write_done
5230 * @hw: pointer to the HW structure.
5231 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
5232 * @reset_needed: indicates the SW should trigger GLOBAL reset
5234 * Indicates to the FW that alternate structures have been changed.
5237 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
5238 u8 bios_mode, bool *reset_needed)
5240 struct i40e_aq_desc desc;
5241 struct i40e_aqc_alternate_write_done *cmd =
5242 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5243 enum i40e_status_code status;
5245 if (reset_needed == NULL)
5246 return I40E_ERR_PARAM;
5248 i40e_fill_default_direct_cmd_desc(&desc,
5249 i40e_aqc_opc_alternate_write_done);
5251 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
5253 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5254 if (!status && reset_needed)
5255 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
5256 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
5262 * i40e_aq_set_oem_mode
5263 * @hw: pointer to the HW structure.
5264 * @oem_mode: the OEM mode to be used
5266 * Sets the device to a specific operating mode. Currently the only supported
5267 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
5270 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
5273 struct i40e_aq_desc desc;
5274 struct i40e_aqc_alternate_write_done *cmd =
5275 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5276 enum i40e_status_code status;
5278 i40e_fill_default_direct_cmd_desc(&desc,
5279 i40e_aqc_opc_alternate_set_mode);
5281 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
5283 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5289 * i40e_aq_resume_port_tx
5290 * @hw: pointer to the hardware structure
5291 * @cmd_details: pointer to command details structure or NULL
5293 * Resume port's Tx traffic
5295 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
5296 struct i40e_asq_cmd_details *cmd_details)
5298 struct i40e_aq_desc desc;
5299 enum i40e_status_code status;
5301 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
5303 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5309 * i40e_set_pci_config_data - store PCI bus info
5310 * @hw: pointer to hardware structure
5311 * @link_status: the link status word from PCI config space
5313 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
5315 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
5317 hw->bus.type = i40e_bus_type_pci_express;
5319 switch (link_status & I40E_PCI_LINK_WIDTH) {
5320 case I40E_PCI_LINK_WIDTH_1:
5321 hw->bus.width = i40e_bus_width_pcie_x1;
5323 case I40E_PCI_LINK_WIDTH_2:
5324 hw->bus.width = i40e_bus_width_pcie_x2;
5326 case I40E_PCI_LINK_WIDTH_4:
5327 hw->bus.width = i40e_bus_width_pcie_x4;
5329 case I40E_PCI_LINK_WIDTH_8:
5330 hw->bus.width = i40e_bus_width_pcie_x8;
5333 hw->bus.width = i40e_bus_width_unknown;
5337 switch (link_status & I40E_PCI_LINK_SPEED) {
5338 case I40E_PCI_LINK_SPEED_2500:
5339 hw->bus.speed = i40e_bus_speed_2500;
5341 case I40E_PCI_LINK_SPEED_5000:
5342 hw->bus.speed = i40e_bus_speed_5000;
5344 case I40E_PCI_LINK_SPEED_8000:
5345 hw->bus.speed = i40e_bus_speed_8000;
5348 hw->bus.speed = i40e_bus_speed_unknown;
5354 * i40e_aq_debug_dump
5355 * @hw: pointer to the hardware structure
5356 * @cluster_id: specific cluster to dump
5357 * @table_id: table id within cluster
5358 * @start_index: index of line in the block to read
5359 * @buff_size: dump buffer size
5360 * @buff: dump buffer
5361 * @ret_buff_size: actual buffer size returned
5362 * @ret_next_table: next block to read
5363 * @ret_next_index: next index to read
5365 * Dump internal FW/HW data for debug purposes.
5368 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
5369 u8 table_id, u32 start_index, u16 buff_size,
5370 void *buff, u16 *ret_buff_size,
5371 u8 *ret_next_table, u32 *ret_next_index,
5372 struct i40e_asq_cmd_details *cmd_details)
5374 struct i40e_aq_desc desc;
5375 struct i40e_aqc_debug_dump_internals *cmd =
5376 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5377 struct i40e_aqc_debug_dump_internals *resp =
5378 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5379 enum i40e_status_code status;
5381 if (buff_size == 0 || !buff)
5382 return I40E_ERR_PARAM;
5384 i40e_fill_default_direct_cmd_desc(&desc,
5385 i40e_aqc_opc_debug_dump_internals);
5386 /* Indirect Command */
5387 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5388 if (buff_size > I40E_AQ_LARGE_BUF)
5389 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5391 cmd->cluster_id = cluster_id;
5392 cmd->table_id = table_id;
5393 cmd->idx = CPU_TO_LE32(start_index);
5395 desc.datalen = CPU_TO_LE16(buff_size);
5397 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5399 if (ret_buff_size != NULL)
5400 *ret_buff_size = LE16_TO_CPU(desc.datalen);
5401 if (ret_next_table != NULL)
5402 *ret_next_table = resp->table_id;
5403 if (ret_next_index != NULL)
5404 *ret_next_index = LE32_TO_CPU(resp->idx);
5411 * i40e_read_bw_from_alt_ram
5412 * @hw: pointer to the hardware structure
5413 * @max_bw: pointer for max_bw read
5414 * @min_bw: pointer for min_bw read
5415 * @min_valid: pointer for bool that is true if min_bw is a valid value
5416 * @max_valid: pointer for bool that is true if max_bw is a valid value
5418 * Read bw from the alternate ram for the given pf
5420 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
5421 u32 *max_bw, u32 *min_bw,
5422 bool *min_valid, bool *max_valid)
5424 enum i40e_status_code status;
5425 u32 max_bw_addr, min_bw_addr;
5427 /* Calculate the address of the min/max bw registers */
5428 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5429 I40E_ALT_STRUCT_MAX_BW_OFFSET +
5430 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
5431 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5432 I40E_ALT_STRUCT_MIN_BW_OFFSET +
5433 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
5435 /* Read the bandwidths from alt ram */
5436 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
5437 min_bw_addr, min_bw);
5439 if (*min_bw & I40E_ALT_BW_VALID_MASK)
5444 if (*max_bw & I40E_ALT_BW_VALID_MASK)
5453 * i40e_aq_configure_partition_bw
5454 * @hw: pointer to the hardware structure
5455 * @bw_data: Buffer holding valid pfs and bw limits
5456 * @cmd_details: pointer to command details
5458 * Configure partitions guaranteed/max bw
5460 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
5461 struct i40e_aqc_configure_partition_bw_data *bw_data,
5462 struct i40e_asq_cmd_details *cmd_details)
5464 enum i40e_status_code status;
5465 struct i40e_aq_desc desc;
5466 u16 bwd_size = sizeof(*bw_data);
5468 i40e_fill_default_direct_cmd_desc(&desc,
5469 i40e_aqc_opc_configure_partition_bw);
5471 /* Indirect command */
5472 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5473 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5475 if (bwd_size > I40E_AQ_LARGE_BUF)
5476 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5478 desc.datalen = CPU_TO_LE16(bwd_size);
5480 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
5484 #endif /* PF_DRIVER */
5488 * i40e_aq_send_msg_to_pf
5489 * @hw: pointer to the hardware structure
5490 * @v_opcode: opcodes for VF-PF communication
5491 * @v_retval: return error code
5492 * @msg: pointer to the msg buffer
5493 * @msglen: msg length
5494 * @cmd_details: pointer to command details
5496 * Send message to PF driver using admin queue. By default, this message
5497 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
5498 * completion before returning.
5500 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
5501 enum i40e_virtchnl_ops v_opcode,
5502 enum i40e_status_code v_retval,
5503 u8 *msg, u16 msglen,
5504 struct i40e_asq_cmd_details *cmd_details)
5506 struct i40e_aq_desc desc;
5507 struct i40e_asq_cmd_details details;
5508 enum i40e_status_code status;
5510 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
5511 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
5512 desc.cookie_high = CPU_TO_LE32(v_opcode);
5513 desc.cookie_low = CPU_TO_LE32(v_retval);
5515 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
5516 | I40E_AQ_FLAG_RD));
5517 if (msglen > I40E_AQ_LARGE_BUF)
5518 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5519 desc.datalen = CPU_TO_LE16(msglen);
5522 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
5523 details.async = true;
5524 cmd_details = &details;
5526 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
5527 msglen, cmd_details);
5532 * i40e_vf_parse_hw_config
5533 * @hw: pointer to the hardware structure
5534 * @msg: pointer to the virtual channel VF resource structure
5536 * Given a VF resource message from the PF, populate the hw struct
5537 * with appropriate information.
5539 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
5540 struct i40e_virtchnl_vf_resource *msg)
5542 struct i40e_virtchnl_vsi_resource *vsi_res;
5545 vsi_res = &msg->vsi_res[0];
5547 hw->dev_caps.num_vsis = msg->num_vsis;
5548 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
5549 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
5550 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
5551 hw->dev_caps.dcb = msg->vf_offload_flags &
5552 I40E_VIRTCHNL_VF_OFFLOAD_L2;
5553 hw->dev_caps.fcoe = (msg->vf_offload_flags &
5554 I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
5555 hw->dev_caps.iwarp = (msg->vf_offload_flags &
5556 I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
5557 for (i = 0; i < msg->num_vsis; i++) {
5558 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
5559 i40e_memcpy(hw->mac.perm_addr,
5560 vsi_res->default_mac_addr,
5561 I40E_ETH_LENGTH_OF_ADDRESS,
5562 I40E_NONDMA_TO_NONDMA);
5563 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
5564 I40E_ETH_LENGTH_OF_ADDRESS,
5565 I40E_NONDMA_TO_NONDMA);
5573 * @hw: pointer to the hardware structure
5575 * Send a VF_RESET message to the PF. Does not wait for response from PF
5576 * as none will be forthcoming. Immediately after calling this function,
5577 * the admin queue should be shut down and (optionally) reinitialized.
5579 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
5581 return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
5582 I40E_SUCCESS, NULL, 0, NULL);
5584 #endif /* VF_DRIVER */