drivers/net/i40e/base/i40e_common.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "i40e_type.h"
  35 #include "i40e_adminq.h"
  36 #include "i40e_prototype.h"
  37 #include "virtchnl.h"
  38
  39
  40 /**
  41  * i40e_set_mac_type - Sets MAC type
  42  * @hw: pointer to the HW structure
  43  *
  44  * This function sets the mac type of the adapter based on the
  45  * vendor ID and device ID stored in the hw structure.
  46  **/
  47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  49 #else
  50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  51 #endif
  52 {
  53         enum i40e_status_code status = I40E_SUCCESS;
  54
  55         DEBUGFUNC("i40e_set_mac_type\n");
  56
  57         if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
  58                 switch (hw->device_id) {
  59                 case I40E_DEV_ID_SFP_XL710:
  60                 case I40E_DEV_ID_QEMU:
  61                 case I40E_DEV_ID_KX_B:
  62                 case I40E_DEV_ID_KX_C:
  63                 case I40E_DEV_ID_QSFP_A:
  64                 case I40E_DEV_ID_QSFP_B:
  65                 case I40E_DEV_ID_QSFP_C:
  66                 case I40E_DEV_ID_10G_BASE_T:
  67                 case I40E_DEV_ID_10G_BASE_T4:
  68                 case I40E_DEV_ID_20G_KR2:
  69                 case I40E_DEV_ID_20G_KR2_A:
  70                 case I40E_DEV_ID_25G_B:
  71                 case I40E_DEV_ID_25G_SFP28:
  72                         hw->mac.type = I40E_MAC_XL710;
  73                         break;
  74 #ifdef X722_A0_SUPPORT
  75                 case I40E_DEV_ID_X722_A0:
  76 #endif
  77                 case I40E_DEV_ID_KX_X722:
  78                 case I40E_DEV_ID_QSFP_X722:
  79                 case I40E_DEV_ID_SFP_X722:
  80                 case I40E_DEV_ID_1G_BASE_T_X722:
  81                 case I40E_DEV_ID_10G_BASE_T_X722:
  82                 case I40E_DEV_ID_SFP_I_X722:
  83                         hw->mac.type = I40E_MAC_X722;
  84                         break;
  85 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  86                 case I40E_DEV_ID_X722_VF:
  87 #ifdef X722_A0_SUPPORT
  88                 case I40E_DEV_ID_X722_A0_VF:
  89 #endif
  90                         hw->mac.type = I40E_MAC_X722_VF;
  91                         break;
  92 #endif /* INTEGRATED_VF || VF_DRIVER */
  93 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  94                 case I40E_DEV_ID_VF:
  95                 case I40E_DEV_ID_VF_HV:
  96                 case I40E_DEV_ID_ADAPTIVE_VF:
  97                         hw->mac.type = I40E_MAC_VF;
  98                         break;
  99 #endif
 100                 default:
 101                         hw->mac.type = I40E_MAC_GENERIC;
 102                         break;
 103                 }
 104         } else {
 105                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
 106         }
 107
 108         DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
 109                   hw->mac.type, status);
 110         return status;
 111 }
 112
 113 /**
 114  * i40e_aq_str - convert AQ err code to a string
 115  * @hw: pointer to the HW structure
 116  * @aq_err: the AQ error code to convert
 117  **/
 118 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
 119 {
 120         switch (aq_err) {
 121         case I40E_AQ_RC_OK:
 122                 return "OK";
 123         case I40E_AQ_RC_EPERM:
 124                 return "I40E_AQ_RC_EPERM";
 125         case I40E_AQ_RC_ENOENT:
 126                 return "I40E_AQ_RC_ENOENT";
 127         case I40E_AQ_RC_ESRCH:
 128                 return "I40E_AQ_RC_ESRCH";
 129         case I40E_AQ_RC_EINTR:
 130                 return "I40E_AQ_RC_EINTR";
 131         case I40E_AQ_RC_EIO:
 132                 return "I40E_AQ_RC_EIO";
 133         case I40E_AQ_RC_ENXIO:
 134                 return "I40E_AQ_RC_ENXIO";
 135         case I40E_AQ_RC_E2BIG:
 136                 return "I40E_AQ_RC_E2BIG";
 137         case I40E_AQ_RC_EAGAIN:
 138                 return "I40E_AQ_RC_EAGAIN";
 139         case I40E_AQ_RC_ENOMEM:
 140                 return "I40E_AQ_RC_ENOMEM";
 141         case I40E_AQ_RC_EACCES:
 142                 return "I40E_AQ_RC_EACCES";
 143         case I40E_AQ_RC_EFAULT:
 144                 return "I40E_AQ_RC_EFAULT";
 145         case I40E_AQ_RC_EBUSY:
 146                 return "I40E_AQ_RC_EBUSY";
 147         case I40E_AQ_RC_EEXIST:
 148                 return "I40E_AQ_RC_EEXIST";
 149         case I40E_AQ_RC_EINVAL:
 150                 return "I40E_AQ_RC_EINVAL";
 151         case I40E_AQ_RC_ENOTTY:
 152                 return "I40E_AQ_RC_ENOTTY";
 153         case I40E_AQ_RC_ENOSPC:
 154                 return "I40E_AQ_RC_ENOSPC";
 155         case I40E_AQ_RC_ENOSYS:
 156                 return "I40E_AQ_RC_ENOSYS";
 157         case I40E_AQ_RC_ERANGE:
 158                 return "I40E_AQ_RC_ERANGE";
 159         case I40E_AQ_RC_EFLUSHED:
 160                 return "I40E_AQ_RC_EFLUSHED";
 161         case I40E_AQ_RC_BAD_ADDR:
 162                 return "I40E_AQ_RC_BAD_ADDR";
 163         case I40E_AQ_RC_EMODE:
 164                 return "I40E_AQ_RC_EMODE";
 165         case I40E_AQ_RC_EFBIG:
 166                 return "I40E_AQ_RC_EFBIG";
 167         }
 168
 169         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 170         return hw->err_str;
 171 }
 172
 173 /**
 174  * i40e_stat_str - convert status err code to a string
 175  * @hw: pointer to the HW structure
 176  * @stat_err: the status error code to convert
 177  **/
 178 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
 179 {
 180         switch (stat_err) {
 181         case I40E_SUCCESS:
 182                 return "OK";
 183         case I40E_ERR_NVM:
 184                 return "I40E_ERR_NVM";
 185         case I40E_ERR_NVM_CHECKSUM:
 186                 return "I40E_ERR_NVM_CHECKSUM";
 187         case I40E_ERR_PHY:
 188                 return "I40E_ERR_PHY";
 189         case I40E_ERR_CONFIG:
 190                 return "I40E_ERR_CONFIG";
 191         case I40E_ERR_PARAM:
 192                 return "I40E_ERR_PARAM";
 193         case I40E_ERR_MAC_TYPE:
 194                 return "I40E_ERR_MAC_TYPE";
 195         case I40E_ERR_UNKNOWN_PHY:
 196                 return "I40E_ERR_UNKNOWN_PHY";
 197         case I40E_ERR_LINK_SETUP:
 198                 return "I40E_ERR_LINK_SETUP";
 199         case I40E_ERR_ADAPTER_STOPPED:
 200                 return "I40E_ERR_ADAPTER_STOPPED";
 201         case I40E_ERR_INVALID_MAC_ADDR:
 202                 return "I40E_ERR_INVALID_MAC_ADDR";
 203         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 204                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 205         case I40E_ERR_MASTER_REQUESTS_PENDING:
 206                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 207         case I40E_ERR_INVALID_LINK_SETTINGS:
 208                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 209         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 210                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 211         case I40E_ERR_RESET_FAILED:
 212                 return "I40E_ERR_RESET_FAILED";
 213         case I40E_ERR_SWFW_SYNC:
 214                 return "I40E_ERR_SWFW_SYNC";
 215         case I40E_ERR_NO_AVAILABLE_VSI:
 216                 return "I40E_ERR_NO_AVAILABLE_VSI";
 217         case I40E_ERR_NO_MEMORY:
 218                 return "I40E_ERR_NO_MEMORY";
 219         case I40E_ERR_BAD_PTR:
 220                 return "I40E_ERR_BAD_PTR";
 221         case I40E_ERR_RING_FULL:
 222                 return "I40E_ERR_RING_FULL";
 223         case I40E_ERR_INVALID_PD_ID:
 224                 return "I40E_ERR_INVALID_PD_ID";
 225         case I40E_ERR_INVALID_QP_ID:
 226                 return "I40E_ERR_INVALID_QP_ID";
 227         case I40E_ERR_INVALID_CQ_ID:
 228                 return "I40E_ERR_INVALID_CQ_ID";
 229         case I40E_ERR_INVALID_CEQ_ID:
 230                 return "I40E_ERR_INVALID_CEQ_ID";
 231         case I40E_ERR_INVALID_AEQ_ID:
 232                 return "I40E_ERR_INVALID_AEQ_ID";
 233         case I40E_ERR_INVALID_SIZE:
 234                 return "I40E_ERR_INVALID_SIZE";
 235         case I40E_ERR_INVALID_ARP_INDEX:
 236                 return "I40E_ERR_INVALID_ARP_INDEX";
 237         case I40E_ERR_INVALID_FPM_FUNC_ID:
 238                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 239         case I40E_ERR_QP_INVALID_MSG_SIZE:
 240                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 241         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 242                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 243         case I40E_ERR_INVALID_FRAG_COUNT:
 244                 return "I40E_ERR_INVALID_FRAG_COUNT";
 245         case I40E_ERR_QUEUE_EMPTY:
 246                 return "I40E_ERR_QUEUE_EMPTY";
 247         case I40E_ERR_INVALID_ALIGNMENT:
 248                 return "I40E_ERR_INVALID_ALIGNMENT";
 249         case I40E_ERR_FLUSHED_QUEUE:
 250                 return "I40E_ERR_FLUSHED_QUEUE";
 251         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 252                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 253         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 254                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 255         case I40E_ERR_TIMEOUT:
 256                 return "I40E_ERR_TIMEOUT";
 257         case I40E_ERR_OPCODE_MISMATCH:
 258                 return "I40E_ERR_OPCODE_MISMATCH";
 259         case I40E_ERR_CQP_COMPL_ERROR:
 260                 return "I40E_ERR_CQP_COMPL_ERROR";
 261         case I40E_ERR_INVALID_VF_ID:
 262                 return "I40E_ERR_INVALID_VF_ID";
 263         case I40E_ERR_INVALID_HMCFN_ID:
 264                 return "I40E_ERR_INVALID_HMCFN_ID";
 265         case I40E_ERR_BACKING_PAGE_ERROR:
 266                 return "I40E_ERR_BACKING_PAGE_ERROR";
 267         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 268                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 269         case I40E_ERR_INVALID_PBLE_INDEX:
 270                 return "I40E_ERR_INVALID_PBLE_INDEX";
 271         case I40E_ERR_INVALID_SD_INDEX:
 272                 return "I40E_ERR_INVALID_SD_INDEX";
 273         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 274                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 275         case I40E_ERR_INVALID_SD_TYPE:
 276                 return "I40E_ERR_INVALID_SD_TYPE";
 277         case I40E_ERR_MEMCPY_FAILED:
 278                 return "I40E_ERR_MEMCPY_FAILED";
 279         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 280                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 281         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 282                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 283         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 284                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 285         case I40E_ERR_SRQ_ENABLED:
 286                 return "I40E_ERR_SRQ_ENABLED";
 287         case I40E_ERR_ADMIN_QUEUE_ERROR:
 288                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 289         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 290                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 291         case I40E_ERR_BUF_TOO_SHORT:
 292                 return "I40E_ERR_BUF_TOO_SHORT";
 293         case I40E_ERR_ADMIN_QUEUE_FULL:
 294                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 295         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 296                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 297         case I40E_ERR_BAD_IWARP_CQE:
 298                 return "I40E_ERR_BAD_IWARP_CQE";
 299         case I40E_ERR_NVM_BLANK_MODE:
 300                 return "I40E_ERR_NVM_BLANK_MODE";
 301         case I40E_ERR_NOT_IMPLEMENTED:
 302                 return "I40E_ERR_NOT_IMPLEMENTED";
 303         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 304                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 305         case I40E_ERR_DIAG_TEST_FAILED:
 306                 return "I40E_ERR_DIAG_TEST_FAILED";
 307         case I40E_ERR_NOT_READY:
 308                 return "I40E_ERR_NOT_READY";
 309         case I40E_NOT_SUPPORTED:
 310                 return "I40E_NOT_SUPPORTED";
 311         case I40E_ERR_FIRMWARE_API_VERSION:
 312                 return "I40E_ERR_FIRMWARE_API_VERSION";
 313         }
 314
 315         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 316         return hw->err_str;
 317 }
 318
 319 /**
 320  * i40e_debug_aq
 321  * @hw: debug mask related to admin queue
 322  * @mask: debug mask
 323  * @desc: pointer to admin queue descriptor
 324  * @buffer: pointer to command buffer
 325  * @buf_len: max length of buffer
 326  *
 327  * Dumps debug log about adminq command with descriptor contents.
 328  **/
 329 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 330                    void *buffer, u16 buf_len)
 331 {
 332         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 333         u8 *buf = (u8 *)buffer;
 334         u16 len;
 335         u16 i = 0;
 336
 337         if ((!(mask & hw->debug_mask)) || (desc == NULL))
 338                 return;
 339
 340         len = LE16_TO_CPU(aq_desc->datalen);
 341
 342         i40e_debug(hw, mask,
 343                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 344                    LE16_TO_CPU(aq_desc->opcode),
 345                    LE16_TO_CPU(aq_desc->flags),
 346                    LE16_TO_CPU(aq_desc->datalen),
 347                    LE16_TO_CPU(aq_desc->retval));
 348         i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
 349                    LE32_TO_CPU(aq_desc->cookie_high),
 350                    LE32_TO_CPU(aq_desc->cookie_low));
 351         i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
 352                    LE32_TO_CPU(aq_desc->params.internal.param0),
 353                    LE32_TO_CPU(aq_desc->params.internal.param1));
 354         i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
 355                    LE32_TO_CPU(aq_desc->params.external.addr_high),
 356                    LE32_TO_CPU(aq_desc->params.external.addr_low));
 357
 358         if ((buffer != NULL) && (aq_desc->datalen != 0)) {
 359                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 360                 if (buf_len < len)
 361                         len = buf_len;
 362                 /* write the full 16-byte chunks */
 363                 for (i = 0; i < (len - 16); i += 16)
 364                         i40e_debug(hw, mask,
 365                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 366                                    i, buf[i], buf[i+1], buf[i+2], buf[i+3],
 367                                    buf[i+4], buf[i+5], buf[i+6], buf[i+7],
 368                                    buf[i+8], buf[i+9], buf[i+10], buf[i+11],
 369                                    buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
 370                 /* the most we could have left is 16 bytes, pad with zeros */
 371                 if (i < len) {
 372                         char d_buf[16];
 373                         int j, i_sav;
 374
 375                         i_sav = i;
 376                         memset(d_buf, 0, sizeof(d_buf));
 377                         for (j = 0; i < len; j++, i++)
 378                                 d_buf[j] = buf[i];
 379                         i40e_debug(hw, mask,
 380                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 381                                    i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
 382                                    d_buf[4], d_buf[5], d_buf[6], d_buf[7],
 383                                    d_buf[8], d_buf[9], d_buf[10], d_buf[11],
 384                                    d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
 385                 }
 386         }
 387 }
 388
 389 /**
 390  * i40e_check_asq_alive
 391  * @hw: pointer to the hw struct
 392  *
 393  * Returns true if Queue is enabled else false.
 394  **/
 395 bool i40e_check_asq_alive(struct i40e_hw *hw)
 396 {
 397         if (hw->aq.asq.len)
 398 #ifdef PF_DRIVER
 399 #ifdef INTEGRATED_VF
 400                 if (!i40e_is_vf(hw))
 401                         return !!(rd32(hw, hw->aq.asq.len) &
 402                                 I40E_PF_ATQLEN_ATQENABLE_MASK);
 403 #else
 404                 return !!(rd32(hw, hw->aq.asq.len) &
 405                         I40E_PF_ATQLEN_ATQENABLE_MASK);
 406 #endif /* INTEGRATED_VF */
 407 #endif /* PF_DRIVER */
 408 #ifdef VF_DRIVER
 409 #ifdef INTEGRATED_VF
 410                 if (i40e_is_vf(hw))
 411                         return !!(rd32(hw, hw->aq.asq.len) &
 412                                 I40E_VF_ATQLEN1_ATQENABLE_MASK);
 413 #else
 414                 return !!(rd32(hw, hw->aq.asq.len) &
 415                         I40E_VF_ATQLEN1_ATQENABLE_MASK);
 416 #endif /* INTEGRATED_VF */
 417 #endif /* VF_DRIVER */
 418         return false;
 419 }
 420
 421 /**
 422  * i40e_aq_queue_shutdown
 423  * @hw: pointer to the hw struct
 424  * @unloading: is the driver unloading itself
 425  *
 426  * Tell the Firmware that we're shutting down the AdminQ and whether
 427  * or not the driver is unloading as well.
 428  **/
 429 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
 430                                              bool unloading)
 431 {
 432         struct i40e_aq_desc desc;
 433         struct i40e_aqc_queue_shutdown *cmd =
 434                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 435         enum i40e_status_code status;
 436
 437         i40e_fill_default_direct_cmd_desc(&desc,
 438                                           i40e_aqc_opc_queue_shutdown);
 439
 440         if (unloading)
 441                 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
 442         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 443
 444         return status;
 445 }
 446
 447 /**
 448  * i40e_aq_get_set_rss_lut
 449  * @hw: pointer to the hardware structure
 450  * @vsi_id: vsi fw index
 451  * @pf_lut: for PF table set true, for VSI table set false
 452  * @lut: pointer to the lut buffer provided by the caller
 453  * @lut_size: size of the lut buffer
 454  * @set: set true to set the table, false to get the table
 455  *
 456  * Internal function to get or set RSS look up table
 457  **/
 458 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 459                                                      u16 vsi_id, bool pf_lut,
 460                                                      u8 *lut, u16 lut_size,
 461                                                      bool set)
 462 {
 463         enum i40e_status_code status;
 464         struct i40e_aq_desc desc;
 465         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 466                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 467
 468         if (set)
 469                 i40e_fill_default_direct_cmd_desc(&desc,
 470                                                   i40e_aqc_opc_set_rss_lut);
 471         else
 472                 i40e_fill_default_direct_cmd_desc(&desc,
 473                                                   i40e_aqc_opc_get_rss_lut);
 474
 475         /* Indirect command */
 476         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 477         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 478
 479         cmd_resp->vsi_id =
 480                         CPU_TO_LE16((u16)((vsi_id <<
 481                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 482                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 483         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 484
 485         if (pf_lut)
 486                 cmd_resp->flags |= CPU_TO_LE16((u16)
 487                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 488                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 489                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 490         else
 491                 cmd_resp->flags |= CPU_TO_LE16((u16)
 492                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 493                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 494                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 495
 496         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 497
 498         return status;
 499 }
 500
 501 /**
 502  * i40e_aq_get_rss_lut
 503  * @hw: pointer to the hardware structure
 504  * @vsi_id: vsi fw index
 505  * @pf_lut: for PF table set true, for VSI table set false
 506  * @lut: pointer to the lut buffer provided by the caller
 507  * @lut_size: size of the lut buffer
 508  *
 509  * get the RSS lookup table, PF or VSI type
 510  **/
 511 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 512                                           bool pf_lut, u8 *lut, u16 lut_size)
 513 {
 514         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 515                                        false);
 516 }
 517
 518 /**
 519  * i40e_aq_set_rss_lut
 520  * @hw: pointer to the hardware structure
 521  * @vsi_id: vsi fw index
 522  * @pf_lut: for PF table set true, for VSI table set false
 523  * @lut: pointer to the lut buffer provided by the caller
 524  * @lut_size: size of the lut buffer
 525  *
 526  * set the RSS lookup table, PF or VSI type
 527  **/
 528 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 529                                           bool pf_lut, u8 *lut, u16 lut_size)
 530 {
 531         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
 532 }
 533
 534 /**
 535  * i40e_aq_get_set_rss_key
 536  * @hw: pointer to the hw struct
 537  * @vsi_id: vsi fw index
 538  * @key: pointer to key info struct
 539  * @set: set true to set the key, false to get the key
 540  *
 541  * get the RSS key per VSI
 542  **/
 543 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 544                                       u16 vsi_id,
 545                                       struct i40e_aqc_get_set_rss_key_data *key,
 546                                       bool set)
 547 {
 548         enum i40e_status_code status;
 549         struct i40e_aq_desc desc;
 550         struct i40e_aqc_get_set_rss_key *cmd_resp =
 551                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 552         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 553
 554         if (set)
 555                 i40e_fill_default_direct_cmd_desc(&desc,
 556                                                   i40e_aqc_opc_set_rss_key);
 557         else
 558                 i40e_fill_default_direct_cmd_desc(&desc,
 559                                                   i40e_aqc_opc_get_rss_key);
 560
 561         /* Indirect command */
 562         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 563         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 564
 565         cmd_resp->vsi_id =
 566                         CPU_TO_LE16((u16)((vsi_id <<
 567                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 568                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 569         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 570
 571         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 572
 573         return status;
 574 }
 575
 576 /**
 577  * i40e_aq_get_rss_key
 578  * @hw: pointer to the hw struct
 579  * @vsi_id: vsi fw index
 580  * @key: pointer to key info struct
 581  *
 582  **/
 583 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
 584                                       u16 vsi_id,
 585                                       struct i40e_aqc_get_set_rss_key_data *key)
 586 {
 587         return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
 588 }
 589
 590 /**
 591  * i40e_aq_set_rss_key
 592  * @hw: pointer to the hw struct
 593  * @vsi_id: vsi fw index
 594  * @key: pointer to key info struct
 595  *
 596  * set the RSS key per VSI
 597  **/
 598 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
 599                                       u16 vsi_id,
 600                                       struct i40e_aqc_get_set_rss_key_data *key)
 601 {
 602         return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
 603 }
 604
 605 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 606  * hardware to a bit-field that can be used by SW to more easily determine the
 607  * packet type.
 608  *
 609  * Macros are used to shorten the table lines and make this table human
 610  * readable.
 611  *
 612  * We store the PTYPE in the top byte of the bit field - this is just so that
 613  * we can check that the table doesn't have a row missing, as the index into
 614  * the table should be the PTYPE.
 615  *
 616  * Typical work flow:
 617  *
 618  * IF NOT i40e_ptype_lookup[ptype].known
 619  * THEN
 620  *      Packet is unknown
 621  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 622  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 623  * ELSE
 624  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 625  * ENDIF
 626  */
 627
 628 /* macro to make the table lines short */
 629 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 630         {       PTYPE, \
 631                 1, \
 632                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 633                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 634                 I40E_RX_PTYPE_##OUTER_FRAG, \
 635                 I40E_RX_PTYPE_TUNNEL_##T, \
 636                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 637                 I40E_RX_PTYPE_##TEF, \
 638                 I40E_RX_PTYPE_INNER_PROT_##I, \
 639                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 640
 641 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 642                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 643
 644 /* shorter macros makes the table fit but are terse */
 645 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 646 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 647 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 648
 649 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 650 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 651         /* L2 Packet types */
 652         I40E_PTT_UNUSED_ENTRY(0),
 653         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 654         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 655         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 656         I40E_PTT_UNUSED_ENTRY(4),
 657         I40E_PTT_UNUSED_ENTRY(5),
 658         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 659         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 660         I40E_PTT_UNUSED_ENTRY(8),
 661         I40E_PTT_UNUSED_ENTRY(9),
 662         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 663         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 664         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 665         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 666         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 667         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 668         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 669         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 670         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 671         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 672         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 673         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 674
 675         /* Non Tunneled IPv4 */
 676         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 677         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 678         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 679         I40E_PTT_UNUSED_ENTRY(25),
 680         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 681         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 682         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 683
 684         /* IPv4 --> IPv4 */
 685         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 686         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 687         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 688         I40E_PTT_UNUSED_ENTRY(32),
 689         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 690         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 691         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 692
 693         /* IPv4 --> IPv6 */
 694         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 695         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 696         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 697         I40E_PTT_UNUSED_ENTRY(39),
 698         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 699         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 700         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 701
 702         /* IPv4 --> GRE/NAT */
 703         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 704
 705         /* IPv4 --> GRE/NAT --> IPv4 */
 706         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 707         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 708         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 709         I40E_PTT_UNUSED_ENTRY(47),
 710         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 711         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 712         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 713
 714         /* IPv4 --> GRE/NAT --> IPv6 */
 715         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 716         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 717         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 718         I40E_PTT_UNUSED_ENTRY(54),
 719         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 720         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 721         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 722
 723         /* IPv4 --> GRE/NAT --> MAC */
 724         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 725
 726         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 727         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 728         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 729         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 730         I40E_PTT_UNUSED_ENTRY(62),
 731         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 732         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 733         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 734
 735         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 736         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 737         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 738         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 739         I40E_PTT_UNUSED_ENTRY(69),
 740         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 741         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 742         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 743
 744         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 745         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 746
 747         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 748         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 749         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 750         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 751         I40E_PTT_UNUSED_ENTRY(77),
 752         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 753         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 754         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 755
 756         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 757         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 758         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 759         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 760         I40E_PTT_UNUSED_ENTRY(84),
 761         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 762         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 763         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 764
 765         /* Non Tunneled IPv6 */
 766         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 767         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 768         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
 769         I40E_PTT_UNUSED_ENTRY(91),
 770         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 771         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 772         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 773
 774         /* IPv6 --> IPv4 */
 775         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 776         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 777         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 778         I40E_PTT_UNUSED_ENTRY(98),
 779         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 780         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 781         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 782
 783         /* IPv6 --> IPv6 */
 784         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 785         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 786         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 787         I40E_PTT_UNUSED_ENTRY(105),
 788         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 789         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 790         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 791
 792         /* IPv6 --> GRE/NAT */
 793         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 794
 795         /* IPv6 --> GRE/NAT -> IPv4 */
 796         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 797         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 798         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 799         I40E_PTT_UNUSED_ENTRY(113),
 800         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 801         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 802         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 803
 804         /* IPv6 --> GRE/NAT -> IPv6 */
 805         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 806         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 807         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 808         I40E_PTT_UNUSED_ENTRY(120),
 809         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 810         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 811         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 812
 813         /* IPv6 --> GRE/NAT -> MAC */
 814         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 815
 816         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 817         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 818         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 819         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 820         I40E_PTT_UNUSED_ENTRY(128),
 821         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 822         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 823         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 824
 825         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 826         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 827         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 828         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 829         I40E_PTT_UNUSED_ENTRY(135),
 830         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 831         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 832         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 833
 834         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 835         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 836
 837         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 838         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 839         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 840         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 841         I40E_PTT_UNUSED_ENTRY(143),
 842         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 843         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 844         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 845
 846         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 847         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 848         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 849         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 850         I40E_PTT_UNUSED_ENTRY(150),
 851         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 852         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 853         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 854
 855         /* unused entries */
 856         I40E_PTT_UNUSED_ENTRY(154),
 857         I40E_PTT_UNUSED_ENTRY(155),
 858         I40E_PTT_UNUSED_ENTRY(156),
 859         I40E_PTT_UNUSED_ENTRY(157),
 860         I40E_PTT_UNUSED_ENTRY(158),
 861         I40E_PTT_UNUSED_ENTRY(159),
 862
 863         I40E_PTT_UNUSED_ENTRY(160),
 864         I40E_PTT_UNUSED_ENTRY(161),
 865         I40E_PTT_UNUSED_ENTRY(162),
 866         I40E_PTT_UNUSED_ENTRY(163),
 867         I40E_PTT_UNUSED_ENTRY(164),
 868         I40E_PTT_UNUSED_ENTRY(165),
 869         I40E_PTT_UNUSED_ENTRY(166),
 870         I40E_PTT_UNUSED_ENTRY(167),
 871         I40E_PTT_UNUSED_ENTRY(168),
 872         I40E_PTT_UNUSED_ENTRY(169),
 873
 874         I40E_PTT_UNUSED_ENTRY(170),
 875         I40E_PTT_UNUSED_ENTRY(171),
 876         I40E_PTT_UNUSED_ENTRY(172),
 877         I40E_PTT_UNUSED_ENTRY(173),
 878         I40E_PTT_UNUSED_ENTRY(174),
 879         I40E_PTT_UNUSED_ENTRY(175),
 880         I40E_PTT_UNUSED_ENTRY(176),
 881         I40E_PTT_UNUSED_ENTRY(177),
 882         I40E_PTT_UNUSED_ENTRY(178),
 883         I40E_PTT_UNUSED_ENTRY(179),
 884
 885         I40E_PTT_UNUSED_ENTRY(180),
 886         I40E_PTT_UNUSED_ENTRY(181),
 887         I40E_PTT_UNUSED_ENTRY(182),
 888         I40E_PTT_UNUSED_ENTRY(183),
 889         I40E_PTT_UNUSED_ENTRY(184),
 890         I40E_PTT_UNUSED_ENTRY(185),
 891         I40E_PTT_UNUSED_ENTRY(186),
 892         I40E_PTT_UNUSED_ENTRY(187),
 893         I40E_PTT_UNUSED_ENTRY(188),
 894         I40E_PTT_UNUSED_ENTRY(189),
 895
 896         I40E_PTT_UNUSED_ENTRY(190),
 897         I40E_PTT_UNUSED_ENTRY(191),
 898         I40E_PTT_UNUSED_ENTRY(192),
 899         I40E_PTT_UNUSED_ENTRY(193),
 900         I40E_PTT_UNUSED_ENTRY(194),
 901         I40E_PTT_UNUSED_ENTRY(195),
 902         I40E_PTT_UNUSED_ENTRY(196),
 903         I40E_PTT_UNUSED_ENTRY(197),
 904         I40E_PTT_UNUSED_ENTRY(198),
 905         I40E_PTT_UNUSED_ENTRY(199),
 906
 907         I40E_PTT_UNUSED_ENTRY(200),
 908         I40E_PTT_UNUSED_ENTRY(201),
 909         I40E_PTT_UNUSED_ENTRY(202),
 910         I40E_PTT_UNUSED_ENTRY(203),
 911         I40E_PTT_UNUSED_ENTRY(204),
 912         I40E_PTT_UNUSED_ENTRY(205),
 913         I40E_PTT_UNUSED_ENTRY(206),
 914         I40E_PTT_UNUSED_ENTRY(207),
 915         I40E_PTT_UNUSED_ENTRY(208),
 916         I40E_PTT_UNUSED_ENTRY(209),
 917
 918         I40E_PTT_UNUSED_ENTRY(210),
 919         I40E_PTT_UNUSED_ENTRY(211),
 920         I40E_PTT_UNUSED_ENTRY(212),
 921         I40E_PTT_UNUSED_ENTRY(213),
 922         I40E_PTT_UNUSED_ENTRY(214),
 923         I40E_PTT_UNUSED_ENTRY(215),
 924         I40E_PTT_UNUSED_ENTRY(216),
 925         I40E_PTT_UNUSED_ENTRY(217),
 926         I40E_PTT_UNUSED_ENTRY(218),
 927         I40E_PTT_UNUSED_ENTRY(219),
 928
 929         I40E_PTT_UNUSED_ENTRY(220),
 930         I40E_PTT_UNUSED_ENTRY(221),
 931         I40E_PTT_UNUSED_ENTRY(222),
 932         I40E_PTT_UNUSED_ENTRY(223),
 933         I40E_PTT_UNUSED_ENTRY(224),
 934         I40E_PTT_UNUSED_ENTRY(225),
 935         I40E_PTT_UNUSED_ENTRY(226),
 936         I40E_PTT_UNUSED_ENTRY(227),
 937         I40E_PTT_UNUSED_ENTRY(228),
 938         I40E_PTT_UNUSED_ENTRY(229),
 939
 940         I40E_PTT_UNUSED_ENTRY(230),
 941         I40E_PTT_UNUSED_ENTRY(231),
 942         I40E_PTT_UNUSED_ENTRY(232),
 943         I40E_PTT_UNUSED_ENTRY(233),
 944         I40E_PTT_UNUSED_ENTRY(234),
 945         I40E_PTT_UNUSED_ENTRY(235),
 946         I40E_PTT_UNUSED_ENTRY(236),
 947         I40E_PTT_UNUSED_ENTRY(237),
 948         I40E_PTT_UNUSED_ENTRY(238),
 949         I40E_PTT_UNUSED_ENTRY(239),
 950
 951         I40E_PTT_UNUSED_ENTRY(240),
 952         I40E_PTT_UNUSED_ENTRY(241),
 953         I40E_PTT_UNUSED_ENTRY(242),
 954         I40E_PTT_UNUSED_ENTRY(243),
 955         I40E_PTT_UNUSED_ENTRY(244),
 956         I40E_PTT_UNUSED_ENTRY(245),
 957         I40E_PTT_UNUSED_ENTRY(246),
 958         I40E_PTT_UNUSED_ENTRY(247),
 959         I40E_PTT_UNUSED_ENTRY(248),
 960         I40E_PTT_UNUSED_ENTRY(249),
 961
 962         I40E_PTT_UNUSED_ENTRY(250),
 963         I40E_PTT_UNUSED_ENTRY(251),
 964         I40E_PTT_UNUSED_ENTRY(252),
 965         I40E_PTT_UNUSED_ENTRY(253),
 966         I40E_PTT_UNUSED_ENTRY(254),
 967         I40E_PTT_UNUSED_ENTRY(255)
 968 };
 969
 970
 971 /**
 972  * i40e_validate_mac_addr - Validate unicast MAC address
 973  * @mac_addr: pointer to MAC address
 974  *
 975  * Tests a MAC address to ensure it is a valid Individual Address
 976  **/
 977 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
 978 {
 979         enum i40e_status_code status = I40E_SUCCESS;
 980
 981         DEBUGFUNC("i40e_validate_mac_addr");
 982
 983         /* Broadcast addresses ARE multicast addresses
 984          * Make sure it is not a multicast address
 985          * Reject the zero address
 986          */
 987         if (I40E_IS_MULTICAST(mac_addr) ||
 988             (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
 989               mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
 990                 status = I40E_ERR_INVALID_MAC_ADDR;
 991
 992         return status;
 993 }
 994 #ifdef PF_DRIVER
 995
 996 /**
 997  * i40e_init_shared_code - Initialize the shared code
 998  * @hw: pointer to hardware structure
 999  *
1000  * This assigns the MAC type and PHY code and inits the NVM.
1001  * Does not touch the hardware. This function must be called prior to any
1002  * other function in the shared code. The i40e_hw structure should be
1003  * memset to 0 prior to calling this function.  The following fields in
1004  * hw structure should be filled in prior to calling this function:
1005  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1006  * subsystem_vendor_id, and revision_id
1007  **/
1008 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
1009 {
1010         enum i40e_status_code status = I40E_SUCCESS;
1011         u32 port, ari, func_rid;
1012
1013         DEBUGFUNC("i40e_init_shared_code");
1014
1015         i40e_set_mac_type(hw);
1016
1017         switch (hw->mac.type) {
1018         case I40E_MAC_XL710:
1019         case I40E_MAC_X722:
1020                 break;
1021         default:
1022                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1023         }
1024
1025         hw->phy.get_link_info = true;
1026
1027         /* Determine port number and PF number*/
1028         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1029                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1030         hw->port = (u8)port;
1031         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1032                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1033         func_rid = rd32(hw, I40E_PF_FUNC_RID);
1034         if (ari)
1035                 hw->pf_id = (u8)(func_rid & 0xff);
1036         else
1037                 hw->pf_id = (u8)(func_rid & 0x7);
1038
1039         if (hw->mac.type == I40E_MAC_X722)
1040                 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
1041
1042         status = i40e_init_nvm(hw);
1043         return status;
1044 }
1045
1046 /**
1047  * i40e_aq_mac_address_read - Retrieve the MAC addresses
1048  * @hw: pointer to the hw struct
1049  * @flags: a return indicator of what addresses were added to the addr store
1050  * @addrs: the requestor's mac addr store
1051  * @cmd_details: pointer to command details structure or NULL
1052  **/
1053 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1054                                    u16 *flags,
1055                                    struct i40e_aqc_mac_address_read_data *addrs,
1056                                    struct i40e_asq_cmd_details *cmd_details)
1057 {
1058         struct i40e_aq_desc desc;
1059         struct i40e_aqc_mac_address_read *cmd_data =
1060                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1061         enum i40e_status_code status;
1062
1063         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1064         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1065
1066         status = i40e_asq_send_command(hw, &desc, addrs,
1067                                        sizeof(*addrs), cmd_details);
1068         *flags = LE16_TO_CPU(cmd_data->command_flags);
1069
1070         return status;
1071 }
1072
1073 /**
1074  * i40e_aq_mac_address_write - Change the MAC addresses
1075  * @hw: pointer to the hw struct
1076  * @flags: indicates which MAC to be written
1077  * @mac_addr: address to write
1078  * @cmd_details: pointer to command details structure or NULL
1079  **/
1080 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1081                                     u16 flags, u8 *mac_addr,
1082                                     struct i40e_asq_cmd_details *cmd_details)
1083 {
1084         struct i40e_aq_desc desc;
1085         struct i40e_aqc_mac_address_write *cmd_data =
1086                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1087         enum i40e_status_code status;
1088
1089         i40e_fill_default_direct_cmd_desc(&desc,
1090                                           i40e_aqc_opc_mac_address_write);
1091         cmd_data->command_flags = CPU_TO_LE16(flags);
1092         cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1093         cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1094                                         ((u32)mac_addr[3] << 16) |
1095                                         ((u32)mac_addr[4] << 8) |
1096                                         mac_addr[5]);
1097
1098         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1099
1100         return status;
1101 }
1102
1103 /**
1104  * i40e_get_mac_addr - get MAC address
1105  * @hw: pointer to the HW structure
1106  * @mac_addr: pointer to MAC address
1107  *
1108  * Reads the adapter's MAC address from register
1109  **/
1110 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1111 {
1112         struct i40e_aqc_mac_address_read_data addrs;
1113         enum i40e_status_code status;
1114         u16 flags = 0;
1115
1116         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1117
1118         if (flags & I40E_AQC_LAN_ADDR_VALID)
1119                 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1120                         I40E_NONDMA_TO_NONDMA);
1121
1122         return status;
1123 }
1124
1125 /**
1126  * i40e_get_port_mac_addr - get Port MAC address
1127  * @hw: pointer to the HW structure
1128  * @mac_addr: pointer to Port MAC address
1129  *
1130  * Reads the adapter's Port MAC address
1131  **/
1132 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1133 {
1134         struct i40e_aqc_mac_address_read_data addrs;
1135         enum i40e_status_code status;
1136         u16 flags = 0;
1137
1138         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1139         if (status)
1140                 return status;
1141
1142         if (flags & I40E_AQC_PORT_ADDR_VALID)
1143                 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1144                         I40E_NONDMA_TO_NONDMA);
1145         else
1146                 status = I40E_ERR_INVALID_MAC_ADDR;
1147
1148         return status;
1149 }
1150
1151 /**
1152  * i40e_pre_tx_queue_cfg - pre tx queue configure
1153  * @hw: pointer to the HW structure
1154  * @queue: target pf queue index
1155  * @enable: state change request
1156  *
1157  * Handles hw requirement to indicate intention to enable
1158  * or disable target queue.
1159  **/
1160 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1161 {
1162         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1163         u32 reg_block = 0;
1164         u32 reg_val;
1165
1166         if (abs_queue_idx >= 128) {
1167                 reg_block = abs_queue_idx / 128;
1168                 abs_queue_idx %= 128;
1169         }
1170
1171         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1172         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1173         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1174
1175         if (enable)
1176                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1177         else
1178                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1179
1180         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1181 }
1182
1183 /**
1184  * i40e_get_san_mac_addr - get SAN MAC address
1185  * @hw: pointer to the HW structure
1186  * @mac_addr: pointer to SAN MAC address
1187  *
1188  * Reads the adapter's SAN MAC address from NVM
1189  **/
1190 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1191                                             u8 *mac_addr)
1192 {
1193         struct i40e_aqc_mac_address_read_data addrs;
1194         enum i40e_status_code status;
1195         u16 flags = 0;
1196
1197         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1198         if (status)
1199                 return status;
1200
1201         if (flags & I40E_AQC_SAN_ADDR_VALID)
1202                 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac),
1203                         I40E_NONDMA_TO_NONDMA);
1204         else
1205                 status = I40E_ERR_INVALID_MAC_ADDR;
1206
1207         return status;
1208 }
1209
1210 /**
1211  *  i40e_read_pba_string - Reads part number string from EEPROM
1212  *  @hw: pointer to hardware structure
1213  *  @pba_num: stores the part number string from the EEPROM
1214  *  @pba_num_size: part number string buffer length
1215  *
1216  *  Reads the part number string from the EEPROM.
1217  **/
1218 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1219                                             u32 pba_num_size)
1220 {
1221         enum i40e_status_code status = I40E_SUCCESS;
1222         u16 pba_word = 0;
1223         u16 pba_size = 0;
1224         u16 pba_ptr = 0;
1225         u16 i = 0;
1226
1227         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1228         if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1229                 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1230                 return status;
1231         }
1232
1233         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1234         if (status != I40E_SUCCESS) {
1235                 DEBUGOUT("Failed to read PBA Block pointer.\n");
1236                 return status;
1237         }
1238
1239         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1240         if (status != I40E_SUCCESS) {
1241                 DEBUGOUT("Failed to read PBA Block size.\n");
1242                 return status;
1243         }
1244
1245         /* Subtract one to get PBA word count (PBA Size word is included in
1246          * total size)
1247          */
1248         pba_size--;
1249         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1250                 DEBUGOUT("Buffer to small for PBA data.\n");
1251                 return I40E_ERR_PARAM;
1252         }
1253
1254         for (i = 0; i < pba_size; i++) {
1255                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1256                 if (status != I40E_SUCCESS) {
1257                         DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1258                         return status;
1259                 }
1260
1261                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1262                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1263         }
1264         pba_num[(pba_size * 2)] = '\0';
1265
1266         return status;
1267 }
1268
1269 /**
1270  * i40e_get_media_type - Gets media type
1271  * @hw: pointer to the hardware structure
1272  **/
1273 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1274 {
1275         enum i40e_media_type media;
1276
1277         switch (hw->phy.link_info.phy_type) {
1278         case I40E_PHY_TYPE_10GBASE_SR:
1279         case I40E_PHY_TYPE_10GBASE_LR:
1280         case I40E_PHY_TYPE_1000BASE_SX:
1281         case I40E_PHY_TYPE_1000BASE_LX:
1282         case I40E_PHY_TYPE_40GBASE_SR4:
1283         case I40E_PHY_TYPE_40GBASE_LR4:
1284         case I40E_PHY_TYPE_25GBASE_LR:
1285         case I40E_PHY_TYPE_25GBASE_SR:
1286                 media = I40E_MEDIA_TYPE_FIBER;
1287                 break;
1288         case I40E_PHY_TYPE_100BASE_TX:
1289         case I40E_PHY_TYPE_1000BASE_T:
1290         case I40E_PHY_TYPE_10GBASE_T:
1291                 media = I40E_MEDIA_TYPE_BASET;
1292                 break;
1293         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1294         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1295         case I40E_PHY_TYPE_10GBASE_CR1:
1296         case I40E_PHY_TYPE_40GBASE_CR4:
1297         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1298         case I40E_PHY_TYPE_40GBASE_AOC:
1299         case I40E_PHY_TYPE_10GBASE_AOC:
1300         case I40E_PHY_TYPE_25GBASE_CR:
1301         case I40E_PHY_TYPE_25GBASE_AOC:
1302         case I40E_PHY_TYPE_25GBASE_ACC:
1303                 media = I40E_MEDIA_TYPE_DA;
1304                 break;
1305         case I40E_PHY_TYPE_1000BASE_KX:
1306         case I40E_PHY_TYPE_10GBASE_KX4:
1307         case I40E_PHY_TYPE_10GBASE_KR:
1308         case I40E_PHY_TYPE_40GBASE_KR4:
1309         case I40E_PHY_TYPE_20GBASE_KR2:
1310         case I40E_PHY_TYPE_25GBASE_KR:
1311                 media = I40E_MEDIA_TYPE_BACKPLANE;
1312                 break;
1313         case I40E_PHY_TYPE_SGMII:
1314         case I40E_PHY_TYPE_XAUI:
1315         case I40E_PHY_TYPE_XFI:
1316         case I40E_PHY_TYPE_XLAUI:
1317         case I40E_PHY_TYPE_XLPPI:
1318         default:
1319                 media = I40E_MEDIA_TYPE_UNKNOWN;
1320                 break;
1321         }
1322
1323         return media;
1324 }
1325
1326 #define I40E_PF_RESET_WAIT_COUNT        200
1327 /**
1328  * i40e_pf_reset - Reset the PF
1329  * @hw: pointer to the hardware structure
1330  *
1331  * Assuming someone else has triggered a global reset,
1332  * assure the global reset is complete and then reset the PF
1333  **/
1334 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1335 {
1336         u32 cnt = 0;
1337         u32 cnt1 = 0;
1338         u32 reg = 0;
1339         u32 grst_del;
1340
1341         /* Poll for Global Reset steady state in case of recent GRST.
1342          * The grst delay value is in 100ms units, and we'll wait a
1343          * couple counts longer to be sure we don't just miss the end.
1344          */
1345         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1346                         I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1347                         I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1348
1349         grst_del = grst_del * 20;
1350
1351         for (cnt = 0; cnt < grst_del; cnt++) {
1352                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1353                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1354                         break;
1355                 i40e_msec_delay(100);
1356         }
1357         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1358                 DEBUGOUT("Global reset polling failed to complete.\n");
1359                 return I40E_ERR_RESET_FAILED;
1360         }
1361
1362         /* Now Wait for the FW to be ready */
1363         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1364                 reg = rd32(hw, I40E_GLNVM_ULD);
1365                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1366                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1367                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1368                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1369                         DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1370                         break;
1371                 }
1372                 i40e_msec_delay(10);
1373         }
1374         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1375                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1376                 DEBUGOUT("wait for FW Reset complete timedout\n");
1377                 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1378                 return I40E_ERR_RESET_FAILED;
1379         }
1380
1381         /* If there was a Global Reset in progress when we got here,
1382          * we don't need to do the PF Reset
1383          */
1384         if (!cnt) {
1385                 reg = rd32(hw, I40E_PFGEN_CTRL);
1386                 wr32(hw, I40E_PFGEN_CTRL,
1387                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1388                 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1389                         reg = rd32(hw, I40E_PFGEN_CTRL);
1390                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1391                                 break;
1392                         i40e_msec_delay(1);
1393                 }
1394                 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1395                         DEBUGOUT("PF reset polling failed to complete.\n");
1396                         return I40E_ERR_RESET_FAILED;
1397                 }
1398         }
1399
1400         i40e_clear_pxe_mode(hw);
1401
1402
1403         return I40E_SUCCESS;
1404 }
1405
1406 /**
1407  * i40e_clear_hw - clear out any left over hw state
1408  * @hw: pointer to the hw struct
1409  *
1410  * Clear queues and interrupts, typically called at init time,
1411  * but after the capabilities have been found so we know how many
1412  * queues and msix vectors have been allocated.
1413  **/
1414 void i40e_clear_hw(struct i40e_hw *hw)
1415 {
1416         u32 num_queues, base_queue;
1417         u32 num_pf_int;
1418         u32 num_vf_int;
1419         u32 num_vfs;
1420         u32 i, j;
1421         u32 val;
1422         u32 eol = 0x7ff;
1423
1424         /* get number of interrupts, queues, and vfs */
1425         val = rd32(hw, I40E_GLPCI_CNF2);
1426         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1427                         I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1428         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1429                         I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1430
1431         val = rd32(hw, I40E_PFLAN_QALLOC);
1432         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1433                         I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1434         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1435                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1436         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1437                 num_queues = (j - base_queue) + 1;
1438         else
1439                 num_queues = 0;
1440
1441         val = rd32(hw, I40E_PF_VT_PFALLOC);
1442         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1443                         I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1444         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1445                         I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1446         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1447                 num_vfs = (j - i) + 1;
1448         else
1449                 num_vfs = 0;
1450
1451         /* stop all the interrupts */
1452         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1453         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1454         for (i = 0; i < num_pf_int - 2; i++)
1455                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1456
1457         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1458         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1459         wr32(hw, I40E_PFINT_LNKLST0, val);
1460         for (i = 0; i < num_pf_int - 2; i++)
1461                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1462         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1463         for (i = 0; i < num_vfs; i++)
1464                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1465         for (i = 0; i < num_vf_int - 2; i++)
1466                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1467
1468         /* warn the HW of the coming Tx disables */
1469         for (i = 0; i < num_queues; i++) {
1470                 u32 abs_queue_idx = base_queue + i;
1471                 u32 reg_block = 0;
1472
1473                 if (abs_queue_idx >= 128) {
1474                         reg_block = abs_queue_idx / 128;
1475                         abs_queue_idx %= 128;
1476                 }
1477
1478                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1479                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1480                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1481                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1482
1483                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1484         }
1485         i40e_usec_delay(400);
1486
1487         /* stop all the queues */
1488         for (i = 0; i < num_queues; i++) {
1489                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1490                 wr32(hw, I40E_QTX_ENA(i), 0);
1491                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1492                 wr32(hw, I40E_QRX_ENA(i), 0);
1493         }
1494
1495         /* short wait for all queue disables to settle */
1496         i40e_usec_delay(50);
1497 }
1498
1499 /**
1500  * i40e_clear_pxe_mode - clear pxe operations mode
1501  * @hw: pointer to the hw struct
1502  *
1503  * Make sure all PXE mode settings are cleared, including things
1504  * like descriptor fetch/write-back mode.
1505  **/
1506 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1507 {
1508         if (i40e_check_asq_alive(hw))
1509                 i40e_aq_clear_pxe_mode(hw, NULL);
1510 }
1511
1512 /**
1513  * i40e_led_is_mine - helper to find matching led
1514  * @hw: pointer to the hw struct
1515  * @idx: index into GPIO registers
1516  *
1517  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1518  */
1519 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1520 {
1521         u32 gpio_val = 0;
1522         u32 port;
1523
1524         if (!hw->func_caps.led[idx])
1525                 return 0;
1526
1527         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1528         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1529                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1530
1531         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1532          * if it is not our port then ignore
1533          */
1534         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1535             (port != hw->port))
1536                 return 0;
1537
1538         return gpio_val;
1539 }
1540
1541 #define I40E_COMBINED_ACTIVITY 0xA
1542 #define I40E_FILTER_ACTIVITY 0xE
1543 #define I40E_LINK_ACTIVITY 0xC
1544 #define I40E_MAC_ACTIVITY 0xD
1545 #define I40E_LED0 22
1546
1547 /**
1548  * i40e_led_get - return current on/off mode
1549  * @hw: pointer to the hw struct
1550  *
1551  * The value returned is the 'mode' field as defined in the
1552  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1553  * values are variations of possible behaviors relating to
1554  * blink, link, and wire.
1555  **/
1556 u32 i40e_led_get(struct i40e_hw *hw)
1557 {
1558         u32 current_mode = 0;
1559         u32 mode = 0;
1560         int i;
1561
1562         /* as per the documentation GPIO 22-29 are the LED
1563          * GPIO pins named LED0..LED7
1564          */
1565         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1566                 u32 gpio_val = i40e_led_is_mine(hw, i);
1567
1568                 if (!gpio_val)
1569                         continue;
1570
1571                 /* ignore gpio LED src mode entries related to the activity
1572                  *  LEDs
1573                  */
1574                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1575                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1576                 switch (current_mode) {
1577                 case I40E_COMBINED_ACTIVITY:
1578                 case I40E_FILTER_ACTIVITY:
1579                 case I40E_MAC_ACTIVITY:
1580                         continue;
1581                 default:
1582                         break;
1583                 }
1584
1585                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1586                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1587                 break;
1588         }
1589
1590         return mode;
1591 }
1592
1593 /**
1594  * i40e_led_set - set new on/off mode
1595  * @hw: pointer to the hw struct
1596  * @mode: 0=off, 0xf=on (else see manual for mode details)
1597  * @blink: true if the LED should blink when on, false if steady
1598  *
1599  * if this function is used to turn on the blink it should
1600  * be used to disable the blink when restoring the original state.
1601  **/
1602 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1603 {
1604         u32 current_mode = 0;
1605         int i;
1606
1607         if (mode & 0xfffffff0)
1608                 DEBUGOUT1("invalid mode passed in %X\n", mode);
1609
1610         /* as per the documentation GPIO 22-29 are the LED
1611          * GPIO pins named LED0..LED7
1612          */
1613         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1614                 u32 gpio_val = i40e_led_is_mine(hw, i);
1615
1616                 if (!gpio_val)
1617                         continue;
1618
1619                 /* ignore gpio LED src mode entries related to the activity
1620                  * LEDs
1621                  */
1622                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1623                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1624                 switch (current_mode) {
1625                 case I40E_COMBINED_ACTIVITY:
1626                 case I40E_FILTER_ACTIVITY:
1627                 case I40E_MAC_ACTIVITY:
1628                         continue;
1629                 default:
1630                         break;
1631                 }
1632
1633                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1634                 /* this & is a bit of paranoia, but serves as a range check */
1635                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1636                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1637
1638                 if (mode == I40E_LINK_ACTIVITY)
1639                         blink = false;
1640
1641                 if (blink)
1642                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1643                 else
1644                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1645
1646                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1647                 break;
1648         }
1649 }
1650
1651 /* Admin command wrappers */
1652
1653 /**
1654  * i40e_aq_get_phy_capabilities
1655  * @hw: pointer to the hw struct
1656  * @abilities: structure for PHY capabilities to be filled
1657  * @qualified_modules: report Qualified Modules
1658  * @report_init: report init capabilities (active are default)
1659  * @cmd_details: pointer to command details structure or NULL
1660  *
1661  * Returns the various PHY abilities supported on the Port.
1662  **/
1663 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1664                         bool qualified_modules, bool report_init,
1665                         struct i40e_aq_get_phy_abilities_resp *abilities,
1666                         struct i40e_asq_cmd_details *cmd_details)
1667 {
1668         struct i40e_aq_desc desc;
1669         enum i40e_status_code status;
1670         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1671
1672         if (!abilities)
1673                 return I40E_ERR_PARAM;
1674
1675         i40e_fill_default_direct_cmd_desc(&desc,
1676                                           i40e_aqc_opc_get_phy_abilities);
1677
1678         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1679         if (abilities_size > I40E_AQ_LARGE_BUF)
1680                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1681
1682         if (qualified_modules)
1683                 desc.params.external.param0 |=
1684                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1685
1686         if (report_init)
1687                 desc.params.external.param0 |=
1688                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1689
1690         status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1691                                     cmd_details);
1692
1693         if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1694                 status = I40E_ERR_UNKNOWN_PHY;
1695
1696         if (report_init) {
1697                 if (hw->mac.type ==  I40E_MAC_XL710 &&
1698                     hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1699                     hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
1700                         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1701                 } else {
1702                         hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1703                         hw->phy.phy_types |=
1704                                         ((u64)abilities->phy_type_ext << 32);
1705                 }
1706         }
1707
1708         return status;
1709 }
1710
1711 /**
1712  * i40e_aq_set_phy_config
1713  * @hw: pointer to the hw struct
1714  * @config: structure with PHY configuration to be set
1715  * @cmd_details: pointer to command details structure or NULL
1716  *
1717  * Set the various PHY configuration parameters
1718  * supported on the Port.One or more of the Set PHY config parameters may be
1719  * ignored in an MFP mode as the PF may not have the privilege to set some
1720  * of the PHY Config parameters. This status will be indicated by the
1721  * command response.
1722  **/
1723 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1724                                 struct i40e_aq_set_phy_config *config,
1725                                 struct i40e_asq_cmd_details *cmd_details)
1726 {
1727         struct i40e_aq_desc desc;
1728         struct i40e_aq_set_phy_config *cmd =
1729                 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1730         enum i40e_status_code status;
1731
1732         if (!config)
1733                 return I40E_ERR_PARAM;
1734
1735         i40e_fill_default_direct_cmd_desc(&desc,
1736                                           i40e_aqc_opc_set_phy_config);
1737
1738         *cmd = *config;
1739
1740         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1741
1742         return status;
1743 }
1744
1745 /**
1746  * i40e_set_fc
1747  * @hw: pointer to the hw struct
1748  *
1749  * Set the requested flow control mode using set_phy_config.
1750  **/
1751 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1752                                   bool atomic_restart)
1753 {
1754         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1755         struct i40e_aq_get_phy_abilities_resp abilities;
1756         struct i40e_aq_set_phy_config config;
1757         enum i40e_status_code status;
1758         u8 pause_mask = 0x0;
1759
1760         *aq_failures = 0x0;
1761
1762         switch (fc_mode) {
1763         case I40E_FC_FULL:
1764                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1765                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1766                 break;
1767         case I40E_FC_RX_PAUSE:
1768                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1769                 break;
1770         case I40E_FC_TX_PAUSE:
1771                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1772                 break;
1773         default:
1774                 break;
1775         }
1776
1777         /* Get the current phy config */
1778         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1779                                               NULL);
1780         if (status) {
1781                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1782                 return status;
1783         }
1784
1785         memset(&config, 0, sizeof(config));
1786         /* clear the old pause settings */
1787         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1788                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1789         /* set the new abilities */
1790         config.abilities |= pause_mask;
1791         /* If the abilities have changed, then set the new config */
1792         if (config.abilities != abilities.abilities) {
1793                 /* Auto restart link so settings take effect */
1794                 if (atomic_restart)
1795                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1796                 /* Copy over all the old settings */
1797                 config.phy_type = abilities.phy_type;
1798                 config.phy_type_ext = abilities.phy_type_ext;
1799                 config.link_speed = abilities.link_speed;
1800                 config.eee_capability = abilities.eee_capability;
1801                 config.eeer = abilities.eeer_val;
1802                 config.low_power_ctrl = abilities.d3_lpan;
1803                 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1804                                     I40E_AQ_PHY_FEC_CONFIG_MASK;
1805                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1806
1807                 if (status)
1808                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1809         }
1810         /* Update the link info */
1811         status = i40e_update_link_info(hw);
1812         if (status) {
1813                 /* Wait a little bit (on 40G cards it sometimes takes a really
1814                  * long time for link to come back from the atomic reset)
1815                  * and try once more
1816                  */
1817                 i40e_msec_delay(1000);
1818                 status = i40e_update_link_info(hw);
1819         }
1820         if (status)
1821                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1822
1823         return status;
1824 }
1825
1826 /**
1827  * i40e_aq_set_mac_config
1828  * @hw: pointer to the hw struct
1829  * @max_frame_size: Maximum Frame Size to be supported by the port
1830  * @crc_en: Tell HW to append a CRC to outgoing frames
1831  * @pacing: Pacing configurations
1832  * @cmd_details: pointer to command details structure or NULL
1833  *
1834  * Configure MAC settings for frame size, jumbo frame support and the
1835  * addition of a CRC by the hardware.
1836  **/
1837 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1838                                 u16 max_frame_size,
1839                                 bool crc_en, u16 pacing,
1840                                 struct i40e_asq_cmd_details *cmd_details)
1841 {
1842         struct i40e_aq_desc desc;
1843         struct i40e_aq_set_mac_config *cmd =
1844                 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1845         enum i40e_status_code status;
1846
1847         if (max_frame_size == 0)
1848                 return I40E_ERR_PARAM;
1849
1850         i40e_fill_default_direct_cmd_desc(&desc,
1851                                           i40e_aqc_opc_set_mac_config);
1852
1853         cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1854         cmd->params = ((u8)pacing & 0x0F) << 3;
1855         if (crc_en)
1856                 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1857
1858         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1859
1860         return status;
1861 }
1862
1863 /**
1864  * i40e_aq_clear_pxe_mode
1865  * @hw: pointer to the hw struct
1866  * @cmd_details: pointer to command details structure or NULL
1867  *
1868  * Tell the firmware that the driver is taking over from PXE
1869  **/
1870 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1871                         struct i40e_asq_cmd_details *cmd_details)
1872 {
1873         enum i40e_status_code status;
1874         struct i40e_aq_desc desc;
1875         struct i40e_aqc_clear_pxe *cmd =
1876                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1877
1878         i40e_fill_default_direct_cmd_desc(&desc,
1879                                           i40e_aqc_opc_clear_pxe_mode);
1880
1881         cmd->rx_cnt = 0x2;
1882
1883         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1884
1885         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1886
1887         return status;
1888 }
1889
1890 /**
1891  * i40e_aq_set_link_restart_an
1892  * @hw: pointer to the hw struct
1893  * @enable_link: if true: enable link, if false: disable link
1894  * @cmd_details: pointer to command details structure or NULL
1895  *
1896  * Sets up the link and restarts the Auto-Negotiation over the link.
1897  **/
1898 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1899                 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1900 {
1901         struct i40e_aq_desc desc;
1902         struct i40e_aqc_set_link_restart_an *cmd =
1903                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1904         enum i40e_status_code status;
1905
1906         i40e_fill_default_direct_cmd_desc(&desc,
1907                                           i40e_aqc_opc_set_link_restart_an);
1908
1909         cmd->command = I40E_AQ_PHY_RESTART_AN;
1910         if (enable_link)
1911                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1912         else
1913                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1914
1915         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1916
1917         return status;
1918 }
1919
1920 /**
1921  * i40e_aq_get_link_info
1922  * @hw: pointer to the hw struct
1923  * @enable_lse: enable/disable LinkStatusEvent reporting
1924  * @link: pointer to link status structure - optional
1925  * @cmd_details: pointer to command details structure or NULL
1926  *
1927  * Returns the link status of the adapter.
1928  **/
1929 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1930                                 bool enable_lse, struct i40e_link_status *link,
1931                                 struct i40e_asq_cmd_details *cmd_details)
1932 {
1933         struct i40e_aq_desc desc;
1934         struct i40e_aqc_get_link_status *resp =
1935                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1936         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1937         enum i40e_status_code status;
1938         bool tx_pause, rx_pause;
1939         u16 command_flags;
1940
1941         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1942
1943         if (enable_lse)
1944                 command_flags = I40E_AQ_LSE_ENABLE;
1945         else
1946                 command_flags = I40E_AQ_LSE_DISABLE;
1947         resp->command_flags = CPU_TO_LE16(command_flags);
1948
1949         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1950
1951         if (status != I40E_SUCCESS)
1952                 goto aq_get_link_info_exit;
1953
1954         /* save off old link status information */
1955         i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1956                     sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1957
1958         /* update link status */
1959         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1960         hw->phy.media_type = i40e_get_media_type(hw);
1961         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1962         hw_link_info->link_info = resp->link_info;
1963         hw_link_info->an_info = resp->an_info;
1964         hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
1965                                                  I40E_AQ_CONFIG_FEC_RS_ENA);
1966         hw_link_info->ext_info = resp->ext_info;
1967         hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
1968         hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1969         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1970
1971         /* update fc info */
1972         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1973         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1974         if (tx_pause & rx_pause)
1975                 hw->fc.current_mode = I40E_FC_FULL;
1976         else if (tx_pause)
1977                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1978         else if (rx_pause)
1979                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1980         else
1981                 hw->fc.current_mode = I40E_FC_NONE;
1982
1983         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1984                 hw_link_info->crc_enable = true;
1985         else
1986                 hw_link_info->crc_enable = false;
1987
1988         if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
1989                 hw_link_info->lse_enable = true;
1990         else
1991                 hw_link_info->lse_enable = false;
1992
1993         if ((hw->mac.type == I40E_MAC_XL710) &&
1994             (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1995              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1996                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1997
1998         if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1999             hw->aq.api_min_ver >= 7) {
2000                 hw->phy.phy_types = LE32_TO_CPU(*(__le32 *)resp->link_type);
2001                 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
2002         }
2003
2004         /* save link status information */
2005         if (link)
2006                 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
2007                             I40E_NONDMA_TO_NONDMA);
2008
2009         /* flag cleared so helper functions don't call AQ again */
2010         hw->phy.get_link_info = false;
2011
2012 aq_get_link_info_exit:
2013         return status;
2014 }
2015
2016 /**
2017  * i40e_aq_set_phy_int_mask
2018  * @hw: pointer to the hw struct
2019  * @mask: interrupt mask to be set
2020  * @cmd_details: pointer to command details structure or NULL
2021  *
2022  * Set link interrupt mask.
2023  **/
2024 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2025                                 u16 mask,
2026                                 struct i40e_asq_cmd_details *cmd_details)
2027 {
2028         struct i40e_aq_desc desc;
2029         struct i40e_aqc_set_phy_int_mask *cmd =
2030                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2031         enum i40e_status_code status;
2032
2033         i40e_fill_default_direct_cmd_desc(&desc,
2034                                           i40e_aqc_opc_set_phy_int_mask);
2035
2036         cmd->event_mask = CPU_TO_LE16(mask);
2037
2038         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2039
2040         return status;
2041 }
2042
2043 /**
2044  * i40e_aq_get_local_advt_reg
2045  * @hw: pointer to the hw struct
2046  * @advt_reg: local AN advertisement register value
2047  * @cmd_details: pointer to command details structure or NULL
2048  *
2049  * Get the Local AN advertisement register value.
2050  **/
2051 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2052                                 u64 *advt_reg,
2053                                 struct i40e_asq_cmd_details *cmd_details)
2054 {
2055         struct i40e_aq_desc desc;
2056         struct i40e_aqc_an_advt_reg *resp =
2057                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2058         enum i40e_status_code status;
2059
2060         i40e_fill_default_direct_cmd_desc(&desc,
2061                                           i40e_aqc_opc_get_local_advt_reg);
2062
2063         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2064
2065         if (status != I40E_SUCCESS)
2066                 goto aq_get_local_advt_reg_exit;
2067
2068         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2069         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2070
2071 aq_get_local_advt_reg_exit:
2072         return status;
2073 }
2074
2075 /**
2076  * i40e_aq_set_local_advt_reg
2077  * @hw: pointer to the hw struct
2078  * @advt_reg: local AN advertisement register value
2079  * @cmd_details: pointer to command details structure or NULL
2080  *
2081  * Get the Local AN advertisement register value.
2082  **/
2083 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2084                                 u64 advt_reg,
2085                                 struct i40e_asq_cmd_details *cmd_details)
2086 {
2087         struct i40e_aq_desc desc;
2088         struct i40e_aqc_an_advt_reg *cmd =
2089                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2090         enum i40e_status_code status;
2091
2092         i40e_fill_default_direct_cmd_desc(&desc,
2093                                           i40e_aqc_opc_get_local_advt_reg);
2094
2095         cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2096         cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2097
2098         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2099
2100         return status;
2101 }
2102
2103 /**
2104  * i40e_aq_get_partner_advt
2105  * @hw: pointer to the hw struct
2106  * @advt_reg: AN partner advertisement register value
2107  * @cmd_details: pointer to command details structure or NULL
2108  *
2109  * Get the link partner AN advertisement register value.
2110  **/
2111 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2112                                 u64 *advt_reg,
2113                                 struct i40e_asq_cmd_details *cmd_details)
2114 {
2115         struct i40e_aq_desc desc;
2116         struct i40e_aqc_an_advt_reg *resp =
2117                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2118         enum i40e_status_code status;
2119
2120         i40e_fill_default_direct_cmd_desc(&desc,
2121                                           i40e_aqc_opc_get_partner_advt);
2122
2123         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2124
2125         if (status != I40E_SUCCESS)
2126                 goto aq_get_partner_advt_exit;
2127
2128         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2129         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2130
2131 aq_get_partner_advt_exit:
2132         return status;
2133 }
2134
2135 /**
2136  * i40e_aq_set_lb_modes
2137  * @hw: pointer to the hw struct
2138  * @lb_modes: loopback mode to be set
2139  * @cmd_details: pointer to command details structure or NULL
2140  *
2141  * Sets loopback modes.
2142  **/
2143 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2144                                 u16 lb_modes,
2145                                 struct i40e_asq_cmd_details *cmd_details)
2146 {
2147         struct i40e_aq_desc desc;
2148         struct i40e_aqc_set_lb_mode *cmd =
2149                 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2150         enum i40e_status_code status;
2151
2152         i40e_fill_default_direct_cmd_desc(&desc,
2153                                           i40e_aqc_opc_set_lb_modes);
2154
2155         cmd->lb_mode = CPU_TO_LE16(lb_modes);
2156
2157         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2158
2159         return status;
2160 }
2161
2162 /**
2163  * i40e_aq_set_phy_debug
2164  * @hw: pointer to the hw struct
2165  * @cmd_flags: debug command flags
2166  * @cmd_details: pointer to command details structure or NULL
2167  *
2168  * Reset the external PHY.
2169  **/
2170 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2171                                 struct i40e_asq_cmd_details *cmd_details)
2172 {
2173         struct i40e_aq_desc desc;
2174         struct i40e_aqc_set_phy_debug *cmd =
2175                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2176         enum i40e_status_code status;
2177
2178         i40e_fill_default_direct_cmd_desc(&desc,
2179                                           i40e_aqc_opc_set_phy_debug);
2180
2181         cmd->command_flags = cmd_flags;
2182
2183         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2184
2185         return status;
2186 }
2187
2188 /**
2189  * i40e_aq_add_vsi
2190  * @hw: pointer to the hw struct
2191  * @vsi_ctx: pointer to a vsi context struct
2192  * @cmd_details: pointer to command details structure or NULL
2193  *
2194  * Add a VSI context to the hardware.
2195 **/
2196 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2197                                 struct i40e_vsi_context *vsi_ctx,
2198                                 struct i40e_asq_cmd_details *cmd_details)
2199 {
2200         struct i40e_aq_desc desc;
2201         struct i40e_aqc_add_get_update_vsi *cmd =
2202                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2203         struct i40e_aqc_add_get_update_vsi_completion *resp =
2204                 (struct i40e_aqc_add_get_update_vsi_completion *)
2205                 &desc.params.raw;
2206         enum i40e_status_code status;
2207
2208         i40e_fill_default_direct_cmd_desc(&desc,
2209                                           i40e_aqc_opc_add_vsi);
2210
2211         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2212         cmd->connection_type = vsi_ctx->connection_type;
2213         cmd->vf_id = vsi_ctx->vf_num;
2214         cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2215
2216         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2217
2218         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2219                                     sizeof(vsi_ctx->info), cmd_details);
2220
2221         if (status != I40E_SUCCESS)
2222                 goto aq_add_vsi_exit;
2223
2224         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2225         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2226         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2227         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2228
2229 aq_add_vsi_exit:
2230         return status;
2231 }
2232
2233 /**
2234  * i40e_aq_set_default_vsi
2235  * @hw: pointer to the hw struct
2236  * @seid: vsi number
2237  * @cmd_details: pointer to command details structure or NULL
2238  **/
2239 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2240                                 u16 seid,
2241                                 struct i40e_asq_cmd_details *cmd_details)
2242 {
2243         struct i40e_aq_desc desc;
2244         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2245                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2246                 &desc.params.raw;
2247         enum i40e_status_code status;
2248
2249         i40e_fill_default_direct_cmd_desc(&desc,
2250                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2251
2252         cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2253         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2254         cmd->seid = CPU_TO_LE16(seid);
2255
2256         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2257
2258         return status;
2259 }
2260
2261 /**
2262  * i40e_aq_clear_default_vsi
2263  * @hw: pointer to the hw struct
2264  * @seid: vsi number
2265  * @cmd_details: pointer to command details structure or NULL
2266  **/
2267 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2268                                 u16 seid,
2269                                 struct i40e_asq_cmd_details *cmd_details)
2270 {
2271         struct i40e_aq_desc desc;
2272         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2273                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2274                 &desc.params.raw;
2275         enum i40e_status_code status;
2276
2277         i40e_fill_default_direct_cmd_desc(&desc,
2278                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2279
2280         cmd->promiscuous_flags = CPU_TO_LE16(0);
2281         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2282         cmd->seid = CPU_TO_LE16(seid);
2283
2284         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2285
2286         return status;
2287 }
2288
2289 /**
2290  * i40e_aq_set_vsi_unicast_promiscuous
2291  * @hw: pointer to the hw struct
2292  * @seid: vsi number
2293  * @set: set unicast promiscuous enable/disable
2294  * @cmd_details: pointer to command details structure or NULL
2295  * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2296  **/
2297 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2298                                 u16 seid, bool set,
2299                                 struct i40e_asq_cmd_details *cmd_details,
2300                                 bool rx_only_promisc)
2301 {
2302         struct i40e_aq_desc desc;
2303         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2304                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2305         enum i40e_status_code status;
2306         u16 flags = 0;
2307
2308         i40e_fill_default_direct_cmd_desc(&desc,
2309                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2310
2311         if (set) {
2312                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2313                 if (rx_only_promisc &&
2314                     (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2315                      (hw->aq.api_maj_ver > 1)))
2316                         flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2317         }
2318
2319         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2320
2321         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2322         if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2323              (hw->aq.api_maj_ver > 1))
2324                 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2325
2326         cmd->seid = CPU_TO_LE16(seid);
2327         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2328
2329         return status;
2330 }
2331
2332 /**
2333  * i40e_aq_set_vsi_multicast_promiscuous
2334  * @hw: pointer to the hw struct
2335  * @seid: vsi number
2336  * @set: set multicast promiscuous enable/disable
2337  * @cmd_details: pointer to command details structure or NULL
2338  **/
2339 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2340                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2341 {
2342         struct i40e_aq_desc desc;
2343         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2344                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2345         enum i40e_status_code status;
2346         u16 flags = 0;
2347
2348         i40e_fill_default_direct_cmd_desc(&desc,
2349                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2350
2351         if (set)
2352                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2353
2354         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2355
2356         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2357
2358         cmd->seid = CPU_TO_LE16(seid);
2359         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2360
2361         return status;
2362 }
2363
2364 /**
2365 * i40e_aq_set_vsi_full_promiscuous
2366 * @hw: pointer to the hw struct
2367 * @seid: VSI number
2368 * @set: set promiscuous enable/disable
2369 * @cmd_details: pointer to command details structure or NULL
2370 **/
2371 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw,
2372                                 u16 seid, bool set,
2373                                 struct i40e_asq_cmd_details *cmd_details)
2374 {
2375         struct i40e_aq_desc desc;
2376         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2377                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2378         enum i40e_status_code status;
2379         u16 flags = 0;
2380
2381         i40e_fill_default_direct_cmd_desc(&desc,
2382                 i40e_aqc_opc_set_vsi_promiscuous_modes);
2383
2384         if (set)
2385                 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2386                         I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2387                         I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2388
2389         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2390
2391         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2392                                        I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2393                                        I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2394
2395         cmd->seid = CPU_TO_LE16(seid);
2396         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2397
2398         return status;
2399 }
2400
2401 /**
2402  * i40e_aq_set_vsi_mc_promisc_on_vlan
2403  * @hw: pointer to the hw struct
2404  * @seid: vsi number
2405  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2406  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2407  * @cmd_details: pointer to command details structure or NULL
2408  **/
2409 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2410                                 u16 seid, bool enable, u16 vid,
2411                                 struct i40e_asq_cmd_details *cmd_details)
2412 {
2413         struct i40e_aq_desc desc;
2414         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2415                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2416         enum i40e_status_code status;
2417         u16 flags = 0;
2418
2419         i40e_fill_default_direct_cmd_desc(&desc,
2420                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2421
2422         if (enable)
2423                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2424
2425         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2426         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2427         cmd->seid = CPU_TO_LE16(seid);
2428         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2429
2430         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2431
2432         return status;
2433 }
2434
2435 /**
2436  * i40e_aq_set_vsi_uc_promisc_on_vlan
2437  * @hw: pointer to the hw struct
2438  * @seid: vsi number
2439  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2440  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2441  * @cmd_details: pointer to command details structure or NULL
2442  **/
2443 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2444                                 u16 seid, bool enable, u16 vid,
2445                                 struct i40e_asq_cmd_details *cmd_details)
2446 {
2447         struct i40e_aq_desc desc;
2448         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2449                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2450         enum i40e_status_code status;
2451         u16 flags = 0;
2452
2453         i40e_fill_default_direct_cmd_desc(&desc,
2454                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2455
2456         if (enable)
2457                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2458
2459         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2460         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2461         cmd->seid = CPU_TO_LE16(seid);
2462         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2463
2464         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2465
2466         return status;
2467 }
2468
2469 /**
2470  * i40e_aq_set_vsi_bc_promisc_on_vlan
2471  * @hw: pointer to the hw struct
2472  * @seid: vsi number
2473  * @enable: set broadcast promiscuous enable/disable for a given VLAN
2474  * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2475  * @cmd_details: pointer to command details structure or NULL
2476  **/
2477 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2478                                 u16 seid, bool enable, u16 vid,
2479                                 struct i40e_asq_cmd_details *cmd_details)
2480 {
2481         struct i40e_aq_desc desc;
2482         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2483                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2484         enum i40e_status_code status;
2485         u16 flags = 0;
2486
2487         i40e_fill_default_direct_cmd_desc(&desc,
2488                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2489
2490         if (enable)
2491                 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2492
2493         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2494         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2495         cmd->seid = CPU_TO_LE16(seid);
2496         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2497
2498         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2499
2500         return status;
2501 }
2502
2503 /**
2504  * i40e_aq_set_vsi_broadcast
2505  * @hw: pointer to the hw struct
2506  * @seid: vsi number
2507  * @set_filter: true to set filter, false to clear filter
2508  * @cmd_details: pointer to command details structure or NULL
2509  *
2510  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2511  **/
2512 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2513                                 u16 seid, bool set_filter,
2514                                 struct i40e_asq_cmd_details *cmd_details)
2515 {
2516         struct i40e_aq_desc desc;
2517         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2518                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2519         enum i40e_status_code status;
2520
2521         i40e_fill_default_direct_cmd_desc(&desc,
2522                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2523
2524         if (set_filter)
2525                 cmd->promiscuous_flags
2526                             |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2527         else
2528                 cmd->promiscuous_flags
2529                             &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2530
2531         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2532         cmd->seid = CPU_TO_LE16(seid);
2533         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2534
2535         return status;
2536 }
2537
2538 /**
2539  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2540  * @hw: pointer to the hw struct
2541  * @seid: vsi number
2542  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2543  * @cmd_details: pointer to command details structure or NULL
2544  **/
2545 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2546                                 u16 seid, bool enable,
2547                                 struct i40e_asq_cmd_details *cmd_details)
2548 {
2549         struct i40e_aq_desc desc;
2550         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2551                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2552         enum i40e_status_code status;
2553         u16 flags = 0;
2554
2555         i40e_fill_default_direct_cmd_desc(&desc,
2556                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2557         if (enable)
2558                 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2559
2560         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2561         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2562         cmd->seid = CPU_TO_LE16(seid);
2563
2564         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2565
2566         return status;
2567 }
2568
2569 /**
2570  * i40e_get_vsi_params - get VSI configuration info
2571  * @hw: pointer to the hw struct
2572  * @vsi_ctx: pointer to a vsi context struct
2573  * @cmd_details: pointer to command details structure or NULL
2574  **/
2575 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2576                                 struct i40e_vsi_context *vsi_ctx,
2577                                 struct i40e_asq_cmd_details *cmd_details)
2578 {
2579         struct i40e_aq_desc desc;
2580         struct i40e_aqc_add_get_update_vsi *cmd =
2581                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2582         struct i40e_aqc_add_get_update_vsi_completion *resp =
2583                 (struct i40e_aqc_add_get_update_vsi_completion *)
2584                 &desc.params.raw;
2585         enum i40e_status_code status;
2586
2587         UNREFERENCED_1PARAMETER(cmd_details);
2588         i40e_fill_default_direct_cmd_desc(&desc,
2589                                           i40e_aqc_opc_get_vsi_parameters);
2590
2591         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2592
2593         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2594
2595         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2596                                     sizeof(vsi_ctx->info), NULL);
2597
2598         if (status != I40E_SUCCESS)
2599                 goto aq_get_vsi_params_exit;
2600
2601         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2602         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2603         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2604         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2605
2606 aq_get_vsi_params_exit:
2607         return status;
2608 }
2609
2610 /**
2611  * i40e_aq_update_vsi_params
2612  * @hw: pointer to the hw struct
2613  * @vsi_ctx: pointer to a vsi context struct
2614  * @cmd_details: pointer to command details structure or NULL
2615  *
2616  * Update a VSI context.
2617  **/
2618 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2619                                 struct i40e_vsi_context *vsi_ctx,
2620                                 struct i40e_asq_cmd_details *cmd_details)
2621 {
2622         struct i40e_aq_desc desc;
2623         struct i40e_aqc_add_get_update_vsi *cmd =
2624                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2625         struct i40e_aqc_add_get_update_vsi_completion *resp =
2626                 (struct i40e_aqc_add_get_update_vsi_completion *)
2627                 &desc.params.raw;
2628         enum i40e_status_code status;
2629
2630         i40e_fill_default_direct_cmd_desc(&desc,
2631                                           i40e_aqc_opc_update_vsi_parameters);
2632         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2633
2634         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2635
2636         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2637                                     sizeof(vsi_ctx->info), cmd_details);
2638
2639         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2640         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2641
2642         return status;
2643 }
2644
2645 /**
2646  * i40e_aq_get_switch_config
2647  * @hw: pointer to the hardware structure
2648  * @buf: pointer to the result buffer
2649  * @buf_size: length of input buffer
2650  * @start_seid: seid to start for the report, 0 == beginning
2651  * @cmd_details: pointer to command details structure or NULL
2652  *
2653  * Fill the buf with switch configuration returned from AdminQ command
2654  **/
2655 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2656                                 struct i40e_aqc_get_switch_config_resp *buf,
2657                                 u16 buf_size, u16 *start_seid,
2658                                 struct i40e_asq_cmd_details *cmd_details)
2659 {
2660         struct i40e_aq_desc desc;
2661         struct i40e_aqc_switch_seid *scfg =
2662                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2663         enum i40e_status_code status;
2664
2665         i40e_fill_default_direct_cmd_desc(&desc,
2666                                           i40e_aqc_opc_get_switch_config);
2667         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2668         if (buf_size > I40E_AQ_LARGE_BUF)
2669                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2670         scfg->seid = CPU_TO_LE16(*start_seid);
2671
2672         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2673         *start_seid = LE16_TO_CPU(scfg->seid);
2674
2675         return status;
2676 }
2677
2678 /**
2679  * i40e_aq_set_switch_config
2680  * @hw: pointer to the hardware structure
2681  * @flags: bit flag values to set
2682  * @valid_flags: which bit flags to set
2683  * @cmd_details: pointer to command details structure or NULL
2684  *
2685  * Set switch configuration bits
2686  **/
2687 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2688                                 u16 flags, u16 valid_flags,
2689                                 struct i40e_asq_cmd_details *cmd_details)
2690 {
2691         struct i40e_aq_desc desc;
2692         struct i40e_aqc_set_switch_config *scfg =
2693                 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2694         enum i40e_status_code status;
2695
2696         i40e_fill_default_direct_cmd_desc(&desc,
2697                                           i40e_aqc_opc_set_switch_config);
2698         scfg->flags = CPU_TO_LE16(flags);
2699         scfg->valid_flags = CPU_TO_LE16(valid_flags);
2700         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
2701                 scfg->switch_tag = CPU_TO_LE16(hw->switch_tag);
2702                 scfg->first_tag = CPU_TO_LE16(hw->first_tag);
2703                 scfg->second_tag = CPU_TO_LE16(hw->second_tag);
2704         }
2705         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2706
2707         return status;
2708 }
2709
2710 /**
2711  * i40e_aq_get_firmware_version
2712  * @hw: pointer to the hw struct
2713  * @fw_major_version: firmware major version
2714  * @fw_minor_version: firmware minor version
2715  * @fw_build: firmware build number
2716  * @api_major_version: major queue version
2717  * @api_minor_version: minor queue version
2718  * @cmd_details: pointer to command details structure or NULL
2719  *
2720  * Get the firmware version from the admin queue commands
2721  **/
2722 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2723                                 u16 *fw_major_version, u16 *fw_minor_version,
2724                                 u32 *fw_build,
2725                                 u16 *api_major_version, u16 *api_minor_version,
2726                                 struct i40e_asq_cmd_details *cmd_details)
2727 {
2728         struct i40e_aq_desc desc;
2729         struct i40e_aqc_get_version *resp =
2730                 (struct i40e_aqc_get_version *)&desc.params.raw;
2731         enum i40e_status_code status;
2732
2733         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2734
2735         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2736
2737         if (status == I40E_SUCCESS) {
2738                 if (fw_major_version != NULL)
2739                         *fw_major_version = LE16_TO_CPU(resp->fw_major);
2740                 if (fw_minor_version != NULL)
2741                         *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2742                 if (fw_build != NULL)
2743                         *fw_build = LE32_TO_CPU(resp->fw_build);
2744                 if (api_major_version != NULL)
2745                         *api_major_version = LE16_TO_CPU(resp->api_major);
2746                 if (api_minor_version != NULL)
2747                         *api_minor_version = LE16_TO_CPU(resp->api_minor);
2748
2749                 /* A workaround to fix the API version in SW */
2750                 if (api_major_version && api_minor_version &&
2751                     fw_major_version && fw_minor_version &&
2752                     ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2753                     (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2754                      (*fw_major_version > 4)))
2755                         *api_minor_version = 2;
2756         }
2757
2758         return status;
2759 }
2760
2761 /**
2762  * i40e_aq_send_driver_version
2763  * @hw: pointer to the hw struct
2764  * @dv: driver's major, minor version
2765  * @cmd_details: pointer to command details structure or NULL
2766  *
2767  * Send the driver version to the firmware
2768  **/
2769 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2770                                 struct i40e_driver_version *dv,
2771                                 struct i40e_asq_cmd_details *cmd_details)
2772 {
2773         struct i40e_aq_desc desc;
2774         struct i40e_aqc_driver_version *cmd =
2775                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2776         enum i40e_status_code status;
2777         u16 len;
2778
2779         if (dv == NULL)
2780                 return I40E_ERR_PARAM;
2781
2782         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2783
2784         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2785         cmd->driver_major_ver = dv->major_version;
2786         cmd->driver_minor_ver = dv->minor_version;
2787         cmd->driver_build_ver = dv->build_version;
2788         cmd->driver_subbuild_ver = dv->subbuild_version;
2789
2790         len = 0;
2791         while (len < sizeof(dv->driver_string) &&
2792                (dv->driver_string[len] < 0x80) &&
2793                dv->driver_string[len])
2794                 len++;
2795         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2796                                        len, cmd_details);
2797
2798         return status;
2799 }
2800
2801 /**
2802  * i40e_get_link_status - get status of the HW network link
2803  * @hw: pointer to the hw struct
2804  * @link_up: pointer to bool (true/false = linkup/linkdown)
2805  *
2806  * Variable link_up true if link is up, false if link is down.
2807  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2808  *
2809  * Side effect: LinkStatusEvent reporting becomes enabled
2810  **/
2811 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2812 {
2813         enum i40e_status_code status = I40E_SUCCESS;
2814
2815         if (hw->phy.get_link_info) {
2816                 status = i40e_update_link_info(hw);
2817
2818                 if (status != I40E_SUCCESS)
2819                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2820                                    status);
2821         }
2822
2823         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2824
2825         return status;
2826 }
2827
2828 /**
2829  * i40e_updatelink_status - update status of the HW network link
2830  * @hw: pointer to the hw struct
2831  **/
2832 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2833 {
2834         struct i40e_aq_get_phy_abilities_resp abilities;
2835         enum i40e_status_code status = I40E_SUCCESS;
2836
2837         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2838         if (status)
2839                 return status;
2840
2841         /* extra checking needed to ensure link info to user is timely */
2842         if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2843             ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2844              !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2845                 status = i40e_aq_get_phy_capabilities(hw, false, false,
2846                                                       &abilities, NULL);
2847                 if (status)
2848                         return status;
2849
2850                 hw->phy.link_info.req_fec_info =
2851                         abilities.fec_cfg_curr_mod_ext_info &
2852                         (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS);
2853
2854                 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2855                         sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2856         }
2857         return status;
2858 }
2859
2860
2861 /**
2862  * i40e_get_link_speed
2863  * @hw: pointer to the hw struct
2864  *
2865  * Returns the link speed of the adapter.
2866  **/
2867 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2868 {
2869         enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2870         enum i40e_status_code status = I40E_SUCCESS;
2871
2872         if (hw->phy.get_link_info) {
2873                 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2874
2875                 if (status != I40E_SUCCESS)
2876                         goto i40e_link_speed_exit;
2877         }
2878
2879         speed = hw->phy.link_info.link_speed;
2880
2881 i40e_link_speed_exit:
2882         return speed;
2883 }
2884
2885 /**
2886  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2887  * @hw: pointer to the hw struct
2888  * @uplink_seid: the MAC or other gizmo SEID
2889  * @downlink_seid: the VSI SEID
2890  * @enabled_tc: bitmap of TCs to be enabled
2891  * @default_port: true for default port VSI, false for control port
2892  * @veb_seid: pointer to where to put the resulting VEB SEID
2893  * @enable_stats: true to turn on VEB stats
2894  * @cmd_details: pointer to command details structure or NULL
2895  *
2896  * This asks the FW to add a VEB between the uplink and downlink
2897  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2898  **/
2899 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2900                                 u16 downlink_seid, u8 enabled_tc,
2901                                 bool default_port, u16 *veb_seid,
2902                                 bool enable_stats,
2903                                 struct i40e_asq_cmd_details *cmd_details)
2904 {
2905         struct i40e_aq_desc desc;
2906         struct i40e_aqc_add_veb *cmd =
2907                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2908         struct i40e_aqc_add_veb_completion *resp =
2909                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2910         enum i40e_status_code status;
2911         u16 veb_flags = 0;
2912
2913         /* SEIDs need to either both be set or both be 0 for floating VEB */
2914         if (!!uplink_seid != !!downlink_seid)
2915                 return I40E_ERR_PARAM;
2916
2917         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2918
2919         cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2920         cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2921         cmd->enable_tcs = enabled_tc;
2922         if (!uplink_seid)
2923                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2924         if (default_port)
2925                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2926         else
2927                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2928
2929         /* reverse logic here: set the bitflag to disable the stats */
2930         if (!enable_stats)
2931                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2932
2933         cmd->veb_flags = CPU_TO_LE16(veb_flags);
2934
2935         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2936
2937         if (!status && veb_seid)
2938                 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2939
2940         return status;
2941 }
2942
2943 /**
2944  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2945  * @hw: pointer to the hw struct
2946  * @veb_seid: the SEID of the VEB to query
2947  * @switch_id: the uplink switch id
2948  * @floating: set to true if the VEB is floating
2949  * @statistic_index: index of the stats counter block for this VEB
2950  * @vebs_used: number of VEB's used by function
2951  * @vebs_free: total VEB's not reserved by any function
2952  * @cmd_details: pointer to command details structure or NULL
2953  *
2954  * This retrieves the parameters for a particular VEB, specified by
2955  * uplink_seid, and returns them to the caller.
2956  **/
2957 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2958                                 u16 veb_seid, u16 *switch_id,
2959                                 bool *floating, u16 *statistic_index,
2960                                 u16 *vebs_used, u16 *vebs_free,
2961                                 struct i40e_asq_cmd_details *cmd_details)
2962 {
2963         struct i40e_aq_desc desc;
2964         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2965                 (struct i40e_aqc_get_veb_parameters_completion *)
2966                 &desc.params.raw;
2967         enum i40e_status_code status;
2968
2969         if (veb_seid == 0)
2970                 return I40E_ERR_PARAM;
2971
2972         i40e_fill_default_direct_cmd_desc(&desc,
2973                                           i40e_aqc_opc_get_veb_parameters);
2974         cmd_resp->seid = CPU_TO_LE16(veb_seid);
2975
2976         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2977         if (status)
2978                 goto get_veb_exit;
2979
2980         if (switch_id)
2981                 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2982         if (statistic_index)
2983                 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2984         if (vebs_used)
2985                 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2986         if (vebs_free)
2987                 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2988         if (floating) {
2989                 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2990
2991                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2992                         *floating = true;
2993                 else
2994                         *floating = false;
2995         }
2996
2997 get_veb_exit:
2998         return status;
2999 }
3000
3001 /**
3002  * i40e_aq_add_macvlan
3003  * @hw: pointer to the hw struct
3004  * @seid: VSI for the mac address
3005  * @mv_list: list of macvlans to be added
3006  * @count: length of the list
3007  * @cmd_details: pointer to command details structure or NULL
3008  *
3009  * Add MAC/VLAN addresses to the HW filtering
3010  **/
3011 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
3012                         struct i40e_aqc_add_macvlan_element_data *mv_list,
3013                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3014 {
3015         struct i40e_aq_desc desc;
3016         struct i40e_aqc_macvlan *cmd =
3017                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3018         enum i40e_status_code status;
3019         u16 buf_size;
3020         int i;
3021
3022         if (count == 0 || !mv_list || !hw)
3023                 return I40E_ERR_PARAM;
3024
3025         buf_size = count * sizeof(*mv_list);
3026
3027         /* prep the rest of the request */
3028         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
3029         cmd->num_addresses = CPU_TO_LE16(count);
3030         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3031         cmd->seid[1] = 0;
3032         cmd->seid[2] = 0;
3033
3034         for (i = 0; i < count; i++)
3035                 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
3036                         mv_list[i].flags |=
3037                             CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
3038
3039         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3040         if (buf_size > I40E_AQ_LARGE_BUF)
3041                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3042
3043         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3044                                        cmd_details);
3045
3046         return status;
3047 }
3048
3049 /**
3050  * i40e_aq_remove_macvlan
3051  * @hw: pointer to the hw struct
3052  * @seid: VSI for the mac address
3053  * @mv_list: list of macvlans to be removed
3054  * @count: length of the list
3055  * @cmd_details: pointer to command details structure or NULL
3056  *
3057  * Remove MAC/VLAN addresses from the HW filtering
3058  **/
3059 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
3060                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
3061                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3062 {
3063         struct i40e_aq_desc desc;
3064         struct i40e_aqc_macvlan *cmd =
3065                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3066         enum i40e_status_code status;
3067         u16 buf_size;
3068
3069         if (count == 0 || !mv_list || !hw)
3070                 return I40E_ERR_PARAM;
3071
3072         buf_size = count * sizeof(*mv_list);
3073
3074         /* prep the rest of the request */
3075         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
3076         cmd->num_addresses = CPU_TO_LE16(count);
3077         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3078         cmd->seid[1] = 0;
3079         cmd->seid[2] = 0;
3080
3081         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3082         if (buf_size > I40E_AQ_LARGE_BUF)
3083                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3084
3085         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3086                                        cmd_details);
3087
3088         return status;
3089 }
3090
3091 /**
3092  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3093  * @hw: pointer to the hw struct
3094  * @opcode: AQ opcode for add or delete mirror rule
3095  * @sw_seid: Switch SEID (to which rule refers)
3096  * @rule_type: Rule Type (ingress/egress/VLAN)
3097  * @id: Destination VSI SEID or Rule ID
3098  * @count: length of the list
3099  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3100  * @cmd_details: pointer to command details structure or NULL
3101  * @rule_id: Rule ID returned from FW
3102  * @rule_used: Number of rules used in internal switch
3103  * @rule_free: Number of rules free in internal switch
3104  *
3105  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3106  * VEBs/VEPA elements only
3107  **/
3108 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3109                         u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3110                         u16 count, __le16 *mr_list,
3111                         struct i40e_asq_cmd_details *cmd_details,
3112                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3113 {
3114         struct i40e_aq_desc desc;
3115         struct i40e_aqc_add_delete_mirror_rule *cmd =
3116                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3117         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3118         (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3119         enum i40e_status_code status;
3120         u16 buf_size;
3121
3122         buf_size = count * sizeof(*mr_list);
3123
3124         /* prep the rest of the request */
3125         i40e_fill_default_direct_cmd_desc(&desc, opcode);
3126         cmd->seid = CPU_TO_LE16(sw_seid);
3127         cmd->rule_type = CPU_TO_LE16(rule_type &
3128                                      I40E_AQC_MIRROR_RULE_TYPE_MASK);
3129         cmd->num_entries = CPU_TO_LE16(count);
3130         /* Dest VSI for add, rule_id for delete */
3131         cmd->destination = CPU_TO_LE16(id);
3132         if (mr_list) {
3133                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3134                                                 I40E_AQ_FLAG_RD));
3135                 if (buf_size > I40E_AQ_LARGE_BUF)
3136                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3137         }
3138
3139         status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3140                                        cmd_details);
3141         if (status == I40E_SUCCESS ||
3142             hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3143                 if (rule_id)
3144                         *rule_id = LE16_TO_CPU(resp->rule_id);
3145                 if (rules_used)
3146                         *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3147                 if (rules_free)
3148                         *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3149         }
3150         return status;
3151 }
3152
3153 /**
3154  * i40e_aq_add_mirrorrule - add a mirror rule
3155  * @hw: pointer to the hw struct
3156  * @sw_seid: Switch SEID (to which rule refers)
3157  * @rule_type: Rule Type (ingress/egress/VLAN)
3158  * @dest_vsi: SEID of VSI to which packets will be mirrored
3159  * @count: length of the list
3160  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3161  * @cmd_details: pointer to command details structure or NULL
3162  * @rule_id: Rule ID returned from FW
3163  * @rule_used: Number of rules used in internal switch
3164  * @rule_free: Number of rules free in internal switch
3165  *
3166  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3167  **/
3168 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3169                         u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3170                         struct i40e_asq_cmd_details *cmd_details,
3171                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3172 {
3173         if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3174             rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3175                 if (count == 0 || !mr_list)
3176                         return I40E_ERR_PARAM;
3177         }
3178
3179         return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3180                                   rule_type, dest_vsi, count, mr_list,
3181                                   cmd_details, rule_id, rules_used, rules_free);
3182 }
3183
3184 /**
3185  * i40e_aq_delete_mirrorrule - delete a mirror rule
3186  * @hw: pointer to the hw struct
3187  * @sw_seid: Switch SEID (to which rule refers)
3188  * @rule_type: Rule Type (ingress/egress/VLAN)
3189  * @count: length of the list
3190  * @rule_id: Rule ID that is returned in the receive desc as part of
3191  *              add_mirrorrule.
3192  * @mr_list: list of mirrored VLAN IDs to be removed
3193  * @cmd_details: pointer to command details structure or NULL
3194  * @rule_used: Number of rules used in internal switch
3195  * @rule_free: Number of rules free in internal switch
3196  *
3197  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3198  **/
3199 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3200                         u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3201                         struct i40e_asq_cmd_details *cmd_details,
3202                         u16 *rules_used, u16 *rules_free)
3203 {
3204         /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3205         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3206                 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3207                  * mirroring. For other rule_type, count and rule_type should
3208                  * not matter.
3209                  */
3210                 if (count == 0 || !mr_list)
3211                         return I40E_ERR_PARAM;
3212         }
3213
3214         return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3215                                   rule_type, rule_id, count, mr_list,
3216                                   cmd_details, NULL, rules_used, rules_free);
3217 }
3218
3219 /**
3220  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3221  * @hw: pointer to the hw struct
3222  * @seid: VSI for the vlan filters
3223  * @v_list: list of vlan filters to be added
3224  * @count: length of the list
3225  * @cmd_details: pointer to command details structure or NULL
3226  **/
3227 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3228                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3229                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3230 {
3231         struct i40e_aq_desc desc;
3232         struct i40e_aqc_macvlan *cmd =
3233                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3234         enum i40e_status_code status;
3235         u16 buf_size;
3236
3237         if (count == 0 || !v_list || !hw)
3238                 return I40E_ERR_PARAM;
3239
3240         buf_size = count * sizeof(*v_list);
3241
3242         /* prep the rest of the request */
3243         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3244         cmd->num_addresses = CPU_TO_LE16(count);
3245         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3246         cmd->seid[1] = 0;
3247         cmd->seid[2] = 0;
3248
3249         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3250         if (buf_size > I40E_AQ_LARGE_BUF)
3251                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3252
3253         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3254                                        cmd_details);
3255
3256         return status;
3257 }
3258
3259 /**
3260  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3261  * @hw: pointer to the hw struct
3262  * @seid: VSI for the vlan filters
3263  * @v_list: list of macvlans to be removed
3264  * @count: length of the list
3265  * @cmd_details: pointer to command details structure or NULL
3266  **/
3267 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3268                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3269                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3270 {
3271         struct i40e_aq_desc desc;
3272         struct i40e_aqc_macvlan *cmd =
3273                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3274         enum i40e_status_code status;
3275         u16 buf_size;
3276
3277         if (count == 0 || !v_list || !hw)
3278                 return I40E_ERR_PARAM;
3279
3280         buf_size = count * sizeof(*v_list);
3281
3282         /* prep the rest of the request */
3283         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3284         cmd->num_addresses = CPU_TO_LE16(count);
3285         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3286         cmd->seid[1] = 0;
3287         cmd->seid[2] = 0;
3288
3289         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3290         if (buf_size > I40E_AQ_LARGE_BUF)
3291                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3292
3293         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3294                                        cmd_details);
3295
3296         return status;
3297 }
3298
3299 /**
3300  * i40e_aq_send_msg_to_vf
3301  * @hw: pointer to the hardware structure
3302  * @vfid: vf id to send msg
3303  * @v_opcode: opcodes for VF-PF communication
3304  * @v_retval: return error code
3305  * @msg: pointer to the msg buffer
3306  * @msglen: msg length
3307  * @cmd_details: pointer to command details
3308  *
3309  * send msg to vf
3310  **/
3311 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3312                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3313                                 struct i40e_asq_cmd_details *cmd_details)
3314 {
3315         struct i40e_aq_desc desc;
3316         struct i40e_aqc_pf_vf_message *cmd =
3317                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3318         enum i40e_status_code status;
3319
3320         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3321         cmd->id = CPU_TO_LE32(vfid);
3322         desc.cookie_high = CPU_TO_LE32(v_opcode);
3323         desc.cookie_low = CPU_TO_LE32(v_retval);
3324         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3325         if (msglen) {
3326                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3327                                                 I40E_AQ_FLAG_RD));
3328                 if (msglen > I40E_AQ_LARGE_BUF)
3329                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3330                 desc.datalen = CPU_TO_LE16(msglen);
3331         }
3332         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3333
3334         return status;
3335 }
3336
3337 /**
3338  * i40e_aq_debug_read_register
3339  * @hw: pointer to the hw struct
3340  * @reg_addr: register address
3341  * @reg_val: register value
3342  * @cmd_details: pointer to command details structure or NULL
3343  *
3344  * Read the register using the admin queue commands
3345  **/
3346 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3347                                 u32 reg_addr, u64 *reg_val,
3348                                 struct i40e_asq_cmd_details *cmd_details)
3349 {
3350         struct i40e_aq_desc desc;
3351         struct i40e_aqc_debug_reg_read_write *cmd_resp =
3352                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3353         enum i40e_status_code status;
3354
3355         if (reg_val == NULL)
3356                 return I40E_ERR_PARAM;
3357
3358         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3359
3360         cmd_resp->address = CPU_TO_LE32(reg_addr);
3361
3362         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3363
3364         if (status == I40E_SUCCESS) {
3365                 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3366                            (u64)LE32_TO_CPU(cmd_resp->value_low);
3367         }
3368
3369         return status;
3370 }
3371
3372 /**
3373  * i40e_aq_debug_write_register
3374  * @hw: pointer to the hw struct
3375  * @reg_addr: register address
3376  * @reg_val: register value
3377  * @cmd_details: pointer to command details structure or NULL
3378  *
3379  * Write to a register using the admin queue commands
3380  **/
3381 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3382                                 u32 reg_addr, u64 reg_val,
3383                                 struct i40e_asq_cmd_details *cmd_details)
3384 {
3385         struct i40e_aq_desc desc;
3386         struct i40e_aqc_debug_reg_read_write *cmd =
3387                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3388         enum i40e_status_code status;
3389
3390         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3391
3392         cmd->address = CPU_TO_LE32(reg_addr);
3393         cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3394         cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3395
3396         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3397
3398         return status;
3399 }
3400
3401 /**
3402  * i40e_aq_request_resource
3403  * @hw: pointer to the hw struct
3404  * @resource: resource id
3405  * @access: access type
3406  * @sdp_number: resource number
3407  * @timeout: the maximum time in ms that the driver may hold the resource
3408  * @cmd_details: pointer to command details structure or NULL
3409  *
3410  * requests common resource using the admin queue commands
3411  **/
3412 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3413                                 enum i40e_aq_resources_ids resource,
3414                                 enum i40e_aq_resource_access_type access,
3415                                 u8 sdp_number, u64 *timeout,
3416                                 struct i40e_asq_cmd_details *cmd_details)
3417 {
3418         struct i40e_aq_desc desc;
3419         struct i40e_aqc_request_resource *cmd_resp =
3420                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3421         enum i40e_status_code status;
3422
3423         DEBUGFUNC("i40e_aq_request_resource");
3424
3425         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3426
3427         cmd_resp->resource_id = CPU_TO_LE16(resource);
3428         cmd_resp->access_type = CPU_TO_LE16(access);
3429         cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3430
3431         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3432         /* The completion specifies the maximum time in ms that the driver
3433          * may hold the resource in the Timeout field.
3434          * If the resource is held by someone else, the command completes with
3435          * busy return value and the timeout field indicates the maximum time
3436          * the current owner of the resource has to free it.
3437          */
3438         if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3439                 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3440
3441         return status;
3442 }
3443
3444 /**
3445  * i40e_aq_release_resource
3446  * @hw: pointer to the hw struct
3447  * @resource: resource id
3448  * @sdp_number: resource number
3449  * @cmd_details: pointer to command details structure or NULL
3450  *
3451  * release common resource using the admin queue commands
3452  **/
3453 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3454                                 enum i40e_aq_resources_ids resource,
3455                                 u8 sdp_number,
3456                                 struct i40e_asq_cmd_details *cmd_details)
3457 {
3458         struct i40e_aq_desc desc;
3459         struct i40e_aqc_request_resource *cmd =
3460                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3461         enum i40e_status_code status;
3462
3463         DEBUGFUNC("i40e_aq_release_resource");
3464
3465         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3466
3467         cmd->resource_id = CPU_TO_LE16(resource);
3468         cmd->resource_number = CPU_TO_LE32(sdp_number);
3469
3470         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3471
3472         return status;
3473 }
3474
3475 /**
3476  * i40e_aq_read_nvm
3477  * @hw: pointer to the hw struct
3478  * @module_pointer: module pointer location in words from the NVM beginning
3479  * @offset: byte offset from the module beginning
3480  * @length: length of the section to be read (in bytes from the offset)
3481  * @data: command buffer (size [bytes] = length)
3482  * @last_command: tells if this is the last command in a series
3483  * @cmd_details: pointer to command details structure or NULL
3484  *
3485  * Read the NVM using the admin queue commands
3486  **/
3487 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3488                                 u32 offset, u16 length, void *data,
3489                                 bool last_command,
3490                                 struct i40e_asq_cmd_details *cmd_details)
3491 {
3492         struct i40e_aq_desc desc;
3493         struct i40e_aqc_nvm_update *cmd =
3494                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3495         enum i40e_status_code status;
3496
3497         DEBUGFUNC("i40e_aq_read_nvm");
3498
3499         /* In offset the highest byte must be zeroed. */
3500         if (offset & 0xFF000000) {
3501                 status = I40E_ERR_PARAM;
3502                 goto i40e_aq_read_nvm_exit;
3503         }
3504
3505         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3506
3507         /* If this is the last command in a series, set the proper flag. */
3508         if (last_command)
3509                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3510         cmd->module_pointer = module_pointer;
3511         cmd->offset = CPU_TO_LE32(offset);
3512         cmd->length = CPU_TO_LE16(length);
3513
3514         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3515         if (length > I40E_AQ_LARGE_BUF)
3516                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3517
3518         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3519
3520 i40e_aq_read_nvm_exit:
3521         return status;
3522 }
3523
3524 /**
3525  * i40e_aq_read_nvm_config - read an nvm config block
3526  * @hw: pointer to the hw struct
3527  * @cmd_flags: NVM access admin command bits
3528  * @field_id: field or feature id
3529  * @data: buffer for result
3530  * @buf_size: buffer size
3531  * @element_count: pointer to count of elements read by FW
3532  * @cmd_details: pointer to command details structure or NULL
3533  **/
3534 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3535                                 u8 cmd_flags, u32 field_id, void *data,
3536                                 u16 buf_size, u16 *element_count,
3537                                 struct i40e_asq_cmd_details *cmd_details)
3538 {
3539         struct i40e_aq_desc desc;
3540         struct i40e_aqc_nvm_config_read *cmd =
3541                 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3542         enum i40e_status_code status;
3543
3544         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3545         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3546         if (buf_size > I40E_AQ_LARGE_BUF)
3547                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3548
3549         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3550         cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3551         if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3552                 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3553         else
3554                 cmd->element_id_msw = 0;
3555
3556         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3557
3558         if (!status && element_count)
3559                 *element_count = LE16_TO_CPU(cmd->element_count);
3560
3561         return status;
3562 }
3563
3564 /**
3565  * i40e_aq_write_nvm_config - write an nvm config block
3566  * @hw: pointer to the hw struct
3567  * @cmd_flags: NVM access admin command bits
3568  * @data: buffer for result
3569  * @buf_size: buffer size
3570  * @element_count: count of elements to be written
3571  * @cmd_details: pointer to command details structure or NULL
3572  **/
3573 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3574                                 u8 cmd_flags, void *data, u16 buf_size,
3575                                 u16 element_count,
3576                                 struct i40e_asq_cmd_details *cmd_details)
3577 {
3578         struct i40e_aq_desc desc;
3579         struct i40e_aqc_nvm_config_write *cmd =
3580                 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3581         enum i40e_status_code status;
3582
3583         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3584         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3585         if (buf_size > I40E_AQ_LARGE_BUF)
3586                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3587
3588         cmd->element_count = CPU_TO_LE16(element_count);
3589         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3590         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3591
3592         return status;
3593 }
3594
3595 /**
3596  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3597  * @hw: pointer to the hw struct
3598  * @cmd_details: pointer to command details structure or NULL
3599  **/
3600 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3601                                 void *buff, u16 buff_size,
3602                                 struct i40e_asq_cmd_details *cmd_details)
3603 {
3604         struct i40e_aq_desc desc;
3605         enum i40e_status_code status;
3606
3607         UNREFERENCED_2PARAMETER(buff, buff_size);
3608
3609         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3610         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3611         if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3612                 status = I40E_ERR_NOT_IMPLEMENTED;
3613
3614         return status;
3615 }
3616
3617 /**
3618  * i40e_aq_erase_nvm
3619  * @hw: pointer to the hw struct
3620  * @module_pointer: module pointer location in words from the NVM beginning
3621  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3622  * @length: length of the section to be erased (expressed in 4 KB)
3623  * @last_command: tells if this is the last command in a series
3624  * @cmd_details: pointer to command details structure or NULL
3625  *
3626  * Erase the NVM sector using the admin queue commands
3627  **/
3628 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3629                                 u32 offset, u16 length, bool last_command,
3630                                 struct i40e_asq_cmd_details *cmd_details)
3631 {
3632         struct i40e_aq_desc desc;
3633         struct i40e_aqc_nvm_update *cmd =
3634                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3635         enum i40e_status_code status;
3636
3637         DEBUGFUNC("i40e_aq_erase_nvm");
3638
3639         /* In offset the highest byte must be zeroed. */
3640         if (offset & 0xFF000000) {
3641                 status = I40E_ERR_PARAM;
3642                 goto i40e_aq_erase_nvm_exit;
3643         }
3644
3645         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3646
3647         /* If this is the last command in a series, set the proper flag. */
3648         if (last_command)
3649                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3650         cmd->module_pointer = module_pointer;
3651         cmd->offset = CPU_TO_LE32(offset);
3652         cmd->length = CPU_TO_LE16(length);
3653
3654         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3655
3656 i40e_aq_erase_nvm_exit:
3657         return status;
3658 }
3659
3660 /**
3661  * i40e_parse_discover_capabilities
3662  * @hw: pointer to the hw struct
3663  * @buff: pointer to a buffer containing device/function capability records
3664  * @cap_count: number of capability records in the list
3665  * @list_type_opc: type of capabilities list to parse
3666  *
3667  * Parse the device/function capabilities list.
3668  **/
3669 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3670                                      u32 cap_count,
3671                                      enum i40e_admin_queue_opc list_type_opc)
3672 {
3673         struct i40e_aqc_list_capabilities_element_resp *cap;
3674         u32 valid_functions, num_functions;
3675         u32 number, logical_id, phys_id;
3676         struct i40e_hw_capabilities *p;
3677         u8 major_rev;
3678         u32 i = 0;
3679         u16 id;
3680
3681         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3682
3683         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3684                 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3685         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3686                 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3687         else
3688                 return;
3689
3690         for (i = 0; i < cap_count; i++, cap++) {
3691                 id = LE16_TO_CPU(cap->id);
3692                 number = LE32_TO_CPU(cap->number);
3693                 logical_id = LE32_TO_CPU(cap->logical_id);
3694                 phys_id = LE32_TO_CPU(cap->phys_id);
3695                 major_rev = cap->major_rev;
3696
3697                 switch (id) {
3698                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3699                         p->switch_mode = number;
3700                         i40e_debug(hw, I40E_DEBUG_INIT,
3701                                    "HW Capability: Switch mode = %d\n",
3702                                    p->switch_mode);
3703                         break;
3704                 case I40E_AQ_CAP_ID_MNG_MODE:
3705                         p->management_mode = number;
3706                         if (major_rev > 1) {
3707                                 p->mng_protocols_over_mctp = logical_id;
3708                                 i40e_debug(hw, I40E_DEBUG_INIT,
3709                                            "HW Capability: Protocols over MCTP = %d\n",
3710                                            p->mng_protocols_over_mctp);
3711                         } else {
3712                                 p->mng_protocols_over_mctp = 0;
3713                         }
3714                         i40e_debug(hw, I40E_DEBUG_INIT,
3715                                    "HW Capability: Management Mode = %d\n",
3716                                    p->management_mode);
3717                         break;
3718                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3719                         p->npar_enable = number;
3720                         i40e_debug(hw, I40E_DEBUG_INIT,
3721                                    "HW Capability: NPAR enable = %d\n",
3722                                    p->npar_enable);
3723                         break;
3724                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3725                         p->os2bmc = number;
3726                         i40e_debug(hw, I40E_DEBUG_INIT,
3727                                    "HW Capability: OS2BMC = %d\n", p->os2bmc);
3728                         break;
3729                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3730                         p->valid_functions = number;
3731                         i40e_debug(hw, I40E_DEBUG_INIT,
3732                                    "HW Capability: Valid Functions = %d\n",
3733                                    p->valid_functions);
3734                         break;
3735                 case I40E_AQ_CAP_ID_SRIOV:
3736                         if (number == 1)
3737                                 p->sr_iov_1_1 = true;
3738                         i40e_debug(hw, I40E_DEBUG_INIT,
3739                                    "HW Capability: SR-IOV = %d\n",
3740                                    p->sr_iov_1_1);
3741                         break;
3742                 case I40E_AQ_CAP_ID_VF:
3743                         p->num_vfs = number;
3744                         p->vf_base_id = logical_id;
3745                         i40e_debug(hw, I40E_DEBUG_INIT,
3746                                    "HW Capability: VF count = %d\n",
3747                                    p->num_vfs);
3748                         i40e_debug(hw, I40E_DEBUG_INIT,
3749                                    "HW Capability: VF base_id = %d\n",
3750                                    p->vf_base_id);
3751                         break;
3752                 case I40E_AQ_CAP_ID_VMDQ:
3753                         if (number == 1)
3754                                 p->vmdq = true;
3755                         i40e_debug(hw, I40E_DEBUG_INIT,
3756                                    "HW Capability: VMDQ = %d\n", p->vmdq);
3757                         break;
3758                 case I40E_AQ_CAP_ID_8021QBG:
3759                         if (number == 1)
3760                                 p->evb_802_1_qbg = true;
3761                         i40e_debug(hw, I40E_DEBUG_INIT,
3762                                    "HW Capability: 802.1Qbg = %d\n", number);
3763                         break;
3764                 case I40E_AQ_CAP_ID_8021QBR:
3765                         if (number == 1)
3766                                 p->evb_802_1_qbh = true;
3767                         i40e_debug(hw, I40E_DEBUG_INIT,
3768                                    "HW Capability: 802.1Qbh = %d\n", number);
3769                         break;
3770                 case I40E_AQ_CAP_ID_VSI:
3771                         p->num_vsis = number;
3772                         i40e_debug(hw, I40E_DEBUG_INIT,
3773                                    "HW Capability: VSI count = %d\n",
3774                                    p->num_vsis);
3775                         break;
3776                 case I40E_AQ_CAP_ID_DCB:
3777                         if (number == 1) {
3778                                 p->dcb = true;
3779                                 p->enabled_tcmap = logical_id;
3780                                 p->maxtc = phys_id;
3781                         }
3782                         i40e_debug(hw, I40E_DEBUG_INIT,
3783                                    "HW Capability: DCB = %d\n", p->dcb);
3784                         i40e_debug(hw, I40E_DEBUG_INIT,
3785                                    "HW Capability: TC Mapping = %d\n",
3786                                    logical_id);
3787                         i40e_debug(hw, I40E_DEBUG_INIT,
3788                                    "HW Capability: TC Max = %d\n", p->maxtc);
3789                         break;
3790                 case I40E_AQ_CAP_ID_FCOE:
3791                         if (number == 1)
3792                                 p->fcoe = true;
3793                         i40e_debug(hw, I40E_DEBUG_INIT,
3794                                    "HW Capability: FCOE = %d\n", p->fcoe);
3795                         break;
3796                 case I40E_AQ_CAP_ID_ISCSI:
3797                         if (number == 1)
3798                                 p->iscsi = true;
3799                         i40e_debug(hw, I40E_DEBUG_INIT,
3800                                    "HW Capability: iSCSI = %d\n", p->iscsi);
3801                         break;
3802                 case I40E_AQ_CAP_ID_RSS:
3803                         p->rss = true;
3804                         p->rss_table_size = number;
3805                         p->rss_table_entry_width = logical_id;
3806                         i40e_debug(hw, I40E_DEBUG_INIT,
3807                                    "HW Capability: RSS = %d\n", p->rss);
3808                         i40e_debug(hw, I40E_DEBUG_INIT,
3809                                    "HW Capability: RSS table size = %d\n",
3810                                    p->rss_table_size);
3811                         i40e_debug(hw, I40E_DEBUG_INIT,
3812                                    "HW Capability: RSS table width = %d\n",
3813                                    p->rss_table_entry_width);
3814                         break;
3815                 case I40E_AQ_CAP_ID_RXQ:
3816                         p->num_rx_qp = number;
3817                         p->base_queue = phys_id;
3818                         i40e_debug(hw, I40E_DEBUG_INIT,
3819                                    "HW Capability: Rx QP = %d\n", number);
3820                         i40e_debug(hw, I40E_DEBUG_INIT,
3821                                    "HW Capability: base_queue = %d\n",
3822                                    p->base_queue);
3823                         break;
3824                 case I40E_AQ_CAP_ID_TXQ:
3825                         p->num_tx_qp = number;
3826                         p->base_queue = phys_id;
3827                         i40e_debug(hw, I40E_DEBUG_INIT,
3828                                    "HW Capability: Tx QP = %d\n", number);
3829                         i40e_debug(hw, I40E_DEBUG_INIT,
3830                                    "HW Capability: base_queue = %d\n",
3831                                    p->base_queue);
3832                         break;
3833                 case I40E_AQ_CAP_ID_MSIX:
3834                         p->num_msix_vectors = number;
3835                         i40e_debug(hw, I40E_DEBUG_INIT,
3836                                    "HW Capability: MSIX vector count = %d\n",
3837                                    p->num_msix_vectors);
3838                         break;
3839                 case I40E_AQ_CAP_ID_VF_MSIX:
3840                         p->num_msix_vectors_vf = number;
3841                         i40e_debug(hw, I40E_DEBUG_INIT,
3842                                    "HW Capability: MSIX VF vector count = %d\n",
3843                                    p->num_msix_vectors_vf);
3844                         break;
3845                 case I40E_AQ_CAP_ID_FLEX10:
3846                         if (major_rev == 1) {
3847                                 if (number == 1) {
3848                                         p->flex10_enable = true;
3849                                         p->flex10_capable = true;
3850                                 }
3851                         } else {
3852                                 /* Capability revision >= 2 */
3853                                 if (number & 1)
3854                                         p->flex10_enable = true;
3855                                 if (number & 2)
3856                                         p->flex10_capable = true;
3857                         }
3858                         p->flex10_mode = logical_id;
3859                         p->flex10_status = phys_id;
3860                         i40e_debug(hw, I40E_DEBUG_INIT,
3861                                    "HW Capability: Flex10 mode = %d\n",
3862                                    p->flex10_mode);
3863                         i40e_debug(hw, I40E_DEBUG_INIT,
3864                                    "HW Capability: Flex10 status = %d\n",
3865                                    p->flex10_status);
3866                         break;
3867                 case I40E_AQ_CAP_ID_CEM:
3868                         if (number == 1)
3869                                 p->mgmt_cem = true;
3870                         i40e_debug(hw, I40E_DEBUG_INIT,
3871                                    "HW Capability: CEM = %d\n", p->mgmt_cem);
3872                         break;
3873                 case I40E_AQ_CAP_ID_IWARP:
3874                         if (number == 1)
3875                                 p->iwarp = true;
3876                         i40e_debug(hw, I40E_DEBUG_INIT,
3877                                    "HW Capability: iWARP = %d\n", p->iwarp);
3878                         break;
3879                 case I40E_AQ_CAP_ID_LED:
3880                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3881                                 p->led[phys_id] = true;
3882                         i40e_debug(hw, I40E_DEBUG_INIT,
3883                                    "HW Capability: LED - PIN %d\n", phys_id);
3884                         break;
3885                 case I40E_AQ_CAP_ID_SDP:
3886                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3887                                 p->sdp[phys_id] = true;
3888                         i40e_debug(hw, I40E_DEBUG_INIT,
3889                                    "HW Capability: SDP - PIN %d\n", phys_id);
3890                         break;
3891                 case I40E_AQ_CAP_ID_MDIO:
3892                         if (number == 1) {
3893                                 p->mdio_port_num = phys_id;
3894                                 p->mdio_port_mode = logical_id;
3895                         }
3896                         i40e_debug(hw, I40E_DEBUG_INIT,
3897                                    "HW Capability: MDIO port number = %d\n",
3898                                    p->mdio_port_num);
3899                         i40e_debug(hw, I40E_DEBUG_INIT,
3900                                    "HW Capability: MDIO port mode = %d\n",
3901                                    p->mdio_port_mode);
3902                         break;
3903                 case I40E_AQ_CAP_ID_1588:
3904                         if (number == 1)
3905                                 p->ieee_1588 = true;
3906                         i40e_debug(hw, I40E_DEBUG_INIT,
3907                                    "HW Capability: IEEE 1588 = %d\n",
3908                                    p->ieee_1588);
3909                         break;
3910                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3911                         p->fd = true;
3912                         p->fd_filters_guaranteed = number;
3913                         p->fd_filters_best_effort = logical_id;
3914                         i40e_debug(hw, I40E_DEBUG_INIT,
3915                                    "HW Capability: Flow Director = 1\n");
3916                         i40e_debug(hw, I40E_DEBUG_INIT,
3917                                    "HW Capability: Guaranteed FD filters = %d\n",
3918                                    p->fd_filters_guaranteed);
3919                         break;
3920                 case I40E_AQ_CAP_ID_WSR_PROT:
3921                         p->wr_csr_prot = (u64)number;
3922                         p->wr_csr_prot |= (u64)logical_id << 32;
3923                         i40e_debug(hw, I40E_DEBUG_INIT,
3924                                    "HW Capability: wr_csr_prot = 0x%llX\n\n",
3925                                    (p->wr_csr_prot & 0xffff));
3926                         break;
3927                 case I40E_AQ_CAP_ID_NVM_MGMT:
3928                         if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3929                                 p->sec_rev_disabled = true;
3930                         if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3931                                 p->update_disabled = true;
3932                         break;
3933                 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3934                         hw->num_wol_proxy_filters = (u16)number;
3935                         hw->wol_proxy_vsi_seid = (u16)logical_id;
3936                         p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3937                         if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3938                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3939                         else
3940                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3941                         p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3942                         i40e_debug(hw, I40E_DEBUG_INIT,
3943                                    "HW Capability: WOL proxy filters = %d\n",
3944                                    hw->num_wol_proxy_filters);
3945                         break;
3946                 default:
3947                         break;
3948                 }
3949         }
3950
3951         if (p->fcoe)
3952                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3953
3954         /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3955         p->fcoe = false;
3956
3957         /* count the enabled ports (aka the "not disabled" ports) */
3958         hw->num_ports = 0;
3959         for (i = 0; i < 4; i++) {
3960                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3961                 u64 port_cfg = 0;
3962
3963                 /* use AQ read to get the physical register offset instead
3964                  * of the port relative offset
3965                  */
3966                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3967                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3968                         hw->num_ports++;
3969         }
3970
3971         valid_functions = p->valid_functions;
3972         num_functions = 0;
3973         while (valid_functions) {
3974                 if (valid_functions & 1)
3975                         num_functions++;
3976                 valid_functions >>= 1;
3977         }
3978
3979         /* partition id is 1-based, and functions are evenly spread
3980          * across the ports as partitions
3981          */
3982         if (hw->num_ports != 0) {
3983                 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3984                 hw->num_partitions = num_functions / hw->num_ports;
3985         }
3986
3987         /* additional HW specific goodies that might
3988          * someday be HW version specific
3989          */
3990         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3991 }
3992
3993 /**
3994  * i40e_aq_discover_capabilities
3995  * @hw: pointer to the hw struct
3996  * @buff: a virtual buffer to hold the capabilities
3997  * @buff_size: Size of the virtual buffer
3998  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3999  * @list_type_opc: capabilities type to discover - pass in the command opcode
4000  * @cmd_details: pointer to command details structure or NULL
4001  *
4002  * Get the device capabilities descriptions from the firmware
4003  **/
4004 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
4005                                 void *buff, u16 buff_size, u16 *data_size,
4006                                 enum i40e_admin_queue_opc list_type_opc,
4007                                 struct i40e_asq_cmd_details *cmd_details)
4008 {
4009         struct i40e_aqc_list_capabilites *cmd;
4010         struct i40e_aq_desc desc;
4011         enum i40e_status_code status = I40E_SUCCESS;
4012
4013         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
4014
4015         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
4016                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
4017                 status = I40E_ERR_PARAM;
4018                 goto exit;
4019         }
4020
4021         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
4022
4023         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4024         if (buff_size > I40E_AQ_LARGE_BUF)
4025                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4026
4027         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4028         *data_size = LE16_TO_CPU(desc.datalen);
4029
4030         if (status)
4031                 goto exit;
4032
4033         i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
4034                                          list_type_opc);
4035
4036 exit:
4037         return status;
4038 }
4039
4040 /**
4041  * i40e_aq_update_nvm
4042  * @hw: pointer to the hw struct
4043  * @module_pointer: module pointer location in words from the NVM beginning
4044  * @offset: byte offset from the module beginning
4045  * @length: length of the section to be written (in bytes from the offset)
4046  * @data: command buffer (size [bytes] = length)
4047  * @last_command: tells if this is the last command in a series
4048  * @cmd_details: pointer to command details structure or NULL
4049  *
4050  * Update the NVM using the admin queue commands
4051  **/
4052 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
4053                                 u32 offset, u16 length, void *data,
4054                                 bool last_command,
4055                                 struct i40e_asq_cmd_details *cmd_details)
4056 {
4057         struct i40e_aq_desc desc;
4058         struct i40e_aqc_nvm_update *cmd =
4059                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
4060         enum i40e_status_code status;
4061
4062         DEBUGFUNC("i40e_aq_update_nvm");
4063
4064         /* In offset the highest byte must be zeroed. */
4065         if (offset & 0xFF000000) {
4066                 status = I40E_ERR_PARAM;
4067                 goto i40e_aq_update_nvm_exit;
4068         }
4069
4070         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4071
4072         /* If this is the last command in a series, set the proper flag. */
4073         if (last_command)
4074                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
4075         cmd->module_pointer = module_pointer;
4076         cmd->offset = CPU_TO_LE32(offset);
4077         cmd->length = CPU_TO_LE16(length);
4078
4079         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4080         if (length > I40E_AQ_LARGE_BUF)
4081                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4082
4083         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
4084
4085 i40e_aq_update_nvm_exit:
4086         return status;
4087 }
4088
4089 /**
4090  * i40e_aq_get_lldp_mib
4091  * @hw: pointer to the hw struct
4092  * @bridge_type: type of bridge requested
4093  * @mib_type: Local, Remote or both Local and Remote MIBs
4094  * @buff: pointer to a user supplied buffer to store the MIB block
4095  * @buff_size: size of the buffer (in bytes)
4096  * @local_len : length of the returned Local LLDP MIB
4097  * @remote_len: length of the returned Remote LLDP MIB
4098  * @cmd_details: pointer to command details structure or NULL
4099  *
4100  * Requests the complete LLDP MIB (entire packet).
4101  **/
4102 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4103                                 u8 mib_type, void *buff, u16 buff_size,
4104                                 u16 *local_len, u16 *remote_len,
4105                                 struct i40e_asq_cmd_details *cmd_details)
4106 {
4107         struct i40e_aq_desc desc;
4108         struct i40e_aqc_lldp_get_mib *cmd =
4109                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4110         struct i40e_aqc_lldp_get_mib *resp =
4111                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4112         enum i40e_status_code status;
4113
4114         if (buff_size == 0 || !buff)
4115                 return I40E_ERR_PARAM;
4116
4117         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4118         /* Indirect Command */
4119         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4120
4121         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4122         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4123                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4124
4125         desc.datalen = CPU_TO_LE16(buff_size);
4126
4127         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4128         if (buff_size > I40E_AQ_LARGE_BUF)
4129                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4130
4131         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4132         if (!status) {
4133                 if (local_len != NULL)
4134                         *local_len = LE16_TO_CPU(resp->local_len);
4135                 if (remote_len != NULL)
4136                         *remote_len = LE16_TO_CPU(resp->remote_len);
4137         }
4138
4139         return status;
4140 }
4141
4142  /**
4143  * i40e_aq_set_lldp_mib - Set the LLDP MIB
4144  * @hw: pointer to the hw struct
4145  * @mib_type: Local, Remote or both Local and Remote MIBs
4146  * @buff: pointer to a user supplied buffer to store the MIB block
4147  * @buff_size: size of the buffer (in bytes)
4148  * @cmd_details: pointer to command details structure or NULL
4149  *
4150  * Set the LLDP MIB.
4151  **/
4152 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4153                                 u8 mib_type, void *buff, u16 buff_size,
4154                                 struct i40e_asq_cmd_details *cmd_details)
4155 {
4156         struct i40e_aq_desc desc;
4157         struct i40e_aqc_lldp_set_local_mib *cmd =
4158                 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4159         enum i40e_status_code status;
4160
4161         if (buff_size == 0 || !buff)
4162                 return I40E_ERR_PARAM;
4163
4164         i40e_fill_default_direct_cmd_desc(&desc,
4165                                 i40e_aqc_opc_lldp_set_local_mib);
4166         /* Indirect Command */
4167         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4168         if (buff_size > I40E_AQ_LARGE_BUF)
4169                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4170         desc.datalen = CPU_TO_LE16(buff_size);
4171
4172         cmd->type = mib_type;
4173         cmd->length = CPU_TO_LE16(buff_size);
4174         cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4175         cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4176
4177         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4178         return status;
4179 }
4180
4181 /**
4182  * i40e_aq_cfg_lldp_mib_change_event
4183  * @hw: pointer to the hw struct
4184  * @enable_update: Enable or Disable event posting
4185  * @cmd_details: pointer to command details structure or NULL
4186  *
4187  * Enable or Disable posting of an event on ARQ when LLDP MIB
4188  * associated with the interface changes
4189  **/
4190 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4191                                 bool enable_update,
4192                                 struct i40e_asq_cmd_details *cmd_details)
4193 {
4194         struct i40e_aq_desc desc;
4195         struct i40e_aqc_lldp_update_mib *cmd =
4196                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4197         enum i40e_status_code status;
4198
4199         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4200
4201         if (!enable_update)
4202                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4203
4204         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4205
4206         return status;
4207 }
4208
4209 /**
4210  * i40e_aq_add_lldp_tlv
4211  * @hw: pointer to the hw struct
4212  * @bridge_type: type of bridge
4213  * @buff: buffer with TLV to add
4214  * @buff_size: length of the buffer
4215  * @tlv_len: length of the TLV to be added
4216  * @mib_len: length of the LLDP MIB returned in response
4217  * @cmd_details: pointer to command details structure or NULL
4218  *
4219  * Add the specified TLV to LLDP Local MIB for the given bridge type,
4220  * it is responsibility of the caller to make sure that the TLV is not
4221  * already present in the LLDPDU.
4222  * In return firmware will write the complete LLDP MIB with the newly
4223  * added TLV in the response buffer.
4224  **/
4225 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4226                                 void *buff, u16 buff_size, u16 tlv_len,
4227                                 u16 *mib_len,
4228                                 struct i40e_asq_cmd_details *cmd_details)
4229 {
4230         struct i40e_aq_desc desc;
4231         struct i40e_aqc_lldp_add_tlv *cmd =
4232                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4233         enum i40e_status_code status;
4234
4235         if (buff_size == 0 || !buff || tlv_len == 0)
4236                 return I40E_ERR_PARAM;
4237
4238         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4239
4240         /* Indirect Command */
4241         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4242         if (buff_size > I40E_AQ_LARGE_BUF)
4243                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4244         desc.datalen = CPU_TO_LE16(buff_size);
4245
4246         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4247                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4248         cmd->len = CPU_TO_LE16(tlv_len);
4249
4250         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4251         if (!status) {
4252                 if (mib_len != NULL)
4253                         *mib_len = LE16_TO_CPU(desc.datalen);
4254         }
4255
4256         return status;
4257 }
4258
4259 /**
4260  * i40e_aq_update_lldp_tlv
4261  * @hw: pointer to the hw struct
4262  * @bridge_type: type of bridge
4263  * @buff: buffer with TLV to update
4264  * @buff_size: size of the buffer holding original and updated TLVs
4265  * @old_len: Length of the Original TLV
4266  * @new_len: Length of the Updated TLV
4267  * @offset: offset of the updated TLV in the buff
4268  * @mib_len: length of the returned LLDP MIB
4269  * @cmd_details: pointer to command details structure or NULL
4270  *
4271  * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4272  * Firmware will place the complete LLDP MIB in response buffer with the
4273  * updated TLV.
4274  **/
4275 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4276                                 u8 bridge_type, void *buff, u16 buff_size,
4277                                 u16 old_len, u16 new_len, u16 offset,
4278                                 u16 *mib_len,
4279                                 struct i40e_asq_cmd_details *cmd_details)
4280 {
4281         struct i40e_aq_desc desc;
4282         struct i40e_aqc_lldp_update_tlv *cmd =
4283                 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4284         enum i40e_status_code status;
4285
4286         if (buff_size == 0 || !buff || offset == 0 ||
4287             old_len == 0 || new_len == 0)
4288                 return I40E_ERR_PARAM;
4289
4290         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4291
4292         /* Indirect Command */
4293         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4294         if (buff_size > I40E_AQ_LARGE_BUF)
4295                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4296         desc.datalen = CPU_TO_LE16(buff_size);
4297
4298         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4299                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4300         cmd->old_len = CPU_TO_LE16(old_len);
4301         cmd->new_offset = CPU_TO_LE16(offset);
4302         cmd->new_len = CPU_TO_LE16(new_len);
4303
4304         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4305         if (!status) {
4306                 if (mib_len != NULL)
4307                         *mib_len = LE16_TO_CPU(desc.datalen);
4308         }
4309
4310         return status;
4311 }
4312
4313 /**
4314  * i40e_aq_delete_lldp_tlv
4315  * @hw: pointer to the hw struct
4316  * @bridge_type: type of bridge
4317  * @buff: pointer to a user supplied buffer that has the TLV
4318  * @buff_size: length of the buffer
4319  * @tlv_len: length of the TLV to be deleted
4320  * @mib_len: length of the returned LLDP MIB
4321  * @cmd_details: pointer to command details structure or NULL
4322  *
4323  * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4324  * The firmware places the entire LLDP MIB in the response buffer.
4325  **/
4326 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4327                                 u8 bridge_type, void *buff, u16 buff_size,
4328                                 u16 tlv_len, u16 *mib_len,
4329                                 struct i40e_asq_cmd_details *cmd_details)
4330 {
4331         struct i40e_aq_desc desc;
4332         struct i40e_aqc_lldp_add_tlv *cmd =
4333                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4334         enum i40e_status_code status;
4335
4336         if (buff_size == 0 || !buff)
4337                 return I40E_ERR_PARAM;
4338
4339         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4340
4341         /* Indirect Command */
4342         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4343         if (buff_size > I40E_AQ_LARGE_BUF)
4344                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4345         desc.datalen = CPU_TO_LE16(buff_size);
4346         cmd->len = CPU_TO_LE16(tlv_len);
4347         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4348                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4349
4350         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4351         if (!status) {
4352                 if (mib_len != NULL)
4353                         *mib_len = LE16_TO_CPU(desc.datalen);
4354         }
4355
4356         return status;
4357 }
4358
4359 /**
4360  * i40e_aq_stop_lldp
4361  * @hw: pointer to the hw struct
4362  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4363  * @cmd_details: pointer to command details structure or NULL
4364  *
4365  * Stop or Shutdown the embedded LLDP Agent
4366  **/
4367 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4368                                 struct i40e_asq_cmd_details *cmd_details)
4369 {
4370         struct i40e_aq_desc desc;
4371         struct i40e_aqc_lldp_stop *cmd =
4372                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4373         enum i40e_status_code status;
4374
4375         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4376
4377         if (shutdown_agent)
4378                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4379
4380         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4381
4382         return status;
4383 }
4384
4385 /**
4386  * i40e_aq_start_lldp
4387  * @hw: pointer to the hw struct
4388  * @cmd_details: pointer to command details structure or NULL
4389  *
4390  * Start the embedded LLDP Agent on all ports.
4391  **/
4392 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4393                                 struct i40e_asq_cmd_details *cmd_details)
4394 {
4395         struct i40e_aq_desc desc;
4396         struct i40e_aqc_lldp_start *cmd =
4397                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4398         enum i40e_status_code status;
4399
4400         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4401
4402         cmd->command = I40E_AQ_LLDP_AGENT_START;
4403
4404         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4405
4406         return status;
4407 }
4408
4409 /**
4410  * i40e_aq_get_cee_dcb_config
4411  * @hw: pointer to the hw struct
4412  * @buff: response buffer that stores CEE operational configuration
4413  * @buff_size: size of the buffer passed
4414  * @cmd_details: pointer to command details structure or NULL
4415  *
4416  * Get CEE DCBX mode operational configuration from firmware
4417  **/
4418 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4419                                 void *buff, u16 buff_size,
4420                                 struct i40e_asq_cmd_details *cmd_details)
4421 {
4422         struct i40e_aq_desc desc;
4423         enum i40e_status_code status;
4424
4425         if (buff_size == 0 || !buff)
4426                 return I40E_ERR_PARAM;
4427
4428         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4429
4430         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4431         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4432                                        cmd_details);
4433
4434         return status;
4435 }
4436
4437 /**
4438  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4439  * @hw: pointer to the hw struct
4440  * @start_agent: True if DCBx Agent needs to be Started
4441  *                              False if DCBx Agent needs to be Stopped
4442  * @cmd_details: pointer to command details structure or NULL
4443  *
4444  * Start/Stop the embedded dcbx Agent
4445  **/
4446 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4447                                 bool start_agent,
4448                                 struct i40e_asq_cmd_details *cmd_details)
4449 {
4450         struct i40e_aq_desc desc;
4451         struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4452                 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4453                                 &desc.params.raw;
4454         enum i40e_status_code status;
4455
4456         i40e_fill_default_direct_cmd_desc(&desc,
4457                                 i40e_aqc_opc_lldp_stop_start_spec_agent);
4458
4459         if (start_agent)
4460                 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4461
4462         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4463
4464         return status;
4465 }
4466
4467 /**
4468  * i40e_aq_add_udp_tunnel
4469  * @hw: pointer to the hw struct
4470  * @udp_port: the UDP port to add in Host byte order
4471  * @header_len: length of the tunneling header length in DWords
4472  * @protocol_index: protocol index type
4473  * @filter_index: pointer to filter index
4474  * @cmd_details: pointer to command details structure or NULL
4475  *
4476  * Note: Firmware expects the udp_port value to be in Little Endian format,
4477  * and this function will call CPU_TO_LE16 to convert from Host byte order to
4478  * Little Endian order.
4479  **/
4480 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4481                                 u16 udp_port, u8 protocol_index,
4482                                 u8 *filter_index,
4483                                 struct i40e_asq_cmd_details *cmd_details)
4484 {
4485         struct i40e_aq_desc desc;
4486         struct i40e_aqc_add_udp_tunnel *cmd =
4487                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4488         struct i40e_aqc_del_udp_tunnel_completion *resp =
4489                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4490         enum i40e_status_code status;
4491
4492         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4493
4494         cmd->udp_port = CPU_TO_LE16(udp_port);
4495         cmd->protocol_type = protocol_index;
4496
4497         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4498
4499         if (!status && filter_index)
4500                 *filter_index = resp->index;
4501
4502         return status;
4503 }
4504
4505 /**
4506  * i40e_aq_del_udp_tunnel
4507  * @hw: pointer to the hw struct
4508  * @index: filter index
4509  * @cmd_details: pointer to command details structure or NULL
4510  **/
4511 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4512                                 struct i40e_asq_cmd_details *cmd_details)
4513 {
4514         struct i40e_aq_desc desc;
4515         struct i40e_aqc_remove_udp_tunnel *cmd =
4516                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4517         enum i40e_status_code status;
4518
4519         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4520
4521         cmd->index = index;
4522
4523         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4524
4525         return status;
4526 }
4527
4528 /**
4529  * i40e_aq_get_switch_resource_alloc (0x0204)
4530  * @hw: pointer to the hw struct
4531  * @num_entries: pointer to u8 to store the number of resource entries returned
4532  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
4533  *        to store the resource information for all resource types.  Each
4534  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
4535  * @count: size, in bytes, of the buffer provided
4536  * @cmd_details: pointer to command details structure or NULL
4537  *
4538  * Query the resources allocated to a function.
4539  **/
4540 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4541                         u8 *num_entries,
4542                         struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4543                         u16 count,
4544                         struct i40e_asq_cmd_details *cmd_details)
4545 {
4546         struct i40e_aq_desc desc;
4547         struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4548                 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4549         enum i40e_status_code status;
4550         u16 length = count * sizeof(*buf);
4551
4552         i40e_fill_default_direct_cmd_desc(&desc,
4553                                         i40e_aqc_opc_get_switch_resource_alloc);
4554
4555         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4556         if (length > I40E_AQ_LARGE_BUF)
4557                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4558
4559         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4560
4561         if (!status && num_entries)
4562                 *num_entries = cmd_resp->num_entries;
4563
4564         return status;
4565 }
4566
4567 /**
4568  * i40e_aq_delete_element - Delete switch element
4569  * @hw: pointer to the hw struct
4570  * @seid: the SEID to delete from the switch
4571  * @cmd_details: pointer to command details structure or NULL
4572  *
4573  * This deletes a switch element from the switch.
4574  **/
4575 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4576                                 struct i40e_asq_cmd_details *cmd_details)
4577 {
4578         struct i40e_aq_desc desc;
4579         struct i40e_aqc_switch_seid *cmd =
4580                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4581         enum i40e_status_code status;
4582
4583         if (seid == 0)
4584                 return I40E_ERR_PARAM;
4585
4586         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4587
4588         cmd->seid = CPU_TO_LE16(seid);
4589
4590         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4591
4592         return status;
4593 }
4594
4595 /**
4596  * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4597  * @hw: pointer to the hw struct
4598  * @flags: component flags
4599  * @mac_seid: uplink seid (MAC SEID)
4600  * @vsi_seid: connected vsi seid
4601  * @ret_seid: seid of create pv component
4602  *
4603  * This instantiates an i40e port virtualizer with specified flags.
4604  * Depending on specified flags the port virtualizer can act as a
4605  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4606  */
4607 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4608                                        u16 mac_seid, u16 vsi_seid,
4609                                        u16 *ret_seid)
4610 {
4611         struct i40e_aq_desc desc;
4612         struct i40e_aqc_add_update_pv *cmd =
4613                 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4614         struct i40e_aqc_add_update_pv_completion *resp =
4615                 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4616         enum i40e_status_code status;
4617
4618         if (vsi_seid == 0)
4619                 return I40E_ERR_PARAM;
4620
4621         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4622         cmd->command_flags = CPU_TO_LE16(flags);
4623         cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4624         cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4625
4626         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4627         if (!status && ret_seid)
4628                 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4629
4630         return status;
4631 }
4632
4633 /**
4634  * i40e_aq_add_tag - Add an S/E-tag
4635  * @hw: pointer to the hw struct
4636  * @direct_to_queue: should s-tag direct flow to a specific queue
4637  * @vsi_seid: VSI SEID to use this tag
4638  * @tag: value of the tag
4639  * @queue_num: queue number, only valid is direct_to_queue is true
4640  * @tags_used: return value, number of tags in use by this PF
4641  * @tags_free: return value, number of unallocated tags
4642  * @cmd_details: pointer to command details structure or NULL
4643  *
4644  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4645  * the number of tags allocated by the PF, and the number of unallocated
4646  * tags available.
4647  **/
4648 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4649                                 u16 vsi_seid, u16 tag, u16 queue_num,
4650                                 u16 *tags_used, u16 *tags_free,
4651                                 struct i40e_asq_cmd_details *cmd_details)
4652 {
4653         struct i40e_aq_desc desc;
4654         struct i40e_aqc_add_tag *cmd =
4655                 (struct i40e_aqc_add_tag *)&desc.params.raw;
4656         struct i40e_aqc_add_remove_tag_completion *resp =
4657                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4658         enum i40e_status_code status;
4659
4660         if (vsi_seid == 0)
4661                 return I40E_ERR_PARAM;
4662
4663         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4664
4665         cmd->seid = CPU_TO_LE16(vsi_seid);
4666         cmd->tag = CPU_TO_LE16(tag);
4667         if (direct_to_queue) {
4668                 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4669                 cmd->queue_number = CPU_TO_LE16(queue_num);
4670         }
4671
4672         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4673
4674         if (!status) {
4675                 if (tags_used != NULL)
4676                         *tags_used = LE16_TO_CPU(resp->tags_used);
4677                 if (tags_free != NULL)
4678                         *tags_free = LE16_TO_CPU(resp->tags_free);
4679         }
4680
4681         return status;
4682 }
4683
4684 /**
4685  * i40e_aq_remove_tag - Remove an S- or E-tag
4686  * @hw: pointer to the hw struct
4687  * @vsi_seid: VSI SEID this tag is associated with
4688  * @tag: value of the S-tag to delete
4689  * @tags_used: return value, number of tags in use by this PF
4690  * @tags_free: return value, number of unallocated tags
4691  * @cmd_details: pointer to command details structure or NULL
4692  *
4693  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4694  * the number of tags allocated by the PF, and the number of unallocated
4695  * tags available.
4696  **/
4697 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4698                                 u16 tag, u16 *tags_used, u16 *tags_free,
4699                                 struct i40e_asq_cmd_details *cmd_details)
4700 {
4701         struct i40e_aq_desc desc;
4702         struct i40e_aqc_remove_tag *cmd =
4703                 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4704         struct i40e_aqc_add_remove_tag_completion *resp =
4705                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4706         enum i40e_status_code status;
4707
4708         if (vsi_seid == 0)
4709                 return I40E_ERR_PARAM;
4710
4711         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4712
4713         cmd->seid = CPU_TO_LE16(vsi_seid);
4714         cmd->tag = CPU_TO_LE16(tag);
4715
4716         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4717
4718         if (!status) {
4719                 if (tags_used != NULL)
4720                         *tags_used = LE16_TO_CPU(resp->tags_used);
4721                 if (tags_free != NULL)
4722                         *tags_free = LE16_TO_CPU(resp->tags_free);
4723         }
4724
4725         return status;
4726 }
4727
4728 /**
4729  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4730  * @hw: pointer to the hw struct
4731  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4732  * @etag: value of E-tag to add
4733  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4734  * @buf: address of indirect buffer
4735  * @tags_used: return value, number of E-tags in use by this port
4736  * @tags_free: return value, number of unallocated M-tags
4737  * @cmd_details: pointer to command details structure or NULL
4738  *
4739  * This associates a multicast E-tag to a port virtualizer.  It will return
4740  * the number of tags allocated by the PF, and the number of unallocated
4741  * tags available.
4742  *
4743  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4744  * num_tags_in_buf long.
4745  **/
4746 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4747                                 u16 etag, u8 num_tags_in_buf, void *buf,
4748                                 u16 *tags_used, u16 *tags_free,
4749                                 struct i40e_asq_cmd_details *cmd_details)
4750 {
4751         struct i40e_aq_desc desc;
4752         struct i40e_aqc_add_remove_mcast_etag *cmd =
4753                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4754         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4755            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4756         enum i40e_status_code status;
4757         u16 length = sizeof(u16) * num_tags_in_buf;
4758
4759         if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4760                 return I40E_ERR_PARAM;
4761
4762         i40e_fill_default_direct_cmd_desc(&desc,
4763                                           i40e_aqc_opc_add_multicast_etag);
4764
4765         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4766         cmd->etag = CPU_TO_LE16(etag);
4767         cmd->num_unicast_etags = num_tags_in_buf;
4768
4769         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4770         if (length > I40E_AQ_LARGE_BUF)
4771                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4772
4773         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4774
4775         if (!status) {
4776                 if (tags_used != NULL)
4777                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4778                 if (tags_free != NULL)
4779                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4780         }
4781
4782         return status;
4783 }
4784
4785 /**
4786  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4787  * @hw: pointer to the hw struct
4788  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4789  * @etag: value of the E-tag to remove
4790  * @tags_used: return value, number of tags in use by this port
4791  * @tags_free: return value, number of unallocated tags
4792  * @cmd_details: pointer to command details structure or NULL
4793  *
4794  * This deletes an E-tag from the port virtualizer.  It will return
4795  * the number of tags allocated by the port, and the number of unallocated
4796  * tags available.
4797  **/
4798 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4799                                 u16 etag, u16 *tags_used, u16 *tags_free,
4800                                 struct i40e_asq_cmd_details *cmd_details)
4801 {
4802         struct i40e_aq_desc desc;
4803         struct i40e_aqc_add_remove_mcast_etag *cmd =
4804                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4805         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4806            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4807         enum i40e_status_code status;
4808
4809
4810         if (pv_seid == 0)
4811                 return I40E_ERR_PARAM;
4812
4813         i40e_fill_default_direct_cmd_desc(&desc,
4814                                           i40e_aqc_opc_remove_multicast_etag);
4815
4816         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4817         cmd->etag = CPU_TO_LE16(etag);
4818
4819         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4820
4821         if (!status) {
4822                 if (tags_used != NULL)
4823                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4824                 if (tags_free != NULL)
4825                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4826         }
4827
4828         return status;
4829 }
4830
4831 /**
4832  * i40e_aq_update_tag - Update an S/E-tag
4833  * @hw: pointer to the hw struct
4834  * @vsi_seid: VSI SEID using this S-tag
4835  * @old_tag: old tag value
4836  * @new_tag: new tag value
4837  * @tags_used: return value, number of tags in use by this PF
4838  * @tags_free: return value, number of unallocated tags
4839  * @cmd_details: pointer to command details structure or NULL
4840  *
4841  * This updates the value of the tag currently attached to this VSI
4842  * in the switch complex.  It will return the number of tags allocated
4843  * by the PF, and the number of unallocated tags available.
4844  **/
4845 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4846                                 u16 old_tag, u16 new_tag, u16 *tags_used,
4847                                 u16 *tags_free,
4848                                 struct i40e_asq_cmd_details *cmd_details)
4849 {
4850         struct i40e_aq_desc desc;
4851         struct i40e_aqc_update_tag *cmd =
4852                 (struct i40e_aqc_update_tag *)&desc.params.raw;
4853         struct i40e_aqc_update_tag_completion *resp =
4854                 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4855         enum i40e_status_code status;
4856
4857         if (vsi_seid == 0)
4858                 return I40E_ERR_PARAM;
4859
4860         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4861
4862         cmd->seid = CPU_TO_LE16(vsi_seid);
4863         cmd->old_tag = CPU_TO_LE16(old_tag);
4864         cmd->new_tag = CPU_TO_LE16(new_tag);
4865
4866         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4867
4868         if (!status) {
4869                 if (tags_used != NULL)
4870                         *tags_used = LE16_TO_CPU(resp->tags_used);
4871                 if (tags_free != NULL)
4872                         *tags_free = LE16_TO_CPU(resp->tags_free);
4873         }
4874
4875         return status;
4876 }
4877
4878 /**
4879  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4880  * @hw: pointer to the hw struct
4881  * @tcmap: TC map for request/release any ignore PFC condition
4882  * @request: request or release ignore PFC condition
4883  * @tcmap_ret: return TCs for which PFC is currently ignored
4884  * @cmd_details: pointer to command details structure or NULL
4885  *
4886  * This sends out request/release to ignore PFC condition for a TC.
4887  * It will return the TCs for which PFC is currently ignored.
4888  **/
4889 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4890                                 bool request, u8 *tcmap_ret,
4891                                 struct i40e_asq_cmd_details *cmd_details)
4892 {
4893         struct i40e_aq_desc desc;
4894         struct i40e_aqc_pfc_ignore *cmd_resp =
4895                 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4896         enum i40e_status_code status;
4897
4898         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4899
4900         if (request)
4901                 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4902
4903         cmd_resp->tc_bitmap = tcmap;
4904
4905         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4906
4907         if (!status) {
4908                 if (tcmap_ret != NULL)
4909                         *tcmap_ret = cmd_resp->tc_bitmap;
4910         }
4911
4912         return status;
4913 }
4914
4915 /**
4916  * i40e_aq_dcb_updated - DCB Updated Command
4917  * @hw: pointer to the hw struct
4918  * @cmd_details: pointer to command details structure or NULL
4919  *
4920  * When LLDP is handled in PF this command is used by the PF
4921  * to notify EMP that a DCB setting is modified.
4922  * When LLDP is handled in EMP this command is used by the PF
4923  * to notify EMP whenever one of the following parameters get
4924  * modified:
4925  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4926  *   - PCIRTT in PRTDCB_GENC.PCIRTT
4927  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4928  * EMP will return when the shared RPB settings have been
4929  * recomputed and modified. The retval field in the descriptor
4930  * will be set to 0 when RPB is modified.
4931  **/
4932 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4933                                 struct i40e_asq_cmd_details *cmd_details)
4934 {
4935         struct i40e_aq_desc desc;
4936         enum i40e_status_code status;
4937
4938         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4939
4940         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4941
4942         return status;
4943 }
4944
4945 /**
4946  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4947  * @hw: pointer to the hw struct
4948  * @seid: defines the SEID of the switch for which the stats are requested
4949  * @vlan_id: the VLAN ID for which the statistics are requested
4950  * @stat_index: index of the statistics counters block assigned to this VLAN
4951  * @cmd_details: pointer to command details structure or NULL
4952  *
4953  * XL710 supports 128 smonVlanStats counters.This command is used to
4954  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4955  * switch.
4956  **/
4957 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4958                                 u16 vlan_id, u16 *stat_index,
4959                                 struct i40e_asq_cmd_details *cmd_details)
4960 {
4961         struct i40e_aq_desc desc;
4962         struct i40e_aqc_add_remove_statistics *cmd_resp =
4963                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4964         enum i40e_status_code status;
4965
4966         if ((seid == 0) || (stat_index == NULL))
4967                 return I40E_ERR_PARAM;
4968
4969         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4970
4971         cmd_resp->seid = CPU_TO_LE16(seid);
4972         cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4973
4974         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4975
4976         if (!status && stat_index)
4977                 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4978
4979         return status;
4980 }
4981
4982 /**
4983  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4984  * @hw: pointer to the hw struct
4985  * @seid: defines the SEID of the switch for which the stats are requested
4986  * @vlan_id: the VLAN ID for which the statistics are requested
4987  * @stat_index: index of the statistics counters block assigned to this VLAN
4988  * @cmd_details: pointer to command details structure or NULL
4989  *
4990  * XL710 supports 128 smonVlanStats counters.This command is used to
4991  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4992  * switch.
4993  **/
4994 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4995                                 u16 vlan_id, u16 stat_index,
4996                                 struct i40e_asq_cmd_details *cmd_details)
4997 {
4998         struct i40e_aq_desc desc;
4999         struct i40e_aqc_add_remove_statistics *cmd =
5000                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5001         enum i40e_status_code status;
5002
5003         if (seid == 0)
5004                 return I40E_ERR_PARAM;
5005
5006         i40e_fill_default_direct_cmd_desc(&desc,
5007                                           i40e_aqc_opc_remove_statistics);
5008
5009         cmd->seid = CPU_TO_LE16(seid);
5010         cmd->vlan  = CPU_TO_LE16(vlan_id);
5011         cmd->stat_index = CPU_TO_LE16(stat_index);
5012
5013         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5014
5015         return status;
5016 }
5017
5018 /**
5019  * i40e_aq_set_port_parameters - set physical port parameters.
5020  * @hw: pointer to the hw struct
5021  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
5022  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
5023  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
5024  * @double_vlan: if set double VLAN is enabled
5025  * @cmd_details: pointer to command details structure or NULL
5026  **/
5027 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
5028                                 u16 bad_frame_vsi, bool save_bad_pac,
5029                                 bool pad_short_pac, bool double_vlan,
5030                                 struct i40e_asq_cmd_details *cmd_details)
5031 {
5032         struct i40e_aqc_set_port_parameters *cmd;
5033         enum i40e_status_code status;
5034         struct i40e_aq_desc desc;
5035         u16 command_flags = 0;
5036
5037         cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
5038
5039         i40e_fill_default_direct_cmd_desc(&desc,
5040                                           i40e_aqc_opc_set_port_parameters);
5041
5042         cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
5043         if (save_bad_pac)
5044                 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
5045         if (pad_short_pac)
5046                 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
5047         if (double_vlan)
5048                 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
5049         cmd->command_flags = CPU_TO_LE16(command_flags);
5050
5051         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5052
5053         return status;
5054 }
5055
5056 /**
5057  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
5058  * @hw: pointer to the hw struct
5059  * @seid: seid for the physical port/switching component/vsi
5060  * @buff: Indirect buffer to hold data parameters and response
5061  * @buff_size: Indirect buffer size
5062  * @opcode: Tx scheduler AQ command opcode
5063  * @cmd_details: pointer to command details structure or NULL
5064  *
5065  * Generic command handler for Tx scheduler AQ commands
5066  **/
5067 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
5068                                 void *buff, u16 buff_size,
5069                                  enum i40e_admin_queue_opc opcode,
5070                                 struct i40e_asq_cmd_details *cmd_details)
5071 {
5072         struct i40e_aq_desc desc;
5073         struct i40e_aqc_tx_sched_ind *cmd =
5074                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
5075         enum i40e_status_code status;
5076         bool cmd_param_flag = false;
5077
5078         switch (opcode) {
5079         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
5080         case i40e_aqc_opc_configure_vsi_tc_bw:
5081         case i40e_aqc_opc_enable_switching_comp_ets:
5082         case i40e_aqc_opc_modify_switching_comp_ets:
5083         case i40e_aqc_opc_disable_switching_comp_ets:
5084         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
5085         case i40e_aqc_opc_configure_switching_comp_bw_config:
5086                 cmd_param_flag = true;
5087                 break;
5088         case i40e_aqc_opc_query_vsi_bw_config:
5089         case i40e_aqc_opc_query_vsi_ets_sla_config:
5090         case i40e_aqc_opc_query_switching_comp_ets_config:
5091         case i40e_aqc_opc_query_port_ets_config:
5092         case i40e_aqc_opc_query_switching_comp_bw_config:
5093                 cmd_param_flag = false;
5094                 break;
5095         default:
5096                 return I40E_ERR_PARAM;
5097         }
5098
5099         i40e_fill_default_direct_cmd_desc(&desc, opcode);
5100
5101         /* Indirect command */
5102         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5103         if (cmd_param_flag)
5104                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5105         if (buff_size > I40E_AQ_LARGE_BUF)
5106                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5107
5108         desc.datalen = CPU_TO_LE16(buff_size);
5109
5110         cmd->vsi_seid = CPU_TO_LE16(seid);
5111
5112         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5113
5114         return status;
5115 }
5116
5117 /**
5118  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5119  * @hw: pointer to the hw struct
5120  * @seid: VSI seid
5121  * @credit: BW limit credits (0 = disabled)
5122  * @max_credit: Max BW limit credits
5123  * @cmd_details: pointer to command details structure or NULL
5124  **/
5125 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5126                                 u16 seid, u16 credit, u8 max_credit,
5127                                 struct i40e_asq_cmd_details *cmd_details)
5128 {
5129         struct i40e_aq_desc desc;
5130         struct i40e_aqc_configure_vsi_bw_limit *cmd =
5131                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5132         enum i40e_status_code status;
5133
5134         i40e_fill_default_direct_cmd_desc(&desc,
5135                                           i40e_aqc_opc_configure_vsi_bw_limit);
5136
5137         cmd->vsi_seid = CPU_TO_LE16(seid);
5138         cmd->credit = CPU_TO_LE16(credit);
5139         cmd->max_credit = max_credit;
5140
5141         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5142
5143         return status;
5144 }
5145
5146 /**
5147  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5148  * @hw: pointer to the hw struct
5149  * @seid: switching component seid
5150  * @credit: BW limit credits (0 = disabled)
5151  * @max_bw: Max BW limit credits
5152  * @cmd_details: pointer to command details structure or NULL
5153  **/
5154 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5155                                 u16 seid, u16 credit, u8 max_bw,
5156                                 struct i40e_asq_cmd_details *cmd_details)
5157 {
5158         struct i40e_aq_desc desc;
5159         struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5160           (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5161         enum i40e_status_code status;
5162
5163         i40e_fill_default_direct_cmd_desc(&desc,
5164                                 i40e_aqc_opc_configure_switching_comp_bw_limit);
5165
5166         cmd->seid = CPU_TO_LE16(seid);
5167         cmd->credit = CPU_TO_LE16(credit);
5168         cmd->max_bw = max_bw;
5169
5170         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5171
5172         return status;
5173 }
5174
5175 /**
5176  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5177  * @hw: pointer to the hw struct
5178  * @seid: VSI seid
5179  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5180  * @cmd_details: pointer to command details structure or NULL
5181  **/
5182 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5183                         u16 seid,
5184                         struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5185                         struct i40e_asq_cmd_details *cmd_details)
5186 {
5187         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5188                                     i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5189                                     cmd_details);
5190 }
5191
5192 /**
5193  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5194  * @hw: pointer to the hw struct
5195  * @seid: VSI seid
5196  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5197  * @cmd_details: pointer to command details structure or NULL
5198  **/
5199 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5200                         u16 seid,
5201                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5202                         struct i40e_asq_cmd_details *cmd_details)
5203 {
5204         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5205                                     i40e_aqc_opc_configure_vsi_tc_bw,
5206                                     cmd_details);
5207 }
5208
5209 /**
5210  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5211  * @hw: pointer to the hw struct
5212  * @seid: seid of the switching component connected to Physical Port
5213  * @ets_data: Buffer holding ETS parameters
5214  * @cmd_details: pointer to command details structure or NULL
5215  **/
5216 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5217                 u16 seid,
5218                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5219                 enum i40e_admin_queue_opc opcode,
5220                 struct i40e_asq_cmd_details *cmd_details)
5221 {
5222         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5223                                     sizeof(*ets_data), opcode, cmd_details);
5224 }
5225
5226 /**
5227  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5228  * @hw: pointer to the hw struct
5229  * @seid: seid of the switching component
5230  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5231  * @cmd_details: pointer to command details structure or NULL
5232  **/
5233 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5234         u16 seid,
5235         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5236         struct i40e_asq_cmd_details *cmd_details)
5237 {
5238         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5239                             i40e_aqc_opc_configure_switching_comp_bw_config,
5240                             cmd_details);
5241 }
5242
5243 /**
5244  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5245  * @hw: pointer to the hw struct
5246  * @seid: seid of the switching component
5247  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5248  * @cmd_details: pointer to command details structure or NULL
5249  **/
5250 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5251         struct i40e_hw *hw, u16 seid,
5252         struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5253         struct i40e_asq_cmd_details *cmd_details)
5254 {
5255         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5256                             i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5257                             cmd_details);
5258 }
5259
5260 /**
5261  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5262  * @hw: pointer to the hw struct
5263  * @seid: seid of the VSI
5264  * @bw_data: Buffer to hold VSI BW configuration
5265  * @cmd_details: pointer to command details structure or NULL
5266  **/
5267 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5268                         u16 seid,
5269                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5270                         struct i40e_asq_cmd_details *cmd_details)
5271 {
5272         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5273                                     i40e_aqc_opc_query_vsi_bw_config,
5274                                     cmd_details);
5275 }
5276
5277 /**
5278  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5279  * @hw: pointer to the hw struct
5280  * @seid: seid of the VSI
5281  * @bw_data: Buffer to hold VSI BW configuration per TC
5282  * @cmd_details: pointer to command details structure or NULL
5283  **/
5284 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5285                         u16 seid,
5286                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5287                         struct i40e_asq_cmd_details *cmd_details)
5288 {
5289         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5290                                     i40e_aqc_opc_query_vsi_ets_sla_config,
5291                                     cmd_details);
5292 }
5293
5294 /**
5295  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5296  * @hw: pointer to the hw struct
5297  * @seid: seid of the switching component
5298  * @bw_data: Buffer to hold switching component's per TC BW config
5299  * @cmd_details: pointer to command details structure or NULL
5300  **/
5301 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5302                 u16 seid,
5303                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5304                 struct i40e_asq_cmd_details *cmd_details)
5305 {
5306         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5307                                    i40e_aqc_opc_query_switching_comp_ets_config,
5308                                    cmd_details);
5309 }
5310
5311 /**
5312  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5313  * @hw: pointer to the hw struct
5314  * @seid: seid of the VSI or switching component connected to Physical Port
5315  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5316  * @cmd_details: pointer to command details structure or NULL
5317  **/
5318 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5319                         u16 seid,
5320                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
5321                         struct i40e_asq_cmd_details *cmd_details)
5322 {
5323         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5324                                     i40e_aqc_opc_query_port_ets_config,
5325                                     cmd_details);
5326 }
5327
5328 /**
5329  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5330  * @hw: pointer to the hw struct
5331  * @seid: seid of the switching component
5332  * @bw_data: Buffer to hold switching component's BW configuration
5333  * @cmd_details: pointer to command details structure or NULL
5334  **/
5335 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5336                 u16 seid,
5337                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5338                 struct i40e_asq_cmd_details *cmd_details)
5339 {
5340         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5341                                     i40e_aqc_opc_query_switching_comp_bw_config,
5342                                     cmd_details);
5343 }
5344
5345 /**
5346  * i40e_validate_filter_settings
5347  * @hw: pointer to the hardware structure
5348  * @settings: Filter control settings
5349  *
5350  * Check and validate the filter control settings passed.
5351  * The function checks for the valid filter/context sizes being
5352  * passed for FCoE and PE.
5353  *
5354  * Returns I40E_SUCCESS if the values passed are valid and within
5355  * range else returns an error.
5356  **/
5357 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5358                                 struct i40e_filter_control_settings *settings)
5359 {
5360         u32 fcoe_cntx_size, fcoe_filt_size;
5361         u32 pe_cntx_size, pe_filt_size;
5362         u32 fcoe_fmax;
5363
5364         u32 val;
5365
5366         /* Validate FCoE settings passed */
5367         switch (settings->fcoe_filt_num) {
5368         case I40E_HASH_FILTER_SIZE_1K:
5369         case I40E_HASH_FILTER_SIZE_2K:
5370         case I40E_HASH_FILTER_SIZE_4K:
5371         case I40E_HASH_FILTER_SIZE_8K:
5372         case I40E_HASH_FILTER_SIZE_16K:
5373         case I40E_HASH_FILTER_SIZE_32K:
5374                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5375                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5376                 break;
5377         default:
5378                 return I40E_ERR_PARAM;
5379         }
5380
5381         switch (settings->fcoe_cntx_num) {
5382         case I40E_DMA_CNTX_SIZE_512:
5383         case I40E_DMA_CNTX_SIZE_1K:
5384         case I40E_DMA_CNTX_SIZE_2K:
5385         case I40E_DMA_CNTX_SIZE_4K:
5386                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5387                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5388                 break;
5389         default:
5390                 return I40E_ERR_PARAM;
5391         }
5392
5393         /* Validate PE settings passed */
5394         switch (settings->pe_filt_num) {
5395         case I40E_HASH_FILTER_SIZE_1K:
5396         case I40E_HASH_FILTER_SIZE_2K:
5397         case I40E_HASH_FILTER_SIZE_4K:
5398         case I40E_HASH_FILTER_SIZE_8K:
5399         case I40E_HASH_FILTER_SIZE_16K:
5400         case I40E_HASH_FILTER_SIZE_32K:
5401         case I40E_HASH_FILTER_SIZE_64K:
5402         case I40E_HASH_FILTER_SIZE_128K:
5403         case I40E_HASH_FILTER_SIZE_256K:
5404         case I40E_HASH_FILTER_SIZE_512K:
5405         case I40E_HASH_FILTER_SIZE_1M:
5406                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5407                 pe_filt_size <<= (u32)settings->pe_filt_num;
5408                 break;
5409         default:
5410                 return I40E_ERR_PARAM;
5411         }
5412
5413         switch (settings->pe_cntx_num) {
5414         case I40E_DMA_CNTX_SIZE_512:
5415         case I40E_DMA_CNTX_SIZE_1K:
5416         case I40E_DMA_CNTX_SIZE_2K:
5417         case I40E_DMA_CNTX_SIZE_4K:
5418         case I40E_DMA_CNTX_SIZE_8K:
5419         case I40E_DMA_CNTX_SIZE_16K:
5420         case I40E_DMA_CNTX_SIZE_32K:
5421         case I40E_DMA_CNTX_SIZE_64K:
5422         case I40E_DMA_CNTX_SIZE_128K:
5423         case I40E_DMA_CNTX_SIZE_256K:
5424                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5425                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5426                 break;
5427         default:
5428                 return I40E_ERR_PARAM;
5429         }
5430
5431         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5432         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5433         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5434                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5435         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
5436                 return I40E_ERR_INVALID_SIZE;
5437
5438         return I40E_SUCCESS;
5439 }
5440
5441 /**
5442  * i40e_set_filter_control
5443  * @hw: pointer to the hardware structure
5444  * @settings: Filter control settings
5445  *
5446  * Set the Queue Filters for PE/FCoE and enable filters required
5447  * for a single PF. It is expected that these settings are programmed
5448  * at the driver initialization time.
5449  **/
5450 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5451                                 struct i40e_filter_control_settings *settings)
5452 {
5453         enum i40e_status_code ret = I40E_SUCCESS;
5454         u32 hash_lut_size = 0;
5455         u32 val;
5456
5457         if (!settings)
5458                 return I40E_ERR_PARAM;
5459
5460         /* Validate the input settings */
5461         ret = i40e_validate_filter_settings(hw, settings);
5462         if (ret)
5463                 return ret;
5464
5465         /* Read the PF Queue Filter control register */
5466         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5467
5468         /* Program required PE hash buckets for the PF */
5469         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5470         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5471                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5472         /* Program required PE contexts for the PF */
5473         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5474         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5475                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5476
5477         /* Program required FCoE hash buckets for the PF */
5478         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5479         val |= ((u32)settings->fcoe_filt_num <<
5480                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5481                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5482         /* Program required FCoE DDP contexts for the PF */
5483         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5484         val |= ((u32)settings->fcoe_cntx_num <<
5485                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5486                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5487
5488         /* Program Hash LUT size for the PF */
5489         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5490         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5491                 hash_lut_size = 1;
5492         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5493                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5494
5495         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5496         if (settings->enable_fdir)
5497                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5498         if (settings->enable_ethtype)
5499                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5500         if (settings->enable_macvlan)
5501                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5502
5503         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5504
5505         return I40E_SUCCESS;
5506 }
5507
5508 /**
5509  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5510  * @hw: pointer to the hw struct
5511  * @mac_addr: MAC address to use in the filter
5512  * @ethtype: Ethertype to use in the filter
5513  * @flags: Flags that needs to be applied to the filter
5514  * @vsi_seid: seid of the control VSI
5515  * @queue: VSI queue number to send the packet to
5516  * @is_add: Add control packet filter if True else remove
5517  * @stats: Structure to hold information on control filter counts
5518  * @cmd_details: pointer to command details structure or NULL
5519  *
5520  * This command will Add or Remove control packet filter for a control VSI.
5521  * In return it will update the total number of perfect filter count in
5522  * the stats member.
5523  **/
5524 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5525                                 u8 *mac_addr, u16 ethtype, u16 flags,
5526                                 u16 vsi_seid, u16 queue, bool is_add,
5527                                 struct i40e_control_filter_stats *stats,
5528                                 struct i40e_asq_cmd_details *cmd_details)
5529 {
5530         struct i40e_aq_desc desc;
5531         struct i40e_aqc_add_remove_control_packet_filter *cmd =
5532                 (struct i40e_aqc_add_remove_control_packet_filter *)
5533                 &desc.params.raw;
5534         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5535                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5536                 &desc.params.raw;
5537         enum i40e_status_code status;
5538
5539         if (vsi_seid == 0)
5540                 return I40E_ERR_PARAM;
5541
5542         if (is_add) {
5543                 i40e_fill_default_direct_cmd_desc(&desc,
5544                                 i40e_aqc_opc_add_control_packet_filter);
5545                 cmd->queue = CPU_TO_LE16(queue);
5546         } else {
5547                 i40e_fill_default_direct_cmd_desc(&desc,
5548                                 i40e_aqc_opc_remove_control_packet_filter);
5549         }
5550
5551         if (mac_addr)
5552                 i40e_memcpy(cmd->mac, mac_addr, ETH_ALEN,
5553                             I40E_NONDMA_TO_NONDMA);
5554
5555         cmd->etype = CPU_TO_LE16(ethtype);
5556         cmd->flags = CPU_TO_LE16(flags);
5557         cmd->seid = CPU_TO_LE16(vsi_seid);
5558
5559         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5560
5561         if (!status && stats) {
5562                 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5563                 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5564                 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5565                 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5566         }
5567
5568         return status;
5569 }
5570
5571 /**
5572  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5573  * @hw: pointer to the hw struct
5574  * @seid: VSI seid to add ethertype filter from
5575  **/
5576 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5577 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5578                                                     u16 seid)
5579 {
5580         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5581                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5582                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5583         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5584         enum i40e_status_code status;
5585
5586         status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5587                                                        seid, 0, true, NULL,
5588                                                        NULL);
5589         if (status)
5590                 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5591 }
5592
5593 /**
5594  * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5595  * @filters: list of cloud filters
5596  * @filter_count: length of list
5597  *
5598  * There's an issue in the device where the Geneve VNI layout needs
5599  * to be shifted 1 byte over from the VxLAN VNI
5600  **/
5601 STATIC void i40e_fix_up_geneve_vni(
5602         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5603         u8 filter_count)
5604 {
5605         struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters;
5606         int i;
5607
5608         for (i = 0; i < filter_count; i++) {
5609                 u16 tnl_type;
5610                 u32 ti;
5611
5612                 tnl_type = (LE16_TO_CPU(f[i].flags) &
5613                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5614                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5615                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5616                         ti = LE32_TO_CPU(f[i].tenant_id);
5617                         f[i].tenant_id = CPU_TO_LE32(ti << 8);
5618                 }
5619         }
5620 }
5621
5622 /**
5623  * i40e_aq_add_cloud_filters
5624  * @hw: pointer to the hardware structure
5625  * @seid: VSI seid to add cloud filters from
5626  * @filters: Buffer which contains the filters to be added
5627  * @filter_count: number of filters contained in the buffer
5628  *
5629  * Set the cloud filters for a given VSI.  The contents of the
5630  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5631  * in by the caller of the function.
5632  *
5633  **/
5634 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5635         u16 seid,
5636         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5637         u8 filter_count)
5638 {
5639         struct i40e_aq_desc desc;
5640         struct i40e_aqc_add_remove_cloud_filters *cmd =
5641         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5642         enum i40e_status_code status;
5643         u16 buff_len;
5644
5645         i40e_fill_default_direct_cmd_desc(&desc,
5646                                           i40e_aqc_opc_add_cloud_filters);
5647
5648         buff_len = filter_count * sizeof(*filters);
5649         desc.datalen = CPU_TO_LE16(buff_len);
5650         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5651         cmd->num_filters = filter_count;
5652         cmd->seid = CPU_TO_LE16(seid);
5653
5654         i40e_fix_up_geneve_vni(filters, filter_count);
5655
5656         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5657
5658         return status;
5659 }
5660
5661 /**
5662  * i40e_aq_add_cloud_filters_big_buffer
5663  * @hw: pointer to the hardware structure
5664  * @seid: VSI seid to add cloud filters from
5665  * @filters: Buffer which contains the filters in big buffer to be added
5666  * @filter_count: number of filters contained in the buffer
5667  *
5668  * Set the cloud filters for a given VSI.  The contents of the
5669  * i40e_aqc_add_rm_cloud_filt_elem_ext are filled in by the caller of
5670  * the function.
5671  *
5672  **/
5673 enum i40e_status_code i40e_aq_add_cloud_filters_big_buffer(struct i40e_hw *hw,
5674         u16 seid,
5675         struct i40e_aqc_add_rm_cloud_filt_elem_ext *filters,
5676         u8 filter_count)
5677 {
5678         struct i40e_aq_desc desc;
5679         struct i40e_aqc_add_remove_cloud_filters *cmd =
5680         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5681         enum i40e_status_code status;
5682         u16 buff_len;
5683         int i;
5684
5685         i40e_fill_default_direct_cmd_desc(&desc,
5686                                           i40e_aqc_opc_add_cloud_filters);
5687
5688         buff_len = filter_count * sizeof(*filters);
5689         desc.datalen = CPU_TO_LE16(buff_len);
5690         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5691         cmd->num_filters = filter_count;
5692         cmd->seid = CPU_TO_LE16(seid);
5693         cmd->big_buffer_flag = I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER;
5694
5695         /* adjust Geneve VNI for HW issue */
5696         for (i = 0; i < filter_count; i++) {
5697                 u16 tnl_type;
5698                 u32 ti;
5699
5700                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5701                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5702                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5703                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5704                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5705                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5706                 }
5707         }
5708
5709         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5710
5711         return status;
5712 }
5713
5714 /**
5715  * i40e_aq_remove_cloud_filters
5716  * @hw: pointer to the hardware structure
5717  * @seid: VSI seid to remove cloud filters from
5718  * @filters: Buffer which contains the filters to be removed
5719  * @filter_count: number of filters contained in the buffer
5720  *
5721  * Remove the cloud filters for a given VSI.  The contents of the
5722  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5723  * in by the caller of the function.
5724  *
5725  **/
5726 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5727         u16 seid,
5728         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5729         u8 filter_count)
5730 {
5731         struct i40e_aq_desc desc;
5732         struct i40e_aqc_add_remove_cloud_filters *cmd =
5733         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5734         enum i40e_status_code status;
5735         u16 buff_len;
5736
5737         i40e_fill_default_direct_cmd_desc(&desc,
5738                                           i40e_aqc_opc_remove_cloud_filters);
5739
5740         buff_len = filter_count * sizeof(*filters);
5741         desc.datalen = CPU_TO_LE16(buff_len);
5742         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5743         cmd->num_filters = filter_count;
5744         cmd->seid = CPU_TO_LE16(seid);
5745
5746         i40e_fix_up_geneve_vni(filters, filter_count);
5747
5748         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5749
5750         return status;
5751 }
5752
5753 /**
5754  * i40e_aq_remove_cloud_filters_big_buffer
5755  * @hw: pointer to the hardware structure
5756  * @seid: VSI seid to remove cloud filters from
5757  * @filters: Buffer which contains the filters in big buffer to be removed
5758  * @filter_count: number of filters contained in the buffer
5759  *
5760  * Remove the cloud filters for a given VSI.  The contents of the
5761  * i40e_aqc_add_rm_cloud_filt_elem_ext are filled in by the caller of
5762  * the function.
5763  *
5764  **/
5765 enum i40e_status_code i40e_aq_remove_cloud_filters_big_buffer(
5766         struct i40e_hw *hw,
5767         u16 seid,
5768         struct i40e_aqc_add_rm_cloud_filt_elem_ext *filters,
5769         u8 filter_count)
5770 {
5771         struct i40e_aq_desc desc;
5772         struct i40e_aqc_add_remove_cloud_filters *cmd =
5773         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5774         enum i40e_status_code status;
5775         u16 buff_len;
5776         int i;
5777
5778         i40e_fill_default_direct_cmd_desc(&desc,
5779                                           i40e_aqc_opc_remove_cloud_filters);
5780
5781         buff_len = filter_count * sizeof(*filters);
5782         desc.datalen = CPU_TO_LE16(buff_len);
5783         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5784         cmd->num_filters = filter_count;
5785         cmd->seid = CPU_TO_LE16(seid);
5786         cmd->big_buffer_flag = I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER;
5787
5788         /* adjust Geneve VNI for HW issue */
5789         for (i = 0; i < filter_count; i++) {
5790                 u16 tnl_type;
5791                 u32 ti;
5792
5793                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5794                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5795                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5796                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5797                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5798                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5799                 }
5800         }
5801
5802         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5803
5804         return status;
5805 }
5806
5807 /**
5808  * i40e_aq_replace_cloud_filters - Replace cloud filter command
5809  * @hw: pointer to the hw struct
5810  * @filters: pointer to the i40e_aqc_replace_cloud_filter_cmd struct
5811  * @cmd_buf: pointer to the i40e_aqc_replace_cloud_filter_cmd_buf struct
5812  *
5813  **/
5814 enum
5815 i40e_status_code i40e_aq_replace_cloud_filters(struct i40e_hw *hw,
5816         struct i40e_aqc_replace_cloud_filters_cmd *filters,
5817         struct i40e_aqc_replace_cloud_filters_cmd_buf *cmd_buf)
5818 {
5819         struct i40e_aq_desc desc;
5820         struct i40e_aqc_replace_cloud_filters_cmd *cmd =
5821                 (struct i40e_aqc_replace_cloud_filters_cmd *)&desc.params.raw;
5822         enum i40e_status_code status = I40E_SUCCESS;
5823         int i = 0;
5824
5825         i40e_fill_default_direct_cmd_desc(&desc,
5826                                           i40e_aqc_opc_replace_cloud_filters);
5827
5828         desc.datalen = CPU_TO_LE16(32);
5829         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5830         cmd->old_filter_type = filters->old_filter_type;
5831         cmd->new_filter_type = filters->new_filter_type;
5832         cmd->valid_flags = filters->valid_flags;
5833         cmd->tr_bit = filters->tr_bit;
5834
5835         status = i40e_asq_send_command(hw, &desc, cmd_buf,
5836                 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf),  NULL);
5837
5838         /* for get cloud filters command */
5839         for (i = 0; i < 32; i += 4) {
5840                 cmd_buf->filters[i / 4].filter_type = cmd_buf->data[i];
5841                 cmd_buf->filters[i / 4].input[0] = cmd_buf->data[i + 1];
5842                 cmd_buf->filters[i / 4].input[1] = cmd_buf->data[i + 2];
5843                 cmd_buf->filters[i / 4].input[2] = cmd_buf->data[i + 3];
5844         }
5845
5846         return status;
5847 }
5848
5849
5850 /**
5851  * i40e_aq_alternate_write
5852  * @hw: pointer to the hardware structure
5853  * @reg_addr0: address of first dword to be read
5854  * @reg_val0: value to be written under 'reg_addr0'
5855  * @reg_addr1: address of second dword to be read
5856  * @reg_val1: value to be written under 'reg_addr1'
5857  *
5858  * Write one or two dwords to alternate structure. Fields are indicated
5859  * by 'reg_addr0' and 'reg_addr1' register numbers.
5860  *
5861  **/
5862 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5863                                 u32 reg_addr0, u32 reg_val0,
5864                                 u32 reg_addr1, u32 reg_val1)
5865 {
5866         struct i40e_aq_desc desc;
5867         struct i40e_aqc_alternate_write *cmd_resp =
5868                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5869         enum i40e_status_code status;
5870
5871         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5872         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5873         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5874         cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5875         cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5876
5877         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5878
5879         return status;
5880 }
5881
5882 /**
5883  * i40e_aq_alternate_write_indirect
5884  * @hw: pointer to the hardware structure
5885  * @addr: address of a first register to be modified
5886  * @dw_count: number of alternate structure fields to write
5887  * @buffer: pointer to the command buffer
5888  *
5889  * Write 'dw_count' dwords from 'buffer' to alternate structure
5890  * starting at 'addr'.
5891  *
5892  **/
5893 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5894                                 u32 addr, u32 dw_count, void *buffer)
5895 {
5896         struct i40e_aq_desc desc;
5897         struct i40e_aqc_alternate_ind_write *cmd_resp =
5898                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5899         enum i40e_status_code status;
5900
5901         if (buffer == NULL)
5902                 return I40E_ERR_PARAM;
5903
5904         /* Indirect command */
5905         i40e_fill_default_direct_cmd_desc(&desc,
5906                                          i40e_aqc_opc_alternate_write_indirect);
5907
5908         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5909         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5910         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5911                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5912
5913         cmd_resp->address = CPU_TO_LE32(addr);
5914         cmd_resp->length = CPU_TO_LE32(dw_count);
5915
5916         status = i40e_asq_send_command(hw, &desc, buffer,
5917                                        I40E_LO_DWORD(4*dw_count), NULL);
5918
5919         return status;
5920 }
5921
5922 /**
5923  * i40e_aq_alternate_read
5924  * @hw: pointer to the hardware structure
5925  * @reg_addr0: address of first dword to be read
5926  * @reg_val0: pointer for data read from 'reg_addr0'
5927  * @reg_addr1: address of second dword to be read
5928  * @reg_val1: pointer for data read from 'reg_addr1'
5929  *
5930  * Read one or two dwords from alternate structure. Fields are indicated
5931  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5932  * is not passed then only register at 'reg_addr0' is read.
5933  *
5934  **/
5935 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5936                                 u32 reg_addr0, u32 *reg_val0,
5937                                 u32 reg_addr1, u32 *reg_val1)
5938 {
5939         struct i40e_aq_desc desc;
5940         struct i40e_aqc_alternate_write *cmd_resp =
5941                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5942         enum i40e_status_code status;
5943
5944         if (reg_val0 == NULL)
5945                 return I40E_ERR_PARAM;
5946
5947         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5948         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5949         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5950
5951         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5952
5953         if (status == I40E_SUCCESS) {
5954                 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5955
5956                 if (reg_val1 != NULL)
5957                         *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5958         }
5959
5960         return status;
5961 }
5962
5963 /**
5964  * i40e_aq_alternate_read_indirect
5965  * @hw: pointer to the hardware structure
5966  * @addr: address of the alternate structure field
5967  * @dw_count: number of alternate structure fields to read
5968  * @buffer: pointer to the command buffer
5969  *
5970  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5971  * place them in 'buffer'. The buffer should be allocated by caller.
5972  *
5973  **/
5974 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5975                                 u32 addr, u32 dw_count, void *buffer)
5976 {
5977         struct i40e_aq_desc desc;
5978         struct i40e_aqc_alternate_ind_write *cmd_resp =
5979                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5980         enum i40e_status_code status;
5981
5982         if (buffer == NULL)
5983                 return I40E_ERR_PARAM;
5984
5985         /* Indirect command */
5986         i40e_fill_default_direct_cmd_desc(&desc,
5987                 i40e_aqc_opc_alternate_read_indirect);
5988
5989         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5990         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5991         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5992                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5993
5994         cmd_resp->address = CPU_TO_LE32(addr);
5995         cmd_resp->length = CPU_TO_LE32(dw_count);
5996
5997         status = i40e_asq_send_command(hw, &desc, buffer,
5998                                        I40E_LO_DWORD(4*dw_count), NULL);
5999
6000         return status;
6001 }
6002
6003 /**
6004  *  i40e_aq_alternate_clear
6005  *  @hw: pointer to the HW structure.
6006  *
6007  *  Clear the alternate structures of the port from which the function
6008  *  is called.
6009  *
6010  **/
6011 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
6012 {
6013         struct i40e_aq_desc desc;
6014         enum i40e_status_code status;
6015
6016         i40e_fill_default_direct_cmd_desc(&desc,
6017                                           i40e_aqc_opc_alternate_clear_port);
6018
6019         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6020
6021         return status;
6022 }
6023
6024 /**
6025  *  i40e_aq_alternate_write_done
6026  *  @hw: pointer to the HW structure.
6027  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
6028  *  @reset_needed: indicates the SW should trigger GLOBAL reset
6029  *
6030  *  Indicates to the FW that alternate structures have been changed.
6031  *
6032  **/
6033 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
6034                 u8 bios_mode, bool *reset_needed)
6035 {
6036         struct i40e_aq_desc desc;
6037         struct i40e_aqc_alternate_write_done *cmd =
6038                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6039         enum i40e_status_code status;
6040
6041         if (reset_needed == NULL)
6042                 return I40E_ERR_PARAM;
6043
6044         i40e_fill_default_direct_cmd_desc(&desc,
6045                                           i40e_aqc_opc_alternate_write_done);
6046
6047         cmd->cmd_flags = CPU_TO_LE16(bios_mode);
6048
6049         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6050         if (!status && reset_needed)
6051                 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
6052                                  I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
6053
6054         return status;
6055 }
6056
6057 /**
6058  *  i40e_aq_set_oem_mode
6059  *  @hw: pointer to the HW structure.
6060  *  @oem_mode: the OEM mode to be used
6061  *
6062  *  Sets the device to a specific operating mode. Currently the only supported
6063  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
6064  *
6065  **/
6066 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
6067                 u8 oem_mode)
6068 {
6069         struct i40e_aq_desc desc;
6070         struct i40e_aqc_alternate_write_done *cmd =
6071                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6072         enum i40e_status_code status;
6073
6074         i40e_fill_default_direct_cmd_desc(&desc,
6075                                           i40e_aqc_opc_alternate_set_mode);
6076
6077         cmd->cmd_flags = CPU_TO_LE16(oem_mode);
6078
6079         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6080
6081         return status;
6082 }
6083
6084 /**
6085  * i40e_aq_resume_port_tx
6086  * @hw: pointer to the hardware structure
6087  * @cmd_details: pointer to command details structure or NULL
6088  *
6089  * Resume port's Tx traffic
6090  **/
6091 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
6092                                 struct i40e_asq_cmd_details *cmd_details)
6093 {
6094         struct i40e_aq_desc desc;
6095         enum i40e_status_code status;
6096
6097         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
6098
6099         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6100
6101         return status;
6102 }
6103
6104 /**
6105  * i40e_set_pci_config_data - store PCI bus info
6106  * @hw: pointer to hardware structure
6107  * @link_status: the link status word from PCI config space
6108  *
6109  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
6110  **/
6111 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
6112 {
6113         hw->bus.type = i40e_bus_type_pci_express;
6114
6115         switch (link_status & I40E_PCI_LINK_WIDTH) {
6116         case I40E_PCI_LINK_WIDTH_1:
6117                 hw->bus.width = i40e_bus_width_pcie_x1;
6118                 break;
6119         case I40E_PCI_LINK_WIDTH_2:
6120                 hw->bus.width = i40e_bus_width_pcie_x2;
6121                 break;
6122         case I40E_PCI_LINK_WIDTH_4:
6123                 hw->bus.width = i40e_bus_width_pcie_x4;
6124                 break;
6125         case I40E_PCI_LINK_WIDTH_8:
6126                 hw->bus.width = i40e_bus_width_pcie_x8;
6127                 break;
6128         default:
6129                 hw->bus.width = i40e_bus_width_unknown;
6130                 break;
6131         }
6132
6133         switch (link_status & I40E_PCI_LINK_SPEED) {
6134         case I40E_PCI_LINK_SPEED_2500:
6135                 hw->bus.speed = i40e_bus_speed_2500;
6136                 break;
6137         case I40E_PCI_LINK_SPEED_5000:
6138                 hw->bus.speed = i40e_bus_speed_5000;
6139                 break;
6140         case I40E_PCI_LINK_SPEED_8000:
6141                 hw->bus.speed = i40e_bus_speed_8000;
6142                 break;
6143         default:
6144                 hw->bus.speed = i40e_bus_speed_unknown;
6145                 break;
6146         }
6147 }
6148
6149 /**
6150  * i40e_aq_debug_dump
6151  * @hw: pointer to the hardware structure
6152  * @cluster_id: specific cluster to dump
6153  * @table_id: table id within cluster
6154  * @start_index: index of line in the block to read
6155  * @buff_size: dump buffer size
6156  * @buff: dump buffer
6157  * @ret_buff_size: actual buffer size returned
6158  * @ret_next_table: next block to read
6159  * @ret_next_index: next index to read
6160  *
6161  * Dump internal FW/HW data for debug purposes.
6162  *
6163  **/
6164 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
6165                                 u8 table_id, u32 start_index, u16 buff_size,
6166                                 void *buff, u16 *ret_buff_size,
6167                                 u8 *ret_next_table, u32 *ret_next_index,
6168                                 struct i40e_asq_cmd_details *cmd_details)
6169 {
6170         struct i40e_aq_desc desc;
6171         struct i40e_aqc_debug_dump_internals *cmd =
6172                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6173         struct i40e_aqc_debug_dump_internals *resp =
6174                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6175         enum i40e_status_code status;
6176
6177         if (buff_size == 0 || !buff)
6178                 return I40E_ERR_PARAM;
6179
6180         i40e_fill_default_direct_cmd_desc(&desc,
6181                                           i40e_aqc_opc_debug_dump_internals);
6182         /* Indirect Command */
6183         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6184         if (buff_size > I40E_AQ_LARGE_BUF)
6185                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6186
6187         cmd->cluster_id = cluster_id;
6188         cmd->table_id = table_id;
6189         cmd->idx = CPU_TO_LE32(start_index);
6190
6191         desc.datalen = CPU_TO_LE16(buff_size);
6192
6193         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
6194         if (!status) {
6195                 if (ret_buff_size != NULL)
6196                         *ret_buff_size = LE16_TO_CPU(desc.datalen);
6197                 if (ret_next_table != NULL)
6198                         *ret_next_table = resp->table_id;
6199                 if (ret_next_index != NULL)
6200                         *ret_next_index = LE32_TO_CPU(resp->idx);
6201         }
6202
6203         return status;
6204 }
6205
6206 /**
6207  * i40e_read_bw_from_alt_ram
6208  * @hw: pointer to the hardware structure
6209  * @max_bw: pointer for max_bw read
6210  * @min_bw: pointer for min_bw read
6211  * @min_valid: pointer for bool that is true if min_bw is a valid value
6212  * @max_valid: pointer for bool that is true if max_bw is a valid value
6213  *
6214  * Read bw from the alternate ram for the given pf
6215  **/
6216 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
6217                                         u32 *max_bw, u32 *min_bw,
6218                                         bool *min_valid, bool *max_valid)
6219 {
6220         enum i40e_status_code status;
6221         u32 max_bw_addr, min_bw_addr;
6222
6223         /* Calculate the address of the min/max bw registers */
6224         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6225                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
6226                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6227         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6228                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
6229                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6230
6231         /* Read the bandwidths from alt ram */
6232         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
6233                                         min_bw_addr, min_bw);
6234
6235         if (*min_bw & I40E_ALT_BW_VALID_MASK)
6236                 *min_valid = true;
6237         else
6238                 *min_valid = false;
6239
6240         if (*max_bw & I40E_ALT_BW_VALID_MASK)
6241                 *max_valid = true;
6242         else
6243                 *max_valid = false;
6244
6245         return status;
6246 }
6247
6248 /**
6249  * i40e_aq_configure_partition_bw
6250  * @hw: pointer to the hardware structure
6251  * @bw_data: Buffer holding valid pfs and bw limits
6252  * @cmd_details: pointer to command details
6253  *
6254  * Configure partitions guaranteed/max bw
6255  **/
6256 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6257                         struct i40e_aqc_configure_partition_bw_data *bw_data,
6258                         struct i40e_asq_cmd_details *cmd_details)
6259 {
6260         enum i40e_status_code status;
6261         struct i40e_aq_desc desc;
6262         u16 bwd_size = sizeof(*bw_data);
6263
6264         i40e_fill_default_direct_cmd_desc(&desc,
6265                                 i40e_aqc_opc_configure_partition_bw);
6266
6267         /* Indirect command */
6268         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6269         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6270
6271         desc.datalen = CPU_TO_LE16(bwd_size);
6272
6273         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6274
6275         return status;
6276 }
6277
6278 /**
6279  * i40e_read_phy_register_clause22
6280  * @hw: pointer to the HW structure
6281  * @reg: register address in the page
6282  * @phy_adr: PHY address on MDIO interface
6283  * @value: PHY register value
6284  *
6285  * Reads specified PHY register value
6286  **/
6287 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
6288                                         u16 reg, u8 phy_addr, u16 *value)
6289 {
6290         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6291         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6292         u32 command = 0;
6293         u16 retry = 1000;
6294
6295         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6296                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6297                   (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
6298                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6299                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6300         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6301         do {
6302                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6303                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6304                         status = I40E_SUCCESS;
6305                         break;
6306                 }
6307                 i40e_usec_delay(10);
6308                 retry--;
6309         } while (retry);
6310
6311         if (status) {
6312                 i40e_debug(hw, I40E_DEBUG_PHY,
6313                            "PHY: Can't write command to external PHY.\n");
6314         } else {
6315                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6316                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6317                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6318         }
6319
6320         return status;
6321 }
6322
6323 /**
6324  * i40e_write_phy_register_clause22
6325  * @hw: pointer to the HW structure
6326  * @reg: register address in the page
6327  * @phy_adr: PHY address on MDIO interface
6328  * @value: PHY register value
6329  *
6330  * Writes specified PHY register value
6331  **/
6332 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6333                                         u16 reg, u8 phy_addr, u16 value)
6334 {
6335         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6336         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6337         u32 command  = 0;
6338         u16 retry = 1000;
6339
6340         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6341         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6342
6343         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6344                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6345                   (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6346                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6347                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6348
6349         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6350         do {
6351                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6352                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6353                         status = I40E_SUCCESS;
6354                         break;
6355                 }
6356                 i40e_usec_delay(10);
6357                 retry--;
6358         } while (retry);
6359
6360         return status;
6361 }
6362
6363 /**
6364  * i40e_read_phy_register_clause45
6365  * @hw: pointer to the HW structure
6366  * @page: registers page number
6367  * @reg: register address in the page
6368  * @phy_adr: PHY address on MDIO interface
6369  * @value: PHY register value
6370  *
6371  * Reads specified PHY register value
6372  **/
6373 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6374                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6375 {
6376         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6377         u32 command  = 0;
6378         u16 retry = 1000;
6379         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6380
6381         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6382                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6383                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6384                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6385                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6386                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6387                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6388         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6389         do {
6390                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6391                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6392                         status = I40E_SUCCESS;
6393                         break;
6394                 }
6395                 i40e_usec_delay(10);
6396                 retry--;
6397         } while (retry);
6398
6399         if (status) {
6400                 i40e_debug(hw, I40E_DEBUG_PHY,
6401                            "PHY: Can't write command to external PHY.\n");
6402                 goto phy_read_end;
6403         }
6404
6405         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6406                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6407                   (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6408                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6409                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6410                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6411         status = I40E_ERR_TIMEOUT;
6412         retry = 1000;
6413         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6414         do {
6415                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6416                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6417                         status = I40E_SUCCESS;
6418                         break;
6419                 }
6420                 i40e_usec_delay(10);
6421                 retry--;
6422         } while (retry);
6423
6424         if (!status) {
6425                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6426                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6427                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6428         } else {
6429                 i40e_debug(hw, I40E_DEBUG_PHY,
6430                            "PHY: Can't read register value from external PHY.\n");
6431         }
6432
6433 phy_read_end:
6434         return status;
6435 }
6436
6437 /**
6438  * i40e_write_phy_register_clause45
6439  * @hw: pointer to the HW structure
6440  * @page: registers page number
6441  * @reg: register address in the page
6442  * @phy_adr: PHY address on MDIO interface
6443  * @value: PHY register value
6444  *
6445  * Writes value to specified PHY register
6446  **/
6447 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6448                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6449 {
6450         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6451         u32 command  = 0;
6452         u16 retry = 1000;
6453         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6454
6455         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6456                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6457                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6458                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6459                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6460                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6461                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6462         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6463         do {
6464                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6465                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6466                         status = I40E_SUCCESS;
6467                         break;
6468                 }
6469                 i40e_usec_delay(10);
6470                 retry--;
6471         } while (retry);
6472         if (status) {
6473                 i40e_debug(hw, I40E_DEBUG_PHY,
6474                            "PHY: Can't write command to external PHY.\n");
6475                 goto phy_write_end;
6476         }
6477
6478         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6479         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6480
6481         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6482                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6483                   (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6484                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6485                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6486                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6487         status = I40E_ERR_TIMEOUT;
6488         retry = 1000;
6489         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6490         do {
6491                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6492                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6493                         status = I40E_SUCCESS;
6494                         break;
6495                 }
6496                 i40e_usec_delay(10);
6497                 retry--;
6498         } while (retry);
6499
6500 phy_write_end:
6501         return status;
6502 }
6503
6504 /**
6505  * i40e_write_phy_register
6506  * @hw: pointer to the HW structure
6507  * @page: registers page number
6508  * @reg: register address in the page
6509  * @phy_adr: PHY address on MDIO interface
6510  * @value: PHY register value
6511  *
6512  * Writes value to specified PHY register
6513  **/
6514 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6515                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6516 {
6517         enum i40e_status_code status;
6518
6519         switch (hw->device_id) {
6520         case I40E_DEV_ID_1G_BASE_T_X722:
6521                 status = i40e_write_phy_register_clause22(hw,
6522                         reg, phy_addr, value);
6523                 break;
6524         case I40E_DEV_ID_10G_BASE_T:
6525         case I40E_DEV_ID_10G_BASE_T4:
6526         case I40E_DEV_ID_10G_BASE_T_X722:
6527         case I40E_DEV_ID_25G_B:
6528         case I40E_DEV_ID_25G_SFP28:
6529                 status = i40e_write_phy_register_clause45(hw,
6530                         page, reg, phy_addr, value);
6531                 break;
6532         default:
6533                 status = I40E_ERR_UNKNOWN_PHY;
6534                 break;
6535         }
6536
6537         return status;
6538 }
6539
6540 /**
6541  * i40e_read_phy_register
6542  * @hw: pointer to the HW structure
6543  * @page: registers page number
6544  * @reg: register address in the page
6545  * @phy_adr: PHY address on MDIO interface
6546  * @value: PHY register value
6547  *
6548  * Reads specified PHY register value
6549  **/
6550 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6551                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6552 {
6553         enum i40e_status_code status;
6554
6555         switch (hw->device_id) {
6556         case I40E_DEV_ID_1G_BASE_T_X722:
6557                 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6558                                                          value);
6559                 break;
6560         case I40E_DEV_ID_10G_BASE_T:
6561         case I40E_DEV_ID_10G_BASE_T4:
6562         case I40E_DEV_ID_10G_BASE_T_X722:
6563         case I40E_DEV_ID_25G_B:
6564         case I40E_DEV_ID_25G_SFP28:
6565                 status = i40e_read_phy_register_clause45(hw, page, reg,
6566                                                          phy_addr, value);
6567                 break;
6568         default:
6569                 status = I40E_ERR_UNKNOWN_PHY;
6570                 break;
6571         }
6572
6573         return status;
6574 }
6575
6576 /**
6577  * i40e_get_phy_address
6578  * @hw: pointer to the HW structure
6579  * @dev_num: PHY port num that address we want
6580  * @phy_addr: Returned PHY address
6581  *
6582  * Gets PHY address for current port
6583  **/
6584 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6585 {
6586         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6587         u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6588
6589         return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6590 }
6591
6592 /**
6593  * i40e_blink_phy_led
6594  * @hw: pointer to the HW structure
6595  * @time: time how long led will blinks in secs
6596  * @interval: gap between LED on and off in msecs
6597  *
6598  * Blinks PHY link LED
6599  **/
6600 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6601                                               u32 time, u32 interval)
6602 {
6603         enum i40e_status_code status = I40E_SUCCESS;
6604         u32 i;
6605         u16 led_ctl = 0;
6606         u16 gpio_led_port;
6607         u16 led_reg;
6608         u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6609         u8 phy_addr = 0;
6610         u8 port_num;
6611
6612         i = rd32(hw, I40E_PFGEN_PORTNUM);
6613         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6614         phy_addr = i40e_get_phy_address(hw, port_num);
6615
6616         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6617              led_addr++) {
6618                 status = i40e_read_phy_register_clause45(hw,
6619                                                          I40E_PHY_COM_REG_PAGE,
6620                                                          led_addr, phy_addr,
6621                                                          &led_reg);
6622                 if (status)
6623                         goto phy_blinking_end;
6624                 led_ctl = led_reg;
6625                 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6626                         led_reg = 0;
6627                         status = i40e_write_phy_register_clause45(hw,
6628                                                          I40E_PHY_COM_REG_PAGE,
6629                                                          led_addr, phy_addr,
6630                                                          led_reg);
6631                         if (status)
6632                                 goto phy_blinking_end;
6633                         break;
6634                 }
6635         }
6636
6637         if (time > 0 && interval > 0) {
6638                 for (i = 0; i < time * 1000; i += interval) {
6639                         status = i40e_read_phy_register_clause45(hw,
6640                                                 I40E_PHY_COM_REG_PAGE,
6641                                                 led_addr, phy_addr, &led_reg);
6642                         if (status)
6643                                 goto restore_config;
6644                         if (led_reg & I40E_PHY_LED_MANUAL_ON)
6645                                 led_reg = 0;
6646                         else
6647                                 led_reg = I40E_PHY_LED_MANUAL_ON;
6648                         status = i40e_write_phy_register_clause45(hw,
6649                                                 I40E_PHY_COM_REG_PAGE,
6650                                                 led_addr, phy_addr, led_reg);
6651                         if (status)
6652                                 goto restore_config;
6653                         i40e_msec_delay(interval);
6654                 }
6655         }
6656
6657 restore_config:
6658         status = i40e_write_phy_register_clause45(hw,
6659                                                   I40E_PHY_COM_REG_PAGE,
6660                                                   led_addr, phy_addr, led_ctl);
6661
6662 phy_blinking_end:
6663         return status;
6664 }
6665
6666 /**
6667  * i40e_led_get_phy - return current on/off mode
6668  * @hw: pointer to the hw struct
6669  * @led_addr: address of led register to use
6670  * @val: original value of register to use
6671  *
6672  **/
6673 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6674                                        u16 *val)
6675 {
6676         enum i40e_status_code status = I40E_SUCCESS;
6677         u16 gpio_led_port;
6678         u8 phy_addr = 0;
6679         u16 reg_val;
6680         u16 temp_addr;
6681         u8 port_num;
6682         u32 i;
6683         u32 reg_val_aq;
6684
6685         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6686                 status =
6687                       i40e_aq_get_phy_register(hw,
6688                                                I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6689                                                I40E_PHY_COM_REG_PAGE,
6690                                                I40E_PHY_LED_PROV_REG_1,
6691                                                &reg_val_aq, NULL);
6692                 if (status)
6693                         return status;
6694                 *val = (u16)reg_val_aq;
6695         } else {
6696                 temp_addr = I40E_PHY_LED_PROV_REG_1;
6697                 i = rd32(hw, I40E_PFGEN_PORTNUM);
6698                 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6699                 phy_addr = i40e_get_phy_address(hw, port_num);
6700
6701                 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6702                      temp_addr++) {
6703                         status =
6704                          i40e_read_phy_register_clause45(hw,
6705                                                          I40E_PHY_COM_REG_PAGE,
6706                                                          temp_addr, phy_addr,
6707                                                          &reg_val);
6708                         if (status)
6709                                 return status;
6710                         *val = reg_val;
6711                         if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6712                                 *led_addr = temp_addr;
6713                                 break;
6714                         }
6715                 }
6716         }
6717         return status;
6718 }
6719
6720 /**
6721  * i40e_led_set_phy
6722  * @hw: pointer to the HW structure
6723  * @on: true or false
6724  * @mode: original val plus bit for set or ignore
6725  * Set led's on or off when controlled by the PHY
6726  *
6727  **/
6728 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6729                                        u16 led_addr, u32 mode)
6730 {
6731         enum i40e_status_code status = I40E_SUCCESS;
6732         u32 led_ctl = 0;
6733         u32 led_reg = 0;
6734         u8 phy_addr = 0;
6735         u8 port_num;
6736         u32 i;
6737
6738         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6739                 status =
6740                       i40e_aq_get_phy_register(hw,
6741                                                I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6742                                                I40E_PHY_COM_REG_PAGE,
6743                                                I40E_PHY_LED_PROV_REG_1,
6744                                                &led_reg, NULL);
6745         } else {
6746                 i = rd32(hw, I40E_PFGEN_PORTNUM);
6747                 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6748                 phy_addr = i40e_get_phy_address(hw, port_num);
6749                 status = i40e_read_phy_register_clause45(hw,
6750                                                          I40E_PHY_COM_REG_PAGE,
6751                                                          led_addr, phy_addr,
6752                                                          (u16 *)&led_reg);
6753         }
6754         if (status)
6755                 return status;
6756         led_ctl = led_reg;
6757         if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6758                 led_reg = 0;
6759                 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
6760                     hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
6761                         status = i40e_aq_set_phy_register(hw,
6762                                         I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6763                                         I40E_PHY_COM_REG_PAGE,
6764                                         I40E_PHY_LED_PROV_REG_1,
6765                                         led_reg, NULL);
6766                 } else {
6767                         status = i40e_write_phy_register_clause45(hw,
6768                                                         I40E_PHY_COM_REG_PAGE,
6769                                                         led_addr, phy_addr,
6770                                                         (u16)led_reg);
6771                 }
6772                 if (status)
6773                         return status;
6774         }
6775         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6776                 status =
6777                       i40e_aq_get_phy_register(hw,
6778                                                I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6779                                                I40E_PHY_COM_REG_PAGE,
6780                                                I40E_PHY_LED_PROV_REG_1,
6781                                                &led_reg, NULL);
6782         } else {
6783                 status = i40e_read_phy_register_clause45(hw,
6784                                                          I40E_PHY_COM_REG_PAGE,
6785                                                          led_addr, phy_addr,
6786                                                          (u16 *)&led_reg);
6787         }
6788         if (status)
6789                 goto restore_config;
6790         if (on)
6791                 led_reg = I40E_PHY_LED_MANUAL_ON;
6792         else
6793                 led_reg = 0;
6794
6795         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6796                 status =
6797                       i40e_aq_set_phy_register(hw,
6798                                                I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6799                                                I40E_PHY_COM_REG_PAGE,
6800                                                I40E_PHY_LED_PROV_REG_1,
6801                                                led_reg, NULL);
6802         } else {
6803                 status =
6804                     i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6805                                                      led_addr, phy_addr,
6806                                                      (u16)led_reg);
6807         }
6808         if (status)
6809                 goto restore_config;
6810         if (mode & I40E_PHY_LED_MODE_ORIG) {
6811                 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6812                 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6813                         status = i40e_aq_set_phy_register(hw,
6814                                         I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6815                                         I40E_PHY_COM_REG_PAGE,
6816                                         I40E_PHY_LED_PROV_REG_1,
6817                                         led_ctl, NULL);
6818                 } else {
6819                         status = i40e_write_phy_register_clause45(hw,
6820                                                          I40E_PHY_COM_REG_PAGE,
6821                                                          led_addr, phy_addr,
6822                                                          (u16)led_ctl);
6823                 }
6824         }
6825         return status;
6826 restore_config:
6827         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6828                 status =
6829                       i40e_aq_set_phy_register(hw,
6830                                                I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6831                                                I40E_PHY_COM_REG_PAGE,
6832                                                I40E_PHY_LED_PROV_REG_1,
6833                                                led_ctl, NULL);
6834         } else {
6835                 status =
6836                         i40e_write_phy_register_clause45(hw,
6837                                                          I40E_PHY_COM_REG_PAGE,
6838                                                          led_addr, phy_addr,
6839                                                          (u16)led_ctl);
6840         }
6841         return status;
6842 }
6843 #endif /* PF_DRIVER */
6844
6845 /**
6846  * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6847  * @hw: pointer to the hw struct
6848  * @reg_addr: register address
6849  * @reg_val: ptr to register value
6850  * @cmd_details: pointer to command details structure or NULL
6851  *
6852  * Use the firmware to read the Rx control register,
6853  * especially useful if the Rx unit is under heavy pressure
6854  **/
6855 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6856                                 u32 reg_addr, u32 *reg_val,
6857                                 struct i40e_asq_cmd_details *cmd_details)
6858 {
6859         struct i40e_aq_desc desc;
6860         struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
6861                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6862         enum i40e_status_code status;
6863
6864         if (reg_val == NULL)
6865                 return I40E_ERR_PARAM;
6866
6867         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
6868
6869         cmd_resp->address = CPU_TO_LE32(reg_addr);
6870
6871         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6872
6873         if (status == I40E_SUCCESS)
6874                 *reg_val = LE32_TO_CPU(cmd_resp->value);
6875
6876         return status;
6877 }
6878
6879 /**
6880  * i40e_read_rx_ctl - read from an Rx control register
6881  * @hw: pointer to the hw struct
6882  * @reg_addr: register address
6883  **/
6884 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
6885 {
6886         enum i40e_status_code status = I40E_SUCCESS;
6887         bool use_register;
6888         int retry = 5;
6889         u32 val = 0;
6890
6891         use_register = (((hw->aq.api_maj_ver == 1) &&
6892                         (hw->aq.api_min_ver < 5)) ||
6893                         (hw->mac.type == I40E_MAC_X722));
6894         if (!use_register) {
6895 do_retry:
6896                 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
6897                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6898                         i40e_msec_delay(1);
6899                         retry--;
6900                         goto do_retry;
6901                 }
6902         }
6903
6904         /* if the AQ access failed, try the old-fashioned way */
6905         if (status || use_register)
6906                 val = rd32(hw, reg_addr);
6907
6908         return val;
6909 }
6910
6911 /**
6912  * i40e_aq_rx_ctl_write_register
6913  * @hw: pointer to the hw struct
6914  * @reg_addr: register address
6915  * @reg_val: register value
6916  * @cmd_details: pointer to command details structure or NULL
6917  *
6918  * Use the firmware to write to an Rx control register,
6919  * especially useful if the Rx unit is under heavy pressure
6920  **/
6921 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
6922                                 u32 reg_addr, u32 reg_val,
6923                                 struct i40e_asq_cmd_details *cmd_details)
6924 {
6925         struct i40e_aq_desc desc;
6926         struct i40e_aqc_rx_ctl_reg_read_write *cmd =
6927                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6928         enum i40e_status_code status;
6929
6930         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
6931
6932         cmd->address = CPU_TO_LE32(reg_addr);
6933         cmd->value = CPU_TO_LE32(reg_val);
6934
6935         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6936
6937         return status;
6938 }
6939
6940 /**
6941  * i40e_write_rx_ctl - write to an Rx control register
6942  * @hw: pointer to the hw struct
6943  * @reg_addr: register address
6944  * @reg_val: register value
6945  **/
6946 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
6947 {
6948         enum i40e_status_code status = I40E_SUCCESS;
6949         bool use_register;
6950         int retry = 5;
6951
6952         use_register = (((hw->aq.api_maj_ver == 1) &&
6953                         (hw->aq.api_min_ver < 5)) ||
6954                         (hw->mac.type == I40E_MAC_X722));
6955         if (!use_register) {
6956 do_retry:
6957                 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
6958                                                        reg_val, NULL);
6959                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6960                         i40e_msec_delay(1);
6961                         retry--;
6962                         goto do_retry;
6963                 }
6964         }
6965
6966         /* if the AQ access failed, try the old-fashioned way */
6967         if (status || use_register)
6968                 wr32(hw, reg_addr, reg_val);
6969 }
6970
6971 /**
6972  * i40e_aq_set_phy_register
6973  * @hw: pointer to the hw struct
6974  * @phy_select: select which phy should be accessed
6975  * @dev_addr: PHY device address
6976  * @reg_addr: PHY register address
6977  * @reg_val: new register value
6978  * @cmd_details: pointer to command details structure or NULL
6979  *
6980  * Write the external PHY register.
6981  **/
6982 enum i40e_status_code i40e_aq_set_phy_register(struct i40e_hw *hw,
6983                                 u8 phy_select, u8 dev_addr,
6984                                 u32 reg_addr, u32 reg_val,
6985                                 struct i40e_asq_cmd_details *cmd_details)
6986 {
6987         struct i40e_aq_desc desc;
6988         struct i40e_aqc_phy_register_access *cmd =
6989                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
6990         enum i40e_status_code status;
6991
6992         i40e_fill_default_direct_cmd_desc(&desc,
6993                                           i40e_aqc_opc_set_phy_register);
6994
6995         cmd->phy_interface = phy_select;
6996         cmd->dev_addres = dev_addr;
6997         cmd->reg_address = reg_addr;
6998         cmd->reg_value = reg_val;
6999
7000         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7001
7002         return status;
7003 }
7004
7005 /**
7006  * i40e_aq_get_phy_register
7007  * @hw: pointer to the hw struct
7008  * @phy_select: select which phy should be accessed
7009  * @dev_addr: PHY device address
7010  * @reg_addr: PHY register address
7011  * @reg_val: read register value
7012  * @cmd_details: pointer to command details structure or NULL
7013  *
7014  * Read the external PHY register.
7015  **/
7016 enum i40e_status_code i40e_aq_get_phy_register(struct i40e_hw *hw,
7017                                 u8 phy_select, u8 dev_addr,
7018                                 u32 reg_addr, u32 *reg_val,
7019                                 struct i40e_asq_cmd_details *cmd_details)
7020 {
7021         struct i40e_aq_desc desc;
7022         struct i40e_aqc_phy_register_access *cmd =
7023                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7024         enum i40e_status_code status;
7025
7026         i40e_fill_default_direct_cmd_desc(&desc,
7027                                           i40e_aqc_opc_get_phy_register);
7028
7029         cmd->phy_interface = phy_select;
7030         cmd->dev_addres = dev_addr;
7031         cmd->reg_address = reg_addr;
7032
7033         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7034         if (!status)
7035                 *reg_val = cmd->reg_value;
7036
7037         return status;
7038 }
7039
7040 #ifdef VF_DRIVER
7041
7042 /**
7043  * i40e_aq_send_msg_to_pf
7044  * @hw: pointer to the hardware structure
7045  * @v_opcode: opcodes for VF-PF communication
7046  * @v_retval: return error code
7047  * @msg: pointer to the msg buffer
7048  * @msglen: msg length
7049  * @cmd_details: pointer to command details
7050  *
7051  * Send message to PF driver using admin queue. By default, this message
7052  * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
7053  * completion before returning.
7054  **/
7055 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
7056                                 enum virtchnl_ops v_opcode,
7057                                 enum i40e_status_code v_retval,
7058                                 u8 *msg, u16 msglen,
7059                                 struct i40e_asq_cmd_details *cmd_details)
7060 {
7061         struct i40e_aq_desc desc;
7062         struct i40e_asq_cmd_details details;
7063         enum i40e_status_code status;
7064
7065         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
7066         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
7067         desc.cookie_high = CPU_TO_LE32(v_opcode);
7068         desc.cookie_low = CPU_TO_LE32(v_retval);
7069         if (msglen) {
7070                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
7071                                                 | I40E_AQ_FLAG_RD));
7072                 if (msglen > I40E_AQ_LARGE_BUF)
7073                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7074                 desc.datalen = CPU_TO_LE16(msglen);
7075         }
7076         if (!cmd_details) {
7077                 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
7078                 details.async = true;
7079                 cmd_details = &details;
7080         }
7081         status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
7082                                        msglen, cmd_details);
7083         return status;
7084 }
7085
7086 /**
7087  * i40e_vf_parse_hw_config
7088  * @hw: pointer to the hardware structure
7089  * @msg: pointer to the virtual channel VF resource structure
7090  *
7091  * Given a VF resource message from the PF, populate the hw struct
7092  * with appropriate information.
7093  **/
7094 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
7095                              struct virtchnl_vf_resource *msg)
7096 {
7097         struct virtchnl_vsi_resource *vsi_res;
7098         int i;
7099
7100         vsi_res = &msg->vsi_res[0];
7101
7102         hw->dev_caps.num_vsis = msg->num_vsis;
7103         hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
7104         hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
7105         hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
7106         hw->dev_caps.dcb = msg->vf_offload_flags &
7107                            VIRTCHNL_VF_OFFLOAD_L2;
7108         hw->dev_caps.iwarp = (msg->vf_offload_flags &
7109                               VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
7110         for (i = 0; i < msg->num_vsis; i++) {
7111                 if (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) {
7112                         i40e_memcpy(hw->mac.perm_addr,
7113                                     vsi_res->default_mac_addr,
7114                                     ETH_ALEN,
7115                                     I40E_NONDMA_TO_NONDMA);
7116                         i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
7117                                     ETH_ALEN,
7118                                     I40E_NONDMA_TO_NONDMA);
7119                 }
7120                 vsi_res++;
7121         }
7122 }
7123
7124 /**
7125  * i40e_vf_reset
7126  * @hw: pointer to the hardware structure
7127  *
7128  * Send a VF_RESET message to the PF. Does not wait for response from PF
7129  * as none will be forthcoming. Immediately after calling this function,
7130  * the admin queue should be shut down and (optionally) reinitialized.
7131  **/
7132 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
7133 {
7134         return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF,
7135                                       I40E_SUCCESS, NULL, 0, NULL);
7136 }
7137 #endif /* VF_DRIVER */
7138
7139 /**
7140  * i40e_aq_set_arp_proxy_config
7141  * @hw: pointer to the HW structure
7142  * @proxy_config - pointer to proxy config command table struct
7143  * @cmd_details: pointer to command details
7144  *
7145  * Set ARP offload parameters from pre-populated
7146  * i40e_aqc_arp_proxy_data struct
7147  **/
7148 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
7149                                 struct i40e_aqc_arp_proxy_data *proxy_config,
7150                                 struct i40e_asq_cmd_details *cmd_details)
7151 {
7152         struct i40e_aq_desc desc;
7153         enum i40e_status_code status;
7154
7155         if (!proxy_config)
7156                 return I40E_ERR_PARAM;
7157
7158         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
7159
7160         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7161         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7162         desc.params.external.addr_high =
7163                                   CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
7164         desc.params.external.addr_low =
7165                                   CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
7166         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_arp_proxy_data));
7167
7168         status = i40e_asq_send_command(hw, &desc, proxy_config,
7169                                        sizeof(struct i40e_aqc_arp_proxy_data),
7170                                        cmd_details);
7171
7172         return status;
7173 }
7174
7175 /**
7176  * i40e_aq_opc_set_ns_proxy_table_entry
7177  * @hw: pointer to the HW structure
7178  * @ns_proxy_table_entry: pointer to NS table entry command struct
7179  * @cmd_details: pointer to command details
7180  *
7181  * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
7182  * from pre-populated i40e_aqc_ns_proxy_data struct
7183  **/
7184 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
7185                         struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
7186                         struct i40e_asq_cmd_details *cmd_details)
7187 {
7188         struct i40e_aq_desc desc;
7189         enum i40e_status_code status;
7190
7191         if (!ns_proxy_table_entry)
7192                 return I40E_ERR_PARAM;
7193
7194         i40e_fill_default_direct_cmd_desc(&desc,
7195                                 i40e_aqc_opc_set_ns_proxy_table_entry);
7196
7197         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7198         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7199         desc.params.external.addr_high =
7200                 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
7201         desc.params.external.addr_low =
7202                 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
7203         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_ns_proxy_data));
7204
7205         status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
7206                                        sizeof(struct i40e_aqc_ns_proxy_data),
7207                                        cmd_details);
7208
7209         return status;
7210 }
7211
7212 /**
7213  * i40e_aq_set_clear_wol_filter
7214  * @hw: pointer to the hw struct
7215  * @filter_index: index of filter to modify (0-7)
7216  * @filter: buffer containing filter to be set
7217  * @set_filter: true to set filter, false to clear filter
7218  * @no_wol_tco: if true, pass through packets cannot cause wake-up
7219  *              if false, pass through packets may cause wake-up
7220  * @filter_valid: true if filter action is valid
7221  * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
7222  * @cmd_details: pointer to command details structure or NULL
7223  *
7224  * Set or clear WoL filter for port attached to the PF
7225  **/
7226 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
7227                                 u8 filter_index,
7228                                 struct i40e_aqc_set_wol_filter_data *filter,
7229                                 bool set_filter, bool no_wol_tco,
7230                                 bool filter_valid, bool no_wol_tco_valid,
7231                                 struct i40e_asq_cmd_details *cmd_details)
7232 {
7233         struct i40e_aq_desc desc;
7234         struct i40e_aqc_set_wol_filter *cmd =
7235                 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
7236         enum i40e_status_code status;
7237         u16 cmd_flags = 0;
7238         u16 valid_flags = 0;
7239         u16 buff_len = 0;
7240
7241         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
7242
7243         if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
7244                 return  I40E_ERR_PARAM;
7245         cmd->filter_index = CPU_TO_LE16(filter_index);
7246
7247         if (set_filter) {
7248                 if (!filter)
7249                         return  I40E_ERR_PARAM;
7250
7251                 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
7252                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR;
7253         }
7254
7255         if (no_wol_tco)
7256                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
7257         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
7258
7259         if (filter_valid)
7260                 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
7261         if (no_wol_tco_valid)
7262                 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
7263         cmd->valid_flags = CPU_TO_LE16(valid_flags);
7264
7265         buff_len = sizeof(*filter);
7266         desc.datalen = CPU_TO_LE16(buff_len);
7267
7268         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7269         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7270
7271         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
7272         cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
7273
7274         status = i40e_asq_send_command(hw, &desc, filter,
7275                                        buff_len, cmd_details);
7276
7277         return status;
7278 }
7279
7280 /**
7281  * i40e_aq_get_wake_event_reason
7282  * @hw: pointer to the hw struct
7283  * @wake_reason: return value, index of matching filter
7284  * @cmd_details: pointer to command details structure or NULL
7285  *
7286  * Get information for the reason of a Wake Up event
7287  **/
7288 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
7289                                 u16 *wake_reason,
7290                                 struct i40e_asq_cmd_details *cmd_details)
7291 {
7292         struct i40e_aq_desc desc;
7293         struct i40e_aqc_get_wake_reason_completion *resp =
7294                 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
7295         enum i40e_status_code status;
7296
7297         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
7298
7299         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7300
7301         if (status == I40E_SUCCESS)
7302                 *wake_reason = LE16_TO_CPU(resp->wake_reason);
7303
7304         return status;
7305 }
7306
7307 /**
7308 * i40e_aq_clear_all_wol_filters
7309 * @hw: pointer to the hw struct
7310 * @cmd_details: pointer to command details structure or NULL
7311 *
7312 * Get information for the reason of a Wake Up event
7313 **/
7314 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw,
7315         struct i40e_asq_cmd_details *cmd_details)
7316 {
7317         struct i40e_aq_desc desc;
7318         enum i40e_status_code status;
7319
7320         i40e_fill_default_direct_cmd_desc(&desc,
7321                                           i40e_aqc_opc_clear_all_wol_filters);
7322
7323         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7324
7325         return status;
7326 }
7327
7328
7329 /**
7330  * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
7331  * @hw: pointer to the hw struct
7332  * @buff: command buffer (size in bytes = buff_size)
7333  * @buff_size: buffer size in bytes
7334  * @track_id: package tracking id
7335  * @error_offset: returns error offset
7336  * @error_info: returns error information
7337  * @cmd_details: pointer to command details structure or NULL
7338  **/
7339 enum
7340 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
7341                                    u16 buff_size, u32 track_id,
7342                                    u32 *error_offset, u32 *error_info,
7343                                    struct i40e_asq_cmd_details *cmd_details)
7344 {
7345         struct i40e_aq_desc desc;
7346         struct i40e_aqc_write_personalization_profile *cmd =
7347                 (struct i40e_aqc_write_personalization_profile *)
7348                 &desc.params.raw;
7349         struct i40e_aqc_write_ddp_resp *resp;
7350         enum i40e_status_code status;
7351
7352         i40e_fill_default_direct_cmd_desc(&desc,
7353                                   i40e_aqc_opc_write_personalization_profile);
7354
7355         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
7356         if (buff_size > I40E_AQ_LARGE_BUF)
7357                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7358
7359         desc.datalen = CPU_TO_LE16(buff_size);
7360
7361         cmd->profile_track_id = CPU_TO_LE32(track_id);
7362
7363         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7364         if (!status) {
7365                 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
7366                 if (error_offset)
7367                         *error_offset = LE32_TO_CPU(resp->error_offset);
7368                 if (error_info)
7369                         *error_info = LE32_TO_CPU(resp->error_info);
7370         }
7371
7372         return status;
7373 }
7374
7375 /**
7376  * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
7377  * @hw: pointer to the hw struct
7378  * @buff: command buffer (size in bytes = buff_size)
7379  * @buff_size: buffer size in bytes
7380  * @cmd_details: pointer to command details structure or NULL
7381  **/
7382 enum
7383 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
7384                                       u16 buff_size, u8 flags,
7385                                       struct i40e_asq_cmd_details *cmd_details)
7386 {
7387         struct i40e_aq_desc desc;
7388         struct i40e_aqc_get_applied_profiles *cmd =
7389                 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
7390         enum i40e_status_code status;
7391
7392         i40e_fill_default_direct_cmd_desc(&desc,
7393                           i40e_aqc_opc_get_personalization_profile_list);
7394
7395         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7396         if (buff_size > I40E_AQ_LARGE_BUF)
7397                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7398         desc.datalen = CPU_TO_LE16(buff_size);
7399
7400         cmd->flags = flags;
7401
7402         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7403
7404         return status;
7405 }
7406
7407 /**
7408  * i40e_find_segment_in_package
7409  * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
7410  * @pkg_hdr: pointer to the package header to be searched
7411  *
7412  * This function searches a package file for a particular segment type. On
7413  * success it returns a pointer to the segment header, otherwise it will
7414  * return NULL.
7415  **/
7416 struct i40e_generic_seg_header *
7417 i40e_find_segment_in_package(u32 segment_type,
7418                              struct i40e_package_header *pkg_hdr)
7419 {
7420         struct i40e_generic_seg_header *segment;
7421         u32 i;
7422
7423         /* Search all package segments for the requested segment type */
7424         for (i = 0; i < pkg_hdr->segment_count; i++) {
7425                 segment =
7426                         (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
7427                          pkg_hdr->segment_offset[i]);
7428
7429                 if (segment->type == segment_type)
7430                         return segment;
7431         }
7432
7433         return NULL;
7434 }
7435
7436 /**
7437  * i40e_write_profile
7438  * @hw: pointer to the hardware structure
7439  * @profile: pointer to the profile segment of the package to be downloaded
7440  * @track_id: package tracking id
7441  *
7442  * Handles the download of a complete package.
7443  */
7444 enum i40e_status_code
7445 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7446                    u32 track_id)
7447 {
7448         enum i40e_status_code status = I40E_SUCCESS;
7449         struct i40e_section_table *sec_tbl;
7450         struct i40e_profile_section_header *sec = NULL;
7451         u32 dev_cnt;
7452         u32 vendor_dev_id;
7453         u32 *nvm;
7454         u32 section_size = 0;
7455         u32 offset = 0, info = 0;
7456         u32 i;
7457
7458         dev_cnt = profile->device_table_count;
7459
7460         for (i = 0; i < dev_cnt; i++) {
7461                 vendor_dev_id = profile->device_table[i].vendor_dev_id;
7462                 if ((vendor_dev_id >> 16) == I40E_INTEL_VENDOR_ID)
7463                         if (hw->device_id == (vendor_dev_id & 0xFFFF))
7464                                 break;
7465         }
7466         if (i == dev_cnt) {
7467                 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Device doesn't support DDP");
7468                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
7469         }
7470
7471         nvm = (u32 *)&profile->device_table[dev_cnt];
7472         sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1];
7473
7474         for (i = 0; i < sec_tbl->section_count; i++) {
7475                 sec = (struct i40e_profile_section_header *)((u8 *)profile +
7476                                              sec_tbl->section_offset[i]);
7477
7478                 /* Skip 'AQ', 'note' and 'name' sections */
7479                 if (sec->section.type != SECTION_TYPE_MMIO)
7480                         continue;
7481
7482                 section_size = sec->section.size +
7483                         sizeof(struct i40e_profile_section_header);
7484
7485                 /* Write profile */
7486                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
7487                                            track_id, &offset, &info, NULL);
7488                 if (status) {
7489                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
7490                                    "Failed to write profile: offset %d, info %d",
7491                                    offset, info);
7492                         break;
7493                 }
7494         }
7495         return status;
7496 }
7497
7498 /**
7499  * i40e_add_pinfo_to_list
7500  * @hw: pointer to the hardware structure
7501  * @profile: pointer to the profile segment of the package
7502  * @profile_info_sec: buffer for information section
7503  * @track_id: package tracking id
7504  *
7505  * Register a profile to the list of loaded profiles.
7506  */
7507 enum i40e_status_code
7508 i40e_add_pinfo_to_list(struct i40e_hw *hw,
7509                        struct i40e_profile_segment *profile,
7510                        u8 *profile_info_sec, u32 track_id)
7511 {
7512         enum i40e_status_code status = I40E_SUCCESS;
7513         struct i40e_profile_section_header *sec = NULL;
7514         struct i40e_profile_info *pinfo;
7515         u32 offset = 0, info = 0;
7516
7517         sec = (struct i40e_profile_section_header *)profile_info_sec;
7518         sec->tbl_size = 1;
7519         sec->data_end = sizeof(struct i40e_profile_section_header) +
7520                         sizeof(struct i40e_profile_info);
7521         sec->section.type = SECTION_TYPE_INFO;
7522         sec->section.offset = sizeof(struct i40e_profile_section_header);
7523         sec->section.size = sizeof(struct i40e_profile_info);
7524         pinfo = (struct i40e_profile_info *)(profile_info_sec +
7525                                              sec->section.offset);
7526         pinfo->track_id = track_id;
7527         pinfo->version = profile->version;
7528         pinfo->op = I40E_DDP_ADD_TRACKID;
7529         memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE);
7530
7531         status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
7532                                    track_id, &offset, &info, NULL);
7533         return status;
7534 }