drivers/net/i40e/base/i40e_common.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "i40e_type.h"
  35 #include "i40e_adminq.h"
  36 #include "i40e_prototype.h"
  37 #include "i40e_virtchnl.h"
  38
  39
  40 /**
  41  * i40e_set_mac_type - Sets MAC type
  42  * @hw: pointer to the HW structure
  43  *
  44  * This function sets the mac type of the adapter based on the
  45  * vendor ID and device ID stored in the hw structure.
  46  **/
  47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  49 #else
  50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  51 #endif
  52 {
  53         enum i40e_status_code status = I40E_SUCCESS;
  54
  55         DEBUGFUNC("i40e_set_mac_type\n");
  56
  57         if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
  58                 switch (hw->device_id) {
  59                 case I40E_DEV_ID_SFP_XL710:
  60                 case I40E_DEV_ID_QEMU:
  61                 case I40E_DEV_ID_KX_B:
  62                 case I40E_DEV_ID_KX_C:
  63                 case I40E_DEV_ID_QSFP_A:
  64                 case I40E_DEV_ID_QSFP_B:
  65                 case I40E_DEV_ID_QSFP_C:
  66                 case I40E_DEV_ID_10G_BASE_T:
  67                 case I40E_DEV_ID_10G_BASE_T4:
  68                 case I40E_DEV_ID_20G_KR2:
  69                 case I40E_DEV_ID_20G_KR2_A:
  70                 case I40E_DEV_ID_25G_B:
  71                 case I40E_DEV_ID_25G_SFP28:
  72                         hw->mac.type = I40E_MAC_XL710;
  73                         break;
  74 #ifdef X722_SUPPORT
  75 #ifdef X722_A0_SUPPORT
  76                 case I40E_DEV_ID_X722_A0:
  77 #endif
  78                 case I40E_DEV_ID_KX_X722:
  79                 case I40E_DEV_ID_QSFP_X722:
  80                 case I40E_DEV_ID_SFP_X722:
  81                 case I40E_DEV_ID_1G_BASE_T_X722:
  82                 case I40E_DEV_ID_10G_BASE_T_X722:
  83                 case I40E_DEV_ID_SFP_I_X722:
  84                         hw->mac.type = I40E_MAC_X722;
  85                         break;
  86 #endif
  87 #ifdef X722_SUPPORT
  88 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  89                 case I40E_DEV_ID_X722_VF:
  90                 case I40E_DEV_ID_X722_VF_HV:
  91 #ifdef X722_A0_SUPPORT
  92                 case I40E_DEV_ID_X722_A0_VF:
  93 #endif
  94                         hw->mac.type = I40E_MAC_X722_VF;
  95                         break;
  96 #endif /* INTEGRATED_VF || VF_DRIVER */
  97 #endif /* X722_SUPPORT */
  98 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  99                 case I40E_DEV_ID_VF:
 100                 case I40E_DEV_ID_VF_HV:
 101                         hw->mac.type = I40E_MAC_VF;
 102                         break;
 103 #endif
 104                 default:
 105                         hw->mac.type = I40E_MAC_GENERIC;
 106                         break;
 107                 }
 108         } else {
 109                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
 110         }
 111
 112         DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
 113                   hw->mac.type, status);
 114         return status;
 115 }
 116
 117 #ifndef I40E_NDIS_SUPPORT
 118 /**
 119  * i40e_aq_str - convert AQ err code to a string
 120  * @hw: pointer to the HW structure
 121  * @aq_err: the AQ error code to convert
 122  **/
 123 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
 124 {
 125         switch (aq_err) {
 126         case I40E_AQ_RC_OK:
 127                 return "OK";
 128         case I40E_AQ_RC_EPERM:
 129                 return "I40E_AQ_RC_EPERM";
 130         case I40E_AQ_RC_ENOENT:
 131                 return "I40E_AQ_RC_ENOENT";
 132         case I40E_AQ_RC_ESRCH:
 133                 return "I40E_AQ_RC_ESRCH";
 134         case I40E_AQ_RC_EINTR:
 135                 return "I40E_AQ_RC_EINTR";
 136         case I40E_AQ_RC_EIO:
 137                 return "I40E_AQ_RC_EIO";
 138         case I40E_AQ_RC_ENXIO:
 139                 return "I40E_AQ_RC_ENXIO";
 140         case I40E_AQ_RC_E2BIG:
 141                 return "I40E_AQ_RC_E2BIG";
 142         case I40E_AQ_RC_EAGAIN:
 143                 return "I40E_AQ_RC_EAGAIN";
 144         case I40E_AQ_RC_ENOMEM:
 145                 return "I40E_AQ_RC_ENOMEM";
 146         case I40E_AQ_RC_EACCES:
 147                 return "I40E_AQ_RC_EACCES";
 148         case I40E_AQ_RC_EFAULT:
 149                 return "I40E_AQ_RC_EFAULT";
 150         case I40E_AQ_RC_EBUSY:
 151                 return "I40E_AQ_RC_EBUSY";
 152         case I40E_AQ_RC_EEXIST:
 153                 return "I40E_AQ_RC_EEXIST";
 154         case I40E_AQ_RC_EINVAL:
 155                 return "I40E_AQ_RC_EINVAL";
 156         case I40E_AQ_RC_ENOTTY:
 157                 return "I40E_AQ_RC_ENOTTY";
 158         case I40E_AQ_RC_ENOSPC:
 159                 return "I40E_AQ_RC_ENOSPC";
 160         case I40E_AQ_RC_ENOSYS:
 161                 return "I40E_AQ_RC_ENOSYS";
 162         case I40E_AQ_RC_ERANGE:
 163                 return "I40E_AQ_RC_ERANGE";
 164         case I40E_AQ_RC_EFLUSHED:
 165                 return "I40E_AQ_RC_EFLUSHED";
 166         case I40E_AQ_RC_BAD_ADDR:
 167                 return "I40E_AQ_RC_BAD_ADDR";
 168         case I40E_AQ_RC_EMODE:
 169                 return "I40E_AQ_RC_EMODE";
 170         case I40E_AQ_RC_EFBIG:
 171                 return "I40E_AQ_RC_EFBIG";
 172         }
 173
 174         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 175         return hw->err_str;
 176 }
 177
 178 /**
 179  * i40e_stat_str - convert status err code to a string
 180  * @hw: pointer to the HW structure
 181  * @stat_err: the status error code to convert
 182  **/
 183 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
 184 {
 185         switch (stat_err) {
 186         case I40E_SUCCESS:
 187                 return "OK";
 188         case I40E_ERR_NVM:
 189                 return "I40E_ERR_NVM";
 190         case I40E_ERR_NVM_CHECKSUM:
 191                 return "I40E_ERR_NVM_CHECKSUM";
 192         case I40E_ERR_PHY:
 193                 return "I40E_ERR_PHY";
 194         case I40E_ERR_CONFIG:
 195                 return "I40E_ERR_CONFIG";
 196         case I40E_ERR_PARAM:
 197                 return "I40E_ERR_PARAM";
 198         case I40E_ERR_MAC_TYPE:
 199                 return "I40E_ERR_MAC_TYPE";
 200         case I40E_ERR_UNKNOWN_PHY:
 201                 return "I40E_ERR_UNKNOWN_PHY";
 202         case I40E_ERR_LINK_SETUP:
 203                 return "I40E_ERR_LINK_SETUP";
 204         case I40E_ERR_ADAPTER_STOPPED:
 205                 return "I40E_ERR_ADAPTER_STOPPED";
 206         case I40E_ERR_INVALID_MAC_ADDR:
 207                 return "I40E_ERR_INVALID_MAC_ADDR";
 208         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 209                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 210         case I40E_ERR_MASTER_REQUESTS_PENDING:
 211                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 212         case I40E_ERR_INVALID_LINK_SETTINGS:
 213                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 214         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 215                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 216         case I40E_ERR_RESET_FAILED:
 217                 return "I40E_ERR_RESET_FAILED";
 218         case I40E_ERR_SWFW_SYNC:
 219                 return "I40E_ERR_SWFW_SYNC";
 220         case I40E_ERR_NO_AVAILABLE_VSI:
 221                 return "I40E_ERR_NO_AVAILABLE_VSI";
 222         case I40E_ERR_NO_MEMORY:
 223                 return "I40E_ERR_NO_MEMORY";
 224         case I40E_ERR_BAD_PTR:
 225                 return "I40E_ERR_BAD_PTR";
 226         case I40E_ERR_RING_FULL:
 227                 return "I40E_ERR_RING_FULL";
 228         case I40E_ERR_INVALID_PD_ID:
 229                 return "I40E_ERR_INVALID_PD_ID";
 230         case I40E_ERR_INVALID_QP_ID:
 231                 return "I40E_ERR_INVALID_QP_ID";
 232         case I40E_ERR_INVALID_CQ_ID:
 233                 return "I40E_ERR_INVALID_CQ_ID";
 234         case I40E_ERR_INVALID_CEQ_ID:
 235                 return "I40E_ERR_INVALID_CEQ_ID";
 236         case I40E_ERR_INVALID_AEQ_ID:
 237                 return "I40E_ERR_INVALID_AEQ_ID";
 238         case I40E_ERR_INVALID_SIZE:
 239                 return "I40E_ERR_INVALID_SIZE";
 240         case I40E_ERR_INVALID_ARP_INDEX:
 241                 return "I40E_ERR_INVALID_ARP_INDEX";
 242         case I40E_ERR_INVALID_FPM_FUNC_ID:
 243                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 244         case I40E_ERR_QP_INVALID_MSG_SIZE:
 245                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 246         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 247                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 248         case I40E_ERR_INVALID_FRAG_COUNT:
 249                 return "I40E_ERR_INVALID_FRAG_COUNT";
 250         case I40E_ERR_QUEUE_EMPTY:
 251                 return "I40E_ERR_QUEUE_EMPTY";
 252         case I40E_ERR_INVALID_ALIGNMENT:
 253                 return "I40E_ERR_INVALID_ALIGNMENT";
 254         case I40E_ERR_FLUSHED_QUEUE:
 255                 return "I40E_ERR_FLUSHED_QUEUE";
 256         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 257                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 258         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 259                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 260         case I40E_ERR_TIMEOUT:
 261                 return "I40E_ERR_TIMEOUT";
 262         case I40E_ERR_OPCODE_MISMATCH:
 263                 return "I40E_ERR_OPCODE_MISMATCH";
 264         case I40E_ERR_CQP_COMPL_ERROR:
 265                 return "I40E_ERR_CQP_COMPL_ERROR";
 266         case I40E_ERR_INVALID_VF_ID:
 267                 return "I40E_ERR_INVALID_VF_ID";
 268         case I40E_ERR_INVALID_HMCFN_ID:
 269                 return "I40E_ERR_INVALID_HMCFN_ID";
 270         case I40E_ERR_BACKING_PAGE_ERROR:
 271                 return "I40E_ERR_BACKING_PAGE_ERROR";
 272         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 273                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 274         case I40E_ERR_INVALID_PBLE_INDEX:
 275                 return "I40E_ERR_INVALID_PBLE_INDEX";
 276         case I40E_ERR_INVALID_SD_INDEX:
 277                 return "I40E_ERR_INVALID_SD_INDEX";
 278         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 279                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 280         case I40E_ERR_INVALID_SD_TYPE:
 281                 return "I40E_ERR_INVALID_SD_TYPE";
 282         case I40E_ERR_MEMCPY_FAILED:
 283                 return "I40E_ERR_MEMCPY_FAILED";
 284         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 285                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 286         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 287                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 288         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 289                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 290         case I40E_ERR_SRQ_ENABLED:
 291                 return "I40E_ERR_SRQ_ENABLED";
 292         case I40E_ERR_ADMIN_QUEUE_ERROR:
 293                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 294         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 295                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 296         case I40E_ERR_BUF_TOO_SHORT:
 297                 return "I40E_ERR_BUF_TOO_SHORT";
 298         case I40E_ERR_ADMIN_QUEUE_FULL:
 299                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 300         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 301                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 302         case I40E_ERR_BAD_IWARP_CQE:
 303                 return "I40E_ERR_BAD_IWARP_CQE";
 304         case I40E_ERR_NVM_BLANK_MODE:
 305                 return "I40E_ERR_NVM_BLANK_MODE";
 306         case I40E_ERR_NOT_IMPLEMENTED:
 307                 return "I40E_ERR_NOT_IMPLEMENTED";
 308         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 309                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 310         case I40E_ERR_DIAG_TEST_FAILED:
 311                 return "I40E_ERR_DIAG_TEST_FAILED";
 312         case I40E_ERR_NOT_READY:
 313                 return "I40E_ERR_NOT_READY";
 314         case I40E_NOT_SUPPORTED:
 315                 return "I40E_NOT_SUPPORTED";
 316         case I40E_ERR_FIRMWARE_API_VERSION:
 317                 return "I40E_ERR_FIRMWARE_API_VERSION";
 318         }
 319
 320         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 321         return hw->err_str;
 322 }
 323
 324 #endif /* I40E_NDIS_SUPPORT */
 325 /**
 326  * i40e_debug_aq
 327  * @hw: debug mask related to admin queue
 328  * @mask: debug mask
 329  * @desc: pointer to admin queue descriptor
 330  * @buffer: pointer to command buffer
 331  * @buf_len: max length of buffer
 332  *
 333  * Dumps debug log about adminq command with descriptor contents.
 334  **/
 335 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 336                    void *buffer, u16 buf_len)
 337 {
 338         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 339         u16 len = LE16_TO_CPU(aq_desc->datalen);
 340         u8 *buf = (u8 *)buffer;
 341         u16 i = 0;
 342
 343         if ((!(mask & hw->debug_mask)) || (desc == NULL))
 344                 return;
 345
 346         i40e_debug(hw, mask,
 347                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 348                    LE16_TO_CPU(aq_desc->opcode),
 349                    LE16_TO_CPU(aq_desc->flags),
 350                    LE16_TO_CPU(aq_desc->datalen),
 351                    LE16_TO_CPU(aq_desc->retval));
 352         i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
 353                    LE32_TO_CPU(aq_desc->cookie_high),
 354                    LE32_TO_CPU(aq_desc->cookie_low));
 355         i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
 356                    LE32_TO_CPU(aq_desc->params.internal.param0),
 357                    LE32_TO_CPU(aq_desc->params.internal.param1));
 358         i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
 359                    LE32_TO_CPU(aq_desc->params.external.addr_high),
 360                    LE32_TO_CPU(aq_desc->params.external.addr_low));
 361
 362         if ((buffer != NULL) && (aq_desc->datalen != 0)) {
 363                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 364                 if (buf_len < len)
 365                         len = buf_len;
 366                 /* write the full 16-byte chunks */
 367                 for (i = 0; i < (len - 16); i += 16)
 368                         i40e_debug(hw, mask,
 369                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 370                                    i, buf[i], buf[i+1], buf[i+2], buf[i+3],
 371                                    buf[i+4], buf[i+5], buf[i+6], buf[i+7],
 372                                    buf[i+8], buf[i+9], buf[i+10], buf[i+11],
 373                                    buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
 374                 /* the most we could have left is 16 bytes, pad with zeros */
 375                 if (i < len) {
 376                         char d_buf[16];
 377                         int j, i_sav;
 378
 379                         i_sav = i;
 380                         memset(d_buf, 0, sizeof(d_buf));
 381                         for (j = 0; i < len; j++, i++)
 382                                 d_buf[j] = buf[i];
 383                         i40e_debug(hw, mask,
 384                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 385                                    i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
 386                                    d_buf[4], d_buf[5], d_buf[6], d_buf[7],
 387                                    d_buf[8], d_buf[9], d_buf[10], d_buf[11],
 388                                    d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
 389                 }
 390         }
 391 }
 392
 393 /**
 394  * i40e_check_asq_alive
 395  * @hw: pointer to the hw struct
 396  *
 397  * Returns true if Queue is enabled else false.
 398  **/
 399 bool i40e_check_asq_alive(struct i40e_hw *hw)
 400 {
 401         if (hw->aq.asq.len)
 402 #ifdef PF_DRIVER
 403 #ifdef INTEGRATED_VF
 404                 if (!i40e_is_vf(hw))
 405                         return !!(rd32(hw, hw->aq.asq.len) &
 406                                 I40E_PF_ATQLEN_ATQENABLE_MASK);
 407 #else
 408                 return !!(rd32(hw, hw->aq.asq.len) &
 409                         I40E_PF_ATQLEN_ATQENABLE_MASK);
 410 #endif /* INTEGRATED_VF */
 411 #endif /* PF_DRIVER */
 412 #ifdef VF_DRIVER
 413 #ifdef INTEGRATED_VF
 414                 if (i40e_is_vf(hw))
 415                         return !!(rd32(hw, hw->aq.asq.len) &
 416                                 I40E_VF_ATQLEN1_ATQENABLE_MASK);
 417 #else
 418                 return !!(rd32(hw, hw->aq.asq.len) &
 419                         I40E_VF_ATQLEN1_ATQENABLE_MASK);
 420 #endif /* INTEGRATED_VF */
 421 #endif /* VF_DRIVER */
 422         return false;
 423 }
 424
 425 /**
 426  * i40e_aq_queue_shutdown
 427  * @hw: pointer to the hw struct
 428  * @unloading: is the driver unloading itself
 429  *
 430  * Tell the Firmware that we're shutting down the AdminQ and whether
 431  * or not the driver is unloading as well.
 432  **/
 433 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
 434                                              bool unloading)
 435 {
 436         struct i40e_aq_desc desc;
 437         struct i40e_aqc_queue_shutdown *cmd =
 438                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 439         enum i40e_status_code status;
 440
 441         i40e_fill_default_direct_cmd_desc(&desc,
 442                                           i40e_aqc_opc_queue_shutdown);
 443
 444         if (unloading)
 445                 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
 446         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 447
 448         return status;
 449 }
 450 #ifdef X722_SUPPORT
 451
 452 /**
 453  * i40e_aq_get_set_rss_lut
 454  * @hw: pointer to the hardware structure
 455  * @vsi_id: vsi fw index
 456  * @pf_lut: for PF table set true, for VSI table set false
 457  * @lut: pointer to the lut buffer provided by the caller
 458  * @lut_size: size of the lut buffer
 459  * @set: set true to set the table, false to get the table
 460  *
 461  * Internal function to get or set RSS look up table
 462  **/
 463 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 464                                                      u16 vsi_id, bool pf_lut,
 465                                                      u8 *lut, u16 lut_size,
 466                                                      bool set)
 467 {
 468         enum i40e_status_code status;
 469         struct i40e_aq_desc desc;
 470         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 471                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 472
 473         if (set)
 474                 i40e_fill_default_direct_cmd_desc(&desc,
 475                                                   i40e_aqc_opc_set_rss_lut);
 476         else
 477                 i40e_fill_default_direct_cmd_desc(&desc,
 478                                                   i40e_aqc_opc_get_rss_lut);
 479
 480         /* Indirect command */
 481         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 482         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 483
 484         cmd_resp->vsi_id =
 485                         CPU_TO_LE16((u16)((vsi_id <<
 486                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 487                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 488         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 489
 490         if (pf_lut)
 491                 cmd_resp->flags |= CPU_TO_LE16((u16)
 492                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 493                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 494                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 495         else
 496                 cmd_resp->flags |= CPU_TO_LE16((u16)
 497                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 498                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 499                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 500
 501         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 502
 503         return status;
 504 }
 505
 506 /**
 507  * i40e_aq_get_rss_lut
 508  * @hw: pointer to the hardware structure
 509  * @vsi_id: vsi fw index
 510  * @pf_lut: for PF table set true, for VSI table set false
 511  * @lut: pointer to the lut buffer provided by the caller
 512  * @lut_size: size of the lut buffer
 513  *
 514  * get the RSS lookup table, PF or VSI type
 515  **/
 516 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 517                                           bool pf_lut, u8 *lut, u16 lut_size)
 518 {
 519         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 520                                        false);
 521 }
 522
 523 /**
 524  * i40e_aq_set_rss_lut
 525  * @hw: pointer to the hardware structure
 526  * @vsi_id: vsi fw index
 527  * @pf_lut: for PF table set true, for VSI table set false
 528  * @lut: pointer to the lut buffer provided by the caller
 529  * @lut_size: size of the lut buffer
 530  *
 531  * set the RSS lookup table, PF or VSI type
 532  **/
 533 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 534                                           bool pf_lut, u8 *lut, u16 lut_size)
 535 {
 536         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
 537 }
 538
 539 /**
 540  * i40e_aq_get_set_rss_key
 541  * @hw: pointer to the hw struct
 542  * @vsi_id: vsi fw index
 543  * @key: pointer to key info struct
 544  * @set: set true to set the key, false to get the key
 545  *
 546  * get the RSS key per VSI
 547  **/
 548 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 549                                       u16 vsi_id,
 550                                       struct i40e_aqc_get_set_rss_key_data *key,
 551                                       bool set)
 552 {
 553         enum i40e_status_code status;
 554         struct i40e_aq_desc desc;
 555         struct i40e_aqc_get_set_rss_key *cmd_resp =
 556                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 557         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 558
 559         if (set)
 560                 i40e_fill_default_direct_cmd_desc(&desc,
 561                                                   i40e_aqc_opc_set_rss_key);
 562         else
 563                 i40e_fill_default_direct_cmd_desc(&desc,
 564                                                   i40e_aqc_opc_get_rss_key);
 565
 566         /* Indirect command */
 567         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 568         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 569
 570         cmd_resp->vsi_id =
 571                         CPU_TO_LE16((u16)((vsi_id <<
 572                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 573                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 574         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 575
 576         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 577
 578         return status;
 579 }
 580
 581 /**
 582  * i40e_aq_get_rss_key
 583  * @hw: pointer to the hw struct
 584  * @vsi_id: vsi fw index
 585  * @key: pointer to key info struct
 586  *
 587  **/
 588 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
 589                                       u16 vsi_id,
 590                                       struct i40e_aqc_get_set_rss_key_data *key)
 591 {
 592         return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
 593 }
 594
 595 /**
 596  * i40e_aq_set_rss_key
 597  * @hw: pointer to the hw struct
 598  * @vsi_id: vsi fw index
 599  * @key: pointer to key info struct
 600  *
 601  * set the RSS key per VSI
 602  **/
 603 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
 604                                       u16 vsi_id,
 605                                       struct i40e_aqc_get_set_rss_key_data *key)
 606 {
 607         return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
 608 }
 609 #endif /* X722_SUPPORT */
 610
 611 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 612  * hardware to a bit-field that can be used by SW to more easily determine the
 613  * packet type.
 614  *
 615  * Macros are used to shorten the table lines and make this table human
 616  * readable.
 617  *
 618  * We store the PTYPE in the top byte of the bit field - this is just so that
 619  * we can check that the table doesn't have a row missing, as the index into
 620  * the table should be the PTYPE.
 621  *
 622  * Typical work flow:
 623  *
 624  * IF NOT i40e_ptype_lookup[ptype].known
 625  * THEN
 626  *      Packet is unknown
 627  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 628  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 629  * ELSE
 630  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 631  * ENDIF
 632  */
 633
 634 /* macro to make the table lines short */
 635 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 636         {       PTYPE, \
 637                 1, \
 638                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 639                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 640                 I40E_RX_PTYPE_##OUTER_FRAG, \
 641                 I40E_RX_PTYPE_TUNNEL_##T, \
 642                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 643                 I40E_RX_PTYPE_##TEF, \
 644                 I40E_RX_PTYPE_INNER_PROT_##I, \
 645                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 646
 647 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 648                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 649
 650 /* shorter macros makes the table fit but are terse */
 651 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 652 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 653 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 654
 655 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 656 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 657         /* L2 Packet types */
 658         I40E_PTT_UNUSED_ENTRY(0),
 659         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 660         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 661         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 662         I40E_PTT_UNUSED_ENTRY(4),
 663         I40E_PTT_UNUSED_ENTRY(5),
 664         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 665         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 666         I40E_PTT_UNUSED_ENTRY(8),
 667         I40E_PTT_UNUSED_ENTRY(9),
 668         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 669         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 670         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 671         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 672         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 673         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 674         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 675         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 676         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 677         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 678         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 679         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 680
 681         /* Non Tunneled IPv4 */
 682         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 683         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 684         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 685         I40E_PTT_UNUSED_ENTRY(25),
 686         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 687         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 688         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 689
 690         /* IPv4 --> IPv4 */
 691         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 692         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 693         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 694         I40E_PTT_UNUSED_ENTRY(32),
 695         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 696         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 697         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 698
 699         /* IPv4 --> IPv6 */
 700         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 701         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 702         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 703         I40E_PTT_UNUSED_ENTRY(39),
 704         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 705         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 706         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 707
 708         /* IPv4 --> GRE/NAT */
 709         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 710
 711         /* IPv4 --> GRE/NAT --> IPv4 */
 712         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 713         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 714         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 715         I40E_PTT_UNUSED_ENTRY(47),
 716         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 717         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 718         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 719
 720         /* IPv4 --> GRE/NAT --> IPv6 */
 721         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 722         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 723         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 724         I40E_PTT_UNUSED_ENTRY(54),
 725         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 726         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 727         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 728
 729         /* IPv4 --> GRE/NAT --> MAC */
 730         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 731
 732         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 733         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 734         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 735         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 736         I40E_PTT_UNUSED_ENTRY(62),
 737         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 738         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 739         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 740
 741         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 742         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 743         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 744         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 745         I40E_PTT_UNUSED_ENTRY(69),
 746         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 747         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 748         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 749
 750         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 751         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 752
 753         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 754         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 755         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 756         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 757         I40E_PTT_UNUSED_ENTRY(77),
 758         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 759         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 760         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 761
 762         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 763         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 764         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 765         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 766         I40E_PTT_UNUSED_ENTRY(84),
 767         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 768         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 769         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 770
 771         /* Non Tunneled IPv6 */
 772         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 773         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 774         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
 775         I40E_PTT_UNUSED_ENTRY(91),
 776         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 777         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 778         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 779
 780         /* IPv6 --> IPv4 */
 781         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 782         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 783         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 784         I40E_PTT_UNUSED_ENTRY(98),
 785         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 786         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 787         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 788
 789         /* IPv6 --> IPv6 */
 790         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 791         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 792         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 793         I40E_PTT_UNUSED_ENTRY(105),
 794         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 795         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 796         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 797
 798         /* IPv6 --> GRE/NAT */
 799         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 800
 801         /* IPv6 --> GRE/NAT -> IPv4 */
 802         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 803         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 804         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 805         I40E_PTT_UNUSED_ENTRY(113),
 806         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 807         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 808         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 809
 810         /* IPv6 --> GRE/NAT -> IPv6 */
 811         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 812         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 813         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 814         I40E_PTT_UNUSED_ENTRY(120),
 815         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 816         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 817         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 818
 819         /* IPv6 --> GRE/NAT -> MAC */
 820         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 821
 822         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 823         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 824         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 825         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 826         I40E_PTT_UNUSED_ENTRY(128),
 827         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 828         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 829         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 830
 831         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 832         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 833         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 834         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 835         I40E_PTT_UNUSED_ENTRY(135),
 836         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 837         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 838         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 839
 840         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 841         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 842
 843         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 844         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 845         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 846         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 847         I40E_PTT_UNUSED_ENTRY(143),
 848         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 849         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 850         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 851
 852         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 853         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 854         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 855         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 856         I40E_PTT_UNUSED_ENTRY(150),
 857         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 858         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 859         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 860
 861         /* unused entries */
 862         I40E_PTT_UNUSED_ENTRY(154),
 863         I40E_PTT_UNUSED_ENTRY(155),
 864         I40E_PTT_UNUSED_ENTRY(156),
 865         I40E_PTT_UNUSED_ENTRY(157),
 866         I40E_PTT_UNUSED_ENTRY(158),
 867         I40E_PTT_UNUSED_ENTRY(159),
 868
 869         I40E_PTT_UNUSED_ENTRY(160),
 870         I40E_PTT_UNUSED_ENTRY(161),
 871         I40E_PTT_UNUSED_ENTRY(162),
 872         I40E_PTT_UNUSED_ENTRY(163),
 873         I40E_PTT_UNUSED_ENTRY(164),
 874         I40E_PTT_UNUSED_ENTRY(165),
 875         I40E_PTT_UNUSED_ENTRY(166),
 876         I40E_PTT_UNUSED_ENTRY(167),
 877         I40E_PTT_UNUSED_ENTRY(168),
 878         I40E_PTT_UNUSED_ENTRY(169),
 879
 880         I40E_PTT_UNUSED_ENTRY(170),
 881         I40E_PTT_UNUSED_ENTRY(171),
 882         I40E_PTT_UNUSED_ENTRY(172),
 883         I40E_PTT_UNUSED_ENTRY(173),
 884         I40E_PTT_UNUSED_ENTRY(174),
 885         I40E_PTT_UNUSED_ENTRY(175),
 886         I40E_PTT_UNUSED_ENTRY(176),
 887         I40E_PTT_UNUSED_ENTRY(177),
 888         I40E_PTT_UNUSED_ENTRY(178),
 889         I40E_PTT_UNUSED_ENTRY(179),
 890
 891         I40E_PTT_UNUSED_ENTRY(180),
 892         I40E_PTT_UNUSED_ENTRY(181),
 893         I40E_PTT_UNUSED_ENTRY(182),
 894         I40E_PTT_UNUSED_ENTRY(183),
 895         I40E_PTT_UNUSED_ENTRY(184),
 896         I40E_PTT_UNUSED_ENTRY(185),
 897         I40E_PTT_UNUSED_ENTRY(186),
 898         I40E_PTT_UNUSED_ENTRY(187),
 899         I40E_PTT_UNUSED_ENTRY(188),
 900         I40E_PTT_UNUSED_ENTRY(189),
 901
 902         I40E_PTT_UNUSED_ENTRY(190),
 903         I40E_PTT_UNUSED_ENTRY(191),
 904         I40E_PTT_UNUSED_ENTRY(192),
 905         I40E_PTT_UNUSED_ENTRY(193),
 906         I40E_PTT_UNUSED_ENTRY(194),
 907         I40E_PTT_UNUSED_ENTRY(195),
 908         I40E_PTT_UNUSED_ENTRY(196),
 909         I40E_PTT_UNUSED_ENTRY(197),
 910         I40E_PTT_UNUSED_ENTRY(198),
 911         I40E_PTT_UNUSED_ENTRY(199),
 912
 913         I40E_PTT_UNUSED_ENTRY(200),
 914         I40E_PTT_UNUSED_ENTRY(201),
 915         I40E_PTT_UNUSED_ENTRY(202),
 916         I40E_PTT_UNUSED_ENTRY(203),
 917         I40E_PTT_UNUSED_ENTRY(204),
 918         I40E_PTT_UNUSED_ENTRY(205),
 919         I40E_PTT_UNUSED_ENTRY(206),
 920         I40E_PTT_UNUSED_ENTRY(207),
 921         I40E_PTT_UNUSED_ENTRY(208),
 922         I40E_PTT_UNUSED_ENTRY(209),
 923
 924         I40E_PTT_UNUSED_ENTRY(210),
 925         I40E_PTT_UNUSED_ENTRY(211),
 926         I40E_PTT_UNUSED_ENTRY(212),
 927         I40E_PTT_UNUSED_ENTRY(213),
 928         I40E_PTT_UNUSED_ENTRY(214),
 929         I40E_PTT_UNUSED_ENTRY(215),
 930         I40E_PTT_UNUSED_ENTRY(216),
 931         I40E_PTT_UNUSED_ENTRY(217),
 932         I40E_PTT_UNUSED_ENTRY(218),
 933         I40E_PTT_UNUSED_ENTRY(219),
 934
 935         I40E_PTT_UNUSED_ENTRY(220),
 936         I40E_PTT_UNUSED_ENTRY(221),
 937         I40E_PTT_UNUSED_ENTRY(222),
 938         I40E_PTT_UNUSED_ENTRY(223),
 939         I40E_PTT_UNUSED_ENTRY(224),
 940         I40E_PTT_UNUSED_ENTRY(225),
 941         I40E_PTT_UNUSED_ENTRY(226),
 942         I40E_PTT_UNUSED_ENTRY(227),
 943         I40E_PTT_UNUSED_ENTRY(228),
 944         I40E_PTT_UNUSED_ENTRY(229),
 945
 946         I40E_PTT_UNUSED_ENTRY(230),
 947         I40E_PTT_UNUSED_ENTRY(231),
 948         I40E_PTT_UNUSED_ENTRY(232),
 949         I40E_PTT_UNUSED_ENTRY(233),
 950         I40E_PTT_UNUSED_ENTRY(234),
 951         I40E_PTT_UNUSED_ENTRY(235),
 952         I40E_PTT_UNUSED_ENTRY(236),
 953         I40E_PTT_UNUSED_ENTRY(237),
 954         I40E_PTT_UNUSED_ENTRY(238),
 955         I40E_PTT_UNUSED_ENTRY(239),
 956
 957         I40E_PTT_UNUSED_ENTRY(240),
 958         I40E_PTT_UNUSED_ENTRY(241),
 959         I40E_PTT_UNUSED_ENTRY(242),
 960         I40E_PTT_UNUSED_ENTRY(243),
 961         I40E_PTT_UNUSED_ENTRY(244),
 962         I40E_PTT_UNUSED_ENTRY(245),
 963         I40E_PTT_UNUSED_ENTRY(246),
 964         I40E_PTT_UNUSED_ENTRY(247),
 965         I40E_PTT_UNUSED_ENTRY(248),
 966         I40E_PTT_UNUSED_ENTRY(249),
 967
 968         I40E_PTT_UNUSED_ENTRY(250),
 969         I40E_PTT_UNUSED_ENTRY(251),
 970         I40E_PTT_UNUSED_ENTRY(252),
 971         I40E_PTT_UNUSED_ENTRY(253),
 972         I40E_PTT_UNUSED_ENTRY(254),
 973         I40E_PTT_UNUSED_ENTRY(255)
 974 };
 975
 976
 977 /**
 978  * i40e_validate_mac_addr - Validate unicast MAC address
 979  * @mac_addr: pointer to MAC address
 980  *
 981  * Tests a MAC address to ensure it is a valid Individual Address
 982  **/
 983 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
 984 {
 985         enum i40e_status_code status = I40E_SUCCESS;
 986
 987         DEBUGFUNC("i40e_validate_mac_addr");
 988
 989         /* Broadcast addresses ARE multicast addresses
 990          * Make sure it is not a multicast address
 991          * Reject the zero address
 992          */
 993         if (I40E_IS_MULTICAST(mac_addr) ||
 994             (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
 995               mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
 996                 status = I40E_ERR_INVALID_MAC_ADDR;
 997
 998         return status;
 999 }
1000 #ifdef PF_DRIVER
1001
1002 /**
1003  * i40e_init_shared_code - Initialize the shared code
1004  * @hw: pointer to hardware structure
1005  *
1006  * This assigns the MAC type and PHY code and inits the NVM.
1007  * Does not touch the hardware. This function must be called prior to any
1008  * other function in the shared code. The i40e_hw structure should be
1009  * memset to 0 prior to calling this function.  The following fields in
1010  * hw structure should be filled in prior to calling this function:
1011  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1012  * subsystem_vendor_id, and revision_id
1013  **/
1014 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
1015 {
1016         enum i40e_status_code status = I40E_SUCCESS;
1017         u32 port, ari, func_rid;
1018
1019         DEBUGFUNC("i40e_init_shared_code");
1020
1021         i40e_set_mac_type(hw);
1022
1023         switch (hw->mac.type) {
1024         case I40E_MAC_XL710:
1025 #ifdef X722_SUPPORT
1026         case I40E_MAC_X722:
1027 #endif
1028                 break;
1029         default:
1030                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1031         }
1032
1033         hw->phy.get_link_info = true;
1034
1035         /* Determine port number and PF number*/
1036         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1037                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1038         hw->port = (u8)port;
1039         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1040                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1041         func_rid = rd32(hw, I40E_PF_FUNC_RID);
1042         if (ari)
1043                 hw->pf_id = (u8)(func_rid & 0xff);
1044         else
1045                 hw->pf_id = (u8)(func_rid & 0x7);
1046
1047 #ifdef X722_SUPPORT
1048         if (hw->mac.type == I40E_MAC_X722)
1049                 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
1050
1051 #endif
1052         status = i40e_init_nvm(hw);
1053         return status;
1054 }
1055
1056 /**
1057  * i40e_aq_mac_address_read - Retrieve the MAC addresses
1058  * @hw: pointer to the hw struct
1059  * @flags: a return indicator of what addresses were added to the addr store
1060  * @addrs: the requestor's mac addr store
1061  * @cmd_details: pointer to command details structure or NULL
1062  **/
1063 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1064                                    u16 *flags,
1065                                    struct i40e_aqc_mac_address_read_data *addrs,
1066                                    struct i40e_asq_cmd_details *cmd_details)
1067 {
1068         struct i40e_aq_desc desc;
1069         struct i40e_aqc_mac_address_read *cmd_data =
1070                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1071         enum i40e_status_code status;
1072
1073         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1074         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1075
1076         status = i40e_asq_send_command(hw, &desc, addrs,
1077                                        sizeof(*addrs), cmd_details);
1078         *flags = LE16_TO_CPU(cmd_data->command_flags);
1079
1080         return status;
1081 }
1082
1083 /**
1084  * i40e_aq_mac_address_write - Change the MAC addresses
1085  * @hw: pointer to the hw struct
1086  * @flags: indicates which MAC to be written
1087  * @mac_addr: address to write
1088  * @cmd_details: pointer to command details structure or NULL
1089  **/
1090 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1091                                     u16 flags, u8 *mac_addr,
1092                                     struct i40e_asq_cmd_details *cmd_details)
1093 {
1094         struct i40e_aq_desc desc;
1095         struct i40e_aqc_mac_address_write *cmd_data =
1096                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1097         enum i40e_status_code status;
1098
1099         i40e_fill_default_direct_cmd_desc(&desc,
1100                                           i40e_aqc_opc_mac_address_write);
1101         cmd_data->command_flags = CPU_TO_LE16(flags);
1102         cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1103         cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1104                                         ((u32)mac_addr[3] << 16) |
1105                                         ((u32)mac_addr[4] << 8) |
1106                                         mac_addr[5]);
1107
1108         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1109
1110         return status;
1111 }
1112
1113 /**
1114  * i40e_get_mac_addr - get MAC address
1115  * @hw: pointer to the HW structure
1116  * @mac_addr: pointer to MAC address
1117  *
1118  * Reads the adapter's MAC address from register
1119  **/
1120 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1121 {
1122         struct i40e_aqc_mac_address_read_data addrs;
1123         enum i40e_status_code status;
1124         u16 flags = 0;
1125
1126         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1127
1128         if (flags & I40E_AQC_LAN_ADDR_VALID)
1129                 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
1130
1131         return status;
1132 }
1133
1134 /**
1135  * i40e_get_port_mac_addr - get Port MAC address
1136  * @hw: pointer to the HW structure
1137  * @mac_addr: pointer to Port MAC address
1138  *
1139  * Reads the adapter's Port MAC address
1140  **/
1141 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1142 {
1143         struct i40e_aqc_mac_address_read_data addrs;
1144         enum i40e_status_code status;
1145         u16 flags = 0;
1146
1147         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1148         if (status)
1149                 return status;
1150
1151         if (flags & I40E_AQC_PORT_ADDR_VALID)
1152                 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
1153         else
1154                 status = I40E_ERR_INVALID_MAC_ADDR;
1155
1156         return status;
1157 }
1158
1159 /**
1160  * i40e_pre_tx_queue_cfg - pre tx queue configure
1161  * @hw: pointer to the HW structure
1162  * @queue: target pf queue index
1163  * @enable: state change request
1164  *
1165  * Handles hw requirement to indicate intention to enable
1166  * or disable target queue.
1167  **/
1168 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1169 {
1170         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1171         u32 reg_block = 0;
1172         u32 reg_val;
1173
1174         if (abs_queue_idx >= 128) {
1175                 reg_block = abs_queue_idx / 128;
1176                 abs_queue_idx %= 128;
1177         }
1178
1179         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1180         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1181         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1182
1183         if (enable)
1184                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1185         else
1186                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1187
1188         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1189 }
1190
1191 /**
1192  * i40e_get_san_mac_addr - get SAN MAC address
1193  * @hw: pointer to the HW structure
1194  * @mac_addr: pointer to SAN MAC address
1195  *
1196  * Reads the adapter's SAN MAC address from NVM
1197  **/
1198 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1199                                             u8 *mac_addr)
1200 {
1201         struct i40e_aqc_mac_address_read_data addrs;
1202         enum i40e_status_code status;
1203         u16 flags = 0;
1204
1205         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1206         if (status)
1207                 return status;
1208
1209         if (flags & I40E_AQC_SAN_ADDR_VALID)
1210                 memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac));
1211         else
1212                 status = I40E_ERR_INVALID_MAC_ADDR;
1213
1214         return status;
1215 }
1216
1217 /**
1218  *  i40e_read_pba_string - Reads part number string from EEPROM
1219  *  @hw: pointer to hardware structure
1220  *  @pba_num: stores the part number string from the EEPROM
1221  *  @pba_num_size: part number string buffer length
1222  *
1223  *  Reads the part number string from the EEPROM.
1224  **/
1225 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1226                                             u32 pba_num_size)
1227 {
1228         enum i40e_status_code status = I40E_SUCCESS;
1229         u16 pba_word = 0;
1230         u16 pba_size = 0;
1231         u16 pba_ptr = 0;
1232         u16 i = 0;
1233
1234         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1235         if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1236                 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1237                 return status;
1238         }
1239
1240         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1241         if (status != I40E_SUCCESS) {
1242                 DEBUGOUT("Failed to read PBA Block pointer.\n");
1243                 return status;
1244         }
1245
1246         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1247         if (status != I40E_SUCCESS) {
1248                 DEBUGOUT("Failed to read PBA Block size.\n");
1249                 return status;
1250         }
1251
1252         /* Subtract one to get PBA word count (PBA Size word is included in
1253          * total size)
1254          */
1255         pba_size--;
1256         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1257                 DEBUGOUT("Buffer to small for PBA data.\n");
1258                 return I40E_ERR_PARAM;
1259         }
1260
1261         for (i = 0; i < pba_size; i++) {
1262                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1263                 if (status != I40E_SUCCESS) {
1264                         DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1265                         return status;
1266                 }
1267
1268                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1269                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1270         }
1271         pba_num[(pba_size * 2)] = '\0';
1272
1273         return status;
1274 }
1275
1276 /**
1277  * i40e_get_media_type - Gets media type
1278  * @hw: pointer to the hardware structure
1279  **/
1280 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1281 {
1282         enum i40e_media_type media;
1283
1284         switch (hw->phy.link_info.phy_type) {
1285         case I40E_PHY_TYPE_10GBASE_SR:
1286         case I40E_PHY_TYPE_10GBASE_LR:
1287         case I40E_PHY_TYPE_1000BASE_SX:
1288         case I40E_PHY_TYPE_1000BASE_LX:
1289         case I40E_PHY_TYPE_40GBASE_SR4:
1290         case I40E_PHY_TYPE_40GBASE_LR4:
1291         case I40E_PHY_TYPE_25GBASE_LR:
1292         case I40E_PHY_TYPE_25GBASE_SR:
1293                 media = I40E_MEDIA_TYPE_FIBER;
1294                 break;
1295         case I40E_PHY_TYPE_100BASE_TX:
1296         case I40E_PHY_TYPE_1000BASE_T:
1297         case I40E_PHY_TYPE_10GBASE_T:
1298                 media = I40E_MEDIA_TYPE_BASET;
1299                 break;
1300         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1301         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1302         case I40E_PHY_TYPE_10GBASE_CR1:
1303         case I40E_PHY_TYPE_40GBASE_CR4:
1304         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1305         case I40E_PHY_TYPE_40GBASE_AOC:
1306         case I40E_PHY_TYPE_10GBASE_AOC:
1307         case I40E_PHY_TYPE_25GBASE_CR:
1308                 media = I40E_MEDIA_TYPE_DA;
1309                 break;
1310         case I40E_PHY_TYPE_1000BASE_KX:
1311         case I40E_PHY_TYPE_10GBASE_KX4:
1312         case I40E_PHY_TYPE_10GBASE_KR:
1313         case I40E_PHY_TYPE_40GBASE_KR4:
1314         case I40E_PHY_TYPE_20GBASE_KR2:
1315         case I40E_PHY_TYPE_25GBASE_KR:
1316                 media = I40E_MEDIA_TYPE_BACKPLANE;
1317                 break;
1318         case I40E_PHY_TYPE_SGMII:
1319         case I40E_PHY_TYPE_XAUI:
1320         case I40E_PHY_TYPE_XFI:
1321         case I40E_PHY_TYPE_XLAUI:
1322         case I40E_PHY_TYPE_XLPPI:
1323         default:
1324                 media = I40E_MEDIA_TYPE_UNKNOWN;
1325                 break;
1326         }
1327
1328         return media;
1329 }
1330
1331 #define I40E_PF_RESET_WAIT_COUNT        200
1332 /**
1333  * i40e_pf_reset - Reset the PF
1334  * @hw: pointer to the hardware structure
1335  *
1336  * Assuming someone else has triggered a global reset,
1337  * assure the global reset is complete and then reset the PF
1338  **/
1339 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1340 {
1341         u32 cnt = 0;
1342         u32 cnt1 = 0;
1343         u32 reg = 0;
1344         u32 grst_del;
1345
1346         /* Poll for Global Reset steady state in case of recent GRST.
1347          * The grst delay value is in 100ms units, and we'll wait a
1348          * couple counts longer to be sure we don't just miss the end.
1349          */
1350         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1351                         I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1352                         I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1353
1354         grst_del = grst_del * 20;
1355
1356         for (cnt = 0; cnt < grst_del; cnt++) {
1357                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1358                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1359                         break;
1360                 i40e_msec_delay(100);
1361         }
1362         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1363                 DEBUGOUT("Global reset polling failed to complete.\n");
1364                 return I40E_ERR_RESET_FAILED;
1365         }
1366
1367         /* Now Wait for the FW to be ready */
1368         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1369                 reg = rd32(hw, I40E_GLNVM_ULD);
1370                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1371                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1372                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1373                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1374                         DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1375                         break;
1376                 }
1377                 i40e_msec_delay(10);
1378         }
1379         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1380                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1381                 DEBUGOUT("wait for FW Reset complete timedout\n");
1382                 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1383                 return I40E_ERR_RESET_FAILED;
1384         }
1385
1386         /* If there was a Global Reset in progress when we got here,
1387          * we don't need to do the PF Reset
1388          */
1389         if (!cnt) {
1390                 reg = rd32(hw, I40E_PFGEN_CTRL);
1391                 wr32(hw, I40E_PFGEN_CTRL,
1392                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1393                 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1394                         reg = rd32(hw, I40E_PFGEN_CTRL);
1395                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1396                                 break;
1397                         i40e_msec_delay(1);
1398                 }
1399                 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1400                         DEBUGOUT("PF reset polling failed to complete.\n");
1401                         return I40E_ERR_RESET_FAILED;
1402                 }
1403         }
1404
1405         i40e_clear_pxe_mode(hw);
1406
1407
1408         return I40E_SUCCESS;
1409 }
1410
1411 /**
1412  * i40e_clear_hw - clear out any left over hw state
1413  * @hw: pointer to the hw struct
1414  *
1415  * Clear queues and interrupts, typically called at init time,
1416  * but after the capabilities have been found so we know how many
1417  * queues and msix vectors have been allocated.
1418  **/
1419 void i40e_clear_hw(struct i40e_hw *hw)
1420 {
1421         u32 num_queues, base_queue;
1422         u32 num_pf_int;
1423         u32 num_vf_int;
1424         u32 num_vfs;
1425         u32 i, j;
1426         u32 val;
1427         u32 eol = 0x7ff;
1428
1429         /* get number of interrupts, queues, and vfs */
1430         val = rd32(hw, I40E_GLPCI_CNF2);
1431         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1432                         I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1433         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1434                         I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1435
1436         val = rd32(hw, I40E_PFLAN_QALLOC);
1437         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1438                         I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1439         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1440                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1441         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1442                 num_queues = (j - base_queue) + 1;
1443         else
1444                 num_queues = 0;
1445
1446         val = rd32(hw, I40E_PF_VT_PFALLOC);
1447         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1448                         I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1449         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1450                         I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1451         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1452                 num_vfs = (j - i) + 1;
1453         else
1454                 num_vfs = 0;
1455
1456         /* stop all the interrupts */
1457         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1458         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1459         for (i = 0; i < num_pf_int - 2; i++)
1460                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1461
1462         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1463         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1464         wr32(hw, I40E_PFINT_LNKLST0, val);
1465         for (i = 0; i < num_pf_int - 2; i++)
1466                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1467         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1468         for (i = 0; i < num_vfs; i++)
1469                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1470         for (i = 0; i < num_vf_int - 2; i++)
1471                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1472
1473         /* warn the HW of the coming Tx disables */
1474         for (i = 0; i < num_queues; i++) {
1475                 u32 abs_queue_idx = base_queue + i;
1476                 u32 reg_block = 0;
1477
1478                 if (abs_queue_idx >= 128) {
1479                         reg_block = abs_queue_idx / 128;
1480                         abs_queue_idx %= 128;
1481                 }
1482
1483                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1484                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1485                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1486                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1487
1488                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1489         }
1490         i40e_usec_delay(400);
1491
1492         /* stop all the queues */
1493         for (i = 0; i < num_queues; i++) {
1494                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1495                 wr32(hw, I40E_QTX_ENA(i), 0);
1496                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1497                 wr32(hw, I40E_QRX_ENA(i), 0);
1498         }
1499
1500         /* short wait for all queue disables to settle */
1501         i40e_usec_delay(50);
1502 }
1503
1504 /**
1505  * i40e_clear_pxe_mode - clear pxe operations mode
1506  * @hw: pointer to the hw struct
1507  *
1508  * Make sure all PXE mode settings are cleared, including things
1509  * like descriptor fetch/write-back mode.
1510  **/
1511 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1512 {
1513         if (i40e_check_asq_alive(hw))
1514                 i40e_aq_clear_pxe_mode(hw, NULL);
1515 }
1516
1517 /**
1518  * i40e_led_is_mine - helper to find matching led
1519  * @hw: pointer to the hw struct
1520  * @idx: index into GPIO registers
1521  *
1522  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1523  */
1524 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1525 {
1526         u32 gpio_val = 0;
1527         u32 port;
1528
1529         if (!hw->func_caps.led[idx])
1530                 return 0;
1531
1532         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1533         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1534                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1535
1536         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1537          * if it is not our port then ignore
1538          */
1539         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1540             (port != hw->port))
1541                 return 0;
1542
1543         return gpio_val;
1544 }
1545
1546 #define I40E_COMBINED_ACTIVITY 0xA
1547 #define I40E_FILTER_ACTIVITY 0xE
1548 #define I40E_LINK_ACTIVITY 0xC
1549 #define I40E_MAC_ACTIVITY 0xD
1550 #define I40E_LED0 22
1551
1552 /**
1553  * i40e_led_get - return current on/off mode
1554  * @hw: pointer to the hw struct
1555  *
1556  * The value returned is the 'mode' field as defined in the
1557  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1558  * values are variations of possible behaviors relating to
1559  * blink, link, and wire.
1560  **/
1561 u32 i40e_led_get(struct i40e_hw *hw)
1562 {
1563         u32 current_mode = 0;
1564         u32 mode = 0;
1565         int i;
1566
1567         /* as per the documentation GPIO 22-29 are the LED
1568          * GPIO pins named LED0..LED7
1569          */
1570         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1571                 u32 gpio_val = i40e_led_is_mine(hw, i);
1572
1573                 if (!gpio_val)
1574                         continue;
1575
1576                 /* ignore gpio LED src mode entries related to the activity
1577                  *  LEDs
1578                  */
1579                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1580                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1581                 switch (current_mode) {
1582                 case I40E_COMBINED_ACTIVITY:
1583                 case I40E_FILTER_ACTIVITY:
1584                 case I40E_MAC_ACTIVITY:
1585                         continue;
1586                 default:
1587                         break;
1588                 }
1589
1590                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1591                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1592                 break;
1593         }
1594
1595         return mode;
1596 }
1597
1598 /**
1599  * i40e_led_set - set new on/off mode
1600  * @hw: pointer to the hw struct
1601  * @mode: 0=off, 0xf=on (else see manual for mode details)
1602  * @blink: true if the LED should blink when on, false if steady
1603  *
1604  * if this function is used to turn on the blink it should
1605  * be used to disable the blink when restoring the original state.
1606  **/
1607 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1608 {
1609         u32 current_mode = 0;
1610         int i;
1611
1612         if (mode & 0xfffffff0)
1613                 DEBUGOUT1("invalid mode passed in %X\n", mode);
1614
1615         /* as per the documentation GPIO 22-29 are the LED
1616          * GPIO pins named LED0..LED7
1617          */
1618         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1619                 u32 gpio_val = i40e_led_is_mine(hw, i);
1620
1621                 if (!gpio_val)
1622                         continue;
1623
1624                 /* ignore gpio LED src mode entries related to the activity
1625                  * LEDs
1626                  */
1627                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1628                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1629                 switch (current_mode) {
1630                 case I40E_COMBINED_ACTIVITY:
1631                 case I40E_FILTER_ACTIVITY:
1632                 case I40E_MAC_ACTIVITY:
1633                         continue;
1634                 default:
1635                         break;
1636                 }
1637
1638                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1639                 /* this & is a bit of paranoia, but serves as a range check */
1640                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1641                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1642
1643                 if (mode == I40E_LINK_ACTIVITY)
1644                         blink = false;
1645
1646                 if (blink)
1647                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1648                 else
1649                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1650
1651                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1652                 break;
1653         }
1654 }
1655
1656 /* Admin command wrappers */
1657
1658 /**
1659  * i40e_aq_get_phy_capabilities
1660  * @hw: pointer to the hw struct
1661  * @abilities: structure for PHY capabilities to be filled
1662  * @qualified_modules: report Qualified Modules
1663  * @report_init: report init capabilities (active are default)
1664  * @cmd_details: pointer to command details structure or NULL
1665  *
1666  * Returns the various PHY abilities supported on the Port.
1667  **/
1668 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1669                         bool qualified_modules, bool report_init,
1670                         struct i40e_aq_get_phy_abilities_resp *abilities,
1671                         struct i40e_asq_cmd_details *cmd_details)
1672 {
1673         struct i40e_aq_desc desc;
1674         enum i40e_status_code status;
1675         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1676
1677         if (!abilities)
1678                 return I40E_ERR_PARAM;
1679
1680         i40e_fill_default_direct_cmd_desc(&desc,
1681                                           i40e_aqc_opc_get_phy_abilities);
1682
1683         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1684         if (abilities_size > I40E_AQ_LARGE_BUF)
1685                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1686
1687         if (qualified_modules)
1688                 desc.params.external.param0 |=
1689                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1690
1691         if (report_init)
1692                 desc.params.external.param0 |=
1693                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1694
1695         status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1696                                     cmd_details);
1697
1698         if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1699                 status = I40E_ERR_UNKNOWN_PHY;
1700
1701         if (report_init) {
1702                 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1703                 hw->phy.phy_types |= ((u64)abilities->phy_type_ext << 32);
1704         }
1705
1706         return status;
1707 }
1708
1709 /**
1710  * i40e_aq_set_phy_config
1711  * @hw: pointer to the hw struct
1712  * @config: structure with PHY configuration to be set
1713  * @cmd_details: pointer to command details structure or NULL
1714  *
1715  * Set the various PHY configuration parameters
1716  * supported on the Port.One or more of the Set PHY config parameters may be
1717  * ignored in an MFP mode as the PF may not have the privilege to set some
1718  * of the PHY Config parameters. This status will be indicated by the
1719  * command response.
1720  **/
1721 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1722                                 struct i40e_aq_set_phy_config *config,
1723                                 struct i40e_asq_cmd_details *cmd_details)
1724 {
1725         struct i40e_aq_desc desc;
1726         struct i40e_aq_set_phy_config *cmd =
1727                 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1728         enum i40e_status_code status;
1729
1730         if (!config)
1731                 return I40E_ERR_PARAM;
1732
1733         i40e_fill_default_direct_cmd_desc(&desc,
1734                                           i40e_aqc_opc_set_phy_config);
1735
1736         *cmd = *config;
1737
1738         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1739
1740         return status;
1741 }
1742
1743 /**
1744  * i40e_set_fc
1745  * @hw: pointer to the hw struct
1746  *
1747  * Set the requested flow control mode using set_phy_config.
1748  **/
1749 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1750                                   bool atomic_restart)
1751 {
1752         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1753         struct i40e_aq_get_phy_abilities_resp abilities;
1754         struct i40e_aq_set_phy_config config;
1755         enum i40e_status_code status;
1756         u8 pause_mask = 0x0;
1757
1758         *aq_failures = 0x0;
1759
1760         switch (fc_mode) {
1761         case I40E_FC_FULL:
1762                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1763                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1764                 break;
1765         case I40E_FC_RX_PAUSE:
1766                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1767                 break;
1768         case I40E_FC_TX_PAUSE:
1769                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1770                 break;
1771         default:
1772                 break;
1773         }
1774
1775         /* Get the current phy config */
1776         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1777                                               NULL);
1778         if (status) {
1779                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1780                 return status;
1781         }
1782
1783         memset(&config, 0, sizeof(config));
1784         /* clear the old pause settings */
1785         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1786                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1787         /* set the new abilities */
1788         config.abilities |= pause_mask;
1789         /* If the abilities have changed, then set the new config */
1790         if (config.abilities != abilities.abilities) {
1791                 /* Auto restart link so settings take effect */
1792                 if (atomic_restart)
1793                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1794                 /* Copy over all the old settings */
1795                 config.phy_type = abilities.phy_type;
1796                 config.phy_type_ext = abilities.phy_type_ext;
1797                 config.link_speed = abilities.link_speed;
1798                 config.eee_capability = abilities.eee_capability;
1799                 config.eeer = abilities.eeer_val;
1800                 config.low_power_ctrl = abilities.d3_lpan;
1801                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1802
1803                 if (status)
1804                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1805         }
1806         /* Update the link info */
1807         status = i40e_update_link_info(hw);
1808         if (status) {
1809                 /* Wait a little bit (on 40G cards it sometimes takes a really
1810                  * long time for link to come back from the atomic reset)
1811                  * and try once more
1812                  */
1813                 i40e_msec_delay(1000);
1814                 status = i40e_update_link_info(hw);
1815         }
1816         if (status)
1817                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1818
1819         return status;
1820 }
1821
1822 /**
1823  * i40e_aq_set_mac_config
1824  * @hw: pointer to the hw struct
1825  * @max_frame_size: Maximum Frame Size to be supported by the port
1826  * @crc_en: Tell HW to append a CRC to outgoing frames
1827  * @pacing: Pacing configurations
1828  * @cmd_details: pointer to command details structure or NULL
1829  *
1830  * Configure MAC settings for frame size, jumbo frame support and the
1831  * addition of a CRC by the hardware.
1832  **/
1833 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1834                                 u16 max_frame_size,
1835                                 bool crc_en, u16 pacing,
1836                                 struct i40e_asq_cmd_details *cmd_details)
1837 {
1838         struct i40e_aq_desc desc;
1839         struct i40e_aq_set_mac_config *cmd =
1840                 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1841         enum i40e_status_code status;
1842
1843         if (max_frame_size == 0)
1844                 return I40E_ERR_PARAM;
1845
1846         i40e_fill_default_direct_cmd_desc(&desc,
1847                                           i40e_aqc_opc_set_mac_config);
1848
1849         cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1850         cmd->params = ((u8)pacing & 0x0F) << 3;
1851         if (crc_en)
1852                 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1853
1854         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1855
1856         return status;
1857 }
1858
1859 /**
1860  * i40e_aq_clear_pxe_mode
1861  * @hw: pointer to the hw struct
1862  * @cmd_details: pointer to command details structure or NULL
1863  *
1864  * Tell the firmware that the driver is taking over from PXE
1865  **/
1866 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1867                         struct i40e_asq_cmd_details *cmd_details)
1868 {
1869         enum i40e_status_code status;
1870         struct i40e_aq_desc desc;
1871         struct i40e_aqc_clear_pxe *cmd =
1872                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1873
1874         i40e_fill_default_direct_cmd_desc(&desc,
1875                                           i40e_aqc_opc_clear_pxe_mode);
1876
1877         cmd->rx_cnt = 0x2;
1878
1879         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1880
1881         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1882
1883         return status;
1884 }
1885
1886 /**
1887  * i40e_aq_set_link_restart_an
1888  * @hw: pointer to the hw struct
1889  * @enable_link: if true: enable link, if false: disable link
1890  * @cmd_details: pointer to command details structure or NULL
1891  *
1892  * Sets up the link and restarts the Auto-Negotiation over the link.
1893  **/
1894 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1895                 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1896 {
1897         struct i40e_aq_desc desc;
1898         struct i40e_aqc_set_link_restart_an *cmd =
1899                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1900         enum i40e_status_code status;
1901
1902         i40e_fill_default_direct_cmd_desc(&desc,
1903                                           i40e_aqc_opc_set_link_restart_an);
1904
1905         cmd->command = I40E_AQ_PHY_RESTART_AN;
1906         if (enable_link)
1907                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1908         else
1909                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1910
1911         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1912
1913         return status;
1914 }
1915
1916 /**
1917  * i40e_aq_get_link_info
1918  * @hw: pointer to the hw struct
1919  * @enable_lse: enable/disable LinkStatusEvent reporting
1920  * @link: pointer to link status structure - optional
1921  * @cmd_details: pointer to command details structure or NULL
1922  *
1923  * Returns the link status of the adapter.
1924  **/
1925 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1926                                 bool enable_lse, struct i40e_link_status *link,
1927                                 struct i40e_asq_cmd_details *cmd_details)
1928 {
1929         struct i40e_aq_desc desc;
1930         struct i40e_aqc_get_link_status *resp =
1931                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1932         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1933         enum i40e_status_code status;
1934         bool tx_pause, rx_pause;
1935         u16 command_flags;
1936
1937         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1938
1939         if (enable_lse)
1940                 command_flags = I40E_AQ_LSE_ENABLE;
1941         else
1942                 command_flags = I40E_AQ_LSE_DISABLE;
1943         resp->command_flags = CPU_TO_LE16(command_flags);
1944
1945         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1946
1947         if (status != I40E_SUCCESS)
1948                 goto aq_get_link_info_exit;
1949
1950         /* save off old link status information */
1951         i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1952                     sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1953
1954         /* update link status */
1955         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1956         hw->phy.media_type = i40e_get_media_type(hw);
1957         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1958         hw_link_info->link_info = resp->link_info;
1959         hw_link_info->an_info = resp->an_info;
1960         hw_link_info->ext_info = resp->ext_info;
1961         hw_link_info->loopback = resp->loopback;
1962         hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1963         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1964
1965         /* update fc info */
1966         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1967         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1968         if (tx_pause & rx_pause)
1969                 hw->fc.current_mode = I40E_FC_FULL;
1970         else if (tx_pause)
1971                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1972         else if (rx_pause)
1973                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1974         else
1975                 hw->fc.current_mode = I40E_FC_NONE;
1976
1977         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1978                 hw_link_info->crc_enable = true;
1979         else
1980                 hw_link_info->crc_enable = false;
1981
1982         if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
1983                 hw_link_info->lse_enable = true;
1984         else
1985                 hw_link_info->lse_enable = false;
1986
1987         if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1988              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1989                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1990
1991         /* save link status information */
1992         if (link)
1993                 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1994                             I40E_NONDMA_TO_NONDMA);
1995
1996         /* flag cleared so helper functions don't call AQ again */
1997         hw->phy.get_link_info = false;
1998
1999 aq_get_link_info_exit:
2000         return status;
2001 }
2002
2003 /**
2004  * i40e_aq_set_phy_int_mask
2005  * @hw: pointer to the hw struct
2006  * @mask: interrupt mask to be set
2007  * @cmd_details: pointer to command details structure or NULL
2008  *
2009  * Set link interrupt mask.
2010  **/
2011 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2012                                 u16 mask,
2013                                 struct i40e_asq_cmd_details *cmd_details)
2014 {
2015         struct i40e_aq_desc desc;
2016         struct i40e_aqc_set_phy_int_mask *cmd =
2017                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2018         enum i40e_status_code status;
2019
2020         i40e_fill_default_direct_cmd_desc(&desc,
2021                                           i40e_aqc_opc_set_phy_int_mask);
2022
2023         cmd->event_mask = CPU_TO_LE16(mask);
2024
2025         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2026
2027         return status;
2028 }
2029
2030 /**
2031  * i40e_aq_get_local_advt_reg
2032  * @hw: pointer to the hw struct
2033  * @advt_reg: local AN advertisement register value
2034  * @cmd_details: pointer to command details structure or NULL
2035  *
2036  * Get the Local AN advertisement register value.
2037  **/
2038 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2039                                 u64 *advt_reg,
2040                                 struct i40e_asq_cmd_details *cmd_details)
2041 {
2042         struct i40e_aq_desc desc;
2043         struct i40e_aqc_an_advt_reg *resp =
2044                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2045         enum i40e_status_code status;
2046
2047         i40e_fill_default_direct_cmd_desc(&desc,
2048                                           i40e_aqc_opc_get_local_advt_reg);
2049
2050         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2051
2052         if (status != I40E_SUCCESS)
2053                 goto aq_get_local_advt_reg_exit;
2054
2055         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2056         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2057
2058 aq_get_local_advt_reg_exit:
2059         return status;
2060 }
2061
2062 /**
2063  * i40e_aq_set_local_advt_reg
2064  * @hw: pointer to the hw struct
2065  * @advt_reg: local AN advertisement register value
2066  * @cmd_details: pointer to command details structure or NULL
2067  *
2068  * Get the Local AN advertisement register value.
2069  **/
2070 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2071                                 u64 advt_reg,
2072                                 struct i40e_asq_cmd_details *cmd_details)
2073 {
2074         struct i40e_aq_desc desc;
2075         struct i40e_aqc_an_advt_reg *cmd =
2076                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2077         enum i40e_status_code status;
2078
2079         i40e_fill_default_direct_cmd_desc(&desc,
2080                                           i40e_aqc_opc_get_local_advt_reg);
2081
2082         cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2083         cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2084
2085         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2086
2087         return status;
2088 }
2089
2090 /**
2091  * i40e_aq_get_partner_advt
2092  * @hw: pointer to the hw struct
2093  * @advt_reg: AN partner advertisement register value
2094  * @cmd_details: pointer to command details structure or NULL
2095  *
2096  * Get the link partner AN advertisement register value.
2097  **/
2098 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2099                                 u64 *advt_reg,
2100                                 struct i40e_asq_cmd_details *cmd_details)
2101 {
2102         struct i40e_aq_desc desc;
2103         struct i40e_aqc_an_advt_reg *resp =
2104                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2105         enum i40e_status_code status;
2106
2107         i40e_fill_default_direct_cmd_desc(&desc,
2108                                           i40e_aqc_opc_get_partner_advt);
2109
2110         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2111
2112         if (status != I40E_SUCCESS)
2113                 goto aq_get_partner_advt_exit;
2114
2115         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2116         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2117
2118 aq_get_partner_advt_exit:
2119         return status;
2120 }
2121
2122 /**
2123  * i40e_aq_set_lb_modes
2124  * @hw: pointer to the hw struct
2125  * @lb_modes: loopback mode to be set
2126  * @cmd_details: pointer to command details structure or NULL
2127  *
2128  * Sets loopback modes.
2129  **/
2130 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2131                                 u16 lb_modes,
2132                                 struct i40e_asq_cmd_details *cmd_details)
2133 {
2134         struct i40e_aq_desc desc;
2135         struct i40e_aqc_set_lb_mode *cmd =
2136                 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2137         enum i40e_status_code status;
2138
2139         i40e_fill_default_direct_cmd_desc(&desc,
2140                                           i40e_aqc_opc_set_lb_modes);
2141
2142         cmd->lb_mode = CPU_TO_LE16(lb_modes);
2143
2144         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2145
2146         return status;
2147 }
2148
2149 /**
2150  * i40e_aq_set_phy_debug
2151  * @hw: pointer to the hw struct
2152  * @cmd_flags: debug command flags
2153  * @cmd_details: pointer to command details structure or NULL
2154  *
2155  * Reset the external PHY.
2156  **/
2157 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2158                                 struct i40e_asq_cmd_details *cmd_details)
2159 {
2160         struct i40e_aq_desc desc;
2161         struct i40e_aqc_set_phy_debug *cmd =
2162                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2163         enum i40e_status_code status;
2164
2165         i40e_fill_default_direct_cmd_desc(&desc,
2166                                           i40e_aqc_opc_set_phy_debug);
2167
2168         cmd->command_flags = cmd_flags;
2169
2170         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2171
2172         return status;
2173 }
2174
2175 /**
2176  * i40e_aq_add_vsi
2177  * @hw: pointer to the hw struct
2178  * @vsi_ctx: pointer to a vsi context struct
2179  * @cmd_details: pointer to command details structure or NULL
2180  *
2181  * Add a VSI context to the hardware.
2182 **/
2183 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2184                                 struct i40e_vsi_context *vsi_ctx,
2185                                 struct i40e_asq_cmd_details *cmd_details)
2186 {
2187         struct i40e_aq_desc desc;
2188         struct i40e_aqc_add_get_update_vsi *cmd =
2189                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2190         struct i40e_aqc_add_get_update_vsi_completion *resp =
2191                 (struct i40e_aqc_add_get_update_vsi_completion *)
2192                 &desc.params.raw;
2193         enum i40e_status_code status;
2194
2195         i40e_fill_default_direct_cmd_desc(&desc,
2196                                           i40e_aqc_opc_add_vsi);
2197
2198         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2199         cmd->connection_type = vsi_ctx->connection_type;
2200         cmd->vf_id = vsi_ctx->vf_num;
2201         cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2202
2203         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2204
2205         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2206                                     sizeof(vsi_ctx->info), cmd_details);
2207
2208         if (status != I40E_SUCCESS)
2209                 goto aq_add_vsi_exit;
2210
2211         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2212         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2213         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2214         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2215
2216 aq_add_vsi_exit:
2217         return status;
2218 }
2219
2220 /**
2221  * i40e_aq_set_default_vsi
2222  * @hw: pointer to the hw struct
2223  * @seid: vsi number
2224  * @cmd_details: pointer to command details structure or NULL
2225  **/
2226 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2227                                 u16 seid,
2228                                 struct i40e_asq_cmd_details *cmd_details)
2229 {
2230         struct i40e_aq_desc desc;
2231         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2232                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2233                 &desc.params.raw;
2234         enum i40e_status_code status;
2235
2236         i40e_fill_default_direct_cmd_desc(&desc,
2237                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2238
2239         cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2240         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2241         cmd->seid = CPU_TO_LE16(seid);
2242
2243         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2244
2245         return status;
2246 }
2247
2248 /**
2249  * i40e_aq_clear_default_vsi
2250  * @hw: pointer to the hw struct
2251  * @seid: vsi number
2252  * @cmd_details: pointer to command details structure or NULL
2253  **/
2254 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2255                                 u16 seid,
2256                                 struct i40e_asq_cmd_details *cmd_details)
2257 {
2258         struct i40e_aq_desc desc;
2259         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2260                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2261                 &desc.params.raw;
2262         enum i40e_status_code status;
2263
2264         i40e_fill_default_direct_cmd_desc(&desc,
2265                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2266
2267         cmd->promiscuous_flags = CPU_TO_LE16(0);
2268         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2269         cmd->seid = CPU_TO_LE16(seid);
2270
2271         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2272
2273         return status;
2274 }
2275
2276 /**
2277  * i40e_aq_set_vsi_unicast_promiscuous
2278  * @hw: pointer to the hw struct
2279  * @seid: vsi number
2280  * @set: set unicast promiscuous enable/disable
2281  * @cmd_details: pointer to command details structure or NULL
2282  * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2283  **/
2284 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2285                                 u16 seid, bool set,
2286                                 struct i40e_asq_cmd_details *cmd_details,
2287                                 bool rx_only_promisc)
2288 {
2289         struct i40e_aq_desc desc;
2290         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2291                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2292         enum i40e_status_code status;
2293         u16 flags = 0;
2294
2295         i40e_fill_default_direct_cmd_desc(&desc,
2296                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2297
2298         if (set) {
2299                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2300                 if (rx_only_promisc &&
2301                     (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2302                      (hw->aq.api_maj_ver > 1)))
2303                         flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2304         }
2305
2306         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2307
2308         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2309         if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2310              (hw->aq.api_maj_ver > 1))
2311                 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2312
2313         cmd->seid = CPU_TO_LE16(seid);
2314         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2315
2316         return status;
2317 }
2318
2319 /**
2320  * i40e_aq_set_vsi_multicast_promiscuous
2321  * @hw: pointer to the hw struct
2322  * @seid: vsi number
2323  * @set: set multicast promiscuous enable/disable
2324  * @cmd_details: pointer to command details structure or NULL
2325  **/
2326 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2327                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2328 {
2329         struct i40e_aq_desc desc;
2330         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2331                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2332         enum i40e_status_code status;
2333         u16 flags = 0;
2334
2335         i40e_fill_default_direct_cmd_desc(&desc,
2336                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2337
2338         if (set)
2339                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2340
2341         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2342
2343         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2344
2345         cmd->seid = CPU_TO_LE16(seid);
2346         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2347
2348         return status;
2349 }
2350
2351 /**
2352  * i40e_aq_set_vsi_mc_promisc_on_vlan
2353  * @hw: pointer to the hw struct
2354  * @seid: vsi number
2355  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2356  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2357  * @cmd_details: pointer to command details structure or NULL
2358  **/
2359 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2360                                 u16 seid, bool enable, u16 vid,
2361                                 struct i40e_asq_cmd_details *cmd_details)
2362 {
2363         struct i40e_aq_desc desc;
2364         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2365                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2366         enum i40e_status_code status;
2367         u16 flags = 0;
2368
2369         i40e_fill_default_direct_cmd_desc(&desc,
2370                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2371
2372         if (enable)
2373                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2374
2375         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2376         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2377         cmd->seid = CPU_TO_LE16(seid);
2378         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2379
2380         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2381
2382         return status;
2383 }
2384
2385 /**
2386  * i40e_aq_set_vsi_uc_promisc_on_vlan
2387  * @hw: pointer to the hw struct
2388  * @seid: vsi number
2389  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2390  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2391  * @cmd_details: pointer to command details structure or NULL
2392  **/
2393 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2394                                 u16 seid, bool enable, u16 vid,
2395                                 struct i40e_asq_cmd_details *cmd_details)
2396 {
2397         struct i40e_aq_desc desc;
2398         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2399                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2400         enum i40e_status_code status;
2401         u16 flags = 0;
2402
2403         i40e_fill_default_direct_cmd_desc(&desc,
2404                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2405
2406         if (enable)
2407                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2408
2409         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2410         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2411         cmd->seid = CPU_TO_LE16(seid);
2412         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2413
2414         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2415
2416         return status;
2417 }
2418
2419 /**
2420  * i40e_aq_set_vsi_broadcast
2421  * @hw: pointer to the hw struct
2422  * @seid: vsi number
2423  * @set_filter: true to set filter, false to clear filter
2424  * @cmd_details: pointer to command details structure or NULL
2425  *
2426  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2427  **/
2428 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2429                                 u16 seid, bool set_filter,
2430                                 struct i40e_asq_cmd_details *cmd_details)
2431 {
2432         struct i40e_aq_desc desc;
2433         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2434                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2435         enum i40e_status_code status;
2436
2437         i40e_fill_default_direct_cmd_desc(&desc,
2438                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2439
2440         if (set_filter)
2441                 cmd->promiscuous_flags
2442                             |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2443         else
2444                 cmd->promiscuous_flags
2445                             &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2446
2447         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2448         cmd->seid = CPU_TO_LE16(seid);
2449         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2450
2451         return status;
2452 }
2453
2454 /**
2455  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2456  * @hw: pointer to the hw struct
2457  * @seid: vsi number
2458  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2459  * @cmd_details: pointer to command details structure or NULL
2460  **/
2461 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2462                                 u16 seid, bool enable,
2463                                 struct i40e_asq_cmd_details *cmd_details)
2464 {
2465         struct i40e_aq_desc desc;
2466         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2467                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2468         enum i40e_status_code status;
2469         u16 flags = 0;
2470
2471         i40e_fill_default_direct_cmd_desc(&desc,
2472                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2473         if (enable)
2474                 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2475
2476         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2477         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2478         cmd->seid = CPU_TO_LE16(seid);
2479
2480         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2481
2482         return status;
2483 }
2484
2485 /**
2486  * i40e_get_vsi_params - get VSI configuration info
2487  * @hw: pointer to the hw struct
2488  * @vsi_ctx: pointer to a vsi context struct
2489  * @cmd_details: pointer to command details structure or NULL
2490  **/
2491 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2492                                 struct i40e_vsi_context *vsi_ctx,
2493                                 struct i40e_asq_cmd_details *cmd_details)
2494 {
2495         struct i40e_aq_desc desc;
2496         struct i40e_aqc_add_get_update_vsi *cmd =
2497                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2498         struct i40e_aqc_add_get_update_vsi_completion *resp =
2499                 (struct i40e_aqc_add_get_update_vsi_completion *)
2500                 &desc.params.raw;
2501         enum i40e_status_code status;
2502
2503         UNREFERENCED_1PARAMETER(cmd_details);
2504         i40e_fill_default_direct_cmd_desc(&desc,
2505                                           i40e_aqc_opc_get_vsi_parameters);
2506
2507         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2508
2509         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2510
2511         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2512                                     sizeof(vsi_ctx->info), NULL);
2513
2514         if (status != I40E_SUCCESS)
2515                 goto aq_get_vsi_params_exit;
2516
2517         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2518         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2519         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2520         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2521
2522 aq_get_vsi_params_exit:
2523         return status;
2524 }
2525
2526 /**
2527  * i40e_aq_update_vsi_params
2528  * @hw: pointer to the hw struct
2529  * @vsi_ctx: pointer to a vsi context struct
2530  * @cmd_details: pointer to command details structure or NULL
2531  *
2532  * Update a VSI context.
2533  **/
2534 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2535                                 struct i40e_vsi_context *vsi_ctx,
2536                                 struct i40e_asq_cmd_details *cmd_details)
2537 {
2538         struct i40e_aq_desc desc;
2539         struct i40e_aqc_add_get_update_vsi *cmd =
2540                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2541         struct i40e_aqc_add_get_update_vsi_completion *resp =
2542                 (struct i40e_aqc_add_get_update_vsi_completion *)
2543                 &desc.params.raw;
2544         enum i40e_status_code status;
2545
2546         i40e_fill_default_direct_cmd_desc(&desc,
2547                                           i40e_aqc_opc_update_vsi_parameters);
2548         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2549
2550         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2551
2552         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2553                                     sizeof(vsi_ctx->info), cmd_details);
2554
2555         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2556         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2557
2558         return status;
2559 }
2560
2561 /**
2562  * i40e_aq_get_switch_config
2563  * @hw: pointer to the hardware structure
2564  * @buf: pointer to the result buffer
2565  * @buf_size: length of input buffer
2566  * @start_seid: seid to start for the report, 0 == beginning
2567  * @cmd_details: pointer to command details structure or NULL
2568  *
2569  * Fill the buf with switch configuration returned from AdminQ command
2570  **/
2571 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2572                                 struct i40e_aqc_get_switch_config_resp *buf,
2573                                 u16 buf_size, u16 *start_seid,
2574                                 struct i40e_asq_cmd_details *cmd_details)
2575 {
2576         struct i40e_aq_desc desc;
2577         struct i40e_aqc_switch_seid *scfg =
2578                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2579         enum i40e_status_code status;
2580
2581         i40e_fill_default_direct_cmd_desc(&desc,
2582                                           i40e_aqc_opc_get_switch_config);
2583         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2584         if (buf_size > I40E_AQ_LARGE_BUF)
2585                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2586         scfg->seid = CPU_TO_LE16(*start_seid);
2587
2588         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2589         *start_seid = LE16_TO_CPU(scfg->seid);
2590
2591         return status;
2592 }
2593
2594 /**
2595  * i40e_aq_set_switch_config
2596  * @hw: pointer to the hardware structure
2597  * @flags: bit flag values to set
2598  * @valid_flags: which bit flags to set
2599  * @cmd_details: pointer to command details structure or NULL
2600  *
2601  * Set switch configuration bits
2602  **/
2603 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2604                                 u16 flags, u16 valid_flags,
2605                                 struct i40e_asq_cmd_details *cmd_details)
2606 {
2607         struct i40e_aq_desc desc;
2608         struct i40e_aqc_set_switch_config *scfg =
2609                 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2610         enum i40e_status_code status;
2611
2612         i40e_fill_default_direct_cmd_desc(&desc,
2613                                           i40e_aqc_opc_set_switch_config);
2614         scfg->flags = CPU_TO_LE16(flags);
2615         scfg->valid_flags = CPU_TO_LE16(valid_flags);
2616
2617         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2618
2619         return status;
2620 }
2621
2622 /**
2623  * i40e_aq_get_firmware_version
2624  * @hw: pointer to the hw struct
2625  * @fw_major_version: firmware major version
2626  * @fw_minor_version: firmware minor version
2627  * @fw_build: firmware build number
2628  * @api_major_version: major queue version
2629  * @api_minor_version: minor queue version
2630  * @cmd_details: pointer to command details structure or NULL
2631  *
2632  * Get the firmware version from the admin queue commands
2633  **/
2634 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2635                                 u16 *fw_major_version, u16 *fw_minor_version,
2636                                 u32 *fw_build,
2637                                 u16 *api_major_version, u16 *api_minor_version,
2638                                 struct i40e_asq_cmd_details *cmd_details)
2639 {
2640         struct i40e_aq_desc desc;
2641         struct i40e_aqc_get_version *resp =
2642                 (struct i40e_aqc_get_version *)&desc.params.raw;
2643         enum i40e_status_code status;
2644
2645         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2646
2647         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2648
2649         if (status == I40E_SUCCESS) {
2650                 if (fw_major_version != NULL)
2651                         *fw_major_version = LE16_TO_CPU(resp->fw_major);
2652                 if (fw_minor_version != NULL)
2653                         *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2654                 if (fw_build != NULL)
2655                         *fw_build = LE32_TO_CPU(resp->fw_build);
2656                 if (api_major_version != NULL)
2657                         *api_major_version = LE16_TO_CPU(resp->api_major);
2658                 if (api_minor_version != NULL)
2659                         *api_minor_version = LE16_TO_CPU(resp->api_minor);
2660
2661                 /* A workaround to fix the API version in SW */
2662                 if (api_major_version && api_minor_version &&
2663                     fw_major_version && fw_minor_version &&
2664                     ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2665                     (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2666                      (*fw_major_version > 4)))
2667                         *api_minor_version = 2;
2668         }
2669
2670         return status;
2671 }
2672
2673 /**
2674  * i40e_aq_send_driver_version
2675  * @hw: pointer to the hw struct
2676  * @dv: driver's major, minor version
2677  * @cmd_details: pointer to command details structure or NULL
2678  *
2679  * Send the driver version to the firmware
2680  **/
2681 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2682                                 struct i40e_driver_version *dv,
2683                                 struct i40e_asq_cmd_details *cmd_details)
2684 {
2685         struct i40e_aq_desc desc;
2686         struct i40e_aqc_driver_version *cmd =
2687                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2688         enum i40e_status_code status;
2689         u16 len;
2690
2691         if (dv == NULL)
2692                 return I40E_ERR_PARAM;
2693
2694         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2695
2696         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2697         cmd->driver_major_ver = dv->major_version;
2698         cmd->driver_minor_ver = dv->minor_version;
2699         cmd->driver_build_ver = dv->build_version;
2700         cmd->driver_subbuild_ver = dv->subbuild_version;
2701
2702         len = 0;
2703         while (len < sizeof(dv->driver_string) &&
2704                (dv->driver_string[len] < 0x80) &&
2705                dv->driver_string[len])
2706                 len++;
2707         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2708                                        len, cmd_details);
2709
2710         return status;
2711 }
2712
2713 /**
2714  * i40e_get_link_status - get status of the HW network link
2715  * @hw: pointer to the hw struct
2716  * @link_up: pointer to bool (true/false = linkup/linkdown)
2717  *
2718  * Variable link_up true if link is up, false if link is down.
2719  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2720  *
2721  * Side effect: LinkStatusEvent reporting becomes enabled
2722  **/
2723 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2724 {
2725         enum i40e_status_code status = I40E_SUCCESS;
2726
2727         if (hw->phy.get_link_info) {
2728                 status = i40e_update_link_info(hw);
2729
2730                 if (status != I40E_SUCCESS)
2731                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2732                                    status);
2733         }
2734
2735         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2736
2737         return status;
2738 }
2739
2740 /**
2741  * i40e_updatelink_status - update status of the HW network link
2742  * @hw: pointer to the hw struct
2743  **/
2744 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2745 {
2746         struct i40e_aq_get_phy_abilities_resp abilities;
2747         enum i40e_status_code status = I40E_SUCCESS;
2748
2749         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2750         if (status)
2751                 return status;
2752
2753         /* extra checking needed to ensure link info to user is timely */
2754         if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2755             ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2756              !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2757                 status = i40e_aq_get_phy_capabilities(hw, false, false,
2758                                                       &abilities, NULL);
2759                 if (status)
2760                         return status;
2761
2762                 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2763                         sizeof(hw->phy.link_info.module_type));
2764         }
2765         return status;
2766 }
2767
2768
2769 /**
2770  * i40e_get_link_speed
2771  * @hw: pointer to the hw struct
2772  *
2773  * Returns the link speed of the adapter.
2774  **/
2775 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2776 {
2777         enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2778         enum i40e_status_code status = I40E_SUCCESS;
2779
2780         if (hw->phy.get_link_info) {
2781                 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2782
2783                 if (status != I40E_SUCCESS)
2784                         goto i40e_link_speed_exit;
2785         }
2786
2787         speed = hw->phy.link_info.link_speed;
2788
2789 i40e_link_speed_exit:
2790         return speed;
2791 }
2792
2793 /**
2794  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2795  * @hw: pointer to the hw struct
2796  * @uplink_seid: the MAC or other gizmo SEID
2797  * @downlink_seid: the VSI SEID
2798  * @enabled_tc: bitmap of TCs to be enabled
2799  * @default_port: true for default port VSI, false for control port
2800  * @veb_seid: pointer to where to put the resulting VEB SEID
2801  * @enable_stats: true to turn on VEB stats
2802  * @cmd_details: pointer to command details structure or NULL
2803  *
2804  * This asks the FW to add a VEB between the uplink and downlink
2805  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2806  **/
2807 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2808                                 u16 downlink_seid, u8 enabled_tc,
2809                                 bool default_port, u16 *veb_seid,
2810                                 bool enable_stats,
2811                                 struct i40e_asq_cmd_details *cmd_details)
2812 {
2813         struct i40e_aq_desc desc;
2814         struct i40e_aqc_add_veb *cmd =
2815                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2816         struct i40e_aqc_add_veb_completion *resp =
2817                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2818         enum i40e_status_code status;
2819         u16 veb_flags = 0;
2820
2821         /* SEIDs need to either both be set or both be 0 for floating VEB */
2822         if (!!uplink_seid != !!downlink_seid)
2823                 return I40E_ERR_PARAM;
2824
2825         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2826
2827         cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2828         cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2829         cmd->enable_tcs = enabled_tc;
2830         if (!uplink_seid)
2831                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2832         if (default_port)
2833                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2834         else
2835                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2836
2837         /* reverse logic here: set the bitflag to disable the stats */
2838         if (!enable_stats)
2839                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2840
2841         cmd->veb_flags = CPU_TO_LE16(veb_flags);
2842
2843         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2844
2845         if (!status && veb_seid)
2846                 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2847
2848         return status;
2849 }
2850
2851 /**
2852  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2853  * @hw: pointer to the hw struct
2854  * @veb_seid: the SEID of the VEB to query
2855  * @switch_id: the uplink switch id
2856  * @floating: set to true if the VEB is floating
2857  * @statistic_index: index of the stats counter block for this VEB
2858  * @vebs_used: number of VEB's used by function
2859  * @vebs_free: total VEB's not reserved by any function
2860  * @cmd_details: pointer to command details structure or NULL
2861  *
2862  * This retrieves the parameters for a particular VEB, specified by
2863  * uplink_seid, and returns them to the caller.
2864  **/
2865 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2866                                 u16 veb_seid, u16 *switch_id,
2867                                 bool *floating, u16 *statistic_index,
2868                                 u16 *vebs_used, u16 *vebs_free,
2869                                 struct i40e_asq_cmd_details *cmd_details)
2870 {
2871         struct i40e_aq_desc desc;
2872         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2873                 (struct i40e_aqc_get_veb_parameters_completion *)
2874                 &desc.params.raw;
2875         enum i40e_status_code status;
2876
2877         if (veb_seid == 0)
2878                 return I40E_ERR_PARAM;
2879
2880         i40e_fill_default_direct_cmd_desc(&desc,
2881                                           i40e_aqc_opc_get_veb_parameters);
2882         cmd_resp->seid = CPU_TO_LE16(veb_seid);
2883
2884         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2885         if (status)
2886                 goto get_veb_exit;
2887
2888         if (switch_id)
2889                 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2890         if (statistic_index)
2891                 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2892         if (vebs_used)
2893                 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2894         if (vebs_free)
2895                 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2896         if (floating) {
2897                 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2898
2899                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2900                         *floating = true;
2901                 else
2902                         *floating = false;
2903         }
2904
2905 get_veb_exit:
2906         return status;
2907 }
2908
2909 /**
2910  * i40e_aq_add_macvlan
2911  * @hw: pointer to the hw struct
2912  * @seid: VSI for the mac address
2913  * @mv_list: list of macvlans to be added
2914  * @count: length of the list
2915  * @cmd_details: pointer to command details structure or NULL
2916  *
2917  * Add MAC/VLAN addresses to the HW filtering
2918  **/
2919 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2920                         struct i40e_aqc_add_macvlan_element_data *mv_list,
2921                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2922 {
2923         struct i40e_aq_desc desc;
2924         struct i40e_aqc_macvlan *cmd =
2925                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2926         enum i40e_status_code status;
2927         u16 buf_size;
2928         int i;
2929
2930         if (count == 0 || !mv_list || !hw)
2931                 return I40E_ERR_PARAM;
2932
2933         buf_size = count * sizeof(*mv_list);
2934
2935         /* prep the rest of the request */
2936         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2937         cmd->num_addresses = CPU_TO_LE16(count);
2938         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2939         cmd->seid[1] = 0;
2940         cmd->seid[2] = 0;
2941
2942         for (i = 0; i < count; i++)
2943                 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
2944                         mv_list[i].flags |=
2945                             CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2946
2947         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2948         if (buf_size > I40E_AQ_LARGE_BUF)
2949                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2950
2951         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2952                                        cmd_details);
2953
2954         return status;
2955 }
2956
2957 /**
2958  * i40e_aq_remove_macvlan
2959  * @hw: pointer to the hw struct
2960  * @seid: VSI for the mac address
2961  * @mv_list: list of macvlans to be removed
2962  * @count: length of the list
2963  * @cmd_details: pointer to command details structure or NULL
2964  *
2965  * Remove MAC/VLAN addresses from the HW filtering
2966  **/
2967 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2968                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
2969                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2970 {
2971         struct i40e_aq_desc desc;
2972         struct i40e_aqc_macvlan *cmd =
2973                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2974         enum i40e_status_code status;
2975         u16 buf_size;
2976
2977         if (count == 0 || !mv_list || !hw)
2978                 return I40E_ERR_PARAM;
2979
2980         buf_size = count * sizeof(*mv_list);
2981
2982         /* prep the rest of the request */
2983         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2984         cmd->num_addresses = CPU_TO_LE16(count);
2985         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2986         cmd->seid[1] = 0;
2987         cmd->seid[2] = 0;
2988
2989         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2990         if (buf_size > I40E_AQ_LARGE_BUF)
2991                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2992
2993         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2994                                        cmd_details);
2995
2996         return status;
2997 }
2998
2999 /**
3000  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3001  * @hw: pointer to the hw struct
3002  * @opcode: AQ opcode for add or delete mirror rule
3003  * @sw_seid: Switch SEID (to which rule refers)
3004  * @rule_type: Rule Type (ingress/egress/VLAN)
3005  * @id: Destination VSI SEID or Rule ID
3006  * @count: length of the list
3007  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3008  * @cmd_details: pointer to command details structure or NULL
3009  * @rule_id: Rule ID returned from FW
3010  * @rule_used: Number of rules used in internal switch
3011  * @rule_free: Number of rules free in internal switch
3012  *
3013  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3014  * VEBs/VEPA elements only
3015  **/
3016 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3017                         u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3018                         u16 count, __le16 *mr_list,
3019                         struct i40e_asq_cmd_details *cmd_details,
3020                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3021 {
3022         struct i40e_aq_desc desc;
3023         struct i40e_aqc_add_delete_mirror_rule *cmd =
3024                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3025         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3026         (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3027         enum i40e_status_code status;
3028         u16 buf_size;
3029
3030         buf_size = count * sizeof(*mr_list);
3031
3032         /* prep the rest of the request */
3033         i40e_fill_default_direct_cmd_desc(&desc, opcode);
3034         cmd->seid = CPU_TO_LE16(sw_seid);
3035         cmd->rule_type = CPU_TO_LE16(rule_type &
3036                                      I40E_AQC_MIRROR_RULE_TYPE_MASK);
3037         cmd->num_entries = CPU_TO_LE16(count);
3038         /* Dest VSI for add, rule_id for delete */
3039         cmd->destination = CPU_TO_LE16(id);
3040         if (mr_list) {
3041                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3042                                                 I40E_AQ_FLAG_RD));
3043                 if (buf_size > I40E_AQ_LARGE_BUF)
3044                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3045         }
3046
3047         status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3048                                        cmd_details);
3049         if (status == I40E_SUCCESS ||
3050             hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3051                 if (rule_id)
3052                         *rule_id = LE16_TO_CPU(resp->rule_id);
3053                 if (rules_used)
3054                         *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3055                 if (rules_free)
3056                         *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3057         }
3058         return status;
3059 }
3060
3061 /**
3062  * i40e_aq_add_mirrorrule - add a mirror rule
3063  * @hw: pointer to the hw struct
3064  * @sw_seid: Switch SEID (to which rule refers)
3065  * @rule_type: Rule Type (ingress/egress/VLAN)
3066  * @dest_vsi: SEID of VSI to which packets will be mirrored
3067  * @count: length of the list
3068  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3069  * @cmd_details: pointer to command details structure or NULL
3070  * @rule_id: Rule ID returned from FW
3071  * @rule_used: Number of rules used in internal switch
3072  * @rule_free: Number of rules free in internal switch
3073  *
3074  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3075  **/
3076 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3077                         u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3078                         struct i40e_asq_cmd_details *cmd_details,
3079                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3080 {
3081         if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3082             rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3083                 if (count == 0 || !mr_list)
3084                         return I40E_ERR_PARAM;
3085         }
3086
3087         return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3088                                   rule_type, dest_vsi, count, mr_list,
3089                                   cmd_details, rule_id, rules_used, rules_free);
3090 }
3091
3092 /**
3093  * i40e_aq_delete_mirrorrule - delete a mirror rule
3094  * @hw: pointer to the hw struct
3095  * @sw_seid: Switch SEID (to which rule refers)
3096  * @rule_type: Rule Type (ingress/egress/VLAN)
3097  * @count: length of the list
3098  * @rule_id: Rule ID that is returned in the receive desc as part of
3099  *              add_mirrorrule.
3100  * @mr_list: list of mirrored VLAN IDs to be removed
3101  * @cmd_details: pointer to command details structure or NULL
3102  * @rule_used: Number of rules used in internal switch
3103  * @rule_free: Number of rules free in internal switch
3104  *
3105  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3106  **/
3107 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3108                         u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3109                         struct i40e_asq_cmd_details *cmd_details,
3110                         u16 *rules_used, u16 *rules_free)
3111 {
3112         /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3113         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3114                 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3115                  * mirroring. For other rule_type, count and rule_type should
3116                  * not matter.
3117                  */
3118                 if (count == 0 || !mr_list)
3119                         return I40E_ERR_PARAM;
3120         }
3121
3122         return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3123                                   rule_type, rule_id, count, mr_list,
3124                                   cmd_details, NULL, rules_used, rules_free);
3125 }
3126
3127 /**
3128  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3129  * @hw: pointer to the hw struct
3130  * @seid: VSI for the vlan filters
3131  * @v_list: list of vlan filters to be added
3132  * @count: length of the list
3133  * @cmd_details: pointer to command details structure or NULL
3134  **/
3135 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3136                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3137                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3138 {
3139         struct i40e_aq_desc desc;
3140         struct i40e_aqc_macvlan *cmd =
3141                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3142         enum i40e_status_code status;
3143         u16 buf_size;
3144
3145         if (count == 0 || !v_list || !hw)
3146                 return I40E_ERR_PARAM;
3147
3148         buf_size = count * sizeof(*v_list);
3149
3150         /* prep the rest of the request */
3151         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3152         cmd->num_addresses = CPU_TO_LE16(count);
3153         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3154         cmd->seid[1] = 0;
3155         cmd->seid[2] = 0;
3156
3157         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3158         if (buf_size > I40E_AQ_LARGE_BUF)
3159                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3160
3161         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3162                                        cmd_details);
3163
3164         return status;
3165 }
3166
3167 /**
3168  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3169  * @hw: pointer to the hw struct
3170  * @seid: VSI for the vlan filters
3171  * @v_list: list of macvlans to be removed
3172  * @count: length of the list
3173  * @cmd_details: pointer to command details structure or NULL
3174  **/
3175 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3176                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3177                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3178 {
3179         struct i40e_aq_desc desc;
3180         struct i40e_aqc_macvlan *cmd =
3181                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3182         enum i40e_status_code status;
3183         u16 buf_size;
3184
3185         if (count == 0 || !v_list || !hw)
3186                 return I40E_ERR_PARAM;
3187
3188         buf_size = count * sizeof(*v_list);
3189
3190         /* prep the rest of the request */
3191         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3192         cmd->num_addresses = CPU_TO_LE16(count);
3193         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3194         cmd->seid[1] = 0;
3195         cmd->seid[2] = 0;
3196
3197         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3198         if (buf_size > I40E_AQ_LARGE_BUF)
3199                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3200
3201         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3202                                        cmd_details);
3203
3204         return status;
3205 }
3206
3207 /**
3208  * i40e_aq_send_msg_to_vf
3209  * @hw: pointer to the hardware structure
3210  * @vfid: vf id to send msg
3211  * @v_opcode: opcodes for VF-PF communication
3212  * @v_retval: return error code
3213  * @msg: pointer to the msg buffer
3214  * @msglen: msg length
3215  * @cmd_details: pointer to command details
3216  *
3217  * send msg to vf
3218  **/
3219 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3220                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3221                                 struct i40e_asq_cmd_details *cmd_details)
3222 {
3223         struct i40e_aq_desc desc;
3224         struct i40e_aqc_pf_vf_message *cmd =
3225                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3226         enum i40e_status_code status;
3227
3228         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3229         cmd->id = CPU_TO_LE32(vfid);
3230         desc.cookie_high = CPU_TO_LE32(v_opcode);
3231         desc.cookie_low = CPU_TO_LE32(v_retval);
3232         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3233         if (msglen) {
3234                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3235                                                 I40E_AQ_FLAG_RD));
3236                 if (msglen > I40E_AQ_LARGE_BUF)
3237                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3238                 desc.datalen = CPU_TO_LE16(msglen);
3239         }
3240         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3241
3242         return status;
3243 }
3244
3245 /**
3246  * i40e_aq_debug_read_register
3247  * @hw: pointer to the hw struct
3248  * @reg_addr: register address
3249  * @reg_val: register value
3250  * @cmd_details: pointer to command details structure or NULL
3251  *
3252  * Read the register using the admin queue commands
3253  **/
3254 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3255                                 u32 reg_addr, u64 *reg_val,
3256                                 struct i40e_asq_cmd_details *cmd_details)
3257 {
3258         struct i40e_aq_desc desc;
3259         struct i40e_aqc_debug_reg_read_write *cmd_resp =
3260                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3261         enum i40e_status_code status;
3262
3263         if (reg_val == NULL)
3264                 return I40E_ERR_PARAM;
3265
3266         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3267
3268         cmd_resp->address = CPU_TO_LE32(reg_addr);
3269
3270         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3271
3272         if (status == I40E_SUCCESS) {
3273                 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3274                            (u64)LE32_TO_CPU(cmd_resp->value_low);
3275         }
3276
3277         return status;
3278 }
3279
3280 /**
3281  * i40e_aq_debug_write_register
3282  * @hw: pointer to the hw struct
3283  * @reg_addr: register address
3284  * @reg_val: register value
3285  * @cmd_details: pointer to command details structure or NULL
3286  *
3287  * Write to a register using the admin queue commands
3288  **/
3289 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3290                                 u32 reg_addr, u64 reg_val,
3291                                 struct i40e_asq_cmd_details *cmd_details)
3292 {
3293         struct i40e_aq_desc desc;
3294         struct i40e_aqc_debug_reg_read_write *cmd =
3295                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3296         enum i40e_status_code status;
3297
3298         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3299
3300         cmd->address = CPU_TO_LE32(reg_addr);
3301         cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3302         cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3303
3304         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3305
3306         return status;
3307 }
3308
3309 /**
3310  * i40e_aq_request_resource
3311  * @hw: pointer to the hw struct
3312  * @resource: resource id
3313  * @access: access type
3314  * @sdp_number: resource number
3315  * @timeout: the maximum time in ms that the driver may hold the resource
3316  * @cmd_details: pointer to command details structure or NULL
3317  *
3318  * requests common resource using the admin queue commands
3319  **/
3320 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3321                                 enum i40e_aq_resources_ids resource,
3322                                 enum i40e_aq_resource_access_type access,
3323                                 u8 sdp_number, u64 *timeout,
3324                                 struct i40e_asq_cmd_details *cmd_details)
3325 {
3326         struct i40e_aq_desc desc;
3327         struct i40e_aqc_request_resource *cmd_resp =
3328                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3329         enum i40e_status_code status;
3330
3331         DEBUGFUNC("i40e_aq_request_resource");
3332
3333         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3334
3335         cmd_resp->resource_id = CPU_TO_LE16(resource);
3336         cmd_resp->access_type = CPU_TO_LE16(access);
3337         cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3338
3339         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3340         /* The completion specifies the maximum time in ms that the driver
3341          * may hold the resource in the Timeout field.
3342          * If the resource is held by someone else, the command completes with
3343          * busy return value and the timeout field indicates the maximum time
3344          * the current owner of the resource has to free it.
3345          */
3346         if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3347                 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3348
3349         return status;
3350 }
3351
3352 /**
3353  * i40e_aq_release_resource
3354  * @hw: pointer to the hw struct
3355  * @resource: resource id
3356  * @sdp_number: resource number
3357  * @cmd_details: pointer to command details structure or NULL
3358  *
3359  * release common resource using the admin queue commands
3360  **/
3361 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3362                                 enum i40e_aq_resources_ids resource,
3363                                 u8 sdp_number,
3364                                 struct i40e_asq_cmd_details *cmd_details)
3365 {
3366         struct i40e_aq_desc desc;
3367         struct i40e_aqc_request_resource *cmd =
3368                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3369         enum i40e_status_code status;
3370
3371         DEBUGFUNC("i40e_aq_release_resource");
3372
3373         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3374
3375         cmd->resource_id = CPU_TO_LE16(resource);
3376         cmd->resource_number = CPU_TO_LE32(sdp_number);
3377
3378         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3379
3380         return status;
3381 }
3382
3383 /**
3384  * i40e_aq_read_nvm
3385  * @hw: pointer to the hw struct
3386  * @module_pointer: module pointer location in words from the NVM beginning
3387  * @offset: byte offset from the module beginning
3388  * @length: length of the section to be read (in bytes from the offset)
3389  * @data: command buffer (size [bytes] = length)
3390  * @last_command: tells if this is the last command in a series
3391  * @cmd_details: pointer to command details structure or NULL
3392  *
3393  * Read the NVM using the admin queue commands
3394  **/
3395 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3396                                 u32 offset, u16 length, void *data,
3397                                 bool last_command,
3398                                 struct i40e_asq_cmd_details *cmd_details)
3399 {
3400         struct i40e_aq_desc desc;
3401         struct i40e_aqc_nvm_update *cmd =
3402                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3403         enum i40e_status_code status;
3404
3405         DEBUGFUNC("i40e_aq_read_nvm");
3406
3407         /* In offset the highest byte must be zeroed. */
3408         if (offset & 0xFF000000) {
3409                 status = I40E_ERR_PARAM;
3410                 goto i40e_aq_read_nvm_exit;
3411         }
3412
3413         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3414
3415         /* If this is the last command in a series, set the proper flag. */
3416         if (last_command)
3417                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3418         cmd->module_pointer = module_pointer;
3419         cmd->offset = CPU_TO_LE32(offset);
3420         cmd->length = CPU_TO_LE16(length);
3421
3422         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3423         if (length > I40E_AQ_LARGE_BUF)
3424                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3425
3426         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3427
3428 i40e_aq_read_nvm_exit:
3429         return status;
3430 }
3431
3432 /**
3433  * i40e_aq_read_nvm_config - read an nvm config block
3434  * @hw: pointer to the hw struct
3435  * @cmd_flags: NVM access admin command bits
3436  * @field_id: field or feature id
3437  * @data: buffer for result
3438  * @buf_size: buffer size
3439  * @element_count: pointer to count of elements read by FW
3440  * @cmd_details: pointer to command details structure or NULL
3441  **/
3442 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3443                                 u8 cmd_flags, u32 field_id, void *data,
3444                                 u16 buf_size, u16 *element_count,
3445                                 struct i40e_asq_cmd_details *cmd_details)
3446 {
3447         struct i40e_aq_desc desc;
3448         struct i40e_aqc_nvm_config_read *cmd =
3449                 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3450         enum i40e_status_code status;
3451
3452         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3453         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3454         if (buf_size > I40E_AQ_LARGE_BUF)
3455                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3456
3457         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3458         cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3459         if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3460                 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3461         else
3462                 cmd->element_id_msw = 0;
3463
3464         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3465
3466         if (!status && element_count)
3467                 *element_count = LE16_TO_CPU(cmd->element_count);
3468
3469         return status;
3470 }
3471
3472 /**
3473  * i40e_aq_write_nvm_config - write an nvm config block
3474  * @hw: pointer to the hw struct
3475  * @cmd_flags: NVM access admin command bits
3476  * @data: buffer for result
3477  * @buf_size: buffer size
3478  * @element_count: count of elements to be written
3479  * @cmd_details: pointer to command details structure or NULL
3480  **/
3481 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3482                                 u8 cmd_flags, void *data, u16 buf_size,
3483                                 u16 element_count,
3484                                 struct i40e_asq_cmd_details *cmd_details)
3485 {
3486         struct i40e_aq_desc desc;
3487         struct i40e_aqc_nvm_config_write *cmd =
3488                 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3489         enum i40e_status_code status;
3490
3491         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3492         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3493         if (buf_size > I40E_AQ_LARGE_BUF)
3494                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3495
3496         cmd->element_count = CPU_TO_LE16(element_count);
3497         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3498         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3499
3500         return status;
3501 }
3502
3503 /**
3504  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3505  * @hw: pointer to the hw struct
3506  * @cmd_details: pointer to command details structure or NULL
3507  **/
3508 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3509                                 void *buff, u16 buff_size,
3510                                 struct i40e_asq_cmd_details *cmd_details)
3511 {
3512         struct i40e_aq_desc desc;
3513         enum i40e_status_code status;
3514
3515         UNREFERENCED_2PARAMETER(buff, buff_size);
3516
3517         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3518         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3519         if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3520                 status = I40E_ERR_NOT_IMPLEMENTED;
3521
3522         return status;
3523 }
3524
3525 /**
3526  * i40e_aq_erase_nvm
3527  * @hw: pointer to the hw struct
3528  * @module_pointer: module pointer location in words from the NVM beginning
3529  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3530  * @length: length of the section to be erased (expressed in 4 KB)
3531  * @last_command: tells if this is the last command in a series
3532  * @cmd_details: pointer to command details structure or NULL
3533  *
3534  * Erase the NVM sector using the admin queue commands
3535  **/
3536 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3537                                 u32 offset, u16 length, bool last_command,
3538                                 struct i40e_asq_cmd_details *cmd_details)
3539 {
3540         struct i40e_aq_desc desc;
3541         struct i40e_aqc_nvm_update *cmd =
3542                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3543         enum i40e_status_code status;
3544
3545         DEBUGFUNC("i40e_aq_erase_nvm");
3546
3547         /* In offset the highest byte must be zeroed. */
3548         if (offset & 0xFF000000) {
3549                 status = I40E_ERR_PARAM;
3550                 goto i40e_aq_erase_nvm_exit;
3551         }
3552
3553         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3554
3555         /* If this is the last command in a series, set the proper flag. */
3556         if (last_command)
3557                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3558         cmd->module_pointer = module_pointer;
3559         cmd->offset = CPU_TO_LE32(offset);
3560         cmd->length = CPU_TO_LE16(length);
3561
3562         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3563
3564 i40e_aq_erase_nvm_exit:
3565         return status;
3566 }
3567
3568 /**
3569  * i40e_parse_discover_capabilities
3570  * @hw: pointer to the hw struct
3571  * @buff: pointer to a buffer containing device/function capability records
3572  * @cap_count: number of capability records in the list
3573  * @list_type_opc: type of capabilities list to parse
3574  *
3575  * Parse the device/function capabilities list.
3576  **/
3577 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3578                                      u32 cap_count,
3579                                      enum i40e_admin_queue_opc list_type_opc)
3580 {
3581         struct i40e_aqc_list_capabilities_element_resp *cap;
3582         u32 valid_functions, num_functions;
3583         u32 number, logical_id, phys_id;
3584         struct i40e_hw_capabilities *p;
3585         u8 major_rev;
3586         u32 i = 0;
3587         u16 id;
3588
3589         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3590
3591         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3592                 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3593         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3594                 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3595         else
3596                 return;
3597
3598         for (i = 0; i < cap_count; i++, cap++) {
3599                 id = LE16_TO_CPU(cap->id);
3600                 number = LE32_TO_CPU(cap->number);
3601                 logical_id = LE32_TO_CPU(cap->logical_id);
3602                 phys_id = LE32_TO_CPU(cap->phys_id);
3603                 major_rev = cap->major_rev;
3604
3605                 switch (id) {
3606                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3607                         p->switch_mode = number;
3608                         i40e_debug(hw, I40E_DEBUG_INIT,
3609                                    "HW Capability: Switch mode = %d\n",
3610                                    p->switch_mode);
3611                         break;
3612                 case I40E_AQ_CAP_ID_MNG_MODE:
3613                         p->management_mode = number;
3614                         i40e_debug(hw, I40E_DEBUG_INIT,
3615                                    "HW Capability: Management Mode = %d\n",
3616                                    p->management_mode);
3617                         break;
3618                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3619                         p->npar_enable = number;
3620                         i40e_debug(hw, I40E_DEBUG_INIT,
3621                                    "HW Capability: NPAR enable = %d\n",
3622                                    p->npar_enable);
3623                         break;
3624                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3625                         p->os2bmc = number;
3626                         i40e_debug(hw, I40E_DEBUG_INIT,
3627                                    "HW Capability: OS2BMC = %d\n", p->os2bmc);
3628                         break;
3629                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3630                         p->valid_functions = number;
3631                         i40e_debug(hw, I40E_DEBUG_INIT,
3632                                    "HW Capability: Valid Functions = %d\n",
3633                                    p->valid_functions);
3634                         break;
3635                 case I40E_AQ_CAP_ID_SRIOV:
3636                         if (number == 1)
3637                                 p->sr_iov_1_1 = true;
3638                         i40e_debug(hw, I40E_DEBUG_INIT,
3639                                    "HW Capability: SR-IOV = %d\n",
3640                                    p->sr_iov_1_1);
3641                         break;
3642                 case I40E_AQ_CAP_ID_VF:
3643                         p->num_vfs = number;
3644                         p->vf_base_id = logical_id;
3645                         i40e_debug(hw, I40E_DEBUG_INIT,
3646                                    "HW Capability: VF count = %d\n",
3647                                    p->num_vfs);
3648                         i40e_debug(hw, I40E_DEBUG_INIT,
3649                                    "HW Capability: VF base_id = %d\n",
3650                                    p->vf_base_id);
3651                         break;
3652                 case I40E_AQ_CAP_ID_VMDQ:
3653                         if (number == 1)
3654                                 p->vmdq = true;
3655                         i40e_debug(hw, I40E_DEBUG_INIT,
3656                                    "HW Capability: VMDQ = %d\n", p->vmdq);
3657                         break;
3658                 case I40E_AQ_CAP_ID_8021QBG:
3659                         if (number == 1)
3660                                 p->evb_802_1_qbg = true;
3661                         i40e_debug(hw, I40E_DEBUG_INIT,
3662                                    "HW Capability: 802.1Qbg = %d\n", number);
3663                         break;
3664                 case I40E_AQ_CAP_ID_8021QBR:
3665                         if (number == 1)
3666                                 p->evb_802_1_qbh = true;
3667                         i40e_debug(hw, I40E_DEBUG_INIT,
3668                                    "HW Capability: 802.1Qbh = %d\n", number);
3669                         break;
3670                 case I40E_AQ_CAP_ID_VSI:
3671                         p->num_vsis = number;
3672                         i40e_debug(hw, I40E_DEBUG_INIT,
3673                                    "HW Capability: VSI count = %d\n",
3674                                    p->num_vsis);
3675                         break;
3676                 case I40E_AQ_CAP_ID_DCB:
3677                         if (number == 1) {
3678                                 p->dcb = true;
3679                                 p->enabled_tcmap = logical_id;
3680                                 p->maxtc = phys_id;
3681                         }
3682                         i40e_debug(hw, I40E_DEBUG_INIT,
3683                                    "HW Capability: DCB = %d\n", p->dcb);
3684                         i40e_debug(hw, I40E_DEBUG_INIT,
3685                                    "HW Capability: TC Mapping = %d\n",
3686                                    logical_id);
3687                         i40e_debug(hw, I40E_DEBUG_INIT,
3688                                    "HW Capability: TC Max = %d\n", p->maxtc);
3689                         break;
3690                 case I40E_AQ_CAP_ID_FCOE:
3691                         if (number == 1)
3692                                 p->fcoe = true;
3693                         i40e_debug(hw, I40E_DEBUG_INIT,
3694                                    "HW Capability: FCOE = %d\n", p->fcoe);
3695                         break;
3696                 case I40E_AQ_CAP_ID_ISCSI:
3697                         if (number == 1)
3698                                 p->iscsi = true;
3699                         i40e_debug(hw, I40E_DEBUG_INIT,
3700                                    "HW Capability: iSCSI = %d\n", p->iscsi);
3701                         break;
3702                 case I40E_AQ_CAP_ID_RSS:
3703                         p->rss = true;
3704                         p->rss_table_size = number;
3705                         p->rss_table_entry_width = logical_id;
3706                         i40e_debug(hw, I40E_DEBUG_INIT,
3707                                    "HW Capability: RSS = %d\n", p->rss);
3708                         i40e_debug(hw, I40E_DEBUG_INIT,
3709                                    "HW Capability: RSS table size = %d\n",
3710                                    p->rss_table_size);
3711                         i40e_debug(hw, I40E_DEBUG_INIT,
3712                                    "HW Capability: RSS table width = %d\n",
3713                                    p->rss_table_entry_width);
3714                         break;
3715                 case I40E_AQ_CAP_ID_RXQ:
3716                         p->num_rx_qp = number;
3717                         p->base_queue = phys_id;
3718                         i40e_debug(hw, I40E_DEBUG_INIT,
3719                                    "HW Capability: Rx QP = %d\n", number);
3720                         i40e_debug(hw, I40E_DEBUG_INIT,
3721                                    "HW Capability: base_queue = %d\n",
3722                                    p->base_queue);
3723                         break;
3724                 case I40E_AQ_CAP_ID_TXQ:
3725                         p->num_tx_qp = number;
3726                         p->base_queue = phys_id;
3727                         i40e_debug(hw, I40E_DEBUG_INIT,
3728                                    "HW Capability: Tx QP = %d\n", number);
3729                         i40e_debug(hw, I40E_DEBUG_INIT,
3730                                    "HW Capability: base_queue = %d\n",
3731                                    p->base_queue);
3732                         break;
3733                 case I40E_AQ_CAP_ID_MSIX:
3734                         p->num_msix_vectors = number;
3735                         i40e_debug(hw, I40E_DEBUG_INIT,
3736                                    "HW Capability: MSIX vector count = %d\n",
3737                                    p->num_msix_vectors);
3738                         break;
3739                 case I40E_AQ_CAP_ID_VF_MSIX:
3740                         p->num_msix_vectors_vf = number;
3741                         i40e_debug(hw, I40E_DEBUG_INIT,
3742                                    "HW Capability: MSIX VF vector count = %d\n",
3743                                    p->num_msix_vectors_vf);
3744                         break;
3745                 case I40E_AQ_CAP_ID_FLEX10:
3746                         if (major_rev == 1) {
3747                                 if (number == 1) {
3748                                         p->flex10_enable = true;
3749                                         p->flex10_capable = true;
3750                                 }
3751                         } else {
3752                                 /* Capability revision >= 2 */
3753                                 if (number & 1)
3754                                         p->flex10_enable = true;
3755                                 if (number & 2)
3756                                         p->flex10_capable = true;
3757                         }
3758                         p->flex10_mode = logical_id;
3759                         p->flex10_status = phys_id;
3760                         i40e_debug(hw, I40E_DEBUG_INIT,
3761                                    "HW Capability: Flex10 mode = %d\n",
3762                                    p->flex10_mode);
3763                         i40e_debug(hw, I40E_DEBUG_INIT,
3764                                    "HW Capability: Flex10 status = %d\n",
3765                                    p->flex10_status);
3766                         break;
3767                 case I40E_AQ_CAP_ID_CEM:
3768                         if (number == 1)
3769                                 p->mgmt_cem = true;
3770                         i40e_debug(hw, I40E_DEBUG_INIT,
3771                                    "HW Capability: CEM = %d\n", p->mgmt_cem);
3772                         break;
3773                 case I40E_AQ_CAP_ID_IWARP:
3774                         if (number == 1)
3775                                 p->iwarp = true;
3776                         i40e_debug(hw, I40E_DEBUG_INIT,
3777                                    "HW Capability: iWARP = %d\n", p->iwarp);
3778                         break;
3779                 case I40E_AQ_CAP_ID_LED:
3780                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3781                                 p->led[phys_id] = true;
3782                         i40e_debug(hw, I40E_DEBUG_INIT,
3783                                    "HW Capability: LED - PIN %d\n", phys_id);
3784                         break;
3785                 case I40E_AQ_CAP_ID_SDP:
3786                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3787                                 p->sdp[phys_id] = true;
3788                         i40e_debug(hw, I40E_DEBUG_INIT,
3789                                    "HW Capability: SDP - PIN %d\n", phys_id);
3790                         break;
3791                 case I40E_AQ_CAP_ID_MDIO:
3792                         if (number == 1) {
3793                                 p->mdio_port_num = phys_id;
3794                                 p->mdio_port_mode = logical_id;
3795                         }
3796                         i40e_debug(hw, I40E_DEBUG_INIT,
3797                                    "HW Capability: MDIO port number = %d\n",
3798                                    p->mdio_port_num);
3799                         i40e_debug(hw, I40E_DEBUG_INIT,
3800                                    "HW Capability: MDIO port mode = %d\n",
3801                                    p->mdio_port_mode);
3802                         break;
3803                 case I40E_AQ_CAP_ID_1588:
3804                         if (number == 1)
3805                                 p->ieee_1588 = true;
3806                         i40e_debug(hw, I40E_DEBUG_INIT,
3807                                    "HW Capability: IEEE 1588 = %d\n",
3808                                    p->ieee_1588);
3809                         break;
3810                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3811                         p->fd = true;
3812                         p->fd_filters_guaranteed = number;
3813                         p->fd_filters_best_effort = logical_id;
3814                         i40e_debug(hw, I40E_DEBUG_INIT,
3815                                    "HW Capability: Flow Director = 1\n");
3816                         i40e_debug(hw, I40E_DEBUG_INIT,
3817                                    "HW Capability: Guaranteed FD filters = %d\n",
3818                                    p->fd_filters_guaranteed);
3819                         break;
3820                 case I40E_AQ_CAP_ID_WSR_PROT:
3821                         p->wr_csr_prot = (u64)number;
3822                         p->wr_csr_prot |= (u64)logical_id << 32;
3823                         i40e_debug(hw, I40E_DEBUG_INIT,
3824                                    "HW Capability: wr_csr_prot = 0x%llX\n\n",
3825                                    (p->wr_csr_prot & 0xffff));
3826                         break;
3827                 case I40E_AQ_CAP_ID_NVM_MGMT:
3828                         if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3829                                 p->sec_rev_disabled = true;
3830                         if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3831                                 p->update_disabled = true;
3832                         break;
3833 #ifdef X722_SUPPORT
3834                 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3835                         hw->num_wol_proxy_filters = (u16)number;
3836                         hw->wol_proxy_vsi_seid = (u16)logical_id;
3837                         p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3838                         if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3839                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3840                         else
3841                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3842                         p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3843                         i40e_debug(hw, I40E_DEBUG_INIT,
3844                                    "HW Capability: WOL proxy filters = %d\n",
3845                                    hw->num_wol_proxy_filters);
3846                         break;
3847 #endif
3848                 default:
3849                         break;
3850                 }
3851         }
3852
3853         if (p->fcoe)
3854                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3855
3856         /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3857         p->fcoe = false;
3858
3859         /* count the enabled ports (aka the "not disabled" ports) */
3860         hw->num_ports = 0;
3861         for (i = 0; i < 4; i++) {
3862                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3863                 u64 port_cfg = 0;
3864
3865                 /* use AQ read to get the physical register offset instead
3866                  * of the port relative offset
3867                  */
3868                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3869                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3870                         hw->num_ports++;
3871         }
3872
3873         valid_functions = p->valid_functions;
3874         num_functions = 0;
3875         while (valid_functions) {
3876                 if (valid_functions & 1)
3877                         num_functions++;
3878                 valid_functions >>= 1;
3879         }
3880
3881         /* partition id is 1-based, and functions are evenly spread
3882          * across the ports as partitions
3883          */
3884         hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3885         hw->num_partitions = num_functions / hw->num_ports;
3886
3887         /* additional HW specific goodies that might
3888          * someday be HW version specific
3889          */
3890         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3891 }
3892
3893 /**
3894  * i40e_aq_discover_capabilities
3895  * @hw: pointer to the hw struct
3896  * @buff: a virtual buffer to hold the capabilities
3897  * @buff_size: Size of the virtual buffer
3898  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3899  * @list_type_opc: capabilities type to discover - pass in the command opcode
3900  * @cmd_details: pointer to command details structure or NULL
3901  *
3902  * Get the device capabilities descriptions from the firmware
3903  **/
3904 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3905                                 void *buff, u16 buff_size, u16 *data_size,
3906                                 enum i40e_admin_queue_opc list_type_opc,
3907                                 struct i40e_asq_cmd_details *cmd_details)
3908 {
3909         struct i40e_aqc_list_capabilites *cmd;
3910         struct i40e_aq_desc desc;
3911         enum i40e_status_code status = I40E_SUCCESS;
3912
3913         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3914
3915         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3916                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3917                 status = I40E_ERR_PARAM;
3918                 goto exit;
3919         }
3920
3921         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3922
3923         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3924         if (buff_size > I40E_AQ_LARGE_BUF)
3925                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3926
3927         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3928         *data_size = LE16_TO_CPU(desc.datalen);
3929
3930         if (status)
3931                 goto exit;
3932
3933         i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3934                                          list_type_opc);
3935
3936 exit:
3937         return status;
3938 }
3939
3940 /**
3941  * i40e_aq_update_nvm
3942  * @hw: pointer to the hw struct
3943  * @module_pointer: module pointer location in words from the NVM beginning
3944  * @offset: byte offset from the module beginning
3945  * @length: length of the section to be written (in bytes from the offset)
3946  * @data: command buffer (size [bytes] = length)
3947  * @last_command: tells if this is the last command in a series
3948  * @cmd_details: pointer to command details structure or NULL
3949  *
3950  * Update the NVM using the admin queue commands
3951  **/
3952 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3953                                 u32 offset, u16 length, void *data,
3954                                 bool last_command,
3955                                 struct i40e_asq_cmd_details *cmd_details)
3956 {
3957         struct i40e_aq_desc desc;
3958         struct i40e_aqc_nvm_update *cmd =
3959                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3960         enum i40e_status_code status;
3961
3962         DEBUGFUNC("i40e_aq_update_nvm");
3963
3964         /* In offset the highest byte must be zeroed. */
3965         if (offset & 0xFF000000) {
3966                 status = I40E_ERR_PARAM;
3967                 goto i40e_aq_update_nvm_exit;
3968         }
3969
3970         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3971
3972         /* If this is the last command in a series, set the proper flag. */
3973         if (last_command)
3974                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3975         cmd->module_pointer = module_pointer;
3976         cmd->offset = CPU_TO_LE32(offset);
3977         cmd->length = CPU_TO_LE16(length);
3978
3979         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3980         if (length > I40E_AQ_LARGE_BUF)
3981                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3982
3983         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3984
3985 i40e_aq_update_nvm_exit:
3986         return status;
3987 }
3988
3989 /**
3990  * i40e_aq_get_lldp_mib
3991  * @hw: pointer to the hw struct
3992  * @bridge_type: type of bridge requested
3993  * @mib_type: Local, Remote or both Local and Remote MIBs
3994  * @buff: pointer to a user supplied buffer to store the MIB block
3995  * @buff_size: size of the buffer (in bytes)
3996  * @local_len : length of the returned Local LLDP MIB
3997  * @remote_len: length of the returned Remote LLDP MIB
3998  * @cmd_details: pointer to command details structure or NULL
3999  *
4000  * Requests the complete LLDP MIB (entire packet).
4001  **/
4002 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4003                                 u8 mib_type, void *buff, u16 buff_size,
4004                                 u16 *local_len, u16 *remote_len,
4005                                 struct i40e_asq_cmd_details *cmd_details)
4006 {
4007         struct i40e_aq_desc desc;
4008         struct i40e_aqc_lldp_get_mib *cmd =
4009                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4010         struct i40e_aqc_lldp_get_mib *resp =
4011                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4012         enum i40e_status_code status;
4013
4014         if (buff_size == 0 || !buff)
4015                 return I40E_ERR_PARAM;
4016
4017         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4018         /* Indirect Command */
4019         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4020
4021         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4022         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4023                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4024
4025         desc.datalen = CPU_TO_LE16(buff_size);
4026
4027         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4028         if (buff_size > I40E_AQ_LARGE_BUF)
4029                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4030
4031         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4032         if (!status) {
4033                 if (local_len != NULL)
4034                         *local_len = LE16_TO_CPU(resp->local_len);
4035                 if (remote_len != NULL)
4036                         *remote_len = LE16_TO_CPU(resp->remote_len);
4037         }
4038
4039         return status;
4040 }
4041
4042  /**
4043  * i40e_aq_set_lldp_mib - Set the LLDP MIB
4044  * @hw: pointer to the hw struct
4045  * @mib_type: Local, Remote or both Local and Remote MIBs
4046  * @buff: pointer to a user supplied buffer to store the MIB block
4047  * @buff_size: size of the buffer (in bytes)
4048  * @cmd_details: pointer to command details structure or NULL
4049  *
4050  * Set the LLDP MIB.
4051  **/
4052 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4053                                 u8 mib_type, void *buff, u16 buff_size,
4054                                 struct i40e_asq_cmd_details *cmd_details)
4055 {
4056         struct i40e_aq_desc desc;
4057         struct i40e_aqc_lldp_set_local_mib *cmd =
4058                 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4059         enum i40e_status_code status;
4060
4061         if (buff_size == 0 || !buff)
4062                 return I40E_ERR_PARAM;
4063
4064         i40e_fill_default_direct_cmd_desc(&desc,
4065                                 i40e_aqc_opc_lldp_set_local_mib);
4066         /* Indirect Command */
4067         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4068         if (buff_size > I40E_AQ_LARGE_BUF)
4069                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4070         desc.datalen = CPU_TO_LE16(buff_size);
4071
4072         cmd->type = mib_type;
4073         cmd->length = CPU_TO_LE16(buff_size);
4074         cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4075         cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4076
4077         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4078         return status;
4079 }
4080
4081 /**
4082  * i40e_aq_cfg_lldp_mib_change_event
4083  * @hw: pointer to the hw struct
4084  * @enable_update: Enable or Disable event posting
4085  * @cmd_details: pointer to command details structure or NULL
4086  *
4087  * Enable or Disable posting of an event on ARQ when LLDP MIB
4088  * associated with the interface changes
4089  **/
4090 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4091                                 bool enable_update,
4092                                 struct i40e_asq_cmd_details *cmd_details)
4093 {
4094         struct i40e_aq_desc desc;
4095         struct i40e_aqc_lldp_update_mib *cmd =
4096                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4097         enum i40e_status_code status;
4098
4099         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4100
4101         if (!enable_update)
4102                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4103
4104         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4105
4106         return status;
4107 }
4108
4109 /**
4110  * i40e_aq_add_lldp_tlv
4111  * @hw: pointer to the hw struct
4112  * @bridge_type: type of bridge
4113  * @buff: buffer with TLV to add
4114  * @buff_size: length of the buffer
4115  * @tlv_len: length of the TLV to be added
4116  * @mib_len: length of the LLDP MIB returned in response
4117  * @cmd_details: pointer to command details structure or NULL
4118  *
4119  * Add the specified TLV to LLDP Local MIB for the given bridge type,
4120  * it is responsibility of the caller to make sure that the TLV is not
4121  * already present in the LLDPDU.
4122  * In return firmware will write the complete LLDP MIB with the newly
4123  * added TLV in the response buffer.
4124  **/
4125 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4126                                 void *buff, u16 buff_size, u16 tlv_len,
4127                                 u16 *mib_len,
4128                                 struct i40e_asq_cmd_details *cmd_details)
4129 {
4130         struct i40e_aq_desc desc;
4131         struct i40e_aqc_lldp_add_tlv *cmd =
4132                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4133         enum i40e_status_code status;
4134
4135         if (buff_size == 0 || !buff || tlv_len == 0)
4136                 return I40E_ERR_PARAM;
4137
4138         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4139
4140         /* Indirect Command */
4141         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4142         if (buff_size > I40E_AQ_LARGE_BUF)
4143                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4144         desc.datalen = CPU_TO_LE16(buff_size);
4145
4146         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4147                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4148         cmd->len = CPU_TO_LE16(tlv_len);
4149
4150         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4151         if (!status) {
4152                 if (mib_len != NULL)
4153                         *mib_len = LE16_TO_CPU(desc.datalen);
4154         }
4155
4156         return status;
4157 }
4158
4159 /**
4160  * i40e_aq_update_lldp_tlv
4161  * @hw: pointer to the hw struct
4162  * @bridge_type: type of bridge
4163  * @buff: buffer with TLV to update
4164  * @buff_size: size of the buffer holding original and updated TLVs
4165  * @old_len: Length of the Original TLV
4166  * @new_len: Length of the Updated TLV
4167  * @offset: offset of the updated TLV in the buff
4168  * @mib_len: length of the returned LLDP MIB
4169  * @cmd_details: pointer to command details structure or NULL
4170  *
4171  * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4172  * Firmware will place the complete LLDP MIB in response buffer with the
4173  * updated TLV.
4174  **/
4175 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4176                                 u8 bridge_type, void *buff, u16 buff_size,
4177                                 u16 old_len, u16 new_len, u16 offset,
4178                                 u16 *mib_len,
4179                                 struct i40e_asq_cmd_details *cmd_details)
4180 {
4181         struct i40e_aq_desc desc;
4182         struct i40e_aqc_lldp_update_tlv *cmd =
4183                 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4184         enum i40e_status_code status;
4185
4186         if (buff_size == 0 || !buff || offset == 0 ||
4187             old_len == 0 || new_len == 0)
4188                 return I40E_ERR_PARAM;
4189
4190         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4191
4192         /* Indirect Command */
4193         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4194         if (buff_size > I40E_AQ_LARGE_BUF)
4195                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4196         desc.datalen = CPU_TO_LE16(buff_size);
4197
4198         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4199                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4200         cmd->old_len = CPU_TO_LE16(old_len);
4201         cmd->new_offset = CPU_TO_LE16(offset);
4202         cmd->new_len = CPU_TO_LE16(new_len);
4203
4204         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4205         if (!status) {
4206                 if (mib_len != NULL)
4207                         *mib_len = LE16_TO_CPU(desc.datalen);
4208         }
4209
4210         return status;
4211 }
4212
4213 /**
4214  * i40e_aq_delete_lldp_tlv
4215  * @hw: pointer to the hw struct
4216  * @bridge_type: type of bridge
4217  * @buff: pointer to a user supplied buffer that has the TLV
4218  * @buff_size: length of the buffer
4219  * @tlv_len: length of the TLV to be deleted
4220  * @mib_len: length of the returned LLDP MIB
4221  * @cmd_details: pointer to command details structure or NULL
4222  *
4223  * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4224  * The firmware places the entire LLDP MIB in the response buffer.
4225  **/
4226 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4227                                 u8 bridge_type, void *buff, u16 buff_size,
4228                                 u16 tlv_len, u16 *mib_len,
4229                                 struct i40e_asq_cmd_details *cmd_details)
4230 {
4231         struct i40e_aq_desc desc;
4232         struct i40e_aqc_lldp_add_tlv *cmd =
4233                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4234         enum i40e_status_code status;
4235
4236         if (buff_size == 0 || !buff)
4237                 return I40E_ERR_PARAM;
4238
4239         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4240
4241         /* Indirect Command */
4242         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4243         if (buff_size > I40E_AQ_LARGE_BUF)
4244                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4245         desc.datalen = CPU_TO_LE16(buff_size);
4246         cmd->len = CPU_TO_LE16(tlv_len);
4247         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4248                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4249
4250         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4251         if (!status) {
4252                 if (mib_len != NULL)
4253                         *mib_len = LE16_TO_CPU(desc.datalen);
4254         }
4255
4256         return status;
4257 }
4258
4259 /**
4260  * i40e_aq_stop_lldp
4261  * @hw: pointer to the hw struct
4262  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4263  * @cmd_details: pointer to command details structure or NULL
4264  *
4265  * Stop or Shutdown the embedded LLDP Agent
4266  **/
4267 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4268                                 struct i40e_asq_cmd_details *cmd_details)
4269 {
4270         struct i40e_aq_desc desc;
4271         struct i40e_aqc_lldp_stop *cmd =
4272                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4273         enum i40e_status_code status;
4274
4275         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4276
4277         if (shutdown_agent)
4278                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4279
4280         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4281
4282         return status;
4283 }
4284
4285 /**
4286  * i40e_aq_start_lldp
4287  * @hw: pointer to the hw struct
4288  * @cmd_details: pointer to command details structure or NULL
4289  *
4290  * Start the embedded LLDP Agent on all ports.
4291  **/
4292 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4293                                 struct i40e_asq_cmd_details *cmd_details)
4294 {
4295         struct i40e_aq_desc desc;
4296         struct i40e_aqc_lldp_start *cmd =
4297                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4298         enum i40e_status_code status;
4299
4300         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4301
4302         cmd->command = I40E_AQ_LLDP_AGENT_START;
4303
4304         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4305
4306         return status;
4307 }
4308
4309 /**
4310  * i40e_aq_get_cee_dcb_config
4311  * @hw: pointer to the hw struct
4312  * @buff: response buffer that stores CEE operational configuration
4313  * @buff_size: size of the buffer passed
4314  * @cmd_details: pointer to command details structure or NULL
4315  *
4316  * Get CEE DCBX mode operational configuration from firmware
4317  **/
4318 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4319                                 void *buff, u16 buff_size,
4320                                 struct i40e_asq_cmd_details *cmd_details)
4321 {
4322         struct i40e_aq_desc desc;
4323         enum i40e_status_code status;
4324
4325         if (buff_size == 0 || !buff)
4326                 return I40E_ERR_PARAM;
4327
4328         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4329
4330         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4331         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4332                                        cmd_details);
4333
4334         return status;
4335 }
4336
4337 /**
4338  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4339  * @hw: pointer to the hw struct
4340  * @start_agent: True if DCBx Agent needs to be Started
4341  *                              False if DCBx Agent needs to be Stopped
4342  * @cmd_details: pointer to command details structure or NULL
4343  *
4344  * Start/Stop the embedded dcbx Agent
4345  **/
4346 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4347                                 bool start_agent,
4348                                 struct i40e_asq_cmd_details *cmd_details)
4349 {
4350         struct i40e_aq_desc desc;
4351         struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4352                 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4353                                 &desc.params.raw;
4354         enum i40e_status_code status;
4355
4356         i40e_fill_default_direct_cmd_desc(&desc,
4357                                 i40e_aqc_opc_lldp_stop_start_spec_agent);
4358
4359         if (start_agent)
4360                 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4361
4362         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4363
4364         return status;
4365 }
4366
4367 /**
4368  * i40e_aq_add_udp_tunnel
4369  * @hw: pointer to the hw struct
4370  * @udp_port: the UDP port to add
4371  * @header_len: length of the tunneling header length in DWords
4372  * @protocol_index: protocol index type
4373  * @filter_index: pointer to filter index
4374  * @cmd_details: pointer to command details structure or NULL
4375  **/
4376 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4377                                 u16 udp_port, u8 protocol_index,
4378                                 u8 *filter_index,
4379                                 struct i40e_asq_cmd_details *cmd_details)
4380 {
4381         struct i40e_aq_desc desc;
4382         struct i40e_aqc_add_udp_tunnel *cmd =
4383                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4384         struct i40e_aqc_del_udp_tunnel_completion *resp =
4385                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4386         enum i40e_status_code status;
4387
4388         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4389
4390         cmd->udp_port = CPU_TO_LE16(udp_port);
4391         cmd->protocol_type = protocol_index;
4392
4393         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4394
4395         if (!status && filter_index)
4396                 *filter_index = resp->index;
4397
4398         return status;
4399 }
4400
4401 /**
4402  * i40e_aq_del_udp_tunnel
4403  * @hw: pointer to the hw struct
4404  * @index: filter index
4405  * @cmd_details: pointer to command details structure or NULL
4406  **/
4407 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4408                                 struct i40e_asq_cmd_details *cmd_details)
4409 {
4410         struct i40e_aq_desc desc;
4411         struct i40e_aqc_remove_udp_tunnel *cmd =
4412                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4413         enum i40e_status_code status;
4414
4415         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4416
4417         cmd->index = index;
4418
4419         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4420
4421         return status;
4422 }
4423
4424 /**
4425  * i40e_aq_get_switch_resource_alloc (0x0204)
4426  * @hw: pointer to the hw struct
4427  * @num_entries: pointer to u8 to store the number of resource entries returned
4428  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
4429  *        to store the resource information for all resource types.  Each
4430  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
4431  * @count: size, in bytes, of the buffer provided
4432  * @cmd_details: pointer to command details structure or NULL
4433  *
4434  * Query the resources allocated to a function.
4435  **/
4436 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4437                         u8 *num_entries,
4438                         struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4439                         u16 count,
4440                         struct i40e_asq_cmd_details *cmd_details)
4441 {
4442         struct i40e_aq_desc desc;
4443         struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4444                 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4445         enum i40e_status_code status;
4446         u16 length = count * sizeof(*buf);
4447
4448         i40e_fill_default_direct_cmd_desc(&desc,
4449                                         i40e_aqc_opc_get_switch_resource_alloc);
4450
4451         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4452         if (length > I40E_AQ_LARGE_BUF)
4453                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4454
4455         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4456
4457         if (!status && num_entries)
4458                 *num_entries = cmd_resp->num_entries;
4459
4460         return status;
4461 }
4462
4463 /**
4464  * i40e_aq_delete_element - Delete switch element
4465  * @hw: pointer to the hw struct
4466  * @seid: the SEID to delete from the switch
4467  * @cmd_details: pointer to command details structure or NULL
4468  *
4469  * This deletes a switch element from the switch.
4470  **/
4471 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4472                                 struct i40e_asq_cmd_details *cmd_details)
4473 {
4474         struct i40e_aq_desc desc;
4475         struct i40e_aqc_switch_seid *cmd =
4476                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4477         enum i40e_status_code status;
4478
4479         if (seid == 0)
4480                 return I40E_ERR_PARAM;
4481
4482         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4483
4484         cmd->seid = CPU_TO_LE16(seid);
4485
4486         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4487
4488         return status;
4489 }
4490
4491 /**
4492  * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4493  * @hw: pointer to the hw struct
4494  * @flags: component flags
4495  * @mac_seid: uplink seid (MAC SEID)
4496  * @vsi_seid: connected vsi seid
4497  * @ret_seid: seid of create pv component
4498  *
4499  * This instantiates an i40e port virtualizer with specified flags.
4500  * Depending on specified flags the port virtualizer can act as a
4501  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4502  */
4503 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4504                                        u16 mac_seid, u16 vsi_seid,
4505                                        u16 *ret_seid)
4506 {
4507         struct i40e_aq_desc desc;
4508         struct i40e_aqc_add_update_pv *cmd =
4509                 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4510         struct i40e_aqc_add_update_pv_completion *resp =
4511                 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4512         enum i40e_status_code status;
4513
4514         if (vsi_seid == 0)
4515                 return I40E_ERR_PARAM;
4516
4517         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4518         cmd->command_flags = CPU_TO_LE16(flags);
4519         cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4520         cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4521
4522         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4523         if (!status && ret_seid)
4524                 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4525
4526         return status;
4527 }
4528
4529 /**
4530  * i40e_aq_add_tag - Add an S/E-tag
4531  * @hw: pointer to the hw struct
4532  * @direct_to_queue: should s-tag direct flow to a specific queue
4533  * @vsi_seid: VSI SEID to use this tag
4534  * @tag: value of the tag
4535  * @queue_num: queue number, only valid is direct_to_queue is true
4536  * @tags_used: return value, number of tags in use by this PF
4537  * @tags_free: return value, number of unallocated tags
4538  * @cmd_details: pointer to command details structure or NULL
4539  *
4540  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4541  * the number of tags allocated by the PF, and the number of unallocated
4542  * tags available.
4543  **/
4544 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4545                                 u16 vsi_seid, u16 tag, u16 queue_num,
4546                                 u16 *tags_used, u16 *tags_free,
4547                                 struct i40e_asq_cmd_details *cmd_details)
4548 {
4549         struct i40e_aq_desc desc;
4550         struct i40e_aqc_add_tag *cmd =
4551                 (struct i40e_aqc_add_tag *)&desc.params.raw;
4552         struct i40e_aqc_add_remove_tag_completion *resp =
4553                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4554         enum i40e_status_code status;
4555
4556         if (vsi_seid == 0)
4557                 return I40E_ERR_PARAM;
4558
4559         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4560
4561         cmd->seid = CPU_TO_LE16(vsi_seid);
4562         cmd->tag = CPU_TO_LE16(tag);
4563         if (direct_to_queue) {
4564                 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4565                 cmd->queue_number = CPU_TO_LE16(queue_num);
4566         }
4567
4568         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4569
4570         if (!status) {
4571                 if (tags_used != NULL)
4572                         *tags_used = LE16_TO_CPU(resp->tags_used);
4573                 if (tags_free != NULL)
4574                         *tags_free = LE16_TO_CPU(resp->tags_free);
4575         }
4576
4577         return status;
4578 }
4579
4580 /**
4581  * i40e_aq_remove_tag - Remove an S- or E-tag
4582  * @hw: pointer to the hw struct
4583  * @vsi_seid: VSI SEID this tag is associated with
4584  * @tag: value of the S-tag to delete
4585  * @tags_used: return value, number of tags in use by this PF
4586  * @tags_free: return value, number of unallocated tags
4587  * @cmd_details: pointer to command details structure or NULL
4588  *
4589  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4590  * the number of tags allocated by the PF, and the number of unallocated
4591  * tags available.
4592  **/
4593 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4594                                 u16 tag, u16 *tags_used, u16 *tags_free,
4595                                 struct i40e_asq_cmd_details *cmd_details)
4596 {
4597         struct i40e_aq_desc desc;
4598         struct i40e_aqc_remove_tag *cmd =
4599                 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4600         struct i40e_aqc_add_remove_tag_completion *resp =
4601                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4602         enum i40e_status_code status;
4603
4604         if (vsi_seid == 0)
4605                 return I40E_ERR_PARAM;
4606
4607         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4608
4609         cmd->seid = CPU_TO_LE16(vsi_seid);
4610         cmd->tag = CPU_TO_LE16(tag);
4611
4612         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4613
4614         if (!status) {
4615                 if (tags_used != NULL)
4616                         *tags_used = LE16_TO_CPU(resp->tags_used);
4617                 if (tags_free != NULL)
4618                         *tags_free = LE16_TO_CPU(resp->tags_free);
4619         }
4620
4621         return status;
4622 }
4623
4624 /**
4625  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4626  * @hw: pointer to the hw struct
4627  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4628  * @etag: value of E-tag to add
4629  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4630  * @buf: address of indirect buffer
4631  * @tags_used: return value, number of E-tags in use by this port
4632  * @tags_free: return value, number of unallocated M-tags
4633  * @cmd_details: pointer to command details structure or NULL
4634  *
4635  * This associates a multicast E-tag to a port virtualizer.  It will return
4636  * the number of tags allocated by the PF, and the number of unallocated
4637  * tags available.
4638  *
4639  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4640  * num_tags_in_buf long.
4641  **/
4642 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4643                                 u16 etag, u8 num_tags_in_buf, void *buf,
4644                                 u16 *tags_used, u16 *tags_free,
4645                                 struct i40e_asq_cmd_details *cmd_details)
4646 {
4647         struct i40e_aq_desc desc;
4648         struct i40e_aqc_add_remove_mcast_etag *cmd =
4649                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4650         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4651            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4652         enum i40e_status_code status;
4653         u16 length = sizeof(u16) * num_tags_in_buf;
4654
4655         if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4656                 return I40E_ERR_PARAM;
4657
4658         i40e_fill_default_direct_cmd_desc(&desc,
4659                                           i40e_aqc_opc_add_multicast_etag);
4660
4661         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4662         cmd->etag = CPU_TO_LE16(etag);
4663         cmd->num_unicast_etags = num_tags_in_buf;
4664
4665         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4666         if (length > I40E_AQ_LARGE_BUF)
4667                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4668
4669         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4670
4671         if (!status) {
4672                 if (tags_used != NULL)
4673                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4674                 if (tags_free != NULL)
4675                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4676         }
4677
4678         return status;
4679 }
4680
4681 /**
4682  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4683  * @hw: pointer to the hw struct
4684  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4685  * @etag: value of the E-tag to remove
4686  * @tags_used: return value, number of tags in use by this port
4687  * @tags_free: return value, number of unallocated tags
4688  * @cmd_details: pointer to command details structure or NULL
4689  *
4690  * This deletes an E-tag from the port virtualizer.  It will return
4691  * the number of tags allocated by the port, and the number of unallocated
4692  * tags available.
4693  **/
4694 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4695                                 u16 etag, u16 *tags_used, u16 *tags_free,
4696                                 struct i40e_asq_cmd_details *cmd_details)
4697 {
4698         struct i40e_aq_desc desc;
4699         struct i40e_aqc_add_remove_mcast_etag *cmd =
4700                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4701         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4702            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4703         enum i40e_status_code status;
4704
4705
4706         if (pv_seid == 0)
4707                 return I40E_ERR_PARAM;
4708
4709         i40e_fill_default_direct_cmd_desc(&desc,
4710                                           i40e_aqc_opc_remove_multicast_etag);
4711
4712         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4713         cmd->etag = CPU_TO_LE16(etag);
4714
4715         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4716
4717         if (!status) {
4718                 if (tags_used != NULL)
4719                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4720                 if (tags_free != NULL)
4721                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4722         }
4723
4724         return status;
4725 }
4726
4727 /**
4728  * i40e_aq_update_tag - Update an S/E-tag
4729  * @hw: pointer to the hw struct
4730  * @vsi_seid: VSI SEID using this S-tag
4731  * @old_tag: old tag value
4732  * @new_tag: new tag value
4733  * @tags_used: return value, number of tags in use by this PF
4734  * @tags_free: return value, number of unallocated tags
4735  * @cmd_details: pointer to command details structure or NULL
4736  *
4737  * This updates the value of the tag currently attached to this VSI
4738  * in the switch complex.  It will return the number of tags allocated
4739  * by the PF, and the number of unallocated tags available.
4740  **/
4741 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4742                                 u16 old_tag, u16 new_tag, u16 *tags_used,
4743                                 u16 *tags_free,
4744                                 struct i40e_asq_cmd_details *cmd_details)
4745 {
4746         struct i40e_aq_desc desc;
4747         struct i40e_aqc_update_tag *cmd =
4748                 (struct i40e_aqc_update_tag *)&desc.params.raw;
4749         struct i40e_aqc_update_tag_completion *resp =
4750                 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4751         enum i40e_status_code status;
4752
4753         if (vsi_seid == 0)
4754                 return I40E_ERR_PARAM;
4755
4756         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4757
4758         cmd->seid = CPU_TO_LE16(vsi_seid);
4759         cmd->old_tag = CPU_TO_LE16(old_tag);
4760         cmd->new_tag = CPU_TO_LE16(new_tag);
4761
4762         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4763
4764         if (!status) {
4765                 if (tags_used != NULL)
4766                         *tags_used = LE16_TO_CPU(resp->tags_used);
4767                 if (tags_free != NULL)
4768                         *tags_free = LE16_TO_CPU(resp->tags_free);
4769         }
4770
4771         return status;
4772 }
4773
4774 /**
4775  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4776  * @hw: pointer to the hw struct
4777  * @tcmap: TC map for request/release any ignore PFC condition
4778  * @request: request or release ignore PFC condition
4779  * @tcmap_ret: return TCs for which PFC is currently ignored
4780  * @cmd_details: pointer to command details structure or NULL
4781  *
4782  * This sends out request/release to ignore PFC condition for a TC.
4783  * It will return the TCs for which PFC is currently ignored.
4784  **/
4785 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4786                                 bool request, u8 *tcmap_ret,
4787                                 struct i40e_asq_cmd_details *cmd_details)
4788 {
4789         struct i40e_aq_desc desc;
4790         struct i40e_aqc_pfc_ignore *cmd_resp =
4791                 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4792         enum i40e_status_code status;
4793
4794         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4795
4796         if (request)
4797                 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4798
4799         cmd_resp->tc_bitmap = tcmap;
4800
4801         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4802
4803         if (!status) {
4804                 if (tcmap_ret != NULL)
4805                         *tcmap_ret = cmd_resp->tc_bitmap;
4806         }
4807
4808         return status;
4809 }
4810
4811 /**
4812  * i40e_aq_dcb_updated - DCB Updated Command
4813  * @hw: pointer to the hw struct
4814  * @cmd_details: pointer to command details structure or NULL
4815  *
4816  * When LLDP is handled in PF this command is used by the PF
4817  * to notify EMP that a DCB setting is modified.
4818  * When LLDP is handled in EMP this command is used by the PF
4819  * to notify EMP whenever one of the following parameters get
4820  * modified:
4821  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4822  *   - PCIRTT in PRTDCB_GENC.PCIRTT
4823  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4824  * EMP will return when the shared RPB settings have been
4825  * recomputed and modified. The retval field in the descriptor
4826  * will be set to 0 when RPB is modified.
4827  **/
4828 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4829                                 struct i40e_asq_cmd_details *cmd_details)
4830 {
4831         struct i40e_aq_desc desc;
4832         enum i40e_status_code status;
4833
4834         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4835
4836         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4837
4838         return status;
4839 }
4840
4841 /**
4842  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4843  * @hw: pointer to the hw struct
4844  * @seid: defines the SEID of the switch for which the stats are requested
4845  * @vlan_id: the VLAN ID for which the statistics are requested
4846  * @stat_index: index of the statistics counters block assigned to this VLAN
4847  * @cmd_details: pointer to command details structure or NULL
4848  *
4849  * XL710 supports 128 smonVlanStats counters.This command is used to
4850  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4851  * switch.
4852  **/
4853 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4854                                 u16 vlan_id, u16 *stat_index,
4855                                 struct i40e_asq_cmd_details *cmd_details)
4856 {
4857         struct i40e_aq_desc desc;
4858         struct i40e_aqc_add_remove_statistics *cmd_resp =
4859                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4860         enum i40e_status_code status;
4861
4862         if ((seid == 0) || (stat_index == NULL))
4863                 return I40E_ERR_PARAM;
4864
4865         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4866
4867         cmd_resp->seid = CPU_TO_LE16(seid);
4868         cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4869
4870         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4871
4872         if (!status && stat_index)
4873                 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4874
4875         return status;
4876 }
4877
4878 /**
4879  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4880  * @hw: pointer to the hw struct
4881  * @seid: defines the SEID of the switch for which the stats are requested
4882  * @vlan_id: the VLAN ID for which the statistics are requested
4883  * @stat_index: index of the statistics counters block assigned to this VLAN
4884  * @cmd_details: pointer to command details structure or NULL
4885  *
4886  * XL710 supports 128 smonVlanStats counters.This command is used to
4887  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4888  * switch.
4889  **/
4890 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4891                                 u16 vlan_id, u16 stat_index,
4892                                 struct i40e_asq_cmd_details *cmd_details)
4893 {
4894         struct i40e_aq_desc desc;
4895         struct i40e_aqc_add_remove_statistics *cmd =
4896                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4897         enum i40e_status_code status;
4898
4899         if (seid == 0)
4900                 return I40E_ERR_PARAM;
4901
4902         i40e_fill_default_direct_cmd_desc(&desc,
4903                                           i40e_aqc_opc_remove_statistics);
4904
4905         cmd->seid = CPU_TO_LE16(seid);
4906         cmd->vlan  = CPU_TO_LE16(vlan_id);
4907         cmd->stat_index = CPU_TO_LE16(stat_index);
4908
4909         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4910
4911         return status;
4912 }
4913
4914 /**
4915  * i40e_aq_set_port_parameters - set physical port parameters.
4916  * @hw: pointer to the hw struct
4917  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4918  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4919  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4920  * @double_vlan: if set double VLAN is enabled
4921  * @cmd_details: pointer to command details structure or NULL
4922  **/
4923 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4924                                 u16 bad_frame_vsi, bool save_bad_pac,
4925                                 bool pad_short_pac, bool double_vlan,
4926                                 struct i40e_asq_cmd_details *cmd_details)
4927 {
4928         struct i40e_aqc_set_port_parameters *cmd;
4929         enum i40e_status_code status;
4930         struct i40e_aq_desc desc;
4931         u16 command_flags = 0;
4932
4933         cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4934
4935         i40e_fill_default_direct_cmd_desc(&desc,
4936                                           i40e_aqc_opc_set_port_parameters);
4937
4938         cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4939         if (save_bad_pac)
4940                 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4941         if (pad_short_pac)
4942                 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4943         if (double_vlan)
4944                 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4945         cmd->command_flags = CPU_TO_LE16(command_flags);
4946
4947         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4948
4949         return status;
4950 }
4951
4952 /**
4953  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
4954  * @hw: pointer to the hw struct
4955  * @seid: seid for the physical port/switching component/vsi
4956  * @buff: Indirect buffer to hold data parameters and response
4957  * @buff_size: Indirect buffer size
4958  * @opcode: Tx scheduler AQ command opcode
4959  * @cmd_details: pointer to command details structure or NULL
4960  *
4961  * Generic command handler for Tx scheduler AQ commands
4962  **/
4963 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
4964                                 void *buff, u16 buff_size,
4965                                  enum i40e_admin_queue_opc opcode,
4966                                 struct i40e_asq_cmd_details *cmd_details)
4967 {
4968         struct i40e_aq_desc desc;
4969         struct i40e_aqc_tx_sched_ind *cmd =
4970                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4971         enum i40e_status_code status;
4972         bool cmd_param_flag = false;
4973
4974         switch (opcode) {
4975         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
4976         case i40e_aqc_opc_configure_vsi_tc_bw:
4977         case i40e_aqc_opc_enable_switching_comp_ets:
4978         case i40e_aqc_opc_modify_switching_comp_ets:
4979         case i40e_aqc_opc_disable_switching_comp_ets:
4980         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
4981         case i40e_aqc_opc_configure_switching_comp_bw_config:
4982                 cmd_param_flag = true;
4983                 break;
4984         case i40e_aqc_opc_query_vsi_bw_config:
4985         case i40e_aqc_opc_query_vsi_ets_sla_config:
4986         case i40e_aqc_opc_query_switching_comp_ets_config:
4987         case i40e_aqc_opc_query_port_ets_config:
4988         case i40e_aqc_opc_query_switching_comp_bw_config:
4989                 cmd_param_flag = false;
4990                 break;
4991         default:
4992                 return I40E_ERR_PARAM;
4993         }
4994
4995         i40e_fill_default_direct_cmd_desc(&desc, opcode);
4996
4997         /* Indirect command */
4998         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4999         if (cmd_param_flag)
5000                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5001         if (buff_size > I40E_AQ_LARGE_BUF)
5002                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5003
5004         desc.datalen = CPU_TO_LE16(buff_size);
5005
5006         cmd->vsi_seid = CPU_TO_LE16(seid);
5007
5008         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5009
5010         return status;
5011 }
5012
5013 /**
5014  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5015  * @hw: pointer to the hw struct
5016  * @seid: VSI seid
5017  * @credit: BW limit credits (0 = disabled)
5018  * @max_credit: Max BW limit credits
5019  * @cmd_details: pointer to command details structure or NULL
5020  **/
5021 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5022                                 u16 seid, u16 credit, u8 max_credit,
5023                                 struct i40e_asq_cmd_details *cmd_details)
5024 {
5025         struct i40e_aq_desc desc;
5026         struct i40e_aqc_configure_vsi_bw_limit *cmd =
5027                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5028         enum i40e_status_code status;
5029
5030         i40e_fill_default_direct_cmd_desc(&desc,
5031                                           i40e_aqc_opc_configure_vsi_bw_limit);
5032
5033         cmd->vsi_seid = CPU_TO_LE16(seid);
5034         cmd->credit = CPU_TO_LE16(credit);
5035         cmd->max_credit = max_credit;
5036
5037         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5038
5039         return status;
5040 }
5041
5042 /**
5043  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5044  * @hw: pointer to the hw struct
5045  * @seid: switching component seid
5046  * @credit: BW limit credits (0 = disabled)
5047  * @max_bw: Max BW limit credits
5048  * @cmd_details: pointer to command details structure or NULL
5049  **/
5050 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5051                                 u16 seid, u16 credit, u8 max_bw,
5052                                 struct i40e_asq_cmd_details *cmd_details)
5053 {
5054         struct i40e_aq_desc desc;
5055         struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5056           (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5057         enum i40e_status_code status;
5058
5059         i40e_fill_default_direct_cmd_desc(&desc,
5060                                 i40e_aqc_opc_configure_switching_comp_bw_limit);
5061
5062         cmd->seid = CPU_TO_LE16(seid);
5063         cmd->credit = CPU_TO_LE16(credit);
5064         cmd->max_bw = max_bw;
5065
5066         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5067
5068         return status;
5069 }
5070
5071 /**
5072  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5073  * @hw: pointer to the hw struct
5074  * @seid: VSI seid
5075  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5076  * @cmd_details: pointer to command details structure or NULL
5077  **/
5078 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5079                         u16 seid,
5080                         struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5081                         struct i40e_asq_cmd_details *cmd_details)
5082 {
5083         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5084                                     i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5085                                     cmd_details);
5086 }
5087
5088 /**
5089  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5090  * @hw: pointer to the hw struct
5091  * @seid: VSI seid
5092  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5093  * @cmd_details: pointer to command details structure or NULL
5094  **/
5095 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5096                         u16 seid,
5097                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5098                         struct i40e_asq_cmd_details *cmd_details)
5099 {
5100         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5101                                     i40e_aqc_opc_configure_vsi_tc_bw,
5102                                     cmd_details);
5103 }
5104
5105 /**
5106  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5107  * @hw: pointer to the hw struct
5108  * @seid: seid of the switching component connected to Physical Port
5109  * @ets_data: Buffer holding ETS parameters
5110  * @cmd_details: pointer to command details structure or NULL
5111  **/
5112 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5113                 u16 seid,
5114                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5115                 enum i40e_admin_queue_opc opcode,
5116                 struct i40e_asq_cmd_details *cmd_details)
5117 {
5118         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5119                                     sizeof(*ets_data), opcode, cmd_details);
5120 }
5121
5122 /**
5123  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5124  * @hw: pointer to the hw struct
5125  * @seid: seid of the switching component
5126  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5127  * @cmd_details: pointer to command details structure or NULL
5128  **/
5129 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5130         u16 seid,
5131         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5132         struct i40e_asq_cmd_details *cmd_details)
5133 {
5134         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5135                             i40e_aqc_opc_configure_switching_comp_bw_config,
5136                             cmd_details);
5137 }
5138
5139 /**
5140  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5141  * @hw: pointer to the hw struct
5142  * @seid: seid of the switching component
5143  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5144  * @cmd_details: pointer to command details structure or NULL
5145  **/
5146 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5147         struct i40e_hw *hw, u16 seid,
5148         struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5149         struct i40e_asq_cmd_details *cmd_details)
5150 {
5151         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5152                             i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5153                             cmd_details);
5154 }
5155
5156 /**
5157  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5158  * @hw: pointer to the hw struct
5159  * @seid: seid of the VSI
5160  * @bw_data: Buffer to hold VSI BW configuration
5161  * @cmd_details: pointer to command details structure or NULL
5162  **/
5163 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5164                         u16 seid,
5165                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5166                         struct i40e_asq_cmd_details *cmd_details)
5167 {
5168         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5169                                     i40e_aqc_opc_query_vsi_bw_config,
5170                                     cmd_details);
5171 }
5172
5173 /**
5174  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5175  * @hw: pointer to the hw struct
5176  * @seid: seid of the VSI
5177  * @bw_data: Buffer to hold VSI BW configuration per TC
5178  * @cmd_details: pointer to command details structure or NULL
5179  **/
5180 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5181                         u16 seid,
5182                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5183                         struct i40e_asq_cmd_details *cmd_details)
5184 {
5185         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5186                                     i40e_aqc_opc_query_vsi_ets_sla_config,
5187                                     cmd_details);
5188 }
5189
5190 /**
5191  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5192  * @hw: pointer to the hw struct
5193  * @seid: seid of the switching component
5194  * @bw_data: Buffer to hold switching component's per TC BW config
5195  * @cmd_details: pointer to command details structure or NULL
5196  **/
5197 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5198                 u16 seid,
5199                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5200                 struct i40e_asq_cmd_details *cmd_details)
5201 {
5202         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5203                                    i40e_aqc_opc_query_switching_comp_ets_config,
5204                                    cmd_details);
5205 }
5206
5207 /**
5208  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5209  * @hw: pointer to the hw struct
5210  * @seid: seid of the VSI or switching component connected to Physical Port
5211  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5212  * @cmd_details: pointer to command details structure or NULL
5213  **/
5214 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5215                         u16 seid,
5216                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
5217                         struct i40e_asq_cmd_details *cmd_details)
5218 {
5219         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5220                                     i40e_aqc_opc_query_port_ets_config,
5221                                     cmd_details);
5222 }
5223
5224 /**
5225  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5226  * @hw: pointer to the hw struct
5227  * @seid: seid of the switching component
5228  * @bw_data: Buffer to hold switching component's BW configuration
5229  * @cmd_details: pointer to command details structure or NULL
5230  **/
5231 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5232                 u16 seid,
5233                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5234                 struct i40e_asq_cmd_details *cmd_details)
5235 {
5236         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5237                                     i40e_aqc_opc_query_switching_comp_bw_config,
5238                                     cmd_details);
5239 }
5240
5241 /**
5242  * i40e_validate_filter_settings
5243  * @hw: pointer to the hardware structure
5244  * @settings: Filter control settings
5245  *
5246  * Check and validate the filter control settings passed.
5247  * The function checks for the valid filter/context sizes being
5248  * passed for FCoE and PE.
5249  *
5250  * Returns I40E_SUCCESS if the values passed are valid and within
5251  * range else returns an error.
5252  **/
5253 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5254                                 struct i40e_filter_control_settings *settings)
5255 {
5256         u32 fcoe_cntx_size, fcoe_filt_size;
5257         u32 pe_cntx_size, pe_filt_size;
5258         u32 fcoe_fmax;
5259
5260         u32 val;
5261
5262         /* Validate FCoE settings passed */
5263         switch (settings->fcoe_filt_num) {
5264         case I40E_HASH_FILTER_SIZE_1K:
5265         case I40E_HASH_FILTER_SIZE_2K:
5266         case I40E_HASH_FILTER_SIZE_4K:
5267         case I40E_HASH_FILTER_SIZE_8K:
5268         case I40E_HASH_FILTER_SIZE_16K:
5269         case I40E_HASH_FILTER_SIZE_32K:
5270                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5271                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5272                 break;
5273         default:
5274                 return I40E_ERR_PARAM;
5275         }
5276
5277         switch (settings->fcoe_cntx_num) {
5278         case I40E_DMA_CNTX_SIZE_512:
5279         case I40E_DMA_CNTX_SIZE_1K:
5280         case I40E_DMA_CNTX_SIZE_2K:
5281         case I40E_DMA_CNTX_SIZE_4K:
5282                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5283                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5284                 break;
5285         default:
5286                 return I40E_ERR_PARAM;
5287         }
5288
5289         /* Validate PE settings passed */
5290         switch (settings->pe_filt_num) {
5291         case I40E_HASH_FILTER_SIZE_1K:
5292         case I40E_HASH_FILTER_SIZE_2K:
5293         case I40E_HASH_FILTER_SIZE_4K:
5294         case I40E_HASH_FILTER_SIZE_8K:
5295         case I40E_HASH_FILTER_SIZE_16K:
5296         case I40E_HASH_FILTER_SIZE_32K:
5297         case I40E_HASH_FILTER_SIZE_64K:
5298         case I40E_HASH_FILTER_SIZE_128K:
5299         case I40E_HASH_FILTER_SIZE_256K:
5300         case I40E_HASH_FILTER_SIZE_512K:
5301         case I40E_HASH_FILTER_SIZE_1M:
5302                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5303                 pe_filt_size <<= (u32)settings->pe_filt_num;
5304                 break;
5305         default:
5306                 return I40E_ERR_PARAM;
5307         }
5308
5309         switch (settings->pe_cntx_num) {
5310         case I40E_DMA_CNTX_SIZE_512:
5311         case I40E_DMA_CNTX_SIZE_1K:
5312         case I40E_DMA_CNTX_SIZE_2K:
5313         case I40E_DMA_CNTX_SIZE_4K:
5314         case I40E_DMA_CNTX_SIZE_8K:
5315         case I40E_DMA_CNTX_SIZE_16K:
5316         case I40E_DMA_CNTX_SIZE_32K:
5317         case I40E_DMA_CNTX_SIZE_64K:
5318         case I40E_DMA_CNTX_SIZE_128K:
5319         case I40E_DMA_CNTX_SIZE_256K:
5320                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5321                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5322                 break;
5323         default:
5324                 return I40E_ERR_PARAM;
5325         }
5326
5327         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5328         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5329         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5330                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5331         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
5332                 return I40E_ERR_INVALID_SIZE;
5333
5334         return I40E_SUCCESS;
5335 }
5336
5337 /**
5338  * i40e_set_filter_control
5339  * @hw: pointer to the hardware structure
5340  * @settings: Filter control settings
5341  *
5342  * Set the Queue Filters for PE/FCoE and enable filters required
5343  * for a single PF. It is expected that these settings are programmed
5344  * at the driver initialization time.
5345  **/
5346 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5347                                 struct i40e_filter_control_settings *settings)
5348 {
5349         enum i40e_status_code ret = I40E_SUCCESS;
5350         u32 hash_lut_size = 0;
5351         u32 val;
5352
5353         if (!settings)
5354                 return I40E_ERR_PARAM;
5355
5356         /* Validate the input settings */
5357         ret = i40e_validate_filter_settings(hw, settings);
5358         if (ret)
5359                 return ret;
5360
5361         /* Read the PF Queue Filter control register */
5362         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5363
5364         /* Program required PE hash buckets for the PF */
5365         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5366         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5367                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5368         /* Program required PE contexts for the PF */
5369         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5370         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5371                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5372
5373         /* Program required FCoE hash buckets for the PF */
5374         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5375         val |= ((u32)settings->fcoe_filt_num <<
5376                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5377                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5378         /* Program required FCoE DDP contexts for the PF */
5379         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5380         val |= ((u32)settings->fcoe_cntx_num <<
5381                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5382                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5383
5384         /* Program Hash LUT size for the PF */
5385         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5386         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5387                 hash_lut_size = 1;
5388         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5389                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5390
5391         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5392         if (settings->enable_fdir)
5393                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5394         if (settings->enable_ethtype)
5395                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5396         if (settings->enable_macvlan)
5397                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5398
5399         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5400
5401         return I40E_SUCCESS;
5402 }
5403
5404 /**
5405  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5406  * @hw: pointer to the hw struct
5407  * @mac_addr: MAC address to use in the filter
5408  * @ethtype: Ethertype to use in the filter
5409  * @flags: Flags that needs to be applied to the filter
5410  * @vsi_seid: seid of the control VSI
5411  * @queue: VSI queue number to send the packet to
5412  * @is_add: Add control packet filter if True else remove
5413  * @stats: Structure to hold information on control filter counts
5414  * @cmd_details: pointer to command details structure or NULL
5415  *
5416  * This command will Add or Remove control packet filter for a control VSI.
5417  * In return it will update the total number of perfect filter count in
5418  * the stats member.
5419  **/
5420 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5421                                 u8 *mac_addr, u16 ethtype, u16 flags,
5422                                 u16 vsi_seid, u16 queue, bool is_add,
5423                                 struct i40e_control_filter_stats *stats,
5424                                 struct i40e_asq_cmd_details *cmd_details)
5425 {
5426         struct i40e_aq_desc desc;
5427         struct i40e_aqc_add_remove_control_packet_filter *cmd =
5428                 (struct i40e_aqc_add_remove_control_packet_filter *)
5429                 &desc.params.raw;
5430         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5431                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5432                 &desc.params.raw;
5433         enum i40e_status_code status;
5434
5435         if (vsi_seid == 0)
5436                 return I40E_ERR_PARAM;
5437
5438         if (is_add) {
5439                 i40e_fill_default_direct_cmd_desc(&desc,
5440                                 i40e_aqc_opc_add_control_packet_filter);
5441                 cmd->queue = CPU_TO_LE16(queue);
5442         } else {
5443                 i40e_fill_default_direct_cmd_desc(&desc,
5444                                 i40e_aqc_opc_remove_control_packet_filter);
5445         }
5446
5447         if (mac_addr)
5448                 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
5449                             I40E_NONDMA_TO_NONDMA);
5450
5451         cmd->etype = CPU_TO_LE16(ethtype);
5452         cmd->flags = CPU_TO_LE16(flags);
5453         cmd->seid = CPU_TO_LE16(vsi_seid);
5454
5455         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5456
5457         if (!status && stats) {
5458                 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5459                 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5460                 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5461                 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5462         }
5463
5464         return status;
5465 }
5466
5467 /**
5468  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5469  * @hw: pointer to the hw struct
5470  * @seid: VSI seid to add ethertype filter from
5471  **/
5472 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5473 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5474                                                     u16 seid)
5475 {
5476         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5477                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5478                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5479         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5480         enum i40e_status_code status;
5481
5482         status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5483                                                        seid, 0, true, NULL,
5484                                                        NULL);
5485         if (status)
5486                 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5487 }
5488
5489 /**
5490  * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5491  * @filters: list of cloud filters
5492  * @filter_count: length of list
5493  *
5494  * There's an issue in the device where the Geneve VNI layout needs
5495  * to be shifted 1 byte over from the VxLAN VNI
5496  **/
5497 STATIC void i40e_fix_up_geneve_vni(
5498         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5499         u8 filter_count)
5500 {
5501         struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters;
5502         int i;
5503
5504         for (i = 0; i < filter_count; i++) {
5505                 u16 tnl_type;
5506                 u32 ti;
5507
5508                 tnl_type = (LE16_TO_CPU(f[i].flags) &
5509                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5510                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5511                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5512                         ti = LE32_TO_CPU(f[i].tenant_id);
5513                         f[i].tenant_id = CPU_TO_LE32(ti << 8);
5514                 }
5515         }
5516 }
5517
5518 /**
5519  * i40e_aq_add_cloud_filters
5520  * @hw: pointer to the hardware structure
5521  * @seid: VSI seid to add cloud filters from
5522  * @filters: Buffer which contains the filters to be added
5523  * @filter_count: number of filters contained in the buffer
5524  *
5525  * Set the cloud filters for a given VSI.  The contents of the
5526  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5527  * in by the caller of the function.
5528  *
5529  **/
5530 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5531         u16 seid,
5532         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5533         u8 filter_count)
5534 {
5535         struct i40e_aq_desc desc;
5536         struct i40e_aqc_add_remove_cloud_filters *cmd =
5537         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5538         enum i40e_status_code status;
5539         u16 buff_len;
5540
5541         i40e_fill_default_direct_cmd_desc(&desc,
5542                                           i40e_aqc_opc_add_cloud_filters);
5543
5544         buff_len = filter_count * sizeof(*filters);
5545         desc.datalen = CPU_TO_LE16(buff_len);
5546         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5547         cmd->num_filters = filter_count;
5548         cmd->seid = CPU_TO_LE16(seid);
5549
5550         i40e_fix_up_geneve_vni(filters, filter_count);
5551
5552         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5553
5554         return status;
5555 }
5556
5557 /**
5558  * i40e_aq_remove_cloud_filters
5559  * @hw: pointer to the hardware structure
5560  * @seid: VSI seid to remove cloud filters from
5561  * @filters: Buffer which contains the filters to be removed
5562  * @filter_count: number of filters contained in the buffer
5563  *
5564  * Remove the cloud filters for a given VSI.  The contents of the
5565  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5566  * in by the caller of the function.
5567  *
5568  **/
5569 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5570                 u16 seid,
5571                 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5572                 u8 filter_count)
5573 {
5574         struct i40e_aq_desc desc;
5575         struct i40e_aqc_add_remove_cloud_filters *cmd =
5576         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5577         enum i40e_status_code status;
5578         u16 buff_len;
5579
5580         i40e_fill_default_direct_cmd_desc(&desc,
5581                                           i40e_aqc_opc_remove_cloud_filters);
5582
5583         buff_len = filter_count * sizeof(*filters);
5584         desc.datalen = CPU_TO_LE16(buff_len);
5585         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5586         cmd->num_filters = filter_count;
5587         cmd->seid = CPU_TO_LE16(seid);
5588
5589         i40e_fix_up_geneve_vni(filters, filter_count);
5590
5591         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5592
5593         return status;
5594 }
5595
5596 /**
5597  * i40e_aq_alternate_write
5598  * @hw: pointer to the hardware structure
5599  * @reg_addr0: address of first dword to be read
5600  * @reg_val0: value to be written under 'reg_addr0'
5601  * @reg_addr1: address of second dword to be read
5602  * @reg_val1: value to be written under 'reg_addr1'
5603  *
5604  * Write one or two dwords to alternate structure. Fields are indicated
5605  * by 'reg_addr0' and 'reg_addr1' register numbers.
5606  *
5607  **/
5608 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5609                                 u32 reg_addr0, u32 reg_val0,
5610                                 u32 reg_addr1, u32 reg_val1)
5611 {
5612         struct i40e_aq_desc desc;
5613         struct i40e_aqc_alternate_write *cmd_resp =
5614                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5615         enum i40e_status_code status;
5616
5617         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5618         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5619         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5620         cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5621         cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5622
5623         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5624
5625         return status;
5626 }
5627
5628 /**
5629  * i40e_aq_alternate_write_indirect
5630  * @hw: pointer to the hardware structure
5631  * @addr: address of a first register to be modified
5632  * @dw_count: number of alternate structure fields to write
5633  * @buffer: pointer to the command buffer
5634  *
5635  * Write 'dw_count' dwords from 'buffer' to alternate structure
5636  * starting at 'addr'.
5637  *
5638  **/
5639 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5640                                 u32 addr, u32 dw_count, void *buffer)
5641 {
5642         struct i40e_aq_desc desc;
5643         struct i40e_aqc_alternate_ind_write *cmd_resp =
5644                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5645         enum i40e_status_code status;
5646
5647         if (buffer == NULL)
5648                 return I40E_ERR_PARAM;
5649
5650         /* Indirect command */
5651         i40e_fill_default_direct_cmd_desc(&desc,
5652                                          i40e_aqc_opc_alternate_write_indirect);
5653
5654         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5655         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5656         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5657                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5658
5659         cmd_resp->address = CPU_TO_LE32(addr);
5660         cmd_resp->length = CPU_TO_LE32(dw_count);
5661
5662         status = i40e_asq_send_command(hw, &desc, buffer,
5663                                        I40E_LO_DWORD(4*dw_count), NULL);
5664
5665         return status;
5666 }
5667
5668 /**
5669  * i40e_aq_alternate_read
5670  * @hw: pointer to the hardware structure
5671  * @reg_addr0: address of first dword to be read
5672  * @reg_val0: pointer for data read from 'reg_addr0'
5673  * @reg_addr1: address of second dword to be read
5674  * @reg_val1: pointer for data read from 'reg_addr1'
5675  *
5676  * Read one or two dwords from alternate structure. Fields are indicated
5677  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5678  * is not passed then only register at 'reg_addr0' is read.
5679  *
5680  **/
5681 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5682                                 u32 reg_addr0, u32 *reg_val0,
5683                                 u32 reg_addr1, u32 *reg_val1)
5684 {
5685         struct i40e_aq_desc desc;
5686         struct i40e_aqc_alternate_write *cmd_resp =
5687                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5688         enum i40e_status_code status;
5689
5690         if (reg_val0 == NULL)
5691                 return I40E_ERR_PARAM;
5692
5693         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5694         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5695         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5696
5697         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5698
5699         if (status == I40E_SUCCESS) {
5700                 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5701
5702                 if (reg_val1 != NULL)
5703                         *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5704         }
5705
5706         return status;
5707 }
5708
5709 /**
5710  * i40e_aq_alternate_read_indirect
5711  * @hw: pointer to the hardware structure
5712  * @addr: address of the alternate structure field
5713  * @dw_count: number of alternate structure fields to read
5714  * @buffer: pointer to the command buffer
5715  *
5716  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5717  * place them in 'buffer'. The buffer should be allocated by caller.
5718  *
5719  **/
5720 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5721                                 u32 addr, u32 dw_count, void *buffer)
5722 {
5723         struct i40e_aq_desc desc;
5724         struct i40e_aqc_alternate_ind_write *cmd_resp =
5725                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5726         enum i40e_status_code status;
5727
5728         if (buffer == NULL)
5729                 return I40E_ERR_PARAM;
5730
5731         /* Indirect command */
5732         i40e_fill_default_direct_cmd_desc(&desc,
5733                 i40e_aqc_opc_alternate_read_indirect);
5734
5735         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5736         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5737         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5738                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5739
5740         cmd_resp->address = CPU_TO_LE32(addr);
5741         cmd_resp->length = CPU_TO_LE32(dw_count);
5742
5743         status = i40e_asq_send_command(hw, &desc, buffer,
5744                                        I40E_LO_DWORD(4*dw_count), NULL);
5745
5746         return status;
5747 }
5748
5749 /**
5750  *  i40e_aq_alternate_clear
5751  *  @hw: pointer to the HW structure.
5752  *
5753  *  Clear the alternate structures of the port from which the function
5754  *  is called.
5755  *
5756  **/
5757 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5758 {
5759         struct i40e_aq_desc desc;
5760         enum i40e_status_code status;
5761
5762         i40e_fill_default_direct_cmd_desc(&desc,
5763                                           i40e_aqc_opc_alternate_clear_port);
5764
5765         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5766
5767         return status;
5768 }
5769
5770 /**
5771  *  i40e_aq_alternate_write_done
5772  *  @hw: pointer to the HW structure.
5773  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
5774  *  @reset_needed: indicates the SW should trigger GLOBAL reset
5775  *
5776  *  Indicates to the FW that alternate structures have been changed.
5777  *
5778  **/
5779 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
5780                 u8 bios_mode, bool *reset_needed)
5781 {
5782         struct i40e_aq_desc desc;
5783         struct i40e_aqc_alternate_write_done *cmd =
5784                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5785         enum i40e_status_code status;
5786
5787         if (reset_needed == NULL)
5788                 return I40E_ERR_PARAM;
5789
5790         i40e_fill_default_direct_cmd_desc(&desc,
5791                                           i40e_aqc_opc_alternate_write_done);
5792
5793         cmd->cmd_flags = CPU_TO_LE16(bios_mode);
5794
5795         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5796         if (!status && reset_needed)
5797                 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
5798                                  I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
5799
5800         return status;
5801 }
5802
5803 /**
5804  *  i40e_aq_set_oem_mode
5805  *  @hw: pointer to the HW structure.
5806  *  @oem_mode: the OEM mode to be used
5807  *
5808  *  Sets the device to a specific operating mode. Currently the only supported
5809  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
5810  *
5811  **/
5812 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
5813                 u8 oem_mode)
5814 {
5815         struct i40e_aq_desc desc;
5816         struct i40e_aqc_alternate_write_done *cmd =
5817                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5818         enum i40e_status_code status;
5819
5820         i40e_fill_default_direct_cmd_desc(&desc,
5821                                           i40e_aqc_opc_alternate_set_mode);
5822
5823         cmd->cmd_flags = CPU_TO_LE16(oem_mode);
5824
5825         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5826
5827         return status;
5828 }
5829
5830 /**
5831  * i40e_aq_resume_port_tx
5832  * @hw: pointer to the hardware structure
5833  * @cmd_details: pointer to command details structure or NULL
5834  *
5835  * Resume port's Tx traffic
5836  **/
5837 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
5838                                 struct i40e_asq_cmd_details *cmd_details)
5839 {
5840         struct i40e_aq_desc desc;
5841         enum i40e_status_code status;
5842
5843         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
5844
5845         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5846
5847         return status;
5848 }
5849
5850 /**
5851  * i40e_set_pci_config_data - store PCI bus info
5852  * @hw: pointer to hardware structure
5853  * @link_status: the link status word from PCI config space
5854  *
5855  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
5856  **/
5857 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
5858 {
5859         hw->bus.type = i40e_bus_type_pci_express;
5860
5861         switch (link_status & I40E_PCI_LINK_WIDTH) {
5862         case I40E_PCI_LINK_WIDTH_1:
5863                 hw->bus.width = i40e_bus_width_pcie_x1;
5864                 break;
5865         case I40E_PCI_LINK_WIDTH_2:
5866                 hw->bus.width = i40e_bus_width_pcie_x2;
5867                 break;
5868         case I40E_PCI_LINK_WIDTH_4:
5869                 hw->bus.width = i40e_bus_width_pcie_x4;
5870                 break;
5871         case I40E_PCI_LINK_WIDTH_8:
5872                 hw->bus.width = i40e_bus_width_pcie_x8;
5873                 break;
5874         default:
5875                 hw->bus.width = i40e_bus_width_unknown;
5876                 break;
5877         }
5878
5879         switch (link_status & I40E_PCI_LINK_SPEED) {
5880         case I40E_PCI_LINK_SPEED_2500:
5881                 hw->bus.speed = i40e_bus_speed_2500;
5882                 break;
5883         case I40E_PCI_LINK_SPEED_5000:
5884                 hw->bus.speed = i40e_bus_speed_5000;
5885                 break;
5886         case I40E_PCI_LINK_SPEED_8000:
5887                 hw->bus.speed = i40e_bus_speed_8000;
5888                 break;
5889         default:
5890                 hw->bus.speed = i40e_bus_speed_unknown;
5891                 break;
5892         }
5893 }
5894
5895 /**
5896  * i40e_aq_debug_dump
5897  * @hw: pointer to the hardware structure
5898  * @cluster_id: specific cluster to dump
5899  * @table_id: table id within cluster
5900  * @start_index: index of line in the block to read
5901  * @buff_size: dump buffer size
5902  * @buff: dump buffer
5903  * @ret_buff_size: actual buffer size returned
5904  * @ret_next_table: next block to read
5905  * @ret_next_index: next index to read
5906  *
5907  * Dump internal FW/HW data for debug purposes.
5908  *
5909  **/
5910 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
5911                                 u8 table_id, u32 start_index, u16 buff_size,
5912                                 void *buff, u16 *ret_buff_size,
5913                                 u8 *ret_next_table, u32 *ret_next_index,
5914                                 struct i40e_asq_cmd_details *cmd_details)
5915 {
5916         struct i40e_aq_desc desc;
5917         struct i40e_aqc_debug_dump_internals *cmd =
5918                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5919         struct i40e_aqc_debug_dump_internals *resp =
5920                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5921         enum i40e_status_code status;
5922
5923         if (buff_size == 0 || !buff)
5924                 return I40E_ERR_PARAM;
5925
5926         i40e_fill_default_direct_cmd_desc(&desc,
5927                                           i40e_aqc_opc_debug_dump_internals);
5928         /* Indirect Command */
5929         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5930         if (buff_size > I40E_AQ_LARGE_BUF)
5931                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5932
5933         cmd->cluster_id = cluster_id;
5934         cmd->table_id = table_id;
5935         cmd->idx = CPU_TO_LE32(start_index);
5936
5937         desc.datalen = CPU_TO_LE16(buff_size);
5938
5939         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5940         if (!status) {
5941                 if (ret_buff_size != NULL)
5942                         *ret_buff_size = LE16_TO_CPU(desc.datalen);
5943                 if (ret_next_table != NULL)
5944                         *ret_next_table = resp->table_id;
5945                 if (ret_next_index != NULL)
5946                         *ret_next_index = LE32_TO_CPU(resp->idx);
5947         }
5948
5949         return status;
5950 }
5951
5952 /**
5953  * i40e_read_bw_from_alt_ram
5954  * @hw: pointer to the hardware structure
5955  * @max_bw: pointer for max_bw read
5956  * @min_bw: pointer for min_bw read
5957  * @min_valid: pointer for bool that is true if min_bw is a valid value
5958  * @max_valid: pointer for bool that is true if max_bw is a valid value
5959  *
5960  * Read bw from the alternate ram for the given pf
5961  **/
5962 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
5963                                         u32 *max_bw, u32 *min_bw,
5964                                         bool *min_valid, bool *max_valid)
5965 {
5966         enum i40e_status_code status;
5967         u32 max_bw_addr, min_bw_addr;
5968
5969         /* Calculate the address of the min/max bw registers */
5970         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5971                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
5972                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5973         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5974                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
5975                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5976
5977         /* Read the bandwidths from alt ram */
5978         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
5979                                         min_bw_addr, min_bw);
5980
5981         if (*min_bw & I40E_ALT_BW_VALID_MASK)
5982                 *min_valid = true;
5983         else
5984                 *min_valid = false;
5985
5986         if (*max_bw & I40E_ALT_BW_VALID_MASK)
5987                 *max_valid = true;
5988         else
5989                 *max_valid = false;
5990
5991         return status;
5992 }
5993
5994 /**
5995  * i40e_aq_configure_partition_bw
5996  * @hw: pointer to the hardware structure
5997  * @bw_data: Buffer holding valid pfs and bw limits
5998  * @cmd_details: pointer to command details
5999  *
6000  * Configure partitions guaranteed/max bw
6001  **/
6002 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6003                         struct i40e_aqc_configure_partition_bw_data *bw_data,
6004                         struct i40e_asq_cmd_details *cmd_details)
6005 {
6006         enum i40e_status_code status;
6007         struct i40e_aq_desc desc;
6008         u16 bwd_size = sizeof(*bw_data);
6009
6010         i40e_fill_default_direct_cmd_desc(&desc,
6011                                 i40e_aqc_opc_configure_partition_bw);
6012
6013         /* Indirect command */
6014         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6015         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6016
6017         desc.datalen = CPU_TO_LE16(bwd_size);
6018
6019         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6020
6021         return status;
6022 }
6023
6024 /**
6025  * i40e_read_phy_register
6026  * @hw: pointer to the HW structure
6027  * @page: registers page number
6028  * @reg: register address in the page
6029  * @phy_adr: PHY address on MDIO interface
6030  * @value: PHY register value
6031  *
6032  * Reads specified PHY register value
6033  **/
6034 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6035                                              u8 page, u16 reg, u8 phy_addr,
6036                                              u16 *value)
6037 {
6038         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6039         u32 command  = 0;
6040         u16 retry = 1000;
6041         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6042
6043         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6044                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6045                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6046                   (I40E_MDIO_OPCODE_ADDRESS) |
6047                   (I40E_MDIO_STCODE) |
6048                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6049                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6050         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6051         do {
6052                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6053                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6054                         status = I40E_SUCCESS;
6055                         break;
6056                 }
6057                 i40e_usec_delay(10);
6058                 retry--;
6059         } while (retry);
6060
6061         if (status) {
6062                 i40e_debug(hw, I40E_DEBUG_PHY,
6063                            "PHY: Can't write command to external PHY.\n");
6064                 goto phy_read_end;
6065         }
6066
6067         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6068                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6069                   (I40E_MDIO_OPCODE_READ) |
6070                   (I40E_MDIO_STCODE) |
6071                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6072                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6073         status = I40E_ERR_TIMEOUT;
6074         retry = 1000;
6075         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6076         do {
6077                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6078                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6079                         status = I40E_SUCCESS;
6080                         break;
6081                 }
6082                 i40e_usec_delay(10);
6083                 retry--;
6084         } while (retry);
6085
6086         if (!status) {
6087                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6088                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6089                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6090         } else {
6091                 i40e_debug(hw, I40E_DEBUG_PHY,
6092                            "PHY: Can't read register value from external PHY.\n");
6093         }
6094
6095 phy_read_end:
6096         return status;
6097 }
6098
6099 /**
6100  * i40e_write_phy_register
6101  * @hw: pointer to the HW structure
6102  * @page: registers page number
6103  * @reg: register address in the page
6104  * @phy_adr: PHY address on MDIO interface
6105  * @value: PHY register value
6106  *
6107  * Writes value to specified PHY register
6108  **/
6109 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6110                                               u8 page, u16 reg, u8 phy_addr,
6111                                               u16 value)
6112 {
6113         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6114         u32 command  = 0;
6115         u16 retry = 1000;
6116         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6117
6118         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6119                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6120                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6121                   (I40E_MDIO_OPCODE_ADDRESS) |
6122                   (I40E_MDIO_STCODE) |
6123                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6124                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6125         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6126         do {
6127                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6128                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6129                         status = I40E_SUCCESS;
6130                         break;
6131                 }
6132                 i40e_usec_delay(10);
6133                 retry--;
6134         } while (retry);
6135         if (status) {
6136                 i40e_debug(hw, I40E_DEBUG_PHY,
6137                            "PHY: Can't write command to external PHY.\n");
6138                 goto phy_write_end;
6139         }
6140
6141         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6142         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6143
6144         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6145                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6146                   (I40E_MDIO_OPCODE_WRITE) |
6147                   (I40E_MDIO_STCODE) |
6148                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6149                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6150         status = I40E_ERR_TIMEOUT;
6151         retry = 1000;
6152         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6153         do {
6154                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6155                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6156                         status = I40E_SUCCESS;
6157                         break;
6158                 }
6159                 i40e_usec_delay(10);
6160                 retry--;
6161         } while (retry);
6162
6163 phy_write_end:
6164         return status;
6165 }
6166
6167 /**
6168  * i40e_get_phy_address
6169  * @hw: pointer to the HW structure
6170  * @dev_num: PHY port num that address we want
6171  * @phy_addr: Returned PHY address
6172  *
6173  * Gets PHY address for current port
6174  **/
6175 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6176 {
6177         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6178         u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6179
6180         return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6181 }
6182
6183 /**
6184  * i40e_blink_phy_led
6185  * @hw: pointer to the HW structure
6186  * @time: time how long led will blinks in secs
6187  * @interval: gap between LED on and off in msecs
6188  *
6189  * Blinks PHY link LED
6190  **/
6191 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6192                                               u32 time, u32 interval)
6193 {
6194         enum i40e_status_code status = I40E_SUCCESS;
6195         u32 i;
6196         u16 led_ctl = 0;
6197         u16 gpio_led_port;
6198         u16 led_reg;
6199         u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6200         u8 phy_addr = 0;
6201         u8 port_num;
6202
6203         i = rd32(hw, I40E_PFGEN_PORTNUM);
6204         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6205         phy_addr = i40e_get_phy_address(hw, port_num);
6206
6207         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6208              led_addr++) {
6209                 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6210                                                 led_addr, phy_addr, &led_reg);
6211                 if (status)
6212                         goto phy_blinking_end;
6213                 led_ctl = led_reg;
6214                 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6215                         led_reg = 0;
6216                         status = i40e_write_phy_register(hw,
6217                                                          I40E_PHY_COM_REG_PAGE,
6218                                                          led_addr, phy_addr,
6219                                                          led_reg);
6220                         if (status)
6221                                 goto phy_blinking_end;
6222                         break;
6223                 }
6224         }
6225
6226         if (time > 0 && interval > 0) {
6227                 for (i = 0; i < time * 1000; i += interval) {
6228                         status = i40e_read_phy_register(hw,
6229                                                         I40E_PHY_COM_REG_PAGE,
6230                                                         led_addr, phy_addr,
6231                                                         &led_reg);
6232                         if (status)
6233                                 goto restore_config;
6234                         if (led_reg & I40E_PHY_LED_MANUAL_ON)
6235                                 led_reg = 0;
6236                         else
6237                                 led_reg = I40E_PHY_LED_MANUAL_ON;
6238                         status = i40e_write_phy_register(hw,
6239                                                          I40E_PHY_COM_REG_PAGE,
6240                                                          led_addr, phy_addr,
6241                                                          led_reg);
6242                         if (status)
6243                                 goto restore_config;
6244                         i40e_msec_delay(interval);
6245                 }
6246         }
6247
6248 restore_config:
6249         status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6250                                          phy_addr, led_ctl);
6251
6252 phy_blinking_end:
6253         return status;
6254 }
6255
6256 /**
6257  * i40e_led_get_phy - return current on/off mode
6258  * @hw: pointer to the hw struct
6259  * @led_addr: address of led register to use
6260  * @val: original value of register to use
6261  *
6262  **/
6263 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6264                                        u16 *val)
6265 {
6266         enum i40e_status_code status = I40E_SUCCESS;
6267         u16 gpio_led_port;
6268         u8 phy_addr = 0;
6269         u16 reg_val;
6270         u16 temp_addr;
6271         u8 port_num;
6272         u32 i;
6273
6274         temp_addr = I40E_PHY_LED_PROV_REG_1;
6275         i = rd32(hw, I40E_PFGEN_PORTNUM);
6276         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6277         phy_addr = i40e_get_phy_address(hw, port_num);
6278
6279         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6280              temp_addr++) {
6281                 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6282                                                 temp_addr, phy_addr, &reg_val);
6283                 if (status)
6284                         return status;
6285                 *val = reg_val;
6286                 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6287                         *led_addr = temp_addr;
6288                         break;
6289                 }
6290         }
6291         return status;
6292 }
6293
6294 /**
6295  * i40e_led_set_phy
6296  * @hw: pointer to the HW structure
6297  * @on: true or false
6298  * @mode: original val plus bit for set or ignore
6299  * Set led's on or off when controlled by the PHY
6300  *
6301  **/
6302 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6303                                        u16 led_addr, u32 mode)
6304 {
6305         enum i40e_status_code status = I40E_SUCCESS;
6306         u16 led_ctl = 0;
6307         u16 led_reg = 0;
6308         u8 phy_addr = 0;
6309         u8 port_num;
6310         u32 i;
6311
6312         i = rd32(hw, I40E_PFGEN_PORTNUM);
6313         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6314         phy_addr = i40e_get_phy_address(hw, port_num);
6315
6316         status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6317                                         phy_addr, &led_reg);
6318         if (status)
6319                 return status;
6320         led_ctl = led_reg;
6321         if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6322                 led_reg = 0;
6323                 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6324                                                  led_addr, phy_addr, led_reg);
6325                 if (status)
6326                         return status;
6327         }
6328         status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6329                                         led_addr, phy_addr, &led_reg);
6330         if (status)
6331                 goto restore_config;
6332         if (on)
6333                 led_reg = I40E_PHY_LED_MANUAL_ON;
6334         else
6335                 led_reg = 0;
6336         status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6337                                          led_addr, phy_addr, led_reg);
6338         if (status)
6339                 goto restore_config;
6340         if (mode & I40E_PHY_LED_MODE_ORIG) {
6341                 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6342                 status = i40e_write_phy_register(hw,
6343                                                  I40E_PHY_COM_REG_PAGE,
6344                                                  led_addr, phy_addr, led_ctl);
6345         }
6346         return status;
6347 restore_config:
6348         status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6349                                          phy_addr, led_ctl);
6350         return status;
6351 }
6352 #endif /* PF_DRIVER */
6353
6354 /**
6355  * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6356  * @hw: pointer to the hw struct
6357  * @reg_addr: register address
6358  * @reg_val: ptr to register value
6359  * @cmd_details: pointer to command details structure or NULL
6360  *
6361  * Use the firmware to read the Rx control register,
6362  * especially useful if the Rx unit is under heavy pressure
6363  **/
6364 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6365                                 u32 reg_addr, u32 *reg_val,
6366                                 struct i40e_asq_cmd_details *cmd_details)
6367 {
6368         struct i40e_aq_desc desc;
6369         struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
6370                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6371         enum i40e_status_code status;
6372
6373         if (reg_val == NULL)
6374                 return I40E_ERR_PARAM;
6375
6376         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
6377
6378         cmd_resp->address = CPU_TO_LE32(reg_addr);
6379
6380         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6381
6382         if (status == I40E_SUCCESS)
6383                 *reg_val = LE32_TO_CPU(cmd_resp->value);
6384
6385         return status;
6386 }
6387
6388 /**
6389  * i40e_read_rx_ctl - read from an Rx control register
6390  * @hw: pointer to the hw struct
6391  * @reg_addr: register address
6392  **/
6393 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
6394 {
6395         enum i40e_status_code status = I40E_SUCCESS;
6396         bool use_register;
6397         int retry = 5;
6398         u32 val = 0;
6399
6400         use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6401         if (!use_register) {
6402 do_retry:
6403                 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
6404                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6405                         i40e_msec_delay(1);
6406                         retry--;
6407                         goto do_retry;
6408                 }
6409         }
6410
6411         /* if the AQ access failed, try the old-fashioned way */
6412         if (status || use_register)
6413                 val = rd32(hw, reg_addr);
6414
6415         return val;
6416 }
6417
6418 /**
6419  * i40e_aq_rx_ctl_write_register
6420  * @hw: pointer to the hw struct
6421  * @reg_addr: register address
6422  * @reg_val: register value
6423  * @cmd_details: pointer to command details structure or NULL
6424  *
6425  * Use the firmware to write to an Rx control register,
6426  * especially useful if the Rx unit is under heavy pressure
6427  **/
6428 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
6429                                 u32 reg_addr, u32 reg_val,
6430                                 struct i40e_asq_cmd_details *cmd_details)
6431 {
6432         struct i40e_aq_desc desc;
6433         struct i40e_aqc_rx_ctl_reg_read_write *cmd =
6434                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6435         enum i40e_status_code status;
6436
6437         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
6438
6439         cmd->address = CPU_TO_LE32(reg_addr);
6440         cmd->value = CPU_TO_LE32(reg_val);
6441
6442         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6443
6444         return status;
6445 }
6446
6447 /**
6448  * i40e_write_rx_ctl - write to an Rx control register
6449  * @hw: pointer to the hw struct
6450  * @reg_addr: register address
6451  * @reg_val: register value
6452  **/
6453 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
6454 {
6455         enum i40e_status_code status = I40E_SUCCESS;
6456         bool use_register;
6457         int retry = 5;
6458
6459         use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6460         if (!use_register) {
6461 do_retry:
6462                 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
6463                                                        reg_val, NULL);
6464                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6465                         i40e_msec_delay(1);
6466                         retry--;
6467                         goto do_retry;
6468                 }
6469         }
6470
6471         /* if the AQ access failed, try the old-fashioned way */
6472         if (status || use_register)
6473                 wr32(hw, reg_addr, reg_val);
6474 }
6475 #ifdef VF_DRIVER
6476
6477 /**
6478  * i40e_aq_send_msg_to_pf
6479  * @hw: pointer to the hardware structure
6480  * @v_opcode: opcodes for VF-PF communication
6481  * @v_retval: return error code
6482  * @msg: pointer to the msg buffer
6483  * @msglen: msg length
6484  * @cmd_details: pointer to command details
6485  *
6486  * Send message to PF driver using admin queue. By default, this message
6487  * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
6488  * completion before returning.
6489  **/
6490 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
6491                                 enum i40e_virtchnl_ops v_opcode,
6492                                 enum i40e_status_code v_retval,
6493                                 u8 *msg, u16 msglen,
6494                                 struct i40e_asq_cmd_details *cmd_details)
6495 {
6496         struct i40e_aq_desc desc;
6497         struct i40e_asq_cmd_details details;
6498         enum i40e_status_code status;
6499
6500         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
6501         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
6502         desc.cookie_high = CPU_TO_LE32(v_opcode);
6503         desc.cookie_low = CPU_TO_LE32(v_retval);
6504         if (msglen) {
6505                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
6506                                                 | I40E_AQ_FLAG_RD));
6507                 if (msglen > I40E_AQ_LARGE_BUF)
6508                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6509                 desc.datalen = CPU_TO_LE16(msglen);
6510         }
6511         if (!cmd_details) {
6512                 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
6513                 details.async = true;
6514                 cmd_details = &details;
6515         }
6516         status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
6517                                        msglen, cmd_details);
6518         return status;
6519 }
6520
6521 /**
6522  * i40e_vf_parse_hw_config
6523  * @hw: pointer to the hardware structure
6524  * @msg: pointer to the virtual channel VF resource structure
6525  *
6526  * Given a VF resource message from the PF, populate the hw struct
6527  * with appropriate information.
6528  **/
6529 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
6530                              struct i40e_virtchnl_vf_resource *msg)
6531 {
6532         struct i40e_virtchnl_vsi_resource *vsi_res;
6533         int i;
6534
6535         vsi_res = &msg->vsi_res[0];
6536
6537         hw->dev_caps.num_vsis = msg->num_vsis;
6538         hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
6539         hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
6540         hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
6541         hw->dev_caps.dcb = msg->vf_offload_flags &
6542                            I40E_VIRTCHNL_VF_OFFLOAD_L2;
6543         hw->dev_caps.fcoe = (msg->vf_offload_flags &
6544                              I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
6545         hw->dev_caps.iwarp = (msg->vf_offload_flags &
6546                               I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
6547         for (i = 0; i < msg->num_vsis; i++) {
6548                 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
6549                         i40e_memcpy(hw->mac.perm_addr,
6550                                     vsi_res->default_mac_addr,
6551                                     I40E_ETH_LENGTH_OF_ADDRESS,
6552                                     I40E_NONDMA_TO_NONDMA);
6553                         i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
6554                                     I40E_ETH_LENGTH_OF_ADDRESS,
6555                                     I40E_NONDMA_TO_NONDMA);
6556                 }
6557                 vsi_res++;
6558         }
6559 }
6560
6561 /**
6562  * i40e_vf_reset
6563  * @hw: pointer to the hardware structure
6564  *
6565  * Send a VF_RESET message to the PF. Does not wait for response from PF
6566  * as none will be forthcoming. Immediately after calling this function,
6567  * the admin queue should be shut down and (optionally) reinitialized.
6568  **/
6569 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
6570 {
6571         return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
6572                                       I40E_SUCCESS, NULL, 0, NULL);
6573 }
6574 #endif /* VF_DRIVER */
6575 #ifdef X722_SUPPORT
6576
6577 /**
6578  * i40e_aq_set_arp_proxy_config
6579  * @hw: pointer to the HW structure
6580  * @proxy_config - pointer to proxy config command table struct
6581  * @cmd_details: pointer to command details
6582  *
6583  * Set ARP offload parameters from pre-populated
6584  * i40e_aqc_arp_proxy_data struct
6585  **/
6586 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
6587                                 struct i40e_aqc_arp_proxy_data *proxy_config,
6588                                 struct i40e_asq_cmd_details *cmd_details)
6589 {
6590         struct i40e_aq_desc desc;
6591         enum i40e_status_code status;
6592
6593         if (!proxy_config)
6594                 return I40E_ERR_PARAM;
6595
6596         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
6597
6598         desc.params.external.addr_high =
6599                                   CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
6600         desc.params.external.addr_low =
6601                                   CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
6602
6603         status = i40e_asq_send_command(hw, &desc, proxy_config,
6604                                        sizeof(struct i40e_aqc_arp_proxy_data),
6605                                        cmd_details);
6606
6607         return status;
6608 }
6609
6610 /**
6611  * i40e_aq_opc_set_ns_proxy_table_entry
6612  * @hw: pointer to the HW structure
6613  * @ns_proxy_table_entry: pointer to NS table entry command struct
6614  * @cmd_details: pointer to command details
6615  *
6616  * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
6617  * from pre-populated i40e_aqc_ns_proxy_data struct
6618  **/
6619 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
6620                         struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
6621                         struct i40e_asq_cmd_details *cmd_details)
6622 {
6623         struct i40e_aq_desc desc;
6624         enum i40e_status_code status;
6625
6626         if (!ns_proxy_table_entry)
6627                 return I40E_ERR_PARAM;
6628
6629         i40e_fill_default_direct_cmd_desc(&desc,
6630                                 i40e_aqc_opc_set_ns_proxy_table_entry);
6631
6632         desc.params.external.addr_high =
6633                 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
6634         desc.params.external.addr_low =
6635                 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
6636
6637         status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
6638                                        sizeof(struct i40e_aqc_ns_proxy_data),
6639                                        cmd_details);
6640
6641         return status;
6642 }
6643
6644 /**
6645  * i40e_aq_set_clear_wol_filter
6646  * @hw: pointer to the hw struct
6647  * @filter_index: index of filter to modify (0-7)
6648  * @filter: buffer containing filter to be set
6649  * @set_filter: true to set filter, false to clear filter
6650  * @no_wol_tco: if true, pass through packets cannot cause wake-up
6651  *              if false, pass through packets may cause wake-up
6652  * @filter_valid: true if filter action is valid
6653  * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
6654  * @cmd_details: pointer to command details structure or NULL
6655  *
6656  * Set or clear WoL filter for port attached to the PF
6657  **/
6658 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
6659                                 u8 filter_index,
6660                                 struct i40e_aqc_set_wol_filter_data *filter,
6661                                 bool set_filter, bool no_wol_tco,
6662                                 bool filter_valid, bool no_wol_tco_valid,
6663                                 struct i40e_asq_cmd_details *cmd_details)
6664 {
6665         struct i40e_aq_desc desc;
6666         struct i40e_aqc_set_wol_filter *cmd =
6667                 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
6668         enum i40e_status_code status;
6669         u16 cmd_flags = 0;
6670         u16 valid_flags = 0;
6671         u16 buff_len = 0;
6672
6673         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
6674
6675         if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
6676                 return  I40E_ERR_PARAM;
6677         cmd->filter_index = CPU_TO_LE16(filter_index);
6678
6679         if (set_filter) {
6680                 if (!filter)
6681                         return  I40E_ERR_PARAM;
6682                 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
6683                 buff_len = sizeof(*filter);
6684         }
6685         if (no_wol_tco)
6686                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
6687         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
6688
6689         if (filter_valid)
6690                 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
6691         if (no_wol_tco_valid)
6692                 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
6693         cmd->valid_flags = CPU_TO_LE16(valid_flags);
6694
6695         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
6696         cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
6697
6698         status = i40e_asq_send_command(hw, &desc, filter,
6699                                        buff_len, cmd_details);
6700
6701         return status;
6702 }
6703
6704 /**
6705  * i40e_aq_get_wake_event_reason
6706  * @hw: pointer to the hw struct
6707  * @wake_reason: return value, index of matching filter
6708  * @cmd_details: pointer to command details structure or NULL
6709  *
6710  * Get information for the reason of a Wake Up event
6711  **/
6712 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
6713                                 u16 *wake_reason,
6714                                 struct i40e_asq_cmd_details *cmd_details)
6715 {
6716         struct i40e_aq_desc desc;
6717         struct i40e_aqc_get_wake_reason_completion *resp =
6718                 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
6719         enum i40e_status_code status;
6720
6721         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
6722
6723         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6724
6725         if (status == I40E_SUCCESS)
6726                 *wake_reason = LE16_TO_CPU(resp->wake_reason);
6727
6728         return status;
6729 }
6730
6731 #endif /* X722_SUPPORT */