drivers/net/i40e/base/i40e_common.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001-2018
   3  */
   4
   5 #include "i40e_type.h"
   6 #include "i40e_adminq.h"
   7 #include "i40e_prototype.h"
   8 #include "virtchnl.h"
   9
  10 /**
  11  * i40e_set_mac_type - Sets MAC type
  12  * @hw: pointer to the HW structure
  13  *
  14  * This function sets the mac type of the adapter based on the
  15  * vendor ID and device ID stored in the hw structure.
  16  **/
  17 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  18 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  19 #else
  20 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  21 #endif
  22 {
  23         enum i40e_status_code status = I40E_SUCCESS;
  24
  25         DEBUGFUNC("i40e_set_mac_type\n");
  26
  27         if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
  28                 switch (hw->device_id) {
  29                 case I40E_DEV_ID_SFP_XL710:
  30                 case I40E_DEV_ID_QEMU:
  31                 case I40E_DEV_ID_KX_B:
  32                 case I40E_DEV_ID_KX_C:
  33                 case I40E_DEV_ID_QSFP_A:
  34                 case I40E_DEV_ID_QSFP_B:
  35                 case I40E_DEV_ID_QSFP_C:
  36                 case I40E_DEV_ID_10G_BASE_T:
  37                 case I40E_DEV_ID_10G_BASE_T4:
  38                 case I40E_DEV_ID_10G_BASE_T_BC:
  39                 case I40E_DEV_ID_20G_KR2:
  40                 case I40E_DEV_ID_20G_KR2_A:
  41                 case I40E_DEV_ID_25G_B:
  42                 case I40E_DEV_ID_25G_SFP28:
  43                 case I40E_DEV_ID_X710_N3000:
  44                 case I40E_DEV_ID_XXV710_N3000:
  45                         hw->mac.type = I40E_MAC_XL710;
  46                         break;
  47 #ifdef X722_A0_SUPPORT
  48                 case I40E_DEV_ID_X722_A0:
  49 #endif
  50                 case I40E_DEV_ID_KX_X722:
  51                 case I40E_DEV_ID_QSFP_X722:
  52                 case I40E_DEV_ID_SFP_X722:
  53                 case I40E_DEV_ID_1G_BASE_T_X722:
  54                 case I40E_DEV_ID_10G_BASE_T_X722:
  55                 case I40E_DEV_ID_SFP_I_X722:
  56                         hw->mac.type = I40E_MAC_X722;
  57                         break;
  58 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  59                 case I40E_DEV_ID_X722_VF:
  60 #ifdef X722_A0_SUPPORT
  61                 case I40E_DEV_ID_X722_A0_VF:
  62 #endif
  63                         hw->mac.type = I40E_MAC_X722_VF;
  64                         break;
  65 #endif /* INTEGRATED_VF || VF_DRIVER */
  66 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  67                 case I40E_DEV_ID_VF:
  68                 case I40E_DEV_ID_VF_HV:
  69                 case I40E_DEV_ID_ADAPTIVE_VF:
  70                         hw->mac.type = I40E_MAC_VF;
  71                         break;
  72 #endif
  73                 default:
  74                         hw->mac.type = I40E_MAC_GENERIC;
  75                         break;
  76                 }
  77         } else {
  78                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
  79         }
  80
  81         DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
  82                   hw->mac.type, status);
  83         return status;
  84 }
  85
  86 /**
  87  * i40e_aq_str - convert AQ err code to a string
  88  * @hw: pointer to the HW structure
  89  * @aq_err: the AQ error code to convert
  90  **/
  91 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
  92 {
  93         switch (aq_err) {
  94         case I40E_AQ_RC_OK:
  95                 return "OK";
  96         case I40E_AQ_RC_EPERM:
  97                 return "I40E_AQ_RC_EPERM";
  98         case I40E_AQ_RC_ENOENT:
  99                 return "I40E_AQ_RC_ENOENT";
 100         case I40E_AQ_RC_ESRCH:
 101                 return "I40E_AQ_RC_ESRCH";
 102         case I40E_AQ_RC_EINTR:
 103                 return "I40E_AQ_RC_EINTR";
 104         case I40E_AQ_RC_EIO:
 105                 return "I40E_AQ_RC_EIO";
 106         case I40E_AQ_RC_ENXIO:
 107                 return "I40E_AQ_RC_ENXIO";
 108         case I40E_AQ_RC_E2BIG:
 109                 return "I40E_AQ_RC_E2BIG";
 110         case I40E_AQ_RC_EAGAIN:
 111                 return "I40E_AQ_RC_EAGAIN";
 112         case I40E_AQ_RC_ENOMEM:
 113                 return "I40E_AQ_RC_ENOMEM";
 114         case I40E_AQ_RC_EACCES:
 115                 return "I40E_AQ_RC_EACCES";
 116         case I40E_AQ_RC_EFAULT:
 117                 return "I40E_AQ_RC_EFAULT";
 118         case I40E_AQ_RC_EBUSY:
 119                 return "I40E_AQ_RC_EBUSY";
 120         case I40E_AQ_RC_EEXIST:
 121                 return "I40E_AQ_RC_EEXIST";
 122         case I40E_AQ_RC_EINVAL:
 123                 return "I40E_AQ_RC_EINVAL";
 124         case I40E_AQ_RC_ENOTTY:
 125                 return "I40E_AQ_RC_ENOTTY";
 126         case I40E_AQ_RC_ENOSPC:
 127                 return "I40E_AQ_RC_ENOSPC";
 128         case I40E_AQ_RC_ENOSYS:
 129                 return "I40E_AQ_RC_ENOSYS";
 130         case I40E_AQ_RC_ERANGE:
 131                 return "I40E_AQ_RC_ERANGE";
 132         case I40E_AQ_RC_EFLUSHED:
 133                 return "I40E_AQ_RC_EFLUSHED";
 134         case I40E_AQ_RC_BAD_ADDR:
 135                 return "I40E_AQ_RC_BAD_ADDR";
 136         case I40E_AQ_RC_EMODE:
 137                 return "I40E_AQ_RC_EMODE";
 138         case I40E_AQ_RC_EFBIG:
 139                 return "I40E_AQ_RC_EFBIG";
 140         }
 141
 142         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 143         return hw->err_str;
 144 }
 145
 146 /**
 147  * i40e_stat_str - convert status err code to a string
 148  * @hw: pointer to the HW structure
 149  * @stat_err: the status error code to convert
 150  **/
 151 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
 152 {
 153         switch (stat_err) {
 154         case I40E_SUCCESS:
 155                 return "OK";
 156         case I40E_ERR_NVM:
 157                 return "I40E_ERR_NVM";
 158         case I40E_ERR_NVM_CHECKSUM:
 159                 return "I40E_ERR_NVM_CHECKSUM";
 160         case I40E_ERR_PHY:
 161                 return "I40E_ERR_PHY";
 162         case I40E_ERR_CONFIG:
 163                 return "I40E_ERR_CONFIG";
 164         case I40E_ERR_PARAM:
 165                 return "I40E_ERR_PARAM";
 166         case I40E_ERR_MAC_TYPE:
 167                 return "I40E_ERR_MAC_TYPE";
 168         case I40E_ERR_UNKNOWN_PHY:
 169                 return "I40E_ERR_UNKNOWN_PHY";
 170         case I40E_ERR_LINK_SETUP:
 171                 return "I40E_ERR_LINK_SETUP";
 172         case I40E_ERR_ADAPTER_STOPPED:
 173                 return "I40E_ERR_ADAPTER_STOPPED";
 174         case I40E_ERR_INVALID_MAC_ADDR:
 175                 return "I40E_ERR_INVALID_MAC_ADDR";
 176         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 177                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 178         case I40E_ERR_MASTER_REQUESTS_PENDING:
 179                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 180         case I40E_ERR_INVALID_LINK_SETTINGS:
 181                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 182         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 183                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 184         case I40E_ERR_RESET_FAILED:
 185                 return "I40E_ERR_RESET_FAILED";
 186         case I40E_ERR_SWFW_SYNC:
 187                 return "I40E_ERR_SWFW_SYNC";
 188         case I40E_ERR_NO_AVAILABLE_VSI:
 189                 return "I40E_ERR_NO_AVAILABLE_VSI";
 190         case I40E_ERR_NO_MEMORY:
 191                 return "I40E_ERR_NO_MEMORY";
 192         case I40E_ERR_BAD_PTR:
 193                 return "I40E_ERR_BAD_PTR";
 194         case I40E_ERR_RING_FULL:
 195                 return "I40E_ERR_RING_FULL";
 196         case I40E_ERR_INVALID_PD_ID:
 197                 return "I40E_ERR_INVALID_PD_ID";
 198         case I40E_ERR_INVALID_QP_ID:
 199                 return "I40E_ERR_INVALID_QP_ID";
 200         case I40E_ERR_INVALID_CQ_ID:
 201                 return "I40E_ERR_INVALID_CQ_ID";
 202         case I40E_ERR_INVALID_CEQ_ID:
 203                 return "I40E_ERR_INVALID_CEQ_ID";
 204         case I40E_ERR_INVALID_AEQ_ID:
 205                 return "I40E_ERR_INVALID_AEQ_ID";
 206         case I40E_ERR_INVALID_SIZE:
 207                 return "I40E_ERR_INVALID_SIZE";
 208         case I40E_ERR_INVALID_ARP_INDEX:
 209                 return "I40E_ERR_INVALID_ARP_INDEX";
 210         case I40E_ERR_INVALID_FPM_FUNC_ID:
 211                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 212         case I40E_ERR_QP_INVALID_MSG_SIZE:
 213                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 214         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 215                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 216         case I40E_ERR_INVALID_FRAG_COUNT:
 217                 return "I40E_ERR_INVALID_FRAG_COUNT";
 218         case I40E_ERR_QUEUE_EMPTY:
 219                 return "I40E_ERR_QUEUE_EMPTY";
 220         case I40E_ERR_INVALID_ALIGNMENT:
 221                 return "I40E_ERR_INVALID_ALIGNMENT";
 222         case I40E_ERR_FLUSHED_QUEUE:
 223                 return "I40E_ERR_FLUSHED_QUEUE";
 224         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 225                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 226         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 227                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 228         case I40E_ERR_TIMEOUT:
 229                 return "I40E_ERR_TIMEOUT";
 230         case I40E_ERR_OPCODE_MISMATCH:
 231                 return "I40E_ERR_OPCODE_MISMATCH";
 232         case I40E_ERR_CQP_COMPL_ERROR:
 233                 return "I40E_ERR_CQP_COMPL_ERROR";
 234         case I40E_ERR_INVALID_VF_ID:
 235                 return "I40E_ERR_INVALID_VF_ID";
 236         case I40E_ERR_INVALID_HMCFN_ID:
 237                 return "I40E_ERR_INVALID_HMCFN_ID";
 238         case I40E_ERR_BACKING_PAGE_ERROR:
 239                 return "I40E_ERR_BACKING_PAGE_ERROR";
 240         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 241                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 242         case I40E_ERR_INVALID_PBLE_INDEX:
 243                 return "I40E_ERR_INVALID_PBLE_INDEX";
 244         case I40E_ERR_INVALID_SD_INDEX:
 245                 return "I40E_ERR_INVALID_SD_INDEX";
 246         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 247                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 248         case I40E_ERR_INVALID_SD_TYPE:
 249                 return "I40E_ERR_INVALID_SD_TYPE";
 250         case I40E_ERR_MEMCPY_FAILED:
 251                 return "I40E_ERR_MEMCPY_FAILED";
 252         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 253                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 254         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 255                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 256         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 257                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 258         case I40E_ERR_SRQ_ENABLED:
 259                 return "I40E_ERR_SRQ_ENABLED";
 260         case I40E_ERR_ADMIN_QUEUE_ERROR:
 261                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 262         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 263                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 264         case I40E_ERR_BUF_TOO_SHORT:
 265                 return "I40E_ERR_BUF_TOO_SHORT";
 266         case I40E_ERR_ADMIN_QUEUE_FULL:
 267                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 268         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 269                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 270         case I40E_ERR_BAD_IWARP_CQE:
 271                 return "I40E_ERR_BAD_IWARP_CQE";
 272         case I40E_ERR_NVM_BLANK_MODE:
 273                 return "I40E_ERR_NVM_BLANK_MODE";
 274         case I40E_ERR_NOT_IMPLEMENTED:
 275                 return "I40E_ERR_NOT_IMPLEMENTED";
 276         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 277                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 278         case I40E_ERR_DIAG_TEST_FAILED:
 279                 return "I40E_ERR_DIAG_TEST_FAILED";
 280         case I40E_ERR_NOT_READY:
 281                 return "I40E_ERR_NOT_READY";
 282         case I40E_NOT_SUPPORTED:
 283                 return "I40E_NOT_SUPPORTED";
 284         case I40E_ERR_FIRMWARE_API_VERSION:
 285                 return "I40E_ERR_FIRMWARE_API_VERSION";
 286         case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR:
 287                 return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR";
 288         }
 289
 290         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 291         return hw->err_str;
 292 }
 293
 294 /**
 295  * i40e_debug_aq
 296  * @hw: debug mask related to admin queue
 297  * @mask: debug mask
 298  * @desc: pointer to admin queue descriptor
 299  * @buffer: pointer to command buffer
 300  * @buf_len: max length of buffer
 301  *
 302  * Dumps debug log about adminq command with descriptor contents.
 303  **/
 304 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 305                    void *buffer, u16 buf_len)
 306 {
 307         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 308         u8 *buf = (u8 *)buffer;
 309         u16 len;
 310         u16 i = 0;
 311
 312         if ((!(mask & hw->debug_mask)) || (desc == NULL))
 313                 return;
 314
 315         len = LE16_TO_CPU(aq_desc->datalen);
 316
 317         i40e_debug(hw, mask,
 318                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 319                    LE16_TO_CPU(aq_desc->opcode),
 320                    LE16_TO_CPU(aq_desc->flags),
 321                    LE16_TO_CPU(aq_desc->datalen),
 322                    LE16_TO_CPU(aq_desc->retval));
 323         i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
 324                    LE32_TO_CPU(aq_desc->cookie_high),
 325                    LE32_TO_CPU(aq_desc->cookie_low));
 326         i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
 327                    LE32_TO_CPU(aq_desc->params.internal.param0),
 328                    LE32_TO_CPU(aq_desc->params.internal.param1));
 329         i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
 330                    LE32_TO_CPU(aq_desc->params.external.addr_high),
 331                    LE32_TO_CPU(aq_desc->params.external.addr_low));
 332
 333         if ((buffer != NULL) && (aq_desc->datalen != 0)) {
 334                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 335                 if (buf_len < len)
 336                         len = buf_len;
 337                 /* write the full 16-byte chunks */
 338                 for (i = 0; i < (len - 16); i += 16)
 339                         i40e_debug(hw, mask,
 340                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 341                                    i, buf[i], buf[i+1], buf[i+2], buf[i+3],
 342                                    buf[i+4], buf[i+5], buf[i+6], buf[i+7],
 343                                    buf[i+8], buf[i+9], buf[i+10], buf[i+11],
 344                                    buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
 345                 /* the most we could have left is 16 bytes, pad with zeros */
 346                 if (i < len) {
 347                         char d_buf[16];
 348                         int j, i_sav;
 349
 350                         i_sav = i;
 351                         memset(d_buf, 0, sizeof(d_buf));
 352                         for (j = 0; i < len; j++, i++)
 353                                 d_buf[j] = buf[i];
 354                         i40e_debug(hw, mask,
 355                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 356                                    i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
 357                                    d_buf[4], d_buf[5], d_buf[6], d_buf[7],
 358                                    d_buf[8], d_buf[9], d_buf[10], d_buf[11],
 359                                    d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
 360                 }
 361         }
 362 }
 363
 364 /**
 365  * i40e_check_asq_alive
 366  * @hw: pointer to the hw struct
 367  *
 368  * Returns true if Queue is enabled else false.
 369  **/
 370 bool i40e_check_asq_alive(struct i40e_hw *hw)
 371 {
 372         if (hw->aq.asq.len)
 373 #ifdef PF_DRIVER
 374 #ifdef INTEGRATED_VF
 375                 if (!i40e_is_vf(hw))
 376                         return !!(rd32(hw, hw->aq.asq.len) &
 377                                 I40E_PF_ATQLEN_ATQENABLE_MASK);
 378 #else
 379                 return !!(rd32(hw, hw->aq.asq.len) &
 380                         I40E_PF_ATQLEN_ATQENABLE_MASK);
 381 #endif /* INTEGRATED_VF */
 382 #endif /* PF_DRIVER */
 383 #ifdef VF_DRIVER
 384 #ifdef INTEGRATED_VF
 385                 if (i40e_is_vf(hw))
 386                         return !!(rd32(hw, hw->aq.asq.len) &
 387                                 I40E_VF_ATQLEN1_ATQENABLE_MASK);
 388 #else
 389                 return !!(rd32(hw, hw->aq.asq.len) &
 390                         I40E_VF_ATQLEN1_ATQENABLE_MASK);
 391 #endif /* INTEGRATED_VF */
 392 #endif /* VF_DRIVER */
 393         return false;
 394 }
 395
 396 /**
 397  * i40e_aq_queue_shutdown
 398  * @hw: pointer to the hw struct
 399  * @unloading: is the driver unloading itself
 400  *
 401  * Tell the Firmware that we're shutting down the AdminQ and whether
 402  * or not the driver is unloading as well.
 403  **/
 404 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
 405                                              bool unloading)
 406 {
 407         struct i40e_aq_desc desc;
 408         struct i40e_aqc_queue_shutdown *cmd =
 409                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 410         enum i40e_status_code status;
 411
 412         i40e_fill_default_direct_cmd_desc(&desc,
 413                                           i40e_aqc_opc_queue_shutdown);
 414
 415         if (unloading)
 416                 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
 417         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 418
 419         return status;
 420 }
 421
 422 /**
 423  * i40e_aq_get_set_rss_lut
 424  * @hw: pointer to the hardware structure
 425  * @vsi_id: vsi fw index
 426  * @pf_lut: for PF table set true, for VSI table set false
 427  * @lut: pointer to the lut buffer provided by the caller
 428  * @lut_size: size of the lut buffer
 429  * @set: set true to set the table, false to get the table
 430  *
 431  * Internal function to get or set RSS look up table
 432  **/
 433 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 434                                                      u16 vsi_id, bool pf_lut,
 435                                                      u8 *lut, u16 lut_size,
 436                                                      bool set)
 437 {
 438         enum i40e_status_code status;
 439         struct i40e_aq_desc desc;
 440         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 441                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 442
 443         if (set)
 444                 i40e_fill_default_direct_cmd_desc(&desc,
 445                                                   i40e_aqc_opc_set_rss_lut);
 446         else
 447                 i40e_fill_default_direct_cmd_desc(&desc,
 448                                                   i40e_aqc_opc_get_rss_lut);
 449
 450         /* Indirect command */
 451         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 452         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 453
 454         cmd_resp->vsi_id =
 455                         CPU_TO_LE16((u16)((vsi_id <<
 456                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 457                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 458         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 459
 460         if (pf_lut)
 461                 cmd_resp->flags |= CPU_TO_LE16((u16)
 462                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 463                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 464                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 465         else
 466                 cmd_resp->flags |= CPU_TO_LE16((u16)
 467                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 468                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 469                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 470
 471         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 472
 473         return status;
 474 }
 475
 476 /**
 477  * i40e_aq_get_rss_lut
 478  * @hw: pointer to the hardware structure
 479  * @vsi_id: vsi fw index
 480  * @pf_lut: for PF table set true, for VSI table set false
 481  * @lut: pointer to the lut buffer provided by the caller
 482  * @lut_size: size of the lut buffer
 483  *
 484  * get the RSS lookup table, PF or VSI type
 485  **/
 486 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 487                                           bool pf_lut, u8 *lut, u16 lut_size)
 488 {
 489         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 490                                        false);
 491 }
 492
 493 /**
 494  * i40e_aq_set_rss_lut
 495  * @hw: pointer to the hardware structure
 496  * @vsi_id: vsi fw index
 497  * @pf_lut: for PF table set true, for VSI table set false
 498  * @lut: pointer to the lut buffer provided by the caller
 499  * @lut_size: size of the lut buffer
 500  *
 501  * set the RSS lookup table, PF or VSI type
 502  **/
 503 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 504                                           bool pf_lut, u8 *lut, u16 lut_size)
 505 {
 506         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
 507 }
 508
 509 /**
 510  * i40e_aq_get_set_rss_key
 511  * @hw: pointer to the hw struct
 512  * @vsi_id: vsi fw index
 513  * @key: pointer to key info struct
 514  * @set: set true to set the key, false to get the key
 515  *
 516  * get the RSS key per VSI
 517  **/
 518 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 519                                       u16 vsi_id,
 520                                       struct i40e_aqc_get_set_rss_key_data *key,
 521                                       bool set)
 522 {
 523         enum i40e_status_code status;
 524         struct i40e_aq_desc desc;
 525         struct i40e_aqc_get_set_rss_key *cmd_resp =
 526                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 527         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 528
 529         if (set)
 530                 i40e_fill_default_direct_cmd_desc(&desc,
 531                                                   i40e_aqc_opc_set_rss_key);
 532         else
 533                 i40e_fill_default_direct_cmd_desc(&desc,
 534                                                   i40e_aqc_opc_get_rss_key);
 535
 536         /* Indirect command */
 537         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 538         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 539
 540         cmd_resp->vsi_id =
 541                         CPU_TO_LE16((u16)((vsi_id <<
 542                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 543                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 544         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 545
 546         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 547
 548         return status;
 549 }
 550
 551 /**
 552  * i40e_aq_get_rss_key
 553  * @hw: pointer to the hw struct
 554  * @vsi_id: vsi fw index
 555  * @key: pointer to key info struct
 556  *
 557  **/
 558 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
 559                                       u16 vsi_id,
 560                                       struct i40e_aqc_get_set_rss_key_data *key)
 561 {
 562         return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
 563 }
 564
 565 /**
 566  * i40e_aq_set_rss_key
 567  * @hw: pointer to the hw struct
 568  * @vsi_id: vsi fw index
 569  * @key: pointer to key info struct
 570  *
 571  * set the RSS key per VSI
 572  **/
 573 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
 574                                       u16 vsi_id,
 575                                       struct i40e_aqc_get_set_rss_key_data *key)
 576 {
 577         return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
 578 }
 579
 580 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 581  * hardware to a bit-field that can be used by SW to more easily determine the
 582  * packet type.
 583  *
 584  * Macros are used to shorten the table lines and make this table human
 585  * readable.
 586  *
 587  * We store the PTYPE in the top byte of the bit field - this is just so that
 588  * we can check that the table doesn't have a row missing, as the index into
 589  * the table should be the PTYPE.
 590  *
 591  * Typical work flow:
 592  *
 593  * IF NOT i40e_ptype_lookup[ptype].known
 594  * THEN
 595  *      Packet is unknown
 596  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 597  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 598  * ELSE
 599  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 600  * ENDIF
 601  */
 602
 603 /* macro to make the table lines short */
 604 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 605         {       PTYPE, \
 606                 1, \
 607                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 608                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 609                 I40E_RX_PTYPE_##OUTER_FRAG, \
 610                 I40E_RX_PTYPE_TUNNEL_##T, \
 611                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 612                 I40E_RX_PTYPE_##TEF, \
 613                 I40E_RX_PTYPE_INNER_PROT_##I, \
 614                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 615
 616 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 617                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 618
 619 /* shorter macros makes the table fit but are terse */
 620 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 621 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 622 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 623
 624 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 625 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 626         /* L2 Packet types */
 627         I40E_PTT_UNUSED_ENTRY(0),
 628         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 629         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 630         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 631         I40E_PTT_UNUSED_ENTRY(4),
 632         I40E_PTT_UNUSED_ENTRY(5),
 633         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 634         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 635         I40E_PTT_UNUSED_ENTRY(8),
 636         I40E_PTT_UNUSED_ENTRY(9),
 637         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 638         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 639         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 640         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 641         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 642         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 643         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 644         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 645         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 646         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 647         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 648         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 649
 650         /* Non Tunneled IPv4 */
 651         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 652         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 653         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 654         I40E_PTT_UNUSED_ENTRY(25),
 655         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 656         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 657         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 658
 659         /* IPv4 --> IPv4 */
 660         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 661         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 662         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 663         I40E_PTT_UNUSED_ENTRY(32),
 664         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 665         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 666         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 667
 668         /* IPv4 --> IPv6 */
 669         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 670         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 671         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 672         I40E_PTT_UNUSED_ENTRY(39),
 673         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 674         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 675         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 676
 677         /* IPv4 --> GRE/NAT */
 678         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 679
 680         /* IPv4 --> GRE/NAT --> IPv4 */
 681         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 682         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 683         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 684         I40E_PTT_UNUSED_ENTRY(47),
 685         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 686         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 687         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 688
 689         /* IPv4 --> GRE/NAT --> IPv6 */
 690         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 691         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 692         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 693         I40E_PTT_UNUSED_ENTRY(54),
 694         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 695         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 696         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 697
 698         /* IPv4 --> GRE/NAT --> MAC */
 699         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 700
 701         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 702         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 703         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 704         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 705         I40E_PTT_UNUSED_ENTRY(62),
 706         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 707         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 708         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 709
 710         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 711         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 712         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 713         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 714         I40E_PTT_UNUSED_ENTRY(69),
 715         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 716         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 717         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 718
 719         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 720         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 721
 722         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 723         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 724         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 725         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 726         I40E_PTT_UNUSED_ENTRY(77),
 727         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 728         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 729         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 730
 731         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 732         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 733         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 734         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 735         I40E_PTT_UNUSED_ENTRY(84),
 736         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 737         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 738         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 739
 740         /* Non Tunneled IPv6 */
 741         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 742         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 743         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
 744         I40E_PTT_UNUSED_ENTRY(91),
 745         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 746         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 747         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 748
 749         /* IPv6 --> IPv4 */
 750         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 751         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 752         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 753         I40E_PTT_UNUSED_ENTRY(98),
 754         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 755         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 756         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 757
 758         /* IPv6 --> IPv6 */
 759         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 760         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 761         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 762         I40E_PTT_UNUSED_ENTRY(105),
 763         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 764         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 765         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 766
 767         /* IPv6 --> GRE/NAT */
 768         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 769
 770         /* IPv6 --> GRE/NAT -> IPv4 */
 771         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 772         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 773         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 774         I40E_PTT_UNUSED_ENTRY(113),
 775         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 776         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 777         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 778
 779         /* IPv6 --> GRE/NAT -> IPv6 */
 780         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 781         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 782         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 783         I40E_PTT_UNUSED_ENTRY(120),
 784         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 785         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 786         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 787
 788         /* IPv6 --> GRE/NAT -> MAC */
 789         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 790
 791         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 792         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 793         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 794         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 795         I40E_PTT_UNUSED_ENTRY(128),
 796         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 797         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 798         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 799
 800         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 801         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 802         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 803         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 804         I40E_PTT_UNUSED_ENTRY(135),
 805         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 806         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 807         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 808
 809         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 810         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 811
 812         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 813         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 814         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 815         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 816         I40E_PTT_UNUSED_ENTRY(143),
 817         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 818         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 819         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 820
 821         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 822         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 823         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 824         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 825         I40E_PTT_UNUSED_ENTRY(150),
 826         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 827         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 828         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 829
 830         /* unused entries */
 831         I40E_PTT_UNUSED_ENTRY(154),
 832         I40E_PTT_UNUSED_ENTRY(155),
 833         I40E_PTT_UNUSED_ENTRY(156),
 834         I40E_PTT_UNUSED_ENTRY(157),
 835         I40E_PTT_UNUSED_ENTRY(158),
 836         I40E_PTT_UNUSED_ENTRY(159),
 837
 838         I40E_PTT_UNUSED_ENTRY(160),
 839         I40E_PTT_UNUSED_ENTRY(161),
 840         I40E_PTT_UNUSED_ENTRY(162),
 841         I40E_PTT_UNUSED_ENTRY(163),
 842         I40E_PTT_UNUSED_ENTRY(164),
 843         I40E_PTT_UNUSED_ENTRY(165),
 844         I40E_PTT_UNUSED_ENTRY(166),
 845         I40E_PTT_UNUSED_ENTRY(167),
 846         I40E_PTT_UNUSED_ENTRY(168),
 847         I40E_PTT_UNUSED_ENTRY(169),
 848
 849         I40E_PTT_UNUSED_ENTRY(170),
 850         I40E_PTT_UNUSED_ENTRY(171),
 851         I40E_PTT_UNUSED_ENTRY(172),
 852         I40E_PTT_UNUSED_ENTRY(173),
 853         I40E_PTT_UNUSED_ENTRY(174),
 854         I40E_PTT_UNUSED_ENTRY(175),
 855         I40E_PTT_UNUSED_ENTRY(176),
 856         I40E_PTT_UNUSED_ENTRY(177),
 857         I40E_PTT_UNUSED_ENTRY(178),
 858         I40E_PTT_UNUSED_ENTRY(179),
 859
 860         I40E_PTT_UNUSED_ENTRY(180),
 861         I40E_PTT_UNUSED_ENTRY(181),
 862         I40E_PTT_UNUSED_ENTRY(182),
 863         I40E_PTT_UNUSED_ENTRY(183),
 864         I40E_PTT_UNUSED_ENTRY(184),
 865         I40E_PTT_UNUSED_ENTRY(185),
 866         I40E_PTT_UNUSED_ENTRY(186),
 867         I40E_PTT_UNUSED_ENTRY(187),
 868         I40E_PTT_UNUSED_ENTRY(188),
 869         I40E_PTT_UNUSED_ENTRY(189),
 870
 871         I40E_PTT_UNUSED_ENTRY(190),
 872         I40E_PTT_UNUSED_ENTRY(191),
 873         I40E_PTT_UNUSED_ENTRY(192),
 874         I40E_PTT_UNUSED_ENTRY(193),
 875         I40E_PTT_UNUSED_ENTRY(194),
 876         I40E_PTT_UNUSED_ENTRY(195),
 877         I40E_PTT_UNUSED_ENTRY(196),
 878         I40E_PTT_UNUSED_ENTRY(197),
 879         I40E_PTT_UNUSED_ENTRY(198),
 880         I40E_PTT_UNUSED_ENTRY(199),
 881
 882         I40E_PTT_UNUSED_ENTRY(200),
 883         I40E_PTT_UNUSED_ENTRY(201),
 884         I40E_PTT_UNUSED_ENTRY(202),
 885         I40E_PTT_UNUSED_ENTRY(203),
 886         I40E_PTT_UNUSED_ENTRY(204),
 887         I40E_PTT_UNUSED_ENTRY(205),
 888         I40E_PTT_UNUSED_ENTRY(206),
 889         I40E_PTT_UNUSED_ENTRY(207),
 890         I40E_PTT_UNUSED_ENTRY(208),
 891         I40E_PTT_UNUSED_ENTRY(209),
 892
 893         I40E_PTT_UNUSED_ENTRY(210),
 894         I40E_PTT_UNUSED_ENTRY(211),
 895         I40E_PTT_UNUSED_ENTRY(212),
 896         I40E_PTT_UNUSED_ENTRY(213),
 897         I40E_PTT_UNUSED_ENTRY(214),
 898         I40E_PTT_UNUSED_ENTRY(215),
 899         I40E_PTT_UNUSED_ENTRY(216),
 900         I40E_PTT_UNUSED_ENTRY(217),
 901         I40E_PTT_UNUSED_ENTRY(218),
 902         I40E_PTT_UNUSED_ENTRY(219),
 903
 904         I40E_PTT_UNUSED_ENTRY(220),
 905         I40E_PTT_UNUSED_ENTRY(221),
 906         I40E_PTT_UNUSED_ENTRY(222),
 907         I40E_PTT_UNUSED_ENTRY(223),
 908         I40E_PTT_UNUSED_ENTRY(224),
 909         I40E_PTT_UNUSED_ENTRY(225),
 910         I40E_PTT_UNUSED_ENTRY(226),
 911         I40E_PTT_UNUSED_ENTRY(227),
 912         I40E_PTT_UNUSED_ENTRY(228),
 913         I40E_PTT_UNUSED_ENTRY(229),
 914
 915         I40E_PTT_UNUSED_ENTRY(230),
 916         I40E_PTT_UNUSED_ENTRY(231),
 917         I40E_PTT_UNUSED_ENTRY(232),
 918         I40E_PTT_UNUSED_ENTRY(233),
 919         I40E_PTT_UNUSED_ENTRY(234),
 920         I40E_PTT_UNUSED_ENTRY(235),
 921         I40E_PTT_UNUSED_ENTRY(236),
 922         I40E_PTT_UNUSED_ENTRY(237),
 923         I40E_PTT_UNUSED_ENTRY(238),
 924         I40E_PTT_UNUSED_ENTRY(239),
 925
 926         I40E_PTT_UNUSED_ENTRY(240),
 927         I40E_PTT_UNUSED_ENTRY(241),
 928         I40E_PTT_UNUSED_ENTRY(242),
 929         I40E_PTT_UNUSED_ENTRY(243),
 930         I40E_PTT_UNUSED_ENTRY(244),
 931         I40E_PTT_UNUSED_ENTRY(245),
 932         I40E_PTT_UNUSED_ENTRY(246),
 933         I40E_PTT_UNUSED_ENTRY(247),
 934         I40E_PTT_UNUSED_ENTRY(248),
 935         I40E_PTT_UNUSED_ENTRY(249),
 936
 937         I40E_PTT_UNUSED_ENTRY(250),
 938         I40E_PTT_UNUSED_ENTRY(251),
 939         I40E_PTT_UNUSED_ENTRY(252),
 940         I40E_PTT_UNUSED_ENTRY(253),
 941         I40E_PTT_UNUSED_ENTRY(254),
 942         I40E_PTT_UNUSED_ENTRY(255)
 943 };
 944
 945
 946 /**
 947  * i40e_validate_mac_addr - Validate unicast MAC address
 948  * @mac_addr: pointer to MAC address
 949  *
 950  * Tests a MAC address to ensure it is a valid Individual Address
 951  **/
 952 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
 953 {
 954         enum i40e_status_code status = I40E_SUCCESS;
 955
 956         DEBUGFUNC("i40e_validate_mac_addr");
 957
 958         /* Broadcast addresses ARE multicast addresses
 959          * Make sure it is not a multicast address
 960          * Reject the zero address
 961          */
 962         if (I40E_IS_MULTICAST(mac_addr) ||
 963             (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
 964               mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
 965                 status = I40E_ERR_INVALID_MAC_ADDR;
 966
 967         return status;
 968 }
 969 #ifdef PF_DRIVER
 970
 971 /**
 972  * i40e_init_shared_code - Initialize the shared code
 973  * @hw: pointer to hardware structure
 974  *
 975  * This assigns the MAC type and PHY code and inits the NVM.
 976  * Does not touch the hardware. This function must be called prior to any
 977  * other function in the shared code. The i40e_hw structure should be
 978  * memset to 0 prior to calling this function.  The following fields in
 979  * hw structure should be filled in prior to calling this function:
 980  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
 981  * subsystem_vendor_id, and revision_id
 982  **/
 983 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
 984 {
 985         enum i40e_status_code status = I40E_SUCCESS;
 986         u32 port, ari, func_rid;
 987
 988         DEBUGFUNC("i40e_init_shared_code");
 989
 990         i40e_set_mac_type(hw);
 991
 992         switch (hw->mac.type) {
 993         case I40E_MAC_XL710:
 994         case I40E_MAC_X722:
 995                 break;
 996         default:
 997                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
 998         }
 999
1000         hw->phy.get_link_info = true;
1001
1002         /* Determine port number and PF number*/
1003         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1004                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1005         hw->port = (u8)port;
1006         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1007                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1008         func_rid = rd32(hw, I40E_PF_FUNC_RID);
1009         if (ari)
1010                 hw->pf_id = (u8)(func_rid & 0xff);
1011         else
1012                 hw->pf_id = (u8)(func_rid & 0x7);
1013
1014         if (hw->mac.type == I40E_MAC_X722)
1015                 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE |
1016                              I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK;
1017         /* NVMUpdate features structure initialization */
1018         hw->nvmupd_features.major = I40E_NVMUPD_FEATURES_API_VER_MAJOR;
1019         hw->nvmupd_features.minor = I40E_NVMUPD_FEATURES_API_VER_MINOR;
1020         hw->nvmupd_features.size = sizeof(hw->nvmupd_features);
1021         i40e_memset(hw->nvmupd_features.features, 0x0,
1022                     I40E_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN *
1023                     sizeof(*hw->nvmupd_features.features),
1024                     I40E_NONDMA_MEM);
1025
1026         /* No features supported at the moment */
1027         hw->nvmupd_features.features[0] = 0;
1028
1029         status = i40e_init_nvm(hw);
1030         return status;
1031 }
1032
1033 /**
1034  * i40e_aq_mac_address_read - Retrieve the MAC addresses
1035  * @hw: pointer to the hw struct
1036  * @flags: a return indicator of what addresses were added to the addr store
1037  * @addrs: the requestor's mac addr store
1038  * @cmd_details: pointer to command details structure or NULL
1039  **/
1040 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1041                                    u16 *flags,
1042                                    struct i40e_aqc_mac_address_read_data *addrs,
1043                                    struct i40e_asq_cmd_details *cmd_details)
1044 {
1045         struct i40e_aq_desc desc;
1046         struct i40e_aqc_mac_address_read *cmd_data =
1047                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1048         enum i40e_status_code status;
1049
1050         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1051         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1052
1053         status = i40e_asq_send_command(hw, &desc, addrs,
1054                                        sizeof(*addrs), cmd_details);
1055         *flags = LE16_TO_CPU(cmd_data->command_flags);
1056
1057         return status;
1058 }
1059
1060 /**
1061  * i40e_aq_mac_address_write - Change the MAC addresses
1062  * @hw: pointer to the hw struct
1063  * @flags: indicates which MAC to be written
1064  * @mac_addr: address to write
1065  * @cmd_details: pointer to command details structure or NULL
1066  **/
1067 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1068                                     u16 flags, u8 *mac_addr,
1069                                     struct i40e_asq_cmd_details *cmd_details)
1070 {
1071         struct i40e_aq_desc desc;
1072         struct i40e_aqc_mac_address_write *cmd_data =
1073                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1074         enum i40e_status_code status;
1075
1076         i40e_fill_default_direct_cmd_desc(&desc,
1077                                           i40e_aqc_opc_mac_address_write);
1078         cmd_data->command_flags = CPU_TO_LE16(flags);
1079         cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1080         cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1081                                         ((u32)mac_addr[3] << 16) |
1082                                         ((u32)mac_addr[4] << 8) |
1083                                         mac_addr[5]);
1084
1085         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1086
1087         return status;
1088 }
1089
1090 /**
1091  * i40e_get_mac_addr - get MAC address
1092  * @hw: pointer to the HW structure
1093  * @mac_addr: pointer to MAC address
1094  *
1095  * Reads the adapter's MAC address from register
1096  **/
1097 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1098 {
1099         struct i40e_aqc_mac_address_read_data addrs;
1100         enum i40e_status_code status;
1101         u16 flags = 0;
1102
1103         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1104
1105         if (flags & I40E_AQC_LAN_ADDR_VALID)
1106                 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1107                         I40E_NONDMA_TO_NONDMA);
1108
1109         return status;
1110 }
1111
1112 /**
1113  * i40e_get_port_mac_addr - get Port MAC address
1114  * @hw: pointer to the HW structure
1115  * @mac_addr: pointer to Port MAC address
1116  *
1117  * Reads the adapter's Port MAC address
1118  **/
1119 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1120 {
1121         struct i40e_aqc_mac_address_read_data addrs;
1122         enum i40e_status_code status;
1123         u16 flags = 0;
1124
1125         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1126         if (status)
1127                 return status;
1128
1129         if (flags & I40E_AQC_PORT_ADDR_VALID)
1130                 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1131                         I40E_NONDMA_TO_NONDMA);
1132         else
1133                 status = I40E_ERR_INVALID_MAC_ADDR;
1134
1135         return status;
1136 }
1137
1138 /**
1139  * i40e_pre_tx_queue_cfg - pre tx queue configure
1140  * @hw: pointer to the HW structure
1141  * @queue: target pf queue index
1142  * @enable: state change request
1143  *
1144  * Handles hw requirement to indicate intention to enable
1145  * or disable target queue.
1146  **/
1147 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1148 {
1149         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1150         u32 reg_block = 0;
1151         u32 reg_val;
1152
1153         if (abs_queue_idx >= 128) {
1154                 reg_block = abs_queue_idx / 128;
1155                 abs_queue_idx %= 128;
1156         }
1157
1158         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1159         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1160         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1161
1162         if (enable)
1163                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1164         else
1165                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1166
1167         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1168 }
1169
1170 /**
1171  * i40e_get_san_mac_addr - get SAN MAC address
1172  * @hw: pointer to the HW structure
1173  * @mac_addr: pointer to SAN MAC address
1174  *
1175  * Reads the adapter's SAN MAC address from NVM
1176  **/
1177 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1178                                             u8 *mac_addr)
1179 {
1180         struct i40e_aqc_mac_address_read_data addrs;
1181         enum i40e_status_code status;
1182         u16 flags = 0;
1183
1184         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1185         if (status)
1186                 return status;
1187
1188         if (flags & I40E_AQC_SAN_ADDR_VALID)
1189                 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac),
1190                         I40E_NONDMA_TO_NONDMA);
1191         else
1192                 status = I40E_ERR_INVALID_MAC_ADDR;
1193
1194         return status;
1195 }
1196
1197 /**
1198  *  i40e_read_pba_string - Reads part number string from EEPROM
1199  *  @hw: pointer to hardware structure
1200  *  @pba_num: stores the part number string from the EEPROM
1201  *  @pba_num_size: part number string buffer length
1202  *
1203  *  Reads the part number string from the EEPROM.
1204  **/
1205 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1206                                             u32 pba_num_size)
1207 {
1208         enum i40e_status_code status = I40E_SUCCESS;
1209         u16 pba_word = 0;
1210         u16 pba_size = 0;
1211         u16 pba_ptr = 0;
1212         u16 i = 0;
1213
1214         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1215         if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1216                 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1217                 return status;
1218         }
1219
1220         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1221         if (status != I40E_SUCCESS) {
1222                 DEBUGOUT("Failed to read PBA Block pointer.\n");
1223                 return status;
1224         }
1225
1226         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1227         if (status != I40E_SUCCESS) {
1228                 DEBUGOUT("Failed to read PBA Block size.\n");
1229                 return status;
1230         }
1231
1232         /* Subtract one to get PBA word count (PBA Size word is included in
1233          * total size)
1234          */
1235         pba_size--;
1236         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1237                 DEBUGOUT("Buffer to small for PBA data.\n");
1238                 return I40E_ERR_PARAM;
1239         }
1240
1241         for (i = 0; i < pba_size; i++) {
1242                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1243                 if (status != I40E_SUCCESS) {
1244                         DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1245                         return status;
1246                 }
1247
1248                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1249                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1250         }
1251         pba_num[(pba_size * 2)] = '\0';
1252
1253         return status;
1254 }
1255
1256 /**
1257  * i40e_get_media_type - Gets media type
1258  * @hw: pointer to the hardware structure
1259  **/
1260 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1261 {
1262         enum i40e_media_type media;
1263
1264         switch (hw->phy.link_info.phy_type) {
1265         case I40E_PHY_TYPE_10GBASE_SR:
1266         case I40E_PHY_TYPE_10GBASE_LR:
1267         case I40E_PHY_TYPE_1000BASE_SX:
1268         case I40E_PHY_TYPE_1000BASE_LX:
1269         case I40E_PHY_TYPE_40GBASE_SR4:
1270         case I40E_PHY_TYPE_40GBASE_LR4:
1271         case I40E_PHY_TYPE_25GBASE_LR:
1272         case I40E_PHY_TYPE_25GBASE_SR:
1273                 media = I40E_MEDIA_TYPE_FIBER;
1274                 break;
1275         case I40E_PHY_TYPE_100BASE_TX:
1276         case I40E_PHY_TYPE_1000BASE_T:
1277         case I40E_PHY_TYPE_2_5GBASE_T:
1278         case I40E_PHY_TYPE_5GBASE_T:
1279         case I40E_PHY_TYPE_10GBASE_T:
1280                 media = I40E_MEDIA_TYPE_BASET;
1281                 break;
1282         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1283         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1284         case I40E_PHY_TYPE_10GBASE_CR1:
1285         case I40E_PHY_TYPE_40GBASE_CR4:
1286         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1287         case I40E_PHY_TYPE_40GBASE_AOC:
1288         case I40E_PHY_TYPE_10GBASE_AOC:
1289         case I40E_PHY_TYPE_25GBASE_CR:
1290         case I40E_PHY_TYPE_25GBASE_AOC:
1291         case I40E_PHY_TYPE_25GBASE_ACC:
1292                 media = I40E_MEDIA_TYPE_DA;
1293                 break;
1294         case I40E_PHY_TYPE_1000BASE_KX:
1295         case I40E_PHY_TYPE_10GBASE_KX4:
1296         case I40E_PHY_TYPE_10GBASE_KR:
1297         case I40E_PHY_TYPE_40GBASE_KR4:
1298         case I40E_PHY_TYPE_20GBASE_KR2:
1299         case I40E_PHY_TYPE_25GBASE_KR:
1300                 media = I40E_MEDIA_TYPE_BACKPLANE;
1301                 break;
1302         case I40E_PHY_TYPE_SGMII:
1303         case I40E_PHY_TYPE_XAUI:
1304         case I40E_PHY_TYPE_XFI:
1305         case I40E_PHY_TYPE_XLAUI:
1306         case I40E_PHY_TYPE_XLPPI:
1307         default:
1308                 media = I40E_MEDIA_TYPE_UNKNOWN;
1309                 break;
1310         }
1311
1312         return media;
1313 }
1314
1315 /**
1316  * i40e_poll_globr - Poll for Global Reset completion
1317  * @hw: pointer to the hardware structure
1318  * @retry_limit: how many times to retry before failure
1319  **/
1320 STATIC enum i40e_status_code i40e_poll_globr(struct i40e_hw *hw,
1321                                              u32 retry_limit)
1322 {
1323         u32 cnt, reg = 0;
1324
1325         for (cnt = 0; cnt < retry_limit; cnt++) {
1326                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1327                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1328                         return I40E_SUCCESS;
1329                 i40e_msec_delay(100);
1330         }
1331
1332         DEBUGOUT("Global reset failed.\n");
1333         DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg);
1334
1335         return I40E_ERR_RESET_FAILED;
1336 }
1337
1338 #define I40E_PF_RESET_WAIT_COUNT        200
1339 /**
1340  * i40e_pf_reset - Reset the PF
1341  * @hw: pointer to the hardware structure
1342  *
1343  * Assuming someone else has triggered a global reset,
1344  * assure the global reset is complete and then reset the PF
1345  **/
1346 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1347 {
1348         u32 cnt = 0;
1349         u32 cnt1 = 0;
1350         u32 reg = 0;
1351         u32 grst_del;
1352
1353         /* Poll for Global Reset steady state in case of recent GRST.
1354          * The grst delay value is in 100ms units, and we'll wait a
1355          * couple counts longer to be sure we don't just miss the end.
1356          */
1357         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1358                         I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1359                         I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1360
1361         grst_del = min(grst_del * 20, 160U);
1362
1363         for (cnt = 0; cnt < grst_del; cnt++) {
1364                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1365                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1366                         break;
1367                 i40e_msec_delay(100);
1368         }
1369         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1370                 DEBUGOUT("Global reset polling failed to complete.\n");
1371                 return I40E_ERR_RESET_FAILED;
1372         }
1373
1374         /* Now Wait for the FW to be ready */
1375         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1376                 reg = rd32(hw, I40E_GLNVM_ULD);
1377                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1378                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1379                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1380                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1381                         DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1382                         break;
1383                 }
1384                 i40e_msec_delay(10);
1385         }
1386         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1387                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1388                 DEBUGOUT("wait for FW Reset complete timedout\n");
1389                 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1390                 return I40E_ERR_RESET_FAILED;
1391         }
1392
1393         /* If there was a Global Reset in progress when we got here,
1394          * we don't need to do the PF Reset
1395          */
1396         if (!cnt) {
1397                 u32 reg2 = 0;
1398
1399                 reg = rd32(hw, I40E_PFGEN_CTRL);
1400                 wr32(hw, I40E_PFGEN_CTRL,
1401                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1402                 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1403                         reg = rd32(hw, I40E_PFGEN_CTRL);
1404                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1405                                 break;
1406                         reg2 = rd32(hw, I40E_GLGEN_RSTAT);
1407                         if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK)
1408                                 break;
1409                         i40e_msec_delay(1);
1410                 }
1411                 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1412                         if (i40e_poll_globr(hw, grst_del) != I40E_SUCCESS)
1413                                 return I40E_ERR_RESET_FAILED;
1414                 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1415                         DEBUGOUT("PF reset polling failed to complete.\n");
1416                         return I40E_ERR_RESET_FAILED;
1417                 }
1418         }
1419
1420         i40e_clear_pxe_mode(hw);
1421
1422
1423         return I40E_SUCCESS;
1424 }
1425
1426 /**
1427  * i40e_clear_hw - clear out any left over hw state
1428  * @hw: pointer to the hw struct
1429  *
1430  * Clear queues and interrupts, typically called at init time,
1431  * but after the capabilities have been found so we know how many
1432  * queues and msix vectors have been allocated.
1433  **/
1434 void i40e_clear_hw(struct i40e_hw *hw)
1435 {
1436         u32 num_queues, base_queue;
1437         u32 num_pf_int;
1438         u32 num_vf_int;
1439         u32 num_vfs;
1440         u32 i, j;
1441         u32 val;
1442         u32 eol = 0x7ff;
1443
1444         /* get number of interrupts, queues, and vfs */
1445         val = rd32(hw, I40E_GLPCI_CNF2);
1446         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1447                         I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1448         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1449                         I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1450
1451         val = rd32(hw, I40E_PFLAN_QALLOC);
1452         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1453                         I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1454         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1455                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1456         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1457                 num_queues = (j - base_queue) + 1;
1458         else
1459                 num_queues = 0;
1460
1461         val = rd32(hw, I40E_PF_VT_PFALLOC);
1462         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1463                         I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1464         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1465                         I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1466         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1467                 num_vfs = (j - i) + 1;
1468         else
1469                 num_vfs = 0;
1470
1471         /* stop all the interrupts */
1472         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1473         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1474         for (i = 0; i < num_pf_int - 2; i++)
1475                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1476
1477         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1478         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1479         wr32(hw, I40E_PFINT_LNKLST0, val);
1480         for (i = 0; i < num_pf_int - 2; i++)
1481                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1482         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1483         for (i = 0; i < num_vfs; i++)
1484                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1485         for (i = 0; i < num_vf_int - 2; i++)
1486                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1487
1488         /* warn the HW of the coming Tx disables */
1489         for (i = 0; i < num_queues; i++) {
1490                 u32 abs_queue_idx = base_queue + i;
1491                 u32 reg_block = 0;
1492
1493                 if (abs_queue_idx >= 128) {
1494                         reg_block = abs_queue_idx / 128;
1495                         abs_queue_idx %= 128;
1496                 }
1497
1498                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1499                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1500                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1501                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1502
1503                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1504         }
1505         i40e_usec_delay(400);
1506
1507         /* stop all the queues */
1508         for (i = 0; i < num_queues; i++) {
1509                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1510                 wr32(hw, I40E_QTX_ENA(i), 0);
1511                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1512                 wr32(hw, I40E_QRX_ENA(i), 0);
1513         }
1514
1515         /* short wait for all queue disables to settle */
1516         i40e_usec_delay(50);
1517 }
1518
1519 /**
1520  * i40e_clear_pxe_mode - clear pxe operations mode
1521  * @hw: pointer to the hw struct
1522  *
1523  * Make sure all PXE mode settings are cleared, including things
1524  * like descriptor fetch/write-back mode.
1525  **/
1526 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1527 {
1528         if (i40e_check_asq_alive(hw))
1529                 i40e_aq_clear_pxe_mode(hw, NULL);
1530 }
1531
1532 /**
1533  * i40e_led_is_mine - helper to find matching led
1534  * @hw: pointer to the hw struct
1535  * @idx: index into GPIO registers
1536  *
1537  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1538  */
1539 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1540 {
1541         u32 gpio_val = 0;
1542         u32 port;
1543
1544         if (!hw->func_caps.led[idx])
1545                 return 0;
1546
1547         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1548         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1549                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1550
1551         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1552          * if it is not our port then ignore
1553          */
1554         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1555             (port != hw->port))
1556                 return 0;
1557
1558         return gpio_val;
1559 }
1560
1561 #define I40E_COMBINED_ACTIVITY 0xA
1562 #define I40E_FILTER_ACTIVITY 0xE
1563 #define I40E_LINK_ACTIVITY 0xC
1564 #define I40E_MAC_ACTIVITY 0xD
1565 #define I40E_LED0 22
1566
1567 /**
1568  * i40e_led_get - return current on/off mode
1569  * @hw: pointer to the hw struct
1570  *
1571  * The value returned is the 'mode' field as defined in the
1572  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1573  * values are variations of possible behaviors relating to
1574  * blink, link, and wire.
1575  **/
1576 u32 i40e_led_get(struct i40e_hw *hw)
1577 {
1578         u32 current_mode = 0;
1579         u32 mode = 0;
1580         int i;
1581
1582         /* as per the documentation GPIO 22-29 are the LED
1583          * GPIO pins named LED0..LED7
1584          */
1585         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1586                 u32 gpio_val = i40e_led_is_mine(hw, i);
1587
1588                 if (!gpio_val)
1589                         continue;
1590
1591                 /* ignore gpio LED src mode entries related to the activity
1592                  *  LEDs
1593                  */
1594                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1595                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1596                 switch (current_mode) {
1597                 case I40E_COMBINED_ACTIVITY:
1598                 case I40E_FILTER_ACTIVITY:
1599                 case I40E_MAC_ACTIVITY:
1600                 case I40E_LINK_ACTIVITY:
1601                         continue;
1602                 default:
1603                         break;
1604                 }
1605
1606                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1607                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1608                 break;
1609         }
1610
1611         return mode;
1612 }
1613
1614 /**
1615  * i40e_led_set - set new on/off mode
1616  * @hw: pointer to the hw struct
1617  * @mode: 0=off, 0xf=on (else see manual for mode details)
1618  * @blink: true if the LED should blink when on, false if steady
1619  *
1620  * if this function is used to turn on the blink it should
1621  * be used to disable the blink when restoring the original state.
1622  **/
1623 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1624 {
1625         u32 current_mode = 0;
1626         int i;
1627
1628         if (mode & 0xfffffff0)
1629                 DEBUGOUT1("invalid mode passed in %X\n", mode);
1630
1631         /* as per the documentation GPIO 22-29 are the LED
1632          * GPIO pins named LED0..LED7
1633          */
1634         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1635                 u32 gpio_val = i40e_led_is_mine(hw, i);
1636
1637                 if (!gpio_val)
1638                         continue;
1639
1640                 /* ignore gpio LED src mode entries related to the activity
1641                  * LEDs
1642                  */
1643                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1644                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1645                 switch (current_mode) {
1646                 case I40E_COMBINED_ACTIVITY:
1647                 case I40E_FILTER_ACTIVITY:
1648                 case I40E_MAC_ACTIVITY:
1649                 case I40E_LINK_ACTIVITY:
1650                         continue;
1651                 default:
1652                         break;
1653                 }
1654
1655                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1656                 /* this & is a bit of paranoia, but serves as a range check */
1657                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1658                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1659
1660                 if (blink)
1661                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1662                 else
1663                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1664
1665                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1666                 break;
1667         }
1668 }
1669
1670 /* Admin command wrappers */
1671
1672 /**
1673  * i40e_aq_get_phy_capabilities
1674  * @hw: pointer to the hw struct
1675  * @abilities: structure for PHY capabilities to be filled
1676  * @qualified_modules: report Qualified Modules
1677  * @report_init: report init capabilities (active are default)
1678  * @cmd_details: pointer to command details structure or NULL
1679  *
1680  * Returns the various PHY abilities supported on the Port.
1681  **/
1682 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1683                         bool qualified_modules, bool report_init,
1684                         struct i40e_aq_get_phy_abilities_resp *abilities,
1685                         struct i40e_asq_cmd_details *cmd_details)
1686 {
1687         struct i40e_aq_desc desc;
1688         enum i40e_status_code status;
1689         u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0;
1690         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1691
1692         if (!abilities)
1693                 return I40E_ERR_PARAM;
1694
1695         do {
1696                 i40e_fill_default_direct_cmd_desc(&desc,
1697                                                i40e_aqc_opc_get_phy_abilities);
1698
1699                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1700                 if (abilities_size > I40E_AQ_LARGE_BUF)
1701                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1702
1703                 if (qualified_modules)
1704                         desc.params.external.param0 |=
1705                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1706
1707                 if (report_init)
1708                         desc.params.external.param0 |=
1709                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1710
1711                 status = i40e_asq_send_command(hw, &desc, abilities,
1712                                                abilities_size, cmd_details);
1713
1714                 if (status != I40E_SUCCESS)
1715                         break;
1716
1717                 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) {
1718                         status = I40E_ERR_UNKNOWN_PHY;
1719                         break;
1720                 } else if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) {
1721                         i40e_msec_delay(1);
1722                         total_delay++;
1723                         status = I40E_ERR_TIMEOUT;
1724                 }
1725         } while ((hw->aq.asq_last_status != I40E_AQ_RC_OK) &&
1726                  (total_delay < max_delay));
1727
1728         if (status != I40E_SUCCESS)
1729                 return status;
1730
1731         if (report_init) {
1732                 if (hw->mac.type ==  I40E_MAC_XL710 &&
1733                     hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1734                     hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
1735                         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1736                 } else {
1737                         hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1738                         hw->phy.phy_types |=
1739                                         ((u64)abilities->phy_type_ext << 32);
1740                 }
1741         }
1742
1743         return status;
1744 }
1745
1746 /**
1747  * i40e_aq_set_phy_config
1748  * @hw: pointer to the hw struct
1749  * @config: structure with PHY configuration to be set
1750  * @cmd_details: pointer to command details structure or NULL
1751  *
1752  * Set the various PHY configuration parameters
1753  * supported on the Port.One or more of the Set PHY config parameters may be
1754  * ignored in an MFP mode as the PF may not have the privilege to set some
1755  * of the PHY Config parameters. This status will be indicated by the
1756  * command response.
1757  **/
1758 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1759                                 struct i40e_aq_set_phy_config *config,
1760                                 struct i40e_asq_cmd_details *cmd_details)
1761 {
1762         struct i40e_aq_desc desc;
1763         struct i40e_aq_set_phy_config *cmd =
1764                 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1765         enum i40e_status_code status;
1766
1767         if (!config)
1768                 return I40E_ERR_PARAM;
1769
1770         i40e_fill_default_direct_cmd_desc(&desc,
1771                                           i40e_aqc_opc_set_phy_config);
1772
1773         *cmd = *config;
1774
1775         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1776
1777         return status;
1778 }
1779
1780 /**
1781  * i40e_set_fc
1782  * @hw: pointer to the hw struct
1783  * @aq_failures: buffer to return AdminQ failure information
1784  * @atomic_restart: whether to enable atomic link restart
1785  *
1786  * Set the requested flow control mode using set_phy_config.
1787  **/
1788 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1789                                   bool atomic_restart)
1790 {
1791         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1792         struct i40e_aq_get_phy_abilities_resp abilities;
1793         struct i40e_aq_set_phy_config config;
1794         enum i40e_status_code status;
1795         u8 pause_mask = 0x0;
1796
1797         *aq_failures = 0x0;
1798
1799         switch (fc_mode) {
1800         case I40E_FC_FULL:
1801                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1802                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1803                 break;
1804         case I40E_FC_RX_PAUSE:
1805                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1806                 break;
1807         case I40E_FC_TX_PAUSE:
1808                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1809                 break;
1810         default:
1811                 break;
1812         }
1813
1814         /* Get the current phy config */
1815         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1816                                               NULL);
1817         if (status) {
1818                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1819                 return status;
1820         }
1821
1822         memset(&config, 0, sizeof(config));
1823         /* clear the old pause settings */
1824         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1825                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1826         /* set the new abilities */
1827         config.abilities |= pause_mask;
1828         /* If the abilities have changed, then set the new config */
1829         if (config.abilities != abilities.abilities) {
1830                 /* Auto restart link so settings take effect */
1831                 if (atomic_restart)
1832                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1833                 /* Copy over all the old settings */
1834                 config.phy_type = abilities.phy_type;
1835                 config.phy_type_ext = abilities.phy_type_ext;
1836                 config.link_speed = abilities.link_speed;
1837                 config.eee_capability = abilities.eee_capability;
1838                 config.eeer = abilities.eeer_val;
1839                 config.low_power_ctrl = abilities.d3_lpan;
1840                 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1841                                     I40E_AQ_PHY_FEC_CONFIG_MASK;
1842                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1843
1844                 if (status)
1845                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1846         }
1847         /* Update the link info */
1848         status = i40e_update_link_info(hw);
1849         if (status) {
1850                 /* Wait a little bit (on 40G cards it sometimes takes a really
1851                  * long time for link to come back from the atomic reset)
1852                  * and try once more
1853                  */
1854                 i40e_msec_delay(1000);
1855                 status = i40e_update_link_info(hw);
1856         }
1857         if (status)
1858                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1859
1860         return status;
1861 }
1862
1863 /**
1864  * i40e_aq_set_mac_config
1865  * @hw: pointer to the hw struct
1866  * @max_frame_size: Maximum Frame Size to be supported by the port
1867  * @crc_en: Tell HW to append a CRC to outgoing frames
1868  * @pacing: Pacing configurations
1869  * @cmd_details: pointer to command details structure or NULL
1870  *
1871  * Configure MAC settings for frame size, jumbo frame support and the
1872  * addition of a CRC by the hardware.
1873  **/
1874 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1875                                 u16 max_frame_size,
1876                                 bool crc_en, u16 pacing,
1877                                 struct i40e_asq_cmd_details *cmd_details)
1878 {
1879         struct i40e_aq_desc desc;
1880         struct i40e_aq_set_mac_config *cmd =
1881                 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1882         enum i40e_status_code status;
1883
1884         if (max_frame_size == 0)
1885                 return I40E_ERR_PARAM;
1886
1887         i40e_fill_default_direct_cmd_desc(&desc,
1888                                           i40e_aqc_opc_set_mac_config);
1889
1890         cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1891         cmd->params = ((u8)pacing & 0x0F) << 3;
1892         if (crc_en)
1893                 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1894
1895 #define I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD     0x7FFF
1896         cmd->fc_refresh_threshold =
1897                 CPU_TO_LE16(I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD);
1898
1899         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1900
1901         return status;
1902 }
1903
1904 /**
1905  * i40e_aq_clear_pxe_mode
1906  * @hw: pointer to the hw struct
1907  * @cmd_details: pointer to command details structure or NULL
1908  *
1909  * Tell the firmware that the driver is taking over from PXE
1910  **/
1911 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1912                         struct i40e_asq_cmd_details *cmd_details)
1913 {
1914         enum i40e_status_code status;
1915         struct i40e_aq_desc desc;
1916         struct i40e_aqc_clear_pxe *cmd =
1917                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1918
1919         i40e_fill_default_direct_cmd_desc(&desc,
1920                                           i40e_aqc_opc_clear_pxe_mode);
1921
1922         cmd->rx_cnt = 0x2;
1923
1924         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1925
1926         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1927
1928         return status;
1929 }
1930
1931 /**
1932  * i40e_aq_set_link_restart_an
1933  * @hw: pointer to the hw struct
1934  * @enable_link: if true: enable link, if false: disable link
1935  * @cmd_details: pointer to command details structure or NULL
1936  *
1937  * Sets up the link and restarts the Auto-Negotiation over the link.
1938  **/
1939 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1940                 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1941 {
1942         struct i40e_aq_desc desc;
1943         struct i40e_aqc_set_link_restart_an *cmd =
1944                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1945         enum i40e_status_code status;
1946
1947         i40e_fill_default_direct_cmd_desc(&desc,
1948                                           i40e_aqc_opc_set_link_restart_an);
1949
1950         cmd->command = I40E_AQ_PHY_RESTART_AN;
1951         if (enable_link)
1952                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1953         else
1954                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1955
1956         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1957
1958         return status;
1959 }
1960
1961 /**
1962  * i40e_aq_get_link_info
1963  * @hw: pointer to the hw struct
1964  * @enable_lse: enable/disable LinkStatusEvent reporting
1965  * @link: pointer to link status structure - optional
1966  * @cmd_details: pointer to command details structure or NULL
1967  *
1968  * Returns the link status of the adapter.
1969  **/
1970 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1971                                 bool enable_lse, struct i40e_link_status *link,
1972                                 struct i40e_asq_cmd_details *cmd_details)
1973 {
1974         struct i40e_aq_desc desc;
1975         struct i40e_aqc_get_link_status *resp =
1976                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1977         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1978         enum i40e_status_code status;
1979         bool tx_pause, rx_pause;
1980         u16 command_flags;
1981
1982         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1983
1984         if (enable_lse)
1985                 command_flags = I40E_AQ_LSE_ENABLE;
1986         else
1987                 command_flags = I40E_AQ_LSE_DISABLE;
1988         resp->command_flags = CPU_TO_LE16(command_flags);
1989
1990         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1991
1992         if (status != I40E_SUCCESS)
1993                 goto aq_get_link_info_exit;
1994
1995         /* save off old link status information */
1996         i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1997                     sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1998
1999         /* update link status */
2000         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
2001         hw->phy.media_type = i40e_get_media_type(hw);
2002         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
2003         hw_link_info->link_info = resp->link_info;
2004         hw_link_info->an_info = resp->an_info;
2005         hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
2006                                                  I40E_AQ_CONFIG_FEC_RS_ENA);
2007         hw_link_info->ext_info = resp->ext_info;
2008         hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
2009         hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
2010         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
2011
2012         /* update fc info */
2013         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
2014         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
2015         if (tx_pause & rx_pause)
2016                 hw->fc.current_mode = I40E_FC_FULL;
2017         else if (tx_pause)
2018                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
2019         else if (rx_pause)
2020                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
2021         else
2022                 hw->fc.current_mode = I40E_FC_NONE;
2023
2024         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
2025                 hw_link_info->crc_enable = true;
2026         else
2027                 hw_link_info->crc_enable = false;
2028
2029         if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
2030                 hw_link_info->lse_enable = true;
2031         else
2032                 hw_link_info->lse_enable = false;
2033
2034         if ((hw->mac.type == I40E_MAC_XL710) &&
2035             (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
2036              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
2037                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
2038
2039         if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
2040             hw->aq.api_min_ver >= 7) {
2041                 __le32 tmp;
2042
2043                 i40e_memcpy(&tmp, resp->link_type, sizeof(tmp),
2044                             I40E_NONDMA_TO_NONDMA);
2045                 hw->phy.phy_types = LE32_TO_CPU(tmp);
2046                 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
2047         }
2048
2049         /* save link status information */
2050         if (link)
2051                 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
2052                             I40E_NONDMA_TO_NONDMA);
2053
2054         /* flag cleared so helper functions don't call AQ again */
2055         hw->phy.get_link_info = false;
2056
2057 aq_get_link_info_exit:
2058         return status;
2059 }
2060
2061 /**
2062  * i40e_aq_set_phy_int_mask
2063  * @hw: pointer to the hw struct
2064  * @mask: interrupt mask to be set
2065  * @cmd_details: pointer to command details structure or NULL
2066  *
2067  * Set link interrupt mask.
2068  **/
2069 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2070                                 u16 mask,
2071                                 struct i40e_asq_cmd_details *cmd_details)
2072 {
2073         struct i40e_aq_desc desc;
2074         struct i40e_aqc_set_phy_int_mask *cmd =
2075                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2076         enum i40e_status_code status;
2077
2078         i40e_fill_default_direct_cmd_desc(&desc,
2079                                           i40e_aqc_opc_set_phy_int_mask);
2080
2081         cmd->event_mask = CPU_TO_LE16(mask);
2082
2083         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2084
2085         return status;
2086 }
2087
2088 /**
2089  * i40e_aq_get_local_advt_reg
2090  * @hw: pointer to the hw struct
2091  * @advt_reg: local AN advertisement register value
2092  * @cmd_details: pointer to command details structure or NULL
2093  *
2094  * Get the Local AN advertisement register value.
2095  **/
2096 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2097                                 u64 *advt_reg,
2098                                 struct i40e_asq_cmd_details *cmd_details)
2099 {
2100         struct i40e_aq_desc desc;
2101         struct i40e_aqc_an_advt_reg *resp =
2102                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2103         enum i40e_status_code status;
2104
2105         i40e_fill_default_direct_cmd_desc(&desc,
2106                                           i40e_aqc_opc_get_local_advt_reg);
2107
2108         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2109
2110         if (status != I40E_SUCCESS)
2111                 goto aq_get_local_advt_reg_exit;
2112
2113         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2114         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2115
2116 aq_get_local_advt_reg_exit:
2117         return status;
2118 }
2119
2120 /**
2121  * i40e_aq_set_local_advt_reg
2122  * @hw: pointer to the hw struct
2123  * @advt_reg: local AN advertisement register value
2124  * @cmd_details: pointer to command details structure or NULL
2125  *
2126  * Get the Local AN advertisement register value.
2127  **/
2128 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2129                                 u64 advt_reg,
2130                                 struct i40e_asq_cmd_details *cmd_details)
2131 {
2132         struct i40e_aq_desc desc;
2133         struct i40e_aqc_an_advt_reg *cmd =
2134                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2135         enum i40e_status_code status;
2136
2137         i40e_fill_default_direct_cmd_desc(&desc,
2138                                           i40e_aqc_opc_get_local_advt_reg);
2139
2140         cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2141         cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2142
2143         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2144
2145         return status;
2146 }
2147
2148 /**
2149  * i40e_aq_get_partner_advt
2150  * @hw: pointer to the hw struct
2151  * @advt_reg: AN partner advertisement register value
2152  * @cmd_details: pointer to command details structure or NULL
2153  *
2154  * Get the link partner AN advertisement register value.
2155  **/
2156 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2157                                 u64 *advt_reg,
2158                                 struct i40e_asq_cmd_details *cmd_details)
2159 {
2160         struct i40e_aq_desc desc;
2161         struct i40e_aqc_an_advt_reg *resp =
2162                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2163         enum i40e_status_code status;
2164
2165         i40e_fill_default_direct_cmd_desc(&desc,
2166                                           i40e_aqc_opc_get_partner_advt);
2167
2168         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2169
2170         if (status != I40E_SUCCESS)
2171                 goto aq_get_partner_advt_exit;
2172
2173         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2174         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2175
2176 aq_get_partner_advt_exit:
2177         return status;
2178 }
2179
2180 /**
2181  * i40e_aq_set_lb_modes
2182  * @hw: pointer to the hw struct
2183  * @lb_modes: loopback mode to be set
2184  * @cmd_details: pointer to command details structure or NULL
2185  *
2186  * Sets loopback modes.
2187  **/
2188 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2189                                 u16 lb_modes,
2190                                 struct i40e_asq_cmd_details *cmd_details)
2191 {
2192         struct i40e_aq_desc desc;
2193         struct i40e_aqc_set_lb_mode *cmd =
2194                 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2195         enum i40e_status_code status;
2196
2197         i40e_fill_default_direct_cmd_desc(&desc,
2198                                           i40e_aqc_opc_set_lb_modes);
2199
2200         cmd->lb_mode = CPU_TO_LE16(lb_modes);
2201
2202         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2203
2204         return status;
2205 }
2206
2207 /**
2208  * i40e_aq_set_phy_debug
2209  * @hw: pointer to the hw struct
2210  * @cmd_flags: debug command flags
2211  * @cmd_details: pointer to command details structure or NULL
2212  *
2213  * Reset the external PHY.
2214  **/
2215 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2216                                 struct i40e_asq_cmd_details *cmd_details)
2217 {
2218         struct i40e_aq_desc desc;
2219         struct i40e_aqc_set_phy_debug *cmd =
2220                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2221         enum i40e_status_code status;
2222
2223         i40e_fill_default_direct_cmd_desc(&desc,
2224                                           i40e_aqc_opc_set_phy_debug);
2225
2226         cmd->command_flags = cmd_flags;
2227
2228         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2229
2230         return status;
2231 }
2232
2233 /**
2234  * i40e_aq_add_vsi
2235  * @hw: pointer to the hw struct
2236  * @vsi_ctx: pointer to a vsi context struct
2237  * @cmd_details: pointer to command details structure or NULL
2238  *
2239  * Add a VSI context to the hardware.
2240 **/
2241 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2242                                 struct i40e_vsi_context *vsi_ctx,
2243                                 struct i40e_asq_cmd_details *cmd_details)
2244 {
2245         struct i40e_aq_desc desc;
2246         struct i40e_aqc_add_get_update_vsi *cmd =
2247                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2248         struct i40e_aqc_add_get_update_vsi_completion *resp =
2249                 (struct i40e_aqc_add_get_update_vsi_completion *)
2250                 &desc.params.raw;
2251         enum i40e_status_code status;
2252
2253         i40e_fill_default_direct_cmd_desc(&desc,
2254                                           i40e_aqc_opc_add_vsi);
2255
2256         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2257         cmd->connection_type = vsi_ctx->connection_type;
2258         cmd->vf_id = vsi_ctx->vf_num;
2259         cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2260
2261         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2262
2263         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2264                                     sizeof(vsi_ctx->info), cmd_details);
2265
2266         if (status != I40E_SUCCESS)
2267                 goto aq_add_vsi_exit;
2268
2269         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2270         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2271         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2272         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2273
2274 aq_add_vsi_exit:
2275         return status;
2276 }
2277
2278 /**
2279  * i40e_aq_set_default_vsi
2280  * @hw: pointer to the hw struct
2281  * @seid: vsi number
2282  * @cmd_details: pointer to command details structure or NULL
2283  **/
2284 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2285                                 u16 seid,
2286                                 struct i40e_asq_cmd_details *cmd_details)
2287 {
2288         struct i40e_aq_desc desc;
2289         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2290                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2291                 &desc.params.raw;
2292         enum i40e_status_code status;
2293
2294         i40e_fill_default_direct_cmd_desc(&desc,
2295                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2296
2297         cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2298         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2299         cmd->seid = CPU_TO_LE16(seid);
2300
2301         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2302
2303         return status;
2304 }
2305
2306 /**
2307  * i40e_aq_clear_default_vsi
2308  * @hw: pointer to the hw struct
2309  * @seid: vsi number
2310  * @cmd_details: pointer to command details structure or NULL
2311  **/
2312 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2313                                 u16 seid,
2314                                 struct i40e_asq_cmd_details *cmd_details)
2315 {
2316         struct i40e_aq_desc desc;
2317         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2318                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2319                 &desc.params.raw;
2320         enum i40e_status_code status;
2321
2322         i40e_fill_default_direct_cmd_desc(&desc,
2323                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2324
2325         cmd->promiscuous_flags = CPU_TO_LE16(0);
2326         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2327         cmd->seid = CPU_TO_LE16(seid);
2328
2329         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2330
2331         return status;
2332 }
2333
2334 /**
2335  * i40e_aq_set_vsi_unicast_promiscuous
2336  * @hw: pointer to the hw struct
2337  * @seid: vsi number
2338  * @set: set unicast promiscuous enable/disable
2339  * @cmd_details: pointer to command details structure or NULL
2340  * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2341  **/
2342 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2343                                 u16 seid, bool set,
2344                                 struct i40e_asq_cmd_details *cmd_details,
2345                                 bool rx_only_promisc)
2346 {
2347         struct i40e_aq_desc desc;
2348         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2349                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2350         enum i40e_status_code status;
2351         u16 flags = 0;
2352
2353         i40e_fill_default_direct_cmd_desc(&desc,
2354                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2355
2356         if (set) {
2357                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2358                 if (rx_only_promisc &&
2359                     (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2360                      (hw->aq.api_maj_ver > 1)))
2361                         flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2362         }
2363
2364         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2365
2366         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2367         if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2368              (hw->aq.api_maj_ver > 1))
2369                 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2370
2371         cmd->seid = CPU_TO_LE16(seid);
2372         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2373
2374         return status;
2375 }
2376
2377 /**
2378  * i40e_aq_set_vsi_multicast_promiscuous
2379  * @hw: pointer to the hw struct
2380  * @seid: vsi number
2381  * @set: set multicast promiscuous enable/disable
2382  * @cmd_details: pointer to command details structure or NULL
2383  **/
2384 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2385                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2386 {
2387         struct i40e_aq_desc desc;
2388         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2389                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2390         enum i40e_status_code status;
2391         u16 flags = 0;
2392
2393         i40e_fill_default_direct_cmd_desc(&desc,
2394                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2395
2396         if (set)
2397                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2398
2399         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2400
2401         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2402
2403         cmd->seid = CPU_TO_LE16(seid);
2404         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2405
2406         return status;
2407 }
2408
2409 /**
2410 * i40e_aq_set_vsi_full_promiscuous
2411 * @hw: pointer to the hw struct
2412 * @seid: VSI number
2413 * @set: set promiscuous enable/disable
2414 * @cmd_details: pointer to command details structure or NULL
2415 **/
2416 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw,
2417                                 u16 seid, bool set,
2418                                 struct i40e_asq_cmd_details *cmd_details)
2419 {
2420         struct i40e_aq_desc desc;
2421         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2422                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2423         enum i40e_status_code status;
2424         u16 flags = 0;
2425
2426         i40e_fill_default_direct_cmd_desc(&desc,
2427                 i40e_aqc_opc_set_vsi_promiscuous_modes);
2428
2429         if (set)
2430                 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2431                         I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2432                         I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2433
2434         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2435
2436         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2437                                        I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2438                                        I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2439
2440         cmd->seid = CPU_TO_LE16(seid);
2441         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2442
2443         return status;
2444 }
2445
2446 /**
2447  * i40e_aq_set_vsi_mc_promisc_on_vlan
2448  * @hw: pointer to the hw struct
2449  * @seid: vsi number
2450  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2451  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2452  * @cmd_details: pointer to command details structure or NULL
2453  **/
2454 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2455                                 u16 seid, bool enable, u16 vid,
2456                                 struct i40e_asq_cmd_details *cmd_details)
2457 {
2458         struct i40e_aq_desc desc;
2459         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2460                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2461         enum i40e_status_code status;
2462         u16 flags = 0;
2463
2464         i40e_fill_default_direct_cmd_desc(&desc,
2465                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2466
2467         if (enable)
2468                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2469
2470         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2471         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2472         cmd->seid = CPU_TO_LE16(seid);
2473         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2474
2475         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2476
2477         return status;
2478 }
2479
2480 /**
2481  * i40e_aq_set_vsi_uc_promisc_on_vlan
2482  * @hw: pointer to the hw struct
2483  * @seid: vsi number
2484  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2485  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2486  * @cmd_details: pointer to command details structure or NULL
2487  **/
2488 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2489                                 u16 seid, bool enable, u16 vid,
2490                                 struct i40e_asq_cmd_details *cmd_details)
2491 {
2492         struct i40e_aq_desc desc;
2493         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2494                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2495         enum i40e_status_code status;
2496         u16 flags = 0;
2497
2498         i40e_fill_default_direct_cmd_desc(&desc,
2499                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2500
2501         if (enable)
2502                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2503
2504         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2505         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2506         cmd->seid = CPU_TO_LE16(seid);
2507         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2508
2509         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2510
2511         return status;
2512 }
2513
2514 /**
2515  * i40e_aq_set_vsi_bc_promisc_on_vlan
2516  * @hw: pointer to the hw struct
2517  * @seid: vsi number
2518  * @enable: set broadcast promiscuous enable/disable for a given VLAN
2519  * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2520  * @cmd_details: pointer to command details structure or NULL
2521  **/
2522 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2523                                 u16 seid, bool enable, u16 vid,
2524                                 struct i40e_asq_cmd_details *cmd_details)
2525 {
2526         struct i40e_aq_desc desc;
2527         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2528                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2529         enum i40e_status_code status;
2530         u16 flags = 0;
2531
2532         i40e_fill_default_direct_cmd_desc(&desc,
2533                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2534
2535         if (enable)
2536                 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2537
2538         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2539         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2540         cmd->seid = CPU_TO_LE16(seid);
2541         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2542
2543         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2544
2545         return status;
2546 }
2547
2548 /**
2549  * i40e_aq_set_vsi_broadcast
2550  * @hw: pointer to the hw struct
2551  * @seid: vsi number
2552  * @set_filter: true to set filter, false to clear filter
2553  * @cmd_details: pointer to command details structure or NULL
2554  *
2555  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2556  **/
2557 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2558                                 u16 seid, bool set_filter,
2559                                 struct i40e_asq_cmd_details *cmd_details)
2560 {
2561         struct i40e_aq_desc desc;
2562         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2563                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2564         enum i40e_status_code status;
2565
2566         i40e_fill_default_direct_cmd_desc(&desc,
2567                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2568
2569         if (set_filter)
2570                 cmd->promiscuous_flags
2571                             |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2572         else
2573                 cmd->promiscuous_flags
2574                             &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2575
2576         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2577         cmd->seid = CPU_TO_LE16(seid);
2578         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2579
2580         return status;
2581 }
2582
2583 /**
2584  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2585  * @hw: pointer to the hw struct
2586  * @seid: vsi number
2587  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2588  * @cmd_details: pointer to command details structure or NULL
2589  **/
2590 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2591                                 u16 seid, bool enable,
2592                                 struct i40e_asq_cmd_details *cmd_details)
2593 {
2594         struct i40e_aq_desc desc;
2595         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2596                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2597         enum i40e_status_code status;
2598         u16 flags = 0;
2599
2600         i40e_fill_default_direct_cmd_desc(&desc,
2601                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2602         if (enable)
2603                 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2604
2605         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2606         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2607         cmd->seid = CPU_TO_LE16(seid);
2608
2609         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2610
2611         return status;
2612 }
2613
2614 /**
2615  * i40e_get_vsi_params - get VSI configuration info
2616  * @hw: pointer to the hw struct
2617  * @vsi_ctx: pointer to a vsi context struct
2618  * @cmd_details: pointer to command details structure or NULL
2619  **/
2620 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2621                                 struct i40e_vsi_context *vsi_ctx,
2622                                 struct i40e_asq_cmd_details *cmd_details)
2623 {
2624         struct i40e_aq_desc desc;
2625         struct i40e_aqc_add_get_update_vsi *cmd =
2626                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2627         struct i40e_aqc_add_get_update_vsi_completion *resp =
2628                 (struct i40e_aqc_add_get_update_vsi_completion *)
2629                 &desc.params.raw;
2630         enum i40e_status_code status;
2631
2632         UNREFERENCED_1PARAMETER(cmd_details);
2633         i40e_fill_default_direct_cmd_desc(&desc,
2634                                           i40e_aqc_opc_get_vsi_parameters);
2635
2636         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2637
2638         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2639
2640         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2641                                     sizeof(vsi_ctx->info), NULL);
2642
2643         if (status != I40E_SUCCESS)
2644                 goto aq_get_vsi_params_exit;
2645
2646         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2647         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2648         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2649         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2650
2651 aq_get_vsi_params_exit:
2652         return status;
2653 }
2654
2655 /**
2656  * i40e_aq_update_vsi_params
2657  * @hw: pointer to the hw struct
2658  * @vsi_ctx: pointer to a vsi context struct
2659  * @cmd_details: pointer to command details structure or NULL
2660  *
2661  * Update a VSI context.
2662  **/
2663 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2664                                 struct i40e_vsi_context *vsi_ctx,
2665                                 struct i40e_asq_cmd_details *cmd_details)
2666 {
2667         struct i40e_aq_desc desc;
2668         struct i40e_aqc_add_get_update_vsi *cmd =
2669                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2670         struct i40e_aqc_add_get_update_vsi_completion *resp =
2671                 (struct i40e_aqc_add_get_update_vsi_completion *)
2672                 &desc.params.raw;
2673         enum i40e_status_code status;
2674
2675         i40e_fill_default_direct_cmd_desc(&desc,
2676                                           i40e_aqc_opc_update_vsi_parameters);
2677         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2678
2679         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2680
2681         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2682                                     sizeof(vsi_ctx->info), cmd_details);
2683
2684         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2685         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2686
2687         return status;
2688 }
2689
2690 /**
2691  * i40e_aq_get_switch_config
2692  * @hw: pointer to the hardware structure
2693  * @buf: pointer to the result buffer
2694  * @buf_size: length of input buffer
2695  * @start_seid: seid to start for the report, 0 == beginning
2696  * @cmd_details: pointer to command details structure or NULL
2697  *
2698  * Fill the buf with switch configuration returned from AdminQ command
2699  **/
2700 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2701                                 struct i40e_aqc_get_switch_config_resp *buf,
2702                                 u16 buf_size, u16 *start_seid,
2703                                 struct i40e_asq_cmd_details *cmd_details)
2704 {
2705         struct i40e_aq_desc desc;
2706         struct i40e_aqc_switch_seid *scfg =
2707                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2708         enum i40e_status_code status;
2709
2710         i40e_fill_default_direct_cmd_desc(&desc,
2711                                           i40e_aqc_opc_get_switch_config);
2712         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2713         if (buf_size > I40E_AQ_LARGE_BUF)
2714                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2715         scfg->seid = CPU_TO_LE16(*start_seid);
2716
2717         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2718         *start_seid = LE16_TO_CPU(scfg->seid);
2719
2720         return status;
2721 }
2722
2723 /**
2724  * i40e_aq_set_switch_config
2725  * @hw: pointer to the hardware structure
2726  * @flags: bit flag values to set
2727  * @mode: cloud filter mode
2728  * @valid_flags: which bit flags to set
2729  * @cmd_details: pointer to command details structure or NULL
2730  *
2731  * Set switch configuration bits
2732  **/
2733 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2734                                 u16 flags, u16 valid_flags, u8 mode,
2735                                 struct i40e_asq_cmd_details *cmd_details)
2736 {
2737         struct i40e_aq_desc desc;
2738         struct i40e_aqc_set_switch_config *scfg =
2739                 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2740         enum i40e_status_code status;
2741
2742         i40e_fill_default_direct_cmd_desc(&desc,
2743                                           i40e_aqc_opc_set_switch_config);
2744         scfg->flags = CPU_TO_LE16(flags);
2745         scfg->valid_flags = CPU_TO_LE16(valid_flags);
2746         scfg->mode = mode;
2747         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
2748                 scfg->switch_tag = CPU_TO_LE16(hw->switch_tag);
2749                 scfg->first_tag = CPU_TO_LE16(hw->first_tag);
2750                 scfg->second_tag = CPU_TO_LE16(hw->second_tag);
2751         }
2752         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2753
2754         return status;
2755 }
2756
2757 /**
2758  * i40e_aq_get_firmware_version
2759  * @hw: pointer to the hw struct
2760  * @fw_major_version: firmware major version
2761  * @fw_minor_version: firmware minor version
2762  * @fw_build: firmware build number
2763  * @api_major_version: major queue version
2764  * @api_minor_version: minor queue version
2765  * @cmd_details: pointer to command details structure or NULL
2766  *
2767  * Get the firmware version from the admin queue commands
2768  **/
2769 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2770                                 u16 *fw_major_version, u16 *fw_minor_version,
2771                                 u32 *fw_build,
2772                                 u16 *api_major_version, u16 *api_minor_version,
2773                                 struct i40e_asq_cmd_details *cmd_details)
2774 {
2775         struct i40e_aq_desc desc;
2776         struct i40e_aqc_get_version *resp =
2777                 (struct i40e_aqc_get_version *)&desc.params.raw;
2778         enum i40e_status_code status;
2779
2780         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2781
2782         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2783
2784         if (status == I40E_SUCCESS) {
2785                 if (fw_major_version != NULL)
2786                         *fw_major_version = LE16_TO_CPU(resp->fw_major);
2787                 if (fw_minor_version != NULL)
2788                         *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2789                 if (fw_build != NULL)
2790                         *fw_build = LE32_TO_CPU(resp->fw_build);
2791                 if (api_major_version != NULL)
2792                         *api_major_version = LE16_TO_CPU(resp->api_major);
2793                 if (api_minor_version != NULL)
2794                         *api_minor_version = LE16_TO_CPU(resp->api_minor);
2795
2796                 /* A workaround to fix the API version in SW */
2797                 if (api_major_version && api_minor_version &&
2798                     fw_major_version && fw_minor_version &&
2799                     ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2800                     (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2801                      (*fw_major_version > 4)))
2802                         *api_minor_version = 2;
2803         }
2804
2805         return status;
2806 }
2807
2808 /**
2809  * i40e_aq_send_driver_version
2810  * @hw: pointer to the hw struct
2811  * @dv: driver's major, minor version
2812  * @cmd_details: pointer to command details structure or NULL
2813  *
2814  * Send the driver version to the firmware
2815  **/
2816 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2817                                 struct i40e_driver_version *dv,
2818                                 struct i40e_asq_cmd_details *cmd_details)
2819 {
2820         struct i40e_aq_desc desc;
2821         struct i40e_aqc_driver_version *cmd =
2822                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2823         enum i40e_status_code status;
2824         u16 len;
2825
2826         if (dv == NULL)
2827                 return I40E_ERR_PARAM;
2828
2829         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2830
2831         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2832         cmd->driver_major_ver = dv->major_version;
2833         cmd->driver_minor_ver = dv->minor_version;
2834         cmd->driver_build_ver = dv->build_version;
2835         cmd->driver_subbuild_ver = dv->subbuild_version;
2836
2837         len = 0;
2838         while (len < sizeof(dv->driver_string) &&
2839                (dv->driver_string[len] < 0x80) &&
2840                dv->driver_string[len])
2841                 len++;
2842         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2843                                        len, cmd_details);
2844
2845         return status;
2846 }
2847
2848 /**
2849  * i40e_get_link_status - get status of the HW network link
2850  * @hw: pointer to the hw struct
2851  * @link_up: pointer to bool (true/false = linkup/linkdown)
2852  *
2853  * Variable link_up true if link is up, false if link is down.
2854  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2855  *
2856  * Side effect: LinkStatusEvent reporting becomes enabled
2857  **/
2858 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2859 {
2860         enum i40e_status_code status = I40E_SUCCESS;
2861
2862         if (hw->phy.get_link_info) {
2863                 status = i40e_update_link_info(hw);
2864
2865                 if (status != I40E_SUCCESS)
2866                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2867                                    status);
2868         }
2869
2870         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2871
2872         return status;
2873 }
2874
2875 /**
2876  * i40e_updatelink_status - update status of the HW network link
2877  * @hw: pointer to the hw struct
2878  **/
2879 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2880 {
2881         struct i40e_aq_get_phy_abilities_resp abilities;
2882         enum i40e_status_code status = I40E_SUCCESS;
2883
2884         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2885         if (status)
2886                 return status;
2887
2888         /* extra checking needed to ensure link info to user is timely */
2889         if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2890             ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2891              !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2892                 status = i40e_aq_get_phy_capabilities(hw, false, false,
2893                                                       &abilities, NULL);
2894                 if (status)
2895                         return status;
2896
2897                 hw->phy.link_info.req_fec_info =
2898                         abilities.fec_cfg_curr_mod_ext_info &
2899                         (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS);
2900
2901                 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2902                         sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2903         }
2904         return status;
2905 }
2906
2907
2908 /**
2909  * i40e_get_link_speed
2910  * @hw: pointer to the hw struct
2911  *
2912  * Returns the link speed of the adapter.
2913  **/
2914 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2915 {
2916         enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2917         enum i40e_status_code status = I40E_SUCCESS;
2918
2919         if (hw->phy.get_link_info) {
2920                 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2921
2922                 if (status != I40E_SUCCESS)
2923                         goto i40e_link_speed_exit;
2924         }
2925
2926         speed = hw->phy.link_info.link_speed;
2927
2928 i40e_link_speed_exit:
2929         return speed;
2930 }
2931
2932 /**
2933  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2934  * @hw: pointer to the hw struct
2935  * @uplink_seid: the MAC or other gizmo SEID
2936  * @downlink_seid: the VSI SEID
2937  * @enabled_tc: bitmap of TCs to be enabled
2938  * @default_port: true for default port VSI, false for control port
2939  * @veb_seid: pointer to where to put the resulting VEB SEID
2940  * @enable_stats: true to turn on VEB stats
2941  * @cmd_details: pointer to command details structure or NULL
2942  *
2943  * This asks the FW to add a VEB between the uplink and downlink
2944  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2945  **/
2946 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2947                                 u16 downlink_seid, u8 enabled_tc,
2948                                 bool default_port, u16 *veb_seid,
2949                                 bool enable_stats,
2950                                 struct i40e_asq_cmd_details *cmd_details)
2951 {
2952         struct i40e_aq_desc desc;
2953         struct i40e_aqc_add_veb *cmd =
2954                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2955         struct i40e_aqc_add_veb_completion *resp =
2956                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2957         enum i40e_status_code status;
2958         u16 veb_flags = 0;
2959
2960         /* SEIDs need to either both be set or both be 0 for floating VEB */
2961         if (!!uplink_seid != !!downlink_seid)
2962                 return I40E_ERR_PARAM;
2963
2964         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2965
2966         cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2967         cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2968         cmd->enable_tcs = enabled_tc;
2969         if (!uplink_seid)
2970                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2971         if (default_port)
2972                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2973         else
2974                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2975
2976         /* reverse logic here: set the bitflag to disable the stats */
2977         if (!enable_stats)
2978                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2979
2980         cmd->veb_flags = CPU_TO_LE16(veb_flags);
2981
2982         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2983
2984         if (!status && veb_seid)
2985                 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2986
2987         return status;
2988 }
2989
2990 /**
2991  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2992  * @hw: pointer to the hw struct
2993  * @veb_seid: the SEID of the VEB to query
2994  * @switch_id: the uplink switch id
2995  * @floating: set to true if the VEB is floating
2996  * @statistic_index: index of the stats counter block for this VEB
2997  * @vebs_used: number of VEB's used by function
2998  * @vebs_free: total VEB's not reserved by any function
2999  * @cmd_details: pointer to command details structure or NULL
3000  *
3001  * This retrieves the parameters for a particular VEB, specified by
3002  * uplink_seid, and returns them to the caller.
3003  **/
3004 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
3005                                 u16 veb_seid, u16 *switch_id,
3006                                 bool *floating, u16 *statistic_index,
3007                                 u16 *vebs_used, u16 *vebs_free,
3008                                 struct i40e_asq_cmd_details *cmd_details)
3009 {
3010         struct i40e_aq_desc desc;
3011         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
3012                 (struct i40e_aqc_get_veb_parameters_completion *)
3013                 &desc.params.raw;
3014         enum i40e_status_code status;
3015
3016         if (veb_seid == 0)
3017                 return I40E_ERR_PARAM;
3018
3019         i40e_fill_default_direct_cmd_desc(&desc,
3020                                           i40e_aqc_opc_get_veb_parameters);
3021         cmd_resp->seid = CPU_TO_LE16(veb_seid);
3022
3023         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3024         if (status)
3025                 goto get_veb_exit;
3026
3027         if (switch_id)
3028                 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
3029         if (statistic_index)
3030                 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
3031         if (vebs_used)
3032                 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
3033         if (vebs_free)
3034                 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
3035         if (floating) {
3036                 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
3037
3038                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
3039                         *floating = true;
3040                 else
3041                         *floating = false;
3042         }
3043
3044 get_veb_exit:
3045         return status;
3046 }
3047
3048 /**
3049  * i40e_aq_add_macvlan
3050  * @hw: pointer to the hw struct
3051  * @seid: VSI for the mac address
3052  * @mv_list: list of macvlans to be added
3053  * @count: length of the list
3054  * @cmd_details: pointer to command details structure or NULL
3055  *
3056  * Add MAC/VLAN addresses to the HW filtering
3057  **/
3058 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
3059                         struct i40e_aqc_add_macvlan_element_data *mv_list,
3060                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3061 {
3062         struct i40e_aq_desc desc;
3063         struct i40e_aqc_macvlan *cmd =
3064                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3065         enum i40e_status_code status;
3066         u16 buf_size;
3067         int i;
3068
3069         if (count == 0 || !mv_list || !hw)
3070                 return I40E_ERR_PARAM;
3071
3072         buf_size = count * sizeof(*mv_list);
3073
3074         /* prep the rest of the request */
3075         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
3076         cmd->num_addresses = CPU_TO_LE16(count);
3077         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3078         cmd->seid[1] = 0;
3079         cmd->seid[2] = 0;
3080
3081         for (i = 0; i < count; i++)
3082                 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
3083                         mv_list[i].flags |=
3084                             CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
3085
3086         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3087         if (buf_size > I40E_AQ_LARGE_BUF)
3088                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3089
3090         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3091                                        cmd_details);
3092
3093         return status;
3094 }
3095
3096 /**
3097  * i40e_aq_remove_macvlan
3098  * @hw: pointer to the hw struct
3099  * @seid: VSI for the mac address
3100  * @mv_list: list of macvlans to be removed
3101  * @count: length of the list
3102  * @cmd_details: pointer to command details structure or NULL
3103  *
3104  * Remove MAC/VLAN addresses from the HW filtering
3105  **/
3106 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
3107                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
3108                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3109 {
3110         struct i40e_aq_desc desc;
3111         struct i40e_aqc_macvlan *cmd =
3112                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3113         enum i40e_status_code status;
3114         u16 buf_size;
3115
3116         if (count == 0 || !mv_list || !hw)
3117                 return I40E_ERR_PARAM;
3118
3119         buf_size = count * sizeof(*mv_list);
3120
3121         /* prep the rest of the request */
3122         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
3123         cmd->num_addresses = CPU_TO_LE16(count);
3124         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3125         cmd->seid[1] = 0;
3126         cmd->seid[2] = 0;
3127
3128         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3129         if (buf_size > I40E_AQ_LARGE_BUF)
3130                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3131
3132         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3133                                        cmd_details);
3134
3135         return status;
3136 }
3137
3138 /**
3139  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3140  * @hw: pointer to the hw struct
3141  * @opcode: AQ opcode for add or delete mirror rule
3142  * @sw_seid: Switch SEID (to which rule refers)
3143  * @rule_type: Rule Type (ingress/egress/VLAN)
3144  * @id: Destination VSI SEID or Rule ID
3145  * @count: length of the list
3146  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3147  * @cmd_details: pointer to command details structure or NULL
3148  * @rule_id: Rule ID returned from FW
3149  * @rules_used: Number of rules used in internal switch
3150  * @rules_free: Number of rules free in internal switch
3151  *
3152  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3153  * VEBs/VEPA elements only
3154  **/
3155 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3156                         u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3157                         u16 count, __le16 *mr_list,
3158                         struct i40e_asq_cmd_details *cmd_details,
3159                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3160 {
3161         struct i40e_aq_desc desc;
3162         struct i40e_aqc_add_delete_mirror_rule *cmd =
3163                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3164         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3165         (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3166         enum i40e_status_code status;
3167         u16 buf_size;
3168
3169         buf_size = count * sizeof(*mr_list);
3170
3171         /* prep the rest of the request */
3172         i40e_fill_default_direct_cmd_desc(&desc, opcode);
3173         cmd->seid = CPU_TO_LE16(sw_seid);
3174         cmd->rule_type = CPU_TO_LE16(rule_type &
3175                                      I40E_AQC_MIRROR_RULE_TYPE_MASK);
3176         cmd->num_entries = CPU_TO_LE16(count);
3177         /* Dest VSI for add, rule_id for delete */
3178         cmd->destination = CPU_TO_LE16(id);
3179         if (mr_list) {
3180                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3181                                                 I40E_AQ_FLAG_RD));
3182                 if (buf_size > I40E_AQ_LARGE_BUF)
3183                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3184         }
3185
3186         status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3187                                        cmd_details);
3188         if (status == I40E_SUCCESS ||
3189             hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3190                 if (rule_id)
3191                         *rule_id = LE16_TO_CPU(resp->rule_id);
3192                 if (rules_used)
3193                         *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3194                 if (rules_free)
3195                         *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3196         }
3197         return status;
3198 }
3199
3200 /**
3201  * i40e_aq_add_mirrorrule - add a mirror rule
3202  * @hw: pointer to the hw struct
3203  * @sw_seid: Switch SEID (to which rule refers)
3204  * @rule_type: Rule Type (ingress/egress/VLAN)
3205  * @dest_vsi: SEID of VSI to which packets will be mirrored
3206  * @count: length of the list
3207  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3208  * @cmd_details: pointer to command details structure or NULL
3209  * @rule_id: Rule ID returned from FW
3210  * @rules_used: Number of rules used in internal switch
3211  * @rules_free: Number of rules free in internal switch
3212  *
3213  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3214  **/
3215 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3216                         u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3217                         struct i40e_asq_cmd_details *cmd_details,
3218                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3219 {
3220         if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3221             rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3222                 if (count == 0 || !mr_list)
3223                         return I40E_ERR_PARAM;
3224         }
3225
3226         return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3227                                   rule_type, dest_vsi, count, mr_list,
3228                                   cmd_details, rule_id, rules_used, rules_free);
3229 }
3230
3231 /**
3232  * i40e_aq_delete_mirrorrule - delete a mirror rule
3233  * @hw: pointer to the hw struct
3234  * @sw_seid: Switch SEID (to which rule refers)
3235  * @rule_type: Rule Type (ingress/egress/VLAN)
3236  * @count: length of the list
3237  * @rule_id: Rule ID that is returned in the receive desc as part of
3238  *              add_mirrorrule.
3239  * @mr_list: list of mirrored VLAN IDs to be removed
3240  * @cmd_details: pointer to command details structure or NULL
3241  * @rules_used: Number of rules used in internal switch
3242  * @rules_free: Number of rules free in internal switch
3243  *
3244  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3245  **/
3246 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3247                         u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3248                         struct i40e_asq_cmd_details *cmd_details,
3249                         u16 *rules_used, u16 *rules_free)
3250 {
3251         /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3252         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3253                 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3254                  * mirroring. For other rule_type, count and rule_type should
3255                  * not matter.
3256                  */
3257                 if (count == 0 || !mr_list)
3258                         return I40E_ERR_PARAM;
3259         }
3260
3261         return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3262                                   rule_type, rule_id, count, mr_list,
3263                                   cmd_details, NULL, rules_used, rules_free);
3264 }
3265
3266 /**
3267  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3268  * @hw: pointer to the hw struct
3269  * @seid: VSI for the vlan filters
3270  * @v_list: list of vlan filters to be added
3271  * @count: length of the list
3272  * @cmd_details: pointer to command details structure or NULL
3273  **/
3274 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3275                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3276                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3277 {
3278         struct i40e_aq_desc desc;
3279         struct i40e_aqc_macvlan *cmd =
3280                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3281         enum i40e_status_code status;
3282         u16 buf_size;
3283
3284         if (count == 0 || !v_list || !hw)
3285                 return I40E_ERR_PARAM;
3286
3287         buf_size = count * sizeof(*v_list);
3288
3289         /* prep the rest of the request */
3290         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3291         cmd->num_addresses = CPU_TO_LE16(count);
3292         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3293         cmd->seid[1] = 0;
3294         cmd->seid[2] = 0;
3295
3296         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3297         if (buf_size > I40E_AQ_LARGE_BUF)
3298                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3299
3300         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3301                                        cmd_details);
3302
3303         return status;
3304 }
3305
3306 /**
3307  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3308  * @hw: pointer to the hw struct
3309  * @seid: VSI for the vlan filters
3310  * @v_list: list of macvlans to be removed
3311  * @count: length of the list
3312  * @cmd_details: pointer to command details structure or NULL
3313  **/
3314 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3315                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3316                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3317 {
3318         struct i40e_aq_desc desc;
3319         struct i40e_aqc_macvlan *cmd =
3320                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3321         enum i40e_status_code status;
3322         u16 buf_size;
3323
3324         if (count == 0 || !v_list || !hw)
3325                 return I40E_ERR_PARAM;
3326
3327         buf_size = count * sizeof(*v_list);
3328
3329         /* prep the rest of the request */
3330         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3331         cmd->num_addresses = CPU_TO_LE16(count);
3332         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3333         cmd->seid[1] = 0;
3334         cmd->seid[2] = 0;
3335
3336         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3337         if (buf_size > I40E_AQ_LARGE_BUF)
3338                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3339
3340         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3341                                        cmd_details);
3342
3343         return status;
3344 }
3345
3346 /**
3347  * i40e_aq_send_msg_to_vf
3348  * @hw: pointer to the hardware structure
3349  * @vfid: vf id to send msg
3350  * @v_opcode: opcodes for VF-PF communication
3351  * @v_retval: return error code
3352  * @msg: pointer to the msg buffer
3353  * @msglen: msg length
3354  * @cmd_details: pointer to command details
3355  *
3356  * send msg to vf
3357  **/
3358 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3359                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3360                                 struct i40e_asq_cmd_details *cmd_details)
3361 {
3362         struct i40e_aq_desc desc;
3363         struct i40e_aqc_pf_vf_message *cmd =
3364                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3365         enum i40e_status_code status;
3366
3367         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3368         cmd->id = CPU_TO_LE32(vfid);
3369         desc.cookie_high = CPU_TO_LE32(v_opcode);
3370         desc.cookie_low = CPU_TO_LE32(v_retval);
3371         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3372         if (msglen) {
3373                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3374                                                 I40E_AQ_FLAG_RD));
3375                 if (msglen > I40E_AQ_LARGE_BUF)
3376                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3377                 desc.datalen = CPU_TO_LE16(msglen);
3378         }
3379         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3380
3381         return status;
3382 }
3383
3384 /**
3385  * i40e_aq_debug_read_register
3386  * @hw: pointer to the hw struct
3387  * @reg_addr: register address
3388  * @reg_val: register value
3389  * @cmd_details: pointer to command details structure or NULL
3390  *
3391  * Read the register using the admin queue commands
3392  **/
3393 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3394                                 u32 reg_addr, u64 *reg_val,
3395                                 struct i40e_asq_cmd_details *cmd_details)
3396 {
3397         struct i40e_aq_desc desc;
3398         struct i40e_aqc_debug_reg_read_write *cmd_resp =
3399                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3400         enum i40e_status_code status;
3401
3402         if (reg_val == NULL)
3403                 return I40E_ERR_PARAM;
3404
3405         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3406
3407         cmd_resp->address = CPU_TO_LE32(reg_addr);
3408
3409         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3410
3411         if (status == I40E_SUCCESS) {
3412                 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3413                            (u64)LE32_TO_CPU(cmd_resp->value_low);
3414         }
3415
3416         return status;
3417 }
3418
3419 /**
3420  * i40e_aq_debug_write_register
3421  * @hw: pointer to the hw struct
3422  * @reg_addr: register address
3423  * @reg_val: register value
3424  * @cmd_details: pointer to command details structure or NULL
3425  *
3426  * Write to a register using the admin queue commands
3427  **/
3428 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3429                                 u32 reg_addr, u64 reg_val,
3430                                 struct i40e_asq_cmd_details *cmd_details)
3431 {
3432         struct i40e_aq_desc desc;
3433         struct i40e_aqc_debug_reg_read_write *cmd =
3434                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3435         enum i40e_status_code status;
3436
3437         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3438
3439         cmd->address = CPU_TO_LE32(reg_addr);
3440         cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3441         cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3442
3443         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3444
3445         return status;
3446 }
3447
3448 /**
3449  * i40e_aq_request_resource
3450  * @hw: pointer to the hw struct
3451  * @resource: resource id
3452  * @access: access type
3453  * @sdp_number: resource number
3454  * @timeout: the maximum time in ms that the driver may hold the resource
3455  * @cmd_details: pointer to command details structure or NULL
3456  *
3457  * requests common resource using the admin queue commands
3458  **/
3459 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3460                                 enum i40e_aq_resources_ids resource,
3461                                 enum i40e_aq_resource_access_type access,
3462                                 u8 sdp_number, u64 *timeout,
3463                                 struct i40e_asq_cmd_details *cmd_details)
3464 {
3465         struct i40e_aq_desc desc;
3466         struct i40e_aqc_request_resource *cmd_resp =
3467                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3468         enum i40e_status_code status;
3469
3470         DEBUGFUNC("i40e_aq_request_resource");
3471
3472         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3473
3474         cmd_resp->resource_id = CPU_TO_LE16(resource);
3475         cmd_resp->access_type = CPU_TO_LE16(access);
3476         cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3477
3478         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3479         /* The completion specifies the maximum time in ms that the driver
3480          * may hold the resource in the Timeout field.
3481          * If the resource is held by someone else, the command completes with
3482          * busy return value and the timeout field indicates the maximum time
3483          * the current owner of the resource has to free it.
3484          */
3485         if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3486                 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3487
3488         return status;
3489 }
3490
3491 /**
3492  * i40e_aq_release_resource
3493  * @hw: pointer to the hw struct
3494  * @resource: resource id
3495  * @sdp_number: resource number
3496  * @cmd_details: pointer to command details structure or NULL
3497  *
3498  * release common resource using the admin queue commands
3499  **/
3500 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3501                                 enum i40e_aq_resources_ids resource,
3502                                 u8 sdp_number,
3503                                 struct i40e_asq_cmd_details *cmd_details)
3504 {
3505         struct i40e_aq_desc desc;
3506         struct i40e_aqc_request_resource *cmd =
3507                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3508         enum i40e_status_code status;
3509
3510         DEBUGFUNC("i40e_aq_release_resource");
3511
3512         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3513
3514         cmd->resource_id = CPU_TO_LE16(resource);
3515         cmd->resource_number = CPU_TO_LE32(sdp_number);
3516
3517         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3518
3519         return status;
3520 }
3521
3522 /**
3523  * i40e_aq_read_nvm
3524  * @hw: pointer to the hw struct
3525  * @module_pointer: module pointer location in words from the NVM beginning
3526  * @offset: byte offset from the module beginning
3527  * @length: length of the section to be read (in bytes from the offset)
3528  * @data: command buffer (size [bytes] = length)
3529  * @last_command: tells if this is the last command in a series
3530  * @cmd_details: pointer to command details structure or NULL
3531  *
3532  * Read the NVM using the admin queue commands
3533  **/
3534 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3535                                 u32 offset, u16 length, void *data,
3536                                 bool last_command,
3537                                 struct i40e_asq_cmd_details *cmd_details)
3538 {
3539         struct i40e_aq_desc desc;
3540         struct i40e_aqc_nvm_update *cmd =
3541                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3542         enum i40e_status_code status;
3543
3544         DEBUGFUNC("i40e_aq_read_nvm");
3545
3546         /* In offset the highest byte must be zeroed. */
3547         if (offset & 0xFF000000) {
3548                 status = I40E_ERR_PARAM;
3549                 goto i40e_aq_read_nvm_exit;
3550         }
3551
3552         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3553
3554         /* If this is the last command in a series, set the proper flag. */
3555         if (last_command)
3556                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3557         cmd->module_pointer = module_pointer;
3558         cmd->offset = CPU_TO_LE32(offset);
3559         cmd->length = CPU_TO_LE16(length);
3560
3561         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3562         if (length > I40E_AQ_LARGE_BUF)
3563                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3564
3565         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3566
3567 i40e_aq_read_nvm_exit:
3568         return status;
3569 }
3570
3571 /**
3572  * i40e_aq_read_nvm_config - read an nvm config block
3573  * @hw: pointer to the hw struct
3574  * @cmd_flags: NVM access admin command bits
3575  * @field_id: field or feature id
3576  * @data: buffer for result
3577  * @buf_size: buffer size
3578  * @element_count: pointer to count of elements read by FW
3579  * @cmd_details: pointer to command details structure or NULL
3580  **/
3581 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3582                                 u8 cmd_flags, u32 field_id, void *data,
3583                                 u16 buf_size, u16 *element_count,
3584                                 struct i40e_asq_cmd_details *cmd_details)
3585 {
3586         struct i40e_aq_desc desc;
3587         struct i40e_aqc_nvm_config_read *cmd =
3588                 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3589         enum i40e_status_code status;
3590
3591         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3592         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3593         if (buf_size > I40E_AQ_LARGE_BUF)
3594                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3595
3596         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3597         cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3598         if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3599                 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3600         else
3601                 cmd->element_id_msw = 0;
3602
3603         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3604
3605         if (!status && element_count)
3606                 *element_count = LE16_TO_CPU(cmd->element_count);
3607
3608         return status;
3609 }
3610
3611 /**
3612  * i40e_aq_write_nvm_config - write an nvm config block
3613  * @hw: pointer to the hw struct
3614  * @cmd_flags: NVM access admin command bits
3615  * @data: buffer for result
3616  * @buf_size: buffer size
3617  * @element_count: count of elements to be written
3618  * @cmd_details: pointer to command details structure or NULL
3619  **/
3620 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3621                                 u8 cmd_flags, void *data, u16 buf_size,
3622                                 u16 element_count,
3623                                 struct i40e_asq_cmd_details *cmd_details)
3624 {
3625         struct i40e_aq_desc desc;
3626         struct i40e_aqc_nvm_config_write *cmd =
3627                 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3628         enum i40e_status_code status;
3629
3630         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3631         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3632         if (buf_size > I40E_AQ_LARGE_BUF)
3633                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3634
3635         cmd->element_count = CPU_TO_LE16(element_count);
3636         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3637         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3638
3639         return status;
3640 }
3641
3642 /**
3643  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3644  * @hw: pointer to the hw struct
3645  * @buff: buffer for result
3646  * @buff_size: buffer size
3647  * @cmd_details: pointer to command details structure or NULL
3648  **/
3649 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3650                                 void *buff, u16 buff_size,
3651                                 struct i40e_asq_cmd_details *cmd_details)
3652 {
3653         struct i40e_aq_desc desc;
3654         enum i40e_status_code status;
3655
3656         UNREFERENCED_2PARAMETER(buff, buff_size);
3657
3658         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3659         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3660         if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3661                 status = I40E_ERR_NOT_IMPLEMENTED;
3662
3663         return status;
3664 }
3665
3666 /**
3667  * i40e_aq_erase_nvm
3668  * @hw: pointer to the hw struct
3669  * @module_pointer: module pointer location in words from the NVM beginning
3670  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3671  * @length: length of the section to be erased (expressed in 4 KB)
3672  * @last_command: tells if this is the last command in a series
3673  * @cmd_details: pointer to command details structure or NULL
3674  *
3675  * Erase the NVM sector using the admin queue commands
3676  **/
3677 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3678                                 u32 offset, u16 length, bool last_command,
3679                                 struct i40e_asq_cmd_details *cmd_details)
3680 {
3681         struct i40e_aq_desc desc;
3682         struct i40e_aqc_nvm_update *cmd =
3683                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3684         enum i40e_status_code status;
3685
3686         DEBUGFUNC("i40e_aq_erase_nvm");
3687
3688         /* In offset the highest byte must be zeroed. */
3689         if (offset & 0xFF000000) {
3690                 status = I40E_ERR_PARAM;
3691                 goto i40e_aq_erase_nvm_exit;
3692         }
3693
3694         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3695
3696         /* If this is the last command in a series, set the proper flag. */
3697         if (last_command)
3698                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3699         cmd->module_pointer = module_pointer;
3700         cmd->offset = CPU_TO_LE32(offset);
3701         cmd->length = CPU_TO_LE16(length);
3702
3703         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3704
3705 i40e_aq_erase_nvm_exit:
3706         return status;
3707 }
3708
3709 /**
3710  * i40e_parse_discover_capabilities
3711  * @hw: pointer to the hw struct
3712  * @buff: pointer to a buffer containing device/function capability records
3713  * @cap_count: number of capability records in the list
3714  * @list_type_opc: type of capabilities list to parse
3715  *
3716  * Parse the device/function capabilities list.
3717  **/
3718 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3719                                      u32 cap_count,
3720                                      enum i40e_admin_queue_opc list_type_opc)
3721 {
3722         struct i40e_aqc_list_capabilities_element_resp *cap;
3723         u32 valid_functions, num_functions;
3724         u32 number, logical_id, phys_id;
3725         struct i40e_hw_capabilities *p;
3726         enum i40e_status_code status;
3727         u16 id, ocp_cfg_word0;
3728         u8 major_rev;
3729         u32 i = 0;
3730
3731         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3732
3733         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3734                 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3735         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3736                 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3737         else
3738                 return;
3739
3740         for (i = 0; i < cap_count; i++, cap++) {
3741                 id = LE16_TO_CPU(cap->id);
3742                 number = LE32_TO_CPU(cap->number);
3743                 logical_id = LE32_TO_CPU(cap->logical_id);
3744                 phys_id = LE32_TO_CPU(cap->phys_id);
3745                 major_rev = cap->major_rev;
3746
3747                 switch (id) {
3748                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3749                         p->switch_mode = number;
3750                         i40e_debug(hw, I40E_DEBUG_INIT,
3751                                    "HW Capability: Switch mode = %d\n",
3752                                    p->switch_mode);
3753                         break;
3754                 case I40E_AQ_CAP_ID_MNG_MODE:
3755                         p->management_mode = number;
3756                         if (major_rev > 1) {
3757                                 p->mng_protocols_over_mctp = logical_id;
3758                                 i40e_debug(hw, I40E_DEBUG_INIT,
3759                                            "HW Capability: Protocols over MCTP = %d\n",
3760                                            p->mng_protocols_over_mctp);
3761                         } else {
3762                                 p->mng_protocols_over_mctp = 0;
3763                         }
3764                         i40e_debug(hw, I40E_DEBUG_INIT,
3765                                    "HW Capability: Management Mode = %d\n",
3766                                    p->management_mode);
3767                         break;
3768                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3769                         p->npar_enable = number;
3770                         i40e_debug(hw, I40E_DEBUG_INIT,
3771                                    "HW Capability: NPAR enable = %d\n",
3772                                    p->npar_enable);
3773                         break;
3774                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3775                         p->os2bmc = number;
3776                         i40e_debug(hw, I40E_DEBUG_INIT,
3777                                    "HW Capability: OS2BMC = %d\n", p->os2bmc);
3778                         break;
3779                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3780                         p->valid_functions = number;
3781                         i40e_debug(hw, I40E_DEBUG_INIT,
3782                                    "HW Capability: Valid Functions = %d\n",
3783                                    p->valid_functions);
3784                         break;
3785                 case I40E_AQ_CAP_ID_SRIOV:
3786                         if (number == 1)
3787                                 p->sr_iov_1_1 = true;
3788                         i40e_debug(hw, I40E_DEBUG_INIT,
3789                                    "HW Capability: SR-IOV = %d\n",
3790                                    p->sr_iov_1_1);
3791                         break;
3792                 case I40E_AQ_CAP_ID_VF:
3793                         p->num_vfs = number;
3794                         p->vf_base_id = logical_id;
3795                         i40e_debug(hw, I40E_DEBUG_INIT,
3796                                    "HW Capability: VF count = %d\n",
3797                                    p->num_vfs);
3798                         i40e_debug(hw, I40E_DEBUG_INIT,
3799                                    "HW Capability: VF base_id = %d\n",
3800                                    p->vf_base_id);
3801                         break;
3802                 case I40E_AQ_CAP_ID_VMDQ:
3803                         if (number == 1)
3804                                 p->vmdq = true;
3805                         i40e_debug(hw, I40E_DEBUG_INIT,
3806                                    "HW Capability: VMDQ = %d\n", p->vmdq);
3807                         break;
3808                 case I40E_AQ_CAP_ID_8021QBG:
3809                         if (number == 1)
3810                                 p->evb_802_1_qbg = true;
3811                         i40e_debug(hw, I40E_DEBUG_INIT,
3812                                    "HW Capability: 802.1Qbg = %d\n", number);
3813                         break;
3814                 case I40E_AQ_CAP_ID_8021QBR:
3815                         if (number == 1)
3816                                 p->evb_802_1_qbh = true;
3817                         i40e_debug(hw, I40E_DEBUG_INIT,
3818                                    "HW Capability: 802.1Qbh = %d\n", number);
3819                         break;
3820                 case I40E_AQ_CAP_ID_VSI:
3821                         p->num_vsis = number;
3822                         i40e_debug(hw, I40E_DEBUG_INIT,
3823                                    "HW Capability: VSI count = %d\n",
3824                                    p->num_vsis);
3825                         break;
3826                 case I40E_AQ_CAP_ID_DCB:
3827                         if (number == 1) {
3828                                 p->dcb = true;
3829                                 p->enabled_tcmap = logical_id;
3830                                 p->maxtc = phys_id;
3831                         }
3832                         i40e_debug(hw, I40E_DEBUG_INIT,
3833                                    "HW Capability: DCB = %d\n", p->dcb);
3834                         i40e_debug(hw, I40E_DEBUG_INIT,
3835                                    "HW Capability: TC Mapping = %d\n",
3836                                    logical_id);
3837                         i40e_debug(hw, I40E_DEBUG_INIT,
3838                                    "HW Capability: TC Max = %d\n", p->maxtc);
3839                         break;
3840                 case I40E_AQ_CAP_ID_FCOE:
3841                         if (number == 1)
3842                                 p->fcoe = true;
3843                         i40e_debug(hw, I40E_DEBUG_INIT,
3844                                    "HW Capability: FCOE = %d\n", p->fcoe);
3845                         break;
3846                 case I40E_AQ_CAP_ID_ISCSI:
3847                         if (number == 1)
3848                                 p->iscsi = true;
3849                         i40e_debug(hw, I40E_DEBUG_INIT,
3850                                    "HW Capability: iSCSI = %d\n", p->iscsi);
3851                         break;
3852                 case I40E_AQ_CAP_ID_RSS:
3853                         p->rss = true;
3854                         p->rss_table_size = number;
3855                         p->rss_table_entry_width = logical_id;
3856                         i40e_debug(hw, I40E_DEBUG_INIT,
3857                                    "HW Capability: RSS = %d\n", p->rss);
3858                         i40e_debug(hw, I40E_DEBUG_INIT,
3859                                    "HW Capability: RSS table size = %d\n",
3860                                    p->rss_table_size);
3861                         i40e_debug(hw, I40E_DEBUG_INIT,
3862                                    "HW Capability: RSS table width = %d\n",
3863                                    p->rss_table_entry_width);
3864                         break;
3865                 case I40E_AQ_CAP_ID_RXQ:
3866                         p->num_rx_qp = number;
3867                         p->base_queue = phys_id;
3868                         i40e_debug(hw, I40E_DEBUG_INIT,
3869                                    "HW Capability: Rx QP = %d\n", number);
3870                         i40e_debug(hw, I40E_DEBUG_INIT,
3871                                    "HW Capability: base_queue = %d\n",
3872                                    p->base_queue);
3873                         break;
3874                 case I40E_AQ_CAP_ID_TXQ:
3875                         p->num_tx_qp = number;
3876                         p->base_queue = phys_id;
3877                         i40e_debug(hw, I40E_DEBUG_INIT,
3878                                    "HW Capability: Tx QP = %d\n", number);
3879                         i40e_debug(hw, I40E_DEBUG_INIT,
3880                                    "HW Capability: base_queue = %d\n",
3881                                    p->base_queue);
3882                         break;
3883                 case I40E_AQ_CAP_ID_MSIX:
3884                         p->num_msix_vectors = number;
3885                         i40e_debug(hw, I40E_DEBUG_INIT,
3886                                    "HW Capability: MSIX vector count = %d\n",
3887                                    p->num_msix_vectors);
3888                         break;
3889                 case I40E_AQ_CAP_ID_VF_MSIX:
3890                         p->num_msix_vectors_vf = number;
3891                         i40e_debug(hw, I40E_DEBUG_INIT,
3892                                    "HW Capability: MSIX VF vector count = %d\n",
3893                                    p->num_msix_vectors_vf);
3894                         break;
3895                 case I40E_AQ_CAP_ID_FLEX10:
3896                         if (major_rev == 1) {
3897                                 if (number == 1) {
3898                                         p->flex10_enable = true;
3899                                         p->flex10_capable = true;
3900                                 }
3901                         } else {
3902                                 /* Capability revision >= 2 */
3903                                 if (number & 1)
3904                                         p->flex10_enable = true;
3905                                 if (number & 2)
3906                                         p->flex10_capable = true;
3907                         }
3908                         p->flex10_mode = logical_id;
3909                         p->flex10_status = phys_id;
3910                         i40e_debug(hw, I40E_DEBUG_INIT,
3911                                    "HW Capability: Flex10 mode = %d\n",
3912                                    p->flex10_mode);
3913                         i40e_debug(hw, I40E_DEBUG_INIT,
3914                                    "HW Capability: Flex10 status = %d\n",
3915                                    p->flex10_status);
3916                         break;
3917                 case I40E_AQ_CAP_ID_CEM:
3918                         if (number == 1)
3919                                 p->mgmt_cem = true;
3920                         i40e_debug(hw, I40E_DEBUG_INIT,
3921                                    "HW Capability: CEM = %d\n", p->mgmt_cem);
3922                         break;
3923                 case I40E_AQ_CAP_ID_IWARP:
3924                         if (number == 1)
3925                                 p->iwarp = true;
3926                         i40e_debug(hw, I40E_DEBUG_INIT,
3927                                    "HW Capability: iWARP = %d\n", p->iwarp);
3928                         break;
3929                 case I40E_AQ_CAP_ID_LED:
3930                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3931                                 p->led[phys_id] = true;
3932                         i40e_debug(hw, I40E_DEBUG_INIT,
3933                                    "HW Capability: LED - PIN %d\n", phys_id);
3934                         break;
3935                 case I40E_AQ_CAP_ID_SDP:
3936                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3937                                 p->sdp[phys_id] = true;
3938                         i40e_debug(hw, I40E_DEBUG_INIT,
3939                                    "HW Capability: SDP - PIN %d\n", phys_id);
3940                         break;
3941                 case I40E_AQ_CAP_ID_MDIO:
3942                         if (number == 1) {
3943                                 p->mdio_port_num = phys_id;
3944                                 p->mdio_port_mode = logical_id;
3945                         }
3946                         i40e_debug(hw, I40E_DEBUG_INIT,
3947                                    "HW Capability: MDIO port number = %d\n",
3948                                    p->mdio_port_num);
3949                         i40e_debug(hw, I40E_DEBUG_INIT,
3950                                    "HW Capability: MDIO port mode = %d\n",
3951                                    p->mdio_port_mode);
3952                         break;
3953                 case I40E_AQ_CAP_ID_1588:
3954                         if (number == 1)
3955                                 p->ieee_1588 = true;
3956                         i40e_debug(hw, I40E_DEBUG_INIT,
3957                                    "HW Capability: IEEE 1588 = %d\n",
3958                                    p->ieee_1588);
3959                         break;
3960                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3961                         p->fd = true;
3962                         p->fd_filters_guaranteed = number;
3963                         p->fd_filters_best_effort = logical_id;
3964                         i40e_debug(hw, I40E_DEBUG_INIT,
3965                                    "HW Capability: Flow Director = 1\n");
3966                         i40e_debug(hw, I40E_DEBUG_INIT,
3967                                    "HW Capability: Guaranteed FD filters = %d\n",
3968                                    p->fd_filters_guaranteed);
3969                         break;
3970                 case I40E_AQ_CAP_ID_WSR_PROT:
3971                         p->wr_csr_prot = (u64)number;
3972                         p->wr_csr_prot |= (u64)logical_id << 32;
3973                         i40e_debug(hw, I40E_DEBUG_INIT,
3974                                    "HW Capability: wr_csr_prot = 0x%llX\n\n",
3975                                    (p->wr_csr_prot & 0xffff));
3976                         break;
3977                 case I40E_AQ_CAP_ID_NVM_MGMT:
3978                         if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3979                                 p->sec_rev_disabled = true;
3980                         if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3981                                 p->update_disabled = true;
3982                         break;
3983                 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3984                         hw->num_wol_proxy_filters = (u16)number;
3985                         hw->wol_proxy_vsi_seid = (u16)logical_id;
3986                         p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3987                         if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3988                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3989                         else
3990                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3991                         p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3992                         i40e_debug(hw, I40E_DEBUG_INIT,
3993                                    "HW Capability: WOL proxy filters = %d\n",
3994                                    hw->num_wol_proxy_filters);
3995                         break;
3996                 default:
3997                         break;
3998                 }
3999         }
4000
4001         if (p->fcoe)
4002                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
4003
4004         /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
4005         p->fcoe = false;
4006
4007         /* count the enabled ports (aka the "not disabled" ports) */
4008         hw->num_ports = 0;
4009         for (i = 0; i < 4; i++) {
4010                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
4011                 u64 port_cfg = 0;
4012
4013                 /* use AQ read to get the physical register offset instead
4014                  * of the port relative offset
4015                  */
4016                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
4017                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
4018                         hw->num_ports++;
4019         }
4020
4021         /* OCP cards case: if a mezz is removed the ethernet port is at
4022          * disabled state in PRTGEN_CNF register. Additional NVM read is
4023          * needed in order to check if we are dealing with OCP card.
4024          * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting
4025          * physical ports results in wrong partition id calculation and thus
4026          * not supporting WoL.
4027          */
4028         if (hw->mac.type == I40E_MAC_X722) {
4029                 if (i40e_acquire_nvm(hw, I40E_RESOURCE_READ) == I40E_SUCCESS) {
4030                         status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR,
4031                                                   2 * I40E_SR_OCP_CFG_WORD0,
4032                                                   sizeof(ocp_cfg_word0),
4033                                                   &ocp_cfg_word0, true, NULL);
4034                         if (status == I40E_SUCCESS &&
4035                             (ocp_cfg_word0 & I40E_SR_OCP_ENABLED))
4036                                 hw->num_ports = 4;
4037                         i40e_release_nvm(hw);
4038                 }
4039         }
4040
4041         valid_functions = p->valid_functions;
4042         num_functions = 0;
4043         while (valid_functions) {
4044                 if (valid_functions & 1)
4045                         num_functions++;
4046                 valid_functions >>= 1;
4047         }
4048
4049         /* partition id is 1-based, and functions are evenly spread
4050          * across the ports as partitions
4051          */
4052         if (hw->num_ports != 0) {
4053                 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
4054                 hw->num_partitions = num_functions / hw->num_ports;
4055         }
4056
4057         /* additional HW specific goodies that might
4058          * someday be HW version specific
4059          */
4060         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
4061 }
4062
4063 /**
4064  * i40e_aq_discover_capabilities
4065  * @hw: pointer to the hw struct
4066  * @buff: a virtual buffer to hold the capabilities
4067  * @buff_size: Size of the virtual buffer
4068  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
4069  * @list_type_opc: capabilities type to discover - pass in the command opcode
4070  * @cmd_details: pointer to command details structure or NULL
4071  *
4072  * Get the device capabilities descriptions from the firmware
4073  **/
4074 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
4075                                 void *buff, u16 buff_size, u16 *data_size,
4076                                 enum i40e_admin_queue_opc list_type_opc,
4077                                 struct i40e_asq_cmd_details *cmd_details)
4078 {
4079         struct i40e_aqc_list_capabilites *cmd;
4080         struct i40e_aq_desc desc;
4081         enum i40e_status_code status = I40E_SUCCESS;
4082
4083         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
4084
4085         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
4086                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
4087                 status = I40E_ERR_PARAM;
4088                 goto exit;
4089         }
4090
4091         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
4092
4093         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4094         if (buff_size > I40E_AQ_LARGE_BUF)
4095                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4096
4097         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4098         *data_size = LE16_TO_CPU(desc.datalen);
4099
4100         if (status)
4101                 goto exit;
4102
4103         i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
4104                                          list_type_opc);
4105
4106 exit:
4107         return status;
4108 }
4109
4110 /**
4111  * i40e_aq_update_nvm
4112  * @hw: pointer to the hw struct
4113  * @module_pointer: module pointer location in words from the NVM beginning
4114  * @offset: byte offset from the module beginning
4115  * @length: length of the section to be written (in bytes from the offset)
4116  * @data: command buffer (size [bytes] = length)
4117  * @last_command: tells if this is the last command in a series
4118  * @preservation_flags: Preservation mode flags
4119  * @cmd_details: pointer to command details structure or NULL
4120  *
4121  * Update the NVM using the admin queue commands
4122  **/
4123 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
4124                                 u32 offset, u16 length, void *data,
4125                                 bool last_command, u8 preservation_flags,
4126                                 struct i40e_asq_cmd_details *cmd_details)
4127 {
4128         struct i40e_aq_desc desc;
4129         struct i40e_aqc_nvm_update *cmd =
4130                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
4131         enum i40e_status_code status;
4132
4133         DEBUGFUNC("i40e_aq_update_nvm");
4134
4135         /* In offset the highest byte must be zeroed. */
4136         if (offset & 0xFF000000) {
4137                 status = I40E_ERR_PARAM;
4138                 goto i40e_aq_update_nvm_exit;
4139         }
4140
4141         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4142
4143         /* If this is the last command in a series, set the proper flag. */
4144         if (last_command)
4145                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
4146         if (hw->mac.type == I40E_MAC_X722) {
4147                 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED)
4148                         cmd->command_flags |=
4149                                 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED <<
4150                                  I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4151                 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL)
4152                         cmd->command_flags |=
4153                                 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL <<
4154                                  I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4155         }
4156         cmd->module_pointer = module_pointer;
4157         cmd->offset = CPU_TO_LE32(offset);
4158         cmd->length = CPU_TO_LE16(length);
4159
4160         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4161         if (length > I40E_AQ_LARGE_BUF)
4162                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4163
4164         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
4165
4166 i40e_aq_update_nvm_exit:
4167         return status;
4168 }
4169
4170 /**
4171  * i40e_aq_rearrange_nvm
4172  * @hw: pointer to the hw struct
4173  * @rearrange_nvm: defines direction of rearrangement
4174  * @cmd_details: pointer to command details structure or NULL
4175  *
4176  * Rearrange NVM structure, available only for transition FW
4177  **/
4178 enum i40e_status_code i40e_aq_rearrange_nvm(struct i40e_hw *hw,
4179                                 u8 rearrange_nvm,
4180                                 struct i40e_asq_cmd_details *cmd_details)
4181 {
4182         struct i40e_aqc_nvm_update *cmd;
4183         enum i40e_status_code status;
4184         struct i40e_aq_desc desc;
4185
4186         DEBUGFUNC("i40e_aq_rearrange_nvm");
4187
4188         cmd = (struct i40e_aqc_nvm_update *)&desc.params.raw;
4189
4190         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4191
4192         rearrange_nvm &= (I40E_AQ_NVM_REARRANGE_TO_FLAT |
4193                          I40E_AQ_NVM_REARRANGE_TO_STRUCT);
4194
4195         if (!rearrange_nvm) {
4196                 status = I40E_ERR_PARAM;
4197                 goto i40e_aq_rearrange_nvm_exit;
4198         }
4199
4200         cmd->command_flags |= rearrange_nvm;
4201         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4202
4203 i40e_aq_rearrange_nvm_exit:
4204         return status;
4205 }
4206
4207 /**
4208  * i40e_aq_nvm_progress
4209  * @hw: pointer to the hw struct
4210  * @progress: pointer to progress returned from AQ
4211  * @cmd_details: pointer to command details structure or NULL
4212  *
4213  * Gets progress of flash rearrangement process
4214  **/
4215 enum i40e_status_code i40e_aq_nvm_progress(struct i40e_hw *hw, u8 *progress,
4216                                 struct i40e_asq_cmd_details *cmd_details)
4217 {
4218         enum i40e_status_code status;
4219         struct i40e_aq_desc desc;
4220
4221         DEBUGFUNC("i40e_aq_nvm_progress");
4222
4223         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_progress);
4224         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4225         *progress = desc.params.raw[0];
4226         return status;
4227 }
4228
4229 /**
4230  * i40e_aq_get_lldp_mib
4231  * @hw: pointer to the hw struct
4232  * @bridge_type: type of bridge requested
4233  * @mib_type: Local, Remote or both Local and Remote MIBs
4234  * @buff: pointer to a user supplied buffer to store the MIB block
4235  * @buff_size: size of the buffer (in bytes)
4236  * @local_len : length of the returned Local LLDP MIB
4237  * @remote_len: length of the returned Remote LLDP MIB
4238  * @cmd_details: pointer to command details structure or NULL
4239  *
4240  * Requests the complete LLDP MIB (entire packet).
4241  **/
4242 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4243                                 u8 mib_type, void *buff, u16 buff_size,
4244                                 u16 *local_len, u16 *remote_len,
4245                                 struct i40e_asq_cmd_details *cmd_details)
4246 {
4247         struct i40e_aq_desc desc;
4248         struct i40e_aqc_lldp_get_mib *cmd =
4249                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4250         struct i40e_aqc_lldp_get_mib *resp =
4251                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4252         enum i40e_status_code status;
4253
4254         if (buff_size == 0 || !buff)
4255                 return I40E_ERR_PARAM;
4256
4257         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4258         /* Indirect Command */
4259         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4260
4261         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4262         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4263                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4264
4265         desc.datalen = CPU_TO_LE16(buff_size);
4266
4267         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4268         if (buff_size > I40E_AQ_LARGE_BUF)
4269                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4270
4271         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4272         if (!status) {
4273                 if (local_len != NULL)
4274                         *local_len = LE16_TO_CPU(resp->local_len);
4275                 if (remote_len != NULL)
4276                         *remote_len = LE16_TO_CPU(resp->remote_len);
4277         }
4278
4279         return status;
4280 }
4281
4282  /**
4283  * i40e_aq_set_lldp_mib - Set the LLDP MIB
4284  * @hw: pointer to the hw struct
4285  * @mib_type: Local, Remote or both Local and Remote MIBs
4286  * @buff: pointer to a user supplied buffer to store the MIB block
4287  * @buff_size: size of the buffer (in bytes)
4288  * @cmd_details: pointer to command details structure or NULL
4289  *
4290  * Set the LLDP MIB.
4291  **/
4292 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4293                                 u8 mib_type, void *buff, u16 buff_size,
4294                                 struct i40e_asq_cmd_details *cmd_details)
4295 {
4296         struct i40e_aq_desc desc;
4297         struct i40e_aqc_lldp_set_local_mib *cmd =
4298                 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4299         enum i40e_status_code status;
4300
4301         if (buff_size == 0 || !buff)
4302                 return I40E_ERR_PARAM;
4303
4304         i40e_fill_default_direct_cmd_desc(&desc,
4305                                 i40e_aqc_opc_lldp_set_local_mib);
4306         /* Indirect Command */
4307         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4308         if (buff_size > I40E_AQ_LARGE_BUF)
4309                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4310         desc.datalen = CPU_TO_LE16(buff_size);
4311
4312         cmd->type = mib_type;
4313         cmd->length = CPU_TO_LE16(buff_size);
4314         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)buff));
4315         cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4316
4317         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4318         return status;
4319 }
4320
4321 /**
4322  * i40e_aq_cfg_lldp_mib_change_event
4323  * @hw: pointer to the hw struct
4324  * @enable_update: Enable or Disable event posting
4325  * @cmd_details: pointer to command details structure or NULL
4326  *
4327  * Enable or Disable posting of an event on ARQ when LLDP MIB
4328  * associated with the interface changes
4329  **/
4330 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4331                                 bool enable_update,
4332                                 struct i40e_asq_cmd_details *cmd_details)
4333 {
4334         struct i40e_aq_desc desc;
4335         struct i40e_aqc_lldp_update_mib *cmd =
4336                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4337         enum i40e_status_code status;
4338
4339         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4340
4341         if (!enable_update)
4342                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4343
4344         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4345
4346         return status;
4347 }
4348
4349 /**
4350  * i40e_aq_restore_lldp
4351  * @hw: pointer to the hw struct
4352  * @setting: pointer to factory setting variable or NULL
4353  * @restore: True if factory settings should be restored
4354  * @cmd_details: pointer to command details structure or NULL
4355  *
4356  * Restore LLDP Agent factory settings if @restore set to True. In other case
4357  * only returns factory setting in AQ response.
4358  **/
4359 enum i40e_status_code
4360 i40e_aq_restore_lldp(struct i40e_hw *hw, u8 *setting, bool restore,
4361                      struct i40e_asq_cmd_details *cmd_details)
4362 {
4363         struct i40e_aq_desc desc;
4364         struct i40e_aqc_lldp_restore *cmd =
4365                 (struct i40e_aqc_lldp_restore *)&desc.params.raw;
4366         enum i40e_status_code status;
4367
4368         if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)) {
4369                 i40e_debug(hw, I40E_DEBUG_ALL,
4370                            "Restore LLDP not supported by current FW version.\n");
4371                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
4372         }
4373
4374         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_restore);
4375
4376         if (restore)
4377                 cmd->command |= I40E_AQ_LLDP_AGENT_RESTORE;
4378
4379         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4380
4381         if (setting)
4382                 *setting = cmd->command & 1;
4383
4384         return status;
4385 }
4386
4387 /**
4388  * i40e_aq_stop_lldp
4389  * @hw: pointer to the hw struct
4390  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4391  * @persist: True if stop of LLDP should be persistent across power cycles
4392  * @cmd_details: pointer to command details structure or NULL
4393  *
4394  * Stop or Shutdown the embedded LLDP Agent
4395  **/
4396 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4397                                 bool persist,
4398                                 struct i40e_asq_cmd_details *cmd_details)
4399 {
4400         struct i40e_aq_desc desc;
4401         struct i40e_aqc_lldp_stop *cmd =
4402                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4403         enum i40e_status_code status;
4404
4405         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4406
4407         if (shutdown_agent)
4408                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4409
4410         if (persist) {
4411                 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)
4412                         cmd->command |= I40E_AQ_LLDP_AGENT_STOP_PERSIST;
4413                 else
4414                         i40e_debug(hw, I40E_DEBUG_ALL,
4415                                    "Persistent Stop LLDP not supported by current FW version.\n");
4416         }
4417
4418         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4419
4420         return status;
4421 }
4422
4423 /**
4424  * i40e_aq_start_lldp
4425  * @hw: pointer to the hw struct
4426  * @persist: True if start of LLDP should be persistent across power cycles
4427  * @cmd_details: pointer to command details structure or NULL
4428  *
4429  * Start the embedded LLDP Agent on all ports.
4430  **/
4431 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4432                                 bool persist,
4433                                 struct i40e_asq_cmd_details *cmd_details)
4434 {
4435         struct i40e_aq_desc desc;
4436         struct i40e_aqc_lldp_start *cmd =
4437                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4438         enum i40e_status_code status;
4439
4440         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4441
4442         cmd->command = I40E_AQ_LLDP_AGENT_START;
4443
4444         if (persist) {
4445                 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)
4446                         cmd->command |= I40E_AQ_LLDP_AGENT_START_PERSIST;
4447                 else
4448                         i40e_debug(hw, I40E_DEBUG_ALL,
4449                                    "Persistent Start LLDP not supported by current FW version.\n");
4450         }
4451
4452         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4453
4454         return status;
4455 }
4456
4457 /**
4458  * i40e_aq_set_dcb_parameters
4459  * @hw: pointer to the hw struct
4460  * @cmd_details: pointer to command details structure or NULL
4461  * @dcb_enable: True if DCB configuration needs to be applied
4462  *
4463  **/
4464 enum i40e_status_code
4465 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable,
4466                            struct i40e_asq_cmd_details *cmd_details)
4467 {
4468         struct i40e_aq_desc desc;
4469         struct i40e_aqc_set_dcb_parameters *cmd =
4470                 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw;
4471         enum i40e_status_code status;
4472
4473         if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_STOPPABLE))
4474                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
4475
4476         i40e_fill_default_direct_cmd_desc(&desc,
4477                                           i40e_aqc_opc_set_dcb_parameters);
4478
4479         if (dcb_enable) {
4480                 cmd->valid_flags = I40E_DCB_VALID;
4481                 cmd->command = I40E_AQ_DCB_SET_AGENT;
4482         }
4483         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4484
4485         return status;
4486 }
4487
4488 /**
4489  * i40e_aq_get_cee_dcb_config
4490  * @hw: pointer to the hw struct
4491  * @buff: response buffer that stores CEE operational configuration
4492  * @buff_size: size of the buffer passed
4493  * @cmd_details: pointer to command details structure or NULL
4494  *
4495  * Get CEE DCBX mode operational configuration from firmware
4496  **/
4497 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4498                                 void *buff, u16 buff_size,
4499                                 struct i40e_asq_cmd_details *cmd_details)
4500 {
4501         struct i40e_aq_desc desc;
4502         enum i40e_status_code status;
4503
4504         if (buff_size == 0 || !buff)
4505                 return I40E_ERR_PARAM;
4506
4507         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4508
4509         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4510         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4511                                        cmd_details);
4512
4513         return status;
4514 }
4515
4516 /**
4517  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4518  * @hw: pointer to the hw struct
4519  * @start_agent: True if DCBx Agent needs to be Started
4520  *                              False if DCBx Agent needs to be Stopped
4521  * @cmd_details: pointer to command details structure or NULL
4522  *
4523  * Start/Stop the embedded dcbx Agent
4524  **/
4525 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4526                                 bool start_agent,
4527                                 struct i40e_asq_cmd_details *cmd_details)
4528 {
4529         struct i40e_aq_desc desc;
4530         struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4531                 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4532                                 &desc.params.raw;
4533         enum i40e_status_code status;
4534
4535         i40e_fill_default_direct_cmd_desc(&desc,
4536                                 i40e_aqc_opc_lldp_stop_start_spec_agent);
4537
4538         if (start_agent)
4539                 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4540
4541         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4542
4543         return status;
4544 }
4545
4546 /**
4547  * i40e_aq_add_udp_tunnel
4548  * @hw: pointer to the hw struct
4549  * @udp_port: the UDP port to add in Host byte order
4550  * @protocol_index: protocol index type
4551  * @filter_index: pointer to filter index
4552  * @cmd_details: pointer to command details structure or NULL
4553  *
4554  * Note: Firmware expects the udp_port value to be in Little Endian format,
4555  * and this function will call CPU_TO_LE16 to convert from Host byte order to
4556  * Little Endian order.
4557  **/
4558 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4559                                 u16 udp_port, u8 protocol_index,
4560                                 u8 *filter_index,
4561                                 struct i40e_asq_cmd_details *cmd_details)
4562 {
4563         struct i40e_aq_desc desc;
4564         struct i40e_aqc_add_udp_tunnel *cmd =
4565                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4566         struct i40e_aqc_del_udp_tunnel_completion *resp =
4567                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4568         enum i40e_status_code status;
4569
4570         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4571
4572         cmd->udp_port = CPU_TO_LE16(udp_port);
4573         cmd->protocol_type = protocol_index;
4574
4575         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4576
4577         if (!status && filter_index)
4578                 *filter_index = resp->index;
4579
4580         return status;
4581 }
4582
4583 /**
4584  * i40e_aq_del_udp_tunnel
4585  * @hw: pointer to the hw struct
4586  * @index: filter index
4587  * @cmd_details: pointer to command details structure or NULL
4588  **/
4589 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4590                                 struct i40e_asq_cmd_details *cmd_details)
4591 {
4592         struct i40e_aq_desc desc;
4593         struct i40e_aqc_remove_udp_tunnel *cmd =
4594                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4595         enum i40e_status_code status;
4596
4597         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4598
4599         cmd->index = index;
4600
4601         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4602
4603         return status;
4604 }
4605
4606 /**
4607  * i40e_aq_get_switch_resource_alloc (0x0204)
4608  * @hw: pointer to the hw struct
4609  * @num_entries: pointer to u8 to store the number of resource entries returned
4610  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
4611  *        to store the resource information for all resource types.  Each
4612  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
4613  * @count: size, in bytes, of the buffer provided
4614  * @cmd_details: pointer to command details structure or NULL
4615  *
4616  * Query the resources allocated to a function.
4617  **/
4618 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4619                         u8 *num_entries,
4620                         struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4621                         u16 count,
4622                         struct i40e_asq_cmd_details *cmd_details)
4623 {
4624         struct i40e_aq_desc desc;
4625         struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4626                 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4627         enum i40e_status_code status;
4628         u16 length = count * sizeof(*buf);
4629
4630         i40e_fill_default_direct_cmd_desc(&desc,
4631                                         i40e_aqc_opc_get_switch_resource_alloc);
4632
4633         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4634         if (length > I40E_AQ_LARGE_BUF)
4635                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4636
4637         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4638
4639         if (!status && num_entries)
4640                 *num_entries = cmd_resp->num_entries;
4641
4642         return status;
4643 }
4644
4645 /**
4646  * i40e_aq_delete_element - Delete switch element
4647  * @hw: pointer to the hw struct
4648  * @seid: the SEID to delete from the switch
4649  * @cmd_details: pointer to command details structure or NULL
4650  *
4651  * This deletes a switch element from the switch.
4652  **/
4653 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4654                                 struct i40e_asq_cmd_details *cmd_details)
4655 {
4656         struct i40e_aq_desc desc;
4657         struct i40e_aqc_switch_seid *cmd =
4658                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4659         enum i40e_status_code status;
4660
4661         if (seid == 0)
4662                 return I40E_ERR_PARAM;
4663
4664         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4665
4666         cmd->seid = CPU_TO_LE16(seid);
4667
4668         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4669
4670         return status;
4671 }
4672
4673 /**
4674  * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4675  * @hw: pointer to the hw struct
4676  * @flags: component flags
4677  * @mac_seid: uplink seid (MAC SEID)
4678  * @vsi_seid: connected vsi seid
4679  * @ret_seid: seid of create pv component
4680  *
4681  * This instantiates an i40e port virtualizer with specified flags.
4682  * Depending on specified flags the port virtualizer can act as a
4683  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4684  */
4685 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4686                                        u16 mac_seid, u16 vsi_seid,
4687                                        u16 *ret_seid)
4688 {
4689         struct i40e_aq_desc desc;
4690         struct i40e_aqc_add_update_pv *cmd =
4691                 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4692         struct i40e_aqc_add_update_pv_completion *resp =
4693                 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4694         enum i40e_status_code status;
4695
4696         if (vsi_seid == 0)
4697                 return I40E_ERR_PARAM;
4698
4699         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4700         cmd->command_flags = CPU_TO_LE16(flags);
4701         cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4702         cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4703
4704         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4705         if (!status && ret_seid)
4706                 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4707
4708         return status;
4709 }
4710
4711 /**
4712  * i40e_aq_add_tag - Add an S/E-tag
4713  * @hw: pointer to the hw struct
4714  * @direct_to_queue: should s-tag direct flow to a specific queue
4715  * @vsi_seid: VSI SEID to use this tag
4716  * @tag: value of the tag
4717  * @queue_num: queue number, only valid is direct_to_queue is true
4718  * @tags_used: return value, number of tags in use by this PF
4719  * @tags_free: return value, number of unallocated tags
4720  * @cmd_details: pointer to command details structure or NULL
4721  *
4722  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4723  * the number of tags allocated by the PF, and the number of unallocated
4724  * tags available.
4725  **/
4726 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4727                                 u16 vsi_seid, u16 tag, u16 queue_num,
4728                                 u16 *tags_used, u16 *tags_free,
4729                                 struct i40e_asq_cmd_details *cmd_details)
4730 {
4731         struct i40e_aq_desc desc;
4732         struct i40e_aqc_add_tag *cmd =
4733                 (struct i40e_aqc_add_tag *)&desc.params.raw;
4734         struct i40e_aqc_add_remove_tag_completion *resp =
4735                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4736         enum i40e_status_code status;
4737
4738         if (vsi_seid == 0)
4739                 return I40E_ERR_PARAM;
4740
4741         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4742
4743         cmd->seid = CPU_TO_LE16(vsi_seid);
4744         cmd->tag = CPU_TO_LE16(tag);
4745         if (direct_to_queue) {
4746                 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4747                 cmd->queue_number = CPU_TO_LE16(queue_num);
4748         }
4749
4750         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4751
4752         if (!status) {
4753                 if (tags_used != NULL)
4754                         *tags_used = LE16_TO_CPU(resp->tags_used);
4755                 if (tags_free != NULL)
4756                         *tags_free = LE16_TO_CPU(resp->tags_free);
4757         }
4758
4759         return status;
4760 }
4761
4762 /**
4763  * i40e_aq_remove_tag - Remove an S- or E-tag
4764  * @hw: pointer to the hw struct
4765  * @vsi_seid: VSI SEID this tag is associated with
4766  * @tag: value of the S-tag to delete
4767  * @tags_used: return value, number of tags in use by this PF
4768  * @tags_free: return value, number of unallocated tags
4769  * @cmd_details: pointer to command details structure or NULL
4770  *
4771  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4772  * the number of tags allocated by the PF, and the number of unallocated
4773  * tags available.
4774  **/
4775 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4776                                 u16 tag, u16 *tags_used, u16 *tags_free,
4777                                 struct i40e_asq_cmd_details *cmd_details)
4778 {
4779         struct i40e_aq_desc desc;
4780         struct i40e_aqc_remove_tag *cmd =
4781                 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4782         struct i40e_aqc_add_remove_tag_completion *resp =
4783                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4784         enum i40e_status_code status;
4785
4786         if (vsi_seid == 0)
4787                 return I40E_ERR_PARAM;
4788
4789         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4790
4791         cmd->seid = CPU_TO_LE16(vsi_seid);
4792         cmd->tag = CPU_TO_LE16(tag);
4793
4794         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4795
4796         if (!status) {
4797                 if (tags_used != NULL)
4798                         *tags_used = LE16_TO_CPU(resp->tags_used);
4799                 if (tags_free != NULL)
4800                         *tags_free = LE16_TO_CPU(resp->tags_free);
4801         }
4802
4803         return status;
4804 }
4805
4806 /**
4807  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4808  * @hw: pointer to the hw struct
4809  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4810  * @etag: value of E-tag to add
4811  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4812  * @buf: address of indirect buffer
4813  * @tags_used: return value, number of E-tags in use by this port
4814  * @tags_free: return value, number of unallocated M-tags
4815  * @cmd_details: pointer to command details structure or NULL
4816  *
4817  * This associates a multicast E-tag to a port virtualizer.  It will return
4818  * the number of tags allocated by the PF, and the number of unallocated
4819  * tags available.
4820  *
4821  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4822  * num_tags_in_buf long.
4823  **/
4824 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4825                                 u16 etag, u8 num_tags_in_buf, void *buf,
4826                                 u16 *tags_used, u16 *tags_free,
4827                                 struct i40e_asq_cmd_details *cmd_details)
4828 {
4829         struct i40e_aq_desc desc;
4830         struct i40e_aqc_add_remove_mcast_etag *cmd =
4831                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4832         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4833            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4834         enum i40e_status_code status;
4835         u16 length = sizeof(u16) * num_tags_in_buf;
4836
4837         if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4838                 return I40E_ERR_PARAM;
4839
4840         i40e_fill_default_direct_cmd_desc(&desc,
4841                                           i40e_aqc_opc_add_multicast_etag);
4842
4843         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4844         cmd->etag = CPU_TO_LE16(etag);
4845         cmd->num_unicast_etags = num_tags_in_buf;
4846
4847         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4848         if (length > I40E_AQ_LARGE_BUF)
4849                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4850
4851         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4852
4853         if (!status) {
4854                 if (tags_used != NULL)
4855                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4856                 if (tags_free != NULL)
4857                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4858         }
4859
4860         return status;
4861 }
4862
4863 /**
4864  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4865  * @hw: pointer to the hw struct
4866  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4867  * @etag: value of the E-tag to remove
4868  * @tags_used: return value, number of tags in use by this port
4869  * @tags_free: return value, number of unallocated tags
4870  * @cmd_details: pointer to command details structure or NULL
4871  *
4872  * This deletes an E-tag from the port virtualizer.  It will return
4873  * the number of tags allocated by the port, and the number of unallocated
4874  * tags available.
4875  **/
4876 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4877                                 u16 etag, u16 *tags_used, u16 *tags_free,
4878                                 struct i40e_asq_cmd_details *cmd_details)
4879 {
4880         struct i40e_aq_desc desc;
4881         struct i40e_aqc_add_remove_mcast_etag *cmd =
4882                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4883         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4884            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4885         enum i40e_status_code status;
4886
4887
4888         if (pv_seid == 0)
4889                 return I40E_ERR_PARAM;
4890
4891         i40e_fill_default_direct_cmd_desc(&desc,
4892                                           i40e_aqc_opc_remove_multicast_etag);
4893
4894         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4895         cmd->etag = CPU_TO_LE16(etag);
4896
4897         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4898
4899         if (!status) {
4900                 if (tags_used != NULL)
4901                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4902                 if (tags_free != NULL)
4903                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4904         }
4905
4906         return status;
4907 }
4908
4909 /**
4910  * i40e_aq_update_tag - Update an S/E-tag
4911  * @hw: pointer to the hw struct
4912  * @vsi_seid: VSI SEID using this S-tag
4913  * @old_tag: old tag value
4914  * @new_tag: new tag value
4915  * @tags_used: return value, number of tags in use by this PF
4916  * @tags_free: return value, number of unallocated tags
4917  * @cmd_details: pointer to command details structure or NULL
4918  *
4919  * This updates the value of the tag currently attached to this VSI
4920  * in the switch complex.  It will return the number of tags allocated
4921  * by the PF, and the number of unallocated tags available.
4922  **/
4923 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4924                                 u16 old_tag, u16 new_tag, u16 *tags_used,
4925                                 u16 *tags_free,
4926                                 struct i40e_asq_cmd_details *cmd_details)
4927 {
4928         struct i40e_aq_desc desc;
4929         struct i40e_aqc_update_tag *cmd =
4930                 (struct i40e_aqc_update_tag *)&desc.params.raw;
4931         struct i40e_aqc_update_tag_completion *resp =
4932                 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4933         enum i40e_status_code status;
4934
4935         if (vsi_seid == 0)
4936                 return I40E_ERR_PARAM;
4937
4938         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4939
4940         cmd->seid = CPU_TO_LE16(vsi_seid);
4941         cmd->old_tag = CPU_TO_LE16(old_tag);
4942         cmd->new_tag = CPU_TO_LE16(new_tag);
4943
4944         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4945
4946         if (!status) {
4947                 if (tags_used != NULL)
4948                         *tags_used = LE16_TO_CPU(resp->tags_used);
4949                 if (tags_free != NULL)
4950                         *tags_free = LE16_TO_CPU(resp->tags_free);
4951         }
4952
4953         return status;
4954 }
4955
4956 /**
4957  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4958  * @hw: pointer to the hw struct
4959  * @tcmap: TC map for request/release any ignore PFC condition
4960  * @request: request or release ignore PFC condition
4961  * @tcmap_ret: return TCs for which PFC is currently ignored
4962  * @cmd_details: pointer to command details structure or NULL
4963  *
4964  * This sends out request/release to ignore PFC condition for a TC.
4965  * It will return the TCs for which PFC is currently ignored.
4966  **/
4967 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4968                                 bool request, u8 *tcmap_ret,
4969                                 struct i40e_asq_cmd_details *cmd_details)
4970 {
4971         struct i40e_aq_desc desc;
4972         struct i40e_aqc_pfc_ignore *cmd_resp =
4973                 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4974         enum i40e_status_code status;
4975
4976         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4977
4978         if (request)
4979                 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4980
4981         cmd_resp->tc_bitmap = tcmap;
4982
4983         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4984
4985         if (!status) {
4986                 if (tcmap_ret != NULL)
4987                         *tcmap_ret = cmd_resp->tc_bitmap;
4988         }
4989
4990         return status;
4991 }
4992
4993 /**
4994  * i40e_aq_dcb_updated - DCB Updated Command
4995  * @hw: pointer to the hw struct
4996  * @cmd_details: pointer to command details structure or NULL
4997  *
4998  * When LLDP is handled in PF this command is used by the PF
4999  * to notify EMP that a DCB setting is modified.
5000  * When LLDP is handled in EMP this command is used by the PF
5001  * to notify EMP whenever one of the following parameters get
5002  * modified:
5003  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
5004  *   - PCIRTT in PRTDCB_GENC.PCIRTT
5005  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
5006  * EMP will return when the shared RPB settings have been
5007  * recomputed and modified. The retval field in the descriptor
5008  * will be set to 0 when RPB is modified.
5009  **/
5010 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
5011                                 struct i40e_asq_cmd_details *cmd_details)
5012 {
5013         struct i40e_aq_desc desc;
5014         enum i40e_status_code status;
5015
5016         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
5017
5018         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5019
5020         return status;
5021 }
5022
5023 /**
5024  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
5025  * @hw: pointer to the hw struct
5026  * @seid: defines the SEID of the switch for which the stats are requested
5027  * @vlan_id: the VLAN ID for which the statistics are requested
5028  * @stat_index: index of the statistics counters block assigned to this VLAN
5029  * @cmd_details: pointer to command details structure or NULL
5030  *
5031  * XL710 supports 128 smonVlanStats counters.This command is used to
5032  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
5033  * switch.
5034  **/
5035 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
5036                                 u16 vlan_id, u16 *stat_index,
5037                                 struct i40e_asq_cmd_details *cmd_details)
5038 {
5039         struct i40e_aq_desc desc;
5040         struct i40e_aqc_add_remove_statistics *cmd_resp =
5041                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5042         enum i40e_status_code status;
5043
5044         if ((seid == 0) || (stat_index == NULL))
5045                 return I40E_ERR_PARAM;
5046
5047         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
5048
5049         cmd_resp->seid = CPU_TO_LE16(seid);
5050         cmd_resp->vlan = CPU_TO_LE16(vlan_id);
5051
5052         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5053
5054         if (!status && stat_index)
5055                 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
5056
5057         return status;
5058 }
5059
5060 /**
5061  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
5062  * @hw: pointer to the hw struct
5063  * @seid: defines the SEID of the switch for which the stats are requested
5064  * @vlan_id: the VLAN ID for which the statistics are requested
5065  * @stat_index: index of the statistics counters block assigned to this VLAN
5066  * @cmd_details: pointer to command details structure or NULL
5067  *
5068  * XL710 supports 128 smonVlanStats counters.This command is used to
5069  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
5070  * switch.
5071  **/
5072 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
5073                                 u16 vlan_id, u16 stat_index,
5074                                 struct i40e_asq_cmd_details *cmd_details)
5075 {
5076         struct i40e_aq_desc desc;
5077         struct i40e_aqc_add_remove_statistics *cmd =
5078                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5079         enum i40e_status_code status;
5080
5081         if (seid == 0)
5082                 return I40E_ERR_PARAM;
5083
5084         i40e_fill_default_direct_cmd_desc(&desc,
5085                                           i40e_aqc_opc_remove_statistics);
5086
5087         cmd->seid = CPU_TO_LE16(seid);
5088         cmd->vlan  = CPU_TO_LE16(vlan_id);
5089         cmd->stat_index = CPU_TO_LE16(stat_index);
5090
5091         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5092
5093         return status;
5094 }
5095
5096 /**
5097  * i40e_aq_set_port_parameters - set physical port parameters.
5098  * @hw: pointer to the hw struct
5099  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
5100  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
5101  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
5102  * @double_vlan: if set double VLAN is enabled
5103  * @cmd_details: pointer to command details structure or NULL
5104  **/
5105 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
5106                                 u16 bad_frame_vsi, bool save_bad_pac,
5107                                 bool pad_short_pac, bool double_vlan,
5108                                 struct i40e_asq_cmd_details *cmd_details)
5109 {
5110         struct i40e_aqc_set_port_parameters *cmd;
5111         enum i40e_status_code status;
5112         struct i40e_aq_desc desc;
5113         u16 command_flags = 0;
5114
5115         cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
5116
5117         i40e_fill_default_direct_cmd_desc(&desc,
5118                                           i40e_aqc_opc_set_port_parameters);
5119
5120         cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
5121         if (save_bad_pac)
5122                 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
5123         if (pad_short_pac)
5124                 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
5125         if (double_vlan)
5126                 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
5127         cmd->command_flags = CPU_TO_LE16(command_flags);
5128
5129         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5130
5131         return status;
5132 }
5133
5134 /**
5135  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
5136  * @hw: pointer to the hw struct
5137  * @seid: seid for the physical port/switching component/vsi
5138  * @buff: Indirect buffer to hold data parameters and response
5139  * @buff_size: Indirect buffer size
5140  * @opcode: Tx scheduler AQ command opcode
5141  * @cmd_details: pointer to command details structure or NULL
5142  *
5143  * Generic command handler for Tx scheduler AQ commands
5144  **/
5145 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
5146                                 void *buff, u16 buff_size,
5147                                  enum i40e_admin_queue_opc opcode,
5148                                 struct i40e_asq_cmd_details *cmd_details)
5149 {
5150         struct i40e_aq_desc desc;
5151         struct i40e_aqc_tx_sched_ind *cmd =
5152                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
5153         enum i40e_status_code status;
5154         bool cmd_param_flag = false;
5155
5156         switch (opcode) {
5157         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
5158         case i40e_aqc_opc_configure_vsi_tc_bw:
5159         case i40e_aqc_opc_enable_switching_comp_ets:
5160         case i40e_aqc_opc_modify_switching_comp_ets:
5161         case i40e_aqc_opc_disable_switching_comp_ets:
5162         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
5163         case i40e_aqc_opc_configure_switching_comp_bw_config:
5164                 cmd_param_flag = true;
5165                 break;
5166         case i40e_aqc_opc_query_vsi_bw_config:
5167         case i40e_aqc_opc_query_vsi_ets_sla_config:
5168         case i40e_aqc_opc_query_switching_comp_ets_config:
5169         case i40e_aqc_opc_query_port_ets_config:
5170         case i40e_aqc_opc_query_switching_comp_bw_config:
5171                 cmd_param_flag = false;
5172                 break;
5173         default:
5174                 return I40E_ERR_PARAM;
5175         }
5176
5177         i40e_fill_default_direct_cmd_desc(&desc, opcode);
5178
5179         /* Indirect command */
5180         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5181         if (cmd_param_flag)
5182                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5183         if (buff_size > I40E_AQ_LARGE_BUF)
5184                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5185
5186         desc.datalen = CPU_TO_LE16(buff_size);
5187
5188         cmd->vsi_seid = CPU_TO_LE16(seid);
5189
5190         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5191
5192         return status;
5193 }
5194
5195 /**
5196  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5197  * @hw: pointer to the hw struct
5198  * @seid: VSI seid
5199  * @credit: BW limit credits (0 = disabled)
5200  * @max_credit: Max BW limit credits
5201  * @cmd_details: pointer to command details structure or NULL
5202  **/
5203 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5204                                 u16 seid, u16 credit, u8 max_credit,
5205                                 struct i40e_asq_cmd_details *cmd_details)
5206 {
5207         struct i40e_aq_desc desc;
5208         struct i40e_aqc_configure_vsi_bw_limit *cmd =
5209                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5210         enum i40e_status_code status;
5211
5212         i40e_fill_default_direct_cmd_desc(&desc,
5213                                           i40e_aqc_opc_configure_vsi_bw_limit);
5214
5215         cmd->vsi_seid = CPU_TO_LE16(seid);
5216         cmd->credit = CPU_TO_LE16(credit);
5217         cmd->max_credit = max_credit;
5218
5219         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5220
5221         return status;
5222 }
5223
5224 /**
5225  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5226  * @hw: pointer to the hw struct
5227  * @seid: switching component seid
5228  * @credit: BW limit credits (0 = disabled)
5229  * @max_bw: Max BW limit credits
5230  * @cmd_details: pointer to command details structure or NULL
5231  **/
5232 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5233                                 u16 seid, u16 credit, u8 max_bw,
5234                                 struct i40e_asq_cmd_details *cmd_details)
5235 {
5236         struct i40e_aq_desc desc;
5237         struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5238           (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5239         enum i40e_status_code status;
5240
5241         i40e_fill_default_direct_cmd_desc(&desc,
5242                                 i40e_aqc_opc_configure_switching_comp_bw_limit);
5243
5244         cmd->seid = CPU_TO_LE16(seid);
5245         cmd->credit = CPU_TO_LE16(credit);
5246         cmd->max_bw = max_bw;
5247
5248         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5249
5250         return status;
5251 }
5252
5253 /**
5254  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5255  * @hw: pointer to the hw struct
5256  * @seid: VSI seid
5257  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5258  * @cmd_details: pointer to command details structure or NULL
5259  **/
5260 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5261                         u16 seid,
5262                         struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5263                         struct i40e_asq_cmd_details *cmd_details)
5264 {
5265         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5266                                     i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5267                                     cmd_details);
5268 }
5269
5270 /**
5271  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5272  * @hw: pointer to the hw struct
5273  * @seid: VSI seid
5274  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5275  * @cmd_details: pointer to command details structure or NULL
5276  **/
5277 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5278                         u16 seid,
5279                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5280                         struct i40e_asq_cmd_details *cmd_details)
5281 {
5282         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5283                                     i40e_aqc_opc_configure_vsi_tc_bw,
5284                                     cmd_details);
5285 }
5286
5287 /**
5288  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5289  * @hw: pointer to the hw struct
5290  * @seid: seid of the switching component connected to Physical Port
5291  * @ets_data: Buffer holding ETS parameters
5292  * @opcode: Tx scheduler AQ command opcode
5293  * @cmd_details: pointer to command details structure or NULL
5294  **/
5295 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5296                 u16 seid,
5297                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5298                 enum i40e_admin_queue_opc opcode,
5299                 struct i40e_asq_cmd_details *cmd_details)
5300 {
5301         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5302                                     sizeof(*ets_data), opcode, cmd_details);
5303 }
5304
5305 /**
5306  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5307  * @hw: pointer to the hw struct
5308  * @seid: seid of the switching component
5309  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5310  * @cmd_details: pointer to command details structure or NULL
5311  **/
5312 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5313         u16 seid,
5314         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5315         struct i40e_asq_cmd_details *cmd_details)
5316 {
5317         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5318                             i40e_aqc_opc_configure_switching_comp_bw_config,
5319                             cmd_details);
5320 }
5321
5322 /**
5323  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5324  * @hw: pointer to the hw struct
5325  * @seid: seid of the switching component
5326  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5327  * @cmd_details: pointer to command details structure or NULL
5328  **/
5329 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5330         struct i40e_hw *hw, u16 seid,
5331         struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5332         struct i40e_asq_cmd_details *cmd_details)
5333 {
5334         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5335                             i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5336                             cmd_details);
5337 }
5338
5339 /**
5340  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5341  * @hw: pointer to the hw struct
5342  * @seid: seid of the VSI
5343  * @bw_data: Buffer to hold VSI BW configuration
5344  * @cmd_details: pointer to command details structure or NULL
5345  **/
5346 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5347                         u16 seid,
5348                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5349                         struct i40e_asq_cmd_details *cmd_details)
5350 {
5351         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5352                                     i40e_aqc_opc_query_vsi_bw_config,
5353                                     cmd_details);
5354 }
5355
5356 /**
5357  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5358  * @hw: pointer to the hw struct
5359  * @seid: seid of the VSI
5360  * @bw_data: Buffer to hold VSI BW configuration per TC
5361  * @cmd_details: pointer to command details structure or NULL
5362  **/
5363 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5364                         u16 seid,
5365                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5366                         struct i40e_asq_cmd_details *cmd_details)
5367 {
5368         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5369                                     i40e_aqc_opc_query_vsi_ets_sla_config,
5370                                     cmd_details);
5371 }
5372
5373 /**
5374  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5375  * @hw: pointer to the hw struct
5376  * @seid: seid of the switching component
5377  * @bw_data: Buffer to hold switching component's per TC BW config
5378  * @cmd_details: pointer to command details structure or NULL
5379  **/
5380 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5381                 u16 seid,
5382                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5383                 struct i40e_asq_cmd_details *cmd_details)
5384 {
5385         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5386                                    i40e_aqc_opc_query_switching_comp_ets_config,
5387                                    cmd_details);
5388 }
5389
5390 /**
5391  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5392  * @hw: pointer to the hw struct
5393  * @seid: seid of the VSI or switching component connected to Physical Port
5394  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5395  * @cmd_details: pointer to command details structure or NULL
5396  **/
5397 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5398                         u16 seid,
5399                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
5400                         struct i40e_asq_cmd_details *cmd_details)
5401 {
5402         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5403                                     i40e_aqc_opc_query_port_ets_config,
5404                                     cmd_details);
5405 }
5406
5407 /**
5408  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5409  * @hw: pointer to the hw struct
5410  * @seid: seid of the switching component
5411  * @bw_data: Buffer to hold switching component's BW configuration
5412  * @cmd_details: pointer to command details structure or NULL
5413  **/
5414 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5415                 u16 seid,
5416                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5417                 struct i40e_asq_cmd_details *cmd_details)
5418 {
5419         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5420                                     i40e_aqc_opc_query_switching_comp_bw_config,
5421                                     cmd_details);
5422 }
5423
5424 /**
5425  * i40e_validate_filter_settings
5426  * @hw: pointer to the hardware structure
5427  * @settings: Filter control settings
5428  *
5429  * Check and validate the filter control settings passed.
5430  * The function checks for the valid filter/context sizes being
5431  * passed for FCoE and PE.
5432  *
5433  * Returns I40E_SUCCESS if the values passed are valid and within
5434  * range else returns an error.
5435  **/
5436 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5437                                 struct i40e_filter_control_settings *settings)
5438 {
5439         u32 fcoe_cntx_size, fcoe_filt_size;
5440         u32 pe_cntx_size, pe_filt_size;
5441         u32 fcoe_fmax;
5442
5443         u32 val;
5444
5445         /* Validate FCoE settings passed */
5446         switch (settings->fcoe_filt_num) {
5447         case I40E_HASH_FILTER_SIZE_1K:
5448         case I40E_HASH_FILTER_SIZE_2K:
5449         case I40E_HASH_FILTER_SIZE_4K:
5450         case I40E_HASH_FILTER_SIZE_8K:
5451         case I40E_HASH_FILTER_SIZE_16K:
5452         case I40E_HASH_FILTER_SIZE_32K:
5453                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5454                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5455                 break;
5456         default:
5457                 return I40E_ERR_PARAM;
5458         }
5459
5460         switch (settings->fcoe_cntx_num) {
5461         case I40E_DMA_CNTX_SIZE_512:
5462         case I40E_DMA_CNTX_SIZE_1K:
5463         case I40E_DMA_CNTX_SIZE_2K:
5464         case I40E_DMA_CNTX_SIZE_4K:
5465                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5466                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5467                 break;
5468         default:
5469                 return I40E_ERR_PARAM;
5470         }
5471
5472         /* Validate PE settings passed */
5473         switch (settings->pe_filt_num) {
5474         case I40E_HASH_FILTER_SIZE_1K:
5475         case I40E_HASH_FILTER_SIZE_2K:
5476         case I40E_HASH_FILTER_SIZE_4K:
5477         case I40E_HASH_FILTER_SIZE_8K:
5478         case I40E_HASH_FILTER_SIZE_16K:
5479         case I40E_HASH_FILTER_SIZE_32K:
5480         case I40E_HASH_FILTER_SIZE_64K:
5481         case I40E_HASH_FILTER_SIZE_128K:
5482         case I40E_HASH_FILTER_SIZE_256K:
5483         case I40E_HASH_FILTER_SIZE_512K:
5484         case I40E_HASH_FILTER_SIZE_1M:
5485                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5486                 pe_filt_size <<= (u32)settings->pe_filt_num;
5487                 break;
5488         default:
5489                 return I40E_ERR_PARAM;
5490         }
5491
5492         switch (settings->pe_cntx_num) {
5493         case I40E_DMA_CNTX_SIZE_512:
5494         case I40E_DMA_CNTX_SIZE_1K:
5495         case I40E_DMA_CNTX_SIZE_2K:
5496         case I40E_DMA_CNTX_SIZE_4K:
5497         case I40E_DMA_CNTX_SIZE_8K:
5498         case I40E_DMA_CNTX_SIZE_16K:
5499         case I40E_DMA_CNTX_SIZE_32K:
5500         case I40E_DMA_CNTX_SIZE_64K:
5501         case I40E_DMA_CNTX_SIZE_128K:
5502         case I40E_DMA_CNTX_SIZE_256K:
5503                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5504                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5505                 break;
5506         default:
5507                 return I40E_ERR_PARAM;
5508         }
5509
5510         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5511         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5512         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5513                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5514         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
5515                 return I40E_ERR_INVALID_SIZE;
5516
5517         return I40E_SUCCESS;
5518 }
5519
5520 /**
5521  * i40e_set_filter_control
5522  * @hw: pointer to the hardware structure
5523  * @settings: Filter control settings
5524  *
5525  * Set the Queue Filters for PE/FCoE and enable filters required
5526  * for a single PF. It is expected that these settings are programmed
5527  * at the driver initialization time.
5528  **/
5529 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5530                                 struct i40e_filter_control_settings *settings)
5531 {
5532         enum i40e_status_code ret = I40E_SUCCESS;
5533         u32 hash_lut_size = 0;
5534         u32 val;
5535
5536         if (!settings)
5537                 return I40E_ERR_PARAM;
5538
5539         /* Validate the input settings */
5540         ret = i40e_validate_filter_settings(hw, settings);
5541         if (ret)
5542                 return ret;
5543
5544         /* Read the PF Queue Filter control register */
5545         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5546
5547         /* Program required PE hash buckets for the PF */
5548         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5549         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5550                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5551         /* Program required PE contexts for the PF */
5552         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5553         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5554                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5555
5556         /* Program required FCoE hash buckets for the PF */
5557         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5558         val |= ((u32)settings->fcoe_filt_num <<
5559                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5560                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5561         /* Program required FCoE DDP contexts for the PF */
5562         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5563         val |= ((u32)settings->fcoe_cntx_num <<
5564                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5565                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5566
5567         /* Program Hash LUT size for the PF */
5568         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5569         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5570                 hash_lut_size = 1;
5571         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5572                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5573
5574         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5575         if (settings->enable_fdir)
5576                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5577         if (settings->enable_ethtype)
5578                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5579         if (settings->enable_macvlan)
5580                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5581
5582         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5583
5584         return I40E_SUCCESS;
5585 }
5586
5587 /**
5588  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5589  * @hw: pointer to the hw struct
5590  * @mac_addr: MAC address to use in the filter
5591  * @ethtype: Ethertype to use in the filter
5592  * @flags: Flags that needs to be applied to the filter
5593  * @vsi_seid: seid of the control VSI
5594  * @queue: VSI queue number to send the packet to
5595  * @is_add: Add control packet filter if True else remove
5596  * @stats: Structure to hold information on control filter counts
5597  * @cmd_details: pointer to command details structure or NULL
5598  *
5599  * This command will Add or Remove control packet filter for a control VSI.
5600  * In return it will update the total number of perfect filter count in
5601  * the stats member.
5602  **/
5603 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5604                                 u8 *mac_addr, u16 ethtype, u16 flags,
5605                                 u16 vsi_seid, u16 queue, bool is_add,
5606                                 struct i40e_control_filter_stats *stats,
5607                                 struct i40e_asq_cmd_details *cmd_details)
5608 {
5609         struct i40e_aq_desc desc;
5610         struct i40e_aqc_add_remove_control_packet_filter *cmd =
5611                 (struct i40e_aqc_add_remove_control_packet_filter *)
5612                 &desc.params.raw;
5613         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5614                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5615                 &desc.params.raw;
5616         enum i40e_status_code status;
5617
5618         if (vsi_seid == 0)
5619                 return I40E_ERR_PARAM;
5620
5621         if (is_add) {
5622                 i40e_fill_default_direct_cmd_desc(&desc,
5623                                 i40e_aqc_opc_add_control_packet_filter);
5624                 cmd->queue = CPU_TO_LE16(queue);
5625         } else {
5626                 i40e_fill_default_direct_cmd_desc(&desc,
5627                                 i40e_aqc_opc_remove_control_packet_filter);
5628         }
5629
5630         if (mac_addr)
5631                 i40e_memcpy(cmd->mac, mac_addr, ETH_ALEN,
5632                             I40E_NONDMA_TO_NONDMA);
5633
5634         cmd->etype = CPU_TO_LE16(ethtype);
5635         cmd->flags = CPU_TO_LE16(flags);
5636         cmd->seid = CPU_TO_LE16(vsi_seid);
5637
5638         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5639
5640         if (!status && stats) {
5641                 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5642                 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5643                 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5644                 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5645         }
5646
5647         return status;
5648 }
5649
5650 /**
5651  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5652  * @hw: pointer to the hw struct
5653  * @seid: VSI seid to add ethertype filter from
5654  **/
5655 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5656                                                     u16 seid)
5657 {
5658 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5659         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5660                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5661                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5662         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5663         enum i40e_status_code status;
5664
5665         status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5666                                                        seid, 0, true, NULL,
5667                                                        NULL);
5668         if (status)
5669                 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5670 }
5671
5672 /**
5673  * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5674  * @filters: list of cloud filters
5675  * @filter_count: length of list
5676  *
5677  * There's an issue in the device where the Geneve VNI layout needs
5678  * to be shifted 1 byte over from the VxLAN VNI
5679  **/
5680 STATIC void i40e_fix_up_geneve_vni(
5681         struct i40e_aqc_cloud_filters_element_data *filters,
5682         u8 filter_count)
5683 {
5684         struct i40e_aqc_cloud_filters_element_data *f = filters;
5685         int i;
5686
5687         for (i = 0; i < filter_count; i++) {
5688                 u16 tnl_type;
5689                 u32 ti;
5690
5691                 tnl_type = (LE16_TO_CPU(f[i].flags) &
5692                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5693                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5694                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5695                         ti = LE32_TO_CPU(f[i].tenant_id);
5696                         f[i].tenant_id = CPU_TO_LE32(ti << 8);
5697                 }
5698         }
5699 }
5700
5701 /**
5702  * i40e_aq_add_cloud_filters
5703  * @hw: pointer to the hardware structure
5704  * @seid: VSI seid to add cloud filters from
5705  * @filters: Buffer which contains the filters to be added
5706  * @filter_count: number of filters contained in the buffer
5707  *
5708  * Set the cloud filters for a given VSI.  The contents of the
5709  * i40e_aqc_cloud_filters_element_data are filled
5710  * in by the caller of the function.
5711  *
5712  **/
5713 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5714         u16 seid,
5715         struct i40e_aqc_cloud_filters_element_data *filters,
5716         u8 filter_count)
5717 {
5718         struct i40e_aq_desc desc;
5719         struct i40e_aqc_add_remove_cloud_filters *cmd =
5720         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5721         enum i40e_status_code status;
5722         u16 buff_len;
5723
5724         i40e_fill_default_direct_cmd_desc(&desc,
5725                                           i40e_aqc_opc_add_cloud_filters);
5726
5727         buff_len = filter_count * sizeof(*filters);
5728         desc.datalen = CPU_TO_LE16(buff_len);
5729         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5730         cmd->num_filters = filter_count;
5731         cmd->seid = CPU_TO_LE16(seid);
5732
5733         i40e_fix_up_geneve_vni(filters, filter_count);
5734
5735         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5736
5737         return status;
5738 }
5739
5740 /**
5741  * i40e_aq_add_cloud_filters_bb
5742  * @hw: pointer to the hardware structure
5743  * @seid: VSI seid to add cloud filters from
5744  * @filters: Buffer which contains the filters in big buffer to be added
5745  * @filter_count: number of filters contained in the buffer
5746  *
5747  * Set the cloud filters for a given VSI.  The contents of the
5748  * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5749  * the function.
5750  *
5751  **/
5752 enum i40e_status_code
5753 i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5754                              struct i40e_aqc_cloud_filters_element_bb *filters,
5755                              u8 filter_count)
5756 {
5757         struct i40e_aq_desc desc;
5758         struct i40e_aqc_add_remove_cloud_filters *cmd =
5759         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5760         enum i40e_status_code status;
5761         u16 buff_len;
5762         int i;
5763
5764         i40e_fill_default_direct_cmd_desc(&desc,
5765                                           i40e_aqc_opc_add_cloud_filters);
5766
5767         buff_len = filter_count * sizeof(*filters);
5768         desc.datalen = CPU_TO_LE16(buff_len);
5769         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5770         cmd->num_filters = filter_count;
5771         cmd->seid = CPU_TO_LE16(seid);
5772         cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5773
5774         for (i = 0; i < filter_count; i++) {
5775                 u16 tnl_type;
5776                 u32 ti;
5777
5778                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5779                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5780                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5781
5782                 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5783                  * one more byte further than normally used for Tenant ID in
5784                  * other tunnel types.
5785                  */
5786                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5787                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5788                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5789                 }
5790         }
5791
5792         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5793
5794         return status;
5795 }
5796
5797 /**
5798  * i40e_aq_rem_cloud_filters
5799  * @hw: pointer to the hardware structure
5800  * @seid: VSI seid to remove cloud filters from
5801  * @filters: Buffer which contains the filters to be removed
5802  * @filter_count: number of filters contained in the buffer
5803  *
5804  * Remove the cloud filters for a given VSI.  The contents of the
5805  * i40e_aqc_cloud_filters_element_data are filled in by the caller
5806  * of the function.
5807  *
5808  **/
5809 enum i40e_status_code
5810 i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid,
5811                           struct i40e_aqc_cloud_filters_element_data *filters,
5812                           u8 filter_count)
5813 {
5814         struct i40e_aq_desc desc;
5815         struct i40e_aqc_add_remove_cloud_filters *cmd =
5816         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5817         enum i40e_status_code status;
5818         u16 buff_len;
5819
5820         i40e_fill_default_direct_cmd_desc(&desc,
5821                                           i40e_aqc_opc_remove_cloud_filters);
5822
5823         buff_len = filter_count * sizeof(*filters);
5824         desc.datalen = CPU_TO_LE16(buff_len);
5825         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5826         cmd->num_filters = filter_count;
5827         cmd->seid = CPU_TO_LE16(seid);
5828
5829         i40e_fix_up_geneve_vni(filters, filter_count);
5830
5831         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5832
5833         return status;
5834 }
5835
5836 /**
5837  * i40e_aq_rem_cloud_filters_bb
5838  * @hw: pointer to the hardware structure
5839  * @seid: VSI seid to remove cloud filters from
5840  * @filters: Buffer which contains the filters in big buffer to be removed
5841  * @filter_count: number of filters contained in the buffer
5842  *
5843  * Remove the big buffer cloud filters for a given VSI.  The contents of the
5844  * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5845  * function.
5846  *
5847  **/
5848 enum i40e_status_code
5849 i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5850                              struct i40e_aqc_cloud_filters_element_bb *filters,
5851                              u8 filter_count)
5852 {
5853         struct i40e_aq_desc desc;
5854         struct i40e_aqc_add_remove_cloud_filters *cmd =
5855         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5856         enum i40e_status_code status;
5857         u16 buff_len;
5858         int i;
5859
5860         i40e_fill_default_direct_cmd_desc(&desc,
5861                                           i40e_aqc_opc_remove_cloud_filters);
5862
5863         buff_len = filter_count * sizeof(*filters);
5864         desc.datalen = CPU_TO_LE16(buff_len);
5865         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5866         cmd->num_filters = filter_count;
5867         cmd->seid = CPU_TO_LE16(seid);
5868         cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5869
5870         for (i = 0; i < filter_count; i++) {
5871                 u16 tnl_type;
5872                 u32 ti;
5873
5874                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5875                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5876                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5877
5878                 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5879                  * one more byte further than normally used for Tenant ID in
5880                  * other tunnel types.
5881                  */
5882                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5883                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5884                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5885                 }
5886         }
5887
5888         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5889
5890         return status;
5891 }
5892
5893 /**
5894  * i40e_aq_replace_cloud_filters - Replace cloud filter command
5895  * @hw: pointer to the hw struct
5896  * @filters: pointer to the i40e_aqc_replace_cloud_filter_cmd struct
5897  * @cmd_buf: pointer to the i40e_aqc_replace_cloud_filter_cmd_buf struct
5898  *
5899  **/
5900 enum
5901 i40e_status_code i40e_aq_replace_cloud_filters(struct i40e_hw *hw,
5902         struct i40e_aqc_replace_cloud_filters_cmd *filters,
5903         struct i40e_aqc_replace_cloud_filters_cmd_buf *cmd_buf)
5904 {
5905         struct i40e_aq_desc desc;
5906         struct i40e_aqc_replace_cloud_filters_cmd *cmd =
5907                 (struct i40e_aqc_replace_cloud_filters_cmd *)&desc.params.raw;
5908         enum i40e_status_code status = I40E_SUCCESS;
5909         int i = 0;
5910
5911         /* X722 doesn't support this command */
5912         if (hw->mac.type == I40E_MAC_X722)
5913                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
5914
5915         /* need FW version greater than 6.00 */
5916         if (hw->aq.fw_maj_ver < 6)
5917                 return I40E_NOT_SUPPORTED;
5918
5919         i40e_fill_default_direct_cmd_desc(&desc,
5920                                           i40e_aqc_opc_replace_cloud_filters);
5921
5922         desc.datalen = CPU_TO_LE16(32);
5923         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5924         cmd->old_filter_type = filters->old_filter_type;
5925         cmd->new_filter_type = filters->new_filter_type;
5926         cmd->valid_flags = filters->valid_flags;
5927         cmd->tr_bit = filters->tr_bit;
5928         cmd->tr_bit2 = filters->tr_bit2;
5929
5930         status = i40e_asq_send_command(hw, &desc, cmd_buf,
5931                 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf),  NULL);
5932
5933         /* for get cloud filters command */
5934         for (i = 0; i < 32; i += 4) {
5935                 cmd_buf->filters[i / 4].filter_type = cmd_buf->data[i];
5936                 cmd_buf->filters[i / 4].input[0] = cmd_buf->data[i + 1];
5937                 cmd_buf->filters[i / 4].input[1] = cmd_buf->data[i + 2];
5938                 cmd_buf->filters[i / 4].input[2] = cmd_buf->data[i + 3];
5939         }
5940
5941         return status;
5942 }
5943
5944
5945 /**
5946  * i40e_aq_alternate_write
5947  * @hw: pointer to the hardware structure
5948  * @reg_addr0: address of first dword to be read
5949  * @reg_val0: value to be written under 'reg_addr0'
5950  * @reg_addr1: address of second dword to be read
5951  * @reg_val1: value to be written under 'reg_addr1'
5952  *
5953  * Write one or two dwords to alternate structure. Fields are indicated
5954  * by 'reg_addr0' and 'reg_addr1' register numbers.
5955  *
5956  **/
5957 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5958                                 u32 reg_addr0, u32 reg_val0,
5959                                 u32 reg_addr1, u32 reg_val1)
5960 {
5961         struct i40e_aq_desc desc;
5962         struct i40e_aqc_alternate_write *cmd_resp =
5963                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5964         enum i40e_status_code status;
5965
5966         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5967         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5968         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5969         cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5970         cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5971
5972         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5973
5974         return status;
5975 }
5976
5977 /**
5978  * i40e_aq_alternate_write_indirect
5979  * @hw: pointer to the hardware structure
5980  * @addr: address of a first register to be modified
5981  * @dw_count: number of alternate structure fields to write
5982  * @buffer: pointer to the command buffer
5983  *
5984  * Write 'dw_count' dwords from 'buffer' to alternate structure
5985  * starting at 'addr'.
5986  *
5987  **/
5988 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5989                                 u32 addr, u32 dw_count, void *buffer)
5990 {
5991         struct i40e_aq_desc desc;
5992         struct i40e_aqc_alternate_ind_write *cmd_resp =
5993                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5994         enum i40e_status_code status;
5995
5996         if (buffer == NULL)
5997                 return I40E_ERR_PARAM;
5998
5999         /* Indirect command */
6000         i40e_fill_default_direct_cmd_desc(&desc,
6001                                          i40e_aqc_opc_alternate_write_indirect);
6002
6003         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6004         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6005         if (dw_count > (I40E_AQ_LARGE_BUF/4))
6006                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6007
6008         cmd_resp->address = CPU_TO_LE32(addr);
6009         cmd_resp->length = CPU_TO_LE32(dw_count);
6010
6011         status = i40e_asq_send_command(hw, &desc, buffer,
6012                                        I40E_LO_DWORD(4*dw_count), NULL);
6013
6014         return status;
6015 }
6016
6017 /**
6018  * i40e_aq_alternate_read
6019  * @hw: pointer to the hardware structure
6020  * @reg_addr0: address of first dword to be read
6021  * @reg_val0: pointer for data read from 'reg_addr0'
6022  * @reg_addr1: address of second dword to be read
6023  * @reg_val1: pointer for data read from 'reg_addr1'
6024  *
6025  * Read one or two dwords from alternate structure. Fields are indicated
6026  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
6027  * is not passed then only register at 'reg_addr0' is read.
6028  *
6029  **/
6030 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
6031                                 u32 reg_addr0, u32 *reg_val0,
6032                                 u32 reg_addr1, u32 *reg_val1)
6033 {
6034         struct i40e_aq_desc desc;
6035         struct i40e_aqc_alternate_write *cmd_resp =
6036                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
6037         enum i40e_status_code status;
6038
6039         if (reg_val0 == NULL)
6040                 return I40E_ERR_PARAM;
6041
6042         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
6043         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
6044         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
6045
6046         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6047
6048         if (status == I40E_SUCCESS) {
6049                 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
6050
6051                 if (reg_val1 != NULL)
6052                         *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
6053         }
6054
6055         return status;
6056 }
6057
6058 /**
6059  * i40e_aq_alternate_read_indirect
6060  * @hw: pointer to the hardware structure
6061  * @addr: address of the alternate structure field
6062  * @dw_count: number of alternate structure fields to read
6063  * @buffer: pointer to the command buffer
6064  *
6065  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
6066  * place them in 'buffer'. The buffer should be allocated by caller.
6067  *
6068  **/
6069 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
6070                                 u32 addr, u32 dw_count, void *buffer)
6071 {
6072         struct i40e_aq_desc desc;
6073         struct i40e_aqc_alternate_ind_write *cmd_resp =
6074                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
6075         enum i40e_status_code status;
6076
6077         if (buffer == NULL)
6078                 return I40E_ERR_PARAM;
6079
6080         /* Indirect command */
6081         i40e_fill_default_direct_cmd_desc(&desc,
6082                 i40e_aqc_opc_alternate_read_indirect);
6083
6084         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6085         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6086         if (dw_count > (I40E_AQ_LARGE_BUF/4))
6087                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6088
6089         cmd_resp->address = CPU_TO_LE32(addr);
6090         cmd_resp->length = CPU_TO_LE32(dw_count);
6091
6092         status = i40e_asq_send_command(hw, &desc, buffer,
6093                                        I40E_LO_DWORD(4*dw_count), NULL);
6094
6095         return status;
6096 }
6097
6098 /**
6099  *  i40e_aq_alternate_clear
6100  *  @hw: pointer to the HW structure.
6101  *
6102  *  Clear the alternate structures of the port from which the function
6103  *  is called.
6104  *
6105  **/
6106 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
6107 {
6108         struct i40e_aq_desc desc;
6109         enum i40e_status_code status;
6110
6111         i40e_fill_default_direct_cmd_desc(&desc,
6112                                           i40e_aqc_opc_alternate_clear_port);
6113
6114         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6115
6116         return status;
6117 }
6118
6119 /**
6120  *  i40e_aq_alternate_write_done
6121  *  @hw: pointer to the HW structure.
6122  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
6123  *  @reset_needed: indicates the SW should trigger GLOBAL reset
6124  *
6125  *  Indicates to the FW that alternate structures have been changed.
6126  *
6127  **/
6128 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
6129                 u8 bios_mode, bool *reset_needed)
6130 {
6131         struct i40e_aq_desc desc;
6132         struct i40e_aqc_alternate_write_done *cmd =
6133                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6134         enum i40e_status_code status;
6135
6136         if (reset_needed == NULL)
6137                 return I40E_ERR_PARAM;
6138
6139         i40e_fill_default_direct_cmd_desc(&desc,
6140                                           i40e_aqc_opc_alternate_write_done);
6141
6142         cmd->cmd_flags = CPU_TO_LE16(bios_mode);
6143
6144         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6145         if (!status && reset_needed)
6146                 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
6147                                  I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
6148
6149         return status;
6150 }
6151
6152 /**
6153  *  i40e_aq_set_oem_mode
6154  *  @hw: pointer to the HW structure.
6155  *  @oem_mode: the OEM mode to be used
6156  *
6157  *  Sets the device to a specific operating mode. Currently the only supported
6158  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
6159  *
6160  **/
6161 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
6162                 u8 oem_mode)
6163 {
6164         struct i40e_aq_desc desc;
6165         struct i40e_aqc_alternate_write_done *cmd =
6166                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6167         enum i40e_status_code status;
6168
6169         i40e_fill_default_direct_cmd_desc(&desc,
6170                                           i40e_aqc_opc_alternate_set_mode);
6171
6172         cmd->cmd_flags = CPU_TO_LE16(oem_mode);
6173
6174         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6175
6176         return status;
6177 }
6178
6179 /**
6180  * i40e_aq_resume_port_tx
6181  * @hw: pointer to the hardware structure
6182  * @cmd_details: pointer to command details structure or NULL
6183  *
6184  * Resume port's Tx traffic
6185  **/
6186 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
6187                                 struct i40e_asq_cmd_details *cmd_details)
6188 {
6189         struct i40e_aq_desc desc;
6190         enum i40e_status_code status;
6191
6192         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
6193
6194         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6195
6196         return status;
6197 }
6198
6199 /**
6200  * i40e_set_pci_config_data - store PCI bus info
6201  * @hw: pointer to hardware structure
6202  * @link_status: the link status word from PCI config space
6203  *
6204  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
6205  **/
6206 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
6207 {
6208         hw->bus.type = i40e_bus_type_pci_express;
6209
6210         switch (link_status & I40E_PCI_LINK_WIDTH) {
6211         case I40E_PCI_LINK_WIDTH_1:
6212                 hw->bus.width = i40e_bus_width_pcie_x1;
6213                 break;
6214         case I40E_PCI_LINK_WIDTH_2:
6215                 hw->bus.width = i40e_bus_width_pcie_x2;
6216                 break;
6217         case I40E_PCI_LINK_WIDTH_4:
6218                 hw->bus.width = i40e_bus_width_pcie_x4;
6219                 break;
6220         case I40E_PCI_LINK_WIDTH_8:
6221                 hw->bus.width = i40e_bus_width_pcie_x8;
6222                 break;
6223         default:
6224                 hw->bus.width = i40e_bus_width_unknown;
6225                 break;
6226         }
6227
6228         switch (link_status & I40E_PCI_LINK_SPEED) {
6229         case I40E_PCI_LINK_SPEED_2500:
6230                 hw->bus.speed = i40e_bus_speed_2500;
6231                 break;
6232         case I40E_PCI_LINK_SPEED_5000:
6233                 hw->bus.speed = i40e_bus_speed_5000;
6234                 break;
6235         case I40E_PCI_LINK_SPEED_8000:
6236                 hw->bus.speed = i40e_bus_speed_8000;
6237                 break;
6238         default:
6239                 hw->bus.speed = i40e_bus_speed_unknown;
6240                 break;
6241         }
6242 }
6243
6244 /**
6245  * i40e_aq_debug_dump
6246  * @hw: pointer to the hardware structure
6247  * @cluster_id: specific cluster to dump
6248  * @table_id: table id within cluster
6249  * @start_index: index of line in the block to read
6250  * @buff_size: dump buffer size
6251  * @buff: dump buffer
6252  * @ret_buff_size: actual buffer size returned
6253  * @ret_next_table: next block to read
6254  * @ret_next_index: next index to read
6255  * @cmd_details: pointer to command details structure or NULL
6256  *
6257  * Dump internal FW/HW data for debug purposes.
6258  *
6259  **/
6260 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
6261                                 u8 table_id, u32 start_index, u16 buff_size,
6262                                 void *buff, u16 *ret_buff_size,
6263                                 u8 *ret_next_table, u32 *ret_next_index,
6264                                 struct i40e_asq_cmd_details *cmd_details)
6265 {
6266         struct i40e_aq_desc desc;
6267         struct i40e_aqc_debug_dump_internals *cmd =
6268                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6269         struct i40e_aqc_debug_dump_internals *resp =
6270                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6271         enum i40e_status_code status;
6272
6273         if (buff_size == 0 || !buff)
6274                 return I40E_ERR_PARAM;
6275
6276         i40e_fill_default_direct_cmd_desc(&desc,
6277                                           i40e_aqc_opc_debug_dump_internals);
6278         /* Indirect Command */
6279         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6280         if (buff_size > I40E_AQ_LARGE_BUF)
6281                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6282
6283         cmd->cluster_id = cluster_id;
6284         cmd->table_id = table_id;
6285         cmd->idx = CPU_TO_LE32(start_index);
6286
6287         desc.datalen = CPU_TO_LE16(buff_size);
6288
6289         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
6290         if (!status) {
6291                 if (ret_buff_size != NULL)
6292                         *ret_buff_size = LE16_TO_CPU(desc.datalen);
6293                 if (ret_next_table != NULL)
6294                         *ret_next_table = resp->table_id;
6295                 if (ret_next_index != NULL)
6296                         *ret_next_index = LE32_TO_CPU(resp->idx);
6297         }
6298
6299         return status;
6300 }
6301
6302 /**
6303  * i40e_read_bw_from_alt_ram
6304  * @hw: pointer to the hardware structure
6305  * @max_bw: pointer for max_bw read
6306  * @min_bw: pointer for min_bw read
6307  * @min_valid: pointer for bool that is true if min_bw is a valid value
6308  * @max_valid: pointer for bool that is true if max_bw is a valid value
6309  *
6310  * Read bw from the alternate ram for the given pf
6311  **/
6312 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
6313                                         u32 *max_bw, u32 *min_bw,
6314                                         bool *min_valid, bool *max_valid)
6315 {
6316         enum i40e_status_code status;
6317         u32 max_bw_addr, min_bw_addr;
6318
6319         /* Calculate the address of the min/max bw registers */
6320         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6321                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
6322                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6323         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6324                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
6325                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6326
6327         /* Read the bandwidths from alt ram */
6328         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
6329                                         min_bw_addr, min_bw);
6330
6331         if (*min_bw & I40E_ALT_BW_VALID_MASK)
6332                 *min_valid = true;
6333         else
6334                 *min_valid = false;
6335
6336         if (*max_bw & I40E_ALT_BW_VALID_MASK)
6337                 *max_valid = true;
6338         else
6339                 *max_valid = false;
6340
6341         return status;
6342 }
6343
6344 /**
6345  * i40e_aq_configure_partition_bw
6346  * @hw: pointer to the hardware structure
6347  * @bw_data: Buffer holding valid pfs and bw limits
6348  * @cmd_details: pointer to command details
6349  *
6350  * Configure partitions guaranteed/max bw
6351  **/
6352 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6353                         struct i40e_aqc_configure_partition_bw_data *bw_data,
6354                         struct i40e_asq_cmd_details *cmd_details)
6355 {
6356         enum i40e_status_code status;
6357         struct i40e_aq_desc desc;
6358         u16 bwd_size = sizeof(*bw_data);
6359
6360         i40e_fill_default_direct_cmd_desc(&desc,
6361                                 i40e_aqc_opc_configure_partition_bw);
6362
6363         /* Indirect command */
6364         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6365         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6366
6367         desc.datalen = CPU_TO_LE16(bwd_size);
6368
6369         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6370
6371         return status;
6372 }
6373
6374 /**
6375  * i40e_read_phy_register_clause22
6376  * @hw: pointer to the HW structure
6377  * @reg: register address in the page
6378  * @phy_addr: PHY address on MDIO interface
6379  * @value: PHY register value
6380  *
6381  * Reads specified PHY register value
6382  **/
6383 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
6384                                         u16 reg, u8 phy_addr, u16 *value)
6385 {
6386         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6387         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6388         u32 command = 0;
6389         u16 retry = 1000;
6390
6391         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6392                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6393                   (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
6394                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6395                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6396         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6397         do {
6398                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6399                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6400                         status = I40E_SUCCESS;
6401                         break;
6402                 }
6403                 i40e_usec_delay(10);
6404                 retry--;
6405         } while (retry);
6406
6407         if (status) {
6408                 i40e_debug(hw, I40E_DEBUG_PHY,
6409                            "PHY: Can't write command to external PHY.\n");
6410         } else {
6411                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6412                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6413                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6414         }
6415
6416         return status;
6417 }
6418
6419 /**
6420  * i40e_write_phy_register_clause22
6421  * @hw: pointer to the HW structure
6422  * @reg: register address in the page
6423  * @phy_addr: PHY address on MDIO interface
6424  * @value: PHY register value
6425  *
6426  * Writes specified PHY register value
6427  **/
6428 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6429                                         u16 reg, u8 phy_addr, u16 value)
6430 {
6431         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6432         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6433         u32 command  = 0;
6434         u16 retry = 1000;
6435
6436         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6437         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6438
6439         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6440                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6441                   (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6442                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6443                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6444
6445         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6446         do {
6447                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6448                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6449                         status = I40E_SUCCESS;
6450                         break;
6451                 }
6452                 i40e_usec_delay(10);
6453                 retry--;
6454         } while (retry);
6455
6456         return status;
6457 }
6458
6459 /**
6460  * i40e_read_phy_register_clause45
6461  * @hw: pointer to the HW structure
6462  * @page: registers page number
6463  * @reg: register address in the page
6464  * @phy_addr: PHY address on MDIO interface
6465  * @value: PHY register value
6466  *
6467  * Reads specified PHY register value
6468  **/
6469 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6470                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6471 {
6472         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6473         u32 command  = 0;
6474         u16 retry = 1000;
6475         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6476
6477         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6478                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6479                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6480                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6481                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6482                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6483                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6484         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6485         do {
6486                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6487                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6488                         status = I40E_SUCCESS;
6489                         break;
6490                 }
6491                 i40e_usec_delay(10);
6492                 retry--;
6493         } while (retry);
6494
6495         if (status) {
6496                 i40e_debug(hw, I40E_DEBUG_PHY,
6497                            "PHY: Can't write command to external PHY.\n");
6498                 goto phy_read_end;
6499         }
6500
6501         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6502                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6503                   (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6504                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6505                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6506                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6507         status = I40E_ERR_TIMEOUT;
6508         retry = 1000;
6509         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6510         do {
6511                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6512                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6513                         status = I40E_SUCCESS;
6514                         break;
6515                 }
6516                 i40e_usec_delay(10);
6517                 retry--;
6518         } while (retry);
6519
6520         if (!status) {
6521                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6522                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6523                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6524         } else {
6525                 i40e_debug(hw, I40E_DEBUG_PHY,
6526                            "PHY: Can't read register value from external PHY.\n");
6527         }
6528
6529 phy_read_end:
6530         return status;
6531 }
6532
6533 /**
6534  * i40e_write_phy_register_clause45
6535  * @hw: pointer to the HW structure
6536  * @page: registers page number
6537  * @reg: register address in the page
6538  * @phy_addr: PHY address on MDIO interface
6539  * @value: PHY register value
6540  *
6541  * Writes value to specified PHY register
6542  **/
6543 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6544                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6545 {
6546         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6547         u32 command  = 0;
6548         u16 retry = 1000;
6549         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6550
6551         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6552                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6553                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6554                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6555                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6556                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6557                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6558         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6559         do {
6560                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6561                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6562                         status = I40E_SUCCESS;
6563                         break;
6564                 }
6565                 i40e_usec_delay(10);
6566                 retry--;
6567         } while (retry);
6568         if (status) {
6569                 i40e_debug(hw, I40E_DEBUG_PHY,
6570                            "PHY: Can't write command to external PHY.\n");
6571                 goto phy_write_end;
6572         }
6573
6574         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6575         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6576
6577         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6578                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6579                   (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6580                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6581                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6582                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6583         status = I40E_ERR_TIMEOUT;
6584         retry = 1000;
6585         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6586         do {
6587                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6588                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6589                         status = I40E_SUCCESS;
6590                         break;
6591                 }
6592                 i40e_usec_delay(10);
6593                 retry--;
6594         } while (retry);
6595
6596 phy_write_end:
6597         return status;
6598 }
6599
6600 /**
6601  * i40e_write_phy_register
6602  * @hw: pointer to the HW structure
6603  * @page: registers page number
6604  * @reg: register address in the page
6605  * @phy_addr: PHY address on MDIO interface
6606  * @value: PHY register value
6607  *
6608  * Writes value to specified PHY register
6609  **/
6610 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6611                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6612 {
6613         enum i40e_status_code status;
6614
6615         switch (hw->device_id) {
6616         case I40E_DEV_ID_1G_BASE_T_X722:
6617                 status = i40e_write_phy_register_clause22(hw,
6618                         reg, phy_addr, value);
6619                 break;
6620         case I40E_DEV_ID_10G_BASE_T:
6621         case I40E_DEV_ID_10G_BASE_T4:
6622         case I40E_DEV_ID_10G_BASE_T_BC:
6623         case I40E_DEV_ID_10G_BASE_T_X722:
6624         case I40E_DEV_ID_25G_B:
6625         case I40E_DEV_ID_25G_SFP28:
6626                 status = i40e_write_phy_register_clause45(hw,
6627                         page, reg, phy_addr, value);
6628                 break;
6629         default:
6630                 status = I40E_ERR_UNKNOWN_PHY;
6631                 break;
6632         }
6633
6634         return status;
6635 }
6636
6637 /**
6638  * i40e_read_phy_register
6639  * @hw: pointer to the HW structure
6640  * @page: registers page number
6641  * @reg: register address in the page
6642  * @phy_addr: PHY address on MDIO interface
6643  * @value: PHY register value
6644  *
6645  * Reads specified PHY register value
6646  **/
6647 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6648                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6649 {
6650         enum i40e_status_code status;
6651
6652         switch (hw->device_id) {
6653         case I40E_DEV_ID_1G_BASE_T_X722:
6654                 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6655                                                          value);
6656                 break;
6657         case I40E_DEV_ID_10G_BASE_T:
6658         case I40E_DEV_ID_10G_BASE_T4:
6659         case I40E_DEV_ID_10G_BASE_T_X722:
6660         case I40E_DEV_ID_25G_B:
6661         case I40E_DEV_ID_25G_SFP28:
6662                 status = i40e_read_phy_register_clause45(hw, page, reg,
6663                                                          phy_addr, value);
6664                 break;
6665         default:
6666                 status = I40E_ERR_UNKNOWN_PHY;
6667                 break;
6668         }
6669
6670         return status;
6671 }
6672
6673 /**
6674  * i40e_get_phy_address
6675  * @hw: pointer to the HW structure
6676  * @dev_num: PHY port num that address we want
6677  *
6678  * Gets PHY address for current port
6679  **/
6680 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6681 {
6682         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6683         u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6684
6685         return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6686 }
6687
6688 /**
6689  * i40e_blink_phy_led
6690  * @hw: pointer to the HW structure
6691  * @time: time how long led will blinks in secs
6692  * @interval: gap between LED on and off in msecs
6693  *
6694  * Blinks PHY link LED
6695  **/
6696 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6697                                               u32 time, u32 interval)
6698 {
6699         enum i40e_status_code status = I40E_SUCCESS;
6700         u32 i;
6701         u16 led_ctl = 0;
6702         u16 gpio_led_port;
6703         u16 led_reg;
6704         u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6705         u8 phy_addr = 0;
6706         u8 port_num;
6707
6708         i = rd32(hw, I40E_PFGEN_PORTNUM);
6709         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6710         phy_addr = i40e_get_phy_address(hw, port_num);
6711
6712         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6713              led_addr++) {
6714                 status = i40e_read_phy_register_clause45(hw,
6715                                                          I40E_PHY_COM_REG_PAGE,
6716                                                          led_addr, phy_addr,
6717                                                          &led_reg);
6718                 if (status)
6719                         goto phy_blinking_end;
6720                 led_ctl = led_reg;
6721                 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6722                         led_reg = 0;
6723                         status = i40e_write_phy_register_clause45(hw,
6724                                                          I40E_PHY_COM_REG_PAGE,
6725                                                          led_addr, phy_addr,
6726                                                          led_reg);
6727                         if (status)
6728                                 goto phy_blinking_end;
6729                         break;
6730                 }
6731         }
6732
6733         if (time > 0 && interval > 0) {
6734                 for (i = 0; i < time * 1000; i += interval) {
6735                         status = i40e_read_phy_register_clause45(hw,
6736                                                 I40E_PHY_COM_REG_PAGE,
6737                                                 led_addr, phy_addr, &led_reg);
6738                         if (status)
6739                                 goto restore_config;
6740                         if (led_reg & I40E_PHY_LED_MANUAL_ON)
6741                                 led_reg = 0;
6742                         else
6743                                 led_reg = I40E_PHY_LED_MANUAL_ON;
6744                         status = i40e_write_phy_register_clause45(hw,
6745                                                 I40E_PHY_COM_REG_PAGE,
6746                                                 led_addr, phy_addr, led_reg);
6747                         if (status)
6748                                 goto restore_config;
6749                         i40e_msec_delay(interval);
6750                 }
6751         }
6752
6753 restore_config:
6754         status = i40e_write_phy_register_clause45(hw,
6755                                                   I40E_PHY_COM_REG_PAGE,
6756                                                   led_addr, phy_addr, led_ctl);
6757
6758 phy_blinking_end:
6759         return status;
6760 }
6761
6762 /**
6763  * i40e_led_get_reg - read LED register
6764  * @hw: pointer to the HW structure
6765  * @led_addr: LED register address
6766  * @reg_val: read register value
6767  **/
6768 static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr,
6769                                               u32 *reg_val)
6770 {
6771         enum i40e_status_code status;
6772         u8 phy_addr = 0;
6773
6774         *reg_val = 0;
6775         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6776                 status = i40e_aq_get_phy_register(hw,
6777                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6778                                                 I40E_PHY_COM_REG_PAGE, true,
6779                                                 I40E_PHY_LED_PROV_REG_1,
6780                                                 reg_val, NULL);
6781         } else {
6782                 phy_addr = i40e_get_phy_address(hw, hw->port);
6783                 status = i40e_read_phy_register_clause45(hw,
6784                                                          I40E_PHY_COM_REG_PAGE,
6785                                                          led_addr, phy_addr,
6786                                                          (u16 *)reg_val);
6787         }
6788         return status;
6789 }
6790
6791 /**
6792  * i40e_led_set_reg - write LED register
6793  * @hw: pointer to the HW structure
6794  * @led_addr: LED register address
6795  * @reg_val: register value to write
6796  **/
6797 static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr,
6798                                               u32 reg_val)
6799 {
6800         enum i40e_status_code status;
6801         u8 phy_addr = 0;
6802
6803         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6804                 status = i40e_aq_set_phy_register(hw,
6805                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6806                                                 I40E_PHY_COM_REG_PAGE, true,
6807                                                 I40E_PHY_LED_PROV_REG_1,
6808                                                 reg_val, NULL);
6809         } else {
6810                 phy_addr = i40e_get_phy_address(hw, hw->port);
6811                 status = i40e_write_phy_register_clause45(hw,
6812                                                           I40E_PHY_COM_REG_PAGE,
6813                                                           led_addr, phy_addr,
6814                                                           (u16)reg_val);
6815         }
6816
6817         return status;
6818 }
6819
6820 /**
6821  * i40e_led_get_phy - return current on/off mode
6822  * @hw: pointer to the hw struct
6823  * @led_addr: address of led register to use
6824  * @val: original value of register to use
6825  *
6826  **/
6827 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6828                                        u16 *val)
6829 {
6830         enum i40e_status_code status = I40E_SUCCESS;
6831         u16 gpio_led_port;
6832         u32 reg_val_aq;
6833         u16 temp_addr;
6834         u8 phy_addr = 0;
6835         u16 reg_val;
6836
6837         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6838                 status = i40e_aq_get_phy_register(hw,
6839                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6840                                                 I40E_PHY_COM_REG_PAGE, true,
6841                                                 I40E_PHY_LED_PROV_REG_1,
6842                                                 &reg_val_aq, NULL);
6843                 if (status == I40E_SUCCESS)
6844                         *val = (u16)reg_val_aq;
6845                 return status;
6846         }
6847         temp_addr = I40E_PHY_LED_PROV_REG_1;
6848         phy_addr = i40e_get_phy_address(hw, hw->port);
6849         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6850              temp_addr++) {
6851                 status = i40e_read_phy_register_clause45(hw,
6852                                                          I40E_PHY_COM_REG_PAGE,
6853                                                          temp_addr, phy_addr,
6854                                                          &reg_val);
6855                 if (status)
6856                         return status;
6857                 *val = reg_val;
6858                 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6859                         *led_addr = temp_addr;
6860                         break;
6861                 }
6862         }
6863         return status;
6864 }
6865
6866 /**
6867  * i40e_led_set_phy
6868  * @hw: pointer to the HW structure
6869  * @on: true or false
6870  * @led_addr: address of led register to use
6871  * @mode: original val plus bit for set or ignore
6872  *
6873  * Set led's on or off when controlled by the PHY
6874  *
6875  **/
6876 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6877                                        u16 led_addr, u32 mode)
6878 {
6879         enum i40e_status_code status = I40E_SUCCESS;
6880         u32 led_ctl = 0;
6881         u32 led_reg = 0;
6882
6883         status = i40e_led_get_reg(hw, led_addr, &led_reg);
6884         if (status)
6885                 return status;
6886         led_ctl = led_reg;
6887         if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6888                 led_reg = 0;
6889                 status = i40e_led_set_reg(hw, led_addr, led_reg);
6890                 if (status)
6891                         return status;
6892         }
6893         status = i40e_led_get_reg(hw, led_addr, &led_reg);
6894         if (status)
6895                 goto restore_config;
6896         if (on)
6897                 led_reg = I40E_PHY_LED_MANUAL_ON;
6898         else
6899                 led_reg = 0;
6900         status = i40e_led_set_reg(hw, led_addr, led_reg);
6901         if (status)
6902                 goto restore_config;
6903         if (mode & I40E_PHY_LED_MODE_ORIG) {
6904                 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6905                 status = i40e_led_set_reg(hw, led_addr, led_ctl);
6906         }
6907         return status;
6908
6909 restore_config:
6910         status = i40e_led_set_reg(hw, led_addr, led_ctl);
6911         return status;
6912 }
6913 #endif /* PF_DRIVER */
6914
6915 /**
6916  * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6917  * @hw: pointer to the hw struct
6918  * @reg_addr: register address
6919  * @reg_val: ptr to register value
6920  * @cmd_details: pointer to command details structure or NULL
6921  *
6922  * Use the firmware to read the Rx control register,
6923  * especially useful if the Rx unit is under heavy pressure
6924  **/
6925 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6926                                 u32 reg_addr, u32 *reg_val,
6927                                 struct i40e_asq_cmd_details *cmd_details)
6928 {
6929         struct i40e_aq_desc desc;
6930         struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
6931                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6932         enum i40e_status_code status;
6933
6934         if (reg_val == NULL)
6935                 return I40E_ERR_PARAM;
6936
6937         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
6938
6939         cmd_resp->address = CPU_TO_LE32(reg_addr);
6940
6941         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6942
6943         if (status == I40E_SUCCESS)
6944                 *reg_val = LE32_TO_CPU(cmd_resp->value);
6945
6946         return status;
6947 }
6948
6949 /**
6950  * i40e_read_rx_ctl - read from an Rx control register
6951  * @hw: pointer to the hw struct
6952  * @reg_addr: register address
6953  **/
6954 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
6955 {
6956         enum i40e_status_code status = I40E_SUCCESS;
6957         bool use_register;
6958         int retry = 5;
6959         u32 val = 0;
6960
6961         use_register = (((hw->aq.api_maj_ver == 1) &&
6962                         (hw->aq.api_min_ver < 5)) ||
6963                         (hw->mac.type == I40E_MAC_X722));
6964         if (!use_register) {
6965 do_retry:
6966                 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
6967                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6968                         i40e_msec_delay(1);
6969                         retry--;
6970                         goto do_retry;
6971                 }
6972         }
6973
6974         /* if the AQ access failed, try the old-fashioned way */
6975         if (status || use_register)
6976                 val = rd32(hw, reg_addr);
6977
6978         return val;
6979 }
6980
6981 /**
6982  * i40e_aq_rx_ctl_write_register
6983  * @hw: pointer to the hw struct
6984  * @reg_addr: register address
6985  * @reg_val: register value
6986  * @cmd_details: pointer to command details structure or NULL
6987  *
6988  * Use the firmware to write to an Rx control register,
6989  * especially useful if the Rx unit is under heavy pressure
6990  **/
6991 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
6992                                 u32 reg_addr, u32 reg_val,
6993                                 struct i40e_asq_cmd_details *cmd_details)
6994 {
6995         struct i40e_aq_desc desc;
6996         struct i40e_aqc_rx_ctl_reg_read_write *cmd =
6997                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6998         enum i40e_status_code status;
6999
7000         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
7001
7002         cmd->address = CPU_TO_LE32(reg_addr);
7003         cmd->value = CPU_TO_LE32(reg_val);
7004
7005         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7006
7007         return status;
7008 }
7009
7010 /**
7011  * i40e_write_rx_ctl - write to an Rx control register
7012  * @hw: pointer to the hw struct
7013  * @reg_addr: register address
7014  * @reg_val: register value
7015  **/
7016 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
7017 {
7018         enum i40e_status_code status = I40E_SUCCESS;
7019         bool use_register;
7020         int retry = 5;
7021
7022         use_register = (((hw->aq.api_maj_ver == 1) &&
7023                         (hw->aq.api_min_ver < 5)) ||
7024                         (hw->mac.type == I40E_MAC_X722));
7025         if (!use_register) {
7026 do_retry:
7027                 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
7028                                                        reg_val, NULL);
7029                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
7030                         i40e_msec_delay(1);
7031                         retry--;
7032                         goto do_retry;
7033                 }
7034         }
7035
7036         /* if the AQ access failed, try the old-fashioned way */
7037         if (status || use_register)
7038                 wr32(hw, reg_addr, reg_val);
7039 }
7040
7041 #ifdef PF_DRIVER
7042 /**
7043  * i40e_aq_set_phy_register
7044  * @hw: pointer to the hw struct
7045  * @phy_select: select which phy should be accessed
7046  * @dev_addr: PHY device address
7047  * @page_change: enable auto page change
7048  * @reg_addr: PHY register address
7049  * @reg_val: new register value
7050  * @cmd_details: pointer to command details structure or NULL
7051  *
7052  * Write the external PHY register.
7053  **/
7054 enum i40e_status_code i40e_aq_set_phy_register(struct i40e_hw *hw,
7055                                 u8 phy_select, u8 dev_addr, bool page_change,
7056                                 u32 reg_addr, u32 reg_val,
7057                                 struct i40e_asq_cmd_details *cmd_details)
7058 {
7059         struct i40e_aq_desc desc;
7060         struct i40e_aqc_phy_register_access *cmd =
7061                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7062         enum i40e_status_code status;
7063
7064         i40e_fill_default_direct_cmd_desc(&desc,
7065                                           i40e_aqc_opc_set_phy_register);
7066
7067         cmd->phy_interface = phy_select;
7068         cmd->dev_addres = dev_addr;
7069         cmd->reg_address = CPU_TO_LE32(reg_addr);
7070         cmd->reg_value = CPU_TO_LE32(reg_val);
7071
7072         if (!page_change)
7073                 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
7074
7075         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7076
7077         return status;
7078 }
7079
7080 /**
7081  * i40e_aq_get_phy_register
7082  * @hw: pointer to the hw struct
7083  * @phy_select: select which phy should be accessed
7084  * @dev_addr: PHY device address
7085  * @page_change: enable auto page change
7086  * @reg_addr: PHY register address
7087  * @reg_val: read register value
7088  * @cmd_details: pointer to command details structure or NULL
7089  *
7090  * Read the external PHY register.
7091  **/
7092 enum i40e_status_code i40e_aq_get_phy_register(struct i40e_hw *hw,
7093                                 u8 phy_select, u8 dev_addr, bool page_change,
7094                                 u32 reg_addr, u32 *reg_val,
7095                                 struct i40e_asq_cmd_details *cmd_details)
7096 {
7097         struct i40e_aq_desc desc;
7098         struct i40e_aqc_phy_register_access *cmd =
7099                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7100         enum i40e_status_code status;
7101
7102         i40e_fill_default_direct_cmd_desc(&desc,
7103                                           i40e_aqc_opc_get_phy_register);
7104
7105         cmd->phy_interface = phy_select;
7106         cmd->dev_addres = dev_addr;
7107         cmd->reg_address = CPU_TO_LE32(reg_addr);
7108
7109         if (!page_change)
7110                 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
7111
7112         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7113         if (!status)
7114                 *reg_val = LE32_TO_CPU(cmd->reg_value);
7115
7116         return status;
7117 }
7118
7119 #endif /* PF_DRIVER */
7120 #ifdef VF_DRIVER
7121
7122 /**
7123  * i40e_aq_send_msg_to_pf
7124  * @hw: pointer to the hardware structure
7125  * @v_opcode: opcodes for VF-PF communication
7126  * @v_retval: return error code
7127  * @msg: pointer to the msg buffer
7128  * @msglen: msg length
7129  * @cmd_details: pointer to command details
7130  *
7131  * Send message to PF driver using admin queue. By default, this message
7132  * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
7133  * completion before returning.
7134  **/
7135 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
7136                                 enum virtchnl_ops v_opcode,
7137                                 enum i40e_status_code v_retval,
7138                                 u8 *msg, u16 msglen,
7139                                 struct i40e_asq_cmd_details *cmd_details)
7140 {
7141         struct i40e_aq_desc desc;
7142         struct i40e_asq_cmd_details details;
7143         enum i40e_status_code status;
7144
7145         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
7146         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
7147         desc.cookie_high = CPU_TO_LE32(v_opcode);
7148         desc.cookie_low = CPU_TO_LE32(v_retval);
7149         if (msglen) {
7150                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
7151                                                 | I40E_AQ_FLAG_RD));
7152                 if (msglen > I40E_AQ_LARGE_BUF)
7153                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7154                 desc.datalen = CPU_TO_LE16(msglen);
7155         }
7156         if (!cmd_details) {
7157                 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
7158                 details.async = true;
7159                 cmd_details = &details;
7160         }
7161         status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
7162                                        msglen, cmd_details);
7163         return status;
7164 }
7165
7166 /**
7167  * i40e_vf_parse_hw_config
7168  * @hw: pointer to the hardware structure
7169  * @msg: pointer to the virtual channel VF resource structure
7170  *
7171  * Given a VF resource message from the PF, populate the hw struct
7172  * with appropriate information.
7173  **/
7174 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
7175                              struct virtchnl_vf_resource *msg)
7176 {
7177         struct virtchnl_vsi_resource *vsi_res;
7178         int i;
7179
7180         vsi_res = &msg->vsi_res[0];
7181
7182         hw->dev_caps.num_vsis = msg->num_vsis;
7183         hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
7184         hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
7185         hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
7186         hw->dev_caps.dcb = msg->vf_cap_flags &
7187                            VIRTCHNL_VF_OFFLOAD_L2;
7188         hw->dev_caps.iwarp = (msg->vf_cap_flags &
7189                               VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
7190         for (i = 0; i < msg->num_vsis; i++) {
7191                 if (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) {
7192                         i40e_memcpy(hw->mac.perm_addr,
7193                                     vsi_res->default_mac_addr,
7194                                     ETH_ALEN,
7195                                     I40E_NONDMA_TO_NONDMA);
7196                         i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
7197                                     ETH_ALEN,
7198                                     I40E_NONDMA_TO_NONDMA);
7199                 }
7200                 vsi_res++;
7201         }
7202 }
7203
7204 /**
7205  * i40e_vf_reset
7206  * @hw: pointer to the hardware structure
7207  *
7208  * Send a VF_RESET message to the PF. Does not wait for response from PF
7209  * as none will be forthcoming. Immediately after calling this function,
7210  * the admin queue should be shut down and (optionally) reinitialized.
7211  **/
7212 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
7213 {
7214         return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF,
7215                                       I40E_SUCCESS, NULL, 0, NULL);
7216 }
7217 #endif /* VF_DRIVER */
7218
7219 /**
7220  * i40e_aq_set_arp_proxy_config
7221  * @hw: pointer to the HW structure
7222  * @proxy_config: pointer to proxy config command table struct
7223  * @cmd_details: pointer to command details
7224  *
7225  * Set ARP offload parameters from pre-populated
7226  * i40e_aqc_arp_proxy_data struct
7227  **/
7228 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
7229                                 struct i40e_aqc_arp_proxy_data *proxy_config,
7230                                 struct i40e_asq_cmd_details *cmd_details)
7231 {
7232         struct i40e_aq_desc desc;
7233         enum i40e_status_code status;
7234
7235         if (!proxy_config)
7236                 return I40E_ERR_PARAM;
7237
7238         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
7239
7240         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7241         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7242         desc.params.external.addr_high =
7243                                   CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
7244         desc.params.external.addr_low =
7245                                   CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
7246         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_arp_proxy_data));
7247
7248         status = i40e_asq_send_command(hw, &desc, proxy_config,
7249                                        sizeof(struct i40e_aqc_arp_proxy_data),
7250                                        cmd_details);
7251
7252         return status;
7253 }
7254
7255 /**
7256  * i40e_aq_opc_set_ns_proxy_table_entry
7257  * @hw: pointer to the HW structure
7258  * @ns_proxy_table_entry: pointer to NS table entry command struct
7259  * @cmd_details: pointer to command details
7260  *
7261  * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
7262  * from pre-populated i40e_aqc_ns_proxy_data struct
7263  **/
7264 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
7265                         struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
7266                         struct i40e_asq_cmd_details *cmd_details)
7267 {
7268         struct i40e_aq_desc desc;
7269         enum i40e_status_code status;
7270
7271         if (!ns_proxy_table_entry)
7272                 return I40E_ERR_PARAM;
7273
7274         i40e_fill_default_direct_cmd_desc(&desc,
7275                                 i40e_aqc_opc_set_ns_proxy_table_entry);
7276
7277         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7278         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7279         desc.params.external.addr_high =
7280                 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
7281         desc.params.external.addr_low =
7282                 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
7283         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_ns_proxy_data));
7284
7285         status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
7286                                        sizeof(struct i40e_aqc_ns_proxy_data),
7287                                        cmd_details);
7288
7289         return status;
7290 }
7291
7292 /**
7293  * i40e_aq_set_clear_wol_filter
7294  * @hw: pointer to the hw struct
7295  * @filter_index: index of filter to modify (0-7)
7296  * @filter: buffer containing filter to be set
7297  * @set_filter: true to set filter, false to clear filter
7298  * @no_wol_tco: if true, pass through packets cannot cause wake-up
7299  *              if false, pass through packets may cause wake-up
7300  * @filter_valid: true if filter action is valid
7301  * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
7302  * @cmd_details: pointer to command details structure or NULL
7303  *
7304  * Set or clear WoL filter for port attached to the PF
7305  **/
7306 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
7307                                 u8 filter_index,
7308                                 struct i40e_aqc_set_wol_filter_data *filter,
7309                                 bool set_filter, bool no_wol_tco,
7310                                 bool filter_valid, bool no_wol_tco_valid,
7311                                 struct i40e_asq_cmd_details *cmd_details)
7312 {
7313         struct i40e_aq_desc desc;
7314         struct i40e_aqc_set_wol_filter *cmd =
7315                 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
7316         enum i40e_status_code status;
7317         u16 cmd_flags = 0;
7318         u16 valid_flags = 0;
7319         u16 buff_len = 0;
7320
7321         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
7322
7323         if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
7324                 return  I40E_ERR_PARAM;
7325         cmd->filter_index = CPU_TO_LE16(filter_index);
7326
7327         if (set_filter) {
7328                 if (!filter)
7329                         return  I40E_ERR_PARAM;
7330
7331                 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
7332                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR;
7333         }
7334
7335         if (no_wol_tco)
7336                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
7337         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
7338
7339         if (filter_valid)
7340                 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
7341         if (no_wol_tco_valid)
7342                 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
7343         cmd->valid_flags = CPU_TO_LE16(valid_flags);
7344
7345         buff_len = sizeof(*filter);
7346         desc.datalen = CPU_TO_LE16(buff_len);
7347
7348         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7349         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7350
7351         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
7352         cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
7353
7354         status = i40e_asq_send_command(hw, &desc, filter,
7355                                        buff_len, cmd_details);
7356
7357         return status;
7358 }
7359
7360 /**
7361  * i40e_aq_get_wake_event_reason
7362  * @hw: pointer to the hw struct
7363  * @wake_reason: return value, index of matching filter
7364  * @cmd_details: pointer to command details structure or NULL
7365  *
7366  * Get information for the reason of a Wake Up event
7367  **/
7368 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
7369                                 u16 *wake_reason,
7370                                 struct i40e_asq_cmd_details *cmd_details)
7371 {
7372         struct i40e_aq_desc desc;
7373         struct i40e_aqc_get_wake_reason_completion *resp =
7374                 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
7375         enum i40e_status_code status;
7376
7377         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
7378
7379         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7380
7381         if (status == I40E_SUCCESS)
7382                 *wake_reason = LE16_TO_CPU(resp->wake_reason);
7383
7384         return status;
7385 }
7386
7387 /**
7388 * i40e_aq_clear_all_wol_filters
7389 * @hw: pointer to the hw struct
7390 * @cmd_details: pointer to command details structure or NULL
7391 *
7392 * Get information for the reason of a Wake Up event
7393 **/
7394 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw,
7395         struct i40e_asq_cmd_details *cmd_details)
7396 {
7397         struct i40e_aq_desc desc;
7398         enum i40e_status_code status;
7399
7400         i40e_fill_default_direct_cmd_desc(&desc,
7401                                           i40e_aqc_opc_clear_all_wol_filters);
7402
7403         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7404
7405         return status;
7406 }
7407
7408 /**
7409  * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
7410  * @hw: pointer to the hw struct
7411  * @buff: command buffer (size in bytes = buff_size)
7412  * @buff_size: buffer size in bytes
7413  * @track_id: package tracking id
7414  * @error_offset: returns error offset
7415  * @error_info: returns error information
7416  * @cmd_details: pointer to command details structure or NULL
7417  **/
7418 enum
7419 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
7420                                    u16 buff_size, u32 track_id,
7421                                    u32 *error_offset, u32 *error_info,
7422                                    struct i40e_asq_cmd_details *cmd_details)
7423 {
7424         struct i40e_aq_desc desc;
7425         struct i40e_aqc_write_personalization_profile *cmd =
7426                 (struct i40e_aqc_write_personalization_profile *)
7427                 &desc.params.raw;
7428         struct i40e_aqc_write_ddp_resp *resp;
7429         enum i40e_status_code status;
7430
7431         i40e_fill_default_direct_cmd_desc(&desc,
7432                                   i40e_aqc_opc_write_personalization_profile);
7433
7434         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
7435         if (buff_size > I40E_AQ_LARGE_BUF)
7436                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7437
7438         desc.datalen = CPU_TO_LE16(buff_size);
7439
7440         cmd->profile_track_id = CPU_TO_LE32(track_id);
7441
7442         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7443         if (!status) {
7444                 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
7445                 if (error_offset)
7446                         *error_offset = LE32_TO_CPU(resp->error_offset);
7447                 if (error_info)
7448                         *error_info = LE32_TO_CPU(resp->error_info);
7449         }
7450
7451         return status;
7452 }
7453
7454 /**
7455  * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
7456  * @hw: pointer to the hw struct
7457  * @buff: command buffer (size in bytes = buff_size)
7458  * @buff_size: buffer size in bytes
7459  * @flags: AdminQ command flags
7460  * @cmd_details: pointer to command details structure or NULL
7461  **/
7462 enum
7463 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
7464                                       u16 buff_size, u8 flags,
7465                                       struct i40e_asq_cmd_details *cmd_details)
7466 {
7467         struct i40e_aq_desc desc;
7468         struct i40e_aqc_get_applied_profiles *cmd =
7469                 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
7470         enum i40e_status_code status;
7471
7472         i40e_fill_default_direct_cmd_desc(&desc,
7473                           i40e_aqc_opc_get_personalization_profile_list);
7474
7475         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7476         if (buff_size > I40E_AQ_LARGE_BUF)
7477                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7478         desc.datalen = CPU_TO_LE16(buff_size);
7479
7480         cmd->flags = flags;
7481
7482         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7483
7484         return status;
7485 }
7486
7487 /**
7488  * i40e_find_segment_in_package
7489  * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
7490  * @pkg_hdr: pointer to the package header to be searched
7491  *
7492  * This function searches a package file for a particular segment type. On
7493  * success it returns a pointer to the segment header, otherwise it will
7494  * return NULL.
7495  **/
7496 struct i40e_generic_seg_header *
7497 i40e_find_segment_in_package(u32 segment_type,
7498                              struct i40e_package_header *pkg_hdr)
7499 {
7500         struct i40e_generic_seg_header *segment;
7501         u32 i;
7502
7503         /* Search all package segments for the requested segment type */
7504         for (i = 0; i < pkg_hdr->segment_count; i++) {
7505                 segment =
7506                         (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
7507                          pkg_hdr->segment_offset[i]);
7508
7509                 if (segment->type == segment_type)
7510                         return segment;
7511         }
7512
7513         return NULL;
7514 }
7515
7516 /* Get section table in profile */
7517 #define I40E_SECTION_TABLE(profile, sec_tbl)                            \
7518         do {                                                            \
7519                 struct i40e_profile_segment *p = (profile);             \
7520                 u32 count;                                              \
7521                 u32 *nvm;                                               \
7522                 count = p->device_table_count;                          \
7523                 nvm = (u32 *)&p->device_table[count];                   \
7524                 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \
7525         } while (0)
7526
7527 /* Get section header in profile */
7528 #define I40E_SECTION_HEADER(profile, offset)                            \
7529         (struct i40e_profile_section_header *)((u8 *)(profile) + (offset))
7530
7531 /**
7532  * i40e_find_section_in_profile
7533  * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE)
7534  * @profile: pointer to the i40e segment header to be searched
7535  *
7536  * This function searches i40e segment for a particular section type. On
7537  * success it returns a pointer to the section header, otherwise it will
7538  * return NULL.
7539  **/
7540 struct i40e_profile_section_header *
7541 i40e_find_section_in_profile(u32 section_type,
7542                              struct i40e_profile_segment *profile)
7543 {
7544         struct i40e_profile_section_header *sec;
7545         struct i40e_section_table *sec_tbl;
7546         u32 sec_off;
7547         u32 i;
7548
7549         if (profile->header.type != SEGMENT_TYPE_I40E)
7550                 return NULL;
7551
7552         I40E_SECTION_TABLE(profile, sec_tbl);
7553
7554         for (i = 0; i < sec_tbl->section_count; i++) {
7555                 sec_off = sec_tbl->section_offset[i];
7556                 sec = I40E_SECTION_HEADER(profile, sec_off);
7557                 if (sec->section.type == section_type)
7558                         return sec;
7559         }
7560
7561         return NULL;
7562 }
7563
7564 /**
7565  * i40e_ddp_exec_aq_section - Execute generic AQ for DDP
7566  * @hw: pointer to the hw struct
7567  * @aq: command buffer containing all data to execute AQ
7568  **/
7569 STATIC enum
7570 i40e_status_code i40e_ddp_exec_aq_section(struct i40e_hw *hw,
7571                                           struct i40e_profile_aq_section *aq)
7572 {
7573         enum i40e_status_code status;
7574         struct i40e_aq_desc desc;
7575         u8 *msg = NULL;
7576         u16 msglen;
7577
7578         i40e_fill_default_direct_cmd_desc(&desc, aq->opcode);
7579         desc.flags |= CPU_TO_LE16(aq->flags);
7580         i40e_memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw),
7581                     I40E_NONDMA_TO_NONDMA);
7582
7583         msglen = aq->datalen;
7584         if (msglen) {
7585                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
7586                                                 I40E_AQ_FLAG_RD));
7587                 if (msglen > I40E_AQ_LARGE_BUF)
7588                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7589                 desc.datalen = CPU_TO_LE16(msglen);
7590                 msg = &aq->data[0];
7591         }
7592
7593         status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL);
7594
7595         if (status != I40E_SUCCESS) {
7596                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7597                            "unable to exec DDP AQ opcode %u, error %d\n",
7598                            aq->opcode, status);
7599                 return status;
7600         }
7601
7602         /* copy returned desc to aq_buf */
7603         i40e_memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw),
7604                     I40E_NONDMA_TO_NONDMA);
7605
7606         return I40E_SUCCESS;
7607 }
7608
7609 /**
7610  * i40e_validate_profile
7611  * @hw: pointer to the hardware structure
7612  * @profile: pointer to the profile segment of the package to be validated
7613  * @track_id: package tracking id
7614  * @rollback: flag if the profile is for rollback.
7615  *
7616  * Validates supported devices and profile's sections.
7617  */
7618 STATIC enum i40e_status_code
7619 i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7620                       u32 track_id, bool rollback)
7621 {
7622         struct i40e_profile_section_header *sec = NULL;
7623         enum i40e_status_code status = I40E_SUCCESS;
7624         struct i40e_section_table *sec_tbl;
7625         u32 vendor_dev_id;
7626         u32 dev_cnt;
7627         u32 sec_off;
7628         u32 i;
7629
7630         if (track_id == I40E_DDP_TRACKID_INVALID) {
7631                 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n");
7632                 return I40E_NOT_SUPPORTED;
7633         }
7634
7635         dev_cnt = profile->device_table_count;
7636         for (i = 0; i < dev_cnt; i++) {
7637                 vendor_dev_id = profile->device_table[i].vendor_dev_id;
7638                 if ((vendor_dev_id >> 16) == I40E_INTEL_VENDOR_ID &&
7639                     hw->device_id == (vendor_dev_id & 0xFFFF))
7640                         break;
7641         }
7642         if (dev_cnt && (i == dev_cnt)) {
7643                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7644                            "Device doesn't support DDP\n");
7645                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
7646         }
7647
7648         I40E_SECTION_TABLE(profile, sec_tbl);
7649
7650         /* Validate sections types */
7651         for (i = 0; i < sec_tbl->section_count; i++) {
7652                 sec_off = sec_tbl->section_offset[i];
7653                 sec = I40E_SECTION_HEADER(profile, sec_off);
7654                 if (rollback) {
7655                         if (sec->section.type == SECTION_TYPE_MMIO ||
7656                             sec->section.type == SECTION_TYPE_AQ ||
7657                             sec->section.type == SECTION_TYPE_RB_AQ) {
7658                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7659                                            "Not a roll-back package\n");
7660                                 return I40E_NOT_SUPPORTED;
7661                         }
7662                 } else {
7663                         if (sec->section.type == SECTION_TYPE_RB_AQ ||
7664                             sec->section.type == SECTION_TYPE_RB_MMIO) {
7665                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7666                                            "Not an original package\n");
7667                                 return I40E_NOT_SUPPORTED;
7668                         }
7669                 }
7670         }
7671
7672         return status;
7673 }
7674
7675 /**
7676  * i40e_write_profile
7677  * @hw: pointer to the hardware structure
7678  * @profile: pointer to the profile segment of the package to be downloaded
7679  * @track_id: package tracking id
7680  *
7681  * Handles the download of a complete package.
7682  */
7683 enum i40e_status_code
7684 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7685                    u32 track_id)
7686 {
7687         enum i40e_status_code status = I40E_SUCCESS;
7688         struct i40e_section_table *sec_tbl;
7689         struct i40e_profile_section_header *sec = NULL;
7690         struct i40e_profile_aq_section *ddp_aq;
7691         u32 section_size = 0;
7692         u32 offset = 0, info = 0;
7693         u32 sec_off;
7694         u32 i;
7695
7696         status = i40e_validate_profile(hw, profile, track_id, false);
7697         if (status)
7698                 return status;
7699
7700         I40E_SECTION_TABLE(profile, sec_tbl);
7701
7702         for (i = 0; i < sec_tbl->section_count; i++) {
7703                 sec_off = sec_tbl->section_offset[i];
7704                 sec = I40E_SECTION_HEADER(profile, sec_off);
7705                 /* Process generic admin command */
7706                 if (sec->section.type == SECTION_TYPE_AQ) {
7707                         ddp_aq = (struct i40e_profile_aq_section *)&sec[1];
7708                         status = i40e_ddp_exec_aq_section(hw, ddp_aq);
7709                         if (status) {
7710                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7711                                            "Failed to execute aq: section %d, opcode %u\n",
7712                                            i, ddp_aq->opcode);
7713                                 break;
7714                         }
7715                         sec->section.type = SECTION_TYPE_RB_AQ;
7716                 }
7717
7718                 /* Skip any non-mmio sections */
7719                 if (sec->section.type != SECTION_TYPE_MMIO)
7720                         continue;
7721
7722                 section_size = sec->section.size +
7723                         sizeof(struct i40e_profile_section_header);
7724
7725                 /* Write MMIO section */
7726                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
7727                                            track_id, &offset, &info, NULL);
7728                 if (status) {
7729                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
7730                                    "Failed to write profile: section %d, offset %d, info %d\n",
7731                                    i, offset, info);
7732                         break;
7733                 }
7734         }
7735         return status;
7736 }
7737
7738 /**
7739  * i40e_rollback_profile
7740  * @hw: pointer to the hardware structure
7741  * @profile: pointer to the profile segment of the package to be removed
7742  * @track_id: package tracking id
7743  *
7744  * Rolls back previously loaded package.
7745  */
7746 enum i40e_status_code
7747 i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7748                       u32 track_id)
7749 {
7750         struct i40e_profile_section_header *sec = NULL;
7751         enum i40e_status_code status = I40E_SUCCESS;
7752         struct i40e_section_table *sec_tbl;
7753         u32 offset = 0, info = 0;
7754         u32 section_size = 0;
7755         u32 sec_off;
7756         int i;
7757
7758         status = i40e_validate_profile(hw, profile, track_id, true);
7759         if (status)
7760                 return status;
7761
7762         I40E_SECTION_TABLE(profile, sec_tbl);
7763
7764         /* For rollback write sections in reverse */
7765         for (i = sec_tbl->section_count - 1; i >= 0; i--) {
7766                 sec_off = sec_tbl->section_offset[i];
7767                 sec = I40E_SECTION_HEADER(profile, sec_off);
7768
7769                 /* Skip any non-rollback sections */
7770                 if (sec->section.type != SECTION_TYPE_RB_MMIO)
7771                         continue;
7772
7773                 section_size = sec->section.size +
7774                         sizeof(struct i40e_profile_section_header);
7775
7776                 /* Write roll-back MMIO section */
7777                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
7778                                            track_id, &offset, &info, NULL);
7779                 if (status) {
7780                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
7781                                    "Failed to write profile: section %d, offset %d, info %d\n",
7782                                    i, offset, info);
7783                         break;
7784                 }
7785         }
7786         return status;
7787 }
7788
7789 /**
7790  * i40e_add_pinfo_to_list
7791  * @hw: pointer to the hardware structure
7792  * @profile: pointer to the profile segment of the package
7793  * @profile_info_sec: buffer for information section
7794  * @track_id: package tracking id
7795  *
7796  * Register a profile to the list of loaded profiles.
7797  */
7798 enum i40e_status_code
7799 i40e_add_pinfo_to_list(struct i40e_hw *hw,
7800                        struct i40e_profile_segment *profile,
7801                        u8 *profile_info_sec, u32 track_id)
7802 {
7803         enum i40e_status_code status = I40E_SUCCESS;
7804         struct i40e_profile_section_header *sec = NULL;
7805         struct i40e_profile_info *pinfo;
7806         u32 offset = 0, info = 0;
7807
7808         sec = (struct i40e_profile_section_header *)profile_info_sec;
7809         sec->tbl_size = 1;
7810         sec->data_end = sizeof(struct i40e_profile_section_header) +
7811                         sizeof(struct i40e_profile_info);
7812         sec->section.type = SECTION_TYPE_INFO;
7813         sec->section.offset = sizeof(struct i40e_profile_section_header);
7814         sec->section.size = sizeof(struct i40e_profile_info);
7815         pinfo = (struct i40e_profile_info *)(profile_info_sec +
7816                                              sec->section.offset);
7817         pinfo->track_id = track_id;
7818         pinfo->version = profile->version;
7819         pinfo->op = I40E_DDP_ADD_TRACKID;
7820         i40e_memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE,
7821                     I40E_NONDMA_TO_NONDMA);
7822
7823         status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
7824                                    track_id, &offset, &info, NULL);
7825         return status;
7826 }