1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "i40e_type.h"
35 #include "i40e_adminq.h"
36 #include "i40e_prototype.h"
41 * i40e_set_mac_type - Sets MAC type
42 * @hw: pointer to the HW structure
44 * This function sets the mac type of the adapter based on the
45 * vendor ID and device ID stored in the hw structure.
47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
53 enum i40e_status_code status = I40E_SUCCESS;
55 DEBUGFUNC("i40e_set_mac_type\n");
57 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
58 switch (hw->device_id) {
59 case I40E_DEV_ID_SFP_XL710:
60 case I40E_DEV_ID_QEMU:
61 case I40E_DEV_ID_KX_B:
62 case I40E_DEV_ID_KX_C:
63 case I40E_DEV_ID_QSFP_A:
64 case I40E_DEV_ID_QSFP_B:
65 case I40E_DEV_ID_QSFP_C:
66 case I40E_DEV_ID_10G_BASE_T:
67 case I40E_DEV_ID_10G_BASE_T4:
68 case I40E_DEV_ID_20G_KR2:
69 case I40E_DEV_ID_20G_KR2_A:
70 case I40E_DEV_ID_25G_B:
71 case I40E_DEV_ID_25G_SFP28:
72 hw->mac.type = I40E_MAC_XL710;
74 #ifdef X722_A0_SUPPORT
75 case I40E_DEV_ID_X722_A0:
77 case I40E_DEV_ID_KX_X722:
78 case I40E_DEV_ID_QSFP_X722:
79 case I40E_DEV_ID_SFP_X722:
80 case I40E_DEV_ID_1G_BASE_T_X722:
81 case I40E_DEV_ID_10G_BASE_T_X722:
82 case I40E_DEV_ID_SFP_I_X722:
83 hw->mac.type = I40E_MAC_X722;
85 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
86 case I40E_DEV_ID_X722_VF:
87 #ifdef X722_A0_SUPPORT
88 case I40E_DEV_ID_X722_A0_VF:
90 hw->mac.type = I40E_MAC_X722_VF;
92 #endif /* INTEGRATED_VF || VF_DRIVER */
93 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
95 case I40E_DEV_ID_VF_HV:
96 case I40E_DEV_ID_ADAPTIVE_VF:
97 hw->mac.type = I40E_MAC_VF;
101 hw->mac.type = I40E_MAC_GENERIC;
105 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
108 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
109 hw->mac.type, status);
114 * i40e_aq_str - convert AQ err code to a string
115 * @hw: pointer to the HW structure
116 * @aq_err: the AQ error code to convert
118 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
123 case I40E_AQ_RC_EPERM:
124 return "I40E_AQ_RC_EPERM";
125 case I40E_AQ_RC_ENOENT:
126 return "I40E_AQ_RC_ENOENT";
127 case I40E_AQ_RC_ESRCH:
128 return "I40E_AQ_RC_ESRCH";
129 case I40E_AQ_RC_EINTR:
130 return "I40E_AQ_RC_EINTR";
132 return "I40E_AQ_RC_EIO";
133 case I40E_AQ_RC_ENXIO:
134 return "I40E_AQ_RC_ENXIO";
135 case I40E_AQ_RC_E2BIG:
136 return "I40E_AQ_RC_E2BIG";
137 case I40E_AQ_RC_EAGAIN:
138 return "I40E_AQ_RC_EAGAIN";
139 case I40E_AQ_RC_ENOMEM:
140 return "I40E_AQ_RC_ENOMEM";
141 case I40E_AQ_RC_EACCES:
142 return "I40E_AQ_RC_EACCES";
143 case I40E_AQ_RC_EFAULT:
144 return "I40E_AQ_RC_EFAULT";
145 case I40E_AQ_RC_EBUSY:
146 return "I40E_AQ_RC_EBUSY";
147 case I40E_AQ_RC_EEXIST:
148 return "I40E_AQ_RC_EEXIST";
149 case I40E_AQ_RC_EINVAL:
150 return "I40E_AQ_RC_EINVAL";
151 case I40E_AQ_RC_ENOTTY:
152 return "I40E_AQ_RC_ENOTTY";
153 case I40E_AQ_RC_ENOSPC:
154 return "I40E_AQ_RC_ENOSPC";
155 case I40E_AQ_RC_ENOSYS:
156 return "I40E_AQ_RC_ENOSYS";
157 case I40E_AQ_RC_ERANGE:
158 return "I40E_AQ_RC_ERANGE";
159 case I40E_AQ_RC_EFLUSHED:
160 return "I40E_AQ_RC_EFLUSHED";
161 case I40E_AQ_RC_BAD_ADDR:
162 return "I40E_AQ_RC_BAD_ADDR";
163 case I40E_AQ_RC_EMODE:
164 return "I40E_AQ_RC_EMODE";
165 case I40E_AQ_RC_EFBIG:
166 return "I40E_AQ_RC_EFBIG";
169 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
174 * i40e_stat_str - convert status err code to a string
175 * @hw: pointer to the HW structure
176 * @stat_err: the status error code to convert
178 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
184 return "I40E_ERR_NVM";
185 case I40E_ERR_NVM_CHECKSUM:
186 return "I40E_ERR_NVM_CHECKSUM";
188 return "I40E_ERR_PHY";
189 case I40E_ERR_CONFIG:
190 return "I40E_ERR_CONFIG";
192 return "I40E_ERR_PARAM";
193 case I40E_ERR_MAC_TYPE:
194 return "I40E_ERR_MAC_TYPE";
195 case I40E_ERR_UNKNOWN_PHY:
196 return "I40E_ERR_UNKNOWN_PHY";
197 case I40E_ERR_LINK_SETUP:
198 return "I40E_ERR_LINK_SETUP";
199 case I40E_ERR_ADAPTER_STOPPED:
200 return "I40E_ERR_ADAPTER_STOPPED";
201 case I40E_ERR_INVALID_MAC_ADDR:
202 return "I40E_ERR_INVALID_MAC_ADDR";
203 case I40E_ERR_DEVICE_NOT_SUPPORTED:
204 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
205 case I40E_ERR_MASTER_REQUESTS_PENDING:
206 return "I40E_ERR_MASTER_REQUESTS_PENDING";
207 case I40E_ERR_INVALID_LINK_SETTINGS:
208 return "I40E_ERR_INVALID_LINK_SETTINGS";
209 case I40E_ERR_AUTONEG_NOT_COMPLETE:
210 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
211 case I40E_ERR_RESET_FAILED:
212 return "I40E_ERR_RESET_FAILED";
213 case I40E_ERR_SWFW_SYNC:
214 return "I40E_ERR_SWFW_SYNC";
215 case I40E_ERR_NO_AVAILABLE_VSI:
216 return "I40E_ERR_NO_AVAILABLE_VSI";
217 case I40E_ERR_NO_MEMORY:
218 return "I40E_ERR_NO_MEMORY";
219 case I40E_ERR_BAD_PTR:
220 return "I40E_ERR_BAD_PTR";
221 case I40E_ERR_RING_FULL:
222 return "I40E_ERR_RING_FULL";
223 case I40E_ERR_INVALID_PD_ID:
224 return "I40E_ERR_INVALID_PD_ID";
225 case I40E_ERR_INVALID_QP_ID:
226 return "I40E_ERR_INVALID_QP_ID";
227 case I40E_ERR_INVALID_CQ_ID:
228 return "I40E_ERR_INVALID_CQ_ID";
229 case I40E_ERR_INVALID_CEQ_ID:
230 return "I40E_ERR_INVALID_CEQ_ID";
231 case I40E_ERR_INVALID_AEQ_ID:
232 return "I40E_ERR_INVALID_AEQ_ID";
233 case I40E_ERR_INVALID_SIZE:
234 return "I40E_ERR_INVALID_SIZE";
235 case I40E_ERR_INVALID_ARP_INDEX:
236 return "I40E_ERR_INVALID_ARP_INDEX";
237 case I40E_ERR_INVALID_FPM_FUNC_ID:
238 return "I40E_ERR_INVALID_FPM_FUNC_ID";
239 case I40E_ERR_QP_INVALID_MSG_SIZE:
240 return "I40E_ERR_QP_INVALID_MSG_SIZE";
241 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
242 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
243 case I40E_ERR_INVALID_FRAG_COUNT:
244 return "I40E_ERR_INVALID_FRAG_COUNT";
245 case I40E_ERR_QUEUE_EMPTY:
246 return "I40E_ERR_QUEUE_EMPTY";
247 case I40E_ERR_INVALID_ALIGNMENT:
248 return "I40E_ERR_INVALID_ALIGNMENT";
249 case I40E_ERR_FLUSHED_QUEUE:
250 return "I40E_ERR_FLUSHED_QUEUE";
251 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
252 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
253 case I40E_ERR_INVALID_IMM_DATA_SIZE:
254 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
255 case I40E_ERR_TIMEOUT:
256 return "I40E_ERR_TIMEOUT";
257 case I40E_ERR_OPCODE_MISMATCH:
258 return "I40E_ERR_OPCODE_MISMATCH";
259 case I40E_ERR_CQP_COMPL_ERROR:
260 return "I40E_ERR_CQP_COMPL_ERROR";
261 case I40E_ERR_INVALID_VF_ID:
262 return "I40E_ERR_INVALID_VF_ID";
263 case I40E_ERR_INVALID_HMCFN_ID:
264 return "I40E_ERR_INVALID_HMCFN_ID";
265 case I40E_ERR_BACKING_PAGE_ERROR:
266 return "I40E_ERR_BACKING_PAGE_ERROR";
267 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
268 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
269 case I40E_ERR_INVALID_PBLE_INDEX:
270 return "I40E_ERR_INVALID_PBLE_INDEX";
271 case I40E_ERR_INVALID_SD_INDEX:
272 return "I40E_ERR_INVALID_SD_INDEX";
273 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
274 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
275 case I40E_ERR_INVALID_SD_TYPE:
276 return "I40E_ERR_INVALID_SD_TYPE";
277 case I40E_ERR_MEMCPY_FAILED:
278 return "I40E_ERR_MEMCPY_FAILED";
279 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
280 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
281 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
282 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
283 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
284 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
285 case I40E_ERR_SRQ_ENABLED:
286 return "I40E_ERR_SRQ_ENABLED";
287 case I40E_ERR_ADMIN_QUEUE_ERROR:
288 return "I40E_ERR_ADMIN_QUEUE_ERROR";
289 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
290 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
291 case I40E_ERR_BUF_TOO_SHORT:
292 return "I40E_ERR_BUF_TOO_SHORT";
293 case I40E_ERR_ADMIN_QUEUE_FULL:
294 return "I40E_ERR_ADMIN_QUEUE_FULL";
295 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
296 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
297 case I40E_ERR_BAD_IWARP_CQE:
298 return "I40E_ERR_BAD_IWARP_CQE";
299 case I40E_ERR_NVM_BLANK_MODE:
300 return "I40E_ERR_NVM_BLANK_MODE";
301 case I40E_ERR_NOT_IMPLEMENTED:
302 return "I40E_ERR_NOT_IMPLEMENTED";
303 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
304 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
305 case I40E_ERR_DIAG_TEST_FAILED:
306 return "I40E_ERR_DIAG_TEST_FAILED";
307 case I40E_ERR_NOT_READY:
308 return "I40E_ERR_NOT_READY";
309 case I40E_NOT_SUPPORTED:
310 return "I40E_NOT_SUPPORTED";
311 case I40E_ERR_FIRMWARE_API_VERSION:
312 return "I40E_ERR_FIRMWARE_API_VERSION";
315 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
321 * @hw: debug mask related to admin queue
323 * @desc: pointer to admin queue descriptor
324 * @buffer: pointer to command buffer
325 * @buf_len: max length of buffer
327 * Dumps debug log about adminq command with descriptor contents.
329 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
330 void *buffer, u16 buf_len)
332 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
333 u16 len = LE16_TO_CPU(aq_desc->datalen);
334 u8 *buf = (u8 *)buffer;
337 if ((!(mask & hw->debug_mask)) || (desc == NULL))
341 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
342 LE16_TO_CPU(aq_desc->opcode),
343 LE16_TO_CPU(aq_desc->flags),
344 LE16_TO_CPU(aq_desc->datalen),
345 LE16_TO_CPU(aq_desc->retval));
346 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
347 LE32_TO_CPU(aq_desc->cookie_high),
348 LE32_TO_CPU(aq_desc->cookie_low));
349 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
350 LE32_TO_CPU(aq_desc->params.internal.param0),
351 LE32_TO_CPU(aq_desc->params.internal.param1));
352 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
353 LE32_TO_CPU(aq_desc->params.external.addr_high),
354 LE32_TO_CPU(aq_desc->params.external.addr_low));
356 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
357 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
360 /* write the full 16-byte chunks */
361 for (i = 0; i < (len - 16); i += 16)
363 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
364 i, buf[i], buf[i+1], buf[i+2], buf[i+3],
365 buf[i+4], buf[i+5], buf[i+6], buf[i+7],
366 buf[i+8], buf[i+9], buf[i+10], buf[i+11],
367 buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
368 /* the most we could have left is 16 bytes, pad with zeros */
374 memset(d_buf, 0, sizeof(d_buf));
375 for (j = 0; i < len; j++, i++)
378 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
379 i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
380 d_buf[4], d_buf[5], d_buf[6], d_buf[7],
381 d_buf[8], d_buf[9], d_buf[10], d_buf[11],
382 d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
388 * i40e_check_asq_alive
389 * @hw: pointer to the hw struct
391 * Returns true if Queue is enabled else false.
393 bool i40e_check_asq_alive(struct i40e_hw *hw)
399 return !!(rd32(hw, hw->aq.asq.len) &
400 I40E_PF_ATQLEN_ATQENABLE_MASK);
402 return !!(rd32(hw, hw->aq.asq.len) &
403 I40E_PF_ATQLEN_ATQENABLE_MASK);
404 #endif /* INTEGRATED_VF */
405 #endif /* PF_DRIVER */
409 return !!(rd32(hw, hw->aq.asq.len) &
410 I40E_VF_ATQLEN1_ATQENABLE_MASK);
412 return !!(rd32(hw, hw->aq.asq.len) &
413 I40E_VF_ATQLEN1_ATQENABLE_MASK);
414 #endif /* INTEGRATED_VF */
415 #endif /* VF_DRIVER */
420 * i40e_aq_queue_shutdown
421 * @hw: pointer to the hw struct
422 * @unloading: is the driver unloading itself
424 * Tell the Firmware that we're shutting down the AdminQ and whether
425 * or not the driver is unloading as well.
427 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
430 struct i40e_aq_desc desc;
431 struct i40e_aqc_queue_shutdown *cmd =
432 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
433 enum i40e_status_code status;
435 i40e_fill_default_direct_cmd_desc(&desc,
436 i40e_aqc_opc_queue_shutdown);
439 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
440 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
446 * i40e_aq_get_set_rss_lut
447 * @hw: pointer to the hardware structure
448 * @vsi_id: vsi fw index
449 * @pf_lut: for PF table set true, for VSI table set false
450 * @lut: pointer to the lut buffer provided by the caller
451 * @lut_size: size of the lut buffer
452 * @set: set true to set the table, false to get the table
454 * Internal function to get or set RSS look up table
456 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
457 u16 vsi_id, bool pf_lut,
458 u8 *lut, u16 lut_size,
461 enum i40e_status_code status;
462 struct i40e_aq_desc desc;
463 struct i40e_aqc_get_set_rss_lut *cmd_resp =
464 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
467 i40e_fill_default_direct_cmd_desc(&desc,
468 i40e_aqc_opc_set_rss_lut);
470 i40e_fill_default_direct_cmd_desc(&desc,
471 i40e_aqc_opc_get_rss_lut);
473 /* Indirect command */
474 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
475 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
478 CPU_TO_LE16((u16)((vsi_id <<
479 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
480 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
481 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
484 cmd_resp->flags |= CPU_TO_LE16((u16)
485 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
486 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
487 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
489 cmd_resp->flags |= CPU_TO_LE16((u16)
490 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
491 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
492 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
494 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
500 * i40e_aq_get_rss_lut
501 * @hw: pointer to the hardware structure
502 * @vsi_id: vsi fw index
503 * @pf_lut: for PF table set true, for VSI table set false
504 * @lut: pointer to the lut buffer provided by the caller
505 * @lut_size: size of the lut buffer
507 * get the RSS lookup table, PF or VSI type
509 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
510 bool pf_lut, u8 *lut, u16 lut_size)
512 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
517 * i40e_aq_set_rss_lut
518 * @hw: pointer to the hardware structure
519 * @vsi_id: vsi fw index
520 * @pf_lut: for PF table set true, for VSI table set false
521 * @lut: pointer to the lut buffer provided by the caller
522 * @lut_size: size of the lut buffer
524 * set the RSS lookup table, PF or VSI type
526 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
527 bool pf_lut, u8 *lut, u16 lut_size)
529 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
533 * i40e_aq_get_set_rss_key
534 * @hw: pointer to the hw struct
535 * @vsi_id: vsi fw index
536 * @key: pointer to key info struct
537 * @set: set true to set the key, false to get the key
539 * get the RSS key per VSI
541 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
543 struct i40e_aqc_get_set_rss_key_data *key,
546 enum i40e_status_code status;
547 struct i40e_aq_desc desc;
548 struct i40e_aqc_get_set_rss_key *cmd_resp =
549 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
550 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
553 i40e_fill_default_direct_cmd_desc(&desc,
554 i40e_aqc_opc_set_rss_key);
556 i40e_fill_default_direct_cmd_desc(&desc,
557 i40e_aqc_opc_get_rss_key);
559 /* Indirect command */
560 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
561 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
564 CPU_TO_LE16((u16)((vsi_id <<
565 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
566 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
567 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
569 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
575 * i40e_aq_get_rss_key
576 * @hw: pointer to the hw struct
577 * @vsi_id: vsi fw index
578 * @key: pointer to key info struct
581 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
583 struct i40e_aqc_get_set_rss_key_data *key)
585 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
589 * i40e_aq_set_rss_key
590 * @hw: pointer to the hw struct
591 * @vsi_id: vsi fw index
592 * @key: pointer to key info struct
594 * set the RSS key per VSI
596 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
598 struct i40e_aqc_get_set_rss_key_data *key)
600 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
603 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
604 * hardware to a bit-field that can be used by SW to more easily determine the
607 * Macros are used to shorten the table lines and make this table human
610 * We store the PTYPE in the top byte of the bit field - this is just so that
611 * we can check that the table doesn't have a row missing, as the index into
612 * the table should be the PTYPE.
616 * IF NOT i40e_ptype_lookup[ptype].known
619 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
620 * Use the rest of the fields to look at the tunnels, inner protocols, etc
622 * Use the enum i40e_rx_l2_ptype to decode the packet type
626 /* macro to make the table lines short */
627 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
630 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
631 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
632 I40E_RX_PTYPE_##OUTER_FRAG, \
633 I40E_RX_PTYPE_TUNNEL_##T, \
634 I40E_RX_PTYPE_TUNNEL_END_##TE, \
635 I40E_RX_PTYPE_##TEF, \
636 I40E_RX_PTYPE_INNER_PROT_##I, \
637 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
639 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
640 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
642 /* shorter macros makes the table fit but are terse */
643 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
644 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
645 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
647 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
648 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
649 /* L2 Packet types */
650 I40E_PTT_UNUSED_ENTRY(0),
651 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
652 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
653 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
654 I40E_PTT_UNUSED_ENTRY(4),
655 I40E_PTT_UNUSED_ENTRY(5),
656 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
657 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
658 I40E_PTT_UNUSED_ENTRY(8),
659 I40E_PTT_UNUSED_ENTRY(9),
660 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
661 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
662 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
663 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
664 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
665 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
666 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
667 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
668 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
669 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
670 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
671 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
673 /* Non Tunneled IPv4 */
674 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
675 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
676 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
677 I40E_PTT_UNUSED_ENTRY(25),
678 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
679 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
680 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
683 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
684 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
685 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
686 I40E_PTT_UNUSED_ENTRY(32),
687 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
688 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
689 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
692 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
693 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
694 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
695 I40E_PTT_UNUSED_ENTRY(39),
696 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
697 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
698 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
700 /* IPv4 --> GRE/NAT */
701 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
703 /* IPv4 --> GRE/NAT --> IPv4 */
704 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
705 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
706 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
707 I40E_PTT_UNUSED_ENTRY(47),
708 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
709 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
710 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
712 /* IPv4 --> GRE/NAT --> IPv6 */
713 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
714 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
715 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
716 I40E_PTT_UNUSED_ENTRY(54),
717 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
718 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
719 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
721 /* IPv4 --> GRE/NAT --> MAC */
722 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
724 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
725 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
726 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
727 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
728 I40E_PTT_UNUSED_ENTRY(62),
729 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
730 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
731 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
733 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
734 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
735 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
736 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
737 I40E_PTT_UNUSED_ENTRY(69),
738 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
739 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
740 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
742 /* IPv4 --> GRE/NAT --> MAC/VLAN */
743 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
745 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
746 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
747 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
748 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
749 I40E_PTT_UNUSED_ENTRY(77),
750 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
751 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
752 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
754 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
755 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
756 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
757 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
758 I40E_PTT_UNUSED_ENTRY(84),
759 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
760 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
761 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
763 /* Non Tunneled IPv6 */
764 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
765 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
766 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4),
767 I40E_PTT_UNUSED_ENTRY(91),
768 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
769 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
770 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
773 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
774 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
775 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
776 I40E_PTT_UNUSED_ENTRY(98),
777 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
778 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
779 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
782 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
783 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
784 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
785 I40E_PTT_UNUSED_ENTRY(105),
786 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
787 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
788 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
790 /* IPv6 --> GRE/NAT */
791 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
793 /* IPv6 --> GRE/NAT -> IPv4 */
794 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
795 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
796 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
797 I40E_PTT_UNUSED_ENTRY(113),
798 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
799 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
800 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
802 /* IPv6 --> GRE/NAT -> IPv6 */
803 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
804 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
805 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
806 I40E_PTT_UNUSED_ENTRY(120),
807 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
808 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
809 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
811 /* IPv6 --> GRE/NAT -> MAC */
812 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
814 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
815 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
816 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
817 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
818 I40E_PTT_UNUSED_ENTRY(128),
819 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
820 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
821 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
823 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
824 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
825 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
826 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
827 I40E_PTT_UNUSED_ENTRY(135),
828 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
829 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
830 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
832 /* IPv6 --> GRE/NAT -> MAC/VLAN */
833 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
835 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
836 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
837 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
838 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
839 I40E_PTT_UNUSED_ENTRY(143),
840 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
841 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
842 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
844 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
845 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
846 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
847 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
848 I40E_PTT_UNUSED_ENTRY(150),
849 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
850 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
851 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
854 I40E_PTT_UNUSED_ENTRY(154),
855 I40E_PTT_UNUSED_ENTRY(155),
856 I40E_PTT_UNUSED_ENTRY(156),
857 I40E_PTT_UNUSED_ENTRY(157),
858 I40E_PTT_UNUSED_ENTRY(158),
859 I40E_PTT_UNUSED_ENTRY(159),
861 I40E_PTT_UNUSED_ENTRY(160),
862 I40E_PTT_UNUSED_ENTRY(161),
863 I40E_PTT_UNUSED_ENTRY(162),
864 I40E_PTT_UNUSED_ENTRY(163),
865 I40E_PTT_UNUSED_ENTRY(164),
866 I40E_PTT_UNUSED_ENTRY(165),
867 I40E_PTT_UNUSED_ENTRY(166),
868 I40E_PTT_UNUSED_ENTRY(167),
869 I40E_PTT_UNUSED_ENTRY(168),
870 I40E_PTT_UNUSED_ENTRY(169),
872 I40E_PTT_UNUSED_ENTRY(170),
873 I40E_PTT_UNUSED_ENTRY(171),
874 I40E_PTT_UNUSED_ENTRY(172),
875 I40E_PTT_UNUSED_ENTRY(173),
876 I40E_PTT_UNUSED_ENTRY(174),
877 I40E_PTT_UNUSED_ENTRY(175),
878 I40E_PTT_UNUSED_ENTRY(176),
879 I40E_PTT_UNUSED_ENTRY(177),
880 I40E_PTT_UNUSED_ENTRY(178),
881 I40E_PTT_UNUSED_ENTRY(179),
883 I40E_PTT_UNUSED_ENTRY(180),
884 I40E_PTT_UNUSED_ENTRY(181),
885 I40E_PTT_UNUSED_ENTRY(182),
886 I40E_PTT_UNUSED_ENTRY(183),
887 I40E_PTT_UNUSED_ENTRY(184),
888 I40E_PTT_UNUSED_ENTRY(185),
889 I40E_PTT_UNUSED_ENTRY(186),
890 I40E_PTT_UNUSED_ENTRY(187),
891 I40E_PTT_UNUSED_ENTRY(188),
892 I40E_PTT_UNUSED_ENTRY(189),
894 I40E_PTT_UNUSED_ENTRY(190),
895 I40E_PTT_UNUSED_ENTRY(191),
896 I40E_PTT_UNUSED_ENTRY(192),
897 I40E_PTT_UNUSED_ENTRY(193),
898 I40E_PTT_UNUSED_ENTRY(194),
899 I40E_PTT_UNUSED_ENTRY(195),
900 I40E_PTT_UNUSED_ENTRY(196),
901 I40E_PTT_UNUSED_ENTRY(197),
902 I40E_PTT_UNUSED_ENTRY(198),
903 I40E_PTT_UNUSED_ENTRY(199),
905 I40E_PTT_UNUSED_ENTRY(200),
906 I40E_PTT_UNUSED_ENTRY(201),
907 I40E_PTT_UNUSED_ENTRY(202),
908 I40E_PTT_UNUSED_ENTRY(203),
909 I40E_PTT_UNUSED_ENTRY(204),
910 I40E_PTT_UNUSED_ENTRY(205),
911 I40E_PTT_UNUSED_ENTRY(206),
912 I40E_PTT_UNUSED_ENTRY(207),
913 I40E_PTT_UNUSED_ENTRY(208),
914 I40E_PTT_UNUSED_ENTRY(209),
916 I40E_PTT_UNUSED_ENTRY(210),
917 I40E_PTT_UNUSED_ENTRY(211),
918 I40E_PTT_UNUSED_ENTRY(212),
919 I40E_PTT_UNUSED_ENTRY(213),
920 I40E_PTT_UNUSED_ENTRY(214),
921 I40E_PTT_UNUSED_ENTRY(215),
922 I40E_PTT_UNUSED_ENTRY(216),
923 I40E_PTT_UNUSED_ENTRY(217),
924 I40E_PTT_UNUSED_ENTRY(218),
925 I40E_PTT_UNUSED_ENTRY(219),
927 I40E_PTT_UNUSED_ENTRY(220),
928 I40E_PTT_UNUSED_ENTRY(221),
929 I40E_PTT_UNUSED_ENTRY(222),
930 I40E_PTT_UNUSED_ENTRY(223),
931 I40E_PTT_UNUSED_ENTRY(224),
932 I40E_PTT_UNUSED_ENTRY(225),
933 I40E_PTT_UNUSED_ENTRY(226),
934 I40E_PTT_UNUSED_ENTRY(227),
935 I40E_PTT_UNUSED_ENTRY(228),
936 I40E_PTT_UNUSED_ENTRY(229),
938 I40E_PTT_UNUSED_ENTRY(230),
939 I40E_PTT_UNUSED_ENTRY(231),
940 I40E_PTT_UNUSED_ENTRY(232),
941 I40E_PTT_UNUSED_ENTRY(233),
942 I40E_PTT_UNUSED_ENTRY(234),
943 I40E_PTT_UNUSED_ENTRY(235),
944 I40E_PTT_UNUSED_ENTRY(236),
945 I40E_PTT_UNUSED_ENTRY(237),
946 I40E_PTT_UNUSED_ENTRY(238),
947 I40E_PTT_UNUSED_ENTRY(239),
949 I40E_PTT_UNUSED_ENTRY(240),
950 I40E_PTT_UNUSED_ENTRY(241),
951 I40E_PTT_UNUSED_ENTRY(242),
952 I40E_PTT_UNUSED_ENTRY(243),
953 I40E_PTT_UNUSED_ENTRY(244),
954 I40E_PTT_UNUSED_ENTRY(245),
955 I40E_PTT_UNUSED_ENTRY(246),
956 I40E_PTT_UNUSED_ENTRY(247),
957 I40E_PTT_UNUSED_ENTRY(248),
958 I40E_PTT_UNUSED_ENTRY(249),
960 I40E_PTT_UNUSED_ENTRY(250),
961 I40E_PTT_UNUSED_ENTRY(251),
962 I40E_PTT_UNUSED_ENTRY(252),
963 I40E_PTT_UNUSED_ENTRY(253),
964 I40E_PTT_UNUSED_ENTRY(254),
965 I40E_PTT_UNUSED_ENTRY(255)
970 * i40e_validate_mac_addr - Validate unicast MAC address
971 * @mac_addr: pointer to MAC address
973 * Tests a MAC address to ensure it is a valid Individual Address
975 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
977 enum i40e_status_code status = I40E_SUCCESS;
979 DEBUGFUNC("i40e_validate_mac_addr");
981 /* Broadcast addresses ARE multicast addresses
982 * Make sure it is not a multicast address
983 * Reject the zero address
985 if (I40E_IS_MULTICAST(mac_addr) ||
986 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
987 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
988 status = I40E_ERR_INVALID_MAC_ADDR;
995 * i40e_init_shared_code - Initialize the shared code
996 * @hw: pointer to hardware structure
998 * This assigns the MAC type and PHY code and inits the NVM.
999 * Does not touch the hardware. This function must be called prior to any
1000 * other function in the shared code. The i40e_hw structure should be
1001 * memset to 0 prior to calling this function. The following fields in
1002 * hw structure should be filled in prior to calling this function:
1003 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1004 * subsystem_vendor_id, and revision_id
1006 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
1008 enum i40e_status_code status = I40E_SUCCESS;
1009 u32 port, ari, func_rid;
1011 DEBUGFUNC("i40e_init_shared_code");
1013 i40e_set_mac_type(hw);
1015 switch (hw->mac.type) {
1016 case I40E_MAC_XL710:
1020 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1023 hw->phy.get_link_info = true;
1025 /* Determine port number and PF number*/
1026 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1027 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1028 hw->port = (u8)port;
1029 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1030 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1031 func_rid = rd32(hw, I40E_PF_FUNC_RID);
1033 hw->pf_id = (u8)(func_rid & 0xff);
1035 hw->pf_id = (u8)(func_rid & 0x7);
1037 if (hw->mac.type == I40E_MAC_X722)
1038 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
1040 status = i40e_init_nvm(hw);
1045 * i40e_aq_mac_address_read - Retrieve the MAC addresses
1046 * @hw: pointer to the hw struct
1047 * @flags: a return indicator of what addresses were added to the addr store
1048 * @addrs: the requestor's mac addr store
1049 * @cmd_details: pointer to command details structure or NULL
1051 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1053 struct i40e_aqc_mac_address_read_data *addrs,
1054 struct i40e_asq_cmd_details *cmd_details)
1056 struct i40e_aq_desc desc;
1057 struct i40e_aqc_mac_address_read *cmd_data =
1058 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1059 enum i40e_status_code status;
1061 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1062 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1064 status = i40e_asq_send_command(hw, &desc, addrs,
1065 sizeof(*addrs), cmd_details);
1066 *flags = LE16_TO_CPU(cmd_data->command_flags);
1072 * i40e_aq_mac_address_write - Change the MAC addresses
1073 * @hw: pointer to the hw struct
1074 * @flags: indicates which MAC to be written
1075 * @mac_addr: address to write
1076 * @cmd_details: pointer to command details structure or NULL
1078 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1079 u16 flags, u8 *mac_addr,
1080 struct i40e_asq_cmd_details *cmd_details)
1082 struct i40e_aq_desc desc;
1083 struct i40e_aqc_mac_address_write *cmd_data =
1084 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1085 enum i40e_status_code status;
1087 i40e_fill_default_direct_cmd_desc(&desc,
1088 i40e_aqc_opc_mac_address_write);
1089 cmd_data->command_flags = CPU_TO_LE16(flags);
1090 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1091 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1092 ((u32)mac_addr[3] << 16) |
1093 ((u32)mac_addr[4] << 8) |
1096 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1102 * i40e_get_mac_addr - get MAC address
1103 * @hw: pointer to the HW structure
1104 * @mac_addr: pointer to MAC address
1106 * Reads the adapter's MAC address from register
1108 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1110 struct i40e_aqc_mac_address_read_data addrs;
1111 enum i40e_status_code status;
1114 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1116 if (flags & I40E_AQC_LAN_ADDR_VALID)
1117 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1118 I40E_NONDMA_TO_NONDMA);
1124 * i40e_get_port_mac_addr - get Port MAC address
1125 * @hw: pointer to the HW structure
1126 * @mac_addr: pointer to Port MAC address
1128 * Reads the adapter's Port MAC address
1130 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1132 struct i40e_aqc_mac_address_read_data addrs;
1133 enum i40e_status_code status;
1136 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1140 if (flags & I40E_AQC_PORT_ADDR_VALID)
1141 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1142 I40E_NONDMA_TO_NONDMA);
1144 status = I40E_ERR_INVALID_MAC_ADDR;
1150 * i40e_pre_tx_queue_cfg - pre tx queue configure
1151 * @hw: pointer to the HW structure
1152 * @queue: target pf queue index
1153 * @enable: state change request
1155 * Handles hw requirement to indicate intention to enable
1156 * or disable target queue.
1158 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1160 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1164 if (abs_queue_idx >= 128) {
1165 reg_block = abs_queue_idx / 128;
1166 abs_queue_idx %= 128;
1169 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1170 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1171 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1174 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1176 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1178 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1182 * i40e_get_san_mac_addr - get SAN MAC address
1183 * @hw: pointer to the HW structure
1184 * @mac_addr: pointer to SAN MAC address
1186 * Reads the adapter's SAN MAC address from NVM
1188 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1191 struct i40e_aqc_mac_address_read_data addrs;
1192 enum i40e_status_code status;
1195 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1199 if (flags & I40E_AQC_SAN_ADDR_VALID)
1200 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac),
1201 I40E_NONDMA_TO_NONDMA);
1203 status = I40E_ERR_INVALID_MAC_ADDR;
1209 * i40e_read_pba_string - Reads part number string from EEPROM
1210 * @hw: pointer to hardware structure
1211 * @pba_num: stores the part number string from the EEPROM
1212 * @pba_num_size: part number string buffer length
1214 * Reads the part number string from the EEPROM.
1216 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1219 enum i40e_status_code status = I40E_SUCCESS;
1225 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1226 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1227 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1231 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1232 if (status != I40E_SUCCESS) {
1233 DEBUGOUT("Failed to read PBA Block pointer.\n");
1237 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1238 if (status != I40E_SUCCESS) {
1239 DEBUGOUT("Failed to read PBA Block size.\n");
1243 /* Subtract one to get PBA word count (PBA Size word is included in
1247 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1248 DEBUGOUT("Buffer to small for PBA data.\n");
1249 return I40E_ERR_PARAM;
1252 for (i = 0; i < pba_size; i++) {
1253 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1254 if (status != I40E_SUCCESS) {
1255 DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1259 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1260 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1262 pba_num[(pba_size * 2)] = '\0';
1268 * i40e_get_media_type - Gets media type
1269 * @hw: pointer to the hardware structure
1271 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1273 enum i40e_media_type media;
1275 switch (hw->phy.link_info.phy_type) {
1276 case I40E_PHY_TYPE_10GBASE_SR:
1277 case I40E_PHY_TYPE_10GBASE_LR:
1278 case I40E_PHY_TYPE_1000BASE_SX:
1279 case I40E_PHY_TYPE_1000BASE_LX:
1280 case I40E_PHY_TYPE_40GBASE_SR4:
1281 case I40E_PHY_TYPE_40GBASE_LR4:
1282 case I40E_PHY_TYPE_25GBASE_LR:
1283 case I40E_PHY_TYPE_25GBASE_SR:
1284 media = I40E_MEDIA_TYPE_FIBER;
1286 case I40E_PHY_TYPE_100BASE_TX:
1287 case I40E_PHY_TYPE_1000BASE_T:
1288 case I40E_PHY_TYPE_10GBASE_T:
1289 media = I40E_MEDIA_TYPE_BASET;
1291 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1292 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1293 case I40E_PHY_TYPE_10GBASE_CR1:
1294 case I40E_PHY_TYPE_40GBASE_CR4:
1295 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1296 case I40E_PHY_TYPE_40GBASE_AOC:
1297 case I40E_PHY_TYPE_10GBASE_AOC:
1298 case I40E_PHY_TYPE_25GBASE_CR:
1299 case I40E_PHY_TYPE_25GBASE_AOC:
1300 case I40E_PHY_TYPE_25GBASE_ACC:
1301 media = I40E_MEDIA_TYPE_DA;
1303 case I40E_PHY_TYPE_1000BASE_KX:
1304 case I40E_PHY_TYPE_10GBASE_KX4:
1305 case I40E_PHY_TYPE_10GBASE_KR:
1306 case I40E_PHY_TYPE_40GBASE_KR4:
1307 case I40E_PHY_TYPE_20GBASE_KR2:
1308 case I40E_PHY_TYPE_25GBASE_KR:
1309 media = I40E_MEDIA_TYPE_BACKPLANE;
1311 case I40E_PHY_TYPE_SGMII:
1312 case I40E_PHY_TYPE_XAUI:
1313 case I40E_PHY_TYPE_XFI:
1314 case I40E_PHY_TYPE_XLAUI:
1315 case I40E_PHY_TYPE_XLPPI:
1317 media = I40E_MEDIA_TYPE_UNKNOWN;
1324 #define I40E_PF_RESET_WAIT_COUNT 200
1326 * i40e_pf_reset - Reset the PF
1327 * @hw: pointer to the hardware structure
1329 * Assuming someone else has triggered a global reset,
1330 * assure the global reset is complete and then reset the PF
1332 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1339 /* Poll for Global Reset steady state in case of recent GRST.
1340 * The grst delay value is in 100ms units, and we'll wait a
1341 * couple counts longer to be sure we don't just miss the end.
1343 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1344 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1345 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1347 grst_del = grst_del * 20;
1349 for (cnt = 0; cnt < grst_del; cnt++) {
1350 reg = rd32(hw, I40E_GLGEN_RSTAT);
1351 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1353 i40e_msec_delay(100);
1355 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1356 DEBUGOUT("Global reset polling failed to complete.\n");
1357 return I40E_ERR_RESET_FAILED;
1360 /* Now Wait for the FW to be ready */
1361 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1362 reg = rd32(hw, I40E_GLNVM_ULD);
1363 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1364 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1365 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1366 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1367 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1370 i40e_msec_delay(10);
1372 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1373 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1374 DEBUGOUT("wait for FW Reset complete timedout\n");
1375 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1376 return I40E_ERR_RESET_FAILED;
1379 /* If there was a Global Reset in progress when we got here,
1380 * we don't need to do the PF Reset
1383 reg = rd32(hw, I40E_PFGEN_CTRL);
1384 wr32(hw, I40E_PFGEN_CTRL,
1385 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1386 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1387 reg = rd32(hw, I40E_PFGEN_CTRL);
1388 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1392 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1393 DEBUGOUT("PF reset polling failed to complete.\n");
1394 return I40E_ERR_RESET_FAILED;
1398 i40e_clear_pxe_mode(hw);
1401 return I40E_SUCCESS;
1405 * i40e_clear_hw - clear out any left over hw state
1406 * @hw: pointer to the hw struct
1408 * Clear queues and interrupts, typically called at init time,
1409 * but after the capabilities have been found so we know how many
1410 * queues and msix vectors have been allocated.
1412 void i40e_clear_hw(struct i40e_hw *hw)
1414 u32 num_queues, base_queue;
1422 /* get number of interrupts, queues, and vfs */
1423 val = rd32(hw, I40E_GLPCI_CNF2);
1424 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1425 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1426 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1427 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1429 val = rd32(hw, I40E_PFLAN_QALLOC);
1430 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1431 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1432 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1433 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1434 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1435 num_queues = (j - base_queue) + 1;
1439 val = rd32(hw, I40E_PF_VT_PFALLOC);
1440 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1441 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1442 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1443 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1444 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1445 num_vfs = (j - i) + 1;
1449 /* stop all the interrupts */
1450 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1451 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1452 for (i = 0; i < num_pf_int - 2; i++)
1453 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1455 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1456 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1457 wr32(hw, I40E_PFINT_LNKLST0, val);
1458 for (i = 0; i < num_pf_int - 2; i++)
1459 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1460 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1461 for (i = 0; i < num_vfs; i++)
1462 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1463 for (i = 0; i < num_vf_int - 2; i++)
1464 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1466 /* warn the HW of the coming Tx disables */
1467 for (i = 0; i < num_queues; i++) {
1468 u32 abs_queue_idx = base_queue + i;
1471 if (abs_queue_idx >= 128) {
1472 reg_block = abs_queue_idx / 128;
1473 abs_queue_idx %= 128;
1476 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1477 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1478 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1479 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1481 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1483 i40e_usec_delay(400);
1485 /* stop all the queues */
1486 for (i = 0; i < num_queues; i++) {
1487 wr32(hw, I40E_QINT_TQCTL(i), 0);
1488 wr32(hw, I40E_QTX_ENA(i), 0);
1489 wr32(hw, I40E_QINT_RQCTL(i), 0);
1490 wr32(hw, I40E_QRX_ENA(i), 0);
1493 /* short wait for all queue disables to settle */
1494 i40e_usec_delay(50);
1498 * i40e_clear_pxe_mode - clear pxe operations mode
1499 * @hw: pointer to the hw struct
1501 * Make sure all PXE mode settings are cleared, including things
1502 * like descriptor fetch/write-back mode.
1504 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1506 if (i40e_check_asq_alive(hw))
1507 i40e_aq_clear_pxe_mode(hw, NULL);
1511 * i40e_led_is_mine - helper to find matching led
1512 * @hw: pointer to the hw struct
1513 * @idx: index into GPIO registers
1515 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1517 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1522 if (!hw->func_caps.led[idx])
1525 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1526 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1527 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1529 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1530 * if it is not our port then ignore
1532 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1539 #define I40E_COMBINED_ACTIVITY 0xA
1540 #define I40E_FILTER_ACTIVITY 0xE
1541 #define I40E_LINK_ACTIVITY 0xC
1542 #define I40E_MAC_ACTIVITY 0xD
1543 #define I40E_LED0 22
1546 * i40e_led_get - return current on/off mode
1547 * @hw: pointer to the hw struct
1549 * The value returned is the 'mode' field as defined in the
1550 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1551 * values are variations of possible behaviors relating to
1552 * blink, link, and wire.
1554 u32 i40e_led_get(struct i40e_hw *hw)
1556 u32 current_mode = 0;
1560 /* as per the documentation GPIO 22-29 are the LED
1561 * GPIO pins named LED0..LED7
1563 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1564 u32 gpio_val = i40e_led_is_mine(hw, i);
1569 /* ignore gpio LED src mode entries related to the activity
1572 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1573 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1574 switch (current_mode) {
1575 case I40E_COMBINED_ACTIVITY:
1576 case I40E_FILTER_ACTIVITY:
1577 case I40E_MAC_ACTIVITY:
1583 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1584 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1592 * i40e_led_set - set new on/off mode
1593 * @hw: pointer to the hw struct
1594 * @mode: 0=off, 0xf=on (else see manual for mode details)
1595 * @blink: true if the LED should blink when on, false if steady
1597 * if this function is used to turn on the blink it should
1598 * be used to disable the blink when restoring the original state.
1600 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1602 u32 current_mode = 0;
1605 if (mode & 0xfffffff0)
1606 DEBUGOUT1("invalid mode passed in %X\n", mode);
1608 /* as per the documentation GPIO 22-29 are the LED
1609 * GPIO pins named LED0..LED7
1611 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1612 u32 gpio_val = i40e_led_is_mine(hw, i);
1617 /* ignore gpio LED src mode entries related to the activity
1620 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1621 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1622 switch (current_mode) {
1623 case I40E_COMBINED_ACTIVITY:
1624 case I40E_FILTER_ACTIVITY:
1625 case I40E_MAC_ACTIVITY:
1631 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1632 /* this & is a bit of paranoia, but serves as a range check */
1633 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1634 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1636 if (mode == I40E_LINK_ACTIVITY)
1640 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1642 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1644 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1649 /* Admin command wrappers */
1652 * i40e_aq_get_phy_capabilities
1653 * @hw: pointer to the hw struct
1654 * @abilities: structure for PHY capabilities to be filled
1655 * @qualified_modules: report Qualified Modules
1656 * @report_init: report init capabilities (active are default)
1657 * @cmd_details: pointer to command details structure or NULL
1659 * Returns the various PHY abilities supported on the Port.
1661 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1662 bool qualified_modules, bool report_init,
1663 struct i40e_aq_get_phy_abilities_resp *abilities,
1664 struct i40e_asq_cmd_details *cmd_details)
1666 struct i40e_aq_desc desc;
1667 enum i40e_status_code status;
1668 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1671 return I40E_ERR_PARAM;
1673 i40e_fill_default_direct_cmd_desc(&desc,
1674 i40e_aqc_opc_get_phy_abilities);
1676 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1677 if (abilities_size > I40E_AQ_LARGE_BUF)
1678 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1680 if (qualified_modules)
1681 desc.params.external.param0 |=
1682 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1685 desc.params.external.param0 |=
1686 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1688 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1691 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1692 status = I40E_ERR_UNKNOWN_PHY;
1695 if (hw->mac.type == I40E_MAC_XL710 &&
1696 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1697 hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
1698 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1700 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1701 hw->phy.phy_types |=
1702 ((u64)abilities->phy_type_ext << 32);
1710 * i40e_aq_set_phy_config
1711 * @hw: pointer to the hw struct
1712 * @config: structure with PHY configuration to be set
1713 * @cmd_details: pointer to command details structure or NULL
1715 * Set the various PHY configuration parameters
1716 * supported on the Port.One or more of the Set PHY config parameters may be
1717 * ignored in an MFP mode as the PF may not have the privilege to set some
1718 * of the PHY Config parameters. This status will be indicated by the
1721 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1722 struct i40e_aq_set_phy_config *config,
1723 struct i40e_asq_cmd_details *cmd_details)
1725 struct i40e_aq_desc desc;
1726 struct i40e_aq_set_phy_config *cmd =
1727 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1728 enum i40e_status_code status;
1731 return I40E_ERR_PARAM;
1733 i40e_fill_default_direct_cmd_desc(&desc,
1734 i40e_aqc_opc_set_phy_config);
1738 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1745 * @hw: pointer to the hw struct
1747 * Set the requested flow control mode using set_phy_config.
1749 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1750 bool atomic_restart)
1752 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1753 struct i40e_aq_get_phy_abilities_resp abilities;
1754 struct i40e_aq_set_phy_config config;
1755 enum i40e_status_code status;
1756 u8 pause_mask = 0x0;
1762 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1763 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1765 case I40E_FC_RX_PAUSE:
1766 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1768 case I40E_FC_TX_PAUSE:
1769 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1775 /* Get the current phy config */
1776 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1779 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1783 memset(&config, 0, sizeof(config));
1784 /* clear the old pause settings */
1785 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1786 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1787 /* set the new abilities */
1788 config.abilities |= pause_mask;
1789 /* If the abilities have changed, then set the new config */
1790 if (config.abilities != abilities.abilities) {
1791 /* Auto restart link so settings take effect */
1793 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1794 /* Copy over all the old settings */
1795 config.phy_type = abilities.phy_type;
1796 config.phy_type_ext = abilities.phy_type_ext;
1797 config.link_speed = abilities.link_speed;
1798 config.eee_capability = abilities.eee_capability;
1799 config.eeer = abilities.eeer_val;
1800 config.low_power_ctrl = abilities.d3_lpan;
1801 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1802 I40E_AQ_PHY_FEC_CONFIG_MASK;
1803 status = i40e_aq_set_phy_config(hw, &config, NULL);
1806 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1808 /* Update the link info */
1809 status = i40e_update_link_info(hw);
1811 /* Wait a little bit (on 40G cards it sometimes takes a really
1812 * long time for link to come back from the atomic reset)
1815 i40e_msec_delay(1000);
1816 status = i40e_update_link_info(hw);
1819 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1825 * i40e_aq_set_mac_config
1826 * @hw: pointer to the hw struct
1827 * @max_frame_size: Maximum Frame Size to be supported by the port
1828 * @crc_en: Tell HW to append a CRC to outgoing frames
1829 * @pacing: Pacing configurations
1830 * @cmd_details: pointer to command details structure or NULL
1832 * Configure MAC settings for frame size, jumbo frame support and the
1833 * addition of a CRC by the hardware.
1835 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1837 bool crc_en, u16 pacing,
1838 struct i40e_asq_cmd_details *cmd_details)
1840 struct i40e_aq_desc desc;
1841 struct i40e_aq_set_mac_config *cmd =
1842 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1843 enum i40e_status_code status;
1845 if (max_frame_size == 0)
1846 return I40E_ERR_PARAM;
1848 i40e_fill_default_direct_cmd_desc(&desc,
1849 i40e_aqc_opc_set_mac_config);
1851 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1852 cmd->params = ((u8)pacing & 0x0F) << 3;
1854 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1856 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1862 * i40e_aq_clear_pxe_mode
1863 * @hw: pointer to the hw struct
1864 * @cmd_details: pointer to command details structure or NULL
1866 * Tell the firmware that the driver is taking over from PXE
1868 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1869 struct i40e_asq_cmd_details *cmd_details)
1871 enum i40e_status_code status;
1872 struct i40e_aq_desc desc;
1873 struct i40e_aqc_clear_pxe *cmd =
1874 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1876 i40e_fill_default_direct_cmd_desc(&desc,
1877 i40e_aqc_opc_clear_pxe_mode);
1881 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1883 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1889 * i40e_aq_set_link_restart_an
1890 * @hw: pointer to the hw struct
1891 * @enable_link: if true: enable link, if false: disable link
1892 * @cmd_details: pointer to command details structure or NULL
1894 * Sets up the link and restarts the Auto-Negotiation over the link.
1896 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1897 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1899 struct i40e_aq_desc desc;
1900 struct i40e_aqc_set_link_restart_an *cmd =
1901 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1902 enum i40e_status_code status;
1904 i40e_fill_default_direct_cmd_desc(&desc,
1905 i40e_aqc_opc_set_link_restart_an);
1907 cmd->command = I40E_AQ_PHY_RESTART_AN;
1909 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1911 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1913 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1919 * i40e_aq_get_link_info
1920 * @hw: pointer to the hw struct
1921 * @enable_lse: enable/disable LinkStatusEvent reporting
1922 * @link: pointer to link status structure - optional
1923 * @cmd_details: pointer to command details structure or NULL
1925 * Returns the link status of the adapter.
1927 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1928 bool enable_lse, struct i40e_link_status *link,
1929 struct i40e_asq_cmd_details *cmd_details)
1931 struct i40e_aq_desc desc;
1932 struct i40e_aqc_get_link_status *resp =
1933 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1934 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1935 enum i40e_status_code status;
1936 bool tx_pause, rx_pause;
1939 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1942 command_flags = I40E_AQ_LSE_ENABLE;
1944 command_flags = I40E_AQ_LSE_DISABLE;
1945 resp->command_flags = CPU_TO_LE16(command_flags);
1947 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1949 if (status != I40E_SUCCESS)
1950 goto aq_get_link_info_exit;
1952 /* save off old link status information */
1953 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1954 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1956 /* update link status */
1957 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1958 hw->phy.media_type = i40e_get_media_type(hw);
1959 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1960 hw_link_info->link_info = resp->link_info;
1961 hw_link_info->an_info = resp->an_info;
1962 hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
1963 I40E_AQ_CONFIG_FEC_RS_ENA);
1964 hw_link_info->ext_info = resp->ext_info;
1965 hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
1966 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1967 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1969 /* update fc info */
1970 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1971 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1972 if (tx_pause & rx_pause)
1973 hw->fc.current_mode = I40E_FC_FULL;
1975 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1977 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1979 hw->fc.current_mode = I40E_FC_NONE;
1981 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1982 hw_link_info->crc_enable = true;
1984 hw_link_info->crc_enable = false;
1986 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
1987 hw_link_info->lse_enable = true;
1989 hw_link_info->lse_enable = false;
1991 if ((hw->mac.type == I40E_MAC_XL710) &&
1992 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1993 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1994 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1996 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1997 hw->aq.api_min_ver >= 7) {
1998 hw->phy.phy_types = LE32_TO_CPU(*(__le32 *)resp->link_type);
1999 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
2002 /* save link status information */
2004 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
2005 I40E_NONDMA_TO_NONDMA);
2007 /* flag cleared so helper functions don't call AQ again */
2008 hw->phy.get_link_info = false;
2010 aq_get_link_info_exit:
2015 * i40e_aq_set_phy_int_mask
2016 * @hw: pointer to the hw struct
2017 * @mask: interrupt mask to be set
2018 * @cmd_details: pointer to command details structure or NULL
2020 * Set link interrupt mask.
2022 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2024 struct i40e_asq_cmd_details *cmd_details)
2026 struct i40e_aq_desc desc;
2027 struct i40e_aqc_set_phy_int_mask *cmd =
2028 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2029 enum i40e_status_code status;
2031 i40e_fill_default_direct_cmd_desc(&desc,
2032 i40e_aqc_opc_set_phy_int_mask);
2034 cmd->event_mask = CPU_TO_LE16(mask);
2036 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2042 * i40e_aq_get_local_advt_reg
2043 * @hw: pointer to the hw struct
2044 * @advt_reg: local AN advertisement register value
2045 * @cmd_details: pointer to command details structure or NULL
2047 * Get the Local AN advertisement register value.
2049 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2051 struct i40e_asq_cmd_details *cmd_details)
2053 struct i40e_aq_desc desc;
2054 struct i40e_aqc_an_advt_reg *resp =
2055 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2056 enum i40e_status_code status;
2058 i40e_fill_default_direct_cmd_desc(&desc,
2059 i40e_aqc_opc_get_local_advt_reg);
2061 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2063 if (status != I40E_SUCCESS)
2064 goto aq_get_local_advt_reg_exit;
2066 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2067 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2069 aq_get_local_advt_reg_exit:
2074 * i40e_aq_set_local_advt_reg
2075 * @hw: pointer to the hw struct
2076 * @advt_reg: local AN advertisement register value
2077 * @cmd_details: pointer to command details structure or NULL
2079 * Get the Local AN advertisement register value.
2081 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2083 struct i40e_asq_cmd_details *cmd_details)
2085 struct i40e_aq_desc desc;
2086 struct i40e_aqc_an_advt_reg *cmd =
2087 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2088 enum i40e_status_code status;
2090 i40e_fill_default_direct_cmd_desc(&desc,
2091 i40e_aqc_opc_get_local_advt_reg);
2093 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2094 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2096 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2102 * i40e_aq_get_partner_advt
2103 * @hw: pointer to the hw struct
2104 * @advt_reg: AN partner advertisement register value
2105 * @cmd_details: pointer to command details structure or NULL
2107 * Get the link partner AN advertisement register value.
2109 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2111 struct i40e_asq_cmd_details *cmd_details)
2113 struct i40e_aq_desc desc;
2114 struct i40e_aqc_an_advt_reg *resp =
2115 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2116 enum i40e_status_code status;
2118 i40e_fill_default_direct_cmd_desc(&desc,
2119 i40e_aqc_opc_get_partner_advt);
2121 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2123 if (status != I40E_SUCCESS)
2124 goto aq_get_partner_advt_exit;
2126 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2127 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2129 aq_get_partner_advt_exit:
2134 * i40e_aq_set_lb_modes
2135 * @hw: pointer to the hw struct
2136 * @lb_modes: loopback mode to be set
2137 * @cmd_details: pointer to command details structure or NULL
2139 * Sets loopback modes.
2141 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2143 struct i40e_asq_cmd_details *cmd_details)
2145 struct i40e_aq_desc desc;
2146 struct i40e_aqc_set_lb_mode *cmd =
2147 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2148 enum i40e_status_code status;
2150 i40e_fill_default_direct_cmd_desc(&desc,
2151 i40e_aqc_opc_set_lb_modes);
2153 cmd->lb_mode = CPU_TO_LE16(lb_modes);
2155 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2161 * i40e_aq_set_phy_debug
2162 * @hw: pointer to the hw struct
2163 * @cmd_flags: debug command flags
2164 * @cmd_details: pointer to command details structure or NULL
2166 * Reset the external PHY.
2168 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2169 struct i40e_asq_cmd_details *cmd_details)
2171 struct i40e_aq_desc desc;
2172 struct i40e_aqc_set_phy_debug *cmd =
2173 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2174 enum i40e_status_code status;
2176 i40e_fill_default_direct_cmd_desc(&desc,
2177 i40e_aqc_opc_set_phy_debug);
2179 cmd->command_flags = cmd_flags;
2181 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2188 * @hw: pointer to the hw struct
2189 * @vsi_ctx: pointer to a vsi context struct
2190 * @cmd_details: pointer to command details structure or NULL
2192 * Add a VSI context to the hardware.
2194 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2195 struct i40e_vsi_context *vsi_ctx,
2196 struct i40e_asq_cmd_details *cmd_details)
2198 struct i40e_aq_desc desc;
2199 struct i40e_aqc_add_get_update_vsi *cmd =
2200 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2201 struct i40e_aqc_add_get_update_vsi_completion *resp =
2202 (struct i40e_aqc_add_get_update_vsi_completion *)
2204 enum i40e_status_code status;
2206 i40e_fill_default_direct_cmd_desc(&desc,
2207 i40e_aqc_opc_add_vsi);
2209 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2210 cmd->connection_type = vsi_ctx->connection_type;
2211 cmd->vf_id = vsi_ctx->vf_num;
2212 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2214 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2216 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2217 sizeof(vsi_ctx->info), cmd_details);
2219 if (status != I40E_SUCCESS)
2220 goto aq_add_vsi_exit;
2222 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2223 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2224 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2225 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2232 * i40e_aq_set_default_vsi
2233 * @hw: pointer to the hw struct
2235 * @cmd_details: pointer to command details structure or NULL
2237 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2239 struct i40e_asq_cmd_details *cmd_details)
2241 struct i40e_aq_desc desc;
2242 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2243 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2245 enum i40e_status_code status;
2247 i40e_fill_default_direct_cmd_desc(&desc,
2248 i40e_aqc_opc_set_vsi_promiscuous_modes);
2250 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2251 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2252 cmd->seid = CPU_TO_LE16(seid);
2254 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2260 * i40e_aq_clear_default_vsi
2261 * @hw: pointer to the hw struct
2263 * @cmd_details: pointer to command details structure or NULL
2265 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2267 struct i40e_asq_cmd_details *cmd_details)
2269 struct i40e_aq_desc desc;
2270 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2271 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2273 enum i40e_status_code status;
2275 i40e_fill_default_direct_cmd_desc(&desc,
2276 i40e_aqc_opc_set_vsi_promiscuous_modes);
2278 cmd->promiscuous_flags = CPU_TO_LE16(0);
2279 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2280 cmd->seid = CPU_TO_LE16(seid);
2282 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2288 * i40e_aq_set_vsi_unicast_promiscuous
2289 * @hw: pointer to the hw struct
2291 * @set: set unicast promiscuous enable/disable
2292 * @cmd_details: pointer to command details structure or NULL
2293 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2295 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2297 struct i40e_asq_cmd_details *cmd_details,
2298 bool rx_only_promisc)
2300 struct i40e_aq_desc desc;
2301 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2302 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2303 enum i40e_status_code status;
2306 i40e_fill_default_direct_cmd_desc(&desc,
2307 i40e_aqc_opc_set_vsi_promiscuous_modes);
2310 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2311 if (rx_only_promisc &&
2312 (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2313 (hw->aq.api_maj_ver > 1)))
2314 flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2317 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2319 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2320 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2321 (hw->aq.api_maj_ver > 1))
2322 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2324 cmd->seid = CPU_TO_LE16(seid);
2325 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2331 * i40e_aq_set_vsi_multicast_promiscuous
2332 * @hw: pointer to the hw struct
2334 * @set: set multicast promiscuous enable/disable
2335 * @cmd_details: pointer to command details structure or NULL
2337 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2338 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2340 struct i40e_aq_desc desc;
2341 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2342 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2343 enum i40e_status_code status;
2346 i40e_fill_default_direct_cmd_desc(&desc,
2347 i40e_aqc_opc_set_vsi_promiscuous_modes);
2350 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2352 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2354 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2356 cmd->seid = CPU_TO_LE16(seid);
2357 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2363 * i40e_aq_set_vsi_full_promiscuous
2364 * @hw: pointer to the hw struct
2366 * @set: set promiscuous enable/disable
2367 * @cmd_details: pointer to command details structure or NULL
2369 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw,
2371 struct i40e_asq_cmd_details *cmd_details)
2373 struct i40e_aq_desc desc;
2374 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2375 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2376 enum i40e_status_code status;
2379 i40e_fill_default_direct_cmd_desc(&desc,
2380 i40e_aqc_opc_set_vsi_promiscuous_modes);
2383 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST |
2384 I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2385 I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2387 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2389 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST |
2390 I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2391 I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2393 cmd->seid = CPU_TO_LE16(seid);
2394 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2400 * i40e_aq_set_vsi_mc_promisc_on_vlan
2401 * @hw: pointer to the hw struct
2403 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2404 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2405 * @cmd_details: pointer to command details structure or NULL
2407 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2408 u16 seid, bool enable, u16 vid,
2409 struct i40e_asq_cmd_details *cmd_details)
2411 struct i40e_aq_desc desc;
2412 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2413 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2414 enum i40e_status_code status;
2417 i40e_fill_default_direct_cmd_desc(&desc,
2418 i40e_aqc_opc_set_vsi_promiscuous_modes);
2421 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2423 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2424 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2425 cmd->seid = CPU_TO_LE16(seid);
2426 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2428 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2434 * i40e_aq_set_vsi_uc_promisc_on_vlan
2435 * @hw: pointer to the hw struct
2437 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2438 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2439 * @cmd_details: pointer to command details structure or NULL
2441 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2442 u16 seid, bool enable, u16 vid,
2443 struct i40e_asq_cmd_details *cmd_details)
2445 struct i40e_aq_desc desc;
2446 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2447 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2448 enum i40e_status_code status;
2451 i40e_fill_default_direct_cmd_desc(&desc,
2452 i40e_aqc_opc_set_vsi_promiscuous_modes);
2455 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2457 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2458 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2459 cmd->seid = CPU_TO_LE16(seid);
2460 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2462 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2468 * i40e_aq_set_vsi_bc_promisc_on_vlan
2469 * @hw: pointer to the hw struct
2471 * @enable: set broadcast promiscuous enable/disable for a given VLAN
2472 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2473 * @cmd_details: pointer to command details structure or NULL
2475 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2476 u16 seid, bool enable, u16 vid,
2477 struct i40e_asq_cmd_details *cmd_details)
2479 struct i40e_aq_desc desc;
2480 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2481 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2482 enum i40e_status_code status;
2485 i40e_fill_default_direct_cmd_desc(&desc,
2486 i40e_aqc_opc_set_vsi_promiscuous_modes);
2489 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2491 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2492 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2493 cmd->seid = CPU_TO_LE16(seid);
2494 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2496 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2502 * i40e_aq_set_vsi_broadcast
2503 * @hw: pointer to the hw struct
2505 * @set_filter: true to set filter, false to clear filter
2506 * @cmd_details: pointer to command details structure or NULL
2508 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2510 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2511 u16 seid, bool set_filter,
2512 struct i40e_asq_cmd_details *cmd_details)
2514 struct i40e_aq_desc desc;
2515 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2516 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2517 enum i40e_status_code status;
2519 i40e_fill_default_direct_cmd_desc(&desc,
2520 i40e_aqc_opc_set_vsi_promiscuous_modes);
2523 cmd->promiscuous_flags
2524 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2526 cmd->promiscuous_flags
2527 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2529 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2530 cmd->seid = CPU_TO_LE16(seid);
2531 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2537 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2538 * @hw: pointer to the hw struct
2540 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2541 * @cmd_details: pointer to command details structure or NULL
2543 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2544 u16 seid, bool enable,
2545 struct i40e_asq_cmd_details *cmd_details)
2547 struct i40e_aq_desc desc;
2548 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2549 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2550 enum i40e_status_code status;
2553 i40e_fill_default_direct_cmd_desc(&desc,
2554 i40e_aqc_opc_set_vsi_promiscuous_modes);
2556 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2558 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2559 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2560 cmd->seid = CPU_TO_LE16(seid);
2562 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2568 * i40e_get_vsi_params - get VSI configuration info
2569 * @hw: pointer to the hw struct
2570 * @vsi_ctx: pointer to a vsi context struct
2571 * @cmd_details: pointer to command details structure or NULL
2573 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2574 struct i40e_vsi_context *vsi_ctx,
2575 struct i40e_asq_cmd_details *cmd_details)
2577 struct i40e_aq_desc desc;
2578 struct i40e_aqc_add_get_update_vsi *cmd =
2579 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2580 struct i40e_aqc_add_get_update_vsi_completion *resp =
2581 (struct i40e_aqc_add_get_update_vsi_completion *)
2583 enum i40e_status_code status;
2585 UNREFERENCED_1PARAMETER(cmd_details);
2586 i40e_fill_default_direct_cmd_desc(&desc,
2587 i40e_aqc_opc_get_vsi_parameters);
2589 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2591 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2593 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2594 sizeof(vsi_ctx->info), NULL);
2596 if (status != I40E_SUCCESS)
2597 goto aq_get_vsi_params_exit;
2599 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2600 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2601 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2602 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2604 aq_get_vsi_params_exit:
2609 * i40e_aq_update_vsi_params
2610 * @hw: pointer to the hw struct
2611 * @vsi_ctx: pointer to a vsi context struct
2612 * @cmd_details: pointer to command details structure or NULL
2614 * Update a VSI context.
2616 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2617 struct i40e_vsi_context *vsi_ctx,
2618 struct i40e_asq_cmd_details *cmd_details)
2620 struct i40e_aq_desc desc;
2621 struct i40e_aqc_add_get_update_vsi *cmd =
2622 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2623 struct i40e_aqc_add_get_update_vsi_completion *resp =
2624 (struct i40e_aqc_add_get_update_vsi_completion *)
2626 enum i40e_status_code status;
2628 i40e_fill_default_direct_cmd_desc(&desc,
2629 i40e_aqc_opc_update_vsi_parameters);
2630 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2632 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2634 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2635 sizeof(vsi_ctx->info), cmd_details);
2637 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2638 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2644 * i40e_aq_get_switch_config
2645 * @hw: pointer to the hardware structure
2646 * @buf: pointer to the result buffer
2647 * @buf_size: length of input buffer
2648 * @start_seid: seid to start for the report, 0 == beginning
2649 * @cmd_details: pointer to command details structure or NULL
2651 * Fill the buf with switch configuration returned from AdminQ command
2653 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2654 struct i40e_aqc_get_switch_config_resp *buf,
2655 u16 buf_size, u16 *start_seid,
2656 struct i40e_asq_cmd_details *cmd_details)
2658 struct i40e_aq_desc desc;
2659 struct i40e_aqc_switch_seid *scfg =
2660 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2661 enum i40e_status_code status;
2663 i40e_fill_default_direct_cmd_desc(&desc,
2664 i40e_aqc_opc_get_switch_config);
2665 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2666 if (buf_size > I40E_AQ_LARGE_BUF)
2667 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2668 scfg->seid = CPU_TO_LE16(*start_seid);
2670 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2671 *start_seid = LE16_TO_CPU(scfg->seid);
2677 * i40e_aq_set_switch_config
2678 * @hw: pointer to the hardware structure
2679 * @flags: bit flag values to set
2680 * @valid_flags: which bit flags to set
2681 * @cmd_details: pointer to command details structure or NULL
2683 * Set switch configuration bits
2685 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2686 u16 flags, u16 valid_flags,
2687 struct i40e_asq_cmd_details *cmd_details)
2689 struct i40e_aq_desc desc;
2690 struct i40e_aqc_set_switch_config *scfg =
2691 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2692 enum i40e_status_code status;
2694 i40e_fill_default_direct_cmd_desc(&desc,
2695 i40e_aqc_opc_set_switch_config);
2696 scfg->flags = CPU_TO_LE16(flags);
2697 scfg->valid_flags = CPU_TO_LE16(valid_flags);
2699 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2705 * i40e_aq_get_firmware_version
2706 * @hw: pointer to the hw struct
2707 * @fw_major_version: firmware major version
2708 * @fw_minor_version: firmware minor version
2709 * @fw_build: firmware build number
2710 * @api_major_version: major queue version
2711 * @api_minor_version: minor queue version
2712 * @cmd_details: pointer to command details structure or NULL
2714 * Get the firmware version from the admin queue commands
2716 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2717 u16 *fw_major_version, u16 *fw_minor_version,
2719 u16 *api_major_version, u16 *api_minor_version,
2720 struct i40e_asq_cmd_details *cmd_details)
2722 struct i40e_aq_desc desc;
2723 struct i40e_aqc_get_version *resp =
2724 (struct i40e_aqc_get_version *)&desc.params.raw;
2725 enum i40e_status_code status;
2727 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2729 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2731 if (status == I40E_SUCCESS) {
2732 if (fw_major_version != NULL)
2733 *fw_major_version = LE16_TO_CPU(resp->fw_major);
2734 if (fw_minor_version != NULL)
2735 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2736 if (fw_build != NULL)
2737 *fw_build = LE32_TO_CPU(resp->fw_build);
2738 if (api_major_version != NULL)
2739 *api_major_version = LE16_TO_CPU(resp->api_major);
2740 if (api_minor_version != NULL)
2741 *api_minor_version = LE16_TO_CPU(resp->api_minor);
2743 /* A workaround to fix the API version in SW */
2744 if (api_major_version && api_minor_version &&
2745 fw_major_version && fw_minor_version &&
2746 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2747 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2748 (*fw_major_version > 4)))
2749 *api_minor_version = 2;
2756 * i40e_aq_send_driver_version
2757 * @hw: pointer to the hw struct
2758 * @dv: driver's major, minor version
2759 * @cmd_details: pointer to command details structure or NULL
2761 * Send the driver version to the firmware
2763 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2764 struct i40e_driver_version *dv,
2765 struct i40e_asq_cmd_details *cmd_details)
2767 struct i40e_aq_desc desc;
2768 struct i40e_aqc_driver_version *cmd =
2769 (struct i40e_aqc_driver_version *)&desc.params.raw;
2770 enum i40e_status_code status;
2774 return I40E_ERR_PARAM;
2776 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2778 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2779 cmd->driver_major_ver = dv->major_version;
2780 cmd->driver_minor_ver = dv->minor_version;
2781 cmd->driver_build_ver = dv->build_version;
2782 cmd->driver_subbuild_ver = dv->subbuild_version;
2785 while (len < sizeof(dv->driver_string) &&
2786 (dv->driver_string[len] < 0x80) &&
2787 dv->driver_string[len])
2789 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2796 * i40e_get_link_status - get status of the HW network link
2797 * @hw: pointer to the hw struct
2798 * @link_up: pointer to bool (true/false = linkup/linkdown)
2800 * Variable link_up true if link is up, false if link is down.
2801 * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2803 * Side effect: LinkStatusEvent reporting becomes enabled
2805 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2807 enum i40e_status_code status = I40E_SUCCESS;
2809 if (hw->phy.get_link_info) {
2810 status = i40e_update_link_info(hw);
2812 if (status != I40E_SUCCESS)
2813 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2817 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2823 * i40e_updatelink_status - update status of the HW network link
2824 * @hw: pointer to the hw struct
2826 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2828 struct i40e_aq_get_phy_abilities_resp abilities;
2829 enum i40e_status_code status = I40E_SUCCESS;
2831 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2835 /* extra checking needed to ensure link info to user is timely */
2836 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2837 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2838 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2839 status = i40e_aq_get_phy_capabilities(hw, false, false,
2844 hw->phy.link_info.req_fec_info =
2845 abilities.fec_cfg_curr_mod_ext_info &
2846 (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS);
2848 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2849 sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2856 * i40e_get_link_speed
2857 * @hw: pointer to the hw struct
2859 * Returns the link speed of the adapter.
2861 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2863 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2864 enum i40e_status_code status = I40E_SUCCESS;
2866 if (hw->phy.get_link_info) {
2867 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2869 if (status != I40E_SUCCESS)
2870 goto i40e_link_speed_exit;
2873 speed = hw->phy.link_info.link_speed;
2875 i40e_link_speed_exit:
2880 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2881 * @hw: pointer to the hw struct
2882 * @uplink_seid: the MAC or other gizmo SEID
2883 * @downlink_seid: the VSI SEID
2884 * @enabled_tc: bitmap of TCs to be enabled
2885 * @default_port: true for default port VSI, false for control port
2886 * @veb_seid: pointer to where to put the resulting VEB SEID
2887 * @enable_stats: true to turn on VEB stats
2888 * @cmd_details: pointer to command details structure or NULL
2890 * This asks the FW to add a VEB between the uplink and downlink
2891 * elements. If the uplink SEID is 0, this will be a floating VEB.
2893 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2894 u16 downlink_seid, u8 enabled_tc,
2895 bool default_port, u16 *veb_seid,
2897 struct i40e_asq_cmd_details *cmd_details)
2899 struct i40e_aq_desc desc;
2900 struct i40e_aqc_add_veb *cmd =
2901 (struct i40e_aqc_add_veb *)&desc.params.raw;
2902 struct i40e_aqc_add_veb_completion *resp =
2903 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2904 enum i40e_status_code status;
2907 /* SEIDs need to either both be set or both be 0 for floating VEB */
2908 if (!!uplink_seid != !!downlink_seid)
2909 return I40E_ERR_PARAM;
2911 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2913 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2914 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2915 cmd->enable_tcs = enabled_tc;
2917 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2919 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2921 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2923 /* reverse logic here: set the bitflag to disable the stats */
2925 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2927 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2929 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2931 if (!status && veb_seid)
2932 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2938 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2939 * @hw: pointer to the hw struct
2940 * @veb_seid: the SEID of the VEB to query
2941 * @switch_id: the uplink switch id
2942 * @floating: set to true if the VEB is floating
2943 * @statistic_index: index of the stats counter block for this VEB
2944 * @vebs_used: number of VEB's used by function
2945 * @vebs_free: total VEB's not reserved by any function
2946 * @cmd_details: pointer to command details structure or NULL
2948 * This retrieves the parameters for a particular VEB, specified by
2949 * uplink_seid, and returns them to the caller.
2951 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2952 u16 veb_seid, u16 *switch_id,
2953 bool *floating, u16 *statistic_index,
2954 u16 *vebs_used, u16 *vebs_free,
2955 struct i40e_asq_cmd_details *cmd_details)
2957 struct i40e_aq_desc desc;
2958 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2959 (struct i40e_aqc_get_veb_parameters_completion *)
2961 enum i40e_status_code status;
2964 return I40E_ERR_PARAM;
2966 i40e_fill_default_direct_cmd_desc(&desc,
2967 i40e_aqc_opc_get_veb_parameters);
2968 cmd_resp->seid = CPU_TO_LE16(veb_seid);
2970 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2975 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2976 if (statistic_index)
2977 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2979 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2981 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2983 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2985 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2996 * i40e_aq_add_macvlan
2997 * @hw: pointer to the hw struct
2998 * @seid: VSI for the mac address
2999 * @mv_list: list of macvlans to be added
3000 * @count: length of the list
3001 * @cmd_details: pointer to command details structure or NULL
3003 * Add MAC/VLAN addresses to the HW filtering
3005 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
3006 struct i40e_aqc_add_macvlan_element_data *mv_list,
3007 u16 count, struct i40e_asq_cmd_details *cmd_details)
3009 struct i40e_aq_desc desc;
3010 struct i40e_aqc_macvlan *cmd =
3011 (struct i40e_aqc_macvlan *)&desc.params.raw;
3012 enum i40e_status_code status;
3016 if (count == 0 || !mv_list || !hw)
3017 return I40E_ERR_PARAM;
3019 buf_size = count * sizeof(*mv_list);
3021 /* prep the rest of the request */
3022 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
3023 cmd->num_addresses = CPU_TO_LE16(count);
3024 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3028 for (i = 0; i < count; i++)
3029 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
3031 CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
3033 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3034 if (buf_size > I40E_AQ_LARGE_BUF)
3035 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3037 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3044 * i40e_aq_remove_macvlan
3045 * @hw: pointer to the hw struct
3046 * @seid: VSI for the mac address
3047 * @mv_list: list of macvlans to be removed
3048 * @count: length of the list
3049 * @cmd_details: pointer to command details structure or NULL
3051 * Remove MAC/VLAN addresses from the HW filtering
3053 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
3054 struct i40e_aqc_remove_macvlan_element_data *mv_list,
3055 u16 count, struct i40e_asq_cmd_details *cmd_details)
3057 struct i40e_aq_desc desc;
3058 struct i40e_aqc_macvlan *cmd =
3059 (struct i40e_aqc_macvlan *)&desc.params.raw;
3060 enum i40e_status_code status;
3063 if (count == 0 || !mv_list || !hw)
3064 return I40E_ERR_PARAM;
3066 buf_size = count * sizeof(*mv_list);
3068 /* prep the rest of the request */
3069 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
3070 cmd->num_addresses = CPU_TO_LE16(count);
3071 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3075 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3076 if (buf_size > I40E_AQ_LARGE_BUF)
3077 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3079 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3086 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3087 * @hw: pointer to the hw struct
3088 * @opcode: AQ opcode for add or delete mirror rule
3089 * @sw_seid: Switch SEID (to which rule refers)
3090 * @rule_type: Rule Type (ingress/egress/VLAN)
3091 * @id: Destination VSI SEID or Rule ID
3092 * @count: length of the list
3093 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3094 * @cmd_details: pointer to command details structure or NULL
3095 * @rule_id: Rule ID returned from FW
3096 * @rule_used: Number of rules used in internal switch
3097 * @rule_free: Number of rules free in internal switch
3099 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3100 * VEBs/VEPA elements only
3102 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3103 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3104 u16 count, __le16 *mr_list,
3105 struct i40e_asq_cmd_details *cmd_details,
3106 u16 *rule_id, u16 *rules_used, u16 *rules_free)
3108 struct i40e_aq_desc desc;
3109 struct i40e_aqc_add_delete_mirror_rule *cmd =
3110 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3111 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3112 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3113 enum i40e_status_code status;
3116 buf_size = count * sizeof(*mr_list);
3118 /* prep the rest of the request */
3119 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3120 cmd->seid = CPU_TO_LE16(sw_seid);
3121 cmd->rule_type = CPU_TO_LE16(rule_type &
3122 I40E_AQC_MIRROR_RULE_TYPE_MASK);
3123 cmd->num_entries = CPU_TO_LE16(count);
3124 /* Dest VSI for add, rule_id for delete */
3125 cmd->destination = CPU_TO_LE16(id);
3127 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3129 if (buf_size > I40E_AQ_LARGE_BUF)
3130 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3133 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3135 if (status == I40E_SUCCESS ||
3136 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3138 *rule_id = LE16_TO_CPU(resp->rule_id);
3140 *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3142 *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3148 * i40e_aq_add_mirrorrule - add a mirror rule
3149 * @hw: pointer to the hw struct
3150 * @sw_seid: Switch SEID (to which rule refers)
3151 * @rule_type: Rule Type (ingress/egress/VLAN)
3152 * @dest_vsi: SEID of VSI to which packets will be mirrored
3153 * @count: length of the list
3154 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3155 * @cmd_details: pointer to command details structure or NULL
3156 * @rule_id: Rule ID returned from FW
3157 * @rule_used: Number of rules used in internal switch
3158 * @rule_free: Number of rules free in internal switch
3160 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3162 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3163 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3164 struct i40e_asq_cmd_details *cmd_details,
3165 u16 *rule_id, u16 *rules_used, u16 *rules_free)
3167 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3168 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3169 if (count == 0 || !mr_list)
3170 return I40E_ERR_PARAM;
3173 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3174 rule_type, dest_vsi, count, mr_list,
3175 cmd_details, rule_id, rules_used, rules_free);
3179 * i40e_aq_delete_mirrorrule - delete a mirror rule
3180 * @hw: pointer to the hw struct
3181 * @sw_seid: Switch SEID (to which rule refers)
3182 * @rule_type: Rule Type (ingress/egress/VLAN)
3183 * @count: length of the list
3184 * @rule_id: Rule ID that is returned in the receive desc as part of
3186 * @mr_list: list of mirrored VLAN IDs to be removed
3187 * @cmd_details: pointer to command details structure or NULL
3188 * @rule_used: Number of rules used in internal switch
3189 * @rule_free: Number of rules free in internal switch
3191 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3193 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3194 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3195 struct i40e_asq_cmd_details *cmd_details,
3196 u16 *rules_used, u16 *rules_free)
3198 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3199 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3200 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3201 * mirroring. For other rule_type, count and rule_type should
3204 if (count == 0 || !mr_list)
3205 return I40E_ERR_PARAM;
3208 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3209 rule_type, rule_id, count, mr_list,
3210 cmd_details, NULL, rules_used, rules_free);
3214 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3215 * @hw: pointer to the hw struct
3216 * @seid: VSI for the vlan filters
3217 * @v_list: list of vlan filters to be added
3218 * @count: length of the list
3219 * @cmd_details: pointer to command details structure or NULL
3221 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3222 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3223 u8 count, struct i40e_asq_cmd_details *cmd_details)
3225 struct i40e_aq_desc desc;
3226 struct i40e_aqc_macvlan *cmd =
3227 (struct i40e_aqc_macvlan *)&desc.params.raw;
3228 enum i40e_status_code status;
3231 if (count == 0 || !v_list || !hw)
3232 return I40E_ERR_PARAM;
3234 buf_size = count * sizeof(*v_list);
3236 /* prep the rest of the request */
3237 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3238 cmd->num_addresses = CPU_TO_LE16(count);
3239 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3243 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3244 if (buf_size > I40E_AQ_LARGE_BUF)
3245 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3247 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3254 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3255 * @hw: pointer to the hw struct
3256 * @seid: VSI for the vlan filters
3257 * @v_list: list of macvlans to be removed
3258 * @count: length of the list
3259 * @cmd_details: pointer to command details structure or NULL
3261 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3262 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3263 u8 count, struct i40e_asq_cmd_details *cmd_details)
3265 struct i40e_aq_desc desc;
3266 struct i40e_aqc_macvlan *cmd =
3267 (struct i40e_aqc_macvlan *)&desc.params.raw;
3268 enum i40e_status_code status;
3271 if (count == 0 || !v_list || !hw)
3272 return I40E_ERR_PARAM;
3274 buf_size = count * sizeof(*v_list);
3276 /* prep the rest of the request */
3277 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3278 cmd->num_addresses = CPU_TO_LE16(count);
3279 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3283 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3284 if (buf_size > I40E_AQ_LARGE_BUF)
3285 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3287 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3294 * i40e_aq_send_msg_to_vf
3295 * @hw: pointer to the hardware structure
3296 * @vfid: vf id to send msg
3297 * @v_opcode: opcodes for VF-PF communication
3298 * @v_retval: return error code
3299 * @msg: pointer to the msg buffer
3300 * @msglen: msg length
3301 * @cmd_details: pointer to command details
3305 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3306 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3307 struct i40e_asq_cmd_details *cmd_details)
3309 struct i40e_aq_desc desc;
3310 struct i40e_aqc_pf_vf_message *cmd =
3311 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3312 enum i40e_status_code status;
3314 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3315 cmd->id = CPU_TO_LE32(vfid);
3316 desc.cookie_high = CPU_TO_LE32(v_opcode);
3317 desc.cookie_low = CPU_TO_LE32(v_retval);
3318 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3320 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3322 if (msglen > I40E_AQ_LARGE_BUF)
3323 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3324 desc.datalen = CPU_TO_LE16(msglen);
3326 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3332 * i40e_aq_debug_read_register
3333 * @hw: pointer to the hw struct
3334 * @reg_addr: register address
3335 * @reg_val: register value
3336 * @cmd_details: pointer to command details structure or NULL
3338 * Read the register using the admin queue commands
3340 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3341 u32 reg_addr, u64 *reg_val,
3342 struct i40e_asq_cmd_details *cmd_details)
3344 struct i40e_aq_desc desc;
3345 struct i40e_aqc_debug_reg_read_write *cmd_resp =
3346 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3347 enum i40e_status_code status;
3349 if (reg_val == NULL)
3350 return I40E_ERR_PARAM;
3352 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3354 cmd_resp->address = CPU_TO_LE32(reg_addr);
3356 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3358 if (status == I40E_SUCCESS) {
3359 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3360 (u64)LE32_TO_CPU(cmd_resp->value_low);
3367 * i40e_aq_debug_write_register
3368 * @hw: pointer to the hw struct
3369 * @reg_addr: register address
3370 * @reg_val: register value
3371 * @cmd_details: pointer to command details structure or NULL
3373 * Write to a register using the admin queue commands
3375 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3376 u32 reg_addr, u64 reg_val,
3377 struct i40e_asq_cmd_details *cmd_details)
3379 struct i40e_aq_desc desc;
3380 struct i40e_aqc_debug_reg_read_write *cmd =
3381 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3382 enum i40e_status_code status;
3384 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3386 cmd->address = CPU_TO_LE32(reg_addr);
3387 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3388 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3390 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3396 * i40e_aq_request_resource
3397 * @hw: pointer to the hw struct
3398 * @resource: resource id
3399 * @access: access type
3400 * @sdp_number: resource number
3401 * @timeout: the maximum time in ms that the driver may hold the resource
3402 * @cmd_details: pointer to command details structure or NULL
3404 * requests common resource using the admin queue commands
3406 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3407 enum i40e_aq_resources_ids resource,
3408 enum i40e_aq_resource_access_type access,
3409 u8 sdp_number, u64 *timeout,
3410 struct i40e_asq_cmd_details *cmd_details)
3412 struct i40e_aq_desc desc;
3413 struct i40e_aqc_request_resource *cmd_resp =
3414 (struct i40e_aqc_request_resource *)&desc.params.raw;
3415 enum i40e_status_code status;
3417 DEBUGFUNC("i40e_aq_request_resource");
3419 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3421 cmd_resp->resource_id = CPU_TO_LE16(resource);
3422 cmd_resp->access_type = CPU_TO_LE16(access);
3423 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3425 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3426 /* The completion specifies the maximum time in ms that the driver
3427 * may hold the resource in the Timeout field.
3428 * If the resource is held by someone else, the command completes with
3429 * busy return value and the timeout field indicates the maximum time
3430 * the current owner of the resource has to free it.
3432 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3433 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3439 * i40e_aq_release_resource
3440 * @hw: pointer to the hw struct
3441 * @resource: resource id
3442 * @sdp_number: resource number
3443 * @cmd_details: pointer to command details structure or NULL
3445 * release common resource using the admin queue commands
3447 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3448 enum i40e_aq_resources_ids resource,
3450 struct i40e_asq_cmd_details *cmd_details)
3452 struct i40e_aq_desc desc;
3453 struct i40e_aqc_request_resource *cmd =
3454 (struct i40e_aqc_request_resource *)&desc.params.raw;
3455 enum i40e_status_code status;
3457 DEBUGFUNC("i40e_aq_release_resource");
3459 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3461 cmd->resource_id = CPU_TO_LE16(resource);
3462 cmd->resource_number = CPU_TO_LE32(sdp_number);
3464 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3471 * @hw: pointer to the hw struct
3472 * @module_pointer: module pointer location in words from the NVM beginning
3473 * @offset: byte offset from the module beginning
3474 * @length: length of the section to be read (in bytes from the offset)
3475 * @data: command buffer (size [bytes] = length)
3476 * @last_command: tells if this is the last command in a series
3477 * @cmd_details: pointer to command details structure or NULL
3479 * Read the NVM using the admin queue commands
3481 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3482 u32 offset, u16 length, void *data,
3484 struct i40e_asq_cmd_details *cmd_details)
3486 struct i40e_aq_desc desc;
3487 struct i40e_aqc_nvm_update *cmd =
3488 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3489 enum i40e_status_code status;
3491 DEBUGFUNC("i40e_aq_read_nvm");
3493 /* In offset the highest byte must be zeroed. */
3494 if (offset & 0xFF000000) {
3495 status = I40E_ERR_PARAM;
3496 goto i40e_aq_read_nvm_exit;
3499 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3501 /* If this is the last command in a series, set the proper flag. */
3503 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3504 cmd->module_pointer = module_pointer;
3505 cmd->offset = CPU_TO_LE32(offset);
3506 cmd->length = CPU_TO_LE16(length);
3508 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3509 if (length > I40E_AQ_LARGE_BUF)
3510 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3512 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3514 i40e_aq_read_nvm_exit:
3519 * i40e_aq_read_nvm_config - read an nvm config block
3520 * @hw: pointer to the hw struct
3521 * @cmd_flags: NVM access admin command bits
3522 * @field_id: field or feature id
3523 * @data: buffer for result
3524 * @buf_size: buffer size
3525 * @element_count: pointer to count of elements read by FW
3526 * @cmd_details: pointer to command details structure or NULL
3528 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3529 u8 cmd_flags, u32 field_id, void *data,
3530 u16 buf_size, u16 *element_count,
3531 struct i40e_asq_cmd_details *cmd_details)
3533 struct i40e_aq_desc desc;
3534 struct i40e_aqc_nvm_config_read *cmd =
3535 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3536 enum i40e_status_code status;
3538 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3539 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3540 if (buf_size > I40E_AQ_LARGE_BUF)
3541 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3543 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3544 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3545 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3546 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3548 cmd->element_id_msw = 0;
3550 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3552 if (!status && element_count)
3553 *element_count = LE16_TO_CPU(cmd->element_count);
3559 * i40e_aq_write_nvm_config - write an nvm config block
3560 * @hw: pointer to the hw struct
3561 * @cmd_flags: NVM access admin command bits
3562 * @data: buffer for result
3563 * @buf_size: buffer size
3564 * @element_count: count of elements to be written
3565 * @cmd_details: pointer to command details structure or NULL
3567 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3568 u8 cmd_flags, void *data, u16 buf_size,
3570 struct i40e_asq_cmd_details *cmd_details)
3572 struct i40e_aq_desc desc;
3573 struct i40e_aqc_nvm_config_write *cmd =
3574 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3575 enum i40e_status_code status;
3577 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3578 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3579 if (buf_size > I40E_AQ_LARGE_BUF)
3580 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3582 cmd->element_count = CPU_TO_LE16(element_count);
3583 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3584 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3590 * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3591 * @hw: pointer to the hw struct
3592 * @cmd_details: pointer to command details structure or NULL
3594 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3595 void *buff, u16 buff_size,
3596 struct i40e_asq_cmd_details *cmd_details)
3598 struct i40e_aq_desc desc;
3599 enum i40e_status_code status;
3601 UNREFERENCED_2PARAMETER(buff, buff_size);
3603 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3604 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3605 if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3606 status = I40E_ERR_NOT_IMPLEMENTED;
3613 * @hw: pointer to the hw struct
3614 * @module_pointer: module pointer location in words from the NVM beginning
3615 * @offset: offset in the module (expressed in 4 KB from module's beginning)
3616 * @length: length of the section to be erased (expressed in 4 KB)
3617 * @last_command: tells if this is the last command in a series
3618 * @cmd_details: pointer to command details structure or NULL
3620 * Erase the NVM sector using the admin queue commands
3622 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3623 u32 offset, u16 length, bool last_command,
3624 struct i40e_asq_cmd_details *cmd_details)
3626 struct i40e_aq_desc desc;
3627 struct i40e_aqc_nvm_update *cmd =
3628 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3629 enum i40e_status_code status;
3631 DEBUGFUNC("i40e_aq_erase_nvm");
3633 /* In offset the highest byte must be zeroed. */
3634 if (offset & 0xFF000000) {
3635 status = I40E_ERR_PARAM;
3636 goto i40e_aq_erase_nvm_exit;
3639 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3641 /* If this is the last command in a series, set the proper flag. */
3643 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3644 cmd->module_pointer = module_pointer;
3645 cmd->offset = CPU_TO_LE32(offset);
3646 cmd->length = CPU_TO_LE16(length);
3648 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3650 i40e_aq_erase_nvm_exit:
3655 * i40e_parse_discover_capabilities
3656 * @hw: pointer to the hw struct
3657 * @buff: pointer to a buffer containing device/function capability records
3658 * @cap_count: number of capability records in the list
3659 * @list_type_opc: type of capabilities list to parse
3661 * Parse the device/function capabilities list.
3663 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3665 enum i40e_admin_queue_opc list_type_opc)
3667 struct i40e_aqc_list_capabilities_element_resp *cap;
3668 u32 valid_functions, num_functions;
3669 u32 number, logical_id, phys_id;
3670 struct i40e_hw_capabilities *p;
3675 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3677 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3678 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3679 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3680 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3684 for (i = 0; i < cap_count; i++, cap++) {
3685 id = LE16_TO_CPU(cap->id);
3686 number = LE32_TO_CPU(cap->number);
3687 logical_id = LE32_TO_CPU(cap->logical_id);
3688 phys_id = LE32_TO_CPU(cap->phys_id);
3689 major_rev = cap->major_rev;
3692 case I40E_AQ_CAP_ID_SWITCH_MODE:
3693 p->switch_mode = number;
3694 i40e_debug(hw, I40E_DEBUG_INIT,
3695 "HW Capability: Switch mode = %d\n",
3698 case I40E_AQ_CAP_ID_MNG_MODE:
3699 p->management_mode = number;
3700 if (major_rev > 1) {
3701 p->mng_protocols_over_mctp = logical_id;
3702 i40e_debug(hw, I40E_DEBUG_INIT,
3703 "HW Capability: Protocols over MCTP = %d\n",
3704 p->mng_protocols_over_mctp);
3706 p->mng_protocols_over_mctp = 0;
3708 i40e_debug(hw, I40E_DEBUG_INIT,
3709 "HW Capability: Management Mode = %d\n",
3710 p->management_mode);
3712 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3713 p->npar_enable = number;
3714 i40e_debug(hw, I40E_DEBUG_INIT,
3715 "HW Capability: NPAR enable = %d\n",
3718 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3720 i40e_debug(hw, I40E_DEBUG_INIT,
3721 "HW Capability: OS2BMC = %d\n", p->os2bmc);
3723 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3724 p->valid_functions = number;
3725 i40e_debug(hw, I40E_DEBUG_INIT,
3726 "HW Capability: Valid Functions = %d\n",
3727 p->valid_functions);
3729 case I40E_AQ_CAP_ID_SRIOV:
3731 p->sr_iov_1_1 = true;
3732 i40e_debug(hw, I40E_DEBUG_INIT,
3733 "HW Capability: SR-IOV = %d\n",
3736 case I40E_AQ_CAP_ID_VF:
3737 p->num_vfs = number;
3738 p->vf_base_id = logical_id;
3739 i40e_debug(hw, I40E_DEBUG_INIT,
3740 "HW Capability: VF count = %d\n",
3742 i40e_debug(hw, I40E_DEBUG_INIT,
3743 "HW Capability: VF base_id = %d\n",
3746 case I40E_AQ_CAP_ID_VMDQ:
3749 i40e_debug(hw, I40E_DEBUG_INIT,
3750 "HW Capability: VMDQ = %d\n", p->vmdq);
3752 case I40E_AQ_CAP_ID_8021QBG:
3754 p->evb_802_1_qbg = true;
3755 i40e_debug(hw, I40E_DEBUG_INIT,
3756 "HW Capability: 802.1Qbg = %d\n", number);
3758 case I40E_AQ_CAP_ID_8021QBR:
3760 p->evb_802_1_qbh = true;
3761 i40e_debug(hw, I40E_DEBUG_INIT,
3762 "HW Capability: 802.1Qbh = %d\n", number);
3764 case I40E_AQ_CAP_ID_VSI:
3765 p->num_vsis = number;
3766 i40e_debug(hw, I40E_DEBUG_INIT,
3767 "HW Capability: VSI count = %d\n",
3770 case I40E_AQ_CAP_ID_DCB:
3773 p->enabled_tcmap = logical_id;
3776 i40e_debug(hw, I40E_DEBUG_INIT,
3777 "HW Capability: DCB = %d\n", p->dcb);
3778 i40e_debug(hw, I40E_DEBUG_INIT,
3779 "HW Capability: TC Mapping = %d\n",
3781 i40e_debug(hw, I40E_DEBUG_INIT,
3782 "HW Capability: TC Max = %d\n", p->maxtc);
3784 case I40E_AQ_CAP_ID_FCOE:
3787 i40e_debug(hw, I40E_DEBUG_INIT,
3788 "HW Capability: FCOE = %d\n", p->fcoe);
3790 case I40E_AQ_CAP_ID_ISCSI:
3793 i40e_debug(hw, I40E_DEBUG_INIT,
3794 "HW Capability: iSCSI = %d\n", p->iscsi);
3796 case I40E_AQ_CAP_ID_RSS:
3798 p->rss_table_size = number;
3799 p->rss_table_entry_width = logical_id;
3800 i40e_debug(hw, I40E_DEBUG_INIT,
3801 "HW Capability: RSS = %d\n", p->rss);
3802 i40e_debug(hw, I40E_DEBUG_INIT,
3803 "HW Capability: RSS table size = %d\n",
3805 i40e_debug(hw, I40E_DEBUG_INIT,
3806 "HW Capability: RSS table width = %d\n",
3807 p->rss_table_entry_width);
3809 case I40E_AQ_CAP_ID_RXQ:
3810 p->num_rx_qp = number;
3811 p->base_queue = phys_id;
3812 i40e_debug(hw, I40E_DEBUG_INIT,
3813 "HW Capability: Rx QP = %d\n", number);
3814 i40e_debug(hw, I40E_DEBUG_INIT,
3815 "HW Capability: base_queue = %d\n",
3818 case I40E_AQ_CAP_ID_TXQ:
3819 p->num_tx_qp = number;
3820 p->base_queue = phys_id;
3821 i40e_debug(hw, I40E_DEBUG_INIT,
3822 "HW Capability: Tx QP = %d\n", number);
3823 i40e_debug(hw, I40E_DEBUG_INIT,
3824 "HW Capability: base_queue = %d\n",
3827 case I40E_AQ_CAP_ID_MSIX:
3828 p->num_msix_vectors = number;
3829 i40e_debug(hw, I40E_DEBUG_INIT,
3830 "HW Capability: MSIX vector count = %d\n",
3831 p->num_msix_vectors);
3833 case I40E_AQ_CAP_ID_VF_MSIX:
3834 p->num_msix_vectors_vf = number;
3835 i40e_debug(hw, I40E_DEBUG_INIT,
3836 "HW Capability: MSIX VF vector count = %d\n",
3837 p->num_msix_vectors_vf);
3839 case I40E_AQ_CAP_ID_FLEX10:
3840 if (major_rev == 1) {
3842 p->flex10_enable = true;
3843 p->flex10_capable = true;
3846 /* Capability revision >= 2 */
3848 p->flex10_enable = true;
3850 p->flex10_capable = true;
3852 p->flex10_mode = logical_id;
3853 p->flex10_status = phys_id;
3854 i40e_debug(hw, I40E_DEBUG_INIT,
3855 "HW Capability: Flex10 mode = %d\n",
3857 i40e_debug(hw, I40E_DEBUG_INIT,
3858 "HW Capability: Flex10 status = %d\n",
3861 case I40E_AQ_CAP_ID_CEM:
3864 i40e_debug(hw, I40E_DEBUG_INIT,
3865 "HW Capability: CEM = %d\n", p->mgmt_cem);
3867 case I40E_AQ_CAP_ID_IWARP:
3870 i40e_debug(hw, I40E_DEBUG_INIT,
3871 "HW Capability: iWARP = %d\n", p->iwarp);
3873 case I40E_AQ_CAP_ID_LED:
3874 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3875 p->led[phys_id] = true;
3876 i40e_debug(hw, I40E_DEBUG_INIT,
3877 "HW Capability: LED - PIN %d\n", phys_id);
3879 case I40E_AQ_CAP_ID_SDP:
3880 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3881 p->sdp[phys_id] = true;
3882 i40e_debug(hw, I40E_DEBUG_INIT,
3883 "HW Capability: SDP - PIN %d\n", phys_id);
3885 case I40E_AQ_CAP_ID_MDIO:
3887 p->mdio_port_num = phys_id;
3888 p->mdio_port_mode = logical_id;
3890 i40e_debug(hw, I40E_DEBUG_INIT,
3891 "HW Capability: MDIO port number = %d\n",
3893 i40e_debug(hw, I40E_DEBUG_INIT,
3894 "HW Capability: MDIO port mode = %d\n",
3897 case I40E_AQ_CAP_ID_1588:
3899 p->ieee_1588 = true;
3900 i40e_debug(hw, I40E_DEBUG_INIT,
3901 "HW Capability: IEEE 1588 = %d\n",
3904 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3906 p->fd_filters_guaranteed = number;
3907 p->fd_filters_best_effort = logical_id;
3908 i40e_debug(hw, I40E_DEBUG_INIT,
3909 "HW Capability: Flow Director = 1\n");
3910 i40e_debug(hw, I40E_DEBUG_INIT,
3911 "HW Capability: Guaranteed FD filters = %d\n",
3912 p->fd_filters_guaranteed);
3914 case I40E_AQ_CAP_ID_WSR_PROT:
3915 p->wr_csr_prot = (u64)number;
3916 p->wr_csr_prot |= (u64)logical_id << 32;
3917 i40e_debug(hw, I40E_DEBUG_INIT,
3918 "HW Capability: wr_csr_prot = 0x%llX\n\n",
3919 (p->wr_csr_prot & 0xffff));
3921 case I40E_AQ_CAP_ID_NVM_MGMT:
3922 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3923 p->sec_rev_disabled = true;
3924 if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3925 p->update_disabled = true;
3927 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3928 hw->num_wol_proxy_filters = (u16)number;
3929 hw->wol_proxy_vsi_seid = (u16)logical_id;
3930 p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3931 if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3932 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3934 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3935 p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3936 i40e_debug(hw, I40E_DEBUG_INIT,
3937 "HW Capability: WOL proxy filters = %d\n",
3938 hw->num_wol_proxy_filters);
3946 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3948 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3951 /* count the enabled ports (aka the "not disabled" ports) */
3953 for (i = 0; i < 4; i++) {
3954 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3957 /* use AQ read to get the physical register offset instead
3958 * of the port relative offset
3960 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3961 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3965 valid_functions = p->valid_functions;
3967 while (valid_functions) {
3968 if (valid_functions & 1)
3970 valid_functions >>= 1;
3973 /* partition id is 1-based, and functions are evenly spread
3974 * across the ports as partitions
3976 if (hw->num_ports != 0) {
3977 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3978 hw->num_partitions = num_functions / hw->num_ports;
3981 /* additional HW specific goodies that might
3982 * someday be HW version specific
3984 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3988 * i40e_aq_discover_capabilities
3989 * @hw: pointer to the hw struct
3990 * @buff: a virtual buffer to hold the capabilities
3991 * @buff_size: Size of the virtual buffer
3992 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3993 * @list_type_opc: capabilities type to discover - pass in the command opcode
3994 * @cmd_details: pointer to command details structure or NULL
3996 * Get the device capabilities descriptions from the firmware
3998 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3999 void *buff, u16 buff_size, u16 *data_size,
4000 enum i40e_admin_queue_opc list_type_opc,
4001 struct i40e_asq_cmd_details *cmd_details)
4003 struct i40e_aqc_list_capabilites *cmd;
4004 struct i40e_aq_desc desc;
4005 enum i40e_status_code status = I40E_SUCCESS;
4007 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
4009 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
4010 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
4011 status = I40E_ERR_PARAM;
4015 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
4017 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4018 if (buff_size > I40E_AQ_LARGE_BUF)
4019 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4021 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4022 *data_size = LE16_TO_CPU(desc.datalen);
4027 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
4035 * i40e_aq_update_nvm
4036 * @hw: pointer to the hw struct
4037 * @module_pointer: module pointer location in words from the NVM beginning
4038 * @offset: byte offset from the module beginning
4039 * @length: length of the section to be written (in bytes from the offset)
4040 * @data: command buffer (size [bytes] = length)
4041 * @last_command: tells if this is the last command in a series
4042 * @cmd_details: pointer to command details structure or NULL
4044 * Update the NVM using the admin queue commands
4046 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
4047 u32 offset, u16 length, void *data,
4049 struct i40e_asq_cmd_details *cmd_details)
4051 struct i40e_aq_desc desc;
4052 struct i40e_aqc_nvm_update *cmd =
4053 (struct i40e_aqc_nvm_update *)&desc.params.raw;
4054 enum i40e_status_code status;
4056 DEBUGFUNC("i40e_aq_update_nvm");
4058 /* In offset the highest byte must be zeroed. */
4059 if (offset & 0xFF000000) {
4060 status = I40E_ERR_PARAM;
4061 goto i40e_aq_update_nvm_exit;
4064 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4066 /* If this is the last command in a series, set the proper flag. */
4068 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
4069 cmd->module_pointer = module_pointer;
4070 cmd->offset = CPU_TO_LE32(offset);
4071 cmd->length = CPU_TO_LE16(length);
4073 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4074 if (length > I40E_AQ_LARGE_BUF)
4075 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4077 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
4079 i40e_aq_update_nvm_exit:
4084 * i40e_aq_get_lldp_mib
4085 * @hw: pointer to the hw struct
4086 * @bridge_type: type of bridge requested
4087 * @mib_type: Local, Remote or both Local and Remote MIBs
4088 * @buff: pointer to a user supplied buffer to store the MIB block
4089 * @buff_size: size of the buffer (in bytes)
4090 * @local_len : length of the returned Local LLDP MIB
4091 * @remote_len: length of the returned Remote LLDP MIB
4092 * @cmd_details: pointer to command details structure or NULL
4094 * Requests the complete LLDP MIB (entire packet).
4096 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4097 u8 mib_type, void *buff, u16 buff_size,
4098 u16 *local_len, u16 *remote_len,
4099 struct i40e_asq_cmd_details *cmd_details)
4101 struct i40e_aq_desc desc;
4102 struct i40e_aqc_lldp_get_mib *cmd =
4103 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4104 struct i40e_aqc_lldp_get_mib *resp =
4105 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4106 enum i40e_status_code status;
4108 if (buff_size == 0 || !buff)
4109 return I40E_ERR_PARAM;
4111 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4112 /* Indirect Command */
4113 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4115 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4116 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4117 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4119 desc.datalen = CPU_TO_LE16(buff_size);
4121 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4122 if (buff_size > I40E_AQ_LARGE_BUF)
4123 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4125 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4127 if (local_len != NULL)
4128 *local_len = LE16_TO_CPU(resp->local_len);
4129 if (remote_len != NULL)
4130 *remote_len = LE16_TO_CPU(resp->remote_len);
4137 * i40e_aq_set_lldp_mib - Set the LLDP MIB
4138 * @hw: pointer to the hw struct
4139 * @mib_type: Local, Remote or both Local and Remote MIBs
4140 * @buff: pointer to a user supplied buffer to store the MIB block
4141 * @buff_size: size of the buffer (in bytes)
4142 * @cmd_details: pointer to command details structure or NULL
4146 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4147 u8 mib_type, void *buff, u16 buff_size,
4148 struct i40e_asq_cmd_details *cmd_details)
4150 struct i40e_aq_desc desc;
4151 struct i40e_aqc_lldp_set_local_mib *cmd =
4152 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4153 enum i40e_status_code status;
4155 if (buff_size == 0 || !buff)
4156 return I40E_ERR_PARAM;
4158 i40e_fill_default_direct_cmd_desc(&desc,
4159 i40e_aqc_opc_lldp_set_local_mib);
4160 /* Indirect Command */
4161 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4162 if (buff_size > I40E_AQ_LARGE_BUF)
4163 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4164 desc.datalen = CPU_TO_LE16(buff_size);
4166 cmd->type = mib_type;
4167 cmd->length = CPU_TO_LE16(buff_size);
4168 cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4169 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4171 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4176 * i40e_aq_cfg_lldp_mib_change_event
4177 * @hw: pointer to the hw struct
4178 * @enable_update: Enable or Disable event posting
4179 * @cmd_details: pointer to command details structure or NULL
4181 * Enable or Disable posting of an event on ARQ when LLDP MIB
4182 * associated with the interface changes
4184 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4186 struct i40e_asq_cmd_details *cmd_details)
4188 struct i40e_aq_desc desc;
4189 struct i40e_aqc_lldp_update_mib *cmd =
4190 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4191 enum i40e_status_code status;
4193 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4196 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4198 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4204 * i40e_aq_add_lldp_tlv
4205 * @hw: pointer to the hw struct
4206 * @bridge_type: type of bridge
4207 * @buff: buffer with TLV to add
4208 * @buff_size: length of the buffer
4209 * @tlv_len: length of the TLV to be added
4210 * @mib_len: length of the LLDP MIB returned in response
4211 * @cmd_details: pointer to command details structure or NULL
4213 * Add the specified TLV to LLDP Local MIB for the given bridge type,
4214 * it is responsibility of the caller to make sure that the TLV is not
4215 * already present in the LLDPDU.
4216 * In return firmware will write the complete LLDP MIB with the newly
4217 * added TLV in the response buffer.
4219 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4220 void *buff, u16 buff_size, u16 tlv_len,
4222 struct i40e_asq_cmd_details *cmd_details)
4224 struct i40e_aq_desc desc;
4225 struct i40e_aqc_lldp_add_tlv *cmd =
4226 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4227 enum i40e_status_code status;
4229 if (buff_size == 0 || !buff || tlv_len == 0)
4230 return I40E_ERR_PARAM;
4232 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4234 /* Indirect Command */
4235 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4236 if (buff_size > I40E_AQ_LARGE_BUF)
4237 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4238 desc.datalen = CPU_TO_LE16(buff_size);
4240 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4241 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4242 cmd->len = CPU_TO_LE16(tlv_len);
4244 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4246 if (mib_len != NULL)
4247 *mib_len = LE16_TO_CPU(desc.datalen);
4254 * i40e_aq_update_lldp_tlv
4255 * @hw: pointer to the hw struct
4256 * @bridge_type: type of bridge
4257 * @buff: buffer with TLV to update
4258 * @buff_size: size of the buffer holding original and updated TLVs
4259 * @old_len: Length of the Original TLV
4260 * @new_len: Length of the Updated TLV
4261 * @offset: offset of the updated TLV in the buff
4262 * @mib_len: length of the returned LLDP MIB
4263 * @cmd_details: pointer to command details structure or NULL
4265 * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4266 * Firmware will place the complete LLDP MIB in response buffer with the
4269 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4270 u8 bridge_type, void *buff, u16 buff_size,
4271 u16 old_len, u16 new_len, u16 offset,
4273 struct i40e_asq_cmd_details *cmd_details)
4275 struct i40e_aq_desc desc;
4276 struct i40e_aqc_lldp_update_tlv *cmd =
4277 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4278 enum i40e_status_code status;
4280 if (buff_size == 0 || !buff || offset == 0 ||
4281 old_len == 0 || new_len == 0)
4282 return I40E_ERR_PARAM;
4284 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4286 /* Indirect Command */
4287 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4288 if (buff_size > I40E_AQ_LARGE_BUF)
4289 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4290 desc.datalen = CPU_TO_LE16(buff_size);
4292 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4293 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4294 cmd->old_len = CPU_TO_LE16(old_len);
4295 cmd->new_offset = CPU_TO_LE16(offset);
4296 cmd->new_len = CPU_TO_LE16(new_len);
4298 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4300 if (mib_len != NULL)
4301 *mib_len = LE16_TO_CPU(desc.datalen);
4308 * i40e_aq_delete_lldp_tlv
4309 * @hw: pointer to the hw struct
4310 * @bridge_type: type of bridge
4311 * @buff: pointer to a user supplied buffer that has the TLV
4312 * @buff_size: length of the buffer
4313 * @tlv_len: length of the TLV to be deleted
4314 * @mib_len: length of the returned LLDP MIB
4315 * @cmd_details: pointer to command details structure or NULL
4317 * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4318 * The firmware places the entire LLDP MIB in the response buffer.
4320 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4321 u8 bridge_type, void *buff, u16 buff_size,
4322 u16 tlv_len, u16 *mib_len,
4323 struct i40e_asq_cmd_details *cmd_details)
4325 struct i40e_aq_desc desc;
4326 struct i40e_aqc_lldp_add_tlv *cmd =
4327 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4328 enum i40e_status_code status;
4330 if (buff_size == 0 || !buff)
4331 return I40E_ERR_PARAM;
4333 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4335 /* Indirect Command */
4336 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4337 if (buff_size > I40E_AQ_LARGE_BUF)
4338 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4339 desc.datalen = CPU_TO_LE16(buff_size);
4340 cmd->len = CPU_TO_LE16(tlv_len);
4341 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4342 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4344 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4346 if (mib_len != NULL)
4347 *mib_len = LE16_TO_CPU(desc.datalen);
4355 * @hw: pointer to the hw struct
4356 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4357 * @cmd_details: pointer to command details structure or NULL
4359 * Stop or Shutdown the embedded LLDP Agent
4361 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4362 struct i40e_asq_cmd_details *cmd_details)
4364 struct i40e_aq_desc desc;
4365 struct i40e_aqc_lldp_stop *cmd =
4366 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4367 enum i40e_status_code status;
4369 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4372 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4374 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4380 * i40e_aq_start_lldp
4381 * @hw: pointer to the hw struct
4382 * @cmd_details: pointer to command details structure or NULL
4384 * Start the embedded LLDP Agent on all ports.
4386 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4387 struct i40e_asq_cmd_details *cmd_details)
4389 struct i40e_aq_desc desc;
4390 struct i40e_aqc_lldp_start *cmd =
4391 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4392 enum i40e_status_code status;
4394 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4396 cmd->command = I40E_AQ_LLDP_AGENT_START;
4398 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4404 * i40e_aq_get_cee_dcb_config
4405 * @hw: pointer to the hw struct
4406 * @buff: response buffer that stores CEE operational configuration
4407 * @buff_size: size of the buffer passed
4408 * @cmd_details: pointer to command details structure or NULL
4410 * Get CEE DCBX mode operational configuration from firmware
4412 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4413 void *buff, u16 buff_size,
4414 struct i40e_asq_cmd_details *cmd_details)
4416 struct i40e_aq_desc desc;
4417 enum i40e_status_code status;
4419 if (buff_size == 0 || !buff)
4420 return I40E_ERR_PARAM;
4422 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4424 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4425 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4432 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4433 * @hw: pointer to the hw struct
4434 * @start_agent: True if DCBx Agent needs to be Started
4435 * False if DCBx Agent needs to be Stopped
4436 * @cmd_details: pointer to command details structure or NULL
4438 * Start/Stop the embedded dcbx Agent
4440 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4442 struct i40e_asq_cmd_details *cmd_details)
4444 struct i40e_aq_desc desc;
4445 struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4446 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4448 enum i40e_status_code status;
4450 i40e_fill_default_direct_cmd_desc(&desc,
4451 i40e_aqc_opc_lldp_stop_start_spec_agent);
4454 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4456 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4462 * i40e_aq_add_udp_tunnel
4463 * @hw: pointer to the hw struct
4464 * @udp_port: the UDP port to add in Host byte order
4465 * @header_len: length of the tunneling header length in DWords
4466 * @protocol_index: protocol index type
4467 * @filter_index: pointer to filter index
4468 * @cmd_details: pointer to command details structure or NULL
4470 * Note: Firmware expects the udp_port value to be in Little Endian format,
4471 * and this function will call CPU_TO_LE16 to convert from Host byte order to
4472 * Little Endian order.
4474 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4475 u16 udp_port, u8 protocol_index,
4477 struct i40e_asq_cmd_details *cmd_details)
4479 struct i40e_aq_desc desc;
4480 struct i40e_aqc_add_udp_tunnel *cmd =
4481 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4482 struct i40e_aqc_del_udp_tunnel_completion *resp =
4483 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4484 enum i40e_status_code status;
4486 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4488 cmd->udp_port = CPU_TO_LE16(udp_port);
4489 cmd->protocol_type = protocol_index;
4491 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4493 if (!status && filter_index)
4494 *filter_index = resp->index;
4500 * i40e_aq_del_udp_tunnel
4501 * @hw: pointer to the hw struct
4502 * @index: filter index
4503 * @cmd_details: pointer to command details structure or NULL
4505 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4506 struct i40e_asq_cmd_details *cmd_details)
4508 struct i40e_aq_desc desc;
4509 struct i40e_aqc_remove_udp_tunnel *cmd =
4510 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4511 enum i40e_status_code status;
4513 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4517 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4523 * i40e_aq_get_switch_resource_alloc (0x0204)
4524 * @hw: pointer to the hw struct
4525 * @num_entries: pointer to u8 to store the number of resource entries returned
4526 * @buf: pointer to a user supplied buffer. This buffer must be large enough
4527 * to store the resource information for all resource types. Each
4528 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
4529 * @count: size, in bytes, of the buffer provided
4530 * @cmd_details: pointer to command details structure or NULL
4532 * Query the resources allocated to a function.
4534 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4536 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4538 struct i40e_asq_cmd_details *cmd_details)
4540 struct i40e_aq_desc desc;
4541 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4542 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4543 enum i40e_status_code status;
4544 u16 length = count * sizeof(*buf);
4546 i40e_fill_default_direct_cmd_desc(&desc,
4547 i40e_aqc_opc_get_switch_resource_alloc);
4549 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4550 if (length > I40E_AQ_LARGE_BUF)
4551 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4553 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4555 if (!status && num_entries)
4556 *num_entries = cmd_resp->num_entries;
4562 * i40e_aq_delete_element - Delete switch element
4563 * @hw: pointer to the hw struct
4564 * @seid: the SEID to delete from the switch
4565 * @cmd_details: pointer to command details structure or NULL
4567 * This deletes a switch element from the switch.
4569 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4570 struct i40e_asq_cmd_details *cmd_details)
4572 struct i40e_aq_desc desc;
4573 struct i40e_aqc_switch_seid *cmd =
4574 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4575 enum i40e_status_code status;
4578 return I40E_ERR_PARAM;
4580 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4582 cmd->seid = CPU_TO_LE16(seid);
4584 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4590 * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4591 * @hw: pointer to the hw struct
4592 * @flags: component flags
4593 * @mac_seid: uplink seid (MAC SEID)
4594 * @vsi_seid: connected vsi seid
4595 * @ret_seid: seid of create pv component
4597 * This instantiates an i40e port virtualizer with specified flags.
4598 * Depending on specified flags the port virtualizer can act as a
4599 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4601 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4602 u16 mac_seid, u16 vsi_seid,
4605 struct i40e_aq_desc desc;
4606 struct i40e_aqc_add_update_pv *cmd =
4607 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4608 struct i40e_aqc_add_update_pv_completion *resp =
4609 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4610 enum i40e_status_code status;
4613 return I40E_ERR_PARAM;
4615 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4616 cmd->command_flags = CPU_TO_LE16(flags);
4617 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4618 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4620 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4621 if (!status && ret_seid)
4622 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4628 * i40e_aq_add_tag - Add an S/E-tag
4629 * @hw: pointer to the hw struct
4630 * @direct_to_queue: should s-tag direct flow to a specific queue
4631 * @vsi_seid: VSI SEID to use this tag
4632 * @tag: value of the tag
4633 * @queue_num: queue number, only valid is direct_to_queue is true
4634 * @tags_used: return value, number of tags in use by this PF
4635 * @tags_free: return value, number of unallocated tags
4636 * @cmd_details: pointer to command details structure or NULL
4638 * This associates an S- or E-tag to a VSI in the switch complex. It returns
4639 * the number of tags allocated by the PF, and the number of unallocated
4642 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4643 u16 vsi_seid, u16 tag, u16 queue_num,
4644 u16 *tags_used, u16 *tags_free,
4645 struct i40e_asq_cmd_details *cmd_details)
4647 struct i40e_aq_desc desc;
4648 struct i40e_aqc_add_tag *cmd =
4649 (struct i40e_aqc_add_tag *)&desc.params.raw;
4650 struct i40e_aqc_add_remove_tag_completion *resp =
4651 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4652 enum i40e_status_code status;
4655 return I40E_ERR_PARAM;
4657 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4659 cmd->seid = CPU_TO_LE16(vsi_seid);
4660 cmd->tag = CPU_TO_LE16(tag);
4661 if (direct_to_queue) {
4662 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4663 cmd->queue_number = CPU_TO_LE16(queue_num);
4666 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4669 if (tags_used != NULL)
4670 *tags_used = LE16_TO_CPU(resp->tags_used);
4671 if (tags_free != NULL)
4672 *tags_free = LE16_TO_CPU(resp->tags_free);
4679 * i40e_aq_remove_tag - Remove an S- or E-tag
4680 * @hw: pointer to the hw struct
4681 * @vsi_seid: VSI SEID this tag is associated with
4682 * @tag: value of the S-tag to delete
4683 * @tags_used: return value, number of tags in use by this PF
4684 * @tags_free: return value, number of unallocated tags
4685 * @cmd_details: pointer to command details structure or NULL
4687 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
4688 * the number of tags allocated by the PF, and the number of unallocated
4691 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4692 u16 tag, u16 *tags_used, u16 *tags_free,
4693 struct i40e_asq_cmd_details *cmd_details)
4695 struct i40e_aq_desc desc;
4696 struct i40e_aqc_remove_tag *cmd =
4697 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4698 struct i40e_aqc_add_remove_tag_completion *resp =
4699 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4700 enum i40e_status_code status;
4703 return I40E_ERR_PARAM;
4705 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4707 cmd->seid = CPU_TO_LE16(vsi_seid);
4708 cmd->tag = CPU_TO_LE16(tag);
4710 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4713 if (tags_used != NULL)
4714 *tags_used = LE16_TO_CPU(resp->tags_used);
4715 if (tags_free != NULL)
4716 *tags_free = LE16_TO_CPU(resp->tags_free);
4723 * i40e_aq_add_mcast_etag - Add a multicast E-tag
4724 * @hw: pointer to the hw struct
4725 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4726 * @etag: value of E-tag to add
4727 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4728 * @buf: address of indirect buffer
4729 * @tags_used: return value, number of E-tags in use by this port
4730 * @tags_free: return value, number of unallocated M-tags
4731 * @cmd_details: pointer to command details structure or NULL
4733 * This associates a multicast E-tag to a port virtualizer. It will return
4734 * the number of tags allocated by the PF, and the number of unallocated
4737 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4738 * num_tags_in_buf long.
4740 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4741 u16 etag, u8 num_tags_in_buf, void *buf,
4742 u16 *tags_used, u16 *tags_free,
4743 struct i40e_asq_cmd_details *cmd_details)
4745 struct i40e_aq_desc desc;
4746 struct i40e_aqc_add_remove_mcast_etag *cmd =
4747 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4748 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4749 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4750 enum i40e_status_code status;
4751 u16 length = sizeof(u16) * num_tags_in_buf;
4753 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4754 return I40E_ERR_PARAM;
4756 i40e_fill_default_direct_cmd_desc(&desc,
4757 i40e_aqc_opc_add_multicast_etag);
4759 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4760 cmd->etag = CPU_TO_LE16(etag);
4761 cmd->num_unicast_etags = num_tags_in_buf;
4763 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4764 if (length > I40E_AQ_LARGE_BUF)
4765 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4767 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4770 if (tags_used != NULL)
4771 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4772 if (tags_free != NULL)
4773 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4780 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4781 * @hw: pointer to the hw struct
4782 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4783 * @etag: value of the E-tag to remove
4784 * @tags_used: return value, number of tags in use by this port
4785 * @tags_free: return value, number of unallocated tags
4786 * @cmd_details: pointer to command details structure or NULL
4788 * This deletes an E-tag from the port virtualizer. It will return
4789 * the number of tags allocated by the port, and the number of unallocated
4792 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4793 u16 etag, u16 *tags_used, u16 *tags_free,
4794 struct i40e_asq_cmd_details *cmd_details)
4796 struct i40e_aq_desc desc;
4797 struct i40e_aqc_add_remove_mcast_etag *cmd =
4798 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4799 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4800 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4801 enum i40e_status_code status;
4805 return I40E_ERR_PARAM;
4807 i40e_fill_default_direct_cmd_desc(&desc,
4808 i40e_aqc_opc_remove_multicast_etag);
4810 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4811 cmd->etag = CPU_TO_LE16(etag);
4813 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4816 if (tags_used != NULL)
4817 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4818 if (tags_free != NULL)
4819 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4826 * i40e_aq_update_tag - Update an S/E-tag
4827 * @hw: pointer to the hw struct
4828 * @vsi_seid: VSI SEID using this S-tag
4829 * @old_tag: old tag value
4830 * @new_tag: new tag value
4831 * @tags_used: return value, number of tags in use by this PF
4832 * @tags_free: return value, number of unallocated tags
4833 * @cmd_details: pointer to command details structure or NULL
4835 * This updates the value of the tag currently attached to this VSI
4836 * in the switch complex. It will return the number of tags allocated
4837 * by the PF, and the number of unallocated tags available.
4839 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4840 u16 old_tag, u16 new_tag, u16 *tags_used,
4842 struct i40e_asq_cmd_details *cmd_details)
4844 struct i40e_aq_desc desc;
4845 struct i40e_aqc_update_tag *cmd =
4846 (struct i40e_aqc_update_tag *)&desc.params.raw;
4847 struct i40e_aqc_update_tag_completion *resp =
4848 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4849 enum i40e_status_code status;
4852 return I40E_ERR_PARAM;
4854 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4856 cmd->seid = CPU_TO_LE16(vsi_seid);
4857 cmd->old_tag = CPU_TO_LE16(old_tag);
4858 cmd->new_tag = CPU_TO_LE16(new_tag);
4860 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4863 if (tags_used != NULL)
4864 *tags_used = LE16_TO_CPU(resp->tags_used);
4865 if (tags_free != NULL)
4866 *tags_free = LE16_TO_CPU(resp->tags_free);
4873 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4874 * @hw: pointer to the hw struct
4875 * @tcmap: TC map for request/release any ignore PFC condition
4876 * @request: request or release ignore PFC condition
4877 * @tcmap_ret: return TCs for which PFC is currently ignored
4878 * @cmd_details: pointer to command details structure or NULL
4880 * This sends out request/release to ignore PFC condition for a TC.
4881 * It will return the TCs for which PFC is currently ignored.
4883 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4884 bool request, u8 *tcmap_ret,
4885 struct i40e_asq_cmd_details *cmd_details)
4887 struct i40e_aq_desc desc;
4888 struct i40e_aqc_pfc_ignore *cmd_resp =
4889 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4890 enum i40e_status_code status;
4892 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4895 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4897 cmd_resp->tc_bitmap = tcmap;
4899 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4902 if (tcmap_ret != NULL)
4903 *tcmap_ret = cmd_resp->tc_bitmap;
4910 * i40e_aq_dcb_updated - DCB Updated Command
4911 * @hw: pointer to the hw struct
4912 * @cmd_details: pointer to command details structure or NULL
4914 * When LLDP is handled in PF this command is used by the PF
4915 * to notify EMP that a DCB setting is modified.
4916 * When LLDP is handled in EMP this command is used by the PF
4917 * to notify EMP whenever one of the following parameters get
4919 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4920 * - PCIRTT in PRTDCB_GENC.PCIRTT
4921 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4922 * EMP will return when the shared RPB settings have been
4923 * recomputed and modified. The retval field in the descriptor
4924 * will be set to 0 when RPB is modified.
4926 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4927 struct i40e_asq_cmd_details *cmd_details)
4929 struct i40e_aq_desc desc;
4930 enum i40e_status_code status;
4932 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4934 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4940 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4941 * @hw: pointer to the hw struct
4942 * @seid: defines the SEID of the switch for which the stats are requested
4943 * @vlan_id: the VLAN ID for which the statistics are requested
4944 * @stat_index: index of the statistics counters block assigned to this VLAN
4945 * @cmd_details: pointer to command details structure or NULL
4947 * XL710 supports 128 smonVlanStats counters.This command is used to
4948 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4951 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4952 u16 vlan_id, u16 *stat_index,
4953 struct i40e_asq_cmd_details *cmd_details)
4955 struct i40e_aq_desc desc;
4956 struct i40e_aqc_add_remove_statistics *cmd_resp =
4957 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4958 enum i40e_status_code status;
4960 if ((seid == 0) || (stat_index == NULL))
4961 return I40E_ERR_PARAM;
4963 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4965 cmd_resp->seid = CPU_TO_LE16(seid);
4966 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4968 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4970 if (!status && stat_index)
4971 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4977 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4978 * @hw: pointer to the hw struct
4979 * @seid: defines the SEID of the switch for which the stats are requested
4980 * @vlan_id: the VLAN ID for which the statistics are requested
4981 * @stat_index: index of the statistics counters block assigned to this VLAN
4982 * @cmd_details: pointer to command details structure or NULL
4984 * XL710 supports 128 smonVlanStats counters.This command is used to
4985 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4988 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4989 u16 vlan_id, u16 stat_index,
4990 struct i40e_asq_cmd_details *cmd_details)
4992 struct i40e_aq_desc desc;
4993 struct i40e_aqc_add_remove_statistics *cmd =
4994 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4995 enum i40e_status_code status;
4998 return I40E_ERR_PARAM;
5000 i40e_fill_default_direct_cmd_desc(&desc,
5001 i40e_aqc_opc_remove_statistics);
5003 cmd->seid = CPU_TO_LE16(seid);
5004 cmd->vlan = CPU_TO_LE16(vlan_id);
5005 cmd->stat_index = CPU_TO_LE16(stat_index);
5007 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5013 * i40e_aq_set_port_parameters - set physical port parameters.
5014 * @hw: pointer to the hw struct
5015 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
5016 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
5017 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
5018 * @double_vlan: if set double VLAN is enabled
5019 * @cmd_details: pointer to command details structure or NULL
5021 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
5022 u16 bad_frame_vsi, bool save_bad_pac,
5023 bool pad_short_pac, bool double_vlan,
5024 struct i40e_asq_cmd_details *cmd_details)
5026 struct i40e_aqc_set_port_parameters *cmd;
5027 enum i40e_status_code status;
5028 struct i40e_aq_desc desc;
5029 u16 command_flags = 0;
5031 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
5033 i40e_fill_default_direct_cmd_desc(&desc,
5034 i40e_aqc_opc_set_port_parameters);
5036 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
5038 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
5040 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
5042 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
5043 cmd->command_flags = CPU_TO_LE16(command_flags);
5045 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5051 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
5052 * @hw: pointer to the hw struct
5053 * @seid: seid for the physical port/switching component/vsi
5054 * @buff: Indirect buffer to hold data parameters and response
5055 * @buff_size: Indirect buffer size
5056 * @opcode: Tx scheduler AQ command opcode
5057 * @cmd_details: pointer to command details structure or NULL
5059 * Generic command handler for Tx scheduler AQ commands
5061 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
5062 void *buff, u16 buff_size,
5063 enum i40e_admin_queue_opc opcode,
5064 struct i40e_asq_cmd_details *cmd_details)
5066 struct i40e_aq_desc desc;
5067 struct i40e_aqc_tx_sched_ind *cmd =
5068 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
5069 enum i40e_status_code status;
5070 bool cmd_param_flag = false;
5073 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
5074 case i40e_aqc_opc_configure_vsi_tc_bw:
5075 case i40e_aqc_opc_enable_switching_comp_ets:
5076 case i40e_aqc_opc_modify_switching_comp_ets:
5077 case i40e_aqc_opc_disable_switching_comp_ets:
5078 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
5079 case i40e_aqc_opc_configure_switching_comp_bw_config:
5080 cmd_param_flag = true;
5082 case i40e_aqc_opc_query_vsi_bw_config:
5083 case i40e_aqc_opc_query_vsi_ets_sla_config:
5084 case i40e_aqc_opc_query_switching_comp_ets_config:
5085 case i40e_aqc_opc_query_port_ets_config:
5086 case i40e_aqc_opc_query_switching_comp_bw_config:
5087 cmd_param_flag = false;
5090 return I40E_ERR_PARAM;
5093 i40e_fill_default_direct_cmd_desc(&desc, opcode);
5095 /* Indirect command */
5096 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5098 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5099 if (buff_size > I40E_AQ_LARGE_BUF)
5100 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5102 desc.datalen = CPU_TO_LE16(buff_size);
5104 cmd->vsi_seid = CPU_TO_LE16(seid);
5106 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5112 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5113 * @hw: pointer to the hw struct
5115 * @credit: BW limit credits (0 = disabled)
5116 * @max_credit: Max BW limit credits
5117 * @cmd_details: pointer to command details structure or NULL
5119 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5120 u16 seid, u16 credit, u8 max_credit,
5121 struct i40e_asq_cmd_details *cmd_details)
5123 struct i40e_aq_desc desc;
5124 struct i40e_aqc_configure_vsi_bw_limit *cmd =
5125 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5126 enum i40e_status_code status;
5128 i40e_fill_default_direct_cmd_desc(&desc,
5129 i40e_aqc_opc_configure_vsi_bw_limit);
5131 cmd->vsi_seid = CPU_TO_LE16(seid);
5132 cmd->credit = CPU_TO_LE16(credit);
5133 cmd->max_credit = max_credit;
5135 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5141 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5142 * @hw: pointer to the hw struct
5143 * @seid: switching component seid
5144 * @credit: BW limit credits (0 = disabled)
5145 * @max_bw: Max BW limit credits
5146 * @cmd_details: pointer to command details structure or NULL
5148 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5149 u16 seid, u16 credit, u8 max_bw,
5150 struct i40e_asq_cmd_details *cmd_details)
5152 struct i40e_aq_desc desc;
5153 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5154 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5155 enum i40e_status_code status;
5157 i40e_fill_default_direct_cmd_desc(&desc,
5158 i40e_aqc_opc_configure_switching_comp_bw_limit);
5160 cmd->seid = CPU_TO_LE16(seid);
5161 cmd->credit = CPU_TO_LE16(credit);
5162 cmd->max_bw = max_bw;
5164 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5170 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5171 * @hw: pointer to the hw struct
5173 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5174 * @cmd_details: pointer to command details structure or NULL
5176 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5178 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5179 struct i40e_asq_cmd_details *cmd_details)
5181 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5182 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5187 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5188 * @hw: pointer to the hw struct
5190 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5191 * @cmd_details: pointer to command details structure or NULL
5193 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5195 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5196 struct i40e_asq_cmd_details *cmd_details)
5198 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5199 i40e_aqc_opc_configure_vsi_tc_bw,
5204 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5205 * @hw: pointer to the hw struct
5206 * @seid: seid of the switching component connected to Physical Port
5207 * @ets_data: Buffer holding ETS parameters
5208 * @cmd_details: pointer to command details structure or NULL
5210 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5212 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5213 enum i40e_admin_queue_opc opcode,
5214 struct i40e_asq_cmd_details *cmd_details)
5216 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5217 sizeof(*ets_data), opcode, cmd_details);
5221 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5222 * @hw: pointer to the hw struct
5223 * @seid: seid of the switching component
5224 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5225 * @cmd_details: pointer to command details structure or NULL
5227 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5229 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5230 struct i40e_asq_cmd_details *cmd_details)
5232 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5233 i40e_aqc_opc_configure_switching_comp_bw_config,
5238 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5239 * @hw: pointer to the hw struct
5240 * @seid: seid of the switching component
5241 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5242 * @cmd_details: pointer to command details structure or NULL
5244 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5245 struct i40e_hw *hw, u16 seid,
5246 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5247 struct i40e_asq_cmd_details *cmd_details)
5249 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5250 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5255 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5256 * @hw: pointer to the hw struct
5257 * @seid: seid of the VSI
5258 * @bw_data: Buffer to hold VSI BW configuration
5259 * @cmd_details: pointer to command details structure or NULL
5261 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5263 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5264 struct i40e_asq_cmd_details *cmd_details)
5266 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5267 i40e_aqc_opc_query_vsi_bw_config,
5272 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5273 * @hw: pointer to the hw struct
5274 * @seid: seid of the VSI
5275 * @bw_data: Buffer to hold VSI BW configuration per TC
5276 * @cmd_details: pointer to command details structure or NULL
5278 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5280 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5281 struct i40e_asq_cmd_details *cmd_details)
5283 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5284 i40e_aqc_opc_query_vsi_ets_sla_config,
5289 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5290 * @hw: pointer to the hw struct
5291 * @seid: seid of the switching component
5292 * @bw_data: Buffer to hold switching component's per TC BW config
5293 * @cmd_details: pointer to command details structure or NULL
5295 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5297 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5298 struct i40e_asq_cmd_details *cmd_details)
5300 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5301 i40e_aqc_opc_query_switching_comp_ets_config,
5306 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5307 * @hw: pointer to the hw struct
5308 * @seid: seid of the VSI or switching component connected to Physical Port
5309 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5310 * @cmd_details: pointer to command details structure or NULL
5312 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5314 struct i40e_aqc_query_port_ets_config_resp *bw_data,
5315 struct i40e_asq_cmd_details *cmd_details)
5317 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5318 i40e_aqc_opc_query_port_ets_config,
5323 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5324 * @hw: pointer to the hw struct
5325 * @seid: seid of the switching component
5326 * @bw_data: Buffer to hold switching component's BW configuration
5327 * @cmd_details: pointer to command details structure or NULL
5329 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5331 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5332 struct i40e_asq_cmd_details *cmd_details)
5334 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5335 i40e_aqc_opc_query_switching_comp_bw_config,
5340 * i40e_validate_filter_settings
5341 * @hw: pointer to the hardware structure
5342 * @settings: Filter control settings
5344 * Check and validate the filter control settings passed.
5345 * The function checks for the valid filter/context sizes being
5346 * passed for FCoE and PE.
5348 * Returns I40E_SUCCESS if the values passed are valid and within
5349 * range else returns an error.
5351 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5352 struct i40e_filter_control_settings *settings)
5354 u32 fcoe_cntx_size, fcoe_filt_size;
5355 u32 pe_cntx_size, pe_filt_size;
5360 /* Validate FCoE settings passed */
5361 switch (settings->fcoe_filt_num) {
5362 case I40E_HASH_FILTER_SIZE_1K:
5363 case I40E_HASH_FILTER_SIZE_2K:
5364 case I40E_HASH_FILTER_SIZE_4K:
5365 case I40E_HASH_FILTER_SIZE_8K:
5366 case I40E_HASH_FILTER_SIZE_16K:
5367 case I40E_HASH_FILTER_SIZE_32K:
5368 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5369 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5372 return I40E_ERR_PARAM;
5375 switch (settings->fcoe_cntx_num) {
5376 case I40E_DMA_CNTX_SIZE_512:
5377 case I40E_DMA_CNTX_SIZE_1K:
5378 case I40E_DMA_CNTX_SIZE_2K:
5379 case I40E_DMA_CNTX_SIZE_4K:
5380 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5381 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5384 return I40E_ERR_PARAM;
5387 /* Validate PE settings passed */
5388 switch (settings->pe_filt_num) {
5389 case I40E_HASH_FILTER_SIZE_1K:
5390 case I40E_HASH_FILTER_SIZE_2K:
5391 case I40E_HASH_FILTER_SIZE_4K:
5392 case I40E_HASH_FILTER_SIZE_8K:
5393 case I40E_HASH_FILTER_SIZE_16K:
5394 case I40E_HASH_FILTER_SIZE_32K:
5395 case I40E_HASH_FILTER_SIZE_64K:
5396 case I40E_HASH_FILTER_SIZE_128K:
5397 case I40E_HASH_FILTER_SIZE_256K:
5398 case I40E_HASH_FILTER_SIZE_512K:
5399 case I40E_HASH_FILTER_SIZE_1M:
5400 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5401 pe_filt_size <<= (u32)settings->pe_filt_num;
5404 return I40E_ERR_PARAM;
5407 switch (settings->pe_cntx_num) {
5408 case I40E_DMA_CNTX_SIZE_512:
5409 case I40E_DMA_CNTX_SIZE_1K:
5410 case I40E_DMA_CNTX_SIZE_2K:
5411 case I40E_DMA_CNTX_SIZE_4K:
5412 case I40E_DMA_CNTX_SIZE_8K:
5413 case I40E_DMA_CNTX_SIZE_16K:
5414 case I40E_DMA_CNTX_SIZE_32K:
5415 case I40E_DMA_CNTX_SIZE_64K:
5416 case I40E_DMA_CNTX_SIZE_128K:
5417 case I40E_DMA_CNTX_SIZE_256K:
5418 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5419 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5422 return I40E_ERR_PARAM;
5425 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5426 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5427 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5428 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5429 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
5430 return I40E_ERR_INVALID_SIZE;
5432 return I40E_SUCCESS;
5436 * i40e_set_filter_control
5437 * @hw: pointer to the hardware structure
5438 * @settings: Filter control settings
5440 * Set the Queue Filters for PE/FCoE and enable filters required
5441 * for a single PF. It is expected that these settings are programmed
5442 * at the driver initialization time.
5444 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5445 struct i40e_filter_control_settings *settings)
5447 enum i40e_status_code ret = I40E_SUCCESS;
5448 u32 hash_lut_size = 0;
5452 return I40E_ERR_PARAM;
5454 /* Validate the input settings */
5455 ret = i40e_validate_filter_settings(hw, settings);
5459 /* Read the PF Queue Filter control register */
5460 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5462 /* Program required PE hash buckets for the PF */
5463 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5464 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5465 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5466 /* Program required PE contexts for the PF */
5467 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5468 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5469 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5471 /* Program required FCoE hash buckets for the PF */
5472 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5473 val |= ((u32)settings->fcoe_filt_num <<
5474 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5475 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5476 /* Program required FCoE DDP contexts for the PF */
5477 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5478 val |= ((u32)settings->fcoe_cntx_num <<
5479 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5480 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5482 /* Program Hash LUT size for the PF */
5483 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5484 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5486 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5487 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5489 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5490 if (settings->enable_fdir)
5491 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5492 if (settings->enable_ethtype)
5493 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5494 if (settings->enable_macvlan)
5495 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5497 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5499 return I40E_SUCCESS;
5503 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5504 * @hw: pointer to the hw struct
5505 * @mac_addr: MAC address to use in the filter
5506 * @ethtype: Ethertype to use in the filter
5507 * @flags: Flags that needs to be applied to the filter
5508 * @vsi_seid: seid of the control VSI
5509 * @queue: VSI queue number to send the packet to
5510 * @is_add: Add control packet filter if True else remove
5511 * @stats: Structure to hold information on control filter counts
5512 * @cmd_details: pointer to command details structure or NULL
5514 * This command will Add or Remove control packet filter for a control VSI.
5515 * In return it will update the total number of perfect filter count in
5518 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5519 u8 *mac_addr, u16 ethtype, u16 flags,
5520 u16 vsi_seid, u16 queue, bool is_add,
5521 struct i40e_control_filter_stats *stats,
5522 struct i40e_asq_cmd_details *cmd_details)
5524 struct i40e_aq_desc desc;
5525 struct i40e_aqc_add_remove_control_packet_filter *cmd =
5526 (struct i40e_aqc_add_remove_control_packet_filter *)
5528 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5529 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5531 enum i40e_status_code status;
5534 return I40E_ERR_PARAM;
5537 i40e_fill_default_direct_cmd_desc(&desc,
5538 i40e_aqc_opc_add_control_packet_filter);
5539 cmd->queue = CPU_TO_LE16(queue);
5541 i40e_fill_default_direct_cmd_desc(&desc,
5542 i40e_aqc_opc_remove_control_packet_filter);
5546 i40e_memcpy(cmd->mac, mac_addr, ETH_ALEN,
5547 I40E_NONDMA_TO_NONDMA);
5549 cmd->etype = CPU_TO_LE16(ethtype);
5550 cmd->flags = CPU_TO_LE16(flags);
5551 cmd->seid = CPU_TO_LE16(vsi_seid);
5553 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5555 if (!status && stats) {
5556 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5557 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5558 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5559 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5566 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5567 * @hw: pointer to the hw struct
5568 * @seid: VSI seid to add ethertype filter from
5570 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5571 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5574 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5575 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5576 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5577 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5578 enum i40e_status_code status;
5580 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5581 seid, 0, true, NULL,
5584 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5588 * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5589 * @filters: list of cloud filters
5590 * @filter_count: length of list
5592 * There's an issue in the device where the Geneve VNI layout needs
5593 * to be shifted 1 byte over from the VxLAN VNI
5595 STATIC void i40e_fix_up_geneve_vni(
5596 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5599 struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters;
5602 for (i = 0; i < filter_count; i++) {
5606 tnl_type = (LE16_TO_CPU(f[i].flags) &
5607 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5608 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5609 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5610 ti = LE32_TO_CPU(f[i].tenant_id);
5611 f[i].tenant_id = CPU_TO_LE32(ti << 8);
5617 * i40e_aq_add_cloud_filters
5618 * @hw: pointer to the hardware structure
5619 * @seid: VSI seid to add cloud filters from
5620 * @filters: Buffer which contains the filters to be added
5621 * @filter_count: number of filters contained in the buffer
5623 * Set the cloud filters for a given VSI. The contents of the
5624 * i40e_aqc_add_remove_cloud_filters_element_data are filled
5625 * in by the caller of the function.
5628 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5630 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5633 struct i40e_aq_desc desc;
5634 struct i40e_aqc_add_remove_cloud_filters *cmd =
5635 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5636 enum i40e_status_code status;
5639 i40e_fill_default_direct_cmd_desc(&desc,
5640 i40e_aqc_opc_add_cloud_filters);
5642 buff_len = filter_count * sizeof(*filters);
5643 desc.datalen = CPU_TO_LE16(buff_len);
5644 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5645 cmd->num_filters = filter_count;
5646 cmd->seid = CPU_TO_LE16(seid);
5648 i40e_fix_up_geneve_vni(filters, filter_count);
5650 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5656 * i40e_aq_add_cloud_filters_big_buffer
5657 * @hw: pointer to the hardware structure
5658 * @seid: VSI seid to add cloud filters from
5659 * @filters: Buffer which contains the filters in big buffer to be added
5660 * @filter_count: number of filters contained in the buffer
5662 * Set the cloud filters for a given VSI. The contents of the
5663 * i40e_aqc_add_rm_cloud_filt_elem_ext are filled in by the caller of
5667 enum i40e_status_code i40e_aq_add_cloud_filters_big_buffer(struct i40e_hw *hw,
5669 struct i40e_aqc_add_rm_cloud_filt_elem_ext *filters,
5672 struct i40e_aq_desc desc;
5673 struct i40e_aqc_add_remove_cloud_filters *cmd =
5674 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5675 enum i40e_status_code status;
5679 i40e_fill_default_direct_cmd_desc(&desc,
5680 i40e_aqc_opc_add_cloud_filters);
5682 buff_len = filter_count * sizeof(*filters);
5683 desc.datalen = CPU_TO_LE16(buff_len);
5684 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5685 cmd->num_filters = filter_count;
5686 cmd->seid = CPU_TO_LE16(seid);
5687 cmd->big_buffer_flag = I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER;
5689 /* adjust Geneve VNI for HW issue */
5690 for (i = 0; i < filter_count; i++) {
5694 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5695 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5696 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5697 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5698 ti = LE32_TO_CPU(filters[i].element.tenant_id);
5699 filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5703 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5709 * i40e_aq_remove_cloud_filters
5710 * @hw: pointer to the hardware structure
5711 * @seid: VSI seid to remove cloud filters from
5712 * @filters: Buffer which contains the filters to be removed
5713 * @filter_count: number of filters contained in the buffer
5715 * Remove the cloud filters for a given VSI. The contents of the
5716 * i40e_aqc_add_remove_cloud_filters_element_data are filled
5717 * in by the caller of the function.
5720 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5722 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5725 struct i40e_aq_desc desc;
5726 struct i40e_aqc_add_remove_cloud_filters *cmd =
5727 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5728 enum i40e_status_code status;
5731 i40e_fill_default_direct_cmd_desc(&desc,
5732 i40e_aqc_opc_remove_cloud_filters);
5734 buff_len = filter_count * sizeof(*filters);
5735 desc.datalen = CPU_TO_LE16(buff_len);
5736 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5737 cmd->num_filters = filter_count;
5738 cmd->seid = CPU_TO_LE16(seid);
5740 i40e_fix_up_geneve_vni(filters, filter_count);
5742 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5748 * i40e_aq_remove_cloud_filters_big_buffer
5749 * @hw: pointer to the hardware structure
5750 * @seid: VSI seid to remove cloud filters from
5751 * @filters: Buffer which contains the filters in big buffer to be removed
5752 * @filter_count: number of filters contained in the buffer
5754 * Remove the cloud filters for a given VSI. The contents of the
5755 * i40e_aqc_add_rm_cloud_filt_elem_ext are filled in by the caller of
5759 enum i40e_status_code i40e_aq_remove_cloud_filters_big_buffer(
5762 struct i40e_aqc_add_rm_cloud_filt_elem_ext *filters,
5765 struct i40e_aq_desc desc;
5766 struct i40e_aqc_add_remove_cloud_filters *cmd =
5767 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5768 enum i40e_status_code status;
5772 i40e_fill_default_direct_cmd_desc(&desc,
5773 i40e_aqc_opc_remove_cloud_filters);
5775 buff_len = filter_count * sizeof(*filters);
5776 desc.datalen = CPU_TO_LE16(buff_len);
5777 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5778 cmd->num_filters = filter_count;
5779 cmd->seid = CPU_TO_LE16(seid);
5780 cmd->big_buffer_flag = I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER;
5782 /* adjust Geneve VNI for HW issue */
5783 for (i = 0; i < filter_count; i++) {
5787 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5788 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5789 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5790 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5791 ti = LE32_TO_CPU(filters[i].element.tenant_id);
5792 filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5796 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5802 * i40e_aq_replace_cloud_filters - Replace cloud filter command
5803 * @hw: pointer to the hw struct
5804 * @filters: pointer to the i40e_aqc_replace_cloud_filter_cmd struct
5805 * @cmd_buf: pointer to the i40e_aqc_replace_cloud_filter_cmd_buf struct
5809 i40e_status_code i40e_aq_replace_cloud_filters(struct i40e_hw *hw,
5810 struct i40e_aqc_replace_cloud_filters_cmd *filters,
5811 struct i40e_aqc_replace_cloud_filters_cmd_buf *cmd_buf)
5813 struct i40e_aq_desc desc;
5814 struct i40e_aqc_replace_cloud_filters_cmd *cmd =
5815 (struct i40e_aqc_replace_cloud_filters_cmd *)&desc.params.raw;
5816 enum i40e_status_code status = I40E_SUCCESS;
5819 i40e_fill_default_direct_cmd_desc(&desc,
5820 i40e_aqc_opc_replace_cloud_filters);
5822 desc.datalen = CPU_TO_LE16(32);
5823 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5824 cmd->old_filter_type = filters->old_filter_type;
5825 cmd->new_filter_type = filters->new_filter_type;
5826 cmd->valid_flags = filters->valid_flags;
5827 cmd->tr_bit = filters->tr_bit;
5829 status = i40e_asq_send_command(hw, &desc, cmd_buf,
5830 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf), NULL);
5832 /* for get cloud filters command */
5833 for (i = 0; i < 32; i += 4) {
5834 cmd_buf->filters[i / 4].filter_type = cmd_buf->data[i];
5835 cmd_buf->filters[i / 4].input[0] = cmd_buf->data[i + 1];
5836 cmd_buf->filters[i / 4].input[1] = cmd_buf->data[i + 2];
5837 cmd_buf->filters[i / 4].input[2] = cmd_buf->data[i + 3];
5845 * i40e_aq_alternate_write
5846 * @hw: pointer to the hardware structure
5847 * @reg_addr0: address of first dword to be read
5848 * @reg_val0: value to be written under 'reg_addr0'
5849 * @reg_addr1: address of second dword to be read
5850 * @reg_val1: value to be written under 'reg_addr1'
5852 * Write one or two dwords to alternate structure. Fields are indicated
5853 * by 'reg_addr0' and 'reg_addr1' register numbers.
5856 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5857 u32 reg_addr0, u32 reg_val0,
5858 u32 reg_addr1, u32 reg_val1)
5860 struct i40e_aq_desc desc;
5861 struct i40e_aqc_alternate_write *cmd_resp =
5862 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5863 enum i40e_status_code status;
5865 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5866 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5867 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5868 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5869 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5871 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5877 * i40e_aq_alternate_write_indirect
5878 * @hw: pointer to the hardware structure
5879 * @addr: address of a first register to be modified
5880 * @dw_count: number of alternate structure fields to write
5881 * @buffer: pointer to the command buffer
5883 * Write 'dw_count' dwords from 'buffer' to alternate structure
5884 * starting at 'addr'.
5887 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5888 u32 addr, u32 dw_count, void *buffer)
5890 struct i40e_aq_desc desc;
5891 struct i40e_aqc_alternate_ind_write *cmd_resp =
5892 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5893 enum i40e_status_code status;
5896 return I40E_ERR_PARAM;
5898 /* Indirect command */
5899 i40e_fill_default_direct_cmd_desc(&desc,
5900 i40e_aqc_opc_alternate_write_indirect);
5902 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5903 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5904 if (dw_count > (I40E_AQ_LARGE_BUF/4))
5905 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5907 cmd_resp->address = CPU_TO_LE32(addr);
5908 cmd_resp->length = CPU_TO_LE32(dw_count);
5910 status = i40e_asq_send_command(hw, &desc, buffer,
5911 I40E_LO_DWORD(4*dw_count), NULL);
5917 * i40e_aq_alternate_read
5918 * @hw: pointer to the hardware structure
5919 * @reg_addr0: address of first dword to be read
5920 * @reg_val0: pointer for data read from 'reg_addr0'
5921 * @reg_addr1: address of second dword to be read
5922 * @reg_val1: pointer for data read from 'reg_addr1'
5924 * Read one or two dwords from alternate structure. Fields are indicated
5925 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5926 * is not passed then only register at 'reg_addr0' is read.
5929 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5930 u32 reg_addr0, u32 *reg_val0,
5931 u32 reg_addr1, u32 *reg_val1)
5933 struct i40e_aq_desc desc;
5934 struct i40e_aqc_alternate_write *cmd_resp =
5935 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5936 enum i40e_status_code status;
5938 if (reg_val0 == NULL)
5939 return I40E_ERR_PARAM;
5941 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5942 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5943 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5945 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5947 if (status == I40E_SUCCESS) {
5948 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5950 if (reg_val1 != NULL)
5951 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5958 * i40e_aq_alternate_read_indirect
5959 * @hw: pointer to the hardware structure
5960 * @addr: address of the alternate structure field
5961 * @dw_count: number of alternate structure fields to read
5962 * @buffer: pointer to the command buffer
5964 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5965 * place them in 'buffer'. The buffer should be allocated by caller.
5968 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5969 u32 addr, u32 dw_count, void *buffer)
5971 struct i40e_aq_desc desc;
5972 struct i40e_aqc_alternate_ind_write *cmd_resp =
5973 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5974 enum i40e_status_code status;
5977 return I40E_ERR_PARAM;
5979 /* Indirect command */
5980 i40e_fill_default_direct_cmd_desc(&desc,
5981 i40e_aqc_opc_alternate_read_indirect);
5983 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5984 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5985 if (dw_count > (I40E_AQ_LARGE_BUF/4))
5986 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5988 cmd_resp->address = CPU_TO_LE32(addr);
5989 cmd_resp->length = CPU_TO_LE32(dw_count);
5991 status = i40e_asq_send_command(hw, &desc, buffer,
5992 I40E_LO_DWORD(4*dw_count), NULL);
5998 * i40e_aq_alternate_clear
5999 * @hw: pointer to the HW structure.
6001 * Clear the alternate structures of the port from which the function
6005 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
6007 struct i40e_aq_desc desc;
6008 enum i40e_status_code status;
6010 i40e_fill_default_direct_cmd_desc(&desc,
6011 i40e_aqc_opc_alternate_clear_port);
6013 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6019 * i40e_aq_alternate_write_done
6020 * @hw: pointer to the HW structure.
6021 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
6022 * @reset_needed: indicates the SW should trigger GLOBAL reset
6024 * Indicates to the FW that alternate structures have been changed.
6027 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
6028 u8 bios_mode, bool *reset_needed)
6030 struct i40e_aq_desc desc;
6031 struct i40e_aqc_alternate_write_done *cmd =
6032 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6033 enum i40e_status_code status;
6035 if (reset_needed == NULL)
6036 return I40E_ERR_PARAM;
6038 i40e_fill_default_direct_cmd_desc(&desc,
6039 i40e_aqc_opc_alternate_write_done);
6041 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
6043 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6044 if (!status && reset_needed)
6045 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
6046 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
6052 * i40e_aq_set_oem_mode
6053 * @hw: pointer to the HW structure.
6054 * @oem_mode: the OEM mode to be used
6056 * Sets the device to a specific operating mode. Currently the only supported
6057 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
6060 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
6063 struct i40e_aq_desc desc;
6064 struct i40e_aqc_alternate_write_done *cmd =
6065 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6066 enum i40e_status_code status;
6068 i40e_fill_default_direct_cmd_desc(&desc,
6069 i40e_aqc_opc_alternate_set_mode);
6071 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
6073 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6079 * i40e_aq_resume_port_tx
6080 * @hw: pointer to the hardware structure
6081 * @cmd_details: pointer to command details structure or NULL
6083 * Resume port's Tx traffic
6085 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
6086 struct i40e_asq_cmd_details *cmd_details)
6088 struct i40e_aq_desc desc;
6089 enum i40e_status_code status;
6091 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
6093 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6099 * i40e_set_pci_config_data - store PCI bus info
6100 * @hw: pointer to hardware structure
6101 * @link_status: the link status word from PCI config space
6103 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
6105 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
6107 hw->bus.type = i40e_bus_type_pci_express;
6109 switch (link_status & I40E_PCI_LINK_WIDTH) {
6110 case I40E_PCI_LINK_WIDTH_1:
6111 hw->bus.width = i40e_bus_width_pcie_x1;
6113 case I40E_PCI_LINK_WIDTH_2:
6114 hw->bus.width = i40e_bus_width_pcie_x2;
6116 case I40E_PCI_LINK_WIDTH_4:
6117 hw->bus.width = i40e_bus_width_pcie_x4;
6119 case I40E_PCI_LINK_WIDTH_8:
6120 hw->bus.width = i40e_bus_width_pcie_x8;
6123 hw->bus.width = i40e_bus_width_unknown;
6127 switch (link_status & I40E_PCI_LINK_SPEED) {
6128 case I40E_PCI_LINK_SPEED_2500:
6129 hw->bus.speed = i40e_bus_speed_2500;
6131 case I40E_PCI_LINK_SPEED_5000:
6132 hw->bus.speed = i40e_bus_speed_5000;
6134 case I40E_PCI_LINK_SPEED_8000:
6135 hw->bus.speed = i40e_bus_speed_8000;
6138 hw->bus.speed = i40e_bus_speed_unknown;
6144 * i40e_aq_debug_dump
6145 * @hw: pointer to the hardware structure
6146 * @cluster_id: specific cluster to dump
6147 * @table_id: table id within cluster
6148 * @start_index: index of line in the block to read
6149 * @buff_size: dump buffer size
6150 * @buff: dump buffer
6151 * @ret_buff_size: actual buffer size returned
6152 * @ret_next_table: next block to read
6153 * @ret_next_index: next index to read
6155 * Dump internal FW/HW data for debug purposes.
6158 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
6159 u8 table_id, u32 start_index, u16 buff_size,
6160 void *buff, u16 *ret_buff_size,
6161 u8 *ret_next_table, u32 *ret_next_index,
6162 struct i40e_asq_cmd_details *cmd_details)
6164 struct i40e_aq_desc desc;
6165 struct i40e_aqc_debug_dump_internals *cmd =
6166 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6167 struct i40e_aqc_debug_dump_internals *resp =
6168 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6169 enum i40e_status_code status;
6171 if (buff_size == 0 || !buff)
6172 return I40E_ERR_PARAM;
6174 i40e_fill_default_direct_cmd_desc(&desc,
6175 i40e_aqc_opc_debug_dump_internals);
6176 /* Indirect Command */
6177 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6178 if (buff_size > I40E_AQ_LARGE_BUF)
6179 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6181 cmd->cluster_id = cluster_id;
6182 cmd->table_id = table_id;
6183 cmd->idx = CPU_TO_LE32(start_index);
6185 desc.datalen = CPU_TO_LE16(buff_size);
6187 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
6189 if (ret_buff_size != NULL)
6190 *ret_buff_size = LE16_TO_CPU(desc.datalen);
6191 if (ret_next_table != NULL)
6192 *ret_next_table = resp->table_id;
6193 if (ret_next_index != NULL)
6194 *ret_next_index = LE32_TO_CPU(resp->idx);
6201 * i40e_read_bw_from_alt_ram
6202 * @hw: pointer to the hardware structure
6203 * @max_bw: pointer for max_bw read
6204 * @min_bw: pointer for min_bw read
6205 * @min_valid: pointer for bool that is true if min_bw is a valid value
6206 * @max_valid: pointer for bool that is true if max_bw is a valid value
6208 * Read bw from the alternate ram for the given pf
6210 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
6211 u32 *max_bw, u32 *min_bw,
6212 bool *min_valid, bool *max_valid)
6214 enum i40e_status_code status;
6215 u32 max_bw_addr, min_bw_addr;
6217 /* Calculate the address of the min/max bw registers */
6218 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6219 I40E_ALT_STRUCT_MAX_BW_OFFSET +
6220 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6221 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6222 I40E_ALT_STRUCT_MIN_BW_OFFSET +
6223 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6225 /* Read the bandwidths from alt ram */
6226 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
6227 min_bw_addr, min_bw);
6229 if (*min_bw & I40E_ALT_BW_VALID_MASK)
6234 if (*max_bw & I40E_ALT_BW_VALID_MASK)
6243 * i40e_aq_configure_partition_bw
6244 * @hw: pointer to the hardware structure
6245 * @bw_data: Buffer holding valid pfs and bw limits
6246 * @cmd_details: pointer to command details
6248 * Configure partitions guaranteed/max bw
6250 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6251 struct i40e_aqc_configure_partition_bw_data *bw_data,
6252 struct i40e_asq_cmd_details *cmd_details)
6254 enum i40e_status_code status;
6255 struct i40e_aq_desc desc;
6256 u16 bwd_size = sizeof(*bw_data);
6258 i40e_fill_default_direct_cmd_desc(&desc,
6259 i40e_aqc_opc_configure_partition_bw);
6261 /* Indirect command */
6262 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6263 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6265 desc.datalen = CPU_TO_LE16(bwd_size);
6267 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6273 * i40e_read_phy_register_clause22
6274 * @hw: pointer to the HW structure
6275 * @reg: register address in the page
6276 * @phy_adr: PHY address on MDIO interface
6277 * @value: PHY register value
6279 * Reads specified PHY register value
6281 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
6282 u16 reg, u8 phy_addr, u16 *value)
6284 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6285 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6289 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6290 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6291 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
6292 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6293 (I40E_GLGEN_MSCA_MDICMD_MASK);
6294 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6296 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6297 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6298 status = I40E_SUCCESS;
6301 i40e_usec_delay(10);
6306 i40e_debug(hw, I40E_DEBUG_PHY,
6307 "PHY: Can't write command to external PHY.\n");
6309 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6310 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6311 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6318 * i40e_write_phy_register_clause22
6319 * @hw: pointer to the HW structure
6320 * @reg: register address in the page
6321 * @phy_adr: PHY address on MDIO interface
6322 * @value: PHY register value
6324 * Writes specified PHY register value
6326 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6327 u16 reg, u8 phy_addr, u16 value)
6329 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6330 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6334 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6335 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6337 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6338 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6339 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6340 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6341 (I40E_GLGEN_MSCA_MDICMD_MASK);
6343 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6345 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6346 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6347 status = I40E_SUCCESS;
6350 i40e_usec_delay(10);
6358 * i40e_read_phy_register_clause45
6359 * @hw: pointer to the HW structure
6360 * @page: registers page number
6361 * @reg: register address in the page
6362 * @phy_adr: PHY address on MDIO interface
6363 * @value: PHY register value
6365 * Reads specified PHY register value
6367 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6368 u8 page, u16 reg, u8 phy_addr, u16 *value)
6370 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6373 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6375 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6376 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6377 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6378 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6379 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6380 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6381 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6382 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6384 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6385 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6386 status = I40E_SUCCESS;
6389 i40e_usec_delay(10);
6394 i40e_debug(hw, I40E_DEBUG_PHY,
6395 "PHY: Can't write command to external PHY.\n");
6399 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6400 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6401 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6402 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6403 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6404 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6405 status = I40E_ERR_TIMEOUT;
6407 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6409 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6410 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6411 status = I40E_SUCCESS;
6414 i40e_usec_delay(10);
6419 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6420 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6421 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6423 i40e_debug(hw, I40E_DEBUG_PHY,
6424 "PHY: Can't read register value from external PHY.\n");
6432 * i40e_write_phy_register_clause45
6433 * @hw: pointer to the HW structure
6434 * @page: registers page number
6435 * @reg: register address in the page
6436 * @phy_adr: PHY address on MDIO interface
6437 * @value: PHY register value
6439 * Writes value to specified PHY register
6441 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6442 u8 page, u16 reg, u8 phy_addr, u16 value)
6444 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6447 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6449 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6450 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6451 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6452 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6453 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6454 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6455 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6456 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6458 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6459 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6460 status = I40E_SUCCESS;
6463 i40e_usec_delay(10);
6467 i40e_debug(hw, I40E_DEBUG_PHY,
6468 "PHY: Can't write command to external PHY.\n");
6472 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6473 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6475 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6476 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6477 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6478 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6479 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6480 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6481 status = I40E_ERR_TIMEOUT;
6483 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6485 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6486 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6487 status = I40E_SUCCESS;
6490 i40e_usec_delay(10);
6499 * i40e_write_phy_register
6500 * @hw: pointer to the HW structure
6501 * @page: registers page number
6502 * @reg: register address in the page
6503 * @phy_adr: PHY address on MDIO interface
6504 * @value: PHY register value
6506 * Writes value to specified PHY register
6508 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6509 u8 page, u16 reg, u8 phy_addr, u16 value)
6511 enum i40e_status_code status;
6513 switch (hw->device_id) {
6514 case I40E_DEV_ID_1G_BASE_T_X722:
6515 status = i40e_write_phy_register_clause22(hw,
6516 reg, phy_addr, value);
6518 case I40E_DEV_ID_10G_BASE_T:
6519 case I40E_DEV_ID_10G_BASE_T4:
6520 case I40E_DEV_ID_10G_BASE_T_X722:
6521 case I40E_DEV_ID_25G_B:
6522 case I40E_DEV_ID_25G_SFP28:
6523 status = i40e_write_phy_register_clause45(hw,
6524 page, reg, phy_addr, value);
6527 status = I40E_ERR_UNKNOWN_PHY;
6535 * i40e_read_phy_register
6536 * @hw: pointer to the HW structure
6537 * @page: registers page number
6538 * @reg: register address in the page
6539 * @phy_adr: PHY address on MDIO interface
6540 * @value: PHY register value
6542 * Reads specified PHY register value
6544 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6545 u8 page, u16 reg, u8 phy_addr, u16 *value)
6547 enum i40e_status_code status;
6549 switch (hw->device_id) {
6550 case I40E_DEV_ID_1G_BASE_T_X722:
6551 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6554 case I40E_DEV_ID_10G_BASE_T:
6555 case I40E_DEV_ID_10G_BASE_T4:
6556 case I40E_DEV_ID_10G_BASE_T_X722:
6557 case I40E_DEV_ID_25G_B:
6558 case I40E_DEV_ID_25G_SFP28:
6559 status = i40e_read_phy_register_clause45(hw, page, reg,
6563 status = I40E_ERR_UNKNOWN_PHY;
6571 * i40e_get_phy_address
6572 * @hw: pointer to the HW structure
6573 * @dev_num: PHY port num that address we want
6574 * @phy_addr: Returned PHY address
6576 * Gets PHY address for current port
6578 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6580 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6581 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6583 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6587 * i40e_blink_phy_led
6588 * @hw: pointer to the HW structure
6589 * @time: time how long led will blinks in secs
6590 * @interval: gap between LED on and off in msecs
6592 * Blinks PHY link LED
6594 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6595 u32 time, u32 interval)
6597 enum i40e_status_code status = I40E_SUCCESS;
6602 u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6606 i = rd32(hw, I40E_PFGEN_PORTNUM);
6607 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6608 phy_addr = i40e_get_phy_address(hw, port_num);
6610 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6612 status = i40e_read_phy_register_clause45(hw,
6613 I40E_PHY_COM_REG_PAGE,
6617 goto phy_blinking_end;
6619 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6621 status = i40e_write_phy_register_clause45(hw,
6622 I40E_PHY_COM_REG_PAGE,
6626 goto phy_blinking_end;
6631 if (time > 0 && interval > 0) {
6632 for (i = 0; i < time * 1000; i += interval) {
6633 status = i40e_read_phy_register_clause45(hw,
6634 I40E_PHY_COM_REG_PAGE,
6635 led_addr, phy_addr, &led_reg);
6637 goto restore_config;
6638 if (led_reg & I40E_PHY_LED_MANUAL_ON)
6641 led_reg = I40E_PHY_LED_MANUAL_ON;
6642 status = i40e_write_phy_register_clause45(hw,
6643 I40E_PHY_COM_REG_PAGE,
6644 led_addr, phy_addr, led_reg);
6646 goto restore_config;
6647 i40e_msec_delay(interval);
6652 status = i40e_write_phy_register_clause45(hw,
6653 I40E_PHY_COM_REG_PAGE,
6654 led_addr, phy_addr, led_ctl);
6661 * i40e_led_get_phy - return current on/off mode
6662 * @hw: pointer to the hw struct
6663 * @led_addr: address of led register to use
6664 * @val: original value of register to use
6667 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6670 enum i40e_status_code status = I40E_SUCCESS;
6678 temp_addr = I40E_PHY_LED_PROV_REG_1;
6679 i = rd32(hw, I40E_PFGEN_PORTNUM);
6680 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6681 phy_addr = i40e_get_phy_address(hw, port_num);
6683 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6685 status = i40e_read_phy_register_clause45(hw,
6686 I40E_PHY_COM_REG_PAGE,
6687 temp_addr, phy_addr,
6692 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6693 *led_addr = temp_addr;
6702 * @hw: pointer to the HW structure
6703 * @on: true or false
6704 * @mode: original val plus bit for set or ignore
6705 * Set led's on or off when controlled by the PHY
6708 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6709 u16 led_addr, u32 mode)
6711 enum i40e_status_code status = I40E_SUCCESS;
6718 i = rd32(hw, I40E_PFGEN_PORTNUM);
6719 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6720 phy_addr = i40e_get_phy_address(hw, port_num);
6721 status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6722 led_addr, phy_addr, &led_reg);
6726 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6728 status = i40e_write_phy_register_clause45(hw,
6729 I40E_PHY_COM_REG_PAGE,
6735 status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6736 led_addr, phy_addr, &led_reg);
6738 goto restore_config;
6740 led_reg = I40E_PHY_LED_MANUAL_ON;
6743 status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6744 led_addr, phy_addr, led_reg);
6746 goto restore_config;
6747 if (mode & I40E_PHY_LED_MODE_ORIG) {
6748 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6749 status = i40e_write_phy_register_clause45(hw,
6750 I40E_PHY_COM_REG_PAGE,
6751 led_addr, phy_addr, led_ctl);
6755 status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6756 led_addr, phy_addr, led_ctl);
6759 #endif /* PF_DRIVER */
6762 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6763 * @hw: pointer to the hw struct
6764 * @reg_addr: register address
6765 * @reg_val: ptr to register value
6766 * @cmd_details: pointer to command details structure or NULL
6768 * Use the firmware to read the Rx control register,
6769 * especially useful if the Rx unit is under heavy pressure
6771 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6772 u32 reg_addr, u32 *reg_val,
6773 struct i40e_asq_cmd_details *cmd_details)
6775 struct i40e_aq_desc desc;
6776 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
6777 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6778 enum i40e_status_code status;
6780 if (reg_val == NULL)
6781 return I40E_ERR_PARAM;
6783 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
6785 cmd_resp->address = CPU_TO_LE32(reg_addr);
6787 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6789 if (status == I40E_SUCCESS)
6790 *reg_val = LE32_TO_CPU(cmd_resp->value);
6796 * i40e_read_rx_ctl - read from an Rx control register
6797 * @hw: pointer to the hw struct
6798 * @reg_addr: register address
6800 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
6802 enum i40e_status_code status = I40E_SUCCESS;
6807 use_register = (((hw->aq.api_maj_ver == 1) &&
6808 (hw->aq.api_min_ver < 5)) ||
6809 (hw->mac.type == I40E_MAC_X722));
6810 if (!use_register) {
6812 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
6813 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6820 /* if the AQ access failed, try the old-fashioned way */
6821 if (status || use_register)
6822 val = rd32(hw, reg_addr);
6828 * i40e_aq_rx_ctl_write_register
6829 * @hw: pointer to the hw struct
6830 * @reg_addr: register address
6831 * @reg_val: register value
6832 * @cmd_details: pointer to command details structure or NULL
6834 * Use the firmware to write to an Rx control register,
6835 * especially useful if the Rx unit is under heavy pressure
6837 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
6838 u32 reg_addr, u32 reg_val,
6839 struct i40e_asq_cmd_details *cmd_details)
6841 struct i40e_aq_desc desc;
6842 struct i40e_aqc_rx_ctl_reg_read_write *cmd =
6843 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6844 enum i40e_status_code status;
6846 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
6848 cmd->address = CPU_TO_LE32(reg_addr);
6849 cmd->value = CPU_TO_LE32(reg_val);
6851 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6857 * i40e_write_rx_ctl - write to an Rx control register
6858 * @hw: pointer to the hw struct
6859 * @reg_addr: register address
6860 * @reg_val: register value
6862 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
6864 enum i40e_status_code status = I40E_SUCCESS;
6868 use_register = (((hw->aq.api_maj_ver == 1) &&
6869 (hw->aq.api_min_ver < 5)) ||
6870 (hw->mac.type == I40E_MAC_X722));
6871 if (!use_register) {
6873 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
6875 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6882 /* if the AQ access failed, try the old-fashioned way */
6883 if (status || use_register)
6884 wr32(hw, reg_addr, reg_val);
6888 * i40e_aq_set_phy_register
6889 * @hw: pointer to the hw struct
6890 * @phy_select: select which phy should be accessed
6891 * @dev_addr: PHY device address
6892 * @reg_addr: PHY register address
6893 * @reg_val: new register value
6894 * @cmd_details: pointer to command details structure or NULL
6896 * Write the external PHY register.
6898 enum i40e_status_code i40e_aq_set_phy_register(struct i40e_hw *hw,
6899 u8 phy_select, u8 dev_addr,
6900 u32 reg_addr, u32 reg_val,
6901 struct i40e_asq_cmd_details *cmd_details)
6903 struct i40e_aq_desc desc;
6904 struct i40e_aqc_phy_register_access *cmd =
6905 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
6906 enum i40e_status_code status;
6908 i40e_fill_default_direct_cmd_desc(&desc,
6909 i40e_aqc_opc_set_phy_register);
6911 cmd->phy_interface = phy_select;
6912 cmd->dev_addres = dev_addr;
6913 cmd->reg_address = reg_addr;
6914 cmd->reg_value = reg_val;
6916 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6922 * i40e_aq_get_phy_register
6923 * @hw: pointer to the hw struct
6924 * @phy_select: select which phy should be accessed
6925 * @dev_addr: PHY device address
6926 * @reg_addr: PHY register address
6927 * @reg_val: read register value
6928 * @cmd_details: pointer to command details structure or NULL
6930 * Read the external PHY register.
6932 enum i40e_status_code i40e_aq_get_phy_register(struct i40e_hw *hw,
6933 u8 phy_select, u8 dev_addr,
6934 u32 reg_addr, u32 *reg_val,
6935 struct i40e_asq_cmd_details *cmd_details)
6937 struct i40e_aq_desc desc;
6938 struct i40e_aqc_phy_register_access *cmd =
6939 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
6940 enum i40e_status_code status;
6942 i40e_fill_default_direct_cmd_desc(&desc,
6943 i40e_aqc_opc_get_phy_register);
6945 cmd->phy_interface = phy_select;
6946 cmd->dev_addres = dev_addr;
6947 cmd->reg_address = reg_addr;
6949 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6951 *reg_val = cmd->reg_value;
6959 * i40e_aq_send_msg_to_pf
6960 * @hw: pointer to the hardware structure
6961 * @v_opcode: opcodes for VF-PF communication
6962 * @v_retval: return error code
6963 * @msg: pointer to the msg buffer
6964 * @msglen: msg length
6965 * @cmd_details: pointer to command details
6967 * Send message to PF driver using admin queue. By default, this message
6968 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
6969 * completion before returning.
6971 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
6972 enum virtchnl_ops v_opcode,
6973 enum i40e_status_code v_retval,
6974 u8 *msg, u16 msglen,
6975 struct i40e_asq_cmd_details *cmd_details)
6977 struct i40e_aq_desc desc;
6978 struct i40e_asq_cmd_details details;
6979 enum i40e_status_code status;
6981 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
6982 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
6983 desc.cookie_high = CPU_TO_LE32(v_opcode);
6984 desc.cookie_low = CPU_TO_LE32(v_retval);
6986 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
6987 | I40E_AQ_FLAG_RD));
6988 if (msglen > I40E_AQ_LARGE_BUF)
6989 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6990 desc.datalen = CPU_TO_LE16(msglen);
6993 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
6994 details.async = true;
6995 cmd_details = &details;
6997 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
6998 msglen, cmd_details);
7003 * i40e_vf_parse_hw_config
7004 * @hw: pointer to the hardware structure
7005 * @msg: pointer to the virtual channel VF resource structure
7007 * Given a VF resource message from the PF, populate the hw struct
7008 * with appropriate information.
7010 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
7011 struct virtchnl_vf_resource *msg)
7013 struct virtchnl_vsi_resource *vsi_res;
7016 vsi_res = &msg->vsi_res[0];
7018 hw->dev_caps.num_vsis = msg->num_vsis;
7019 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
7020 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
7021 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
7022 hw->dev_caps.dcb = msg->vf_offload_flags &
7023 VIRTCHNL_VF_OFFLOAD_L2;
7024 hw->dev_caps.iwarp = (msg->vf_offload_flags &
7025 VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
7026 for (i = 0; i < msg->num_vsis; i++) {
7027 if (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) {
7028 i40e_memcpy(hw->mac.perm_addr,
7029 vsi_res->default_mac_addr,
7031 I40E_NONDMA_TO_NONDMA);
7032 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
7034 I40E_NONDMA_TO_NONDMA);
7042 * @hw: pointer to the hardware structure
7044 * Send a VF_RESET message to the PF. Does not wait for response from PF
7045 * as none will be forthcoming. Immediately after calling this function,
7046 * the admin queue should be shut down and (optionally) reinitialized.
7048 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
7050 return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF,
7051 I40E_SUCCESS, NULL, 0, NULL);
7053 #endif /* VF_DRIVER */
7056 * i40e_aq_set_arp_proxy_config
7057 * @hw: pointer to the HW structure
7058 * @proxy_config - pointer to proxy config command table struct
7059 * @cmd_details: pointer to command details
7061 * Set ARP offload parameters from pre-populated
7062 * i40e_aqc_arp_proxy_data struct
7064 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
7065 struct i40e_aqc_arp_proxy_data *proxy_config,
7066 struct i40e_asq_cmd_details *cmd_details)
7068 struct i40e_aq_desc desc;
7069 enum i40e_status_code status;
7072 return I40E_ERR_PARAM;
7074 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
7076 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7077 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7078 desc.params.external.addr_high =
7079 CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
7080 desc.params.external.addr_low =
7081 CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
7082 desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_arp_proxy_data));
7084 status = i40e_asq_send_command(hw, &desc, proxy_config,
7085 sizeof(struct i40e_aqc_arp_proxy_data),
7092 * i40e_aq_opc_set_ns_proxy_table_entry
7093 * @hw: pointer to the HW structure
7094 * @ns_proxy_table_entry: pointer to NS table entry command struct
7095 * @cmd_details: pointer to command details
7097 * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
7098 * from pre-populated i40e_aqc_ns_proxy_data struct
7100 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
7101 struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
7102 struct i40e_asq_cmd_details *cmd_details)
7104 struct i40e_aq_desc desc;
7105 enum i40e_status_code status;
7107 if (!ns_proxy_table_entry)
7108 return I40E_ERR_PARAM;
7110 i40e_fill_default_direct_cmd_desc(&desc,
7111 i40e_aqc_opc_set_ns_proxy_table_entry);
7113 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7114 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7115 desc.params.external.addr_high =
7116 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
7117 desc.params.external.addr_low =
7118 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
7119 desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_ns_proxy_data));
7121 status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
7122 sizeof(struct i40e_aqc_ns_proxy_data),
7129 * i40e_aq_set_clear_wol_filter
7130 * @hw: pointer to the hw struct
7131 * @filter_index: index of filter to modify (0-7)
7132 * @filter: buffer containing filter to be set
7133 * @set_filter: true to set filter, false to clear filter
7134 * @no_wol_tco: if true, pass through packets cannot cause wake-up
7135 * if false, pass through packets may cause wake-up
7136 * @filter_valid: true if filter action is valid
7137 * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
7138 * @cmd_details: pointer to command details structure or NULL
7140 * Set or clear WoL filter for port attached to the PF
7142 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
7144 struct i40e_aqc_set_wol_filter_data *filter,
7145 bool set_filter, bool no_wol_tco,
7146 bool filter_valid, bool no_wol_tco_valid,
7147 struct i40e_asq_cmd_details *cmd_details)
7149 struct i40e_aq_desc desc;
7150 struct i40e_aqc_set_wol_filter *cmd =
7151 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
7152 enum i40e_status_code status;
7154 u16 valid_flags = 0;
7157 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
7159 if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
7160 return I40E_ERR_PARAM;
7161 cmd->filter_index = CPU_TO_LE16(filter_index);
7165 return I40E_ERR_PARAM;
7167 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
7168 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR;
7172 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
7173 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
7176 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
7177 if (no_wol_tco_valid)
7178 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
7179 cmd->valid_flags = CPU_TO_LE16(valid_flags);
7181 buff_len = sizeof(*filter);
7182 desc.datalen = CPU_TO_LE16(buff_len);
7184 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7185 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7187 cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
7188 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
7190 status = i40e_asq_send_command(hw, &desc, filter,
7191 buff_len, cmd_details);
7197 * i40e_aq_get_wake_event_reason
7198 * @hw: pointer to the hw struct
7199 * @wake_reason: return value, index of matching filter
7200 * @cmd_details: pointer to command details structure or NULL
7202 * Get information for the reason of a Wake Up event
7204 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
7206 struct i40e_asq_cmd_details *cmd_details)
7208 struct i40e_aq_desc desc;
7209 struct i40e_aqc_get_wake_reason_completion *resp =
7210 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
7211 enum i40e_status_code status;
7213 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
7215 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7217 if (status == I40E_SUCCESS)
7218 *wake_reason = LE16_TO_CPU(resp->wake_reason);
7224 * i40e_aq_clear_all_wol_filters
7225 * @hw: pointer to the hw struct
7226 * @cmd_details: pointer to command details structure or NULL
7228 * Get information for the reason of a Wake Up event
7230 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw,
7231 struct i40e_asq_cmd_details *cmd_details)
7233 struct i40e_aq_desc desc;
7234 enum i40e_status_code status;
7236 i40e_fill_default_direct_cmd_desc(&desc,
7237 i40e_aqc_opc_clear_all_wol_filters);
7239 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7246 * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
7247 * @hw: pointer to the hw struct
7248 * @buff: command buffer (size in bytes = buff_size)
7249 * @buff_size: buffer size in bytes
7250 * @track_id: package tracking id
7251 * @error_offset: returns error offset
7252 * @error_info: returns error information
7253 * @cmd_details: pointer to command details structure or NULL
7256 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
7257 u16 buff_size, u32 track_id,
7258 u32 *error_offset, u32 *error_info,
7259 struct i40e_asq_cmd_details *cmd_details)
7261 struct i40e_aq_desc desc;
7262 struct i40e_aqc_write_personalization_profile *cmd =
7263 (struct i40e_aqc_write_personalization_profile *)
7265 struct i40e_aqc_write_ddp_resp *resp;
7266 enum i40e_status_code status;
7268 i40e_fill_default_direct_cmd_desc(&desc,
7269 i40e_aqc_opc_write_personalization_profile);
7271 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
7272 if (buff_size > I40E_AQ_LARGE_BUF)
7273 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7275 desc.datalen = CPU_TO_LE16(buff_size);
7277 cmd->profile_track_id = CPU_TO_LE32(track_id);
7279 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7281 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
7283 *error_offset = LE32_TO_CPU(resp->error_offset);
7285 *error_info = LE32_TO_CPU(resp->error_info);
7292 * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
7293 * @hw: pointer to the hw struct
7294 * @buff: command buffer (size in bytes = buff_size)
7295 * @buff_size: buffer size in bytes
7296 * @cmd_details: pointer to command details structure or NULL
7299 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
7300 u16 buff_size, u8 flags,
7301 struct i40e_asq_cmd_details *cmd_details)
7303 struct i40e_aq_desc desc;
7304 struct i40e_aqc_get_applied_profiles *cmd =
7305 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
7306 enum i40e_status_code status;
7308 i40e_fill_default_direct_cmd_desc(&desc,
7309 i40e_aqc_opc_get_personalization_profile_list);
7311 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7312 if (buff_size > I40E_AQ_LARGE_BUF)
7313 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7314 desc.datalen = CPU_TO_LE16(buff_size);
7318 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7324 * i40e_find_segment_in_package
7325 * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
7326 * @pkg_hdr: pointer to the package header to be searched
7328 * This function searches a package file for a particular segment type. On
7329 * success it returns a pointer to the segment header, otherwise it will
7332 struct i40e_generic_seg_header *
7333 i40e_find_segment_in_package(u32 segment_type,
7334 struct i40e_package_header *pkg_hdr)
7336 struct i40e_generic_seg_header *segment;
7339 /* Search all package segments for the requested segment type */
7340 for (i = 0; i < pkg_hdr->segment_count; i++) {
7342 (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
7343 pkg_hdr->segment_offset[i]);
7345 if (segment->type == segment_type)
7353 * i40e_write_profile
7354 * @hw: pointer to the hardware structure
7355 * @profile: pointer to the profile segment of the package to be downloaded
7356 * @track_id: package tracking id
7358 * Handles the download of a complete package.
7360 enum i40e_status_code
7361 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7364 enum i40e_status_code status = I40E_SUCCESS;
7365 struct i40e_section_table *sec_tbl;
7366 struct i40e_profile_section_header *sec = NULL;
7370 u32 section_size = 0;
7371 u32 offset = 0, info = 0;
7374 dev_cnt = profile->device_table_count;
7376 for (i = 0; i < dev_cnt; i++) {
7377 vendor_dev_id = profile->device_table[i].vendor_dev_id;
7378 if ((vendor_dev_id >> 16) == I40E_INTEL_VENDOR_ID)
7379 if (hw->device_id == (vendor_dev_id & 0xFFFF))
7383 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Device doesn't support DDP");
7384 return I40E_ERR_DEVICE_NOT_SUPPORTED;
7387 nvm = (u32 *)&profile->device_table[dev_cnt];
7388 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1];
7390 for (i = 0; i < sec_tbl->section_count; i++) {
7391 sec = (struct i40e_profile_section_header *)((u8 *)profile +
7392 sec_tbl->section_offset[i]);
7394 /* Skip 'AQ', 'note' and 'name' sections */
7395 if (sec->section.type != SECTION_TYPE_MMIO)
7398 section_size = sec->section.size +
7399 sizeof(struct i40e_profile_section_header);
7402 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
7403 track_id, &offset, &info, NULL);
7405 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7406 "Failed to write profile: offset %d, info %d",
7415 * i40e_add_pinfo_to_list
7416 * @hw: pointer to the hardware structure
7417 * @profile: pointer to the profile segment of the package
7418 * @profile_info_sec: buffer for information section
7419 * @track_id: package tracking id
7421 * Register a profile to the list of loaded profiles.
7423 enum i40e_status_code
7424 i40e_add_pinfo_to_list(struct i40e_hw *hw,
7425 struct i40e_profile_segment *profile,
7426 u8 *profile_info_sec, u32 track_id)
7428 enum i40e_status_code status = I40E_SUCCESS;
7429 struct i40e_profile_section_header *sec = NULL;
7430 struct i40e_profile_info *pinfo;
7431 u32 offset = 0, info = 0;
7433 sec = (struct i40e_profile_section_header *)profile_info_sec;
7435 sec->data_end = sizeof(struct i40e_profile_section_header) +
7436 sizeof(struct i40e_profile_info);
7437 sec->section.type = SECTION_TYPE_INFO;
7438 sec->section.offset = sizeof(struct i40e_profile_section_header);
7439 sec->section.size = sizeof(struct i40e_profile_info);
7440 pinfo = (struct i40e_profile_info *)(profile_info_sec +
7441 sec->section.offset);
7442 pinfo->track_id = track_id;
7443 pinfo->version = profile->version;
7444 pinfo->op = I40E_DDP_ADD_TRACKID;
7445 memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE);
7447 status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
7448 track_id, &offset, &info, NULL);