drivers/net/i40e/base/i40e_common.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "i40e_type.h"
  35 #include "i40e_adminq.h"
  36 #include "i40e_prototype.h"
  37 #include "i40e_virtchnl.h"
  38
  39
  40 /**
  41  * i40e_set_mac_type - Sets MAC type
  42  * @hw: pointer to the HW structure
  43  *
  44  * This function sets the mac type of the adapter based on the
  45  * vendor ID and device ID stored in the hw structure.
  46  **/
  47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  49 #else
  50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  51 #endif
  52 {
  53         enum i40e_status_code status = I40E_SUCCESS;
  54
  55         DEBUGFUNC("i40e_set_mac_type\n");
  56
  57         if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
  58                 switch (hw->device_id) {
  59                 case I40E_DEV_ID_SFP_XL710:
  60                 case I40E_DEV_ID_QEMU:
  61                 case I40E_DEV_ID_KX_B:
  62                 case I40E_DEV_ID_KX_C:
  63                 case I40E_DEV_ID_QSFP_A:
  64                 case I40E_DEV_ID_QSFP_B:
  65                 case I40E_DEV_ID_QSFP_C:
  66                 case I40E_DEV_ID_10G_BASE_T:
  67                 case I40E_DEV_ID_10G_BASE_T4:
  68                 case I40E_DEV_ID_20G_KR2:
  69                 case I40E_DEV_ID_20G_KR2_A:
  70                         hw->mac.type = I40E_MAC_XL710;
  71                         break;
  72 #ifdef X722_SUPPORT
  73 #ifdef X722_A0_SUPPORT
  74                 case I40E_DEV_ID_X722_A0:
  75 #endif
  76                 case I40E_DEV_ID_KX_X722:
  77                 case I40E_DEV_ID_QSFP_X722:
  78                 case I40E_DEV_ID_SFP_X722:
  79                 case I40E_DEV_ID_1G_BASE_T_X722:
  80                 case I40E_DEV_ID_10G_BASE_T_X722:
  81                         hw->mac.type = I40E_MAC_X722;
  82                         break;
  83 #endif
  84 #ifdef X722_SUPPORT
  85 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  86                 case I40E_DEV_ID_X722_VF:
  87                 case I40E_DEV_ID_X722_VF_HV:
  88 #ifdef X722_A0_SUPPORT
  89                 case I40E_DEV_ID_X722_A0_VF:
  90 #endif
  91                         hw->mac.type = I40E_MAC_X722_VF;
  92                         break;
  93 #endif /* INTEGRATED_VF || VF_DRIVER */
  94 #endif /* X722_SUPPORT */
  95 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  96                 case I40E_DEV_ID_VF:
  97                 case I40E_DEV_ID_VF_HV:
  98                         hw->mac.type = I40E_MAC_VF;
  99                         break;
 100 #endif
 101                 default:
 102                         hw->mac.type = I40E_MAC_GENERIC;
 103                         break;
 104                 }
 105         } else {
 106                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
 107         }
 108
 109         DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
 110                   hw->mac.type, status);
 111         return status;
 112 }
 113
 114 #ifndef I40E_NDIS_SUPPORT
 115 /**
 116  * i40e_aq_str - convert AQ err code to a string
 117  * @hw: pointer to the HW structure
 118  * @aq_err: the AQ error code to convert
 119  **/
 120 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
 121 {
 122         switch (aq_err) {
 123         case I40E_AQ_RC_OK:
 124                 return "OK";
 125         case I40E_AQ_RC_EPERM:
 126                 return "I40E_AQ_RC_EPERM";
 127         case I40E_AQ_RC_ENOENT:
 128                 return "I40E_AQ_RC_ENOENT";
 129         case I40E_AQ_RC_ESRCH:
 130                 return "I40E_AQ_RC_ESRCH";
 131         case I40E_AQ_RC_EINTR:
 132                 return "I40E_AQ_RC_EINTR";
 133         case I40E_AQ_RC_EIO:
 134                 return "I40E_AQ_RC_EIO";
 135         case I40E_AQ_RC_ENXIO:
 136                 return "I40E_AQ_RC_ENXIO";
 137         case I40E_AQ_RC_E2BIG:
 138                 return "I40E_AQ_RC_E2BIG";
 139         case I40E_AQ_RC_EAGAIN:
 140                 return "I40E_AQ_RC_EAGAIN";
 141         case I40E_AQ_RC_ENOMEM:
 142                 return "I40E_AQ_RC_ENOMEM";
 143         case I40E_AQ_RC_EACCES:
 144                 return "I40E_AQ_RC_EACCES";
 145         case I40E_AQ_RC_EFAULT:
 146                 return "I40E_AQ_RC_EFAULT";
 147         case I40E_AQ_RC_EBUSY:
 148                 return "I40E_AQ_RC_EBUSY";
 149         case I40E_AQ_RC_EEXIST:
 150                 return "I40E_AQ_RC_EEXIST";
 151         case I40E_AQ_RC_EINVAL:
 152                 return "I40E_AQ_RC_EINVAL";
 153         case I40E_AQ_RC_ENOTTY:
 154                 return "I40E_AQ_RC_ENOTTY";
 155         case I40E_AQ_RC_ENOSPC:
 156                 return "I40E_AQ_RC_ENOSPC";
 157         case I40E_AQ_RC_ENOSYS:
 158                 return "I40E_AQ_RC_ENOSYS";
 159         case I40E_AQ_RC_ERANGE:
 160                 return "I40E_AQ_RC_ERANGE";
 161         case I40E_AQ_RC_EFLUSHED:
 162                 return "I40E_AQ_RC_EFLUSHED";
 163         case I40E_AQ_RC_BAD_ADDR:
 164                 return "I40E_AQ_RC_BAD_ADDR";
 165         case I40E_AQ_RC_EMODE:
 166                 return "I40E_AQ_RC_EMODE";
 167         case I40E_AQ_RC_EFBIG:
 168                 return "I40E_AQ_RC_EFBIG";
 169         }
 170
 171         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 172         return hw->err_str;
 173 }
 174
 175 /**
 176  * i40e_stat_str - convert status err code to a string
 177  * @hw: pointer to the HW structure
 178  * @stat_err: the status error code to convert
 179  **/
 180 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
 181 {
 182         switch (stat_err) {
 183         case I40E_SUCCESS:
 184                 return "OK";
 185         case I40E_ERR_NVM:
 186                 return "I40E_ERR_NVM";
 187         case I40E_ERR_NVM_CHECKSUM:
 188                 return "I40E_ERR_NVM_CHECKSUM";
 189         case I40E_ERR_PHY:
 190                 return "I40E_ERR_PHY";
 191         case I40E_ERR_CONFIG:
 192                 return "I40E_ERR_CONFIG";
 193         case I40E_ERR_PARAM:
 194                 return "I40E_ERR_PARAM";
 195         case I40E_ERR_MAC_TYPE:
 196                 return "I40E_ERR_MAC_TYPE";
 197         case I40E_ERR_UNKNOWN_PHY:
 198                 return "I40E_ERR_UNKNOWN_PHY";
 199         case I40E_ERR_LINK_SETUP:
 200                 return "I40E_ERR_LINK_SETUP";
 201         case I40E_ERR_ADAPTER_STOPPED:
 202                 return "I40E_ERR_ADAPTER_STOPPED";
 203         case I40E_ERR_INVALID_MAC_ADDR:
 204                 return "I40E_ERR_INVALID_MAC_ADDR";
 205         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 206                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 207         case I40E_ERR_MASTER_REQUESTS_PENDING:
 208                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 209         case I40E_ERR_INVALID_LINK_SETTINGS:
 210                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 211         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 212                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 213         case I40E_ERR_RESET_FAILED:
 214                 return "I40E_ERR_RESET_FAILED";
 215         case I40E_ERR_SWFW_SYNC:
 216                 return "I40E_ERR_SWFW_SYNC";
 217         case I40E_ERR_NO_AVAILABLE_VSI:
 218                 return "I40E_ERR_NO_AVAILABLE_VSI";
 219         case I40E_ERR_NO_MEMORY:
 220                 return "I40E_ERR_NO_MEMORY";
 221         case I40E_ERR_BAD_PTR:
 222                 return "I40E_ERR_BAD_PTR";
 223         case I40E_ERR_RING_FULL:
 224                 return "I40E_ERR_RING_FULL";
 225         case I40E_ERR_INVALID_PD_ID:
 226                 return "I40E_ERR_INVALID_PD_ID";
 227         case I40E_ERR_INVALID_QP_ID:
 228                 return "I40E_ERR_INVALID_QP_ID";
 229         case I40E_ERR_INVALID_CQ_ID:
 230                 return "I40E_ERR_INVALID_CQ_ID";
 231         case I40E_ERR_INVALID_CEQ_ID:
 232                 return "I40E_ERR_INVALID_CEQ_ID";
 233         case I40E_ERR_INVALID_AEQ_ID:
 234                 return "I40E_ERR_INVALID_AEQ_ID";
 235         case I40E_ERR_INVALID_SIZE:
 236                 return "I40E_ERR_INVALID_SIZE";
 237         case I40E_ERR_INVALID_ARP_INDEX:
 238                 return "I40E_ERR_INVALID_ARP_INDEX";
 239         case I40E_ERR_INVALID_FPM_FUNC_ID:
 240                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 241         case I40E_ERR_QP_INVALID_MSG_SIZE:
 242                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 243         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 244                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 245         case I40E_ERR_INVALID_FRAG_COUNT:
 246                 return "I40E_ERR_INVALID_FRAG_COUNT";
 247         case I40E_ERR_QUEUE_EMPTY:
 248                 return "I40E_ERR_QUEUE_EMPTY";
 249         case I40E_ERR_INVALID_ALIGNMENT:
 250                 return "I40E_ERR_INVALID_ALIGNMENT";
 251         case I40E_ERR_FLUSHED_QUEUE:
 252                 return "I40E_ERR_FLUSHED_QUEUE";
 253         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 254                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 255         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 256                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 257         case I40E_ERR_TIMEOUT:
 258                 return "I40E_ERR_TIMEOUT";
 259         case I40E_ERR_OPCODE_MISMATCH:
 260                 return "I40E_ERR_OPCODE_MISMATCH";
 261         case I40E_ERR_CQP_COMPL_ERROR:
 262                 return "I40E_ERR_CQP_COMPL_ERROR";
 263         case I40E_ERR_INVALID_VF_ID:
 264                 return "I40E_ERR_INVALID_VF_ID";
 265         case I40E_ERR_INVALID_HMCFN_ID:
 266                 return "I40E_ERR_INVALID_HMCFN_ID";
 267         case I40E_ERR_BACKING_PAGE_ERROR:
 268                 return "I40E_ERR_BACKING_PAGE_ERROR";
 269         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 270                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 271         case I40E_ERR_INVALID_PBLE_INDEX:
 272                 return "I40E_ERR_INVALID_PBLE_INDEX";
 273         case I40E_ERR_INVALID_SD_INDEX:
 274                 return "I40E_ERR_INVALID_SD_INDEX";
 275         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 276                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 277         case I40E_ERR_INVALID_SD_TYPE:
 278                 return "I40E_ERR_INVALID_SD_TYPE";
 279         case I40E_ERR_MEMCPY_FAILED:
 280                 return "I40E_ERR_MEMCPY_FAILED";
 281         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 282                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 283         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 284                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 285         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 286                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 287         case I40E_ERR_SRQ_ENABLED:
 288                 return "I40E_ERR_SRQ_ENABLED";
 289         case I40E_ERR_ADMIN_QUEUE_ERROR:
 290                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 291         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 292                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 293         case I40E_ERR_BUF_TOO_SHORT:
 294                 return "I40E_ERR_BUF_TOO_SHORT";
 295         case I40E_ERR_ADMIN_QUEUE_FULL:
 296                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 297         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 298                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 299         case I40E_ERR_BAD_IWARP_CQE:
 300                 return "I40E_ERR_BAD_IWARP_CQE";
 301         case I40E_ERR_NVM_BLANK_MODE:
 302                 return "I40E_ERR_NVM_BLANK_MODE";
 303         case I40E_ERR_NOT_IMPLEMENTED:
 304                 return "I40E_ERR_NOT_IMPLEMENTED";
 305         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 306                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 307         case I40E_ERR_DIAG_TEST_FAILED:
 308                 return "I40E_ERR_DIAG_TEST_FAILED";
 309         case I40E_ERR_NOT_READY:
 310                 return "I40E_ERR_NOT_READY";
 311         case I40E_NOT_SUPPORTED:
 312                 return "I40E_NOT_SUPPORTED";
 313         case I40E_ERR_FIRMWARE_API_VERSION:
 314                 return "I40E_ERR_FIRMWARE_API_VERSION";
 315         }
 316
 317         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 318         return hw->err_str;
 319 }
 320
 321 #endif /* I40E_NDIS_SUPPORT */
 322 /**
 323  * i40e_debug_aq
 324  * @hw: debug mask related to admin queue
 325  * @mask: debug mask
 326  * @desc: pointer to admin queue descriptor
 327  * @buffer: pointer to command buffer
 328  * @buf_len: max length of buffer
 329  *
 330  * Dumps debug log about adminq command with descriptor contents.
 331  **/
 332 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 333                    void *buffer, u16 buf_len)
 334 {
 335         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 336         u16 len = LE16_TO_CPU(aq_desc->datalen);
 337         u8 *buf = (u8 *)buffer;
 338         u16 i = 0;
 339
 340         if ((!(mask & hw->debug_mask)) || (desc == NULL))
 341                 return;
 342
 343         i40e_debug(hw, mask,
 344                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 345                    LE16_TO_CPU(aq_desc->opcode),
 346                    LE16_TO_CPU(aq_desc->flags),
 347                    LE16_TO_CPU(aq_desc->datalen),
 348                    LE16_TO_CPU(aq_desc->retval));
 349         i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
 350                    LE32_TO_CPU(aq_desc->cookie_high),
 351                    LE32_TO_CPU(aq_desc->cookie_low));
 352         i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
 353                    LE32_TO_CPU(aq_desc->params.internal.param0),
 354                    LE32_TO_CPU(aq_desc->params.internal.param1));
 355         i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
 356                    LE32_TO_CPU(aq_desc->params.external.addr_high),
 357                    LE32_TO_CPU(aq_desc->params.external.addr_low));
 358
 359         if ((buffer != NULL) && (aq_desc->datalen != 0)) {
 360                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 361                 if (buf_len < len)
 362                         len = buf_len;
 363                 /* write the full 16-byte chunks */
 364                 for (i = 0; i < (len - 16); i += 16)
 365                         i40e_debug(hw, mask,
 366                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 367                                    i, buf[i], buf[i+1], buf[i+2], buf[i+3],
 368                                    buf[i+4], buf[i+5], buf[i+6], buf[i+7],
 369                                    buf[i+8], buf[i+9], buf[i+10], buf[i+11],
 370                                    buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
 371                 /* the most we could have left is 16 bytes, pad with zeros */
 372                 if (i < len) {
 373                         char d_buf[16];
 374                         int j;
 375
 376                         memset(d_buf, 0, sizeof(d_buf));
 377                         for (j = 0; i < len; j++, i++)
 378                                 d_buf[j] = buf[i];
 379                         i40e_debug(hw, mask,
 380                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 381                                    i, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
 382                                    d_buf[4], d_buf[5], d_buf[6], d_buf[7],
 383                                    d_buf[8], d_buf[9], d_buf[10], d_buf[11],
 384                                    d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
 385                 }
 386         }
 387 }
 388
 389 /**
 390  * i40e_check_asq_alive
 391  * @hw: pointer to the hw struct
 392  *
 393  * Returns true if Queue is enabled else false.
 394  **/
 395 bool i40e_check_asq_alive(struct i40e_hw *hw)
 396 {
 397         if (hw->aq.asq.len)
 398 #ifdef PF_DRIVER
 399 #ifdef INTEGRATED_VF
 400                 if (!i40e_is_vf(hw))
 401                         return !!(rd32(hw, hw->aq.asq.len) &
 402                                 I40E_PF_ATQLEN_ATQENABLE_MASK);
 403 #else
 404                 return !!(rd32(hw, hw->aq.asq.len) &
 405                         I40E_PF_ATQLEN_ATQENABLE_MASK);
 406 #endif /* INTEGRATED_VF */
 407 #endif /* PF_DRIVER */
 408 #ifdef VF_DRIVER
 409 #ifdef INTEGRATED_VF
 410                 if (i40e_is_vf(hw))
 411                         return !!(rd32(hw, hw->aq.asq.len) &
 412                                 I40E_VF_ATQLEN1_ATQENABLE_MASK);
 413 #else
 414                 return !!(rd32(hw, hw->aq.asq.len) &
 415                         I40E_VF_ATQLEN1_ATQENABLE_MASK);
 416 #endif /* INTEGRATED_VF */
 417 #endif /* VF_DRIVER */
 418         return false;
 419 }
 420
 421 /**
 422  * i40e_aq_queue_shutdown
 423  * @hw: pointer to the hw struct
 424  * @unloading: is the driver unloading itself
 425  *
 426  * Tell the Firmware that we're shutting down the AdminQ and whether
 427  * or not the driver is unloading as well.
 428  **/
 429 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
 430                                              bool unloading)
 431 {
 432         struct i40e_aq_desc desc;
 433         struct i40e_aqc_queue_shutdown *cmd =
 434                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 435         enum i40e_status_code status;
 436
 437         i40e_fill_default_direct_cmd_desc(&desc,
 438                                           i40e_aqc_opc_queue_shutdown);
 439
 440         if (unloading)
 441                 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
 442         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 443
 444         return status;
 445 }
 446 #ifdef X722_SUPPORT
 447
 448 /**
 449  * i40e_aq_get_set_rss_lut
 450  * @hw: pointer to the hardware structure
 451  * @vsi_id: vsi fw index
 452  * @pf_lut: for PF table set true, for VSI table set false
 453  * @lut: pointer to the lut buffer provided by the caller
 454  * @lut_size: size of the lut buffer
 455  * @set: set true to set the table, false to get the table
 456  *
 457  * Internal function to get or set RSS look up table
 458  **/
 459 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 460                                                      u16 vsi_id, bool pf_lut,
 461                                                      u8 *lut, u16 lut_size,
 462                                                      bool set)
 463 {
 464         enum i40e_status_code status;
 465         struct i40e_aq_desc desc;
 466         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 467                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 468
 469         if (set)
 470                 i40e_fill_default_direct_cmd_desc(&desc,
 471                                                   i40e_aqc_opc_set_rss_lut);
 472         else
 473                 i40e_fill_default_direct_cmd_desc(&desc,
 474                                                   i40e_aqc_opc_get_rss_lut);
 475
 476         /* Indirect command */
 477         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 478         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 479
 480         cmd_resp->vsi_id =
 481                         CPU_TO_LE16((u16)((vsi_id <<
 482                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 483                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 484         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 485
 486         if (pf_lut)
 487                 cmd_resp->flags |= CPU_TO_LE16((u16)
 488                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 489                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 490                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 491         else
 492                 cmd_resp->flags |= CPU_TO_LE16((u16)
 493                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 494                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 495                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 496
 497         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 498
 499         return status;
 500 }
 501
 502 /**
 503  * i40e_aq_get_rss_lut
 504  * @hw: pointer to the hardware structure
 505  * @vsi_id: vsi fw index
 506  * @pf_lut: for PF table set true, for VSI table set false
 507  * @lut: pointer to the lut buffer provided by the caller
 508  * @lut_size: size of the lut buffer
 509  *
 510  * get the RSS lookup table, PF or VSI type
 511  **/
 512 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 513                                           bool pf_lut, u8 *lut, u16 lut_size)
 514 {
 515         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 516                                        false);
 517 }
 518
 519 /**
 520  * i40e_aq_set_rss_lut
 521  * @hw: pointer to the hardware structure
 522  * @vsi_id: vsi fw index
 523  * @pf_lut: for PF table set true, for VSI table set false
 524  * @lut: pointer to the lut buffer provided by the caller
 525  * @lut_size: size of the lut buffer
 526  *
 527  * set the RSS lookup table, PF or VSI type
 528  **/
 529 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 530                                           bool pf_lut, u8 *lut, u16 lut_size)
 531 {
 532         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
 533 }
 534
 535 /**
 536  * i40e_aq_get_set_rss_key
 537  * @hw: pointer to the hw struct
 538  * @vsi_id: vsi fw index
 539  * @key: pointer to key info struct
 540  * @set: set true to set the key, false to get the key
 541  *
 542  * get the RSS key per VSI
 543  **/
 544 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 545                                       u16 vsi_id,
 546                                       struct i40e_aqc_get_set_rss_key_data *key,
 547                                       bool set)
 548 {
 549         enum i40e_status_code status;
 550         struct i40e_aq_desc desc;
 551         struct i40e_aqc_get_set_rss_key *cmd_resp =
 552                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 553         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 554
 555         if (set)
 556                 i40e_fill_default_direct_cmd_desc(&desc,
 557                                                   i40e_aqc_opc_set_rss_key);
 558         else
 559                 i40e_fill_default_direct_cmd_desc(&desc,
 560                                                   i40e_aqc_opc_get_rss_key);
 561
 562         /* Indirect command */
 563         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 564         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 565
 566         cmd_resp->vsi_id =
 567                         CPU_TO_LE16((u16)((vsi_id <<
 568                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 569                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 570         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 571
 572         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 573
 574         return status;
 575 }
 576
 577 /**
 578  * i40e_aq_get_rss_key
 579  * @hw: pointer to the hw struct
 580  * @vsi_id: vsi fw index
 581  * @key: pointer to key info struct
 582  *
 583  **/
 584 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
 585                                       u16 vsi_id,
 586                                       struct i40e_aqc_get_set_rss_key_data *key)
 587 {
 588         return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
 589 }
 590
 591 /**
 592  * i40e_aq_set_rss_key
 593  * @hw: pointer to the hw struct
 594  * @vsi_id: vsi fw index
 595  * @key: pointer to key info struct
 596  *
 597  * set the RSS key per VSI
 598  **/
 599 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
 600                                       u16 vsi_id,
 601                                       struct i40e_aqc_get_set_rss_key_data *key)
 602 {
 603         return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
 604 }
 605 #endif /* X722_SUPPORT */
 606
 607 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 608  * hardware to a bit-field that can be used by SW to more easily determine the
 609  * packet type.
 610  *
 611  * Macros are used to shorten the table lines and make this table human
 612  * readable.
 613  *
 614  * We store the PTYPE in the top byte of the bit field - this is just so that
 615  * we can check that the table doesn't have a row missing, as the index into
 616  * the table should be the PTYPE.
 617  *
 618  * Typical work flow:
 619  *
 620  * IF NOT i40e_ptype_lookup[ptype].known
 621  * THEN
 622  *      Packet is unknown
 623  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 624  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 625  * ELSE
 626  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 627  * ENDIF
 628  */
 629
 630 /* macro to make the table lines short */
 631 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 632         {       PTYPE, \
 633                 1, \
 634                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 635                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 636                 I40E_RX_PTYPE_##OUTER_FRAG, \
 637                 I40E_RX_PTYPE_TUNNEL_##T, \
 638                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 639                 I40E_RX_PTYPE_##TEF, \
 640                 I40E_RX_PTYPE_INNER_PROT_##I, \
 641                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 642
 643 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 644                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 645
 646 /* shorter macros makes the table fit but are terse */
 647 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 648 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 649 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 650
 651 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 652 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 653         /* L2 Packet types */
 654         I40E_PTT_UNUSED_ENTRY(0),
 655         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 656         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 657         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 658         I40E_PTT_UNUSED_ENTRY(4),
 659         I40E_PTT_UNUSED_ENTRY(5),
 660         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 661         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 662         I40E_PTT_UNUSED_ENTRY(8),
 663         I40E_PTT_UNUSED_ENTRY(9),
 664         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 665         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 666         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 667         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 668         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 669         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 670         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 671         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 672         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 673         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 674         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 675         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 676
 677         /* Non Tunneled IPv4 */
 678         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 679         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 680         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 681         I40E_PTT_UNUSED_ENTRY(25),
 682         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 683         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 684         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 685
 686         /* IPv4 --> IPv4 */
 687         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 688         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 689         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 690         I40E_PTT_UNUSED_ENTRY(32),
 691         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 692         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 693         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 694
 695         /* IPv4 --> IPv6 */
 696         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 697         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 698         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 699         I40E_PTT_UNUSED_ENTRY(39),
 700         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 701         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 702         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 703
 704         /* IPv4 --> GRE/NAT */
 705         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 706
 707         /* IPv4 --> GRE/NAT --> IPv4 */
 708         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 709         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 710         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 711         I40E_PTT_UNUSED_ENTRY(47),
 712         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 713         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 714         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 715
 716         /* IPv4 --> GRE/NAT --> IPv6 */
 717         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 718         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 719         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 720         I40E_PTT_UNUSED_ENTRY(54),
 721         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 722         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 723         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 724
 725         /* IPv4 --> GRE/NAT --> MAC */
 726         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 727
 728         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 729         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 730         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 731         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 732         I40E_PTT_UNUSED_ENTRY(62),
 733         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 734         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 735         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 736
 737         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 738         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 739         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 740         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 741         I40E_PTT_UNUSED_ENTRY(69),
 742         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 743         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 744         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 745
 746         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 747         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 748
 749         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 750         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 751         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 752         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 753         I40E_PTT_UNUSED_ENTRY(77),
 754         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 755         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 756         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 757
 758         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 759         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 760         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 761         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 762         I40E_PTT_UNUSED_ENTRY(84),
 763         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 764         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 765         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 766
 767         /* Non Tunneled IPv6 */
 768         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 769         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 770         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY3),
 771         I40E_PTT_UNUSED_ENTRY(91),
 772         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 773         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 774         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 775
 776         /* IPv6 --> IPv4 */
 777         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 778         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 779         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 780         I40E_PTT_UNUSED_ENTRY(98),
 781         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 782         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 783         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 784
 785         /* IPv6 --> IPv6 */
 786         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 787         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 788         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 789         I40E_PTT_UNUSED_ENTRY(105),
 790         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 791         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 792         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 793
 794         /* IPv6 --> GRE/NAT */
 795         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 796
 797         /* IPv6 --> GRE/NAT -> IPv4 */
 798         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 799         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 800         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 801         I40E_PTT_UNUSED_ENTRY(113),
 802         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 803         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 804         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 805
 806         /* IPv6 --> GRE/NAT -> IPv6 */
 807         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 808         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 809         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 810         I40E_PTT_UNUSED_ENTRY(120),
 811         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 812         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 813         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 814
 815         /* IPv6 --> GRE/NAT -> MAC */
 816         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 817
 818         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 819         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 820         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 821         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 822         I40E_PTT_UNUSED_ENTRY(128),
 823         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 824         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 825         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 826
 827         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 828         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 829         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 830         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 831         I40E_PTT_UNUSED_ENTRY(135),
 832         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 833         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 834         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 835
 836         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 837         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 838
 839         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 840         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 841         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 842         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 843         I40E_PTT_UNUSED_ENTRY(143),
 844         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 845         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 846         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 847
 848         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 849         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 850         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 851         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 852         I40E_PTT_UNUSED_ENTRY(150),
 853         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 854         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 855         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 856
 857         /* unused entries */
 858         I40E_PTT_UNUSED_ENTRY(154),
 859         I40E_PTT_UNUSED_ENTRY(155),
 860         I40E_PTT_UNUSED_ENTRY(156),
 861         I40E_PTT_UNUSED_ENTRY(157),
 862         I40E_PTT_UNUSED_ENTRY(158),
 863         I40E_PTT_UNUSED_ENTRY(159),
 864
 865         I40E_PTT_UNUSED_ENTRY(160),
 866         I40E_PTT_UNUSED_ENTRY(161),
 867         I40E_PTT_UNUSED_ENTRY(162),
 868         I40E_PTT_UNUSED_ENTRY(163),
 869         I40E_PTT_UNUSED_ENTRY(164),
 870         I40E_PTT_UNUSED_ENTRY(165),
 871         I40E_PTT_UNUSED_ENTRY(166),
 872         I40E_PTT_UNUSED_ENTRY(167),
 873         I40E_PTT_UNUSED_ENTRY(168),
 874         I40E_PTT_UNUSED_ENTRY(169),
 875
 876         I40E_PTT_UNUSED_ENTRY(170),
 877         I40E_PTT_UNUSED_ENTRY(171),
 878         I40E_PTT_UNUSED_ENTRY(172),
 879         I40E_PTT_UNUSED_ENTRY(173),
 880         I40E_PTT_UNUSED_ENTRY(174),
 881         I40E_PTT_UNUSED_ENTRY(175),
 882         I40E_PTT_UNUSED_ENTRY(176),
 883         I40E_PTT_UNUSED_ENTRY(177),
 884         I40E_PTT_UNUSED_ENTRY(178),
 885         I40E_PTT_UNUSED_ENTRY(179),
 886
 887         I40E_PTT_UNUSED_ENTRY(180),
 888         I40E_PTT_UNUSED_ENTRY(181),
 889         I40E_PTT_UNUSED_ENTRY(182),
 890         I40E_PTT_UNUSED_ENTRY(183),
 891         I40E_PTT_UNUSED_ENTRY(184),
 892         I40E_PTT_UNUSED_ENTRY(185),
 893         I40E_PTT_UNUSED_ENTRY(186),
 894         I40E_PTT_UNUSED_ENTRY(187),
 895         I40E_PTT_UNUSED_ENTRY(188),
 896         I40E_PTT_UNUSED_ENTRY(189),
 897
 898         I40E_PTT_UNUSED_ENTRY(190),
 899         I40E_PTT_UNUSED_ENTRY(191),
 900         I40E_PTT_UNUSED_ENTRY(192),
 901         I40E_PTT_UNUSED_ENTRY(193),
 902         I40E_PTT_UNUSED_ENTRY(194),
 903         I40E_PTT_UNUSED_ENTRY(195),
 904         I40E_PTT_UNUSED_ENTRY(196),
 905         I40E_PTT_UNUSED_ENTRY(197),
 906         I40E_PTT_UNUSED_ENTRY(198),
 907         I40E_PTT_UNUSED_ENTRY(199),
 908
 909         I40E_PTT_UNUSED_ENTRY(200),
 910         I40E_PTT_UNUSED_ENTRY(201),
 911         I40E_PTT_UNUSED_ENTRY(202),
 912         I40E_PTT_UNUSED_ENTRY(203),
 913         I40E_PTT_UNUSED_ENTRY(204),
 914         I40E_PTT_UNUSED_ENTRY(205),
 915         I40E_PTT_UNUSED_ENTRY(206),
 916         I40E_PTT_UNUSED_ENTRY(207),
 917         I40E_PTT_UNUSED_ENTRY(208),
 918         I40E_PTT_UNUSED_ENTRY(209),
 919
 920         I40E_PTT_UNUSED_ENTRY(210),
 921         I40E_PTT_UNUSED_ENTRY(211),
 922         I40E_PTT_UNUSED_ENTRY(212),
 923         I40E_PTT_UNUSED_ENTRY(213),
 924         I40E_PTT_UNUSED_ENTRY(214),
 925         I40E_PTT_UNUSED_ENTRY(215),
 926         I40E_PTT_UNUSED_ENTRY(216),
 927         I40E_PTT_UNUSED_ENTRY(217),
 928         I40E_PTT_UNUSED_ENTRY(218),
 929         I40E_PTT_UNUSED_ENTRY(219),
 930
 931         I40E_PTT_UNUSED_ENTRY(220),
 932         I40E_PTT_UNUSED_ENTRY(221),
 933         I40E_PTT_UNUSED_ENTRY(222),
 934         I40E_PTT_UNUSED_ENTRY(223),
 935         I40E_PTT_UNUSED_ENTRY(224),
 936         I40E_PTT_UNUSED_ENTRY(225),
 937         I40E_PTT_UNUSED_ENTRY(226),
 938         I40E_PTT_UNUSED_ENTRY(227),
 939         I40E_PTT_UNUSED_ENTRY(228),
 940         I40E_PTT_UNUSED_ENTRY(229),
 941
 942         I40E_PTT_UNUSED_ENTRY(230),
 943         I40E_PTT_UNUSED_ENTRY(231),
 944         I40E_PTT_UNUSED_ENTRY(232),
 945         I40E_PTT_UNUSED_ENTRY(233),
 946         I40E_PTT_UNUSED_ENTRY(234),
 947         I40E_PTT_UNUSED_ENTRY(235),
 948         I40E_PTT_UNUSED_ENTRY(236),
 949         I40E_PTT_UNUSED_ENTRY(237),
 950         I40E_PTT_UNUSED_ENTRY(238),
 951         I40E_PTT_UNUSED_ENTRY(239),
 952
 953         I40E_PTT_UNUSED_ENTRY(240),
 954         I40E_PTT_UNUSED_ENTRY(241),
 955         I40E_PTT_UNUSED_ENTRY(242),
 956         I40E_PTT_UNUSED_ENTRY(243),
 957         I40E_PTT_UNUSED_ENTRY(244),
 958         I40E_PTT_UNUSED_ENTRY(245),
 959         I40E_PTT_UNUSED_ENTRY(246),
 960         I40E_PTT_UNUSED_ENTRY(247),
 961         I40E_PTT_UNUSED_ENTRY(248),
 962         I40E_PTT_UNUSED_ENTRY(249),
 963
 964         I40E_PTT_UNUSED_ENTRY(250),
 965         I40E_PTT_UNUSED_ENTRY(251),
 966         I40E_PTT_UNUSED_ENTRY(252),
 967         I40E_PTT_UNUSED_ENTRY(253),
 968         I40E_PTT_UNUSED_ENTRY(254),
 969         I40E_PTT_UNUSED_ENTRY(255)
 970 };
 971
 972
 973 /**
 974  * i40e_validate_mac_addr - Validate unicast MAC address
 975  * @mac_addr: pointer to MAC address
 976  *
 977  * Tests a MAC address to ensure it is a valid Individual Address
 978  **/
 979 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
 980 {
 981         enum i40e_status_code status = I40E_SUCCESS;
 982
 983         DEBUGFUNC("i40e_validate_mac_addr");
 984
 985         /* Broadcast addresses ARE multicast addresses
 986          * Make sure it is not a multicast address
 987          * Reject the zero address
 988          */
 989         if (I40E_IS_MULTICAST(mac_addr) ||
 990             (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
 991               mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
 992                 status = I40E_ERR_INVALID_MAC_ADDR;
 993
 994         return status;
 995 }
 996 #ifdef PF_DRIVER
 997
 998 /**
 999  * i40e_init_shared_code - Initialize the shared code
1000  * @hw: pointer to hardware structure
1001  *
1002  * This assigns the MAC type and PHY code and inits the NVM.
1003  * Does not touch the hardware. This function must be called prior to any
1004  * other function in the shared code. The i40e_hw structure should be
1005  * memset to 0 prior to calling this function.  The following fields in
1006  * hw structure should be filled in prior to calling this function:
1007  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1008  * subsystem_vendor_id, and revision_id
1009  **/
1010 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
1011 {
1012         enum i40e_status_code status = I40E_SUCCESS;
1013         u32 port, ari, func_rid;
1014
1015         DEBUGFUNC("i40e_init_shared_code");
1016
1017         i40e_set_mac_type(hw);
1018
1019         switch (hw->mac.type) {
1020         case I40E_MAC_XL710:
1021 #ifdef X722_SUPPORT
1022         case I40E_MAC_X722:
1023 #endif
1024                 break;
1025         default:
1026                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1027         }
1028
1029         hw->phy.get_link_info = true;
1030
1031         /* Determine port number and PF number*/
1032         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1033                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1034         hw->port = (u8)port;
1035         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1036                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1037         func_rid = rd32(hw, I40E_PF_FUNC_RID);
1038         if (ari)
1039                 hw->pf_id = (u8)(func_rid & 0xff);
1040         else
1041                 hw->pf_id = (u8)(func_rid & 0x7);
1042
1043 #ifdef X722_SUPPORT
1044         if (hw->mac.type == I40E_MAC_X722)
1045                 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
1046
1047 #endif
1048         status = i40e_init_nvm(hw);
1049         return status;
1050 }
1051
1052 /**
1053  * i40e_aq_mac_address_read - Retrieve the MAC addresses
1054  * @hw: pointer to the hw struct
1055  * @flags: a return indicator of what addresses were added to the addr store
1056  * @addrs: the requestor's mac addr store
1057  * @cmd_details: pointer to command details structure or NULL
1058  **/
1059 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1060                                    u16 *flags,
1061                                    struct i40e_aqc_mac_address_read_data *addrs,
1062                                    struct i40e_asq_cmd_details *cmd_details)
1063 {
1064         struct i40e_aq_desc desc;
1065         struct i40e_aqc_mac_address_read *cmd_data =
1066                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1067         enum i40e_status_code status;
1068
1069         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1070         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1071
1072         status = i40e_asq_send_command(hw, &desc, addrs,
1073                                        sizeof(*addrs), cmd_details);
1074         *flags = LE16_TO_CPU(cmd_data->command_flags);
1075
1076         return status;
1077 }
1078
1079 /**
1080  * i40e_aq_mac_address_write - Change the MAC addresses
1081  * @hw: pointer to the hw struct
1082  * @flags: indicates which MAC to be written
1083  * @mac_addr: address to write
1084  * @cmd_details: pointer to command details structure or NULL
1085  **/
1086 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1087                                     u16 flags, u8 *mac_addr,
1088                                     struct i40e_asq_cmd_details *cmd_details)
1089 {
1090         struct i40e_aq_desc desc;
1091         struct i40e_aqc_mac_address_write *cmd_data =
1092                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1093         enum i40e_status_code status;
1094
1095         i40e_fill_default_direct_cmd_desc(&desc,
1096                                           i40e_aqc_opc_mac_address_write);
1097         cmd_data->command_flags = CPU_TO_LE16(flags);
1098         cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1099         cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1100                                         ((u32)mac_addr[3] << 16) |
1101                                         ((u32)mac_addr[4] << 8) |
1102                                         mac_addr[5]);
1103
1104         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1105
1106         return status;
1107 }
1108
1109 /**
1110  * i40e_get_mac_addr - get MAC address
1111  * @hw: pointer to the HW structure
1112  * @mac_addr: pointer to MAC address
1113  *
1114  * Reads the adapter's MAC address from register
1115  **/
1116 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1117 {
1118         struct i40e_aqc_mac_address_read_data addrs;
1119         enum i40e_status_code status;
1120         u16 flags = 0;
1121
1122         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1123
1124         if (flags & I40E_AQC_LAN_ADDR_VALID)
1125                 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
1126
1127         return status;
1128 }
1129
1130 /**
1131  * i40e_get_port_mac_addr - get Port MAC address
1132  * @hw: pointer to the HW structure
1133  * @mac_addr: pointer to Port MAC address
1134  *
1135  * Reads the adapter's Port MAC address
1136  **/
1137 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1138 {
1139         struct i40e_aqc_mac_address_read_data addrs;
1140         enum i40e_status_code status;
1141         u16 flags = 0;
1142
1143         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1144         if (status)
1145                 return status;
1146
1147         if (flags & I40E_AQC_PORT_ADDR_VALID)
1148                 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
1149         else
1150                 status = I40E_ERR_INVALID_MAC_ADDR;
1151
1152         return status;
1153 }
1154
1155 /**
1156  * i40e_pre_tx_queue_cfg - pre tx queue configure
1157  * @hw: pointer to the HW structure
1158  * @queue: target pf queue index
1159  * @enable: state change request
1160  *
1161  * Handles hw requirement to indicate intention to enable
1162  * or disable target queue.
1163  **/
1164 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1165 {
1166         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1167         u32 reg_block = 0;
1168         u32 reg_val;
1169
1170         if (abs_queue_idx >= 128) {
1171                 reg_block = abs_queue_idx / 128;
1172                 abs_queue_idx %= 128;
1173         }
1174
1175         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1176         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1177         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1178
1179         if (enable)
1180                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1181         else
1182                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1183
1184         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1185 }
1186
1187 /**
1188  *  i40e_read_pba_string - Reads part number string from EEPROM
1189  *  @hw: pointer to hardware structure
1190  *  @pba_num: stores the part number string from the EEPROM
1191  *  @pba_num_size: part number string buffer length
1192  *
1193  *  Reads the part number string from the EEPROM.
1194  **/
1195 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1196                                             u32 pba_num_size)
1197 {
1198         enum i40e_status_code status = I40E_SUCCESS;
1199         u16 pba_word = 0;
1200         u16 pba_size = 0;
1201         u16 pba_ptr = 0;
1202         u16 i = 0;
1203
1204         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1205         if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1206                 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1207                 return status;
1208         }
1209
1210         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1211         if (status != I40E_SUCCESS) {
1212                 DEBUGOUT("Failed to read PBA Block pointer.\n");
1213                 return status;
1214         }
1215
1216         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1217         if (status != I40E_SUCCESS) {
1218                 DEBUGOUT("Failed to read PBA Block size.\n");
1219                 return status;
1220         }
1221
1222         /* Subtract one to get PBA word count (PBA Size word is included in
1223          * total size)
1224          */
1225         pba_size--;
1226         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1227                 DEBUGOUT("Buffer to small for PBA data.\n");
1228                 return I40E_ERR_PARAM;
1229         }
1230
1231         for (i = 0; i < pba_size; i++) {
1232                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1233                 if (status != I40E_SUCCESS) {
1234                         DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1235                         return status;
1236                 }
1237
1238                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1239                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1240         }
1241         pba_num[(pba_size * 2)] = '\0';
1242
1243         return status;
1244 }
1245
1246 /**
1247  * i40e_get_media_type - Gets media type
1248  * @hw: pointer to the hardware structure
1249  **/
1250 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1251 {
1252         enum i40e_media_type media;
1253
1254         switch (hw->phy.link_info.phy_type) {
1255         case I40E_PHY_TYPE_10GBASE_SR:
1256         case I40E_PHY_TYPE_10GBASE_LR:
1257         case I40E_PHY_TYPE_1000BASE_SX:
1258         case I40E_PHY_TYPE_1000BASE_LX:
1259         case I40E_PHY_TYPE_40GBASE_SR4:
1260         case I40E_PHY_TYPE_40GBASE_LR4:
1261                 media = I40E_MEDIA_TYPE_FIBER;
1262                 break;
1263         case I40E_PHY_TYPE_100BASE_TX:
1264         case I40E_PHY_TYPE_1000BASE_T:
1265         case I40E_PHY_TYPE_10GBASE_T:
1266                 media = I40E_MEDIA_TYPE_BASET;
1267                 break;
1268         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1269         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1270         case I40E_PHY_TYPE_10GBASE_CR1:
1271         case I40E_PHY_TYPE_40GBASE_CR4:
1272         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1273         case I40E_PHY_TYPE_40GBASE_AOC:
1274         case I40E_PHY_TYPE_10GBASE_AOC:
1275                 media = I40E_MEDIA_TYPE_DA;
1276                 break;
1277         case I40E_PHY_TYPE_1000BASE_KX:
1278         case I40E_PHY_TYPE_10GBASE_KX4:
1279         case I40E_PHY_TYPE_10GBASE_KR:
1280         case I40E_PHY_TYPE_40GBASE_KR4:
1281         case I40E_PHY_TYPE_20GBASE_KR2:
1282                 media = I40E_MEDIA_TYPE_BACKPLANE;
1283                 break;
1284         case I40E_PHY_TYPE_SGMII:
1285         case I40E_PHY_TYPE_XAUI:
1286         case I40E_PHY_TYPE_XFI:
1287         case I40E_PHY_TYPE_XLAUI:
1288         case I40E_PHY_TYPE_XLPPI:
1289         default:
1290                 media = I40E_MEDIA_TYPE_UNKNOWN;
1291                 break;
1292         }
1293
1294         return media;
1295 }
1296
1297 #define I40E_PF_RESET_WAIT_COUNT        200
1298 /**
1299  * i40e_pf_reset - Reset the PF
1300  * @hw: pointer to the hardware structure
1301  *
1302  * Assuming someone else has triggered a global reset,
1303  * assure the global reset is complete and then reset the PF
1304  **/
1305 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1306 {
1307         u32 cnt = 0;
1308         u32 cnt1 = 0;
1309         u32 reg = 0;
1310         u32 grst_del;
1311
1312         /* Poll for Global Reset steady state in case of recent GRST.
1313          * The grst delay value is in 100ms units, and we'll wait a
1314          * couple counts longer to be sure we don't just miss the end.
1315          */
1316         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1317                         I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1318                         I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1319
1320         /* It can take upto 15 secs for GRST steady state */
1321         grst_del = grst_del * 20; /* bump it to 16 secs max to be safe */
1322
1323         for (cnt = 0; cnt < grst_del; cnt++) {
1324                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1325                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1326                         break;
1327                 i40e_msec_delay(100);
1328         }
1329         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1330                 DEBUGOUT("Global reset polling failed to complete.\n");
1331                 return I40E_ERR_RESET_FAILED;
1332         }
1333
1334         /* Now Wait for the FW to be ready */
1335         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1336                 reg = rd32(hw, I40E_GLNVM_ULD);
1337                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1338                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1339                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1340                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1341                         DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1342                         break;
1343                 }
1344                 i40e_msec_delay(10);
1345         }
1346         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1347                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1348                 DEBUGOUT("wait for FW Reset complete timedout\n");
1349                 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1350                 return I40E_ERR_RESET_FAILED;
1351         }
1352
1353         /* If there was a Global Reset in progress when we got here,
1354          * we don't need to do the PF Reset
1355          */
1356         if (!cnt) {
1357                 reg = rd32(hw, I40E_PFGEN_CTRL);
1358                 wr32(hw, I40E_PFGEN_CTRL,
1359                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1360                 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1361                         reg = rd32(hw, I40E_PFGEN_CTRL);
1362                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1363                                 break;
1364                         i40e_msec_delay(1);
1365                 }
1366                 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1367                         DEBUGOUT("PF reset polling failed to complete.\n");
1368                         return I40E_ERR_RESET_FAILED;
1369                 }
1370         }
1371
1372         i40e_clear_pxe_mode(hw);
1373
1374
1375         return I40E_SUCCESS;
1376 }
1377
1378 /**
1379  * i40e_clear_hw - clear out any left over hw state
1380  * @hw: pointer to the hw struct
1381  *
1382  * Clear queues and interrupts, typically called at init time,
1383  * but after the capabilities have been found so we know how many
1384  * queues and msix vectors have been allocated.
1385  **/
1386 void i40e_clear_hw(struct i40e_hw *hw)
1387 {
1388         u32 num_queues, base_queue;
1389         u32 num_pf_int;
1390         u32 num_vf_int;
1391         u32 num_vfs;
1392         u32 i, j;
1393         u32 val;
1394         u32 eol = 0x7ff;
1395
1396         /* get number of interrupts, queues, and vfs */
1397         val = rd32(hw, I40E_GLPCI_CNF2);
1398         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1399                         I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1400         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1401                         I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1402
1403         val = rd32(hw, I40E_PFLAN_QALLOC);
1404         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1405                         I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1406         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1407                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1408         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1409                 num_queues = (j - base_queue) + 1;
1410         else
1411                 num_queues = 0;
1412
1413         val = rd32(hw, I40E_PF_VT_PFALLOC);
1414         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1415                         I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1416         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1417                         I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1418         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1419                 num_vfs = (j - i) + 1;
1420         else
1421                 num_vfs = 0;
1422
1423         /* stop all the interrupts */
1424         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1425         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1426         for (i = 0; i < num_pf_int - 2; i++)
1427                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1428
1429         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1430         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1431         wr32(hw, I40E_PFINT_LNKLST0, val);
1432         for (i = 0; i < num_pf_int - 2; i++)
1433                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1434         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1435         for (i = 0; i < num_vfs; i++)
1436                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1437         for (i = 0; i < num_vf_int - 2; i++)
1438                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1439
1440         /* warn the HW of the coming Tx disables */
1441         for (i = 0; i < num_queues; i++) {
1442                 u32 abs_queue_idx = base_queue + i;
1443                 u32 reg_block = 0;
1444
1445                 if (abs_queue_idx >= 128) {
1446                         reg_block = abs_queue_idx / 128;
1447                         abs_queue_idx %= 128;
1448                 }
1449
1450                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1451                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1452                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1453                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1454
1455                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1456         }
1457         i40e_usec_delay(400);
1458
1459         /* stop all the queues */
1460         for (i = 0; i < num_queues; i++) {
1461                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1462                 wr32(hw, I40E_QTX_ENA(i), 0);
1463                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1464                 wr32(hw, I40E_QRX_ENA(i), 0);
1465         }
1466
1467         /* short wait for all queue disables to settle */
1468         i40e_usec_delay(50);
1469 }
1470
1471 /**
1472  * i40e_clear_pxe_mode - clear pxe operations mode
1473  * @hw: pointer to the hw struct
1474  *
1475  * Make sure all PXE mode settings are cleared, including things
1476  * like descriptor fetch/write-back mode.
1477  **/
1478 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1479 {
1480         if (i40e_check_asq_alive(hw))
1481                 i40e_aq_clear_pxe_mode(hw, NULL);
1482 }
1483
1484 /**
1485  * i40e_led_is_mine - helper to find matching led
1486  * @hw: pointer to the hw struct
1487  * @idx: index into GPIO registers
1488  *
1489  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1490  */
1491 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1492 {
1493         u32 gpio_val = 0;
1494         u32 port;
1495
1496         if (!hw->func_caps.led[idx])
1497                 return 0;
1498
1499         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1500         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1501                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1502
1503         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1504          * if it is not our port then ignore
1505          */
1506         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1507             (port != hw->port))
1508                 return 0;
1509
1510         return gpio_val;
1511 }
1512
1513 #define I40E_COMBINED_ACTIVITY 0xA
1514 #define I40E_FILTER_ACTIVITY 0xE
1515 #define I40E_LINK_ACTIVITY 0xC
1516 #define I40E_MAC_ACTIVITY 0xD
1517 #define I40E_LED0 22
1518
1519 /**
1520  * i40e_led_get - return current on/off mode
1521  * @hw: pointer to the hw struct
1522  *
1523  * The value returned is the 'mode' field as defined in the
1524  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1525  * values are variations of possible behaviors relating to
1526  * blink, link, and wire.
1527  **/
1528 u32 i40e_led_get(struct i40e_hw *hw)
1529 {
1530         u32 current_mode = 0;
1531         u32 mode = 0;
1532         int i;
1533
1534         /* as per the documentation GPIO 22-29 are the LED
1535          * GPIO pins named LED0..LED7
1536          */
1537         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1538                 u32 gpio_val = i40e_led_is_mine(hw, i);
1539
1540                 if (!gpio_val)
1541                         continue;
1542
1543                 /* ignore gpio LED src mode entries related to the activity LEDs */
1544                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1545                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1546                 switch (current_mode) {
1547                 case I40E_COMBINED_ACTIVITY:
1548                 case I40E_FILTER_ACTIVITY:
1549                 case I40E_MAC_ACTIVITY:
1550                         continue;
1551                 default:
1552                         break;
1553                 }
1554
1555                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1556                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1557                 break;
1558         }
1559
1560         return mode;
1561 }
1562
1563 /**
1564  * i40e_led_set - set new on/off mode
1565  * @hw: pointer to the hw struct
1566  * @mode: 0=off, 0xf=on (else see manual for mode details)
1567  * @blink: true if the LED should blink when on, false if steady
1568  *
1569  * if this function is used to turn on the blink it should
1570  * be used to disable the blink when restoring the original state.
1571  **/
1572 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1573 {
1574         u32 current_mode = 0;
1575         int i;
1576
1577         if (mode & 0xfffffff0)
1578                 DEBUGOUT1("invalid mode passed in %X\n", mode);
1579
1580         /* as per the documentation GPIO 22-29 are the LED
1581          * GPIO pins named LED0..LED7
1582          */
1583         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1584                 u32 gpio_val = i40e_led_is_mine(hw, i);
1585
1586                 if (!gpio_val)
1587                         continue;
1588
1589                 /* ignore gpio LED src mode entries related to the activity LEDs */
1590                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1591                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1592                 switch (current_mode) {
1593                 case I40E_COMBINED_ACTIVITY:
1594                 case I40E_FILTER_ACTIVITY:
1595                 case I40E_MAC_ACTIVITY:
1596                         continue;
1597                 default:
1598                         break;
1599                 }
1600
1601                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1602                 /* this & is a bit of paranoia, but serves as a range check */
1603                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1604                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1605
1606                 if (mode == I40E_LINK_ACTIVITY)
1607                         blink = false;
1608
1609                 if (blink)
1610                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1611                 else
1612                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1613
1614                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1615                 break;
1616         }
1617 }
1618
1619 /* Admin command wrappers */
1620
1621 /**
1622  * i40e_aq_get_phy_capabilities
1623  * @hw: pointer to the hw struct
1624  * @abilities: structure for PHY capabilities to be filled
1625  * @qualified_modules: report Qualified Modules
1626  * @report_init: report init capabilities (active are default)
1627  * @cmd_details: pointer to command details structure or NULL
1628  *
1629  * Returns the various PHY abilities supported on the Port.
1630  **/
1631 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1632                         bool qualified_modules, bool report_init,
1633                         struct i40e_aq_get_phy_abilities_resp *abilities,
1634                         struct i40e_asq_cmd_details *cmd_details)
1635 {
1636         struct i40e_aq_desc desc;
1637         enum i40e_status_code status;
1638         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1639
1640         if (!abilities)
1641                 return I40E_ERR_PARAM;
1642
1643         i40e_fill_default_direct_cmd_desc(&desc,
1644                                           i40e_aqc_opc_get_phy_abilities);
1645
1646         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1647         if (abilities_size > I40E_AQ_LARGE_BUF)
1648                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1649
1650         if (qualified_modules)
1651                 desc.params.external.param0 |=
1652                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1653
1654         if (report_init)
1655                 desc.params.external.param0 |=
1656                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1657
1658         status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1659                                     cmd_details);
1660
1661         if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1662                 status = I40E_ERR_UNKNOWN_PHY;
1663
1664         if (report_init)
1665                 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1666
1667         return status;
1668 }
1669
1670 /**
1671  * i40e_aq_set_phy_config
1672  * @hw: pointer to the hw struct
1673  * @config: structure with PHY configuration to be set
1674  * @cmd_details: pointer to command details structure or NULL
1675  *
1676  * Set the various PHY configuration parameters
1677  * supported on the Port.One or more of the Set PHY config parameters may be
1678  * ignored in an MFP mode as the PF may not have the privilege to set some
1679  * of the PHY Config parameters. This status will be indicated by the
1680  * command response.
1681  **/
1682 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1683                                 struct i40e_aq_set_phy_config *config,
1684                                 struct i40e_asq_cmd_details *cmd_details)
1685 {
1686         struct i40e_aq_desc desc;
1687         struct i40e_aq_set_phy_config *cmd =
1688                 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1689         enum i40e_status_code status;
1690
1691         if (!config)
1692                 return I40E_ERR_PARAM;
1693
1694         i40e_fill_default_direct_cmd_desc(&desc,
1695                                           i40e_aqc_opc_set_phy_config);
1696
1697         *cmd = *config;
1698
1699         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1700
1701         return status;
1702 }
1703
1704 /**
1705  * i40e_set_fc
1706  * @hw: pointer to the hw struct
1707  *
1708  * Set the requested flow control mode using set_phy_config.
1709  **/
1710 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1711                                   bool atomic_restart)
1712 {
1713         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1714         struct i40e_aq_get_phy_abilities_resp abilities;
1715         struct i40e_aq_set_phy_config config;
1716         enum i40e_status_code status;
1717         u8 pause_mask = 0x0;
1718
1719         *aq_failures = 0x0;
1720
1721         switch (fc_mode) {
1722         case I40E_FC_FULL:
1723                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1724                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1725                 break;
1726         case I40E_FC_RX_PAUSE:
1727                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1728                 break;
1729         case I40E_FC_TX_PAUSE:
1730                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1731                 break;
1732         default:
1733                 break;
1734         }
1735
1736         /* Get the current phy config */
1737         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1738                                               NULL);
1739         if (status) {
1740                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1741                 return status;
1742         }
1743
1744         memset(&config, 0, sizeof(config));
1745         /* clear the old pause settings */
1746         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1747                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1748         /* set the new abilities */
1749         config.abilities |= pause_mask;
1750         /* If the abilities have changed, then set the new config */
1751         if (config.abilities != abilities.abilities) {
1752                 /* Auto restart link so settings take effect */
1753                 if (atomic_restart)
1754                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1755                 /* Copy over all the old settings */
1756                 config.phy_type = abilities.phy_type;
1757                 config.link_speed = abilities.link_speed;
1758                 config.eee_capability = abilities.eee_capability;
1759                 config.eeer = abilities.eeer_val;
1760                 config.low_power_ctrl = abilities.d3_lpan;
1761                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1762
1763                 if (status)
1764                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1765         }
1766         /* Update the link info */
1767         status = i40e_update_link_info(hw);
1768         if (status) {
1769                 /* Wait a little bit (on 40G cards it sometimes takes a really
1770                  * long time for link to come back from the atomic reset)
1771                  * and try once more
1772                  */
1773                 i40e_msec_delay(1000);
1774                 status = i40e_update_link_info(hw);
1775         }
1776         if (status)
1777                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1778
1779         return status;
1780 }
1781
1782 /**
1783  * i40e_aq_set_mac_config
1784  * @hw: pointer to the hw struct
1785  * @max_frame_size: Maximum Frame Size to be supported by the port
1786  * @crc_en: Tell HW to append a CRC to outgoing frames
1787  * @pacing: Pacing configurations
1788  * @cmd_details: pointer to command details structure or NULL
1789  *
1790  * Configure MAC settings for frame size, jumbo frame support and the
1791  * addition of a CRC by the hardware.
1792  **/
1793 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1794                                 u16 max_frame_size,
1795                                 bool crc_en, u16 pacing,
1796                                 struct i40e_asq_cmd_details *cmd_details)
1797 {
1798         struct i40e_aq_desc desc;
1799         struct i40e_aq_set_mac_config *cmd =
1800                 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1801         enum i40e_status_code status;
1802
1803         if (max_frame_size == 0)
1804                 return I40E_ERR_PARAM;
1805
1806         i40e_fill_default_direct_cmd_desc(&desc,
1807                                           i40e_aqc_opc_set_mac_config);
1808
1809         cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1810         cmd->params = ((u8)pacing & 0x0F) << 3;
1811         if (crc_en)
1812                 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1813
1814         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1815
1816         return status;
1817 }
1818
1819 /**
1820  * i40e_aq_clear_pxe_mode
1821  * @hw: pointer to the hw struct
1822  * @cmd_details: pointer to command details structure or NULL
1823  *
1824  * Tell the firmware that the driver is taking over from PXE
1825  **/
1826 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1827                         struct i40e_asq_cmd_details *cmd_details)
1828 {
1829         enum i40e_status_code status;
1830         struct i40e_aq_desc desc;
1831         struct i40e_aqc_clear_pxe *cmd =
1832                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1833
1834         i40e_fill_default_direct_cmd_desc(&desc,
1835                                           i40e_aqc_opc_clear_pxe_mode);
1836
1837         cmd->rx_cnt = 0x2;
1838
1839         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1840
1841         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1842
1843         return status;
1844 }
1845
1846 /**
1847  * i40e_aq_set_link_restart_an
1848  * @hw: pointer to the hw struct
1849  * @enable_link: if true: enable link, if false: disable link
1850  * @cmd_details: pointer to command details structure or NULL
1851  *
1852  * Sets up the link and restarts the Auto-Negotiation over the link.
1853  **/
1854 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1855                 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1856 {
1857         struct i40e_aq_desc desc;
1858         struct i40e_aqc_set_link_restart_an *cmd =
1859                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1860         enum i40e_status_code status;
1861
1862         i40e_fill_default_direct_cmd_desc(&desc,
1863                                           i40e_aqc_opc_set_link_restart_an);
1864
1865         cmd->command = I40E_AQ_PHY_RESTART_AN;
1866         if (enable_link)
1867                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1868         else
1869                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1870
1871         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1872
1873         return status;
1874 }
1875
1876 /**
1877  * i40e_aq_get_link_info
1878  * @hw: pointer to the hw struct
1879  * @enable_lse: enable/disable LinkStatusEvent reporting
1880  * @link: pointer to link status structure - optional
1881  * @cmd_details: pointer to command details structure or NULL
1882  *
1883  * Returns the link status of the adapter.
1884  **/
1885 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1886                                 bool enable_lse, struct i40e_link_status *link,
1887                                 struct i40e_asq_cmd_details *cmd_details)
1888 {
1889         struct i40e_aq_desc desc;
1890         struct i40e_aqc_get_link_status *resp =
1891                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1892         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1893         enum i40e_status_code status;
1894         bool tx_pause, rx_pause;
1895         u16 command_flags;
1896
1897         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1898
1899         if (enable_lse)
1900                 command_flags = I40E_AQ_LSE_ENABLE;
1901         else
1902                 command_flags = I40E_AQ_LSE_DISABLE;
1903         resp->command_flags = CPU_TO_LE16(command_flags);
1904
1905         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1906
1907         if (status != I40E_SUCCESS)
1908                 goto aq_get_link_info_exit;
1909
1910         /* save off old link status information */
1911         i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1912                     sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1913
1914         /* update link status */
1915         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1916         hw->phy.media_type = i40e_get_media_type(hw);
1917         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1918         hw_link_info->link_info = resp->link_info;
1919         hw_link_info->an_info = resp->an_info;
1920         hw_link_info->ext_info = resp->ext_info;
1921         hw_link_info->loopback = resp->loopback;
1922         hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1923         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1924
1925         /* update fc info */
1926         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1927         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1928         if (tx_pause & rx_pause)
1929                 hw->fc.current_mode = I40E_FC_FULL;
1930         else if (tx_pause)
1931                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1932         else if (rx_pause)
1933                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1934         else
1935                 hw->fc.current_mode = I40E_FC_NONE;
1936
1937         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1938                 hw_link_info->crc_enable = true;
1939         else
1940                 hw_link_info->crc_enable = false;
1941
1942         if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1943                 hw_link_info->lse_enable = true;
1944         else
1945                 hw_link_info->lse_enable = false;
1946
1947         if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1948              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1949                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1950
1951         /* save link status information */
1952         if (link)
1953                 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1954                             I40E_NONDMA_TO_NONDMA);
1955
1956         /* flag cleared so helper functions don't call AQ again */
1957         hw->phy.get_link_info = false;
1958
1959 aq_get_link_info_exit:
1960         return status;
1961 }
1962
1963 /**
1964  * i40e_aq_set_phy_int_mask
1965  * @hw: pointer to the hw struct
1966  * @mask: interrupt mask to be set
1967  * @cmd_details: pointer to command details structure or NULL
1968  *
1969  * Set link interrupt mask.
1970  **/
1971 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1972                                 u16 mask,
1973                                 struct i40e_asq_cmd_details *cmd_details)
1974 {
1975         struct i40e_aq_desc desc;
1976         struct i40e_aqc_set_phy_int_mask *cmd =
1977                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1978         enum i40e_status_code status;
1979
1980         i40e_fill_default_direct_cmd_desc(&desc,
1981                                           i40e_aqc_opc_set_phy_int_mask);
1982
1983         cmd->event_mask = CPU_TO_LE16(mask);
1984
1985         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1986
1987         return status;
1988 }
1989
1990 /**
1991  * i40e_aq_get_local_advt_reg
1992  * @hw: pointer to the hw struct
1993  * @advt_reg: local AN advertisement register value
1994  * @cmd_details: pointer to command details structure or NULL
1995  *
1996  * Get the Local AN advertisement register value.
1997  **/
1998 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
1999                                 u64 *advt_reg,
2000                                 struct i40e_asq_cmd_details *cmd_details)
2001 {
2002         struct i40e_aq_desc desc;
2003         struct i40e_aqc_an_advt_reg *resp =
2004                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2005         enum i40e_status_code status;
2006
2007         i40e_fill_default_direct_cmd_desc(&desc,
2008                                           i40e_aqc_opc_get_local_advt_reg);
2009
2010         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2011
2012         if (status != I40E_SUCCESS)
2013                 goto aq_get_local_advt_reg_exit;
2014
2015         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2016         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2017
2018 aq_get_local_advt_reg_exit:
2019         return status;
2020 }
2021
2022 /**
2023  * i40e_aq_set_local_advt_reg
2024  * @hw: pointer to the hw struct
2025  * @advt_reg: local AN advertisement register value
2026  * @cmd_details: pointer to command details structure or NULL
2027  *
2028  * Get the Local AN advertisement register value.
2029  **/
2030 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2031                                 u64 advt_reg,
2032                                 struct i40e_asq_cmd_details *cmd_details)
2033 {
2034         struct i40e_aq_desc desc;
2035         struct i40e_aqc_an_advt_reg *cmd =
2036                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2037         enum i40e_status_code status;
2038
2039         i40e_fill_default_direct_cmd_desc(&desc,
2040                                           i40e_aqc_opc_get_local_advt_reg);
2041
2042         cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2043         cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2044
2045         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2046
2047         return status;
2048 }
2049
2050 /**
2051  * i40e_aq_get_partner_advt
2052  * @hw: pointer to the hw struct
2053  * @advt_reg: AN partner advertisement register value
2054  * @cmd_details: pointer to command details structure or NULL
2055  *
2056  * Get the link partner AN advertisement register value.
2057  **/
2058 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2059                                 u64 *advt_reg,
2060                                 struct i40e_asq_cmd_details *cmd_details)
2061 {
2062         struct i40e_aq_desc desc;
2063         struct i40e_aqc_an_advt_reg *resp =
2064                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2065         enum i40e_status_code status;
2066
2067         i40e_fill_default_direct_cmd_desc(&desc,
2068                                           i40e_aqc_opc_get_partner_advt);
2069
2070         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2071
2072         if (status != I40E_SUCCESS)
2073                 goto aq_get_partner_advt_exit;
2074
2075         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2076         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2077
2078 aq_get_partner_advt_exit:
2079         return status;
2080 }
2081
2082 /**
2083  * i40e_aq_set_lb_modes
2084  * @hw: pointer to the hw struct
2085  * @lb_modes: loopback mode to be set
2086  * @cmd_details: pointer to command details structure or NULL
2087  *
2088  * Sets loopback modes.
2089  **/
2090 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2091                                 u16 lb_modes,
2092                                 struct i40e_asq_cmd_details *cmd_details)
2093 {
2094         struct i40e_aq_desc desc;
2095         struct i40e_aqc_set_lb_mode *cmd =
2096                 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2097         enum i40e_status_code status;
2098
2099         i40e_fill_default_direct_cmd_desc(&desc,
2100                                           i40e_aqc_opc_set_lb_modes);
2101
2102         cmd->lb_mode = CPU_TO_LE16(lb_modes);
2103
2104         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2105
2106         return status;
2107 }
2108
2109 /**
2110  * i40e_aq_set_phy_debug
2111  * @hw: pointer to the hw struct
2112  * @cmd_flags: debug command flags
2113  * @cmd_details: pointer to command details structure or NULL
2114  *
2115  * Reset the external PHY.
2116  **/
2117 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2118                                 struct i40e_asq_cmd_details *cmd_details)
2119 {
2120         struct i40e_aq_desc desc;
2121         struct i40e_aqc_set_phy_debug *cmd =
2122                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2123         enum i40e_status_code status;
2124
2125         i40e_fill_default_direct_cmd_desc(&desc,
2126                                           i40e_aqc_opc_set_phy_debug);
2127
2128         cmd->command_flags = cmd_flags;
2129
2130         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2131
2132         return status;
2133 }
2134
2135 /**
2136  * i40e_aq_add_vsi
2137  * @hw: pointer to the hw struct
2138  * @vsi_ctx: pointer to a vsi context struct
2139  * @cmd_details: pointer to command details structure or NULL
2140  *
2141  * Add a VSI context to the hardware.
2142 **/
2143 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2144                                 struct i40e_vsi_context *vsi_ctx,
2145                                 struct i40e_asq_cmd_details *cmd_details)
2146 {
2147         struct i40e_aq_desc desc;
2148         struct i40e_aqc_add_get_update_vsi *cmd =
2149                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2150         struct i40e_aqc_add_get_update_vsi_completion *resp =
2151                 (struct i40e_aqc_add_get_update_vsi_completion *)
2152                 &desc.params.raw;
2153         enum i40e_status_code status;
2154
2155         i40e_fill_default_direct_cmd_desc(&desc,
2156                                           i40e_aqc_opc_add_vsi);
2157
2158         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2159         cmd->connection_type = vsi_ctx->connection_type;
2160         cmd->vf_id = vsi_ctx->vf_num;
2161         cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2162
2163         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2164
2165         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2166                                     sizeof(vsi_ctx->info), cmd_details);
2167
2168         if (status != I40E_SUCCESS)
2169                 goto aq_add_vsi_exit;
2170
2171         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2172         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2173         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2174         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2175
2176 aq_add_vsi_exit:
2177         return status;
2178 }
2179
2180 /**
2181  * i40e_aq_set_default_vsi
2182  * @hw: pointer to the hw struct
2183  * @seid: vsi number
2184  * @cmd_details: pointer to command details structure or NULL
2185  **/
2186 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2187                                 u16 seid,
2188                                 struct i40e_asq_cmd_details *cmd_details)
2189 {
2190         struct i40e_aq_desc desc;
2191         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2192                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2193                 &desc.params.raw;
2194         enum i40e_status_code status;
2195
2196         i40e_fill_default_direct_cmd_desc(&desc,
2197                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2198
2199         cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2200         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2201         cmd->seid = CPU_TO_LE16(seid);
2202
2203         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2204
2205         return status;
2206 }
2207
2208 /**
2209  * i40e_aq_set_vsi_unicast_promiscuous
2210  * @hw: pointer to the hw struct
2211  * @seid: vsi number
2212  * @set: set unicast promiscuous enable/disable
2213  * @cmd_details: pointer to command details structure or NULL
2214  **/
2215 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2216                                 u16 seid, bool set,
2217                                 struct i40e_asq_cmd_details *cmd_details)
2218 {
2219         struct i40e_aq_desc desc;
2220         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2221                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2222         enum i40e_status_code status;
2223         u16 flags = 0;
2224
2225         i40e_fill_default_direct_cmd_desc(&desc,
2226                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2227
2228         if (set) {
2229                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2230                 if (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2231                      (hw->aq.api_maj_ver > 1))
2232                         flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2233         }
2234
2235         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2236
2237         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2238         if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2239              (hw->aq.api_maj_ver > 1))
2240                 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2241
2242         cmd->seid = CPU_TO_LE16(seid);
2243         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2244
2245         return status;
2246 }
2247
2248 /**
2249  * i40e_aq_set_vsi_multicast_promiscuous
2250  * @hw: pointer to the hw struct
2251  * @seid: vsi number
2252  * @set: set multicast promiscuous enable/disable
2253  * @cmd_details: pointer to command details structure or NULL
2254  **/
2255 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2256                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2257 {
2258         struct i40e_aq_desc desc;
2259         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2260                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2261         enum i40e_status_code status;
2262         u16 flags = 0;
2263
2264         i40e_fill_default_direct_cmd_desc(&desc,
2265                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2266
2267         if (set)
2268                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2269
2270         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2271
2272         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2273
2274         cmd->seid = CPU_TO_LE16(seid);
2275         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2276
2277         return status;
2278 }
2279
2280 /**
2281  * i40e_aq_set_vsi_mc_promisc_on_vlan
2282  * @hw: pointer to the hw struct
2283  * @seid: vsi number
2284  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2285  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2286  * @cmd_details: pointer to command details structure or NULL
2287  **/
2288 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2289                                 u16 seid, bool enable, u16 vid,
2290                                 struct i40e_asq_cmd_details *cmd_details)
2291 {
2292         struct i40e_aq_desc desc;
2293         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2294                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2295         enum i40e_status_code status;
2296         u16 flags = 0;
2297
2298         i40e_fill_default_direct_cmd_desc(&desc,
2299                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2300
2301         if (enable)
2302                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2303
2304         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2305         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2306         cmd->seid = CPU_TO_LE16(seid);
2307         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2308
2309         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2310
2311         return status;
2312 }
2313
2314 /**
2315  * i40e_aq_set_vsi_uc_promisc_on_vlan
2316  * @hw: pointer to the hw struct
2317  * @seid: vsi number
2318  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2319  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2320  * @cmd_details: pointer to command details structure or NULL
2321  **/
2322 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2323                                 u16 seid, bool enable, u16 vid,
2324                                 struct i40e_asq_cmd_details *cmd_details)
2325 {
2326         struct i40e_aq_desc desc;
2327         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2328                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2329         enum i40e_status_code status;
2330         u16 flags = 0;
2331
2332         i40e_fill_default_direct_cmd_desc(&desc,
2333                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2334
2335         if (enable)
2336                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2337
2338         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2339         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2340         cmd->seid = CPU_TO_LE16(seid);
2341         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2342
2343         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2344
2345         return status;
2346 }
2347
2348 /**
2349  * i40e_aq_set_vsi_broadcast
2350  * @hw: pointer to the hw struct
2351  * @seid: vsi number
2352  * @set_filter: true to set filter, false to clear filter
2353  * @cmd_details: pointer to command details structure or NULL
2354  *
2355  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2356  **/
2357 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2358                                 u16 seid, bool set_filter,
2359                                 struct i40e_asq_cmd_details *cmd_details)
2360 {
2361         struct i40e_aq_desc desc;
2362         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2363                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2364         enum i40e_status_code status;
2365
2366         i40e_fill_default_direct_cmd_desc(&desc,
2367                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2368
2369         if (set_filter)
2370                 cmd->promiscuous_flags
2371                             |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2372         else
2373                 cmd->promiscuous_flags
2374                             &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2375
2376         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2377         cmd->seid = CPU_TO_LE16(seid);
2378         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2379
2380         return status;
2381 }
2382
2383 /**
2384  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2385  * @hw: pointer to the hw struct
2386  * @seid: vsi number
2387  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2388  * @cmd_details: pointer to command details structure or NULL
2389  **/
2390 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2391                                 u16 seid, bool enable,
2392                                 struct i40e_asq_cmd_details *cmd_details)
2393 {
2394         struct i40e_aq_desc desc;
2395         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2396                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2397         enum i40e_status_code status;
2398         u16 flags = 0;
2399
2400         i40e_fill_default_direct_cmd_desc(&desc,
2401                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2402         if (enable)
2403                 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2404
2405         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2406         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2407         cmd->seid = CPU_TO_LE16(seid);
2408
2409         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2410
2411         return status;
2412 }
2413
2414 /**
2415  * i40e_get_vsi_params - get VSI configuration info
2416  * @hw: pointer to the hw struct
2417  * @vsi_ctx: pointer to a vsi context struct
2418  * @cmd_details: pointer to command details structure or NULL
2419  **/
2420 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2421                                 struct i40e_vsi_context *vsi_ctx,
2422                                 struct i40e_asq_cmd_details *cmd_details)
2423 {
2424         struct i40e_aq_desc desc;
2425         struct i40e_aqc_add_get_update_vsi *cmd =
2426                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2427         struct i40e_aqc_add_get_update_vsi_completion *resp =
2428                 (struct i40e_aqc_add_get_update_vsi_completion *)
2429                 &desc.params.raw;
2430         enum i40e_status_code status;
2431
2432         UNREFERENCED_1PARAMETER(cmd_details);
2433         i40e_fill_default_direct_cmd_desc(&desc,
2434                                           i40e_aqc_opc_get_vsi_parameters);
2435
2436         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2437
2438         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2439
2440         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2441                                     sizeof(vsi_ctx->info), NULL);
2442
2443         if (status != I40E_SUCCESS)
2444                 goto aq_get_vsi_params_exit;
2445
2446         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2447         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2448         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2449         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2450
2451 aq_get_vsi_params_exit:
2452         return status;
2453 }
2454
2455 /**
2456  * i40e_aq_update_vsi_params
2457  * @hw: pointer to the hw struct
2458  * @vsi_ctx: pointer to a vsi context struct
2459  * @cmd_details: pointer to command details structure or NULL
2460  *
2461  * Update a VSI context.
2462  **/
2463 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2464                                 struct i40e_vsi_context *vsi_ctx,
2465                                 struct i40e_asq_cmd_details *cmd_details)
2466 {
2467         struct i40e_aq_desc desc;
2468         struct i40e_aqc_add_get_update_vsi *cmd =
2469                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2470         struct i40e_aqc_add_get_update_vsi_completion *resp =
2471                 (struct i40e_aqc_add_get_update_vsi_completion *)
2472                 &desc.params.raw;
2473         enum i40e_status_code status;
2474
2475         i40e_fill_default_direct_cmd_desc(&desc,
2476                                           i40e_aqc_opc_update_vsi_parameters);
2477         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2478
2479         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2480
2481         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2482                                     sizeof(vsi_ctx->info), cmd_details);
2483
2484         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2485         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2486
2487         return status;
2488 }
2489
2490 /**
2491  * i40e_aq_get_switch_config
2492  * @hw: pointer to the hardware structure
2493  * @buf: pointer to the result buffer
2494  * @buf_size: length of input buffer
2495  * @start_seid: seid to start for the report, 0 == beginning
2496  * @cmd_details: pointer to command details structure or NULL
2497  *
2498  * Fill the buf with switch configuration returned from AdminQ command
2499  **/
2500 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2501                                 struct i40e_aqc_get_switch_config_resp *buf,
2502                                 u16 buf_size, u16 *start_seid,
2503                                 struct i40e_asq_cmd_details *cmd_details)
2504 {
2505         struct i40e_aq_desc desc;
2506         struct i40e_aqc_switch_seid *scfg =
2507                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2508         enum i40e_status_code status;
2509
2510         i40e_fill_default_direct_cmd_desc(&desc,
2511                                           i40e_aqc_opc_get_switch_config);
2512         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2513         if (buf_size > I40E_AQ_LARGE_BUF)
2514                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2515         scfg->seid = CPU_TO_LE16(*start_seid);
2516
2517         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2518         *start_seid = LE16_TO_CPU(scfg->seid);
2519
2520         return status;
2521 }
2522
2523 /**
2524  * i40e_aq_set_switch_config
2525  * @hw: pointer to the hardware structure
2526  * @flags: bit flag values to set
2527  * @valid_flags: which bit flags to set
2528  * @cmd_details: pointer to command details structure or NULL
2529  *
2530  * Set switch configuration bits
2531  **/
2532 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2533                                 u16 flags, u16 valid_flags,
2534                                 struct i40e_asq_cmd_details *cmd_details)
2535 {
2536         struct i40e_aq_desc desc;
2537         struct i40e_aqc_set_switch_config *scfg =
2538                 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2539         enum i40e_status_code status;
2540
2541         i40e_fill_default_direct_cmd_desc(&desc,
2542                                           i40e_aqc_opc_set_switch_config);
2543         scfg->flags = CPU_TO_LE16(flags);
2544         scfg->valid_flags = CPU_TO_LE16(valid_flags);
2545
2546         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2547
2548         return status;
2549 }
2550
2551 /**
2552  * i40e_aq_get_firmware_version
2553  * @hw: pointer to the hw struct
2554  * @fw_major_version: firmware major version
2555  * @fw_minor_version: firmware minor version
2556  * @fw_build: firmware build number
2557  * @api_major_version: major queue version
2558  * @api_minor_version: minor queue version
2559  * @cmd_details: pointer to command details structure or NULL
2560  *
2561  * Get the firmware version from the admin queue commands
2562  **/
2563 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2564                                 u16 *fw_major_version, u16 *fw_minor_version,
2565                                 u32 *fw_build,
2566                                 u16 *api_major_version, u16 *api_minor_version,
2567                                 struct i40e_asq_cmd_details *cmd_details)
2568 {
2569         struct i40e_aq_desc desc;
2570         struct i40e_aqc_get_version *resp =
2571                 (struct i40e_aqc_get_version *)&desc.params.raw;
2572         enum i40e_status_code status;
2573
2574         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2575
2576         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2577
2578         if (status == I40E_SUCCESS) {
2579                 if (fw_major_version != NULL)
2580                         *fw_major_version = LE16_TO_CPU(resp->fw_major);
2581                 if (fw_minor_version != NULL)
2582                         *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2583                 if (fw_build != NULL)
2584                         *fw_build = LE32_TO_CPU(resp->fw_build);
2585                 if (api_major_version != NULL)
2586                         *api_major_version = LE16_TO_CPU(resp->api_major);
2587                 if (api_minor_version != NULL)
2588                         *api_minor_version = LE16_TO_CPU(resp->api_minor);
2589
2590                 /* A workaround to fix the API version in SW */
2591                 if (api_major_version && api_minor_version &&
2592                     fw_major_version && fw_minor_version &&
2593                     ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2594                     (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2595                      (*fw_major_version > 4)))
2596                         *api_minor_version = 2;
2597         }
2598
2599         return status;
2600 }
2601
2602 /**
2603  * i40e_aq_send_driver_version
2604  * @hw: pointer to the hw struct
2605  * @dv: driver's major, minor version
2606  * @cmd_details: pointer to command details structure or NULL
2607  *
2608  * Send the driver version to the firmware
2609  **/
2610 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2611                                 struct i40e_driver_version *dv,
2612                                 struct i40e_asq_cmd_details *cmd_details)
2613 {
2614         struct i40e_aq_desc desc;
2615         struct i40e_aqc_driver_version *cmd =
2616                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2617         enum i40e_status_code status;
2618         u16 len;
2619
2620         if (dv == NULL)
2621                 return I40E_ERR_PARAM;
2622
2623         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2624
2625         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2626         cmd->driver_major_ver = dv->major_version;
2627         cmd->driver_minor_ver = dv->minor_version;
2628         cmd->driver_build_ver = dv->build_version;
2629         cmd->driver_subbuild_ver = dv->subbuild_version;
2630
2631         len = 0;
2632         while (len < sizeof(dv->driver_string) &&
2633                (dv->driver_string[len] < 0x80) &&
2634                dv->driver_string[len])
2635                 len++;
2636         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2637                                        len, cmd_details);
2638
2639         return status;
2640 }
2641
2642 /**
2643  * i40e_get_link_status - get status of the HW network link
2644  * @hw: pointer to the hw struct
2645  * @link_up: pointer to bool (true/false = linkup/linkdown)
2646  *
2647  * Variable link_up true if link is up, false if link is down.
2648  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2649  *
2650  * Side effect: LinkStatusEvent reporting becomes enabled
2651  **/
2652 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2653 {
2654         enum i40e_status_code status = I40E_SUCCESS;
2655
2656         if (hw->phy.get_link_info) {
2657                 status = i40e_update_link_info(hw);
2658
2659                 if (status != I40E_SUCCESS)
2660                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2661                                    status);
2662         }
2663
2664         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2665
2666         return status;
2667 }
2668
2669 /**
2670  * i40e_updatelink_status - update status of the HW network link
2671  * @hw: pointer to the hw struct
2672  **/
2673 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2674 {
2675         struct i40e_aq_get_phy_abilities_resp abilities;
2676         enum i40e_status_code status = I40E_SUCCESS;
2677
2678         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2679         if (status)
2680                 return status;
2681
2682         if (hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) {
2683                 status = i40e_aq_get_phy_capabilities(hw, false, false,
2684                                                       &abilities, NULL);
2685                 if (status)
2686                         return status;
2687
2688                 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2689                         sizeof(hw->phy.link_info.module_type));
2690         }
2691         return status;
2692 }
2693
2694
2695 /**
2696  * i40e_get_link_speed
2697  * @hw: pointer to the hw struct
2698  *
2699  * Returns the link speed of the adapter.
2700  **/
2701 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2702 {
2703         enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2704         enum i40e_status_code status = I40E_SUCCESS;
2705
2706         if (hw->phy.get_link_info) {
2707                 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2708
2709                 if (status != I40E_SUCCESS)
2710                         goto i40e_link_speed_exit;
2711         }
2712
2713         speed = hw->phy.link_info.link_speed;
2714
2715 i40e_link_speed_exit:
2716         return speed;
2717 }
2718
2719 /**
2720  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2721  * @hw: pointer to the hw struct
2722  * @uplink_seid: the MAC or other gizmo SEID
2723  * @downlink_seid: the VSI SEID
2724  * @enabled_tc: bitmap of TCs to be enabled
2725  * @default_port: true for default port VSI, false for control port
2726  * @veb_seid: pointer to where to put the resulting VEB SEID
2727  * @enable_stats: true to turn on VEB stats
2728  * @cmd_details: pointer to command details structure or NULL
2729  *
2730  * This asks the FW to add a VEB between the uplink and downlink
2731  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2732  **/
2733 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2734                                 u16 downlink_seid, u8 enabled_tc,
2735                                 bool default_port, u16 *veb_seid,
2736                                 bool enable_stats,
2737                                 struct i40e_asq_cmd_details *cmd_details)
2738 {
2739         struct i40e_aq_desc desc;
2740         struct i40e_aqc_add_veb *cmd =
2741                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2742         struct i40e_aqc_add_veb_completion *resp =
2743                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2744         enum i40e_status_code status;
2745         u16 veb_flags = 0;
2746
2747         /* SEIDs need to either both be set or both be 0 for floating VEB */
2748         if (!!uplink_seid != !!downlink_seid)
2749                 return I40E_ERR_PARAM;
2750
2751         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2752
2753         cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2754         cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2755         cmd->enable_tcs = enabled_tc;
2756         if (!uplink_seid)
2757                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2758         if (default_port)
2759                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2760         else
2761                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2762
2763         /* reverse logic here: set the bitflag to disable the stats */
2764         if (!enable_stats)
2765                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2766
2767         cmd->veb_flags = CPU_TO_LE16(veb_flags);
2768
2769         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2770
2771         if (!status && veb_seid)
2772                 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2773
2774         return status;
2775 }
2776
2777 /**
2778  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2779  * @hw: pointer to the hw struct
2780  * @veb_seid: the SEID of the VEB to query
2781  * @switch_id: the uplink switch id
2782  * @floating: set to true if the VEB is floating
2783  * @statistic_index: index of the stats counter block for this VEB
2784  * @vebs_used: number of VEB's used by function
2785  * @vebs_free: total VEB's not reserved by any function
2786  * @cmd_details: pointer to command details structure or NULL
2787  *
2788  * This retrieves the parameters for a particular VEB, specified by
2789  * uplink_seid, and returns them to the caller.
2790  **/
2791 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2792                                 u16 veb_seid, u16 *switch_id,
2793                                 bool *floating, u16 *statistic_index,
2794                                 u16 *vebs_used, u16 *vebs_free,
2795                                 struct i40e_asq_cmd_details *cmd_details)
2796 {
2797         struct i40e_aq_desc desc;
2798         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2799                 (struct i40e_aqc_get_veb_parameters_completion *)
2800                 &desc.params.raw;
2801         enum i40e_status_code status;
2802
2803         if (veb_seid == 0)
2804                 return I40E_ERR_PARAM;
2805
2806         i40e_fill_default_direct_cmd_desc(&desc,
2807                                           i40e_aqc_opc_get_veb_parameters);
2808         cmd_resp->seid = CPU_TO_LE16(veb_seid);
2809
2810         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2811         if (status)
2812                 goto get_veb_exit;
2813
2814         if (switch_id)
2815                 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2816         if (statistic_index)
2817                 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2818         if (vebs_used)
2819                 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2820         if (vebs_free)
2821                 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2822         if (floating) {
2823                 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2824                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2825                         *floating = true;
2826                 else
2827                         *floating = false;
2828         }
2829
2830 get_veb_exit:
2831         return status;
2832 }
2833
2834 /**
2835  * i40e_aq_add_macvlan
2836  * @hw: pointer to the hw struct
2837  * @seid: VSI for the mac address
2838  * @mv_list: list of macvlans to be added
2839  * @count: length of the list
2840  * @cmd_details: pointer to command details structure or NULL
2841  *
2842  * Add MAC/VLAN addresses to the HW filtering
2843  **/
2844 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2845                         struct i40e_aqc_add_macvlan_element_data *mv_list,
2846                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2847 {
2848         struct i40e_aq_desc desc;
2849         struct i40e_aqc_macvlan *cmd =
2850                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2851         enum i40e_status_code status;
2852         u16 buf_size;
2853         int i;
2854
2855         if (count == 0 || !mv_list || !hw)
2856                 return I40E_ERR_PARAM;
2857
2858         buf_size = count * sizeof(*mv_list);
2859
2860         /* prep the rest of the request */
2861         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2862         cmd->num_addresses = CPU_TO_LE16(count);
2863         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2864         cmd->seid[1] = 0;
2865         cmd->seid[2] = 0;
2866
2867         for (i = 0; i < count; i++)
2868                 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
2869                         mv_list[i].flags |=
2870                             CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2871
2872         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2873         if (buf_size > I40E_AQ_LARGE_BUF)
2874                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2875
2876         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2877                                        cmd_details);
2878
2879         return status;
2880 }
2881
2882 /**
2883  * i40e_aq_remove_macvlan
2884  * @hw: pointer to the hw struct
2885  * @seid: VSI for the mac address
2886  * @mv_list: list of macvlans to be removed
2887  * @count: length of the list
2888  * @cmd_details: pointer to command details structure or NULL
2889  *
2890  * Remove MAC/VLAN addresses from the HW filtering
2891  **/
2892 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2893                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
2894                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2895 {
2896         struct i40e_aq_desc desc;
2897         struct i40e_aqc_macvlan *cmd =
2898                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2899         enum i40e_status_code status;
2900         u16 buf_size;
2901
2902         if (count == 0 || !mv_list || !hw)
2903                 return I40E_ERR_PARAM;
2904
2905         buf_size = count * sizeof(*mv_list);
2906
2907         /* prep the rest of the request */
2908         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2909         cmd->num_addresses = CPU_TO_LE16(count);
2910         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2911         cmd->seid[1] = 0;
2912         cmd->seid[2] = 0;
2913
2914         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2915         if (buf_size > I40E_AQ_LARGE_BUF)
2916                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2917
2918         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2919                                        cmd_details);
2920
2921         return status;
2922 }
2923
2924 /**
2925  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
2926  * @hw: pointer to the hw struct
2927  * @opcode: AQ opcode for add or delete mirror rule
2928  * @sw_seid: Switch SEID (to which rule refers)
2929  * @rule_type: Rule Type (ingress/egress/VLAN)
2930  * @id: Destination VSI SEID or Rule ID
2931  * @count: length of the list
2932  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2933  * @cmd_details: pointer to command details structure or NULL
2934  * @rule_id: Rule ID returned from FW
2935  * @rule_used: Number of rules used in internal switch
2936  * @rule_free: Number of rules free in internal switch
2937  *
2938  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
2939  * VEBs/VEPA elements only
2940  **/
2941 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
2942                         u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
2943                         u16 count, __le16 *mr_list,
2944                         struct i40e_asq_cmd_details *cmd_details,
2945                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
2946 {
2947         struct i40e_aq_desc desc;
2948         struct i40e_aqc_add_delete_mirror_rule *cmd =
2949                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
2950         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
2951         (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
2952         enum i40e_status_code status;
2953         u16 buf_size;
2954
2955         buf_size = count * sizeof(*mr_list);
2956
2957         /* prep the rest of the request */
2958         i40e_fill_default_direct_cmd_desc(&desc, opcode);
2959         cmd->seid = CPU_TO_LE16(sw_seid);
2960         cmd->rule_type = CPU_TO_LE16(rule_type &
2961                                      I40E_AQC_MIRROR_RULE_TYPE_MASK);
2962         cmd->num_entries = CPU_TO_LE16(count);
2963         /* Dest VSI for add, rule_id for delete */
2964         cmd->destination = CPU_TO_LE16(id);
2965         if (mr_list) {
2966                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
2967                                                 I40E_AQ_FLAG_RD));
2968                 if (buf_size > I40E_AQ_LARGE_BUF)
2969                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2970         }
2971
2972         status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
2973                                        cmd_details);
2974         if (status == I40E_SUCCESS ||
2975             hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
2976                 if (rule_id)
2977                         *rule_id = LE16_TO_CPU(resp->rule_id);
2978                 if (rules_used)
2979                         *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
2980                 if (rules_free)
2981                         *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
2982         }
2983         return status;
2984 }
2985
2986 /**
2987  * i40e_aq_add_mirrorrule - add a mirror rule
2988  * @hw: pointer to the hw struct
2989  * @sw_seid: Switch SEID (to which rule refers)
2990  * @rule_type: Rule Type (ingress/egress/VLAN)
2991  * @dest_vsi: SEID of VSI to which packets will be mirrored
2992  * @count: length of the list
2993  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2994  * @cmd_details: pointer to command details structure or NULL
2995  * @rule_id: Rule ID returned from FW
2996  * @rule_used: Number of rules used in internal switch
2997  * @rule_free: Number of rules free in internal switch
2998  *
2999  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3000  **/
3001 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3002                         u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3003                         struct i40e_asq_cmd_details *cmd_details,
3004                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3005 {
3006         if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3007             rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3008                 if (count == 0 || !mr_list)
3009                         return I40E_ERR_PARAM;
3010         }
3011
3012         return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3013                                   rule_type, dest_vsi, count, mr_list,
3014                                   cmd_details, rule_id, rules_used, rules_free);
3015 }
3016
3017 /**
3018  * i40e_aq_delete_mirrorrule - delete a mirror rule
3019  * @hw: pointer to the hw struct
3020  * @sw_seid: Switch SEID (to which rule refers)
3021  * @rule_type: Rule Type (ingress/egress/VLAN)
3022  * @count: length of the list
3023  * @rule_id: Rule ID that is returned in the receive desc as part of
3024  *              add_mirrorrule.
3025  * @mr_list: list of mirrored VLAN IDs to be removed
3026  * @cmd_details: pointer to command details structure or NULL
3027  * @rule_used: Number of rules used in internal switch
3028  * @rule_free: Number of rules free in internal switch
3029  *
3030  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3031  **/
3032 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3033                         u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3034                         struct i40e_asq_cmd_details *cmd_details,
3035                         u16 *rules_used, u16 *rules_free)
3036 {
3037         /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3038         if (rule_type != I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3039                 if (!rule_id)
3040                         return I40E_ERR_PARAM;
3041         } else {
3042                 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3043                  * mirroring. For other rule_type, count and rule_type should
3044                  * not matter.
3045                  */
3046                 if (count == 0 || !mr_list)
3047                         return I40E_ERR_PARAM;
3048         }
3049
3050         return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3051                                   rule_type, rule_id, count, mr_list,
3052                                   cmd_details, NULL, rules_used, rules_free);
3053 }
3054
3055 /**
3056  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3057  * @hw: pointer to the hw struct
3058  * @seid: VSI for the vlan filters
3059  * @v_list: list of vlan filters to be added
3060  * @count: length of the list
3061  * @cmd_details: pointer to command details structure or NULL
3062  **/
3063 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3064                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3065                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3066 {
3067         struct i40e_aq_desc desc;
3068         struct i40e_aqc_macvlan *cmd =
3069                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3070         enum i40e_status_code status;
3071         u16 buf_size;
3072
3073         if (count == 0 || !v_list || !hw)
3074                 return I40E_ERR_PARAM;
3075
3076         buf_size = count * sizeof(*v_list);
3077
3078         /* prep the rest of the request */
3079         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3080         cmd->num_addresses = CPU_TO_LE16(count);
3081         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3082         cmd->seid[1] = 0;
3083         cmd->seid[2] = 0;
3084
3085         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3086         if (buf_size > I40E_AQ_LARGE_BUF)
3087                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3088
3089         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3090                                        cmd_details);
3091
3092         return status;
3093 }
3094
3095 /**
3096  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3097  * @hw: pointer to the hw struct
3098  * @seid: VSI for the vlan filters
3099  * @v_list: list of macvlans to be removed
3100  * @count: length of the list
3101  * @cmd_details: pointer to command details structure or NULL
3102  **/
3103 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3104                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3105                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3106 {
3107         struct i40e_aq_desc desc;
3108         struct i40e_aqc_macvlan *cmd =
3109                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3110         enum i40e_status_code status;
3111         u16 buf_size;
3112
3113         if (count == 0 || !v_list || !hw)
3114                 return I40E_ERR_PARAM;
3115
3116         buf_size = count * sizeof(*v_list);
3117
3118         /* prep the rest of the request */
3119         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3120         cmd->num_addresses = CPU_TO_LE16(count);
3121         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3122         cmd->seid[1] = 0;
3123         cmd->seid[2] = 0;
3124
3125         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3126         if (buf_size > I40E_AQ_LARGE_BUF)
3127                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3128
3129         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3130                                        cmd_details);
3131
3132         return status;
3133 }
3134
3135 /**
3136  * i40e_aq_send_msg_to_vf
3137  * @hw: pointer to the hardware structure
3138  * @vfid: vf id to send msg
3139  * @v_opcode: opcodes for VF-PF communication
3140  * @v_retval: return error code
3141  * @msg: pointer to the msg buffer
3142  * @msglen: msg length
3143  * @cmd_details: pointer to command details
3144  *
3145  * send msg to vf
3146  **/
3147 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3148                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3149                                 struct i40e_asq_cmd_details *cmd_details)
3150 {
3151         struct i40e_aq_desc desc;
3152         struct i40e_aqc_pf_vf_message *cmd =
3153                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3154         enum i40e_status_code status;
3155
3156         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3157         cmd->id = CPU_TO_LE32(vfid);
3158         desc.cookie_high = CPU_TO_LE32(v_opcode);
3159         desc.cookie_low = CPU_TO_LE32(v_retval);
3160         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3161         if (msglen) {
3162                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3163                                                 I40E_AQ_FLAG_RD));
3164                 if (msglen > I40E_AQ_LARGE_BUF)
3165                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3166                 desc.datalen = CPU_TO_LE16(msglen);
3167         }
3168         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3169
3170         return status;
3171 }
3172
3173 /**
3174  * i40e_aq_debug_read_register
3175  * @hw: pointer to the hw struct
3176  * @reg_addr: register address
3177  * @reg_val: register value
3178  * @cmd_details: pointer to command details structure or NULL
3179  *
3180  * Read the register using the admin queue commands
3181  **/
3182 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3183                                 u32 reg_addr, u64 *reg_val,
3184                                 struct i40e_asq_cmd_details *cmd_details)
3185 {
3186         struct i40e_aq_desc desc;
3187         struct i40e_aqc_debug_reg_read_write *cmd_resp =
3188                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3189         enum i40e_status_code status;
3190
3191         if (reg_val == NULL)
3192                 return I40E_ERR_PARAM;
3193
3194         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3195
3196         cmd_resp->address = CPU_TO_LE32(reg_addr);
3197
3198         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3199
3200         if (status == I40E_SUCCESS) {
3201                 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3202                            (u64)LE32_TO_CPU(cmd_resp->value_low);
3203         }
3204
3205         return status;
3206 }
3207
3208 /**
3209  * i40e_aq_debug_write_register
3210  * @hw: pointer to the hw struct
3211  * @reg_addr: register address
3212  * @reg_val: register value
3213  * @cmd_details: pointer to command details structure or NULL
3214  *
3215  * Write to a register using the admin queue commands
3216  **/
3217 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3218                                 u32 reg_addr, u64 reg_val,
3219                                 struct i40e_asq_cmd_details *cmd_details)
3220 {
3221         struct i40e_aq_desc desc;
3222         struct i40e_aqc_debug_reg_read_write *cmd =
3223                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3224         enum i40e_status_code status;
3225
3226         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3227
3228         cmd->address = CPU_TO_LE32(reg_addr);
3229         cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3230         cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3231
3232         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3233
3234         return status;
3235 }
3236
3237 /**
3238  * i40e_aq_get_hmc_resource_profile
3239  * @hw: pointer to the hw struct
3240  * @profile: type of profile the HMC is to be set as
3241  * @pe_vf_enabled_count: the number of PE enabled VFs the system has
3242  * @cmd_details: pointer to command details structure or NULL
3243  *
3244  * query the HMC profile of the device.
3245  **/
3246 enum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw,
3247                                 enum i40e_aq_hmc_profile *profile,
3248                                 u8 *pe_vf_enabled_count,
3249                                 struct i40e_asq_cmd_details *cmd_details)
3250 {
3251         struct i40e_aq_desc desc;
3252         struct i40e_aq_get_set_hmc_resource_profile *resp =
3253                 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
3254         enum i40e_status_code status;
3255
3256         i40e_fill_default_direct_cmd_desc(&desc,
3257                                 i40e_aqc_opc_query_hmc_resource_profile);
3258         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3259
3260         *profile = (enum i40e_aq_hmc_profile)(resp->pm_profile &
3261                    I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK);
3262         *pe_vf_enabled_count = resp->pe_vf_enabled &
3263                                I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK;
3264
3265         return status;
3266 }
3267
3268 /**
3269  * i40e_aq_set_hmc_resource_profile
3270  * @hw: pointer to the hw struct
3271  * @profile: type of profile the HMC is to be set as
3272  * @pe_vf_enabled_count: the number of PE enabled VFs the system has
3273  * @cmd_details: pointer to command details structure or NULL
3274  *
3275  * set the HMC profile of the device.
3276  **/
3277 enum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
3278                                 enum i40e_aq_hmc_profile profile,
3279                                 u8 pe_vf_enabled_count,
3280                                 struct i40e_asq_cmd_details *cmd_details)
3281 {
3282         struct i40e_aq_desc desc;
3283         struct i40e_aq_get_set_hmc_resource_profile *cmd =
3284                 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
3285         enum i40e_status_code status;
3286
3287         i40e_fill_default_direct_cmd_desc(&desc,
3288                                         i40e_aqc_opc_set_hmc_resource_profile);
3289
3290         cmd->pm_profile = (u8)profile;
3291         cmd->pe_vf_enabled = pe_vf_enabled_count;
3292
3293         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3294
3295         return status;
3296 }
3297
3298 /**
3299  * i40e_aq_request_resource
3300  * @hw: pointer to the hw struct
3301  * @resource: resource id
3302  * @access: access type
3303  * @sdp_number: resource number
3304  * @timeout: the maximum time in ms that the driver may hold the resource
3305  * @cmd_details: pointer to command details structure or NULL
3306  *
3307  * requests common resource using the admin queue commands
3308  **/
3309 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3310                                 enum i40e_aq_resources_ids resource,
3311                                 enum i40e_aq_resource_access_type access,
3312                                 u8 sdp_number, u64 *timeout,
3313                                 struct i40e_asq_cmd_details *cmd_details)
3314 {
3315         struct i40e_aq_desc desc;
3316         struct i40e_aqc_request_resource *cmd_resp =
3317                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3318         enum i40e_status_code status;
3319
3320         DEBUGFUNC("i40e_aq_request_resource");
3321
3322         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3323
3324         cmd_resp->resource_id = CPU_TO_LE16(resource);
3325         cmd_resp->access_type = CPU_TO_LE16(access);
3326         cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3327
3328         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3329         /* The completion specifies the maximum time in ms that the driver
3330          * may hold the resource in the Timeout field.
3331          * If the resource is held by someone else, the command completes with
3332          * busy return value and the timeout field indicates the maximum time
3333          * the current owner of the resource has to free it.
3334          */
3335         if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3336                 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3337
3338         return status;
3339 }
3340
3341 /**
3342  * i40e_aq_release_resource
3343  * @hw: pointer to the hw struct
3344  * @resource: resource id
3345  * @sdp_number: resource number
3346  * @cmd_details: pointer to command details structure or NULL
3347  *
3348  * release common resource using the admin queue commands
3349  **/
3350 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3351                                 enum i40e_aq_resources_ids resource,
3352                                 u8 sdp_number,
3353                                 struct i40e_asq_cmd_details *cmd_details)
3354 {
3355         struct i40e_aq_desc desc;
3356         struct i40e_aqc_request_resource *cmd =
3357                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3358         enum i40e_status_code status;
3359
3360         DEBUGFUNC("i40e_aq_release_resource");
3361
3362         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3363
3364         cmd->resource_id = CPU_TO_LE16(resource);
3365         cmd->resource_number = CPU_TO_LE32(sdp_number);
3366
3367         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3368
3369         return status;
3370 }
3371
3372 /**
3373  * i40e_aq_read_nvm
3374  * @hw: pointer to the hw struct
3375  * @module_pointer: module pointer location in words from the NVM beginning
3376  * @offset: byte offset from the module beginning
3377  * @length: length of the section to be read (in bytes from the offset)
3378  * @data: command buffer (size [bytes] = length)
3379  * @last_command: tells if this is the last command in a series
3380  * @cmd_details: pointer to command details structure or NULL
3381  *
3382  * Read the NVM using the admin queue commands
3383  **/
3384 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3385                                 u32 offset, u16 length, void *data,
3386                                 bool last_command,
3387                                 struct i40e_asq_cmd_details *cmd_details)
3388 {
3389         struct i40e_aq_desc desc;
3390         struct i40e_aqc_nvm_update *cmd =
3391                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3392         enum i40e_status_code status;
3393
3394         DEBUGFUNC("i40e_aq_read_nvm");
3395
3396         /* In offset the highest byte must be zeroed. */
3397         if (offset & 0xFF000000) {
3398                 status = I40E_ERR_PARAM;
3399                 goto i40e_aq_read_nvm_exit;
3400         }
3401
3402         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3403
3404         /* If this is the last command in a series, set the proper flag. */
3405         if (last_command)
3406                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3407         cmd->module_pointer = module_pointer;
3408         cmd->offset = CPU_TO_LE32(offset);
3409         cmd->length = CPU_TO_LE16(length);
3410
3411         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3412         if (length > I40E_AQ_LARGE_BUF)
3413                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3414
3415         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3416
3417 i40e_aq_read_nvm_exit:
3418         return status;
3419 }
3420
3421 /**
3422  * i40e_aq_read_nvm_config - read an nvm config block
3423  * @hw: pointer to the hw struct
3424  * @cmd_flags: NVM access admin command bits
3425  * @field_id: field or feature id
3426  * @data: buffer for result
3427  * @buf_size: buffer size
3428  * @element_count: pointer to count of elements read by FW
3429  * @cmd_details: pointer to command details structure or NULL
3430  **/
3431 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3432                                 u8 cmd_flags, u32 field_id, void *data,
3433                                 u16 buf_size, u16 *element_count,
3434                                 struct i40e_asq_cmd_details *cmd_details)
3435 {
3436         struct i40e_aq_desc desc;
3437         struct i40e_aqc_nvm_config_read *cmd =
3438                 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3439         enum i40e_status_code status;
3440
3441         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3442         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3443         if (buf_size > I40E_AQ_LARGE_BUF)
3444                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3445
3446         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3447         cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3448         if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3449                 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3450         else
3451                 cmd->element_id_msw = 0;
3452
3453         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3454
3455         if (!status && element_count)
3456                 *element_count = LE16_TO_CPU(cmd->element_count);
3457
3458         return status;
3459 }
3460
3461 /**
3462  * i40e_aq_write_nvm_config - write an nvm config block
3463  * @hw: pointer to the hw struct
3464  * @cmd_flags: NVM access admin command bits
3465  * @data: buffer for result
3466  * @buf_size: buffer size
3467  * @element_count: count of elements to be written
3468  * @cmd_details: pointer to command details structure or NULL
3469  **/
3470 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3471                                 u8 cmd_flags, void *data, u16 buf_size,
3472                                 u16 element_count,
3473                                 struct i40e_asq_cmd_details *cmd_details)
3474 {
3475         struct i40e_aq_desc desc;
3476         struct i40e_aqc_nvm_config_write *cmd =
3477                 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3478         enum i40e_status_code status;
3479
3480         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3481         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3482         if (buf_size > I40E_AQ_LARGE_BUF)
3483                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3484
3485         cmd->element_count = CPU_TO_LE16(element_count);
3486         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3487         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3488
3489         return status;
3490 }
3491
3492 /**
3493  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3494  * @hw: pointer to the hw struct
3495  * @cmd_details: pointer to command details structure or NULL
3496  **/
3497 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3498                                 void *buff, u16 buff_size,
3499                                 struct i40e_asq_cmd_details *cmd_details)
3500 {
3501         struct i40e_aq_desc desc;
3502         enum i40e_status_code status;
3503
3504         UNREFERENCED_2PARAMETER(buff, buff_size);
3505
3506         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3507         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3508         if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3509                 status = I40E_ERR_NOT_IMPLEMENTED;
3510
3511         return status;
3512 }
3513
3514 /**
3515  * i40e_aq_erase_nvm
3516  * @hw: pointer to the hw struct
3517  * @module_pointer: module pointer location in words from the NVM beginning
3518  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3519  * @length: length of the section to be erased (expressed in 4 KB)
3520  * @last_command: tells if this is the last command in a series
3521  * @cmd_details: pointer to command details structure or NULL
3522  *
3523  * Erase the NVM sector using the admin queue commands
3524  **/
3525 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3526                                 u32 offset, u16 length, bool last_command,
3527                                 struct i40e_asq_cmd_details *cmd_details)
3528 {
3529         struct i40e_aq_desc desc;
3530         struct i40e_aqc_nvm_update *cmd =
3531                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3532         enum i40e_status_code status;
3533
3534         DEBUGFUNC("i40e_aq_erase_nvm");
3535
3536         /* In offset the highest byte must be zeroed. */
3537         if (offset & 0xFF000000) {
3538                 status = I40E_ERR_PARAM;
3539                 goto i40e_aq_erase_nvm_exit;
3540         }
3541
3542         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3543
3544         /* If this is the last command in a series, set the proper flag. */
3545         if (last_command)
3546                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3547         cmd->module_pointer = module_pointer;
3548         cmd->offset = CPU_TO_LE32(offset);
3549         cmd->length = CPU_TO_LE16(length);
3550
3551         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3552
3553 i40e_aq_erase_nvm_exit:
3554         return status;
3555 }
3556
3557 /**
3558  * i40e_parse_discover_capabilities
3559  * @hw: pointer to the hw struct
3560  * @buff: pointer to a buffer containing device/function capability records
3561  * @cap_count: number of capability records in the list
3562  * @list_type_opc: type of capabilities list to parse
3563  *
3564  * Parse the device/function capabilities list.
3565  **/
3566 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3567                                      u32 cap_count,
3568                                      enum i40e_admin_queue_opc list_type_opc)
3569 {
3570         struct i40e_aqc_list_capabilities_element_resp *cap;
3571         u32 valid_functions, num_functions;
3572         u32 number, logical_id, phys_id;
3573         struct i40e_hw_capabilities *p;
3574         u8 major_rev;
3575         u32 i = 0;
3576         u16 id;
3577
3578         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3579
3580         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3581                 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3582         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3583                 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3584         else
3585                 return;
3586
3587         for (i = 0; i < cap_count; i++, cap++) {
3588                 id = LE16_TO_CPU(cap->id);
3589                 number = LE32_TO_CPU(cap->number);
3590                 logical_id = LE32_TO_CPU(cap->logical_id);
3591                 phys_id = LE32_TO_CPU(cap->phys_id);
3592                 major_rev = cap->major_rev;
3593
3594                 switch (id) {
3595                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3596                         p->switch_mode = number;
3597                         i40e_debug(hw, I40E_DEBUG_INIT,
3598                                    "HW Capability: Switch mode = %d\n",
3599                                    p->switch_mode);
3600                         break;
3601                 case I40E_AQ_CAP_ID_MNG_MODE:
3602                         p->management_mode = number;
3603                         i40e_debug(hw, I40E_DEBUG_INIT,
3604                                    "HW Capability: Management Mode = %d\n",
3605                                    p->management_mode);
3606                         break;
3607                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3608                         p->npar_enable = number;
3609                         i40e_debug(hw, I40E_DEBUG_INIT,
3610                                    "HW Capability: NPAR enable = %d\n",
3611                                    p->npar_enable);
3612                         break;
3613                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3614                         p->os2bmc = number;
3615                         i40e_debug(hw, I40E_DEBUG_INIT,
3616                                    "HW Capability: OS2BMC = %d\n", p->os2bmc);
3617                         break;
3618                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3619                         p->valid_functions = number;
3620                         i40e_debug(hw, I40E_DEBUG_INIT,
3621                                    "HW Capability: Valid Functions = %d\n",
3622                                    p->valid_functions);
3623                         break;
3624                 case I40E_AQ_CAP_ID_SRIOV:
3625                         if (number == 1)
3626                                 p->sr_iov_1_1 = true;
3627                         i40e_debug(hw, I40E_DEBUG_INIT,
3628                                    "HW Capability: SR-IOV = %d\n",
3629                                    p->sr_iov_1_1);
3630                         break;
3631                 case I40E_AQ_CAP_ID_VF:
3632                         p->num_vfs = number;
3633                         p->vf_base_id = logical_id;
3634                         i40e_debug(hw, I40E_DEBUG_INIT,
3635                                    "HW Capability: VF count = %d\n",
3636                                    p->num_vfs);
3637                         i40e_debug(hw, I40E_DEBUG_INIT,
3638                                    "HW Capability: VF base_id = %d\n",
3639                                    p->vf_base_id);
3640                         break;
3641                 case I40E_AQ_CAP_ID_VMDQ:
3642                         if (number == 1)
3643                                 p->vmdq = true;
3644                         i40e_debug(hw, I40E_DEBUG_INIT,
3645                                    "HW Capability: VMDQ = %d\n", p->vmdq);
3646                         break;
3647                 case I40E_AQ_CAP_ID_8021QBG:
3648                         if (number == 1)
3649                                 p->evb_802_1_qbg = true;
3650                         i40e_debug(hw, I40E_DEBUG_INIT,
3651                                    "HW Capability: 802.1Qbg = %d\n", number);
3652                         break;
3653                 case I40E_AQ_CAP_ID_8021QBR:
3654                         if (number == 1)
3655                                 p->evb_802_1_qbh = true;
3656                         i40e_debug(hw, I40E_DEBUG_INIT,
3657                                    "HW Capability: 802.1Qbh = %d\n", number);
3658                         break;
3659                 case I40E_AQ_CAP_ID_VSI:
3660                         p->num_vsis = number;
3661                         i40e_debug(hw, I40E_DEBUG_INIT,
3662                                    "HW Capability: VSI count = %d\n",
3663                                    p->num_vsis);
3664                         break;
3665                 case I40E_AQ_CAP_ID_DCB:
3666                         if (number == 1) {
3667                                 p->dcb = true;
3668                                 p->enabled_tcmap = logical_id;
3669                                 p->maxtc = phys_id;
3670                         }
3671                         i40e_debug(hw, I40E_DEBUG_INIT,
3672                                    "HW Capability: DCB = %d\n", p->dcb);
3673                         i40e_debug(hw, I40E_DEBUG_INIT,
3674                                    "HW Capability: TC Mapping = %d\n",
3675                                    logical_id);
3676                         i40e_debug(hw, I40E_DEBUG_INIT,
3677                                    "HW Capability: TC Max = %d\n", p->maxtc);
3678                         break;
3679                 case I40E_AQ_CAP_ID_FCOE:
3680                         if (number == 1)
3681                                 p->fcoe = true;
3682                         i40e_debug(hw, I40E_DEBUG_INIT,
3683                                    "HW Capability: FCOE = %d\n", p->fcoe);
3684                         break;
3685                 case I40E_AQ_CAP_ID_ISCSI:
3686                         if (number == 1)
3687                                 p->iscsi = true;
3688                         i40e_debug(hw, I40E_DEBUG_INIT,
3689                                    "HW Capability: iSCSI = %d\n", p->iscsi);
3690                         break;
3691                 case I40E_AQ_CAP_ID_RSS:
3692                         p->rss = true;
3693                         p->rss_table_size = number;
3694                         p->rss_table_entry_width = logical_id;
3695                         i40e_debug(hw, I40E_DEBUG_INIT,
3696                                    "HW Capability: RSS = %d\n", p->rss);
3697                         i40e_debug(hw, I40E_DEBUG_INIT,
3698                                    "HW Capability: RSS table size = %d\n",
3699                                    p->rss_table_size);
3700                         i40e_debug(hw, I40E_DEBUG_INIT,
3701                                    "HW Capability: RSS table width = %d\n",
3702                                    p->rss_table_entry_width);
3703                         break;
3704                 case I40E_AQ_CAP_ID_RXQ:
3705                         p->num_rx_qp = number;
3706                         p->base_queue = phys_id;
3707                         i40e_debug(hw, I40E_DEBUG_INIT,
3708                                    "HW Capability: Rx QP = %d\n", number);
3709                         i40e_debug(hw, I40E_DEBUG_INIT,
3710                                    "HW Capability: base_queue = %d\n",
3711                                    p->base_queue);
3712                         break;
3713                 case I40E_AQ_CAP_ID_TXQ:
3714                         p->num_tx_qp = number;
3715                         p->base_queue = phys_id;
3716                         i40e_debug(hw, I40E_DEBUG_INIT,
3717                                    "HW Capability: Tx QP = %d\n", number);
3718                         i40e_debug(hw, I40E_DEBUG_INIT,
3719                                    "HW Capability: base_queue = %d\n",
3720                                    p->base_queue);
3721                         break;
3722                 case I40E_AQ_CAP_ID_MSIX:
3723                         p->num_msix_vectors = number;
3724                         i40e_debug(hw, I40E_DEBUG_INIT,
3725                                    "HW Capability: MSIX vector count = %d\n",
3726                                    p->num_msix_vectors_vf);
3727                         break;
3728                 case I40E_AQ_CAP_ID_VF_MSIX:
3729                         p->num_msix_vectors_vf = number;
3730                         i40e_debug(hw, I40E_DEBUG_INIT,
3731                                    "HW Capability: MSIX VF vector count = %d\n",
3732                                    p->num_msix_vectors_vf);
3733                         break;
3734                 case I40E_AQ_CAP_ID_FLEX10:
3735                         if (major_rev == 1) {
3736                                 if (number == 1) {
3737                                         p->flex10_enable = true;
3738                                         p->flex10_capable = true;
3739                                 }
3740                         } else {
3741                                 /* Capability revision >= 2 */
3742                                 if (number & 1)
3743                                         p->flex10_enable = true;
3744                                 if (number & 2)
3745                                         p->flex10_capable = true;
3746                         }
3747                         p->flex10_mode = logical_id;
3748                         p->flex10_status = phys_id;
3749                         i40e_debug(hw, I40E_DEBUG_INIT,
3750                                    "HW Capability: Flex10 mode = %d\n",
3751                                    p->flex10_mode);
3752                         i40e_debug(hw, I40E_DEBUG_INIT,
3753                                    "HW Capability: Flex10 status = %d\n",
3754                                    p->flex10_status);
3755                         break;
3756                 case I40E_AQ_CAP_ID_CEM:
3757                         if (number == 1)
3758                                 p->mgmt_cem = true;
3759                         i40e_debug(hw, I40E_DEBUG_INIT,
3760                                    "HW Capability: CEM = %d\n", p->mgmt_cem);
3761                         break;
3762                 case I40E_AQ_CAP_ID_IWARP:
3763                         if (number == 1)
3764                                 p->iwarp = true;
3765                         i40e_debug(hw, I40E_DEBUG_INIT,
3766                                    "HW Capability: iWARP = %d\n", p->iwarp);
3767                         break;
3768                 case I40E_AQ_CAP_ID_LED:
3769                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3770                                 p->led[phys_id] = true;
3771                         i40e_debug(hw, I40E_DEBUG_INIT,
3772                                    "HW Capability: LED - PIN %d\n", phys_id);
3773                         break;
3774                 case I40E_AQ_CAP_ID_SDP:
3775                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3776                                 p->sdp[phys_id] = true;
3777                         i40e_debug(hw, I40E_DEBUG_INIT,
3778                                    "HW Capability: SDP - PIN %d\n", phys_id);
3779                         break;
3780                 case I40E_AQ_CAP_ID_MDIO:
3781                         if (number == 1) {
3782                                 p->mdio_port_num = phys_id;
3783                                 p->mdio_port_mode = logical_id;
3784                         }
3785                         i40e_debug(hw, I40E_DEBUG_INIT,
3786                                    "HW Capability: MDIO port number = %d\n",
3787                                    p->mdio_port_num);
3788                         i40e_debug(hw, I40E_DEBUG_INIT,
3789                                    "HW Capability: MDIO port mode = %d\n",
3790                                    p->mdio_port_mode);
3791                         break;
3792                 case I40E_AQ_CAP_ID_1588:
3793                         if (number == 1)
3794                                 p->ieee_1588 = true;
3795                         i40e_debug(hw, I40E_DEBUG_INIT,
3796                                    "HW Capability: IEEE 1588 = %d\n",
3797                                    p->ieee_1588);
3798                         break;
3799                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3800                         p->fd = true;
3801                         p->fd_filters_guaranteed = number;
3802                         p->fd_filters_best_effort = logical_id;
3803                         i40e_debug(hw, I40E_DEBUG_INIT,
3804                                    "HW Capability: Flow Director = 1\n");
3805                         i40e_debug(hw, I40E_DEBUG_INIT,
3806                                    "HW Capability: Guaranteed FD filters = %d\n",
3807                                    p->fd_filters_guaranteed);
3808                         break;
3809                 case I40E_AQ_CAP_ID_WSR_PROT:
3810                         p->wr_csr_prot = (u64)number;
3811                         p->wr_csr_prot |= (u64)logical_id << 32;
3812                         i40e_debug(hw, I40E_DEBUG_INIT,
3813                                    "HW Capability: wr_csr_prot = 0x%llX\n\n",
3814                                    (p->wr_csr_prot & 0xffff));
3815                         break;
3816 #ifdef X722_SUPPORT
3817                 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3818                         hw->num_wol_proxy_filters = (u16)number;
3819                         hw->wol_proxy_vsi_seid = (u16)logical_id;
3820                         p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3821                         if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3822                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3823                         else
3824                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3825                         p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3826                         p->proxy_support = p->proxy_support;
3827                         i40e_debug(hw, I40E_DEBUG_INIT,
3828                                    "HW Capability: WOL proxy filters = %d\n",
3829                                    hw->num_wol_proxy_filters);
3830                         break;
3831 #endif
3832                 default:
3833                         break;
3834                 }
3835         }
3836
3837         if (p->fcoe)
3838                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3839
3840 #ifdef I40E_FCOE_ENA
3841         /* Software override ensuring FCoE is disabled if npar or mfp
3842          * mode because it is not supported in these modes.
3843          */
3844         if (p->npar_enable || p->flex10_enable)
3845                 p->fcoe = false;
3846 #else
3847         /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3848         p->fcoe = false;
3849 #endif
3850
3851         /* count the enabled ports (aka the "not disabled" ports) */
3852         hw->num_ports = 0;
3853         for (i = 0; i < 4; i++) {
3854                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3855                 u64 port_cfg = 0;
3856
3857                 /* use AQ read to get the physical register offset instead
3858                  * of the port relative offset
3859                  */
3860                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3861                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3862                         hw->num_ports++;
3863         }
3864
3865         valid_functions = p->valid_functions;
3866         num_functions = 0;
3867         while (valid_functions) {
3868                 if (valid_functions & 1)
3869                         num_functions++;
3870                 valid_functions >>= 1;
3871         }
3872
3873         /* partition id is 1-based, and functions are evenly spread
3874          * across the ports as partitions
3875          */
3876         hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3877         hw->num_partitions = num_functions / hw->num_ports;
3878
3879         /* additional HW specific goodies that might
3880          * someday be HW version specific
3881          */
3882         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3883 }
3884
3885 /**
3886  * i40e_aq_discover_capabilities
3887  * @hw: pointer to the hw struct
3888  * @buff: a virtual buffer to hold the capabilities
3889  * @buff_size: Size of the virtual buffer
3890  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3891  * @list_type_opc: capabilities type to discover - pass in the command opcode
3892  * @cmd_details: pointer to command details structure or NULL
3893  *
3894  * Get the device capabilities descriptions from the firmware
3895  **/
3896 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3897                                 void *buff, u16 buff_size, u16 *data_size,
3898                                 enum i40e_admin_queue_opc list_type_opc,
3899                                 struct i40e_asq_cmd_details *cmd_details)
3900 {
3901         struct i40e_aqc_list_capabilites *cmd;
3902         struct i40e_aq_desc desc;
3903         enum i40e_status_code status = I40E_SUCCESS;
3904
3905         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3906
3907         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3908                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3909                 status = I40E_ERR_PARAM;
3910                 goto exit;
3911         }
3912
3913         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3914
3915         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3916         if (buff_size > I40E_AQ_LARGE_BUF)
3917                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3918
3919         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3920         *data_size = LE16_TO_CPU(desc.datalen);
3921
3922         if (status)
3923                 goto exit;
3924
3925         i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3926                                          list_type_opc);
3927
3928 exit:
3929         return status;
3930 }
3931
3932 /**
3933  * i40e_aq_update_nvm
3934  * @hw: pointer to the hw struct
3935  * @module_pointer: module pointer location in words from the NVM beginning
3936  * @offset: byte offset from the module beginning
3937  * @length: length of the section to be written (in bytes from the offset)
3938  * @data: command buffer (size [bytes] = length)
3939  * @last_command: tells if this is the last command in a series
3940  * @cmd_details: pointer to command details structure or NULL
3941  *
3942  * Update the NVM using the admin queue commands
3943  **/
3944 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3945                                 u32 offset, u16 length, void *data,
3946                                 bool last_command,
3947                                 struct i40e_asq_cmd_details *cmd_details)
3948 {
3949         struct i40e_aq_desc desc;
3950         struct i40e_aqc_nvm_update *cmd =
3951                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3952         enum i40e_status_code status;
3953
3954         DEBUGFUNC("i40e_aq_update_nvm");
3955
3956         /* In offset the highest byte must be zeroed. */
3957         if (offset & 0xFF000000) {
3958                 status = I40E_ERR_PARAM;
3959                 goto i40e_aq_update_nvm_exit;
3960         }
3961
3962         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3963
3964         /* If this is the last command in a series, set the proper flag. */
3965         if (last_command)
3966                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3967         cmd->module_pointer = module_pointer;
3968         cmd->offset = CPU_TO_LE32(offset);
3969         cmd->length = CPU_TO_LE16(length);
3970
3971         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3972         if (length > I40E_AQ_LARGE_BUF)
3973                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3974
3975         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3976
3977 i40e_aq_update_nvm_exit:
3978         return status;
3979 }
3980
3981 /**
3982  * i40e_aq_get_lldp_mib
3983  * @hw: pointer to the hw struct
3984  * @bridge_type: type of bridge requested
3985  * @mib_type: Local, Remote or both Local and Remote MIBs
3986  * @buff: pointer to a user supplied buffer to store the MIB block
3987  * @buff_size: size of the buffer (in bytes)
3988  * @local_len : length of the returned Local LLDP MIB
3989  * @remote_len: length of the returned Remote LLDP MIB
3990  * @cmd_details: pointer to command details structure or NULL
3991  *
3992  * Requests the complete LLDP MIB (entire packet).
3993  **/
3994 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3995                                 u8 mib_type, void *buff, u16 buff_size,
3996                                 u16 *local_len, u16 *remote_len,
3997                                 struct i40e_asq_cmd_details *cmd_details)
3998 {
3999         struct i40e_aq_desc desc;
4000         struct i40e_aqc_lldp_get_mib *cmd =
4001                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4002         struct i40e_aqc_lldp_get_mib *resp =
4003                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4004         enum i40e_status_code status;
4005
4006         if (buff_size == 0 || !buff)
4007                 return I40E_ERR_PARAM;
4008
4009         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4010         /* Indirect Command */
4011         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4012
4013         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4014         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4015                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4016
4017         desc.datalen = CPU_TO_LE16(buff_size);
4018
4019         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4020         if (buff_size > I40E_AQ_LARGE_BUF)
4021                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4022
4023         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4024         if (!status) {
4025                 if (local_len != NULL)
4026                         *local_len = LE16_TO_CPU(resp->local_len);
4027                 if (remote_len != NULL)
4028                         *remote_len = LE16_TO_CPU(resp->remote_len);
4029         }
4030
4031         return status;
4032 }
4033
4034  /**
4035  * i40e_aq_set_lldp_mib - Set the LLDP MIB
4036  * @hw: pointer to the hw struct
4037  * @mib_type: Local, Remote or both Local and Remote MIBs
4038  * @buff: pointer to a user supplied buffer to store the MIB block
4039  * @buff_size: size of the buffer (in bytes)
4040  * @cmd_details: pointer to command details structure or NULL
4041  *
4042  * Set the LLDP MIB.
4043  **/
4044 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4045                                 u8 mib_type, void *buff, u16 buff_size,
4046                                 struct i40e_asq_cmd_details *cmd_details)
4047 {
4048         struct i40e_aq_desc desc;
4049         struct i40e_aqc_lldp_set_local_mib *cmd =
4050                 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4051         enum i40e_status_code status;
4052
4053         if (buff_size == 0 || !buff)
4054                 return I40E_ERR_PARAM;
4055
4056         i40e_fill_default_direct_cmd_desc(&desc,
4057                                 i40e_aqc_opc_lldp_set_local_mib);
4058         /* Indirect Command */
4059         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4060         if (buff_size > I40E_AQ_LARGE_BUF)
4061                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4062         desc.datalen = CPU_TO_LE16(buff_size);
4063
4064         cmd->type = mib_type;
4065         cmd->length = CPU_TO_LE16(buff_size);
4066         cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4067         cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4068
4069         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4070         return status;
4071 }
4072
4073 /**
4074  * i40e_aq_cfg_lldp_mib_change_event
4075  * @hw: pointer to the hw struct
4076  * @enable_update: Enable or Disable event posting
4077  * @cmd_details: pointer to command details structure or NULL
4078  *
4079  * Enable or Disable posting of an event on ARQ when LLDP MIB
4080  * associated with the interface changes
4081  **/
4082 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4083                                 bool enable_update,
4084                                 struct i40e_asq_cmd_details *cmd_details)
4085 {
4086         struct i40e_aq_desc desc;
4087         struct i40e_aqc_lldp_update_mib *cmd =
4088                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4089         enum i40e_status_code status;
4090
4091         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4092
4093         if (!enable_update)
4094                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4095
4096         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4097
4098         return status;
4099 }
4100
4101 /**
4102  * i40e_aq_add_lldp_tlv
4103  * @hw: pointer to the hw struct
4104  * @bridge_type: type of bridge
4105  * @buff: buffer with TLV to add
4106  * @buff_size: length of the buffer
4107  * @tlv_len: length of the TLV to be added
4108  * @mib_len: length of the LLDP MIB returned in response
4109  * @cmd_details: pointer to command details structure or NULL
4110  *
4111  * Add the specified TLV to LLDP Local MIB for the given bridge type,
4112  * it is responsibility of the caller to make sure that the TLV is not
4113  * already present in the LLDPDU.
4114  * In return firmware will write the complete LLDP MIB with the newly
4115  * added TLV in the response buffer.
4116  **/
4117 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4118                                 void *buff, u16 buff_size, u16 tlv_len,
4119                                 u16 *mib_len,
4120                                 struct i40e_asq_cmd_details *cmd_details)
4121 {
4122         struct i40e_aq_desc desc;
4123         struct i40e_aqc_lldp_add_tlv *cmd =
4124                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4125         enum i40e_status_code status;
4126
4127         if (buff_size == 0 || !buff || tlv_len == 0)
4128                 return I40E_ERR_PARAM;
4129
4130         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4131
4132         /* Indirect Command */
4133         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4134         if (buff_size > I40E_AQ_LARGE_BUF)
4135                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4136         desc.datalen = CPU_TO_LE16(buff_size);
4137
4138         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4139                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4140         cmd->len = CPU_TO_LE16(tlv_len);
4141
4142         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4143         if (!status) {
4144                 if (mib_len != NULL)
4145                         *mib_len = LE16_TO_CPU(desc.datalen);
4146         }
4147
4148         return status;
4149 }
4150
4151 /**
4152  * i40e_aq_update_lldp_tlv
4153  * @hw: pointer to the hw struct
4154  * @bridge_type: type of bridge
4155  * @buff: buffer with TLV to update
4156  * @buff_size: size of the buffer holding original and updated TLVs
4157  * @old_len: Length of the Original TLV
4158  * @new_len: Length of the Updated TLV
4159  * @offset: offset of the updated TLV in the buff
4160  * @mib_len: length of the returned LLDP MIB
4161  * @cmd_details: pointer to command details structure or NULL
4162  *
4163  * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4164  * Firmware will place the complete LLDP MIB in response buffer with the
4165  * updated TLV.
4166  **/
4167 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4168                                 u8 bridge_type, void *buff, u16 buff_size,
4169                                 u16 old_len, u16 new_len, u16 offset,
4170                                 u16 *mib_len,
4171                                 struct i40e_asq_cmd_details *cmd_details)
4172 {
4173         struct i40e_aq_desc desc;
4174         struct i40e_aqc_lldp_update_tlv *cmd =
4175                 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4176         enum i40e_status_code status;
4177
4178         if (buff_size == 0 || !buff || offset == 0 ||
4179             old_len == 0 || new_len == 0)
4180                 return I40E_ERR_PARAM;
4181
4182         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4183
4184         /* Indirect Command */
4185         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4186         if (buff_size > I40E_AQ_LARGE_BUF)
4187                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4188         desc.datalen = CPU_TO_LE16(buff_size);
4189
4190         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4191                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4192         cmd->old_len = CPU_TO_LE16(old_len);
4193         cmd->new_offset = CPU_TO_LE16(offset);
4194         cmd->new_len = CPU_TO_LE16(new_len);
4195
4196         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4197         if (!status) {
4198                 if (mib_len != NULL)
4199                         *mib_len = LE16_TO_CPU(desc.datalen);
4200         }
4201
4202         return status;
4203 }
4204
4205 /**
4206  * i40e_aq_delete_lldp_tlv
4207  * @hw: pointer to the hw struct
4208  * @bridge_type: type of bridge
4209  * @buff: pointer to a user supplied buffer that has the TLV
4210  * @buff_size: length of the buffer
4211  * @tlv_len: length of the TLV to be deleted
4212  * @mib_len: length of the returned LLDP MIB
4213  * @cmd_details: pointer to command details structure or NULL
4214  *
4215  * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4216  * The firmware places the entire LLDP MIB in the response buffer.
4217  **/
4218 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4219                                 u8 bridge_type, void *buff, u16 buff_size,
4220                                 u16 tlv_len, u16 *mib_len,
4221                                 struct i40e_asq_cmd_details *cmd_details)
4222 {
4223         struct i40e_aq_desc desc;
4224         struct i40e_aqc_lldp_add_tlv *cmd =
4225                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4226         enum i40e_status_code status;
4227
4228         if (buff_size == 0 || !buff)
4229                 return I40E_ERR_PARAM;
4230
4231         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4232
4233         /* Indirect Command */
4234         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4235         if (buff_size > I40E_AQ_LARGE_BUF)
4236                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4237         desc.datalen = CPU_TO_LE16(buff_size);
4238         cmd->len = CPU_TO_LE16(tlv_len);
4239         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4240                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4241
4242         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4243         if (!status) {
4244                 if (mib_len != NULL)
4245                         *mib_len = LE16_TO_CPU(desc.datalen);
4246         }
4247
4248         return status;
4249 }
4250
4251 /**
4252  * i40e_aq_stop_lldp
4253  * @hw: pointer to the hw struct
4254  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4255  * @cmd_details: pointer to command details structure or NULL
4256  *
4257  * Stop or Shutdown the embedded LLDP Agent
4258  **/
4259 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4260                                 struct i40e_asq_cmd_details *cmd_details)
4261 {
4262         struct i40e_aq_desc desc;
4263         struct i40e_aqc_lldp_stop *cmd =
4264                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4265         enum i40e_status_code status;
4266
4267         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4268
4269         if (shutdown_agent)
4270                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4271
4272         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4273
4274         return status;
4275 }
4276
4277 /**
4278  * i40e_aq_start_lldp
4279  * @hw: pointer to the hw struct
4280  * @cmd_details: pointer to command details structure or NULL
4281  *
4282  * Start the embedded LLDP Agent on all ports.
4283  **/
4284 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4285                                 struct i40e_asq_cmd_details *cmd_details)
4286 {
4287         struct i40e_aq_desc desc;
4288         struct i40e_aqc_lldp_start *cmd =
4289                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4290         enum i40e_status_code status;
4291
4292         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4293
4294         cmd->command = I40E_AQ_LLDP_AGENT_START;
4295
4296         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4297
4298         return status;
4299 }
4300
4301 /**
4302  * i40e_aq_get_cee_dcb_config
4303  * @hw: pointer to the hw struct
4304  * @buff: response buffer that stores CEE operational configuration
4305  * @buff_size: size of the buffer passed
4306  * @cmd_details: pointer to command details structure or NULL
4307  *
4308  * Get CEE DCBX mode operational configuration from firmware
4309  **/
4310 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4311                                 void *buff, u16 buff_size,
4312                                 struct i40e_asq_cmd_details *cmd_details)
4313 {
4314         struct i40e_aq_desc desc;
4315         enum i40e_status_code status;
4316
4317         if (buff_size == 0 || !buff)
4318                 return I40E_ERR_PARAM;
4319
4320         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4321
4322         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4323         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4324                                        cmd_details);
4325
4326         return status;
4327 }
4328
4329 /**
4330  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4331  * @hw: pointer to the hw struct
4332  * @start_agent: True if DCBx Agent needs to be Started
4333  *                              False if DCBx Agent needs to be Stopped
4334  * @cmd_details: pointer to command details structure or NULL
4335  *
4336  * Start/Stop the embedded dcbx Agent
4337  **/
4338 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4339                                 bool start_agent,
4340                                 struct i40e_asq_cmd_details *cmd_details)
4341 {
4342         struct i40e_aq_desc desc;
4343         struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4344                 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4345                                 &desc.params.raw;
4346         enum i40e_status_code status;
4347
4348         i40e_fill_default_direct_cmd_desc(&desc,
4349                                 i40e_aqc_opc_lldp_stop_start_spec_agent);
4350
4351         if (start_agent)
4352                 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4353
4354         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4355
4356         return status;
4357 }
4358
4359 /**
4360  * i40e_aq_add_udp_tunnel
4361  * @hw: pointer to the hw struct
4362  * @udp_port: the UDP port to add
4363  * @header_len: length of the tunneling header length in DWords
4364  * @protocol_index: protocol index type
4365  * @filter_index: pointer to filter index
4366  * @cmd_details: pointer to command details structure or NULL
4367  **/
4368 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4369                                 u16 udp_port, u8 protocol_index,
4370                                 u8 *filter_index,
4371                                 struct i40e_asq_cmd_details *cmd_details)
4372 {
4373         struct i40e_aq_desc desc;
4374         struct i40e_aqc_add_udp_tunnel *cmd =
4375                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4376         struct i40e_aqc_del_udp_tunnel_completion *resp =
4377                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4378         enum i40e_status_code status;
4379
4380         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4381
4382         cmd->udp_port = CPU_TO_LE16(udp_port);
4383         cmd->protocol_type = protocol_index;
4384
4385         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4386
4387         if (!status && filter_index)
4388                 *filter_index = resp->index;
4389
4390         return status;
4391 }
4392
4393 /**
4394  * i40e_aq_del_udp_tunnel
4395  * @hw: pointer to the hw struct
4396  * @index: filter index
4397  * @cmd_details: pointer to command details structure or NULL
4398  **/
4399 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4400                                 struct i40e_asq_cmd_details *cmd_details)
4401 {
4402         struct i40e_aq_desc desc;
4403         struct i40e_aqc_remove_udp_tunnel *cmd =
4404                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4405         enum i40e_status_code status;
4406
4407         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4408
4409         cmd->index = index;
4410
4411         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4412
4413         return status;
4414 }
4415
4416 /**
4417  * i40e_aq_get_switch_resource_alloc (0x0204)
4418  * @hw: pointer to the hw struct
4419  * @num_entries: pointer to u8 to store the number of resource entries returned
4420  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
4421  *        to store the resource information for all resource types.  Each
4422  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
4423  * @count: size, in bytes, of the buffer provided
4424  * @cmd_details: pointer to command details structure or NULL
4425  *
4426  * Query the resources allocated to a function.
4427  **/
4428 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4429                         u8 *num_entries,
4430                         struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4431                         u16 count,
4432                         struct i40e_asq_cmd_details *cmd_details)
4433 {
4434         struct i40e_aq_desc desc;
4435         struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4436                 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4437         enum i40e_status_code status;
4438         u16 length = count * sizeof(*buf);
4439
4440         i40e_fill_default_direct_cmd_desc(&desc,
4441                                         i40e_aqc_opc_get_switch_resource_alloc);
4442
4443         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4444         if (length > I40E_AQ_LARGE_BUF)
4445                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4446
4447         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4448
4449         if (!status && num_entries)
4450                 *num_entries = cmd_resp->num_entries;
4451
4452         return status;
4453 }
4454
4455 /**
4456  * i40e_aq_delete_element - Delete switch element
4457  * @hw: pointer to the hw struct
4458  * @seid: the SEID to delete from the switch
4459  * @cmd_details: pointer to command details structure or NULL
4460  *
4461  * This deletes a switch element from the switch.
4462  **/
4463 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4464                                 struct i40e_asq_cmd_details *cmd_details)
4465 {
4466         struct i40e_aq_desc desc;
4467         struct i40e_aqc_switch_seid *cmd =
4468                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4469         enum i40e_status_code status;
4470
4471         if (seid == 0)
4472                 return I40E_ERR_PARAM;
4473
4474         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4475
4476         cmd->seid = CPU_TO_LE16(seid);
4477
4478         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4479
4480         return status;
4481 }
4482
4483 /**
4484  * i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4485  * @hw: pointer to the hw struct
4486  * @flags: component flags
4487  * @mac_seid: uplink seid (MAC SEID)
4488  * @vsi_seid: connected vsi seid
4489  * @ret_seid: seid of create pv component
4490  *
4491  * This instantiates an i40e port virtualizer with specified flags.
4492  * Depending on specified flags the port virtualizer can act as a
4493  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4494  */
4495 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4496                                        u16 mac_seid, u16 vsi_seid,
4497                                        u16 *ret_seid)
4498 {
4499         struct i40e_aq_desc desc;
4500         struct i40e_aqc_add_update_pv *cmd =
4501                 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4502         struct i40e_aqc_add_update_pv_completion *resp =
4503                 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4504         enum i40e_status_code status;
4505
4506         if (vsi_seid == 0)
4507                 return I40E_ERR_PARAM;
4508
4509         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4510         cmd->command_flags = CPU_TO_LE16(flags);
4511         cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4512         cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4513
4514         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4515         if (!status && ret_seid)
4516                 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4517
4518         return status;
4519 }
4520
4521 /**
4522  * i40e_aq_add_tag - Add an S/E-tag
4523  * @hw: pointer to the hw struct
4524  * @direct_to_queue: should s-tag direct flow to a specific queue
4525  * @vsi_seid: VSI SEID to use this tag
4526  * @tag: value of the tag
4527  * @queue_num: queue number, only valid is direct_to_queue is true
4528  * @tags_used: return value, number of tags in use by this PF
4529  * @tags_free: return value, number of unallocated tags
4530  * @cmd_details: pointer to command details structure or NULL
4531  *
4532  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4533  * the number of tags allocated by the PF, and the number of unallocated
4534  * tags available.
4535  **/
4536 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4537                                 u16 vsi_seid, u16 tag, u16 queue_num,
4538                                 u16 *tags_used, u16 *tags_free,
4539                                 struct i40e_asq_cmd_details *cmd_details)
4540 {
4541         struct i40e_aq_desc desc;
4542         struct i40e_aqc_add_tag *cmd =
4543                 (struct i40e_aqc_add_tag *)&desc.params.raw;
4544         struct i40e_aqc_add_remove_tag_completion *resp =
4545                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4546         enum i40e_status_code status;
4547
4548         if (vsi_seid == 0)
4549                 return I40E_ERR_PARAM;
4550
4551         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4552
4553         cmd->seid = CPU_TO_LE16(vsi_seid);
4554         cmd->tag = CPU_TO_LE16(tag);
4555         if (direct_to_queue) {
4556                 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4557                 cmd->queue_number = CPU_TO_LE16(queue_num);
4558         }
4559
4560         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4561
4562         if (!status) {
4563                 if (tags_used != NULL)
4564                         *tags_used = LE16_TO_CPU(resp->tags_used);
4565                 if (tags_free != NULL)
4566                         *tags_free = LE16_TO_CPU(resp->tags_free);
4567         }
4568
4569         return status;
4570 }
4571
4572 /**
4573  * i40e_aq_remove_tag - Remove an S- or E-tag
4574  * @hw: pointer to the hw struct
4575  * @vsi_seid: VSI SEID this tag is associated with
4576  * @tag: value of the S-tag to delete
4577  * @tags_used: return value, number of tags in use by this PF
4578  * @tags_free: return value, number of unallocated tags
4579  * @cmd_details: pointer to command details structure or NULL
4580  *
4581  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4582  * the number of tags allocated by the PF, and the number of unallocated
4583  * tags available.
4584  **/
4585 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4586                                 u16 tag, u16 *tags_used, u16 *tags_free,
4587                                 struct i40e_asq_cmd_details *cmd_details)
4588 {
4589         struct i40e_aq_desc desc;
4590         struct i40e_aqc_remove_tag *cmd =
4591                 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4592         struct i40e_aqc_add_remove_tag_completion *resp =
4593                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4594         enum i40e_status_code status;
4595
4596         if (vsi_seid == 0)
4597                 return I40E_ERR_PARAM;
4598
4599         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4600
4601         cmd->seid = CPU_TO_LE16(vsi_seid);
4602         cmd->tag = CPU_TO_LE16(tag);
4603
4604         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4605
4606         if (!status) {
4607                 if (tags_used != NULL)
4608                         *tags_used = LE16_TO_CPU(resp->tags_used);
4609                 if (tags_free != NULL)
4610                         *tags_free = LE16_TO_CPU(resp->tags_free);
4611         }
4612
4613         return status;
4614 }
4615
4616 /**
4617  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4618  * @hw: pointer to the hw struct
4619  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4620  * @etag: value of E-tag to add
4621  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4622  * @buf: address of indirect buffer
4623  * @tags_used: return value, number of E-tags in use by this port
4624  * @tags_free: return value, number of unallocated M-tags
4625  * @cmd_details: pointer to command details structure or NULL
4626  *
4627  * This associates a multicast E-tag to a port virtualizer.  It will return
4628  * the number of tags allocated by the PF, and the number of unallocated
4629  * tags available.
4630  *
4631  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4632  * num_tags_in_buf long.
4633  **/
4634 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4635                                 u16 etag, u8 num_tags_in_buf, void *buf,
4636                                 u16 *tags_used, u16 *tags_free,
4637                                 struct i40e_asq_cmd_details *cmd_details)
4638 {
4639         struct i40e_aq_desc desc;
4640         struct i40e_aqc_add_remove_mcast_etag *cmd =
4641                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4642         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4643            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4644         enum i40e_status_code status;
4645         u16 length = sizeof(u16) * num_tags_in_buf;
4646
4647         if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4648                 return I40E_ERR_PARAM;
4649
4650         i40e_fill_default_direct_cmd_desc(&desc,
4651                                           i40e_aqc_opc_add_multicast_etag);
4652
4653         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4654         cmd->etag = CPU_TO_LE16(etag);
4655         cmd->num_unicast_etags = num_tags_in_buf;
4656
4657         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4658         if (length > I40E_AQ_LARGE_BUF)
4659                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4660
4661         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4662
4663         if (!status) {
4664                 if (tags_used != NULL)
4665                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4666                 if (tags_free != NULL)
4667                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4668         }
4669
4670         return status;
4671 }
4672
4673 /**
4674  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4675  * @hw: pointer to the hw struct
4676  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4677  * @etag: value of the E-tag to remove
4678  * @tags_used: return value, number of tags in use by this port
4679  * @tags_free: return value, number of unallocated tags
4680  * @cmd_details: pointer to command details structure or NULL
4681  *
4682  * This deletes an E-tag from the port virtualizer.  It will return
4683  * the number of tags allocated by the port, and the number of unallocated
4684  * tags available.
4685  **/
4686 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4687                                 u16 etag, u16 *tags_used, u16 *tags_free,
4688                                 struct i40e_asq_cmd_details *cmd_details)
4689 {
4690         struct i40e_aq_desc desc;
4691         struct i40e_aqc_add_remove_mcast_etag *cmd =
4692                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4693         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4694            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4695         enum i40e_status_code status;
4696
4697
4698         if (pv_seid == 0)
4699                 return I40E_ERR_PARAM;
4700
4701         i40e_fill_default_direct_cmd_desc(&desc,
4702                                           i40e_aqc_opc_remove_multicast_etag);
4703
4704         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4705         cmd->etag = CPU_TO_LE16(etag);
4706
4707         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4708
4709         if (!status) {
4710                 if (tags_used != NULL)
4711                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4712                 if (tags_free != NULL)
4713                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4714         }
4715
4716         return status;
4717 }
4718
4719 /**
4720  * i40e_aq_update_tag - Update an S/E-tag
4721  * @hw: pointer to the hw struct
4722  * @vsi_seid: VSI SEID using this S-tag
4723  * @old_tag: old tag value
4724  * @new_tag: new tag value
4725  * @tags_used: return value, number of tags in use by this PF
4726  * @tags_free: return value, number of unallocated tags
4727  * @cmd_details: pointer to command details structure or NULL
4728  *
4729  * This updates the value of the tag currently attached to this VSI
4730  * in the switch complex.  It will return the number of tags allocated
4731  * by the PF, and the number of unallocated tags available.
4732  **/
4733 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4734                                 u16 old_tag, u16 new_tag, u16 *tags_used,
4735                                 u16 *tags_free,
4736                                 struct i40e_asq_cmd_details *cmd_details)
4737 {
4738         struct i40e_aq_desc desc;
4739         struct i40e_aqc_update_tag *cmd =
4740                 (struct i40e_aqc_update_tag *)&desc.params.raw;
4741         struct i40e_aqc_update_tag_completion *resp =
4742                 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4743         enum i40e_status_code status;
4744
4745         if (vsi_seid == 0)
4746                 return I40E_ERR_PARAM;
4747
4748         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4749
4750         cmd->seid = CPU_TO_LE16(vsi_seid);
4751         cmd->old_tag = CPU_TO_LE16(old_tag);
4752         cmd->new_tag = CPU_TO_LE16(new_tag);
4753
4754         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4755
4756         if (!status) {
4757                 if (tags_used != NULL)
4758                         *tags_used = LE16_TO_CPU(resp->tags_used);
4759                 if (tags_free != NULL)
4760                         *tags_free = LE16_TO_CPU(resp->tags_free);
4761         }
4762
4763         return status;
4764 }
4765
4766 /**
4767  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4768  * @hw: pointer to the hw struct
4769  * @tcmap: TC map for request/release any ignore PFC condition
4770  * @request: request or release ignore PFC condition
4771  * @tcmap_ret: return TCs for which PFC is currently ignored
4772  * @cmd_details: pointer to command details structure or NULL
4773  *
4774  * This sends out request/release to ignore PFC condition for a TC.
4775  * It will return the TCs for which PFC is currently ignored.
4776  **/
4777 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4778                                 bool request, u8 *tcmap_ret,
4779                                 struct i40e_asq_cmd_details *cmd_details)
4780 {
4781         struct i40e_aq_desc desc;
4782         struct i40e_aqc_pfc_ignore *cmd_resp =
4783                 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4784         enum i40e_status_code status;
4785
4786         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4787
4788         if (request)
4789                 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4790
4791         cmd_resp->tc_bitmap = tcmap;
4792
4793         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4794
4795         if (!status) {
4796                 if (tcmap_ret != NULL)
4797                         *tcmap_ret = cmd_resp->tc_bitmap;
4798         }
4799
4800         return status;
4801 }
4802
4803 /**
4804  * i40e_aq_dcb_updated - DCB Updated Command
4805  * @hw: pointer to the hw struct
4806  * @cmd_details: pointer to command details structure or NULL
4807  *
4808  * When LLDP is handled in PF this command is used by the PF
4809  * to notify EMP that a DCB setting is modified.
4810  * When LLDP is handled in EMP this command is used by the PF
4811  * to notify EMP whenever one of the following parameters get
4812  * modified:
4813  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4814  *   - PCIRTT in PRTDCB_GENC.PCIRTT
4815  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4816  * EMP will return when the shared RPB settings have been
4817  * recomputed and modified. The retval field in the descriptor
4818  * will be set to 0 when RPB is modified.
4819  **/
4820 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4821                                 struct i40e_asq_cmd_details *cmd_details)
4822 {
4823         struct i40e_aq_desc desc;
4824         enum i40e_status_code status;
4825
4826         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4827
4828         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4829
4830         return status;
4831 }
4832
4833 /**
4834  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4835  * @hw: pointer to the hw struct
4836  * @seid: defines the SEID of the switch for which the stats are requested
4837  * @vlan_id: the VLAN ID for which the statistics are requested
4838  * @stat_index: index of the statistics counters block assigned to this VLAN
4839  * @cmd_details: pointer to command details structure or NULL
4840  *
4841  * XL710 supports 128 smonVlanStats counters.This command is used to
4842  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4843  * switch.
4844  **/
4845 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4846                                 u16 vlan_id, u16 *stat_index,
4847                                 struct i40e_asq_cmd_details *cmd_details)
4848 {
4849         struct i40e_aq_desc desc;
4850         struct i40e_aqc_add_remove_statistics *cmd_resp =
4851                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4852         enum i40e_status_code status;
4853
4854         if ((seid == 0) || (stat_index == NULL))
4855                 return I40E_ERR_PARAM;
4856
4857         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4858
4859         cmd_resp->seid = CPU_TO_LE16(seid);
4860         cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4861
4862         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4863
4864         if (!status && stat_index)
4865                 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4866
4867         return status;
4868 }
4869
4870 /**
4871  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4872  * @hw: pointer to the hw struct
4873  * @seid: defines the SEID of the switch for which the stats are requested
4874  * @vlan_id: the VLAN ID for which the statistics are requested
4875  * @stat_index: index of the statistics counters block assigned to this VLAN
4876  * @cmd_details: pointer to command details structure or NULL
4877  *
4878  * XL710 supports 128 smonVlanStats counters.This command is used to
4879  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4880  * switch.
4881  **/
4882 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4883                                 u16 vlan_id, u16 stat_index,
4884                                 struct i40e_asq_cmd_details *cmd_details)
4885 {
4886         struct i40e_aq_desc desc;
4887         struct i40e_aqc_add_remove_statistics *cmd =
4888                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4889         enum i40e_status_code status;
4890
4891         if (seid == 0)
4892                 return I40E_ERR_PARAM;
4893
4894         i40e_fill_default_direct_cmd_desc(&desc,
4895                                           i40e_aqc_opc_remove_statistics);
4896
4897         cmd->seid = CPU_TO_LE16(seid);
4898         cmd->vlan  = CPU_TO_LE16(vlan_id);
4899         cmd->stat_index = CPU_TO_LE16(stat_index);
4900
4901         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4902
4903         return status;
4904 }
4905
4906 /**
4907  * i40e_aq_set_port_parameters - set physical port parameters.
4908  * @hw: pointer to the hw struct
4909  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4910  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4911  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4912  * @double_vlan: if set double VLAN is enabled
4913  * @cmd_details: pointer to command details structure or NULL
4914  **/
4915 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4916                                 u16 bad_frame_vsi, bool save_bad_pac,
4917                                 bool pad_short_pac, bool double_vlan,
4918                                 struct i40e_asq_cmd_details *cmd_details)
4919 {
4920         struct i40e_aqc_set_port_parameters *cmd;
4921         enum i40e_status_code status;
4922         struct i40e_aq_desc desc;
4923         u16 command_flags = 0;
4924
4925         cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4926
4927         i40e_fill_default_direct_cmd_desc(&desc,
4928                                           i40e_aqc_opc_set_port_parameters);
4929
4930         cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4931         if (save_bad_pac)
4932                 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4933         if (pad_short_pac)
4934                 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4935         if (double_vlan)
4936                 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4937         cmd->command_flags = CPU_TO_LE16(command_flags);
4938
4939         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4940
4941         return status;
4942 }
4943
4944 /**
4945  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
4946  * @hw: pointer to the hw struct
4947  * @seid: seid for the physical port/switching component/vsi
4948  * @buff: Indirect buffer to hold data parameters and response
4949  * @buff_size: Indirect buffer size
4950  * @opcode: Tx scheduler AQ command opcode
4951  * @cmd_details: pointer to command details structure or NULL
4952  *
4953  * Generic command handler for Tx scheduler AQ commands
4954  **/
4955 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
4956                                 void *buff, u16 buff_size,
4957                                  enum i40e_admin_queue_opc opcode,
4958                                 struct i40e_asq_cmd_details *cmd_details)
4959 {
4960         struct i40e_aq_desc desc;
4961         struct i40e_aqc_tx_sched_ind *cmd =
4962                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4963         enum i40e_status_code status;
4964         bool cmd_param_flag = false;
4965
4966         switch (opcode) {
4967         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
4968         case i40e_aqc_opc_configure_vsi_tc_bw:
4969         case i40e_aqc_opc_enable_switching_comp_ets:
4970         case i40e_aqc_opc_modify_switching_comp_ets:
4971         case i40e_aqc_opc_disable_switching_comp_ets:
4972         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
4973         case i40e_aqc_opc_configure_switching_comp_bw_config:
4974                 cmd_param_flag = true;
4975                 break;
4976         case i40e_aqc_opc_query_vsi_bw_config:
4977         case i40e_aqc_opc_query_vsi_ets_sla_config:
4978         case i40e_aqc_opc_query_switching_comp_ets_config:
4979         case i40e_aqc_opc_query_port_ets_config:
4980         case i40e_aqc_opc_query_switching_comp_bw_config:
4981                 cmd_param_flag = false;
4982                 break;
4983         default:
4984                 return I40E_ERR_PARAM;
4985         }
4986
4987         i40e_fill_default_direct_cmd_desc(&desc, opcode);
4988
4989         /* Indirect command */
4990         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4991         if (cmd_param_flag)
4992                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4993         if (buff_size > I40E_AQ_LARGE_BUF)
4994                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4995
4996         desc.datalen = CPU_TO_LE16(buff_size);
4997
4998         cmd->vsi_seid = CPU_TO_LE16(seid);
4999
5000         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5001
5002         return status;
5003 }
5004
5005 /**
5006  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5007  * @hw: pointer to the hw struct
5008  * @seid: VSI seid
5009  * @credit: BW limit credits (0 = disabled)
5010  * @max_credit: Max BW limit credits
5011  * @cmd_details: pointer to command details structure or NULL
5012  **/
5013 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5014                                 u16 seid, u16 credit, u8 max_credit,
5015                                 struct i40e_asq_cmd_details *cmd_details)
5016 {
5017         struct i40e_aq_desc desc;
5018         struct i40e_aqc_configure_vsi_bw_limit *cmd =
5019                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5020         enum i40e_status_code status;
5021
5022         i40e_fill_default_direct_cmd_desc(&desc,
5023                                           i40e_aqc_opc_configure_vsi_bw_limit);
5024
5025         cmd->vsi_seid = CPU_TO_LE16(seid);
5026         cmd->credit = CPU_TO_LE16(credit);
5027         cmd->max_credit = max_credit;
5028
5029         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5030
5031         return status;
5032 }
5033
5034 /**
5035  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5036  * @hw: pointer to the hw struct
5037  * @seid: switching component seid
5038  * @credit: BW limit credits (0 = disabled)
5039  * @max_bw: Max BW limit credits
5040  * @cmd_details: pointer to command details structure or NULL
5041  **/
5042 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5043                                 u16 seid, u16 credit, u8 max_bw,
5044                                 struct i40e_asq_cmd_details *cmd_details)
5045 {
5046         struct i40e_aq_desc desc;
5047         struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5048           (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5049         enum i40e_status_code status;
5050
5051         i40e_fill_default_direct_cmd_desc(&desc,
5052                                 i40e_aqc_opc_configure_switching_comp_bw_limit);
5053
5054         cmd->seid = CPU_TO_LE16(seid);
5055         cmd->credit = CPU_TO_LE16(credit);
5056         cmd->max_bw = max_bw;
5057
5058         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5059
5060         return status;
5061 }
5062
5063 /**
5064  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5065  * @hw: pointer to the hw struct
5066  * @seid: VSI seid
5067  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5068  * @cmd_details: pointer to command details structure or NULL
5069  **/
5070 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5071                         u16 seid,
5072                         struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5073                         struct i40e_asq_cmd_details *cmd_details)
5074 {
5075         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5076                                     i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5077                                     cmd_details);
5078 }
5079
5080 /**
5081  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5082  * @hw: pointer to the hw struct
5083  * @seid: VSI seid
5084  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5085  * @cmd_details: pointer to command details structure or NULL
5086  **/
5087 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5088                         u16 seid,
5089                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5090                         struct i40e_asq_cmd_details *cmd_details)
5091 {
5092         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5093                                     i40e_aqc_opc_configure_vsi_tc_bw,
5094                                     cmd_details);
5095 }
5096
5097 /**
5098  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5099  * @hw: pointer to the hw struct
5100  * @seid: seid of the switching component connected to Physical Port
5101  * @ets_data: Buffer holding ETS parameters
5102  * @cmd_details: pointer to command details structure or NULL
5103  **/
5104 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5105                 u16 seid,
5106                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5107                 enum i40e_admin_queue_opc opcode,
5108                 struct i40e_asq_cmd_details *cmd_details)
5109 {
5110         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5111                                     sizeof(*ets_data), opcode, cmd_details);
5112 }
5113
5114 /**
5115  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5116  * @hw: pointer to the hw struct
5117  * @seid: seid of the switching component
5118  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5119  * @cmd_details: pointer to command details structure or NULL
5120  **/
5121 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5122         u16 seid,
5123         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5124         struct i40e_asq_cmd_details *cmd_details)
5125 {
5126         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5127                             i40e_aqc_opc_configure_switching_comp_bw_config,
5128                             cmd_details);
5129 }
5130
5131 /**
5132  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5133  * @hw: pointer to the hw struct
5134  * @seid: seid of the switching component
5135  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5136  * @cmd_details: pointer to command details structure or NULL
5137  **/
5138 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5139         struct i40e_hw *hw, u16 seid,
5140         struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5141         struct i40e_asq_cmd_details *cmd_details)
5142 {
5143         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5144                             i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5145                             cmd_details);
5146 }
5147
5148 /**
5149  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5150  * @hw: pointer to the hw struct
5151  * @seid: seid of the VSI
5152  * @bw_data: Buffer to hold VSI BW configuration
5153  * @cmd_details: pointer to command details structure or NULL
5154  **/
5155 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5156                         u16 seid,
5157                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5158                         struct i40e_asq_cmd_details *cmd_details)
5159 {
5160         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5161                                     i40e_aqc_opc_query_vsi_bw_config,
5162                                     cmd_details);
5163 }
5164
5165 /**
5166  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5167  * @hw: pointer to the hw struct
5168  * @seid: seid of the VSI
5169  * @bw_data: Buffer to hold VSI BW configuration per TC
5170  * @cmd_details: pointer to command details structure or NULL
5171  **/
5172 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5173                         u16 seid,
5174                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5175                         struct i40e_asq_cmd_details *cmd_details)
5176 {
5177         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5178                                     i40e_aqc_opc_query_vsi_ets_sla_config,
5179                                     cmd_details);
5180 }
5181
5182 /**
5183  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5184  * @hw: pointer to the hw struct
5185  * @seid: seid of the switching component
5186  * @bw_data: Buffer to hold switching component's per TC BW config
5187  * @cmd_details: pointer to command details structure or NULL
5188  **/
5189 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5190                 u16 seid,
5191                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5192                 struct i40e_asq_cmd_details *cmd_details)
5193 {
5194         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5195                                    i40e_aqc_opc_query_switching_comp_ets_config,
5196                                    cmd_details);
5197 }
5198
5199 /**
5200  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5201  * @hw: pointer to the hw struct
5202  * @seid: seid of the VSI or switching component connected to Physical Port
5203  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5204  * @cmd_details: pointer to command details structure or NULL
5205  **/
5206 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5207                         u16 seid,
5208                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
5209                         struct i40e_asq_cmd_details *cmd_details)
5210 {
5211         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5212                                     i40e_aqc_opc_query_port_ets_config,
5213                                     cmd_details);
5214 }
5215
5216 /**
5217  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5218  * @hw: pointer to the hw struct
5219  * @seid: seid of the switching component
5220  * @bw_data: Buffer to hold switching component's BW configuration
5221  * @cmd_details: pointer to command details structure or NULL
5222  **/
5223 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5224                 u16 seid,
5225                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5226                 struct i40e_asq_cmd_details *cmd_details)
5227 {
5228         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5229                                     i40e_aqc_opc_query_switching_comp_bw_config,
5230                                     cmd_details);
5231 }
5232
5233 /**
5234  * i40e_validate_filter_settings
5235  * @hw: pointer to the hardware structure
5236  * @settings: Filter control settings
5237  *
5238  * Check and validate the filter control settings passed.
5239  * The function checks for the valid filter/context sizes being
5240  * passed for FCoE and PE.
5241  *
5242  * Returns I40E_SUCCESS if the values passed are valid and within
5243  * range else returns an error.
5244  **/
5245 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5246                                 struct i40e_filter_control_settings *settings)
5247 {
5248         u32 fcoe_cntx_size, fcoe_filt_size;
5249         u32 pe_cntx_size, pe_filt_size;
5250         u32 fcoe_fmax;
5251
5252         u32 val;
5253
5254         /* Validate FCoE settings passed */
5255         switch (settings->fcoe_filt_num) {
5256         case I40E_HASH_FILTER_SIZE_1K:
5257         case I40E_HASH_FILTER_SIZE_2K:
5258         case I40E_HASH_FILTER_SIZE_4K:
5259         case I40E_HASH_FILTER_SIZE_8K:
5260         case I40E_HASH_FILTER_SIZE_16K:
5261         case I40E_HASH_FILTER_SIZE_32K:
5262                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5263                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5264                 break;
5265         default:
5266                 return I40E_ERR_PARAM;
5267         }
5268
5269         switch (settings->fcoe_cntx_num) {
5270         case I40E_DMA_CNTX_SIZE_512:
5271         case I40E_DMA_CNTX_SIZE_1K:
5272         case I40E_DMA_CNTX_SIZE_2K:
5273         case I40E_DMA_CNTX_SIZE_4K:
5274                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5275                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5276                 break;
5277         default:
5278                 return I40E_ERR_PARAM;
5279         }
5280
5281         /* Validate PE settings passed */
5282         switch (settings->pe_filt_num) {
5283         case I40E_HASH_FILTER_SIZE_1K:
5284         case I40E_HASH_FILTER_SIZE_2K:
5285         case I40E_HASH_FILTER_SIZE_4K:
5286         case I40E_HASH_FILTER_SIZE_8K:
5287         case I40E_HASH_FILTER_SIZE_16K:
5288         case I40E_HASH_FILTER_SIZE_32K:
5289         case I40E_HASH_FILTER_SIZE_64K:
5290         case I40E_HASH_FILTER_SIZE_128K:
5291         case I40E_HASH_FILTER_SIZE_256K:
5292         case I40E_HASH_FILTER_SIZE_512K:
5293         case I40E_HASH_FILTER_SIZE_1M:
5294                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5295                 pe_filt_size <<= (u32)settings->pe_filt_num;
5296                 break;
5297         default:
5298                 return I40E_ERR_PARAM;
5299         }
5300
5301         switch (settings->pe_cntx_num) {
5302         case I40E_DMA_CNTX_SIZE_512:
5303         case I40E_DMA_CNTX_SIZE_1K:
5304         case I40E_DMA_CNTX_SIZE_2K:
5305         case I40E_DMA_CNTX_SIZE_4K:
5306         case I40E_DMA_CNTX_SIZE_8K:
5307         case I40E_DMA_CNTX_SIZE_16K:
5308         case I40E_DMA_CNTX_SIZE_32K:
5309         case I40E_DMA_CNTX_SIZE_64K:
5310         case I40E_DMA_CNTX_SIZE_128K:
5311         case I40E_DMA_CNTX_SIZE_256K:
5312                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5313                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5314                 break;
5315         default:
5316                 return I40E_ERR_PARAM;
5317         }
5318
5319         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5320         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5321         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5322                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5323         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
5324                 return I40E_ERR_INVALID_SIZE;
5325
5326         return I40E_SUCCESS;
5327 }
5328
5329 /**
5330  * i40e_set_filter_control
5331  * @hw: pointer to the hardware structure
5332  * @settings: Filter control settings
5333  *
5334  * Set the Queue Filters for PE/FCoE and enable filters required
5335  * for a single PF. It is expected that these settings are programmed
5336  * at the driver initialization time.
5337  **/
5338 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5339                                 struct i40e_filter_control_settings *settings)
5340 {
5341         enum i40e_status_code ret = I40E_SUCCESS;
5342         u32 hash_lut_size = 0;
5343         u32 val;
5344
5345         if (!settings)
5346                 return I40E_ERR_PARAM;
5347
5348         /* Validate the input settings */
5349         ret = i40e_validate_filter_settings(hw, settings);
5350         if (ret)
5351                 return ret;
5352
5353         /* Read the PF Queue Filter control register */
5354         val = rd32(hw, I40E_PFQF_CTL_0);
5355
5356         /* Program required PE hash buckets for the PF */
5357         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5358         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5359                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5360         /* Program required PE contexts for the PF */
5361         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5362         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5363                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5364
5365         /* Program required FCoE hash buckets for the PF */
5366         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5367         val |= ((u32)settings->fcoe_filt_num <<
5368                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5369                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5370         /* Program required FCoE DDP contexts for the PF */
5371         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5372         val |= ((u32)settings->fcoe_cntx_num <<
5373                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5374                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5375
5376         /* Program Hash LUT size for the PF */
5377         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5378         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5379                 hash_lut_size = 1;
5380         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5381                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5382
5383         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5384         if (settings->enable_fdir)
5385                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5386         if (settings->enable_ethtype)
5387                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5388         if (settings->enable_macvlan)
5389                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5390
5391         wr32(hw, I40E_PFQF_CTL_0, val);
5392
5393         return I40E_SUCCESS;
5394 }
5395
5396 /**
5397  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5398  * @hw: pointer to the hw struct
5399  * @mac_addr: MAC address to use in the filter
5400  * @ethtype: Ethertype to use in the filter
5401  * @flags: Flags that needs to be applied to the filter
5402  * @vsi_seid: seid of the control VSI
5403  * @queue: VSI queue number to send the packet to
5404  * @is_add: Add control packet filter if True else remove
5405  * @stats: Structure to hold information on control filter counts
5406  * @cmd_details: pointer to command details structure or NULL
5407  *
5408  * This command will Add or Remove control packet filter for a control VSI.
5409  * In return it will update the total number of perfect filter count in
5410  * the stats member.
5411  **/
5412 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5413                                 u8 *mac_addr, u16 ethtype, u16 flags,
5414                                 u16 vsi_seid, u16 queue, bool is_add,
5415                                 struct i40e_control_filter_stats *stats,
5416                                 struct i40e_asq_cmd_details *cmd_details)
5417 {
5418         struct i40e_aq_desc desc;
5419         struct i40e_aqc_add_remove_control_packet_filter *cmd =
5420                 (struct i40e_aqc_add_remove_control_packet_filter *)
5421                 &desc.params.raw;
5422         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5423                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5424                 &desc.params.raw;
5425         enum i40e_status_code status;
5426
5427         if (vsi_seid == 0)
5428                 return I40E_ERR_PARAM;
5429
5430         if (is_add) {
5431                 i40e_fill_default_direct_cmd_desc(&desc,
5432                                 i40e_aqc_opc_add_control_packet_filter);
5433                 cmd->queue = CPU_TO_LE16(queue);
5434         } else {
5435                 i40e_fill_default_direct_cmd_desc(&desc,
5436                                 i40e_aqc_opc_remove_control_packet_filter);
5437         }
5438
5439         if (mac_addr)
5440                 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
5441                             I40E_NONDMA_TO_NONDMA);
5442
5443         cmd->etype = CPU_TO_LE16(ethtype);
5444         cmd->flags = CPU_TO_LE16(flags);
5445         cmd->seid = CPU_TO_LE16(vsi_seid);
5446
5447         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5448
5449         if (!status && stats) {
5450                 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5451                 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5452                 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5453                 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5454         }
5455
5456         return status;
5457 }
5458
5459 /**
5460  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5461  * @hw: pointer to the hw struct
5462  * @seid: VSI seid to add ethertype filter from
5463  **/
5464 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5465 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5466                                                     u16 seid)
5467 {
5468         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5469                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5470                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5471         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5472         enum i40e_status_code status;
5473
5474         status = i40e_aq_add_rem_control_packet_filter(hw, 0, ethtype, flag,
5475                                                        seid, 0, true, NULL,
5476                                                        NULL);
5477         if (status)
5478                 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5479 }
5480
5481 /**
5482  * i40e_aq_add_cloud_filters
5483  * @hw: pointer to the hardware structure
5484  * @seid: VSI seid to add cloud filters from
5485  * @filters: Buffer which contains the filters to be added
5486  * @filter_count: number of filters contained in the buffer
5487  *
5488  * Set the cloud filters for a given VSI.  The contents of the
5489  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5490  * in by the caller of the function.
5491  *
5492  **/
5493 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5494         u16 seid,
5495         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5496         u8 filter_count)
5497 {
5498         struct i40e_aq_desc desc;
5499         struct i40e_aqc_add_remove_cloud_filters *cmd =
5500         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5501         u16 buff_len;
5502         enum i40e_status_code status;
5503
5504         i40e_fill_default_direct_cmd_desc(&desc,
5505                                           i40e_aqc_opc_add_cloud_filters);
5506
5507         buff_len = filter_count * sizeof(*filters);
5508         desc.datalen = CPU_TO_LE16(buff_len);
5509         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5510         cmd->num_filters = filter_count;
5511         cmd->seid = CPU_TO_LE16(seid);
5512
5513         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5514
5515         return status;
5516 }
5517
5518 /**
5519  * i40e_aq_remove_cloud_filters
5520  * @hw: pointer to the hardware structure
5521  * @seid: VSI seid to remove cloud filters from
5522  * @filters: Buffer which contains the filters to be removed
5523  * @filter_count: number of filters contained in the buffer
5524  *
5525  * Remove the cloud filters for a given VSI.  The contents of the
5526  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5527  * in by the caller of the function.
5528  *
5529  **/
5530 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5531                 u16 seid,
5532                 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5533                 u8 filter_count)
5534 {
5535         struct i40e_aq_desc desc;
5536         struct i40e_aqc_add_remove_cloud_filters *cmd =
5537         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5538         enum i40e_status_code status;
5539         u16 buff_len;
5540
5541         i40e_fill_default_direct_cmd_desc(&desc,
5542                                           i40e_aqc_opc_remove_cloud_filters);
5543
5544         buff_len = filter_count * sizeof(*filters);
5545         desc.datalen = CPU_TO_LE16(buff_len);
5546         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5547         cmd->num_filters = filter_count;
5548         cmd->seid = CPU_TO_LE16(seid);
5549
5550         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5551
5552         return status;
5553 }
5554
5555 /**
5556  * i40e_aq_alternate_write
5557  * @hw: pointer to the hardware structure
5558  * @reg_addr0: address of first dword to be read
5559  * @reg_val0: value to be written under 'reg_addr0'
5560  * @reg_addr1: address of second dword to be read
5561  * @reg_val1: value to be written under 'reg_addr1'
5562  *
5563  * Write one or two dwords to alternate structure. Fields are indicated
5564  * by 'reg_addr0' and 'reg_addr1' register numbers.
5565  *
5566  **/
5567 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5568                                 u32 reg_addr0, u32 reg_val0,
5569                                 u32 reg_addr1, u32 reg_val1)
5570 {
5571         struct i40e_aq_desc desc;
5572         struct i40e_aqc_alternate_write *cmd_resp =
5573                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5574         enum i40e_status_code status;
5575
5576         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5577         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5578         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5579         cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5580         cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5581
5582         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5583
5584         return status;
5585 }
5586
5587 /**
5588  * i40e_aq_alternate_write_indirect
5589  * @hw: pointer to the hardware structure
5590  * @addr: address of a first register to be modified
5591  * @dw_count: number of alternate structure fields to write
5592  * @buffer: pointer to the command buffer
5593  *
5594  * Write 'dw_count' dwords from 'buffer' to alternate structure
5595  * starting at 'addr'.
5596  *
5597  **/
5598 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5599                                 u32 addr, u32 dw_count, void *buffer)
5600 {
5601         struct i40e_aq_desc desc;
5602         struct i40e_aqc_alternate_ind_write *cmd_resp =
5603                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5604         enum i40e_status_code status;
5605
5606         if (buffer == NULL)
5607                 return I40E_ERR_PARAM;
5608
5609         /* Indirect command */
5610         i40e_fill_default_direct_cmd_desc(&desc,
5611                                          i40e_aqc_opc_alternate_write_indirect);
5612
5613         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5614         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5615         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5616                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5617
5618         cmd_resp->address = CPU_TO_LE32(addr);
5619         cmd_resp->length = CPU_TO_LE32(dw_count);
5620
5621         status = i40e_asq_send_command(hw, &desc, buffer,
5622                                        I40E_LO_DWORD(4*dw_count), NULL);
5623
5624         return status;
5625 }
5626
5627 /**
5628  * i40e_aq_alternate_read
5629  * @hw: pointer to the hardware structure
5630  * @reg_addr0: address of first dword to be read
5631  * @reg_val0: pointer for data read from 'reg_addr0'
5632  * @reg_addr1: address of second dword to be read
5633  * @reg_val1: pointer for data read from 'reg_addr1'
5634  *
5635  * Read one or two dwords from alternate structure. Fields are indicated
5636  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5637  * is not passed then only register at 'reg_addr0' is read.
5638  *
5639  **/
5640 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5641                                 u32 reg_addr0, u32 *reg_val0,
5642                                 u32 reg_addr1, u32 *reg_val1)
5643 {
5644         struct i40e_aq_desc desc;
5645         struct i40e_aqc_alternate_write *cmd_resp =
5646                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5647         enum i40e_status_code status;
5648
5649         if (reg_val0 == NULL)
5650                 return I40E_ERR_PARAM;
5651
5652         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5653         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5654         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5655
5656         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5657
5658         if (status == I40E_SUCCESS) {
5659                 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5660
5661                 if (reg_val1 != NULL)
5662                         *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5663         }
5664
5665         return status;
5666 }
5667
5668 /**
5669  * i40e_aq_alternate_read_indirect
5670  * @hw: pointer to the hardware structure
5671  * @addr: address of the alternate structure field
5672  * @dw_count: number of alternate structure fields to read
5673  * @buffer: pointer to the command buffer
5674  *
5675  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5676  * place them in 'buffer'. The buffer should be allocated by caller.
5677  *
5678  **/
5679 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5680                                 u32 addr, u32 dw_count, void *buffer)
5681 {
5682         struct i40e_aq_desc desc;
5683         struct i40e_aqc_alternate_ind_write *cmd_resp =
5684                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5685         enum i40e_status_code status;
5686
5687         if (buffer == NULL)
5688                 return I40E_ERR_PARAM;
5689
5690         /* Indirect command */
5691         i40e_fill_default_direct_cmd_desc(&desc,
5692                 i40e_aqc_opc_alternate_read_indirect);
5693
5694         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5695         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5696         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5697                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5698
5699         cmd_resp->address = CPU_TO_LE32(addr);
5700         cmd_resp->length = CPU_TO_LE32(dw_count);
5701
5702         status = i40e_asq_send_command(hw, &desc, buffer,
5703                                        I40E_LO_DWORD(4*dw_count), NULL);
5704
5705         return status;
5706 }
5707
5708 /**
5709  *  i40e_aq_alternate_clear
5710  *  @hw: pointer to the HW structure.
5711  *
5712  *  Clear the alternate structures of the port from which the function
5713  *  is called.
5714  *
5715  **/
5716 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5717 {
5718         struct i40e_aq_desc desc;
5719         enum i40e_status_code status;
5720
5721         i40e_fill_default_direct_cmd_desc(&desc,
5722                                           i40e_aqc_opc_alternate_clear_port);
5723
5724         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5725
5726         return status;
5727 }
5728
5729 /**
5730  *  i40e_aq_alternate_write_done
5731  *  @hw: pointer to the HW structure.
5732  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
5733  *  @reset_needed: indicates the SW should trigger GLOBAL reset
5734  *
5735  *  Indicates to the FW that alternate structures have been changed.
5736  *
5737  **/
5738 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
5739                 u8 bios_mode, bool *reset_needed)
5740 {
5741         struct i40e_aq_desc desc;
5742         struct i40e_aqc_alternate_write_done *cmd =
5743                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5744         enum i40e_status_code status;
5745
5746         if (reset_needed == NULL)
5747                 return I40E_ERR_PARAM;
5748
5749         i40e_fill_default_direct_cmd_desc(&desc,
5750                                           i40e_aqc_opc_alternate_write_done);
5751
5752         cmd->cmd_flags = CPU_TO_LE16(bios_mode);
5753
5754         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5755         if (!status && reset_needed)
5756                 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
5757                                  I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
5758
5759         return status;
5760 }
5761
5762 /**
5763  *  i40e_aq_set_oem_mode
5764  *  @hw: pointer to the HW structure.
5765  *  @oem_mode: the OEM mode to be used
5766  *
5767  *  Sets the device to a specific operating mode. Currently the only supported
5768  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
5769  *
5770  **/
5771 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
5772                 u8 oem_mode)
5773 {
5774         struct i40e_aq_desc desc;
5775         struct i40e_aqc_alternate_write_done *cmd =
5776                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5777         enum i40e_status_code status;
5778
5779         i40e_fill_default_direct_cmd_desc(&desc,
5780                                           i40e_aqc_opc_alternate_set_mode);
5781
5782         cmd->cmd_flags = CPU_TO_LE16(oem_mode);
5783
5784         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5785
5786         return status;
5787 }
5788
5789 /**
5790  * i40e_aq_resume_port_tx
5791  * @hw: pointer to the hardware structure
5792  * @cmd_details: pointer to command details structure or NULL
5793  *
5794  * Resume port's Tx traffic
5795  **/
5796 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
5797                                 struct i40e_asq_cmd_details *cmd_details)
5798 {
5799         struct i40e_aq_desc desc;
5800         enum i40e_status_code status;
5801
5802         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
5803
5804         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5805
5806         return status;
5807 }
5808
5809 /**
5810  * i40e_set_pci_config_data - store PCI bus info
5811  * @hw: pointer to hardware structure
5812  * @link_status: the link status word from PCI config space
5813  *
5814  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
5815  **/
5816 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
5817 {
5818         hw->bus.type = i40e_bus_type_pci_express;
5819
5820         switch (link_status & I40E_PCI_LINK_WIDTH) {
5821         case I40E_PCI_LINK_WIDTH_1:
5822                 hw->bus.width = i40e_bus_width_pcie_x1;
5823                 break;
5824         case I40E_PCI_LINK_WIDTH_2:
5825                 hw->bus.width = i40e_bus_width_pcie_x2;
5826                 break;
5827         case I40E_PCI_LINK_WIDTH_4:
5828                 hw->bus.width = i40e_bus_width_pcie_x4;
5829                 break;
5830         case I40E_PCI_LINK_WIDTH_8:
5831                 hw->bus.width = i40e_bus_width_pcie_x8;
5832                 break;
5833         default:
5834                 hw->bus.width = i40e_bus_width_unknown;
5835                 break;
5836         }
5837
5838         switch (link_status & I40E_PCI_LINK_SPEED) {
5839         case I40E_PCI_LINK_SPEED_2500:
5840                 hw->bus.speed = i40e_bus_speed_2500;
5841                 break;
5842         case I40E_PCI_LINK_SPEED_5000:
5843                 hw->bus.speed = i40e_bus_speed_5000;
5844                 break;
5845         case I40E_PCI_LINK_SPEED_8000:
5846                 hw->bus.speed = i40e_bus_speed_8000;
5847                 break;
5848         default:
5849                 hw->bus.speed = i40e_bus_speed_unknown;
5850                 break;
5851         }
5852 }
5853
5854 /**
5855  * i40e_aq_debug_dump
5856  * @hw: pointer to the hardware structure
5857  * @cluster_id: specific cluster to dump
5858  * @table_id: table id within cluster
5859  * @start_index: index of line in the block to read
5860  * @buff_size: dump buffer size
5861  * @buff: dump buffer
5862  * @ret_buff_size: actual buffer size returned
5863  * @ret_next_table: next block to read
5864  * @ret_next_index: next index to read
5865  *
5866  * Dump internal FW/HW data for debug purposes.
5867  *
5868  **/
5869 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
5870                                 u8 table_id, u32 start_index, u16 buff_size,
5871                                 void *buff, u16 *ret_buff_size,
5872                                 u8 *ret_next_table, u32 *ret_next_index,
5873                                 struct i40e_asq_cmd_details *cmd_details)
5874 {
5875         struct i40e_aq_desc desc;
5876         struct i40e_aqc_debug_dump_internals *cmd =
5877                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5878         struct i40e_aqc_debug_dump_internals *resp =
5879                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5880         enum i40e_status_code status;
5881
5882         if (buff_size == 0 || !buff)
5883                 return I40E_ERR_PARAM;
5884
5885         i40e_fill_default_direct_cmd_desc(&desc,
5886                                           i40e_aqc_opc_debug_dump_internals);
5887         /* Indirect Command */
5888         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5889         if (buff_size > I40E_AQ_LARGE_BUF)
5890                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5891
5892         cmd->cluster_id = cluster_id;
5893         cmd->table_id = table_id;
5894         cmd->idx = CPU_TO_LE32(start_index);
5895
5896         desc.datalen = CPU_TO_LE16(buff_size);
5897
5898         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5899         if (!status) {
5900                 if (ret_buff_size != NULL)
5901                         *ret_buff_size = LE16_TO_CPU(desc.datalen);
5902                 if (ret_next_table != NULL)
5903                         *ret_next_table = resp->table_id;
5904                 if (ret_next_index != NULL)
5905                         *ret_next_index = LE32_TO_CPU(resp->idx);
5906         }
5907
5908         return status;
5909 }
5910
5911 /**
5912  * i40e_read_bw_from_alt_ram
5913  * @hw: pointer to the hardware structure
5914  * @max_bw: pointer for max_bw read
5915  * @min_bw: pointer for min_bw read
5916  * @min_valid: pointer for bool that is true if min_bw is a valid value
5917  * @max_valid: pointer for bool that is true if max_bw is a valid value
5918  *
5919  * Read bw from the alternate ram for the given pf
5920  **/
5921 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
5922                                         u32 *max_bw, u32 *min_bw,
5923                                         bool *min_valid, bool *max_valid)
5924 {
5925         enum i40e_status_code status;
5926         u32 max_bw_addr, min_bw_addr;
5927
5928         /* Calculate the address of the min/max bw registers */
5929         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5930                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
5931                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5932         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5933                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
5934                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5935
5936         /* Read the bandwidths from alt ram */
5937         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
5938                                         min_bw_addr, min_bw);
5939
5940         if (*min_bw & I40E_ALT_BW_VALID_MASK)
5941                 *min_valid = true;
5942         else
5943                 *min_valid = false;
5944
5945         if (*max_bw & I40E_ALT_BW_VALID_MASK)
5946                 *max_valid = true;
5947         else
5948                 *max_valid = false;
5949
5950         return status;
5951 }
5952
5953 /**
5954  * i40e_aq_configure_partition_bw
5955  * @hw: pointer to the hardware structure
5956  * @bw_data: Buffer holding valid pfs and bw limits
5957  * @cmd_details: pointer to command details
5958  *
5959  * Configure partitions guaranteed/max bw
5960  **/
5961 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
5962                         struct i40e_aqc_configure_partition_bw_data *bw_data,
5963                         struct i40e_asq_cmd_details *cmd_details)
5964 {
5965         enum i40e_status_code status;
5966         struct i40e_aq_desc desc;
5967         u16 bwd_size = sizeof(*bw_data);
5968
5969         i40e_fill_default_direct_cmd_desc(&desc,
5970                                 i40e_aqc_opc_configure_partition_bw);
5971
5972         /* Indirect command */
5973         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5974         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5975
5976         if (bwd_size > I40E_AQ_LARGE_BUF)
5977                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5978
5979         desc.datalen = CPU_TO_LE16(bwd_size);
5980
5981         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
5982
5983         return status;
5984 }
5985
5986 /**
5987  * i40e_read_phy_register
5988  * @hw: pointer to the HW structure
5989  * @page: registers page number
5990  * @reg: register address in the page
5991  * @phy_adr: PHY address on MDIO interface
5992  * @value: PHY register value
5993  *
5994  * Reads specified PHY register value
5995  **/
5996 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
5997                                              u8 page, u16 reg, u8 phy_addr,
5998                                              u16 *value)
5999 {
6000         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6001         u32 command  = 0;
6002         u16 retry = 1000;
6003         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6004
6005         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6006                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6007                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6008                   (I40E_MDIO_OPCODE_ADDRESS) |
6009                   (I40E_MDIO_STCODE) |
6010                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6011                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6012         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6013         do {
6014                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6015                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6016                         status = I40E_SUCCESS;
6017                         break;
6018                 }
6019                 i40e_usec_delay(10);
6020                 retry--;
6021         } while (retry);
6022
6023         if (status) {
6024                 i40e_debug(hw, I40E_DEBUG_PHY,
6025                            "PHY: Can't write command to external PHY.\n");
6026                 goto phy_read_end;
6027         }
6028
6029         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6030                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6031                   (I40E_MDIO_OPCODE_READ) |
6032                   (I40E_MDIO_STCODE) |
6033                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6034                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6035         status = I40E_ERR_TIMEOUT;
6036         retry = 1000;
6037         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6038         do {
6039                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6040                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6041                         status = I40E_SUCCESS;
6042                         break;
6043                 }
6044                 i40e_usec_delay(10);
6045                 retry--;
6046         } while (retry);
6047
6048         if (!status) {
6049                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6050                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6051                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6052         } else {
6053                 i40e_debug(hw, I40E_DEBUG_PHY,
6054                            "PHY: Can't read register value from external PHY.\n");
6055         }
6056
6057 phy_read_end:
6058         return status;
6059 }
6060
6061 /**
6062  * i40e_write_phy_register
6063  * @hw: pointer to the HW structure
6064  * @page: registers page number
6065  * @reg: register address in the page
6066  * @phy_adr: PHY address on MDIO interface
6067  * @value: PHY register value
6068  *
6069  * Writes value to specified PHY register
6070  **/
6071 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6072                                               u8 page, u16 reg, u8 phy_addr,
6073                                               u16 value)
6074 {
6075         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6076         u32 command  = 0;
6077         u16 retry = 1000;
6078         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6079
6080         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6081                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6082                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6083                   (I40E_MDIO_OPCODE_ADDRESS) |
6084                   (I40E_MDIO_STCODE) |
6085                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6086                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6087         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6088         do {
6089                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6090                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6091                         status = I40E_SUCCESS;
6092                         break;
6093                 }
6094                 i40e_usec_delay(10);
6095                 retry--;
6096         } while (retry);
6097         if (status) {
6098                 i40e_debug(hw, I40E_DEBUG_PHY,
6099                            "PHY: Can't write command to external PHY.\n");
6100                 goto phy_write_end;
6101         }
6102
6103         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6104         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6105
6106         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6107                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6108                   (I40E_MDIO_OPCODE_WRITE) |
6109                   (I40E_MDIO_STCODE) |
6110                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6111                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6112         status = I40E_ERR_TIMEOUT;
6113         retry = 1000;
6114         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6115         do {
6116                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6117                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6118                         status = I40E_SUCCESS;
6119                         break;
6120                 }
6121                 i40e_usec_delay(10);
6122                 retry--;
6123         } while (retry);
6124
6125 phy_write_end:
6126         return status;
6127 }
6128
6129 /**
6130  * i40e_get_phy_address
6131  * @hw: pointer to the HW structure
6132  * @dev_num: PHY port num that address we want
6133  * @phy_addr: Returned PHY address
6134  *
6135  * Gets PHY address for current port
6136  **/
6137 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6138 {
6139         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6140         u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6141
6142         return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6143 }
6144
6145 /**
6146  * i40e_blink_phy_led
6147  * @hw: pointer to the HW structure
6148  * @time: time how long led will blinks in secs
6149  * @interval: gap between LED on and off in msecs
6150  *
6151  * Blinks PHY link LED
6152  **/
6153 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6154                                               u32 time, u32 interval)
6155 {
6156         enum i40e_status_code status = I40E_SUCCESS;
6157         u32 i;
6158         u16 led_ctl = 0;
6159         u16 gpio_led_port;
6160         u16 led_reg;
6161         u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6162         u8 phy_addr = 0;
6163         u8 port_num;
6164
6165         i = rd32(hw, I40E_PFGEN_PORTNUM);
6166         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6167         phy_addr = i40e_get_phy_address(hw, port_num);
6168
6169         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6170              led_addr++) {
6171                 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6172                                                 led_addr, phy_addr, &led_reg);
6173                 if (status)
6174                         goto phy_blinking_end;
6175                 led_ctl = led_reg;
6176                 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6177                         led_reg = 0;
6178                         status = i40e_write_phy_register(hw,
6179                                                          I40E_PHY_COM_REG_PAGE,
6180                                                          led_addr, phy_addr,
6181                                                          led_reg);
6182                         if (status)
6183                                 goto phy_blinking_end;
6184                         break;
6185                 }
6186         }
6187
6188         if (time > 0 && interval > 0) {
6189                 for (i = 0; i < time * 1000; i += interval) {
6190                         status = i40e_read_phy_register(hw,
6191                                                         I40E_PHY_COM_REG_PAGE,
6192                                                         led_addr, phy_addr,
6193                                                         &led_reg);
6194                         if (status)
6195                                 goto restore_config;
6196                         if (led_reg & I40E_PHY_LED_MANUAL_ON)
6197                                 led_reg = 0;
6198                         else
6199                                 led_reg = I40E_PHY_LED_MANUAL_ON;
6200                         status = i40e_write_phy_register(hw,
6201                                                          I40E_PHY_COM_REG_PAGE,
6202                                                          led_addr, phy_addr,
6203                                                          led_reg);
6204                         if (status)
6205                                 goto restore_config;
6206                         i40e_msec_delay(interval);
6207                 }
6208         }
6209
6210 restore_config:
6211         status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6212                                          phy_addr, led_ctl);
6213
6214 phy_blinking_end:
6215         return status;
6216 }
6217
6218 /**
6219  * i40e_led_get_phy - return current on/off mode
6220  * @hw: pointer to the hw struct
6221  * @led_addr: address of led register to use
6222  * @val: original value of register to use
6223  *
6224  **/
6225 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6226                                        u16 *val)
6227 {
6228         enum i40e_status_code status = I40E_SUCCESS;
6229         u16 gpio_led_port;
6230         u8 phy_addr = 0;
6231         u16 reg_val;
6232         u16 temp_addr;
6233         u8 port_num;
6234         u32 i;
6235
6236         temp_addr = I40E_PHY_LED_PROV_REG_1;
6237         i = rd32(hw, I40E_PFGEN_PORTNUM);
6238         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6239         phy_addr = i40e_get_phy_address(hw, port_num);
6240
6241         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6242              temp_addr++) {
6243                 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6244                                                 temp_addr, phy_addr, &reg_val);
6245                 if (status)
6246                         return status;
6247                 *val = reg_val;
6248                 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6249                         *led_addr = temp_addr;
6250                         break;
6251                 }
6252         }
6253         return status;
6254 }
6255
6256 /**
6257  * i40e_led_set_phy
6258  * @hw: pointer to the HW structure
6259  * @on: true or false
6260  * @mode: original val plus bit for set or ignore
6261  * Set led's on or off when controlled by the PHY
6262  *
6263  **/
6264 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6265                                        u16 led_addr, u32 mode)
6266 {
6267         enum i40e_status_code status = I40E_SUCCESS;
6268         u16 led_ctl = 0;
6269         u16 led_reg = 0;
6270         u8 phy_addr = 0;
6271         u8 port_num;
6272         u32 i;
6273
6274         i = rd32(hw, I40E_PFGEN_PORTNUM);
6275         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6276         phy_addr = i40e_get_phy_address(hw, port_num);
6277
6278         status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6279                                         phy_addr, &led_reg);
6280         if (status)
6281                 return status;
6282         led_ctl = led_reg;
6283         if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6284                 led_reg = 0;
6285                 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6286                                                  led_addr, phy_addr, led_reg);
6287                 if (status)
6288                         return status;
6289         }
6290         status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6291                                         led_addr, phy_addr, &led_reg);
6292         if (status)
6293                 goto restore_config;
6294         if (on)
6295                 led_reg = I40E_PHY_LED_MANUAL_ON;
6296         else
6297                 led_reg = 0;
6298         status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6299                                          led_addr, phy_addr, led_reg);
6300         if (status)
6301                 goto restore_config;
6302         if (mode & I40E_PHY_LED_MODE_ORIG) {
6303                 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6304                 status = i40e_write_phy_register(hw,
6305                                                  I40E_PHY_COM_REG_PAGE,
6306                                                  led_addr, phy_addr, led_ctl);
6307         }
6308         return status;
6309 restore_config:
6310         status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6311                                          phy_addr, led_ctl);
6312         return status;
6313 }
6314 #endif /* PF_DRIVER */
6315 #ifdef VF_DRIVER
6316
6317 /**
6318  * i40e_aq_send_msg_to_pf
6319  * @hw: pointer to the hardware structure
6320  * @v_opcode: opcodes for VF-PF communication
6321  * @v_retval: return error code
6322  * @msg: pointer to the msg buffer
6323  * @msglen: msg length
6324  * @cmd_details: pointer to command details
6325  *
6326  * Send message to PF driver using admin queue. By default, this message
6327  * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
6328  * completion before returning.
6329  **/
6330 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
6331                                 enum i40e_virtchnl_ops v_opcode,
6332                                 enum i40e_status_code v_retval,
6333                                 u8 *msg, u16 msglen,
6334                                 struct i40e_asq_cmd_details *cmd_details)
6335 {
6336         struct i40e_aq_desc desc;
6337         struct i40e_asq_cmd_details details;
6338         enum i40e_status_code status;
6339
6340         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
6341         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
6342         desc.cookie_high = CPU_TO_LE32(v_opcode);
6343         desc.cookie_low = CPU_TO_LE32(v_retval);
6344         if (msglen) {
6345                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
6346                                                 | I40E_AQ_FLAG_RD));
6347                 if (msglen > I40E_AQ_LARGE_BUF)
6348                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6349                 desc.datalen = CPU_TO_LE16(msglen);
6350         }
6351         if (!cmd_details) {
6352                 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
6353                 details.async = true;
6354                 cmd_details = &details;
6355         }
6356         status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
6357                                        msglen, cmd_details);
6358         return status;
6359 }
6360
6361 /**
6362  * i40e_vf_parse_hw_config
6363  * @hw: pointer to the hardware structure
6364  * @msg: pointer to the virtual channel VF resource structure
6365  *
6366  * Given a VF resource message from the PF, populate the hw struct
6367  * with appropriate information.
6368  **/
6369 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
6370                              struct i40e_virtchnl_vf_resource *msg)
6371 {
6372         struct i40e_virtchnl_vsi_resource *vsi_res;
6373         int i;
6374
6375         vsi_res = &msg->vsi_res[0];
6376
6377         hw->dev_caps.num_vsis = msg->num_vsis;
6378         hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
6379         hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
6380         hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
6381         hw->dev_caps.dcb = msg->vf_offload_flags &
6382                            I40E_VIRTCHNL_VF_OFFLOAD_L2;
6383         hw->dev_caps.fcoe = (msg->vf_offload_flags &
6384                              I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
6385         hw->dev_caps.iwarp = (msg->vf_offload_flags &
6386                               I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
6387         for (i = 0; i < msg->num_vsis; i++) {
6388                 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
6389                         i40e_memcpy(hw->mac.perm_addr,
6390                                     vsi_res->default_mac_addr,
6391                                     I40E_ETH_LENGTH_OF_ADDRESS,
6392                                     I40E_NONDMA_TO_NONDMA);
6393                         i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
6394                                     I40E_ETH_LENGTH_OF_ADDRESS,
6395                                     I40E_NONDMA_TO_NONDMA);
6396                 }
6397                 vsi_res++;
6398         }
6399 }
6400
6401 /**
6402  * i40e_vf_reset
6403  * @hw: pointer to the hardware structure
6404  *
6405  * Send a VF_RESET message to the PF. Does not wait for response from PF
6406  * as none will be forthcoming. Immediately after calling this function,
6407  * the admin queue should be shut down and (optionally) reinitialized.
6408  **/
6409 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
6410 {
6411         return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
6412                                       I40E_SUCCESS, NULL, 0, NULL);
6413 }
6414 #endif /* VF_DRIVER */
6415 #ifdef X722_SUPPORT
6416
6417 /**
6418  * i40e_aq_set_arp_proxy_config
6419  * @hw: pointer to the HW structure
6420  * @proxy_config - pointer to proxy config command table struct
6421  * @cmd_details: pointer to command details
6422  *
6423  * Set ARP offload parameters from pre-populated
6424  * i40e_aqc_arp_proxy_data struct
6425  **/
6426 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
6427                                 struct i40e_aqc_arp_proxy_data *proxy_config,
6428                                 struct i40e_asq_cmd_details *cmd_details)
6429 {
6430         struct i40e_aq_desc desc;
6431         enum i40e_status_code status;
6432
6433         if (!proxy_config)
6434                 return I40E_ERR_PARAM;
6435
6436         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
6437
6438         desc.params.external.addr_high =
6439                                   CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
6440         desc.params.external.addr_low =
6441                                   CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
6442
6443         status = i40e_asq_send_command(hw, &desc, proxy_config,
6444                                        sizeof(struct i40e_aqc_arp_proxy_data),
6445                                        cmd_details);
6446
6447         return status;
6448 }
6449
6450 /**
6451  * i40e_aq_opc_set_ns_proxy_table_entry
6452  * @hw: pointer to the HW structure
6453  * @ns_proxy_table_entry: pointer to NS table entry command struct
6454  * @cmd_details: pointer to command details
6455  *
6456  * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
6457  * from pre-populated i40e_aqc_ns_proxy_data struct
6458  **/
6459 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
6460                         struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
6461                         struct i40e_asq_cmd_details *cmd_details)
6462 {
6463         struct i40e_aq_desc desc;
6464         enum i40e_status_code status;
6465
6466         if (!ns_proxy_table_entry)
6467                 return I40E_ERR_PARAM;
6468
6469         i40e_fill_default_direct_cmd_desc(&desc,
6470                                 i40e_aqc_opc_set_ns_proxy_table_entry);
6471
6472         desc.params.external.addr_high =
6473                 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
6474         desc.params.external.addr_low =
6475                 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
6476
6477         status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
6478                                        sizeof(struct i40e_aqc_ns_proxy_data),
6479                                        cmd_details);
6480
6481         return status;
6482 }
6483
6484 /**
6485  * i40e_aq_set_clear_wol_filter
6486  * @hw: pointer to the hw struct
6487  * @filter_index: index of filter to modify (0-7)
6488  * @filter: buffer containing filter to be set
6489  * @set_filter: true to set filter, false to clear filter
6490  * @no_wol_tco: if true, pass through packets cannot cause wake-up
6491  *              if false, pass through packets may cause wake-up
6492  * @filter_valid: true if filter action is valid
6493  * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
6494  * @cmd_details: pointer to command details structure or NULL
6495  *
6496  * Set or clear WoL filter for port attached to the PF
6497  **/
6498 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
6499                                 u8 filter_index,
6500                                 struct i40e_aqc_set_wol_filter_data *filter,
6501                                 bool set_filter, bool no_wol_tco,
6502                                 bool filter_valid, bool no_wol_tco_valid,
6503                                 struct i40e_asq_cmd_details *cmd_details)
6504 {
6505         struct i40e_aq_desc desc;
6506         struct i40e_aqc_set_wol_filter *cmd =
6507                 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
6508         enum i40e_status_code status;
6509         u16 cmd_flags = 0;
6510         u16 valid_flags = 0;
6511         u16 buff_len = 0;
6512
6513         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
6514
6515         if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
6516                 return  I40E_ERR_PARAM;
6517         cmd->filter_index = CPU_TO_LE16(filter_index);
6518
6519         if (set_filter) {
6520                 if (!filter)
6521                         return  I40E_ERR_PARAM;
6522                 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
6523                 buff_len = sizeof(*filter);
6524         }
6525         if (no_wol_tco)
6526                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
6527         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
6528
6529         if (filter_valid)
6530                 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
6531         if (no_wol_tco_valid)
6532                 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
6533         cmd->valid_flags = CPU_TO_LE16(valid_flags);
6534
6535         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
6536         cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
6537
6538         status = i40e_asq_send_command(hw, &desc, filter,
6539                                        buff_len, cmd_details);
6540
6541         return status;
6542 }
6543
6544 /**
6545  * i40e_aq_get_wake_event_reason
6546  * @hw: pointer to the hw struct
6547  * @wake_reason: return value, index of matching filter
6548  * @cmd_details: pointer to command details structure or NULL
6549  *
6550  * Get information for the reason of a Wake Up event
6551  **/
6552 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
6553                                 u16 *wake_reason,
6554                                 struct i40e_asq_cmd_details *cmd_details)
6555 {
6556         struct i40e_aq_desc desc;
6557         struct i40e_aqc_get_wake_reason_completion *resp =
6558                 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
6559         enum i40e_status_code status;
6560
6561         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
6562
6563         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6564
6565         if (status == I40E_SUCCESS)
6566                 *wake_reason = LE16_TO_CPU(resp->wake_reason);
6567
6568         return status;
6569 }
6570
6571 #endif /* X722_SUPPORT */