1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2018
6 #include "i40e_adminq.h"
7 #include "i40e_prototype.h"
11 * i40e_set_mac_type - Sets MAC type
12 * @hw: pointer to the HW structure
14 * This function sets the mac type of the adapter based on the
15 * vendor ID and device ID stored in the hw structure.
17 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
19 enum i40e_status_code status = I40E_SUCCESS;
21 DEBUGFUNC("i40e_set_mac_type\n");
23 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
24 switch (hw->device_id) {
25 case I40E_DEV_ID_SFP_XL710:
26 case I40E_DEV_ID_QEMU:
27 case I40E_DEV_ID_KX_B:
28 case I40E_DEV_ID_KX_C:
29 case I40E_DEV_ID_QSFP_A:
30 case I40E_DEV_ID_QSFP_B:
31 case I40E_DEV_ID_QSFP_C:
32 case I40E_DEV_ID_10G_BASE_T:
33 case I40E_DEV_ID_10G_BASE_T4:
34 case I40E_DEV_ID_10G_BASE_T_BC:
35 case I40E_DEV_ID_10G_B:
36 case I40E_DEV_ID_10G_SFP:
37 case I40E_DEV_ID_20G_KR2:
38 case I40E_DEV_ID_20G_KR2_A:
39 case I40E_DEV_ID_25G_B:
40 case I40E_DEV_ID_25G_SFP28:
41 case I40E_DEV_ID_X710_N3000:
42 case I40E_DEV_ID_XXV710_N3000:
43 hw->mac.type = I40E_MAC_XL710;
45 #ifdef X722_A0_SUPPORT
46 case I40E_DEV_ID_X722_A0:
48 case I40E_DEV_ID_KX_X722:
49 case I40E_DEV_ID_QSFP_X722:
50 case I40E_DEV_ID_SFP_X722:
51 case I40E_DEV_ID_1G_BASE_T_X722:
52 case I40E_DEV_ID_10G_BASE_T_X722:
53 case I40E_DEV_ID_SFP_I_X722:
54 hw->mac.type = I40E_MAC_X722;
56 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
57 case I40E_DEV_ID_X722_VF:
58 #ifdef X722_A0_SUPPORT
59 case I40E_DEV_ID_X722_A0_VF:
61 hw->mac.type = I40E_MAC_X722_VF;
63 #endif /* INTEGRATED_VF || VF_DRIVER */
64 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
66 case I40E_DEV_ID_VF_HV:
67 case I40E_DEV_ID_ADAPTIVE_VF:
68 hw->mac.type = I40E_MAC_VF;
72 hw->mac.type = I40E_MAC_GENERIC;
76 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
79 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
80 hw->mac.type, status);
85 * i40e_aq_str - convert AQ err code to a string
86 * @hw: pointer to the HW structure
87 * @aq_err: the AQ error code to convert
89 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
94 case I40E_AQ_RC_EPERM:
95 return "I40E_AQ_RC_EPERM";
96 case I40E_AQ_RC_ENOENT:
97 return "I40E_AQ_RC_ENOENT";
98 case I40E_AQ_RC_ESRCH:
99 return "I40E_AQ_RC_ESRCH";
100 case I40E_AQ_RC_EINTR:
101 return "I40E_AQ_RC_EINTR";
103 return "I40E_AQ_RC_EIO";
104 case I40E_AQ_RC_ENXIO:
105 return "I40E_AQ_RC_ENXIO";
106 case I40E_AQ_RC_E2BIG:
107 return "I40E_AQ_RC_E2BIG";
108 case I40E_AQ_RC_EAGAIN:
109 return "I40E_AQ_RC_EAGAIN";
110 case I40E_AQ_RC_ENOMEM:
111 return "I40E_AQ_RC_ENOMEM";
112 case I40E_AQ_RC_EACCES:
113 return "I40E_AQ_RC_EACCES";
114 case I40E_AQ_RC_EFAULT:
115 return "I40E_AQ_RC_EFAULT";
116 case I40E_AQ_RC_EBUSY:
117 return "I40E_AQ_RC_EBUSY";
118 case I40E_AQ_RC_EEXIST:
119 return "I40E_AQ_RC_EEXIST";
120 case I40E_AQ_RC_EINVAL:
121 return "I40E_AQ_RC_EINVAL";
122 case I40E_AQ_RC_ENOTTY:
123 return "I40E_AQ_RC_ENOTTY";
124 case I40E_AQ_RC_ENOSPC:
125 return "I40E_AQ_RC_ENOSPC";
126 case I40E_AQ_RC_ENOSYS:
127 return "I40E_AQ_RC_ENOSYS";
128 case I40E_AQ_RC_ERANGE:
129 return "I40E_AQ_RC_ERANGE";
130 case I40E_AQ_RC_EFLUSHED:
131 return "I40E_AQ_RC_EFLUSHED";
132 case I40E_AQ_RC_BAD_ADDR:
133 return "I40E_AQ_RC_BAD_ADDR";
134 case I40E_AQ_RC_EMODE:
135 return "I40E_AQ_RC_EMODE";
136 case I40E_AQ_RC_EFBIG:
137 return "I40E_AQ_RC_EFBIG";
140 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
145 * i40e_stat_str - convert status err code to a string
146 * @hw: pointer to the HW structure
147 * @stat_err: the status error code to convert
149 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
155 return "I40E_ERR_NVM";
156 case I40E_ERR_NVM_CHECKSUM:
157 return "I40E_ERR_NVM_CHECKSUM";
159 return "I40E_ERR_PHY";
160 case I40E_ERR_CONFIG:
161 return "I40E_ERR_CONFIG";
163 return "I40E_ERR_PARAM";
164 case I40E_ERR_MAC_TYPE:
165 return "I40E_ERR_MAC_TYPE";
166 case I40E_ERR_UNKNOWN_PHY:
167 return "I40E_ERR_UNKNOWN_PHY";
168 case I40E_ERR_LINK_SETUP:
169 return "I40E_ERR_LINK_SETUP";
170 case I40E_ERR_ADAPTER_STOPPED:
171 return "I40E_ERR_ADAPTER_STOPPED";
172 case I40E_ERR_INVALID_MAC_ADDR:
173 return "I40E_ERR_INVALID_MAC_ADDR";
174 case I40E_ERR_DEVICE_NOT_SUPPORTED:
175 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
176 case I40E_ERR_MASTER_REQUESTS_PENDING:
177 return "I40E_ERR_MASTER_REQUESTS_PENDING";
178 case I40E_ERR_INVALID_LINK_SETTINGS:
179 return "I40E_ERR_INVALID_LINK_SETTINGS";
180 case I40E_ERR_AUTONEG_NOT_COMPLETE:
181 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
182 case I40E_ERR_RESET_FAILED:
183 return "I40E_ERR_RESET_FAILED";
184 case I40E_ERR_SWFW_SYNC:
185 return "I40E_ERR_SWFW_SYNC";
186 case I40E_ERR_NO_AVAILABLE_VSI:
187 return "I40E_ERR_NO_AVAILABLE_VSI";
188 case I40E_ERR_NO_MEMORY:
189 return "I40E_ERR_NO_MEMORY";
190 case I40E_ERR_BAD_PTR:
191 return "I40E_ERR_BAD_PTR";
192 case I40E_ERR_RING_FULL:
193 return "I40E_ERR_RING_FULL";
194 case I40E_ERR_INVALID_PD_ID:
195 return "I40E_ERR_INVALID_PD_ID";
196 case I40E_ERR_INVALID_QP_ID:
197 return "I40E_ERR_INVALID_QP_ID";
198 case I40E_ERR_INVALID_CQ_ID:
199 return "I40E_ERR_INVALID_CQ_ID";
200 case I40E_ERR_INVALID_CEQ_ID:
201 return "I40E_ERR_INVALID_CEQ_ID";
202 case I40E_ERR_INVALID_AEQ_ID:
203 return "I40E_ERR_INVALID_AEQ_ID";
204 case I40E_ERR_INVALID_SIZE:
205 return "I40E_ERR_INVALID_SIZE";
206 case I40E_ERR_INVALID_ARP_INDEX:
207 return "I40E_ERR_INVALID_ARP_INDEX";
208 case I40E_ERR_INVALID_FPM_FUNC_ID:
209 return "I40E_ERR_INVALID_FPM_FUNC_ID";
210 case I40E_ERR_QP_INVALID_MSG_SIZE:
211 return "I40E_ERR_QP_INVALID_MSG_SIZE";
212 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
213 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
214 case I40E_ERR_INVALID_FRAG_COUNT:
215 return "I40E_ERR_INVALID_FRAG_COUNT";
216 case I40E_ERR_QUEUE_EMPTY:
217 return "I40E_ERR_QUEUE_EMPTY";
218 case I40E_ERR_INVALID_ALIGNMENT:
219 return "I40E_ERR_INVALID_ALIGNMENT";
220 case I40E_ERR_FLUSHED_QUEUE:
221 return "I40E_ERR_FLUSHED_QUEUE";
222 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
223 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
224 case I40E_ERR_INVALID_IMM_DATA_SIZE:
225 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
226 case I40E_ERR_TIMEOUT:
227 return "I40E_ERR_TIMEOUT";
228 case I40E_ERR_OPCODE_MISMATCH:
229 return "I40E_ERR_OPCODE_MISMATCH";
230 case I40E_ERR_CQP_COMPL_ERROR:
231 return "I40E_ERR_CQP_COMPL_ERROR";
232 case I40E_ERR_INVALID_VF_ID:
233 return "I40E_ERR_INVALID_VF_ID";
234 case I40E_ERR_INVALID_HMCFN_ID:
235 return "I40E_ERR_INVALID_HMCFN_ID";
236 case I40E_ERR_BACKING_PAGE_ERROR:
237 return "I40E_ERR_BACKING_PAGE_ERROR";
238 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
239 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
240 case I40E_ERR_INVALID_PBLE_INDEX:
241 return "I40E_ERR_INVALID_PBLE_INDEX";
242 case I40E_ERR_INVALID_SD_INDEX:
243 return "I40E_ERR_INVALID_SD_INDEX";
244 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
245 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
246 case I40E_ERR_INVALID_SD_TYPE:
247 return "I40E_ERR_INVALID_SD_TYPE";
248 case I40E_ERR_MEMCPY_FAILED:
249 return "I40E_ERR_MEMCPY_FAILED";
250 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
251 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
252 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
253 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
254 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
255 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
256 case I40E_ERR_SRQ_ENABLED:
257 return "I40E_ERR_SRQ_ENABLED";
258 case I40E_ERR_ADMIN_QUEUE_ERROR:
259 return "I40E_ERR_ADMIN_QUEUE_ERROR";
260 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
261 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
262 case I40E_ERR_BUF_TOO_SHORT:
263 return "I40E_ERR_BUF_TOO_SHORT";
264 case I40E_ERR_ADMIN_QUEUE_FULL:
265 return "I40E_ERR_ADMIN_QUEUE_FULL";
266 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
267 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
268 case I40E_ERR_BAD_IWARP_CQE:
269 return "I40E_ERR_BAD_IWARP_CQE";
270 case I40E_ERR_NVM_BLANK_MODE:
271 return "I40E_ERR_NVM_BLANK_MODE";
272 case I40E_ERR_NOT_IMPLEMENTED:
273 return "I40E_ERR_NOT_IMPLEMENTED";
274 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
275 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
276 case I40E_ERR_DIAG_TEST_FAILED:
277 return "I40E_ERR_DIAG_TEST_FAILED";
278 case I40E_ERR_NOT_READY:
279 return "I40E_ERR_NOT_READY";
280 case I40E_NOT_SUPPORTED:
281 return "I40E_NOT_SUPPORTED";
282 case I40E_ERR_FIRMWARE_API_VERSION:
283 return "I40E_ERR_FIRMWARE_API_VERSION";
284 case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR:
285 return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR";
288 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
294 * @hw: debug mask related to admin queue
296 * @desc: pointer to admin queue descriptor
297 * @buffer: pointer to command buffer
298 * @buf_len: max length of buffer
300 * Dumps debug log about adminq command with descriptor contents.
302 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
303 void *buffer, u16 buf_len)
305 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
306 u32 effective_mask = hw->debug_mask & mask;
307 u8 *buf = (u8 *)buffer;
311 if (!effective_mask || !desc)
314 len = LE16_TO_CPU(aq_desc->datalen);
316 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
317 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
318 LE16_TO_CPU(aq_desc->opcode),
319 LE16_TO_CPU(aq_desc->flags),
320 LE16_TO_CPU(aq_desc->datalen),
321 LE16_TO_CPU(aq_desc->retval));
322 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
323 "\tcookie (h,l) 0x%08X 0x%08X\n",
324 LE32_TO_CPU(aq_desc->cookie_high),
325 LE32_TO_CPU(aq_desc->cookie_low));
326 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
327 "\tparam (0,1) 0x%08X 0x%08X\n",
328 LE32_TO_CPU(aq_desc->params.internal.param0),
329 LE32_TO_CPU(aq_desc->params.internal.param1));
330 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
331 "\taddr (h,l) 0x%08X 0x%08X\n",
332 LE32_TO_CPU(aq_desc->params.external.addr_high),
333 LE32_TO_CPU(aq_desc->params.external.addr_low));
335 if (buffer && (buf_len != 0) && (len != 0) &&
336 (effective_mask & I40E_DEBUG_AQ_DESC_BUFFER)) {
337 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
340 /* write the full 16-byte chunks */
341 for (i = 0; i < (len - 16); i += 16)
343 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
344 i, buf[i], buf[i+1], buf[i+2], buf[i+3],
345 buf[i+4], buf[i+5], buf[i+6], buf[i+7],
346 buf[i+8], buf[i+9], buf[i+10], buf[i+11],
347 buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
348 /* the most we could have left is 16 bytes, pad with zeros */
354 memset(d_buf, 0, sizeof(d_buf));
355 for (j = 0; i < len; j++, i++)
358 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
359 i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
360 d_buf[4], d_buf[5], d_buf[6], d_buf[7],
361 d_buf[8], d_buf[9], d_buf[10], d_buf[11],
362 d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
368 * i40e_check_asq_alive
369 * @hw: pointer to the hw struct
371 * Returns true if Queue is enabled else false.
373 bool i40e_check_asq_alive(struct i40e_hw *hw)
379 return !!(rd32(hw, hw->aq.asq.len) &
380 I40E_PF_ATQLEN_ATQENABLE_MASK);
382 return !!(rd32(hw, hw->aq.asq.len) &
383 I40E_PF_ATQLEN_ATQENABLE_MASK);
384 #endif /* INTEGRATED_VF */
385 #endif /* PF_DRIVER */
389 return !!(rd32(hw, hw->aq.asq.len) &
390 I40E_VF_ATQLEN1_ATQENABLE_MASK);
392 return !!(rd32(hw, hw->aq.asq.len) &
393 I40E_VF_ATQLEN1_ATQENABLE_MASK);
394 #endif /* INTEGRATED_VF */
395 #endif /* VF_DRIVER */
400 * i40e_aq_queue_shutdown
401 * @hw: pointer to the hw struct
402 * @unloading: is the driver unloading itself
404 * Tell the Firmware that we're shutting down the AdminQ and whether
405 * or not the driver is unloading as well.
407 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
410 struct i40e_aq_desc desc;
411 struct i40e_aqc_queue_shutdown *cmd =
412 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
413 enum i40e_status_code status;
415 i40e_fill_default_direct_cmd_desc(&desc,
416 i40e_aqc_opc_queue_shutdown);
419 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
420 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
426 * i40e_aq_get_set_rss_lut
427 * @hw: pointer to the hardware structure
428 * @vsi_id: vsi fw index
429 * @pf_lut: for PF table set true, for VSI table set false
430 * @lut: pointer to the lut buffer provided by the caller
431 * @lut_size: size of the lut buffer
432 * @set: set true to set the table, false to get the table
434 * Internal function to get or set RSS look up table
436 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
437 u16 vsi_id, bool pf_lut,
438 u8 *lut, u16 lut_size,
441 enum i40e_status_code status;
442 struct i40e_aq_desc desc;
443 struct i40e_aqc_get_set_rss_lut *cmd_resp =
444 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
447 i40e_fill_default_direct_cmd_desc(&desc,
448 i40e_aqc_opc_set_rss_lut);
450 i40e_fill_default_direct_cmd_desc(&desc,
451 i40e_aqc_opc_get_rss_lut);
453 /* Indirect command */
454 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
455 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
458 CPU_TO_LE16((u16)((vsi_id <<
459 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
460 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
461 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
464 cmd_resp->flags |= CPU_TO_LE16((u16)
465 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
466 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
467 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
469 cmd_resp->flags |= CPU_TO_LE16((u16)
470 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
471 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
472 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
474 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
480 * i40e_aq_get_rss_lut
481 * @hw: pointer to the hardware structure
482 * @vsi_id: vsi fw index
483 * @pf_lut: for PF table set true, for VSI table set false
484 * @lut: pointer to the lut buffer provided by the caller
485 * @lut_size: size of the lut buffer
487 * get the RSS lookup table, PF or VSI type
489 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
490 bool pf_lut, u8 *lut, u16 lut_size)
492 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
497 * i40e_aq_set_rss_lut
498 * @hw: pointer to the hardware structure
499 * @vsi_id: vsi fw index
500 * @pf_lut: for PF table set true, for VSI table set false
501 * @lut: pointer to the lut buffer provided by the caller
502 * @lut_size: size of the lut buffer
504 * set the RSS lookup table, PF or VSI type
506 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
507 bool pf_lut, u8 *lut, u16 lut_size)
509 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
513 * i40e_aq_get_set_rss_key
514 * @hw: pointer to the hw struct
515 * @vsi_id: vsi fw index
516 * @key: pointer to key info struct
517 * @set: set true to set the key, false to get the key
519 * get the RSS key per VSI
521 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
523 struct i40e_aqc_get_set_rss_key_data *key,
526 enum i40e_status_code status;
527 struct i40e_aq_desc desc;
528 struct i40e_aqc_get_set_rss_key *cmd_resp =
529 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
530 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
533 i40e_fill_default_direct_cmd_desc(&desc,
534 i40e_aqc_opc_set_rss_key);
536 i40e_fill_default_direct_cmd_desc(&desc,
537 i40e_aqc_opc_get_rss_key);
539 /* Indirect command */
540 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
541 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
544 CPU_TO_LE16((u16)((vsi_id <<
545 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
546 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
547 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
549 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
555 * i40e_aq_get_rss_key
556 * @hw: pointer to the hw struct
557 * @vsi_id: vsi fw index
558 * @key: pointer to key info struct
561 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
563 struct i40e_aqc_get_set_rss_key_data *key)
565 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
569 * i40e_aq_set_rss_key
570 * @hw: pointer to the hw struct
571 * @vsi_id: vsi fw index
572 * @key: pointer to key info struct
574 * set the RSS key per VSI
576 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
578 struct i40e_aqc_get_set_rss_key_data *key)
580 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
583 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
584 * hardware to a bit-field that can be used by SW to more easily determine the
587 * Macros are used to shorten the table lines and make this table human
590 * We store the PTYPE in the top byte of the bit field - this is just so that
591 * we can check that the table doesn't have a row missing, as the index into
592 * the table should be the PTYPE.
596 * IF NOT i40e_ptype_lookup[ptype].known
599 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
600 * Use the rest of the fields to look at the tunnels, inner protocols, etc
602 * Use the enum i40e_rx_l2_ptype to decode the packet type
606 /* macro to make the table lines short */
607 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
610 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
611 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
612 I40E_RX_PTYPE_##OUTER_FRAG, \
613 I40E_RX_PTYPE_TUNNEL_##T, \
614 I40E_RX_PTYPE_TUNNEL_END_##TE, \
615 I40E_RX_PTYPE_##TEF, \
616 I40E_RX_PTYPE_INNER_PROT_##I, \
617 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
619 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
620 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
622 /* shorter macros makes the table fit but are terse */
623 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
624 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
625 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
627 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
628 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
629 /* L2 Packet types */
630 I40E_PTT_UNUSED_ENTRY(0),
631 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
632 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
633 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
634 I40E_PTT_UNUSED_ENTRY(4),
635 I40E_PTT_UNUSED_ENTRY(5),
636 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
637 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
638 I40E_PTT_UNUSED_ENTRY(8),
639 I40E_PTT_UNUSED_ENTRY(9),
640 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
641 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
642 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
643 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
644 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
645 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
646 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
647 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
648 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
649 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
650 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
651 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
653 /* Non Tunneled IPv4 */
654 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
655 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
656 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
657 I40E_PTT_UNUSED_ENTRY(25),
658 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
659 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
660 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
663 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
664 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
665 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
666 I40E_PTT_UNUSED_ENTRY(32),
667 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
668 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
669 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
672 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
673 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
674 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
675 I40E_PTT_UNUSED_ENTRY(39),
676 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
677 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
678 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
680 /* IPv4 --> GRE/NAT */
681 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
683 /* IPv4 --> GRE/NAT --> IPv4 */
684 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
685 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
686 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
687 I40E_PTT_UNUSED_ENTRY(47),
688 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
689 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
690 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
692 /* IPv4 --> GRE/NAT --> IPv6 */
693 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
694 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
695 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
696 I40E_PTT_UNUSED_ENTRY(54),
697 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
698 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
699 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
701 /* IPv4 --> GRE/NAT --> MAC */
702 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
704 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
705 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
706 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
707 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
708 I40E_PTT_UNUSED_ENTRY(62),
709 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
710 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
711 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
713 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
714 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
715 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
716 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
717 I40E_PTT_UNUSED_ENTRY(69),
718 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
719 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
720 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
722 /* IPv4 --> GRE/NAT --> MAC/VLAN */
723 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
725 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
726 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
727 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
728 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
729 I40E_PTT_UNUSED_ENTRY(77),
730 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
731 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
732 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
734 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
735 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
736 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
737 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
738 I40E_PTT_UNUSED_ENTRY(84),
739 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
740 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
741 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
743 /* Non Tunneled IPv6 */
744 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
745 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
746 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4),
747 I40E_PTT_UNUSED_ENTRY(91),
748 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
749 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
750 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
753 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
754 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
755 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
756 I40E_PTT_UNUSED_ENTRY(98),
757 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
758 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
759 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
762 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
763 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
764 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
765 I40E_PTT_UNUSED_ENTRY(105),
766 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
767 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
768 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
770 /* IPv6 --> GRE/NAT */
771 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
773 /* IPv6 --> GRE/NAT -> IPv4 */
774 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
775 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
776 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
777 I40E_PTT_UNUSED_ENTRY(113),
778 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
779 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
780 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
782 /* IPv6 --> GRE/NAT -> IPv6 */
783 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
784 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
785 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
786 I40E_PTT_UNUSED_ENTRY(120),
787 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
788 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
789 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
791 /* IPv6 --> GRE/NAT -> MAC */
792 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
794 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
795 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
796 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
797 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
798 I40E_PTT_UNUSED_ENTRY(128),
799 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
800 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
801 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
803 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
804 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
805 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
806 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
807 I40E_PTT_UNUSED_ENTRY(135),
808 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
809 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
810 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
812 /* IPv6 --> GRE/NAT -> MAC/VLAN */
813 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
815 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
816 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
817 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
818 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
819 I40E_PTT_UNUSED_ENTRY(143),
820 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
821 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
822 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
824 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
825 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
826 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
827 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
828 I40E_PTT_UNUSED_ENTRY(150),
829 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
830 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
831 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
834 I40E_PTT_UNUSED_ENTRY(154),
835 I40E_PTT_UNUSED_ENTRY(155),
836 I40E_PTT_UNUSED_ENTRY(156),
837 I40E_PTT_UNUSED_ENTRY(157),
838 I40E_PTT_UNUSED_ENTRY(158),
839 I40E_PTT_UNUSED_ENTRY(159),
841 I40E_PTT_UNUSED_ENTRY(160),
842 I40E_PTT_UNUSED_ENTRY(161),
843 I40E_PTT_UNUSED_ENTRY(162),
844 I40E_PTT_UNUSED_ENTRY(163),
845 I40E_PTT_UNUSED_ENTRY(164),
846 I40E_PTT_UNUSED_ENTRY(165),
847 I40E_PTT_UNUSED_ENTRY(166),
848 I40E_PTT_UNUSED_ENTRY(167),
849 I40E_PTT_UNUSED_ENTRY(168),
850 I40E_PTT_UNUSED_ENTRY(169),
852 I40E_PTT_UNUSED_ENTRY(170),
853 I40E_PTT_UNUSED_ENTRY(171),
854 I40E_PTT_UNUSED_ENTRY(172),
855 I40E_PTT_UNUSED_ENTRY(173),
856 I40E_PTT_UNUSED_ENTRY(174),
857 I40E_PTT_UNUSED_ENTRY(175),
858 I40E_PTT_UNUSED_ENTRY(176),
859 I40E_PTT_UNUSED_ENTRY(177),
860 I40E_PTT_UNUSED_ENTRY(178),
861 I40E_PTT_UNUSED_ENTRY(179),
863 I40E_PTT_UNUSED_ENTRY(180),
864 I40E_PTT_UNUSED_ENTRY(181),
865 I40E_PTT_UNUSED_ENTRY(182),
866 I40E_PTT_UNUSED_ENTRY(183),
867 I40E_PTT_UNUSED_ENTRY(184),
868 I40E_PTT_UNUSED_ENTRY(185),
869 I40E_PTT_UNUSED_ENTRY(186),
870 I40E_PTT_UNUSED_ENTRY(187),
871 I40E_PTT_UNUSED_ENTRY(188),
872 I40E_PTT_UNUSED_ENTRY(189),
874 I40E_PTT_UNUSED_ENTRY(190),
875 I40E_PTT_UNUSED_ENTRY(191),
876 I40E_PTT_UNUSED_ENTRY(192),
877 I40E_PTT_UNUSED_ENTRY(193),
878 I40E_PTT_UNUSED_ENTRY(194),
879 I40E_PTT_UNUSED_ENTRY(195),
880 I40E_PTT_UNUSED_ENTRY(196),
881 I40E_PTT_UNUSED_ENTRY(197),
882 I40E_PTT_UNUSED_ENTRY(198),
883 I40E_PTT_UNUSED_ENTRY(199),
885 I40E_PTT_UNUSED_ENTRY(200),
886 I40E_PTT_UNUSED_ENTRY(201),
887 I40E_PTT_UNUSED_ENTRY(202),
888 I40E_PTT_UNUSED_ENTRY(203),
889 I40E_PTT_UNUSED_ENTRY(204),
890 I40E_PTT_UNUSED_ENTRY(205),
891 I40E_PTT_UNUSED_ENTRY(206),
892 I40E_PTT_UNUSED_ENTRY(207),
893 I40E_PTT_UNUSED_ENTRY(208),
894 I40E_PTT_UNUSED_ENTRY(209),
896 I40E_PTT_UNUSED_ENTRY(210),
897 I40E_PTT_UNUSED_ENTRY(211),
898 I40E_PTT_UNUSED_ENTRY(212),
899 I40E_PTT_UNUSED_ENTRY(213),
900 I40E_PTT_UNUSED_ENTRY(214),
901 I40E_PTT_UNUSED_ENTRY(215),
902 I40E_PTT_UNUSED_ENTRY(216),
903 I40E_PTT_UNUSED_ENTRY(217),
904 I40E_PTT_UNUSED_ENTRY(218),
905 I40E_PTT_UNUSED_ENTRY(219),
907 I40E_PTT_UNUSED_ENTRY(220),
908 I40E_PTT_UNUSED_ENTRY(221),
909 I40E_PTT_UNUSED_ENTRY(222),
910 I40E_PTT_UNUSED_ENTRY(223),
911 I40E_PTT_UNUSED_ENTRY(224),
912 I40E_PTT_UNUSED_ENTRY(225),
913 I40E_PTT_UNUSED_ENTRY(226),
914 I40E_PTT_UNUSED_ENTRY(227),
915 I40E_PTT_UNUSED_ENTRY(228),
916 I40E_PTT_UNUSED_ENTRY(229),
918 I40E_PTT_UNUSED_ENTRY(230),
919 I40E_PTT_UNUSED_ENTRY(231),
920 I40E_PTT_UNUSED_ENTRY(232),
921 I40E_PTT_UNUSED_ENTRY(233),
922 I40E_PTT_UNUSED_ENTRY(234),
923 I40E_PTT_UNUSED_ENTRY(235),
924 I40E_PTT_UNUSED_ENTRY(236),
925 I40E_PTT_UNUSED_ENTRY(237),
926 I40E_PTT_UNUSED_ENTRY(238),
927 I40E_PTT_UNUSED_ENTRY(239),
929 I40E_PTT_UNUSED_ENTRY(240),
930 I40E_PTT_UNUSED_ENTRY(241),
931 I40E_PTT_UNUSED_ENTRY(242),
932 I40E_PTT_UNUSED_ENTRY(243),
933 I40E_PTT_UNUSED_ENTRY(244),
934 I40E_PTT_UNUSED_ENTRY(245),
935 I40E_PTT_UNUSED_ENTRY(246),
936 I40E_PTT_UNUSED_ENTRY(247),
937 I40E_PTT_UNUSED_ENTRY(248),
938 I40E_PTT_UNUSED_ENTRY(249),
940 I40E_PTT_UNUSED_ENTRY(250),
941 I40E_PTT_UNUSED_ENTRY(251),
942 I40E_PTT_UNUSED_ENTRY(252),
943 I40E_PTT_UNUSED_ENTRY(253),
944 I40E_PTT_UNUSED_ENTRY(254),
945 I40E_PTT_UNUSED_ENTRY(255)
950 * i40e_validate_mac_addr - Validate unicast MAC address
951 * @mac_addr: pointer to MAC address
953 * Tests a MAC address to ensure it is a valid Individual Address
955 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
957 enum i40e_status_code status = I40E_SUCCESS;
959 DEBUGFUNC("i40e_validate_mac_addr");
961 /* Broadcast addresses ARE multicast addresses
962 * Make sure it is not a multicast address
963 * Reject the zero address
965 if (I40E_IS_MULTICAST(mac_addr) ||
966 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
967 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
968 status = I40E_ERR_INVALID_MAC_ADDR;
975 * i40e_init_shared_code - Initialize the shared code
976 * @hw: pointer to hardware structure
978 * This assigns the MAC type and PHY code and inits the NVM.
979 * Does not touch the hardware. This function must be called prior to any
980 * other function in the shared code. The i40e_hw structure should be
981 * memset to 0 prior to calling this function. The following fields in
982 * hw structure should be filled in prior to calling this function:
983 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
984 * subsystem_vendor_id, and revision_id
986 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
988 enum i40e_status_code status = I40E_SUCCESS;
989 u32 port, ari, func_rid;
991 DEBUGFUNC("i40e_init_shared_code");
993 i40e_set_mac_type(hw);
995 switch (hw->mac.type) {
1000 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1003 hw->phy.get_link_info = true;
1005 /* Determine port number and PF number*/
1006 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1007 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1008 hw->port = (u8)port;
1009 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1010 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1011 func_rid = rd32(hw, I40E_PF_FUNC_RID);
1013 hw->pf_id = (u8)(func_rid & 0xff);
1015 hw->pf_id = (u8)(func_rid & 0x7);
1017 if (hw->mac.type == I40E_MAC_X722)
1018 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE |
1019 I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK;
1020 /* NVMUpdate features structure initialization */
1021 hw->nvmupd_features.major = I40E_NVMUPD_FEATURES_API_VER_MAJOR;
1022 hw->nvmupd_features.minor = I40E_NVMUPD_FEATURES_API_VER_MINOR;
1023 hw->nvmupd_features.size = sizeof(hw->nvmupd_features);
1024 i40e_memset(hw->nvmupd_features.features, 0x0,
1025 I40E_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN *
1026 sizeof(*hw->nvmupd_features.features),
1029 /* No features supported at the moment */
1030 hw->nvmupd_features.features[0] = 0;
1032 status = i40e_init_nvm(hw);
1037 * i40e_aq_mac_address_read - Retrieve the MAC addresses
1038 * @hw: pointer to the hw struct
1039 * @flags: a return indicator of what addresses were added to the addr store
1040 * @addrs: the requestor's mac addr store
1041 * @cmd_details: pointer to command details structure or NULL
1043 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1045 struct i40e_aqc_mac_address_read_data *addrs,
1046 struct i40e_asq_cmd_details *cmd_details)
1048 struct i40e_aq_desc desc;
1049 struct i40e_aqc_mac_address_read *cmd_data =
1050 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1051 enum i40e_status_code status;
1053 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1054 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1056 status = i40e_asq_send_command(hw, &desc, addrs,
1057 sizeof(*addrs), cmd_details);
1058 *flags = LE16_TO_CPU(cmd_data->command_flags);
1064 * i40e_aq_mac_address_write - Change the MAC addresses
1065 * @hw: pointer to the hw struct
1066 * @flags: indicates which MAC to be written
1067 * @mac_addr: address to write
1068 * @cmd_details: pointer to command details structure or NULL
1070 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1071 u16 flags, u8 *mac_addr,
1072 struct i40e_asq_cmd_details *cmd_details)
1074 struct i40e_aq_desc desc;
1075 struct i40e_aqc_mac_address_write *cmd_data =
1076 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1077 enum i40e_status_code status;
1079 i40e_fill_default_direct_cmd_desc(&desc,
1080 i40e_aqc_opc_mac_address_write);
1081 cmd_data->command_flags = CPU_TO_LE16(flags);
1082 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1083 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1084 ((u32)mac_addr[3] << 16) |
1085 ((u32)mac_addr[4] << 8) |
1088 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1094 * i40e_get_mac_addr - get MAC address
1095 * @hw: pointer to the HW structure
1096 * @mac_addr: pointer to MAC address
1098 * Reads the adapter's MAC address from register
1100 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1102 struct i40e_aqc_mac_address_read_data addrs;
1103 enum i40e_status_code status;
1106 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1108 if (flags & I40E_AQC_LAN_ADDR_VALID)
1109 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1110 I40E_NONDMA_TO_NONDMA);
1116 * i40e_get_port_mac_addr - get Port MAC address
1117 * @hw: pointer to the HW structure
1118 * @mac_addr: pointer to Port MAC address
1120 * Reads the adapter's Port MAC address
1122 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1124 struct i40e_aqc_mac_address_read_data addrs;
1125 enum i40e_status_code status;
1128 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1132 if (flags & I40E_AQC_PORT_ADDR_VALID)
1133 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1134 I40E_NONDMA_TO_NONDMA);
1136 status = I40E_ERR_INVALID_MAC_ADDR;
1142 * i40e_pre_tx_queue_cfg - pre tx queue configure
1143 * @hw: pointer to the HW structure
1144 * @queue: target pf queue index
1145 * @enable: state change request
1147 * Handles hw requirement to indicate intention to enable
1148 * or disable target queue.
1150 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1152 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1156 if (abs_queue_idx >= 128) {
1157 reg_block = abs_queue_idx / 128;
1158 abs_queue_idx %= 128;
1161 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1162 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1163 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1166 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1168 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1170 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1174 * i40e_get_san_mac_addr - get SAN MAC address
1175 * @hw: pointer to the HW structure
1176 * @mac_addr: pointer to SAN MAC address
1178 * Reads the adapter's SAN MAC address from NVM
1180 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1183 struct i40e_aqc_mac_address_read_data addrs;
1184 enum i40e_status_code status;
1187 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1191 if (flags & I40E_AQC_SAN_ADDR_VALID)
1192 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac),
1193 I40E_NONDMA_TO_NONDMA);
1195 status = I40E_ERR_INVALID_MAC_ADDR;
1201 * i40e_read_pba_string - Reads part number string from EEPROM
1202 * @hw: pointer to hardware structure
1203 * @pba_num: stores the part number string from the EEPROM
1204 * @pba_num_size: part number string buffer length
1206 * Reads the part number string from the EEPROM.
1208 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1211 enum i40e_status_code status = I40E_SUCCESS;
1217 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1218 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1219 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1223 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1224 if (status != I40E_SUCCESS) {
1225 DEBUGOUT("Failed to read PBA Block pointer.\n");
1229 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1230 if (status != I40E_SUCCESS) {
1231 DEBUGOUT("Failed to read PBA Block size.\n");
1235 /* Subtract one to get PBA word count (PBA Size word is included in
1239 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1240 DEBUGOUT("Buffer to small for PBA data.\n");
1241 return I40E_ERR_PARAM;
1244 for (i = 0; i < pba_size; i++) {
1245 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1246 if (status != I40E_SUCCESS) {
1247 DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1251 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1252 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1254 pba_num[(pba_size * 2)] = '\0';
1260 * i40e_get_media_type - Gets media type
1261 * @hw: pointer to the hardware structure
1263 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1265 enum i40e_media_type media;
1267 switch (hw->phy.link_info.phy_type) {
1268 case I40E_PHY_TYPE_10GBASE_SR:
1269 case I40E_PHY_TYPE_10GBASE_LR:
1270 case I40E_PHY_TYPE_1000BASE_SX:
1271 case I40E_PHY_TYPE_1000BASE_LX:
1272 case I40E_PHY_TYPE_40GBASE_SR4:
1273 case I40E_PHY_TYPE_40GBASE_LR4:
1274 case I40E_PHY_TYPE_25GBASE_LR:
1275 case I40E_PHY_TYPE_25GBASE_SR:
1276 media = I40E_MEDIA_TYPE_FIBER;
1278 case I40E_PHY_TYPE_100BASE_TX:
1279 case I40E_PHY_TYPE_1000BASE_T:
1280 case I40E_PHY_TYPE_2_5GBASE_T:
1281 case I40E_PHY_TYPE_5GBASE_T:
1282 case I40E_PHY_TYPE_10GBASE_T:
1283 media = I40E_MEDIA_TYPE_BASET;
1285 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1286 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1287 case I40E_PHY_TYPE_10GBASE_CR1:
1288 case I40E_PHY_TYPE_40GBASE_CR4:
1289 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1290 case I40E_PHY_TYPE_40GBASE_AOC:
1291 case I40E_PHY_TYPE_10GBASE_AOC:
1292 case I40E_PHY_TYPE_25GBASE_CR:
1293 case I40E_PHY_TYPE_25GBASE_AOC:
1294 case I40E_PHY_TYPE_25GBASE_ACC:
1295 media = I40E_MEDIA_TYPE_DA;
1297 case I40E_PHY_TYPE_1000BASE_KX:
1298 case I40E_PHY_TYPE_10GBASE_KX4:
1299 case I40E_PHY_TYPE_10GBASE_KR:
1300 case I40E_PHY_TYPE_40GBASE_KR4:
1301 case I40E_PHY_TYPE_20GBASE_KR2:
1302 case I40E_PHY_TYPE_25GBASE_KR:
1303 media = I40E_MEDIA_TYPE_BACKPLANE;
1305 case I40E_PHY_TYPE_SGMII:
1306 case I40E_PHY_TYPE_XAUI:
1307 case I40E_PHY_TYPE_XFI:
1308 case I40E_PHY_TYPE_XLAUI:
1309 case I40E_PHY_TYPE_XLPPI:
1311 media = I40E_MEDIA_TYPE_UNKNOWN;
1319 * i40e_poll_globr - Poll for Global Reset completion
1320 * @hw: pointer to the hardware structure
1321 * @retry_limit: how many times to retry before failure
1323 STATIC enum i40e_status_code i40e_poll_globr(struct i40e_hw *hw,
1328 for (cnt = 0; cnt < retry_limit; cnt++) {
1329 reg = rd32(hw, I40E_GLGEN_RSTAT);
1330 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1331 return I40E_SUCCESS;
1332 i40e_msec_delay(100);
1335 DEBUGOUT("Global reset failed.\n");
1336 DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg);
1338 return I40E_ERR_RESET_FAILED;
1341 #define I40E_PF_RESET_WAIT_COUNT 200
1343 * i40e_pf_reset - Reset the PF
1344 * @hw: pointer to the hardware structure
1346 * Assuming someone else has triggered a global reset,
1347 * assure the global reset is complete and then reset the PF
1349 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1356 /* Poll for Global Reset steady state in case of recent GRST.
1357 * The grst delay value is in 100ms units, and we'll wait a
1358 * couple counts longer to be sure we don't just miss the end.
1360 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1361 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1362 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1364 grst_del = min(grst_del * 20, 160U);
1366 for (cnt = 0; cnt < grst_del; cnt++) {
1367 reg = rd32(hw, I40E_GLGEN_RSTAT);
1368 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1370 i40e_msec_delay(100);
1372 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1373 DEBUGOUT("Global reset polling failed to complete.\n");
1374 return I40E_ERR_RESET_FAILED;
1377 /* Now Wait for the FW to be ready */
1378 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1379 reg = rd32(hw, I40E_GLNVM_ULD);
1380 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1381 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1382 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1383 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1384 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1387 i40e_msec_delay(10);
1389 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1390 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1391 DEBUGOUT("wait for FW Reset complete timedout\n");
1392 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1393 return I40E_ERR_RESET_FAILED;
1396 /* If there was a Global Reset in progress when we got here,
1397 * we don't need to do the PF Reset
1402 reg = rd32(hw, I40E_PFGEN_CTRL);
1403 wr32(hw, I40E_PFGEN_CTRL,
1404 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1405 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1406 reg = rd32(hw, I40E_PFGEN_CTRL);
1407 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1409 reg2 = rd32(hw, I40E_GLGEN_RSTAT);
1410 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK)
1414 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1415 if (i40e_poll_globr(hw, grst_del) != I40E_SUCCESS)
1416 return I40E_ERR_RESET_FAILED;
1417 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1418 DEBUGOUT("PF reset polling failed to complete.\n");
1419 return I40E_ERR_RESET_FAILED;
1423 i40e_clear_pxe_mode(hw);
1426 return I40E_SUCCESS;
1430 * i40e_clear_hw - clear out any left over hw state
1431 * @hw: pointer to the hw struct
1433 * Clear queues and interrupts, typically called at init time,
1434 * but after the capabilities have been found so we know how many
1435 * queues and msix vectors have been allocated.
1437 void i40e_clear_hw(struct i40e_hw *hw)
1439 u32 num_queues, base_queue;
1447 /* get number of interrupts, queues, and vfs */
1448 val = rd32(hw, I40E_GLPCI_CNF2);
1449 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1450 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1451 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1452 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1454 val = rd32(hw, I40E_PFLAN_QALLOC);
1455 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1456 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1457 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1458 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1459 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1460 num_queues = (j - base_queue) + 1;
1464 val = rd32(hw, I40E_PF_VT_PFALLOC);
1465 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1466 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1467 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1468 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1469 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1470 num_vfs = (j - i) + 1;
1474 /* stop all the interrupts */
1475 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1476 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1477 for (i = 0; i < num_pf_int - 2; i++)
1478 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1480 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1481 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1482 wr32(hw, I40E_PFINT_LNKLST0, val);
1483 for (i = 0; i < num_pf_int - 2; i++)
1484 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1485 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1486 for (i = 0; i < num_vfs; i++)
1487 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1488 for (i = 0; i < num_vf_int - 2; i++)
1489 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1491 /* warn the HW of the coming Tx disables */
1492 for (i = 0; i < num_queues; i++) {
1493 u32 abs_queue_idx = base_queue + i;
1496 if (abs_queue_idx >= 128) {
1497 reg_block = abs_queue_idx / 128;
1498 abs_queue_idx %= 128;
1501 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1502 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1503 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1504 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1506 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1508 i40e_usec_delay(400);
1510 /* stop all the queues */
1511 for (i = 0; i < num_queues; i++) {
1512 wr32(hw, I40E_QINT_TQCTL(i), 0);
1513 wr32(hw, I40E_QTX_ENA(i), 0);
1514 wr32(hw, I40E_QINT_RQCTL(i), 0);
1515 wr32(hw, I40E_QRX_ENA(i), 0);
1518 /* short wait for all queue disables to settle */
1519 i40e_usec_delay(50);
1523 * i40e_clear_pxe_mode - clear pxe operations mode
1524 * @hw: pointer to the hw struct
1526 * Make sure all PXE mode settings are cleared, including things
1527 * like descriptor fetch/write-back mode.
1529 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1531 if (i40e_check_asq_alive(hw))
1532 i40e_aq_clear_pxe_mode(hw, NULL);
1536 * i40e_led_is_mine - helper to find matching led
1537 * @hw: pointer to the hw struct
1538 * @idx: index into GPIO registers
1540 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1542 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1547 if (!hw->func_caps.led[idx])
1550 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1551 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1552 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1554 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1555 * if it is not our port then ignore
1557 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1564 #define I40E_COMBINED_ACTIVITY 0xA
1565 #define I40E_FILTER_ACTIVITY 0xE
1566 #define I40E_LINK_ACTIVITY 0xC
1567 #define I40E_MAC_ACTIVITY 0xD
1568 #define I40E_LED0 22
1571 * i40e_led_get - return current on/off mode
1572 * @hw: pointer to the hw struct
1574 * The value returned is the 'mode' field as defined in the
1575 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1576 * values are variations of possible behaviors relating to
1577 * blink, link, and wire.
1579 u32 i40e_led_get(struct i40e_hw *hw)
1581 u32 current_mode = 0;
1585 /* as per the documentation GPIO 22-29 are the LED
1586 * GPIO pins named LED0..LED7
1588 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1589 u32 gpio_val = i40e_led_is_mine(hw, i);
1594 /* ignore gpio LED src mode entries related to the activity
1597 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1598 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1599 switch (current_mode) {
1600 case I40E_COMBINED_ACTIVITY:
1601 case I40E_FILTER_ACTIVITY:
1602 case I40E_MAC_ACTIVITY:
1603 case I40E_LINK_ACTIVITY:
1609 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1610 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1618 * i40e_led_set - set new on/off mode
1619 * @hw: pointer to the hw struct
1620 * @mode: 0=off, 0xf=on (else see manual for mode details)
1621 * @blink: true if the LED should blink when on, false if steady
1623 * if this function is used to turn on the blink it should
1624 * be used to disable the blink when restoring the original state.
1626 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1628 u32 current_mode = 0;
1631 if (mode & 0xfffffff0)
1632 DEBUGOUT1("invalid mode passed in %X\n", mode);
1634 /* as per the documentation GPIO 22-29 are the LED
1635 * GPIO pins named LED0..LED7
1637 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1638 u32 gpio_val = i40e_led_is_mine(hw, i);
1643 /* ignore gpio LED src mode entries related to the activity
1646 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1647 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1648 switch (current_mode) {
1649 case I40E_COMBINED_ACTIVITY:
1650 case I40E_FILTER_ACTIVITY:
1651 case I40E_MAC_ACTIVITY:
1652 case I40E_LINK_ACTIVITY:
1658 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1659 /* this & is a bit of paranoia, but serves as a range check */
1660 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1661 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1664 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1666 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1668 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1673 /* Admin command wrappers */
1676 * i40e_aq_get_phy_capabilities
1677 * @hw: pointer to the hw struct
1678 * @abilities: structure for PHY capabilities to be filled
1679 * @qualified_modules: report Qualified Modules
1680 * @report_init: report init capabilities (active are default)
1681 * @cmd_details: pointer to command details structure or NULL
1683 * Returns the various PHY abilities supported on the Port.
1685 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1686 bool qualified_modules, bool report_init,
1687 struct i40e_aq_get_phy_abilities_resp *abilities,
1688 struct i40e_asq_cmd_details *cmd_details)
1690 struct i40e_aq_desc desc;
1691 enum i40e_status_code status;
1692 u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0;
1693 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1696 return I40E_ERR_PARAM;
1699 i40e_fill_default_direct_cmd_desc(&desc,
1700 i40e_aqc_opc_get_phy_abilities);
1702 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1703 if (abilities_size > I40E_AQ_LARGE_BUF)
1704 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1706 if (qualified_modules)
1707 desc.params.external.param0 |=
1708 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1711 desc.params.external.param0 |=
1712 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1714 status = i40e_asq_send_command(hw, &desc, abilities,
1715 abilities_size, cmd_details);
1717 switch (hw->aq.asq_last_status) {
1718 case I40E_AQ_RC_EIO:
1719 status = I40E_ERR_UNKNOWN_PHY;
1721 case I40E_AQ_RC_EAGAIN:
1724 status = I40E_ERR_TIMEOUT;
1726 /* also covers I40E_AQ_RC_OK */
1731 } while ((hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) &&
1732 (total_delay < max_delay));
1734 if (status != I40E_SUCCESS)
1738 if (hw->mac.type == I40E_MAC_XL710 &&
1739 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1740 hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
1741 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1743 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1744 hw->phy.phy_types |=
1745 ((u64)abilities->phy_type_ext << 32);
1753 * i40e_aq_set_phy_config
1754 * @hw: pointer to the hw struct
1755 * @config: structure with PHY configuration to be set
1756 * @cmd_details: pointer to command details structure or NULL
1758 * Set the various PHY configuration parameters
1759 * supported on the Port.One or more of the Set PHY config parameters may be
1760 * ignored in an MFP mode as the PF may not have the privilege to set some
1761 * of the PHY Config parameters. This status will be indicated by the
1764 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1765 struct i40e_aq_set_phy_config *config,
1766 struct i40e_asq_cmd_details *cmd_details)
1768 struct i40e_aq_desc desc;
1769 struct i40e_aq_set_phy_config *cmd =
1770 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1771 enum i40e_status_code status;
1774 return I40E_ERR_PARAM;
1776 i40e_fill_default_direct_cmd_desc(&desc,
1777 i40e_aqc_opc_set_phy_config);
1781 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1788 * @hw: pointer to the hw struct
1789 * @aq_failures: buffer to return AdminQ failure information
1790 * @atomic_restart: whether to enable atomic link restart
1792 * Set the requested flow control mode using set_phy_config.
1794 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1795 bool atomic_restart)
1797 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1798 struct i40e_aq_get_phy_abilities_resp abilities;
1799 struct i40e_aq_set_phy_config config;
1800 enum i40e_status_code status;
1801 u8 pause_mask = 0x0;
1807 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1808 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1810 case I40E_FC_RX_PAUSE:
1811 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1813 case I40E_FC_TX_PAUSE:
1814 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1820 /* Get the current phy config */
1821 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1824 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1828 memset(&config, 0, sizeof(config));
1829 /* clear the old pause settings */
1830 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1831 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1832 /* set the new abilities */
1833 config.abilities |= pause_mask;
1834 /* If the abilities have changed, then set the new config */
1835 if (config.abilities != abilities.abilities) {
1836 /* Auto restart link so settings take effect */
1838 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1839 /* Copy over all the old settings */
1840 config.phy_type = abilities.phy_type;
1841 config.phy_type_ext = abilities.phy_type_ext;
1842 config.link_speed = abilities.link_speed;
1843 config.eee_capability = abilities.eee_capability;
1844 config.eeer = abilities.eeer_val;
1845 config.low_power_ctrl = abilities.d3_lpan;
1846 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1847 I40E_AQ_PHY_FEC_CONFIG_MASK;
1848 status = i40e_aq_set_phy_config(hw, &config, NULL);
1851 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1853 /* Update the link info */
1854 status = i40e_update_link_info(hw);
1856 /* Wait a little bit (on 40G cards it sometimes takes a really
1857 * long time for link to come back from the atomic reset)
1860 i40e_msec_delay(1000);
1861 status = i40e_update_link_info(hw);
1864 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1870 * i40e_aq_set_mac_config
1871 * @hw: pointer to the hw struct
1872 * @max_frame_size: Maximum Frame Size to be supported by the port
1873 * @crc_en: Tell HW to append a CRC to outgoing frames
1874 * @pacing: Pacing configurations
1875 * @auto_drop_blocking_packets: Tell HW to drop packets if TC queue is blocked
1876 * @cmd_details: pointer to command details structure or NULL
1878 * Configure MAC settings for frame size, jumbo frame support and the
1879 * addition of a CRC by the hardware.
1881 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1883 bool crc_en, u16 pacing,
1884 bool auto_drop_blocking_packets,
1885 struct i40e_asq_cmd_details *cmd_details)
1887 struct i40e_aq_desc desc;
1888 struct i40e_aq_set_mac_config *cmd =
1889 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1890 enum i40e_status_code status;
1892 if (max_frame_size == 0)
1893 return I40E_ERR_PARAM;
1895 i40e_fill_default_direct_cmd_desc(&desc,
1896 i40e_aqc_opc_set_mac_config);
1898 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1899 cmd->params = ((u8)pacing & 0x0F) << 3;
1901 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1903 if (auto_drop_blocking_packets) {
1904 if (hw->flags & I40E_HW_FLAG_DROP_MODE)
1906 I40E_AQ_SET_MAC_CONFIG_DROP_BLOCKING_PACKET_EN;
1908 i40e_debug(hw, I40E_DEBUG_ALL,
1909 "This FW api version does not support drop mode.\n");
1912 #define I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD 0x7FFF
1913 cmd->fc_refresh_threshold =
1914 CPU_TO_LE16(I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD);
1916 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1922 * i40e_aq_clear_pxe_mode
1923 * @hw: pointer to the hw struct
1924 * @cmd_details: pointer to command details structure or NULL
1926 * Tell the firmware that the driver is taking over from PXE
1928 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1929 struct i40e_asq_cmd_details *cmd_details)
1931 enum i40e_status_code status;
1932 struct i40e_aq_desc desc;
1933 struct i40e_aqc_clear_pxe *cmd =
1934 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1936 i40e_fill_default_direct_cmd_desc(&desc,
1937 i40e_aqc_opc_clear_pxe_mode);
1941 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1943 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1949 * i40e_aq_set_link_restart_an
1950 * @hw: pointer to the hw struct
1951 * @enable_link: if true: enable link, if false: disable link
1952 * @cmd_details: pointer to command details structure or NULL
1954 * Sets up the link and restarts the Auto-Negotiation over the link.
1956 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1957 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1959 struct i40e_aq_desc desc;
1960 struct i40e_aqc_set_link_restart_an *cmd =
1961 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1962 enum i40e_status_code status;
1964 i40e_fill_default_direct_cmd_desc(&desc,
1965 i40e_aqc_opc_set_link_restart_an);
1967 cmd->command = I40E_AQ_PHY_RESTART_AN;
1969 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1971 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1973 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1979 * i40e_aq_get_link_info
1980 * @hw: pointer to the hw struct
1981 * @enable_lse: enable/disable LinkStatusEvent reporting
1982 * @link: pointer to link status structure - optional
1983 * @cmd_details: pointer to command details structure or NULL
1985 * Returns the link status of the adapter.
1987 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1988 bool enable_lse, struct i40e_link_status *link,
1989 struct i40e_asq_cmd_details *cmd_details)
1991 struct i40e_aq_desc desc;
1992 struct i40e_aqc_get_link_status *resp =
1993 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1994 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1995 enum i40e_status_code status;
1996 bool tx_pause, rx_pause;
1999 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
2002 command_flags = I40E_AQ_LSE_ENABLE;
2004 command_flags = I40E_AQ_LSE_DISABLE;
2005 resp->command_flags = CPU_TO_LE16(command_flags);
2007 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2009 if (status != I40E_SUCCESS)
2010 goto aq_get_link_info_exit;
2012 /* save off old link status information */
2013 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
2014 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
2016 /* update link status */
2017 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
2018 hw->phy.media_type = i40e_get_media_type(hw);
2019 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
2020 hw_link_info->link_info = resp->link_info;
2021 hw_link_info->an_info = resp->an_info;
2022 hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
2023 I40E_AQ_CONFIG_FEC_RS_ENA);
2024 hw_link_info->ext_info = resp->ext_info;
2025 hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
2026 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
2027 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
2029 /* update fc info */
2030 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
2031 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
2032 if (tx_pause & rx_pause)
2033 hw->fc.current_mode = I40E_FC_FULL;
2035 hw->fc.current_mode = I40E_FC_TX_PAUSE;
2037 hw->fc.current_mode = I40E_FC_RX_PAUSE;
2039 hw->fc.current_mode = I40E_FC_NONE;
2041 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
2042 hw_link_info->crc_enable = true;
2044 hw_link_info->crc_enable = false;
2046 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
2047 hw_link_info->lse_enable = true;
2049 hw_link_info->lse_enable = false;
2051 if ((hw->mac.type == I40E_MAC_XL710) &&
2052 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
2053 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
2054 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
2056 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE &&
2057 hw->mac.type != I40E_MAC_X722) {
2060 i40e_memcpy(&tmp, resp->link_type, sizeof(tmp),
2061 I40E_NONDMA_TO_NONDMA);
2062 hw->phy.phy_types = LE32_TO_CPU(tmp);
2063 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
2066 /* save link status information */
2068 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
2069 I40E_NONDMA_TO_NONDMA);
2071 /* flag cleared so helper functions don't call AQ again */
2072 hw->phy.get_link_info = false;
2074 aq_get_link_info_exit:
2079 * i40e_aq_set_phy_int_mask
2080 * @hw: pointer to the hw struct
2081 * @mask: interrupt mask to be set
2082 * @cmd_details: pointer to command details structure or NULL
2084 * Set link interrupt mask.
2086 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2088 struct i40e_asq_cmd_details *cmd_details)
2090 struct i40e_aq_desc desc;
2091 struct i40e_aqc_set_phy_int_mask *cmd =
2092 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2093 enum i40e_status_code status;
2095 i40e_fill_default_direct_cmd_desc(&desc,
2096 i40e_aqc_opc_set_phy_int_mask);
2098 cmd->event_mask = CPU_TO_LE16(mask);
2100 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2106 * i40e_aq_get_local_advt_reg
2107 * @hw: pointer to the hw struct
2108 * @advt_reg: local AN advertisement register value
2109 * @cmd_details: pointer to command details structure or NULL
2111 * Get the Local AN advertisement register value.
2113 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2115 struct i40e_asq_cmd_details *cmd_details)
2117 struct i40e_aq_desc desc;
2118 struct i40e_aqc_an_advt_reg *resp =
2119 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2120 enum i40e_status_code status;
2122 i40e_fill_default_direct_cmd_desc(&desc,
2123 i40e_aqc_opc_get_local_advt_reg);
2125 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2127 if (status != I40E_SUCCESS)
2128 goto aq_get_local_advt_reg_exit;
2130 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2131 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2133 aq_get_local_advt_reg_exit:
2138 * i40e_aq_set_local_advt_reg
2139 * @hw: pointer to the hw struct
2140 * @advt_reg: local AN advertisement register value
2141 * @cmd_details: pointer to command details structure or NULL
2143 * Get the Local AN advertisement register value.
2145 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2147 struct i40e_asq_cmd_details *cmd_details)
2149 struct i40e_aq_desc desc;
2150 struct i40e_aqc_an_advt_reg *cmd =
2151 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2152 enum i40e_status_code status;
2154 i40e_fill_default_direct_cmd_desc(&desc,
2155 i40e_aqc_opc_get_local_advt_reg);
2157 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2158 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2160 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2166 * i40e_aq_get_partner_advt
2167 * @hw: pointer to the hw struct
2168 * @advt_reg: AN partner advertisement register value
2169 * @cmd_details: pointer to command details structure or NULL
2171 * Get the link partner AN advertisement register value.
2173 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2175 struct i40e_asq_cmd_details *cmd_details)
2177 struct i40e_aq_desc desc;
2178 struct i40e_aqc_an_advt_reg *resp =
2179 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2180 enum i40e_status_code status;
2182 i40e_fill_default_direct_cmd_desc(&desc,
2183 i40e_aqc_opc_get_partner_advt);
2185 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2187 if (status != I40E_SUCCESS)
2188 goto aq_get_partner_advt_exit;
2190 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2191 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2193 aq_get_partner_advt_exit:
2198 * i40e_aq_set_lb_modes
2199 * @hw: pointer to the hw struct
2200 * @lb_modes: loopback mode to be set
2201 * @cmd_details: pointer to command details structure or NULL
2203 * Sets loopback modes.
2205 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2207 struct i40e_asq_cmd_details *cmd_details)
2209 struct i40e_aq_desc desc;
2210 struct i40e_aqc_set_lb_mode *cmd =
2211 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2212 enum i40e_status_code status;
2214 i40e_fill_default_direct_cmd_desc(&desc,
2215 i40e_aqc_opc_set_lb_modes);
2217 cmd->lb_mode = CPU_TO_LE16(lb_modes);
2219 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2225 * i40e_aq_set_phy_debug
2226 * @hw: pointer to the hw struct
2227 * @cmd_flags: debug command flags
2228 * @cmd_details: pointer to command details structure or NULL
2230 * Reset the external PHY.
2232 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2233 struct i40e_asq_cmd_details *cmd_details)
2235 struct i40e_aq_desc desc;
2236 struct i40e_aqc_set_phy_debug *cmd =
2237 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2238 enum i40e_status_code status;
2240 i40e_fill_default_direct_cmd_desc(&desc,
2241 i40e_aqc_opc_set_phy_debug);
2243 cmd->command_flags = cmd_flags;
2245 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2252 * @hw: pointer to the hw struct
2253 * @vsi_ctx: pointer to a vsi context struct
2254 * @cmd_details: pointer to command details structure or NULL
2256 * Add a VSI context to the hardware.
2258 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2259 struct i40e_vsi_context *vsi_ctx,
2260 struct i40e_asq_cmd_details *cmd_details)
2262 struct i40e_aq_desc desc;
2263 struct i40e_aqc_add_get_update_vsi *cmd =
2264 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2265 struct i40e_aqc_add_get_update_vsi_completion *resp =
2266 (struct i40e_aqc_add_get_update_vsi_completion *)
2268 enum i40e_status_code status;
2270 i40e_fill_default_direct_cmd_desc(&desc,
2271 i40e_aqc_opc_add_vsi);
2273 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2274 cmd->connection_type = vsi_ctx->connection_type;
2275 cmd->vf_id = vsi_ctx->vf_num;
2276 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2278 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2280 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2281 sizeof(vsi_ctx->info), cmd_details);
2283 if (status != I40E_SUCCESS)
2284 goto aq_add_vsi_exit;
2286 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2287 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2288 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2289 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2296 * i40e_aq_set_default_vsi
2297 * @hw: pointer to the hw struct
2299 * @cmd_details: pointer to command details structure or NULL
2301 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2303 struct i40e_asq_cmd_details *cmd_details)
2305 struct i40e_aq_desc desc;
2306 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2307 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2309 enum i40e_status_code status;
2311 i40e_fill_default_direct_cmd_desc(&desc,
2312 i40e_aqc_opc_set_vsi_promiscuous_modes);
2314 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2315 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2316 cmd->seid = CPU_TO_LE16(seid);
2318 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2324 * i40e_aq_clear_default_vsi
2325 * @hw: pointer to the hw struct
2327 * @cmd_details: pointer to command details structure or NULL
2329 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2331 struct i40e_asq_cmd_details *cmd_details)
2333 struct i40e_aq_desc desc;
2334 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2335 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2337 enum i40e_status_code status;
2339 i40e_fill_default_direct_cmd_desc(&desc,
2340 i40e_aqc_opc_set_vsi_promiscuous_modes);
2342 cmd->promiscuous_flags = CPU_TO_LE16(0);
2343 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2344 cmd->seid = CPU_TO_LE16(seid);
2346 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2352 * i40e_aq_set_vsi_unicast_promiscuous
2353 * @hw: pointer to the hw struct
2355 * @set: set unicast promiscuous enable/disable
2356 * @cmd_details: pointer to command details structure or NULL
2357 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2359 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2361 struct i40e_asq_cmd_details *cmd_details,
2362 bool rx_only_promisc)
2364 struct i40e_aq_desc desc;
2365 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2366 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2367 enum i40e_status_code status;
2370 i40e_fill_default_direct_cmd_desc(&desc,
2371 i40e_aqc_opc_set_vsi_promiscuous_modes);
2374 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2375 if (rx_only_promisc &&
2376 (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2377 (hw->aq.api_maj_ver > 1)))
2378 flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2381 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2383 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2384 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2385 (hw->aq.api_maj_ver > 1))
2386 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2388 cmd->seid = CPU_TO_LE16(seid);
2389 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2395 * i40e_aq_set_vsi_multicast_promiscuous
2396 * @hw: pointer to the hw struct
2398 * @set: set multicast promiscuous enable/disable
2399 * @cmd_details: pointer to command details structure or NULL
2401 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2402 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2404 struct i40e_aq_desc desc;
2405 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2406 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2407 enum i40e_status_code status;
2410 i40e_fill_default_direct_cmd_desc(&desc,
2411 i40e_aqc_opc_set_vsi_promiscuous_modes);
2414 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2416 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2418 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2420 cmd->seid = CPU_TO_LE16(seid);
2421 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2427 * i40e_aq_set_vsi_full_promiscuous
2428 * @hw: pointer to the hw struct
2430 * @set: set promiscuous enable/disable
2431 * @cmd_details: pointer to command details structure or NULL
2433 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw,
2435 struct i40e_asq_cmd_details *cmd_details)
2437 struct i40e_aq_desc desc;
2438 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2439 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2440 enum i40e_status_code status;
2443 i40e_fill_default_direct_cmd_desc(&desc,
2444 i40e_aqc_opc_set_vsi_promiscuous_modes);
2447 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST |
2448 I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2449 I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2451 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2453 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST |
2454 I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2455 I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2457 cmd->seid = CPU_TO_LE16(seid);
2458 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2464 * i40e_aq_set_vsi_mc_promisc_on_vlan
2465 * @hw: pointer to the hw struct
2467 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2468 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2469 * @cmd_details: pointer to command details structure or NULL
2471 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2472 u16 seid, bool enable, u16 vid,
2473 struct i40e_asq_cmd_details *cmd_details)
2475 struct i40e_aq_desc desc;
2476 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2477 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2478 enum i40e_status_code status;
2481 i40e_fill_default_direct_cmd_desc(&desc,
2482 i40e_aqc_opc_set_vsi_promiscuous_modes);
2485 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2487 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2488 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2489 cmd->seid = CPU_TO_LE16(seid);
2490 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2492 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2498 * i40e_aq_set_vsi_uc_promisc_on_vlan
2499 * @hw: pointer to the hw struct
2501 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2502 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2503 * @cmd_details: pointer to command details structure or NULL
2505 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2506 u16 seid, bool enable, u16 vid,
2507 struct i40e_asq_cmd_details *cmd_details)
2509 struct i40e_aq_desc desc;
2510 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2511 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2512 enum i40e_status_code status;
2515 i40e_fill_default_direct_cmd_desc(&desc,
2516 i40e_aqc_opc_set_vsi_promiscuous_modes);
2519 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2521 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2522 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2523 cmd->seid = CPU_TO_LE16(seid);
2524 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2526 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2532 * i40e_aq_set_vsi_bc_promisc_on_vlan
2533 * @hw: pointer to the hw struct
2535 * @enable: set broadcast promiscuous enable/disable for a given VLAN
2536 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2537 * @cmd_details: pointer to command details structure or NULL
2539 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2540 u16 seid, bool enable, u16 vid,
2541 struct i40e_asq_cmd_details *cmd_details)
2543 struct i40e_aq_desc desc;
2544 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2545 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2546 enum i40e_status_code status;
2549 i40e_fill_default_direct_cmd_desc(&desc,
2550 i40e_aqc_opc_set_vsi_promiscuous_modes);
2553 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2555 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2556 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2557 cmd->seid = CPU_TO_LE16(seid);
2558 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2560 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2566 * i40e_aq_set_vsi_broadcast
2567 * @hw: pointer to the hw struct
2569 * @set_filter: true to set filter, false to clear filter
2570 * @cmd_details: pointer to command details structure or NULL
2572 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2574 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2575 u16 seid, bool set_filter,
2576 struct i40e_asq_cmd_details *cmd_details)
2578 struct i40e_aq_desc desc;
2579 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2580 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2581 enum i40e_status_code status;
2583 i40e_fill_default_direct_cmd_desc(&desc,
2584 i40e_aqc_opc_set_vsi_promiscuous_modes);
2587 cmd->promiscuous_flags
2588 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2590 cmd->promiscuous_flags
2591 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2593 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2594 cmd->seid = CPU_TO_LE16(seid);
2595 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2601 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2602 * @hw: pointer to the hw struct
2604 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2605 * @cmd_details: pointer to command details structure or NULL
2607 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2608 u16 seid, bool enable,
2609 struct i40e_asq_cmd_details *cmd_details)
2611 struct i40e_aq_desc desc;
2612 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2613 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2614 enum i40e_status_code status;
2617 i40e_fill_default_direct_cmd_desc(&desc,
2618 i40e_aqc_opc_set_vsi_promiscuous_modes);
2620 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2622 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2623 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2624 cmd->seid = CPU_TO_LE16(seid);
2626 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2632 * i40e_get_vsi_params - get VSI configuration info
2633 * @hw: pointer to the hw struct
2634 * @vsi_ctx: pointer to a vsi context struct
2635 * @cmd_details: pointer to command details structure or NULL
2637 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2638 struct i40e_vsi_context *vsi_ctx,
2639 struct i40e_asq_cmd_details *cmd_details)
2641 struct i40e_aq_desc desc;
2642 struct i40e_aqc_add_get_update_vsi *cmd =
2643 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2644 struct i40e_aqc_add_get_update_vsi_completion *resp =
2645 (struct i40e_aqc_add_get_update_vsi_completion *)
2647 enum i40e_status_code status;
2649 UNREFERENCED_1PARAMETER(cmd_details);
2650 i40e_fill_default_direct_cmd_desc(&desc,
2651 i40e_aqc_opc_get_vsi_parameters);
2653 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2655 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2657 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2658 sizeof(vsi_ctx->info), NULL);
2660 if (status != I40E_SUCCESS)
2661 goto aq_get_vsi_params_exit;
2663 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2664 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2665 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2666 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2668 aq_get_vsi_params_exit:
2673 * i40e_aq_update_vsi_params
2674 * @hw: pointer to the hw struct
2675 * @vsi_ctx: pointer to a vsi context struct
2676 * @cmd_details: pointer to command details structure or NULL
2678 * Update a VSI context.
2680 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2681 struct i40e_vsi_context *vsi_ctx,
2682 struct i40e_asq_cmd_details *cmd_details)
2684 struct i40e_aq_desc desc;
2685 struct i40e_aqc_add_get_update_vsi *cmd =
2686 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2687 struct i40e_aqc_add_get_update_vsi_completion *resp =
2688 (struct i40e_aqc_add_get_update_vsi_completion *)
2690 enum i40e_status_code status;
2692 i40e_fill_default_direct_cmd_desc(&desc,
2693 i40e_aqc_opc_update_vsi_parameters);
2694 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2696 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2698 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2699 sizeof(vsi_ctx->info), cmd_details);
2701 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2702 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2708 * i40e_aq_get_switch_config
2709 * @hw: pointer to the hardware structure
2710 * @buf: pointer to the result buffer
2711 * @buf_size: length of input buffer
2712 * @start_seid: seid to start for the report, 0 == beginning
2713 * @cmd_details: pointer to command details structure or NULL
2715 * Fill the buf with switch configuration returned from AdminQ command
2717 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2718 struct i40e_aqc_get_switch_config_resp *buf,
2719 u16 buf_size, u16 *start_seid,
2720 struct i40e_asq_cmd_details *cmd_details)
2722 struct i40e_aq_desc desc;
2723 struct i40e_aqc_switch_seid *scfg =
2724 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2725 enum i40e_status_code status;
2727 i40e_fill_default_direct_cmd_desc(&desc,
2728 i40e_aqc_opc_get_switch_config);
2729 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2730 if (buf_size > I40E_AQ_LARGE_BUF)
2731 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2732 scfg->seid = CPU_TO_LE16(*start_seid);
2734 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2735 *start_seid = LE16_TO_CPU(scfg->seid);
2741 * i40e_aq_set_switch_config
2742 * @hw: pointer to the hardware structure
2743 * @flags: bit flag values to set
2744 * @mode: cloud filter mode
2745 * @valid_flags: which bit flags to set
2746 * @cmd_details: pointer to command details structure or NULL
2748 * Set switch configuration bits
2750 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2751 u16 flags, u16 valid_flags, u8 mode,
2752 struct i40e_asq_cmd_details *cmd_details)
2754 struct i40e_aq_desc desc;
2755 struct i40e_aqc_set_switch_config *scfg =
2756 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2757 enum i40e_status_code status;
2759 i40e_fill_default_direct_cmd_desc(&desc,
2760 i40e_aqc_opc_set_switch_config);
2761 scfg->flags = CPU_TO_LE16(flags);
2762 scfg->valid_flags = CPU_TO_LE16(valid_flags);
2764 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
2765 scfg->switch_tag = CPU_TO_LE16(hw->switch_tag);
2766 scfg->first_tag = CPU_TO_LE16(hw->first_tag);
2767 scfg->second_tag = CPU_TO_LE16(hw->second_tag);
2769 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2775 * i40e_aq_get_firmware_version
2776 * @hw: pointer to the hw struct
2777 * @fw_major_version: firmware major version
2778 * @fw_minor_version: firmware minor version
2779 * @fw_build: firmware build number
2780 * @api_major_version: major queue version
2781 * @api_minor_version: minor queue version
2782 * @cmd_details: pointer to command details structure or NULL
2784 * Get the firmware version from the admin queue commands
2786 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2787 u16 *fw_major_version, u16 *fw_minor_version,
2789 u16 *api_major_version, u16 *api_minor_version,
2790 struct i40e_asq_cmd_details *cmd_details)
2792 struct i40e_aq_desc desc;
2793 struct i40e_aqc_get_version *resp =
2794 (struct i40e_aqc_get_version *)&desc.params.raw;
2795 enum i40e_status_code status;
2797 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2799 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2801 if (status == I40E_SUCCESS) {
2802 if (fw_major_version != NULL)
2803 *fw_major_version = LE16_TO_CPU(resp->fw_major);
2804 if (fw_minor_version != NULL)
2805 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2806 if (fw_build != NULL)
2807 *fw_build = LE32_TO_CPU(resp->fw_build);
2808 if (api_major_version != NULL)
2809 *api_major_version = LE16_TO_CPU(resp->api_major);
2810 if (api_minor_version != NULL)
2811 *api_minor_version = LE16_TO_CPU(resp->api_minor);
2813 /* A workaround to fix the API version in SW */
2814 if (api_major_version && api_minor_version &&
2815 fw_major_version && fw_minor_version &&
2816 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2817 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2818 (*fw_major_version > 4)))
2819 *api_minor_version = 2;
2826 * i40e_aq_send_driver_version
2827 * @hw: pointer to the hw struct
2828 * @dv: driver's major, minor version
2829 * @cmd_details: pointer to command details structure or NULL
2831 * Send the driver version to the firmware
2833 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2834 struct i40e_driver_version *dv,
2835 struct i40e_asq_cmd_details *cmd_details)
2837 struct i40e_aq_desc desc;
2838 struct i40e_aqc_driver_version *cmd =
2839 (struct i40e_aqc_driver_version *)&desc.params.raw;
2840 enum i40e_status_code status;
2844 return I40E_ERR_PARAM;
2846 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2848 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2849 cmd->driver_major_ver = dv->major_version;
2850 cmd->driver_minor_ver = dv->minor_version;
2851 cmd->driver_build_ver = dv->build_version;
2852 cmd->driver_subbuild_ver = dv->subbuild_version;
2855 while (len < sizeof(dv->driver_string) &&
2856 (dv->driver_string[len] < 0x80) &&
2857 dv->driver_string[len])
2859 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2866 * i40e_get_link_status - get status of the HW network link
2867 * @hw: pointer to the hw struct
2868 * @link_up: pointer to bool (true/false = linkup/linkdown)
2870 * Variable link_up true if link is up, false if link is down.
2871 * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2873 * Side effect: LinkStatusEvent reporting becomes enabled
2875 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2877 enum i40e_status_code status = I40E_SUCCESS;
2879 if (hw->phy.get_link_info) {
2880 status = i40e_update_link_info(hw);
2882 if (status != I40E_SUCCESS)
2883 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2887 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2893 * i40e_updatelink_status - update status of the HW network link
2894 * @hw: pointer to the hw struct
2896 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2898 struct i40e_aq_get_phy_abilities_resp abilities;
2899 enum i40e_status_code status = I40E_SUCCESS;
2901 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2905 /* extra checking needed to ensure link info to user is timely */
2906 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2907 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2908 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2909 status = i40e_aq_get_phy_capabilities(hw, false, false,
2914 hw->phy.link_info.req_fec_info =
2915 abilities.fec_cfg_curr_mod_ext_info &
2916 (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS);
2918 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2919 sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2926 * i40e_get_link_speed
2927 * @hw: pointer to the hw struct
2929 * Returns the link speed of the adapter.
2931 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2933 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2934 enum i40e_status_code status = I40E_SUCCESS;
2936 if (hw->phy.get_link_info) {
2937 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2939 if (status != I40E_SUCCESS)
2940 goto i40e_link_speed_exit;
2943 speed = hw->phy.link_info.link_speed;
2945 i40e_link_speed_exit:
2950 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2951 * @hw: pointer to the hw struct
2952 * @uplink_seid: the MAC or other gizmo SEID
2953 * @downlink_seid: the VSI SEID
2954 * @enabled_tc: bitmap of TCs to be enabled
2955 * @default_port: true for default port VSI, false for control port
2956 * @veb_seid: pointer to where to put the resulting VEB SEID
2957 * @enable_stats: true to turn on VEB stats
2958 * @cmd_details: pointer to command details structure or NULL
2960 * This asks the FW to add a VEB between the uplink and downlink
2961 * elements. If the uplink SEID is 0, this will be a floating VEB.
2963 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2964 u16 downlink_seid, u8 enabled_tc,
2965 bool default_port, u16 *veb_seid,
2967 struct i40e_asq_cmd_details *cmd_details)
2969 struct i40e_aq_desc desc;
2970 struct i40e_aqc_add_veb *cmd =
2971 (struct i40e_aqc_add_veb *)&desc.params.raw;
2972 struct i40e_aqc_add_veb_completion *resp =
2973 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2974 enum i40e_status_code status;
2977 /* SEIDs need to either both be set or both be 0 for floating VEB */
2978 if (!!uplink_seid != !!downlink_seid)
2979 return I40E_ERR_PARAM;
2981 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2983 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2984 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2985 cmd->enable_tcs = enabled_tc;
2987 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2989 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2991 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2993 /* reverse logic here: set the bitflag to disable the stats */
2995 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2997 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2999 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3001 if (!status && veb_seid)
3002 *veb_seid = LE16_TO_CPU(resp->veb_seid);
3008 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
3009 * @hw: pointer to the hw struct
3010 * @veb_seid: the SEID of the VEB to query
3011 * @switch_id: the uplink switch id
3012 * @floating: set to true if the VEB is floating
3013 * @statistic_index: index of the stats counter block for this VEB
3014 * @vebs_used: number of VEB's used by function
3015 * @vebs_free: total VEB's not reserved by any function
3016 * @cmd_details: pointer to command details structure or NULL
3018 * This retrieves the parameters for a particular VEB, specified by
3019 * uplink_seid, and returns them to the caller.
3021 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
3022 u16 veb_seid, u16 *switch_id,
3023 bool *floating, u16 *statistic_index,
3024 u16 *vebs_used, u16 *vebs_free,
3025 struct i40e_asq_cmd_details *cmd_details)
3027 struct i40e_aq_desc desc;
3028 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
3029 (struct i40e_aqc_get_veb_parameters_completion *)
3031 enum i40e_status_code status;
3034 return I40E_ERR_PARAM;
3036 i40e_fill_default_direct_cmd_desc(&desc,
3037 i40e_aqc_opc_get_veb_parameters);
3038 cmd_resp->seid = CPU_TO_LE16(veb_seid);
3040 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3045 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
3046 if (statistic_index)
3047 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
3049 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
3051 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
3053 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
3055 if (flags & I40E_AQC_ADD_VEB_FLOATING)
3066 * i40e_aq_add_macvlan
3067 * @hw: pointer to the hw struct
3068 * @seid: VSI for the mac address
3069 * @mv_list: list of macvlans to be added
3070 * @count: length of the list
3071 * @cmd_details: pointer to command details structure or NULL
3073 * Add MAC/VLAN addresses to the HW filtering
3075 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
3076 struct i40e_aqc_add_macvlan_element_data *mv_list,
3077 u16 count, struct i40e_asq_cmd_details *cmd_details)
3079 struct i40e_aq_desc desc;
3080 struct i40e_aqc_macvlan *cmd =
3081 (struct i40e_aqc_macvlan *)&desc.params.raw;
3082 enum i40e_status_code status;
3086 if (count == 0 || !mv_list || !hw)
3087 return I40E_ERR_PARAM;
3089 buf_size = count * sizeof(*mv_list);
3091 /* prep the rest of the request */
3092 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
3093 cmd->num_addresses = CPU_TO_LE16(count);
3094 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3098 for (i = 0; i < count; i++)
3099 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
3101 CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
3103 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3104 if (buf_size > I40E_AQ_LARGE_BUF)
3105 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3107 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3114 * i40e_aq_remove_macvlan
3115 * @hw: pointer to the hw struct
3116 * @seid: VSI for the mac address
3117 * @mv_list: list of macvlans to be removed
3118 * @count: length of the list
3119 * @cmd_details: pointer to command details structure or NULL
3121 * Remove MAC/VLAN addresses from the HW filtering
3123 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
3124 struct i40e_aqc_remove_macvlan_element_data *mv_list,
3125 u16 count, struct i40e_asq_cmd_details *cmd_details)
3127 struct i40e_aq_desc desc;
3128 struct i40e_aqc_macvlan *cmd =
3129 (struct i40e_aqc_macvlan *)&desc.params.raw;
3130 enum i40e_status_code status;
3133 if (count == 0 || !mv_list || !hw)
3134 return I40E_ERR_PARAM;
3136 buf_size = count * sizeof(*mv_list);
3138 /* prep the rest of the request */
3139 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
3140 cmd->num_addresses = CPU_TO_LE16(count);
3141 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3145 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3146 if (buf_size > I40E_AQ_LARGE_BUF)
3147 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3149 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3156 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3157 * @hw: pointer to the hw struct
3158 * @opcode: AQ opcode for add or delete mirror rule
3159 * @sw_seid: Switch SEID (to which rule refers)
3160 * @rule_type: Rule Type (ingress/egress/VLAN)
3161 * @id: Destination VSI SEID or Rule ID
3162 * @count: length of the list
3163 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3164 * @cmd_details: pointer to command details structure or NULL
3165 * @rule_id: Rule ID returned from FW
3166 * @rules_used: Number of rules used in internal switch
3167 * @rules_free: Number of rules free in internal switch
3169 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3170 * VEBs/VEPA elements only
3172 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3173 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3174 u16 count, __le16 *mr_list,
3175 struct i40e_asq_cmd_details *cmd_details,
3176 u16 *rule_id, u16 *rules_used, u16 *rules_free)
3178 struct i40e_aq_desc desc;
3179 struct i40e_aqc_add_delete_mirror_rule *cmd =
3180 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3181 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3182 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3183 enum i40e_status_code status;
3186 buf_size = count * sizeof(*mr_list);
3188 /* prep the rest of the request */
3189 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3190 cmd->seid = CPU_TO_LE16(sw_seid);
3191 cmd->rule_type = CPU_TO_LE16(rule_type &
3192 I40E_AQC_MIRROR_RULE_TYPE_MASK);
3193 cmd->num_entries = CPU_TO_LE16(count);
3194 /* Dest VSI for add, rule_id for delete */
3195 cmd->destination = CPU_TO_LE16(id);
3197 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3199 if (buf_size > I40E_AQ_LARGE_BUF)
3200 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3203 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3205 if (status == I40E_SUCCESS ||
3206 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3208 *rule_id = LE16_TO_CPU(resp->rule_id);
3210 *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3212 *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3218 * i40e_aq_add_mirrorrule - add a mirror rule
3219 * @hw: pointer to the hw struct
3220 * @sw_seid: Switch SEID (to which rule refers)
3221 * @rule_type: Rule Type (ingress/egress/VLAN)
3222 * @dest_vsi: SEID of VSI to which packets will be mirrored
3223 * @count: length of the list
3224 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3225 * @cmd_details: pointer to command details structure or NULL
3226 * @rule_id: Rule ID returned from FW
3227 * @rules_used: Number of rules used in internal switch
3228 * @rules_free: Number of rules free in internal switch
3230 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3232 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3233 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3234 struct i40e_asq_cmd_details *cmd_details,
3235 u16 *rule_id, u16 *rules_used, u16 *rules_free)
3237 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3238 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3239 if (count == 0 || !mr_list)
3240 return I40E_ERR_PARAM;
3243 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3244 rule_type, dest_vsi, count, mr_list,
3245 cmd_details, rule_id, rules_used, rules_free);
3249 * i40e_aq_delete_mirrorrule - delete a mirror rule
3250 * @hw: pointer to the hw struct
3251 * @sw_seid: Switch SEID (to which rule refers)
3252 * @rule_type: Rule Type (ingress/egress/VLAN)
3253 * @count: length of the list
3254 * @rule_id: Rule ID that is returned in the receive desc as part of
3256 * @mr_list: list of mirrored VLAN IDs to be removed
3257 * @cmd_details: pointer to command details structure or NULL
3258 * @rules_used: Number of rules used in internal switch
3259 * @rules_free: Number of rules free in internal switch
3261 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3263 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3264 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3265 struct i40e_asq_cmd_details *cmd_details,
3266 u16 *rules_used, u16 *rules_free)
3268 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3269 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3270 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3271 * mirroring. For other rule_type, count and rule_type should
3274 if (count == 0 || !mr_list)
3275 return I40E_ERR_PARAM;
3278 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3279 rule_type, rule_id, count, mr_list,
3280 cmd_details, NULL, rules_used, rules_free);
3284 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3285 * @hw: pointer to the hw struct
3286 * @seid: VSI for the vlan filters
3287 * @v_list: list of vlan filters to be added
3288 * @count: length of the list
3289 * @cmd_details: pointer to command details structure or NULL
3291 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3292 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3293 u8 count, struct i40e_asq_cmd_details *cmd_details)
3295 struct i40e_aq_desc desc;
3296 struct i40e_aqc_macvlan *cmd =
3297 (struct i40e_aqc_macvlan *)&desc.params.raw;
3298 enum i40e_status_code status;
3301 if (count == 0 || !v_list || !hw)
3302 return I40E_ERR_PARAM;
3304 buf_size = count * sizeof(*v_list);
3306 /* prep the rest of the request */
3307 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3308 cmd->num_addresses = CPU_TO_LE16(count);
3309 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3313 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3314 if (buf_size > I40E_AQ_LARGE_BUF)
3315 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3317 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3324 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3325 * @hw: pointer to the hw struct
3326 * @seid: VSI for the vlan filters
3327 * @v_list: list of macvlans to be removed
3328 * @count: length of the list
3329 * @cmd_details: pointer to command details structure or NULL
3331 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3332 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3333 u8 count, struct i40e_asq_cmd_details *cmd_details)
3335 struct i40e_aq_desc desc;
3336 struct i40e_aqc_macvlan *cmd =
3337 (struct i40e_aqc_macvlan *)&desc.params.raw;
3338 enum i40e_status_code status;
3341 if (count == 0 || !v_list || !hw)
3342 return I40E_ERR_PARAM;
3344 buf_size = count * sizeof(*v_list);
3346 /* prep the rest of the request */
3347 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3348 cmd->num_addresses = CPU_TO_LE16(count);
3349 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3353 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3354 if (buf_size > I40E_AQ_LARGE_BUF)
3355 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3357 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3364 * i40e_aq_send_msg_to_vf
3365 * @hw: pointer to the hardware structure
3366 * @vfid: vf id to send msg
3367 * @v_opcode: opcodes for VF-PF communication
3368 * @v_retval: return error code
3369 * @msg: pointer to the msg buffer
3370 * @msglen: msg length
3371 * @cmd_details: pointer to command details
3375 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3376 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3377 struct i40e_asq_cmd_details *cmd_details)
3379 struct i40e_aq_desc desc;
3380 struct i40e_aqc_pf_vf_message *cmd =
3381 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3382 enum i40e_status_code status;
3384 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3385 cmd->id = CPU_TO_LE32(vfid);
3386 desc.cookie_high = CPU_TO_LE32(v_opcode);
3387 desc.cookie_low = CPU_TO_LE32(v_retval);
3388 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3390 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3392 if (msglen > I40E_AQ_LARGE_BUF)
3393 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3394 desc.datalen = CPU_TO_LE16(msglen);
3396 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3402 * i40e_aq_debug_read_register
3403 * @hw: pointer to the hw struct
3404 * @reg_addr: register address
3405 * @reg_val: register value
3406 * @cmd_details: pointer to command details structure or NULL
3408 * Read the register using the admin queue commands
3410 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3411 u32 reg_addr, u64 *reg_val,
3412 struct i40e_asq_cmd_details *cmd_details)
3414 struct i40e_aq_desc desc;
3415 struct i40e_aqc_debug_reg_read_write *cmd_resp =
3416 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3417 enum i40e_status_code status;
3419 if (reg_val == NULL)
3420 return I40E_ERR_PARAM;
3422 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3424 cmd_resp->address = CPU_TO_LE32(reg_addr);
3426 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3428 if (status == I40E_SUCCESS) {
3429 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3430 (u64)LE32_TO_CPU(cmd_resp->value_low);
3437 * i40e_aq_debug_write_register
3438 * @hw: pointer to the hw struct
3439 * @reg_addr: register address
3440 * @reg_val: register value
3441 * @cmd_details: pointer to command details structure or NULL
3443 * Write to a register using the admin queue commands
3445 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3446 u32 reg_addr, u64 reg_val,
3447 struct i40e_asq_cmd_details *cmd_details)
3449 struct i40e_aq_desc desc;
3450 struct i40e_aqc_debug_reg_read_write *cmd =
3451 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3452 enum i40e_status_code status;
3454 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3456 cmd->address = CPU_TO_LE32(reg_addr);
3457 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3458 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3460 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3466 * i40e_aq_request_resource
3467 * @hw: pointer to the hw struct
3468 * @resource: resource id
3469 * @access: access type
3470 * @sdp_number: resource number
3471 * @timeout: the maximum time in ms that the driver may hold the resource
3472 * @cmd_details: pointer to command details structure or NULL
3474 * requests common resource using the admin queue commands
3476 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3477 enum i40e_aq_resources_ids resource,
3478 enum i40e_aq_resource_access_type access,
3479 u8 sdp_number, u64 *timeout,
3480 struct i40e_asq_cmd_details *cmd_details)
3482 struct i40e_aq_desc desc;
3483 struct i40e_aqc_request_resource *cmd_resp =
3484 (struct i40e_aqc_request_resource *)&desc.params.raw;
3485 enum i40e_status_code status;
3487 DEBUGFUNC("i40e_aq_request_resource");
3489 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3491 cmd_resp->resource_id = CPU_TO_LE16(resource);
3492 cmd_resp->access_type = CPU_TO_LE16(access);
3493 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3495 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3496 /* The completion specifies the maximum time in ms that the driver
3497 * may hold the resource in the Timeout field.
3498 * If the resource is held by someone else, the command completes with
3499 * busy return value and the timeout field indicates the maximum time
3500 * the current owner of the resource has to free it.
3502 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3503 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3509 * i40e_aq_release_resource
3510 * @hw: pointer to the hw struct
3511 * @resource: resource id
3512 * @sdp_number: resource number
3513 * @cmd_details: pointer to command details structure or NULL
3515 * release common resource using the admin queue commands
3517 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3518 enum i40e_aq_resources_ids resource,
3520 struct i40e_asq_cmd_details *cmd_details)
3522 struct i40e_aq_desc desc;
3523 struct i40e_aqc_request_resource *cmd =
3524 (struct i40e_aqc_request_resource *)&desc.params.raw;
3525 enum i40e_status_code status;
3527 DEBUGFUNC("i40e_aq_release_resource");
3529 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3531 cmd->resource_id = CPU_TO_LE16(resource);
3532 cmd->resource_number = CPU_TO_LE32(sdp_number);
3534 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3541 * @hw: pointer to the hw struct
3542 * @module_pointer: module pointer location in words from the NVM beginning
3543 * @offset: byte offset from the module beginning
3544 * @length: length of the section to be read (in bytes from the offset)
3545 * @data: command buffer (size [bytes] = length)
3546 * @last_command: tells if this is the last command in a series
3547 * @cmd_details: pointer to command details structure or NULL
3549 * Read the NVM using the admin queue commands
3551 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3552 u32 offset, u16 length, void *data,
3554 struct i40e_asq_cmd_details *cmd_details)
3556 struct i40e_aq_desc desc;
3557 struct i40e_aqc_nvm_update *cmd =
3558 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3559 enum i40e_status_code status;
3561 DEBUGFUNC("i40e_aq_read_nvm");
3563 /* In offset the highest byte must be zeroed. */
3564 if (offset & 0xFF000000) {
3565 status = I40E_ERR_PARAM;
3566 goto i40e_aq_read_nvm_exit;
3569 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3571 /* If this is the last command in a series, set the proper flag. */
3573 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3574 cmd->module_pointer = module_pointer;
3575 cmd->offset = CPU_TO_LE32(offset);
3576 cmd->length = CPU_TO_LE16(length);
3578 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3579 if (length > I40E_AQ_LARGE_BUF)
3580 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3582 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3584 i40e_aq_read_nvm_exit:
3589 * i40e_aq_read_nvm_config - read an nvm config block
3590 * @hw: pointer to the hw struct
3591 * @cmd_flags: NVM access admin command bits
3592 * @field_id: field or feature id
3593 * @data: buffer for result
3594 * @buf_size: buffer size
3595 * @element_count: pointer to count of elements read by FW
3596 * @cmd_details: pointer to command details structure or NULL
3598 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3599 u8 cmd_flags, u32 field_id, void *data,
3600 u16 buf_size, u16 *element_count,
3601 struct i40e_asq_cmd_details *cmd_details)
3603 struct i40e_aq_desc desc;
3604 struct i40e_aqc_nvm_config_read *cmd =
3605 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3606 enum i40e_status_code status;
3608 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3609 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3610 if (buf_size > I40E_AQ_LARGE_BUF)
3611 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3613 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3614 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3615 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3616 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3618 cmd->element_id_msw = 0;
3620 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3622 if (!status && element_count)
3623 *element_count = LE16_TO_CPU(cmd->element_count);
3629 * i40e_aq_write_nvm_config - write an nvm config block
3630 * @hw: pointer to the hw struct
3631 * @cmd_flags: NVM access admin command bits
3632 * @data: buffer for result
3633 * @buf_size: buffer size
3634 * @element_count: count of elements to be written
3635 * @cmd_details: pointer to command details structure or NULL
3637 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3638 u8 cmd_flags, void *data, u16 buf_size,
3640 struct i40e_asq_cmd_details *cmd_details)
3642 struct i40e_aq_desc desc;
3643 struct i40e_aqc_nvm_config_write *cmd =
3644 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3645 enum i40e_status_code status;
3647 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3648 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3649 if (buf_size > I40E_AQ_LARGE_BUF)
3650 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3652 cmd->element_count = CPU_TO_LE16(element_count);
3653 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3654 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3660 * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3661 * @hw: pointer to the hw struct
3662 * @buff: buffer for result
3663 * @buff_size: buffer size
3664 * @cmd_details: pointer to command details structure or NULL
3666 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3667 void *buff, u16 buff_size,
3668 struct i40e_asq_cmd_details *cmd_details)
3670 struct i40e_aq_desc desc;
3671 enum i40e_status_code status;
3673 UNREFERENCED_2PARAMETER(buff, buff_size);
3675 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3676 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3677 if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3678 status = I40E_ERR_NOT_IMPLEMENTED;
3685 * @hw: pointer to the hw struct
3686 * @module_pointer: module pointer location in words from the NVM beginning
3687 * @offset: offset in the module (expressed in 4 KB from module's beginning)
3688 * @length: length of the section to be erased (expressed in 4 KB)
3689 * @last_command: tells if this is the last command in a series
3690 * @cmd_details: pointer to command details structure or NULL
3692 * Erase the NVM sector using the admin queue commands
3694 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3695 u32 offset, u16 length, bool last_command,
3696 struct i40e_asq_cmd_details *cmd_details)
3698 struct i40e_aq_desc desc;
3699 struct i40e_aqc_nvm_update *cmd =
3700 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3701 enum i40e_status_code status;
3703 DEBUGFUNC("i40e_aq_erase_nvm");
3705 /* In offset the highest byte must be zeroed. */
3706 if (offset & 0xFF000000) {
3707 status = I40E_ERR_PARAM;
3708 goto i40e_aq_erase_nvm_exit;
3711 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3713 /* If this is the last command in a series, set the proper flag. */
3715 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3716 cmd->module_pointer = module_pointer;
3717 cmd->offset = CPU_TO_LE32(offset);
3718 cmd->length = CPU_TO_LE16(length);
3720 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3722 i40e_aq_erase_nvm_exit:
3727 * i40e_parse_discover_capabilities
3728 * @hw: pointer to the hw struct
3729 * @buff: pointer to a buffer containing device/function capability records
3730 * @cap_count: number of capability records in the list
3731 * @list_type_opc: type of capabilities list to parse
3733 * Parse the device/function capabilities list.
3735 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3737 enum i40e_admin_queue_opc list_type_opc)
3739 struct i40e_aqc_list_capabilities_element_resp *cap;
3740 u32 valid_functions, num_functions;
3741 u32 number, logical_id, phys_id;
3742 struct i40e_hw_capabilities *p;
3743 enum i40e_status_code status;
3744 u16 id, ocp_cfg_word0;
3748 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3750 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3751 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3752 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3753 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3757 for (i = 0; i < cap_count; i++, cap++) {
3758 id = LE16_TO_CPU(cap->id);
3759 number = LE32_TO_CPU(cap->number);
3760 logical_id = LE32_TO_CPU(cap->logical_id);
3761 phys_id = LE32_TO_CPU(cap->phys_id);
3762 major_rev = cap->major_rev;
3765 case I40E_AQ_CAP_ID_SWITCH_MODE:
3766 p->switch_mode = number;
3767 i40e_debug(hw, I40E_DEBUG_INIT,
3768 "HW Capability: Switch mode = %d\n",
3771 case I40E_AQ_CAP_ID_MNG_MODE:
3772 p->management_mode = number;
3773 if (major_rev > 1) {
3774 p->mng_protocols_over_mctp = logical_id;
3775 i40e_debug(hw, I40E_DEBUG_INIT,
3776 "HW Capability: Protocols over MCTP = %d\n",
3777 p->mng_protocols_over_mctp);
3779 p->mng_protocols_over_mctp = 0;
3781 i40e_debug(hw, I40E_DEBUG_INIT,
3782 "HW Capability: Management Mode = %d\n",
3783 p->management_mode);
3785 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3786 p->npar_enable = number;
3787 i40e_debug(hw, I40E_DEBUG_INIT,
3788 "HW Capability: NPAR enable = %d\n",
3791 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3793 i40e_debug(hw, I40E_DEBUG_INIT,
3794 "HW Capability: OS2BMC = %d\n", p->os2bmc);
3796 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3797 p->valid_functions = number;
3798 i40e_debug(hw, I40E_DEBUG_INIT,
3799 "HW Capability: Valid Functions = %d\n",
3800 p->valid_functions);
3802 case I40E_AQ_CAP_ID_SRIOV:
3804 p->sr_iov_1_1 = true;
3805 i40e_debug(hw, I40E_DEBUG_INIT,
3806 "HW Capability: SR-IOV = %d\n",
3809 case I40E_AQ_CAP_ID_VF:
3810 p->num_vfs = number;
3811 p->vf_base_id = logical_id;
3812 i40e_debug(hw, I40E_DEBUG_INIT,
3813 "HW Capability: VF count = %d\n",
3815 i40e_debug(hw, I40E_DEBUG_INIT,
3816 "HW Capability: VF base_id = %d\n",
3819 case I40E_AQ_CAP_ID_VMDQ:
3822 i40e_debug(hw, I40E_DEBUG_INIT,
3823 "HW Capability: VMDQ = %d\n", p->vmdq);
3825 case I40E_AQ_CAP_ID_8021QBG:
3827 p->evb_802_1_qbg = true;
3828 i40e_debug(hw, I40E_DEBUG_INIT,
3829 "HW Capability: 802.1Qbg = %d\n", number);
3831 case I40E_AQ_CAP_ID_8021QBR:
3833 p->evb_802_1_qbh = true;
3834 i40e_debug(hw, I40E_DEBUG_INIT,
3835 "HW Capability: 802.1Qbh = %d\n", number);
3837 case I40E_AQ_CAP_ID_VSI:
3838 p->num_vsis = number;
3839 i40e_debug(hw, I40E_DEBUG_INIT,
3840 "HW Capability: VSI count = %d\n",
3843 case I40E_AQ_CAP_ID_DCB:
3846 p->enabled_tcmap = logical_id;
3849 i40e_debug(hw, I40E_DEBUG_INIT,
3850 "HW Capability: DCB = %d\n", p->dcb);
3851 i40e_debug(hw, I40E_DEBUG_INIT,
3852 "HW Capability: TC Mapping = %d\n",
3854 i40e_debug(hw, I40E_DEBUG_INIT,
3855 "HW Capability: TC Max = %d\n", p->maxtc);
3857 case I40E_AQ_CAP_ID_FCOE:
3860 i40e_debug(hw, I40E_DEBUG_INIT,
3861 "HW Capability: FCOE = %d\n", p->fcoe);
3863 case I40E_AQ_CAP_ID_ISCSI:
3866 i40e_debug(hw, I40E_DEBUG_INIT,
3867 "HW Capability: iSCSI = %d\n", p->iscsi);
3869 case I40E_AQ_CAP_ID_RSS:
3871 p->rss_table_size = number;
3872 p->rss_table_entry_width = logical_id;
3873 i40e_debug(hw, I40E_DEBUG_INIT,
3874 "HW Capability: RSS = %d\n", p->rss);
3875 i40e_debug(hw, I40E_DEBUG_INIT,
3876 "HW Capability: RSS table size = %d\n",
3878 i40e_debug(hw, I40E_DEBUG_INIT,
3879 "HW Capability: RSS table width = %d\n",
3880 p->rss_table_entry_width);
3882 case I40E_AQ_CAP_ID_RXQ:
3883 p->num_rx_qp = number;
3884 p->base_queue = phys_id;
3885 i40e_debug(hw, I40E_DEBUG_INIT,
3886 "HW Capability: Rx QP = %d\n", number);
3887 i40e_debug(hw, I40E_DEBUG_INIT,
3888 "HW Capability: base_queue = %d\n",
3891 case I40E_AQ_CAP_ID_TXQ:
3892 p->num_tx_qp = number;
3893 p->base_queue = phys_id;
3894 i40e_debug(hw, I40E_DEBUG_INIT,
3895 "HW Capability: Tx QP = %d\n", number);
3896 i40e_debug(hw, I40E_DEBUG_INIT,
3897 "HW Capability: base_queue = %d\n",
3900 case I40E_AQ_CAP_ID_MSIX:
3901 p->num_msix_vectors = number;
3902 i40e_debug(hw, I40E_DEBUG_INIT,
3903 "HW Capability: MSIX vector count = %d\n",
3904 p->num_msix_vectors);
3906 case I40E_AQ_CAP_ID_VF_MSIX:
3907 p->num_msix_vectors_vf = number;
3908 i40e_debug(hw, I40E_DEBUG_INIT,
3909 "HW Capability: MSIX VF vector count = %d\n",
3910 p->num_msix_vectors_vf);
3912 case I40E_AQ_CAP_ID_FLEX10:
3913 if (major_rev == 1) {
3915 p->flex10_enable = true;
3916 p->flex10_capable = true;
3919 /* Capability revision >= 2 */
3921 p->flex10_enable = true;
3923 p->flex10_capable = true;
3925 p->flex10_mode = logical_id;
3926 p->flex10_status = phys_id;
3927 i40e_debug(hw, I40E_DEBUG_INIT,
3928 "HW Capability: Flex10 mode = %d\n",
3930 i40e_debug(hw, I40E_DEBUG_INIT,
3931 "HW Capability: Flex10 status = %d\n",
3934 case I40E_AQ_CAP_ID_CEM:
3937 i40e_debug(hw, I40E_DEBUG_INIT,
3938 "HW Capability: CEM = %d\n", p->mgmt_cem);
3940 case I40E_AQ_CAP_ID_IWARP:
3943 i40e_debug(hw, I40E_DEBUG_INIT,
3944 "HW Capability: iWARP = %d\n", p->iwarp);
3946 case I40E_AQ_CAP_ID_LED:
3947 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3948 p->led[phys_id] = true;
3949 i40e_debug(hw, I40E_DEBUG_INIT,
3950 "HW Capability: LED - PIN %d\n", phys_id);
3952 case I40E_AQ_CAP_ID_SDP:
3953 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3954 p->sdp[phys_id] = true;
3955 i40e_debug(hw, I40E_DEBUG_INIT,
3956 "HW Capability: SDP - PIN %d\n", phys_id);
3958 case I40E_AQ_CAP_ID_MDIO:
3960 p->mdio_port_num = phys_id;
3961 p->mdio_port_mode = logical_id;
3963 i40e_debug(hw, I40E_DEBUG_INIT,
3964 "HW Capability: MDIO port number = %d\n",
3966 i40e_debug(hw, I40E_DEBUG_INIT,
3967 "HW Capability: MDIO port mode = %d\n",
3970 case I40E_AQ_CAP_ID_1588:
3972 p->ieee_1588 = true;
3973 i40e_debug(hw, I40E_DEBUG_INIT,
3974 "HW Capability: IEEE 1588 = %d\n",
3977 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3979 p->fd_filters_guaranteed = number;
3980 p->fd_filters_best_effort = logical_id;
3981 i40e_debug(hw, I40E_DEBUG_INIT,
3982 "HW Capability: Flow Director = 1\n");
3983 i40e_debug(hw, I40E_DEBUG_INIT,
3984 "HW Capability: Guaranteed FD filters = %d\n",
3985 p->fd_filters_guaranteed);
3987 case I40E_AQ_CAP_ID_WSR_PROT:
3988 p->wr_csr_prot = (u64)number;
3989 p->wr_csr_prot |= (u64)logical_id << 32;
3990 i40e_debug(hw, I40E_DEBUG_INIT,
3991 "HW Capability: wr_csr_prot = 0x%llX\n\n",
3992 (p->wr_csr_prot & 0xffff));
3994 case I40E_AQ_CAP_ID_NVM_MGMT:
3995 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3996 p->sec_rev_disabled = true;
3997 if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3998 p->update_disabled = true;
4000 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
4001 hw->num_wol_proxy_filters = (u16)number;
4002 hw->wol_proxy_vsi_seid = (u16)logical_id;
4003 p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
4004 if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
4005 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
4007 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
4008 p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
4009 i40e_debug(hw, I40E_DEBUG_INIT,
4010 "HW Capability: WOL proxy filters = %d\n",
4011 hw->num_wol_proxy_filters);
4019 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
4021 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
4024 /* count the enabled ports (aka the "not disabled" ports) */
4026 for (i = 0; i < 4; i++) {
4027 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
4030 /* use AQ read to get the physical register offset instead
4031 * of the port relative offset
4033 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
4034 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
4038 /* OCP cards case: if a mezz is removed the ethernet port is at
4039 * disabled state in PRTGEN_CNF register. Additional NVM read is
4040 * needed in order to check if we are dealing with OCP card.
4041 * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting
4042 * physical ports results in wrong partition id calculation and thus
4043 * not supporting WoL.
4045 if (hw->mac.type == I40E_MAC_X722) {
4046 if (i40e_acquire_nvm(hw, I40E_RESOURCE_READ) == I40E_SUCCESS) {
4047 status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR,
4048 2 * I40E_SR_OCP_CFG_WORD0,
4049 sizeof(ocp_cfg_word0),
4050 &ocp_cfg_word0, true, NULL);
4051 if (status == I40E_SUCCESS &&
4052 (ocp_cfg_word0 & I40E_SR_OCP_ENABLED))
4054 i40e_release_nvm(hw);
4058 valid_functions = p->valid_functions;
4060 while (valid_functions) {
4061 if (valid_functions & 1)
4063 valid_functions >>= 1;
4066 /* partition id is 1-based, and functions are evenly spread
4067 * across the ports as partitions
4069 if (hw->num_ports != 0) {
4070 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
4071 hw->num_partitions = num_functions / hw->num_ports;
4074 /* additional HW specific goodies that might
4075 * someday be HW version specific
4077 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
4081 * i40e_aq_discover_capabilities
4082 * @hw: pointer to the hw struct
4083 * @buff: a virtual buffer to hold the capabilities
4084 * @buff_size: Size of the virtual buffer
4085 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
4086 * @list_type_opc: capabilities type to discover - pass in the command opcode
4087 * @cmd_details: pointer to command details structure or NULL
4089 * Get the device capabilities descriptions from the firmware
4091 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
4092 void *buff, u16 buff_size, u16 *data_size,
4093 enum i40e_admin_queue_opc list_type_opc,
4094 struct i40e_asq_cmd_details *cmd_details)
4096 struct i40e_aqc_list_capabilites *cmd;
4097 struct i40e_aq_desc desc;
4098 enum i40e_status_code status = I40E_SUCCESS;
4100 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
4102 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
4103 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
4104 status = I40E_ERR_PARAM;
4108 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
4110 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4111 if (buff_size > I40E_AQ_LARGE_BUF)
4112 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4114 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4115 *data_size = LE16_TO_CPU(desc.datalen);
4120 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
4128 * i40e_aq_update_nvm
4129 * @hw: pointer to the hw struct
4130 * @module_pointer: module pointer location in words from the NVM beginning
4131 * @offset: byte offset from the module beginning
4132 * @length: length of the section to be written (in bytes from the offset)
4133 * @data: command buffer (size [bytes] = length)
4134 * @last_command: tells if this is the last command in a series
4135 * @preservation_flags: Preservation mode flags
4136 * @cmd_details: pointer to command details structure or NULL
4138 * Update the NVM using the admin queue commands
4140 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
4141 u32 offset, u16 length, void *data,
4142 bool last_command, u8 preservation_flags,
4143 struct i40e_asq_cmd_details *cmd_details)
4145 struct i40e_aq_desc desc;
4146 struct i40e_aqc_nvm_update *cmd =
4147 (struct i40e_aqc_nvm_update *)&desc.params.raw;
4148 enum i40e_status_code status;
4150 DEBUGFUNC("i40e_aq_update_nvm");
4152 /* In offset the highest byte must be zeroed. */
4153 if (offset & 0xFF000000) {
4154 status = I40E_ERR_PARAM;
4155 goto i40e_aq_update_nvm_exit;
4158 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4160 /* If this is the last command in a series, set the proper flag. */
4162 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
4163 if (hw->mac.type == I40E_MAC_X722) {
4164 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED)
4165 cmd->command_flags |=
4166 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED <<
4167 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4168 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL)
4169 cmd->command_flags |=
4170 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL <<
4171 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4173 cmd->module_pointer = module_pointer;
4174 cmd->offset = CPU_TO_LE32(offset);
4175 cmd->length = CPU_TO_LE16(length);
4177 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4178 if (length > I40E_AQ_LARGE_BUF)
4179 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4181 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
4183 i40e_aq_update_nvm_exit:
4188 * i40e_aq_rearrange_nvm
4189 * @hw: pointer to the hw struct
4190 * @rearrange_nvm: defines direction of rearrangement
4191 * @cmd_details: pointer to command details structure or NULL
4193 * Rearrange NVM structure, available only for transition FW
4195 enum i40e_status_code i40e_aq_rearrange_nvm(struct i40e_hw *hw,
4197 struct i40e_asq_cmd_details *cmd_details)
4199 struct i40e_aqc_nvm_update *cmd;
4200 enum i40e_status_code status;
4201 struct i40e_aq_desc desc;
4203 DEBUGFUNC("i40e_aq_rearrange_nvm");
4205 cmd = (struct i40e_aqc_nvm_update *)&desc.params.raw;
4207 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4209 rearrange_nvm &= (I40E_AQ_NVM_REARRANGE_TO_FLAT |
4210 I40E_AQ_NVM_REARRANGE_TO_STRUCT);
4212 if (!rearrange_nvm) {
4213 status = I40E_ERR_PARAM;
4214 goto i40e_aq_rearrange_nvm_exit;
4217 cmd->command_flags |= rearrange_nvm;
4218 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4220 i40e_aq_rearrange_nvm_exit:
4225 * i40e_aq_nvm_progress
4226 * @hw: pointer to the hw struct
4227 * @progress: pointer to progress returned from AQ
4228 * @cmd_details: pointer to command details structure or NULL
4230 * Gets progress of flash rearrangement process
4232 enum i40e_status_code i40e_aq_nvm_progress(struct i40e_hw *hw, u8 *progress,
4233 struct i40e_asq_cmd_details *cmd_details)
4235 enum i40e_status_code status;
4236 struct i40e_aq_desc desc;
4238 DEBUGFUNC("i40e_aq_nvm_progress");
4240 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_progress);
4241 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4242 *progress = desc.params.raw[0];
4247 * i40e_aq_get_lldp_mib
4248 * @hw: pointer to the hw struct
4249 * @bridge_type: type of bridge requested
4250 * @mib_type: Local, Remote or both Local and Remote MIBs
4251 * @buff: pointer to a user supplied buffer to store the MIB block
4252 * @buff_size: size of the buffer (in bytes)
4253 * @local_len : length of the returned Local LLDP MIB
4254 * @remote_len: length of the returned Remote LLDP MIB
4255 * @cmd_details: pointer to command details structure or NULL
4257 * Requests the complete LLDP MIB (entire packet).
4259 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4260 u8 mib_type, void *buff, u16 buff_size,
4261 u16 *local_len, u16 *remote_len,
4262 struct i40e_asq_cmd_details *cmd_details)
4264 struct i40e_aq_desc desc;
4265 struct i40e_aqc_lldp_get_mib *cmd =
4266 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4267 struct i40e_aqc_lldp_get_mib *resp =
4268 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4269 enum i40e_status_code status;
4271 if (buff_size == 0 || !buff)
4272 return I40E_ERR_PARAM;
4274 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4275 /* Indirect Command */
4276 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4278 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4279 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4280 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4282 desc.datalen = CPU_TO_LE16(buff_size);
4284 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4285 if (buff_size > I40E_AQ_LARGE_BUF)
4286 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4288 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4290 if (local_len != NULL)
4291 *local_len = LE16_TO_CPU(resp->local_len);
4292 if (remote_len != NULL)
4293 *remote_len = LE16_TO_CPU(resp->remote_len);
4300 * i40e_aq_set_lldp_mib - Set the LLDP MIB
4301 * @hw: pointer to the hw struct
4302 * @mib_type: Local, Remote or both Local and Remote MIBs
4303 * @buff: pointer to a user supplied buffer to store the MIB block
4304 * @buff_size: size of the buffer (in bytes)
4305 * @cmd_details: pointer to command details structure or NULL
4309 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4310 u8 mib_type, void *buff, u16 buff_size,
4311 struct i40e_asq_cmd_details *cmd_details)
4313 struct i40e_aq_desc desc;
4314 struct i40e_aqc_lldp_set_local_mib *cmd =
4315 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4316 enum i40e_status_code status;
4318 if (buff_size == 0 || !buff)
4319 return I40E_ERR_PARAM;
4321 i40e_fill_default_direct_cmd_desc(&desc,
4322 i40e_aqc_opc_lldp_set_local_mib);
4323 /* Indirect Command */
4324 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4325 if (buff_size > I40E_AQ_LARGE_BUF)
4326 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4327 desc.datalen = CPU_TO_LE16(buff_size);
4329 cmd->type = mib_type;
4330 cmd->length = CPU_TO_LE16(buff_size);
4331 cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)buff));
4332 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4334 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4339 * i40e_aq_cfg_lldp_mib_change_event
4340 * @hw: pointer to the hw struct
4341 * @enable_update: Enable or Disable event posting
4342 * @cmd_details: pointer to command details structure or NULL
4344 * Enable or Disable posting of an event on ARQ when LLDP MIB
4345 * associated with the interface changes
4347 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4349 struct i40e_asq_cmd_details *cmd_details)
4351 struct i40e_aq_desc desc;
4352 struct i40e_aqc_lldp_update_mib *cmd =
4353 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4354 enum i40e_status_code status;
4356 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4359 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4361 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4367 * i40e_aq_restore_lldp
4368 * @hw: pointer to the hw struct
4369 * @setting: pointer to factory setting variable or NULL
4370 * @restore: True if factory settings should be restored
4371 * @cmd_details: pointer to command details structure or NULL
4373 * Restore LLDP Agent factory settings if @restore set to True. In other case
4374 * only returns factory setting in AQ response.
4376 enum i40e_status_code
4377 i40e_aq_restore_lldp(struct i40e_hw *hw, u8 *setting, bool restore,
4378 struct i40e_asq_cmd_details *cmd_details)
4380 struct i40e_aq_desc desc;
4381 struct i40e_aqc_lldp_restore *cmd =
4382 (struct i40e_aqc_lldp_restore *)&desc.params.raw;
4383 enum i40e_status_code status;
4385 if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)) {
4386 i40e_debug(hw, I40E_DEBUG_ALL,
4387 "Restore LLDP not supported by current FW version.\n");
4388 return I40E_ERR_DEVICE_NOT_SUPPORTED;
4391 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_restore);
4394 cmd->command |= I40E_AQ_LLDP_AGENT_RESTORE;
4396 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4399 *setting = cmd->command & 1;
4406 * @hw: pointer to the hw struct
4407 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4408 * @persist: True if stop of LLDP should be persistent across power cycles
4409 * @cmd_details: pointer to command details structure or NULL
4411 * Stop or Shutdown the embedded LLDP Agent
4413 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4415 struct i40e_asq_cmd_details *cmd_details)
4417 struct i40e_aq_desc desc;
4418 struct i40e_aqc_lldp_stop *cmd =
4419 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4420 enum i40e_status_code status;
4422 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4425 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4428 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)
4429 cmd->command |= I40E_AQ_LLDP_AGENT_STOP_PERSIST;
4431 i40e_debug(hw, I40E_DEBUG_ALL,
4432 "Persistent Stop LLDP not supported by current FW version.\n");
4435 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4441 * i40e_aq_start_lldp
4442 * @hw: pointer to the hw struct
4443 * @persist: True if start of LLDP should be persistent across power cycles
4444 * @cmd_details: pointer to command details structure or NULL
4446 * Start the embedded LLDP Agent on all ports.
4448 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4450 struct i40e_asq_cmd_details *cmd_details)
4452 struct i40e_aq_desc desc;
4453 struct i40e_aqc_lldp_start *cmd =
4454 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4455 enum i40e_status_code status;
4457 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4459 cmd->command = I40E_AQ_LLDP_AGENT_START;
4462 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)
4463 cmd->command |= I40E_AQ_LLDP_AGENT_START_PERSIST;
4465 i40e_debug(hw, I40E_DEBUG_ALL,
4466 "Persistent Start LLDP not supported by current FW version.\n");
4469 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4475 * i40e_aq_set_dcb_parameters
4476 * @hw: pointer to the hw struct
4477 * @cmd_details: pointer to command details structure or NULL
4478 * @dcb_enable: True if DCB configuration needs to be applied
4481 enum i40e_status_code
4482 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable,
4483 struct i40e_asq_cmd_details *cmd_details)
4485 struct i40e_aq_desc desc;
4486 struct i40e_aqc_set_dcb_parameters *cmd =
4487 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw;
4488 enum i40e_status_code status;
4490 if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_STOPPABLE))
4491 return I40E_ERR_DEVICE_NOT_SUPPORTED;
4493 i40e_fill_default_direct_cmd_desc(&desc,
4494 i40e_aqc_opc_set_dcb_parameters);
4497 cmd->valid_flags = I40E_DCB_VALID;
4498 cmd->command = I40E_AQ_DCB_SET_AGENT;
4500 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4506 * i40e_aq_get_cee_dcb_config
4507 * @hw: pointer to the hw struct
4508 * @buff: response buffer that stores CEE operational configuration
4509 * @buff_size: size of the buffer passed
4510 * @cmd_details: pointer to command details structure or NULL
4512 * Get CEE DCBX mode operational configuration from firmware
4514 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4515 void *buff, u16 buff_size,
4516 struct i40e_asq_cmd_details *cmd_details)
4518 struct i40e_aq_desc desc;
4519 enum i40e_status_code status;
4521 if (buff_size == 0 || !buff)
4522 return I40E_ERR_PARAM;
4524 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4526 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4527 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4534 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4535 * @hw: pointer to the hw struct
4536 * @start_agent: True if DCBx Agent needs to be Started
4537 * False if DCBx Agent needs to be Stopped
4538 * @cmd_details: pointer to command details structure or NULL
4540 * Start/Stop the embedded dcbx Agent
4542 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4544 struct i40e_asq_cmd_details *cmd_details)
4546 struct i40e_aq_desc desc;
4547 struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4548 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4550 enum i40e_status_code status;
4552 i40e_fill_default_direct_cmd_desc(&desc,
4553 i40e_aqc_opc_lldp_stop_start_spec_agent);
4556 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4558 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4564 * i40e_aq_add_udp_tunnel
4565 * @hw: pointer to the hw struct
4566 * @udp_port: the UDP port to add in Host byte order
4567 * @protocol_index: protocol index type
4568 * @filter_index: pointer to filter index
4569 * @cmd_details: pointer to command details structure or NULL
4571 * Note: Firmware expects the udp_port value to be in Little Endian format,
4572 * and this function will call CPU_TO_LE16 to convert from Host byte order to
4573 * Little Endian order.
4575 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4576 u16 udp_port, u8 protocol_index,
4578 struct i40e_asq_cmd_details *cmd_details)
4580 struct i40e_aq_desc desc;
4581 struct i40e_aqc_add_udp_tunnel *cmd =
4582 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4583 struct i40e_aqc_del_udp_tunnel_completion *resp =
4584 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4585 enum i40e_status_code status;
4587 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4589 cmd->udp_port = CPU_TO_LE16(udp_port);
4590 cmd->protocol_type = protocol_index;
4592 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4594 if (!status && filter_index)
4595 *filter_index = resp->index;
4601 * i40e_aq_del_udp_tunnel
4602 * @hw: pointer to the hw struct
4603 * @index: filter index
4604 * @cmd_details: pointer to command details structure or NULL
4606 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4607 struct i40e_asq_cmd_details *cmd_details)
4609 struct i40e_aq_desc desc;
4610 struct i40e_aqc_remove_udp_tunnel *cmd =
4611 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4612 enum i40e_status_code status;
4614 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4618 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4624 * i40e_aq_get_switch_resource_alloc (0x0204)
4625 * @hw: pointer to the hw struct
4626 * @num_entries: pointer to u8 to store the number of resource entries returned
4627 * @buf: pointer to a user supplied buffer. This buffer must be large enough
4628 * to store the resource information for all resource types. Each
4629 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
4630 * @count: size, in bytes, of the buffer provided
4631 * @cmd_details: pointer to command details structure or NULL
4633 * Query the resources allocated to a function.
4635 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4637 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4639 struct i40e_asq_cmd_details *cmd_details)
4641 struct i40e_aq_desc desc;
4642 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4643 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4644 enum i40e_status_code status;
4645 u16 length = count * sizeof(*buf);
4647 i40e_fill_default_direct_cmd_desc(&desc,
4648 i40e_aqc_opc_get_switch_resource_alloc);
4650 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4651 if (length > I40E_AQ_LARGE_BUF)
4652 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4654 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4656 if (!status && num_entries)
4657 *num_entries = cmd_resp->num_entries;
4663 * i40e_aq_delete_element - Delete switch element
4664 * @hw: pointer to the hw struct
4665 * @seid: the SEID to delete from the switch
4666 * @cmd_details: pointer to command details structure or NULL
4668 * This deletes a switch element from the switch.
4670 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4671 struct i40e_asq_cmd_details *cmd_details)
4673 struct i40e_aq_desc desc;
4674 struct i40e_aqc_switch_seid *cmd =
4675 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4676 enum i40e_status_code status;
4679 return I40E_ERR_PARAM;
4681 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4683 cmd->seid = CPU_TO_LE16(seid);
4685 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4691 * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4692 * @hw: pointer to the hw struct
4693 * @flags: component flags
4694 * @mac_seid: uplink seid (MAC SEID)
4695 * @vsi_seid: connected vsi seid
4696 * @ret_seid: seid of create pv component
4698 * This instantiates an i40e port virtualizer with specified flags.
4699 * Depending on specified flags the port virtualizer can act as a
4700 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4702 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4703 u16 mac_seid, u16 vsi_seid,
4706 struct i40e_aq_desc desc;
4707 struct i40e_aqc_add_update_pv *cmd =
4708 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4709 struct i40e_aqc_add_update_pv_completion *resp =
4710 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4711 enum i40e_status_code status;
4714 return I40E_ERR_PARAM;
4716 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4717 cmd->command_flags = CPU_TO_LE16(flags);
4718 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4719 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4721 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4722 if (!status && ret_seid)
4723 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4729 * i40e_aq_add_tag - Add an S/E-tag
4730 * @hw: pointer to the hw struct
4731 * @direct_to_queue: should s-tag direct flow to a specific queue
4732 * @vsi_seid: VSI SEID to use this tag
4733 * @tag: value of the tag
4734 * @queue_num: queue number, only valid is direct_to_queue is true
4735 * @tags_used: return value, number of tags in use by this PF
4736 * @tags_free: return value, number of unallocated tags
4737 * @cmd_details: pointer to command details structure or NULL
4739 * This associates an S- or E-tag to a VSI in the switch complex. It returns
4740 * the number of tags allocated by the PF, and the number of unallocated
4743 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4744 u16 vsi_seid, u16 tag, u16 queue_num,
4745 u16 *tags_used, u16 *tags_free,
4746 struct i40e_asq_cmd_details *cmd_details)
4748 struct i40e_aq_desc desc;
4749 struct i40e_aqc_add_tag *cmd =
4750 (struct i40e_aqc_add_tag *)&desc.params.raw;
4751 struct i40e_aqc_add_remove_tag_completion *resp =
4752 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4753 enum i40e_status_code status;
4756 return I40E_ERR_PARAM;
4758 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4760 cmd->seid = CPU_TO_LE16(vsi_seid);
4761 cmd->tag = CPU_TO_LE16(tag);
4762 if (direct_to_queue) {
4763 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4764 cmd->queue_number = CPU_TO_LE16(queue_num);
4767 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4770 if (tags_used != NULL)
4771 *tags_used = LE16_TO_CPU(resp->tags_used);
4772 if (tags_free != NULL)
4773 *tags_free = LE16_TO_CPU(resp->tags_free);
4780 * i40e_aq_remove_tag - Remove an S- or E-tag
4781 * @hw: pointer to the hw struct
4782 * @vsi_seid: VSI SEID this tag is associated with
4783 * @tag: value of the S-tag to delete
4784 * @tags_used: return value, number of tags in use by this PF
4785 * @tags_free: return value, number of unallocated tags
4786 * @cmd_details: pointer to command details structure or NULL
4788 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
4789 * the number of tags allocated by the PF, and the number of unallocated
4792 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4793 u16 tag, u16 *tags_used, u16 *tags_free,
4794 struct i40e_asq_cmd_details *cmd_details)
4796 struct i40e_aq_desc desc;
4797 struct i40e_aqc_remove_tag *cmd =
4798 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4799 struct i40e_aqc_add_remove_tag_completion *resp =
4800 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4801 enum i40e_status_code status;
4804 return I40E_ERR_PARAM;
4806 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4808 cmd->seid = CPU_TO_LE16(vsi_seid);
4809 cmd->tag = CPU_TO_LE16(tag);
4811 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4814 if (tags_used != NULL)
4815 *tags_used = LE16_TO_CPU(resp->tags_used);
4816 if (tags_free != NULL)
4817 *tags_free = LE16_TO_CPU(resp->tags_free);
4824 * i40e_aq_add_mcast_etag - Add a multicast E-tag
4825 * @hw: pointer to the hw struct
4826 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4827 * @etag: value of E-tag to add
4828 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4829 * @buf: address of indirect buffer
4830 * @tags_used: return value, number of E-tags in use by this port
4831 * @tags_free: return value, number of unallocated M-tags
4832 * @cmd_details: pointer to command details structure or NULL
4834 * This associates a multicast E-tag to a port virtualizer. It will return
4835 * the number of tags allocated by the PF, and the number of unallocated
4838 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4839 * num_tags_in_buf long.
4841 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4842 u16 etag, u8 num_tags_in_buf, void *buf,
4843 u16 *tags_used, u16 *tags_free,
4844 struct i40e_asq_cmd_details *cmd_details)
4846 struct i40e_aq_desc desc;
4847 struct i40e_aqc_add_remove_mcast_etag *cmd =
4848 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4849 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4850 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4851 enum i40e_status_code status;
4852 u16 length = sizeof(u16) * num_tags_in_buf;
4854 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4855 return I40E_ERR_PARAM;
4857 i40e_fill_default_direct_cmd_desc(&desc,
4858 i40e_aqc_opc_add_multicast_etag);
4860 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4861 cmd->etag = CPU_TO_LE16(etag);
4862 cmd->num_unicast_etags = num_tags_in_buf;
4864 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4865 if (length > I40E_AQ_LARGE_BUF)
4866 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4868 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4871 if (tags_used != NULL)
4872 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4873 if (tags_free != NULL)
4874 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4881 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4882 * @hw: pointer to the hw struct
4883 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4884 * @etag: value of the E-tag to remove
4885 * @tags_used: return value, number of tags in use by this port
4886 * @tags_free: return value, number of unallocated tags
4887 * @cmd_details: pointer to command details structure or NULL
4889 * This deletes an E-tag from the port virtualizer. It will return
4890 * the number of tags allocated by the port, and the number of unallocated
4893 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4894 u16 etag, u16 *tags_used, u16 *tags_free,
4895 struct i40e_asq_cmd_details *cmd_details)
4897 struct i40e_aq_desc desc;
4898 struct i40e_aqc_add_remove_mcast_etag *cmd =
4899 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4900 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4901 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4902 enum i40e_status_code status;
4906 return I40E_ERR_PARAM;
4908 i40e_fill_default_direct_cmd_desc(&desc,
4909 i40e_aqc_opc_remove_multicast_etag);
4911 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4912 cmd->etag = CPU_TO_LE16(etag);
4914 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4917 if (tags_used != NULL)
4918 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4919 if (tags_free != NULL)
4920 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4927 * i40e_aq_update_tag - Update an S/E-tag
4928 * @hw: pointer to the hw struct
4929 * @vsi_seid: VSI SEID using this S-tag
4930 * @old_tag: old tag value
4931 * @new_tag: new tag value
4932 * @tags_used: return value, number of tags in use by this PF
4933 * @tags_free: return value, number of unallocated tags
4934 * @cmd_details: pointer to command details structure or NULL
4936 * This updates the value of the tag currently attached to this VSI
4937 * in the switch complex. It will return the number of tags allocated
4938 * by the PF, and the number of unallocated tags available.
4940 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4941 u16 old_tag, u16 new_tag, u16 *tags_used,
4943 struct i40e_asq_cmd_details *cmd_details)
4945 struct i40e_aq_desc desc;
4946 struct i40e_aqc_update_tag *cmd =
4947 (struct i40e_aqc_update_tag *)&desc.params.raw;
4948 struct i40e_aqc_update_tag_completion *resp =
4949 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4950 enum i40e_status_code status;
4953 return I40E_ERR_PARAM;
4955 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4957 cmd->seid = CPU_TO_LE16(vsi_seid);
4958 cmd->old_tag = CPU_TO_LE16(old_tag);
4959 cmd->new_tag = CPU_TO_LE16(new_tag);
4961 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4964 if (tags_used != NULL)
4965 *tags_used = LE16_TO_CPU(resp->tags_used);
4966 if (tags_free != NULL)
4967 *tags_free = LE16_TO_CPU(resp->tags_free);
4974 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4975 * @hw: pointer to the hw struct
4976 * @tcmap: TC map for request/release any ignore PFC condition
4977 * @request: request or release ignore PFC condition
4978 * @tcmap_ret: return TCs for which PFC is currently ignored
4979 * @cmd_details: pointer to command details structure or NULL
4981 * This sends out request/release to ignore PFC condition for a TC.
4982 * It will return the TCs for which PFC is currently ignored.
4984 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4985 bool request, u8 *tcmap_ret,
4986 struct i40e_asq_cmd_details *cmd_details)
4988 struct i40e_aq_desc desc;
4989 struct i40e_aqc_pfc_ignore *cmd_resp =
4990 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4991 enum i40e_status_code status;
4993 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4996 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4998 cmd_resp->tc_bitmap = tcmap;
5000 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5003 if (tcmap_ret != NULL)
5004 *tcmap_ret = cmd_resp->tc_bitmap;
5011 * i40e_aq_dcb_updated - DCB Updated Command
5012 * @hw: pointer to the hw struct
5013 * @cmd_details: pointer to command details structure or NULL
5015 * When LLDP is handled in PF this command is used by the PF
5016 * to notify EMP that a DCB setting is modified.
5017 * When LLDP is handled in EMP this command is used by the PF
5018 * to notify EMP whenever one of the following parameters get
5020 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
5021 * - PCIRTT in PRTDCB_GENC.PCIRTT
5022 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
5023 * EMP will return when the shared RPB settings have been
5024 * recomputed and modified. The retval field in the descriptor
5025 * will be set to 0 when RPB is modified.
5027 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
5028 struct i40e_asq_cmd_details *cmd_details)
5030 struct i40e_aq_desc desc;
5031 enum i40e_status_code status;
5033 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
5035 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5041 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
5042 * @hw: pointer to the hw struct
5043 * @seid: defines the SEID of the switch for which the stats are requested
5044 * @vlan_id: the VLAN ID for which the statistics are requested
5045 * @stat_index: index of the statistics counters block assigned to this VLAN
5046 * @cmd_details: pointer to command details structure or NULL
5048 * XL710 supports 128 smonVlanStats counters.This command is used to
5049 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
5052 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
5053 u16 vlan_id, u16 *stat_index,
5054 struct i40e_asq_cmd_details *cmd_details)
5056 struct i40e_aq_desc desc;
5057 struct i40e_aqc_add_remove_statistics *cmd_resp =
5058 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5059 enum i40e_status_code status;
5061 if ((seid == 0) || (stat_index == NULL))
5062 return I40E_ERR_PARAM;
5064 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
5066 cmd_resp->seid = CPU_TO_LE16(seid);
5067 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
5069 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5071 if (!status && stat_index)
5072 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
5078 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
5079 * @hw: pointer to the hw struct
5080 * @seid: defines the SEID of the switch for which the stats are requested
5081 * @vlan_id: the VLAN ID for which the statistics are requested
5082 * @stat_index: index of the statistics counters block assigned to this VLAN
5083 * @cmd_details: pointer to command details structure or NULL
5085 * XL710 supports 128 smonVlanStats counters.This command is used to
5086 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
5089 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
5090 u16 vlan_id, u16 stat_index,
5091 struct i40e_asq_cmd_details *cmd_details)
5093 struct i40e_aq_desc desc;
5094 struct i40e_aqc_add_remove_statistics *cmd =
5095 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5096 enum i40e_status_code status;
5099 return I40E_ERR_PARAM;
5101 i40e_fill_default_direct_cmd_desc(&desc,
5102 i40e_aqc_opc_remove_statistics);
5104 cmd->seid = CPU_TO_LE16(seid);
5105 cmd->vlan = CPU_TO_LE16(vlan_id);
5106 cmd->stat_index = CPU_TO_LE16(stat_index);
5108 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5114 * i40e_aq_set_port_parameters - set physical port parameters.
5115 * @hw: pointer to the hw struct
5116 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
5117 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
5118 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
5119 * @double_vlan: if set double VLAN is enabled
5120 * @cmd_details: pointer to command details structure or NULL
5122 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
5123 u16 bad_frame_vsi, bool save_bad_pac,
5124 bool pad_short_pac, bool double_vlan,
5125 struct i40e_asq_cmd_details *cmd_details)
5127 struct i40e_aqc_set_port_parameters *cmd;
5128 enum i40e_status_code status;
5129 struct i40e_aq_desc desc;
5130 u16 command_flags = 0;
5132 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
5134 i40e_fill_default_direct_cmd_desc(&desc,
5135 i40e_aqc_opc_set_port_parameters);
5137 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
5139 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
5141 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
5143 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
5144 cmd->command_flags = CPU_TO_LE16(command_flags);
5146 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5152 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
5153 * @hw: pointer to the hw struct
5154 * @seid: seid for the physical port/switching component/vsi
5155 * @buff: Indirect buffer to hold data parameters and response
5156 * @buff_size: Indirect buffer size
5157 * @opcode: Tx scheduler AQ command opcode
5158 * @cmd_details: pointer to command details structure or NULL
5160 * Generic command handler for Tx scheduler AQ commands
5162 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
5163 void *buff, u16 buff_size,
5164 enum i40e_admin_queue_opc opcode,
5165 struct i40e_asq_cmd_details *cmd_details)
5167 struct i40e_aq_desc desc;
5168 struct i40e_aqc_tx_sched_ind *cmd =
5169 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
5170 enum i40e_status_code status;
5171 bool cmd_param_flag = false;
5174 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
5175 case i40e_aqc_opc_configure_vsi_tc_bw:
5176 case i40e_aqc_opc_enable_switching_comp_ets:
5177 case i40e_aqc_opc_modify_switching_comp_ets:
5178 case i40e_aqc_opc_disable_switching_comp_ets:
5179 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
5180 case i40e_aqc_opc_configure_switching_comp_bw_config:
5181 cmd_param_flag = true;
5183 case i40e_aqc_opc_query_vsi_bw_config:
5184 case i40e_aqc_opc_query_vsi_ets_sla_config:
5185 case i40e_aqc_opc_query_switching_comp_ets_config:
5186 case i40e_aqc_opc_query_port_ets_config:
5187 case i40e_aqc_opc_query_switching_comp_bw_config:
5188 cmd_param_flag = false;
5191 return I40E_ERR_PARAM;
5194 i40e_fill_default_direct_cmd_desc(&desc, opcode);
5196 /* Indirect command */
5197 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5199 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5200 if (buff_size > I40E_AQ_LARGE_BUF)
5201 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5203 desc.datalen = CPU_TO_LE16(buff_size);
5205 cmd->vsi_seid = CPU_TO_LE16(seid);
5207 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5213 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5214 * @hw: pointer to the hw struct
5216 * @credit: BW limit credits (0 = disabled)
5217 * @max_credit: Max BW limit credits
5218 * @cmd_details: pointer to command details structure or NULL
5220 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5221 u16 seid, u16 credit, u8 max_credit,
5222 struct i40e_asq_cmd_details *cmd_details)
5224 struct i40e_aq_desc desc;
5225 struct i40e_aqc_configure_vsi_bw_limit *cmd =
5226 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5227 enum i40e_status_code status;
5229 i40e_fill_default_direct_cmd_desc(&desc,
5230 i40e_aqc_opc_configure_vsi_bw_limit);
5232 cmd->vsi_seid = CPU_TO_LE16(seid);
5233 cmd->credit = CPU_TO_LE16(credit);
5234 cmd->max_credit = max_credit;
5236 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5242 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5243 * @hw: pointer to the hw struct
5244 * @seid: switching component seid
5245 * @credit: BW limit credits (0 = disabled)
5246 * @max_bw: Max BW limit credits
5247 * @cmd_details: pointer to command details structure or NULL
5249 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5250 u16 seid, u16 credit, u8 max_bw,
5251 struct i40e_asq_cmd_details *cmd_details)
5253 struct i40e_aq_desc desc;
5254 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5255 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5256 enum i40e_status_code status;
5258 i40e_fill_default_direct_cmd_desc(&desc,
5259 i40e_aqc_opc_configure_switching_comp_bw_limit);
5261 cmd->seid = CPU_TO_LE16(seid);
5262 cmd->credit = CPU_TO_LE16(credit);
5263 cmd->max_bw = max_bw;
5265 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5271 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5272 * @hw: pointer to the hw struct
5274 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5275 * @cmd_details: pointer to command details structure or NULL
5277 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5279 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5280 struct i40e_asq_cmd_details *cmd_details)
5282 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5283 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5288 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5289 * @hw: pointer to the hw struct
5291 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5292 * @cmd_details: pointer to command details structure or NULL
5294 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5296 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5297 struct i40e_asq_cmd_details *cmd_details)
5299 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5300 i40e_aqc_opc_configure_vsi_tc_bw,
5305 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5306 * @hw: pointer to the hw struct
5307 * @seid: seid of the switching component connected to Physical Port
5308 * @ets_data: Buffer holding ETS parameters
5309 * @opcode: Tx scheduler AQ command opcode
5310 * @cmd_details: pointer to command details structure or NULL
5312 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5314 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5315 enum i40e_admin_queue_opc opcode,
5316 struct i40e_asq_cmd_details *cmd_details)
5318 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5319 sizeof(*ets_data), opcode, cmd_details);
5323 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5324 * @hw: pointer to the hw struct
5325 * @seid: seid of the switching component
5326 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5327 * @cmd_details: pointer to command details structure or NULL
5329 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5331 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5332 struct i40e_asq_cmd_details *cmd_details)
5334 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5335 i40e_aqc_opc_configure_switching_comp_bw_config,
5340 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5341 * @hw: pointer to the hw struct
5342 * @seid: seid of the switching component
5343 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5344 * @cmd_details: pointer to command details structure or NULL
5346 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5347 struct i40e_hw *hw, u16 seid,
5348 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5349 struct i40e_asq_cmd_details *cmd_details)
5351 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5352 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5357 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5358 * @hw: pointer to the hw struct
5359 * @seid: seid of the VSI
5360 * @bw_data: Buffer to hold VSI BW configuration
5361 * @cmd_details: pointer to command details structure or NULL
5363 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5365 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5366 struct i40e_asq_cmd_details *cmd_details)
5368 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5369 i40e_aqc_opc_query_vsi_bw_config,
5374 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5375 * @hw: pointer to the hw struct
5376 * @seid: seid of the VSI
5377 * @bw_data: Buffer to hold VSI BW configuration per TC
5378 * @cmd_details: pointer to command details structure or NULL
5380 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5382 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5383 struct i40e_asq_cmd_details *cmd_details)
5385 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5386 i40e_aqc_opc_query_vsi_ets_sla_config,
5391 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5392 * @hw: pointer to the hw struct
5393 * @seid: seid of the switching component
5394 * @bw_data: Buffer to hold switching component's per TC BW config
5395 * @cmd_details: pointer to command details structure or NULL
5397 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5399 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5400 struct i40e_asq_cmd_details *cmd_details)
5402 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5403 i40e_aqc_opc_query_switching_comp_ets_config,
5408 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5409 * @hw: pointer to the hw struct
5410 * @seid: seid of the VSI or switching component connected to Physical Port
5411 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5412 * @cmd_details: pointer to command details structure or NULL
5414 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5416 struct i40e_aqc_query_port_ets_config_resp *bw_data,
5417 struct i40e_asq_cmd_details *cmd_details)
5419 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5420 i40e_aqc_opc_query_port_ets_config,
5425 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5426 * @hw: pointer to the hw struct
5427 * @seid: seid of the switching component
5428 * @bw_data: Buffer to hold switching component's BW configuration
5429 * @cmd_details: pointer to command details structure or NULL
5431 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5433 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5434 struct i40e_asq_cmd_details *cmd_details)
5436 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5437 i40e_aqc_opc_query_switching_comp_bw_config,
5442 * i40e_validate_filter_settings
5443 * @hw: pointer to the hardware structure
5444 * @settings: Filter control settings
5446 * Check and validate the filter control settings passed.
5447 * The function checks for the valid filter/context sizes being
5448 * passed for FCoE and PE.
5450 * Returns I40E_SUCCESS if the values passed are valid and within
5451 * range else returns an error.
5453 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5454 struct i40e_filter_control_settings *settings)
5456 u32 fcoe_cntx_size, fcoe_filt_size;
5457 u32 pe_cntx_size, pe_filt_size;
5462 /* Validate FCoE settings passed */
5463 switch (settings->fcoe_filt_num) {
5464 case I40E_HASH_FILTER_SIZE_1K:
5465 case I40E_HASH_FILTER_SIZE_2K:
5466 case I40E_HASH_FILTER_SIZE_4K:
5467 case I40E_HASH_FILTER_SIZE_8K:
5468 case I40E_HASH_FILTER_SIZE_16K:
5469 case I40E_HASH_FILTER_SIZE_32K:
5470 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5471 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5474 return I40E_ERR_PARAM;
5477 switch (settings->fcoe_cntx_num) {
5478 case I40E_DMA_CNTX_SIZE_512:
5479 case I40E_DMA_CNTX_SIZE_1K:
5480 case I40E_DMA_CNTX_SIZE_2K:
5481 case I40E_DMA_CNTX_SIZE_4K:
5482 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5483 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5486 return I40E_ERR_PARAM;
5489 /* Validate PE settings passed */
5490 switch (settings->pe_filt_num) {
5491 case I40E_HASH_FILTER_SIZE_1K:
5492 case I40E_HASH_FILTER_SIZE_2K:
5493 case I40E_HASH_FILTER_SIZE_4K:
5494 case I40E_HASH_FILTER_SIZE_8K:
5495 case I40E_HASH_FILTER_SIZE_16K:
5496 case I40E_HASH_FILTER_SIZE_32K:
5497 case I40E_HASH_FILTER_SIZE_64K:
5498 case I40E_HASH_FILTER_SIZE_128K:
5499 case I40E_HASH_FILTER_SIZE_256K:
5500 case I40E_HASH_FILTER_SIZE_512K:
5501 case I40E_HASH_FILTER_SIZE_1M:
5502 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5503 pe_filt_size <<= (u32)settings->pe_filt_num;
5506 return I40E_ERR_PARAM;
5509 switch (settings->pe_cntx_num) {
5510 case I40E_DMA_CNTX_SIZE_512:
5511 case I40E_DMA_CNTX_SIZE_1K:
5512 case I40E_DMA_CNTX_SIZE_2K:
5513 case I40E_DMA_CNTX_SIZE_4K:
5514 case I40E_DMA_CNTX_SIZE_8K:
5515 case I40E_DMA_CNTX_SIZE_16K:
5516 case I40E_DMA_CNTX_SIZE_32K:
5517 case I40E_DMA_CNTX_SIZE_64K:
5518 case I40E_DMA_CNTX_SIZE_128K:
5519 case I40E_DMA_CNTX_SIZE_256K:
5520 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5521 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5524 return I40E_ERR_PARAM;
5527 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5528 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5529 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5530 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5531 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
5532 return I40E_ERR_INVALID_SIZE;
5534 return I40E_SUCCESS;
5538 * i40e_set_filter_control
5539 * @hw: pointer to the hardware structure
5540 * @settings: Filter control settings
5542 * Set the Queue Filters for PE/FCoE and enable filters required
5543 * for a single PF. It is expected that these settings are programmed
5544 * at the driver initialization time.
5546 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5547 struct i40e_filter_control_settings *settings)
5549 enum i40e_status_code ret = I40E_SUCCESS;
5550 u32 hash_lut_size = 0;
5554 return I40E_ERR_PARAM;
5556 /* Validate the input settings */
5557 ret = i40e_validate_filter_settings(hw, settings);
5561 /* Read the PF Queue Filter control register */
5562 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5564 /* Program required PE hash buckets for the PF */
5565 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5566 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5567 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5568 /* Program required PE contexts for the PF */
5569 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5570 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5571 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5573 /* Program required FCoE hash buckets for the PF */
5574 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5575 val |= ((u32)settings->fcoe_filt_num <<
5576 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5577 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5578 /* Program required FCoE DDP contexts for the PF */
5579 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5580 val |= ((u32)settings->fcoe_cntx_num <<
5581 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5582 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5584 /* Program Hash LUT size for the PF */
5585 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5586 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5588 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5589 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5591 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5592 if (settings->enable_fdir)
5593 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5594 if (settings->enable_ethtype)
5595 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5596 if (settings->enable_macvlan)
5597 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5599 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5601 return I40E_SUCCESS;
5605 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5606 * @hw: pointer to the hw struct
5607 * @mac_addr: MAC address to use in the filter
5608 * @ethtype: Ethertype to use in the filter
5609 * @flags: Flags that needs to be applied to the filter
5610 * @vsi_seid: seid of the control VSI
5611 * @queue: VSI queue number to send the packet to
5612 * @is_add: Add control packet filter if True else remove
5613 * @stats: Structure to hold information on control filter counts
5614 * @cmd_details: pointer to command details structure or NULL
5616 * This command will Add or Remove control packet filter for a control VSI.
5617 * In return it will update the total number of perfect filter count in
5620 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5621 u8 *mac_addr, u16 ethtype, u16 flags,
5622 u16 vsi_seid, u16 queue, bool is_add,
5623 struct i40e_control_filter_stats *stats,
5624 struct i40e_asq_cmd_details *cmd_details)
5626 struct i40e_aq_desc desc;
5627 struct i40e_aqc_add_remove_control_packet_filter *cmd =
5628 (struct i40e_aqc_add_remove_control_packet_filter *)
5630 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5631 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5633 enum i40e_status_code status;
5636 return I40E_ERR_PARAM;
5639 i40e_fill_default_direct_cmd_desc(&desc,
5640 i40e_aqc_opc_add_control_packet_filter);
5641 cmd->queue = CPU_TO_LE16(queue);
5643 i40e_fill_default_direct_cmd_desc(&desc,
5644 i40e_aqc_opc_remove_control_packet_filter);
5648 i40e_memcpy(cmd->mac, mac_addr, ETH_ALEN,
5649 I40E_NONDMA_TO_NONDMA);
5651 cmd->etype = CPU_TO_LE16(ethtype);
5652 cmd->flags = CPU_TO_LE16(flags);
5653 cmd->seid = CPU_TO_LE16(vsi_seid);
5655 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5657 if (!status && stats) {
5658 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5659 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5660 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5661 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5668 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5669 * @hw: pointer to the hw struct
5670 * @seid: VSI seid to add ethertype filter from
5672 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5675 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5676 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5677 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5678 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5679 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5680 enum i40e_status_code status;
5682 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5683 seid, 0, true, NULL,
5686 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5690 * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5691 * @filters: list of cloud filters
5692 * @filter_count: length of list
5694 * There's an issue in the device where the Geneve VNI layout needs
5695 * to be shifted 1 byte over from the VxLAN VNI
5697 STATIC void i40e_fix_up_geneve_vni(
5698 struct i40e_aqc_cloud_filters_element_data *filters,
5701 struct i40e_aqc_cloud_filters_element_data *f = filters;
5704 for (i = 0; i < filter_count; i++) {
5708 tnl_type = (LE16_TO_CPU(f[i].flags) &
5709 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5710 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5711 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5712 ti = LE32_TO_CPU(f[i].tenant_id);
5713 f[i].tenant_id = CPU_TO_LE32(ti << 8);
5719 * i40e_aq_add_cloud_filters
5720 * @hw: pointer to the hardware structure
5721 * @seid: VSI seid to add cloud filters from
5722 * @filters: Buffer which contains the filters to be added
5723 * @filter_count: number of filters contained in the buffer
5725 * Set the cloud filters for a given VSI. The contents of the
5726 * i40e_aqc_cloud_filters_element_data are filled
5727 * in by the caller of the function.
5730 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5732 struct i40e_aqc_cloud_filters_element_data *filters,
5735 struct i40e_aq_desc desc;
5736 struct i40e_aqc_add_remove_cloud_filters *cmd =
5737 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5738 enum i40e_status_code status;
5741 i40e_fill_default_direct_cmd_desc(&desc,
5742 i40e_aqc_opc_add_cloud_filters);
5744 buff_len = filter_count * sizeof(*filters);
5745 desc.datalen = CPU_TO_LE16(buff_len);
5746 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5747 cmd->num_filters = filter_count;
5748 cmd->seid = CPU_TO_LE16(seid);
5750 i40e_fix_up_geneve_vni(filters, filter_count);
5752 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5758 * i40e_aq_add_cloud_filters_bb
5759 * @hw: pointer to the hardware structure
5760 * @seid: VSI seid to add cloud filters from
5761 * @filters: Buffer which contains the filters in big buffer to be added
5762 * @filter_count: number of filters contained in the buffer
5764 * Set the cloud filters for a given VSI. The contents of the
5765 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5769 enum i40e_status_code
5770 i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5771 struct i40e_aqc_cloud_filters_element_bb *filters,
5774 struct i40e_aq_desc desc;
5775 struct i40e_aqc_add_remove_cloud_filters *cmd =
5776 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5777 enum i40e_status_code status;
5781 i40e_fill_default_direct_cmd_desc(&desc,
5782 i40e_aqc_opc_add_cloud_filters);
5784 buff_len = filter_count * sizeof(*filters);
5785 desc.datalen = CPU_TO_LE16(buff_len);
5786 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5787 cmd->num_filters = filter_count;
5788 cmd->seid = CPU_TO_LE16(seid);
5789 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5791 for (i = 0; i < filter_count; i++) {
5795 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5796 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5797 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5799 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5800 * one more byte further than normally used for Tenant ID in
5801 * other tunnel types.
5803 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5804 ti = LE32_TO_CPU(filters[i].element.tenant_id);
5805 filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5809 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5815 * i40e_aq_rem_cloud_filters
5816 * @hw: pointer to the hardware structure
5817 * @seid: VSI seid to remove cloud filters from
5818 * @filters: Buffer which contains the filters to be removed
5819 * @filter_count: number of filters contained in the buffer
5821 * Remove the cloud filters for a given VSI. The contents of the
5822 * i40e_aqc_cloud_filters_element_data are filled in by the caller
5826 enum i40e_status_code
5827 i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid,
5828 struct i40e_aqc_cloud_filters_element_data *filters,
5831 struct i40e_aq_desc desc;
5832 struct i40e_aqc_add_remove_cloud_filters *cmd =
5833 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5834 enum i40e_status_code status;
5837 i40e_fill_default_direct_cmd_desc(&desc,
5838 i40e_aqc_opc_remove_cloud_filters);
5840 buff_len = filter_count * sizeof(*filters);
5841 desc.datalen = CPU_TO_LE16(buff_len);
5842 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5843 cmd->num_filters = filter_count;
5844 cmd->seid = CPU_TO_LE16(seid);
5846 i40e_fix_up_geneve_vni(filters, filter_count);
5848 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5854 * i40e_aq_rem_cloud_filters_bb
5855 * @hw: pointer to the hardware structure
5856 * @seid: VSI seid to remove cloud filters from
5857 * @filters: Buffer which contains the filters in big buffer to be removed
5858 * @filter_count: number of filters contained in the buffer
5860 * Remove the big buffer cloud filters for a given VSI. The contents of the
5861 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5865 enum i40e_status_code
5866 i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5867 struct i40e_aqc_cloud_filters_element_bb *filters,
5870 struct i40e_aq_desc desc;
5871 struct i40e_aqc_add_remove_cloud_filters *cmd =
5872 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5873 enum i40e_status_code status;
5877 i40e_fill_default_direct_cmd_desc(&desc,
5878 i40e_aqc_opc_remove_cloud_filters);
5880 buff_len = filter_count * sizeof(*filters);
5881 desc.datalen = CPU_TO_LE16(buff_len);
5882 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5883 cmd->num_filters = filter_count;
5884 cmd->seid = CPU_TO_LE16(seid);
5885 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5887 for (i = 0; i < filter_count; i++) {
5891 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5892 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5893 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5895 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5896 * one more byte further than normally used for Tenant ID in
5897 * other tunnel types.
5899 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5900 ti = LE32_TO_CPU(filters[i].element.tenant_id);
5901 filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5905 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5911 * i40e_aq_replace_cloud_filters - Replace cloud filter command
5912 * @hw: pointer to the hw struct
5913 * @filters: pointer to the i40e_aqc_replace_cloud_filter_cmd struct
5914 * @cmd_buf: pointer to the i40e_aqc_replace_cloud_filter_cmd_buf struct
5918 i40e_status_code i40e_aq_replace_cloud_filters(struct i40e_hw *hw,
5919 struct i40e_aqc_replace_cloud_filters_cmd *filters,
5920 struct i40e_aqc_replace_cloud_filters_cmd_buf *cmd_buf)
5922 struct i40e_aq_desc desc;
5923 struct i40e_aqc_replace_cloud_filters_cmd *cmd =
5924 (struct i40e_aqc_replace_cloud_filters_cmd *)&desc.params.raw;
5925 enum i40e_status_code status = I40E_SUCCESS;
5928 /* X722 doesn't support this command */
5929 if (hw->mac.type == I40E_MAC_X722)
5930 return I40E_ERR_DEVICE_NOT_SUPPORTED;
5932 /* need FW version greater than 6.00 */
5933 if (hw->aq.fw_maj_ver < 6)
5934 return I40E_NOT_SUPPORTED;
5936 i40e_fill_default_direct_cmd_desc(&desc,
5937 i40e_aqc_opc_replace_cloud_filters);
5939 desc.datalen = CPU_TO_LE16(32);
5940 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5941 cmd->old_filter_type = filters->old_filter_type;
5942 cmd->new_filter_type = filters->new_filter_type;
5943 cmd->valid_flags = filters->valid_flags;
5944 cmd->tr_bit = filters->tr_bit;
5945 cmd->tr_bit2 = filters->tr_bit2;
5947 status = i40e_asq_send_command(hw, &desc, cmd_buf,
5948 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf), NULL);
5950 /* for get cloud filters command */
5951 for (i = 0; i < 32; i += 4) {
5952 cmd_buf->filters[i / 4].filter_type = cmd_buf->data[i];
5953 cmd_buf->filters[i / 4].input[0] = cmd_buf->data[i + 1];
5954 cmd_buf->filters[i / 4].input[1] = cmd_buf->data[i + 2];
5955 cmd_buf->filters[i / 4].input[2] = cmd_buf->data[i + 3];
5963 * i40e_aq_alternate_write
5964 * @hw: pointer to the hardware structure
5965 * @reg_addr0: address of first dword to be read
5966 * @reg_val0: value to be written under 'reg_addr0'
5967 * @reg_addr1: address of second dword to be read
5968 * @reg_val1: value to be written under 'reg_addr1'
5970 * Write one or two dwords to alternate structure. Fields are indicated
5971 * by 'reg_addr0' and 'reg_addr1' register numbers.
5974 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5975 u32 reg_addr0, u32 reg_val0,
5976 u32 reg_addr1, u32 reg_val1)
5978 struct i40e_aq_desc desc;
5979 struct i40e_aqc_alternate_write *cmd_resp =
5980 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5981 enum i40e_status_code status;
5983 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5984 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5985 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5986 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5987 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5989 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5995 * i40e_aq_alternate_write_indirect
5996 * @hw: pointer to the hardware structure
5997 * @addr: address of a first register to be modified
5998 * @dw_count: number of alternate structure fields to write
5999 * @buffer: pointer to the command buffer
6001 * Write 'dw_count' dwords from 'buffer' to alternate structure
6002 * starting at 'addr'.
6005 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
6006 u32 addr, u32 dw_count, void *buffer)
6008 struct i40e_aq_desc desc;
6009 struct i40e_aqc_alternate_ind_write *cmd_resp =
6010 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
6011 enum i40e_status_code status;
6014 return I40E_ERR_PARAM;
6016 /* Indirect command */
6017 i40e_fill_default_direct_cmd_desc(&desc,
6018 i40e_aqc_opc_alternate_write_indirect);
6020 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6021 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6022 if (dw_count > (I40E_AQ_LARGE_BUF/4))
6023 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6025 cmd_resp->address = CPU_TO_LE32(addr);
6026 cmd_resp->length = CPU_TO_LE32(dw_count);
6028 status = i40e_asq_send_command(hw, &desc, buffer,
6029 I40E_LO_DWORD(4*dw_count), NULL);
6035 * i40e_aq_alternate_read
6036 * @hw: pointer to the hardware structure
6037 * @reg_addr0: address of first dword to be read
6038 * @reg_val0: pointer for data read from 'reg_addr0'
6039 * @reg_addr1: address of second dword to be read
6040 * @reg_val1: pointer for data read from 'reg_addr1'
6042 * Read one or two dwords from alternate structure. Fields are indicated
6043 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
6044 * is not passed then only register at 'reg_addr0' is read.
6047 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
6048 u32 reg_addr0, u32 *reg_val0,
6049 u32 reg_addr1, u32 *reg_val1)
6051 struct i40e_aq_desc desc;
6052 struct i40e_aqc_alternate_write *cmd_resp =
6053 (struct i40e_aqc_alternate_write *)&desc.params.raw;
6054 enum i40e_status_code status;
6056 if (reg_val0 == NULL)
6057 return I40E_ERR_PARAM;
6059 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
6060 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
6061 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
6063 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6065 if (status == I40E_SUCCESS) {
6066 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
6068 if (reg_val1 != NULL)
6069 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
6076 * i40e_aq_alternate_read_indirect
6077 * @hw: pointer to the hardware structure
6078 * @addr: address of the alternate structure field
6079 * @dw_count: number of alternate structure fields to read
6080 * @buffer: pointer to the command buffer
6082 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
6083 * place them in 'buffer'. The buffer should be allocated by caller.
6086 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
6087 u32 addr, u32 dw_count, void *buffer)
6089 struct i40e_aq_desc desc;
6090 struct i40e_aqc_alternate_ind_write *cmd_resp =
6091 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
6092 enum i40e_status_code status;
6095 return I40E_ERR_PARAM;
6097 /* Indirect command */
6098 i40e_fill_default_direct_cmd_desc(&desc,
6099 i40e_aqc_opc_alternate_read_indirect);
6101 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6102 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6103 if (dw_count > (I40E_AQ_LARGE_BUF/4))
6104 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6106 cmd_resp->address = CPU_TO_LE32(addr);
6107 cmd_resp->length = CPU_TO_LE32(dw_count);
6109 status = i40e_asq_send_command(hw, &desc, buffer,
6110 I40E_LO_DWORD(4*dw_count), NULL);
6116 * i40e_aq_alternate_clear
6117 * @hw: pointer to the HW structure.
6119 * Clear the alternate structures of the port from which the function
6123 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
6125 struct i40e_aq_desc desc;
6126 enum i40e_status_code status;
6128 i40e_fill_default_direct_cmd_desc(&desc,
6129 i40e_aqc_opc_alternate_clear_port);
6131 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6137 * i40e_aq_alternate_write_done
6138 * @hw: pointer to the HW structure.
6139 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
6140 * @reset_needed: indicates the SW should trigger GLOBAL reset
6142 * Indicates to the FW that alternate structures have been changed.
6145 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
6146 u8 bios_mode, bool *reset_needed)
6148 struct i40e_aq_desc desc;
6149 struct i40e_aqc_alternate_write_done *cmd =
6150 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6151 enum i40e_status_code status;
6153 if (reset_needed == NULL)
6154 return I40E_ERR_PARAM;
6156 i40e_fill_default_direct_cmd_desc(&desc,
6157 i40e_aqc_opc_alternate_write_done);
6159 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
6161 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6162 if (!status && reset_needed)
6163 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
6164 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
6170 * i40e_aq_set_oem_mode
6171 * @hw: pointer to the HW structure.
6172 * @oem_mode: the OEM mode to be used
6174 * Sets the device to a specific operating mode. Currently the only supported
6175 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
6178 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
6181 struct i40e_aq_desc desc;
6182 struct i40e_aqc_alternate_write_done *cmd =
6183 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6184 enum i40e_status_code status;
6186 i40e_fill_default_direct_cmd_desc(&desc,
6187 i40e_aqc_opc_alternate_set_mode);
6189 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
6191 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6197 * i40e_aq_resume_port_tx
6198 * @hw: pointer to the hardware structure
6199 * @cmd_details: pointer to command details structure or NULL
6201 * Resume port's Tx traffic
6203 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
6204 struct i40e_asq_cmd_details *cmd_details)
6206 struct i40e_aq_desc desc;
6207 enum i40e_status_code status;
6209 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
6211 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6217 * i40e_set_pci_config_data - store PCI bus info
6218 * @hw: pointer to hardware structure
6219 * @link_status: the link status word from PCI config space
6221 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
6223 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
6225 hw->bus.type = i40e_bus_type_pci_express;
6227 switch (link_status & I40E_PCI_LINK_WIDTH) {
6228 case I40E_PCI_LINK_WIDTH_1:
6229 hw->bus.width = i40e_bus_width_pcie_x1;
6231 case I40E_PCI_LINK_WIDTH_2:
6232 hw->bus.width = i40e_bus_width_pcie_x2;
6234 case I40E_PCI_LINK_WIDTH_4:
6235 hw->bus.width = i40e_bus_width_pcie_x4;
6237 case I40E_PCI_LINK_WIDTH_8:
6238 hw->bus.width = i40e_bus_width_pcie_x8;
6241 hw->bus.width = i40e_bus_width_unknown;
6245 switch (link_status & I40E_PCI_LINK_SPEED) {
6246 case I40E_PCI_LINK_SPEED_2500:
6247 hw->bus.speed = i40e_bus_speed_2500;
6249 case I40E_PCI_LINK_SPEED_5000:
6250 hw->bus.speed = i40e_bus_speed_5000;
6252 case I40E_PCI_LINK_SPEED_8000:
6253 hw->bus.speed = i40e_bus_speed_8000;
6256 hw->bus.speed = i40e_bus_speed_unknown;
6262 * i40e_aq_debug_dump
6263 * @hw: pointer to the hardware structure
6264 * @cluster_id: specific cluster to dump
6265 * @table_id: table id within cluster
6266 * @start_index: index of line in the block to read
6267 * @buff_size: dump buffer size
6268 * @buff: dump buffer
6269 * @ret_buff_size: actual buffer size returned
6270 * @ret_next_table: next block to read
6271 * @ret_next_index: next index to read
6272 * @cmd_details: pointer to command details structure or NULL
6274 * Dump internal FW/HW data for debug purposes.
6277 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
6278 u8 table_id, u32 start_index, u16 buff_size,
6279 void *buff, u16 *ret_buff_size,
6280 u8 *ret_next_table, u32 *ret_next_index,
6281 struct i40e_asq_cmd_details *cmd_details)
6283 struct i40e_aq_desc desc;
6284 struct i40e_aqc_debug_dump_internals *cmd =
6285 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6286 struct i40e_aqc_debug_dump_internals *resp =
6287 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6288 enum i40e_status_code status;
6290 if (buff_size == 0 || !buff)
6291 return I40E_ERR_PARAM;
6293 i40e_fill_default_direct_cmd_desc(&desc,
6294 i40e_aqc_opc_debug_dump_internals);
6295 /* Indirect Command */
6296 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6297 if (buff_size > I40E_AQ_LARGE_BUF)
6298 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6300 cmd->cluster_id = cluster_id;
6301 cmd->table_id = table_id;
6302 cmd->idx = CPU_TO_LE32(start_index);
6304 desc.datalen = CPU_TO_LE16(buff_size);
6306 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
6308 if (ret_buff_size != NULL)
6309 *ret_buff_size = LE16_TO_CPU(desc.datalen);
6310 if (ret_next_table != NULL)
6311 *ret_next_table = resp->table_id;
6312 if (ret_next_index != NULL)
6313 *ret_next_index = LE32_TO_CPU(resp->idx);
6322 * @hw: pointer to the hardware structure
6323 * @enable: state of Energy Efficient Ethernet mode to be set
6325 * Enables or disables Energy Efficient Ethernet (EEE) mode
6326 * accordingly to @enable parameter.
6328 enum i40e_status_code i40e_enable_eee(struct i40e_hw *hw, bool enable)
6330 struct i40e_aq_get_phy_abilities_resp abilities;
6331 struct i40e_aq_set_phy_config config;
6332 enum i40e_status_code status;
6333 __le16 eee_capability;
6335 /* Get initial PHY capabilities */
6336 status = i40e_aq_get_phy_capabilities(hw, false, true, &abilities,
6341 /* Check whether NIC configuration is compatible with Energy Efficient
6342 * Ethernet (EEE) mode.
6344 if (abilities.eee_capability == 0) {
6345 status = I40E_ERR_CONFIG;
6349 /* Cache initial EEE capability */
6350 eee_capability = abilities.eee_capability;
6352 /* Get current configuration */
6353 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
6358 /* Cache current configuration */
6359 config.phy_type = abilities.phy_type;
6360 config.link_speed = abilities.link_speed;
6361 config.abilities = abilities.abilities |
6362 I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
6363 config.eeer = abilities.eeer_val;
6364 config.low_power_ctrl = abilities.d3_lpan;
6365 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
6366 I40E_AQ_PHY_FEC_CONFIG_MASK;
6368 /* Set desired EEE state */
6370 config.eee_capability = eee_capability;
6371 config.eeer |= I40E_PRTPM_EEER_TX_LPI_EN_MASK;
6373 config.eee_capability = 0;
6374 config.eeer &= ~I40E_PRTPM_EEER_TX_LPI_EN_MASK;
6377 /* Save modified config */
6378 status = i40e_aq_set_phy_config(hw, &config, NULL);
6384 * i40e_read_bw_from_alt_ram
6385 * @hw: pointer to the hardware structure
6386 * @max_bw: pointer for max_bw read
6387 * @min_bw: pointer for min_bw read
6388 * @min_valid: pointer for bool that is true if min_bw is a valid value
6389 * @max_valid: pointer for bool that is true if max_bw is a valid value
6391 * Read bw from the alternate ram for the given pf
6393 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
6394 u32 *max_bw, u32 *min_bw,
6395 bool *min_valid, bool *max_valid)
6397 enum i40e_status_code status;
6398 u32 max_bw_addr, min_bw_addr;
6400 /* Calculate the address of the min/max bw registers */
6401 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6402 I40E_ALT_STRUCT_MAX_BW_OFFSET +
6403 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6404 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6405 I40E_ALT_STRUCT_MIN_BW_OFFSET +
6406 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6408 /* Read the bandwidths from alt ram */
6409 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
6410 min_bw_addr, min_bw);
6412 if (*min_bw & I40E_ALT_BW_VALID_MASK)
6417 if (*max_bw & I40E_ALT_BW_VALID_MASK)
6426 * i40e_aq_configure_partition_bw
6427 * @hw: pointer to the hardware structure
6428 * @bw_data: Buffer holding valid pfs and bw limits
6429 * @cmd_details: pointer to command details
6431 * Configure partitions guaranteed/max bw
6433 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6434 struct i40e_aqc_configure_partition_bw_data *bw_data,
6435 struct i40e_asq_cmd_details *cmd_details)
6437 enum i40e_status_code status;
6438 struct i40e_aq_desc desc;
6439 u16 bwd_size = sizeof(*bw_data);
6441 i40e_fill_default_direct_cmd_desc(&desc,
6442 i40e_aqc_opc_configure_partition_bw);
6444 /* Indirect command */
6445 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6446 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6448 desc.datalen = CPU_TO_LE16(bwd_size);
6450 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6456 * i40e_read_phy_register_clause22
6457 * @hw: pointer to the HW structure
6458 * @reg: register address in the page
6459 * @phy_addr: PHY address on MDIO interface
6460 * @value: PHY register value
6462 * Reads specified PHY register value
6464 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
6465 u16 reg, u8 phy_addr, u16 *value)
6467 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6468 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6472 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6473 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6474 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
6475 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6476 (I40E_GLGEN_MSCA_MDICMD_MASK);
6477 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6479 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6480 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6481 status = I40E_SUCCESS;
6484 i40e_usec_delay(10);
6489 i40e_debug(hw, I40E_DEBUG_PHY,
6490 "PHY: Can't write command to external PHY.\n");
6492 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6493 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6494 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6501 * i40e_write_phy_register_clause22
6502 * @hw: pointer to the HW structure
6503 * @reg: register address in the page
6504 * @phy_addr: PHY address on MDIO interface
6505 * @value: PHY register value
6507 * Writes specified PHY register value
6509 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6510 u16 reg, u8 phy_addr, u16 value)
6512 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6513 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6517 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6518 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6520 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6521 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6522 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6523 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6524 (I40E_GLGEN_MSCA_MDICMD_MASK);
6526 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6528 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6529 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6530 status = I40E_SUCCESS;
6533 i40e_usec_delay(10);
6541 * i40e_read_phy_register_clause45
6542 * @hw: pointer to the HW structure
6543 * @page: registers page number
6544 * @reg: register address in the page
6545 * @phy_addr: PHY address on MDIO interface
6546 * @value: PHY register value
6548 * Reads specified PHY register value
6550 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6551 u8 page, u16 reg, u8 phy_addr, u16 *value)
6553 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6556 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6558 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6559 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6560 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6561 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6562 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6563 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6564 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6565 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6567 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6568 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6569 status = I40E_SUCCESS;
6572 i40e_usec_delay(10);
6577 i40e_debug(hw, I40E_DEBUG_PHY,
6578 "PHY: Can't write command to external PHY.\n");
6582 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6583 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6584 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6585 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6586 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6587 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6588 status = I40E_ERR_TIMEOUT;
6590 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6592 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6593 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6594 status = I40E_SUCCESS;
6597 i40e_usec_delay(10);
6602 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6603 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6604 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6606 i40e_debug(hw, I40E_DEBUG_PHY,
6607 "PHY: Can't read register value from external PHY.\n");
6615 * i40e_write_phy_register_clause45
6616 * @hw: pointer to the HW structure
6617 * @page: registers page number
6618 * @reg: register address in the page
6619 * @phy_addr: PHY address on MDIO interface
6620 * @value: PHY register value
6622 * Writes value to specified PHY register
6624 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6625 u8 page, u16 reg, u8 phy_addr, u16 value)
6627 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6630 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6632 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6633 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6634 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6635 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6636 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6637 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6638 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6639 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6641 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6642 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6643 status = I40E_SUCCESS;
6646 i40e_usec_delay(10);
6650 i40e_debug(hw, I40E_DEBUG_PHY,
6651 "PHY: Can't write command to external PHY.\n");
6655 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6656 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6658 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6659 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6660 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6661 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6662 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6663 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6664 status = I40E_ERR_TIMEOUT;
6666 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6668 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6669 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6670 status = I40E_SUCCESS;
6673 i40e_usec_delay(10);
6682 * i40e_write_phy_register
6683 * @hw: pointer to the HW structure
6684 * @page: registers page number
6685 * @reg: register address in the page
6686 * @phy_addr: PHY address on MDIO interface
6687 * @value: PHY register value
6689 * Writes value to specified PHY register
6691 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6692 u8 page, u16 reg, u8 phy_addr, u16 value)
6694 enum i40e_status_code status;
6696 switch (hw->device_id) {
6697 case I40E_DEV_ID_1G_BASE_T_X722:
6698 status = i40e_write_phy_register_clause22(hw,
6699 reg, phy_addr, value);
6701 case I40E_DEV_ID_10G_BASE_T:
6702 case I40E_DEV_ID_10G_BASE_T4:
6703 case I40E_DEV_ID_10G_BASE_T_BC:
6704 case I40E_DEV_ID_10G_BASE_T_X722:
6705 case I40E_DEV_ID_25G_B:
6706 case I40E_DEV_ID_25G_SFP28:
6707 status = i40e_write_phy_register_clause45(hw,
6708 page, reg, phy_addr, value);
6711 status = I40E_ERR_UNKNOWN_PHY;
6719 * i40e_read_phy_register
6720 * @hw: pointer to the HW structure
6721 * @page: registers page number
6722 * @reg: register address in the page
6723 * @phy_addr: PHY address on MDIO interface
6724 * @value: PHY register value
6726 * Reads specified PHY register value
6728 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6729 u8 page, u16 reg, u8 phy_addr, u16 *value)
6731 enum i40e_status_code status;
6733 switch (hw->device_id) {
6734 case I40E_DEV_ID_1G_BASE_T_X722:
6735 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6738 case I40E_DEV_ID_10G_BASE_T:
6739 case I40E_DEV_ID_10G_BASE_T4:
6740 case I40E_DEV_ID_10G_BASE_T_X722:
6741 case I40E_DEV_ID_25G_B:
6742 case I40E_DEV_ID_25G_SFP28:
6743 status = i40e_read_phy_register_clause45(hw, page, reg,
6747 status = I40E_ERR_UNKNOWN_PHY;
6755 * i40e_get_phy_address
6756 * @hw: pointer to the HW structure
6757 * @dev_num: PHY port num that address we want
6759 * Gets PHY address for current port
6761 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6763 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6764 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6766 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6770 * i40e_blink_phy_led
6771 * @hw: pointer to the HW structure
6772 * @time: time how long led will blinks in secs
6773 * @interval: gap between LED on and off in msecs
6775 * Blinks PHY link LED
6777 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6778 u32 time, u32 interval)
6780 enum i40e_status_code status = I40E_SUCCESS;
6785 u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6789 i = rd32(hw, I40E_PFGEN_PORTNUM);
6790 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6791 phy_addr = i40e_get_phy_address(hw, port_num);
6793 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6795 status = i40e_read_phy_register_clause45(hw,
6796 I40E_PHY_COM_REG_PAGE,
6800 goto phy_blinking_end;
6802 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6804 status = i40e_write_phy_register_clause45(hw,
6805 I40E_PHY_COM_REG_PAGE,
6809 goto phy_blinking_end;
6814 if (time > 0 && interval > 0) {
6815 for (i = 0; i < time * 1000; i += interval) {
6816 status = i40e_read_phy_register_clause45(hw,
6817 I40E_PHY_COM_REG_PAGE,
6818 led_addr, phy_addr, &led_reg);
6820 goto restore_config;
6821 if (led_reg & I40E_PHY_LED_MANUAL_ON)
6824 led_reg = I40E_PHY_LED_MANUAL_ON;
6825 status = i40e_write_phy_register_clause45(hw,
6826 I40E_PHY_COM_REG_PAGE,
6827 led_addr, phy_addr, led_reg);
6829 goto restore_config;
6830 i40e_msec_delay(interval);
6835 status = i40e_write_phy_register_clause45(hw,
6836 I40E_PHY_COM_REG_PAGE,
6837 led_addr, phy_addr, led_ctl);
6844 * i40e_led_get_reg - read LED register
6845 * @hw: pointer to the HW structure
6846 * @led_addr: LED register address
6847 * @reg_val: read register value
6849 static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr,
6852 enum i40e_status_code status;
6856 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6857 status = i40e_aq_get_phy_register(hw,
6858 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6859 I40E_PHY_COM_REG_PAGE, true,
6860 I40E_PHY_LED_PROV_REG_1,
6863 phy_addr = i40e_get_phy_address(hw, hw->port);
6864 status = i40e_read_phy_register_clause45(hw,
6865 I40E_PHY_COM_REG_PAGE,
6873 * i40e_led_set_reg - write LED register
6874 * @hw: pointer to the HW structure
6875 * @led_addr: LED register address
6876 * @reg_val: register value to write
6878 static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr,
6881 enum i40e_status_code status;
6884 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6885 status = i40e_aq_set_phy_register(hw,
6886 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6887 I40E_PHY_COM_REG_PAGE, true,
6888 I40E_PHY_LED_PROV_REG_1,
6891 phy_addr = i40e_get_phy_address(hw, hw->port);
6892 status = i40e_write_phy_register_clause45(hw,
6893 I40E_PHY_COM_REG_PAGE,
6902 * i40e_led_get_phy - return current on/off mode
6903 * @hw: pointer to the hw struct
6904 * @led_addr: address of led register to use
6905 * @val: original value of register to use
6908 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6911 enum i40e_status_code status = I40E_SUCCESS;
6918 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6919 status = i40e_aq_get_phy_register(hw,
6920 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6921 I40E_PHY_COM_REG_PAGE, true,
6922 I40E_PHY_LED_PROV_REG_1,
6924 if (status == I40E_SUCCESS)
6925 *val = (u16)reg_val_aq;
6928 temp_addr = I40E_PHY_LED_PROV_REG_1;
6929 phy_addr = i40e_get_phy_address(hw, hw->port);
6930 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6932 status = i40e_read_phy_register_clause45(hw,
6933 I40E_PHY_COM_REG_PAGE,
6934 temp_addr, phy_addr,
6939 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6940 *led_addr = temp_addr;
6949 * @hw: pointer to the HW structure
6950 * @on: true or false
6951 * @led_addr: address of led register to use
6952 * @mode: original val plus bit for set or ignore
6954 * Set led's on or off when controlled by the PHY
6957 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6958 u16 led_addr, u32 mode)
6960 enum i40e_status_code status = I40E_SUCCESS;
6964 status = i40e_led_get_reg(hw, led_addr, &led_reg);
6968 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6970 status = i40e_led_set_reg(hw, led_addr, led_reg);
6974 status = i40e_led_get_reg(hw, led_addr, &led_reg);
6976 goto restore_config;
6978 led_reg = I40E_PHY_LED_MANUAL_ON;
6981 status = i40e_led_set_reg(hw, led_addr, led_reg);
6983 goto restore_config;
6984 if (mode & I40E_PHY_LED_MODE_ORIG) {
6985 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6986 status = i40e_led_set_reg(hw, led_addr, led_ctl);
6991 status = i40e_led_set_reg(hw, led_addr, led_ctl);
6994 #endif /* PF_DRIVER */
6996 * i40e_get_phy_lpi_status - read LPI status from PHY or MAC register
6997 * @hw: pointer to the hw struct
6998 * @stat: pointer to structure with status of rx and tx lpi
7000 * Read LPI state directly from external PHY register or from MAC
7001 * register, depending on device ID and current link speed.
7003 enum i40e_status_code i40e_get_phy_lpi_status(struct i40e_hw *hw,
7004 struct i40e_hw_port_stats *stat)
7006 enum i40e_status_code ret = I40E_SUCCESS;
7009 stat->rx_lpi_status = 0;
7010 stat->tx_lpi_status = 0;
7012 if (hw->device_id == I40E_DEV_ID_10G_BASE_T_BC &&
7013 (hw->phy.link_info.link_speed == I40E_LINK_SPEED_2_5GB ||
7014 hw->phy.link_info.link_speed == I40E_LINK_SPEED_5GB)) {
7015 ret = i40e_aq_get_phy_register(hw,
7016 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
7017 I40E_BCM_PHY_PCS_STATUS1_PAGE,
7019 I40E_BCM_PHY_PCS_STATUS1_REG,
7022 if (ret != I40E_SUCCESS)
7025 stat->rx_lpi_status = !!(val & I40E_BCM_PHY_PCS_STATUS1_RX_LPI);
7026 stat->tx_lpi_status = !!(val & I40E_BCM_PHY_PCS_STATUS1_TX_LPI);
7031 val = rd32(hw, I40E_PRTPM_EEE_STAT);
7032 stat->rx_lpi_status = (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
7033 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
7034 stat->tx_lpi_status = (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
7035 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
7041 * i40e_get_lpi_counters - read LPI counters from EEE statistics
7042 * @hw: pointer to the hw struct
7043 * @tx_counter: pointer to memory for TX LPI counter
7044 * @rx_counter: pointer to memory for RX LPI counter
7045 * @is_clear: returns true if counters are clear after read
7047 * Read Low Power Idle (LPI) mode counters from Energy Efficient
7048 * Ethernet (EEE) statistics.
7050 enum i40e_status_code i40e_get_lpi_counters(struct i40e_hw *hw,
7051 u32 *tx_counter, u32 *rx_counter,
7054 /* only X710-T*L requires special handling of counters
7055 * for other devices we just read the MAC registers
7057 if (hw->device_id == I40E_DEV_ID_10G_BASE_T_BC &&
7058 hw->phy.link_info.link_speed != I40E_LINK_SPEED_1GB) {
7059 enum i40e_status_code retval;
7063 retval = i40e_aq_run_phy_activity(hw,
7064 I40E_AQ_RUN_PHY_ACT_ID_USR_DFND,
7065 I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_STAT,
7066 &cmd_status, tx_counter, rx_counter, NULL);
7068 if (cmd_status != I40E_AQ_RUN_PHY_ACT_CMD_STAT_SUCC)
7069 retval = I40E_ERR_ADMIN_QUEUE_ERROR;
7075 *tx_counter = rd32(hw, I40E_PRTPM_TLPIC);
7076 *rx_counter = rd32(hw, I40E_PRTPM_RLPIC);
7078 return I40E_SUCCESS;
7082 * i40e_lpi_stat_update - update LPI counters with values relative to offset
7083 * @hw: pointer to the hw struct
7084 * @offset_loaded: flag indicating need of writing current value to offset
7085 * @tx_offset: pointer to offset of TX LPI counter
7086 * @tx_stat: pointer to value of TX LPI counter
7087 * @rx_offset: pointer to offset of RX LPI counter
7088 * @rx_stat: pointer to value of RX LPI counter
7090 * Update Low Power Idle (LPI) mode counters while having regard to passed
7093 enum i40e_status_code i40e_lpi_stat_update(struct i40e_hw *hw,
7094 bool offset_loaded, u64 *tx_offset,
7095 u64 *tx_stat, u64 *rx_offset,
7098 enum i40e_status_code retval;
7099 u32 tx_counter, rx_counter;
7102 retval = i40e_get_lpi_counters(hw, &tx_counter, &rx_counter, &is_clear);
7107 *tx_stat += tx_counter;
7108 *rx_stat += rx_counter;
7110 if (!offset_loaded) {
7111 *tx_offset = tx_counter;
7112 *rx_offset = rx_counter;
7115 *tx_stat = (tx_counter >= *tx_offset) ?
7116 (u32)(tx_counter - *tx_offset) :
7117 (u32)((tx_counter + BIT_ULL(32)) - *tx_offset);
7118 *rx_stat = (rx_counter >= *rx_offset) ?
7119 (u32)(rx_counter - *rx_offset) :
7120 (u32)((rx_counter + BIT_ULL(32)) - *rx_offset);
7127 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
7128 * @hw: pointer to the hw struct
7129 * @reg_addr: register address
7130 * @reg_val: ptr to register value
7131 * @cmd_details: pointer to command details structure or NULL
7133 * Use the firmware to read the Rx control register,
7134 * especially useful if the Rx unit is under heavy pressure
7136 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
7137 u32 reg_addr, u32 *reg_val,
7138 struct i40e_asq_cmd_details *cmd_details)
7140 struct i40e_aq_desc desc;
7141 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
7142 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
7143 enum i40e_status_code status;
7145 if (reg_val == NULL)
7146 return I40E_ERR_PARAM;
7148 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
7150 cmd_resp->address = CPU_TO_LE32(reg_addr);
7152 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7154 if (status == I40E_SUCCESS)
7155 *reg_val = LE32_TO_CPU(cmd_resp->value);
7161 * i40e_read_rx_ctl - read from an Rx control register
7162 * @hw: pointer to the hw struct
7163 * @reg_addr: register address
7165 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
7167 enum i40e_status_code status = I40E_SUCCESS;
7172 use_register = (((hw->aq.api_maj_ver == 1) &&
7173 (hw->aq.api_min_ver < 5)) ||
7174 (hw->mac.type == I40E_MAC_X722));
7175 if (!use_register) {
7177 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
7178 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
7185 /* if the AQ access failed, try the old-fashioned way */
7186 if (status || use_register)
7187 val = rd32(hw, reg_addr);
7193 * i40e_aq_rx_ctl_write_register
7194 * @hw: pointer to the hw struct
7195 * @reg_addr: register address
7196 * @reg_val: register value
7197 * @cmd_details: pointer to command details structure or NULL
7199 * Use the firmware to write to an Rx control register,
7200 * especially useful if the Rx unit is under heavy pressure
7202 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
7203 u32 reg_addr, u32 reg_val,
7204 struct i40e_asq_cmd_details *cmd_details)
7206 struct i40e_aq_desc desc;
7207 struct i40e_aqc_rx_ctl_reg_read_write *cmd =
7208 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
7209 enum i40e_status_code status;
7211 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
7213 cmd->address = CPU_TO_LE32(reg_addr);
7214 cmd->value = CPU_TO_LE32(reg_val);
7216 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7222 * i40e_write_rx_ctl - write to an Rx control register
7223 * @hw: pointer to the hw struct
7224 * @reg_addr: register address
7225 * @reg_val: register value
7227 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
7229 enum i40e_status_code status = I40E_SUCCESS;
7233 use_register = (((hw->aq.api_maj_ver == 1) &&
7234 (hw->aq.api_min_ver < 5)) ||
7235 (hw->mac.type == I40E_MAC_X722));
7236 if (!use_register) {
7238 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
7240 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
7247 /* if the AQ access failed, try the old-fashioned way */
7248 if (status || use_register)
7249 wr32(hw, reg_addr, reg_val);
7253 * i40e_mdio_if_number_selection - MDIO I/F number selection
7254 * @hw: pointer to the hw struct
7255 * @set_mdio: use MDIO I/F number specified by mdio_num
7256 * @mdio_num: MDIO I/F number
7257 * @cmd: pointer to PHY Register command structure
7260 i40e_mdio_if_number_selection(struct i40e_hw *hw, bool set_mdio, u8 mdio_num,
7261 struct i40e_aqc_phy_register_access *cmd)
7263 if (set_mdio && cmd->phy_interface == I40E_AQ_PHY_REG_ACCESS_EXTERNAL) {
7264 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_EXTENDED)
7266 I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER |
7268 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT) &
7269 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK);
7271 i40e_debug(hw, I40E_DEBUG_PHY,
7272 "MDIO I/F number selection not supported by current FW version.\n");
7277 * i40e_aq_set_phy_register_ext
7278 * @hw: pointer to the hw struct
7279 * @phy_select: select which phy should be accessed
7280 * @dev_addr: PHY device address
7281 * @page_change: enable auto page change
7282 * @set_mdio: use MDIO I/F number specified by mdio_num
7283 * @mdio_num: MDIO I/F number
7284 * @reg_addr: PHY register address
7285 * @reg_val: new register value
7286 * @cmd_details: pointer to command details structure or NULL
7288 * Write the external PHY register.
7289 * NOTE: In common cases MDIO I/F number should not be changed, thats why you
7290 * may use simple wrapper i40e_aq_set_phy_register.
7292 enum i40e_status_code
7293 i40e_aq_set_phy_register_ext(struct i40e_hw *hw,
7294 u8 phy_select, u8 dev_addr, bool page_change,
7295 bool set_mdio, u8 mdio_num,
7296 u32 reg_addr, u32 reg_val,
7297 struct i40e_asq_cmd_details *cmd_details)
7299 struct i40e_aq_desc desc;
7300 struct i40e_aqc_phy_register_access *cmd =
7301 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7302 enum i40e_status_code status;
7304 i40e_fill_default_direct_cmd_desc(&desc,
7305 i40e_aqc_opc_set_phy_register);
7307 cmd->phy_interface = phy_select;
7308 cmd->dev_addres = dev_addr;
7309 cmd->reg_address = CPU_TO_LE32(reg_addr);
7310 cmd->reg_value = CPU_TO_LE32(reg_val);
7313 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
7315 i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd);
7317 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7323 * i40e_aq_get_phy_register_ext
7324 * @hw: pointer to the hw struct
7325 * @phy_select: select which phy should be accessed
7326 * @dev_addr: PHY device address
7327 * @page_change: enable auto page change
7328 * @set_mdio: use MDIO I/F number specified by mdio_num
7329 * @mdio_num: MDIO I/F number
7330 * @reg_addr: PHY register address
7331 * @reg_val: read register value
7332 * @cmd_details: pointer to command details structure or NULL
7334 * Read the external PHY register.
7335 * NOTE: In common cases MDIO I/F number should not be changed, thats why you
7336 * may use simple wrapper i40e_aq_get_phy_register.
7338 enum i40e_status_code
7339 i40e_aq_get_phy_register_ext(struct i40e_hw *hw,
7340 u8 phy_select, u8 dev_addr, bool page_change,
7341 bool set_mdio, u8 mdio_num,
7342 u32 reg_addr, u32 *reg_val,
7343 struct i40e_asq_cmd_details *cmd_details)
7345 struct i40e_aq_desc desc;
7346 struct i40e_aqc_phy_register_access *cmd =
7347 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7348 enum i40e_status_code status;
7350 i40e_fill_default_direct_cmd_desc(&desc,
7351 i40e_aqc_opc_get_phy_register);
7353 cmd->phy_interface = phy_select;
7354 cmd->dev_addres = dev_addr;
7355 cmd->reg_address = CPU_TO_LE32(reg_addr);
7358 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
7360 i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd);
7362 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7364 *reg_val = LE32_TO_CPU(cmd->reg_value);
7370 * i40e_aq_run_phy_activity
7371 * @hw: pointer to the hw struct
7372 * @activity_id: ID of DNL activity to run
7373 * @dnl_opcode: opcode passed to DNL script
7374 * @cmd_status: pointer to memory to write return value of DNL script
7375 * @data0: pointer to memory for first 4 bytes of data returned by DNL script
7376 * @data1: pointer to memory for last 4 bytes of data returned by DNL script
7377 * @cmd_details: pointer to command details structure or NULL
7379 * Run DNL admin command.
7381 enum i40e_status_code
7382 i40e_aq_run_phy_activity(struct i40e_hw *hw, u16 activity_id, u32 dnl_opcode,
7383 u32 *cmd_status, u32 *data0, u32 *data1,
7384 struct i40e_asq_cmd_details *cmd_details)
7386 struct i40e_aqc_run_phy_activity *cmd;
7387 enum i40e_status_code retval;
7388 struct i40e_aq_desc desc;
7390 cmd = (struct i40e_aqc_run_phy_activity *)&desc.params.raw;
7392 if (!cmd_status || !data0 || !data1) {
7393 retval = I40E_ERR_PARAM;
7397 i40e_fill_default_direct_cmd_desc(&desc,
7398 i40e_aqc_opc_run_phy_activity);
7400 cmd->activity_id = CPU_TO_LE16(activity_id);
7401 cmd->params.cmd.dnl_opcode = CPU_TO_LE32(dnl_opcode);
7403 retval = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7407 *cmd_status = LE32_TO_CPU(cmd->params.resp.cmd_status);
7408 *data0 = LE32_TO_CPU(cmd->params.resp.data0);
7409 *data1 = LE32_TO_CPU(cmd->params.resp.data1);
7417 * i40e_aq_send_msg_to_pf
7418 * @hw: pointer to the hardware structure
7419 * @v_opcode: opcodes for VF-PF communication
7420 * @v_retval: return error code
7421 * @msg: pointer to the msg buffer
7422 * @msglen: msg length
7423 * @cmd_details: pointer to command details
7425 * Send message to PF driver using admin queue. By default, this message
7426 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
7427 * completion before returning.
7429 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
7430 enum virtchnl_ops v_opcode,
7431 enum i40e_status_code v_retval,
7432 u8 *msg, u16 msglen,
7433 struct i40e_asq_cmd_details *cmd_details)
7435 struct i40e_aq_desc desc;
7436 struct i40e_asq_cmd_details details;
7437 enum i40e_status_code status;
7439 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
7440 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
7441 desc.cookie_high = CPU_TO_LE32(v_opcode);
7442 desc.cookie_low = CPU_TO_LE32(v_retval);
7444 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
7445 | I40E_AQ_FLAG_RD));
7446 if (msglen > I40E_AQ_LARGE_BUF)
7447 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7448 desc.datalen = CPU_TO_LE16(msglen);
7451 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
7452 details.async = true;
7453 cmd_details = &details;
7455 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
7456 msglen, cmd_details);
7461 * i40e_vf_parse_hw_config
7462 * @hw: pointer to the hardware structure
7463 * @msg: pointer to the virtual channel VF resource structure
7465 * Given a VF resource message from the PF, populate the hw struct
7466 * with appropriate information.
7468 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
7469 struct virtchnl_vf_resource *msg)
7471 struct virtchnl_vsi_resource *vsi_res;
7474 vsi_res = &msg->vsi_res[0];
7476 hw->dev_caps.num_vsis = msg->num_vsis;
7477 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
7478 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
7479 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
7480 hw->dev_caps.dcb = msg->vf_cap_flags &
7481 VIRTCHNL_VF_OFFLOAD_L2;
7482 hw->dev_caps.iwarp = (msg->vf_cap_flags &
7483 VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
7484 for (i = 0; i < msg->num_vsis; i++) {
7485 if (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) {
7486 i40e_memcpy(hw->mac.perm_addr,
7487 vsi_res->default_mac_addr,
7489 I40E_NONDMA_TO_NONDMA);
7490 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
7492 I40E_NONDMA_TO_NONDMA);
7500 * @hw: pointer to the hardware structure
7502 * Send a VF_RESET message to the PF. Does not wait for response from PF
7503 * as none will be forthcoming. Immediately after calling this function,
7504 * the admin queue should be shut down and (optionally) reinitialized.
7506 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
7508 return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF,
7509 I40E_SUCCESS, NULL, 0, NULL);
7511 #endif /* VF_DRIVER */
7514 * i40e_aq_set_arp_proxy_config
7515 * @hw: pointer to the HW structure
7516 * @proxy_config: pointer to proxy config command table struct
7517 * @cmd_details: pointer to command details
7519 * Set ARP offload parameters from pre-populated
7520 * i40e_aqc_arp_proxy_data struct
7522 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
7523 struct i40e_aqc_arp_proxy_data *proxy_config,
7524 struct i40e_asq_cmd_details *cmd_details)
7526 struct i40e_aq_desc desc;
7527 enum i40e_status_code status;
7530 return I40E_ERR_PARAM;
7532 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
7534 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7535 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7536 desc.params.external.addr_high =
7537 CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
7538 desc.params.external.addr_low =
7539 CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
7540 desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_arp_proxy_data));
7542 status = i40e_asq_send_command(hw, &desc, proxy_config,
7543 sizeof(struct i40e_aqc_arp_proxy_data),
7550 * i40e_aq_opc_set_ns_proxy_table_entry
7551 * @hw: pointer to the HW structure
7552 * @ns_proxy_table_entry: pointer to NS table entry command struct
7553 * @cmd_details: pointer to command details
7555 * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
7556 * from pre-populated i40e_aqc_ns_proxy_data struct
7558 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
7559 struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
7560 struct i40e_asq_cmd_details *cmd_details)
7562 struct i40e_aq_desc desc;
7563 enum i40e_status_code status;
7565 if (!ns_proxy_table_entry)
7566 return I40E_ERR_PARAM;
7568 i40e_fill_default_direct_cmd_desc(&desc,
7569 i40e_aqc_opc_set_ns_proxy_table_entry);
7571 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7572 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7573 desc.params.external.addr_high =
7574 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
7575 desc.params.external.addr_low =
7576 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
7577 desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_ns_proxy_data));
7579 status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
7580 sizeof(struct i40e_aqc_ns_proxy_data),
7587 * i40e_aq_set_clear_wol_filter
7588 * @hw: pointer to the hw struct
7589 * @filter_index: index of filter to modify (0-7)
7590 * @filter: buffer containing filter to be set
7591 * @set_filter: true to set filter, false to clear filter
7592 * @no_wol_tco: if true, pass through packets cannot cause wake-up
7593 * if false, pass through packets may cause wake-up
7594 * @filter_valid: true if filter action is valid
7595 * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
7596 * @cmd_details: pointer to command details structure or NULL
7598 * Set or clear WoL filter for port attached to the PF
7600 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
7602 struct i40e_aqc_set_wol_filter_data *filter,
7603 bool set_filter, bool no_wol_tco,
7604 bool filter_valid, bool no_wol_tco_valid,
7605 struct i40e_asq_cmd_details *cmd_details)
7607 struct i40e_aq_desc desc;
7608 struct i40e_aqc_set_wol_filter *cmd =
7609 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
7610 enum i40e_status_code status;
7612 u16 valid_flags = 0;
7615 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
7617 if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
7618 return I40E_ERR_PARAM;
7619 cmd->filter_index = CPU_TO_LE16(filter_index);
7623 return I40E_ERR_PARAM;
7625 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
7626 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR;
7630 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
7631 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
7634 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
7635 if (no_wol_tco_valid)
7636 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
7637 cmd->valid_flags = CPU_TO_LE16(valid_flags);
7639 buff_len = sizeof(*filter);
7640 desc.datalen = CPU_TO_LE16(buff_len);
7642 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7643 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7645 cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
7646 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
7648 status = i40e_asq_send_command(hw, &desc, filter,
7649 buff_len, cmd_details);
7655 * i40e_aq_get_wake_event_reason
7656 * @hw: pointer to the hw struct
7657 * @wake_reason: return value, index of matching filter
7658 * @cmd_details: pointer to command details structure or NULL
7660 * Get information for the reason of a Wake Up event
7662 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
7664 struct i40e_asq_cmd_details *cmd_details)
7666 struct i40e_aq_desc desc;
7667 struct i40e_aqc_get_wake_reason_completion *resp =
7668 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
7669 enum i40e_status_code status;
7671 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
7673 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7675 if (status == I40E_SUCCESS)
7676 *wake_reason = LE16_TO_CPU(resp->wake_reason);
7682 * i40e_aq_clear_all_wol_filters
7683 * @hw: pointer to the hw struct
7684 * @cmd_details: pointer to command details structure or NULL
7686 * Get information for the reason of a Wake Up event
7688 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw,
7689 struct i40e_asq_cmd_details *cmd_details)
7691 struct i40e_aq_desc desc;
7692 enum i40e_status_code status;
7694 i40e_fill_default_direct_cmd_desc(&desc,
7695 i40e_aqc_opc_clear_all_wol_filters);
7697 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7703 * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
7704 * @hw: pointer to the hw struct
7705 * @buff: command buffer (size in bytes = buff_size)
7706 * @buff_size: buffer size in bytes
7707 * @track_id: package tracking id
7708 * @error_offset: returns error offset
7709 * @error_info: returns error information
7710 * @cmd_details: pointer to command details structure or NULL
7713 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
7714 u16 buff_size, u32 track_id,
7715 u32 *error_offset, u32 *error_info,
7716 struct i40e_asq_cmd_details *cmd_details)
7718 struct i40e_aq_desc desc;
7719 struct i40e_aqc_write_personalization_profile *cmd =
7720 (struct i40e_aqc_write_personalization_profile *)
7722 struct i40e_aqc_write_ddp_resp *resp;
7723 enum i40e_status_code status;
7725 i40e_fill_default_direct_cmd_desc(&desc,
7726 i40e_aqc_opc_write_personalization_profile);
7728 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
7729 if (buff_size > I40E_AQ_LARGE_BUF)
7730 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7732 desc.datalen = CPU_TO_LE16(buff_size);
7734 cmd->profile_track_id = CPU_TO_LE32(track_id);
7736 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7738 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
7740 *error_offset = LE32_TO_CPU(resp->error_offset);
7742 *error_info = LE32_TO_CPU(resp->error_info);
7749 * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
7750 * @hw: pointer to the hw struct
7751 * @buff: command buffer (size in bytes = buff_size)
7752 * @buff_size: buffer size in bytes
7753 * @flags: AdminQ command flags
7754 * @cmd_details: pointer to command details structure or NULL
7757 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
7758 u16 buff_size, u8 flags,
7759 struct i40e_asq_cmd_details *cmd_details)
7761 struct i40e_aq_desc desc;
7762 struct i40e_aqc_get_applied_profiles *cmd =
7763 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
7764 enum i40e_status_code status;
7766 i40e_fill_default_direct_cmd_desc(&desc,
7767 i40e_aqc_opc_get_personalization_profile_list);
7769 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7770 if (buff_size > I40E_AQ_LARGE_BUF)
7771 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7772 desc.datalen = CPU_TO_LE16(buff_size);
7776 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7782 * i40e_find_segment_in_package
7783 * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
7784 * @pkg_hdr: pointer to the package header to be searched
7786 * This function searches a package file for a particular segment type. On
7787 * success it returns a pointer to the segment header, otherwise it will
7790 struct i40e_generic_seg_header *
7791 i40e_find_segment_in_package(u32 segment_type,
7792 struct i40e_package_header *pkg_hdr)
7794 struct i40e_generic_seg_header *segment;
7797 /* Search all package segments for the requested segment type */
7798 for (i = 0; i < pkg_hdr->segment_count; i++) {
7800 (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
7801 pkg_hdr->segment_offset[i]);
7803 if (segment->type == segment_type)
7810 /* Get section table in profile */
7811 #define I40E_SECTION_TABLE(profile, sec_tbl) \
7813 struct i40e_profile_segment *p = (profile); \
7816 count = p->device_table_count; \
7817 nvm = (u32 *)&p->device_table[count]; \
7818 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \
7821 /* Get section header in profile */
7822 #define I40E_SECTION_HEADER(profile, offset) \
7823 (struct i40e_profile_section_header *)((u8 *)(profile) + (offset))
7826 * i40e_find_section_in_profile
7827 * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE)
7828 * @profile: pointer to the i40e segment header to be searched
7830 * This function searches i40e segment for a particular section type. On
7831 * success it returns a pointer to the section header, otherwise it will
7834 struct i40e_profile_section_header *
7835 i40e_find_section_in_profile(u32 section_type,
7836 struct i40e_profile_segment *profile)
7838 struct i40e_profile_section_header *sec;
7839 struct i40e_section_table *sec_tbl;
7843 if (profile->header.type != SEGMENT_TYPE_I40E)
7846 I40E_SECTION_TABLE(profile, sec_tbl);
7848 for (i = 0; i < sec_tbl->section_count; i++) {
7849 sec_off = sec_tbl->section_offset[i];
7850 sec = I40E_SECTION_HEADER(profile, sec_off);
7851 if (sec->section.type == section_type)
7859 * i40e_ddp_exec_aq_section - Execute generic AQ for DDP
7860 * @hw: pointer to the hw struct
7861 * @aq: command buffer containing all data to execute AQ
7864 i40e_status_code i40e_ddp_exec_aq_section(struct i40e_hw *hw,
7865 struct i40e_profile_aq_section *aq)
7867 enum i40e_status_code status;
7868 struct i40e_aq_desc desc;
7872 i40e_fill_default_direct_cmd_desc(&desc, aq->opcode);
7873 desc.flags |= CPU_TO_LE16(aq->flags);
7874 i40e_memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw),
7875 I40E_NONDMA_TO_NONDMA);
7877 msglen = aq->datalen;
7879 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
7881 if (msglen > I40E_AQ_LARGE_BUF)
7882 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7883 desc.datalen = CPU_TO_LE16(msglen);
7887 status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL);
7889 if (status != I40E_SUCCESS) {
7890 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7891 "unable to exec DDP AQ opcode %u, error %d\n",
7892 aq->opcode, status);
7896 /* copy returned desc to aq_buf */
7897 i40e_memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw),
7898 I40E_NONDMA_TO_NONDMA);
7900 return I40E_SUCCESS;
7904 * i40e_validate_profile
7905 * @hw: pointer to the hardware structure
7906 * @profile: pointer to the profile segment of the package to be validated
7907 * @track_id: package tracking id
7908 * @rollback: flag if the profile is for rollback.
7910 * Validates supported devices and profile's sections.
7912 STATIC enum i40e_status_code
7913 i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7914 u32 track_id, bool rollback)
7916 struct i40e_profile_section_header *sec = NULL;
7917 enum i40e_status_code status = I40E_SUCCESS;
7918 struct i40e_section_table *sec_tbl;
7924 if (track_id == I40E_DDP_TRACKID_INVALID) {
7925 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n");
7926 return I40E_NOT_SUPPORTED;
7929 dev_cnt = profile->device_table_count;
7930 for (i = 0; i < dev_cnt; i++) {
7931 vendor_dev_id = profile->device_table[i].vendor_dev_id;
7932 if ((vendor_dev_id >> 16) == I40E_INTEL_VENDOR_ID &&
7933 hw->device_id == (vendor_dev_id & 0xFFFF))
7936 if (dev_cnt && (i == dev_cnt)) {
7937 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7938 "Device doesn't support DDP\n");
7939 return I40E_ERR_DEVICE_NOT_SUPPORTED;
7942 I40E_SECTION_TABLE(profile, sec_tbl);
7944 /* Validate sections types */
7945 for (i = 0; i < sec_tbl->section_count; i++) {
7946 sec_off = sec_tbl->section_offset[i];
7947 sec = I40E_SECTION_HEADER(profile, sec_off);
7949 if (sec->section.type == SECTION_TYPE_MMIO ||
7950 sec->section.type == SECTION_TYPE_AQ ||
7951 sec->section.type == SECTION_TYPE_RB_AQ) {
7952 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7953 "Not a roll-back package\n");
7954 return I40E_NOT_SUPPORTED;
7957 if (sec->section.type == SECTION_TYPE_RB_AQ ||
7958 sec->section.type == SECTION_TYPE_RB_MMIO) {
7959 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7960 "Not an original package\n");
7961 return I40E_NOT_SUPPORTED;
7970 * i40e_write_profile
7971 * @hw: pointer to the hardware structure
7972 * @profile: pointer to the profile segment of the package to be downloaded
7973 * @track_id: package tracking id
7975 * Handles the download of a complete package.
7977 enum i40e_status_code
7978 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7981 enum i40e_status_code status = I40E_SUCCESS;
7982 struct i40e_section_table *sec_tbl;
7983 struct i40e_profile_section_header *sec = NULL;
7984 struct i40e_profile_aq_section *ddp_aq;
7985 u32 section_size = 0;
7986 u32 offset = 0, info = 0;
7990 status = i40e_validate_profile(hw, profile, track_id, false);
7994 I40E_SECTION_TABLE(profile, sec_tbl);
7996 for (i = 0; i < sec_tbl->section_count; i++) {
7997 sec_off = sec_tbl->section_offset[i];
7998 sec = I40E_SECTION_HEADER(profile, sec_off);
7999 /* Process generic admin command */
8000 if (sec->section.type == SECTION_TYPE_AQ) {
8001 ddp_aq = (struct i40e_profile_aq_section *)&sec[1];
8002 status = i40e_ddp_exec_aq_section(hw, ddp_aq);
8004 i40e_debug(hw, I40E_DEBUG_PACKAGE,
8005 "Failed to execute aq: section %d, opcode %u\n",
8009 sec->section.type = SECTION_TYPE_RB_AQ;
8012 /* Skip any non-mmio sections */
8013 if (sec->section.type != SECTION_TYPE_MMIO)
8016 section_size = sec->section.size +
8017 sizeof(struct i40e_profile_section_header);
8019 /* Write MMIO section */
8020 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
8021 track_id, &offset, &info, NULL);
8023 i40e_debug(hw, I40E_DEBUG_PACKAGE,
8024 "Failed to write profile: section %d, offset %d, info %d\n",
8033 * i40e_rollback_profile
8034 * @hw: pointer to the hardware structure
8035 * @profile: pointer to the profile segment of the package to be removed
8036 * @track_id: package tracking id
8038 * Rolls back previously loaded package.
8040 enum i40e_status_code
8041 i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
8044 struct i40e_profile_section_header *sec = NULL;
8045 enum i40e_status_code status = I40E_SUCCESS;
8046 struct i40e_section_table *sec_tbl;
8047 u32 offset = 0, info = 0;
8048 u32 section_size = 0;
8052 status = i40e_validate_profile(hw, profile, track_id, true);
8056 I40E_SECTION_TABLE(profile, sec_tbl);
8058 /* For rollback write sections in reverse */
8059 for (i = sec_tbl->section_count - 1; i >= 0; i--) {
8060 sec_off = sec_tbl->section_offset[i];
8061 sec = I40E_SECTION_HEADER(profile, sec_off);
8063 /* Skip any non-rollback sections */
8064 if (sec->section.type != SECTION_TYPE_RB_MMIO)
8067 section_size = sec->section.size +
8068 sizeof(struct i40e_profile_section_header);
8070 /* Write roll-back MMIO section */
8071 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
8072 track_id, &offset, &info, NULL);
8074 i40e_debug(hw, I40E_DEBUG_PACKAGE,
8075 "Failed to write profile: section %d, offset %d, info %d\n",
8084 * i40e_add_pinfo_to_list
8085 * @hw: pointer to the hardware structure
8086 * @profile: pointer to the profile segment of the package
8087 * @profile_info_sec: buffer for information section
8088 * @track_id: package tracking id
8090 * Register a profile to the list of loaded profiles.
8092 enum i40e_status_code
8093 i40e_add_pinfo_to_list(struct i40e_hw *hw,
8094 struct i40e_profile_segment *profile,
8095 u8 *profile_info_sec, u32 track_id)
8097 enum i40e_status_code status = I40E_SUCCESS;
8098 struct i40e_profile_section_header *sec = NULL;
8099 struct i40e_profile_info *pinfo;
8100 u32 offset = 0, info = 0;
8102 sec = (struct i40e_profile_section_header *)profile_info_sec;
8104 sec->data_end = sizeof(struct i40e_profile_section_header) +
8105 sizeof(struct i40e_profile_info);
8106 sec->section.type = SECTION_TYPE_INFO;
8107 sec->section.offset = sizeof(struct i40e_profile_section_header);
8108 sec->section.size = sizeof(struct i40e_profile_info);
8109 pinfo = (struct i40e_profile_info *)(profile_info_sec +
8110 sec->section.offset);
8111 pinfo->track_id = track_id;
8112 pinfo->version = profile->version;
8113 pinfo->op = I40E_DDP_ADD_TRACKID;
8114 i40e_memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE,
8115 I40E_NONDMA_TO_NONDMA);
8117 status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
8118 track_id, &offset, &info, NULL);