1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "i40e_type.h"
35 #include "i40e_adminq.h"
36 #include "i40e_prototype.h"
37 #include "i40e_virtchnl.h"
41 * i40e_set_mac_type - Sets MAC type
42 * @hw: pointer to the HW structure
44 * This function sets the mac type of the adapter based on the
45 * vendor ID and device ID stored in the hw structure.
47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
53 enum i40e_status_code status = I40E_SUCCESS;
55 DEBUGFUNC("i40e_set_mac_type\n");
57 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
58 switch (hw->device_id) {
59 case I40E_DEV_ID_SFP_XL710:
60 case I40E_DEV_ID_QEMU:
61 case I40E_DEV_ID_KX_B:
62 case I40E_DEV_ID_KX_C:
63 case I40E_DEV_ID_QSFP_A:
64 case I40E_DEV_ID_QSFP_B:
65 case I40E_DEV_ID_QSFP_C:
66 case I40E_DEV_ID_10G_BASE_T:
67 case I40E_DEV_ID_10G_BASE_T4:
68 case I40E_DEV_ID_20G_KR2:
69 case I40E_DEV_ID_20G_KR2_A:
70 case I40E_DEV_ID_25G_B:
71 case I40E_DEV_ID_25G_SFP28:
72 hw->mac.type = I40E_MAC_XL710;
75 #ifdef X722_A0_SUPPORT
76 case I40E_DEV_ID_X722_A0:
78 case I40E_DEV_ID_KX_X722:
79 case I40E_DEV_ID_QSFP_X722:
80 case I40E_DEV_ID_SFP_X722:
81 case I40E_DEV_ID_1G_BASE_T_X722:
82 case I40E_DEV_ID_10G_BASE_T_X722:
83 case I40E_DEV_ID_SFP_I_X722:
84 case I40E_DEV_ID_QSFP_I_X722:
85 hw->mac.type = I40E_MAC_X722;
89 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
90 case I40E_DEV_ID_X722_VF:
91 case I40E_DEV_ID_X722_VF_HV:
92 #ifdef X722_A0_SUPPORT
93 case I40E_DEV_ID_X722_A0_VF:
95 hw->mac.type = I40E_MAC_X722_VF;
97 #endif /* INTEGRATED_VF || VF_DRIVER */
98 #endif /* X722_SUPPORT */
99 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
101 case I40E_DEV_ID_VF_HV:
102 hw->mac.type = I40E_MAC_VF;
106 hw->mac.type = I40E_MAC_GENERIC;
110 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
113 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
114 hw->mac.type, status);
118 #ifndef I40E_NDIS_SUPPORT
120 * i40e_aq_str - convert AQ err code to a string
121 * @hw: pointer to the HW structure
122 * @aq_err: the AQ error code to convert
124 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
129 case I40E_AQ_RC_EPERM:
130 return "I40E_AQ_RC_EPERM";
131 case I40E_AQ_RC_ENOENT:
132 return "I40E_AQ_RC_ENOENT";
133 case I40E_AQ_RC_ESRCH:
134 return "I40E_AQ_RC_ESRCH";
135 case I40E_AQ_RC_EINTR:
136 return "I40E_AQ_RC_EINTR";
138 return "I40E_AQ_RC_EIO";
139 case I40E_AQ_RC_ENXIO:
140 return "I40E_AQ_RC_ENXIO";
141 case I40E_AQ_RC_E2BIG:
142 return "I40E_AQ_RC_E2BIG";
143 case I40E_AQ_RC_EAGAIN:
144 return "I40E_AQ_RC_EAGAIN";
145 case I40E_AQ_RC_ENOMEM:
146 return "I40E_AQ_RC_ENOMEM";
147 case I40E_AQ_RC_EACCES:
148 return "I40E_AQ_RC_EACCES";
149 case I40E_AQ_RC_EFAULT:
150 return "I40E_AQ_RC_EFAULT";
151 case I40E_AQ_RC_EBUSY:
152 return "I40E_AQ_RC_EBUSY";
153 case I40E_AQ_RC_EEXIST:
154 return "I40E_AQ_RC_EEXIST";
155 case I40E_AQ_RC_EINVAL:
156 return "I40E_AQ_RC_EINVAL";
157 case I40E_AQ_RC_ENOTTY:
158 return "I40E_AQ_RC_ENOTTY";
159 case I40E_AQ_RC_ENOSPC:
160 return "I40E_AQ_RC_ENOSPC";
161 case I40E_AQ_RC_ENOSYS:
162 return "I40E_AQ_RC_ENOSYS";
163 case I40E_AQ_RC_ERANGE:
164 return "I40E_AQ_RC_ERANGE";
165 case I40E_AQ_RC_EFLUSHED:
166 return "I40E_AQ_RC_EFLUSHED";
167 case I40E_AQ_RC_BAD_ADDR:
168 return "I40E_AQ_RC_BAD_ADDR";
169 case I40E_AQ_RC_EMODE:
170 return "I40E_AQ_RC_EMODE";
171 case I40E_AQ_RC_EFBIG:
172 return "I40E_AQ_RC_EFBIG";
175 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
180 * i40e_stat_str - convert status err code to a string
181 * @hw: pointer to the HW structure
182 * @stat_err: the status error code to convert
184 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
190 return "I40E_ERR_NVM";
191 case I40E_ERR_NVM_CHECKSUM:
192 return "I40E_ERR_NVM_CHECKSUM";
194 return "I40E_ERR_PHY";
195 case I40E_ERR_CONFIG:
196 return "I40E_ERR_CONFIG";
198 return "I40E_ERR_PARAM";
199 case I40E_ERR_MAC_TYPE:
200 return "I40E_ERR_MAC_TYPE";
201 case I40E_ERR_UNKNOWN_PHY:
202 return "I40E_ERR_UNKNOWN_PHY";
203 case I40E_ERR_LINK_SETUP:
204 return "I40E_ERR_LINK_SETUP";
205 case I40E_ERR_ADAPTER_STOPPED:
206 return "I40E_ERR_ADAPTER_STOPPED";
207 case I40E_ERR_INVALID_MAC_ADDR:
208 return "I40E_ERR_INVALID_MAC_ADDR";
209 case I40E_ERR_DEVICE_NOT_SUPPORTED:
210 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
211 case I40E_ERR_MASTER_REQUESTS_PENDING:
212 return "I40E_ERR_MASTER_REQUESTS_PENDING";
213 case I40E_ERR_INVALID_LINK_SETTINGS:
214 return "I40E_ERR_INVALID_LINK_SETTINGS";
215 case I40E_ERR_AUTONEG_NOT_COMPLETE:
216 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
217 case I40E_ERR_RESET_FAILED:
218 return "I40E_ERR_RESET_FAILED";
219 case I40E_ERR_SWFW_SYNC:
220 return "I40E_ERR_SWFW_SYNC";
221 case I40E_ERR_NO_AVAILABLE_VSI:
222 return "I40E_ERR_NO_AVAILABLE_VSI";
223 case I40E_ERR_NO_MEMORY:
224 return "I40E_ERR_NO_MEMORY";
225 case I40E_ERR_BAD_PTR:
226 return "I40E_ERR_BAD_PTR";
227 case I40E_ERR_RING_FULL:
228 return "I40E_ERR_RING_FULL";
229 case I40E_ERR_INVALID_PD_ID:
230 return "I40E_ERR_INVALID_PD_ID";
231 case I40E_ERR_INVALID_QP_ID:
232 return "I40E_ERR_INVALID_QP_ID";
233 case I40E_ERR_INVALID_CQ_ID:
234 return "I40E_ERR_INVALID_CQ_ID";
235 case I40E_ERR_INVALID_CEQ_ID:
236 return "I40E_ERR_INVALID_CEQ_ID";
237 case I40E_ERR_INVALID_AEQ_ID:
238 return "I40E_ERR_INVALID_AEQ_ID";
239 case I40E_ERR_INVALID_SIZE:
240 return "I40E_ERR_INVALID_SIZE";
241 case I40E_ERR_INVALID_ARP_INDEX:
242 return "I40E_ERR_INVALID_ARP_INDEX";
243 case I40E_ERR_INVALID_FPM_FUNC_ID:
244 return "I40E_ERR_INVALID_FPM_FUNC_ID";
245 case I40E_ERR_QP_INVALID_MSG_SIZE:
246 return "I40E_ERR_QP_INVALID_MSG_SIZE";
247 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
248 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
249 case I40E_ERR_INVALID_FRAG_COUNT:
250 return "I40E_ERR_INVALID_FRAG_COUNT";
251 case I40E_ERR_QUEUE_EMPTY:
252 return "I40E_ERR_QUEUE_EMPTY";
253 case I40E_ERR_INVALID_ALIGNMENT:
254 return "I40E_ERR_INVALID_ALIGNMENT";
255 case I40E_ERR_FLUSHED_QUEUE:
256 return "I40E_ERR_FLUSHED_QUEUE";
257 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
258 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
259 case I40E_ERR_INVALID_IMM_DATA_SIZE:
260 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
261 case I40E_ERR_TIMEOUT:
262 return "I40E_ERR_TIMEOUT";
263 case I40E_ERR_OPCODE_MISMATCH:
264 return "I40E_ERR_OPCODE_MISMATCH";
265 case I40E_ERR_CQP_COMPL_ERROR:
266 return "I40E_ERR_CQP_COMPL_ERROR";
267 case I40E_ERR_INVALID_VF_ID:
268 return "I40E_ERR_INVALID_VF_ID";
269 case I40E_ERR_INVALID_HMCFN_ID:
270 return "I40E_ERR_INVALID_HMCFN_ID";
271 case I40E_ERR_BACKING_PAGE_ERROR:
272 return "I40E_ERR_BACKING_PAGE_ERROR";
273 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
274 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
275 case I40E_ERR_INVALID_PBLE_INDEX:
276 return "I40E_ERR_INVALID_PBLE_INDEX";
277 case I40E_ERR_INVALID_SD_INDEX:
278 return "I40E_ERR_INVALID_SD_INDEX";
279 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
280 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
281 case I40E_ERR_INVALID_SD_TYPE:
282 return "I40E_ERR_INVALID_SD_TYPE";
283 case I40E_ERR_MEMCPY_FAILED:
284 return "I40E_ERR_MEMCPY_FAILED";
285 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
286 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
287 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
288 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
289 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
290 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
291 case I40E_ERR_SRQ_ENABLED:
292 return "I40E_ERR_SRQ_ENABLED";
293 case I40E_ERR_ADMIN_QUEUE_ERROR:
294 return "I40E_ERR_ADMIN_QUEUE_ERROR";
295 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
296 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
297 case I40E_ERR_BUF_TOO_SHORT:
298 return "I40E_ERR_BUF_TOO_SHORT";
299 case I40E_ERR_ADMIN_QUEUE_FULL:
300 return "I40E_ERR_ADMIN_QUEUE_FULL";
301 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
302 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
303 case I40E_ERR_BAD_IWARP_CQE:
304 return "I40E_ERR_BAD_IWARP_CQE";
305 case I40E_ERR_NVM_BLANK_MODE:
306 return "I40E_ERR_NVM_BLANK_MODE";
307 case I40E_ERR_NOT_IMPLEMENTED:
308 return "I40E_ERR_NOT_IMPLEMENTED";
309 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
310 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
311 case I40E_ERR_DIAG_TEST_FAILED:
312 return "I40E_ERR_DIAG_TEST_FAILED";
313 case I40E_ERR_NOT_READY:
314 return "I40E_ERR_NOT_READY";
315 case I40E_NOT_SUPPORTED:
316 return "I40E_NOT_SUPPORTED";
317 case I40E_ERR_FIRMWARE_API_VERSION:
318 return "I40E_ERR_FIRMWARE_API_VERSION";
321 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
325 #endif /* I40E_NDIS_SUPPORT */
328 * @hw: debug mask related to admin queue
330 * @desc: pointer to admin queue descriptor
331 * @buffer: pointer to command buffer
332 * @buf_len: max length of buffer
334 * Dumps debug log about adminq command with descriptor contents.
336 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
337 void *buffer, u16 buf_len)
339 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
340 u16 len = LE16_TO_CPU(aq_desc->datalen);
341 u8 *buf = (u8 *)buffer;
344 if ((!(mask & hw->debug_mask)) || (desc == NULL))
348 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
349 LE16_TO_CPU(aq_desc->opcode),
350 LE16_TO_CPU(aq_desc->flags),
351 LE16_TO_CPU(aq_desc->datalen),
352 LE16_TO_CPU(aq_desc->retval));
353 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
354 LE32_TO_CPU(aq_desc->cookie_high),
355 LE32_TO_CPU(aq_desc->cookie_low));
356 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
357 LE32_TO_CPU(aq_desc->params.internal.param0),
358 LE32_TO_CPU(aq_desc->params.internal.param1));
359 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
360 LE32_TO_CPU(aq_desc->params.external.addr_high),
361 LE32_TO_CPU(aq_desc->params.external.addr_low));
363 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
364 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
367 /* write the full 16-byte chunks */
368 for (i = 0; i < (len - 16); i += 16)
370 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
371 i, buf[i], buf[i+1], buf[i+2], buf[i+3],
372 buf[i+4], buf[i+5], buf[i+6], buf[i+7],
373 buf[i+8], buf[i+9], buf[i+10], buf[i+11],
374 buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
375 /* the most we could have left is 16 bytes, pad with zeros */
381 memset(d_buf, 0, sizeof(d_buf));
382 for (j = 0; i < len; j++, i++)
385 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
386 i_sav, d_buf[0], d_buf[1],
388 d_buf[4], d_buf[5], d_buf[6], d_buf[7],
389 d_buf[8], d_buf[9], d_buf[10], d_buf[11],
390 d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
396 * i40e_check_asq_alive
397 * @hw: pointer to the hw struct
399 * Returns true if Queue is enabled else false.
401 bool i40e_check_asq_alive(struct i40e_hw *hw)
407 return !!(rd32(hw, hw->aq.asq.len) &
408 I40E_PF_ATQLEN_ATQENABLE_MASK);
410 return !!(rd32(hw, hw->aq.asq.len) &
411 I40E_PF_ATQLEN_ATQENABLE_MASK);
412 #endif /* INTEGRATED_VF */
413 #endif /* PF_DRIVER */
417 return !!(rd32(hw, hw->aq.asq.len) &
418 I40E_VF_ATQLEN1_ATQENABLE_MASK);
420 return !!(rd32(hw, hw->aq.asq.len) &
421 I40E_VF_ATQLEN1_ATQENABLE_MASK);
422 #endif /* INTEGRATED_VF */
423 #endif /* VF_DRIVER */
428 * i40e_aq_queue_shutdown
429 * @hw: pointer to the hw struct
430 * @unloading: is the driver unloading itself
432 * Tell the Firmware that we're shutting down the AdminQ and whether
433 * or not the driver is unloading as well.
435 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
438 struct i40e_aq_desc desc;
439 struct i40e_aqc_queue_shutdown *cmd =
440 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
441 enum i40e_status_code status;
443 i40e_fill_default_direct_cmd_desc(&desc,
444 i40e_aqc_opc_queue_shutdown);
447 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
448 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
455 * i40e_aq_get_set_rss_lut
456 * @hw: pointer to the hardware structure
457 * @vsi_id: vsi fw index
458 * @pf_lut: for PF table set true, for VSI table set false
459 * @lut: pointer to the lut buffer provided by the caller
460 * @lut_size: size of the lut buffer
461 * @set: set true to set the table, false to get the table
463 * Internal function to get or set RSS look up table
465 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
466 u16 vsi_id, bool pf_lut,
467 u8 *lut, u16 lut_size,
470 enum i40e_status_code status;
471 struct i40e_aq_desc desc;
472 struct i40e_aqc_get_set_rss_lut *cmd_resp =
473 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
476 i40e_fill_default_direct_cmd_desc(&desc,
477 i40e_aqc_opc_set_rss_lut);
479 i40e_fill_default_direct_cmd_desc(&desc,
480 i40e_aqc_opc_get_rss_lut);
482 /* Indirect command */
483 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
484 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
487 CPU_TO_LE16((u16)((vsi_id <<
488 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
489 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
490 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
493 cmd_resp->flags |= CPU_TO_LE16((u16)
494 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
495 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
496 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
498 cmd_resp->flags |= CPU_TO_LE16((u16)
499 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
500 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
501 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
503 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
509 * i40e_aq_get_rss_lut
510 * @hw: pointer to the hardware structure
511 * @vsi_id: vsi fw index
512 * @pf_lut: for PF table set true, for VSI table set false
513 * @lut: pointer to the lut buffer provided by the caller
514 * @lut_size: size of the lut buffer
516 * get the RSS lookup table, PF or VSI type
518 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
519 bool pf_lut, u8 *lut, u16 lut_size)
521 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
526 * i40e_aq_set_rss_lut
527 * @hw: pointer to the hardware structure
528 * @vsi_id: vsi fw index
529 * @pf_lut: for PF table set true, for VSI table set false
530 * @lut: pointer to the lut buffer provided by the caller
531 * @lut_size: size of the lut buffer
533 * set the RSS lookup table, PF or VSI type
535 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
536 bool pf_lut, u8 *lut, u16 lut_size)
538 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
542 * i40e_aq_get_set_rss_key
543 * @hw: pointer to the hw struct
544 * @vsi_id: vsi fw index
545 * @key: pointer to key info struct
546 * @set: set true to set the key, false to get the key
548 * get the RSS key per VSI
550 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
552 struct i40e_aqc_get_set_rss_key_data *key,
555 enum i40e_status_code status;
556 struct i40e_aq_desc desc;
557 struct i40e_aqc_get_set_rss_key *cmd_resp =
558 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
559 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
562 i40e_fill_default_direct_cmd_desc(&desc,
563 i40e_aqc_opc_set_rss_key);
565 i40e_fill_default_direct_cmd_desc(&desc,
566 i40e_aqc_opc_get_rss_key);
568 /* Indirect command */
569 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
570 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
573 CPU_TO_LE16((u16)((vsi_id <<
574 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
575 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
576 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
578 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
584 * i40e_aq_get_rss_key
585 * @hw: pointer to the hw struct
586 * @vsi_id: vsi fw index
587 * @key: pointer to key info struct
590 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
592 struct i40e_aqc_get_set_rss_key_data *key)
594 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
598 * i40e_aq_set_rss_key
599 * @hw: pointer to the hw struct
600 * @vsi_id: vsi fw index
601 * @key: pointer to key info struct
603 * set the RSS key per VSI
605 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
607 struct i40e_aqc_get_set_rss_key_data *key)
609 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
611 #endif /* X722_SUPPORT */
613 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
614 * hardware to a bit-field that can be used by SW to more easily determine the
617 * Macros are used to shorten the table lines and make this table human
620 * We store the PTYPE in the top byte of the bit field - this is just so that
621 * we can check that the table doesn't have a row missing, as the index into
622 * the table should be the PTYPE.
626 * IF NOT i40e_ptype_lookup[ptype].known
629 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
630 * Use the rest of the fields to look at the tunnels, inner protocols, etc
632 * Use the enum i40e_rx_l2_ptype to decode the packet type
636 /* macro to make the table lines short */
637 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
640 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
641 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
642 I40E_RX_PTYPE_##OUTER_FRAG, \
643 I40E_RX_PTYPE_TUNNEL_##T, \
644 I40E_RX_PTYPE_TUNNEL_END_##TE, \
645 I40E_RX_PTYPE_##TEF, \
646 I40E_RX_PTYPE_INNER_PROT_##I, \
647 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
649 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
650 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
652 /* shorter macros makes the table fit but are terse */
653 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
654 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
655 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
657 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
658 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
659 /* L2 Packet types */
660 I40E_PTT_UNUSED_ENTRY(0),
661 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
662 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
663 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
664 I40E_PTT_UNUSED_ENTRY(4),
665 I40E_PTT_UNUSED_ENTRY(5),
666 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
667 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
668 I40E_PTT_UNUSED_ENTRY(8),
669 I40E_PTT_UNUSED_ENTRY(9),
670 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
671 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
672 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
673 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
674 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
675 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
676 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
677 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
678 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
679 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
680 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
681 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
683 /* Non Tunneled IPv4 */
684 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
685 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
686 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
687 I40E_PTT_UNUSED_ENTRY(25),
688 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
689 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
690 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
693 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
694 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
695 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
696 I40E_PTT_UNUSED_ENTRY(32),
697 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
698 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
699 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
702 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
703 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
704 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
705 I40E_PTT_UNUSED_ENTRY(39),
706 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
707 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
708 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
710 /* IPv4 --> GRE/NAT */
711 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
713 /* IPv4 --> GRE/NAT --> IPv4 */
714 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
715 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
716 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
717 I40E_PTT_UNUSED_ENTRY(47),
718 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
719 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
720 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
722 /* IPv4 --> GRE/NAT --> IPv6 */
723 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
724 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
725 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
726 I40E_PTT_UNUSED_ENTRY(54),
727 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
728 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
729 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
731 /* IPv4 --> GRE/NAT --> MAC */
732 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
734 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
735 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
736 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
737 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
738 I40E_PTT_UNUSED_ENTRY(62),
739 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
740 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
741 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
743 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
744 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
745 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
746 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
747 I40E_PTT_UNUSED_ENTRY(69),
748 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
749 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
750 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
752 /* IPv4 --> GRE/NAT --> MAC/VLAN */
753 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
755 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
756 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
757 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
758 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
759 I40E_PTT_UNUSED_ENTRY(77),
760 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
761 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
762 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
764 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
765 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
766 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
767 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
768 I40E_PTT_UNUSED_ENTRY(84),
769 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
770 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
771 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
773 /* Non Tunneled IPv6 */
774 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
775 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
776 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
777 I40E_PTT_UNUSED_ENTRY(91),
778 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
779 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
780 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
783 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
784 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
785 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
786 I40E_PTT_UNUSED_ENTRY(98),
787 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
788 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
789 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
792 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
793 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
794 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
795 I40E_PTT_UNUSED_ENTRY(105),
796 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
797 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
798 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
800 /* IPv6 --> GRE/NAT */
801 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
803 /* IPv6 --> GRE/NAT -> IPv4 */
804 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
805 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
806 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
807 I40E_PTT_UNUSED_ENTRY(113),
808 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
809 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
810 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
812 /* IPv6 --> GRE/NAT -> IPv6 */
813 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
814 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
815 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
816 I40E_PTT_UNUSED_ENTRY(120),
817 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
818 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
819 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
821 /* IPv6 --> GRE/NAT -> MAC */
822 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
824 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
825 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
826 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
827 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
828 I40E_PTT_UNUSED_ENTRY(128),
829 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
830 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
831 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
833 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
834 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
835 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
836 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
837 I40E_PTT_UNUSED_ENTRY(135),
838 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
839 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
840 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
842 /* IPv6 --> GRE/NAT -> MAC/VLAN */
843 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
845 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
846 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
847 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
848 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
849 I40E_PTT_UNUSED_ENTRY(143),
850 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
851 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
852 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
854 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
855 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
856 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
857 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
858 I40E_PTT_UNUSED_ENTRY(150),
859 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
860 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
861 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
864 I40E_PTT_UNUSED_ENTRY(154),
865 I40E_PTT_UNUSED_ENTRY(155),
866 I40E_PTT_UNUSED_ENTRY(156),
867 I40E_PTT_UNUSED_ENTRY(157),
868 I40E_PTT_UNUSED_ENTRY(158),
869 I40E_PTT_UNUSED_ENTRY(159),
871 I40E_PTT_UNUSED_ENTRY(160),
872 I40E_PTT_UNUSED_ENTRY(161),
873 I40E_PTT_UNUSED_ENTRY(162),
874 I40E_PTT_UNUSED_ENTRY(163),
875 I40E_PTT_UNUSED_ENTRY(164),
876 I40E_PTT_UNUSED_ENTRY(165),
877 I40E_PTT_UNUSED_ENTRY(166),
878 I40E_PTT_UNUSED_ENTRY(167),
879 I40E_PTT_UNUSED_ENTRY(168),
880 I40E_PTT_UNUSED_ENTRY(169),
882 I40E_PTT_UNUSED_ENTRY(170),
883 I40E_PTT_UNUSED_ENTRY(171),
884 I40E_PTT_UNUSED_ENTRY(172),
885 I40E_PTT_UNUSED_ENTRY(173),
886 I40E_PTT_UNUSED_ENTRY(174),
887 I40E_PTT_UNUSED_ENTRY(175),
888 I40E_PTT_UNUSED_ENTRY(176),
889 I40E_PTT_UNUSED_ENTRY(177),
890 I40E_PTT_UNUSED_ENTRY(178),
891 I40E_PTT_UNUSED_ENTRY(179),
893 I40E_PTT_UNUSED_ENTRY(180),
894 I40E_PTT_UNUSED_ENTRY(181),
895 I40E_PTT_UNUSED_ENTRY(182),
896 I40E_PTT_UNUSED_ENTRY(183),
897 I40E_PTT_UNUSED_ENTRY(184),
898 I40E_PTT_UNUSED_ENTRY(185),
899 I40E_PTT_UNUSED_ENTRY(186),
900 I40E_PTT_UNUSED_ENTRY(187),
901 I40E_PTT_UNUSED_ENTRY(188),
902 I40E_PTT_UNUSED_ENTRY(189),
904 I40E_PTT_UNUSED_ENTRY(190),
905 I40E_PTT_UNUSED_ENTRY(191),
906 I40E_PTT_UNUSED_ENTRY(192),
907 I40E_PTT_UNUSED_ENTRY(193),
908 I40E_PTT_UNUSED_ENTRY(194),
909 I40E_PTT_UNUSED_ENTRY(195),
910 I40E_PTT_UNUSED_ENTRY(196),
911 I40E_PTT_UNUSED_ENTRY(197),
912 I40E_PTT_UNUSED_ENTRY(198),
913 I40E_PTT_UNUSED_ENTRY(199),
915 I40E_PTT_UNUSED_ENTRY(200),
916 I40E_PTT_UNUSED_ENTRY(201),
917 I40E_PTT_UNUSED_ENTRY(202),
918 I40E_PTT_UNUSED_ENTRY(203),
919 I40E_PTT_UNUSED_ENTRY(204),
920 I40E_PTT_UNUSED_ENTRY(205),
921 I40E_PTT_UNUSED_ENTRY(206),
922 I40E_PTT_UNUSED_ENTRY(207),
923 I40E_PTT_UNUSED_ENTRY(208),
924 I40E_PTT_UNUSED_ENTRY(209),
926 I40E_PTT_UNUSED_ENTRY(210),
927 I40E_PTT_UNUSED_ENTRY(211),
928 I40E_PTT_UNUSED_ENTRY(212),
929 I40E_PTT_UNUSED_ENTRY(213),
930 I40E_PTT_UNUSED_ENTRY(214),
931 I40E_PTT_UNUSED_ENTRY(215),
932 I40E_PTT_UNUSED_ENTRY(216),
933 I40E_PTT_UNUSED_ENTRY(217),
934 I40E_PTT_UNUSED_ENTRY(218),
935 I40E_PTT_UNUSED_ENTRY(219),
937 I40E_PTT_UNUSED_ENTRY(220),
938 I40E_PTT_UNUSED_ENTRY(221),
939 I40E_PTT_UNUSED_ENTRY(222),
940 I40E_PTT_UNUSED_ENTRY(223),
941 I40E_PTT_UNUSED_ENTRY(224),
942 I40E_PTT_UNUSED_ENTRY(225),
943 I40E_PTT_UNUSED_ENTRY(226),
944 I40E_PTT_UNUSED_ENTRY(227),
945 I40E_PTT_UNUSED_ENTRY(228),
946 I40E_PTT_UNUSED_ENTRY(229),
948 I40E_PTT_UNUSED_ENTRY(230),
949 I40E_PTT_UNUSED_ENTRY(231),
950 I40E_PTT_UNUSED_ENTRY(232),
951 I40E_PTT_UNUSED_ENTRY(233),
952 I40E_PTT_UNUSED_ENTRY(234),
953 I40E_PTT_UNUSED_ENTRY(235),
954 I40E_PTT_UNUSED_ENTRY(236),
955 I40E_PTT_UNUSED_ENTRY(237),
956 I40E_PTT_UNUSED_ENTRY(238),
957 I40E_PTT_UNUSED_ENTRY(239),
959 I40E_PTT_UNUSED_ENTRY(240),
960 I40E_PTT_UNUSED_ENTRY(241),
961 I40E_PTT_UNUSED_ENTRY(242),
962 I40E_PTT_UNUSED_ENTRY(243),
963 I40E_PTT_UNUSED_ENTRY(244),
964 I40E_PTT_UNUSED_ENTRY(245),
965 I40E_PTT_UNUSED_ENTRY(246),
966 I40E_PTT_UNUSED_ENTRY(247),
967 I40E_PTT_UNUSED_ENTRY(248),
968 I40E_PTT_UNUSED_ENTRY(249),
970 I40E_PTT_UNUSED_ENTRY(250),
971 I40E_PTT_UNUSED_ENTRY(251),
972 I40E_PTT_UNUSED_ENTRY(252),
973 I40E_PTT_UNUSED_ENTRY(253),
974 I40E_PTT_UNUSED_ENTRY(254),
975 I40E_PTT_UNUSED_ENTRY(255)
980 * i40e_validate_mac_addr - Validate unicast MAC address
981 * @mac_addr: pointer to MAC address
983 * Tests a MAC address to ensure it is a valid Individual Address
985 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
987 enum i40e_status_code status = I40E_SUCCESS;
989 DEBUGFUNC("i40e_validate_mac_addr");
991 /* Broadcast addresses ARE multicast addresses
992 * Make sure it is not a multicast address
993 * Reject the zero address
995 if (I40E_IS_MULTICAST(mac_addr) ||
996 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
997 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
998 status = I40E_ERR_INVALID_MAC_ADDR;
1005 * i40e_init_shared_code - Initialize the shared code
1006 * @hw: pointer to hardware structure
1008 * This assigns the MAC type and PHY code and inits the NVM.
1009 * Does not touch the hardware. This function must be called prior to any
1010 * other function in the shared code. The i40e_hw structure should be
1011 * memset to 0 prior to calling this function. The following fields in
1012 * hw structure should be filled in prior to calling this function:
1013 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1014 * subsystem_vendor_id, and revision_id
1016 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
1018 enum i40e_status_code status = I40E_SUCCESS;
1019 u32 port, ari, func_rid;
1021 DEBUGFUNC("i40e_init_shared_code");
1023 i40e_set_mac_type(hw);
1025 switch (hw->mac.type) {
1026 case I40E_MAC_XL710:
1032 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1035 hw->phy.get_link_info = true;
1037 /* Determine port number and PF number*/
1038 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1039 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1040 hw->port = (u8)port;
1041 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1042 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1043 func_rid = rd32(hw, I40E_PF_FUNC_RID);
1045 hw->pf_id = (u8)(func_rid & 0xff);
1047 hw->pf_id = (u8)(func_rid & 0x7);
1050 if (hw->mac.type == I40E_MAC_X722)
1051 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
1054 status = i40e_init_nvm(hw);
1059 * i40e_aq_mac_address_read - Retrieve the MAC addresses
1060 * @hw: pointer to the hw struct
1061 * @flags: a return indicator of what addresses were added to the addr store
1062 * @addrs: the requestor's mac addr store
1063 * @cmd_details: pointer to command details structure or NULL
1065 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1067 struct i40e_aqc_mac_address_read_data *addrs,
1068 struct i40e_asq_cmd_details *cmd_details)
1070 struct i40e_aq_desc desc;
1071 struct i40e_aqc_mac_address_read *cmd_data =
1072 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1073 enum i40e_status_code status;
1075 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1076 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1078 status = i40e_asq_send_command(hw, &desc, addrs,
1079 sizeof(*addrs), cmd_details);
1080 *flags = LE16_TO_CPU(cmd_data->command_flags);
1086 * i40e_aq_mac_address_write - Change the MAC addresses
1087 * @hw: pointer to the hw struct
1088 * @flags: indicates which MAC to be written
1089 * @mac_addr: address to write
1090 * @cmd_details: pointer to command details structure or NULL
1092 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1093 u16 flags, u8 *mac_addr,
1094 struct i40e_asq_cmd_details *cmd_details)
1096 struct i40e_aq_desc desc;
1097 struct i40e_aqc_mac_address_write *cmd_data =
1098 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1099 enum i40e_status_code status;
1101 i40e_fill_default_direct_cmd_desc(&desc,
1102 i40e_aqc_opc_mac_address_write);
1103 cmd_data->command_flags = CPU_TO_LE16(flags);
1104 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1105 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1106 ((u32)mac_addr[3] << 16) |
1107 ((u32)mac_addr[4] << 8) |
1110 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1116 * i40e_get_mac_addr - get MAC address
1117 * @hw: pointer to the HW structure
1118 * @mac_addr: pointer to MAC address
1120 * Reads the adapter's MAC address from register
1122 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1124 struct i40e_aqc_mac_address_read_data addrs;
1125 enum i40e_status_code status;
1128 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1130 if (flags & I40E_AQC_LAN_ADDR_VALID)
1131 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
1137 * i40e_get_port_mac_addr - get Port MAC address
1138 * @hw: pointer to the HW structure
1139 * @mac_addr: pointer to Port MAC address
1141 * Reads the adapter's Port MAC address
1143 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1145 struct i40e_aqc_mac_address_read_data addrs;
1146 enum i40e_status_code status;
1149 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1153 if (flags & I40E_AQC_PORT_ADDR_VALID)
1154 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
1156 status = I40E_ERR_INVALID_MAC_ADDR;
1162 * i40e_pre_tx_queue_cfg - pre tx queue configure
1163 * @hw: pointer to the HW structure
1164 * @queue: target pf queue index
1165 * @enable: state change request
1167 * Handles hw requirement to indicate intention to enable
1168 * or disable target queue.
1170 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1172 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1176 if (abs_queue_idx >= 128) {
1177 reg_block = abs_queue_idx / 128;
1178 abs_queue_idx %= 128;
1181 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1182 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1183 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1186 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1188 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1190 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1194 * i40e_read_pba_string - Reads part number string from EEPROM
1195 * @hw: pointer to hardware structure
1196 * @pba_num: stores the part number string from the EEPROM
1197 * @pba_num_size: part number string buffer length
1199 * Reads the part number string from the EEPROM.
1201 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1204 enum i40e_status_code status = I40E_SUCCESS;
1210 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1211 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1212 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1216 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1217 if (status != I40E_SUCCESS) {
1218 DEBUGOUT("Failed to read PBA Block pointer.\n");
1222 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1223 if (status != I40E_SUCCESS) {
1224 DEBUGOUT("Failed to read PBA Block size.\n");
1228 /* Subtract one to get PBA word count (PBA Size word is included in
1232 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1233 DEBUGOUT("Buffer to small for PBA data.\n");
1234 return I40E_ERR_PARAM;
1237 for (i = 0; i < pba_size; i++) {
1238 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1239 if (status != I40E_SUCCESS) {
1240 DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1244 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1245 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1247 pba_num[(pba_size * 2)] = '\0';
1253 * i40e_get_media_type - Gets media type
1254 * @hw: pointer to the hardware structure
1256 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1258 enum i40e_media_type media;
1260 switch (hw->phy.link_info.phy_type) {
1261 case I40E_PHY_TYPE_10GBASE_SR:
1262 case I40E_PHY_TYPE_10GBASE_LR:
1263 case I40E_PHY_TYPE_1000BASE_SX:
1264 case I40E_PHY_TYPE_1000BASE_LX:
1265 case I40E_PHY_TYPE_40GBASE_SR4:
1266 case I40E_PHY_TYPE_40GBASE_LR4:
1267 media = I40E_MEDIA_TYPE_FIBER;
1269 case I40E_PHY_TYPE_100BASE_TX:
1270 case I40E_PHY_TYPE_1000BASE_T:
1271 case I40E_PHY_TYPE_10GBASE_T:
1272 media = I40E_MEDIA_TYPE_BASET;
1274 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1275 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1276 case I40E_PHY_TYPE_10GBASE_CR1:
1277 case I40E_PHY_TYPE_40GBASE_CR4:
1278 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1279 case I40E_PHY_TYPE_40GBASE_AOC:
1280 case I40E_PHY_TYPE_10GBASE_AOC:
1281 media = I40E_MEDIA_TYPE_DA;
1283 case I40E_PHY_TYPE_1000BASE_KX:
1284 case I40E_PHY_TYPE_10GBASE_KX4:
1285 case I40E_PHY_TYPE_10GBASE_KR:
1286 case I40E_PHY_TYPE_40GBASE_KR4:
1287 case I40E_PHY_TYPE_20GBASE_KR2:
1288 media = I40E_MEDIA_TYPE_BACKPLANE;
1290 case I40E_PHY_TYPE_SGMII:
1291 case I40E_PHY_TYPE_XAUI:
1292 case I40E_PHY_TYPE_XFI:
1293 case I40E_PHY_TYPE_XLAUI:
1294 case I40E_PHY_TYPE_XLPPI:
1296 media = I40E_MEDIA_TYPE_UNKNOWN;
1303 #define I40E_PF_RESET_WAIT_COUNT 200
1305 * i40e_pf_reset - Reset the PF
1306 * @hw: pointer to the hardware structure
1308 * Assuming someone else has triggered a global reset,
1309 * assure the global reset is complete and then reset the PF
1311 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1318 /* Poll for Global Reset steady state in case of recent GRST.
1319 * The grst delay value is in 100ms units, and we'll wait a
1320 * couple counts longer to be sure we don't just miss the end.
1322 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1323 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1324 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1326 grst_del = grst_del * 20;
1328 for (cnt = 0; cnt < grst_del; cnt++) {
1329 reg = rd32(hw, I40E_GLGEN_RSTAT);
1330 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1332 i40e_msec_delay(100);
1334 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1335 DEBUGOUT("Global reset polling failed to complete.\n");
1336 return I40E_ERR_RESET_FAILED;
1339 /* Now Wait for the FW to be ready */
1340 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1341 reg = rd32(hw, I40E_GLNVM_ULD);
1342 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1343 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1344 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1345 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1346 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1349 i40e_msec_delay(10);
1351 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1352 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1353 DEBUGOUT("wait for FW Reset complete timedout\n");
1354 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1355 return I40E_ERR_RESET_FAILED;
1358 /* If there was a Global Reset in progress when we got here,
1359 * we don't need to do the PF Reset
1362 reg = rd32(hw, I40E_PFGEN_CTRL);
1363 wr32(hw, I40E_PFGEN_CTRL,
1364 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1365 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1366 reg = rd32(hw, I40E_PFGEN_CTRL);
1367 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1371 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1372 DEBUGOUT("PF reset polling failed to complete.\n");
1373 return I40E_ERR_RESET_FAILED;
1377 i40e_clear_pxe_mode(hw);
1380 return I40E_SUCCESS;
1384 * i40e_clear_hw - clear out any left over hw state
1385 * @hw: pointer to the hw struct
1387 * Clear queues and interrupts, typically called at init time,
1388 * but after the capabilities have been found so we know how many
1389 * queues and msix vectors have been allocated.
1391 void i40e_clear_hw(struct i40e_hw *hw)
1393 u32 num_queues, base_queue;
1401 /* get number of interrupts, queues, and vfs */
1402 val = rd32(hw, I40E_GLPCI_CNF2);
1403 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1404 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1405 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1406 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1408 val = rd32(hw, I40E_PFLAN_QALLOC);
1409 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1410 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1411 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1412 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1413 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1414 num_queues = (j - base_queue) + 1;
1418 val = rd32(hw, I40E_PF_VT_PFALLOC);
1419 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1420 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1421 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1422 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1423 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1424 num_vfs = (j - i) + 1;
1428 /* stop all the interrupts */
1429 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1430 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1431 for (i = 0; i < num_pf_int - 2; i++)
1432 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1434 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1435 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1436 wr32(hw, I40E_PFINT_LNKLST0, val);
1437 for (i = 0; i < num_pf_int - 2; i++)
1438 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1439 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1440 for (i = 0; i < num_vfs; i++)
1441 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1442 for (i = 0; i < num_vf_int - 2; i++)
1443 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1445 /* warn the HW of the coming Tx disables */
1446 for (i = 0; i < num_queues; i++) {
1447 u32 abs_queue_idx = base_queue + i;
1450 if (abs_queue_idx >= 128) {
1451 reg_block = abs_queue_idx / 128;
1452 abs_queue_idx %= 128;
1455 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1456 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1457 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1458 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1460 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1462 i40e_usec_delay(400);
1464 /* stop all the queues */
1465 for (i = 0; i < num_queues; i++) {
1466 wr32(hw, I40E_QINT_TQCTL(i), 0);
1467 wr32(hw, I40E_QTX_ENA(i), 0);
1468 wr32(hw, I40E_QINT_RQCTL(i), 0);
1469 wr32(hw, I40E_QRX_ENA(i), 0);
1472 /* short wait for all queue disables to settle */
1473 i40e_usec_delay(50);
1477 * i40e_clear_pxe_mode - clear pxe operations mode
1478 * @hw: pointer to the hw struct
1480 * Make sure all PXE mode settings are cleared, including things
1481 * like descriptor fetch/write-back mode.
1483 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1485 if (i40e_check_asq_alive(hw))
1486 i40e_aq_clear_pxe_mode(hw, NULL);
1490 * i40e_led_is_mine - helper to find matching led
1491 * @hw: pointer to the hw struct
1492 * @idx: index into GPIO registers
1494 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1496 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1501 if (!hw->func_caps.led[idx])
1504 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1505 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1506 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1508 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1509 * if it is not our port then ignore
1511 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1518 #define I40E_COMBINED_ACTIVITY 0xA
1519 #define I40E_FILTER_ACTIVITY 0xE
1520 #define I40E_LINK_ACTIVITY 0xC
1521 #define I40E_MAC_ACTIVITY 0xD
1522 #define I40E_LED0 22
1525 * i40e_led_get - return current on/off mode
1526 * @hw: pointer to the hw struct
1528 * The value returned is the 'mode' field as defined in the
1529 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1530 * values are variations of possible behaviors relating to
1531 * blink, link, and wire.
1533 u32 i40e_led_get(struct i40e_hw *hw)
1535 u32 current_mode = 0;
1539 /* as per the documentation GPIO 22-29 are the LED
1540 * GPIO pins named LED0..LED7
1542 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1543 u32 gpio_val = i40e_led_is_mine(hw, i);
1548 /* ignore gpio LED src mode entries related to the activity
1551 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1552 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1553 switch (current_mode) {
1554 case I40E_COMBINED_ACTIVITY:
1555 case I40E_FILTER_ACTIVITY:
1556 case I40E_MAC_ACTIVITY:
1562 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1563 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1571 * i40e_led_set - set new on/off mode
1572 * @hw: pointer to the hw struct
1573 * @mode: 0=off, 0xf=on (else see manual for mode details)
1574 * @blink: true if the LED should blink when on, false if steady
1576 * if this function is used to turn on the blink it should
1577 * be used to disable the blink when restoring the original state.
1579 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1581 u32 current_mode = 0;
1584 if (mode & 0xfffffff0)
1585 DEBUGOUT1("invalid mode passed in %X\n", mode);
1587 /* as per the documentation GPIO 22-29 are the LED
1588 * GPIO pins named LED0..LED7
1590 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1591 u32 gpio_val = i40e_led_is_mine(hw, i);
1596 /* ignore gpio LED src mode entries related to the activity
1599 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1600 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1601 switch (current_mode) {
1602 case I40E_COMBINED_ACTIVITY:
1603 case I40E_FILTER_ACTIVITY:
1604 case I40E_MAC_ACTIVITY:
1610 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1611 /* this & is a bit of paranoia, but serves as a range check */
1612 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1613 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1615 if (mode == I40E_LINK_ACTIVITY)
1619 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1621 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1623 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1628 /* Admin command wrappers */
1631 * i40e_aq_get_phy_capabilities
1632 * @hw: pointer to the hw struct
1633 * @abilities: structure for PHY capabilities to be filled
1634 * @qualified_modules: report Qualified Modules
1635 * @report_init: report init capabilities (active are default)
1636 * @cmd_details: pointer to command details structure or NULL
1638 * Returns the various PHY abilities supported on the Port.
1640 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1641 bool qualified_modules, bool report_init,
1642 struct i40e_aq_get_phy_abilities_resp *abilities,
1643 struct i40e_asq_cmd_details *cmd_details)
1645 struct i40e_aq_desc desc;
1646 enum i40e_status_code status;
1647 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1650 return I40E_ERR_PARAM;
1652 i40e_fill_default_direct_cmd_desc(&desc,
1653 i40e_aqc_opc_get_phy_abilities);
1655 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1656 if (abilities_size > I40E_AQ_LARGE_BUF)
1657 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1659 if (qualified_modules)
1660 desc.params.external.param0 |=
1661 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1664 desc.params.external.param0 |=
1665 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1667 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1670 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1671 status = I40E_ERR_UNKNOWN_PHY;
1674 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1680 * i40e_aq_set_phy_config
1681 * @hw: pointer to the hw struct
1682 * @config: structure with PHY configuration to be set
1683 * @cmd_details: pointer to command details structure or NULL
1685 * Set the various PHY configuration parameters
1686 * supported on the Port.One or more of the Set PHY config parameters may be
1687 * ignored in an MFP mode as the PF may not have the privilege to set some
1688 * of the PHY Config parameters. This status will be indicated by the
1691 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1692 struct i40e_aq_set_phy_config *config,
1693 struct i40e_asq_cmd_details *cmd_details)
1695 struct i40e_aq_desc desc;
1696 struct i40e_aq_set_phy_config *cmd =
1697 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1698 enum i40e_status_code status;
1701 return I40E_ERR_PARAM;
1703 i40e_fill_default_direct_cmd_desc(&desc,
1704 i40e_aqc_opc_set_phy_config);
1708 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1715 * @hw: pointer to the hw struct
1717 * Set the requested flow control mode using set_phy_config.
1719 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1720 bool atomic_restart)
1722 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1723 struct i40e_aq_get_phy_abilities_resp abilities;
1724 struct i40e_aq_set_phy_config config;
1725 enum i40e_status_code status;
1726 u8 pause_mask = 0x0;
1732 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1733 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1735 case I40E_FC_RX_PAUSE:
1736 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1738 case I40E_FC_TX_PAUSE:
1739 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1745 /* Get the current phy config */
1746 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1749 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1753 memset(&config, 0, sizeof(config));
1754 /* clear the old pause settings */
1755 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1756 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1757 /* set the new abilities */
1758 config.abilities |= pause_mask;
1759 /* If the abilities have changed, then set the new config */
1760 if (config.abilities != abilities.abilities) {
1761 /* Auto restart link so settings take effect */
1763 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1764 /* Copy over all the old settings */
1765 config.phy_type = abilities.phy_type;
1766 config.link_speed = abilities.link_speed;
1767 config.eee_capability = abilities.eee_capability;
1768 config.eeer = abilities.eeer_val;
1769 config.low_power_ctrl = abilities.d3_lpan;
1770 status = i40e_aq_set_phy_config(hw, &config, NULL);
1773 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1775 /* Update the link info */
1776 status = i40e_update_link_info(hw);
1778 /* Wait a little bit (on 40G cards it sometimes takes a really
1779 * long time for link to come back from the atomic reset)
1782 i40e_msec_delay(1000);
1783 status = i40e_update_link_info(hw);
1786 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1792 * i40e_aq_set_mac_config
1793 * @hw: pointer to the hw struct
1794 * @max_frame_size: Maximum Frame Size to be supported by the port
1795 * @crc_en: Tell HW to append a CRC to outgoing frames
1796 * @pacing: Pacing configurations
1797 * @cmd_details: pointer to command details structure or NULL
1799 * Configure MAC settings for frame size, jumbo frame support and the
1800 * addition of a CRC by the hardware.
1802 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1804 bool crc_en, u16 pacing,
1805 struct i40e_asq_cmd_details *cmd_details)
1807 struct i40e_aq_desc desc;
1808 struct i40e_aq_set_mac_config *cmd =
1809 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1810 enum i40e_status_code status;
1812 if (max_frame_size == 0)
1813 return I40E_ERR_PARAM;
1815 i40e_fill_default_direct_cmd_desc(&desc,
1816 i40e_aqc_opc_set_mac_config);
1818 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1819 cmd->params = ((u8)pacing & 0x0F) << 3;
1821 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1823 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1829 * i40e_aq_clear_pxe_mode
1830 * @hw: pointer to the hw struct
1831 * @cmd_details: pointer to command details structure or NULL
1833 * Tell the firmware that the driver is taking over from PXE
1835 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1836 struct i40e_asq_cmd_details *cmd_details)
1838 enum i40e_status_code status;
1839 struct i40e_aq_desc desc;
1840 struct i40e_aqc_clear_pxe *cmd =
1841 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1843 i40e_fill_default_direct_cmd_desc(&desc,
1844 i40e_aqc_opc_clear_pxe_mode);
1848 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1850 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1856 * i40e_aq_set_link_restart_an
1857 * @hw: pointer to the hw struct
1858 * @enable_link: if true: enable link, if false: disable link
1859 * @cmd_details: pointer to command details structure or NULL
1861 * Sets up the link and restarts the Auto-Negotiation over the link.
1863 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1864 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1866 struct i40e_aq_desc desc;
1867 struct i40e_aqc_set_link_restart_an *cmd =
1868 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1869 enum i40e_status_code status;
1871 i40e_fill_default_direct_cmd_desc(&desc,
1872 i40e_aqc_opc_set_link_restart_an);
1874 cmd->command = I40E_AQ_PHY_RESTART_AN;
1876 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1878 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1880 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1886 * i40e_aq_get_link_info
1887 * @hw: pointer to the hw struct
1888 * @enable_lse: enable/disable LinkStatusEvent reporting
1889 * @link: pointer to link status structure - optional
1890 * @cmd_details: pointer to command details structure or NULL
1892 * Returns the link status of the adapter.
1894 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1895 bool enable_lse, struct i40e_link_status *link,
1896 struct i40e_asq_cmd_details *cmd_details)
1898 struct i40e_aq_desc desc;
1899 struct i40e_aqc_get_link_status *resp =
1900 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1901 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1902 enum i40e_status_code status;
1903 bool tx_pause, rx_pause;
1906 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1909 command_flags = I40E_AQ_LSE_ENABLE;
1911 command_flags = I40E_AQ_LSE_DISABLE;
1912 resp->command_flags = CPU_TO_LE16(command_flags);
1914 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1916 if (status != I40E_SUCCESS)
1917 goto aq_get_link_info_exit;
1919 /* save off old link status information */
1920 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1921 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1923 /* update link status */
1924 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1925 hw->phy.media_type = i40e_get_media_type(hw);
1926 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1927 hw_link_info->link_info = resp->link_info;
1928 hw_link_info->an_info = resp->an_info;
1929 hw_link_info->ext_info = resp->ext_info;
1930 hw_link_info->loopback = resp->loopback;
1931 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1932 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1934 /* update fc info */
1935 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1936 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1937 if (tx_pause & rx_pause)
1938 hw->fc.current_mode = I40E_FC_FULL;
1940 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1942 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1944 hw->fc.current_mode = I40E_FC_NONE;
1946 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1947 hw_link_info->crc_enable = true;
1949 hw_link_info->crc_enable = false;
1951 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1952 hw_link_info->lse_enable = true;
1954 hw_link_info->lse_enable = false;
1956 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1957 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1958 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1960 /* save link status information */
1962 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1963 I40E_NONDMA_TO_NONDMA);
1965 /* flag cleared so helper functions don't call AQ again */
1966 hw->phy.get_link_info = false;
1968 aq_get_link_info_exit:
1973 * i40e_aq_set_phy_int_mask
1974 * @hw: pointer to the hw struct
1975 * @mask: interrupt mask to be set
1976 * @cmd_details: pointer to command details structure or NULL
1978 * Set link interrupt mask.
1980 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1982 struct i40e_asq_cmd_details *cmd_details)
1984 struct i40e_aq_desc desc;
1985 struct i40e_aqc_set_phy_int_mask *cmd =
1986 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1987 enum i40e_status_code status;
1989 i40e_fill_default_direct_cmd_desc(&desc,
1990 i40e_aqc_opc_set_phy_int_mask);
1992 cmd->event_mask = CPU_TO_LE16(mask);
1994 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2000 * i40e_aq_get_local_advt_reg
2001 * @hw: pointer to the hw struct
2002 * @advt_reg: local AN advertisement register value
2003 * @cmd_details: pointer to command details structure or NULL
2005 * Get the Local AN advertisement register value.
2007 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2009 struct i40e_asq_cmd_details *cmd_details)
2011 struct i40e_aq_desc desc;
2012 struct i40e_aqc_an_advt_reg *resp =
2013 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2014 enum i40e_status_code status;
2016 i40e_fill_default_direct_cmd_desc(&desc,
2017 i40e_aqc_opc_get_local_advt_reg);
2019 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2021 if (status != I40E_SUCCESS)
2022 goto aq_get_local_advt_reg_exit;
2024 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2025 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2027 aq_get_local_advt_reg_exit:
2032 * i40e_aq_set_local_advt_reg
2033 * @hw: pointer to the hw struct
2034 * @advt_reg: local AN advertisement register value
2035 * @cmd_details: pointer to command details structure or NULL
2037 * Get the Local AN advertisement register value.
2039 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2041 struct i40e_asq_cmd_details *cmd_details)
2043 struct i40e_aq_desc desc;
2044 struct i40e_aqc_an_advt_reg *cmd =
2045 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2046 enum i40e_status_code status;
2048 i40e_fill_default_direct_cmd_desc(&desc,
2049 i40e_aqc_opc_get_local_advt_reg);
2051 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2052 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2054 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2060 * i40e_aq_get_partner_advt
2061 * @hw: pointer to the hw struct
2062 * @advt_reg: AN partner advertisement register value
2063 * @cmd_details: pointer to command details structure or NULL
2065 * Get the link partner AN advertisement register value.
2067 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2069 struct i40e_asq_cmd_details *cmd_details)
2071 struct i40e_aq_desc desc;
2072 struct i40e_aqc_an_advt_reg *resp =
2073 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2074 enum i40e_status_code status;
2076 i40e_fill_default_direct_cmd_desc(&desc,
2077 i40e_aqc_opc_get_partner_advt);
2079 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2081 if (status != I40E_SUCCESS)
2082 goto aq_get_partner_advt_exit;
2084 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2085 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2087 aq_get_partner_advt_exit:
2092 * i40e_aq_set_lb_modes
2093 * @hw: pointer to the hw struct
2094 * @lb_modes: loopback mode to be set
2095 * @cmd_details: pointer to command details structure or NULL
2097 * Sets loopback modes.
2099 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2101 struct i40e_asq_cmd_details *cmd_details)
2103 struct i40e_aq_desc desc;
2104 struct i40e_aqc_set_lb_mode *cmd =
2105 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2106 enum i40e_status_code status;
2108 i40e_fill_default_direct_cmd_desc(&desc,
2109 i40e_aqc_opc_set_lb_modes);
2111 cmd->lb_mode = CPU_TO_LE16(lb_modes);
2113 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2119 * i40e_aq_set_phy_debug
2120 * @hw: pointer to the hw struct
2121 * @cmd_flags: debug command flags
2122 * @cmd_details: pointer to command details structure or NULL
2124 * Reset the external PHY.
2126 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2127 struct i40e_asq_cmd_details *cmd_details)
2129 struct i40e_aq_desc desc;
2130 struct i40e_aqc_set_phy_debug *cmd =
2131 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2132 enum i40e_status_code status;
2134 i40e_fill_default_direct_cmd_desc(&desc,
2135 i40e_aqc_opc_set_phy_debug);
2137 cmd->command_flags = cmd_flags;
2139 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2146 * @hw: pointer to the hw struct
2147 * @vsi_ctx: pointer to a vsi context struct
2148 * @cmd_details: pointer to command details structure or NULL
2150 * Add a VSI context to the hardware.
2152 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2153 struct i40e_vsi_context *vsi_ctx,
2154 struct i40e_asq_cmd_details *cmd_details)
2156 struct i40e_aq_desc desc;
2157 struct i40e_aqc_add_get_update_vsi *cmd =
2158 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2159 struct i40e_aqc_add_get_update_vsi_completion *resp =
2160 (struct i40e_aqc_add_get_update_vsi_completion *)
2162 enum i40e_status_code status;
2164 i40e_fill_default_direct_cmd_desc(&desc,
2165 i40e_aqc_opc_add_vsi);
2167 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2168 cmd->connection_type = vsi_ctx->connection_type;
2169 cmd->vf_id = vsi_ctx->vf_num;
2170 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2172 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2174 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2175 sizeof(vsi_ctx->info), cmd_details);
2177 if (status != I40E_SUCCESS)
2178 goto aq_add_vsi_exit;
2180 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2181 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2182 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2183 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2190 * i40e_aq_set_default_vsi
2191 * @hw: pointer to the hw struct
2193 * @cmd_details: pointer to command details structure or NULL
2195 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2197 struct i40e_asq_cmd_details *cmd_details)
2199 struct i40e_aq_desc desc;
2200 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2201 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2203 enum i40e_status_code status;
2205 i40e_fill_default_direct_cmd_desc(&desc,
2206 i40e_aqc_opc_set_vsi_promiscuous_modes);
2208 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2209 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2210 cmd->seid = CPU_TO_LE16(seid);
2212 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2218 * i40e_aq_clear_default_vsi
2219 * @hw: pointer to the hw struct
2221 * @cmd_details: pointer to command details structure or NULL
2223 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2225 struct i40e_asq_cmd_details *cmd_details)
2227 struct i40e_aq_desc desc;
2228 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2229 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2231 enum i40e_status_code status;
2233 i40e_fill_default_direct_cmd_desc(&desc,
2234 i40e_aqc_opc_set_vsi_promiscuous_modes);
2236 cmd->promiscuous_flags = CPU_TO_LE16(0);
2237 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2238 cmd->seid = CPU_TO_LE16(seid);
2240 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2246 * i40e_aq_set_vsi_unicast_promiscuous
2247 * @hw: pointer to the hw struct
2249 * @set: set unicast promiscuous enable/disable
2250 * @cmd_details: pointer to command details structure or NULL
2251 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2253 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2255 struct i40e_asq_cmd_details *cmd_details,
2256 bool rx_only_promisc)
2258 struct i40e_aq_desc desc;
2259 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2260 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2261 enum i40e_status_code status;
2264 i40e_fill_default_direct_cmd_desc(&desc,
2265 i40e_aqc_opc_set_vsi_promiscuous_modes);
2268 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2269 if (rx_only_promisc &&
2270 (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2271 (hw->aq.api_maj_ver > 1)))
2272 flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2275 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2277 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2278 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2279 (hw->aq.api_maj_ver > 1))
2280 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2282 cmd->seid = CPU_TO_LE16(seid);
2283 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2289 * i40e_aq_set_vsi_multicast_promiscuous
2290 * @hw: pointer to the hw struct
2292 * @set: set multicast promiscuous enable/disable
2293 * @cmd_details: pointer to command details structure or NULL
2295 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2296 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2298 struct i40e_aq_desc desc;
2299 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2300 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2301 enum i40e_status_code status;
2304 i40e_fill_default_direct_cmd_desc(&desc,
2305 i40e_aqc_opc_set_vsi_promiscuous_modes);
2308 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2310 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2312 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2314 cmd->seid = CPU_TO_LE16(seid);
2315 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2321 * i40e_aq_set_vsi_mc_promisc_on_vlan
2322 * @hw: pointer to the hw struct
2324 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2325 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2326 * @cmd_details: pointer to command details structure or NULL
2328 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2329 u16 seid, bool enable, u16 vid,
2330 struct i40e_asq_cmd_details *cmd_details)
2332 struct i40e_aq_desc desc;
2333 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2334 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2335 enum i40e_status_code status;
2338 i40e_fill_default_direct_cmd_desc(&desc,
2339 i40e_aqc_opc_set_vsi_promiscuous_modes);
2342 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2344 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2345 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2346 cmd->seid = CPU_TO_LE16(seid);
2347 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2349 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2355 * i40e_aq_set_vsi_uc_promisc_on_vlan
2356 * @hw: pointer to the hw struct
2358 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2359 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2360 * @cmd_details: pointer to command details structure or NULL
2362 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2363 u16 seid, bool enable, u16 vid,
2364 struct i40e_asq_cmd_details *cmd_details)
2366 struct i40e_aq_desc desc;
2367 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2368 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2369 enum i40e_status_code status;
2372 i40e_fill_default_direct_cmd_desc(&desc,
2373 i40e_aqc_opc_set_vsi_promiscuous_modes);
2376 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2378 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2379 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2380 cmd->seid = CPU_TO_LE16(seid);
2381 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2383 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2389 * i40e_aq_set_vsi_broadcast
2390 * @hw: pointer to the hw struct
2392 * @set_filter: true to set filter, false to clear filter
2393 * @cmd_details: pointer to command details structure or NULL
2395 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2397 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2398 u16 seid, bool set_filter,
2399 struct i40e_asq_cmd_details *cmd_details)
2401 struct i40e_aq_desc desc;
2402 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2403 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2404 enum i40e_status_code status;
2406 i40e_fill_default_direct_cmd_desc(&desc,
2407 i40e_aqc_opc_set_vsi_promiscuous_modes);
2410 cmd->promiscuous_flags
2411 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2413 cmd->promiscuous_flags
2414 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2416 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2417 cmd->seid = CPU_TO_LE16(seid);
2418 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2424 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2425 * @hw: pointer to the hw struct
2427 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2428 * @cmd_details: pointer to command details structure or NULL
2430 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2431 u16 seid, bool enable,
2432 struct i40e_asq_cmd_details *cmd_details)
2434 struct i40e_aq_desc desc;
2435 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2436 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2437 enum i40e_status_code status;
2440 i40e_fill_default_direct_cmd_desc(&desc,
2441 i40e_aqc_opc_set_vsi_promiscuous_modes);
2443 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2445 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2446 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2447 cmd->seid = CPU_TO_LE16(seid);
2449 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2455 * i40e_get_vsi_params - get VSI configuration info
2456 * @hw: pointer to the hw struct
2457 * @vsi_ctx: pointer to a vsi context struct
2458 * @cmd_details: pointer to command details structure or NULL
2460 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2461 struct i40e_vsi_context *vsi_ctx,
2462 struct i40e_asq_cmd_details *cmd_details)
2464 struct i40e_aq_desc desc;
2465 struct i40e_aqc_add_get_update_vsi *cmd =
2466 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2467 struct i40e_aqc_add_get_update_vsi_completion *resp =
2468 (struct i40e_aqc_add_get_update_vsi_completion *)
2470 enum i40e_status_code status;
2472 UNREFERENCED_1PARAMETER(cmd_details);
2473 i40e_fill_default_direct_cmd_desc(&desc,
2474 i40e_aqc_opc_get_vsi_parameters);
2476 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2478 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2480 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2481 sizeof(vsi_ctx->info), NULL);
2483 if (status != I40E_SUCCESS)
2484 goto aq_get_vsi_params_exit;
2486 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2487 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2488 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2489 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2491 aq_get_vsi_params_exit:
2496 * i40e_aq_update_vsi_params
2497 * @hw: pointer to the hw struct
2498 * @vsi_ctx: pointer to a vsi context struct
2499 * @cmd_details: pointer to command details structure or NULL
2501 * Update a VSI context.
2503 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2504 struct i40e_vsi_context *vsi_ctx,
2505 struct i40e_asq_cmd_details *cmd_details)
2507 struct i40e_aq_desc desc;
2508 struct i40e_aqc_add_get_update_vsi *cmd =
2509 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2510 struct i40e_aqc_add_get_update_vsi_completion *resp =
2511 (struct i40e_aqc_add_get_update_vsi_completion *)
2513 enum i40e_status_code status;
2515 i40e_fill_default_direct_cmd_desc(&desc,
2516 i40e_aqc_opc_update_vsi_parameters);
2517 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2519 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2521 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2522 sizeof(vsi_ctx->info), cmd_details);
2524 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2525 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2531 * i40e_aq_get_switch_config
2532 * @hw: pointer to the hardware structure
2533 * @buf: pointer to the result buffer
2534 * @buf_size: length of input buffer
2535 * @start_seid: seid to start for the report, 0 == beginning
2536 * @cmd_details: pointer to command details structure or NULL
2538 * Fill the buf with switch configuration returned from AdminQ command
2540 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2541 struct i40e_aqc_get_switch_config_resp *buf,
2542 u16 buf_size, u16 *start_seid,
2543 struct i40e_asq_cmd_details *cmd_details)
2545 struct i40e_aq_desc desc;
2546 struct i40e_aqc_switch_seid *scfg =
2547 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2548 enum i40e_status_code status;
2550 i40e_fill_default_direct_cmd_desc(&desc,
2551 i40e_aqc_opc_get_switch_config);
2552 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2553 if (buf_size > I40E_AQ_LARGE_BUF)
2554 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2555 scfg->seid = CPU_TO_LE16(*start_seid);
2557 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2558 *start_seid = LE16_TO_CPU(scfg->seid);
2564 * i40e_aq_set_switch_config
2565 * @hw: pointer to the hardware structure
2566 * @flags: bit flag values to set
2567 * @valid_flags: which bit flags to set
2568 * @cmd_details: pointer to command details structure or NULL
2570 * Set switch configuration bits
2572 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2573 u16 flags, u16 valid_flags,
2574 struct i40e_asq_cmd_details *cmd_details)
2576 struct i40e_aq_desc desc;
2577 struct i40e_aqc_set_switch_config *scfg =
2578 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2579 enum i40e_status_code status;
2581 i40e_fill_default_direct_cmd_desc(&desc,
2582 i40e_aqc_opc_set_switch_config);
2583 scfg->flags = CPU_TO_LE16(flags);
2584 scfg->valid_flags = CPU_TO_LE16(valid_flags);
2586 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2592 * i40e_aq_get_firmware_version
2593 * @hw: pointer to the hw struct
2594 * @fw_major_version: firmware major version
2595 * @fw_minor_version: firmware minor version
2596 * @fw_build: firmware build number
2597 * @api_major_version: major queue version
2598 * @api_minor_version: minor queue version
2599 * @cmd_details: pointer to command details structure or NULL
2601 * Get the firmware version from the admin queue commands
2603 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2604 u16 *fw_major_version, u16 *fw_minor_version,
2606 u16 *api_major_version, u16 *api_minor_version,
2607 struct i40e_asq_cmd_details *cmd_details)
2609 struct i40e_aq_desc desc;
2610 struct i40e_aqc_get_version *resp =
2611 (struct i40e_aqc_get_version *)&desc.params.raw;
2612 enum i40e_status_code status;
2614 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2616 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2618 if (status == I40E_SUCCESS) {
2619 if (fw_major_version != NULL)
2620 *fw_major_version = LE16_TO_CPU(resp->fw_major);
2621 if (fw_minor_version != NULL)
2622 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2623 if (fw_build != NULL)
2624 *fw_build = LE32_TO_CPU(resp->fw_build);
2625 if (api_major_version != NULL)
2626 *api_major_version = LE16_TO_CPU(resp->api_major);
2627 if (api_minor_version != NULL)
2628 *api_minor_version = LE16_TO_CPU(resp->api_minor);
2630 /* A workaround to fix the API version in SW */
2631 if (api_major_version && api_minor_version &&
2632 fw_major_version && fw_minor_version &&
2633 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2634 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2635 (*fw_major_version > 4)))
2636 *api_minor_version = 2;
2643 * i40e_aq_send_driver_version
2644 * @hw: pointer to the hw struct
2645 * @dv: driver's major, minor version
2646 * @cmd_details: pointer to command details structure or NULL
2648 * Send the driver version to the firmware
2650 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2651 struct i40e_driver_version *dv,
2652 struct i40e_asq_cmd_details *cmd_details)
2654 struct i40e_aq_desc desc;
2655 struct i40e_aqc_driver_version *cmd =
2656 (struct i40e_aqc_driver_version *)&desc.params.raw;
2657 enum i40e_status_code status;
2661 return I40E_ERR_PARAM;
2663 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2665 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2666 cmd->driver_major_ver = dv->major_version;
2667 cmd->driver_minor_ver = dv->minor_version;
2668 cmd->driver_build_ver = dv->build_version;
2669 cmd->driver_subbuild_ver = dv->subbuild_version;
2672 while (len < sizeof(dv->driver_string) &&
2673 (dv->driver_string[len] < 0x80) &&
2674 dv->driver_string[len])
2676 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2683 * i40e_get_link_status - get status of the HW network link
2684 * @hw: pointer to the hw struct
2685 * @link_up: pointer to bool (true/false = linkup/linkdown)
2687 * Variable link_up true if link is up, false if link is down.
2688 * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2690 * Side effect: LinkStatusEvent reporting becomes enabled
2692 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2694 enum i40e_status_code status = I40E_SUCCESS;
2696 if (hw->phy.get_link_info) {
2697 status = i40e_update_link_info(hw);
2699 if (status != I40E_SUCCESS)
2700 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2704 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2710 * i40e_updatelink_status - update status of the HW network link
2711 * @hw: pointer to the hw struct
2713 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2715 struct i40e_aq_get_phy_abilities_resp abilities;
2716 enum i40e_status_code status = I40E_SUCCESS;
2718 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2722 if (hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) {
2723 status = i40e_aq_get_phy_capabilities(hw, false, false,
2728 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2729 sizeof(hw->phy.link_info.module_type));
2736 * i40e_get_link_speed
2737 * @hw: pointer to the hw struct
2739 * Returns the link speed of the adapter.
2741 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2743 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2744 enum i40e_status_code status = I40E_SUCCESS;
2746 if (hw->phy.get_link_info) {
2747 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2749 if (status != I40E_SUCCESS)
2750 goto i40e_link_speed_exit;
2753 speed = hw->phy.link_info.link_speed;
2755 i40e_link_speed_exit:
2760 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2761 * @hw: pointer to the hw struct
2762 * @uplink_seid: the MAC or other gizmo SEID
2763 * @downlink_seid: the VSI SEID
2764 * @enabled_tc: bitmap of TCs to be enabled
2765 * @default_port: true for default port VSI, false for control port
2766 * @veb_seid: pointer to where to put the resulting VEB SEID
2767 * @enable_stats: true to turn on VEB stats
2768 * @cmd_details: pointer to command details structure or NULL
2770 * This asks the FW to add a VEB between the uplink and downlink
2771 * elements. If the uplink SEID is 0, this will be a floating VEB.
2773 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2774 u16 downlink_seid, u8 enabled_tc,
2775 bool default_port, u16 *veb_seid,
2777 struct i40e_asq_cmd_details *cmd_details)
2779 struct i40e_aq_desc desc;
2780 struct i40e_aqc_add_veb *cmd =
2781 (struct i40e_aqc_add_veb *)&desc.params.raw;
2782 struct i40e_aqc_add_veb_completion *resp =
2783 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2784 enum i40e_status_code status;
2787 /* SEIDs need to either both be set or both be 0 for floating VEB */
2788 if (!!uplink_seid != !!downlink_seid)
2789 return I40E_ERR_PARAM;
2791 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2793 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2794 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2795 cmd->enable_tcs = enabled_tc;
2797 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2799 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2801 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2803 /* reverse logic here: set the bitflag to disable the stats */
2805 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2807 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2809 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2811 if (!status && veb_seid)
2812 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2818 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2819 * @hw: pointer to the hw struct
2820 * @veb_seid: the SEID of the VEB to query
2821 * @switch_id: the uplink switch id
2822 * @floating: set to true if the VEB is floating
2823 * @statistic_index: index of the stats counter block for this VEB
2824 * @vebs_used: number of VEB's used by function
2825 * @vebs_free: total VEB's not reserved by any function
2826 * @cmd_details: pointer to command details structure or NULL
2828 * This retrieves the parameters for a particular VEB, specified by
2829 * uplink_seid, and returns them to the caller.
2831 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2832 u16 veb_seid, u16 *switch_id,
2833 bool *floating, u16 *statistic_index,
2834 u16 *vebs_used, u16 *vebs_free,
2835 struct i40e_asq_cmd_details *cmd_details)
2837 struct i40e_aq_desc desc;
2838 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2839 (struct i40e_aqc_get_veb_parameters_completion *)
2841 enum i40e_status_code status;
2844 return I40E_ERR_PARAM;
2846 i40e_fill_default_direct_cmd_desc(&desc,
2847 i40e_aqc_opc_get_veb_parameters);
2848 cmd_resp->seid = CPU_TO_LE16(veb_seid);
2850 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2855 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2856 if (statistic_index)
2857 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2859 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2861 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2863 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2865 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2876 * i40e_aq_add_macvlan
2877 * @hw: pointer to the hw struct
2878 * @seid: VSI for the mac address
2879 * @mv_list: list of macvlans to be added
2880 * @count: length of the list
2881 * @cmd_details: pointer to command details structure or NULL
2883 * Add MAC/VLAN addresses to the HW filtering
2885 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2886 struct i40e_aqc_add_macvlan_element_data *mv_list,
2887 u16 count, struct i40e_asq_cmd_details *cmd_details)
2889 struct i40e_aq_desc desc;
2890 struct i40e_aqc_macvlan *cmd =
2891 (struct i40e_aqc_macvlan *)&desc.params.raw;
2892 enum i40e_status_code status;
2896 if (count == 0 || !mv_list || !hw)
2897 return I40E_ERR_PARAM;
2899 buf_size = count * sizeof(*mv_list);
2901 /* prep the rest of the request */
2902 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2903 cmd->num_addresses = CPU_TO_LE16(count);
2904 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2908 for (i = 0; i < count; i++)
2909 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
2911 CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2913 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2914 if (buf_size > I40E_AQ_LARGE_BUF)
2915 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2917 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2924 * i40e_aq_remove_macvlan
2925 * @hw: pointer to the hw struct
2926 * @seid: VSI for the mac address
2927 * @mv_list: list of macvlans to be removed
2928 * @count: length of the list
2929 * @cmd_details: pointer to command details structure or NULL
2931 * Remove MAC/VLAN addresses from the HW filtering
2933 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2934 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2935 u16 count, struct i40e_asq_cmd_details *cmd_details)
2937 struct i40e_aq_desc desc;
2938 struct i40e_aqc_macvlan *cmd =
2939 (struct i40e_aqc_macvlan *)&desc.params.raw;
2940 enum i40e_status_code status;
2943 if (count == 0 || !mv_list || !hw)
2944 return I40E_ERR_PARAM;
2946 buf_size = count * sizeof(*mv_list);
2948 /* prep the rest of the request */
2949 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2950 cmd->num_addresses = CPU_TO_LE16(count);
2951 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2955 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2956 if (buf_size > I40E_AQ_LARGE_BUF)
2957 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2959 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2966 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
2967 * @hw: pointer to the hw struct
2968 * @opcode: AQ opcode for add or delete mirror rule
2969 * @sw_seid: Switch SEID (to which rule refers)
2970 * @rule_type: Rule Type (ingress/egress/VLAN)
2971 * @id: Destination VSI SEID or Rule ID
2972 * @count: length of the list
2973 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2974 * @cmd_details: pointer to command details structure or NULL
2975 * @rule_id: Rule ID returned from FW
2976 * @rule_used: Number of rules used in internal switch
2977 * @rule_free: Number of rules free in internal switch
2979 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
2980 * VEBs/VEPA elements only
2982 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
2983 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
2984 u16 count, __le16 *mr_list,
2985 struct i40e_asq_cmd_details *cmd_details,
2986 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2988 struct i40e_aq_desc desc;
2989 struct i40e_aqc_add_delete_mirror_rule *cmd =
2990 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
2991 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
2992 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
2993 enum i40e_status_code status;
2996 buf_size = count * sizeof(*mr_list);
2998 /* prep the rest of the request */
2999 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3000 cmd->seid = CPU_TO_LE16(sw_seid);
3001 cmd->rule_type = CPU_TO_LE16(rule_type &
3002 I40E_AQC_MIRROR_RULE_TYPE_MASK);
3003 cmd->num_entries = CPU_TO_LE16(count);
3004 /* Dest VSI for add, rule_id for delete */
3005 cmd->destination = CPU_TO_LE16(id);
3007 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3009 if (buf_size > I40E_AQ_LARGE_BUF)
3010 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3013 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3015 if (status == I40E_SUCCESS ||
3016 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3018 *rule_id = LE16_TO_CPU(resp->rule_id);
3020 *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3022 *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3028 * i40e_aq_add_mirrorrule - add a mirror rule
3029 * @hw: pointer to the hw struct
3030 * @sw_seid: Switch SEID (to which rule refers)
3031 * @rule_type: Rule Type (ingress/egress/VLAN)
3032 * @dest_vsi: SEID of VSI to which packets will be mirrored
3033 * @count: length of the list
3034 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3035 * @cmd_details: pointer to command details structure or NULL
3036 * @rule_id: Rule ID returned from FW
3037 * @rule_used: Number of rules used in internal switch
3038 * @rule_free: Number of rules free in internal switch
3040 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3042 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3043 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3044 struct i40e_asq_cmd_details *cmd_details,
3045 u16 *rule_id, u16 *rules_used, u16 *rules_free)
3047 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3048 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3049 if (count == 0 || !mr_list)
3050 return I40E_ERR_PARAM;
3053 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3054 rule_type, dest_vsi, count, mr_list,
3055 cmd_details, rule_id, rules_used, rules_free);
3059 * i40e_aq_delete_mirrorrule - delete a mirror rule
3060 * @hw: pointer to the hw struct
3061 * @sw_seid: Switch SEID (to which rule refers)
3062 * @rule_type: Rule Type (ingress/egress/VLAN)
3063 * @count: length of the list
3064 * @rule_id: Rule ID that is returned in the receive desc as part of
3066 * @mr_list: list of mirrored VLAN IDs to be removed
3067 * @cmd_details: pointer to command details structure or NULL
3068 * @rule_used: Number of rules used in internal switch
3069 * @rule_free: Number of rules free in internal switch
3071 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3073 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3074 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3075 struct i40e_asq_cmd_details *cmd_details,
3076 u16 *rules_used, u16 *rules_free)
3078 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3079 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3080 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3081 * mirroring. For other rule_type, count and rule_type should
3084 if (count == 0 || !mr_list)
3085 return I40E_ERR_PARAM;
3088 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3089 rule_type, rule_id, count, mr_list,
3090 cmd_details, NULL, rules_used, rules_free);
3094 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3095 * @hw: pointer to the hw struct
3096 * @seid: VSI for the vlan filters
3097 * @v_list: list of vlan filters to be added
3098 * @count: length of the list
3099 * @cmd_details: pointer to command details structure or NULL
3101 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3102 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3103 u8 count, struct i40e_asq_cmd_details *cmd_details)
3105 struct i40e_aq_desc desc;
3106 struct i40e_aqc_macvlan *cmd =
3107 (struct i40e_aqc_macvlan *)&desc.params.raw;
3108 enum i40e_status_code status;
3111 if (count == 0 || !v_list || !hw)
3112 return I40E_ERR_PARAM;
3114 buf_size = count * sizeof(*v_list);
3116 /* prep the rest of the request */
3117 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3118 cmd->num_addresses = CPU_TO_LE16(count);
3119 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3123 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3124 if (buf_size > I40E_AQ_LARGE_BUF)
3125 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3127 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3134 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3135 * @hw: pointer to the hw struct
3136 * @seid: VSI for the vlan filters
3137 * @v_list: list of macvlans to be removed
3138 * @count: length of the list
3139 * @cmd_details: pointer to command details structure or NULL
3141 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3142 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3143 u8 count, struct i40e_asq_cmd_details *cmd_details)
3145 struct i40e_aq_desc desc;
3146 struct i40e_aqc_macvlan *cmd =
3147 (struct i40e_aqc_macvlan *)&desc.params.raw;
3148 enum i40e_status_code status;
3151 if (count == 0 || !v_list || !hw)
3152 return I40E_ERR_PARAM;
3154 buf_size = count * sizeof(*v_list);
3156 /* prep the rest of the request */
3157 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3158 cmd->num_addresses = CPU_TO_LE16(count);
3159 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3163 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3164 if (buf_size > I40E_AQ_LARGE_BUF)
3165 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3167 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3174 * i40e_aq_send_msg_to_vf
3175 * @hw: pointer to the hardware structure
3176 * @vfid: vf id to send msg
3177 * @v_opcode: opcodes for VF-PF communication
3178 * @v_retval: return error code
3179 * @msg: pointer to the msg buffer
3180 * @msglen: msg length
3181 * @cmd_details: pointer to command details
3185 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3186 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3187 struct i40e_asq_cmd_details *cmd_details)
3189 struct i40e_aq_desc desc;
3190 struct i40e_aqc_pf_vf_message *cmd =
3191 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3192 enum i40e_status_code status;
3194 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3195 cmd->id = CPU_TO_LE32(vfid);
3196 desc.cookie_high = CPU_TO_LE32(v_opcode);
3197 desc.cookie_low = CPU_TO_LE32(v_retval);
3198 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3200 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3202 if (msglen > I40E_AQ_LARGE_BUF)
3203 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3204 desc.datalen = CPU_TO_LE16(msglen);
3206 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3212 * i40e_aq_debug_read_register
3213 * @hw: pointer to the hw struct
3214 * @reg_addr: register address
3215 * @reg_val: register value
3216 * @cmd_details: pointer to command details structure or NULL
3218 * Read the register using the admin queue commands
3220 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3221 u32 reg_addr, u64 *reg_val,
3222 struct i40e_asq_cmd_details *cmd_details)
3224 struct i40e_aq_desc desc;
3225 struct i40e_aqc_debug_reg_read_write *cmd_resp =
3226 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3227 enum i40e_status_code status;
3229 if (reg_val == NULL)
3230 return I40E_ERR_PARAM;
3232 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3234 cmd_resp->address = CPU_TO_LE32(reg_addr);
3236 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3238 if (status == I40E_SUCCESS) {
3239 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3240 (u64)LE32_TO_CPU(cmd_resp->value_low);
3247 * i40e_aq_debug_write_register
3248 * @hw: pointer to the hw struct
3249 * @reg_addr: register address
3250 * @reg_val: register value
3251 * @cmd_details: pointer to command details structure or NULL
3253 * Write to a register using the admin queue commands
3255 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3256 u32 reg_addr, u64 reg_val,
3257 struct i40e_asq_cmd_details *cmd_details)
3259 struct i40e_aq_desc desc;
3260 struct i40e_aqc_debug_reg_read_write *cmd =
3261 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3262 enum i40e_status_code status;
3264 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3266 cmd->address = CPU_TO_LE32(reg_addr);
3267 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3268 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3270 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3276 * i40e_aq_request_resource
3277 * @hw: pointer to the hw struct
3278 * @resource: resource id
3279 * @access: access type
3280 * @sdp_number: resource number
3281 * @timeout: the maximum time in ms that the driver may hold the resource
3282 * @cmd_details: pointer to command details structure or NULL
3284 * requests common resource using the admin queue commands
3286 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3287 enum i40e_aq_resources_ids resource,
3288 enum i40e_aq_resource_access_type access,
3289 u8 sdp_number, u64 *timeout,
3290 struct i40e_asq_cmd_details *cmd_details)
3292 struct i40e_aq_desc desc;
3293 struct i40e_aqc_request_resource *cmd_resp =
3294 (struct i40e_aqc_request_resource *)&desc.params.raw;
3295 enum i40e_status_code status;
3297 DEBUGFUNC("i40e_aq_request_resource");
3299 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3301 cmd_resp->resource_id = CPU_TO_LE16(resource);
3302 cmd_resp->access_type = CPU_TO_LE16(access);
3303 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3305 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3306 /* The completion specifies the maximum time in ms that the driver
3307 * may hold the resource in the Timeout field.
3308 * If the resource is held by someone else, the command completes with
3309 * busy return value and the timeout field indicates the maximum time
3310 * the current owner of the resource has to free it.
3312 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3313 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3319 * i40e_aq_release_resource
3320 * @hw: pointer to the hw struct
3321 * @resource: resource id
3322 * @sdp_number: resource number
3323 * @cmd_details: pointer to command details structure or NULL
3325 * release common resource using the admin queue commands
3327 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3328 enum i40e_aq_resources_ids resource,
3330 struct i40e_asq_cmd_details *cmd_details)
3332 struct i40e_aq_desc desc;
3333 struct i40e_aqc_request_resource *cmd =
3334 (struct i40e_aqc_request_resource *)&desc.params.raw;
3335 enum i40e_status_code status;
3337 DEBUGFUNC("i40e_aq_release_resource");
3339 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3341 cmd->resource_id = CPU_TO_LE16(resource);
3342 cmd->resource_number = CPU_TO_LE32(sdp_number);
3344 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3351 * @hw: pointer to the hw struct
3352 * @module_pointer: module pointer location in words from the NVM beginning
3353 * @offset: byte offset from the module beginning
3354 * @length: length of the section to be read (in bytes from the offset)
3355 * @data: command buffer (size [bytes] = length)
3356 * @last_command: tells if this is the last command in a series
3357 * @cmd_details: pointer to command details structure or NULL
3359 * Read the NVM using the admin queue commands
3361 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3362 u32 offset, u16 length, void *data,
3364 struct i40e_asq_cmd_details *cmd_details)
3366 struct i40e_aq_desc desc;
3367 struct i40e_aqc_nvm_update *cmd =
3368 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3369 enum i40e_status_code status;
3371 DEBUGFUNC("i40e_aq_read_nvm");
3373 /* In offset the highest byte must be zeroed. */
3374 if (offset & 0xFF000000) {
3375 status = I40E_ERR_PARAM;
3376 goto i40e_aq_read_nvm_exit;
3379 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3381 /* If this is the last command in a series, set the proper flag. */
3383 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3384 cmd->module_pointer = module_pointer;
3385 cmd->offset = CPU_TO_LE32(offset);
3386 cmd->length = CPU_TO_LE16(length);
3388 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3389 if (length > I40E_AQ_LARGE_BUF)
3390 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3392 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3394 i40e_aq_read_nvm_exit:
3399 * i40e_aq_read_nvm_config - read an nvm config block
3400 * @hw: pointer to the hw struct
3401 * @cmd_flags: NVM access admin command bits
3402 * @field_id: field or feature id
3403 * @data: buffer for result
3404 * @buf_size: buffer size
3405 * @element_count: pointer to count of elements read by FW
3406 * @cmd_details: pointer to command details structure or NULL
3408 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3409 u8 cmd_flags, u32 field_id, void *data,
3410 u16 buf_size, u16 *element_count,
3411 struct i40e_asq_cmd_details *cmd_details)
3413 struct i40e_aq_desc desc;
3414 struct i40e_aqc_nvm_config_read *cmd =
3415 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3416 enum i40e_status_code status;
3418 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3419 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3420 if (buf_size > I40E_AQ_LARGE_BUF)
3421 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3423 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3424 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3425 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3426 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3428 cmd->element_id_msw = 0;
3430 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3432 if (!status && element_count)
3433 *element_count = LE16_TO_CPU(cmd->element_count);
3439 * i40e_aq_write_nvm_config - write an nvm config block
3440 * @hw: pointer to the hw struct
3441 * @cmd_flags: NVM access admin command bits
3442 * @data: buffer for result
3443 * @buf_size: buffer size
3444 * @element_count: count of elements to be written
3445 * @cmd_details: pointer to command details structure or NULL
3447 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3448 u8 cmd_flags, void *data, u16 buf_size,
3450 struct i40e_asq_cmd_details *cmd_details)
3452 struct i40e_aq_desc desc;
3453 struct i40e_aqc_nvm_config_write *cmd =
3454 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3455 enum i40e_status_code status;
3457 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3458 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3459 if (buf_size > I40E_AQ_LARGE_BUF)
3460 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3462 cmd->element_count = CPU_TO_LE16(element_count);
3463 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3464 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3470 * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3471 * @hw: pointer to the hw struct
3472 * @cmd_details: pointer to command details structure or NULL
3474 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3475 void *buff, u16 buff_size,
3476 struct i40e_asq_cmd_details *cmd_details)
3478 struct i40e_aq_desc desc;
3479 enum i40e_status_code status;
3481 UNREFERENCED_2PARAMETER(buff, buff_size);
3483 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3484 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3485 if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3486 status = I40E_ERR_NOT_IMPLEMENTED;
3493 * @hw: pointer to the hw struct
3494 * @module_pointer: module pointer location in words from the NVM beginning
3495 * @offset: offset in the module (expressed in 4 KB from module's beginning)
3496 * @length: length of the section to be erased (expressed in 4 KB)
3497 * @last_command: tells if this is the last command in a series
3498 * @cmd_details: pointer to command details structure or NULL
3500 * Erase the NVM sector using the admin queue commands
3502 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3503 u32 offset, u16 length, bool last_command,
3504 struct i40e_asq_cmd_details *cmd_details)
3506 struct i40e_aq_desc desc;
3507 struct i40e_aqc_nvm_update *cmd =
3508 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3509 enum i40e_status_code status;
3511 DEBUGFUNC("i40e_aq_erase_nvm");
3513 /* In offset the highest byte must be zeroed. */
3514 if (offset & 0xFF000000) {
3515 status = I40E_ERR_PARAM;
3516 goto i40e_aq_erase_nvm_exit;
3519 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3521 /* If this is the last command in a series, set the proper flag. */
3523 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3524 cmd->module_pointer = module_pointer;
3525 cmd->offset = CPU_TO_LE32(offset);
3526 cmd->length = CPU_TO_LE16(length);
3528 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3530 i40e_aq_erase_nvm_exit:
3535 * i40e_parse_discover_capabilities
3536 * @hw: pointer to the hw struct
3537 * @buff: pointer to a buffer containing device/function capability records
3538 * @cap_count: number of capability records in the list
3539 * @list_type_opc: type of capabilities list to parse
3541 * Parse the device/function capabilities list.
3543 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3545 enum i40e_admin_queue_opc list_type_opc)
3547 struct i40e_aqc_list_capabilities_element_resp *cap;
3548 u32 valid_functions, num_functions;
3549 u32 number, logical_id, phys_id;
3550 struct i40e_hw_capabilities *p;
3555 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3557 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3558 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3559 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3560 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3564 for (i = 0; i < cap_count; i++, cap++) {
3565 id = LE16_TO_CPU(cap->id);
3566 number = LE32_TO_CPU(cap->number);
3567 logical_id = LE32_TO_CPU(cap->logical_id);
3568 phys_id = LE32_TO_CPU(cap->phys_id);
3569 major_rev = cap->major_rev;
3572 case I40E_AQ_CAP_ID_SWITCH_MODE:
3573 p->switch_mode = number;
3574 i40e_debug(hw, I40E_DEBUG_INIT,
3575 "HW Capability: Switch mode = %d\n",
3578 case I40E_AQ_CAP_ID_MNG_MODE:
3579 p->management_mode = number;
3580 i40e_debug(hw, I40E_DEBUG_INIT,
3581 "HW Capability: Management Mode = %d\n",
3582 p->management_mode);
3584 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3585 p->npar_enable = number;
3586 i40e_debug(hw, I40E_DEBUG_INIT,
3587 "HW Capability: NPAR enable = %d\n",
3590 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3592 i40e_debug(hw, I40E_DEBUG_INIT,
3593 "HW Capability: OS2BMC = %d\n", p->os2bmc);
3595 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3596 p->valid_functions = number;
3597 i40e_debug(hw, I40E_DEBUG_INIT,
3598 "HW Capability: Valid Functions = %d\n",
3599 p->valid_functions);
3601 case I40E_AQ_CAP_ID_SRIOV:
3603 p->sr_iov_1_1 = true;
3604 i40e_debug(hw, I40E_DEBUG_INIT,
3605 "HW Capability: SR-IOV = %d\n",
3608 case I40E_AQ_CAP_ID_VF:
3609 p->num_vfs = number;
3610 p->vf_base_id = logical_id;
3611 i40e_debug(hw, I40E_DEBUG_INIT,
3612 "HW Capability: VF count = %d\n",
3614 i40e_debug(hw, I40E_DEBUG_INIT,
3615 "HW Capability: VF base_id = %d\n",
3618 case I40E_AQ_CAP_ID_VMDQ:
3621 i40e_debug(hw, I40E_DEBUG_INIT,
3622 "HW Capability: VMDQ = %d\n", p->vmdq);
3624 case I40E_AQ_CAP_ID_8021QBG:
3626 p->evb_802_1_qbg = true;
3627 i40e_debug(hw, I40E_DEBUG_INIT,
3628 "HW Capability: 802.1Qbg = %d\n", number);
3630 case I40E_AQ_CAP_ID_8021QBR:
3632 p->evb_802_1_qbh = true;
3633 i40e_debug(hw, I40E_DEBUG_INIT,
3634 "HW Capability: 802.1Qbh = %d\n", number);
3636 case I40E_AQ_CAP_ID_VSI:
3637 p->num_vsis = number;
3638 i40e_debug(hw, I40E_DEBUG_INIT,
3639 "HW Capability: VSI count = %d\n",
3642 case I40E_AQ_CAP_ID_DCB:
3645 p->enabled_tcmap = logical_id;
3648 i40e_debug(hw, I40E_DEBUG_INIT,
3649 "HW Capability: DCB = %d\n", p->dcb);
3650 i40e_debug(hw, I40E_DEBUG_INIT,
3651 "HW Capability: TC Mapping = %d\n",
3653 i40e_debug(hw, I40E_DEBUG_INIT,
3654 "HW Capability: TC Max = %d\n", p->maxtc);
3656 case I40E_AQ_CAP_ID_FCOE:
3659 i40e_debug(hw, I40E_DEBUG_INIT,
3660 "HW Capability: FCOE = %d\n", p->fcoe);
3662 case I40E_AQ_CAP_ID_ISCSI:
3665 i40e_debug(hw, I40E_DEBUG_INIT,
3666 "HW Capability: iSCSI = %d\n", p->iscsi);
3668 case I40E_AQ_CAP_ID_RSS:
3670 p->rss_table_size = number;
3671 p->rss_table_entry_width = logical_id;
3672 i40e_debug(hw, I40E_DEBUG_INIT,
3673 "HW Capability: RSS = %d\n", p->rss);
3674 i40e_debug(hw, I40E_DEBUG_INIT,
3675 "HW Capability: RSS table size = %d\n",
3677 i40e_debug(hw, I40E_DEBUG_INIT,
3678 "HW Capability: RSS table width = %d\n",
3679 p->rss_table_entry_width);
3681 case I40E_AQ_CAP_ID_RXQ:
3682 p->num_rx_qp = number;
3683 p->base_queue = phys_id;
3684 i40e_debug(hw, I40E_DEBUG_INIT,
3685 "HW Capability: Rx QP = %d\n", number);
3686 i40e_debug(hw, I40E_DEBUG_INIT,
3687 "HW Capability: base_queue = %d\n",
3690 case I40E_AQ_CAP_ID_TXQ:
3691 p->num_tx_qp = number;
3692 p->base_queue = phys_id;
3693 i40e_debug(hw, I40E_DEBUG_INIT,
3694 "HW Capability: Tx QP = %d\n", number);
3695 i40e_debug(hw, I40E_DEBUG_INIT,
3696 "HW Capability: base_queue = %d\n",
3699 case I40E_AQ_CAP_ID_MSIX:
3700 p->num_msix_vectors = number;
3701 i40e_debug(hw, I40E_DEBUG_INIT,
3702 "HW Capability: MSIX vector count = %d\n",
3703 p->num_msix_vectors);
3705 case I40E_AQ_CAP_ID_VF_MSIX:
3706 p->num_msix_vectors_vf = number;
3707 i40e_debug(hw, I40E_DEBUG_INIT,
3708 "HW Capability: MSIX VF vector count = %d\n",
3709 p->num_msix_vectors_vf);
3711 case I40E_AQ_CAP_ID_FLEX10:
3712 if (major_rev == 1) {
3714 p->flex10_enable = true;
3715 p->flex10_capable = true;
3718 /* Capability revision >= 2 */
3720 p->flex10_enable = true;
3722 p->flex10_capable = true;
3724 p->flex10_mode = logical_id;
3725 p->flex10_status = phys_id;
3726 i40e_debug(hw, I40E_DEBUG_INIT,
3727 "HW Capability: Flex10 mode = %d\n",
3729 i40e_debug(hw, I40E_DEBUG_INIT,
3730 "HW Capability: Flex10 status = %d\n",
3733 case I40E_AQ_CAP_ID_CEM:
3736 i40e_debug(hw, I40E_DEBUG_INIT,
3737 "HW Capability: CEM = %d\n", p->mgmt_cem);
3739 case I40E_AQ_CAP_ID_IWARP:
3742 i40e_debug(hw, I40E_DEBUG_INIT,
3743 "HW Capability: iWARP = %d\n", p->iwarp);
3745 case I40E_AQ_CAP_ID_LED:
3746 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3747 p->led[phys_id] = true;
3748 i40e_debug(hw, I40E_DEBUG_INIT,
3749 "HW Capability: LED - PIN %d\n", phys_id);
3751 case I40E_AQ_CAP_ID_SDP:
3752 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3753 p->sdp[phys_id] = true;
3754 i40e_debug(hw, I40E_DEBUG_INIT,
3755 "HW Capability: SDP - PIN %d\n", phys_id);
3757 case I40E_AQ_CAP_ID_MDIO:
3759 p->mdio_port_num = phys_id;
3760 p->mdio_port_mode = logical_id;
3762 i40e_debug(hw, I40E_DEBUG_INIT,
3763 "HW Capability: MDIO port number = %d\n",
3765 i40e_debug(hw, I40E_DEBUG_INIT,
3766 "HW Capability: MDIO port mode = %d\n",
3769 case I40E_AQ_CAP_ID_1588:
3771 p->ieee_1588 = true;
3772 i40e_debug(hw, I40E_DEBUG_INIT,
3773 "HW Capability: IEEE 1588 = %d\n",
3776 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3778 p->fd_filters_guaranteed = number;
3779 p->fd_filters_best_effort = logical_id;
3780 i40e_debug(hw, I40E_DEBUG_INIT,
3781 "HW Capability: Flow Director = 1\n");
3782 i40e_debug(hw, I40E_DEBUG_INIT,
3783 "HW Capability: Guaranteed FD filters = %d\n",
3784 p->fd_filters_guaranteed);
3786 case I40E_AQ_CAP_ID_WSR_PROT:
3787 p->wr_csr_prot = (u64)number;
3788 p->wr_csr_prot |= (u64)logical_id << 32;
3789 i40e_debug(hw, I40E_DEBUG_INIT,
3790 "HW Capability: wr_csr_prot = 0x%llX\n\n",
3791 (p->wr_csr_prot & 0xffff));
3793 case I40E_AQ_CAP_ID_NVM_MGMT:
3794 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3795 p->sec_rev_disabled = true;
3796 if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3797 p->update_disabled = true;
3800 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3801 hw->num_wol_proxy_filters = (u16)number;
3802 hw->wol_proxy_vsi_seid = (u16)logical_id;
3803 p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3804 if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3805 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3807 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3808 p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3809 p->proxy_support = p->proxy_support;
3810 i40e_debug(hw, I40E_DEBUG_INIT,
3811 "HW Capability: WOL proxy filters = %d\n",
3812 hw->num_wol_proxy_filters);
3821 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3823 #ifdef I40E_FCOE_ENA
3824 /* Software override ensuring FCoE is disabled if npar or mfp
3825 * mode because it is not supported in these modes.
3827 if (p->npar_enable || p->flex10_enable)
3830 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3834 /* count the enabled ports (aka the "not disabled" ports) */
3836 for (i = 0; i < 4; i++) {
3837 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3840 /* use AQ read to get the physical register offset instead
3841 * of the port relative offset
3843 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3844 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3848 valid_functions = p->valid_functions;
3850 while (valid_functions) {
3851 if (valid_functions & 1)
3853 valid_functions >>= 1;
3856 /* partition id is 1-based, and functions are evenly spread
3857 * across the ports as partitions
3859 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3860 hw->num_partitions = num_functions / hw->num_ports;
3862 /* additional HW specific goodies that might
3863 * someday be HW version specific
3865 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3869 * i40e_aq_discover_capabilities
3870 * @hw: pointer to the hw struct
3871 * @buff: a virtual buffer to hold the capabilities
3872 * @buff_size: Size of the virtual buffer
3873 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3874 * @list_type_opc: capabilities type to discover - pass in the command opcode
3875 * @cmd_details: pointer to command details structure or NULL
3877 * Get the device capabilities descriptions from the firmware
3879 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3880 void *buff, u16 buff_size, u16 *data_size,
3881 enum i40e_admin_queue_opc list_type_opc,
3882 struct i40e_asq_cmd_details *cmd_details)
3884 struct i40e_aqc_list_capabilites *cmd;
3885 struct i40e_aq_desc desc;
3886 enum i40e_status_code status = I40E_SUCCESS;
3888 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3890 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3891 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3892 status = I40E_ERR_PARAM;
3896 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3898 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3899 if (buff_size > I40E_AQ_LARGE_BUF)
3900 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3902 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3903 *data_size = LE16_TO_CPU(desc.datalen);
3908 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3916 * i40e_aq_update_nvm
3917 * @hw: pointer to the hw struct
3918 * @module_pointer: module pointer location in words from the NVM beginning
3919 * @offset: byte offset from the module beginning
3920 * @length: length of the section to be written (in bytes from the offset)
3921 * @data: command buffer (size [bytes] = length)
3922 * @last_command: tells if this is the last command in a series
3923 * @cmd_details: pointer to command details structure or NULL
3925 * Update the NVM using the admin queue commands
3927 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3928 u32 offset, u16 length, void *data,
3930 struct i40e_asq_cmd_details *cmd_details)
3932 struct i40e_aq_desc desc;
3933 struct i40e_aqc_nvm_update *cmd =
3934 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3935 enum i40e_status_code status;
3937 DEBUGFUNC("i40e_aq_update_nvm");
3939 /* In offset the highest byte must be zeroed. */
3940 if (offset & 0xFF000000) {
3941 status = I40E_ERR_PARAM;
3942 goto i40e_aq_update_nvm_exit;
3945 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3947 /* If this is the last command in a series, set the proper flag. */
3949 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3950 cmd->module_pointer = module_pointer;
3951 cmd->offset = CPU_TO_LE32(offset);
3952 cmd->length = CPU_TO_LE16(length);
3954 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3955 if (length > I40E_AQ_LARGE_BUF)
3956 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3958 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3960 i40e_aq_update_nvm_exit:
3965 * i40e_aq_get_lldp_mib
3966 * @hw: pointer to the hw struct
3967 * @bridge_type: type of bridge requested
3968 * @mib_type: Local, Remote or both Local and Remote MIBs
3969 * @buff: pointer to a user supplied buffer to store the MIB block
3970 * @buff_size: size of the buffer (in bytes)
3971 * @local_len : length of the returned Local LLDP MIB
3972 * @remote_len: length of the returned Remote LLDP MIB
3973 * @cmd_details: pointer to command details structure or NULL
3975 * Requests the complete LLDP MIB (entire packet).
3977 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3978 u8 mib_type, void *buff, u16 buff_size,
3979 u16 *local_len, u16 *remote_len,
3980 struct i40e_asq_cmd_details *cmd_details)
3982 struct i40e_aq_desc desc;
3983 struct i40e_aqc_lldp_get_mib *cmd =
3984 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3985 struct i40e_aqc_lldp_get_mib *resp =
3986 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3987 enum i40e_status_code status;
3989 if (buff_size == 0 || !buff)
3990 return I40E_ERR_PARAM;
3992 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3993 /* Indirect Command */
3994 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3996 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3997 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3998 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4000 desc.datalen = CPU_TO_LE16(buff_size);
4002 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4003 if (buff_size > I40E_AQ_LARGE_BUF)
4004 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4006 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4008 if (local_len != NULL)
4009 *local_len = LE16_TO_CPU(resp->local_len);
4010 if (remote_len != NULL)
4011 *remote_len = LE16_TO_CPU(resp->remote_len);
4018 * i40e_aq_set_lldp_mib - Set the LLDP MIB
4019 * @hw: pointer to the hw struct
4020 * @mib_type: Local, Remote or both Local and Remote MIBs
4021 * @buff: pointer to a user supplied buffer to store the MIB block
4022 * @buff_size: size of the buffer (in bytes)
4023 * @cmd_details: pointer to command details structure or NULL
4027 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4028 u8 mib_type, void *buff, u16 buff_size,
4029 struct i40e_asq_cmd_details *cmd_details)
4031 struct i40e_aq_desc desc;
4032 struct i40e_aqc_lldp_set_local_mib *cmd =
4033 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4034 enum i40e_status_code status;
4036 if (buff_size == 0 || !buff)
4037 return I40E_ERR_PARAM;
4039 i40e_fill_default_direct_cmd_desc(&desc,
4040 i40e_aqc_opc_lldp_set_local_mib);
4041 /* Indirect Command */
4042 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4043 if (buff_size > I40E_AQ_LARGE_BUF)
4044 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4045 desc.datalen = CPU_TO_LE16(buff_size);
4047 cmd->type = mib_type;
4048 cmd->length = CPU_TO_LE16(buff_size);
4049 cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4050 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4052 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4057 * i40e_aq_cfg_lldp_mib_change_event
4058 * @hw: pointer to the hw struct
4059 * @enable_update: Enable or Disable event posting
4060 * @cmd_details: pointer to command details structure or NULL
4062 * Enable or Disable posting of an event on ARQ when LLDP MIB
4063 * associated with the interface changes
4065 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4067 struct i40e_asq_cmd_details *cmd_details)
4069 struct i40e_aq_desc desc;
4070 struct i40e_aqc_lldp_update_mib *cmd =
4071 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4072 enum i40e_status_code status;
4074 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4077 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4079 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4085 * i40e_aq_add_lldp_tlv
4086 * @hw: pointer to the hw struct
4087 * @bridge_type: type of bridge
4088 * @buff: buffer with TLV to add
4089 * @buff_size: length of the buffer
4090 * @tlv_len: length of the TLV to be added
4091 * @mib_len: length of the LLDP MIB returned in response
4092 * @cmd_details: pointer to command details structure or NULL
4094 * Add the specified TLV to LLDP Local MIB for the given bridge type,
4095 * it is responsibility of the caller to make sure that the TLV is not
4096 * already present in the LLDPDU.
4097 * In return firmware will write the complete LLDP MIB with the newly
4098 * added TLV in the response buffer.
4100 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4101 void *buff, u16 buff_size, u16 tlv_len,
4103 struct i40e_asq_cmd_details *cmd_details)
4105 struct i40e_aq_desc desc;
4106 struct i40e_aqc_lldp_add_tlv *cmd =
4107 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4108 enum i40e_status_code status;
4110 if (buff_size == 0 || !buff || tlv_len == 0)
4111 return I40E_ERR_PARAM;
4113 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4115 /* Indirect Command */
4116 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4117 if (buff_size > I40E_AQ_LARGE_BUF)
4118 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4119 desc.datalen = CPU_TO_LE16(buff_size);
4121 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4122 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4123 cmd->len = CPU_TO_LE16(tlv_len);
4125 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4127 if (mib_len != NULL)
4128 *mib_len = LE16_TO_CPU(desc.datalen);
4135 * i40e_aq_update_lldp_tlv
4136 * @hw: pointer to the hw struct
4137 * @bridge_type: type of bridge
4138 * @buff: buffer with TLV to update
4139 * @buff_size: size of the buffer holding original and updated TLVs
4140 * @old_len: Length of the Original TLV
4141 * @new_len: Length of the Updated TLV
4142 * @offset: offset of the updated TLV in the buff
4143 * @mib_len: length of the returned LLDP MIB
4144 * @cmd_details: pointer to command details structure or NULL
4146 * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4147 * Firmware will place the complete LLDP MIB in response buffer with the
4150 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4151 u8 bridge_type, void *buff, u16 buff_size,
4152 u16 old_len, u16 new_len, u16 offset,
4154 struct i40e_asq_cmd_details *cmd_details)
4156 struct i40e_aq_desc desc;
4157 struct i40e_aqc_lldp_update_tlv *cmd =
4158 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4159 enum i40e_status_code status;
4161 if (buff_size == 0 || !buff || offset == 0 ||
4162 old_len == 0 || new_len == 0)
4163 return I40E_ERR_PARAM;
4165 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4167 /* Indirect Command */
4168 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4169 if (buff_size > I40E_AQ_LARGE_BUF)
4170 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4171 desc.datalen = CPU_TO_LE16(buff_size);
4173 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4174 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4175 cmd->old_len = CPU_TO_LE16(old_len);
4176 cmd->new_offset = CPU_TO_LE16(offset);
4177 cmd->new_len = CPU_TO_LE16(new_len);
4179 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4181 if (mib_len != NULL)
4182 *mib_len = LE16_TO_CPU(desc.datalen);
4189 * i40e_aq_delete_lldp_tlv
4190 * @hw: pointer to the hw struct
4191 * @bridge_type: type of bridge
4192 * @buff: pointer to a user supplied buffer that has the TLV
4193 * @buff_size: length of the buffer
4194 * @tlv_len: length of the TLV to be deleted
4195 * @mib_len: length of the returned LLDP MIB
4196 * @cmd_details: pointer to command details structure or NULL
4198 * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4199 * The firmware places the entire LLDP MIB in the response buffer.
4201 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4202 u8 bridge_type, void *buff, u16 buff_size,
4203 u16 tlv_len, u16 *mib_len,
4204 struct i40e_asq_cmd_details *cmd_details)
4206 struct i40e_aq_desc desc;
4207 struct i40e_aqc_lldp_add_tlv *cmd =
4208 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4209 enum i40e_status_code status;
4211 if (buff_size == 0 || !buff)
4212 return I40E_ERR_PARAM;
4214 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4216 /* Indirect Command */
4217 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4218 if (buff_size > I40E_AQ_LARGE_BUF)
4219 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4220 desc.datalen = CPU_TO_LE16(buff_size);
4221 cmd->len = CPU_TO_LE16(tlv_len);
4222 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4223 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4225 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4227 if (mib_len != NULL)
4228 *mib_len = LE16_TO_CPU(desc.datalen);
4236 * @hw: pointer to the hw struct
4237 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4238 * @cmd_details: pointer to command details structure or NULL
4240 * Stop or Shutdown the embedded LLDP Agent
4242 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4243 struct i40e_asq_cmd_details *cmd_details)
4245 struct i40e_aq_desc desc;
4246 struct i40e_aqc_lldp_stop *cmd =
4247 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4248 enum i40e_status_code status;
4250 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4253 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4255 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4261 * i40e_aq_start_lldp
4262 * @hw: pointer to the hw struct
4263 * @cmd_details: pointer to command details structure or NULL
4265 * Start the embedded LLDP Agent on all ports.
4267 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4268 struct i40e_asq_cmd_details *cmd_details)
4270 struct i40e_aq_desc desc;
4271 struct i40e_aqc_lldp_start *cmd =
4272 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4273 enum i40e_status_code status;
4275 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4277 cmd->command = I40E_AQ_LLDP_AGENT_START;
4279 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4285 * i40e_aq_get_cee_dcb_config
4286 * @hw: pointer to the hw struct
4287 * @buff: response buffer that stores CEE operational configuration
4288 * @buff_size: size of the buffer passed
4289 * @cmd_details: pointer to command details structure or NULL
4291 * Get CEE DCBX mode operational configuration from firmware
4293 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4294 void *buff, u16 buff_size,
4295 struct i40e_asq_cmd_details *cmd_details)
4297 struct i40e_aq_desc desc;
4298 enum i40e_status_code status;
4300 if (buff_size == 0 || !buff)
4301 return I40E_ERR_PARAM;
4303 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4305 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4306 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4313 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4314 * @hw: pointer to the hw struct
4315 * @start_agent: True if DCBx Agent needs to be Started
4316 * False if DCBx Agent needs to be Stopped
4317 * @cmd_details: pointer to command details structure or NULL
4319 * Start/Stop the embedded dcbx Agent
4321 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4323 struct i40e_asq_cmd_details *cmd_details)
4325 struct i40e_aq_desc desc;
4326 struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4327 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4329 enum i40e_status_code status;
4331 i40e_fill_default_direct_cmd_desc(&desc,
4332 i40e_aqc_opc_lldp_stop_start_spec_agent);
4335 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4337 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4343 * i40e_aq_add_udp_tunnel
4344 * @hw: pointer to the hw struct
4345 * @udp_port: the UDP port to add
4346 * @header_len: length of the tunneling header length in DWords
4347 * @protocol_index: protocol index type
4348 * @filter_index: pointer to filter index
4349 * @cmd_details: pointer to command details structure or NULL
4351 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4352 u16 udp_port, u8 protocol_index,
4354 struct i40e_asq_cmd_details *cmd_details)
4356 struct i40e_aq_desc desc;
4357 struct i40e_aqc_add_udp_tunnel *cmd =
4358 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4359 struct i40e_aqc_del_udp_tunnel_completion *resp =
4360 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4361 enum i40e_status_code status;
4363 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4365 cmd->udp_port = CPU_TO_LE16(udp_port);
4366 cmd->protocol_type = protocol_index;
4368 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4370 if (!status && filter_index)
4371 *filter_index = resp->index;
4377 * i40e_aq_del_udp_tunnel
4378 * @hw: pointer to the hw struct
4379 * @index: filter index
4380 * @cmd_details: pointer to command details structure or NULL
4382 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4383 struct i40e_asq_cmd_details *cmd_details)
4385 struct i40e_aq_desc desc;
4386 struct i40e_aqc_remove_udp_tunnel *cmd =
4387 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4388 enum i40e_status_code status;
4390 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4394 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4400 * i40e_aq_get_switch_resource_alloc (0x0204)
4401 * @hw: pointer to the hw struct
4402 * @num_entries: pointer to u8 to store the number of resource entries returned
4403 * @buf: pointer to a user supplied buffer. This buffer must be large enough
4404 * to store the resource information for all resource types. Each
4405 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
4406 * @count: size, in bytes, of the buffer provided
4407 * @cmd_details: pointer to command details structure or NULL
4409 * Query the resources allocated to a function.
4411 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4413 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4415 struct i40e_asq_cmd_details *cmd_details)
4417 struct i40e_aq_desc desc;
4418 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4419 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4420 enum i40e_status_code status;
4421 u16 length = count * sizeof(*buf);
4423 i40e_fill_default_direct_cmd_desc(&desc,
4424 i40e_aqc_opc_get_switch_resource_alloc);
4426 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4427 if (length > I40E_AQ_LARGE_BUF)
4428 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4430 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4432 if (!status && num_entries)
4433 *num_entries = cmd_resp->num_entries;
4439 * i40e_aq_delete_element - Delete switch element
4440 * @hw: pointer to the hw struct
4441 * @seid: the SEID to delete from the switch
4442 * @cmd_details: pointer to command details structure or NULL
4444 * This deletes a switch element from the switch.
4446 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4447 struct i40e_asq_cmd_details *cmd_details)
4449 struct i40e_aq_desc desc;
4450 struct i40e_aqc_switch_seid *cmd =
4451 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4452 enum i40e_status_code status;
4455 return I40E_ERR_PARAM;
4457 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4459 cmd->seid = CPU_TO_LE16(seid);
4461 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4467 * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4468 * @hw: pointer to the hw struct
4469 * @flags: component flags
4470 * @mac_seid: uplink seid (MAC SEID)
4471 * @vsi_seid: connected vsi seid
4472 * @ret_seid: seid of create pv component
4474 * This instantiates an i40e port virtualizer with specified flags.
4475 * Depending on specified flags the port virtualizer can act as a
4476 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4478 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4479 u16 mac_seid, u16 vsi_seid,
4482 struct i40e_aq_desc desc;
4483 struct i40e_aqc_add_update_pv *cmd =
4484 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4485 struct i40e_aqc_add_update_pv_completion *resp =
4486 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4487 enum i40e_status_code status;
4490 return I40E_ERR_PARAM;
4492 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4493 cmd->command_flags = CPU_TO_LE16(flags);
4494 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4495 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4497 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4498 if (!status && ret_seid)
4499 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4505 * i40e_aq_add_tag - Add an S/E-tag
4506 * @hw: pointer to the hw struct
4507 * @direct_to_queue: should s-tag direct flow to a specific queue
4508 * @vsi_seid: VSI SEID to use this tag
4509 * @tag: value of the tag
4510 * @queue_num: queue number, only valid is direct_to_queue is true
4511 * @tags_used: return value, number of tags in use by this PF
4512 * @tags_free: return value, number of unallocated tags
4513 * @cmd_details: pointer to command details structure or NULL
4515 * This associates an S- or E-tag to a VSI in the switch complex. It returns
4516 * the number of tags allocated by the PF, and the number of unallocated
4519 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4520 u16 vsi_seid, u16 tag, u16 queue_num,
4521 u16 *tags_used, u16 *tags_free,
4522 struct i40e_asq_cmd_details *cmd_details)
4524 struct i40e_aq_desc desc;
4525 struct i40e_aqc_add_tag *cmd =
4526 (struct i40e_aqc_add_tag *)&desc.params.raw;
4527 struct i40e_aqc_add_remove_tag_completion *resp =
4528 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4529 enum i40e_status_code status;
4532 return I40E_ERR_PARAM;
4534 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4536 cmd->seid = CPU_TO_LE16(vsi_seid);
4537 cmd->tag = CPU_TO_LE16(tag);
4538 if (direct_to_queue) {
4539 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4540 cmd->queue_number = CPU_TO_LE16(queue_num);
4543 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4546 if (tags_used != NULL)
4547 *tags_used = LE16_TO_CPU(resp->tags_used);
4548 if (tags_free != NULL)
4549 *tags_free = LE16_TO_CPU(resp->tags_free);
4556 * i40e_aq_remove_tag - Remove an S- or E-tag
4557 * @hw: pointer to the hw struct
4558 * @vsi_seid: VSI SEID this tag is associated with
4559 * @tag: value of the S-tag to delete
4560 * @tags_used: return value, number of tags in use by this PF
4561 * @tags_free: return value, number of unallocated tags
4562 * @cmd_details: pointer to command details structure or NULL
4564 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
4565 * the number of tags allocated by the PF, and the number of unallocated
4568 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4569 u16 tag, u16 *tags_used, u16 *tags_free,
4570 struct i40e_asq_cmd_details *cmd_details)
4572 struct i40e_aq_desc desc;
4573 struct i40e_aqc_remove_tag *cmd =
4574 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4575 struct i40e_aqc_add_remove_tag_completion *resp =
4576 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4577 enum i40e_status_code status;
4580 return I40E_ERR_PARAM;
4582 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4584 cmd->seid = CPU_TO_LE16(vsi_seid);
4585 cmd->tag = CPU_TO_LE16(tag);
4587 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4590 if (tags_used != NULL)
4591 *tags_used = LE16_TO_CPU(resp->tags_used);
4592 if (tags_free != NULL)
4593 *tags_free = LE16_TO_CPU(resp->tags_free);
4600 * i40e_aq_add_mcast_etag - Add a multicast E-tag
4601 * @hw: pointer to the hw struct
4602 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4603 * @etag: value of E-tag to add
4604 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4605 * @buf: address of indirect buffer
4606 * @tags_used: return value, number of E-tags in use by this port
4607 * @tags_free: return value, number of unallocated M-tags
4608 * @cmd_details: pointer to command details structure or NULL
4610 * This associates a multicast E-tag to a port virtualizer. It will return
4611 * the number of tags allocated by the PF, and the number of unallocated
4614 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4615 * num_tags_in_buf long.
4617 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4618 u16 etag, u8 num_tags_in_buf, void *buf,
4619 u16 *tags_used, u16 *tags_free,
4620 struct i40e_asq_cmd_details *cmd_details)
4622 struct i40e_aq_desc desc;
4623 struct i40e_aqc_add_remove_mcast_etag *cmd =
4624 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4625 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4626 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4627 enum i40e_status_code status;
4628 u16 length = sizeof(u16) * num_tags_in_buf;
4630 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4631 return I40E_ERR_PARAM;
4633 i40e_fill_default_direct_cmd_desc(&desc,
4634 i40e_aqc_opc_add_multicast_etag);
4636 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4637 cmd->etag = CPU_TO_LE16(etag);
4638 cmd->num_unicast_etags = num_tags_in_buf;
4640 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4641 if (length > I40E_AQ_LARGE_BUF)
4642 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4644 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4647 if (tags_used != NULL)
4648 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4649 if (tags_free != NULL)
4650 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4657 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4658 * @hw: pointer to the hw struct
4659 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4660 * @etag: value of the E-tag to remove
4661 * @tags_used: return value, number of tags in use by this port
4662 * @tags_free: return value, number of unallocated tags
4663 * @cmd_details: pointer to command details structure or NULL
4665 * This deletes an E-tag from the port virtualizer. It will return
4666 * the number of tags allocated by the port, and the number of unallocated
4669 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4670 u16 etag, u16 *tags_used, u16 *tags_free,
4671 struct i40e_asq_cmd_details *cmd_details)
4673 struct i40e_aq_desc desc;
4674 struct i40e_aqc_add_remove_mcast_etag *cmd =
4675 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4676 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4677 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4678 enum i40e_status_code status;
4682 return I40E_ERR_PARAM;
4684 i40e_fill_default_direct_cmd_desc(&desc,
4685 i40e_aqc_opc_remove_multicast_etag);
4687 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4688 cmd->etag = CPU_TO_LE16(etag);
4690 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4693 if (tags_used != NULL)
4694 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4695 if (tags_free != NULL)
4696 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4703 * i40e_aq_update_tag - Update an S/E-tag
4704 * @hw: pointer to the hw struct
4705 * @vsi_seid: VSI SEID using this S-tag
4706 * @old_tag: old tag value
4707 * @new_tag: new tag value
4708 * @tags_used: return value, number of tags in use by this PF
4709 * @tags_free: return value, number of unallocated tags
4710 * @cmd_details: pointer to command details structure or NULL
4712 * This updates the value of the tag currently attached to this VSI
4713 * in the switch complex. It will return the number of tags allocated
4714 * by the PF, and the number of unallocated tags available.
4716 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4717 u16 old_tag, u16 new_tag, u16 *tags_used,
4719 struct i40e_asq_cmd_details *cmd_details)
4721 struct i40e_aq_desc desc;
4722 struct i40e_aqc_update_tag *cmd =
4723 (struct i40e_aqc_update_tag *)&desc.params.raw;
4724 struct i40e_aqc_update_tag_completion *resp =
4725 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4726 enum i40e_status_code status;
4729 return I40E_ERR_PARAM;
4731 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4733 cmd->seid = CPU_TO_LE16(vsi_seid);
4734 cmd->old_tag = CPU_TO_LE16(old_tag);
4735 cmd->new_tag = CPU_TO_LE16(new_tag);
4737 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4740 if (tags_used != NULL)
4741 *tags_used = LE16_TO_CPU(resp->tags_used);
4742 if (tags_free != NULL)
4743 *tags_free = LE16_TO_CPU(resp->tags_free);
4750 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4751 * @hw: pointer to the hw struct
4752 * @tcmap: TC map for request/release any ignore PFC condition
4753 * @request: request or release ignore PFC condition
4754 * @tcmap_ret: return TCs for which PFC is currently ignored
4755 * @cmd_details: pointer to command details structure or NULL
4757 * This sends out request/release to ignore PFC condition for a TC.
4758 * It will return the TCs for which PFC is currently ignored.
4760 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4761 bool request, u8 *tcmap_ret,
4762 struct i40e_asq_cmd_details *cmd_details)
4764 struct i40e_aq_desc desc;
4765 struct i40e_aqc_pfc_ignore *cmd_resp =
4766 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4767 enum i40e_status_code status;
4769 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4772 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4774 cmd_resp->tc_bitmap = tcmap;
4776 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4779 if (tcmap_ret != NULL)
4780 *tcmap_ret = cmd_resp->tc_bitmap;
4787 * i40e_aq_dcb_updated - DCB Updated Command
4788 * @hw: pointer to the hw struct
4789 * @cmd_details: pointer to command details structure or NULL
4791 * When LLDP is handled in PF this command is used by the PF
4792 * to notify EMP that a DCB setting is modified.
4793 * When LLDP is handled in EMP this command is used by the PF
4794 * to notify EMP whenever one of the following parameters get
4796 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4797 * - PCIRTT in PRTDCB_GENC.PCIRTT
4798 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4799 * EMP will return when the shared RPB settings have been
4800 * recomputed and modified. The retval field in the descriptor
4801 * will be set to 0 when RPB is modified.
4803 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4804 struct i40e_asq_cmd_details *cmd_details)
4806 struct i40e_aq_desc desc;
4807 enum i40e_status_code status;
4809 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4811 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4817 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4818 * @hw: pointer to the hw struct
4819 * @seid: defines the SEID of the switch for which the stats are requested
4820 * @vlan_id: the VLAN ID for which the statistics are requested
4821 * @stat_index: index of the statistics counters block assigned to this VLAN
4822 * @cmd_details: pointer to command details structure or NULL
4824 * XL710 supports 128 smonVlanStats counters.This command is used to
4825 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4828 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4829 u16 vlan_id, u16 *stat_index,
4830 struct i40e_asq_cmd_details *cmd_details)
4832 struct i40e_aq_desc desc;
4833 struct i40e_aqc_add_remove_statistics *cmd_resp =
4834 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4835 enum i40e_status_code status;
4837 if ((seid == 0) || (stat_index == NULL))
4838 return I40E_ERR_PARAM;
4840 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4842 cmd_resp->seid = CPU_TO_LE16(seid);
4843 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4845 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4847 if (!status && stat_index)
4848 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4854 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4855 * @hw: pointer to the hw struct
4856 * @seid: defines the SEID of the switch for which the stats are requested
4857 * @vlan_id: the VLAN ID for which the statistics are requested
4858 * @stat_index: index of the statistics counters block assigned to this VLAN
4859 * @cmd_details: pointer to command details structure or NULL
4861 * XL710 supports 128 smonVlanStats counters.This command is used to
4862 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4865 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4866 u16 vlan_id, u16 stat_index,
4867 struct i40e_asq_cmd_details *cmd_details)
4869 struct i40e_aq_desc desc;
4870 struct i40e_aqc_add_remove_statistics *cmd =
4871 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4872 enum i40e_status_code status;
4875 return I40E_ERR_PARAM;
4877 i40e_fill_default_direct_cmd_desc(&desc,
4878 i40e_aqc_opc_remove_statistics);
4880 cmd->seid = CPU_TO_LE16(seid);
4881 cmd->vlan = CPU_TO_LE16(vlan_id);
4882 cmd->stat_index = CPU_TO_LE16(stat_index);
4884 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4890 * i40e_aq_set_port_parameters - set physical port parameters.
4891 * @hw: pointer to the hw struct
4892 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4893 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4894 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4895 * @double_vlan: if set double VLAN is enabled
4896 * @cmd_details: pointer to command details structure or NULL
4898 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4899 u16 bad_frame_vsi, bool save_bad_pac,
4900 bool pad_short_pac, bool double_vlan,
4901 struct i40e_asq_cmd_details *cmd_details)
4903 struct i40e_aqc_set_port_parameters *cmd;
4904 enum i40e_status_code status;
4905 struct i40e_aq_desc desc;
4906 u16 command_flags = 0;
4908 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4910 i40e_fill_default_direct_cmd_desc(&desc,
4911 i40e_aqc_opc_set_port_parameters);
4913 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4915 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4917 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4919 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4920 cmd->command_flags = CPU_TO_LE16(command_flags);
4922 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4928 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
4929 * @hw: pointer to the hw struct
4930 * @seid: seid for the physical port/switching component/vsi
4931 * @buff: Indirect buffer to hold data parameters and response
4932 * @buff_size: Indirect buffer size
4933 * @opcode: Tx scheduler AQ command opcode
4934 * @cmd_details: pointer to command details structure or NULL
4936 * Generic command handler for Tx scheduler AQ commands
4938 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
4939 void *buff, u16 buff_size,
4940 enum i40e_admin_queue_opc opcode,
4941 struct i40e_asq_cmd_details *cmd_details)
4943 struct i40e_aq_desc desc;
4944 struct i40e_aqc_tx_sched_ind *cmd =
4945 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4946 enum i40e_status_code status;
4947 bool cmd_param_flag = false;
4950 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
4951 case i40e_aqc_opc_configure_vsi_tc_bw:
4952 case i40e_aqc_opc_enable_switching_comp_ets:
4953 case i40e_aqc_opc_modify_switching_comp_ets:
4954 case i40e_aqc_opc_disable_switching_comp_ets:
4955 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
4956 case i40e_aqc_opc_configure_switching_comp_bw_config:
4957 cmd_param_flag = true;
4959 case i40e_aqc_opc_query_vsi_bw_config:
4960 case i40e_aqc_opc_query_vsi_ets_sla_config:
4961 case i40e_aqc_opc_query_switching_comp_ets_config:
4962 case i40e_aqc_opc_query_port_ets_config:
4963 case i40e_aqc_opc_query_switching_comp_bw_config:
4964 cmd_param_flag = false;
4967 return I40E_ERR_PARAM;
4970 i40e_fill_default_direct_cmd_desc(&desc, opcode);
4972 /* Indirect command */
4973 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4975 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4976 if (buff_size > I40E_AQ_LARGE_BUF)
4977 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4979 desc.datalen = CPU_TO_LE16(buff_size);
4981 cmd->vsi_seid = CPU_TO_LE16(seid);
4983 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4989 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
4990 * @hw: pointer to the hw struct
4992 * @credit: BW limit credits (0 = disabled)
4993 * @max_credit: Max BW limit credits
4994 * @cmd_details: pointer to command details structure or NULL
4996 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
4997 u16 seid, u16 credit, u8 max_credit,
4998 struct i40e_asq_cmd_details *cmd_details)
5000 struct i40e_aq_desc desc;
5001 struct i40e_aqc_configure_vsi_bw_limit *cmd =
5002 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5003 enum i40e_status_code status;
5005 i40e_fill_default_direct_cmd_desc(&desc,
5006 i40e_aqc_opc_configure_vsi_bw_limit);
5008 cmd->vsi_seid = CPU_TO_LE16(seid);
5009 cmd->credit = CPU_TO_LE16(credit);
5010 cmd->max_credit = max_credit;
5012 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5018 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5019 * @hw: pointer to the hw struct
5020 * @seid: switching component seid
5021 * @credit: BW limit credits (0 = disabled)
5022 * @max_bw: Max BW limit credits
5023 * @cmd_details: pointer to command details structure or NULL
5025 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5026 u16 seid, u16 credit, u8 max_bw,
5027 struct i40e_asq_cmd_details *cmd_details)
5029 struct i40e_aq_desc desc;
5030 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5031 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5032 enum i40e_status_code status;
5034 i40e_fill_default_direct_cmd_desc(&desc,
5035 i40e_aqc_opc_configure_switching_comp_bw_limit);
5037 cmd->seid = CPU_TO_LE16(seid);
5038 cmd->credit = CPU_TO_LE16(credit);
5039 cmd->max_bw = max_bw;
5041 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5047 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5048 * @hw: pointer to the hw struct
5050 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5051 * @cmd_details: pointer to command details structure or NULL
5053 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5055 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5056 struct i40e_asq_cmd_details *cmd_details)
5058 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5059 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5064 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5065 * @hw: pointer to the hw struct
5067 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5068 * @cmd_details: pointer to command details structure or NULL
5070 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5072 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5073 struct i40e_asq_cmd_details *cmd_details)
5075 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5076 i40e_aqc_opc_configure_vsi_tc_bw,
5081 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5082 * @hw: pointer to the hw struct
5083 * @seid: seid of the switching component connected to Physical Port
5084 * @ets_data: Buffer holding ETS parameters
5085 * @cmd_details: pointer to command details structure or NULL
5087 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5089 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5090 enum i40e_admin_queue_opc opcode,
5091 struct i40e_asq_cmd_details *cmd_details)
5093 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5094 sizeof(*ets_data), opcode, cmd_details);
5098 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5099 * @hw: pointer to the hw struct
5100 * @seid: seid of the switching component
5101 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5102 * @cmd_details: pointer to command details structure or NULL
5104 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5106 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5107 struct i40e_asq_cmd_details *cmd_details)
5109 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5110 i40e_aqc_opc_configure_switching_comp_bw_config,
5115 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5116 * @hw: pointer to the hw struct
5117 * @seid: seid of the switching component
5118 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5119 * @cmd_details: pointer to command details structure or NULL
5121 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5122 struct i40e_hw *hw, u16 seid,
5123 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5124 struct i40e_asq_cmd_details *cmd_details)
5126 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5127 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5132 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5133 * @hw: pointer to the hw struct
5134 * @seid: seid of the VSI
5135 * @bw_data: Buffer to hold VSI BW configuration
5136 * @cmd_details: pointer to command details structure or NULL
5138 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5140 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5141 struct i40e_asq_cmd_details *cmd_details)
5143 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5144 i40e_aqc_opc_query_vsi_bw_config,
5149 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5150 * @hw: pointer to the hw struct
5151 * @seid: seid of the VSI
5152 * @bw_data: Buffer to hold VSI BW configuration per TC
5153 * @cmd_details: pointer to command details structure or NULL
5155 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5157 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5158 struct i40e_asq_cmd_details *cmd_details)
5160 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5161 i40e_aqc_opc_query_vsi_ets_sla_config,
5166 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5167 * @hw: pointer to the hw struct
5168 * @seid: seid of the switching component
5169 * @bw_data: Buffer to hold switching component's per TC BW config
5170 * @cmd_details: pointer to command details structure or NULL
5172 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5174 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5175 struct i40e_asq_cmd_details *cmd_details)
5177 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5178 i40e_aqc_opc_query_switching_comp_ets_config,
5183 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5184 * @hw: pointer to the hw struct
5185 * @seid: seid of the VSI or switching component connected to Physical Port
5186 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5187 * @cmd_details: pointer to command details structure or NULL
5189 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5191 struct i40e_aqc_query_port_ets_config_resp *bw_data,
5192 struct i40e_asq_cmd_details *cmd_details)
5194 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5195 i40e_aqc_opc_query_port_ets_config,
5200 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5201 * @hw: pointer to the hw struct
5202 * @seid: seid of the switching component
5203 * @bw_data: Buffer to hold switching component's BW configuration
5204 * @cmd_details: pointer to command details structure or NULL
5206 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5208 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5209 struct i40e_asq_cmd_details *cmd_details)
5211 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5212 i40e_aqc_opc_query_switching_comp_bw_config,
5217 * i40e_validate_filter_settings
5218 * @hw: pointer to the hardware structure
5219 * @settings: Filter control settings
5221 * Check and validate the filter control settings passed.
5222 * The function checks for the valid filter/context sizes being
5223 * passed for FCoE and PE.
5225 * Returns I40E_SUCCESS if the values passed are valid and within
5226 * range else returns an error.
5228 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5229 struct i40e_filter_control_settings *settings)
5231 u32 fcoe_cntx_size, fcoe_filt_size;
5232 u32 pe_cntx_size, pe_filt_size;
5237 /* Validate FCoE settings passed */
5238 switch (settings->fcoe_filt_num) {
5239 case I40E_HASH_FILTER_SIZE_1K:
5240 case I40E_HASH_FILTER_SIZE_2K:
5241 case I40E_HASH_FILTER_SIZE_4K:
5242 case I40E_HASH_FILTER_SIZE_8K:
5243 case I40E_HASH_FILTER_SIZE_16K:
5244 case I40E_HASH_FILTER_SIZE_32K:
5245 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5246 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5249 return I40E_ERR_PARAM;
5252 switch (settings->fcoe_cntx_num) {
5253 case I40E_DMA_CNTX_SIZE_512:
5254 case I40E_DMA_CNTX_SIZE_1K:
5255 case I40E_DMA_CNTX_SIZE_2K:
5256 case I40E_DMA_CNTX_SIZE_4K:
5257 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5258 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5261 return I40E_ERR_PARAM;
5264 /* Validate PE settings passed */
5265 switch (settings->pe_filt_num) {
5266 case I40E_HASH_FILTER_SIZE_1K:
5267 case I40E_HASH_FILTER_SIZE_2K:
5268 case I40E_HASH_FILTER_SIZE_4K:
5269 case I40E_HASH_FILTER_SIZE_8K:
5270 case I40E_HASH_FILTER_SIZE_16K:
5271 case I40E_HASH_FILTER_SIZE_32K:
5272 case I40E_HASH_FILTER_SIZE_64K:
5273 case I40E_HASH_FILTER_SIZE_128K:
5274 case I40E_HASH_FILTER_SIZE_256K:
5275 case I40E_HASH_FILTER_SIZE_512K:
5276 case I40E_HASH_FILTER_SIZE_1M:
5277 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5278 pe_filt_size <<= (u32)settings->pe_filt_num;
5281 return I40E_ERR_PARAM;
5284 switch (settings->pe_cntx_num) {
5285 case I40E_DMA_CNTX_SIZE_512:
5286 case I40E_DMA_CNTX_SIZE_1K:
5287 case I40E_DMA_CNTX_SIZE_2K:
5288 case I40E_DMA_CNTX_SIZE_4K:
5289 case I40E_DMA_CNTX_SIZE_8K:
5290 case I40E_DMA_CNTX_SIZE_16K:
5291 case I40E_DMA_CNTX_SIZE_32K:
5292 case I40E_DMA_CNTX_SIZE_64K:
5293 case I40E_DMA_CNTX_SIZE_128K:
5294 case I40E_DMA_CNTX_SIZE_256K:
5295 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5296 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5299 return I40E_ERR_PARAM;
5302 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5303 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5304 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5305 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5306 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
5307 return I40E_ERR_INVALID_SIZE;
5309 return I40E_SUCCESS;
5313 * i40e_set_filter_control
5314 * @hw: pointer to the hardware structure
5315 * @settings: Filter control settings
5317 * Set the Queue Filters for PE/FCoE and enable filters required
5318 * for a single PF. It is expected that these settings are programmed
5319 * at the driver initialization time.
5321 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5322 struct i40e_filter_control_settings *settings)
5324 enum i40e_status_code ret = I40E_SUCCESS;
5325 u32 hash_lut_size = 0;
5329 return I40E_ERR_PARAM;
5331 /* Validate the input settings */
5332 ret = i40e_validate_filter_settings(hw, settings);
5336 /* Read the PF Queue Filter control register */
5337 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5339 /* Program required PE hash buckets for the PF */
5340 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5341 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5342 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5343 /* Program required PE contexts for the PF */
5344 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5345 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5346 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5348 /* Program required FCoE hash buckets for the PF */
5349 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5350 val |= ((u32)settings->fcoe_filt_num <<
5351 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5352 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5353 /* Program required FCoE DDP contexts for the PF */
5354 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5355 val |= ((u32)settings->fcoe_cntx_num <<
5356 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5357 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5359 /* Program Hash LUT size for the PF */
5360 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5361 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5363 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5364 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5366 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5367 if (settings->enable_fdir)
5368 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5369 if (settings->enable_ethtype)
5370 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5371 if (settings->enable_macvlan)
5372 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5374 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5376 return I40E_SUCCESS;
5380 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5381 * @hw: pointer to the hw struct
5382 * @mac_addr: MAC address to use in the filter
5383 * @ethtype: Ethertype to use in the filter
5384 * @flags: Flags that needs to be applied to the filter
5385 * @vsi_seid: seid of the control VSI
5386 * @queue: VSI queue number to send the packet to
5387 * @is_add: Add control packet filter if True else remove
5388 * @stats: Structure to hold information on control filter counts
5389 * @cmd_details: pointer to command details structure or NULL
5391 * This command will Add or Remove control packet filter for a control VSI.
5392 * In return it will update the total number of perfect filter count in
5395 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5396 u8 *mac_addr, u16 ethtype, u16 flags,
5397 u16 vsi_seid, u16 queue, bool is_add,
5398 struct i40e_control_filter_stats *stats,
5399 struct i40e_asq_cmd_details *cmd_details)
5401 struct i40e_aq_desc desc;
5402 struct i40e_aqc_add_remove_control_packet_filter *cmd =
5403 (struct i40e_aqc_add_remove_control_packet_filter *)
5405 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5406 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5408 enum i40e_status_code status;
5411 return I40E_ERR_PARAM;
5414 i40e_fill_default_direct_cmd_desc(&desc,
5415 i40e_aqc_opc_add_control_packet_filter);
5416 cmd->queue = CPU_TO_LE16(queue);
5418 i40e_fill_default_direct_cmd_desc(&desc,
5419 i40e_aqc_opc_remove_control_packet_filter);
5423 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
5424 I40E_NONDMA_TO_NONDMA);
5426 cmd->etype = CPU_TO_LE16(ethtype);
5427 cmd->flags = CPU_TO_LE16(flags);
5428 cmd->seid = CPU_TO_LE16(vsi_seid);
5430 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5432 if (!status && stats) {
5433 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5434 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5435 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5436 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5443 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5444 * @hw: pointer to the hw struct
5445 * @seid: VSI seid to add ethertype filter from
5447 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5448 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5451 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5452 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5453 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5454 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5455 enum i40e_status_code status;
5457 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5458 seid, 0, true, NULL,
5461 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5465 * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5466 * @filters: list of cloud filters
5467 * @filter_count: length of list
5469 * There's an issue in the device where the Geneve VNI layout needs
5470 * to be shifted 1 byte over from the VxLAN VNI
5472 STATIC void i40e_fix_up_geneve_vni(
5473 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5476 struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters;
5479 for (i = 0; i < filter_count; i++) {
5483 tnl_type = (le16_to_cpu(f[i].flags) &
5484 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5485 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5486 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5487 ti = le32_to_cpu(f[i].tenant_id);
5488 f[i].tenant_id = cpu_to_le32(ti << 8);
5494 * i40e_aq_add_cloud_filters
5495 * @hw: pointer to the hardware structure
5496 * @seid: VSI seid to add cloud filters from
5497 * @filters: Buffer which contains the filters to be added
5498 * @filter_count: number of filters contained in the buffer
5500 * Set the cloud filters for a given VSI. The contents of the
5501 * i40e_aqc_add_remove_cloud_filters_element_data are filled
5502 * in by the caller of the function.
5505 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5507 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5510 struct i40e_aq_desc desc;
5511 struct i40e_aqc_add_remove_cloud_filters *cmd =
5512 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5513 enum i40e_status_code status;
5516 i40e_fill_default_direct_cmd_desc(&desc,
5517 i40e_aqc_opc_add_cloud_filters);
5519 buff_len = filter_count * sizeof(*filters);
5520 desc.datalen = CPU_TO_LE16(buff_len);
5521 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5522 cmd->num_filters = filter_count;
5523 cmd->seid = CPU_TO_LE16(seid);
5525 i40e_fix_up_geneve_vni(filters, filter_count);
5527 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5533 * i40e_aq_remove_cloud_filters
5534 * @hw: pointer to the hardware structure
5535 * @seid: VSI seid to remove cloud filters from
5536 * @filters: Buffer which contains the filters to be removed
5537 * @filter_count: number of filters contained in the buffer
5539 * Remove the cloud filters for a given VSI. The contents of the
5540 * i40e_aqc_add_remove_cloud_filters_element_data are filled
5541 * in by the caller of the function.
5544 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5546 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5549 struct i40e_aq_desc desc;
5550 struct i40e_aqc_add_remove_cloud_filters *cmd =
5551 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5552 enum i40e_status_code status;
5555 i40e_fill_default_direct_cmd_desc(&desc,
5556 i40e_aqc_opc_remove_cloud_filters);
5558 buff_len = filter_count * sizeof(*filters);
5559 desc.datalen = CPU_TO_LE16(buff_len);
5560 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5561 cmd->num_filters = filter_count;
5562 cmd->seid = CPU_TO_LE16(seid);
5564 i40e_fix_up_geneve_vni(filters, filter_count);
5566 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5572 * i40e_aq_alternate_write
5573 * @hw: pointer to the hardware structure
5574 * @reg_addr0: address of first dword to be read
5575 * @reg_val0: value to be written under 'reg_addr0'
5576 * @reg_addr1: address of second dword to be read
5577 * @reg_val1: value to be written under 'reg_addr1'
5579 * Write one or two dwords to alternate structure. Fields are indicated
5580 * by 'reg_addr0' and 'reg_addr1' register numbers.
5583 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5584 u32 reg_addr0, u32 reg_val0,
5585 u32 reg_addr1, u32 reg_val1)
5587 struct i40e_aq_desc desc;
5588 struct i40e_aqc_alternate_write *cmd_resp =
5589 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5590 enum i40e_status_code status;
5592 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5593 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5594 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5595 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5596 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5598 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5604 * i40e_aq_alternate_write_indirect
5605 * @hw: pointer to the hardware structure
5606 * @addr: address of a first register to be modified
5607 * @dw_count: number of alternate structure fields to write
5608 * @buffer: pointer to the command buffer
5610 * Write 'dw_count' dwords from 'buffer' to alternate structure
5611 * starting at 'addr'.
5614 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5615 u32 addr, u32 dw_count, void *buffer)
5617 struct i40e_aq_desc desc;
5618 struct i40e_aqc_alternate_ind_write *cmd_resp =
5619 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5620 enum i40e_status_code status;
5623 return I40E_ERR_PARAM;
5625 /* Indirect command */
5626 i40e_fill_default_direct_cmd_desc(&desc,
5627 i40e_aqc_opc_alternate_write_indirect);
5629 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5630 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5631 if (dw_count > (I40E_AQ_LARGE_BUF/4))
5632 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5634 cmd_resp->address = CPU_TO_LE32(addr);
5635 cmd_resp->length = CPU_TO_LE32(dw_count);
5637 status = i40e_asq_send_command(hw, &desc, buffer,
5638 I40E_LO_DWORD(4*dw_count), NULL);
5644 * i40e_aq_alternate_read
5645 * @hw: pointer to the hardware structure
5646 * @reg_addr0: address of first dword to be read
5647 * @reg_val0: pointer for data read from 'reg_addr0'
5648 * @reg_addr1: address of second dword to be read
5649 * @reg_val1: pointer for data read from 'reg_addr1'
5651 * Read one or two dwords from alternate structure. Fields are indicated
5652 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5653 * is not passed then only register at 'reg_addr0' is read.
5656 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5657 u32 reg_addr0, u32 *reg_val0,
5658 u32 reg_addr1, u32 *reg_val1)
5660 struct i40e_aq_desc desc;
5661 struct i40e_aqc_alternate_write *cmd_resp =
5662 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5663 enum i40e_status_code status;
5665 if (reg_val0 == NULL)
5666 return I40E_ERR_PARAM;
5668 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5669 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5670 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5672 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5674 if (status == I40E_SUCCESS) {
5675 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5677 if (reg_val1 != NULL)
5678 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5685 * i40e_aq_alternate_read_indirect
5686 * @hw: pointer to the hardware structure
5687 * @addr: address of the alternate structure field
5688 * @dw_count: number of alternate structure fields to read
5689 * @buffer: pointer to the command buffer
5691 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5692 * place them in 'buffer'. The buffer should be allocated by caller.
5695 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5696 u32 addr, u32 dw_count, void *buffer)
5698 struct i40e_aq_desc desc;
5699 struct i40e_aqc_alternate_ind_write *cmd_resp =
5700 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5701 enum i40e_status_code status;
5704 return I40E_ERR_PARAM;
5706 /* Indirect command */
5707 i40e_fill_default_direct_cmd_desc(&desc,
5708 i40e_aqc_opc_alternate_read_indirect);
5710 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5711 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5712 if (dw_count > (I40E_AQ_LARGE_BUF/4))
5713 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5715 cmd_resp->address = CPU_TO_LE32(addr);
5716 cmd_resp->length = CPU_TO_LE32(dw_count);
5718 status = i40e_asq_send_command(hw, &desc, buffer,
5719 I40E_LO_DWORD(4*dw_count), NULL);
5725 * i40e_aq_alternate_clear
5726 * @hw: pointer to the HW structure.
5728 * Clear the alternate structures of the port from which the function
5732 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5734 struct i40e_aq_desc desc;
5735 enum i40e_status_code status;
5737 i40e_fill_default_direct_cmd_desc(&desc,
5738 i40e_aqc_opc_alternate_clear_port);
5740 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5746 * i40e_aq_alternate_write_done
5747 * @hw: pointer to the HW structure.
5748 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
5749 * @reset_needed: indicates the SW should trigger GLOBAL reset
5751 * Indicates to the FW that alternate structures have been changed.
5754 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
5755 u8 bios_mode, bool *reset_needed)
5757 struct i40e_aq_desc desc;
5758 struct i40e_aqc_alternate_write_done *cmd =
5759 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5760 enum i40e_status_code status;
5762 if (reset_needed == NULL)
5763 return I40E_ERR_PARAM;
5765 i40e_fill_default_direct_cmd_desc(&desc,
5766 i40e_aqc_opc_alternate_write_done);
5768 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
5770 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5771 if (!status && reset_needed)
5772 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
5773 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
5779 * i40e_aq_set_oem_mode
5780 * @hw: pointer to the HW structure.
5781 * @oem_mode: the OEM mode to be used
5783 * Sets the device to a specific operating mode. Currently the only supported
5784 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
5787 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
5790 struct i40e_aq_desc desc;
5791 struct i40e_aqc_alternate_write_done *cmd =
5792 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5793 enum i40e_status_code status;
5795 i40e_fill_default_direct_cmd_desc(&desc,
5796 i40e_aqc_opc_alternate_set_mode);
5798 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
5800 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5806 * i40e_aq_resume_port_tx
5807 * @hw: pointer to the hardware structure
5808 * @cmd_details: pointer to command details structure or NULL
5810 * Resume port's Tx traffic
5812 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
5813 struct i40e_asq_cmd_details *cmd_details)
5815 struct i40e_aq_desc desc;
5816 enum i40e_status_code status;
5818 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
5820 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5826 * i40e_set_pci_config_data - store PCI bus info
5827 * @hw: pointer to hardware structure
5828 * @link_status: the link status word from PCI config space
5830 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
5832 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
5834 hw->bus.type = i40e_bus_type_pci_express;
5836 switch (link_status & I40E_PCI_LINK_WIDTH) {
5837 case I40E_PCI_LINK_WIDTH_1:
5838 hw->bus.width = i40e_bus_width_pcie_x1;
5840 case I40E_PCI_LINK_WIDTH_2:
5841 hw->bus.width = i40e_bus_width_pcie_x2;
5843 case I40E_PCI_LINK_WIDTH_4:
5844 hw->bus.width = i40e_bus_width_pcie_x4;
5846 case I40E_PCI_LINK_WIDTH_8:
5847 hw->bus.width = i40e_bus_width_pcie_x8;
5850 hw->bus.width = i40e_bus_width_unknown;
5854 switch (link_status & I40E_PCI_LINK_SPEED) {
5855 case I40E_PCI_LINK_SPEED_2500:
5856 hw->bus.speed = i40e_bus_speed_2500;
5858 case I40E_PCI_LINK_SPEED_5000:
5859 hw->bus.speed = i40e_bus_speed_5000;
5861 case I40E_PCI_LINK_SPEED_8000:
5862 hw->bus.speed = i40e_bus_speed_8000;
5865 hw->bus.speed = i40e_bus_speed_unknown;
5871 * i40e_aq_debug_dump
5872 * @hw: pointer to the hardware structure
5873 * @cluster_id: specific cluster to dump
5874 * @table_id: table id within cluster
5875 * @start_index: index of line in the block to read
5876 * @buff_size: dump buffer size
5877 * @buff: dump buffer
5878 * @ret_buff_size: actual buffer size returned
5879 * @ret_next_table: next block to read
5880 * @ret_next_index: next index to read
5882 * Dump internal FW/HW data for debug purposes.
5885 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
5886 u8 table_id, u32 start_index, u16 buff_size,
5887 void *buff, u16 *ret_buff_size,
5888 u8 *ret_next_table, u32 *ret_next_index,
5889 struct i40e_asq_cmd_details *cmd_details)
5891 struct i40e_aq_desc desc;
5892 struct i40e_aqc_debug_dump_internals *cmd =
5893 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5894 struct i40e_aqc_debug_dump_internals *resp =
5895 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5896 enum i40e_status_code status;
5898 if (buff_size == 0 || !buff)
5899 return I40E_ERR_PARAM;
5901 i40e_fill_default_direct_cmd_desc(&desc,
5902 i40e_aqc_opc_debug_dump_internals);
5903 /* Indirect Command */
5904 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5905 if (buff_size > I40E_AQ_LARGE_BUF)
5906 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5908 cmd->cluster_id = cluster_id;
5909 cmd->table_id = table_id;
5910 cmd->idx = CPU_TO_LE32(start_index);
5912 desc.datalen = CPU_TO_LE16(buff_size);
5914 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5916 if (ret_buff_size != NULL)
5917 *ret_buff_size = LE16_TO_CPU(desc.datalen);
5918 if (ret_next_table != NULL)
5919 *ret_next_table = resp->table_id;
5920 if (ret_next_index != NULL)
5921 *ret_next_index = LE32_TO_CPU(resp->idx);
5928 * i40e_read_bw_from_alt_ram
5929 * @hw: pointer to the hardware structure
5930 * @max_bw: pointer for max_bw read
5931 * @min_bw: pointer for min_bw read
5932 * @min_valid: pointer for bool that is true if min_bw is a valid value
5933 * @max_valid: pointer for bool that is true if max_bw is a valid value
5935 * Read bw from the alternate ram for the given pf
5937 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
5938 u32 *max_bw, u32 *min_bw,
5939 bool *min_valid, bool *max_valid)
5941 enum i40e_status_code status;
5942 u32 max_bw_addr, min_bw_addr;
5944 /* Calculate the address of the min/max bw registers */
5945 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5946 I40E_ALT_STRUCT_MAX_BW_OFFSET +
5947 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5948 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5949 I40E_ALT_STRUCT_MIN_BW_OFFSET +
5950 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5952 /* Read the bandwidths from alt ram */
5953 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
5954 min_bw_addr, min_bw);
5956 if (*min_bw & I40E_ALT_BW_VALID_MASK)
5961 if (*max_bw & I40E_ALT_BW_VALID_MASK)
5970 * i40e_aq_configure_partition_bw
5971 * @hw: pointer to the hardware structure
5972 * @bw_data: Buffer holding valid pfs and bw limits
5973 * @cmd_details: pointer to command details
5975 * Configure partitions guaranteed/max bw
5977 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
5978 struct i40e_aqc_configure_partition_bw_data *bw_data,
5979 struct i40e_asq_cmd_details *cmd_details)
5981 enum i40e_status_code status;
5982 struct i40e_aq_desc desc;
5983 u16 bwd_size = sizeof(*bw_data);
5985 i40e_fill_default_direct_cmd_desc(&desc,
5986 i40e_aqc_opc_configure_partition_bw);
5988 /* Indirect command */
5989 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5990 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5992 if (bwd_size > I40E_AQ_LARGE_BUF)
5993 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5995 desc.datalen = CPU_TO_LE16(bwd_size);
5997 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6003 * i40e_read_phy_register
6004 * @hw: pointer to the HW structure
6005 * @page: registers page number
6006 * @reg: register address in the page
6007 * @phy_adr: PHY address on MDIO interface
6008 * @value: PHY register value
6010 * Reads specified PHY register value
6012 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6013 u8 page, u16 reg, u8 phy_addr,
6016 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6019 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6021 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6022 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6023 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6024 (I40E_MDIO_OPCODE_ADDRESS) |
6025 (I40E_MDIO_STCODE) |
6026 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6027 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6028 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6030 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6031 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6032 status = I40E_SUCCESS;
6035 i40e_usec_delay(10);
6040 i40e_debug(hw, I40E_DEBUG_PHY,
6041 "PHY: Can't write command to external PHY.\n");
6045 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6046 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6047 (I40E_MDIO_OPCODE_READ) |
6048 (I40E_MDIO_STCODE) |
6049 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6050 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6051 status = I40E_ERR_TIMEOUT;
6053 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6055 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6056 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6057 status = I40E_SUCCESS;
6060 i40e_usec_delay(10);
6065 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6066 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6067 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6069 i40e_debug(hw, I40E_DEBUG_PHY,
6070 "PHY: Can't read register value from external PHY.\n");
6078 * i40e_write_phy_register
6079 * @hw: pointer to the HW structure
6080 * @page: registers page number
6081 * @reg: register address in the page
6082 * @phy_adr: PHY address on MDIO interface
6083 * @value: PHY register value
6085 * Writes value to specified PHY register
6087 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6088 u8 page, u16 reg, u8 phy_addr,
6091 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6094 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6096 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6097 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6098 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6099 (I40E_MDIO_OPCODE_ADDRESS) |
6100 (I40E_MDIO_STCODE) |
6101 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6102 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6103 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6105 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6106 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6107 status = I40E_SUCCESS;
6110 i40e_usec_delay(10);
6114 i40e_debug(hw, I40E_DEBUG_PHY,
6115 "PHY: Can't write command to external PHY.\n");
6119 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6120 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6122 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6123 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6124 (I40E_MDIO_OPCODE_WRITE) |
6125 (I40E_MDIO_STCODE) |
6126 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6127 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6128 status = I40E_ERR_TIMEOUT;
6130 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6132 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6133 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6134 status = I40E_SUCCESS;
6137 i40e_usec_delay(10);
6146 * i40e_get_phy_address
6147 * @hw: pointer to the HW structure
6148 * @dev_num: PHY port num that address we want
6149 * @phy_addr: Returned PHY address
6151 * Gets PHY address for current port
6153 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6155 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6156 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6158 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6162 * i40e_blink_phy_led
6163 * @hw: pointer to the HW structure
6164 * @time: time how long led will blinks in secs
6165 * @interval: gap between LED on and off in msecs
6167 * Blinks PHY link LED
6169 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6170 u32 time, u32 interval)
6172 enum i40e_status_code status = I40E_SUCCESS;
6177 u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6181 i = rd32(hw, I40E_PFGEN_PORTNUM);
6182 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6183 phy_addr = i40e_get_phy_address(hw, port_num);
6185 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6187 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6188 led_addr, phy_addr, &led_reg);
6190 goto phy_blinking_end;
6192 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6194 status = i40e_write_phy_register(hw,
6195 I40E_PHY_COM_REG_PAGE,
6199 goto phy_blinking_end;
6204 if (time > 0 && interval > 0) {
6205 for (i = 0; i < time * 1000; i += interval) {
6206 status = i40e_read_phy_register(hw,
6207 I40E_PHY_COM_REG_PAGE,
6211 goto restore_config;
6212 if (led_reg & I40E_PHY_LED_MANUAL_ON)
6215 led_reg = I40E_PHY_LED_MANUAL_ON;
6216 status = i40e_write_phy_register(hw,
6217 I40E_PHY_COM_REG_PAGE,
6221 goto restore_config;
6222 i40e_msec_delay(interval);
6227 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6235 * i40e_led_get_phy - return current on/off mode
6236 * @hw: pointer to the hw struct
6237 * @led_addr: address of led register to use
6238 * @val: original value of register to use
6241 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6244 enum i40e_status_code status = I40E_SUCCESS;
6252 temp_addr = I40E_PHY_LED_PROV_REG_1;
6253 i = rd32(hw, I40E_PFGEN_PORTNUM);
6254 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6255 phy_addr = i40e_get_phy_address(hw, port_num);
6257 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6259 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6260 temp_addr, phy_addr, ®_val);
6264 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6265 *led_addr = temp_addr;
6274 * @hw: pointer to the HW structure
6275 * @on: true or false
6276 * @mode: original val plus bit for set or ignore
6277 * Set led's on or off when controlled by the PHY
6280 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6281 u16 led_addr, u32 mode)
6283 enum i40e_status_code status = I40E_SUCCESS;
6290 i = rd32(hw, I40E_PFGEN_PORTNUM);
6291 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6292 phy_addr = i40e_get_phy_address(hw, port_num);
6294 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6295 phy_addr, &led_reg);
6299 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6301 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6302 led_addr, phy_addr, led_reg);
6306 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6307 led_addr, phy_addr, &led_reg);
6309 goto restore_config;
6311 led_reg = I40E_PHY_LED_MANUAL_ON;
6314 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6315 led_addr, phy_addr, led_reg);
6317 goto restore_config;
6318 if (mode & I40E_PHY_LED_MODE_ORIG) {
6319 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6320 status = i40e_write_phy_register(hw,
6321 I40E_PHY_COM_REG_PAGE,
6322 led_addr, phy_addr, led_ctl);
6326 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6330 #endif /* PF_DRIVER */
6333 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6334 * @hw: pointer to the hw struct
6335 * @reg_addr: register address
6336 * @reg_val: ptr to register value
6337 * @cmd_details: pointer to command details structure or NULL
6339 * Use the firmware to read the Rx control register,
6340 * especially useful if the Rx unit is under heavy pressure
6342 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6343 u32 reg_addr, u32 *reg_val,
6344 struct i40e_asq_cmd_details *cmd_details)
6346 struct i40e_aq_desc desc;
6347 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
6348 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6349 enum i40e_status_code status;
6351 if (reg_val == NULL)
6352 return I40E_ERR_PARAM;
6354 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
6356 cmd_resp->address = CPU_TO_LE32(reg_addr);
6358 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6360 if (status == I40E_SUCCESS)
6361 *reg_val = LE32_TO_CPU(cmd_resp->value);
6367 * i40e_read_rx_ctl - read from an Rx control register
6368 * @hw: pointer to the hw struct
6369 * @reg_addr: register address
6371 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
6373 enum i40e_status_code status = I40E_SUCCESS;
6378 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6379 if (!use_register) {
6381 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
6382 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6389 /* if the AQ access failed, try the old-fashioned way */
6390 if (status || use_register)
6391 val = rd32(hw, reg_addr);
6397 * i40e_aq_rx_ctl_write_register
6398 * @hw: pointer to the hw struct
6399 * @reg_addr: register address
6400 * @reg_val: register value
6401 * @cmd_details: pointer to command details structure or NULL
6403 * Use the firmware to write to an Rx control register,
6404 * especially useful if the Rx unit is under heavy pressure
6406 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
6407 u32 reg_addr, u32 reg_val,
6408 struct i40e_asq_cmd_details *cmd_details)
6410 struct i40e_aq_desc desc;
6411 struct i40e_aqc_rx_ctl_reg_read_write *cmd =
6412 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6413 enum i40e_status_code status;
6415 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
6417 cmd->address = CPU_TO_LE32(reg_addr);
6418 cmd->value = CPU_TO_LE32(reg_val);
6420 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6426 * i40e_write_rx_ctl - write to an Rx control register
6427 * @hw: pointer to the hw struct
6428 * @reg_addr: register address
6429 * @reg_val: register value
6431 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
6433 enum i40e_status_code status = I40E_SUCCESS;
6437 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6438 if (!use_register) {
6440 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
6442 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6449 /* if the AQ access failed, try the old-fashioned way */
6450 if (status || use_register)
6451 wr32(hw, reg_addr, reg_val);
6456 * i40e_aq_send_msg_to_pf
6457 * @hw: pointer to the hardware structure
6458 * @v_opcode: opcodes for VF-PF communication
6459 * @v_retval: return error code
6460 * @msg: pointer to the msg buffer
6461 * @msglen: msg length
6462 * @cmd_details: pointer to command details
6464 * Send message to PF driver using admin queue. By default, this message
6465 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
6466 * completion before returning.
6468 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
6469 enum i40e_virtchnl_ops v_opcode,
6470 enum i40e_status_code v_retval,
6471 u8 *msg, u16 msglen,
6472 struct i40e_asq_cmd_details *cmd_details)
6474 struct i40e_aq_desc desc;
6475 struct i40e_asq_cmd_details details;
6476 enum i40e_status_code status;
6478 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
6479 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
6480 desc.cookie_high = CPU_TO_LE32(v_opcode);
6481 desc.cookie_low = CPU_TO_LE32(v_retval);
6483 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
6484 | I40E_AQ_FLAG_RD));
6485 if (msglen > I40E_AQ_LARGE_BUF)
6486 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6487 desc.datalen = CPU_TO_LE16(msglen);
6490 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
6491 details.async = true;
6492 cmd_details = &details;
6494 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
6495 msglen, cmd_details);
6500 * i40e_vf_parse_hw_config
6501 * @hw: pointer to the hardware structure
6502 * @msg: pointer to the virtual channel VF resource structure
6504 * Given a VF resource message from the PF, populate the hw struct
6505 * with appropriate information.
6507 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
6508 struct i40e_virtchnl_vf_resource *msg)
6510 struct i40e_virtchnl_vsi_resource *vsi_res;
6513 vsi_res = &msg->vsi_res[0];
6515 hw->dev_caps.num_vsis = msg->num_vsis;
6516 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
6517 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
6518 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
6519 hw->dev_caps.dcb = msg->vf_offload_flags &
6520 I40E_VIRTCHNL_VF_OFFLOAD_L2;
6521 hw->dev_caps.fcoe = (msg->vf_offload_flags &
6522 I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
6523 hw->dev_caps.iwarp = (msg->vf_offload_flags &
6524 I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
6525 for (i = 0; i < msg->num_vsis; i++) {
6526 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
6527 i40e_memcpy(hw->mac.perm_addr,
6528 vsi_res->default_mac_addr,
6529 I40E_ETH_LENGTH_OF_ADDRESS,
6530 I40E_NONDMA_TO_NONDMA);
6531 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
6532 I40E_ETH_LENGTH_OF_ADDRESS,
6533 I40E_NONDMA_TO_NONDMA);
6541 * @hw: pointer to the hardware structure
6543 * Send a VF_RESET message to the PF. Does not wait for response from PF
6544 * as none will be forthcoming. Immediately after calling this function,
6545 * the admin queue should be shut down and (optionally) reinitialized.
6547 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
6549 return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
6550 I40E_SUCCESS, NULL, 0, NULL);
6552 #endif /* VF_DRIVER */
6556 * i40e_aq_set_arp_proxy_config
6557 * @hw: pointer to the HW structure
6558 * @proxy_config - pointer to proxy config command table struct
6559 * @cmd_details: pointer to command details
6561 * Set ARP offload parameters from pre-populated
6562 * i40e_aqc_arp_proxy_data struct
6564 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
6565 struct i40e_aqc_arp_proxy_data *proxy_config,
6566 struct i40e_asq_cmd_details *cmd_details)
6568 struct i40e_aq_desc desc;
6569 enum i40e_status_code status;
6572 return I40E_ERR_PARAM;
6574 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
6576 desc.params.external.addr_high =
6577 CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
6578 desc.params.external.addr_low =
6579 CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
6581 status = i40e_asq_send_command(hw, &desc, proxy_config,
6582 sizeof(struct i40e_aqc_arp_proxy_data),
6589 * i40e_aq_opc_set_ns_proxy_table_entry
6590 * @hw: pointer to the HW structure
6591 * @ns_proxy_table_entry: pointer to NS table entry command struct
6592 * @cmd_details: pointer to command details
6594 * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
6595 * from pre-populated i40e_aqc_ns_proxy_data struct
6597 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
6598 struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
6599 struct i40e_asq_cmd_details *cmd_details)
6601 struct i40e_aq_desc desc;
6602 enum i40e_status_code status;
6604 if (!ns_proxy_table_entry)
6605 return I40E_ERR_PARAM;
6607 i40e_fill_default_direct_cmd_desc(&desc,
6608 i40e_aqc_opc_set_ns_proxy_table_entry);
6610 desc.params.external.addr_high =
6611 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
6612 desc.params.external.addr_low =
6613 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
6615 status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
6616 sizeof(struct i40e_aqc_ns_proxy_data),
6623 * i40e_aq_set_clear_wol_filter
6624 * @hw: pointer to the hw struct
6625 * @filter_index: index of filter to modify (0-7)
6626 * @filter: buffer containing filter to be set
6627 * @set_filter: true to set filter, false to clear filter
6628 * @no_wol_tco: if true, pass through packets cannot cause wake-up
6629 * if false, pass through packets may cause wake-up
6630 * @filter_valid: true if filter action is valid
6631 * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
6632 * @cmd_details: pointer to command details structure or NULL
6634 * Set or clear WoL filter for port attached to the PF
6636 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
6638 struct i40e_aqc_set_wol_filter_data *filter,
6639 bool set_filter, bool no_wol_tco,
6640 bool filter_valid, bool no_wol_tco_valid,
6641 struct i40e_asq_cmd_details *cmd_details)
6643 struct i40e_aq_desc desc;
6644 struct i40e_aqc_set_wol_filter *cmd =
6645 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
6646 enum i40e_status_code status;
6648 u16 valid_flags = 0;
6651 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
6653 if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
6654 return I40E_ERR_PARAM;
6655 cmd->filter_index = CPU_TO_LE16(filter_index);
6659 return I40E_ERR_PARAM;
6660 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
6661 buff_len = sizeof(*filter);
6664 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
6665 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
6668 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
6669 if (no_wol_tco_valid)
6670 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
6671 cmd->valid_flags = CPU_TO_LE16(valid_flags);
6673 cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
6674 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
6676 status = i40e_asq_send_command(hw, &desc, filter,
6677 buff_len, cmd_details);
6683 * i40e_aq_get_wake_event_reason
6684 * @hw: pointer to the hw struct
6685 * @wake_reason: return value, index of matching filter
6686 * @cmd_details: pointer to command details structure or NULL
6688 * Get information for the reason of a Wake Up event
6690 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
6692 struct i40e_asq_cmd_details *cmd_details)
6694 struct i40e_aq_desc desc;
6695 struct i40e_aqc_get_wake_reason_completion *resp =
6696 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
6697 enum i40e_status_code status;
6699 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
6701 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6703 if (status == I40E_SUCCESS)
6704 *wake_reason = LE16_TO_CPU(resp->wake_reason);
6709 #endif /* X722_SUPPORT */