drivers/net/i40e/base/i40e_common.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "i40e_type.h"
  35 #include "i40e_adminq.h"
  36 #include "i40e_prototype.h"
  37 #include "i40e_virtchnl.h"
  38
  39
  40 /**
  41  * i40e_set_mac_type - Sets MAC type
  42  * @hw: pointer to the HW structure
  43  *
  44  * This function sets the mac type of the adapter based on the
  45  * vendor ID and device ID stored in the hw structure.
  46  **/
  47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  49 #else
  50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  51 #endif
  52 {
  53         enum i40e_status_code status = I40E_SUCCESS;
  54
  55         DEBUGFUNC("i40e_set_mac_type\n");
  56
  57         if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
  58                 switch (hw->device_id) {
  59                 case I40E_DEV_ID_SFP_XL710:
  60                 case I40E_DEV_ID_QEMU:
  61                 case I40E_DEV_ID_KX_B:
  62                 case I40E_DEV_ID_KX_C:
  63                 case I40E_DEV_ID_QSFP_A:
  64                 case I40E_DEV_ID_QSFP_B:
  65                 case I40E_DEV_ID_QSFP_C:
  66                 case I40E_DEV_ID_10G_BASE_T:
  67                 case I40E_DEV_ID_10G_BASE_T4:
  68                 case I40E_DEV_ID_20G_KR2:
  69                 case I40E_DEV_ID_20G_KR2_A:
  70                         hw->mac.type = I40E_MAC_XL710;
  71                         break;
  72 #ifdef X722_SUPPORT
  73 #ifdef X722_A0_SUPPORT
  74                 case I40E_DEV_ID_X722_A0:
  75 #endif
  76                 case I40E_DEV_ID_KX_X722:
  77                 case I40E_DEV_ID_QSFP_X722:
  78                 case I40E_DEV_ID_SFP_X722:
  79                 case I40E_DEV_ID_1G_BASE_T_X722:
  80                 case I40E_DEV_ID_10G_BASE_T_X722:
  81                         hw->mac.type = I40E_MAC_X722;
  82                         break;
  83 #endif
  84 #ifdef X722_SUPPORT
  85 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  86                 case I40E_DEV_ID_X722_VF:
  87                 case I40E_DEV_ID_X722_VF_HV:
  88 #ifdef X722_A0_SUPPORT
  89                 case I40E_DEV_ID_X722_A0_VF:
  90 #endif
  91                         hw->mac.type = I40E_MAC_X722_VF;
  92                         break;
  93 #endif /* INTEGRATED_VF || VF_DRIVER */
  94 #endif /* X722_SUPPORT */
  95 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  96                 case I40E_DEV_ID_VF:
  97                 case I40E_DEV_ID_VF_HV:
  98                         hw->mac.type = I40E_MAC_VF;
  99                         break;
 100 #endif
 101                 default:
 102                         hw->mac.type = I40E_MAC_GENERIC;
 103                         break;
 104                 }
 105         } else {
 106                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
 107         }
 108
 109         DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
 110                   hw->mac.type, status);
 111         return status;
 112 }
 113
 114 #ifndef I40E_NDIS_SUPPORT
 115 /**
 116  * i40e_aq_str - convert AQ err code to a string
 117  * @hw: pointer to the HW structure
 118  * @aq_err: the AQ error code to convert
 119  **/
 120 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
 121 {
 122         switch (aq_err) {
 123         case I40E_AQ_RC_OK:
 124                 return "OK";
 125         case I40E_AQ_RC_EPERM:
 126                 return "I40E_AQ_RC_EPERM";
 127         case I40E_AQ_RC_ENOENT:
 128                 return "I40E_AQ_RC_ENOENT";
 129         case I40E_AQ_RC_ESRCH:
 130                 return "I40E_AQ_RC_ESRCH";
 131         case I40E_AQ_RC_EINTR:
 132                 return "I40E_AQ_RC_EINTR";
 133         case I40E_AQ_RC_EIO:
 134                 return "I40E_AQ_RC_EIO";
 135         case I40E_AQ_RC_ENXIO:
 136                 return "I40E_AQ_RC_ENXIO";
 137         case I40E_AQ_RC_E2BIG:
 138                 return "I40E_AQ_RC_E2BIG";
 139         case I40E_AQ_RC_EAGAIN:
 140                 return "I40E_AQ_RC_EAGAIN";
 141         case I40E_AQ_RC_ENOMEM:
 142                 return "I40E_AQ_RC_ENOMEM";
 143         case I40E_AQ_RC_EACCES:
 144                 return "I40E_AQ_RC_EACCES";
 145         case I40E_AQ_RC_EFAULT:
 146                 return "I40E_AQ_RC_EFAULT";
 147         case I40E_AQ_RC_EBUSY:
 148                 return "I40E_AQ_RC_EBUSY";
 149         case I40E_AQ_RC_EEXIST:
 150                 return "I40E_AQ_RC_EEXIST";
 151         case I40E_AQ_RC_EINVAL:
 152                 return "I40E_AQ_RC_EINVAL";
 153         case I40E_AQ_RC_ENOTTY:
 154                 return "I40E_AQ_RC_ENOTTY";
 155         case I40E_AQ_RC_ENOSPC:
 156                 return "I40E_AQ_RC_ENOSPC";
 157         case I40E_AQ_RC_ENOSYS:
 158                 return "I40E_AQ_RC_ENOSYS";
 159         case I40E_AQ_RC_ERANGE:
 160                 return "I40E_AQ_RC_ERANGE";
 161         case I40E_AQ_RC_EFLUSHED:
 162                 return "I40E_AQ_RC_EFLUSHED";
 163         case I40E_AQ_RC_BAD_ADDR:
 164                 return "I40E_AQ_RC_BAD_ADDR";
 165         case I40E_AQ_RC_EMODE:
 166                 return "I40E_AQ_RC_EMODE";
 167         case I40E_AQ_RC_EFBIG:
 168                 return "I40E_AQ_RC_EFBIG";
 169         }
 170
 171         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 172         return hw->err_str;
 173 }
 174
 175 /**
 176  * i40e_stat_str - convert status err code to a string
 177  * @hw: pointer to the HW structure
 178  * @stat_err: the status error code to convert
 179  **/
 180 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
 181 {
 182         switch (stat_err) {
 183         case I40E_SUCCESS:
 184                 return "OK";
 185         case I40E_ERR_NVM:
 186                 return "I40E_ERR_NVM";
 187         case I40E_ERR_NVM_CHECKSUM:
 188                 return "I40E_ERR_NVM_CHECKSUM";
 189         case I40E_ERR_PHY:
 190                 return "I40E_ERR_PHY";
 191         case I40E_ERR_CONFIG:
 192                 return "I40E_ERR_CONFIG";
 193         case I40E_ERR_PARAM:
 194                 return "I40E_ERR_PARAM";
 195         case I40E_ERR_MAC_TYPE:
 196                 return "I40E_ERR_MAC_TYPE";
 197         case I40E_ERR_UNKNOWN_PHY:
 198                 return "I40E_ERR_UNKNOWN_PHY";
 199         case I40E_ERR_LINK_SETUP:
 200                 return "I40E_ERR_LINK_SETUP";
 201         case I40E_ERR_ADAPTER_STOPPED:
 202                 return "I40E_ERR_ADAPTER_STOPPED";
 203         case I40E_ERR_INVALID_MAC_ADDR:
 204                 return "I40E_ERR_INVALID_MAC_ADDR";
 205         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 206                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 207         case I40E_ERR_MASTER_REQUESTS_PENDING:
 208                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 209         case I40E_ERR_INVALID_LINK_SETTINGS:
 210                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 211         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 212                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 213         case I40E_ERR_RESET_FAILED:
 214                 return "I40E_ERR_RESET_FAILED";
 215         case I40E_ERR_SWFW_SYNC:
 216                 return "I40E_ERR_SWFW_SYNC";
 217         case I40E_ERR_NO_AVAILABLE_VSI:
 218                 return "I40E_ERR_NO_AVAILABLE_VSI";
 219         case I40E_ERR_NO_MEMORY:
 220                 return "I40E_ERR_NO_MEMORY";
 221         case I40E_ERR_BAD_PTR:
 222                 return "I40E_ERR_BAD_PTR";
 223         case I40E_ERR_RING_FULL:
 224                 return "I40E_ERR_RING_FULL";
 225         case I40E_ERR_INVALID_PD_ID:
 226                 return "I40E_ERR_INVALID_PD_ID";
 227         case I40E_ERR_INVALID_QP_ID:
 228                 return "I40E_ERR_INVALID_QP_ID";
 229         case I40E_ERR_INVALID_CQ_ID:
 230                 return "I40E_ERR_INVALID_CQ_ID";
 231         case I40E_ERR_INVALID_CEQ_ID:
 232                 return "I40E_ERR_INVALID_CEQ_ID";
 233         case I40E_ERR_INVALID_AEQ_ID:
 234                 return "I40E_ERR_INVALID_AEQ_ID";
 235         case I40E_ERR_INVALID_SIZE:
 236                 return "I40E_ERR_INVALID_SIZE";
 237         case I40E_ERR_INVALID_ARP_INDEX:
 238                 return "I40E_ERR_INVALID_ARP_INDEX";
 239         case I40E_ERR_INVALID_FPM_FUNC_ID:
 240                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 241         case I40E_ERR_QP_INVALID_MSG_SIZE:
 242                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 243         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 244                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 245         case I40E_ERR_INVALID_FRAG_COUNT:
 246                 return "I40E_ERR_INVALID_FRAG_COUNT";
 247         case I40E_ERR_QUEUE_EMPTY:
 248                 return "I40E_ERR_QUEUE_EMPTY";
 249         case I40E_ERR_INVALID_ALIGNMENT:
 250                 return "I40E_ERR_INVALID_ALIGNMENT";
 251         case I40E_ERR_FLUSHED_QUEUE:
 252                 return "I40E_ERR_FLUSHED_QUEUE";
 253         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 254                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 255         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 256                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 257         case I40E_ERR_TIMEOUT:
 258                 return "I40E_ERR_TIMEOUT";
 259         case I40E_ERR_OPCODE_MISMATCH:
 260                 return "I40E_ERR_OPCODE_MISMATCH";
 261         case I40E_ERR_CQP_COMPL_ERROR:
 262                 return "I40E_ERR_CQP_COMPL_ERROR";
 263         case I40E_ERR_INVALID_VF_ID:
 264                 return "I40E_ERR_INVALID_VF_ID";
 265         case I40E_ERR_INVALID_HMCFN_ID:
 266                 return "I40E_ERR_INVALID_HMCFN_ID";
 267         case I40E_ERR_BACKING_PAGE_ERROR:
 268                 return "I40E_ERR_BACKING_PAGE_ERROR";
 269         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 270                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 271         case I40E_ERR_INVALID_PBLE_INDEX:
 272                 return "I40E_ERR_INVALID_PBLE_INDEX";
 273         case I40E_ERR_INVALID_SD_INDEX:
 274                 return "I40E_ERR_INVALID_SD_INDEX";
 275         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 276                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 277         case I40E_ERR_INVALID_SD_TYPE:
 278                 return "I40E_ERR_INVALID_SD_TYPE";
 279         case I40E_ERR_MEMCPY_FAILED:
 280                 return "I40E_ERR_MEMCPY_FAILED";
 281         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 282                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 283         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 284                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 285         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 286                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 287         case I40E_ERR_SRQ_ENABLED:
 288                 return "I40E_ERR_SRQ_ENABLED";
 289         case I40E_ERR_ADMIN_QUEUE_ERROR:
 290                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 291         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 292                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 293         case I40E_ERR_BUF_TOO_SHORT:
 294                 return "I40E_ERR_BUF_TOO_SHORT";
 295         case I40E_ERR_ADMIN_QUEUE_FULL:
 296                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 297         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 298                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 299         case I40E_ERR_BAD_IWARP_CQE:
 300                 return "I40E_ERR_BAD_IWARP_CQE";
 301         case I40E_ERR_NVM_BLANK_MODE:
 302                 return "I40E_ERR_NVM_BLANK_MODE";
 303         case I40E_ERR_NOT_IMPLEMENTED:
 304                 return "I40E_ERR_NOT_IMPLEMENTED";
 305         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 306                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 307         case I40E_ERR_DIAG_TEST_FAILED:
 308                 return "I40E_ERR_DIAG_TEST_FAILED";
 309         case I40E_ERR_NOT_READY:
 310                 return "I40E_ERR_NOT_READY";
 311         case I40E_NOT_SUPPORTED:
 312                 return "I40E_NOT_SUPPORTED";
 313         case I40E_ERR_FIRMWARE_API_VERSION:
 314                 return "I40E_ERR_FIRMWARE_API_VERSION";
 315         }
 316
 317         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 318         return hw->err_str;
 319 }
 320
 321 #endif /* I40E_NDIS_SUPPORT */
 322 /**
 323  * i40e_debug_aq
 324  * @hw: debug mask related to admin queue
 325  * @mask: debug mask
 326  * @desc: pointer to admin queue descriptor
 327  * @buffer: pointer to command buffer
 328  * @buf_len: max length of buffer
 329  *
 330  * Dumps debug log about adminq command with descriptor contents.
 331  **/
 332 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 333                    void *buffer, u16 buf_len)
 334 {
 335         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 336         u16 len = LE16_TO_CPU(aq_desc->datalen);
 337         u8 *buf = (u8 *)buffer;
 338         u16 i = 0;
 339
 340         if ((!(mask & hw->debug_mask)) || (desc == NULL))
 341                 return;
 342
 343         i40e_debug(hw, mask,
 344                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 345                    LE16_TO_CPU(aq_desc->opcode),
 346                    LE16_TO_CPU(aq_desc->flags),
 347                    LE16_TO_CPU(aq_desc->datalen),
 348                    LE16_TO_CPU(aq_desc->retval));
 349         i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
 350                    LE32_TO_CPU(aq_desc->cookie_high),
 351                    LE32_TO_CPU(aq_desc->cookie_low));
 352         i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
 353                    LE32_TO_CPU(aq_desc->params.internal.param0),
 354                    LE32_TO_CPU(aq_desc->params.internal.param1));
 355         i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
 356                    LE32_TO_CPU(aq_desc->params.external.addr_high),
 357                    LE32_TO_CPU(aq_desc->params.external.addr_low));
 358
 359         if ((buffer != NULL) && (aq_desc->datalen != 0)) {
 360                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 361                 if (buf_len < len)
 362                         len = buf_len;
 363                 /* write the full 16-byte chunks */
 364                 for (i = 0; i < (len - 16); i += 16)
 365                         i40e_debug(hw, mask,
 366                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 367                                    i, buf[i], buf[i+1], buf[i+2], buf[i+3],
 368                                    buf[i+4], buf[i+5], buf[i+6], buf[i+7],
 369                                    buf[i+8], buf[i+9], buf[i+10], buf[i+11],
 370                                    buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
 371                 /* the most we could have left is 16 bytes, pad with zeros */
 372                 if (i < len) {
 373                         char d_buf[16];
 374                         int j;
 375
 376                         memset(d_buf, 0, sizeof(d_buf));
 377                         for (j = 0; i < len; j++, i++)
 378                                 d_buf[j] = buf[i];
 379                         i40e_debug(hw, mask,
 380                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 381                                    i, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
 382                                    d_buf[4], d_buf[5], d_buf[6], d_buf[7],
 383                                    d_buf[8], d_buf[9], d_buf[10], d_buf[11],
 384                                    d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
 385                 }
 386         }
 387 }
 388
 389 /**
 390  * i40e_check_asq_alive
 391  * @hw: pointer to the hw struct
 392  *
 393  * Returns true if Queue is enabled else false.
 394  **/
 395 bool i40e_check_asq_alive(struct i40e_hw *hw)
 396 {
 397         if (hw->aq.asq.len)
 398 #ifdef PF_DRIVER
 399 #ifdef INTEGRATED_VF
 400                 if (!i40e_is_vf(hw))
 401                         return !!(rd32(hw, hw->aq.asq.len) &
 402                                 I40E_PF_ATQLEN_ATQENABLE_MASK);
 403 #else
 404                 return !!(rd32(hw, hw->aq.asq.len) &
 405                         I40E_PF_ATQLEN_ATQENABLE_MASK);
 406 #endif /* INTEGRATED_VF */
 407 #endif /* PF_DRIVER */
 408 #ifdef VF_DRIVER
 409 #ifdef INTEGRATED_VF
 410                 if (i40e_is_vf(hw))
 411                         return !!(rd32(hw, hw->aq.asq.len) &
 412                                 I40E_VF_ATQLEN1_ATQENABLE_MASK);
 413 #else
 414                 return !!(rd32(hw, hw->aq.asq.len) &
 415                         I40E_VF_ATQLEN1_ATQENABLE_MASK);
 416 #endif /* INTEGRATED_VF */
 417 #endif /* VF_DRIVER */
 418         return false;
 419 }
 420
 421 /**
 422  * i40e_aq_queue_shutdown
 423  * @hw: pointer to the hw struct
 424  * @unloading: is the driver unloading itself
 425  *
 426  * Tell the Firmware that we're shutting down the AdminQ and whether
 427  * or not the driver is unloading as well.
 428  **/
 429 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
 430                                              bool unloading)
 431 {
 432         struct i40e_aq_desc desc;
 433         struct i40e_aqc_queue_shutdown *cmd =
 434                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 435         enum i40e_status_code status;
 436
 437         i40e_fill_default_direct_cmd_desc(&desc,
 438                                           i40e_aqc_opc_queue_shutdown);
 439
 440         if (unloading)
 441                 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
 442         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 443
 444         return status;
 445 }
 446 #ifdef X722_SUPPORT
 447
 448 /**
 449  * i40e_aq_get_set_rss_lut
 450  * @hw: pointer to the hardware structure
 451  * @vsi_id: vsi fw index
 452  * @pf_lut: for PF table set true, for VSI table set false
 453  * @lut: pointer to the lut buffer provided by the caller
 454  * @lut_size: size of the lut buffer
 455  * @set: set true to set the table, false to get the table
 456  *
 457  * Internal function to get or set RSS look up table
 458  **/
 459 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 460                                                      u16 vsi_id, bool pf_lut,
 461                                                      u8 *lut, u16 lut_size,
 462                                                      bool set)
 463 {
 464         enum i40e_status_code status;
 465         struct i40e_aq_desc desc;
 466         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 467                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 468
 469         if (set)
 470                 i40e_fill_default_direct_cmd_desc(&desc,
 471                                                   i40e_aqc_opc_set_rss_lut);
 472         else
 473                 i40e_fill_default_direct_cmd_desc(&desc,
 474                                                   i40e_aqc_opc_get_rss_lut);
 475
 476         /* Indirect command */
 477         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 478         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 479
 480         cmd_resp->vsi_id =
 481                         CPU_TO_LE16((u16)((vsi_id <<
 482                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 483                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 484         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 485
 486         if (pf_lut)
 487                 cmd_resp->flags |= CPU_TO_LE16((u16)
 488                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 489                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 490                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 491         else
 492                 cmd_resp->flags |= CPU_TO_LE16((u16)
 493                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 494                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 495                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 496
 497         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 498
 499         return status;
 500 }
 501
 502 /**
 503  * i40e_aq_get_rss_lut
 504  * @hw: pointer to the hardware structure
 505  * @vsi_id: vsi fw index
 506  * @pf_lut: for PF table set true, for VSI table set false
 507  * @lut: pointer to the lut buffer provided by the caller
 508  * @lut_size: size of the lut buffer
 509  *
 510  * get the RSS lookup table, PF or VSI type
 511  **/
 512 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 513                                           bool pf_lut, u8 *lut, u16 lut_size)
 514 {
 515         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 516                                        false);
 517 }
 518
 519 /**
 520  * i40e_aq_set_rss_lut
 521  * @hw: pointer to the hardware structure
 522  * @vsi_id: vsi fw index
 523  * @pf_lut: for PF table set true, for VSI table set false
 524  * @lut: pointer to the lut buffer provided by the caller
 525  * @lut_size: size of the lut buffer
 526  *
 527  * set the RSS lookup table, PF or VSI type
 528  **/
 529 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 530                                           bool pf_lut, u8 *lut, u16 lut_size)
 531 {
 532         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
 533 }
 534
 535 /**
 536  * i40e_aq_get_set_rss_key
 537  * @hw: pointer to the hw struct
 538  * @vsi_id: vsi fw index
 539  * @key: pointer to key info struct
 540  * @set: set true to set the key, false to get the key
 541  *
 542  * get the RSS key per VSI
 543  **/
 544 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 545                                       u16 vsi_id,
 546                                       struct i40e_aqc_get_set_rss_key_data *key,
 547                                       bool set)
 548 {
 549         enum i40e_status_code status;
 550         struct i40e_aq_desc desc;
 551         struct i40e_aqc_get_set_rss_key *cmd_resp =
 552                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 553         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 554
 555         if (set)
 556                 i40e_fill_default_direct_cmd_desc(&desc,
 557                                                   i40e_aqc_opc_set_rss_key);
 558         else
 559                 i40e_fill_default_direct_cmd_desc(&desc,
 560                                                   i40e_aqc_opc_get_rss_key);
 561
 562         /* Indirect command */
 563         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 564         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 565
 566         cmd_resp->vsi_id =
 567                         CPU_TO_LE16((u16)((vsi_id <<
 568                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 569                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 570         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 571
 572         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 573
 574         return status;
 575 }
 576
 577 /**
 578  * i40e_aq_get_rss_key
 579  * @hw: pointer to the hw struct
 580  * @vsi_id: vsi fw index
 581  * @key: pointer to key info struct
 582  *
 583  **/
 584 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
 585                                       u16 vsi_id,
 586                                       struct i40e_aqc_get_set_rss_key_data *key)
 587 {
 588         return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
 589 }
 590
 591 /**
 592  * i40e_aq_set_rss_key
 593  * @hw: pointer to the hw struct
 594  * @vsi_id: vsi fw index
 595  * @key: pointer to key info struct
 596  *
 597  * set the RSS key per VSI
 598  **/
 599 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
 600                                       u16 vsi_id,
 601                                       struct i40e_aqc_get_set_rss_key_data *key)
 602 {
 603         return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
 604 }
 605 #endif /* X722_SUPPORT */
 606
 607 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 608  * hardware to a bit-field that can be used by SW to more easily determine the
 609  * packet type.
 610  *
 611  * Macros are used to shorten the table lines and make this table human
 612  * readable.
 613  *
 614  * We store the PTYPE in the top byte of the bit field - this is just so that
 615  * we can check that the table doesn't have a row missing, as the index into
 616  * the table should be the PTYPE.
 617  *
 618  * Typical work flow:
 619  *
 620  * IF NOT i40e_ptype_lookup[ptype].known
 621  * THEN
 622  *      Packet is unknown
 623  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 624  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 625  * ELSE
 626  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 627  * ENDIF
 628  */
 629
 630 /* macro to make the table lines short */
 631 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 632         {       PTYPE, \
 633                 1, \
 634                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 635                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 636                 I40E_RX_PTYPE_##OUTER_FRAG, \
 637                 I40E_RX_PTYPE_TUNNEL_##T, \
 638                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 639                 I40E_RX_PTYPE_##TEF, \
 640                 I40E_RX_PTYPE_INNER_PROT_##I, \
 641                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 642
 643 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 644                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 645
 646 /* shorter macros makes the table fit but are terse */
 647 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 648 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 649 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 650
 651 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 652 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 653         /* L2 Packet types */
 654         I40E_PTT_UNUSED_ENTRY(0),
 655         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 656         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 657         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 658         I40E_PTT_UNUSED_ENTRY(4),
 659         I40E_PTT_UNUSED_ENTRY(5),
 660         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 661         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 662         I40E_PTT_UNUSED_ENTRY(8),
 663         I40E_PTT_UNUSED_ENTRY(9),
 664         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 665         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 666         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 667         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 668         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 669         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 670         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 671         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 672         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 673         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 674         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 675         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 676
 677         /* Non Tunneled IPv4 */
 678         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 679         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 680         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 681         I40E_PTT_UNUSED_ENTRY(25),
 682         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 683         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 684         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 685
 686         /* IPv4 --> IPv4 */
 687         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 688         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 689         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 690         I40E_PTT_UNUSED_ENTRY(32),
 691         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 692         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 693         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 694
 695         /* IPv4 --> IPv6 */
 696         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 697         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 698         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 699         I40E_PTT_UNUSED_ENTRY(39),
 700         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 701         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 702         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 703
 704         /* IPv4 --> GRE/NAT */
 705         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 706
 707         /* IPv4 --> GRE/NAT --> IPv4 */
 708         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 709         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 710         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 711         I40E_PTT_UNUSED_ENTRY(47),
 712         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 713         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 714         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 715
 716         /* IPv4 --> GRE/NAT --> IPv6 */
 717         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 718         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 719         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 720         I40E_PTT_UNUSED_ENTRY(54),
 721         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 722         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 723         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 724
 725         /* IPv4 --> GRE/NAT --> MAC */
 726         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 727
 728         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 729         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 730         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 731         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 732         I40E_PTT_UNUSED_ENTRY(62),
 733         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 734         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 735         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 736
 737         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 738         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 739         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 740         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 741         I40E_PTT_UNUSED_ENTRY(69),
 742         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 743         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 744         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 745
 746         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 747         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 748
 749         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 750         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 751         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 752         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 753         I40E_PTT_UNUSED_ENTRY(77),
 754         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 755         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 756         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 757
 758         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 759         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 760         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 761         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 762         I40E_PTT_UNUSED_ENTRY(84),
 763         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 764         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 765         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 766
 767         /* Non Tunneled IPv6 */
 768         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 769         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 770         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY3),
 771         I40E_PTT_UNUSED_ENTRY(91),
 772         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 773         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 774         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 775
 776         /* IPv6 --> IPv4 */
 777         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 778         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 779         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 780         I40E_PTT_UNUSED_ENTRY(98),
 781         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 782         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 783         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 784
 785         /* IPv6 --> IPv6 */
 786         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 787         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 788         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 789         I40E_PTT_UNUSED_ENTRY(105),
 790         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 791         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 792         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 793
 794         /* IPv6 --> GRE/NAT */
 795         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 796
 797         /* IPv6 --> GRE/NAT -> IPv4 */
 798         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 799         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 800         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 801         I40E_PTT_UNUSED_ENTRY(113),
 802         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 803         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 804         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 805
 806         /* IPv6 --> GRE/NAT -> IPv6 */
 807         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 808         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 809         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 810         I40E_PTT_UNUSED_ENTRY(120),
 811         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 812         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 813         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 814
 815         /* IPv6 --> GRE/NAT -> MAC */
 816         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 817
 818         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 819         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 820         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 821         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 822         I40E_PTT_UNUSED_ENTRY(128),
 823         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 824         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 825         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 826
 827         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 828         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 829         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 830         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 831         I40E_PTT_UNUSED_ENTRY(135),
 832         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 833         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 834         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 835
 836         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 837         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 838
 839         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 840         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 841         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 842         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 843         I40E_PTT_UNUSED_ENTRY(143),
 844         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 845         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 846         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 847
 848         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 849         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 850         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 851         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 852         I40E_PTT_UNUSED_ENTRY(150),
 853         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 854         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 855         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 856
 857         /* unused entries */
 858         I40E_PTT_UNUSED_ENTRY(154),
 859         I40E_PTT_UNUSED_ENTRY(155),
 860         I40E_PTT_UNUSED_ENTRY(156),
 861         I40E_PTT_UNUSED_ENTRY(157),
 862         I40E_PTT_UNUSED_ENTRY(158),
 863         I40E_PTT_UNUSED_ENTRY(159),
 864
 865         I40E_PTT_UNUSED_ENTRY(160),
 866         I40E_PTT_UNUSED_ENTRY(161),
 867         I40E_PTT_UNUSED_ENTRY(162),
 868         I40E_PTT_UNUSED_ENTRY(163),
 869         I40E_PTT_UNUSED_ENTRY(164),
 870         I40E_PTT_UNUSED_ENTRY(165),
 871         I40E_PTT_UNUSED_ENTRY(166),
 872         I40E_PTT_UNUSED_ENTRY(167),
 873         I40E_PTT_UNUSED_ENTRY(168),
 874         I40E_PTT_UNUSED_ENTRY(169),
 875
 876         I40E_PTT_UNUSED_ENTRY(170),
 877         I40E_PTT_UNUSED_ENTRY(171),
 878         I40E_PTT_UNUSED_ENTRY(172),
 879         I40E_PTT_UNUSED_ENTRY(173),
 880         I40E_PTT_UNUSED_ENTRY(174),
 881         I40E_PTT_UNUSED_ENTRY(175),
 882         I40E_PTT_UNUSED_ENTRY(176),
 883         I40E_PTT_UNUSED_ENTRY(177),
 884         I40E_PTT_UNUSED_ENTRY(178),
 885         I40E_PTT_UNUSED_ENTRY(179),
 886
 887         I40E_PTT_UNUSED_ENTRY(180),
 888         I40E_PTT_UNUSED_ENTRY(181),
 889         I40E_PTT_UNUSED_ENTRY(182),
 890         I40E_PTT_UNUSED_ENTRY(183),
 891         I40E_PTT_UNUSED_ENTRY(184),
 892         I40E_PTT_UNUSED_ENTRY(185),
 893         I40E_PTT_UNUSED_ENTRY(186),
 894         I40E_PTT_UNUSED_ENTRY(187),
 895         I40E_PTT_UNUSED_ENTRY(188),
 896         I40E_PTT_UNUSED_ENTRY(189),
 897
 898         I40E_PTT_UNUSED_ENTRY(190),
 899         I40E_PTT_UNUSED_ENTRY(191),
 900         I40E_PTT_UNUSED_ENTRY(192),
 901         I40E_PTT_UNUSED_ENTRY(193),
 902         I40E_PTT_UNUSED_ENTRY(194),
 903         I40E_PTT_UNUSED_ENTRY(195),
 904         I40E_PTT_UNUSED_ENTRY(196),
 905         I40E_PTT_UNUSED_ENTRY(197),
 906         I40E_PTT_UNUSED_ENTRY(198),
 907         I40E_PTT_UNUSED_ENTRY(199),
 908
 909         I40E_PTT_UNUSED_ENTRY(200),
 910         I40E_PTT_UNUSED_ENTRY(201),
 911         I40E_PTT_UNUSED_ENTRY(202),
 912         I40E_PTT_UNUSED_ENTRY(203),
 913         I40E_PTT_UNUSED_ENTRY(204),
 914         I40E_PTT_UNUSED_ENTRY(205),
 915         I40E_PTT_UNUSED_ENTRY(206),
 916         I40E_PTT_UNUSED_ENTRY(207),
 917         I40E_PTT_UNUSED_ENTRY(208),
 918         I40E_PTT_UNUSED_ENTRY(209),
 919
 920         I40E_PTT_UNUSED_ENTRY(210),
 921         I40E_PTT_UNUSED_ENTRY(211),
 922         I40E_PTT_UNUSED_ENTRY(212),
 923         I40E_PTT_UNUSED_ENTRY(213),
 924         I40E_PTT_UNUSED_ENTRY(214),
 925         I40E_PTT_UNUSED_ENTRY(215),
 926         I40E_PTT_UNUSED_ENTRY(216),
 927         I40E_PTT_UNUSED_ENTRY(217),
 928         I40E_PTT_UNUSED_ENTRY(218),
 929         I40E_PTT_UNUSED_ENTRY(219),
 930
 931         I40E_PTT_UNUSED_ENTRY(220),
 932         I40E_PTT_UNUSED_ENTRY(221),
 933         I40E_PTT_UNUSED_ENTRY(222),
 934         I40E_PTT_UNUSED_ENTRY(223),
 935         I40E_PTT_UNUSED_ENTRY(224),
 936         I40E_PTT_UNUSED_ENTRY(225),
 937         I40E_PTT_UNUSED_ENTRY(226),
 938         I40E_PTT_UNUSED_ENTRY(227),
 939         I40E_PTT_UNUSED_ENTRY(228),
 940         I40E_PTT_UNUSED_ENTRY(229),
 941
 942         I40E_PTT_UNUSED_ENTRY(230),
 943         I40E_PTT_UNUSED_ENTRY(231),
 944         I40E_PTT_UNUSED_ENTRY(232),
 945         I40E_PTT_UNUSED_ENTRY(233),
 946         I40E_PTT_UNUSED_ENTRY(234),
 947         I40E_PTT_UNUSED_ENTRY(235),
 948         I40E_PTT_UNUSED_ENTRY(236),
 949         I40E_PTT_UNUSED_ENTRY(237),
 950         I40E_PTT_UNUSED_ENTRY(238),
 951         I40E_PTT_UNUSED_ENTRY(239),
 952
 953         I40E_PTT_UNUSED_ENTRY(240),
 954         I40E_PTT_UNUSED_ENTRY(241),
 955         I40E_PTT_UNUSED_ENTRY(242),
 956         I40E_PTT_UNUSED_ENTRY(243),
 957         I40E_PTT_UNUSED_ENTRY(244),
 958         I40E_PTT_UNUSED_ENTRY(245),
 959         I40E_PTT_UNUSED_ENTRY(246),
 960         I40E_PTT_UNUSED_ENTRY(247),
 961         I40E_PTT_UNUSED_ENTRY(248),
 962         I40E_PTT_UNUSED_ENTRY(249),
 963
 964         I40E_PTT_UNUSED_ENTRY(250),
 965         I40E_PTT_UNUSED_ENTRY(251),
 966         I40E_PTT_UNUSED_ENTRY(252),
 967         I40E_PTT_UNUSED_ENTRY(253),
 968         I40E_PTT_UNUSED_ENTRY(254),
 969         I40E_PTT_UNUSED_ENTRY(255)
 970 };
 971
 972
 973 /**
 974  * i40e_validate_mac_addr - Validate unicast MAC address
 975  * @mac_addr: pointer to MAC address
 976  *
 977  * Tests a MAC address to ensure it is a valid Individual Address
 978  **/
 979 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
 980 {
 981         enum i40e_status_code status = I40E_SUCCESS;
 982
 983         DEBUGFUNC("i40e_validate_mac_addr");
 984
 985         /* Broadcast addresses ARE multicast addresses
 986          * Make sure it is not a multicast address
 987          * Reject the zero address
 988          */
 989         if (I40E_IS_MULTICAST(mac_addr) ||
 990             (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
 991               mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
 992                 status = I40E_ERR_INVALID_MAC_ADDR;
 993
 994         return status;
 995 }
 996 #ifdef PF_DRIVER
 997
 998 /**
 999  * i40e_init_shared_code - Initialize the shared code
1000  * @hw: pointer to hardware structure
1001  *
1002  * This assigns the MAC type and PHY code and inits the NVM.
1003  * Does not touch the hardware. This function must be called prior to any
1004  * other function in the shared code. The i40e_hw structure should be
1005  * memset to 0 prior to calling this function.  The following fields in
1006  * hw structure should be filled in prior to calling this function:
1007  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1008  * subsystem_vendor_id, and revision_id
1009  **/
1010 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
1011 {
1012         enum i40e_status_code status = I40E_SUCCESS;
1013         u32 port, ari, func_rid;
1014
1015         DEBUGFUNC("i40e_init_shared_code");
1016
1017         i40e_set_mac_type(hw);
1018
1019         switch (hw->mac.type) {
1020         case I40E_MAC_XL710:
1021 #ifdef X722_SUPPORT
1022         case I40E_MAC_X722:
1023 #endif
1024                 break;
1025         default:
1026                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1027         }
1028
1029         hw->phy.get_link_info = true;
1030
1031         /* Determine port number and PF number*/
1032         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1033                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1034         hw->port = (u8)port;
1035         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1036                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1037         func_rid = rd32(hw, I40E_PF_FUNC_RID);
1038         if (ari)
1039                 hw->pf_id = (u8)(func_rid & 0xff);
1040         else
1041                 hw->pf_id = (u8)(func_rid & 0x7);
1042
1043 #ifdef X722_SUPPORT
1044         if (hw->mac.type == I40E_MAC_X722)
1045                 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
1046
1047 #endif
1048         status = i40e_init_nvm(hw);
1049         return status;
1050 }
1051
1052 /**
1053  * i40e_aq_mac_address_read - Retrieve the MAC addresses
1054  * @hw: pointer to the hw struct
1055  * @flags: a return indicator of what addresses were added to the addr store
1056  * @addrs: the requestor's mac addr store
1057  * @cmd_details: pointer to command details structure or NULL
1058  **/
1059 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1060                                    u16 *flags,
1061                                    struct i40e_aqc_mac_address_read_data *addrs,
1062                                    struct i40e_asq_cmd_details *cmd_details)
1063 {
1064         struct i40e_aq_desc desc;
1065         struct i40e_aqc_mac_address_read *cmd_data =
1066                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1067         enum i40e_status_code status;
1068
1069         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1070         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1071
1072         status = i40e_asq_send_command(hw, &desc, addrs,
1073                                        sizeof(*addrs), cmd_details);
1074         *flags = LE16_TO_CPU(cmd_data->command_flags);
1075
1076         return status;
1077 }
1078
1079 /**
1080  * i40e_aq_mac_address_write - Change the MAC addresses
1081  * @hw: pointer to the hw struct
1082  * @flags: indicates which MAC to be written
1083  * @mac_addr: address to write
1084  * @cmd_details: pointer to command details structure or NULL
1085  **/
1086 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1087                                     u16 flags, u8 *mac_addr,
1088                                     struct i40e_asq_cmd_details *cmd_details)
1089 {
1090         struct i40e_aq_desc desc;
1091         struct i40e_aqc_mac_address_write *cmd_data =
1092                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1093         enum i40e_status_code status;
1094
1095         i40e_fill_default_direct_cmd_desc(&desc,
1096                                           i40e_aqc_opc_mac_address_write);
1097         cmd_data->command_flags = CPU_TO_LE16(flags);
1098         cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1099         cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1100                                         ((u32)mac_addr[3] << 16) |
1101                                         ((u32)mac_addr[4] << 8) |
1102                                         mac_addr[5]);
1103
1104         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1105
1106         return status;
1107 }
1108
1109 /**
1110  * i40e_get_mac_addr - get MAC address
1111  * @hw: pointer to the HW structure
1112  * @mac_addr: pointer to MAC address
1113  *
1114  * Reads the adapter's MAC address from register
1115  **/
1116 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1117 {
1118         struct i40e_aqc_mac_address_read_data addrs;
1119         enum i40e_status_code status;
1120         u16 flags = 0;
1121
1122         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1123
1124         if (flags & I40E_AQC_LAN_ADDR_VALID)
1125                 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
1126
1127         return status;
1128 }
1129
1130 /**
1131  * i40e_get_port_mac_addr - get Port MAC address
1132  * @hw: pointer to the HW structure
1133  * @mac_addr: pointer to Port MAC address
1134  *
1135  * Reads the adapter's Port MAC address
1136  **/
1137 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1138 {
1139         struct i40e_aqc_mac_address_read_data addrs;
1140         enum i40e_status_code status;
1141         u16 flags = 0;
1142
1143         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1144         if (status)
1145                 return status;
1146
1147         if (flags & I40E_AQC_PORT_ADDR_VALID)
1148                 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
1149         else
1150                 status = I40E_ERR_INVALID_MAC_ADDR;
1151
1152         return status;
1153 }
1154
1155 /**
1156  * i40e_pre_tx_queue_cfg - pre tx queue configure
1157  * @hw: pointer to the HW structure
1158  * @queue: target pf queue index
1159  * @enable: state change request
1160  *
1161  * Handles hw requirement to indicate intention to enable
1162  * or disable target queue.
1163  **/
1164 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1165 {
1166         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1167         u32 reg_block = 0;
1168         u32 reg_val;
1169
1170         if (abs_queue_idx >= 128) {
1171                 reg_block = abs_queue_idx / 128;
1172                 abs_queue_idx %= 128;
1173         }
1174
1175         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1176         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1177         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1178
1179         if (enable)
1180                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1181         else
1182                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1183
1184         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1185 }
1186
1187 /**
1188  *  i40e_read_pba_string - Reads part number string from EEPROM
1189  *  @hw: pointer to hardware structure
1190  *  @pba_num: stores the part number string from the EEPROM
1191  *  @pba_num_size: part number string buffer length
1192  *
1193  *  Reads the part number string from the EEPROM.
1194  **/
1195 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1196                                             u32 pba_num_size)
1197 {
1198         enum i40e_status_code status = I40E_SUCCESS;
1199         u16 pba_word = 0;
1200         u16 pba_size = 0;
1201         u16 pba_ptr = 0;
1202         u16 i = 0;
1203
1204         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1205         if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1206                 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1207                 return status;
1208         }
1209
1210         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1211         if (status != I40E_SUCCESS) {
1212                 DEBUGOUT("Failed to read PBA Block pointer.\n");
1213                 return status;
1214         }
1215
1216         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1217         if (status != I40E_SUCCESS) {
1218                 DEBUGOUT("Failed to read PBA Block size.\n");
1219                 return status;
1220         }
1221
1222         /* Subtract one to get PBA word count (PBA Size word is included in
1223          * total size)
1224          */
1225         pba_size--;
1226         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1227                 DEBUGOUT("Buffer to small for PBA data.\n");
1228                 return I40E_ERR_PARAM;
1229         }
1230
1231         for (i = 0; i < pba_size; i++) {
1232                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1233                 if (status != I40E_SUCCESS) {
1234                         DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1235                         return status;
1236                 }
1237
1238                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1239                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1240         }
1241         pba_num[(pba_size * 2)] = '\0';
1242
1243         return status;
1244 }
1245
1246 /**
1247  * i40e_get_media_type - Gets media type
1248  * @hw: pointer to the hardware structure
1249  **/
1250 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1251 {
1252         enum i40e_media_type media;
1253
1254         switch (hw->phy.link_info.phy_type) {
1255         case I40E_PHY_TYPE_10GBASE_SR:
1256         case I40E_PHY_TYPE_10GBASE_LR:
1257         case I40E_PHY_TYPE_1000BASE_SX:
1258         case I40E_PHY_TYPE_1000BASE_LX:
1259         case I40E_PHY_TYPE_40GBASE_SR4:
1260         case I40E_PHY_TYPE_40GBASE_LR4:
1261                 media = I40E_MEDIA_TYPE_FIBER;
1262                 break;
1263         case I40E_PHY_TYPE_100BASE_TX:
1264         case I40E_PHY_TYPE_1000BASE_T:
1265         case I40E_PHY_TYPE_10GBASE_T:
1266                 media = I40E_MEDIA_TYPE_BASET;
1267                 break;
1268         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1269         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1270         case I40E_PHY_TYPE_10GBASE_CR1:
1271         case I40E_PHY_TYPE_40GBASE_CR4:
1272         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1273         case I40E_PHY_TYPE_40GBASE_AOC:
1274         case I40E_PHY_TYPE_10GBASE_AOC:
1275                 media = I40E_MEDIA_TYPE_DA;
1276                 break;
1277         case I40E_PHY_TYPE_1000BASE_KX:
1278         case I40E_PHY_TYPE_10GBASE_KX4:
1279         case I40E_PHY_TYPE_10GBASE_KR:
1280         case I40E_PHY_TYPE_40GBASE_KR4:
1281         case I40E_PHY_TYPE_20GBASE_KR2:
1282                 media = I40E_MEDIA_TYPE_BACKPLANE;
1283                 break;
1284         case I40E_PHY_TYPE_SGMII:
1285         case I40E_PHY_TYPE_XAUI:
1286         case I40E_PHY_TYPE_XFI:
1287         case I40E_PHY_TYPE_XLAUI:
1288         case I40E_PHY_TYPE_XLPPI:
1289         default:
1290                 media = I40E_MEDIA_TYPE_UNKNOWN;
1291                 break;
1292         }
1293
1294         return media;
1295 }
1296
1297 #define I40E_PF_RESET_WAIT_COUNT        200
1298 /**
1299  * i40e_pf_reset - Reset the PF
1300  * @hw: pointer to the hardware structure
1301  *
1302  * Assuming someone else has triggered a global reset,
1303  * assure the global reset is complete and then reset the PF
1304  **/
1305 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1306 {
1307         u32 cnt = 0;
1308         u32 cnt1 = 0;
1309         u32 reg = 0;
1310         u32 grst_del;
1311
1312         /* Poll for Global Reset steady state in case of recent GRST.
1313          * The grst delay value is in 100ms units, and we'll wait a
1314          * couple counts longer to be sure we don't just miss the end.
1315          */
1316         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1317                         I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1318                         I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1319
1320         grst_del = grst_del * 20;
1321
1322         for (cnt = 0; cnt < grst_del; cnt++) {
1323                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1324                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1325                         break;
1326                 i40e_msec_delay(100);
1327         }
1328         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1329                 DEBUGOUT("Global reset polling failed to complete.\n");
1330                 return I40E_ERR_RESET_FAILED;
1331         }
1332
1333         /* Now Wait for the FW to be ready */
1334         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1335                 reg = rd32(hw, I40E_GLNVM_ULD);
1336                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1337                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1338                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1339                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1340                         DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1341                         break;
1342                 }
1343                 i40e_msec_delay(10);
1344         }
1345         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1346                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1347                 DEBUGOUT("wait for FW Reset complete timedout\n");
1348                 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1349                 return I40E_ERR_RESET_FAILED;
1350         }
1351
1352         /* If there was a Global Reset in progress when we got here,
1353          * we don't need to do the PF Reset
1354          */
1355         if (!cnt) {
1356                 reg = rd32(hw, I40E_PFGEN_CTRL);
1357                 wr32(hw, I40E_PFGEN_CTRL,
1358                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1359                 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1360                         reg = rd32(hw, I40E_PFGEN_CTRL);
1361                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1362                                 break;
1363                         i40e_msec_delay(1);
1364                 }
1365                 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1366                         DEBUGOUT("PF reset polling failed to complete.\n");
1367                         return I40E_ERR_RESET_FAILED;
1368                 }
1369         }
1370
1371         i40e_clear_pxe_mode(hw);
1372
1373
1374         return I40E_SUCCESS;
1375 }
1376
1377 /**
1378  * i40e_clear_hw - clear out any left over hw state
1379  * @hw: pointer to the hw struct
1380  *
1381  * Clear queues and interrupts, typically called at init time,
1382  * but after the capabilities have been found so we know how many
1383  * queues and msix vectors have been allocated.
1384  **/
1385 void i40e_clear_hw(struct i40e_hw *hw)
1386 {
1387         u32 num_queues, base_queue;
1388         u32 num_pf_int;
1389         u32 num_vf_int;
1390         u32 num_vfs;
1391         u32 i, j;
1392         u32 val;
1393         u32 eol = 0x7ff;
1394
1395         /* get number of interrupts, queues, and vfs */
1396         val = rd32(hw, I40E_GLPCI_CNF2);
1397         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1398                         I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1399         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1400                         I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1401
1402         val = rd32(hw, I40E_PFLAN_QALLOC);
1403         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1404                         I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1405         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1406                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1407         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1408                 num_queues = (j - base_queue) + 1;
1409         else
1410                 num_queues = 0;
1411
1412         val = rd32(hw, I40E_PF_VT_PFALLOC);
1413         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1414                         I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1415         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1416                         I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1417         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1418                 num_vfs = (j - i) + 1;
1419         else
1420                 num_vfs = 0;
1421
1422         /* stop all the interrupts */
1423         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1424         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1425         for (i = 0; i < num_pf_int - 2; i++)
1426                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1427
1428         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1429         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1430         wr32(hw, I40E_PFINT_LNKLST0, val);
1431         for (i = 0; i < num_pf_int - 2; i++)
1432                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1433         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1434         for (i = 0; i < num_vfs; i++)
1435                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1436         for (i = 0; i < num_vf_int - 2; i++)
1437                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1438
1439         /* warn the HW of the coming Tx disables */
1440         for (i = 0; i < num_queues; i++) {
1441                 u32 abs_queue_idx = base_queue + i;
1442                 u32 reg_block = 0;
1443
1444                 if (abs_queue_idx >= 128) {
1445                         reg_block = abs_queue_idx / 128;
1446                         abs_queue_idx %= 128;
1447                 }
1448
1449                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1450                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1451                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1452                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1453
1454                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1455         }
1456         i40e_usec_delay(400);
1457
1458         /* stop all the queues */
1459         for (i = 0; i < num_queues; i++) {
1460                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1461                 wr32(hw, I40E_QTX_ENA(i), 0);
1462                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1463                 wr32(hw, I40E_QRX_ENA(i), 0);
1464         }
1465
1466         /* short wait for all queue disables to settle */
1467         i40e_usec_delay(50);
1468 }
1469
1470 /**
1471  * i40e_clear_pxe_mode - clear pxe operations mode
1472  * @hw: pointer to the hw struct
1473  *
1474  * Make sure all PXE mode settings are cleared, including things
1475  * like descriptor fetch/write-back mode.
1476  **/
1477 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1478 {
1479         if (i40e_check_asq_alive(hw))
1480                 i40e_aq_clear_pxe_mode(hw, NULL);
1481 }
1482
1483 /**
1484  * i40e_led_is_mine - helper to find matching led
1485  * @hw: pointer to the hw struct
1486  * @idx: index into GPIO registers
1487  *
1488  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1489  */
1490 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1491 {
1492         u32 gpio_val = 0;
1493         u32 port;
1494
1495         if (!hw->func_caps.led[idx])
1496                 return 0;
1497
1498         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1499         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1500                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1501
1502         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1503          * if it is not our port then ignore
1504          */
1505         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1506             (port != hw->port))
1507                 return 0;
1508
1509         return gpio_val;
1510 }
1511
1512 #define I40E_COMBINED_ACTIVITY 0xA
1513 #define I40E_FILTER_ACTIVITY 0xE
1514 #define I40E_LINK_ACTIVITY 0xC
1515 #define I40E_MAC_ACTIVITY 0xD
1516 #define I40E_LED0 22
1517
1518 /**
1519  * i40e_led_get - return current on/off mode
1520  * @hw: pointer to the hw struct
1521  *
1522  * The value returned is the 'mode' field as defined in the
1523  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1524  * values are variations of possible behaviors relating to
1525  * blink, link, and wire.
1526  **/
1527 u32 i40e_led_get(struct i40e_hw *hw)
1528 {
1529         u32 current_mode = 0;
1530         u32 mode = 0;
1531         int i;
1532
1533         /* as per the documentation GPIO 22-29 are the LED
1534          * GPIO pins named LED0..LED7
1535          */
1536         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1537                 u32 gpio_val = i40e_led_is_mine(hw, i);
1538
1539                 if (!gpio_val)
1540                         continue;
1541
1542                 /* ignore gpio LED src mode entries related to the activity
1543                  *  LEDs
1544                  */
1545                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1546                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1547                 switch (current_mode) {
1548                 case I40E_COMBINED_ACTIVITY:
1549                 case I40E_FILTER_ACTIVITY:
1550                 case I40E_MAC_ACTIVITY:
1551                         continue;
1552                 default:
1553                         break;
1554                 }
1555
1556                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1557                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1558                 break;
1559         }
1560
1561         return mode;
1562 }
1563
1564 /**
1565  * i40e_led_set - set new on/off mode
1566  * @hw: pointer to the hw struct
1567  * @mode: 0=off, 0xf=on (else see manual for mode details)
1568  * @blink: true if the LED should blink when on, false if steady
1569  *
1570  * if this function is used to turn on the blink it should
1571  * be used to disable the blink when restoring the original state.
1572  **/
1573 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1574 {
1575         u32 current_mode = 0;
1576         int i;
1577
1578         if (mode & 0xfffffff0)
1579                 DEBUGOUT1("invalid mode passed in %X\n", mode);
1580
1581         /* as per the documentation GPIO 22-29 are the LED
1582          * GPIO pins named LED0..LED7
1583          */
1584         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1585                 u32 gpio_val = i40e_led_is_mine(hw, i);
1586
1587                 if (!gpio_val)
1588                         continue;
1589
1590                 /* ignore gpio LED src mode entries related to the activity
1591                  * LEDs
1592                  */
1593                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1594                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1595                 switch (current_mode) {
1596                 case I40E_COMBINED_ACTIVITY:
1597                 case I40E_FILTER_ACTIVITY:
1598                 case I40E_MAC_ACTIVITY:
1599                         continue;
1600                 default:
1601                         break;
1602                 }
1603
1604                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1605                 /* this & is a bit of paranoia, but serves as a range check */
1606                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1607                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1608
1609                 if (mode == I40E_LINK_ACTIVITY)
1610                         blink = false;
1611
1612                 if (blink)
1613                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1614                 else
1615                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1616
1617                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1618                 break;
1619         }
1620 }
1621
1622 /* Admin command wrappers */
1623
1624 /**
1625  * i40e_aq_get_phy_capabilities
1626  * @hw: pointer to the hw struct
1627  * @abilities: structure for PHY capabilities to be filled
1628  * @qualified_modules: report Qualified Modules
1629  * @report_init: report init capabilities (active are default)
1630  * @cmd_details: pointer to command details structure or NULL
1631  *
1632  * Returns the various PHY abilities supported on the Port.
1633  **/
1634 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1635                         bool qualified_modules, bool report_init,
1636                         struct i40e_aq_get_phy_abilities_resp *abilities,
1637                         struct i40e_asq_cmd_details *cmd_details)
1638 {
1639         struct i40e_aq_desc desc;
1640         enum i40e_status_code status;
1641         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1642
1643         if (!abilities)
1644                 return I40E_ERR_PARAM;
1645
1646         i40e_fill_default_direct_cmd_desc(&desc,
1647                                           i40e_aqc_opc_get_phy_abilities);
1648
1649         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1650         if (abilities_size > I40E_AQ_LARGE_BUF)
1651                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1652
1653         if (qualified_modules)
1654                 desc.params.external.param0 |=
1655                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1656
1657         if (report_init)
1658                 desc.params.external.param0 |=
1659                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1660
1661         status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1662                                     cmd_details);
1663
1664         if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1665                 status = I40E_ERR_UNKNOWN_PHY;
1666
1667         if (report_init)
1668                 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1669
1670         return status;
1671 }
1672
1673 /**
1674  * i40e_aq_set_phy_config
1675  * @hw: pointer to the hw struct
1676  * @config: structure with PHY configuration to be set
1677  * @cmd_details: pointer to command details structure or NULL
1678  *
1679  * Set the various PHY configuration parameters
1680  * supported on the Port.One or more of the Set PHY config parameters may be
1681  * ignored in an MFP mode as the PF may not have the privilege to set some
1682  * of the PHY Config parameters. This status will be indicated by the
1683  * command response.
1684  **/
1685 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1686                                 struct i40e_aq_set_phy_config *config,
1687                                 struct i40e_asq_cmd_details *cmd_details)
1688 {
1689         struct i40e_aq_desc desc;
1690         struct i40e_aq_set_phy_config *cmd =
1691                 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1692         enum i40e_status_code status;
1693
1694         if (!config)
1695                 return I40E_ERR_PARAM;
1696
1697         i40e_fill_default_direct_cmd_desc(&desc,
1698                                           i40e_aqc_opc_set_phy_config);
1699
1700         *cmd = *config;
1701
1702         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1703
1704         return status;
1705 }
1706
1707 /**
1708  * i40e_set_fc
1709  * @hw: pointer to the hw struct
1710  *
1711  * Set the requested flow control mode using set_phy_config.
1712  **/
1713 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1714                                   bool atomic_restart)
1715 {
1716         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1717         struct i40e_aq_get_phy_abilities_resp abilities;
1718         struct i40e_aq_set_phy_config config;
1719         enum i40e_status_code status;
1720         u8 pause_mask = 0x0;
1721
1722         *aq_failures = 0x0;
1723
1724         switch (fc_mode) {
1725         case I40E_FC_FULL:
1726                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1727                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1728                 break;
1729         case I40E_FC_RX_PAUSE:
1730                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1731                 break;
1732         case I40E_FC_TX_PAUSE:
1733                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1734                 break;
1735         default:
1736                 break;
1737         }
1738
1739         /* Get the current phy config */
1740         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1741                                               NULL);
1742         if (status) {
1743                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1744                 return status;
1745         }
1746
1747         memset(&config, 0, sizeof(config));
1748         /* clear the old pause settings */
1749         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1750                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1751         /* set the new abilities */
1752         config.abilities |= pause_mask;
1753         /* If the abilities have changed, then set the new config */
1754         if (config.abilities != abilities.abilities) {
1755                 /* Auto restart link so settings take effect */
1756                 if (atomic_restart)
1757                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1758                 /* Copy over all the old settings */
1759                 config.phy_type = abilities.phy_type;
1760                 config.link_speed = abilities.link_speed;
1761                 config.eee_capability = abilities.eee_capability;
1762                 config.eeer = abilities.eeer_val;
1763                 config.low_power_ctrl = abilities.d3_lpan;
1764                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1765
1766                 if (status)
1767                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1768         }
1769         /* Update the link info */
1770         status = i40e_update_link_info(hw);
1771         if (status) {
1772                 /* Wait a little bit (on 40G cards it sometimes takes a really
1773                  * long time for link to come back from the atomic reset)
1774                  * and try once more
1775                  */
1776                 i40e_msec_delay(1000);
1777                 status = i40e_update_link_info(hw);
1778         }
1779         if (status)
1780                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1781
1782         return status;
1783 }
1784
1785 /**
1786  * i40e_aq_set_mac_config
1787  * @hw: pointer to the hw struct
1788  * @max_frame_size: Maximum Frame Size to be supported by the port
1789  * @crc_en: Tell HW to append a CRC to outgoing frames
1790  * @pacing: Pacing configurations
1791  * @cmd_details: pointer to command details structure or NULL
1792  *
1793  * Configure MAC settings for frame size, jumbo frame support and the
1794  * addition of a CRC by the hardware.
1795  **/
1796 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1797                                 u16 max_frame_size,
1798                                 bool crc_en, u16 pacing,
1799                                 struct i40e_asq_cmd_details *cmd_details)
1800 {
1801         struct i40e_aq_desc desc;
1802         struct i40e_aq_set_mac_config *cmd =
1803                 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1804         enum i40e_status_code status;
1805
1806         if (max_frame_size == 0)
1807                 return I40E_ERR_PARAM;
1808
1809         i40e_fill_default_direct_cmd_desc(&desc,
1810                                           i40e_aqc_opc_set_mac_config);
1811
1812         cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1813         cmd->params = ((u8)pacing & 0x0F) << 3;
1814         if (crc_en)
1815                 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1816
1817         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1818
1819         return status;
1820 }
1821
1822 /**
1823  * i40e_aq_clear_pxe_mode
1824  * @hw: pointer to the hw struct
1825  * @cmd_details: pointer to command details structure or NULL
1826  *
1827  * Tell the firmware that the driver is taking over from PXE
1828  **/
1829 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1830                         struct i40e_asq_cmd_details *cmd_details)
1831 {
1832         enum i40e_status_code status;
1833         struct i40e_aq_desc desc;
1834         struct i40e_aqc_clear_pxe *cmd =
1835                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1836
1837         i40e_fill_default_direct_cmd_desc(&desc,
1838                                           i40e_aqc_opc_clear_pxe_mode);
1839
1840         cmd->rx_cnt = 0x2;
1841
1842         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1843
1844         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1845
1846         return status;
1847 }
1848
1849 /**
1850  * i40e_aq_set_link_restart_an
1851  * @hw: pointer to the hw struct
1852  * @enable_link: if true: enable link, if false: disable link
1853  * @cmd_details: pointer to command details structure or NULL
1854  *
1855  * Sets up the link and restarts the Auto-Negotiation over the link.
1856  **/
1857 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1858                 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1859 {
1860         struct i40e_aq_desc desc;
1861         struct i40e_aqc_set_link_restart_an *cmd =
1862                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1863         enum i40e_status_code status;
1864
1865         i40e_fill_default_direct_cmd_desc(&desc,
1866                                           i40e_aqc_opc_set_link_restart_an);
1867
1868         cmd->command = I40E_AQ_PHY_RESTART_AN;
1869         if (enable_link)
1870                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1871         else
1872                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1873
1874         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1875
1876         return status;
1877 }
1878
1879 /**
1880  * i40e_aq_get_link_info
1881  * @hw: pointer to the hw struct
1882  * @enable_lse: enable/disable LinkStatusEvent reporting
1883  * @link: pointer to link status structure - optional
1884  * @cmd_details: pointer to command details structure or NULL
1885  *
1886  * Returns the link status of the adapter.
1887  **/
1888 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1889                                 bool enable_lse, struct i40e_link_status *link,
1890                                 struct i40e_asq_cmd_details *cmd_details)
1891 {
1892         struct i40e_aq_desc desc;
1893         struct i40e_aqc_get_link_status *resp =
1894                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1895         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1896         enum i40e_status_code status;
1897         bool tx_pause, rx_pause;
1898         u16 command_flags;
1899
1900         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1901
1902         if (enable_lse)
1903                 command_flags = I40E_AQ_LSE_ENABLE;
1904         else
1905                 command_flags = I40E_AQ_LSE_DISABLE;
1906         resp->command_flags = CPU_TO_LE16(command_flags);
1907
1908         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1909
1910         if (status != I40E_SUCCESS)
1911                 goto aq_get_link_info_exit;
1912
1913         /* save off old link status information */
1914         i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1915                     sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1916
1917         /* update link status */
1918         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1919         hw->phy.media_type = i40e_get_media_type(hw);
1920         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1921         hw_link_info->link_info = resp->link_info;
1922         hw_link_info->an_info = resp->an_info;
1923         hw_link_info->ext_info = resp->ext_info;
1924         hw_link_info->loopback = resp->loopback;
1925         hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1926         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1927
1928         /* update fc info */
1929         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1930         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1931         if (tx_pause & rx_pause)
1932                 hw->fc.current_mode = I40E_FC_FULL;
1933         else if (tx_pause)
1934                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1935         else if (rx_pause)
1936                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1937         else
1938                 hw->fc.current_mode = I40E_FC_NONE;
1939
1940         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1941                 hw_link_info->crc_enable = true;
1942         else
1943                 hw_link_info->crc_enable = false;
1944
1945         if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1946                 hw_link_info->lse_enable = true;
1947         else
1948                 hw_link_info->lse_enable = false;
1949
1950         if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1951              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1952                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1953
1954         /* save link status information */
1955         if (link)
1956                 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1957                             I40E_NONDMA_TO_NONDMA);
1958
1959         /* flag cleared so helper functions don't call AQ again */
1960         hw->phy.get_link_info = false;
1961
1962 aq_get_link_info_exit:
1963         return status;
1964 }
1965
1966 /**
1967  * i40e_aq_set_phy_int_mask
1968  * @hw: pointer to the hw struct
1969  * @mask: interrupt mask to be set
1970  * @cmd_details: pointer to command details structure or NULL
1971  *
1972  * Set link interrupt mask.
1973  **/
1974 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1975                                 u16 mask,
1976                                 struct i40e_asq_cmd_details *cmd_details)
1977 {
1978         struct i40e_aq_desc desc;
1979         struct i40e_aqc_set_phy_int_mask *cmd =
1980                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1981         enum i40e_status_code status;
1982
1983         i40e_fill_default_direct_cmd_desc(&desc,
1984                                           i40e_aqc_opc_set_phy_int_mask);
1985
1986         cmd->event_mask = CPU_TO_LE16(mask);
1987
1988         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1989
1990         return status;
1991 }
1992
1993 /**
1994  * i40e_aq_get_local_advt_reg
1995  * @hw: pointer to the hw struct
1996  * @advt_reg: local AN advertisement register value
1997  * @cmd_details: pointer to command details structure or NULL
1998  *
1999  * Get the Local AN advertisement register value.
2000  **/
2001 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2002                                 u64 *advt_reg,
2003                                 struct i40e_asq_cmd_details *cmd_details)
2004 {
2005         struct i40e_aq_desc desc;
2006         struct i40e_aqc_an_advt_reg *resp =
2007                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2008         enum i40e_status_code status;
2009
2010         i40e_fill_default_direct_cmd_desc(&desc,
2011                                           i40e_aqc_opc_get_local_advt_reg);
2012
2013         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2014
2015         if (status != I40E_SUCCESS)
2016                 goto aq_get_local_advt_reg_exit;
2017
2018         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2019         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2020
2021 aq_get_local_advt_reg_exit:
2022         return status;
2023 }
2024
2025 /**
2026  * i40e_aq_set_local_advt_reg
2027  * @hw: pointer to the hw struct
2028  * @advt_reg: local AN advertisement register value
2029  * @cmd_details: pointer to command details structure or NULL
2030  *
2031  * Get the Local AN advertisement register value.
2032  **/
2033 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2034                                 u64 advt_reg,
2035                                 struct i40e_asq_cmd_details *cmd_details)
2036 {
2037         struct i40e_aq_desc desc;
2038         struct i40e_aqc_an_advt_reg *cmd =
2039                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2040         enum i40e_status_code status;
2041
2042         i40e_fill_default_direct_cmd_desc(&desc,
2043                                           i40e_aqc_opc_get_local_advt_reg);
2044
2045         cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2046         cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2047
2048         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2049
2050         return status;
2051 }
2052
2053 /**
2054  * i40e_aq_get_partner_advt
2055  * @hw: pointer to the hw struct
2056  * @advt_reg: AN partner advertisement register value
2057  * @cmd_details: pointer to command details structure or NULL
2058  *
2059  * Get the link partner AN advertisement register value.
2060  **/
2061 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2062                                 u64 *advt_reg,
2063                                 struct i40e_asq_cmd_details *cmd_details)
2064 {
2065         struct i40e_aq_desc desc;
2066         struct i40e_aqc_an_advt_reg *resp =
2067                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2068         enum i40e_status_code status;
2069
2070         i40e_fill_default_direct_cmd_desc(&desc,
2071                                           i40e_aqc_opc_get_partner_advt);
2072
2073         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2074
2075         if (status != I40E_SUCCESS)
2076                 goto aq_get_partner_advt_exit;
2077
2078         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2079         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2080
2081 aq_get_partner_advt_exit:
2082         return status;
2083 }
2084
2085 /**
2086  * i40e_aq_set_lb_modes
2087  * @hw: pointer to the hw struct
2088  * @lb_modes: loopback mode to be set
2089  * @cmd_details: pointer to command details structure or NULL
2090  *
2091  * Sets loopback modes.
2092  **/
2093 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2094                                 u16 lb_modes,
2095                                 struct i40e_asq_cmd_details *cmd_details)
2096 {
2097         struct i40e_aq_desc desc;
2098         struct i40e_aqc_set_lb_mode *cmd =
2099                 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2100         enum i40e_status_code status;
2101
2102         i40e_fill_default_direct_cmd_desc(&desc,
2103                                           i40e_aqc_opc_set_lb_modes);
2104
2105         cmd->lb_mode = CPU_TO_LE16(lb_modes);
2106
2107         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2108
2109         return status;
2110 }
2111
2112 /**
2113  * i40e_aq_set_phy_debug
2114  * @hw: pointer to the hw struct
2115  * @cmd_flags: debug command flags
2116  * @cmd_details: pointer to command details structure or NULL
2117  *
2118  * Reset the external PHY.
2119  **/
2120 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2121                                 struct i40e_asq_cmd_details *cmd_details)
2122 {
2123         struct i40e_aq_desc desc;
2124         struct i40e_aqc_set_phy_debug *cmd =
2125                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2126         enum i40e_status_code status;
2127
2128         i40e_fill_default_direct_cmd_desc(&desc,
2129                                           i40e_aqc_opc_set_phy_debug);
2130
2131         cmd->command_flags = cmd_flags;
2132
2133         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2134
2135         return status;
2136 }
2137
2138 /**
2139  * i40e_aq_add_vsi
2140  * @hw: pointer to the hw struct
2141  * @vsi_ctx: pointer to a vsi context struct
2142  * @cmd_details: pointer to command details structure or NULL
2143  *
2144  * Add a VSI context to the hardware.
2145 **/
2146 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2147                                 struct i40e_vsi_context *vsi_ctx,
2148                                 struct i40e_asq_cmd_details *cmd_details)
2149 {
2150         struct i40e_aq_desc desc;
2151         struct i40e_aqc_add_get_update_vsi *cmd =
2152                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2153         struct i40e_aqc_add_get_update_vsi_completion *resp =
2154                 (struct i40e_aqc_add_get_update_vsi_completion *)
2155                 &desc.params.raw;
2156         enum i40e_status_code status;
2157
2158         i40e_fill_default_direct_cmd_desc(&desc,
2159                                           i40e_aqc_opc_add_vsi);
2160
2161         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2162         cmd->connection_type = vsi_ctx->connection_type;
2163         cmd->vf_id = vsi_ctx->vf_num;
2164         cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2165
2166         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2167
2168         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2169                                     sizeof(vsi_ctx->info), cmd_details);
2170
2171         if (status != I40E_SUCCESS)
2172                 goto aq_add_vsi_exit;
2173
2174         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2175         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2176         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2177         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2178
2179 aq_add_vsi_exit:
2180         return status;
2181 }
2182
2183 /**
2184  * i40e_aq_set_default_vsi
2185  * @hw: pointer to the hw struct
2186  * @seid: vsi number
2187  * @cmd_details: pointer to command details structure or NULL
2188  **/
2189 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2190                                 u16 seid,
2191                                 struct i40e_asq_cmd_details *cmd_details)
2192 {
2193         struct i40e_aq_desc desc;
2194         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2195                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2196                 &desc.params.raw;
2197         enum i40e_status_code status;
2198
2199         i40e_fill_default_direct_cmd_desc(&desc,
2200                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2201
2202         cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2203         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2204         cmd->seid = CPU_TO_LE16(seid);
2205
2206         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2207
2208         return status;
2209 }
2210
2211 /**
2212  * i40e_aq_set_vsi_unicast_promiscuous
2213  * @hw: pointer to the hw struct
2214  * @seid: vsi number
2215  * @set: set unicast promiscuous enable/disable
2216  * @cmd_details: pointer to command details structure or NULL
2217  * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2218  **/
2219 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2220                                 u16 seid, bool set,
2221                                 struct i40e_asq_cmd_details *cmd_details,
2222                                 bool rx_only_promisc)
2223 {
2224         struct i40e_aq_desc desc;
2225         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2226                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2227         enum i40e_status_code status;
2228         u16 flags = 0;
2229
2230         i40e_fill_default_direct_cmd_desc(&desc,
2231                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2232
2233         if (set) {
2234                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2235                 if (rx_only_promisc &&
2236                     (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2237                      (hw->aq.api_maj_ver > 1)))
2238                         flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2239         }
2240
2241         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2242
2243         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2244         if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2245              (hw->aq.api_maj_ver > 1))
2246                 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2247
2248         cmd->seid = CPU_TO_LE16(seid);
2249         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2250
2251         return status;
2252 }
2253
2254 /**
2255  * i40e_aq_set_vsi_multicast_promiscuous
2256  * @hw: pointer to the hw struct
2257  * @seid: vsi number
2258  * @set: set multicast promiscuous enable/disable
2259  * @cmd_details: pointer to command details structure or NULL
2260  **/
2261 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2262                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2263 {
2264         struct i40e_aq_desc desc;
2265         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2266                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2267         enum i40e_status_code status;
2268         u16 flags = 0;
2269
2270         i40e_fill_default_direct_cmd_desc(&desc,
2271                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2272
2273         if (set)
2274                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2275
2276         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2277
2278         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2279
2280         cmd->seid = CPU_TO_LE16(seid);
2281         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2282
2283         return status;
2284 }
2285
2286 /**
2287  * i40e_aq_set_vsi_mc_promisc_on_vlan
2288  * @hw: pointer to the hw struct
2289  * @seid: vsi number
2290  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2291  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2292  * @cmd_details: pointer to command details structure or NULL
2293  **/
2294 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2295                                 u16 seid, bool enable, u16 vid,
2296                                 struct i40e_asq_cmd_details *cmd_details)
2297 {
2298         struct i40e_aq_desc desc;
2299         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2300                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2301         enum i40e_status_code status;
2302         u16 flags = 0;
2303
2304         i40e_fill_default_direct_cmd_desc(&desc,
2305                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2306
2307         if (enable)
2308                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2309
2310         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2311         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2312         cmd->seid = CPU_TO_LE16(seid);
2313         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2314
2315         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2316
2317         return status;
2318 }
2319
2320 /**
2321  * i40e_aq_set_vsi_uc_promisc_on_vlan
2322  * @hw: pointer to the hw struct
2323  * @seid: vsi number
2324  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2325  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2326  * @cmd_details: pointer to command details structure or NULL
2327  **/
2328 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2329                                 u16 seid, bool enable, u16 vid,
2330                                 struct i40e_asq_cmd_details *cmd_details)
2331 {
2332         struct i40e_aq_desc desc;
2333         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2334                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2335         enum i40e_status_code status;
2336         u16 flags = 0;
2337
2338         i40e_fill_default_direct_cmd_desc(&desc,
2339                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2340
2341         if (enable)
2342                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2343
2344         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2345         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2346         cmd->seid = CPU_TO_LE16(seid);
2347         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2348
2349         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2350
2351         return status;
2352 }
2353
2354 /**
2355  * i40e_aq_set_vsi_broadcast
2356  * @hw: pointer to the hw struct
2357  * @seid: vsi number
2358  * @set_filter: true to set filter, false to clear filter
2359  * @cmd_details: pointer to command details structure or NULL
2360  *
2361  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2362  **/
2363 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2364                                 u16 seid, bool set_filter,
2365                                 struct i40e_asq_cmd_details *cmd_details)
2366 {
2367         struct i40e_aq_desc desc;
2368         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2369                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2370         enum i40e_status_code status;
2371
2372         i40e_fill_default_direct_cmd_desc(&desc,
2373                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2374
2375         if (set_filter)
2376                 cmd->promiscuous_flags
2377                             |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2378         else
2379                 cmd->promiscuous_flags
2380                             &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2381
2382         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2383         cmd->seid = CPU_TO_LE16(seid);
2384         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2385
2386         return status;
2387 }
2388
2389 /**
2390  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2391  * @hw: pointer to the hw struct
2392  * @seid: vsi number
2393  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2394  * @cmd_details: pointer to command details structure or NULL
2395  **/
2396 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2397                                 u16 seid, bool enable,
2398                                 struct i40e_asq_cmd_details *cmd_details)
2399 {
2400         struct i40e_aq_desc desc;
2401         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2402                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2403         enum i40e_status_code status;
2404         u16 flags = 0;
2405
2406         i40e_fill_default_direct_cmd_desc(&desc,
2407                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2408         if (enable)
2409                 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2410
2411         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2412         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2413         cmd->seid = CPU_TO_LE16(seid);
2414
2415         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2416
2417         return status;
2418 }
2419
2420 /**
2421  * i40e_get_vsi_params - get VSI configuration info
2422  * @hw: pointer to the hw struct
2423  * @vsi_ctx: pointer to a vsi context struct
2424  * @cmd_details: pointer to command details structure or NULL
2425  **/
2426 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2427                                 struct i40e_vsi_context *vsi_ctx,
2428                                 struct i40e_asq_cmd_details *cmd_details)
2429 {
2430         struct i40e_aq_desc desc;
2431         struct i40e_aqc_add_get_update_vsi *cmd =
2432                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2433         struct i40e_aqc_add_get_update_vsi_completion *resp =
2434                 (struct i40e_aqc_add_get_update_vsi_completion *)
2435                 &desc.params.raw;
2436         enum i40e_status_code status;
2437
2438         UNREFERENCED_1PARAMETER(cmd_details);
2439         i40e_fill_default_direct_cmd_desc(&desc,
2440                                           i40e_aqc_opc_get_vsi_parameters);
2441
2442         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2443
2444         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2445
2446         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2447                                     sizeof(vsi_ctx->info), NULL);
2448
2449         if (status != I40E_SUCCESS)
2450                 goto aq_get_vsi_params_exit;
2451
2452         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2453         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2454         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2455         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2456
2457 aq_get_vsi_params_exit:
2458         return status;
2459 }
2460
2461 /**
2462  * i40e_aq_update_vsi_params
2463  * @hw: pointer to the hw struct
2464  * @vsi_ctx: pointer to a vsi context struct
2465  * @cmd_details: pointer to command details structure or NULL
2466  *
2467  * Update a VSI context.
2468  **/
2469 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2470                                 struct i40e_vsi_context *vsi_ctx,
2471                                 struct i40e_asq_cmd_details *cmd_details)
2472 {
2473         struct i40e_aq_desc desc;
2474         struct i40e_aqc_add_get_update_vsi *cmd =
2475                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2476         struct i40e_aqc_add_get_update_vsi_completion *resp =
2477                 (struct i40e_aqc_add_get_update_vsi_completion *)
2478                 &desc.params.raw;
2479         enum i40e_status_code status;
2480
2481         i40e_fill_default_direct_cmd_desc(&desc,
2482                                           i40e_aqc_opc_update_vsi_parameters);
2483         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2484
2485         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2486
2487         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2488                                     sizeof(vsi_ctx->info), cmd_details);
2489
2490         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2491         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2492
2493         return status;
2494 }
2495
2496 /**
2497  * i40e_aq_get_switch_config
2498  * @hw: pointer to the hardware structure
2499  * @buf: pointer to the result buffer
2500  * @buf_size: length of input buffer
2501  * @start_seid: seid to start for the report, 0 == beginning
2502  * @cmd_details: pointer to command details structure or NULL
2503  *
2504  * Fill the buf with switch configuration returned from AdminQ command
2505  **/
2506 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2507                                 struct i40e_aqc_get_switch_config_resp *buf,
2508                                 u16 buf_size, u16 *start_seid,
2509                                 struct i40e_asq_cmd_details *cmd_details)
2510 {
2511         struct i40e_aq_desc desc;
2512         struct i40e_aqc_switch_seid *scfg =
2513                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2514         enum i40e_status_code status;
2515
2516         i40e_fill_default_direct_cmd_desc(&desc,
2517                                           i40e_aqc_opc_get_switch_config);
2518         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2519         if (buf_size > I40E_AQ_LARGE_BUF)
2520                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2521         scfg->seid = CPU_TO_LE16(*start_seid);
2522
2523         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2524         *start_seid = LE16_TO_CPU(scfg->seid);
2525
2526         return status;
2527 }
2528
2529 /**
2530  * i40e_aq_set_switch_config
2531  * @hw: pointer to the hardware structure
2532  * @flags: bit flag values to set
2533  * @valid_flags: which bit flags to set
2534  * @cmd_details: pointer to command details structure or NULL
2535  *
2536  * Set switch configuration bits
2537  **/
2538 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2539                                 u16 flags, u16 valid_flags,
2540                                 struct i40e_asq_cmd_details *cmd_details)
2541 {
2542         struct i40e_aq_desc desc;
2543         struct i40e_aqc_set_switch_config *scfg =
2544                 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2545         enum i40e_status_code status;
2546
2547         i40e_fill_default_direct_cmd_desc(&desc,
2548                                           i40e_aqc_opc_set_switch_config);
2549         scfg->flags = CPU_TO_LE16(flags);
2550         scfg->valid_flags = CPU_TO_LE16(valid_flags);
2551
2552         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2553
2554         return status;
2555 }
2556
2557 /**
2558  * i40e_aq_get_firmware_version
2559  * @hw: pointer to the hw struct
2560  * @fw_major_version: firmware major version
2561  * @fw_minor_version: firmware minor version
2562  * @fw_build: firmware build number
2563  * @api_major_version: major queue version
2564  * @api_minor_version: minor queue version
2565  * @cmd_details: pointer to command details structure or NULL
2566  *
2567  * Get the firmware version from the admin queue commands
2568  **/
2569 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2570                                 u16 *fw_major_version, u16 *fw_minor_version,
2571                                 u32 *fw_build,
2572                                 u16 *api_major_version, u16 *api_minor_version,
2573                                 struct i40e_asq_cmd_details *cmd_details)
2574 {
2575         struct i40e_aq_desc desc;
2576         struct i40e_aqc_get_version *resp =
2577                 (struct i40e_aqc_get_version *)&desc.params.raw;
2578         enum i40e_status_code status;
2579
2580         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2581
2582         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2583
2584         if (status == I40E_SUCCESS) {
2585                 if (fw_major_version != NULL)
2586                         *fw_major_version = LE16_TO_CPU(resp->fw_major);
2587                 if (fw_minor_version != NULL)
2588                         *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2589                 if (fw_build != NULL)
2590                         *fw_build = LE32_TO_CPU(resp->fw_build);
2591                 if (api_major_version != NULL)
2592                         *api_major_version = LE16_TO_CPU(resp->api_major);
2593                 if (api_minor_version != NULL)
2594                         *api_minor_version = LE16_TO_CPU(resp->api_minor);
2595
2596                 /* A workaround to fix the API version in SW */
2597                 if (api_major_version && api_minor_version &&
2598                     fw_major_version && fw_minor_version &&
2599                     ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2600                     (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2601                      (*fw_major_version > 4)))
2602                         *api_minor_version = 2;
2603         }
2604
2605         return status;
2606 }
2607
2608 /**
2609  * i40e_aq_send_driver_version
2610  * @hw: pointer to the hw struct
2611  * @dv: driver's major, minor version
2612  * @cmd_details: pointer to command details structure or NULL
2613  *
2614  * Send the driver version to the firmware
2615  **/
2616 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2617                                 struct i40e_driver_version *dv,
2618                                 struct i40e_asq_cmd_details *cmd_details)
2619 {
2620         struct i40e_aq_desc desc;
2621         struct i40e_aqc_driver_version *cmd =
2622                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2623         enum i40e_status_code status;
2624         u16 len;
2625
2626         if (dv == NULL)
2627                 return I40E_ERR_PARAM;
2628
2629         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2630
2631         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2632         cmd->driver_major_ver = dv->major_version;
2633         cmd->driver_minor_ver = dv->minor_version;
2634         cmd->driver_build_ver = dv->build_version;
2635         cmd->driver_subbuild_ver = dv->subbuild_version;
2636
2637         len = 0;
2638         while (len < sizeof(dv->driver_string) &&
2639                (dv->driver_string[len] < 0x80) &&
2640                dv->driver_string[len])
2641                 len++;
2642         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2643                                        len, cmd_details);
2644
2645         return status;
2646 }
2647
2648 /**
2649  * i40e_get_link_status - get status of the HW network link
2650  * @hw: pointer to the hw struct
2651  * @link_up: pointer to bool (true/false = linkup/linkdown)
2652  *
2653  * Variable link_up true if link is up, false if link is down.
2654  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2655  *
2656  * Side effect: LinkStatusEvent reporting becomes enabled
2657  **/
2658 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2659 {
2660         enum i40e_status_code status = I40E_SUCCESS;
2661
2662         if (hw->phy.get_link_info) {
2663                 status = i40e_update_link_info(hw);
2664
2665                 if (status != I40E_SUCCESS)
2666                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2667                                    status);
2668         }
2669
2670         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2671
2672         return status;
2673 }
2674
2675 /**
2676  * i40e_updatelink_status - update status of the HW network link
2677  * @hw: pointer to the hw struct
2678  **/
2679 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2680 {
2681         struct i40e_aq_get_phy_abilities_resp abilities;
2682         enum i40e_status_code status = I40E_SUCCESS;
2683
2684         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2685         if (status)
2686                 return status;
2687
2688         if (hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) {
2689                 status = i40e_aq_get_phy_capabilities(hw, false, false,
2690                                                       &abilities, NULL);
2691                 if (status)
2692                         return status;
2693
2694                 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2695                         sizeof(hw->phy.link_info.module_type));
2696         }
2697         return status;
2698 }
2699
2700
2701 /**
2702  * i40e_get_link_speed
2703  * @hw: pointer to the hw struct
2704  *
2705  * Returns the link speed of the adapter.
2706  **/
2707 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2708 {
2709         enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2710         enum i40e_status_code status = I40E_SUCCESS;
2711
2712         if (hw->phy.get_link_info) {
2713                 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2714
2715                 if (status != I40E_SUCCESS)
2716                         goto i40e_link_speed_exit;
2717         }
2718
2719         speed = hw->phy.link_info.link_speed;
2720
2721 i40e_link_speed_exit:
2722         return speed;
2723 }
2724
2725 /**
2726  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2727  * @hw: pointer to the hw struct
2728  * @uplink_seid: the MAC or other gizmo SEID
2729  * @downlink_seid: the VSI SEID
2730  * @enabled_tc: bitmap of TCs to be enabled
2731  * @default_port: true for default port VSI, false for control port
2732  * @veb_seid: pointer to where to put the resulting VEB SEID
2733  * @enable_stats: true to turn on VEB stats
2734  * @cmd_details: pointer to command details structure or NULL
2735  *
2736  * This asks the FW to add a VEB between the uplink and downlink
2737  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2738  **/
2739 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2740                                 u16 downlink_seid, u8 enabled_tc,
2741                                 bool default_port, u16 *veb_seid,
2742                                 bool enable_stats,
2743                                 struct i40e_asq_cmd_details *cmd_details)
2744 {
2745         struct i40e_aq_desc desc;
2746         struct i40e_aqc_add_veb *cmd =
2747                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2748         struct i40e_aqc_add_veb_completion *resp =
2749                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2750         enum i40e_status_code status;
2751         u16 veb_flags = 0;
2752
2753         /* SEIDs need to either both be set or both be 0 for floating VEB */
2754         if (!!uplink_seid != !!downlink_seid)
2755                 return I40E_ERR_PARAM;
2756
2757         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2758
2759         cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2760         cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2761         cmd->enable_tcs = enabled_tc;
2762         if (!uplink_seid)
2763                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2764         if (default_port)
2765                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2766         else
2767                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2768
2769         /* reverse logic here: set the bitflag to disable the stats */
2770         if (!enable_stats)
2771                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2772
2773         cmd->veb_flags = CPU_TO_LE16(veb_flags);
2774
2775         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2776
2777         if (!status && veb_seid)
2778                 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2779
2780         return status;
2781 }
2782
2783 /**
2784  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2785  * @hw: pointer to the hw struct
2786  * @veb_seid: the SEID of the VEB to query
2787  * @switch_id: the uplink switch id
2788  * @floating: set to true if the VEB is floating
2789  * @statistic_index: index of the stats counter block for this VEB
2790  * @vebs_used: number of VEB's used by function
2791  * @vebs_free: total VEB's not reserved by any function
2792  * @cmd_details: pointer to command details structure or NULL
2793  *
2794  * This retrieves the parameters for a particular VEB, specified by
2795  * uplink_seid, and returns them to the caller.
2796  **/
2797 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2798                                 u16 veb_seid, u16 *switch_id,
2799                                 bool *floating, u16 *statistic_index,
2800                                 u16 *vebs_used, u16 *vebs_free,
2801                                 struct i40e_asq_cmd_details *cmd_details)
2802 {
2803         struct i40e_aq_desc desc;
2804         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2805                 (struct i40e_aqc_get_veb_parameters_completion *)
2806                 &desc.params.raw;
2807         enum i40e_status_code status;
2808
2809         if (veb_seid == 0)
2810                 return I40E_ERR_PARAM;
2811
2812         i40e_fill_default_direct_cmd_desc(&desc,
2813                                           i40e_aqc_opc_get_veb_parameters);
2814         cmd_resp->seid = CPU_TO_LE16(veb_seid);
2815
2816         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2817         if (status)
2818                 goto get_veb_exit;
2819
2820         if (switch_id)
2821                 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2822         if (statistic_index)
2823                 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2824         if (vebs_used)
2825                 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2826         if (vebs_free)
2827                 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2828         if (floating) {
2829                 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2830
2831                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2832                         *floating = true;
2833                 else
2834                         *floating = false;
2835         }
2836
2837 get_veb_exit:
2838         return status;
2839 }
2840
2841 /**
2842  * i40e_aq_add_macvlan
2843  * @hw: pointer to the hw struct
2844  * @seid: VSI for the mac address
2845  * @mv_list: list of macvlans to be added
2846  * @count: length of the list
2847  * @cmd_details: pointer to command details structure or NULL
2848  *
2849  * Add MAC/VLAN addresses to the HW filtering
2850  **/
2851 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2852                         struct i40e_aqc_add_macvlan_element_data *mv_list,
2853                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2854 {
2855         struct i40e_aq_desc desc;
2856         struct i40e_aqc_macvlan *cmd =
2857                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2858         enum i40e_status_code status;
2859         u16 buf_size;
2860         int i;
2861
2862         if (count == 0 || !mv_list || !hw)
2863                 return I40E_ERR_PARAM;
2864
2865         buf_size = count * sizeof(*mv_list);
2866
2867         /* prep the rest of the request */
2868         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2869         cmd->num_addresses = CPU_TO_LE16(count);
2870         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2871         cmd->seid[1] = 0;
2872         cmd->seid[2] = 0;
2873
2874         for (i = 0; i < count; i++)
2875                 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
2876                         mv_list[i].flags |=
2877                             CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2878
2879         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2880         if (buf_size > I40E_AQ_LARGE_BUF)
2881                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2882
2883         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2884                                        cmd_details);
2885
2886         return status;
2887 }
2888
2889 /**
2890  * i40e_aq_remove_macvlan
2891  * @hw: pointer to the hw struct
2892  * @seid: VSI for the mac address
2893  * @mv_list: list of macvlans to be removed
2894  * @count: length of the list
2895  * @cmd_details: pointer to command details structure or NULL
2896  *
2897  * Remove MAC/VLAN addresses from the HW filtering
2898  **/
2899 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2900                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
2901                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2902 {
2903         struct i40e_aq_desc desc;
2904         struct i40e_aqc_macvlan *cmd =
2905                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2906         enum i40e_status_code status;
2907         u16 buf_size;
2908
2909         if (count == 0 || !mv_list || !hw)
2910                 return I40E_ERR_PARAM;
2911
2912         buf_size = count * sizeof(*mv_list);
2913
2914         /* prep the rest of the request */
2915         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2916         cmd->num_addresses = CPU_TO_LE16(count);
2917         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2918         cmd->seid[1] = 0;
2919         cmd->seid[2] = 0;
2920
2921         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2922         if (buf_size > I40E_AQ_LARGE_BUF)
2923                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2924
2925         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2926                                        cmd_details);
2927
2928         return status;
2929 }
2930
2931 /**
2932  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
2933  * @hw: pointer to the hw struct
2934  * @opcode: AQ opcode for add or delete mirror rule
2935  * @sw_seid: Switch SEID (to which rule refers)
2936  * @rule_type: Rule Type (ingress/egress/VLAN)
2937  * @id: Destination VSI SEID or Rule ID
2938  * @count: length of the list
2939  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2940  * @cmd_details: pointer to command details structure or NULL
2941  * @rule_id: Rule ID returned from FW
2942  * @rule_used: Number of rules used in internal switch
2943  * @rule_free: Number of rules free in internal switch
2944  *
2945  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
2946  * VEBs/VEPA elements only
2947  **/
2948 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
2949                         u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
2950                         u16 count, __le16 *mr_list,
2951                         struct i40e_asq_cmd_details *cmd_details,
2952                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
2953 {
2954         struct i40e_aq_desc desc;
2955         struct i40e_aqc_add_delete_mirror_rule *cmd =
2956                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
2957         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
2958         (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
2959         enum i40e_status_code status;
2960         u16 buf_size;
2961
2962         buf_size = count * sizeof(*mr_list);
2963
2964         /* prep the rest of the request */
2965         i40e_fill_default_direct_cmd_desc(&desc, opcode);
2966         cmd->seid = CPU_TO_LE16(sw_seid);
2967         cmd->rule_type = CPU_TO_LE16(rule_type &
2968                                      I40E_AQC_MIRROR_RULE_TYPE_MASK);
2969         cmd->num_entries = CPU_TO_LE16(count);
2970         /* Dest VSI for add, rule_id for delete */
2971         cmd->destination = CPU_TO_LE16(id);
2972         if (mr_list) {
2973                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
2974                                                 I40E_AQ_FLAG_RD));
2975                 if (buf_size > I40E_AQ_LARGE_BUF)
2976                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2977         }
2978
2979         status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
2980                                        cmd_details);
2981         if (status == I40E_SUCCESS ||
2982             hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
2983                 if (rule_id)
2984                         *rule_id = LE16_TO_CPU(resp->rule_id);
2985                 if (rules_used)
2986                         *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
2987                 if (rules_free)
2988                         *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
2989         }
2990         return status;
2991 }
2992
2993 /**
2994  * i40e_aq_add_mirrorrule - add a mirror rule
2995  * @hw: pointer to the hw struct
2996  * @sw_seid: Switch SEID (to which rule refers)
2997  * @rule_type: Rule Type (ingress/egress/VLAN)
2998  * @dest_vsi: SEID of VSI to which packets will be mirrored
2999  * @count: length of the list
3000  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3001  * @cmd_details: pointer to command details structure or NULL
3002  * @rule_id: Rule ID returned from FW
3003  * @rule_used: Number of rules used in internal switch
3004  * @rule_free: Number of rules free in internal switch
3005  *
3006  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3007  **/
3008 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3009                         u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3010                         struct i40e_asq_cmd_details *cmd_details,
3011                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3012 {
3013         if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3014             rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3015                 if (count == 0 || !mr_list)
3016                         return I40E_ERR_PARAM;
3017         }
3018
3019         return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3020                                   rule_type, dest_vsi, count, mr_list,
3021                                   cmd_details, rule_id, rules_used, rules_free);
3022 }
3023
3024 /**
3025  * i40e_aq_delete_mirrorrule - delete a mirror rule
3026  * @hw: pointer to the hw struct
3027  * @sw_seid: Switch SEID (to which rule refers)
3028  * @rule_type: Rule Type (ingress/egress/VLAN)
3029  * @count: length of the list
3030  * @rule_id: Rule ID that is returned in the receive desc as part of
3031  *              add_mirrorrule.
3032  * @mr_list: list of mirrored VLAN IDs to be removed
3033  * @cmd_details: pointer to command details structure or NULL
3034  * @rule_used: Number of rules used in internal switch
3035  * @rule_free: Number of rules free in internal switch
3036  *
3037  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3038  **/
3039 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3040                         u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3041                         struct i40e_asq_cmd_details *cmd_details,
3042                         u16 *rules_used, u16 *rules_free)
3043 {
3044         /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3045         if (rule_type != I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3046                 if (!rule_id)
3047                         return I40E_ERR_PARAM;
3048         } else {
3049                 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3050                  * mirroring. For other rule_type, count and rule_type should
3051                  * not matter.
3052                  */
3053                 if (count == 0 || !mr_list)
3054                         return I40E_ERR_PARAM;
3055         }
3056
3057         return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3058                                   rule_type, rule_id, count, mr_list,
3059                                   cmd_details, NULL, rules_used, rules_free);
3060 }
3061
3062 /**
3063  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3064  * @hw: pointer to the hw struct
3065  * @seid: VSI for the vlan filters
3066  * @v_list: list of vlan filters to be added
3067  * @count: length of the list
3068  * @cmd_details: pointer to command details structure or NULL
3069  **/
3070 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3071                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3072                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3073 {
3074         struct i40e_aq_desc desc;
3075         struct i40e_aqc_macvlan *cmd =
3076                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3077         enum i40e_status_code status;
3078         u16 buf_size;
3079
3080         if (count == 0 || !v_list || !hw)
3081                 return I40E_ERR_PARAM;
3082
3083         buf_size = count * sizeof(*v_list);
3084
3085         /* prep the rest of the request */
3086         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3087         cmd->num_addresses = CPU_TO_LE16(count);
3088         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3089         cmd->seid[1] = 0;
3090         cmd->seid[2] = 0;
3091
3092         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3093         if (buf_size > I40E_AQ_LARGE_BUF)
3094                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3095
3096         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3097                                        cmd_details);
3098
3099         return status;
3100 }
3101
3102 /**
3103  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3104  * @hw: pointer to the hw struct
3105  * @seid: VSI for the vlan filters
3106  * @v_list: list of macvlans to be removed
3107  * @count: length of the list
3108  * @cmd_details: pointer to command details structure or NULL
3109  **/
3110 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3111                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3112                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3113 {
3114         struct i40e_aq_desc desc;
3115         struct i40e_aqc_macvlan *cmd =
3116                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3117         enum i40e_status_code status;
3118         u16 buf_size;
3119
3120         if (count == 0 || !v_list || !hw)
3121                 return I40E_ERR_PARAM;
3122
3123         buf_size = count * sizeof(*v_list);
3124
3125         /* prep the rest of the request */
3126         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3127         cmd->num_addresses = CPU_TO_LE16(count);
3128         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3129         cmd->seid[1] = 0;
3130         cmd->seid[2] = 0;
3131
3132         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3133         if (buf_size > I40E_AQ_LARGE_BUF)
3134                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3135
3136         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3137                                        cmd_details);
3138
3139         return status;
3140 }
3141
3142 /**
3143  * i40e_aq_send_msg_to_vf
3144  * @hw: pointer to the hardware structure
3145  * @vfid: vf id to send msg
3146  * @v_opcode: opcodes for VF-PF communication
3147  * @v_retval: return error code
3148  * @msg: pointer to the msg buffer
3149  * @msglen: msg length
3150  * @cmd_details: pointer to command details
3151  *
3152  * send msg to vf
3153  **/
3154 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3155                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3156                                 struct i40e_asq_cmd_details *cmd_details)
3157 {
3158         struct i40e_aq_desc desc;
3159         struct i40e_aqc_pf_vf_message *cmd =
3160                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3161         enum i40e_status_code status;
3162
3163         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3164         cmd->id = CPU_TO_LE32(vfid);
3165         desc.cookie_high = CPU_TO_LE32(v_opcode);
3166         desc.cookie_low = CPU_TO_LE32(v_retval);
3167         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3168         if (msglen) {
3169                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3170                                                 I40E_AQ_FLAG_RD));
3171                 if (msglen > I40E_AQ_LARGE_BUF)
3172                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3173                 desc.datalen = CPU_TO_LE16(msglen);
3174         }
3175         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3176
3177         return status;
3178 }
3179
3180 /**
3181  * i40e_aq_debug_read_register
3182  * @hw: pointer to the hw struct
3183  * @reg_addr: register address
3184  * @reg_val: register value
3185  * @cmd_details: pointer to command details structure or NULL
3186  *
3187  * Read the register using the admin queue commands
3188  **/
3189 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3190                                 u32 reg_addr, u64 *reg_val,
3191                                 struct i40e_asq_cmd_details *cmd_details)
3192 {
3193         struct i40e_aq_desc desc;
3194         struct i40e_aqc_debug_reg_read_write *cmd_resp =
3195                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3196         enum i40e_status_code status;
3197
3198         if (reg_val == NULL)
3199                 return I40E_ERR_PARAM;
3200
3201         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3202
3203         cmd_resp->address = CPU_TO_LE32(reg_addr);
3204
3205         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3206
3207         if (status == I40E_SUCCESS) {
3208                 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3209                            (u64)LE32_TO_CPU(cmd_resp->value_low);
3210         }
3211
3212         return status;
3213 }
3214
3215 /**
3216  * i40e_aq_debug_write_register
3217  * @hw: pointer to the hw struct
3218  * @reg_addr: register address
3219  * @reg_val: register value
3220  * @cmd_details: pointer to command details structure or NULL
3221  *
3222  * Write to a register using the admin queue commands
3223  **/
3224 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3225                                 u32 reg_addr, u64 reg_val,
3226                                 struct i40e_asq_cmd_details *cmd_details)
3227 {
3228         struct i40e_aq_desc desc;
3229         struct i40e_aqc_debug_reg_read_write *cmd =
3230                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3231         enum i40e_status_code status;
3232
3233         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3234
3235         cmd->address = CPU_TO_LE32(reg_addr);
3236         cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3237         cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3238
3239         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3240
3241         return status;
3242 }
3243
3244 /**
3245  * i40e_aq_request_resource
3246  * @hw: pointer to the hw struct
3247  * @resource: resource id
3248  * @access: access type
3249  * @sdp_number: resource number
3250  * @timeout: the maximum time in ms that the driver may hold the resource
3251  * @cmd_details: pointer to command details structure or NULL
3252  *
3253  * requests common resource using the admin queue commands
3254  **/
3255 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3256                                 enum i40e_aq_resources_ids resource,
3257                                 enum i40e_aq_resource_access_type access,
3258                                 u8 sdp_number, u64 *timeout,
3259                                 struct i40e_asq_cmd_details *cmd_details)
3260 {
3261         struct i40e_aq_desc desc;
3262         struct i40e_aqc_request_resource *cmd_resp =
3263                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3264         enum i40e_status_code status;
3265
3266         DEBUGFUNC("i40e_aq_request_resource");
3267
3268         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3269
3270         cmd_resp->resource_id = CPU_TO_LE16(resource);
3271         cmd_resp->access_type = CPU_TO_LE16(access);
3272         cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3273
3274         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3275         /* The completion specifies the maximum time in ms that the driver
3276          * may hold the resource in the Timeout field.
3277          * If the resource is held by someone else, the command completes with
3278          * busy return value and the timeout field indicates the maximum time
3279          * the current owner of the resource has to free it.
3280          */
3281         if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3282                 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3283
3284         return status;
3285 }
3286
3287 /**
3288  * i40e_aq_release_resource
3289  * @hw: pointer to the hw struct
3290  * @resource: resource id
3291  * @sdp_number: resource number
3292  * @cmd_details: pointer to command details structure or NULL
3293  *
3294  * release common resource using the admin queue commands
3295  **/
3296 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3297                                 enum i40e_aq_resources_ids resource,
3298                                 u8 sdp_number,
3299                                 struct i40e_asq_cmd_details *cmd_details)
3300 {
3301         struct i40e_aq_desc desc;
3302         struct i40e_aqc_request_resource *cmd =
3303                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3304         enum i40e_status_code status;
3305
3306         DEBUGFUNC("i40e_aq_release_resource");
3307
3308         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3309
3310         cmd->resource_id = CPU_TO_LE16(resource);
3311         cmd->resource_number = CPU_TO_LE32(sdp_number);
3312
3313         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3314
3315         return status;
3316 }
3317
3318 /**
3319  * i40e_aq_read_nvm
3320  * @hw: pointer to the hw struct
3321  * @module_pointer: module pointer location in words from the NVM beginning
3322  * @offset: byte offset from the module beginning
3323  * @length: length of the section to be read (in bytes from the offset)
3324  * @data: command buffer (size [bytes] = length)
3325  * @last_command: tells if this is the last command in a series
3326  * @cmd_details: pointer to command details structure or NULL
3327  *
3328  * Read the NVM using the admin queue commands
3329  **/
3330 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3331                                 u32 offset, u16 length, void *data,
3332                                 bool last_command,
3333                                 struct i40e_asq_cmd_details *cmd_details)
3334 {
3335         struct i40e_aq_desc desc;
3336         struct i40e_aqc_nvm_update *cmd =
3337                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3338         enum i40e_status_code status;
3339
3340         DEBUGFUNC("i40e_aq_read_nvm");
3341
3342         /* In offset the highest byte must be zeroed. */
3343         if (offset & 0xFF000000) {
3344                 status = I40E_ERR_PARAM;
3345                 goto i40e_aq_read_nvm_exit;
3346         }
3347
3348         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3349
3350         /* If this is the last command in a series, set the proper flag. */
3351         if (last_command)
3352                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3353         cmd->module_pointer = module_pointer;
3354         cmd->offset = CPU_TO_LE32(offset);
3355         cmd->length = CPU_TO_LE16(length);
3356
3357         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3358         if (length > I40E_AQ_LARGE_BUF)
3359                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3360
3361         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3362
3363 i40e_aq_read_nvm_exit:
3364         return status;
3365 }
3366
3367 /**
3368  * i40e_aq_read_nvm_config - read an nvm config block
3369  * @hw: pointer to the hw struct
3370  * @cmd_flags: NVM access admin command bits
3371  * @field_id: field or feature id
3372  * @data: buffer for result
3373  * @buf_size: buffer size
3374  * @element_count: pointer to count of elements read by FW
3375  * @cmd_details: pointer to command details structure or NULL
3376  **/
3377 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3378                                 u8 cmd_flags, u32 field_id, void *data,
3379                                 u16 buf_size, u16 *element_count,
3380                                 struct i40e_asq_cmd_details *cmd_details)
3381 {
3382         struct i40e_aq_desc desc;
3383         struct i40e_aqc_nvm_config_read *cmd =
3384                 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3385         enum i40e_status_code status;
3386
3387         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3388         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3389         if (buf_size > I40E_AQ_LARGE_BUF)
3390                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3391
3392         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3393         cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3394         if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3395                 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3396         else
3397                 cmd->element_id_msw = 0;
3398
3399         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3400
3401         if (!status && element_count)
3402                 *element_count = LE16_TO_CPU(cmd->element_count);
3403
3404         return status;
3405 }
3406
3407 /**
3408  * i40e_aq_write_nvm_config - write an nvm config block
3409  * @hw: pointer to the hw struct
3410  * @cmd_flags: NVM access admin command bits
3411  * @data: buffer for result
3412  * @buf_size: buffer size
3413  * @element_count: count of elements to be written
3414  * @cmd_details: pointer to command details structure or NULL
3415  **/
3416 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3417                                 u8 cmd_flags, void *data, u16 buf_size,
3418                                 u16 element_count,
3419                                 struct i40e_asq_cmd_details *cmd_details)
3420 {
3421         struct i40e_aq_desc desc;
3422         struct i40e_aqc_nvm_config_write *cmd =
3423                 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3424         enum i40e_status_code status;
3425
3426         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3427         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3428         if (buf_size > I40E_AQ_LARGE_BUF)
3429                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3430
3431         cmd->element_count = CPU_TO_LE16(element_count);
3432         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3433         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3434
3435         return status;
3436 }
3437
3438 /**
3439  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3440  * @hw: pointer to the hw struct
3441  * @cmd_details: pointer to command details structure or NULL
3442  **/
3443 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3444                                 void *buff, u16 buff_size,
3445                                 struct i40e_asq_cmd_details *cmd_details)
3446 {
3447         struct i40e_aq_desc desc;
3448         enum i40e_status_code status;
3449
3450         UNREFERENCED_2PARAMETER(buff, buff_size);
3451
3452         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3453         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3454         if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3455                 status = I40E_ERR_NOT_IMPLEMENTED;
3456
3457         return status;
3458 }
3459
3460 /**
3461  * i40e_aq_erase_nvm
3462  * @hw: pointer to the hw struct
3463  * @module_pointer: module pointer location in words from the NVM beginning
3464  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3465  * @length: length of the section to be erased (expressed in 4 KB)
3466  * @last_command: tells if this is the last command in a series
3467  * @cmd_details: pointer to command details structure or NULL
3468  *
3469  * Erase the NVM sector using the admin queue commands
3470  **/
3471 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3472                                 u32 offset, u16 length, bool last_command,
3473                                 struct i40e_asq_cmd_details *cmd_details)
3474 {
3475         struct i40e_aq_desc desc;
3476         struct i40e_aqc_nvm_update *cmd =
3477                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3478         enum i40e_status_code status;
3479
3480         DEBUGFUNC("i40e_aq_erase_nvm");
3481
3482         /* In offset the highest byte must be zeroed. */
3483         if (offset & 0xFF000000) {
3484                 status = I40E_ERR_PARAM;
3485                 goto i40e_aq_erase_nvm_exit;
3486         }
3487
3488         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3489
3490         /* If this is the last command in a series, set the proper flag. */
3491         if (last_command)
3492                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3493         cmd->module_pointer = module_pointer;
3494         cmd->offset = CPU_TO_LE32(offset);
3495         cmd->length = CPU_TO_LE16(length);
3496
3497         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3498
3499 i40e_aq_erase_nvm_exit:
3500         return status;
3501 }
3502
3503 /**
3504  * i40e_parse_discover_capabilities
3505  * @hw: pointer to the hw struct
3506  * @buff: pointer to a buffer containing device/function capability records
3507  * @cap_count: number of capability records in the list
3508  * @list_type_opc: type of capabilities list to parse
3509  *
3510  * Parse the device/function capabilities list.
3511  **/
3512 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3513                                      u32 cap_count,
3514                                      enum i40e_admin_queue_opc list_type_opc)
3515 {
3516         struct i40e_aqc_list_capabilities_element_resp *cap;
3517         u32 valid_functions, num_functions;
3518         u32 number, logical_id, phys_id;
3519         struct i40e_hw_capabilities *p;
3520         u8 major_rev;
3521         u32 i = 0;
3522         u16 id;
3523
3524         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3525
3526         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3527                 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3528         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3529                 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3530         else
3531                 return;
3532
3533         for (i = 0; i < cap_count; i++, cap++) {
3534                 id = LE16_TO_CPU(cap->id);
3535                 number = LE32_TO_CPU(cap->number);
3536                 logical_id = LE32_TO_CPU(cap->logical_id);
3537                 phys_id = LE32_TO_CPU(cap->phys_id);
3538                 major_rev = cap->major_rev;
3539
3540                 switch (id) {
3541                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3542                         p->switch_mode = number;
3543                         i40e_debug(hw, I40E_DEBUG_INIT,
3544                                    "HW Capability: Switch mode = %d\n",
3545                                    p->switch_mode);
3546                         break;
3547                 case I40E_AQ_CAP_ID_MNG_MODE:
3548                         p->management_mode = number;
3549                         i40e_debug(hw, I40E_DEBUG_INIT,
3550                                    "HW Capability: Management Mode = %d\n",
3551                                    p->management_mode);
3552                         break;
3553                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3554                         p->npar_enable = number;
3555                         i40e_debug(hw, I40E_DEBUG_INIT,
3556                                    "HW Capability: NPAR enable = %d\n",
3557                                    p->npar_enable);
3558                         break;
3559                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3560                         p->os2bmc = number;
3561                         i40e_debug(hw, I40E_DEBUG_INIT,
3562                                    "HW Capability: OS2BMC = %d\n", p->os2bmc);
3563                         break;
3564                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3565                         p->valid_functions = number;
3566                         i40e_debug(hw, I40E_DEBUG_INIT,
3567                                    "HW Capability: Valid Functions = %d\n",
3568                                    p->valid_functions);
3569                         break;
3570                 case I40E_AQ_CAP_ID_SRIOV:
3571                         if (number == 1)
3572                                 p->sr_iov_1_1 = true;
3573                         i40e_debug(hw, I40E_DEBUG_INIT,
3574                                    "HW Capability: SR-IOV = %d\n",
3575                                    p->sr_iov_1_1);
3576                         break;
3577                 case I40E_AQ_CAP_ID_VF:
3578                         p->num_vfs = number;
3579                         p->vf_base_id = logical_id;
3580                         i40e_debug(hw, I40E_DEBUG_INIT,
3581                                    "HW Capability: VF count = %d\n",
3582                                    p->num_vfs);
3583                         i40e_debug(hw, I40E_DEBUG_INIT,
3584                                    "HW Capability: VF base_id = %d\n",
3585                                    p->vf_base_id);
3586                         break;
3587                 case I40E_AQ_CAP_ID_VMDQ:
3588                         if (number == 1)
3589                                 p->vmdq = true;
3590                         i40e_debug(hw, I40E_DEBUG_INIT,
3591                                    "HW Capability: VMDQ = %d\n", p->vmdq);
3592                         break;
3593                 case I40E_AQ_CAP_ID_8021QBG:
3594                         if (number == 1)
3595                                 p->evb_802_1_qbg = true;
3596                         i40e_debug(hw, I40E_DEBUG_INIT,
3597                                    "HW Capability: 802.1Qbg = %d\n", number);
3598                         break;
3599                 case I40E_AQ_CAP_ID_8021QBR:
3600                         if (number == 1)
3601                                 p->evb_802_1_qbh = true;
3602                         i40e_debug(hw, I40E_DEBUG_INIT,
3603                                    "HW Capability: 802.1Qbh = %d\n", number);
3604                         break;
3605                 case I40E_AQ_CAP_ID_VSI:
3606                         p->num_vsis = number;
3607                         i40e_debug(hw, I40E_DEBUG_INIT,
3608                                    "HW Capability: VSI count = %d\n",
3609                                    p->num_vsis);
3610                         break;
3611                 case I40E_AQ_CAP_ID_DCB:
3612                         if (number == 1) {
3613                                 p->dcb = true;
3614                                 p->enabled_tcmap = logical_id;
3615                                 p->maxtc = phys_id;
3616                         }
3617                         i40e_debug(hw, I40E_DEBUG_INIT,
3618                                    "HW Capability: DCB = %d\n", p->dcb);
3619                         i40e_debug(hw, I40E_DEBUG_INIT,
3620                                    "HW Capability: TC Mapping = %d\n",
3621                                    logical_id);
3622                         i40e_debug(hw, I40E_DEBUG_INIT,
3623                                    "HW Capability: TC Max = %d\n", p->maxtc);
3624                         break;
3625                 case I40E_AQ_CAP_ID_FCOE:
3626                         if (number == 1)
3627                                 p->fcoe = true;
3628                         i40e_debug(hw, I40E_DEBUG_INIT,
3629                                    "HW Capability: FCOE = %d\n", p->fcoe);
3630                         break;
3631                 case I40E_AQ_CAP_ID_ISCSI:
3632                         if (number == 1)
3633                                 p->iscsi = true;
3634                         i40e_debug(hw, I40E_DEBUG_INIT,
3635                                    "HW Capability: iSCSI = %d\n", p->iscsi);
3636                         break;
3637                 case I40E_AQ_CAP_ID_RSS:
3638                         p->rss = true;
3639                         p->rss_table_size = number;
3640                         p->rss_table_entry_width = logical_id;
3641                         i40e_debug(hw, I40E_DEBUG_INIT,
3642                                    "HW Capability: RSS = %d\n", p->rss);
3643                         i40e_debug(hw, I40E_DEBUG_INIT,
3644                                    "HW Capability: RSS table size = %d\n",
3645                                    p->rss_table_size);
3646                         i40e_debug(hw, I40E_DEBUG_INIT,
3647                                    "HW Capability: RSS table width = %d\n",
3648                                    p->rss_table_entry_width);
3649                         break;
3650                 case I40E_AQ_CAP_ID_RXQ:
3651                         p->num_rx_qp = number;
3652                         p->base_queue = phys_id;
3653                         i40e_debug(hw, I40E_DEBUG_INIT,
3654                                    "HW Capability: Rx QP = %d\n", number);
3655                         i40e_debug(hw, I40E_DEBUG_INIT,
3656                                    "HW Capability: base_queue = %d\n",
3657                                    p->base_queue);
3658                         break;
3659                 case I40E_AQ_CAP_ID_TXQ:
3660                         p->num_tx_qp = number;
3661                         p->base_queue = phys_id;
3662                         i40e_debug(hw, I40E_DEBUG_INIT,
3663                                    "HW Capability: Tx QP = %d\n", number);
3664                         i40e_debug(hw, I40E_DEBUG_INIT,
3665                                    "HW Capability: base_queue = %d\n",
3666                                    p->base_queue);
3667                         break;
3668                 case I40E_AQ_CAP_ID_MSIX:
3669                         p->num_msix_vectors = number;
3670                         i40e_debug(hw, I40E_DEBUG_INIT,
3671                                    "HW Capability: MSIX vector count = %d\n",
3672                                    p->num_msix_vectors_vf);
3673                         break;
3674                 case I40E_AQ_CAP_ID_VF_MSIX:
3675                         p->num_msix_vectors_vf = number;
3676                         i40e_debug(hw, I40E_DEBUG_INIT,
3677                                    "HW Capability: MSIX VF vector count = %d\n",
3678                                    p->num_msix_vectors_vf);
3679                         break;
3680                 case I40E_AQ_CAP_ID_FLEX10:
3681                         if (major_rev == 1) {
3682                                 if (number == 1) {
3683                                         p->flex10_enable = true;
3684                                         p->flex10_capable = true;
3685                                 }
3686                         } else {
3687                                 /* Capability revision >= 2 */
3688                                 if (number & 1)
3689                                         p->flex10_enable = true;
3690                                 if (number & 2)
3691                                         p->flex10_capable = true;
3692                         }
3693                         p->flex10_mode = logical_id;
3694                         p->flex10_status = phys_id;
3695                         i40e_debug(hw, I40E_DEBUG_INIT,
3696                                    "HW Capability: Flex10 mode = %d\n",
3697                                    p->flex10_mode);
3698                         i40e_debug(hw, I40E_DEBUG_INIT,
3699                                    "HW Capability: Flex10 status = %d\n",
3700                                    p->flex10_status);
3701                         break;
3702                 case I40E_AQ_CAP_ID_CEM:
3703                         if (number == 1)
3704                                 p->mgmt_cem = true;
3705                         i40e_debug(hw, I40E_DEBUG_INIT,
3706                                    "HW Capability: CEM = %d\n", p->mgmt_cem);
3707                         break;
3708                 case I40E_AQ_CAP_ID_IWARP:
3709                         if (number == 1)
3710                                 p->iwarp = true;
3711                         i40e_debug(hw, I40E_DEBUG_INIT,
3712                                    "HW Capability: iWARP = %d\n", p->iwarp);
3713                         break;
3714                 case I40E_AQ_CAP_ID_LED:
3715                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3716                                 p->led[phys_id] = true;
3717                         i40e_debug(hw, I40E_DEBUG_INIT,
3718                                    "HW Capability: LED - PIN %d\n", phys_id);
3719                         break;
3720                 case I40E_AQ_CAP_ID_SDP:
3721                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3722                                 p->sdp[phys_id] = true;
3723                         i40e_debug(hw, I40E_DEBUG_INIT,
3724                                    "HW Capability: SDP - PIN %d\n", phys_id);
3725                         break;
3726                 case I40E_AQ_CAP_ID_MDIO:
3727                         if (number == 1) {
3728                                 p->mdio_port_num = phys_id;
3729                                 p->mdio_port_mode = logical_id;
3730                         }
3731                         i40e_debug(hw, I40E_DEBUG_INIT,
3732                                    "HW Capability: MDIO port number = %d\n",
3733                                    p->mdio_port_num);
3734                         i40e_debug(hw, I40E_DEBUG_INIT,
3735                                    "HW Capability: MDIO port mode = %d\n",
3736                                    p->mdio_port_mode);
3737                         break;
3738                 case I40E_AQ_CAP_ID_1588:
3739                         if (number == 1)
3740                                 p->ieee_1588 = true;
3741                         i40e_debug(hw, I40E_DEBUG_INIT,
3742                                    "HW Capability: IEEE 1588 = %d\n",
3743                                    p->ieee_1588);
3744                         break;
3745                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3746                         p->fd = true;
3747                         p->fd_filters_guaranteed = number;
3748                         p->fd_filters_best_effort = logical_id;
3749                         i40e_debug(hw, I40E_DEBUG_INIT,
3750                                    "HW Capability: Flow Director = 1\n");
3751                         i40e_debug(hw, I40E_DEBUG_INIT,
3752                                    "HW Capability: Guaranteed FD filters = %d\n",
3753                                    p->fd_filters_guaranteed);
3754                         break;
3755                 case I40E_AQ_CAP_ID_WSR_PROT:
3756                         p->wr_csr_prot = (u64)number;
3757                         p->wr_csr_prot |= (u64)logical_id << 32;
3758                         i40e_debug(hw, I40E_DEBUG_INIT,
3759                                    "HW Capability: wr_csr_prot = 0x%llX\n\n",
3760                                    (p->wr_csr_prot & 0xffff));
3761                         break;
3762 #ifdef X722_SUPPORT
3763                 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3764                         hw->num_wol_proxy_filters = (u16)number;
3765                         hw->wol_proxy_vsi_seid = (u16)logical_id;
3766                         p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3767                         if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3768                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3769                         else
3770                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3771                         p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3772                         p->proxy_support = p->proxy_support;
3773                         i40e_debug(hw, I40E_DEBUG_INIT,
3774                                    "HW Capability: WOL proxy filters = %d\n",
3775                                    hw->num_wol_proxy_filters);
3776                         break;
3777 #endif
3778                 default:
3779                         break;
3780                 }
3781         }
3782
3783         if (p->fcoe)
3784                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3785
3786 #ifdef I40E_FCOE_ENA
3787         /* Software override ensuring FCoE is disabled if npar or mfp
3788          * mode because it is not supported in these modes.
3789          */
3790         if (p->npar_enable || p->flex10_enable)
3791                 p->fcoe = false;
3792 #else
3793         /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3794         p->fcoe = false;
3795 #endif
3796
3797         /* count the enabled ports (aka the "not disabled" ports) */
3798         hw->num_ports = 0;
3799         for (i = 0; i < 4; i++) {
3800                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3801                 u64 port_cfg = 0;
3802
3803                 /* use AQ read to get the physical register offset instead
3804                  * of the port relative offset
3805                  */
3806                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3807                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3808                         hw->num_ports++;
3809         }
3810
3811         valid_functions = p->valid_functions;
3812         num_functions = 0;
3813         while (valid_functions) {
3814                 if (valid_functions & 1)
3815                         num_functions++;
3816                 valid_functions >>= 1;
3817         }
3818
3819         /* partition id is 1-based, and functions are evenly spread
3820          * across the ports as partitions
3821          */
3822         hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3823         hw->num_partitions = num_functions / hw->num_ports;
3824
3825         /* additional HW specific goodies that might
3826          * someday be HW version specific
3827          */
3828         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3829 }
3830
3831 /**
3832  * i40e_aq_discover_capabilities
3833  * @hw: pointer to the hw struct
3834  * @buff: a virtual buffer to hold the capabilities
3835  * @buff_size: Size of the virtual buffer
3836  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3837  * @list_type_opc: capabilities type to discover - pass in the command opcode
3838  * @cmd_details: pointer to command details structure or NULL
3839  *
3840  * Get the device capabilities descriptions from the firmware
3841  **/
3842 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3843                                 void *buff, u16 buff_size, u16 *data_size,
3844                                 enum i40e_admin_queue_opc list_type_opc,
3845                                 struct i40e_asq_cmd_details *cmd_details)
3846 {
3847         struct i40e_aqc_list_capabilites *cmd;
3848         struct i40e_aq_desc desc;
3849         enum i40e_status_code status = I40E_SUCCESS;
3850
3851         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3852
3853         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3854                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3855                 status = I40E_ERR_PARAM;
3856                 goto exit;
3857         }
3858
3859         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3860
3861         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3862         if (buff_size > I40E_AQ_LARGE_BUF)
3863                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3864
3865         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3866         *data_size = LE16_TO_CPU(desc.datalen);
3867
3868         if (status)
3869                 goto exit;
3870
3871         i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3872                                          list_type_opc);
3873
3874 exit:
3875         return status;
3876 }
3877
3878 /**
3879  * i40e_aq_update_nvm
3880  * @hw: pointer to the hw struct
3881  * @module_pointer: module pointer location in words from the NVM beginning
3882  * @offset: byte offset from the module beginning
3883  * @length: length of the section to be written (in bytes from the offset)
3884  * @data: command buffer (size [bytes] = length)
3885  * @last_command: tells if this is the last command in a series
3886  * @cmd_details: pointer to command details structure or NULL
3887  *
3888  * Update the NVM using the admin queue commands
3889  **/
3890 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3891                                 u32 offset, u16 length, void *data,
3892                                 bool last_command,
3893                                 struct i40e_asq_cmd_details *cmd_details)
3894 {
3895         struct i40e_aq_desc desc;
3896         struct i40e_aqc_nvm_update *cmd =
3897                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3898         enum i40e_status_code status;
3899
3900         DEBUGFUNC("i40e_aq_update_nvm");
3901
3902         /* In offset the highest byte must be zeroed. */
3903         if (offset & 0xFF000000) {
3904                 status = I40E_ERR_PARAM;
3905                 goto i40e_aq_update_nvm_exit;
3906         }
3907
3908         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3909
3910         /* If this is the last command in a series, set the proper flag. */
3911         if (last_command)
3912                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3913         cmd->module_pointer = module_pointer;
3914         cmd->offset = CPU_TO_LE32(offset);
3915         cmd->length = CPU_TO_LE16(length);
3916
3917         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3918         if (length > I40E_AQ_LARGE_BUF)
3919                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3920
3921         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3922
3923 i40e_aq_update_nvm_exit:
3924         return status;
3925 }
3926
3927 /**
3928  * i40e_aq_get_lldp_mib
3929  * @hw: pointer to the hw struct
3930  * @bridge_type: type of bridge requested
3931  * @mib_type: Local, Remote or both Local and Remote MIBs
3932  * @buff: pointer to a user supplied buffer to store the MIB block
3933  * @buff_size: size of the buffer (in bytes)
3934  * @local_len : length of the returned Local LLDP MIB
3935  * @remote_len: length of the returned Remote LLDP MIB
3936  * @cmd_details: pointer to command details structure or NULL
3937  *
3938  * Requests the complete LLDP MIB (entire packet).
3939  **/
3940 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3941                                 u8 mib_type, void *buff, u16 buff_size,
3942                                 u16 *local_len, u16 *remote_len,
3943                                 struct i40e_asq_cmd_details *cmd_details)
3944 {
3945         struct i40e_aq_desc desc;
3946         struct i40e_aqc_lldp_get_mib *cmd =
3947                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3948         struct i40e_aqc_lldp_get_mib *resp =
3949                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3950         enum i40e_status_code status;
3951
3952         if (buff_size == 0 || !buff)
3953                 return I40E_ERR_PARAM;
3954
3955         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3956         /* Indirect Command */
3957         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3958
3959         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3960         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3961                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3962
3963         desc.datalen = CPU_TO_LE16(buff_size);
3964
3965         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3966         if (buff_size > I40E_AQ_LARGE_BUF)
3967                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3968
3969         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3970         if (!status) {
3971                 if (local_len != NULL)
3972                         *local_len = LE16_TO_CPU(resp->local_len);
3973                 if (remote_len != NULL)
3974                         *remote_len = LE16_TO_CPU(resp->remote_len);
3975         }
3976
3977         return status;
3978 }
3979
3980  /**
3981  * i40e_aq_set_lldp_mib - Set the LLDP MIB
3982  * @hw: pointer to the hw struct
3983  * @mib_type: Local, Remote or both Local and Remote MIBs
3984  * @buff: pointer to a user supplied buffer to store the MIB block
3985  * @buff_size: size of the buffer (in bytes)
3986  * @cmd_details: pointer to command details structure or NULL
3987  *
3988  * Set the LLDP MIB.
3989  **/
3990 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
3991                                 u8 mib_type, void *buff, u16 buff_size,
3992                                 struct i40e_asq_cmd_details *cmd_details)
3993 {
3994         struct i40e_aq_desc desc;
3995         struct i40e_aqc_lldp_set_local_mib *cmd =
3996                 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
3997         enum i40e_status_code status;
3998
3999         if (buff_size == 0 || !buff)
4000                 return I40E_ERR_PARAM;
4001
4002         i40e_fill_default_direct_cmd_desc(&desc,
4003                                 i40e_aqc_opc_lldp_set_local_mib);
4004         /* Indirect Command */
4005         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4006         if (buff_size > I40E_AQ_LARGE_BUF)
4007                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4008         desc.datalen = CPU_TO_LE16(buff_size);
4009
4010         cmd->type = mib_type;
4011         cmd->length = CPU_TO_LE16(buff_size);
4012         cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4013         cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4014
4015         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4016         return status;
4017 }
4018
4019 /**
4020  * i40e_aq_cfg_lldp_mib_change_event
4021  * @hw: pointer to the hw struct
4022  * @enable_update: Enable or Disable event posting
4023  * @cmd_details: pointer to command details structure or NULL
4024  *
4025  * Enable or Disable posting of an event on ARQ when LLDP MIB
4026  * associated with the interface changes
4027  **/
4028 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4029                                 bool enable_update,
4030                                 struct i40e_asq_cmd_details *cmd_details)
4031 {
4032         struct i40e_aq_desc desc;
4033         struct i40e_aqc_lldp_update_mib *cmd =
4034                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4035         enum i40e_status_code status;
4036
4037         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4038
4039         if (!enable_update)
4040                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4041
4042         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4043
4044         return status;
4045 }
4046
4047 /**
4048  * i40e_aq_add_lldp_tlv
4049  * @hw: pointer to the hw struct
4050  * @bridge_type: type of bridge
4051  * @buff: buffer with TLV to add
4052  * @buff_size: length of the buffer
4053  * @tlv_len: length of the TLV to be added
4054  * @mib_len: length of the LLDP MIB returned in response
4055  * @cmd_details: pointer to command details structure or NULL
4056  *
4057  * Add the specified TLV to LLDP Local MIB for the given bridge type,
4058  * it is responsibility of the caller to make sure that the TLV is not
4059  * already present in the LLDPDU.
4060  * In return firmware will write the complete LLDP MIB with the newly
4061  * added TLV in the response buffer.
4062  **/
4063 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4064                                 void *buff, u16 buff_size, u16 tlv_len,
4065                                 u16 *mib_len,
4066                                 struct i40e_asq_cmd_details *cmd_details)
4067 {
4068         struct i40e_aq_desc desc;
4069         struct i40e_aqc_lldp_add_tlv *cmd =
4070                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4071         enum i40e_status_code status;
4072
4073         if (buff_size == 0 || !buff || tlv_len == 0)
4074                 return I40E_ERR_PARAM;
4075
4076         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4077
4078         /* Indirect Command */
4079         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4080         if (buff_size > I40E_AQ_LARGE_BUF)
4081                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4082         desc.datalen = CPU_TO_LE16(buff_size);
4083
4084         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4085                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4086         cmd->len = CPU_TO_LE16(tlv_len);
4087
4088         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4089         if (!status) {
4090                 if (mib_len != NULL)
4091                         *mib_len = LE16_TO_CPU(desc.datalen);
4092         }
4093
4094         return status;
4095 }
4096
4097 /**
4098  * i40e_aq_update_lldp_tlv
4099  * @hw: pointer to the hw struct
4100  * @bridge_type: type of bridge
4101  * @buff: buffer with TLV to update
4102  * @buff_size: size of the buffer holding original and updated TLVs
4103  * @old_len: Length of the Original TLV
4104  * @new_len: Length of the Updated TLV
4105  * @offset: offset of the updated TLV in the buff
4106  * @mib_len: length of the returned LLDP MIB
4107  * @cmd_details: pointer to command details structure or NULL
4108  *
4109  * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4110  * Firmware will place the complete LLDP MIB in response buffer with the
4111  * updated TLV.
4112  **/
4113 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4114                                 u8 bridge_type, void *buff, u16 buff_size,
4115                                 u16 old_len, u16 new_len, u16 offset,
4116                                 u16 *mib_len,
4117                                 struct i40e_asq_cmd_details *cmd_details)
4118 {
4119         struct i40e_aq_desc desc;
4120         struct i40e_aqc_lldp_update_tlv *cmd =
4121                 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4122         enum i40e_status_code status;
4123
4124         if (buff_size == 0 || !buff || offset == 0 ||
4125             old_len == 0 || new_len == 0)
4126                 return I40E_ERR_PARAM;
4127
4128         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4129
4130         /* Indirect Command */
4131         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4132         if (buff_size > I40E_AQ_LARGE_BUF)
4133                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4134         desc.datalen = CPU_TO_LE16(buff_size);
4135
4136         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4137                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4138         cmd->old_len = CPU_TO_LE16(old_len);
4139         cmd->new_offset = CPU_TO_LE16(offset);
4140         cmd->new_len = CPU_TO_LE16(new_len);
4141
4142         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4143         if (!status) {
4144                 if (mib_len != NULL)
4145                         *mib_len = LE16_TO_CPU(desc.datalen);
4146         }
4147
4148         return status;
4149 }
4150
4151 /**
4152  * i40e_aq_delete_lldp_tlv
4153  * @hw: pointer to the hw struct
4154  * @bridge_type: type of bridge
4155  * @buff: pointer to a user supplied buffer that has the TLV
4156  * @buff_size: length of the buffer
4157  * @tlv_len: length of the TLV to be deleted
4158  * @mib_len: length of the returned LLDP MIB
4159  * @cmd_details: pointer to command details structure or NULL
4160  *
4161  * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4162  * The firmware places the entire LLDP MIB in the response buffer.
4163  **/
4164 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4165                                 u8 bridge_type, void *buff, u16 buff_size,
4166                                 u16 tlv_len, u16 *mib_len,
4167                                 struct i40e_asq_cmd_details *cmd_details)
4168 {
4169         struct i40e_aq_desc desc;
4170         struct i40e_aqc_lldp_add_tlv *cmd =
4171                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4172         enum i40e_status_code status;
4173
4174         if (buff_size == 0 || !buff)
4175                 return I40E_ERR_PARAM;
4176
4177         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4178
4179         /* Indirect Command */
4180         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4181         if (buff_size > I40E_AQ_LARGE_BUF)
4182                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4183         desc.datalen = CPU_TO_LE16(buff_size);
4184         cmd->len = CPU_TO_LE16(tlv_len);
4185         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4186                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4187
4188         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4189         if (!status) {
4190                 if (mib_len != NULL)
4191                         *mib_len = LE16_TO_CPU(desc.datalen);
4192         }
4193
4194         return status;
4195 }
4196
4197 /**
4198  * i40e_aq_stop_lldp
4199  * @hw: pointer to the hw struct
4200  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4201  * @cmd_details: pointer to command details structure or NULL
4202  *
4203  * Stop or Shutdown the embedded LLDP Agent
4204  **/
4205 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4206                                 struct i40e_asq_cmd_details *cmd_details)
4207 {
4208         struct i40e_aq_desc desc;
4209         struct i40e_aqc_lldp_stop *cmd =
4210                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4211         enum i40e_status_code status;
4212
4213         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4214
4215         if (shutdown_agent)
4216                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4217
4218         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4219
4220         return status;
4221 }
4222
4223 /**
4224  * i40e_aq_start_lldp
4225  * @hw: pointer to the hw struct
4226  * @cmd_details: pointer to command details structure or NULL
4227  *
4228  * Start the embedded LLDP Agent on all ports.
4229  **/
4230 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4231                                 struct i40e_asq_cmd_details *cmd_details)
4232 {
4233         struct i40e_aq_desc desc;
4234         struct i40e_aqc_lldp_start *cmd =
4235                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4236         enum i40e_status_code status;
4237
4238         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4239
4240         cmd->command = I40E_AQ_LLDP_AGENT_START;
4241
4242         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4243
4244         return status;
4245 }
4246
4247 /**
4248  * i40e_aq_get_cee_dcb_config
4249  * @hw: pointer to the hw struct
4250  * @buff: response buffer that stores CEE operational configuration
4251  * @buff_size: size of the buffer passed
4252  * @cmd_details: pointer to command details structure or NULL
4253  *
4254  * Get CEE DCBX mode operational configuration from firmware
4255  **/
4256 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4257                                 void *buff, u16 buff_size,
4258                                 struct i40e_asq_cmd_details *cmd_details)
4259 {
4260         struct i40e_aq_desc desc;
4261         enum i40e_status_code status;
4262
4263         if (buff_size == 0 || !buff)
4264                 return I40E_ERR_PARAM;
4265
4266         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4267
4268         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4269         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4270                                        cmd_details);
4271
4272         return status;
4273 }
4274
4275 /**
4276  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4277  * @hw: pointer to the hw struct
4278  * @start_agent: True if DCBx Agent needs to be Started
4279  *                              False if DCBx Agent needs to be Stopped
4280  * @cmd_details: pointer to command details structure or NULL
4281  *
4282  * Start/Stop the embedded dcbx Agent
4283  **/
4284 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4285                                 bool start_agent,
4286                                 struct i40e_asq_cmd_details *cmd_details)
4287 {
4288         struct i40e_aq_desc desc;
4289         struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4290                 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4291                                 &desc.params.raw;
4292         enum i40e_status_code status;
4293
4294         i40e_fill_default_direct_cmd_desc(&desc,
4295                                 i40e_aqc_opc_lldp_stop_start_spec_agent);
4296
4297         if (start_agent)
4298                 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4299
4300         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4301
4302         return status;
4303 }
4304
4305 /**
4306  * i40e_aq_add_udp_tunnel
4307  * @hw: pointer to the hw struct
4308  * @udp_port: the UDP port to add
4309  * @header_len: length of the tunneling header length in DWords
4310  * @protocol_index: protocol index type
4311  * @filter_index: pointer to filter index
4312  * @cmd_details: pointer to command details structure or NULL
4313  **/
4314 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4315                                 u16 udp_port, u8 protocol_index,
4316                                 u8 *filter_index,
4317                                 struct i40e_asq_cmd_details *cmd_details)
4318 {
4319         struct i40e_aq_desc desc;
4320         struct i40e_aqc_add_udp_tunnel *cmd =
4321                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4322         struct i40e_aqc_del_udp_tunnel_completion *resp =
4323                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4324         enum i40e_status_code status;
4325
4326         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4327
4328         cmd->udp_port = CPU_TO_LE16(udp_port);
4329         cmd->protocol_type = protocol_index;
4330
4331         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4332
4333         if (!status && filter_index)
4334                 *filter_index = resp->index;
4335
4336         return status;
4337 }
4338
4339 /**
4340  * i40e_aq_del_udp_tunnel
4341  * @hw: pointer to the hw struct
4342  * @index: filter index
4343  * @cmd_details: pointer to command details structure or NULL
4344  **/
4345 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4346                                 struct i40e_asq_cmd_details *cmd_details)
4347 {
4348         struct i40e_aq_desc desc;
4349         struct i40e_aqc_remove_udp_tunnel *cmd =
4350                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4351         enum i40e_status_code status;
4352
4353         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4354
4355         cmd->index = index;
4356
4357         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4358
4359         return status;
4360 }
4361
4362 /**
4363  * i40e_aq_get_switch_resource_alloc (0x0204)
4364  * @hw: pointer to the hw struct
4365  * @num_entries: pointer to u8 to store the number of resource entries returned
4366  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
4367  *        to store the resource information for all resource types.  Each
4368  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
4369  * @count: size, in bytes, of the buffer provided
4370  * @cmd_details: pointer to command details structure or NULL
4371  *
4372  * Query the resources allocated to a function.
4373  **/
4374 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4375                         u8 *num_entries,
4376                         struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4377                         u16 count,
4378                         struct i40e_asq_cmd_details *cmd_details)
4379 {
4380         struct i40e_aq_desc desc;
4381         struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4382                 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4383         enum i40e_status_code status;
4384         u16 length = count * sizeof(*buf);
4385
4386         i40e_fill_default_direct_cmd_desc(&desc,
4387                                         i40e_aqc_opc_get_switch_resource_alloc);
4388
4389         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4390         if (length > I40E_AQ_LARGE_BUF)
4391                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4392
4393         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4394
4395         if (!status && num_entries)
4396                 *num_entries = cmd_resp->num_entries;
4397
4398         return status;
4399 }
4400
4401 /**
4402  * i40e_aq_delete_element - Delete switch element
4403  * @hw: pointer to the hw struct
4404  * @seid: the SEID to delete from the switch
4405  * @cmd_details: pointer to command details structure or NULL
4406  *
4407  * This deletes a switch element from the switch.
4408  **/
4409 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4410                                 struct i40e_asq_cmd_details *cmd_details)
4411 {
4412         struct i40e_aq_desc desc;
4413         struct i40e_aqc_switch_seid *cmd =
4414                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4415         enum i40e_status_code status;
4416
4417         if (seid == 0)
4418                 return I40E_ERR_PARAM;
4419
4420         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4421
4422         cmd->seid = CPU_TO_LE16(seid);
4423
4424         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4425
4426         return status;
4427 }
4428
4429 /**
4430  * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4431  * @hw: pointer to the hw struct
4432  * @flags: component flags
4433  * @mac_seid: uplink seid (MAC SEID)
4434  * @vsi_seid: connected vsi seid
4435  * @ret_seid: seid of create pv component
4436  *
4437  * This instantiates an i40e port virtualizer with specified flags.
4438  * Depending on specified flags the port virtualizer can act as a
4439  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4440  */
4441 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4442                                        u16 mac_seid, u16 vsi_seid,
4443                                        u16 *ret_seid)
4444 {
4445         struct i40e_aq_desc desc;
4446         struct i40e_aqc_add_update_pv *cmd =
4447                 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4448         struct i40e_aqc_add_update_pv_completion *resp =
4449                 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4450         enum i40e_status_code status;
4451
4452         if (vsi_seid == 0)
4453                 return I40E_ERR_PARAM;
4454
4455         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4456         cmd->command_flags = CPU_TO_LE16(flags);
4457         cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4458         cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4459
4460         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4461         if (!status && ret_seid)
4462                 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4463
4464         return status;
4465 }
4466
4467 /**
4468  * i40e_aq_add_tag - Add an S/E-tag
4469  * @hw: pointer to the hw struct
4470  * @direct_to_queue: should s-tag direct flow to a specific queue
4471  * @vsi_seid: VSI SEID to use this tag
4472  * @tag: value of the tag
4473  * @queue_num: queue number, only valid is direct_to_queue is true
4474  * @tags_used: return value, number of tags in use by this PF
4475  * @tags_free: return value, number of unallocated tags
4476  * @cmd_details: pointer to command details structure or NULL
4477  *
4478  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4479  * the number of tags allocated by the PF, and the number of unallocated
4480  * tags available.
4481  **/
4482 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4483                                 u16 vsi_seid, u16 tag, u16 queue_num,
4484                                 u16 *tags_used, u16 *tags_free,
4485                                 struct i40e_asq_cmd_details *cmd_details)
4486 {
4487         struct i40e_aq_desc desc;
4488         struct i40e_aqc_add_tag *cmd =
4489                 (struct i40e_aqc_add_tag *)&desc.params.raw;
4490         struct i40e_aqc_add_remove_tag_completion *resp =
4491                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4492         enum i40e_status_code status;
4493
4494         if (vsi_seid == 0)
4495                 return I40E_ERR_PARAM;
4496
4497         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4498
4499         cmd->seid = CPU_TO_LE16(vsi_seid);
4500         cmd->tag = CPU_TO_LE16(tag);
4501         if (direct_to_queue) {
4502                 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4503                 cmd->queue_number = CPU_TO_LE16(queue_num);
4504         }
4505
4506         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4507
4508         if (!status) {
4509                 if (tags_used != NULL)
4510                         *tags_used = LE16_TO_CPU(resp->tags_used);
4511                 if (tags_free != NULL)
4512                         *tags_free = LE16_TO_CPU(resp->tags_free);
4513         }
4514
4515         return status;
4516 }
4517
4518 /**
4519  * i40e_aq_remove_tag - Remove an S- or E-tag
4520  * @hw: pointer to the hw struct
4521  * @vsi_seid: VSI SEID this tag is associated with
4522  * @tag: value of the S-tag to delete
4523  * @tags_used: return value, number of tags in use by this PF
4524  * @tags_free: return value, number of unallocated tags
4525  * @cmd_details: pointer to command details structure or NULL
4526  *
4527  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4528  * the number of tags allocated by the PF, and the number of unallocated
4529  * tags available.
4530  **/
4531 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4532                                 u16 tag, u16 *tags_used, u16 *tags_free,
4533                                 struct i40e_asq_cmd_details *cmd_details)
4534 {
4535         struct i40e_aq_desc desc;
4536         struct i40e_aqc_remove_tag *cmd =
4537                 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4538         struct i40e_aqc_add_remove_tag_completion *resp =
4539                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4540         enum i40e_status_code status;
4541
4542         if (vsi_seid == 0)
4543                 return I40E_ERR_PARAM;
4544
4545         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4546
4547         cmd->seid = CPU_TO_LE16(vsi_seid);
4548         cmd->tag = CPU_TO_LE16(tag);
4549
4550         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4551
4552         if (!status) {
4553                 if (tags_used != NULL)
4554                         *tags_used = LE16_TO_CPU(resp->tags_used);
4555                 if (tags_free != NULL)
4556                         *tags_free = LE16_TO_CPU(resp->tags_free);
4557         }
4558
4559         return status;
4560 }
4561
4562 /**
4563  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4564  * @hw: pointer to the hw struct
4565  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4566  * @etag: value of E-tag to add
4567  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4568  * @buf: address of indirect buffer
4569  * @tags_used: return value, number of E-tags in use by this port
4570  * @tags_free: return value, number of unallocated M-tags
4571  * @cmd_details: pointer to command details structure or NULL
4572  *
4573  * This associates a multicast E-tag to a port virtualizer.  It will return
4574  * the number of tags allocated by the PF, and the number of unallocated
4575  * tags available.
4576  *
4577  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4578  * num_tags_in_buf long.
4579  **/
4580 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4581                                 u16 etag, u8 num_tags_in_buf, void *buf,
4582                                 u16 *tags_used, u16 *tags_free,
4583                                 struct i40e_asq_cmd_details *cmd_details)
4584 {
4585         struct i40e_aq_desc desc;
4586         struct i40e_aqc_add_remove_mcast_etag *cmd =
4587                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4588         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4589            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4590         enum i40e_status_code status;
4591         u16 length = sizeof(u16) * num_tags_in_buf;
4592
4593         if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4594                 return I40E_ERR_PARAM;
4595
4596         i40e_fill_default_direct_cmd_desc(&desc,
4597                                           i40e_aqc_opc_add_multicast_etag);
4598
4599         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4600         cmd->etag = CPU_TO_LE16(etag);
4601         cmd->num_unicast_etags = num_tags_in_buf;
4602
4603         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4604         if (length > I40E_AQ_LARGE_BUF)
4605                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4606
4607         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4608
4609         if (!status) {
4610                 if (tags_used != NULL)
4611                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4612                 if (tags_free != NULL)
4613                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4614         }
4615
4616         return status;
4617 }
4618
4619 /**
4620  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4621  * @hw: pointer to the hw struct
4622  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4623  * @etag: value of the E-tag to remove
4624  * @tags_used: return value, number of tags in use by this port
4625  * @tags_free: return value, number of unallocated tags
4626  * @cmd_details: pointer to command details structure or NULL
4627  *
4628  * This deletes an E-tag from the port virtualizer.  It will return
4629  * the number of tags allocated by the port, and the number of unallocated
4630  * tags available.
4631  **/
4632 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4633                                 u16 etag, u16 *tags_used, u16 *tags_free,
4634                                 struct i40e_asq_cmd_details *cmd_details)
4635 {
4636         struct i40e_aq_desc desc;
4637         struct i40e_aqc_add_remove_mcast_etag *cmd =
4638                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4639         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4640            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4641         enum i40e_status_code status;
4642
4643
4644         if (pv_seid == 0)
4645                 return I40E_ERR_PARAM;
4646
4647         i40e_fill_default_direct_cmd_desc(&desc,
4648                                           i40e_aqc_opc_remove_multicast_etag);
4649
4650         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4651         cmd->etag = CPU_TO_LE16(etag);
4652
4653         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4654
4655         if (!status) {
4656                 if (tags_used != NULL)
4657                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4658                 if (tags_free != NULL)
4659                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4660         }
4661
4662         return status;
4663 }
4664
4665 /**
4666  * i40e_aq_update_tag - Update an S/E-tag
4667  * @hw: pointer to the hw struct
4668  * @vsi_seid: VSI SEID using this S-tag
4669  * @old_tag: old tag value
4670  * @new_tag: new tag value
4671  * @tags_used: return value, number of tags in use by this PF
4672  * @tags_free: return value, number of unallocated tags
4673  * @cmd_details: pointer to command details structure or NULL
4674  *
4675  * This updates the value of the tag currently attached to this VSI
4676  * in the switch complex.  It will return the number of tags allocated
4677  * by the PF, and the number of unallocated tags available.
4678  **/
4679 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4680                                 u16 old_tag, u16 new_tag, u16 *tags_used,
4681                                 u16 *tags_free,
4682                                 struct i40e_asq_cmd_details *cmd_details)
4683 {
4684         struct i40e_aq_desc desc;
4685         struct i40e_aqc_update_tag *cmd =
4686                 (struct i40e_aqc_update_tag *)&desc.params.raw;
4687         struct i40e_aqc_update_tag_completion *resp =
4688                 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4689         enum i40e_status_code status;
4690
4691         if (vsi_seid == 0)
4692                 return I40E_ERR_PARAM;
4693
4694         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4695
4696         cmd->seid = CPU_TO_LE16(vsi_seid);
4697         cmd->old_tag = CPU_TO_LE16(old_tag);
4698         cmd->new_tag = CPU_TO_LE16(new_tag);
4699
4700         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4701
4702         if (!status) {
4703                 if (tags_used != NULL)
4704                         *tags_used = LE16_TO_CPU(resp->tags_used);
4705                 if (tags_free != NULL)
4706                         *tags_free = LE16_TO_CPU(resp->tags_free);
4707         }
4708
4709         return status;
4710 }
4711
4712 /**
4713  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4714  * @hw: pointer to the hw struct
4715  * @tcmap: TC map for request/release any ignore PFC condition
4716  * @request: request or release ignore PFC condition
4717  * @tcmap_ret: return TCs for which PFC is currently ignored
4718  * @cmd_details: pointer to command details structure or NULL
4719  *
4720  * This sends out request/release to ignore PFC condition for a TC.
4721  * It will return the TCs for which PFC is currently ignored.
4722  **/
4723 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4724                                 bool request, u8 *tcmap_ret,
4725                                 struct i40e_asq_cmd_details *cmd_details)
4726 {
4727         struct i40e_aq_desc desc;
4728         struct i40e_aqc_pfc_ignore *cmd_resp =
4729                 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4730         enum i40e_status_code status;
4731
4732         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4733
4734         if (request)
4735                 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4736
4737         cmd_resp->tc_bitmap = tcmap;
4738
4739         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4740
4741         if (!status) {
4742                 if (tcmap_ret != NULL)
4743                         *tcmap_ret = cmd_resp->tc_bitmap;
4744         }
4745
4746         return status;
4747 }
4748
4749 /**
4750  * i40e_aq_dcb_updated - DCB Updated Command
4751  * @hw: pointer to the hw struct
4752  * @cmd_details: pointer to command details structure or NULL
4753  *
4754  * When LLDP is handled in PF this command is used by the PF
4755  * to notify EMP that a DCB setting is modified.
4756  * When LLDP is handled in EMP this command is used by the PF
4757  * to notify EMP whenever one of the following parameters get
4758  * modified:
4759  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4760  *   - PCIRTT in PRTDCB_GENC.PCIRTT
4761  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4762  * EMP will return when the shared RPB settings have been
4763  * recomputed and modified. The retval field in the descriptor
4764  * will be set to 0 when RPB is modified.
4765  **/
4766 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4767                                 struct i40e_asq_cmd_details *cmd_details)
4768 {
4769         struct i40e_aq_desc desc;
4770         enum i40e_status_code status;
4771
4772         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4773
4774         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4775
4776         return status;
4777 }
4778
4779 /**
4780  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4781  * @hw: pointer to the hw struct
4782  * @seid: defines the SEID of the switch for which the stats are requested
4783  * @vlan_id: the VLAN ID for which the statistics are requested
4784  * @stat_index: index of the statistics counters block assigned to this VLAN
4785  * @cmd_details: pointer to command details structure or NULL
4786  *
4787  * XL710 supports 128 smonVlanStats counters.This command is used to
4788  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4789  * switch.
4790  **/
4791 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4792                                 u16 vlan_id, u16 *stat_index,
4793                                 struct i40e_asq_cmd_details *cmd_details)
4794 {
4795         struct i40e_aq_desc desc;
4796         struct i40e_aqc_add_remove_statistics *cmd_resp =
4797                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4798         enum i40e_status_code status;
4799
4800         if ((seid == 0) || (stat_index == NULL))
4801                 return I40E_ERR_PARAM;
4802
4803         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4804
4805         cmd_resp->seid = CPU_TO_LE16(seid);
4806         cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4807
4808         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4809
4810         if (!status && stat_index)
4811                 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4812
4813         return status;
4814 }
4815
4816 /**
4817  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4818  * @hw: pointer to the hw struct
4819  * @seid: defines the SEID of the switch for which the stats are requested
4820  * @vlan_id: the VLAN ID for which the statistics are requested
4821  * @stat_index: index of the statistics counters block assigned to this VLAN
4822  * @cmd_details: pointer to command details structure or NULL
4823  *
4824  * XL710 supports 128 smonVlanStats counters.This command is used to
4825  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4826  * switch.
4827  **/
4828 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4829                                 u16 vlan_id, u16 stat_index,
4830                                 struct i40e_asq_cmd_details *cmd_details)
4831 {
4832         struct i40e_aq_desc desc;
4833         struct i40e_aqc_add_remove_statistics *cmd =
4834                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4835         enum i40e_status_code status;
4836
4837         if (seid == 0)
4838                 return I40E_ERR_PARAM;
4839
4840         i40e_fill_default_direct_cmd_desc(&desc,
4841                                           i40e_aqc_opc_remove_statistics);
4842
4843         cmd->seid = CPU_TO_LE16(seid);
4844         cmd->vlan  = CPU_TO_LE16(vlan_id);
4845         cmd->stat_index = CPU_TO_LE16(stat_index);
4846
4847         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4848
4849         return status;
4850 }
4851
4852 /**
4853  * i40e_aq_set_port_parameters - set physical port parameters.
4854  * @hw: pointer to the hw struct
4855  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4856  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4857  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4858  * @double_vlan: if set double VLAN is enabled
4859  * @cmd_details: pointer to command details structure or NULL
4860  **/
4861 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4862                                 u16 bad_frame_vsi, bool save_bad_pac,
4863                                 bool pad_short_pac, bool double_vlan,
4864                                 struct i40e_asq_cmd_details *cmd_details)
4865 {
4866         struct i40e_aqc_set_port_parameters *cmd;
4867         enum i40e_status_code status;
4868         struct i40e_aq_desc desc;
4869         u16 command_flags = 0;
4870
4871         cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4872
4873         i40e_fill_default_direct_cmd_desc(&desc,
4874                                           i40e_aqc_opc_set_port_parameters);
4875
4876         cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4877         if (save_bad_pac)
4878                 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4879         if (pad_short_pac)
4880                 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4881         if (double_vlan)
4882                 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4883         cmd->command_flags = CPU_TO_LE16(command_flags);
4884
4885         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4886
4887         return status;
4888 }
4889
4890 /**
4891  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
4892  * @hw: pointer to the hw struct
4893  * @seid: seid for the physical port/switching component/vsi
4894  * @buff: Indirect buffer to hold data parameters and response
4895  * @buff_size: Indirect buffer size
4896  * @opcode: Tx scheduler AQ command opcode
4897  * @cmd_details: pointer to command details structure or NULL
4898  *
4899  * Generic command handler for Tx scheduler AQ commands
4900  **/
4901 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
4902                                 void *buff, u16 buff_size,
4903                                  enum i40e_admin_queue_opc opcode,
4904                                 struct i40e_asq_cmd_details *cmd_details)
4905 {
4906         struct i40e_aq_desc desc;
4907         struct i40e_aqc_tx_sched_ind *cmd =
4908                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4909         enum i40e_status_code status;
4910         bool cmd_param_flag = false;
4911
4912         switch (opcode) {
4913         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
4914         case i40e_aqc_opc_configure_vsi_tc_bw:
4915         case i40e_aqc_opc_enable_switching_comp_ets:
4916         case i40e_aqc_opc_modify_switching_comp_ets:
4917         case i40e_aqc_opc_disable_switching_comp_ets:
4918         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
4919         case i40e_aqc_opc_configure_switching_comp_bw_config:
4920                 cmd_param_flag = true;
4921                 break;
4922         case i40e_aqc_opc_query_vsi_bw_config:
4923         case i40e_aqc_opc_query_vsi_ets_sla_config:
4924         case i40e_aqc_opc_query_switching_comp_ets_config:
4925         case i40e_aqc_opc_query_port_ets_config:
4926         case i40e_aqc_opc_query_switching_comp_bw_config:
4927                 cmd_param_flag = false;
4928                 break;
4929         default:
4930                 return I40E_ERR_PARAM;
4931         }
4932
4933         i40e_fill_default_direct_cmd_desc(&desc, opcode);
4934
4935         /* Indirect command */
4936         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4937         if (cmd_param_flag)
4938                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4939         if (buff_size > I40E_AQ_LARGE_BUF)
4940                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4941
4942         desc.datalen = CPU_TO_LE16(buff_size);
4943
4944         cmd->vsi_seid = CPU_TO_LE16(seid);
4945
4946         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4947
4948         return status;
4949 }
4950
4951 /**
4952  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
4953  * @hw: pointer to the hw struct
4954  * @seid: VSI seid
4955  * @credit: BW limit credits (0 = disabled)
4956  * @max_credit: Max BW limit credits
4957  * @cmd_details: pointer to command details structure or NULL
4958  **/
4959 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
4960                                 u16 seid, u16 credit, u8 max_credit,
4961                                 struct i40e_asq_cmd_details *cmd_details)
4962 {
4963         struct i40e_aq_desc desc;
4964         struct i40e_aqc_configure_vsi_bw_limit *cmd =
4965                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
4966         enum i40e_status_code status;
4967
4968         i40e_fill_default_direct_cmd_desc(&desc,
4969                                           i40e_aqc_opc_configure_vsi_bw_limit);
4970
4971         cmd->vsi_seid = CPU_TO_LE16(seid);
4972         cmd->credit = CPU_TO_LE16(credit);
4973         cmd->max_credit = max_credit;
4974
4975         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4976
4977         return status;
4978 }
4979
4980 /**
4981  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
4982  * @hw: pointer to the hw struct
4983  * @seid: switching component seid
4984  * @credit: BW limit credits (0 = disabled)
4985  * @max_bw: Max BW limit credits
4986  * @cmd_details: pointer to command details structure or NULL
4987  **/
4988 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
4989                                 u16 seid, u16 credit, u8 max_bw,
4990                                 struct i40e_asq_cmd_details *cmd_details)
4991 {
4992         struct i40e_aq_desc desc;
4993         struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
4994           (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
4995         enum i40e_status_code status;
4996
4997         i40e_fill_default_direct_cmd_desc(&desc,
4998                                 i40e_aqc_opc_configure_switching_comp_bw_limit);
4999
5000         cmd->seid = CPU_TO_LE16(seid);
5001         cmd->credit = CPU_TO_LE16(credit);
5002         cmd->max_bw = max_bw;
5003
5004         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5005
5006         return status;
5007 }
5008
5009 /**
5010  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5011  * @hw: pointer to the hw struct
5012  * @seid: VSI seid
5013  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5014  * @cmd_details: pointer to command details structure or NULL
5015  **/
5016 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5017                         u16 seid,
5018                         struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5019                         struct i40e_asq_cmd_details *cmd_details)
5020 {
5021         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5022                                     i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5023                                     cmd_details);
5024 }
5025
5026 /**
5027  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5028  * @hw: pointer to the hw struct
5029  * @seid: VSI seid
5030  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5031  * @cmd_details: pointer to command details structure or NULL
5032  **/
5033 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5034                         u16 seid,
5035                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5036                         struct i40e_asq_cmd_details *cmd_details)
5037 {
5038         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5039                                     i40e_aqc_opc_configure_vsi_tc_bw,
5040                                     cmd_details);
5041 }
5042
5043 /**
5044  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5045  * @hw: pointer to the hw struct
5046  * @seid: seid of the switching component connected to Physical Port
5047  * @ets_data: Buffer holding ETS parameters
5048  * @cmd_details: pointer to command details structure or NULL
5049  **/
5050 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5051                 u16 seid,
5052                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5053                 enum i40e_admin_queue_opc opcode,
5054                 struct i40e_asq_cmd_details *cmd_details)
5055 {
5056         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5057                                     sizeof(*ets_data), opcode, cmd_details);
5058 }
5059
5060 /**
5061  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5062  * @hw: pointer to the hw struct
5063  * @seid: seid of the switching component
5064  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5065  * @cmd_details: pointer to command details structure or NULL
5066  **/
5067 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5068         u16 seid,
5069         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5070         struct i40e_asq_cmd_details *cmd_details)
5071 {
5072         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5073                             i40e_aqc_opc_configure_switching_comp_bw_config,
5074                             cmd_details);
5075 }
5076
5077 /**
5078  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5079  * @hw: pointer to the hw struct
5080  * @seid: seid of the switching component
5081  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5082  * @cmd_details: pointer to command details structure or NULL
5083  **/
5084 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5085         struct i40e_hw *hw, u16 seid,
5086         struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5087         struct i40e_asq_cmd_details *cmd_details)
5088 {
5089         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5090                             i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5091                             cmd_details);
5092 }
5093
5094 /**
5095  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5096  * @hw: pointer to the hw struct
5097  * @seid: seid of the VSI
5098  * @bw_data: Buffer to hold VSI BW configuration
5099  * @cmd_details: pointer to command details structure or NULL
5100  **/
5101 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5102                         u16 seid,
5103                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5104                         struct i40e_asq_cmd_details *cmd_details)
5105 {
5106         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5107                                     i40e_aqc_opc_query_vsi_bw_config,
5108                                     cmd_details);
5109 }
5110
5111 /**
5112  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5113  * @hw: pointer to the hw struct
5114  * @seid: seid of the VSI
5115  * @bw_data: Buffer to hold VSI BW configuration per TC
5116  * @cmd_details: pointer to command details structure or NULL
5117  **/
5118 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5119                         u16 seid,
5120                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5121                         struct i40e_asq_cmd_details *cmd_details)
5122 {
5123         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5124                                     i40e_aqc_opc_query_vsi_ets_sla_config,
5125                                     cmd_details);
5126 }
5127
5128 /**
5129  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5130  * @hw: pointer to the hw struct
5131  * @seid: seid of the switching component
5132  * @bw_data: Buffer to hold switching component's per TC BW config
5133  * @cmd_details: pointer to command details structure or NULL
5134  **/
5135 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5136                 u16 seid,
5137                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5138                 struct i40e_asq_cmd_details *cmd_details)
5139 {
5140         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5141                                    i40e_aqc_opc_query_switching_comp_ets_config,
5142                                    cmd_details);
5143 }
5144
5145 /**
5146  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5147  * @hw: pointer to the hw struct
5148  * @seid: seid of the VSI or switching component connected to Physical Port
5149  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5150  * @cmd_details: pointer to command details structure or NULL
5151  **/
5152 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5153                         u16 seid,
5154                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
5155                         struct i40e_asq_cmd_details *cmd_details)
5156 {
5157         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5158                                     i40e_aqc_opc_query_port_ets_config,
5159                                     cmd_details);
5160 }
5161
5162 /**
5163  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5164  * @hw: pointer to the hw struct
5165  * @seid: seid of the switching component
5166  * @bw_data: Buffer to hold switching component's BW configuration
5167  * @cmd_details: pointer to command details structure or NULL
5168  **/
5169 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5170                 u16 seid,
5171                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5172                 struct i40e_asq_cmd_details *cmd_details)
5173 {
5174         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5175                                     i40e_aqc_opc_query_switching_comp_bw_config,
5176                                     cmd_details);
5177 }
5178
5179 /**
5180  * i40e_validate_filter_settings
5181  * @hw: pointer to the hardware structure
5182  * @settings: Filter control settings
5183  *
5184  * Check and validate the filter control settings passed.
5185  * The function checks for the valid filter/context sizes being
5186  * passed for FCoE and PE.
5187  *
5188  * Returns I40E_SUCCESS if the values passed are valid and within
5189  * range else returns an error.
5190  **/
5191 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5192                                 struct i40e_filter_control_settings *settings)
5193 {
5194         u32 fcoe_cntx_size, fcoe_filt_size;
5195         u32 pe_cntx_size, pe_filt_size;
5196         u32 fcoe_fmax;
5197
5198         u32 val;
5199
5200         /* Validate FCoE settings passed */
5201         switch (settings->fcoe_filt_num) {
5202         case I40E_HASH_FILTER_SIZE_1K:
5203         case I40E_HASH_FILTER_SIZE_2K:
5204         case I40E_HASH_FILTER_SIZE_4K:
5205         case I40E_HASH_FILTER_SIZE_8K:
5206         case I40E_HASH_FILTER_SIZE_16K:
5207         case I40E_HASH_FILTER_SIZE_32K:
5208                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5209                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5210                 break;
5211         default:
5212                 return I40E_ERR_PARAM;
5213         }
5214
5215         switch (settings->fcoe_cntx_num) {
5216         case I40E_DMA_CNTX_SIZE_512:
5217         case I40E_DMA_CNTX_SIZE_1K:
5218         case I40E_DMA_CNTX_SIZE_2K:
5219         case I40E_DMA_CNTX_SIZE_4K:
5220                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5221                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5222                 break;
5223         default:
5224                 return I40E_ERR_PARAM;
5225         }
5226
5227         /* Validate PE settings passed */
5228         switch (settings->pe_filt_num) {
5229         case I40E_HASH_FILTER_SIZE_1K:
5230         case I40E_HASH_FILTER_SIZE_2K:
5231         case I40E_HASH_FILTER_SIZE_4K:
5232         case I40E_HASH_FILTER_SIZE_8K:
5233         case I40E_HASH_FILTER_SIZE_16K:
5234         case I40E_HASH_FILTER_SIZE_32K:
5235         case I40E_HASH_FILTER_SIZE_64K:
5236         case I40E_HASH_FILTER_SIZE_128K:
5237         case I40E_HASH_FILTER_SIZE_256K:
5238         case I40E_HASH_FILTER_SIZE_512K:
5239         case I40E_HASH_FILTER_SIZE_1M:
5240                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5241                 pe_filt_size <<= (u32)settings->pe_filt_num;
5242                 break;
5243         default:
5244                 return I40E_ERR_PARAM;
5245         }
5246
5247         switch (settings->pe_cntx_num) {
5248         case I40E_DMA_CNTX_SIZE_512:
5249         case I40E_DMA_CNTX_SIZE_1K:
5250         case I40E_DMA_CNTX_SIZE_2K:
5251         case I40E_DMA_CNTX_SIZE_4K:
5252         case I40E_DMA_CNTX_SIZE_8K:
5253         case I40E_DMA_CNTX_SIZE_16K:
5254         case I40E_DMA_CNTX_SIZE_32K:
5255         case I40E_DMA_CNTX_SIZE_64K:
5256         case I40E_DMA_CNTX_SIZE_128K:
5257         case I40E_DMA_CNTX_SIZE_256K:
5258                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5259                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5260                 break;
5261         default:
5262                 return I40E_ERR_PARAM;
5263         }
5264
5265         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5266         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5267         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5268                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5269         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
5270                 return I40E_ERR_INVALID_SIZE;
5271
5272         return I40E_SUCCESS;
5273 }
5274
5275 /**
5276  * i40e_set_filter_control
5277  * @hw: pointer to the hardware structure
5278  * @settings: Filter control settings
5279  *
5280  * Set the Queue Filters for PE/FCoE and enable filters required
5281  * for a single PF. It is expected that these settings are programmed
5282  * at the driver initialization time.
5283  **/
5284 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5285                                 struct i40e_filter_control_settings *settings)
5286 {
5287         enum i40e_status_code ret = I40E_SUCCESS;
5288         u32 hash_lut_size = 0;
5289         u32 val;
5290
5291         if (!settings)
5292                 return I40E_ERR_PARAM;
5293
5294         /* Validate the input settings */
5295         ret = i40e_validate_filter_settings(hw, settings);
5296         if (ret)
5297                 return ret;
5298
5299         /* Read the PF Queue Filter control register */
5300         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5301
5302         /* Program required PE hash buckets for the PF */
5303         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5304         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5305                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5306         /* Program required PE contexts for the PF */
5307         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5308         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5309                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5310
5311         /* Program required FCoE hash buckets for the PF */
5312         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5313         val |= ((u32)settings->fcoe_filt_num <<
5314                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5315                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5316         /* Program required FCoE DDP contexts for the PF */
5317         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5318         val |= ((u32)settings->fcoe_cntx_num <<
5319                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5320                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5321
5322         /* Program Hash LUT size for the PF */
5323         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5324         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5325                 hash_lut_size = 1;
5326         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5327                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5328
5329         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5330         if (settings->enable_fdir)
5331                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5332         if (settings->enable_ethtype)
5333                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5334         if (settings->enable_macvlan)
5335                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5336
5337         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5338
5339         return I40E_SUCCESS;
5340 }
5341
5342 /**
5343  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5344  * @hw: pointer to the hw struct
5345  * @mac_addr: MAC address to use in the filter
5346  * @ethtype: Ethertype to use in the filter
5347  * @flags: Flags that needs to be applied to the filter
5348  * @vsi_seid: seid of the control VSI
5349  * @queue: VSI queue number to send the packet to
5350  * @is_add: Add control packet filter if True else remove
5351  * @stats: Structure to hold information on control filter counts
5352  * @cmd_details: pointer to command details structure or NULL
5353  *
5354  * This command will Add or Remove control packet filter for a control VSI.
5355  * In return it will update the total number of perfect filter count in
5356  * the stats member.
5357  **/
5358 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5359                                 u8 *mac_addr, u16 ethtype, u16 flags,
5360                                 u16 vsi_seid, u16 queue, bool is_add,
5361                                 struct i40e_control_filter_stats *stats,
5362                                 struct i40e_asq_cmd_details *cmd_details)
5363 {
5364         struct i40e_aq_desc desc;
5365         struct i40e_aqc_add_remove_control_packet_filter *cmd =
5366                 (struct i40e_aqc_add_remove_control_packet_filter *)
5367                 &desc.params.raw;
5368         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5369                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5370                 &desc.params.raw;
5371         enum i40e_status_code status;
5372
5373         if (vsi_seid == 0)
5374                 return I40E_ERR_PARAM;
5375
5376         if (is_add) {
5377                 i40e_fill_default_direct_cmd_desc(&desc,
5378                                 i40e_aqc_opc_add_control_packet_filter);
5379                 cmd->queue = CPU_TO_LE16(queue);
5380         } else {
5381                 i40e_fill_default_direct_cmd_desc(&desc,
5382                                 i40e_aqc_opc_remove_control_packet_filter);
5383         }
5384
5385         if (mac_addr)
5386                 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
5387                             I40E_NONDMA_TO_NONDMA);
5388
5389         cmd->etype = CPU_TO_LE16(ethtype);
5390         cmd->flags = CPU_TO_LE16(flags);
5391         cmd->seid = CPU_TO_LE16(vsi_seid);
5392
5393         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5394
5395         if (!status && stats) {
5396                 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5397                 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5398                 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5399                 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5400         }
5401
5402         return status;
5403 }
5404
5405 /**
5406  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5407  * @hw: pointer to the hw struct
5408  * @seid: VSI seid to add ethertype filter from
5409  **/
5410 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5411 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5412                                                     u16 seid)
5413 {
5414         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5415                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5416                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5417         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5418         enum i40e_status_code status;
5419
5420         status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5421                                                        seid, 0, true, NULL,
5422                                                        NULL);
5423         if (status)
5424                 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5425 }
5426
5427 /**
5428  * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5429  * @filters: list of cloud filters
5430  * @filter_count: length of list
5431  *
5432  * There's an issue in the device where the Geneve VNI layout needs
5433  * to be shifted 1 byte over from the VxLAN VNI
5434  **/
5435 STATIC void i40e_fix_up_geneve_vni(
5436         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5437         u8 filter_count)
5438 {
5439         struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters;
5440         int i;
5441
5442         for (i = 0; i < filter_count; i++) {
5443                 u16 tnl_type;
5444                 u32 ti;
5445
5446                 tnl_type = (le16_to_cpu(f[i].flags) &
5447                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5448                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5449                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5450                         ti = le32_to_cpu(f[i].tenant_id);
5451                         f[i].tenant_id = cpu_to_le32(ti << 8);
5452                 }
5453         }
5454 }
5455
5456 /**
5457  * i40e_aq_add_cloud_filters
5458  * @hw: pointer to the hardware structure
5459  * @seid: VSI seid to add cloud filters from
5460  * @filters: Buffer which contains the filters to be added
5461  * @filter_count: number of filters contained in the buffer
5462  *
5463  * Set the cloud filters for a given VSI.  The contents of the
5464  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5465  * in by the caller of the function.
5466  *
5467  **/
5468 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5469         u16 seid,
5470         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5471         u8 filter_count)
5472 {
5473         struct i40e_aq_desc desc;
5474         struct i40e_aqc_add_remove_cloud_filters *cmd =
5475         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5476         enum i40e_status_code status;
5477         u16 buff_len;
5478
5479         i40e_fill_default_direct_cmd_desc(&desc,
5480                                           i40e_aqc_opc_add_cloud_filters);
5481
5482         buff_len = filter_count * sizeof(*filters);
5483         desc.datalen = CPU_TO_LE16(buff_len);
5484         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5485         cmd->num_filters = filter_count;
5486         cmd->seid = CPU_TO_LE16(seid);
5487
5488         i40e_fix_up_geneve_vni(filters, filter_count);
5489
5490         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5491
5492         return status;
5493 }
5494
5495 /**
5496  * i40e_aq_remove_cloud_filters
5497  * @hw: pointer to the hardware structure
5498  * @seid: VSI seid to remove cloud filters from
5499  * @filters: Buffer which contains the filters to be removed
5500  * @filter_count: number of filters contained in the buffer
5501  *
5502  * Remove the cloud filters for a given VSI.  The contents of the
5503  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5504  * in by the caller of the function.
5505  *
5506  **/
5507 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5508                 u16 seid,
5509                 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5510                 u8 filter_count)
5511 {
5512         struct i40e_aq_desc desc;
5513         struct i40e_aqc_add_remove_cloud_filters *cmd =
5514         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5515         enum i40e_status_code status;
5516         u16 buff_len;
5517
5518         i40e_fill_default_direct_cmd_desc(&desc,
5519                                           i40e_aqc_opc_remove_cloud_filters);
5520
5521         buff_len = filter_count * sizeof(*filters);
5522         desc.datalen = CPU_TO_LE16(buff_len);
5523         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5524         cmd->num_filters = filter_count;
5525         cmd->seid = CPU_TO_LE16(seid);
5526
5527         i40e_fix_up_geneve_vni(filters, filter_count);
5528
5529         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5530
5531         return status;
5532 }
5533
5534 /**
5535  * i40e_aq_alternate_write
5536  * @hw: pointer to the hardware structure
5537  * @reg_addr0: address of first dword to be read
5538  * @reg_val0: value to be written under 'reg_addr0'
5539  * @reg_addr1: address of second dword to be read
5540  * @reg_val1: value to be written under 'reg_addr1'
5541  *
5542  * Write one or two dwords to alternate structure. Fields are indicated
5543  * by 'reg_addr0' and 'reg_addr1' register numbers.
5544  *
5545  **/
5546 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5547                                 u32 reg_addr0, u32 reg_val0,
5548                                 u32 reg_addr1, u32 reg_val1)
5549 {
5550         struct i40e_aq_desc desc;
5551         struct i40e_aqc_alternate_write *cmd_resp =
5552                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5553         enum i40e_status_code status;
5554
5555         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5556         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5557         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5558         cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5559         cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5560
5561         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5562
5563         return status;
5564 }
5565
5566 /**
5567  * i40e_aq_alternate_write_indirect
5568  * @hw: pointer to the hardware structure
5569  * @addr: address of a first register to be modified
5570  * @dw_count: number of alternate structure fields to write
5571  * @buffer: pointer to the command buffer
5572  *
5573  * Write 'dw_count' dwords from 'buffer' to alternate structure
5574  * starting at 'addr'.
5575  *
5576  **/
5577 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5578                                 u32 addr, u32 dw_count, void *buffer)
5579 {
5580         struct i40e_aq_desc desc;
5581         struct i40e_aqc_alternate_ind_write *cmd_resp =
5582                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5583         enum i40e_status_code status;
5584
5585         if (buffer == NULL)
5586                 return I40E_ERR_PARAM;
5587
5588         /* Indirect command */
5589         i40e_fill_default_direct_cmd_desc(&desc,
5590                                          i40e_aqc_opc_alternate_write_indirect);
5591
5592         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5593         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5594         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5595                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5596
5597         cmd_resp->address = CPU_TO_LE32(addr);
5598         cmd_resp->length = CPU_TO_LE32(dw_count);
5599
5600         status = i40e_asq_send_command(hw, &desc, buffer,
5601                                        I40E_LO_DWORD(4*dw_count), NULL);
5602
5603         return status;
5604 }
5605
5606 /**
5607  * i40e_aq_alternate_read
5608  * @hw: pointer to the hardware structure
5609  * @reg_addr0: address of first dword to be read
5610  * @reg_val0: pointer for data read from 'reg_addr0'
5611  * @reg_addr1: address of second dword to be read
5612  * @reg_val1: pointer for data read from 'reg_addr1'
5613  *
5614  * Read one or two dwords from alternate structure. Fields are indicated
5615  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5616  * is not passed then only register at 'reg_addr0' is read.
5617  *
5618  **/
5619 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5620                                 u32 reg_addr0, u32 *reg_val0,
5621                                 u32 reg_addr1, u32 *reg_val1)
5622 {
5623         struct i40e_aq_desc desc;
5624         struct i40e_aqc_alternate_write *cmd_resp =
5625                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5626         enum i40e_status_code status;
5627
5628         if (reg_val0 == NULL)
5629                 return I40E_ERR_PARAM;
5630
5631         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5632         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5633         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5634
5635         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5636
5637         if (status == I40E_SUCCESS) {
5638                 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5639
5640                 if (reg_val1 != NULL)
5641                         *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5642         }
5643
5644         return status;
5645 }
5646
5647 /**
5648  * i40e_aq_alternate_read_indirect
5649  * @hw: pointer to the hardware structure
5650  * @addr: address of the alternate structure field
5651  * @dw_count: number of alternate structure fields to read
5652  * @buffer: pointer to the command buffer
5653  *
5654  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5655  * place them in 'buffer'. The buffer should be allocated by caller.
5656  *
5657  **/
5658 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5659                                 u32 addr, u32 dw_count, void *buffer)
5660 {
5661         struct i40e_aq_desc desc;
5662         struct i40e_aqc_alternate_ind_write *cmd_resp =
5663                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5664         enum i40e_status_code status;
5665
5666         if (buffer == NULL)
5667                 return I40E_ERR_PARAM;
5668
5669         /* Indirect command */
5670         i40e_fill_default_direct_cmd_desc(&desc,
5671                 i40e_aqc_opc_alternate_read_indirect);
5672
5673         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5674         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5675         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5676                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5677
5678         cmd_resp->address = CPU_TO_LE32(addr);
5679         cmd_resp->length = CPU_TO_LE32(dw_count);
5680
5681         status = i40e_asq_send_command(hw, &desc, buffer,
5682                                        I40E_LO_DWORD(4*dw_count), NULL);
5683
5684         return status;
5685 }
5686
5687 /**
5688  *  i40e_aq_alternate_clear
5689  *  @hw: pointer to the HW structure.
5690  *
5691  *  Clear the alternate structures of the port from which the function
5692  *  is called.
5693  *
5694  **/
5695 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5696 {
5697         struct i40e_aq_desc desc;
5698         enum i40e_status_code status;
5699
5700         i40e_fill_default_direct_cmd_desc(&desc,
5701                                           i40e_aqc_opc_alternate_clear_port);
5702
5703         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5704
5705         return status;
5706 }
5707
5708 /**
5709  *  i40e_aq_alternate_write_done
5710  *  @hw: pointer to the HW structure.
5711  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
5712  *  @reset_needed: indicates the SW should trigger GLOBAL reset
5713  *
5714  *  Indicates to the FW that alternate structures have been changed.
5715  *
5716  **/
5717 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
5718                 u8 bios_mode, bool *reset_needed)
5719 {
5720         struct i40e_aq_desc desc;
5721         struct i40e_aqc_alternate_write_done *cmd =
5722                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5723         enum i40e_status_code status;
5724
5725         if (reset_needed == NULL)
5726                 return I40E_ERR_PARAM;
5727
5728         i40e_fill_default_direct_cmd_desc(&desc,
5729                                           i40e_aqc_opc_alternate_write_done);
5730
5731         cmd->cmd_flags = CPU_TO_LE16(bios_mode);
5732
5733         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5734         if (!status && reset_needed)
5735                 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
5736                                  I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
5737
5738         return status;
5739 }
5740
5741 /**
5742  *  i40e_aq_set_oem_mode
5743  *  @hw: pointer to the HW structure.
5744  *  @oem_mode: the OEM mode to be used
5745  *
5746  *  Sets the device to a specific operating mode. Currently the only supported
5747  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
5748  *
5749  **/
5750 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
5751                 u8 oem_mode)
5752 {
5753         struct i40e_aq_desc desc;
5754         struct i40e_aqc_alternate_write_done *cmd =
5755                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5756         enum i40e_status_code status;
5757
5758         i40e_fill_default_direct_cmd_desc(&desc,
5759                                           i40e_aqc_opc_alternate_set_mode);
5760
5761         cmd->cmd_flags = CPU_TO_LE16(oem_mode);
5762
5763         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5764
5765         return status;
5766 }
5767
5768 /**
5769  * i40e_aq_resume_port_tx
5770  * @hw: pointer to the hardware structure
5771  * @cmd_details: pointer to command details structure or NULL
5772  *
5773  * Resume port's Tx traffic
5774  **/
5775 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
5776                                 struct i40e_asq_cmd_details *cmd_details)
5777 {
5778         struct i40e_aq_desc desc;
5779         enum i40e_status_code status;
5780
5781         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
5782
5783         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5784
5785         return status;
5786 }
5787
5788 /**
5789  * i40e_set_pci_config_data - store PCI bus info
5790  * @hw: pointer to hardware structure
5791  * @link_status: the link status word from PCI config space
5792  *
5793  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
5794  **/
5795 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
5796 {
5797         hw->bus.type = i40e_bus_type_pci_express;
5798
5799         switch (link_status & I40E_PCI_LINK_WIDTH) {
5800         case I40E_PCI_LINK_WIDTH_1:
5801                 hw->bus.width = i40e_bus_width_pcie_x1;
5802                 break;
5803         case I40E_PCI_LINK_WIDTH_2:
5804                 hw->bus.width = i40e_bus_width_pcie_x2;
5805                 break;
5806         case I40E_PCI_LINK_WIDTH_4:
5807                 hw->bus.width = i40e_bus_width_pcie_x4;
5808                 break;
5809         case I40E_PCI_LINK_WIDTH_8:
5810                 hw->bus.width = i40e_bus_width_pcie_x8;
5811                 break;
5812         default:
5813                 hw->bus.width = i40e_bus_width_unknown;
5814                 break;
5815         }
5816
5817         switch (link_status & I40E_PCI_LINK_SPEED) {
5818         case I40E_PCI_LINK_SPEED_2500:
5819                 hw->bus.speed = i40e_bus_speed_2500;
5820                 break;
5821         case I40E_PCI_LINK_SPEED_5000:
5822                 hw->bus.speed = i40e_bus_speed_5000;
5823                 break;
5824         case I40E_PCI_LINK_SPEED_8000:
5825                 hw->bus.speed = i40e_bus_speed_8000;
5826                 break;
5827         default:
5828                 hw->bus.speed = i40e_bus_speed_unknown;
5829                 break;
5830         }
5831 }
5832
5833 /**
5834  * i40e_aq_debug_dump
5835  * @hw: pointer to the hardware structure
5836  * @cluster_id: specific cluster to dump
5837  * @table_id: table id within cluster
5838  * @start_index: index of line in the block to read
5839  * @buff_size: dump buffer size
5840  * @buff: dump buffer
5841  * @ret_buff_size: actual buffer size returned
5842  * @ret_next_table: next block to read
5843  * @ret_next_index: next index to read
5844  *
5845  * Dump internal FW/HW data for debug purposes.
5846  *
5847  **/
5848 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
5849                                 u8 table_id, u32 start_index, u16 buff_size,
5850                                 void *buff, u16 *ret_buff_size,
5851                                 u8 *ret_next_table, u32 *ret_next_index,
5852                                 struct i40e_asq_cmd_details *cmd_details)
5853 {
5854         struct i40e_aq_desc desc;
5855         struct i40e_aqc_debug_dump_internals *cmd =
5856                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5857         struct i40e_aqc_debug_dump_internals *resp =
5858                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5859         enum i40e_status_code status;
5860
5861         if (buff_size == 0 || !buff)
5862                 return I40E_ERR_PARAM;
5863
5864         i40e_fill_default_direct_cmd_desc(&desc,
5865                                           i40e_aqc_opc_debug_dump_internals);
5866         /* Indirect Command */
5867         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5868         if (buff_size > I40E_AQ_LARGE_BUF)
5869                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5870
5871         cmd->cluster_id = cluster_id;
5872         cmd->table_id = table_id;
5873         cmd->idx = CPU_TO_LE32(start_index);
5874
5875         desc.datalen = CPU_TO_LE16(buff_size);
5876
5877         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5878         if (!status) {
5879                 if (ret_buff_size != NULL)
5880                         *ret_buff_size = LE16_TO_CPU(desc.datalen);
5881                 if (ret_next_table != NULL)
5882                         *ret_next_table = resp->table_id;
5883                 if (ret_next_index != NULL)
5884                         *ret_next_index = LE32_TO_CPU(resp->idx);
5885         }
5886
5887         return status;
5888 }
5889
5890 /**
5891  * i40e_read_bw_from_alt_ram
5892  * @hw: pointer to the hardware structure
5893  * @max_bw: pointer for max_bw read
5894  * @min_bw: pointer for min_bw read
5895  * @min_valid: pointer for bool that is true if min_bw is a valid value
5896  * @max_valid: pointer for bool that is true if max_bw is a valid value
5897  *
5898  * Read bw from the alternate ram for the given pf
5899  **/
5900 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
5901                                         u32 *max_bw, u32 *min_bw,
5902                                         bool *min_valid, bool *max_valid)
5903 {
5904         enum i40e_status_code status;
5905         u32 max_bw_addr, min_bw_addr;
5906
5907         /* Calculate the address of the min/max bw registers */
5908         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5909                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
5910                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5911         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5912                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
5913                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5914
5915         /* Read the bandwidths from alt ram */
5916         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
5917                                         min_bw_addr, min_bw);
5918
5919         if (*min_bw & I40E_ALT_BW_VALID_MASK)
5920                 *min_valid = true;
5921         else
5922                 *min_valid = false;
5923
5924         if (*max_bw & I40E_ALT_BW_VALID_MASK)
5925                 *max_valid = true;
5926         else
5927                 *max_valid = false;
5928
5929         return status;
5930 }
5931
5932 /**
5933  * i40e_aq_configure_partition_bw
5934  * @hw: pointer to the hardware structure
5935  * @bw_data: Buffer holding valid pfs and bw limits
5936  * @cmd_details: pointer to command details
5937  *
5938  * Configure partitions guaranteed/max bw
5939  **/
5940 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
5941                         struct i40e_aqc_configure_partition_bw_data *bw_data,
5942                         struct i40e_asq_cmd_details *cmd_details)
5943 {
5944         enum i40e_status_code status;
5945         struct i40e_aq_desc desc;
5946         u16 bwd_size = sizeof(*bw_data);
5947
5948         i40e_fill_default_direct_cmd_desc(&desc,
5949                                 i40e_aqc_opc_configure_partition_bw);
5950
5951         /* Indirect command */
5952         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5953         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5954
5955         if (bwd_size > I40E_AQ_LARGE_BUF)
5956                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5957
5958         desc.datalen = CPU_TO_LE16(bwd_size);
5959
5960         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
5961
5962         return status;
5963 }
5964
5965 /**
5966  * i40e_read_phy_register
5967  * @hw: pointer to the HW structure
5968  * @page: registers page number
5969  * @reg: register address in the page
5970  * @phy_adr: PHY address on MDIO interface
5971  * @value: PHY register value
5972  *
5973  * Reads specified PHY register value
5974  **/
5975 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
5976                                              u8 page, u16 reg, u8 phy_addr,
5977                                              u16 *value)
5978 {
5979         enum i40e_status_code status = I40E_ERR_TIMEOUT;
5980         u32 command  = 0;
5981         u16 retry = 1000;
5982         u8 port_num = (u8)hw->func_caps.mdio_port_num;
5983
5984         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
5985                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
5986                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
5987                   (I40E_MDIO_OPCODE_ADDRESS) |
5988                   (I40E_MDIO_STCODE) |
5989                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
5990                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
5991         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
5992         do {
5993                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
5994                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
5995                         status = I40E_SUCCESS;
5996                         break;
5997                 }
5998                 i40e_usec_delay(10);
5999                 retry--;
6000         } while (retry);
6001
6002         if (status) {
6003                 i40e_debug(hw, I40E_DEBUG_PHY,
6004                            "PHY: Can't write command to external PHY.\n");
6005                 goto phy_read_end;
6006         }
6007
6008         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6009                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6010                   (I40E_MDIO_OPCODE_READ) |
6011                   (I40E_MDIO_STCODE) |
6012                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6013                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6014         status = I40E_ERR_TIMEOUT;
6015         retry = 1000;
6016         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6017         do {
6018                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6019                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6020                         status = I40E_SUCCESS;
6021                         break;
6022                 }
6023                 i40e_usec_delay(10);
6024                 retry--;
6025         } while (retry);
6026
6027         if (!status) {
6028                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6029                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6030                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6031         } else {
6032                 i40e_debug(hw, I40E_DEBUG_PHY,
6033                            "PHY: Can't read register value from external PHY.\n");
6034         }
6035
6036 phy_read_end:
6037         return status;
6038 }
6039
6040 /**
6041  * i40e_write_phy_register
6042  * @hw: pointer to the HW structure
6043  * @page: registers page number
6044  * @reg: register address in the page
6045  * @phy_adr: PHY address on MDIO interface
6046  * @value: PHY register value
6047  *
6048  * Writes value to specified PHY register
6049  **/
6050 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6051                                               u8 page, u16 reg, u8 phy_addr,
6052                                               u16 value)
6053 {
6054         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6055         u32 command  = 0;
6056         u16 retry = 1000;
6057         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6058
6059         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6060                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6061                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6062                   (I40E_MDIO_OPCODE_ADDRESS) |
6063                   (I40E_MDIO_STCODE) |
6064                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6065                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6066         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6067         do {
6068                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6069                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6070                         status = I40E_SUCCESS;
6071                         break;
6072                 }
6073                 i40e_usec_delay(10);
6074                 retry--;
6075         } while (retry);
6076         if (status) {
6077                 i40e_debug(hw, I40E_DEBUG_PHY,
6078                            "PHY: Can't write command to external PHY.\n");
6079                 goto phy_write_end;
6080         }
6081
6082         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6083         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6084
6085         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6086                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6087                   (I40E_MDIO_OPCODE_WRITE) |
6088                   (I40E_MDIO_STCODE) |
6089                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6090                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6091         status = I40E_ERR_TIMEOUT;
6092         retry = 1000;
6093         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6094         do {
6095                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6096                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6097                         status = I40E_SUCCESS;
6098                         break;
6099                 }
6100                 i40e_usec_delay(10);
6101                 retry--;
6102         } while (retry);
6103
6104 phy_write_end:
6105         return status;
6106 }
6107
6108 /**
6109  * i40e_get_phy_address
6110  * @hw: pointer to the HW structure
6111  * @dev_num: PHY port num that address we want
6112  * @phy_addr: Returned PHY address
6113  *
6114  * Gets PHY address for current port
6115  **/
6116 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6117 {
6118         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6119         u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6120
6121         return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6122 }
6123
6124 /**
6125  * i40e_blink_phy_led
6126  * @hw: pointer to the HW structure
6127  * @time: time how long led will blinks in secs
6128  * @interval: gap between LED on and off in msecs
6129  *
6130  * Blinks PHY link LED
6131  **/
6132 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6133                                               u32 time, u32 interval)
6134 {
6135         enum i40e_status_code status = I40E_SUCCESS;
6136         u32 i;
6137         u16 led_ctl = 0;
6138         u16 gpio_led_port;
6139         u16 led_reg;
6140         u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6141         u8 phy_addr = 0;
6142         u8 port_num;
6143
6144         i = rd32(hw, I40E_PFGEN_PORTNUM);
6145         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6146         phy_addr = i40e_get_phy_address(hw, port_num);
6147
6148         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6149              led_addr++) {
6150                 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6151                                                 led_addr, phy_addr, &led_reg);
6152                 if (status)
6153                         goto phy_blinking_end;
6154                 led_ctl = led_reg;
6155                 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6156                         led_reg = 0;
6157                         status = i40e_write_phy_register(hw,
6158                                                          I40E_PHY_COM_REG_PAGE,
6159                                                          led_addr, phy_addr,
6160                                                          led_reg);
6161                         if (status)
6162                                 goto phy_blinking_end;
6163                         break;
6164                 }
6165         }
6166
6167         if (time > 0 && interval > 0) {
6168                 for (i = 0; i < time * 1000; i += interval) {
6169                         status = i40e_read_phy_register(hw,
6170                                                         I40E_PHY_COM_REG_PAGE,
6171                                                         led_addr, phy_addr,
6172                                                         &led_reg);
6173                         if (status)
6174                                 goto restore_config;
6175                         if (led_reg & I40E_PHY_LED_MANUAL_ON)
6176                                 led_reg = 0;
6177                         else
6178                                 led_reg = I40E_PHY_LED_MANUAL_ON;
6179                         status = i40e_write_phy_register(hw,
6180                                                          I40E_PHY_COM_REG_PAGE,
6181                                                          led_addr, phy_addr,
6182                                                          led_reg);
6183                         if (status)
6184                                 goto restore_config;
6185                         i40e_msec_delay(interval);
6186                 }
6187         }
6188
6189 restore_config:
6190         status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6191                                          phy_addr, led_ctl);
6192
6193 phy_blinking_end:
6194         return status;
6195 }
6196
6197 /**
6198  * i40e_led_get_phy - return current on/off mode
6199  * @hw: pointer to the hw struct
6200  * @led_addr: address of led register to use
6201  * @val: original value of register to use
6202  *
6203  **/
6204 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6205                                        u16 *val)
6206 {
6207         enum i40e_status_code status = I40E_SUCCESS;
6208         u16 gpio_led_port;
6209         u8 phy_addr = 0;
6210         u16 reg_val;
6211         u16 temp_addr;
6212         u8 port_num;
6213         u32 i;
6214
6215         temp_addr = I40E_PHY_LED_PROV_REG_1;
6216         i = rd32(hw, I40E_PFGEN_PORTNUM);
6217         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6218         phy_addr = i40e_get_phy_address(hw, port_num);
6219
6220         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6221              temp_addr++) {
6222                 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6223                                                 temp_addr, phy_addr, &reg_val);
6224                 if (status)
6225                         return status;
6226                 *val = reg_val;
6227                 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6228                         *led_addr = temp_addr;
6229                         break;
6230                 }
6231         }
6232         return status;
6233 }
6234
6235 /**
6236  * i40e_led_set_phy
6237  * @hw: pointer to the HW structure
6238  * @on: true or false
6239  * @mode: original val plus bit for set or ignore
6240  * Set led's on or off when controlled by the PHY
6241  *
6242  **/
6243 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6244                                        u16 led_addr, u32 mode)
6245 {
6246         enum i40e_status_code status = I40E_SUCCESS;
6247         u16 led_ctl = 0;
6248         u16 led_reg = 0;
6249         u8 phy_addr = 0;
6250         u8 port_num;
6251         u32 i;
6252
6253         i = rd32(hw, I40E_PFGEN_PORTNUM);
6254         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6255         phy_addr = i40e_get_phy_address(hw, port_num);
6256
6257         status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6258                                         phy_addr, &led_reg);
6259         if (status)
6260                 return status;
6261         led_ctl = led_reg;
6262         if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6263                 led_reg = 0;
6264                 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6265                                                  led_addr, phy_addr, led_reg);
6266                 if (status)
6267                         return status;
6268         }
6269         status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6270                                         led_addr, phy_addr, &led_reg);
6271         if (status)
6272                 goto restore_config;
6273         if (on)
6274                 led_reg = I40E_PHY_LED_MANUAL_ON;
6275         else
6276                 led_reg = 0;
6277         status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6278                                          led_addr, phy_addr, led_reg);
6279         if (status)
6280                 goto restore_config;
6281         if (mode & I40E_PHY_LED_MODE_ORIG) {
6282                 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6283                 status = i40e_write_phy_register(hw,
6284                                                  I40E_PHY_COM_REG_PAGE,
6285                                                  led_addr, phy_addr, led_ctl);
6286         }
6287         return status;
6288 restore_config:
6289         status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6290                                          phy_addr, led_ctl);
6291         return status;
6292 }
6293 #endif /* PF_DRIVER */
6294
6295 /**
6296  * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6297  * @hw: pointer to the hw struct
6298  * @reg_addr: register address
6299  * @reg_val: ptr to register value
6300  * @cmd_details: pointer to command details structure or NULL
6301  *
6302  * Use the firmware to read the Rx control register,
6303  * especially useful if the Rx unit is under heavy pressure
6304  **/
6305 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6306                                 u32 reg_addr, u32 *reg_val,
6307                                 struct i40e_asq_cmd_details *cmd_details)
6308 {
6309         struct i40e_aq_desc desc;
6310         struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
6311                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6312         enum i40e_status_code status;
6313
6314         if (reg_val == NULL)
6315                 return I40E_ERR_PARAM;
6316
6317         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
6318
6319         cmd_resp->address = CPU_TO_LE32(reg_addr);
6320
6321         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6322
6323         if (status == I40E_SUCCESS)
6324                 *reg_val = LE32_TO_CPU(cmd_resp->value);
6325
6326         return status;
6327 }
6328
6329 /**
6330  * i40e_read_rx_ctl - read from an Rx control register
6331  * @hw: pointer to the hw struct
6332  * @reg_addr: register address
6333  **/
6334 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
6335 {
6336         enum i40e_status_code status = I40E_SUCCESS;
6337         bool use_register;
6338         int retry = 5;
6339         u32 val = 0;
6340
6341         use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6342         if (!use_register) {
6343 do_retry:
6344                 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
6345                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6346                         i40e_msec_delay(1);
6347                         retry--;
6348                         goto do_retry;
6349                 }
6350         }
6351
6352         /* if the AQ access failed, try the old-fashioned way */
6353         if (status || use_register)
6354                 val = rd32(hw, reg_addr);
6355
6356         return val;
6357 }
6358
6359 /**
6360  * i40e_aq_rx_ctl_write_register
6361  * @hw: pointer to the hw struct
6362  * @reg_addr: register address
6363  * @reg_val: register value
6364  * @cmd_details: pointer to command details structure or NULL
6365  *
6366  * Use the firmware to write to an Rx control register,
6367  * especially useful if the Rx unit is under heavy pressure
6368  **/
6369 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
6370                                 u32 reg_addr, u32 reg_val,
6371                                 struct i40e_asq_cmd_details *cmd_details)
6372 {
6373         struct i40e_aq_desc desc;
6374         struct i40e_aqc_rx_ctl_reg_read_write *cmd =
6375                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6376         enum i40e_status_code status;
6377
6378         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
6379
6380         cmd->address = CPU_TO_LE32(reg_addr);
6381         cmd->value = CPU_TO_LE32(reg_val);
6382
6383         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6384
6385         return status;
6386 }
6387
6388 /**
6389  * i40e_write_rx_ctl - write to an Rx control register
6390  * @hw: pointer to the hw struct
6391  * @reg_addr: register address
6392  * @reg_val: register value
6393  **/
6394 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
6395 {
6396         enum i40e_status_code status = I40E_SUCCESS;
6397         bool use_register;
6398         int retry = 5;
6399
6400         use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6401         if (!use_register) {
6402 do_retry:
6403                 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
6404                                                        reg_val, NULL);
6405                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6406                         i40e_msec_delay(1);
6407                         retry--;
6408                         goto do_retry;
6409                 }
6410         }
6411
6412         /* if the AQ access failed, try the old-fashioned way */
6413         if (status || use_register)
6414                 wr32(hw, reg_addr, reg_val);
6415 }
6416 #ifdef VF_DRIVER
6417
6418 /**
6419  * i40e_aq_send_msg_to_pf
6420  * @hw: pointer to the hardware structure
6421  * @v_opcode: opcodes for VF-PF communication
6422  * @v_retval: return error code
6423  * @msg: pointer to the msg buffer
6424  * @msglen: msg length
6425  * @cmd_details: pointer to command details
6426  *
6427  * Send message to PF driver using admin queue. By default, this message
6428  * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
6429  * completion before returning.
6430  **/
6431 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
6432                                 enum i40e_virtchnl_ops v_opcode,
6433                                 enum i40e_status_code v_retval,
6434                                 u8 *msg, u16 msglen,
6435                                 struct i40e_asq_cmd_details *cmd_details)
6436 {
6437         struct i40e_aq_desc desc;
6438         struct i40e_asq_cmd_details details;
6439         enum i40e_status_code status;
6440
6441         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
6442         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
6443         desc.cookie_high = CPU_TO_LE32(v_opcode);
6444         desc.cookie_low = CPU_TO_LE32(v_retval);
6445         if (msglen) {
6446                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
6447                                                 | I40E_AQ_FLAG_RD));
6448                 if (msglen > I40E_AQ_LARGE_BUF)
6449                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6450                 desc.datalen = CPU_TO_LE16(msglen);
6451         }
6452         if (!cmd_details) {
6453                 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
6454                 details.async = true;
6455                 cmd_details = &details;
6456         }
6457         status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
6458                                        msglen, cmd_details);
6459         return status;
6460 }
6461
6462 /**
6463  * i40e_vf_parse_hw_config
6464  * @hw: pointer to the hardware structure
6465  * @msg: pointer to the virtual channel VF resource structure
6466  *
6467  * Given a VF resource message from the PF, populate the hw struct
6468  * with appropriate information.
6469  **/
6470 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
6471                              struct i40e_virtchnl_vf_resource *msg)
6472 {
6473         struct i40e_virtchnl_vsi_resource *vsi_res;
6474         int i;
6475
6476         vsi_res = &msg->vsi_res[0];
6477
6478         hw->dev_caps.num_vsis = msg->num_vsis;
6479         hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
6480         hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
6481         hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
6482         hw->dev_caps.dcb = msg->vf_offload_flags &
6483                            I40E_VIRTCHNL_VF_OFFLOAD_L2;
6484         hw->dev_caps.fcoe = (msg->vf_offload_flags &
6485                              I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
6486         hw->dev_caps.iwarp = (msg->vf_offload_flags &
6487                               I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
6488         for (i = 0; i < msg->num_vsis; i++) {
6489                 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
6490                         i40e_memcpy(hw->mac.perm_addr,
6491                                     vsi_res->default_mac_addr,
6492                                     I40E_ETH_LENGTH_OF_ADDRESS,
6493                                     I40E_NONDMA_TO_NONDMA);
6494                         i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
6495                                     I40E_ETH_LENGTH_OF_ADDRESS,
6496                                     I40E_NONDMA_TO_NONDMA);
6497                 }
6498                 vsi_res++;
6499         }
6500 }
6501
6502 /**
6503  * i40e_vf_reset
6504  * @hw: pointer to the hardware structure
6505  *
6506  * Send a VF_RESET message to the PF. Does not wait for response from PF
6507  * as none will be forthcoming. Immediately after calling this function,
6508  * the admin queue should be shut down and (optionally) reinitialized.
6509  **/
6510 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
6511 {
6512         return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
6513                                       I40E_SUCCESS, NULL, 0, NULL);
6514 }
6515 #endif /* VF_DRIVER */
6516 #ifdef X722_SUPPORT
6517
6518 /**
6519  * i40e_aq_set_arp_proxy_config
6520  * @hw: pointer to the HW structure
6521  * @proxy_config - pointer to proxy config command table struct
6522  * @cmd_details: pointer to command details
6523  *
6524  * Set ARP offload parameters from pre-populated
6525  * i40e_aqc_arp_proxy_data struct
6526  **/
6527 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
6528                                 struct i40e_aqc_arp_proxy_data *proxy_config,
6529                                 struct i40e_asq_cmd_details *cmd_details)
6530 {
6531         struct i40e_aq_desc desc;
6532         enum i40e_status_code status;
6533
6534         if (!proxy_config)
6535                 return I40E_ERR_PARAM;
6536
6537         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
6538
6539         desc.params.external.addr_high =
6540                                   CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
6541         desc.params.external.addr_low =
6542                                   CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
6543
6544         status = i40e_asq_send_command(hw, &desc, proxy_config,
6545                                        sizeof(struct i40e_aqc_arp_proxy_data),
6546                                        cmd_details);
6547
6548         return status;
6549 }
6550
6551 /**
6552  * i40e_aq_opc_set_ns_proxy_table_entry
6553  * @hw: pointer to the HW structure
6554  * @ns_proxy_table_entry: pointer to NS table entry command struct
6555  * @cmd_details: pointer to command details
6556  *
6557  * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
6558  * from pre-populated i40e_aqc_ns_proxy_data struct
6559  **/
6560 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
6561                         struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
6562                         struct i40e_asq_cmd_details *cmd_details)
6563 {
6564         struct i40e_aq_desc desc;
6565         enum i40e_status_code status;
6566
6567         if (!ns_proxy_table_entry)
6568                 return I40E_ERR_PARAM;
6569
6570         i40e_fill_default_direct_cmd_desc(&desc,
6571                                 i40e_aqc_opc_set_ns_proxy_table_entry);
6572
6573         desc.params.external.addr_high =
6574                 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
6575         desc.params.external.addr_low =
6576                 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
6577
6578         status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
6579                                        sizeof(struct i40e_aqc_ns_proxy_data),
6580                                        cmd_details);
6581
6582         return status;
6583 }
6584
6585 /**
6586  * i40e_aq_set_clear_wol_filter
6587  * @hw: pointer to the hw struct
6588  * @filter_index: index of filter to modify (0-7)
6589  * @filter: buffer containing filter to be set
6590  * @set_filter: true to set filter, false to clear filter
6591  * @no_wol_tco: if true, pass through packets cannot cause wake-up
6592  *              if false, pass through packets may cause wake-up
6593  * @filter_valid: true if filter action is valid
6594  * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
6595  * @cmd_details: pointer to command details structure or NULL
6596  *
6597  * Set or clear WoL filter for port attached to the PF
6598  **/
6599 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
6600                                 u8 filter_index,
6601                                 struct i40e_aqc_set_wol_filter_data *filter,
6602                                 bool set_filter, bool no_wol_tco,
6603                                 bool filter_valid, bool no_wol_tco_valid,
6604                                 struct i40e_asq_cmd_details *cmd_details)
6605 {
6606         struct i40e_aq_desc desc;
6607         struct i40e_aqc_set_wol_filter *cmd =
6608                 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
6609         enum i40e_status_code status;
6610         u16 cmd_flags = 0;
6611         u16 valid_flags = 0;
6612         u16 buff_len = 0;
6613
6614         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
6615
6616         if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
6617                 return  I40E_ERR_PARAM;
6618         cmd->filter_index = CPU_TO_LE16(filter_index);
6619
6620         if (set_filter) {
6621                 if (!filter)
6622                         return  I40E_ERR_PARAM;
6623                 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
6624                 buff_len = sizeof(*filter);
6625         }
6626         if (no_wol_tco)
6627                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
6628         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
6629
6630         if (filter_valid)
6631                 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
6632         if (no_wol_tco_valid)
6633                 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
6634         cmd->valid_flags = CPU_TO_LE16(valid_flags);
6635
6636         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
6637         cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
6638
6639         status = i40e_asq_send_command(hw, &desc, filter,
6640                                        buff_len, cmd_details);
6641
6642         return status;
6643 }
6644
6645 /**
6646  * i40e_aq_get_wake_event_reason
6647  * @hw: pointer to the hw struct
6648  * @wake_reason: return value, index of matching filter
6649  * @cmd_details: pointer to command details structure or NULL
6650  *
6651  * Get information for the reason of a Wake Up event
6652  **/
6653 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
6654                                 u16 *wake_reason,
6655                                 struct i40e_asq_cmd_details *cmd_details)
6656 {
6657         struct i40e_aq_desc desc;
6658         struct i40e_aqc_get_wake_reason_completion *resp =
6659                 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
6660         enum i40e_status_code status;
6661
6662         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
6663
6664         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6665
6666         if (status == I40E_SUCCESS)
6667                 *wake_reason = LE16_TO_CPU(resp->wake_reason);
6668
6669         return status;
6670 }
6671
6672 #endif /* X722_SUPPORT */