drivers/net/i40e/base/i40e_common.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "i40e_type.h"
  35 #include "i40e_adminq.h"
  36 #include "i40e_prototype.h"
  37 #include "i40e_virtchnl.h"
  38
  39
  40 /**
  41  * i40e_set_mac_type - Sets MAC type
  42  * @hw: pointer to the HW structure
  43  *
  44  * This function sets the mac type of the adapter based on the
  45  * vendor ID and device ID stored in the hw structure.
  46  **/
  47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  49 #else
  50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  51 #endif
  52 {
  53         enum i40e_status_code status = I40E_SUCCESS;
  54
  55         DEBUGFUNC("i40e_set_mac_type\n");
  56
  57         if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
  58                 switch (hw->device_id) {
  59                 case I40E_DEV_ID_SFP_XL710:
  60                 case I40E_DEV_ID_QEMU:
  61                 case I40E_DEV_ID_KX_B:
  62                 case I40E_DEV_ID_KX_C:
  63                 case I40E_DEV_ID_QSFP_A:
  64                 case I40E_DEV_ID_QSFP_B:
  65                 case I40E_DEV_ID_QSFP_C:
  66                 case I40E_DEV_ID_10G_BASE_T:
  67                 case I40E_DEV_ID_10G_BASE_T4:
  68                 case I40E_DEV_ID_20G_KR2:
  69                 case I40E_DEV_ID_20G_KR2_A:
  70                         hw->mac.type = I40E_MAC_XL710;
  71                         break;
  72 #ifdef X722_SUPPORT
  73 #ifdef X722_A0_SUPPORT
  74                 case I40E_DEV_ID_X722_A0:
  75 #endif
  76                 case I40E_DEV_ID_KX_X722:
  77                 case I40E_DEV_ID_QSFP_X722:
  78                 case I40E_DEV_ID_SFP_X722:
  79                 case I40E_DEV_ID_1G_BASE_T_X722:
  80                 case I40E_DEV_ID_10G_BASE_T_X722:
  81                         hw->mac.type = I40E_MAC_X722;
  82                         break;
  83 #endif
  84 #ifdef X722_SUPPORT
  85 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  86                 case I40E_DEV_ID_X722_VF:
  87                 case I40E_DEV_ID_X722_VF_HV:
  88 #ifdef X722_A0_SUPPORT
  89                 case I40E_DEV_ID_X722_A0_VF:
  90 #endif
  91                         hw->mac.type = I40E_MAC_X722_VF;
  92                         break;
  93 #endif /* INTEGRATED_VF || VF_DRIVER */
  94 #endif /* X722_SUPPORT */
  95 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  96                 case I40E_DEV_ID_VF:
  97                 case I40E_DEV_ID_VF_HV:
  98                         hw->mac.type = I40E_MAC_VF;
  99                         break;
 100 #endif
 101                 default:
 102                         hw->mac.type = I40E_MAC_GENERIC;
 103                         break;
 104                 }
 105         } else {
 106                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
 107         }
 108
 109         DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
 110                   hw->mac.type, status);
 111         return status;
 112 }
 113
 114 #ifndef I40E_NDIS_SUPPORT
 115 /**
 116  * i40e_aq_str - convert AQ err code to a string
 117  * @hw: pointer to the HW structure
 118  * @aq_err: the AQ error code to convert
 119  **/
 120 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
 121 {
 122         switch (aq_err) {
 123         case I40E_AQ_RC_OK:
 124                 return "OK";
 125         case I40E_AQ_RC_EPERM:
 126                 return "I40E_AQ_RC_EPERM";
 127         case I40E_AQ_RC_ENOENT:
 128                 return "I40E_AQ_RC_ENOENT";
 129         case I40E_AQ_RC_ESRCH:
 130                 return "I40E_AQ_RC_ESRCH";
 131         case I40E_AQ_RC_EINTR:
 132                 return "I40E_AQ_RC_EINTR";
 133         case I40E_AQ_RC_EIO:
 134                 return "I40E_AQ_RC_EIO";
 135         case I40E_AQ_RC_ENXIO:
 136                 return "I40E_AQ_RC_ENXIO";
 137         case I40E_AQ_RC_E2BIG:
 138                 return "I40E_AQ_RC_E2BIG";
 139         case I40E_AQ_RC_EAGAIN:
 140                 return "I40E_AQ_RC_EAGAIN";
 141         case I40E_AQ_RC_ENOMEM:
 142                 return "I40E_AQ_RC_ENOMEM";
 143         case I40E_AQ_RC_EACCES:
 144                 return "I40E_AQ_RC_EACCES";
 145         case I40E_AQ_RC_EFAULT:
 146                 return "I40E_AQ_RC_EFAULT";
 147         case I40E_AQ_RC_EBUSY:
 148                 return "I40E_AQ_RC_EBUSY";
 149         case I40E_AQ_RC_EEXIST:
 150                 return "I40E_AQ_RC_EEXIST";
 151         case I40E_AQ_RC_EINVAL:
 152                 return "I40E_AQ_RC_EINVAL";
 153         case I40E_AQ_RC_ENOTTY:
 154                 return "I40E_AQ_RC_ENOTTY";
 155         case I40E_AQ_RC_ENOSPC:
 156                 return "I40E_AQ_RC_ENOSPC";
 157         case I40E_AQ_RC_ENOSYS:
 158                 return "I40E_AQ_RC_ENOSYS";
 159         case I40E_AQ_RC_ERANGE:
 160                 return "I40E_AQ_RC_ERANGE";
 161         case I40E_AQ_RC_EFLUSHED:
 162                 return "I40E_AQ_RC_EFLUSHED";
 163         case I40E_AQ_RC_BAD_ADDR:
 164                 return "I40E_AQ_RC_BAD_ADDR";
 165         case I40E_AQ_RC_EMODE:
 166                 return "I40E_AQ_RC_EMODE";
 167         case I40E_AQ_RC_EFBIG:
 168                 return "I40E_AQ_RC_EFBIG";
 169         }
 170
 171         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 172         return hw->err_str;
 173 }
 174
 175 /**
 176  * i40e_stat_str - convert status err code to a string
 177  * @hw: pointer to the HW structure
 178  * @stat_err: the status error code to convert
 179  **/
 180 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
 181 {
 182         switch (stat_err) {
 183         case I40E_SUCCESS:
 184                 return "OK";
 185         case I40E_ERR_NVM:
 186                 return "I40E_ERR_NVM";
 187         case I40E_ERR_NVM_CHECKSUM:
 188                 return "I40E_ERR_NVM_CHECKSUM";
 189         case I40E_ERR_PHY:
 190                 return "I40E_ERR_PHY";
 191         case I40E_ERR_CONFIG:
 192                 return "I40E_ERR_CONFIG";
 193         case I40E_ERR_PARAM:
 194                 return "I40E_ERR_PARAM";
 195         case I40E_ERR_MAC_TYPE:
 196                 return "I40E_ERR_MAC_TYPE";
 197         case I40E_ERR_UNKNOWN_PHY:
 198                 return "I40E_ERR_UNKNOWN_PHY";
 199         case I40E_ERR_LINK_SETUP:
 200                 return "I40E_ERR_LINK_SETUP";
 201         case I40E_ERR_ADAPTER_STOPPED:
 202                 return "I40E_ERR_ADAPTER_STOPPED";
 203         case I40E_ERR_INVALID_MAC_ADDR:
 204                 return "I40E_ERR_INVALID_MAC_ADDR";
 205         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 206                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 207         case I40E_ERR_MASTER_REQUESTS_PENDING:
 208                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 209         case I40E_ERR_INVALID_LINK_SETTINGS:
 210                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 211         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 212                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 213         case I40E_ERR_RESET_FAILED:
 214                 return "I40E_ERR_RESET_FAILED";
 215         case I40E_ERR_SWFW_SYNC:
 216                 return "I40E_ERR_SWFW_SYNC";
 217         case I40E_ERR_NO_AVAILABLE_VSI:
 218                 return "I40E_ERR_NO_AVAILABLE_VSI";
 219         case I40E_ERR_NO_MEMORY:
 220                 return "I40E_ERR_NO_MEMORY";
 221         case I40E_ERR_BAD_PTR:
 222                 return "I40E_ERR_BAD_PTR";
 223         case I40E_ERR_RING_FULL:
 224                 return "I40E_ERR_RING_FULL";
 225         case I40E_ERR_INVALID_PD_ID:
 226                 return "I40E_ERR_INVALID_PD_ID";
 227         case I40E_ERR_INVALID_QP_ID:
 228                 return "I40E_ERR_INVALID_QP_ID";
 229         case I40E_ERR_INVALID_CQ_ID:
 230                 return "I40E_ERR_INVALID_CQ_ID";
 231         case I40E_ERR_INVALID_CEQ_ID:
 232                 return "I40E_ERR_INVALID_CEQ_ID";
 233         case I40E_ERR_INVALID_AEQ_ID:
 234                 return "I40E_ERR_INVALID_AEQ_ID";
 235         case I40E_ERR_INVALID_SIZE:
 236                 return "I40E_ERR_INVALID_SIZE";
 237         case I40E_ERR_INVALID_ARP_INDEX:
 238                 return "I40E_ERR_INVALID_ARP_INDEX";
 239         case I40E_ERR_INVALID_FPM_FUNC_ID:
 240                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 241         case I40E_ERR_QP_INVALID_MSG_SIZE:
 242                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 243         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 244                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 245         case I40E_ERR_INVALID_FRAG_COUNT:
 246                 return "I40E_ERR_INVALID_FRAG_COUNT";
 247         case I40E_ERR_QUEUE_EMPTY:
 248                 return "I40E_ERR_QUEUE_EMPTY";
 249         case I40E_ERR_INVALID_ALIGNMENT:
 250                 return "I40E_ERR_INVALID_ALIGNMENT";
 251         case I40E_ERR_FLUSHED_QUEUE:
 252                 return "I40E_ERR_FLUSHED_QUEUE";
 253         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 254                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 255         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 256                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 257         case I40E_ERR_TIMEOUT:
 258                 return "I40E_ERR_TIMEOUT";
 259         case I40E_ERR_OPCODE_MISMATCH:
 260                 return "I40E_ERR_OPCODE_MISMATCH";
 261         case I40E_ERR_CQP_COMPL_ERROR:
 262                 return "I40E_ERR_CQP_COMPL_ERROR";
 263         case I40E_ERR_INVALID_VF_ID:
 264                 return "I40E_ERR_INVALID_VF_ID";
 265         case I40E_ERR_INVALID_HMCFN_ID:
 266                 return "I40E_ERR_INVALID_HMCFN_ID";
 267         case I40E_ERR_BACKING_PAGE_ERROR:
 268                 return "I40E_ERR_BACKING_PAGE_ERROR";
 269         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 270                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 271         case I40E_ERR_INVALID_PBLE_INDEX:
 272                 return "I40E_ERR_INVALID_PBLE_INDEX";
 273         case I40E_ERR_INVALID_SD_INDEX:
 274                 return "I40E_ERR_INVALID_SD_INDEX";
 275         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 276                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 277         case I40E_ERR_INVALID_SD_TYPE:
 278                 return "I40E_ERR_INVALID_SD_TYPE";
 279         case I40E_ERR_MEMCPY_FAILED:
 280                 return "I40E_ERR_MEMCPY_FAILED";
 281         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 282                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 283         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 284                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 285         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 286                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 287         case I40E_ERR_SRQ_ENABLED:
 288                 return "I40E_ERR_SRQ_ENABLED";
 289         case I40E_ERR_ADMIN_QUEUE_ERROR:
 290                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 291         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 292                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 293         case I40E_ERR_BUF_TOO_SHORT:
 294                 return "I40E_ERR_BUF_TOO_SHORT";
 295         case I40E_ERR_ADMIN_QUEUE_FULL:
 296                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 297         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 298                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 299         case I40E_ERR_BAD_IWARP_CQE:
 300                 return "I40E_ERR_BAD_IWARP_CQE";
 301         case I40E_ERR_NVM_BLANK_MODE:
 302                 return "I40E_ERR_NVM_BLANK_MODE";
 303         case I40E_ERR_NOT_IMPLEMENTED:
 304                 return "I40E_ERR_NOT_IMPLEMENTED";
 305         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 306                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 307         case I40E_ERR_DIAG_TEST_FAILED:
 308                 return "I40E_ERR_DIAG_TEST_FAILED";
 309         case I40E_ERR_NOT_READY:
 310                 return "I40E_ERR_NOT_READY";
 311         case I40E_NOT_SUPPORTED:
 312                 return "I40E_NOT_SUPPORTED";
 313         case I40E_ERR_FIRMWARE_API_VERSION:
 314                 return "I40E_ERR_FIRMWARE_API_VERSION";
 315         }
 316
 317         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 318         return hw->err_str;
 319 }
 320
 321 #endif /* I40E_NDIS_SUPPORT */
 322 /**
 323  * i40e_debug_aq
 324  * @hw: debug mask related to admin queue
 325  * @mask: debug mask
 326  * @desc: pointer to admin queue descriptor
 327  * @buffer: pointer to command buffer
 328  * @buf_len: max length of buffer
 329  *
 330  * Dumps debug log about adminq command with descriptor contents.
 331  **/
 332 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 333                    void *buffer, u16 buf_len)
 334 {
 335         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 336         u16 len = LE16_TO_CPU(aq_desc->datalen);
 337         u8 *buf = (u8 *)buffer;
 338         u16 i = 0;
 339
 340         if ((!(mask & hw->debug_mask)) || (desc == NULL))
 341                 return;
 342
 343         i40e_debug(hw, mask,
 344                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 345                    LE16_TO_CPU(aq_desc->opcode),
 346                    LE16_TO_CPU(aq_desc->flags),
 347                    LE16_TO_CPU(aq_desc->datalen),
 348                    LE16_TO_CPU(aq_desc->retval));
 349         i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
 350                    LE32_TO_CPU(aq_desc->cookie_high),
 351                    LE32_TO_CPU(aq_desc->cookie_low));
 352         i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
 353                    LE32_TO_CPU(aq_desc->params.internal.param0),
 354                    LE32_TO_CPU(aq_desc->params.internal.param1));
 355         i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
 356                    LE32_TO_CPU(aq_desc->params.external.addr_high),
 357                    LE32_TO_CPU(aq_desc->params.external.addr_low));
 358
 359         if ((buffer != NULL) && (aq_desc->datalen != 0)) {
 360                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 361                 if (buf_len < len)
 362                         len = buf_len;
 363                 /* write the full 16-byte chunks */
 364                 for (i = 0; i < (len - 16); i += 16)
 365                         i40e_debug(hw, mask,
 366                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 367                                    i, buf[i], buf[i+1], buf[i+2], buf[i+3],
 368                                    buf[i+4], buf[i+5], buf[i+6], buf[i+7],
 369                                    buf[i+8], buf[i+9], buf[i+10], buf[i+11],
 370                                    buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
 371                 /* the most we could have left is 16 bytes, pad with zeros */
 372                 if (i < len) {
 373                         char d_buf[16];
 374                         int j;
 375
 376                         memset(d_buf, 0, sizeof(d_buf));
 377                         for (j = 0; i < len; j++, i++)
 378                                 d_buf[j] = buf[i];
 379                         i40e_debug(hw, mask,
 380                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 381                                    i, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
 382                                    d_buf[4], d_buf[5], d_buf[6], d_buf[7],
 383                                    d_buf[8], d_buf[9], d_buf[10], d_buf[11],
 384                                    d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
 385                 }
 386         }
 387 }
 388
 389 /**
 390  * i40e_check_asq_alive
 391  * @hw: pointer to the hw struct
 392  *
 393  * Returns true if Queue is enabled else false.
 394  **/
 395 bool i40e_check_asq_alive(struct i40e_hw *hw)
 396 {
 397         if (hw->aq.asq.len)
 398 #ifdef PF_DRIVER
 399 #ifdef INTEGRATED_VF
 400                 if (!i40e_is_vf(hw))
 401                         return !!(rd32(hw, hw->aq.asq.len) &
 402                                 I40E_PF_ATQLEN_ATQENABLE_MASK);
 403 #else
 404                 return !!(rd32(hw, hw->aq.asq.len) &
 405                         I40E_PF_ATQLEN_ATQENABLE_MASK);
 406 #endif /* INTEGRATED_VF */
 407 #endif /* PF_DRIVER */
 408 #ifdef VF_DRIVER
 409 #ifdef INTEGRATED_VF
 410                 if (i40e_is_vf(hw))
 411                         return !!(rd32(hw, hw->aq.asq.len) &
 412                                 I40E_VF_ATQLEN1_ATQENABLE_MASK);
 413 #else
 414                 return !!(rd32(hw, hw->aq.asq.len) &
 415                         I40E_VF_ATQLEN1_ATQENABLE_MASK);
 416 #endif /* INTEGRATED_VF */
 417 #endif /* VF_DRIVER */
 418         return false;
 419 }
 420
 421 /**
 422  * i40e_aq_queue_shutdown
 423  * @hw: pointer to the hw struct
 424  * @unloading: is the driver unloading itself
 425  *
 426  * Tell the Firmware that we're shutting down the AdminQ and whether
 427  * or not the driver is unloading as well.
 428  **/
 429 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
 430                                              bool unloading)
 431 {
 432         struct i40e_aq_desc desc;
 433         struct i40e_aqc_queue_shutdown *cmd =
 434                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 435         enum i40e_status_code status;
 436
 437         i40e_fill_default_direct_cmd_desc(&desc,
 438                                           i40e_aqc_opc_queue_shutdown);
 439
 440         if (unloading)
 441                 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
 442         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 443
 444         return status;
 445 }
 446 #ifdef X722_SUPPORT
 447
 448 /**
 449  * i40e_aq_get_set_rss_lut
 450  * @hw: pointer to the hardware structure
 451  * @vsi_id: vsi fw index
 452  * @pf_lut: for PF table set true, for VSI table set false
 453  * @lut: pointer to the lut buffer provided by the caller
 454  * @lut_size: size of the lut buffer
 455  * @set: set true to set the table, false to get the table
 456  *
 457  * Internal function to get or set RSS look up table
 458  **/
 459 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 460                                                      u16 vsi_id, bool pf_lut,
 461                                                      u8 *lut, u16 lut_size,
 462                                                      bool set)
 463 {
 464         enum i40e_status_code status;
 465         struct i40e_aq_desc desc;
 466         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 467                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 468
 469         if (set)
 470                 i40e_fill_default_direct_cmd_desc(&desc,
 471                                                   i40e_aqc_opc_set_rss_lut);
 472         else
 473                 i40e_fill_default_direct_cmd_desc(&desc,
 474                                                   i40e_aqc_opc_get_rss_lut);
 475
 476         /* Indirect command */
 477         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 478         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 479
 480         cmd_resp->vsi_id =
 481                         CPU_TO_LE16((u16)((vsi_id <<
 482                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 483                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 484         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 485
 486         if (pf_lut)
 487                 cmd_resp->flags |= CPU_TO_LE16((u16)
 488                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 489                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 490                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 491         else
 492                 cmd_resp->flags |= CPU_TO_LE16((u16)
 493                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 494                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 495                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 496
 497         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 498
 499         return status;
 500 }
 501
 502 /**
 503  * i40e_aq_get_rss_lut
 504  * @hw: pointer to the hardware structure
 505  * @vsi_id: vsi fw index
 506  * @pf_lut: for PF table set true, for VSI table set false
 507  * @lut: pointer to the lut buffer provided by the caller
 508  * @lut_size: size of the lut buffer
 509  *
 510  * get the RSS lookup table, PF or VSI type
 511  **/
 512 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 513                                           bool pf_lut, u8 *lut, u16 lut_size)
 514 {
 515         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 516                                        false);
 517 }
 518
 519 /**
 520  * i40e_aq_set_rss_lut
 521  * @hw: pointer to the hardware structure
 522  * @vsi_id: vsi fw index
 523  * @pf_lut: for PF table set true, for VSI table set false
 524  * @lut: pointer to the lut buffer provided by the caller
 525  * @lut_size: size of the lut buffer
 526  *
 527  * set the RSS lookup table, PF or VSI type
 528  **/
 529 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 530                                           bool pf_lut, u8 *lut, u16 lut_size)
 531 {
 532         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
 533 }
 534
 535 /**
 536  * i40e_aq_get_set_rss_key
 537  * @hw: pointer to the hw struct
 538  * @vsi_id: vsi fw index
 539  * @key: pointer to key info struct
 540  * @set: set true to set the key, false to get the key
 541  *
 542  * get the RSS key per VSI
 543  **/
 544 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 545                                       u16 vsi_id,
 546                                       struct i40e_aqc_get_set_rss_key_data *key,
 547                                       bool set)
 548 {
 549         enum i40e_status_code status;
 550         struct i40e_aq_desc desc;
 551         struct i40e_aqc_get_set_rss_key *cmd_resp =
 552                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 553         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 554
 555         if (set)
 556                 i40e_fill_default_direct_cmd_desc(&desc,
 557                                                   i40e_aqc_opc_set_rss_key);
 558         else
 559                 i40e_fill_default_direct_cmd_desc(&desc,
 560                                                   i40e_aqc_opc_get_rss_key);
 561
 562         /* Indirect command */
 563         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 564         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 565
 566         cmd_resp->vsi_id =
 567                         CPU_TO_LE16((u16)((vsi_id <<
 568                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 569                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 570         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 571
 572         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 573
 574         return status;
 575 }
 576
 577 /**
 578  * i40e_aq_get_rss_key
 579  * @hw: pointer to the hw struct
 580  * @vsi_id: vsi fw index
 581  * @key: pointer to key info struct
 582  *
 583  **/
 584 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
 585                                       u16 vsi_id,
 586                                       struct i40e_aqc_get_set_rss_key_data *key)
 587 {
 588         return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
 589 }
 590
 591 /**
 592  * i40e_aq_set_rss_key
 593  * @hw: pointer to the hw struct
 594  * @vsi_id: vsi fw index
 595  * @key: pointer to key info struct
 596  *
 597  * set the RSS key per VSI
 598  **/
 599 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
 600                                       u16 vsi_id,
 601                                       struct i40e_aqc_get_set_rss_key_data *key)
 602 {
 603         return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
 604 }
 605 #endif /* X722_SUPPORT */
 606
 607 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 608  * hardware to a bit-field that can be used by SW to more easily determine the
 609  * packet type.
 610  *
 611  * Macros are used to shorten the table lines and make this table human
 612  * readable.
 613  *
 614  * We store the PTYPE in the top byte of the bit field - this is just so that
 615  * we can check that the table doesn't have a row missing, as the index into
 616  * the table should be the PTYPE.
 617  *
 618  * Typical work flow:
 619  *
 620  * IF NOT i40e_ptype_lookup[ptype].known
 621  * THEN
 622  *      Packet is unknown
 623  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 624  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 625  * ELSE
 626  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 627  * ENDIF
 628  */
 629
 630 /* macro to make the table lines short */
 631 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 632         {       PTYPE, \
 633                 1, \
 634                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 635                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 636                 I40E_RX_PTYPE_##OUTER_FRAG, \
 637                 I40E_RX_PTYPE_TUNNEL_##T, \
 638                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 639                 I40E_RX_PTYPE_##TEF, \
 640                 I40E_RX_PTYPE_INNER_PROT_##I, \
 641                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 642
 643 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 644                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 645
 646 /* shorter macros makes the table fit but are terse */
 647 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 648 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 649 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 650
 651 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 652 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 653         /* L2 Packet types */
 654         I40E_PTT_UNUSED_ENTRY(0),
 655         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 656         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 657         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 658         I40E_PTT_UNUSED_ENTRY(4),
 659         I40E_PTT_UNUSED_ENTRY(5),
 660         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 661         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 662         I40E_PTT_UNUSED_ENTRY(8),
 663         I40E_PTT_UNUSED_ENTRY(9),
 664         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 665         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 666         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 667         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 668         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 669         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 670         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 671         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 672         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 673         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 674         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 675         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 676
 677         /* Non Tunneled IPv4 */
 678         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 679         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 680         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 681         I40E_PTT_UNUSED_ENTRY(25),
 682         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 683         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 684         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 685
 686         /* IPv4 --> IPv4 */
 687         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 688         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 689         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 690         I40E_PTT_UNUSED_ENTRY(32),
 691         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 692         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 693         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 694
 695         /* IPv4 --> IPv6 */
 696         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 697         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 698         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 699         I40E_PTT_UNUSED_ENTRY(39),
 700         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 701         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 702         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 703
 704         /* IPv4 --> GRE/NAT */
 705         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 706
 707         /* IPv4 --> GRE/NAT --> IPv4 */
 708         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 709         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 710         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 711         I40E_PTT_UNUSED_ENTRY(47),
 712         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 713         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 714         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 715
 716         /* IPv4 --> GRE/NAT --> IPv6 */
 717         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 718         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 719         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 720         I40E_PTT_UNUSED_ENTRY(54),
 721         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 722         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 723         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 724
 725         /* IPv4 --> GRE/NAT --> MAC */
 726         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 727
 728         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 729         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 730         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 731         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 732         I40E_PTT_UNUSED_ENTRY(62),
 733         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 734         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 735         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 736
 737         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 738         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 739         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 740         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 741         I40E_PTT_UNUSED_ENTRY(69),
 742         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 743         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 744         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 745
 746         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 747         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 748
 749         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 750         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 751         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 752         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 753         I40E_PTT_UNUSED_ENTRY(77),
 754         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 755         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 756         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 757
 758         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 759         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 760         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 761         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 762         I40E_PTT_UNUSED_ENTRY(84),
 763         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 764         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 765         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 766
 767         /* Non Tunneled IPv6 */
 768         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 769         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 770         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY3),
 771         I40E_PTT_UNUSED_ENTRY(91),
 772         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 773         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 774         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 775
 776         /* IPv6 --> IPv4 */
 777         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 778         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 779         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 780         I40E_PTT_UNUSED_ENTRY(98),
 781         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 782         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 783         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 784
 785         /* IPv6 --> IPv6 */
 786         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 787         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 788         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 789         I40E_PTT_UNUSED_ENTRY(105),
 790         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 791         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 792         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 793
 794         /* IPv6 --> GRE/NAT */
 795         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 796
 797         /* IPv6 --> GRE/NAT -> IPv4 */
 798         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 799         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 800         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 801         I40E_PTT_UNUSED_ENTRY(113),
 802         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 803         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 804         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 805
 806         /* IPv6 --> GRE/NAT -> IPv6 */
 807         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 808         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 809         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 810         I40E_PTT_UNUSED_ENTRY(120),
 811         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 812         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 813         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 814
 815         /* IPv6 --> GRE/NAT -> MAC */
 816         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 817
 818         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 819         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 820         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 821         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 822         I40E_PTT_UNUSED_ENTRY(128),
 823         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 824         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 825         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 826
 827         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 828         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 829         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 830         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 831         I40E_PTT_UNUSED_ENTRY(135),
 832         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 833         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 834         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 835
 836         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 837         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 838
 839         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 840         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 841         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 842         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 843         I40E_PTT_UNUSED_ENTRY(143),
 844         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 845         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 846         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 847
 848         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 849         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 850         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 851         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 852         I40E_PTT_UNUSED_ENTRY(150),
 853         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 854         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 855         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 856
 857         /* unused entries */
 858         I40E_PTT_UNUSED_ENTRY(154),
 859         I40E_PTT_UNUSED_ENTRY(155),
 860         I40E_PTT_UNUSED_ENTRY(156),
 861         I40E_PTT_UNUSED_ENTRY(157),
 862         I40E_PTT_UNUSED_ENTRY(158),
 863         I40E_PTT_UNUSED_ENTRY(159),
 864
 865         I40E_PTT_UNUSED_ENTRY(160),
 866         I40E_PTT_UNUSED_ENTRY(161),
 867         I40E_PTT_UNUSED_ENTRY(162),
 868         I40E_PTT_UNUSED_ENTRY(163),
 869         I40E_PTT_UNUSED_ENTRY(164),
 870         I40E_PTT_UNUSED_ENTRY(165),
 871         I40E_PTT_UNUSED_ENTRY(166),
 872         I40E_PTT_UNUSED_ENTRY(167),
 873         I40E_PTT_UNUSED_ENTRY(168),
 874         I40E_PTT_UNUSED_ENTRY(169),
 875
 876         I40E_PTT_UNUSED_ENTRY(170),
 877         I40E_PTT_UNUSED_ENTRY(171),
 878         I40E_PTT_UNUSED_ENTRY(172),
 879         I40E_PTT_UNUSED_ENTRY(173),
 880         I40E_PTT_UNUSED_ENTRY(174),
 881         I40E_PTT_UNUSED_ENTRY(175),
 882         I40E_PTT_UNUSED_ENTRY(176),
 883         I40E_PTT_UNUSED_ENTRY(177),
 884         I40E_PTT_UNUSED_ENTRY(178),
 885         I40E_PTT_UNUSED_ENTRY(179),
 886
 887         I40E_PTT_UNUSED_ENTRY(180),
 888         I40E_PTT_UNUSED_ENTRY(181),
 889         I40E_PTT_UNUSED_ENTRY(182),
 890         I40E_PTT_UNUSED_ENTRY(183),
 891         I40E_PTT_UNUSED_ENTRY(184),
 892         I40E_PTT_UNUSED_ENTRY(185),
 893         I40E_PTT_UNUSED_ENTRY(186),
 894         I40E_PTT_UNUSED_ENTRY(187),
 895         I40E_PTT_UNUSED_ENTRY(188),
 896         I40E_PTT_UNUSED_ENTRY(189),
 897
 898         I40E_PTT_UNUSED_ENTRY(190),
 899         I40E_PTT_UNUSED_ENTRY(191),
 900         I40E_PTT_UNUSED_ENTRY(192),
 901         I40E_PTT_UNUSED_ENTRY(193),
 902         I40E_PTT_UNUSED_ENTRY(194),
 903         I40E_PTT_UNUSED_ENTRY(195),
 904         I40E_PTT_UNUSED_ENTRY(196),
 905         I40E_PTT_UNUSED_ENTRY(197),
 906         I40E_PTT_UNUSED_ENTRY(198),
 907         I40E_PTT_UNUSED_ENTRY(199),
 908
 909         I40E_PTT_UNUSED_ENTRY(200),
 910         I40E_PTT_UNUSED_ENTRY(201),
 911         I40E_PTT_UNUSED_ENTRY(202),
 912         I40E_PTT_UNUSED_ENTRY(203),
 913         I40E_PTT_UNUSED_ENTRY(204),
 914         I40E_PTT_UNUSED_ENTRY(205),
 915         I40E_PTT_UNUSED_ENTRY(206),
 916         I40E_PTT_UNUSED_ENTRY(207),
 917         I40E_PTT_UNUSED_ENTRY(208),
 918         I40E_PTT_UNUSED_ENTRY(209),
 919
 920         I40E_PTT_UNUSED_ENTRY(210),
 921         I40E_PTT_UNUSED_ENTRY(211),
 922         I40E_PTT_UNUSED_ENTRY(212),
 923         I40E_PTT_UNUSED_ENTRY(213),
 924         I40E_PTT_UNUSED_ENTRY(214),
 925         I40E_PTT_UNUSED_ENTRY(215),
 926         I40E_PTT_UNUSED_ENTRY(216),
 927         I40E_PTT_UNUSED_ENTRY(217),
 928         I40E_PTT_UNUSED_ENTRY(218),
 929         I40E_PTT_UNUSED_ENTRY(219),
 930
 931         I40E_PTT_UNUSED_ENTRY(220),
 932         I40E_PTT_UNUSED_ENTRY(221),
 933         I40E_PTT_UNUSED_ENTRY(222),
 934         I40E_PTT_UNUSED_ENTRY(223),
 935         I40E_PTT_UNUSED_ENTRY(224),
 936         I40E_PTT_UNUSED_ENTRY(225),
 937         I40E_PTT_UNUSED_ENTRY(226),
 938         I40E_PTT_UNUSED_ENTRY(227),
 939         I40E_PTT_UNUSED_ENTRY(228),
 940         I40E_PTT_UNUSED_ENTRY(229),
 941
 942         I40E_PTT_UNUSED_ENTRY(230),
 943         I40E_PTT_UNUSED_ENTRY(231),
 944         I40E_PTT_UNUSED_ENTRY(232),
 945         I40E_PTT_UNUSED_ENTRY(233),
 946         I40E_PTT_UNUSED_ENTRY(234),
 947         I40E_PTT_UNUSED_ENTRY(235),
 948         I40E_PTT_UNUSED_ENTRY(236),
 949         I40E_PTT_UNUSED_ENTRY(237),
 950         I40E_PTT_UNUSED_ENTRY(238),
 951         I40E_PTT_UNUSED_ENTRY(239),
 952
 953         I40E_PTT_UNUSED_ENTRY(240),
 954         I40E_PTT_UNUSED_ENTRY(241),
 955         I40E_PTT_UNUSED_ENTRY(242),
 956         I40E_PTT_UNUSED_ENTRY(243),
 957         I40E_PTT_UNUSED_ENTRY(244),
 958         I40E_PTT_UNUSED_ENTRY(245),
 959         I40E_PTT_UNUSED_ENTRY(246),
 960         I40E_PTT_UNUSED_ENTRY(247),
 961         I40E_PTT_UNUSED_ENTRY(248),
 962         I40E_PTT_UNUSED_ENTRY(249),
 963
 964         I40E_PTT_UNUSED_ENTRY(250),
 965         I40E_PTT_UNUSED_ENTRY(251),
 966         I40E_PTT_UNUSED_ENTRY(252),
 967         I40E_PTT_UNUSED_ENTRY(253),
 968         I40E_PTT_UNUSED_ENTRY(254),
 969         I40E_PTT_UNUSED_ENTRY(255)
 970 };
 971
 972
 973 /**
 974  * i40e_validate_mac_addr - Validate unicast MAC address
 975  * @mac_addr: pointer to MAC address
 976  *
 977  * Tests a MAC address to ensure it is a valid Individual Address
 978  **/
 979 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
 980 {
 981         enum i40e_status_code status = I40E_SUCCESS;
 982
 983         DEBUGFUNC("i40e_validate_mac_addr");
 984
 985         /* Broadcast addresses ARE multicast addresses
 986          * Make sure it is not a multicast address
 987          * Reject the zero address
 988          */
 989         if (I40E_IS_MULTICAST(mac_addr) ||
 990             (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
 991               mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
 992                 status = I40E_ERR_INVALID_MAC_ADDR;
 993
 994         return status;
 995 }
 996 #ifdef PF_DRIVER
 997
 998 /**
 999  * i40e_init_shared_code - Initialize the shared code
1000  * @hw: pointer to hardware structure
1001  *
1002  * This assigns the MAC type and PHY code and inits the NVM.
1003  * Does not touch the hardware. This function must be called prior to any
1004  * other function in the shared code. The i40e_hw structure should be
1005  * memset to 0 prior to calling this function.  The following fields in
1006  * hw structure should be filled in prior to calling this function:
1007  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1008  * subsystem_vendor_id, and revision_id
1009  **/
1010 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
1011 {
1012         enum i40e_status_code status = I40E_SUCCESS;
1013         u32 port, ari, func_rid;
1014
1015         DEBUGFUNC("i40e_init_shared_code");
1016
1017         i40e_set_mac_type(hw);
1018
1019         switch (hw->mac.type) {
1020         case I40E_MAC_XL710:
1021 #ifdef X722_SUPPORT
1022         case I40E_MAC_X722:
1023 #endif
1024                 break;
1025         default:
1026                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1027         }
1028
1029         hw->phy.get_link_info = true;
1030
1031         /* Determine port number and PF number*/
1032         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1033                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1034         hw->port = (u8)port;
1035         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1036                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1037         func_rid = rd32(hw, I40E_PF_FUNC_RID);
1038         if (ari)
1039                 hw->pf_id = (u8)(func_rid & 0xff);
1040         else
1041                 hw->pf_id = (u8)(func_rid & 0x7);
1042
1043 #ifdef X722_SUPPORT
1044         if (hw->mac.type == I40E_MAC_X722)
1045                 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
1046
1047 #endif
1048         status = i40e_init_nvm(hw);
1049         return status;
1050 }
1051
1052 /**
1053  * i40e_aq_mac_address_read - Retrieve the MAC addresses
1054  * @hw: pointer to the hw struct
1055  * @flags: a return indicator of what addresses were added to the addr store
1056  * @addrs: the requestor's mac addr store
1057  * @cmd_details: pointer to command details structure or NULL
1058  **/
1059 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1060                                    u16 *flags,
1061                                    struct i40e_aqc_mac_address_read_data *addrs,
1062                                    struct i40e_asq_cmd_details *cmd_details)
1063 {
1064         struct i40e_aq_desc desc;
1065         struct i40e_aqc_mac_address_read *cmd_data =
1066                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1067         enum i40e_status_code status;
1068
1069         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1070         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1071
1072         status = i40e_asq_send_command(hw, &desc, addrs,
1073                                        sizeof(*addrs), cmd_details);
1074         *flags = LE16_TO_CPU(cmd_data->command_flags);
1075
1076         return status;
1077 }
1078
1079 /**
1080  * i40e_aq_mac_address_write - Change the MAC addresses
1081  * @hw: pointer to the hw struct
1082  * @flags: indicates which MAC to be written
1083  * @mac_addr: address to write
1084  * @cmd_details: pointer to command details structure or NULL
1085  **/
1086 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1087                                     u16 flags, u8 *mac_addr,
1088                                     struct i40e_asq_cmd_details *cmd_details)
1089 {
1090         struct i40e_aq_desc desc;
1091         struct i40e_aqc_mac_address_write *cmd_data =
1092                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1093         enum i40e_status_code status;
1094
1095         i40e_fill_default_direct_cmd_desc(&desc,
1096                                           i40e_aqc_opc_mac_address_write);
1097         cmd_data->command_flags = CPU_TO_LE16(flags);
1098         cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1099         cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1100                                         ((u32)mac_addr[3] << 16) |
1101                                         ((u32)mac_addr[4] << 8) |
1102                                         mac_addr[5]);
1103
1104         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1105
1106         return status;
1107 }
1108
1109 /**
1110  * i40e_get_mac_addr - get MAC address
1111  * @hw: pointer to the HW structure
1112  * @mac_addr: pointer to MAC address
1113  *
1114  * Reads the adapter's MAC address from register
1115  **/
1116 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1117 {
1118         struct i40e_aqc_mac_address_read_data addrs;
1119         enum i40e_status_code status;
1120         u16 flags = 0;
1121
1122         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1123
1124         if (flags & I40E_AQC_LAN_ADDR_VALID)
1125                 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
1126
1127         return status;
1128 }
1129
1130 /**
1131  * i40e_get_port_mac_addr - get Port MAC address
1132  * @hw: pointer to the HW structure
1133  * @mac_addr: pointer to Port MAC address
1134  *
1135  * Reads the adapter's Port MAC address
1136  **/
1137 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1138 {
1139         struct i40e_aqc_mac_address_read_data addrs;
1140         enum i40e_status_code status;
1141         u16 flags = 0;
1142
1143         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1144         if (status)
1145                 return status;
1146
1147         if (flags & I40E_AQC_PORT_ADDR_VALID)
1148                 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
1149         else
1150                 status = I40E_ERR_INVALID_MAC_ADDR;
1151
1152         return status;
1153 }
1154
1155 /**
1156  * i40e_pre_tx_queue_cfg - pre tx queue configure
1157  * @hw: pointer to the HW structure
1158  * @queue: target pf queue index
1159  * @enable: state change request
1160  *
1161  * Handles hw requirement to indicate intention to enable
1162  * or disable target queue.
1163  **/
1164 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1165 {
1166         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1167         u32 reg_block = 0;
1168         u32 reg_val;
1169
1170         if (abs_queue_idx >= 128) {
1171                 reg_block = abs_queue_idx / 128;
1172                 abs_queue_idx %= 128;
1173         }
1174
1175         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1176         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1177         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1178
1179         if (enable)
1180                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1181         else
1182                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1183
1184         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1185 }
1186
1187 /**
1188  *  i40e_read_pba_string - Reads part number string from EEPROM
1189  *  @hw: pointer to hardware structure
1190  *  @pba_num: stores the part number string from the EEPROM
1191  *  @pba_num_size: part number string buffer length
1192  *
1193  *  Reads the part number string from the EEPROM.
1194  **/
1195 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1196                                             u32 pba_num_size)
1197 {
1198         enum i40e_status_code status = I40E_SUCCESS;
1199         u16 pba_word = 0;
1200         u16 pba_size = 0;
1201         u16 pba_ptr = 0;
1202         u16 i = 0;
1203
1204         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1205         if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1206                 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1207                 return status;
1208         }
1209
1210         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1211         if (status != I40E_SUCCESS) {
1212                 DEBUGOUT("Failed to read PBA Block pointer.\n");
1213                 return status;
1214         }
1215
1216         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1217         if (status != I40E_SUCCESS) {
1218                 DEBUGOUT("Failed to read PBA Block size.\n");
1219                 return status;
1220         }
1221
1222         /* Subtract one to get PBA word count (PBA Size word is included in
1223          * total size)
1224          */
1225         pba_size--;
1226         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1227                 DEBUGOUT("Buffer to small for PBA data.\n");
1228                 return I40E_ERR_PARAM;
1229         }
1230
1231         for (i = 0; i < pba_size; i++) {
1232                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1233                 if (status != I40E_SUCCESS) {
1234                         DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1235                         return status;
1236                 }
1237
1238                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1239                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1240         }
1241         pba_num[(pba_size * 2)] = '\0';
1242
1243         return status;
1244 }
1245
1246 /**
1247  * i40e_get_media_type - Gets media type
1248  * @hw: pointer to the hardware structure
1249  **/
1250 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1251 {
1252         enum i40e_media_type media;
1253
1254         switch (hw->phy.link_info.phy_type) {
1255         case I40E_PHY_TYPE_10GBASE_SR:
1256         case I40E_PHY_TYPE_10GBASE_LR:
1257         case I40E_PHY_TYPE_1000BASE_SX:
1258         case I40E_PHY_TYPE_1000BASE_LX:
1259         case I40E_PHY_TYPE_40GBASE_SR4:
1260         case I40E_PHY_TYPE_40GBASE_LR4:
1261                 media = I40E_MEDIA_TYPE_FIBER;
1262                 break;
1263         case I40E_PHY_TYPE_100BASE_TX:
1264         case I40E_PHY_TYPE_1000BASE_T:
1265         case I40E_PHY_TYPE_10GBASE_T:
1266                 media = I40E_MEDIA_TYPE_BASET;
1267                 break;
1268         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1269         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1270         case I40E_PHY_TYPE_10GBASE_CR1:
1271         case I40E_PHY_TYPE_40GBASE_CR4:
1272         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1273         case I40E_PHY_TYPE_40GBASE_AOC:
1274         case I40E_PHY_TYPE_10GBASE_AOC:
1275                 media = I40E_MEDIA_TYPE_DA;
1276                 break;
1277         case I40E_PHY_TYPE_1000BASE_KX:
1278         case I40E_PHY_TYPE_10GBASE_KX4:
1279         case I40E_PHY_TYPE_10GBASE_KR:
1280         case I40E_PHY_TYPE_40GBASE_KR4:
1281         case I40E_PHY_TYPE_20GBASE_KR2:
1282                 media = I40E_MEDIA_TYPE_BACKPLANE;
1283                 break;
1284         case I40E_PHY_TYPE_SGMII:
1285         case I40E_PHY_TYPE_XAUI:
1286         case I40E_PHY_TYPE_XFI:
1287         case I40E_PHY_TYPE_XLAUI:
1288         case I40E_PHY_TYPE_XLPPI:
1289         default:
1290                 media = I40E_MEDIA_TYPE_UNKNOWN;
1291                 break;
1292         }
1293
1294         return media;
1295 }
1296
1297 #define I40E_PF_RESET_WAIT_COUNT        200
1298 /**
1299  * i40e_pf_reset - Reset the PF
1300  * @hw: pointer to the hardware structure
1301  *
1302  * Assuming someone else has triggered a global reset,
1303  * assure the global reset is complete and then reset the PF
1304  **/
1305 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1306 {
1307         u32 cnt = 0;
1308         u32 cnt1 = 0;
1309         u32 reg = 0;
1310         u32 grst_del;
1311
1312         /* Poll for Global Reset steady state in case of recent GRST.
1313          * The grst delay value is in 100ms units, and we'll wait a
1314          * couple counts longer to be sure we don't just miss the end.
1315          */
1316         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1317                         I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1318                         I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1319 #ifdef I40E_ESS_SUPPORT
1320         /* It can take upto 15 secs for GRST steady state */
1321         grst_del = grst_del * 20; /* bump it to 16 secs max to be safe */
1322 #endif
1323         for (cnt = 0; cnt < grst_del + 10; cnt++) {
1324                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1325                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1326                         break;
1327                 i40e_msec_delay(100);
1328         }
1329         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1330                 DEBUGOUT("Global reset polling failed to complete.\n");
1331                 return I40E_ERR_RESET_FAILED;
1332         }
1333
1334         /* Now Wait for the FW to be ready */
1335         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1336                 reg = rd32(hw, I40E_GLNVM_ULD);
1337                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1338                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1339                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1340                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1341                         DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1342                         break;
1343                 }
1344                 i40e_msec_delay(10);
1345         }
1346         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1347                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1348                 DEBUGOUT("wait for FW Reset complete timedout\n");
1349                 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1350                 return I40E_ERR_RESET_FAILED;
1351         }
1352
1353         /* If there was a Global Reset in progress when we got here,
1354          * we don't need to do the PF Reset
1355          */
1356         if (!cnt) {
1357                 reg = rd32(hw, I40E_PFGEN_CTRL);
1358                 wr32(hw, I40E_PFGEN_CTRL,
1359                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1360                 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1361                         reg = rd32(hw, I40E_PFGEN_CTRL);
1362                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1363                                 break;
1364                         i40e_msec_delay(1);
1365                 }
1366                 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1367                         DEBUGOUT("PF reset polling failed to complete.\n");
1368                         return I40E_ERR_RESET_FAILED;
1369                 }
1370         }
1371
1372         i40e_clear_pxe_mode(hw);
1373
1374
1375         return I40E_SUCCESS;
1376 }
1377
1378 /**
1379  * i40e_clear_hw - clear out any left over hw state
1380  * @hw: pointer to the hw struct
1381  *
1382  * Clear queues and interrupts, typically called at init time,
1383  * but after the capabilities have been found so we know how many
1384  * queues and msix vectors have been allocated.
1385  **/
1386 void i40e_clear_hw(struct i40e_hw *hw)
1387 {
1388         u32 num_queues, base_queue;
1389         u32 num_pf_int;
1390         u32 num_vf_int;
1391         u32 num_vfs;
1392         u32 i, j;
1393         u32 val;
1394         u32 eol = 0x7ff;
1395
1396         /* get number of interrupts, queues, and vfs */
1397         val = rd32(hw, I40E_GLPCI_CNF2);
1398         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1399                         I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1400         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1401                         I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1402
1403         val = rd32(hw, I40E_PFLAN_QALLOC);
1404         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1405                         I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1406         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1407                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1408         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1409                 num_queues = (j - base_queue) + 1;
1410         else
1411                 num_queues = 0;
1412
1413         val = rd32(hw, I40E_PF_VT_PFALLOC);
1414         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1415                         I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1416         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1417                         I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1418         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1419                 num_vfs = (j - i) + 1;
1420         else
1421                 num_vfs = 0;
1422
1423         /* stop all the interrupts */
1424         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1425         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1426         for (i = 0; i < num_pf_int - 2; i++)
1427                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1428
1429         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1430         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1431         wr32(hw, I40E_PFINT_LNKLST0, val);
1432         for (i = 0; i < num_pf_int - 2; i++)
1433                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1434         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1435         for (i = 0; i < num_vfs; i++)
1436                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1437         for (i = 0; i < num_vf_int - 2; i++)
1438                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1439
1440         /* warn the HW of the coming Tx disables */
1441         for (i = 0; i < num_queues; i++) {
1442                 u32 abs_queue_idx = base_queue + i;
1443                 u32 reg_block = 0;
1444
1445                 if (abs_queue_idx >= 128) {
1446                         reg_block = abs_queue_idx / 128;
1447                         abs_queue_idx %= 128;
1448                 }
1449
1450                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1451                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1452                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1453                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1454
1455                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1456         }
1457         i40e_usec_delay(400);
1458
1459         /* stop all the queues */
1460         for (i = 0; i < num_queues; i++) {
1461                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1462                 wr32(hw, I40E_QTX_ENA(i), 0);
1463                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1464                 wr32(hw, I40E_QRX_ENA(i), 0);
1465         }
1466
1467         /* short wait for all queue disables to settle */
1468         i40e_usec_delay(50);
1469 }
1470
1471 /**
1472  * i40e_clear_pxe_mode - clear pxe operations mode
1473  * @hw: pointer to the hw struct
1474  *
1475  * Make sure all PXE mode settings are cleared, including things
1476  * like descriptor fetch/write-back mode.
1477  **/
1478 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1479 {
1480         if (i40e_check_asq_alive(hw))
1481                 i40e_aq_clear_pxe_mode(hw, NULL);
1482 }
1483
1484 /**
1485  * i40e_led_is_mine - helper to find matching led
1486  * @hw: pointer to the hw struct
1487  * @idx: index into GPIO registers
1488  *
1489  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1490  */
1491 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1492 {
1493         u32 gpio_val = 0;
1494         u32 port;
1495
1496         if (!hw->func_caps.led[idx])
1497                 return 0;
1498
1499         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1500         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1501                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1502
1503         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1504          * if it is not our port then ignore
1505          */
1506         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1507             (port != hw->port))
1508                 return 0;
1509
1510         return gpio_val;
1511 }
1512
1513 #define I40E_COMBINED_ACTIVITY 0xA
1514 #define I40E_FILTER_ACTIVITY 0xE
1515 #define I40E_LINK_ACTIVITY 0xC
1516 #define I40E_MAC_ACTIVITY 0xD
1517 #define I40E_LED0 22
1518
1519 /**
1520  * i40e_led_get - return current on/off mode
1521  * @hw: pointer to the hw struct
1522  *
1523  * The value returned is the 'mode' field as defined in the
1524  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1525  * values are variations of possible behaviors relating to
1526  * blink, link, and wire.
1527  **/
1528 u32 i40e_led_get(struct i40e_hw *hw)
1529 {
1530         u32 current_mode = 0;
1531         u32 mode = 0;
1532         int i;
1533
1534         /* as per the documentation GPIO 22-29 are the LED
1535          * GPIO pins named LED0..LED7
1536          */
1537         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1538                 u32 gpio_val = i40e_led_is_mine(hw, i);
1539
1540                 if (!gpio_val)
1541                         continue;
1542
1543                 /* ignore gpio LED src mode entries related to the activity LEDs */
1544                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1545                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1546                 switch (current_mode) {
1547                 case I40E_COMBINED_ACTIVITY:
1548                 case I40E_FILTER_ACTIVITY:
1549                 case I40E_MAC_ACTIVITY:
1550                         continue;
1551                 default:
1552                         break;
1553                 }
1554
1555                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1556                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1557                 break;
1558         }
1559
1560         return mode;
1561 }
1562
1563 /**
1564  * i40e_led_set - set new on/off mode
1565  * @hw: pointer to the hw struct
1566  * @mode: 0=off, 0xf=on (else see manual for mode details)
1567  * @blink: true if the LED should blink when on, false if steady
1568  *
1569  * if this function is used to turn on the blink it should
1570  * be used to disable the blink when restoring the original state.
1571  **/
1572 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1573 {
1574         u32 current_mode = 0;
1575         int i;
1576
1577         if (mode & 0xfffffff0)
1578                 DEBUGOUT1("invalid mode passed in %X\n", mode);
1579
1580         /* as per the documentation GPIO 22-29 are the LED
1581          * GPIO pins named LED0..LED7
1582          */
1583         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1584                 u32 gpio_val = i40e_led_is_mine(hw, i);
1585
1586                 if (!gpio_val)
1587                         continue;
1588
1589                 /* ignore gpio LED src mode entries related to the activity LEDs */
1590                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1591                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1592                 switch (current_mode) {
1593                 case I40E_COMBINED_ACTIVITY:
1594                 case I40E_FILTER_ACTIVITY:
1595                 case I40E_MAC_ACTIVITY:
1596                         continue;
1597                 default:
1598                         break;
1599                 }
1600
1601                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1602                 /* this & is a bit of paranoia, but serves as a range check */
1603                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1604                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1605
1606                 if (mode == I40E_LINK_ACTIVITY)
1607                         blink = false;
1608
1609                 if (blink)
1610                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1611                 else
1612                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1613
1614                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1615                 break;
1616         }
1617 }
1618
1619 /* Admin command wrappers */
1620
1621 /**
1622  * i40e_aq_get_phy_capabilities
1623  * @hw: pointer to the hw struct
1624  * @abilities: structure for PHY capabilities to be filled
1625  * @qualified_modules: report Qualified Modules
1626  * @report_init: report init capabilities (active are default)
1627  * @cmd_details: pointer to command details structure or NULL
1628  *
1629  * Returns the various PHY abilities supported on the Port.
1630  **/
1631 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1632                         bool qualified_modules, bool report_init,
1633                         struct i40e_aq_get_phy_abilities_resp *abilities,
1634                         struct i40e_asq_cmd_details *cmd_details)
1635 {
1636         struct i40e_aq_desc desc;
1637         enum i40e_status_code status;
1638         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1639
1640         if (!abilities)
1641                 return I40E_ERR_PARAM;
1642
1643         i40e_fill_default_direct_cmd_desc(&desc,
1644                                           i40e_aqc_opc_get_phy_abilities);
1645
1646         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1647         if (abilities_size > I40E_AQ_LARGE_BUF)
1648                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1649
1650         if (qualified_modules)
1651                 desc.params.external.param0 |=
1652                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1653
1654         if (report_init)
1655                 desc.params.external.param0 |=
1656                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1657
1658         status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1659                                     cmd_details);
1660
1661         if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1662                 status = I40E_ERR_UNKNOWN_PHY;
1663
1664         if (report_init)
1665                 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1666
1667         return status;
1668 }
1669
1670 /**
1671  * i40e_aq_set_phy_config
1672  * @hw: pointer to the hw struct
1673  * @config: structure with PHY configuration to be set
1674  * @cmd_details: pointer to command details structure or NULL
1675  *
1676  * Set the various PHY configuration parameters
1677  * supported on the Port.One or more of the Set PHY config parameters may be
1678  * ignored in an MFP mode as the PF may not have the privilege to set some
1679  * of the PHY Config parameters. This status will be indicated by the
1680  * command response.
1681  **/
1682 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1683                                 struct i40e_aq_set_phy_config *config,
1684                                 struct i40e_asq_cmd_details *cmd_details)
1685 {
1686         struct i40e_aq_desc desc;
1687         struct i40e_aq_set_phy_config *cmd =
1688                 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1689         enum i40e_status_code status;
1690
1691         if (!config)
1692                 return I40E_ERR_PARAM;
1693
1694         i40e_fill_default_direct_cmd_desc(&desc,
1695                                           i40e_aqc_opc_set_phy_config);
1696
1697         *cmd = *config;
1698
1699         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1700
1701         return status;
1702 }
1703
1704 /**
1705  * i40e_set_fc
1706  * @hw: pointer to the hw struct
1707  *
1708  * Set the requested flow control mode using set_phy_config.
1709  **/
1710 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1711                                   bool atomic_restart)
1712 {
1713         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1714         struct i40e_aq_get_phy_abilities_resp abilities;
1715         struct i40e_aq_set_phy_config config;
1716         enum i40e_status_code status;
1717         u8 pause_mask = 0x0;
1718
1719         *aq_failures = 0x0;
1720
1721         switch (fc_mode) {
1722         case I40E_FC_FULL:
1723                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1724                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1725                 break;
1726         case I40E_FC_RX_PAUSE:
1727                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1728                 break;
1729         case I40E_FC_TX_PAUSE:
1730                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1731                 break;
1732         default:
1733                 break;
1734         }
1735
1736         /* Get the current phy config */
1737         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1738                                               NULL);
1739         if (status) {
1740                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1741                 return status;
1742         }
1743
1744         memset(&config, 0, sizeof(config));
1745         /* clear the old pause settings */
1746         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1747                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1748         /* set the new abilities */
1749         config.abilities |= pause_mask;
1750         /* If the abilities have changed, then set the new config */
1751         if (config.abilities != abilities.abilities) {
1752                 /* Auto restart link so settings take effect */
1753                 if (atomic_restart)
1754                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1755                 /* Copy over all the old settings */
1756                 config.phy_type = abilities.phy_type;
1757                 config.link_speed = abilities.link_speed;
1758                 config.eee_capability = abilities.eee_capability;
1759                 config.eeer = abilities.eeer_val;
1760                 config.low_power_ctrl = abilities.d3_lpan;
1761                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1762
1763                 if (status)
1764                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1765         }
1766         /* Update the link info */
1767         status = i40e_update_link_info(hw);
1768         if (status) {
1769                 /* Wait a little bit (on 40G cards it sometimes takes a really
1770                  * long time for link to come back from the atomic reset)
1771                  * and try once more
1772                  */
1773                 i40e_msec_delay(1000);
1774                 status = i40e_update_link_info(hw);
1775         }
1776         if (status)
1777                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1778
1779         return status;
1780 }
1781
1782 /**
1783  * i40e_aq_set_mac_config
1784  * @hw: pointer to the hw struct
1785  * @max_frame_size: Maximum Frame Size to be supported by the port
1786  * @crc_en: Tell HW to append a CRC to outgoing frames
1787  * @pacing: Pacing configurations
1788  * @cmd_details: pointer to command details structure or NULL
1789  *
1790  * Configure MAC settings for frame size, jumbo frame support and the
1791  * addition of a CRC by the hardware.
1792  **/
1793 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1794                                 u16 max_frame_size,
1795                                 bool crc_en, u16 pacing,
1796                                 struct i40e_asq_cmd_details *cmd_details)
1797 {
1798         struct i40e_aq_desc desc;
1799         struct i40e_aq_set_mac_config *cmd =
1800                 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1801         enum i40e_status_code status;
1802
1803         if (max_frame_size == 0)
1804                 return I40E_ERR_PARAM;
1805
1806         i40e_fill_default_direct_cmd_desc(&desc,
1807                                           i40e_aqc_opc_set_mac_config);
1808
1809         cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1810         cmd->params = ((u8)pacing & 0x0F) << 3;
1811         if (crc_en)
1812                 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1813
1814         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1815
1816         return status;
1817 }
1818
1819 /**
1820  * i40e_aq_clear_pxe_mode
1821  * @hw: pointer to the hw struct
1822  * @cmd_details: pointer to command details structure or NULL
1823  *
1824  * Tell the firmware that the driver is taking over from PXE
1825  **/
1826 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1827                         struct i40e_asq_cmd_details *cmd_details)
1828 {
1829         enum i40e_status_code status;
1830         struct i40e_aq_desc desc;
1831         struct i40e_aqc_clear_pxe *cmd =
1832                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1833
1834         i40e_fill_default_direct_cmd_desc(&desc,
1835                                           i40e_aqc_opc_clear_pxe_mode);
1836
1837         cmd->rx_cnt = 0x2;
1838
1839         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1840
1841         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1842
1843         return status;
1844 }
1845
1846 /**
1847  * i40e_aq_set_link_restart_an
1848  * @hw: pointer to the hw struct
1849  * @enable_link: if true: enable link, if false: disable link
1850  * @cmd_details: pointer to command details structure or NULL
1851  *
1852  * Sets up the link and restarts the Auto-Negotiation over the link.
1853  **/
1854 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1855                 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1856 {
1857         struct i40e_aq_desc desc;
1858         struct i40e_aqc_set_link_restart_an *cmd =
1859                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1860         enum i40e_status_code status;
1861
1862         i40e_fill_default_direct_cmd_desc(&desc,
1863                                           i40e_aqc_opc_set_link_restart_an);
1864
1865         cmd->command = I40E_AQ_PHY_RESTART_AN;
1866         if (enable_link)
1867                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1868         else
1869                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1870
1871         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1872
1873         return status;
1874 }
1875
1876 /**
1877  * i40e_aq_get_link_info
1878  * @hw: pointer to the hw struct
1879  * @enable_lse: enable/disable LinkStatusEvent reporting
1880  * @link: pointer to link status structure - optional
1881  * @cmd_details: pointer to command details structure or NULL
1882  *
1883  * Returns the link status of the adapter.
1884  **/
1885 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1886                                 bool enable_lse, struct i40e_link_status *link,
1887                                 struct i40e_asq_cmd_details *cmd_details)
1888 {
1889         struct i40e_aq_desc desc;
1890         struct i40e_aqc_get_link_status *resp =
1891                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1892         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1893         enum i40e_status_code status;
1894         bool tx_pause, rx_pause;
1895         u16 command_flags;
1896
1897         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1898
1899         if (enable_lse)
1900                 command_flags = I40E_AQ_LSE_ENABLE;
1901         else
1902                 command_flags = I40E_AQ_LSE_DISABLE;
1903         resp->command_flags = CPU_TO_LE16(command_flags);
1904
1905         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1906
1907         if (status != I40E_SUCCESS)
1908                 goto aq_get_link_info_exit;
1909
1910         /* save off old link status information */
1911         i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1912                     sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1913
1914         /* update link status */
1915         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1916         hw->phy.media_type = i40e_get_media_type(hw);
1917         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1918         hw_link_info->link_info = resp->link_info;
1919         hw_link_info->an_info = resp->an_info;
1920         hw_link_info->ext_info = resp->ext_info;
1921         hw_link_info->loopback = resp->loopback;
1922         hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1923         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1924
1925         /* update fc info */
1926         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1927         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1928         if (tx_pause & rx_pause)
1929                 hw->fc.current_mode = I40E_FC_FULL;
1930         else if (tx_pause)
1931                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1932         else if (rx_pause)
1933                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1934         else
1935                 hw->fc.current_mode = I40E_FC_NONE;
1936
1937         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1938                 hw_link_info->crc_enable = true;
1939         else
1940                 hw_link_info->crc_enable = false;
1941
1942         if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1943                 hw_link_info->lse_enable = true;
1944         else
1945                 hw_link_info->lse_enable = false;
1946
1947         if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1948              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1949                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1950
1951         /* save link status information */
1952         if (link)
1953                 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1954                             I40E_NONDMA_TO_NONDMA);
1955
1956         /* flag cleared so helper functions don't call AQ again */
1957         hw->phy.get_link_info = false;
1958
1959 aq_get_link_info_exit:
1960         return status;
1961 }
1962
1963 /**
1964  * i40e_aq_set_phy_int_mask
1965  * @hw: pointer to the hw struct
1966  * @mask: interrupt mask to be set
1967  * @cmd_details: pointer to command details structure or NULL
1968  *
1969  * Set link interrupt mask.
1970  **/
1971 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1972                                 u16 mask,
1973                                 struct i40e_asq_cmd_details *cmd_details)
1974 {
1975         struct i40e_aq_desc desc;
1976         struct i40e_aqc_set_phy_int_mask *cmd =
1977                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1978         enum i40e_status_code status;
1979
1980         i40e_fill_default_direct_cmd_desc(&desc,
1981                                           i40e_aqc_opc_set_phy_int_mask);
1982
1983         cmd->event_mask = CPU_TO_LE16(mask);
1984
1985         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1986
1987         return status;
1988 }
1989
1990 /**
1991  * i40e_aq_get_local_advt_reg
1992  * @hw: pointer to the hw struct
1993  * @advt_reg: local AN advertisement register value
1994  * @cmd_details: pointer to command details structure or NULL
1995  *
1996  * Get the Local AN advertisement register value.
1997  **/
1998 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
1999                                 u64 *advt_reg,
2000                                 struct i40e_asq_cmd_details *cmd_details)
2001 {
2002         struct i40e_aq_desc desc;
2003         struct i40e_aqc_an_advt_reg *resp =
2004                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2005         enum i40e_status_code status;
2006
2007         i40e_fill_default_direct_cmd_desc(&desc,
2008                                           i40e_aqc_opc_get_local_advt_reg);
2009
2010         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2011
2012         if (status != I40E_SUCCESS)
2013                 goto aq_get_local_advt_reg_exit;
2014
2015         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2016         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2017
2018 aq_get_local_advt_reg_exit:
2019         return status;
2020 }
2021
2022 /**
2023  * i40e_aq_set_local_advt_reg
2024  * @hw: pointer to the hw struct
2025  * @advt_reg: local AN advertisement register value
2026  * @cmd_details: pointer to command details structure or NULL
2027  *
2028  * Get the Local AN advertisement register value.
2029  **/
2030 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2031                                 u64 advt_reg,
2032                                 struct i40e_asq_cmd_details *cmd_details)
2033 {
2034         struct i40e_aq_desc desc;
2035         struct i40e_aqc_an_advt_reg *cmd =
2036                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2037         enum i40e_status_code status;
2038
2039         i40e_fill_default_direct_cmd_desc(&desc,
2040                                           i40e_aqc_opc_get_local_advt_reg);
2041
2042         cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2043         cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2044
2045         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2046
2047         return status;
2048 }
2049
2050 /**
2051  * i40e_aq_get_partner_advt
2052  * @hw: pointer to the hw struct
2053  * @advt_reg: AN partner advertisement register value
2054  * @cmd_details: pointer to command details structure or NULL
2055  *
2056  * Get the link partner AN advertisement register value.
2057  **/
2058 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2059                                 u64 *advt_reg,
2060                                 struct i40e_asq_cmd_details *cmd_details)
2061 {
2062         struct i40e_aq_desc desc;
2063         struct i40e_aqc_an_advt_reg *resp =
2064                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2065         enum i40e_status_code status;
2066
2067         i40e_fill_default_direct_cmd_desc(&desc,
2068                                           i40e_aqc_opc_get_partner_advt);
2069
2070         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2071
2072         if (status != I40E_SUCCESS)
2073                 goto aq_get_partner_advt_exit;
2074
2075         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2076         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2077
2078 aq_get_partner_advt_exit:
2079         return status;
2080 }
2081
2082 /**
2083  * i40e_aq_set_lb_modes
2084  * @hw: pointer to the hw struct
2085  * @lb_modes: loopback mode to be set
2086  * @cmd_details: pointer to command details structure or NULL
2087  *
2088  * Sets loopback modes.
2089  **/
2090 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2091                                 u16 lb_modes,
2092                                 struct i40e_asq_cmd_details *cmd_details)
2093 {
2094         struct i40e_aq_desc desc;
2095         struct i40e_aqc_set_lb_mode *cmd =
2096                 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2097         enum i40e_status_code status;
2098
2099         i40e_fill_default_direct_cmd_desc(&desc,
2100                                           i40e_aqc_opc_set_lb_modes);
2101
2102         cmd->lb_mode = CPU_TO_LE16(lb_modes);
2103
2104         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2105
2106         return status;
2107 }
2108
2109 /**
2110  * i40e_aq_set_phy_debug
2111  * @hw: pointer to the hw struct
2112  * @cmd_flags: debug command flags
2113  * @cmd_details: pointer to command details structure or NULL
2114  *
2115  * Reset the external PHY.
2116  **/
2117 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2118                                 struct i40e_asq_cmd_details *cmd_details)
2119 {
2120         struct i40e_aq_desc desc;
2121         struct i40e_aqc_set_phy_debug *cmd =
2122                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2123         enum i40e_status_code status;
2124
2125         i40e_fill_default_direct_cmd_desc(&desc,
2126                                           i40e_aqc_opc_set_phy_debug);
2127
2128         cmd->command_flags = cmd_flags;
2129
2130         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2131
2132         return status;
2133 }
2134
2135 /**
2136  * i40e_aq_add_vsi
2137  * @hw: pointer to the hw struct
2138  * @vsi_ctx: pointer to a vsi context struct
2139  * @cmd_details: pointer to command details structure or NULL
2140  *
2141  * Add a VSI context to the hardware.
2142 **/
2143 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2144                                 struct i40e_vsi_context *vsi_ctx,
2145                                 struct i40e_asq_cmd_details *cmd_details)
2146 {
2147         struct i40e_aq_desc desc;
2148         struct i40e_aqc_add_get_update_vsi *cmd =
2149                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2150         struct i40e_aqc_add_get_update_vsi_completion *resp =
2151                 (struct i40e_aqc_add_get_update_vsi_completion *)
2152                 &desc.params.raw;
2153         enum i40e_status_code status;
2154
2155         i40e_fill_default_direct_cmd_desc(&desc,
2156                                           i40e_aqc_opc_add_vsi);
2157
2158         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2159         cmd->connection_type = vsi_ctx->connection_type;
2160         cmd->vf_id = vsi_ctx->vf_num;
2161         cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2162
2163         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2164
2165         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2166                                     sizeof(vsi_ctx->info), cmd_details);
2167
2168         if (status != I40E_SUCCESS)
2169                 goto aq_add_vsi_exit;
2170
2171         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2172         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2173         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2174         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2175
2176 aq_add_vsi_exit:
2177         return status;
2178 }
2179
2180 /**
2181  * i40e_aq_set_default_vsi
2182  * @hw: pointer to the hw struct
2183  * @seid: vsi number
2184  * @cmd_details: pointer to command details structure or NULL
2185  **/
2186 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2187                                 u16 seid,
2188                                 struct i40e_asq_cmd_details *cmd_details)
2189 {
2190         struct i40e_aq_desc desc;
2191         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2192                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2193                 &desc.params.raw;
2194         enum i40e_status_code status;
2195
2196         i40e_fill_default_direct_cmd_desc(&desc,
2197                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2198
2199         cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2200         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2201         cmd->seid = CPU_TO_LE16(seid);
2202
2203         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2204
2205         return status;
2206 }
2207
2208 /**
2209  * i40e_aq_set_vsi_unicast_promiscuous
2210  * @hw: pointer to the hw struct
2211  * @seid: vsi number
2212  * @set: set unicast promiscuous enable/disable
2213  * @cmd_details: pointer to command details structure or NULL
2214  **/
2215 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2216                                 u16 seid, bool set,
2217                                 struct i40e_asq_cmd_details *cmd_details)
2218 {
2219         struct i40e_aq_desc desc;
2220         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2221                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2222         enum i40e_status_code status;
2223         u16 flags = 0;
2224
2225         i40e_fill_default_direct_cmd_desc(&desc,
2226                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2227
2228         if (set)
2229                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2230
2231         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2232
2233         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2234
2235         cmd->seid = CPU_TO_LE16(seid);
2236         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2237
2238         return status;
2239 }
2240
2241 /**
2242  * i40e_aq_set_vsi_multicast_promiscuous
2243  * @hw: pointer to the hw struct
2244  * @seid: vsi number
2245  * @set: set multicast promiscuous enable/disable
2246  * @cmd_details: pointer to command details structure or NULL
2247  **/
2248 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2249                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2250 {
2251         struct i40e_aq_desc desc;
2252         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2253                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2254         enum i40e_status_code status;
2255         u16 flags = 0;
2256
2257         i40e_fill_default_direct_cmd_desc(&desc,
2258                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2259
2260         if (set)
2261                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2262
2263         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2264
2265         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2266
2267         cmd->seid = CPU_TO_LE16(seid);
2268         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2269
2270         return status;
2271 }
2272
2273 /**
2274  * i40e_aq_set_vsi_mc_promisc_on_vlan
2275  * @hw: pointer to the hw struct
2276  * @seid: vsi number
2277  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2278  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2279  * @cmd_details: pointer to command details structure or NULL
2280  **/
2281 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2282                                 u16 seid, bool enable, u16 vid,
2283                                 struct i40e_asq_cmd_details *cmd_details)
2284 {
2285         struct i40e_aq_desc desc;
2286         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2287                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2288         enum i40e_status_code status;
2289         u16 flags = 0;
2290
2291         i40e_fill_default_direct_cmd_desc(&desc,
2292                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2293
2294         if (enable)
2295                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2296
2297         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2298         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2299         cmd->seid = CPU_TO_LE16(seid);
2300         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2301
2302         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2303
2304         return status;
2305 }
2306
2307 /**
2308  * i40e_aq_set_vsi_uc_promisc_on_vlan
2309  * @hw: pointer to the hw struct
2310  * @seid: vsi number
2311  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2312  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2313  * @cmd_details: pointer to command details structure or NULL
2314  **/
2315 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2316                                 u16 seid, bool enable, u16 vid,
2317                                 struct i40e_asq_cmd_details *cmd_details)
2318 {
2319         struct i40e_aq_desc desc;
2320         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2321                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2322         enum i40e_status_code status;
2323         u16 flags = 0;
2324
2325         i40e_fill_default_direct_cmd_desc(&desc,
2326                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2327
2328         if (enable)
2329                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2330
2331         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2332         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2333         cmd->seid = CPU_TO_LE16(seid);
2334         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2335
2336         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2337
2338         return status;
2339 }
2340
2341 /**
2342  * i40e_aq_set_vsi_broadcast
2343  * @hw: pointer to the hw struct
2344  * @seid: vsi number
2345  * @set_filter: true to set filter, false to clear filter
2346  * @cmd_details: pointer to command details structure or NULL
2347  *
2348  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2349  **/
2350 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2351                                 u16 seid, bool set_filter,
2352                                 struct i40e_asq_cmd_details *cmd_details)
2353 {
2354         struct i40e_aq_desc desc;
2355         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2356                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2357         enum i40e_status_code status;
2358
2359         i40e_fill_default_direct_cmd_desc(&desc,
2360                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2361
2362         if (set_filter)
2363                 cmd->promiscuous_flags
2364                             |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2365         else
2366                 cmd->promiscuous_flags
2367                             &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2368
2369         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2370         cmd->seid = CPU_TO_LE16(seid);
2371         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2372
2373         return status;
2374 }
2375
2376 /**
2377  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2378  * @hw: pointer to the hw struct
2379  * @seid: vsi number
2380  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2381  * @cmd_details: pointer to command details structure or NULL
2382  **/
2383 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2384                                 u16 seid, bool enable,
2385                                 struct i40e_asq_cmd_details *cmd_details)
2386 {
2387         struct i40e_aq_desc desc;
2388         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2389                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2390         enum i40e_status_code status;
2391         u16 flags = 0;
2392
2393         i40e_fill_default_direct_cmd_desc(&desc,
2394                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2395         if (enable)
2396                 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2397
2398         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2399         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2400         cmd->seid = CPU_TO_LE16(seid);
2401
2402         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2403
2404         return status;
2405 }
2406
2407 /**
2408  * i40e_get_vsi_params - get VSI configuration info
2409  * @hw: pointer to the hw struct
2410  * @vsi_ctx: pointer to a vsi context struct
2411  * @cmd_details: pointer to command details structure or NULL
2412  **/
2413 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2414                                 struct i40e_vsi_context *vsi_ctx,
2415                                 struct i40e_asq_cmd_details *cmd_details)
2416 {
2417         struct i40e_aq_desc desc;
2418         struct i40e_aqc_add_get_update_vsi *cmd =
2419                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2420         struct i40e_aqc_add_get_update_vsi_completion *resp =
2421                 (struct i40e_aqc_add_get_update_vsi_completion *)
2422                 &desc.params.raw;
2423         enum i40e_status_code status;
2424
2425         UNREFERENCED_1PARAMETER(cmd_details);
2426         i40e_fill_default_direct_cmd_desc(&desc,
2427                                           i40e_aqc_opc_get_vsi_parameters);
2428
2429         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2430
2431         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2432
2433         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2434                                     sizeof(vsi_ctx->info), NULL);
2435
2436         if (status != I40E_SUCCESS)
2437                 goto aq_get_vsi_params_exit;
2438
2439         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2440         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2441         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2442         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2443
2444 aq_get_vsi_params_exit:
2445         return status;
2446 }
2447
2448 /**
2449  * i40e_aq_update_vsi_params
2450  * @hw: pointer to the hw struct
2451  * @vsi_ctx: pointer to a vsi context struct
2452  * @cmd_details: pointer to command details structure or NULL
2453  *
2454  * Update a VSI context.
2455  **/
2456 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2457                                 struct i40e_vsi_context *vsi_ctx,
2458                                 struct i40e_asq_cmd_details *cmd_details)
2459 {
2460         struct i40e_aq_desc desc;
2461         struct i40e_aqc_add_get_update_vsi *cmd =
2462                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2463         enum i40e_status_code status;
2464
2465         i40e_fill_default_direct_cmd_desc(&desc,
2466                                           i40e_aqc_opc_update_vsi_parameters);
2467         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2468
2469         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2470
2471         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2472                                     sizeof(vsi_ctx->info), cmd_details);
2473
2474         return status;
2475 }
2476
2477 /**
2478  * i40e_aq_get_switch_config
2479  * @hw: pointer to the hardware structure
2480  * @buf: pointer to the result buffer
2481  * @buf_size: length of input buffer
2482  * @start_seid: seid to start for the report, 0 == beginning
2483  * @cmd_details: pointer to command details structure or NULL
2484  *
2485  * Fill the buf with switch configuration returned from AdminQ command
2486  **/
2487 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2488                                 struct i40e_aqc_get_switch_config_resp *buf,
2489                                 u16 buf_size, u16 *start_seid,
2490                                 struct i40e_asq_cmd_details *cmd_details)
2491 {
2492         struct i40e_aq_desc desc;
2493         struct i40e_aqc_switch_seid *scfg =
2494                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2495         enum i40e_status_code status;
2496
2497         i40e_fill_default_direct_cmd_desc(&desc,
2498                                           i40e_aqc_opc_get_switch_config);
2499         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2500         if (buf_size > I40E_AQ_LARGE_BUF)
2501                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2502         scfg->seid = CPU_TO_LE16(*start_seid);
2503
2504         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2505         *start_seid = LE16_TO_CPU(scfg->seid);
2506
2507         return status;
2508 }
2509
2510 /**
2511  * i40e_aq_get_firmware_version
2512  * @hw: pointer to the hw struct
2513  * @fw_major_version: firmware major version
2514  * @fw_minor_version: firmware minor version
2515  * @fw_build: firmware build number
2516  * @api_major_version: major queue version
2517  * @api_minor_version: minor queue version
2518  * @cmd_details: pointer to command details structure or NULL
2519  *
2520  * Get the firmware version from the admin queue commands
2521  **/
2522 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2523                                 u16 *fw_major_version, u16 *fw_minor_version,
2524                                 u32 *fw_build,
2525                                 u16 *api_major_version, u16 *api_minor_version,
2526                                 struct i40e_asq_cmd_details *cmd_details)
2527 {
2528         struct i40e_aq_desc desc;
2529         struct i40e_aqc_get_version *resp =
2530                 (struct i40e_aqc_get_version *)&desc.params.raw;
2531         enum i40e_status_code status;
2532
2533         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2534
2535         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2536
2537         if (status == I40E_SUCCESS) {
2538                 if (fw_major_version != NULL)
2539                         *fw_major_version = LE16_TO_CPU(resp->fw_major);
2540                 if (fw_minor_version != NULL)
2541                         *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2542                 if (fw_build != NULL)
2543                         *fw_build = LE32_TO_CPU(resp->fw_build);
2544                 if (api_major_version != NULL)
2545                         *api_major_version = LE16_TO_CPU(resp->api_major);
2546                 if (api_minor_version != NULL)
2547                         *api_minor_version = LE16_TO_CPU(resp->api_minor);
2548
2549                 /* A workaround to fix the API version in SW */
2550                 if (api_major_version && api_minor_version &&
2551                     fw_major_version && fw_minor_version &&
2552                     ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2553                     (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2554                      (*fw_major_version > 4)))
2555                         *api_minor_version = 2;
2556         }
2557
2558         return status;
2559 }
2560
2561 /**
2562  * i40e_aq_send_driver_version
2563  * @hw: pointer to the hw struct
2564  * @dv: driver's major, minor version
2565  * @cmd_details: pointer to command details structure or NULL
2566  *
2567  * Send the driver version to the firmware
2568  **/
2569 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2570                                 struct i40e_driver_version *dv,
2571                                 struct i40e_asq_cmd_details *cmd_details)
2572 {
2573         struct i40e_aq_desc desc;
2574         struct i40e_aqc_driver_version *cmd =
2575                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2576         enum i40e_status_code status;
2577         u16 len;
2578
2579         if (dv == NULL)
2580                 return I40E_ERR_PARAM;
2581
2582         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2583
2584         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2585         cmd->driver_major_ver = dv->major_version;
2586         cmd->driver_minor_ver = dv->minor_version;
2587         cmd->driver_build_ver = dv->build_version;
2588         cmd->driver_subbuild_ver = dv->subbuild_version;
2589
2590         len = 0;
2591         while (len < sizeof(dv->driver_string) &&
2592                (dv->driver_string[len] < 0x80) &&
2593                dv->driver_string[len])
2594                 len++;
2595         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2596                                        len, cmd_details);
2597
2598         return status;
2599 }
2600
2601 /**
2602  * i40e_get_link_status - get status of the HW network link
2603  * @hw: pointer to the hw struct
2604  * @link_up: pointer to bool (true/false = linkup/linkdown)
2605  *
2606  * Variable link_up true if link is up, false if link is down.
2607  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2608  *
2609  * Side effect: LinkStatusEvent reporting becomes enabled
2610  **/
2611 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2612 {
2613         enum i40e_status_code status = I40E_SUCCESS;
2614
2615         if (hw->phy.get_link_info) {
2616                 status = i40e_update_link_info(hw);
2617
2618                 if (status != I40E_SUCCESS)
2619                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2620                                    status);
2621         }
2622
2623         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2624
2625         return status;
2626 }
2627
2628 /**
2629  * i40e_updatelink_status - update status of the HW network link
2630  * @hw: pointer to the hw struct
2631  **/
2632 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2633 {
2634         struct i40e_aq_get_phy_abilities_resp abilities;
2635         enum i40e_status_code status = I40E_SUCCESS;
2636
2637         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2638         if (status)
2639                 return status;
2640
2641         if (hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) {
2642                 status = i40e_aq_get_phy_capabilities(hw, false, false,
2643                                                       &abilities, NULL);
2644                 if (status)
2645                         return status;
2646
2647                 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2648                         sizeof(hw->phy.link_info.module_type));
2649         }
2650         return status;
2651 }
2652
2653
2654 /**
2655  * i40e_get_link_speed
2656  * @hw: pointer to the hw struct
2657  *
2658  * Returns the link speed of the adapter.
2659  **/
2660 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2661 {
2662         enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2663         enum i40e_status_code status = I40E_SUCCESS;
2664
2665         if (hw->phy.get_link_info) {
2666                 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2667
2668                 if (status != I40E_SUCCESS)
2669                         goto i40e_link_speed_exit;
2670         }
2671
2672         speed = hw->phy.link_info.link_speed;
2673
2674 i40e_link_speed_exit:
2675         return speed;
2676 }
2677
2678 /**
2679  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2680  * @hw: pointer to the hw struct
2681  * @uplink_seid: the MAC or other gizmo SEID
2682  * @downlink_seid: the VSI SEID
2683  * @enabled_tc: bitmap of TCs to be enabled
2684  * @default_port: true for default port VSI, false for control port
2685  * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
2686  * @veb_seid: pointer to where to put the resulting VEB SEID
2687  * @cmd_details: pointer to command details structure or NULL
2688  *
2689  * This asks the FW to add a VEB between the uplink and downlink
2690  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2691  **/
2692 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2693                                 u16 downlink_seid, u8 enabled_tc,
2694                                 bool default_port, bool enable_l2_filtering,
2695                                 u16 *veb_seid,
2696                                 struct i40e_asq_cmd_details *cmd_details)
2697 {
2698         struct i40e_aq_desc desc;
2699         struct i40e_aqc_add_veb *cmd =
2700                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2701         struct i40e_aqc_add_veb_completion *resp =
2702                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2703         enum i40e_status_code status;
2704         u16 veb_flags = 0;
2705
2706         /* SEIDs need to either both be set or both be 0 for floating VEB */
2707         if (!!uplink_seid != !!downlink_seid)
2708                 return I40E_ERR_PARAM;
2709
2710         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2711
2712         cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2713         cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2714         cmd->enable_tcs = enabled_tc;
2715         if (!uplink_seid)
2716                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2717         if (default_port)
2718                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2719         else
2720                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2721
2722         if (enable_l2_filtering)
2723                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
2724
2725         cmd->veb_flags = CPU_TO_LE16(veb_flags);
2726
2727         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2728
2729         if (!status && veb_seid)
2730                 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2731
2732         return status;
2733 }
2734
2735 /**
2736  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2737  * @hw: pointer to the hw struct
2738  * @veb_seid: the SEID of the VEB to query
2739  * @switch_id: the uplink switch id
2740  * @floating: set to true if the VEB is floating
2741  * @statistic_index: index of the stats counter block for this VEB
2742  * @vebs_used: number of VEB's used by function
2743  * @vebs_free: total VEB's not reserved by any function
2744  * @cmd_details: pointer to command details structure or NULL
2745  *
2746  * This retrieves the parameters for a particular VEB, specified by
2747  * uplink_seid, and returns them to the caller.
2748  **/
2749 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2750                                 u16 veb_seid, u16 *switch_id,
2751                                 bool *floating, u16 *statistic_index,
2752                                 u16 *vebs_used, u16 *vebs_free,
2753                                 struct i40e_asq_cmd_details *cmd_details)
2754 {
2755         struct i40e_aq_desc desc;
2756         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2757                 (struct i40e_aqc_get_veb_parameters_completion *)
2758                 &desc.params.raw;
2759         enum i40e_status_code status;
2760
2761         if (veb_seid == 0)
2762                 return I40E_ERR_PARAM;
2763
2764         i40e_fill_default_direct_cmd_desc(&desc,
2765                                           i40e_aqc_opc_get_veb_parameters);
2766         cmd_resp->seid = CPU_TO_LE16(veb_seid);
2767
2768         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2769         if (status)
2770                 goto get_veb_exit;
2771
2772         if (switch_id)
2773                 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2774         if (statistic_index)
2775                 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2776         if (vebs_used)
2777                 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2778         if (vebs_free)
2779                 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2780         if (floating) {
2781                 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2782                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2783                         *floating = true;
2784                 else
2785                         *floating = false;
2786         }
2787
2788 get_veb_exit:
2789         return status;
2790 }
2791
2792 /**
2793  * i40e_aq_add_macvlan
2794  * @hw: pointer to the hw struct
2795  * @seid: VSI for the mac address
2796  * @mv_list: list of macvlans to be added
2797  * @count: length of the list
2798  * @cmd_details: pointer to command details structure or NULL
2799  *
2800  * Add MAC/VLAN addresses to the HW filtering
2801  **/
2802 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2803                         struct i40e_aqc_add_macvlan_element_data *mv_list,
2804                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2805 {
2806         struct i40e_aq_desc desc;
2807         struct i40e_aqc_macvlan *cmd =
2808                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2809         enum i40e_status_code status;
2810         u16 buf_size;
2811         int i;
2812
2813         if (count == 0 || !mv_list || !hw)
2814                 return I40E_ERR_PARAM;
2815
2816         buf_size = count * sizeof(*mv_list);
2817
2818         /* prep the rest of the request */
2819         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2820         cmd->num_addresses = CPU_TO_LE16(count);
2821         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2822         cmd->seid[1] = 0;
2823         cmd->seid[2] = 0;
2824
2825         for (i = 0; i < count; i++)
2826                 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
2827                         mv_list[i].flags |=
2828                             CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2829
2830         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2831         if (buf_size > I40E_AQ_LARGE_BUF)
2832                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2833
2834         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2835                                        cmd_details);
2836
2837         return status;
2838 }
2839
2840 /**
2841  * i40e_aq_remove_macvlan
2842  * @hw: pointer to the hw struct
2843  * @seid: VSI for the mac address
2844  * @mv_list: list of macvlans to be removed
2845  * @count: length of the list
2846  * @cmd_details: pointer to command details structure or NULL
2847  *
2848  * Remove MAC/VLAN addresses from the HW filtering
2849  **/
2850 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2851                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
2852                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2853 {
2854         struct i40e_aq_desc desc;
2855         struct i40e_aqc_macvlan *cmd =
2856                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2857         enum i40e_status_code status;
2858         u16 buf_size;
2859
2860         if (count == 0 || !mv_list || !hw)
2861                 return I40E_ERR_PARAM;
2862
2863         buf_size = count * sizeof(*mv_list);
2864
2865         /* prep the rest of the request */
2866         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2867         cmd->num_addresses = CPU_TO_LE16(count);
2868         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2869         cmd->seid[1] = 0;
2870         cmd->seid[2] = 0;
2871
2872         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2873         if (buf_size > I40E_AQ_LARGE_BUF)
2874                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2875
2876         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2877                                        cmd_details);
2878
2879         return status;
2880 }
2881
2882 /**
2883  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
2884  * @hw: pointer to the hw struct
2885  * @opcode: AQ opcode for add or delete mirror rule
2886  * @sw_seid: Switch SEID (to which rule refers)
2887  * @rule_type: Rule Type (ingress/egress/VLAN)
2888  * @id: Destination VSI SEID or Rule ID
2889  * @count: length of the list
2890  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2891  * @cmd_details: pointer to command details structure or NULL
2892  * @rule_id: Rule ID returned from FW
2893  * @rule_used: Number of rules used in internal switch
2894  * @rule_free: Number of rules free in internal switch
2895  *
2896  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
2897  * VEBs/VEPA elements only
2898  **/
2899 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
2900                         u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
2901                         u16 count, __le16 *mr_list,
2902                         struct i40e_asq_cmd_details *cmd_details,
2903                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
2904 {
2905         struct i40e_aq_desc desc;
2906         struct i40e_aqc_add_delete_mirror_rule *cmd =
2907                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
2908         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
2909         (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
2910         enum i40e_status_code status;
2911         u16 buf_size;
2912
2913         buf_size = count * sizeof(*mr_list);
2914
2915         /* prep the rest of the request */
2916         i40e_fill_default_direct_cmd_desc(&desc, opcode);
2917         cmd->seid = CPU_TO_LE16(sw_seid);
2918         cmd->rule_type = CPU_TO_LE16(rule_type &
2919                                      I40E_AQC_MIRROR_RULE_TYPE_MASK);
2920         cmd->num_entries = CPU_TO_LE16(count);
2921         /* Dest VSI for add, rule_id for delete */
2922         cmd->destination = CPU_TO_LE16(id);
2923         if (mr_list) {
2924                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
2925                                                 I40E_AQ_FLAG_RD));
2926                 if (buf_size > I40E_AQ_LARGE_BUF)
2927                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2928         }
2929
2930         status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
2931                                        cmd_details);
2932         if (status == I40E_SUCCESS ||
2933             hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
2934                 if (rule_id)
2935                         *rule_id = LE16_TO_CPU(resp->rule_id);
2936                 if (rules_used)
2937                         *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
2938                 if (rules_free)
2939                         *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
2940         }
2941         return status;
2942 }
2943
2944 /**
2945  * i40e_aq_add_mirrorrule - add a mirror rule
2946  * @hw: pointer to the hw struct
2947  * @sw_seid: Switch SEID (to which rule refers)
2948  * @rule_type: Rule Type (ingress/egress/VLAN)
2949  * @dest_vsi: SEID of VSI to which packets will be mirrored
2950  * @count: length of the list
2951  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2952  * @cmd_details: pointer to command details structure or NULL
2953  * @rule_id: Rule ID returned from FW
2954  * @rule_used: Number of rules used in internal switch
2955  * @rule_free: Number of rules free in internal switch
2956  *
2957  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
2958  **/
2959 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2960                         u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
2961                         struct i40e_asq_cmd_details *cmd_details,
2962                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
2963 {
2964         if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
2965             rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
2966                 if (count == 0 || !mr_list)
2967                         return I40E_ERR_PARAM;
2968         }
2969
2970         return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
2971                                   rule_type, dest_vsi, count, mr_list,
2972                                   cmd_details, rule_id, rules_used, rules_free);
2973 }
2974
2975 /**
2976  * i40e_aq_delete_mirrorrule - delete a mirror rule
2977  * @hw: pointer to the hw struct
2978  * @sw_seid: Switch SEID (to which rule refers)
2979  * @rule_type: Rule Type (ingress/egress/VLAN)
2980  * @count: length of the list
2981  * @rule_id: Rule ID that is returned in the receive desc as part of
2982  *              add_mirrorrule.
2983  * @mr_list: list of mirrored VLAN IDs to be removed
2984  * @cmd_details: pointer to command details structure or NULL
2985  * @rule_used: Number of rules used in internal switch
2986  * @rule_free: Number of rules free in internal switch
2987  *
2988  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
2989  **/
2990 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2991                         u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
2992                         struct i40e_asq_cmd_details *cmd_details,
2993                         u16 *rules_used, u16 *rules_free)
2994 {
2995         /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
2996         if (rule_type != I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
2997                 if (!rule_id)
2998                         return I40E_ERR_PARAM;
2999         } else {
3000                 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3001                  * mirroring. For other rule_type, count and rule_type should
3002                  * not matter.
3003                  */
3004                 if (count == 0 || !mr_list)
3005                         return I40E_ERR_PARAM;
3006         }
3007
3008         return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3009                                   rule_type, rule_id, count, mr_list,
3010                                   cmd_details, NULL, rules_used, rules_free);
3011 }
3012
3013 /**
3014  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3015  * @hw: pointer to the hw struct
3016  * @seid: VSI for the vlan filters
3017  * @v_list: list of vlan filters to be added
3018  * @count: length of the list
3019  * @cmd_details: pointer to command details structure or NULL
3020  **/
3021 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3022                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3023                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3024 {
3025         struct i40e_aq_desc desc;
3026         struct i40e_aqc_macvlan *cmd =
3027                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3028         enum i40e_status_code status;
3029         u16 buf_size;
3030
3031         if (count == 0 || !v_list || !hw)
3032                 return I40E_ERR_PARAM;
3033
3034         buf_size = count * sizeof(*v_list);
3035
3036         /* prep the rest of the request */
3037         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3038         cmd->num_addresses = CPU_TO_LE16(count);
3039         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3040         cmd->seid[1] = 0;
3041         cmd->seid[2] = 0;
3042
3043         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3044         if (buf_size > I40E_AQ_LARGE_BUF)
3045                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3046
3047         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3048                                        cmd_details);
3049
3050         return status;
3051 }
3052
3053 /**
3054  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3055  * @hw: pointer to the hw struct
3056  * @seid: VSI for the vlan filters
3057  * @v_list: list of macvlans to be removed
3058  * @count: length of the list
3059  * @cmd_details: pointer to command details structure or NULL
3060  **/
3061 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3062                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3063                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3064 {
3065         struct i40e_aq_desc desc;
3066         struct i40e_aqc_macvlan *cmd =
3067                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3068         enum i40e_status_code status;
3069         u16 buf_size;
3070
3071         if (count == 0 || !v_list || !hw)
3072                 return I40E_ERR_PARAM;
3073
3074         buf_size = count * sizeof(*v_list);
3075
3076         /* prep the rest of the request */
3077         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3078         cmd->num_addresses = CPU_TO_LE16(count);
3079         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3080         cmd->seid[1] = 0;
3081         cmd->seid[2] = 0;
3082
3083         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3084         if (buf_size > I40E_AQ_LARGE_BUF)
3085                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3086
3087         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3088                                        cmd_details);
3089
3090         return status;
3091 }
3092
3093 /**
3094  * i40e_aq_send_msg_to_vf
3095  * @hw: pointer to the hardware structure
3096  * @vfid: vf id to send msg
3097  * @v_opcode: opcodes for VF-PF communication
3098  * @v_retval: return error code
3099  * @msg: pointer to the msg buffer
3100  * @msglen: msg length
3101  * @cmd_details: pointer to command details
3102  *
3103  * send msg to vf
3104  **/
3105 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3106                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3107                                 struct i40e_asq_cmd_details *cmd_details)
3108 {
3109         struct i40e_aq_desc desc;
3110         struct i40e_aqc_pf_vf_message *cmd =
3111                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3112         enum i40e_status_code status;
3113
3114         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3115         cmd->id = CPU_TO_LE32(vfid);
3116         desc.cookie_high = CPU_TO_LE32(v_opcode);
3117         desc.cookie_low = CPU_TO_LE32(v_retval);
3118         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3119         if (msglen) {
3120                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3121                                                 I40E_AQ_FLAG_RD));
3122                 if (msglen > I40E_AQ_LARGE_BUF)
3123                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3124                 desc.datalen = CPU_TO_LE16(msglen);
3125         }
3126         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3127
3128         return status;
3129 }
3130
3131 /**
3132  * i40e_aq_debug_read_register
3133  * @hw: pointer to the hw struct
3134  * @reg_addr: register address
3135  * @reg_val: register value
3136  * @cmd_details: pointer to command details structure or NULL
3137  *
3138  * Read the register using the admin queue commands
3139  **/
3140 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3141                                 u32 reg_addr, u64 *reg_val,
3142                                 struct i40e_asq_cmd_details *cmd_details)
3143 {
3144         struct i40e_aq_desc desc;
3145         struct i40e_aqc_debug_reg_read_write *cmd_resp =
3146                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3147         enum i40e_status_code status;
3148
3149         if (reg_val == NULL)
3150                 return I40E_ERR_PARAM;
3151
3152         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3153
3154         cmd_resp->address = CPU_TO_LE32(reg_addr);
3155
3156         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3157
3158         if (status == I40E_SUCCESS) {
3159                 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3160                            (u64)LE32_TO_CPU(cmd_resp->value_low);
3161         }
3162
3163         return status;
3164 }
3165
3166 /**
3167  * i40e_aq_debug_write_register
3168  * @hw: pointer to the hw struct
3169  * @reg_addr: register address
3170  * @reg_val: register value
3171  * @cmd_details: pointer to command details structure or NULL
3172  *
3173  * Write to a register using the admin queue commands
3174  **/
3175 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3176                                 u32 reg_addr, u64 reg_val,
3177                                 struct i40e_asq_cmd_details *cmd_details)
3178 {
3179         struct i40e_aq_desc desc;
3180         struct i40e_aqc_debug_reg_read_write *cmd =
3181                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3182         enum i40e_status_code status;
3183
3184         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3185
3186         cmd->address = CPU_TO_LE32(reg_addr);
3187         cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3188         cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3189
3190         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3191
3192         return status;
3193 }
3194
3195 /**
3196  * i40e_aq_get_hmc_resource_profile
3197  * @hw: pointer to the hw struct
3198  * @profile: type of profile the HMC is to be set as
3199  * @pe_vf_enabled_count: the number of PE enabled VFs the system has
3200  * @cmd_details: pointer to command details structure or NULL
3201  *
3202  * query the HMC profile of the device.
3203  **/
3204 enum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw,
3205                                 enum i40e_aq_hmc_profile *profile,
3206                                 u8 *pe_vf_enabled_count,
3207                                 struct i40e_asq_cmd_details *cmd_details)
3208 {
3209         struct i40e_aq_desc desc;
3210         struct i40e_aq_get_set_hmc_resource_profile *resp =
3211                 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
3212         enum i40e_status_code status;
3213
3214         i40e_fill_default_direct_cmd_desc(&desc,
3215                                 i40e_aqc_opc_query_hmc_resource_profile);
3216         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3217
3218         *profile = (enum i40e_aq_hmc_profile)(resp->pm_profile &
3219                    I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK);
3220         *pe_vf_enabled_count = resp->pe_vf_enabled &
3221                                I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK;
3222
3223         return status;
3224 }
3225
3226 /**
3227  * i40e_aq_set_hmc_resource_profile
3228  * @hw: pointer to the hw struct
3229  * @profile: type of profile the HMC is to be set as
3230  * @pe_vf_enabled_count: the number of PE enabled VFs the system has
3231  * @cmd_details: pointer to command details structure or NULL
3232  *
3233  * set the HMC profile of the device.
3234  **/
3235 enum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
3236                                 enum i40e_aq_hmc_profile profile,
3237                                 u8 pe_vf_enabled_count,
3238                                 struct i40e_asq_cmd_details *cmd_details)
3239 {
3240         struct i40e_aq_desc desc;
3241         struct i40e_aq_get_set_hmc_resource_profile *cmd =
3242                 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
3243         enum i40e_status_code status;
3244
3245         i40e_fill_default_direct_cmd_desc(&desc,
3246                                         i40e_aqc_opc_set_hmc_resource_profile);
3247
3248         cmd->pm_profile = (u8)profile;
3249         cmd->pe_vf_enabled = pe_vf_enabled_count;
3250
3251         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3252
3253         return status;
3254 }
3255
3256 /**
3257  * i40e_aq_request_resource
3258  * @hw: pointer to the hw struct
3259  * @resource: resource id
3260  * @access: access type
3261  * @sdp_number: resource number
3262  * @timeout: the maximum time in ms that the driver may hold the resource
3263  * @cmd_details: pointer to command details structure or NULL
3264  *
3265  * requests common resource using the admin queue commands
3266  **/
3267 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3268                                 enum i40e_aq_resources_ids resource,
3269                                 enum i40e_aq_resource_access_type access,
3270                                 u8 sdp_number, u64 *timeout,
3271                                 struct i40e_asq_cmd_details *cmd_details)
3272 {
3273         struct i40e_aq_desc desc;
3274         struct i40e_aqc_request_resource *cmd_resp =
3275                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3276         enum i40e_status_code status;
3277
3278         DEBUGFUNC("i40e_aq_request_resource");
3279
3280         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3281
3282         cmd_resp->resource_id = CPU_TO_LE16(resource);
3283         cmd_resp->access_type = CPU_TO_LE16(access);
3284         cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3285
3286         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3287         /* The completion specifies the maximum time in ms that the driver
3288          * may hold the resource in the Timeout field.
3289          * If the resource is held by someone else, the command completes with
3290          * busy return value and the timeout field indicates the maximum time
3291          * the current owner of the resource has to free it.
3292          */
3293         if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3294                 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3295
3296         return status;
3297 }
3298
3299 /**
3300  * i40e_aq_release_resource
3301  * @hw: pointer to the hw struct
3302  * @resource: resource id
3303  * @sdp_number: resource number
3304  * @cmd_details: pointer to command details structure or NULL
3305  *
3306  * release common resource using the admin queue commands
3307  **/
3308 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3309                                 enum i40e_aq_resources_ids resource,
3310                                 u8 sdp_number,
3311                                 struct i40e_asq_cmd_details *cmd_details)
3312 {
3313         struct i40e_aq_desc desc;
3314         struct i40e_aqc_request_resource *cmd =
3315                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3316         enum i40e_status_code status;
3317
3318         DEBUGFUNC("i40e_aq_release_resource");
3319
3320         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3321
3322         cmd->resource_id = CPU_TO_LE16(resource);
3323         cmd->resource_number = CPU_TO_LE32(sdp_number);
3324
3325         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3326
3327         return status;
3328 }
3329
3330 /**
3331  * i40e_aq_read_nvm
3332  * @hw: pointer to the hw struct
3333  * @module_pointer: module pointer location in words from the NVM beginning
3334  * @offset: byte offset from the module beginning
3335  * @length: length of the section to be read (in bytes from the offset)
3336  * @data: command buffer (size [bytes] = length)
3337  * @last_command: tells if this is the last command in a series
3338  * @cmd_details: pointer to command details structure or NULL
3339  *
3340  * Read the NVM using the admin queue commands
3341  **/
3342 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3343                                 u32 offset, u16 length, void *data,
3344                                 bool last_command,
3345                                 struct i40e_asq_cmd_details *cmd_details)
3346 {
3347         struct i40e_aq_desc desc;
3348         struct i40e_aqc_nvm_update *cmd =
3349                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3350         enum i40e_status_code status;
3351
3352         DEBUGFUNC("i40e_aq_read_nvm");
3353
3354         /* In offset the highest byte must be zeroed. */
3355         if (offset & 0xFF000000) {
3356                 status = I40E_ERR_PARAM;
3357                 goto i40e_aq_read_nvm_exit;
3358         }
3359
3360         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3361
3362         /* If this is the last command in a series, set the proper flag. */
3363         if (last_command)
3364                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3365         cmd->module_pointer = module_pointer;
3366         cmd->offset = CPU_TO_LE32(offset);
3367         cmd->length = CPU_TO_LE16(length);
3368
3369         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3370         if (length > I40E_AQ_LARGE_BUF)
3371                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3372
3373         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3374
3375 i40e_aq_read_nvm_exit:
3376         return status;
3377 }
3378
3379 /**
3380  * i40e_aq_read_nvm_config - read an nvm config block
3381  * @hw: pointer to the hw struct
3382  * @cmd_flags: NVM access admin command bits
3383  * @field_id: field or feature id
3384  * @data: buffer for result
3385  * @buf_size: buffer size
3386  * @element_count: pointer to count of elements read by FW
3387  * @cmd_details: pointer to command details structure or NULL
3388  **/
3389 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3390                                 u8 cmd_flags, u32 field_id, void *data,
3391                                 u16 buf_size, u16 *element_count,
3392                                 struct i40e_asq_cmd_details *cmd_details)
3393 {
3394         struct i40e_aq_desc desc;
3395         struct i40e_aqc_nvm_config_read *cmd =
3396                 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3397         enum i40e_status_code status;
3398
3399         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3400         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3401         if (buf_size > I40E_AQ_LARGE_BUF)
3402                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3403
3404         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3405         cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3406         if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3407                 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3408         else
3409                 cmd->element_id_msw = 0;
3410
3411         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3412
3413         if (!status && element_count)
3414                 *element_count = LE16_TO_CPU(cmd->element_count);
3415
3416         return status;
3417 }
3418
3419 /**
3420  * i40e_aq_write_nvm_config - write an nvm config block
3421  * @hw: pointer to the hw struct
3422  * @cmd_flags: NVM access admin command bits
3423  * @data: buffer for result
3424  * @buf_size: buffer size
3425  * @element_count: count of elements to be written
3426  * @cmd_details: pointer to command details structure or NULL
3427  **/
3428 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3429                                 u8 cmd_flags, void *data, u16 buf_size,
3430                                 u16 element_count,
3431                                 struct i40e_asq_cmd_details *cmd_details)
3432 {
3433         struct i40e_aq_desc desc;
3434         struct i40e_aqc_nvm_config_write *cmd =
3435                 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3436         enum i40e_status_code status;
3437
3438         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3439         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3440         if (buf_size > I40E_AQ_LARGE_BUF)
3441                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3442
3443         cmd->element_count = CPU_TO_LE16(element_count);
3444         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3445         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3446
3447         return status;
3448 }
3449
3450 /**
3451  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3452  * @hw: pointer to the hw struct
3453  * @cmd_details: pointer to command details structure or NULL
3454  **/
3455 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3456                                 void *buff, u16 buff_size,
3457                                 struct i40e_asq_cmd_details *cmd_details)
3458 {
3459         struct i40e_aq_desc desc;
3460         enum i40e_status_code status;
3461
3462         UNREFERENCED_2PARAMETER(buff, buff_size);
3463
3464         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3465         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3466         if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3467                 status = I40E_ERR_NOT_IMPLEMENTED;
3468
3469         return status;
3470 }
3471
3472 /**
3473  * i40e_aq_erase_nvm
3474  * @hw: pointer to the hw struct
3475  * @module_pointer: module pointer location in words from the NVM beginning
3476  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3477  * @length: length of the section to be erased (expressed in 4 KB)
3478  * @last_command: tells if this is the last command in a series
3479  * @cmd_details: pointer to command details structure or NULL
3480  *
3481  * Erase the NVM sector using the admin queue commands
3482  **/
3483 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3484                                 u32 offset, u16 length, bool last_command,
3485                                 struct i40e_asq_cmd_details *cmd_details)
3486 {
3487         struct i40e_aq_desc desc;
3488         struct i40e_aqc_nvm_update *cmd =
3489                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3490         enum i40e_status_code status;
3491
3492         DEBUGFUNC("i40e_aq_erase_nvm");
3493
3494         /* In offset the highest byte must be zeroed. */
3495         if (offset & 0xFF000000) {
3496                 status = I40E_ERR_PARAM;
3497                 goto i40e_aq_erase_nvm_exit;
3498         }
3499
3500         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3501
3502         /* If this is the last command in a series, set the proper flag. */
3503         if (last_command)
3504                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3505         cmd->module_pointer = module_pointer;
3506         cmd->offset = CPU_TO_LE32(offset);
3507         cmd->length = CPU_TO_LE16(length);
3508
3509         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3510
3511 i40e_aq_erase_nvm_exit:
3512         return status;
3513 }
3514
3515 /**
3516  * i40e_parse_discover_capabilities
3517  * @hw: pointer to the hw struct
3518  * @buff: pointer to a buffer containing device/function capability records
3519  * @cap_count: number of capability records in the list
3520  * @list_type_opc: type of capabilities list to parse
3521  *
3522  * Parse the device/function capabilities list.
3523  **/
3524 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3525                                      u32 cap_count,
3526                                      enum i40e_admin_queue_opc list_type_opc)
3527 {
3528         struct i40e_aqc_list_capabilities_element_resp *cap;
3529         u32 valid_functions, num_functions;
3530         u32 number, logical_id, phys_id;
3531         struct i40e_hw_capabilities *p;
3532         u8 major_rev;
3533         u32 i = 0;
3534         u16 id;
3535
3536         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3537
3538         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3539                 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3540         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3541                 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3542         else
3543                 return;
3544
3545         for (i = 0; i < cap_count; i++, cap++) {
3546                 id = LE16_TO_CPU(cap->id);
3547                 number = LE32_TO_CPU(cap->number);
3548                 logical_id = LE32_TO_CPU(cap->logical_id);
3549                 phys_id = LE32_TO_CPU(cap->phys_id);
3550                 major_rev = cap->major_rev;
3551
3552                 switch (id) {
3553                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3554                         p->switch_mode = number;
3555                         i40e_debug(hw, I40E_DEBUG_INIT,
3556                                    "HW Capability: Switch mode = %d\n",
3557                                    p->switch_mode);
3558                         break;
3559                 case I40E_AQ_CAP_ID_MNG_MODE:
3560                         p->management_mode = number;
3561                         i40e_debug(hw, I40E_DEBUG_INIT,
3562                                    "HW Capability: Management Mode = %d\n",
3563                                    p->management_mode);
3564                         break;
3565                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3566                         p->npar_enable = number;
3567                         i40e_debug(hw, I40E_DEBUG_INIT,
3568                                    "HW Capability: NPAR enable = %d\n",
3569                                    p->npar_enable);
3570                         break;
3571                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3572                         p->os2bmc = number;
3573                         i40e_debug(hw, I40E_DEBUG_INIT,
3574                                    "HW Capability: OS2BMC = %d\n", p->os2bmc);
3575                         break;
3576                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3577                         p->valid_functions = number;
3578                         i40e_debug(hw, I40E_DEBUG_INIT,
3579                                    "HW Capability: Valid Functions = %d\n",
3580                                    p->valid_functions);
3581                         break;
3582                 case I40E_AQ_CAP_ID_SRIOV:
3583                         if (number == 1)
3584                                 p->sr_iov_1_1 = true;
3585                         i40e_debug(hw, I40E_DEBUG_INIT,
3586                                    "HW Capability: SR-IOV = %d\n",
3587                                    p->sr_iov_1_1);
3588                         break;
3589                 case I40E_AQ_CAP_ID_VF:
3590                         p->num_vfs = number;
3591                         p->vf_base_id = logical_id;
3592                         i40e_debug(hw, I40E_DEBUG_INIT,
3593                                    "HW Capability: VF count = %d\n",
3594                                    p->num_vfs);
3595                         i40e_debug(hw, I40E_DEBUG_INIT,
3596                                    "HW Capability: VF base_id = %d\n",
3597                                    p->vf_base_id);
3598                         break;
3599                 case I40E_AQ_CAP_ID_VMDQ:
3600                         if (number == 1)
3601                                 p->vmdq = true;
3602                         i40e_debug(hw, I40E_DEBUG_INIT,
3603                                    "HW Capability: VMDQ = %d\n", p->vmdq);
3604                         break;
3605                 case I40E_AQ_CAP_ID_8021QBG:
3606                         if (number == 1)
3607                                 p->evb_802_1_qbg = true;
3608                         i40e_debug(hw, I40E_DEBUG_INIT,
3609                                    "HW Capability: 802.1Qbg = %d\n", number);
3610                         break;
3611                 case I40E_AQ_CAP_ID_8021QBR:
3612                         if (number == 1)
3613                                 p->evb_802_1_qbh = true;
3614                         i40e_debug(hw, I40E_DEBUG_INIT,
3615                                    "HW Capability: 802.1Qbh = %d\n", number);
3616                         break;
3617                 case I40E_AQ_CAP_ID_VSI:
3618                         p->num_vsis = number;
3619                         i40e_debug(hw, I40E_DEBUG_INIT,
3620                                    "HW Capability: VSI count = %d\n",
3621                                    p->num_vsis);
3622                         break;
3623                 case I40E_AQ_CAP_ID_DCB:
3624                         if (number == 1) {
3625                                 p->dcb = true;
3626                                 p->enabled_tcmap = logical_id;
3627                                 p->maxtc = phys_id;
3628                         }
3629                         i40e_debug(hw, I40E_DEBUG_INIT,
3630                                    "HW Capability: DCB = %d\n", p->dcb);
3631                         i40e_debug(hw, I40E_DEBUG_INIT,
3632                                    "HW Capability: TC Mapping = %d\n",
3633                                    logical_id);
3634                         i40e_debug(hw, I40E_DEBUG_INIT,
3635                                    "HW Capability: TC Max = %d\n", p->maxtc);
3636                         break;
3637                 case I40E_AQ_CAP_ID_FCOE:
3638                         if (number == 1)
3639                                 p->fcoe = true;
3640                         i40e_debug(hw, I40E_DEBUG_INIT,
3641                                    "HW Capability: FCOE = %d\n", p->fcoe);
3642                         break;
3643                 case I40E_AQ_CAP_ID_ISCSI:
3644                         if (number == 1)
3645                                 p->iscsi = true;
3646                         i40e_debug(hw, I40E_DEBUG_INIT,
3647                                    "HW Capability: iSCSI = %d\n", p->iscsi);
3648                         break;
3649                 case I40E_AQ_CAP_ID_RSS:
3650                         p->rss = true;
3651                         p->rss_table_size = number;
3652                         p->rss_table_entry_width = logical_id;
3653                         i40e_debug(hw, I40E_DEBUG_INIT,
3654                                    "HW Capability: RSS = %d\n", p->rss);
3655                         i40e_debug(hw, I40E_DEBUG_INIT,
3656                                    "HW Capability: RSS table size = %d\n",
3657                                    p->rss_table_size);
3658                         i40e_debug(hw, I40E_DEBUG_INIT,
3659                                    "HW Capability: RSS table width = %d\n",
3660                                    p->rss_table_entry_width);
3661                         break;
3662                 case I40E_AQ_CAP_ID_RXQ:
3663                         p->num_rx_qp = number;
3664                         p->base_queue = phys_id;
3665                         i40e_debug(hw, I40E_DEBUG_INIT,
3666                                    "HW Capability: Rx QP = %d\n", number);
3667                         i40e_debug(hw, I40E_DEBUG_INIT,
3668                                    "HW Capability: base_queue = %d\n",
3669                                    p->base_queue);
3670                         break;
3671                 case I40E_AQ_CAP_ID_TXQ:
3672                         p->num_tx_qp = number;
3673                         p->base_queue = phys_id;
3674                         i40e_debug(hw, I40E_DEBUG_INIT,
3675                                    "HW Capability: Tx QP = %d\n", number);
3676                         i40e_debug(hw, I40E_DEBUG_INIT,
3677                                    "HW Capability: base_queue = %d\n",
3678                                    p->base_queue);
3679                         break;
3680                 case I40E_AQ_CAP_ID_MSIX:
3681                         p->num_msix_vectors = number;
3682                         i40e_debug(hw, I40E_DEBUG_INIT,
3683                                    "HW Capability: MSIX vector count = %d\n",
3684                                    p->num_msix_vectors_vf);
3685                         break;
3686                 case I40E_AQ_CAP_ID_VF_MSIX:
3687                         p->num_msix_vectors_vf = number;
3688                         i40e_debug(hw, I40E_DEBUG_INIT,
3689                                    "HW Capability: MSIX VF vector count = %d\n",
3690                                    p->num_msix_vectors_vf);
3691                         break;
3692                 case I40E_AQ_CAP_ID_FLEX10:
3693                         if (major_rev == 1) {
3694                                 if (number == 1) {
3695                                         p->flex10_enable = true;
3696                                         p->flex10_capable = true;
3697                                 }
3698                         } else {
3699                                 /* Capability revision >= 2 */
3700                                 if (number & 1)
3701                                         p->flex10_enable = true;
3702                                 if (number & 2)
3703                                         p->flex10_capable = true;
3704                         }
3705                         p->flex10_mode = logical_id;
3706                         p->flex10_status = phys_id;
3707                         i40e_debug(hw, I40E_DEBUG_INIT,
3708                                    "HW Capability: Flex10 mode = %d\n",
3709                                    p->flex10_mode);
3710                         i40e_debug(hw, I40E_DEBUG_INIT,
3711                                    "HW Capability: Flex10 status = %d\n",
3712                                    p->flex10_status);
3713                         break;
3714                 case I40E_AQ_CAP_ID_CEM:
3715                         if (number == 1)
3716                                 p->mgmt_cem = true;
3717                         i40e_debug(hw, I40E_DEBUG_INIT,
3718                                    "HW Capability: CEM = %d\n", p->mgmt_cem);
3719                         break;
3720                 case I40E_AQ_CAP_ID_IWARP:
3721                         if (number == 1)
3722                                 p->iwarp = true;
3723                         i40e_debug(hw, I40E_DEBUG_INIT,
3724                                    "HW Capability: iWARP = %d\n", p->iwarp);
3725                         break;
3726                 case I40E_AQ_CAP_ID_LED:
3727                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3728                                 p->led[phys_id] = true;
3729                         i40e_debug(hw, I40E_DEBUG_INIT,
3730                                    "HW Capability: LED - PIN %d\n", phys_id);
3731                         break;
3732                 case I40E_AQ_CAP_ID_SDP:
3733                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3734                                 p->sdp[phys_id] = true;
3735                         i40e_debug(hw, I40E_DEBUG_INIT,
3736                                    "HW Capability: SDP - PIN %d\n", phys_id);
3737                         break;
3738                 case I40E_AQ_CAP_ID_MDIO:
3739                         if (number == 1) {
3740                                 p->mdio_port_num = phys_id;
3741                                 p->mdio_port_mode = logical_id;
3742                         }
3743                         i40e_debug(hw, I40E_DEBUG_INIT,
3744                                    "HW Capability: MDIO port number = %d\n",
3745                                    p->mdio_port_num);
3746                         i40e_debug(hw, I40E_DEBUG_INIT,
3747                                    "HW Capability: MDIO port mode = %d\n",
3748                                    p->mdio_port_mode);
3749                         break;
3750                 case I40E_AQ_CAP_ID_1588:
3751                         if (number == 1)
3752                                 p->ieee_1588 = true;
3753                         i40e_debug(hw, I40E_DEBUG_INIT,
3754                                    "HW Capability: IEEE 1588 = %d\n",
3755                                    p->ieee_1588);
3756                         break;
3757                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3758                         p->fd = true;
3759                         p->fd_filters_guaranteed = number;
3760                         p->fd_filters_best_effort = logical_id;
3761                         i40e_debug(hw, I40E_DEBUG_INIT,
3762                                    "HW Capability: Flow Director = 1\n");
3763                         i40e_debug(hw, I40E_DEBUG_INIT,
3764                                    "HW Capability: Guaranteed FD filters = %d\n",
3765                                    p->fd_filters_guaranteed);
3766                         break;
3767                 case I40E_AQ_CAP_ID_WSR_PROT:
3768                         p->wr_csr_prot = (u64)number;
3769                         p->wr_csr_prot |= (u64)logical_id << 32;
3770                         i40e_debug(hw, I40E_DEBUG_INIT,
3771                                    "HW Capability: wr_csr_prot = 0x%llX\n\n",
3772                                    (p->wr_csr_prot & 0xffff));
3773                         break;
3774 #ifdef X722_SUPPORT
3775                 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3776                         hw->num_wol_proxy_filters = (u16)number;
3777                         hw->wol_proxy_vsi_seid = (u16)logical_id;
3778                         p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3779                         if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3780                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3781                         else
3782                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3783                         p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3784                         p->proxy_support = p->proxy_support;
3785                         i40e_debug(hw, I40E_DEBUG_INIT,
3786                                    "HW Capability: WOL proxy filters = %d\n",
3787                                    hw->num_wol_proxy_filters);
3788                         break;
3789 #endif
3790                 default:
3791                         break;
3792                 }
3793         }
3794
3795         if (p->fcoe)
3796                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3797
3798 #ifdef I40E_FCOE_ENA
3799         /* Software override ensuring FCoE is disabled if npar or mfp
3800          * mode because it is not supported in these modes.
3801          */
3802         if (p->npar_enable || p->flex10_enable)
3803                 p->fcoe = false;
3804 #else
3805         /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3806         p->fcoe = false;
3807 #endif
3808
3809         /* count the enabled ports (aka the "not disabled" ports) */
3810         hw->num_ports = 0;
3811         for (i = 0; i < 4; i++) {
3812                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3813                 u64 port_cfg = 0;
3814
3815                 /* use AQ read to get the physical register offset instead
3816                  * of the port relative offset
3817                  */
3818                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3819                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3820                         hw->num_ports++;
3821         }
3822
3823         valid_functions = p->valid_functions;
3824         num_functions = 0;
3825         while (valid_functions) {
3826                 if (valid_functions & 1)
3827                         num_functions++;
3828                 valid_functions >>= 1;
3829         }
3830
3831         /* partition id is 1-based, and functions are evenly spread
3832          * across the ports as partitions
3833          */
3834         hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3835         hw->num_partitions = num_functions / hw->num_ports;
3836
3837         /* additional HW specific goodies that might
3838          * someday be HW version specific
3839          */
3840         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3841 }
3842
3843 /**
3844  * i40e_aq_discover_capabilities
3845  * @hw: pointer to the hw struct
3846  * @buff: a virtual buffer to hold the capabilities
3847  * @buff_size: Size of the virtual buffer
3848  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3849  * @list_type_opc: capabilities type to discover - pass in the command opcode
3850  * @cmd_details: pointer to command details structure or NULL
3851  *
3852  * Get the device capabilities descriptions from the firmware
3853  **/
3854 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3855                                 void *buff, u16 buff_size, u16 *data_size,
3856                                 enum i40e_admin_queue_opc list_type_opc,
3857                                 struct i40e_asq_cmd_details *cmd_details)
3858 {
3859         struct i40e_aqc_list_capabilites *cmd;
3860         struct i40e_aq_desc desc;
3861         enum i40e_status_code status = I40E_SUCCESS;
3862
3863         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3864
3865         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3866                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3867                 status = I40E_ERR_PARAM;
3868                 goto exit;
3869         }
3870
3871         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3872
3873         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3874         if (buff_size > I40E_AQ_LARGE_BUF)
3875                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3876
3877         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3878         *data_size = LE16_TO_CPU(desc.datalen);
3879
3880         if (status)
3881                 goto exit;
3882
3883         i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3884                                          list_type_opc);
3885
3886 exit:
3887         return status;
3888 }
3889
3890 /**
3891  * i40e_aq_update_nvm
3892  * @hw: pointer to the hw struct
3893  * @module_pointer: module pointer location in words from the NVM beginning
3894  * @offset: byte offset from the module beginning
3895  * @length: length of the section to be written (in bytes from the offset)
3896  * @data: command buffer (size [bytes] = length)
3897  * @last_command: tells if this is the last command in a series
3898  * @cmd_details: pointer to command details structure or NULL
3899  *
3900  * Update the NVM using the admin queue commands
3901  **/
3902 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3903                                 u32 offset, u16 length, void *data,
3904                                 bool last_command,
3905                                 struct i40e_asq_cmd_details *cmd_details)
3906 {
3907         struct i40e_aq_desc desc;
3908         struct i40e_aqc_nvm_update *cmd =
3909                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3910         enum i40e_status_code status;
3911
3912         DEBUGFUNC("i40e_aq_update_nvm");
3913
3914         /* In offset the highest byte must be zeroed. */
3915         if (offset & 0xFF000000) {
3916                 status = I40E_ERR_PARAM;
3917                 goto i40e_aq_update_nvm_exit;
3918         }
3919
3920         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3921
3922         /* If this is the last command in a series, set the proper flag. */
3923         if (last_command)
3924                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3925         cmd->module_pointer = module_pointer;
3926         cmd->offset = CPU_TO_LE32(offset);
3927         cmd->length = CPU_TO_LE16(length);
3928
3929         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3930         if (length > I40E_AQ_LARGE_BUF)
3931                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3932
3933         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3934
3935 i40e_aq_update_nvm_exit:
3936         return status;
3937 }
3938
3939 /**
3940  * i40e_aq_get_lldp_mib
3941  * @hw: pointer to the hw struct
3942  * @bridge_type: type of bridge requested
3943  * @mib_type: Local, Remote or both Local and Remote MIBs
3944  * @buff: pointer to a user supplied buffer to store the MIB block
3945  * @buff_size: size of the buffer (in bytes)
3946  * @local_len : length of the returned Local LLDP MIB
3947  * @remote_len: length of the returned Remote LLDP MIB
3948  * @cmd_details: pointer to command details structure or NULL
3949  *
3950  * Requests the complete LLDP MIB (entire packet).
3951  **/
3952 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3953                                 u8 mib_type, void *buff, u16 buff_size,
3954                                 u16 *local_len, u16 *remote_len,
3955                                 struct i40e_asq_cmd_details *cmd_details)
3956 {
3957         struct i40e_aq_desc desc;
3958         struct i40e_aqc_lldp_get_mib *cmd =
3959                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3960         struct i40e_aqc_lldp_get_mib *resp =
3961                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3962         enum i40e_status_code status;
3963
3964         if (buff_size == 0 || !buff)
3965                 return I40E_ERR_PARAM;
3966
3967         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3968         /* Indirect Command */
3969         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3970
3971         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3972         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3973                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3974
3975         desc.datalen = CPU_TO_LE16(buff_size);
3976
3977         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3978         if (buff_size > I40E_AQ_LARGE_BUF)
3979                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3980
3981         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3982         if (!status) {
3983                 if (local_len != NULL)
3984                         *local_len = LE16_TO_CPU(resp->local_len);
3985                 if (remote_len != NULL)
3986                         *remote_len = LE16_TO_CPU(resp->remote_len);
3987         }
3988
3989         return status;
3990 }
3991
3992  /**
3993  * i40e_aq_set_lldp_mib - Set the LLDP MIB
3994  * @hw: pointer to the hw struct
3995  * @mib_type: Local, Remote or both Local and Remote MIBs
3996  * @buff: pointer to a user supplied buffer to store the MIB block
3997  * @buff_size: size of the buffer (in bytes)
3998  * @cmd_details: pointer to command details structure or NULL
3999  *
4000  * Set the LLDP MIB.
4001  **/
4002 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4003                                 u8 mib_type, void *buff, u16 buff_size,
4004                                 struct i40e_asq_cmd_details *cmd_details)
4005 {
4006         struct i40e_aq_desc desc;
4007         struct i40e_aqc_lldp_set_local_mib *cmd =
4008                 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4009         enum i40e_status_code status;
4010
4011         if (buff_size == 0 || !buff)
4012                 return I40E_ERR_PARAM;
4013
4014         i40e_fill_default_direct_cmd_desc(&desc,
4015                                 i40e_aqc_opc_lldp_set_local_mib);
4016         /* Indirect Command */
4017         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4018         if (buff_size > I40E_AQ_LARGE_BUF)
4019                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4020         desc.datalen = CPU_TO_LE16(buff_size);
4021
4022         cmd->type = mib_type;
4023         cmd->length = CPU_TO_LE16(buff_size);
4024         cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4025         cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4026
4027         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4028         return status;
4029 }
4030
4031 /**
4032  * i40e_aq_cfg_lldp_mib_change_event
4033  * @hw: pointer to the hw struct
4034  * @enable_update: Enable or Disable event posting
4035  * @cmd_details: pointer to command details structure or NULL
4036  *
4037  * Enable or Disable posting of an event on ARQ when LLDP MIB
4038  * associated with the interface changes
4039  **/
4040 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4041                                 bool enable_update,
4042                                 struct i40e_asq_cmd_details *cmd_details)
4043 {
4044         struct i40e_aq_desc desc;
4045         struct i40e_aqc_lldp_update_mib *cmd =
4046                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4047         enum i40e_status_code status;
4048
4049         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4050
4051         if (!enable_update)
4052                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4053
4054         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4055
4056         return status;
4057 }
4058
4059 /**
4060  * i40e_aq_add_lldp_tlv
4061  * @hw: pointer to the hw struct
4062  * @bridge_type: type of bridge
4063  * @buff: buffer with TLV to add
4064  * @buff_size: length of the buffer
4065  * @tlv_len: length of the TLV to be added
4066  * @mib_len: length of the LLDP MIB returned in response
4067  * @cmd_details: pointer to command details structure or NULL
4068  *
4069  * Add the specified TLV to LLDP Local MIB for the given bridge type,
4070  * it is responsibility of the caller to make sure that the TLV is not
4071  * already present in the LLDPDU.
4072  * In return firmware will write the complete LLDP MIB with the newly
4073  * added TLV in the response buffer.
4074  **/
4075 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4076                                 void *buff, u16 buff_size, u16 tlv_len,
4077                                 u16 *mib_len,
4078                                 struct i40e_asq_cmd_details *cmd_details)
4079 {
4080         struct i40e_aq_desc desc;
4081         struct i40e_aqc_lldp_add_tlv *cmd =
4082                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4083         enum i40e_status_code status;
4084
4085         if (buff_size == 0 || !buff || tlv_len == 0)
4086                 return I40E_ERR_PARAM;
4087
4088         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4089
4090         /* Indirect Command */
4091         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4092         if (buff_size > I40E_AQ_LARGE_BUF)
4093                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4094         desc.datalen = CPU_TO_LE16(buff_size);
4095
4096         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4097                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4098         cmd->len = CPU_TO_LE16(tlv_len);
4099
4100         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4101         if (!status) {
4102                 if (mib_len != NULL)
4103                         *mib_len = LE16_TO_CPU(desc.datalen);
4104         }
4105
4106         return status;
4107 }
4108
4109 /**
4110  * i40e_aq_update_lldp_tlv
4111  * @hw: pointer to the hw struct
4112  * @bridge_type: type of bridge
4113  * @buff: buffer with TLV to update
4114  * @buff_size: size of the buffer holding original and updated TLVs
4115  * @old_len: Length of the Original TLV
4116  * @new_len: Length of the Updated TLV
4117  * @offset: offset of the updated TLV in the buff
4118  * @mib_len: length of the returned LLDP MIB
4119  * @cmd_details: pointer to command details structure or NULL
4120  *
4121  * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4122  * Firmware will place the complete LLDP MIB in response buffer with the
4123  * updated TLV.
4124  **/
4125 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4126                                 u8 bridge_type, void *buff, u16 buff_size,
4127                                 u16 old_len, u16 new_len, u16 offset,
4128                                 u16 *mib_len,
4129                                 struct i40e_asq_cmd_details *cmd_details)
4130 {
4131         struct i40e_aq_desc desc;
4132         struct i40e_aqc_lldp_update_tlv *cmd =
4133                 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4134         enum i40e_status_code status;
4135
4136         if (buff_size == 0 || !buff || offset == 0 ||
4137             old_len == 0 || new_len == 0)
4138                 return I40E_ERR_PARAM;
4139
4140         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4141
4142         /* Indirect Command */
4143         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4144         if (buff_size > I40E_AQ_LARGE_BUF)
4145                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4146         desc.datalen = CPU_TO_LE16(buff_size);
4147
4148         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4149                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4150         cmd->old_len = CPU_TO_LE16(old_len);
4151         cmd->new_offset = CPU_TO_LE16(offset);
4152         cmd->new_len = CPU_TO_LE16(new_len);
4153
4154         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4155         if (!status) {
4156                 if (mib_len != NULL)
4157                         *mib_len = LE16_TO_CPU(desc.datalen);
4158         }
4159
4160         return status;
4161 }
4162
4163 /**
4164  * i40e_aq_delete_lldp_tlv
4165  * @hw: pointer to the hw struct
4166  * @bridge_type: type of bridge
4167  * @buff: pointer to a user supplied buffer that has the TLV
4168  * @buff_size: length of the buffer
4169  * @tlv_len: length of the TLV to be deleted
4170  * @mib_len: length of the returned LLDP MIB
4171  * @cmd_details: pointer to command details structure or NULL
4172  *
4173  * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4174  * The firmware places the entire LLDP MIB in the response buffer.
4175  **/
4176 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4177                                 u8 bridge_type, void *buff, u16 buff_size,
4178                                 u16 tlv_len, u16 *mib_len,
4179                                 struct i40e_asq_cmd_details *cmd_details)
4180 {
4181         struct i40e_aq_desc desc;
4182         struct i40e_aqc_lldp_add_tlv *cmd =
4183                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4184         enum i40e_status_code status;
4185
4186         if (buff_size == 0 || !buff)
4187                 return I40E_ERR_PARAM;
4188
4189         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4190
4191         /* Indirect Command */
4192         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4193         if (buff_size > I40E_AQ_LARGE_BUF)
4194                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4195         desc.datalen = CPU_TO_LE16(buff_size);
4196         cmd->len = CPU_TO_LE16(tlv_len);
4197         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4198                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4199
4200         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4201         if (!status) {
4202                 if (mib_len != NULL)
4203                         *mib_len = LE16_TO_CPU(desc.datalen);
4204         }
4205
4206         return status;
4207 }
4208
4209 /**
4210  * i40e_aq_stop_lldp
4211  * @hw: pointer to the hw struct
4212  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4213  * @cmd_details: pointer to command details structure or NULL
4214  *
4215  * Stop or Shutdown the embedded LLDP Agent
4216  **/
4217 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4218                                 struct i40e_asq_cmd_details *cmd_details)
4219 {
4220         struct i40e_aq_desc desc;
4221         struct i40e_aqc_lldp_stop *cmd =
4222                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4223         enum i40e_status_code status;
4224
4225         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4226
4227         if (shutdown_agent)
4228                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4229
4230         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4231
4232         return status;
4233 }
4234
4235 /**
4236  * i40e_aq_start_lldp
4237  * @hw: pointer to the hw struct
4238  * @cmd_details: pointer to command details structure or NULL
4239  *
4240  * Start the embedded LLDP Agent on all ports.
4241  **/
4242 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4243                                 struct i40e_asq_cmd_details *cmd_details)
4244 {
4245         struct i40e_aq_desc desc;
4246         struct i40e_aqc_lldp_start *cmd =
4247                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4248         enum i40e_status_code status;
4249
4250         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4251
4252         cmd->command = I40E_AQ_LLDP_AGENT_START;
4253
4254         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4255
4256         return status;
4257 }
4258
4259 /**
4260  * i40e_aq_get_cee_dcb_config
4261  * @hw: pointer to the hw struct
4262  * @buff: response buffer that stores CEE operational configuration
4263  * @buff_size: size of the buffer passed
4264  * @cmd_details: pointer to command details structure or NULL
4265  *
4266  * Get CEE DCBX mode operational configuration from firmware
4267  **/
4268 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4269                                 void *buff, u16 buff_size,
4270                                 struct i40e_asq_cmd_details *cmd_details)
4271 {
4272         struct i40e_aq_desc desc;
4273         enum i40e_status_code status;
4274
4275         if (buff_size == 0 || !buff)
4276                 return I40E_ERR_PARAM;
4277
4278         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4279
4280         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4281         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4282                                        cmd_details);
4283
4284         return status;
4285 }
4286
4287 /**
4288  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4289  * @hw: pointer to the hw struct
4290  * @start_agent: True if DCBx Agent needs to be Started
4291  *                              False if DCBx Agent needs to be Stopped
4292  * @cmd_details: pointer to command details structure or NULL
4293  *
4294  * Start/Stop the embedded dcbx Agent
4295  **/
4296 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4297                                 bool start_agent,
4298                                 struct i40e_asq_cmd_details *cmd_details)
4299 {
4300         struct i40e_aq_desc desc;
4301         struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4302                 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4303                                 &desc.params.raw;
4304         enum i40e_status_code status;
4305
4306         i40e_fill_default_direct_cmd_desc(&desc,
4307                                 i40e_aqc_opc_lldp_stop_start_spec_agent);
4308
4309         if (start_agent)
4310                 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4311
4312         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4313
4314         return status;
4315 }
4316
4317 /**
4318  * i40e_aq_add_udp_tunnel
4319  * @hw: pointer to the hw struct
4320  * @udp_port: the UDP port to add
4321  * @header_len: length of the tunneling header length in DWords
4322  * @protocol_index: protocol index type
4323  * @filter_index: pointer to filter index
4324  * @cmd_details: pointer to command details structure or NULL
4325  **/
4326 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4327                                 u16 udp_port, u8 protocol_index,
4328                                 u8 *filter_index,
4329                                 struct i40e_asq_cmd_details *cmd_details)
4330 {
4331         struct i40e_aq_desc desc;
4332         struct i40e_aqc_add_udp_tunnel *cmd =
4333                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4334         struct i40e_aqc_del_udp_tunnel_completion *resp =
4335                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4336         enum i40e_status_code status;
4337
4338         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4339
4340         cmd->udp_port = CPU_TO_LE16(udp_port);
4341         cmd->protocol_type = protocol_index;
4342
4343         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4344
4345         if (!status && filter_index)
4346                 *filter_index = resp->index;
4347
4348         return status;
4349 }
4350
4351 /**
4352  * i40e_aq_del_udp_tunnel
4353  * @hw: pointer to the hw struct
4354  * @index: filter index
4355  * @cmd_details: pointer to command details structure or NULL
4356  **/
4357 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4358                                 struct i40e_asq_cmd_details *cmd_details)
4359 {
4360         struct i40e_aq_desc desc;
4361         struct i40e_aqc_remove_udp_tunnel *cmd =
4362                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4363         enum i40e_status_code status;
4364
4365         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4366
4367         cmd->index = index;
4368
4369         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4370
4371         return status;
4372 }
4373
4374 /**
4375  * i40e_aq_get_switch_resource_alloc (0x0204)
4376  * @hw: pointer to the hw struct
4377  * @num_entries: pointer to u8 to store the number of resource entries returned
4378  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
4379  *        to store the resource information for all resource types.  Each
4380  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
4381  * @count: size, in bytes, of the buffer provided
4382  * @cmd_details: pointer to command details structure or NULL
4383  *
4384  * Query the resources allocated to a function.
4385  **/
4386 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4387                         u8 *num_entries,
4388                         struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4389                         u16 count,
4390                         struct i40e_asq_cmd_details *cmd_details)
4391 {
4392         struct i40e_aq_desc desc;
4393         struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4394                 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4395         enum i40e_status_code status;
4396         u16 length = count * sizeof(*buf);
4397
4398         i40e_fill_default_direct_cmd_desc(&desc,
4399                                         i40e_aqc_opc_get_switch_resource_alloc);
4400
4401         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4402         if (length > I40E_AQ_LARGE_BUF)
4403                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4404
4405         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4406
4407         if (!status && num_entries)
4408                 *num_entries = cmd_resp->num_entries;
4409
4410         return status;
4411 }
4412
4413 /**
4414  * i40e_aq_delete_element - Delete switch element
4415  * @hw: pointer to the hw struct
4416  * @seid: the SEID to delete from the switch
4417  * @cmd_details: pointer to command details structure or NULL
4418  *
4419  * This deletes a switch element from the switch.
4420  **/
4421 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4422                                 struct i40e_asq_cmd_details *cmd_details)
4423 {
4424         struct i40e_aq_desc desc;
4425         struct i40e_aqc_switch_seid *cmd =
4426                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4427         enum i40e_status_code status;
4428
4429         if (seid == 0)
4430                 return I40E_ERR_PARAM;
4431
4432         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4433
4434         cmd->seid = CPU_TO_LE16(seid);
4435
4436         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4437
4438         return status;
4439 }
4440
4441 /**
4442  * i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4443  * @hw: pointer to the hw struct
4444  * @flags: component flags
4445  * @mac_seid: uplink seid (MAC SEID)
4446  * @vsi_seid: connected vsi seid
4447  * @ret_seid: seid of create pv component
4448  *
4449  * This instantiates an i40e port virtualizer with specified flags.
4450  * Depending on specified flags the port virtualizer can act as a
4451  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4452  */
4453 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4454                                        u16 mac_seid, u16 vsi_seid,
4455                                        u16 *ret_seid)
4456 {
4457         struct i40e_aq_desc desc;
4458         struct i40e_aqc_add_update_pv *cmd =
4459                 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4460         struct i40e_aqc_add_update_pv_completion *resp =
4461                 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4462         enum i40e_status_code status;
4463
4464         if (vsi_seid == 0)
4465                 return I40E_ERR_PARAM;
4466
4467         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4468         cmd->command_flags = CPU_TO_LE16(flags);
4469         cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4470         cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4471
4472         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4473         if (!status && ret_seid)
4474                 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4475
4476         return status;
4477 }
4478
4479 /**
4480  * i40e_aq_add_tag - Add an S/E-tag
4481  * @hw: pointer to the hw struct
4482  * @direct_to_queue: should s-tag direct flow to a specific queue
4483  * @vsi_seid: VSI SEID to use this tag
4484  * @tag: value of the tag
4485  * @queue_num: queue number, only valid is direct_to_queue is true
4486  * @tags_used: return value, number of tags in use by this PF
4487  * @tags_free: return value, number of unallocated tags
4488  * @cmd_details: pointer to command details structure or NULL
4489  *
4490  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4491  * the number of tags allocated by the PF, and the number of unallocated
4492  * tags available.
4493  **/
4494 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4495                                 u16 vsi_seid, u16 tag, u16 queue_num,
4496                                 u16 *tags_used, u16 *tags_free,
4497                                 struct i40e_asq_cmd_details *cmd_details)
4498 {
4499         struct i40e_aq_desc desc;
4500         struct i40e_aqc_add_tag *cmd =
4501                 (struct i40e_aqc_add_tag *)&desc.params.raw;
4502         struct i40e_aqc_add_remove_tag_completion *resp =
4503                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4504         enum i40e_status_code status;
4505
4506         if (vsi_seid == 0)
4507                 return I40E_ERR_PARAM;
4508
4509         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4510
4511         cmd->seid = CPU_TO_LE16(vsi_seid);
4512         cmd->tag = CPU_TO_LE16(tag);
4513         if (direct_to_queue) {
4514                 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4515                 cmd->queue_number = CPU_TO_LE16(queue_num);
4516         }
4517
4518         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4519
4520         if (!status) {
4521                 if (tags_used != NULL)
4522                         *tags_used = LE16_TO_CPU(resp->tags_used);
4523                 if (tags_free != NULL)
4524                         *tags_free = LE16_TO_CPU(resp->tags_free);
4525         }
4526
4527         return status;
4528 }
4529
4530 /**
4531  * i40e_aq_remove_tag - Remove an S- or E-tag
4532  * @hw: pointer to the hw struct
4533  * @vsi_seid: VSI SEID this tag is associated with
4534  * @tag: value of the S-tag to delete
4535  * @tags_used: return value, number of tags in use by this PF
4536  * @tags_free: return value, number of unallocated tags
4537  * @cmd_details: pointer to command details structure or NULL
4538  *
4539  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4540  * the number of tags allocated by the PF, and the number of unallocated
4541  * tags available.
4542  **/
4543 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4544                                 u16 tag, u16 *tags_used, u16 *tags_free,
4545                                 struct i40e_asq_cmd_details *cmd_details)
4546 {
4547         struct i40e_aq_desc desc;
4548         struct i40e_aqc_remove_tag *cmd =
4549                 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4550         struct i40e_aqc_add_remove_tag_completion *resp =
4551                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4552         enum i40e_status_code status;
4553
4554         if (vsi_seid == 0)
4555                 return I40E_ERR_PARAM;
4556
4557         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4558
4559         cmd->seid = CPU_TO_LE16(vsi_seid);
4560         cmd->tag = CPU_TO_LE16(tag);
4561
4562         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4563
4564         if (!status) {
4565                 if (tags_used != NULL)
4566                         *tags_used = LE16_TO_CPU(resp->tags_used);
4567                 if (tags_free != NULL)
4568                         *tags_free = LE16_TO_CPU(resp->tags_free);
4569         }
4570
4571         return status;
4572 }
4573
4574 /**
4575  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4576  * @hw: pointer to the hw struct
4577  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4578  * @etag: value of E-tag to add
4579  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4580  * @buf: address of indirect buffer
4581  * @tags_used: return value, number of E-tags in use by this port
4582  * @tags_free: return value, number of unallocated M-tags
4583  * @cmd_details: pointer to command details structure or NULL
4584  *
4585  * This associates a multicast E-tag to a port virtualizer.  It will return
4586  * the number of tags allocated by the PF, and the number of unallocated
4587  * tags available.
4588  *
4589  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4590  * num_tags_in_buf long.
4591  **/
4592 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4593                                 u16 etag, u8 num_tags_in_buf, void *buf,
4594                                 u16 *tags_used, u16 *tags_free,
4595                                 struct i40e_asq_cmd_details *cmd_details)
4596 {
4597         struct i40e_aq_desc desc;
4598         struct i40e_aqc_add_remove_mcast_etag *cmd =
4599                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4600         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4601            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4602         enum i40e_status_code status;
4603         u16 length = sizeof(u16) * num_tags_in_buf;
4604
4605         if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4606                 return I40E_ERR_PARAM;
4607
4608         i40e_fill_default_direct_cmd_desc(&desc,
4609                                           i40e_aqc_opc_add_multicast_etag);
4610
4611         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4612         cmd->etag = CPU_TO_LE16(etag);
4613         cmd->num_unicast_etags = num_tags_in_buf;
4614
4615         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4616         if (length > I40E_AQ_LARGE_BUF)
4617                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4618
4619         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4620
4621         if (!status) {
4622                 if (tags_used != NULL)
4623                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4624                 if (tags_free != NULL)
4625                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4626         }
4627
4628         return status;
4629 }
4630
4631 /**
4632  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4633  * @hw: pointer to the hw struct
4634  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4635  * @etag: value of the E-tag to remove
4636  * @tags_used: return value, number of tags in use by this port
4637  * @tags_free: return value, number of unallocated tags
4638  * @cmd_details: pointer to command details structure or NULL
4639  *
4640  * This deletes an E-tag from the port virtualizer.  It will return
4641  * the number of tags allocated by the port, and the number of unallocated
4642  * tags available.
4643  **/
4644 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4645                                 u16 etag, u16 *tags_used, u16 *tags_free,
4646                                 struct i40e_asq_cmd_details *cmd_details)
4647 {
4648         struct i40e_aq_desc desc;
4649         struct i40e_aqc_add_remove_mcast_etag *cmd =
4650                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4651         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4652            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4653         enum i40e_status_code status;
4654
4655
4656         if (pv_seid == 0)
4657                 return I40E_ERR_PARAM;
4658
4659         i40e_fill_default_direct_cmd_desc(&desc,
4660                                           i40e_aqc_opc_remove_multicast_etag);
4661
4662         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4663         cmd->etag = CPU_TO_LE16(etag);
4664
4665         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4666
4667         if (!status) {
4668                 if (tags_used != NULL)
4669                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4670                 if (tags_free != NULL)
4671                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4672         }
4673
4674         return status;
4675 }
4676
4677 /**
4678  * i40e_aq_update_tag - Update an S/E-tag
4679  * @hw: pointer to the hw struct
4680  * @vsi_seid: VSI SEID using this S-tag
4681  * @old_tag: old tag value
4682  * @new_tag: new tag value
4683  * @tags_used: return value, number of tags in use by this PF
4684  * @tags_free: return value, number of unallocated tags
4685  * @cmd_details: pointer to command details structure or NULL
4686  *
4687  * This updates the value of the tag currently attached to this VSI
4688  * in the switch complex.  It will return the number of tags allocated
4689  * by the PF, and the number of unallocated tags available.
4690  **/
4691 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4692                                 u16 old_tag, u16 new_tag, u16 *tags_used,
4693                                 u16 *tags_free,
4694                                 struct i40e_asq_cmd_details *cmd_details)
4695 {
4696         struct i40e_aq_desc desc;
4697         struct i40e_aqc_update_tag *cmd =
4698                 (struct i40e_aqc_update_tag *)&desc.params.raw;
4699         struct i40e_aqc_update_tag_completion *resp =
4700                 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4701         enum i40e_status_code status;
4702
4703         if (vsi_seid == 0)
4704                 return I40E_ERR_PARAM;
4705
4706         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4707
4708         cmd->seid = CPU_TO_LE16(vsi_seid);
4709         cmd->old_tag = CPU_TO_LE16(old_tag);
4710         cmd->new_tag = CPU_TO_LE16(new_tag);
4711
4712         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4713
4714         if (!status) {
4715                 if (tags_used != NULL)
4716                         *tags_used = LE16_TO_CPU(resp->tags_used);
4717                 if (tags_free != NULL)
4718                         *tags_free = LE16_TO_CPU(resp->tags_free);
4719         }
4720
4721         return status;
4722 }
4723
4724 /**
4725  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4726  * @hw: pointer to the hw struct
4727  * @tcmap: TC map for request/release any ignore PFC condition
4728  * @request: request or release ignore PFC condition
4729  * @tcmap_ret: return TCs for which PFC is currently ignored
4730  * @cmd_details: pointer to command details structure or NULL
4731  *
4732  * This sends out request/release to ignore PFC condition for a TC.
4733  * It will return the TCs for which PFC is currently ignored.
4734  **/
4735 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4736                                 bool request, u8 *tcmap_ret,
4737                                 struct i40e_asq_cmd_details *cmd_details)
4738 {
4739         struct i40e_aq_desc desc;
4740         struct i40e_aqc_pfc_ignore *cmd_resp =
4741                 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4742         enum i40e_status_code status;
4743
4744         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4745
4746         if (request)
4747                 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4748
4749         cmd_resp->tc_bitmap = tcmap;
4750
4751         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4752
4753         if (!status) {
4754                 if (tcmap_ret != NULL)
4755                         *tcmap_ret = cmd_resp->tc_bitmap;
4756         }
4757
4758         return status;
4759 }
4760
4761 /**
4762  * i40e_aq_dcb_updated - DCB Updated Command
4763  * @hw: pointer to the hw struct
4764  * @cmd_details: pointer to command details structure or NULL
4765  *
4766  * When LLDP is handled in PF this command is used by the PF
4767  * to notify EMP that a DCB setting is modified.
4768  * When LLDP is handled in EMP this command is used by the PF
4769  * to notify EMP whenever one of the following parameters get
4770  * modified:
4771  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4772  *   - PCIRTT in PRTDCB_GENC.PCIRTT
4773  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4774  * EMP will return when the shared RPB settings have been
4775  * recomputed and modified. The retval field in the descriptor
4776  * will be set to 0 when RPB is modified.
4777  **/
4778 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4779                                 struct i40e_asq_cmd_details *cmd_details)
4780 {
4781         struct i40e_aq_desc desc;
4782         enum i40e_status_code status;
4783
4784         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4785
4786         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4787
4788         return status;
4789 }
4790
4791 /**
4792  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4793  * @hw: pointer to the hw struct
4794  * @seid: defines the SEID of the switch for which the stats are requested
4795  * @vlan_id: the VLAN ID for which the statistics are requested
4796  * @stat_index: index of the statistics counters block assigned to this VLAN
4797  * @cmd_details: pointer to command details structure or NULL
4798  *
4799  * XL710 supports 128 smonVlanStats counters.This command is used to
4800  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4801  * switch.
4802  **/
4803 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4804                                 u16 vlan_id, u16 *stat_index,
4805                                 struct i40e_asq_cmd_details *cmd_details)
4806 {
4807         struct i40e_aq_desc desc;
4808         struct i40e_aqc_add_remove_statistics *cmd_resp =
4809                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4810         enum i40e_status_code status;
4811
4812         if ((seid == 0) || (stat_index == NULL))
4813                 return I40E_ERR_PARAM;
4814
4815         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4816
4817         cmd_resp->seid = CPU_TO_LE16(seid);
4818         cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4819
4820         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4821
4822         if (!status && stat_index)
4823                 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4824
4825         return status;
4826 }
4827
4828 /**
4829  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4830  * @hw: pointer to the hw struct
4831  * @seid: defines the SEID of the switch for which the stats are requested
4832  * @vlan_id: the VLAN ID for which the statistics are requested
4833  * @stat_index: index of the statistics counters block assigned to this VLAN
4834  * @cmd_details: pointer to command details structure or NULL
4835  *
4836  * XL710 supports 128 smonVlanStats counters.This command is used to
4837  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4838  * switch.
4839  **/
4840 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4841                                 u16 vlan_id, u16 stat_index,
4842                                 struct i40e_asq_cmd_details *cmd_details)
4843 {
4844         struct i40e_aq_desc desc;
4845         struct i40e_aqc_add_remove_statistics *cmd =
4846                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4847         enum i40e_status_code status;
4848
4849         if (seid == 0)
4850                 return I40E_ERR_PARAM;
4851
4852         i40e_fill_default_direct_cmd_desc(&desc,
4853                                           i40e_aqc_opc_remove_statistics);
4854
4855         cmd->seid = CPU_TO_LE16(seid);
4856         cmd->vlan  = CPU_TO_LE16(vlan_id);
4857         cmd->stat_index = CPU_TO_LE16(stat_index);
4858
4859         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4860
4861         return status;
4862 }
4863
4864 /**
4865  * i40e_aq_set_port_parameters - set physical port parameters.
4866  * @hw: pointer to the hw struct
4867  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4868  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4869  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4870  * @double_vlan: if set double VLAN is enabled
4871  * @cmd_details: pointer to command details structure or NULL
4872  **/
4873 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4874                                 u16 bad_frame_vsi, bool save_bad_pac,
4875                                 bool pad_short_pac, bool double_vlan,
4876                                 struct i40e_asq_cmd_details *cmd_details)
4877 {
4878         struct i40e_aqc_set_port_parameters *cmd;
4879         enum i40e_status_code status;
4880         struct i40e_aq_desc desc;
4881         u16 command_flags = 0;
4882
4883         cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4884
4885         i40e_fill_default_direct_cmd_desc(&desc,
4886                                           i40e_aqc_opc_set_port_parameters);
4887
4888         cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4889         if (save_bad_pac)
4890                 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4891         if (pad_short_pac)
4892                 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4893         if (double_vlan)
4894                 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4895         cmd->command_flags = CPU_TO_LE16(command_flags);
4896
4897         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4898
4899         return status;
4900 }
4901
4902 /**
4903  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
4904  * @hw: pointer to the hw struct
4905  * @seid: seid for the physical port/switching component/vsi
4906  * @buff: Indirect buffer to hold data parameters and response
4907  * @buff_size: Indirect buffer size
4908  * @opcode: Tx scheduler AQ command opcode
4909  * @cmd_details: pointer to command details structure or NULL
4910  *
4911  * Generic command handler for Tx scheduler AQ commands
4912  **/
4913 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
4914                                 void *buff, u16 buff_size,
4915                                  enum i40e_admin_queue_opc opcode,
4916                                 struct i40e_asq_cmd_details *cmd_details)
4917 {
4918         struct i40e_aq_desc desc;
4919         struct i40e_aqc_tx_sched_ind *cmd =
4920                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4921         enum i40e_status_code status;
4922         bool cmd_param_flag = false;
4923
4924         switch (opcode) {
4925         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
4926         case i40e_aqc_opc_configure_vsi_tc_bw:
4927         case i40e_aqc_opc_enable_switching_comp_ets:
4928         case i40e_aqc_opc_modify_switching_comp_ets:
4929         case i40e_aqc_opc_disable_switching_comp_ets:
4930         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
4931         case i40e_aqc_opc_configure_switching_comp_bw_config:
4932                 cmd_param_flag = true;
4933                 break;
4934         case i40e_aqc_opc_query_vsi_bw_config:
4935         case i40e_aqc_opc_query_vsi_ets_sla_config:
4936         case i40e_aqc_opc_query_switching_comp_ets_config:
4937         case i40e_aqc_opc_query_port_ets_config:
4938         case i40e_aqc_opc_query_switching_comp_bw_config:
4939                 cmd_param_flag = false;
4940                 break;
4941         default:
4942                 return I40E_ERR_PARAM;
4943         }
4944
4945         i40e_fill_default_direct_cmd_desc(&desc, opcode);
4946
4947         /* Indirect command */
4948         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4949         if (cmd_param_flag)
4950                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4951         if (buff_size > I40E_AQ_LARGE_BUF)
4952                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4953
4954         desc.datalen = CPU_TO_LE16(buff_size);
4955
4956         cmd->vsi_seid = CPU_TO_LE16(seid);
4957
4958         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4959
4960         return status;
4961 }
4962
4963 /**
4964  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
4965  * @hw: pointer to the hw struct
4966  * @seid: VSI seid
4967  * @credit: BW limit credits (0 = disabled)
4968  * @max_credit: Max BW limit credits
4969  * @cmd_details: pointer to command details structure or NULL
4970  **/
4971 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
4972                                 u16 seid, u16 credit, u8 max_credit,
4973                                 struct i40e_asq_cmd_details *cmd_details)
4974 {
4975         struct i40e_aq_desc desc;
4976         struct i40e_aqc_configure_vsi_bw_limit *cmd =
4977                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
4978         enum i40e_status_code status;
4979
4980         i40e_fill_default_direct_cmd_desc(&desc,
4981                                           i40e_aqc_opc_configure_vsi_bw_limit);
4982
4983         cmd->vsi_seid = CPU_TO_LE16(seid);
4984         cmd->credit = CPU_TO_LE16(credit);
4985         cmd->max_credit = max_credit;
4986
4987         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4988
4989         return status;
4990 }
4991
4992 /**
4993  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
4994  * @hw: pointer to the hw struct
4995  * @seid: switching component seid
4996  * @credit: BW limit credits (0 = disabled)
4997  * @max_bw: Max BW limit credits
4998  * @cmd_details: pointer to command details structure or NULL
4999  **/
5000 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5001                                 u16 seid, u16 credit, u8 max_bw,
5002                                 struct i40e_asq_cmd_details *cmd_details)
5003 {
5004         struct i40e_aq_desc desc;
5005         struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5006           (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5007         enum i40e_status_code status;
5008
5009         i40e_fill_default_direct_cmd_desc(&desc,
5010                                 i40e_aqc_opc_configure_switching_comp_bw_limit);
5011
5012         cmd->seid = CPU_TO_LE16(seid);
5013         cmd->credit = CPU_TO_LE16(credit);
5014         cmd->max_bw = max_bw;
5015
5016         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5017
5018         return status;
5019 }
5020
5021 /**
5022  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5023  * @hw: pointer to the hw struct
5024  * @seid: VSI seid
5025  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5026  * @cmd_details: pointer to command details structure or NULL
5027  **/
5028 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5029                         u16 seid,
5030                         struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5031                         struct i40e_asq_cmd_details *cmd_details)
5032 {
5033         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5034                                     i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5035                                     cmd_details);
5036 }
5037
5038 /**
5039  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5040  * @hw: pointer to the hw struct
5041  * @seid: VSI seid
5042  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5043  * @cmd_details: pointer to command details structure or NULL
5044  **/
5045 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5046                         u16 seid,
5047                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5048                         struct i40e_asq_cmd_details *cmd_details)
5049 {
5050         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5051                                     i40e_aqc_opc_configure_vsi_tc_bw,
5052                                     cmd_details);
5053 }
5054
5055 /**
5056  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5057  * @hw: pointer to the hw struct
5058  * @seid: seid of the switching component connected to Physical Port
5059  * @ets_data: Buffer holding ETS parameters
5060  * @cmd_details: pointer to command details structure or NULL
5061  **/
5062 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5063                 u16 seid,
5064                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5065                 enum i40e_admin_queue_opc opcode,
5066                 struct i40e_asq_cmd_details *cmd_details)
5067 {
5068         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5069                                     sizeof(*ets_data), opcode, cmd_details);
5070 }
5071
5072 /**
5073  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5074  * @hw: pointer to the hw struct
5075  * @seid: seid of the switching component
5076  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5077  * @cmd_details: pointer to command details structure or NULL
5078  **/
5079 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5080         u16 seid,
5081         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5082         struct i40e_asq_cmd_details *cmd_details)
5083 {
5084         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5085                             i40e_aqc_opc_configure_switching_comp_bw_config,
5086                             cmd_details);
5087 }
5088
5089 /**
5090  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5091  * @hw: pointer to the hw struct
5092  * @seid: seid of the switching component
5093  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5094  * @cmd_details: pointer to command details structure or NULL
5095  **/
5096 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5097         struct i40e_hw *hw, u16 seid,
5098         struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5099         struct i40e_asq_cmd_details *cmd_details)
5100 {
5101         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5102                             i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5103                             cmd_details);
5104 }
5105
5106 /**
5107  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5108  * @hw: pointer to the hw struct
5109  * @seid: seid of the VSI
5110  * @bw_data: Buffer to hold VSI BW configuration
5111  * @cmd_details: pointer to command details structure or NULL
5112  **/
5113 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5114                         u16 seid,
5115                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5116                         struct i40e_asq_cmd_details *cmd_details)
5117 {
5118         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5119                                     i40e_aqc_opc_query_vsi_bw_config,
5120                                     cmd_details);
5121 }
5122
5123 /**
5124  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5125  * @hw: pointer to the hw struct
5126  * @seid: seid of the VSI
5127  * @bw_data: Buffer to hold VSI BW configuration per TC
5128  * @cmd_details: pointer to command details structure or NULL
5129  **/
5130 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5131                         u16 seid,
5132                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5133                         struct i40e_asq_cmd_details *cmd_details)
5134 {
5135         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5136                                     i40e_aqc_opc_query_vsi_ets_sla_config,
5137                                     cmd_details);
5138 }
5139
5140 /**
5141  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5142  * @hw: pointer to the hw struct
5143  * @seid: seid of the switching component
5144  * @bw_data: Buffer to hold switching component's per TC BW config
5145  * @cmd_details: pointer to command details structure or NULL
5146  **/
5147 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5148                 u16 seid,
5149                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5150                 struct i40e_asq_cmd_details *cmd_details)
5151 {
5152         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5153                                    i40e_aqc_opc_query_switching_comp_ets_config,
5154                                    cmd_details);
5155 }
5156
5157 /**
5158  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5159  * @hw: pointer to the hw struct
5160  * @seid: seid of the VSI or switching component connected to Physical Port
5161  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5162  * @cmd_details: pointer to command details structure or NULL
5163  **/
5164 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5165                         u16 seid,
5166                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
5167                         struct i40e_asq_cmd_details *cmd_details)
5168 {
5169         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5170                                     i40e_aqc_opc_query_port_ets_config,
5171                                     cmd_details);
5172 }
5173
5174 /**
5175  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5176  * @hw: pointer to the hw struct
5177  * @seid: seid of the switching component
5178  * @bw_data: Buffer to hold switching component's BW configuration
5179  * @cmd_details: pointer to command details structure or NULL
5180  **/
5181 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5182                 u16 seid,
5183                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5184                 struct i40e_asq_cmd_details *cmd_details)
5185 {
5186         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5187                                     i40e_aqc_opc_query_switching_comp_bw_config,
5188                                     cmd_details);
5189 }
5190
5191 /**
5192  * i40e_validate_filter_settings
5193  * @hw: pointer to the hardware structure
5194  * @settings: Filter control settings
5195  *
5196  * Check and validate the filter control settings passed.
5197  * The function checks for the valid filter/context sizes being
5198  * passed for FCoE and PE.
5199  *
5200  * Returns I40E_SUCCESS if the values passed are valid and within
5201  * range else returns an error.
5202  **/
5203 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5204                                 struct i40e_filter_control_settings *settings)
5205 {
5206         u32 fcoe_cntx_size, fcoe_filt_size;
5207         u32 pe_cntx_size, pe_filt_size;
5208         u32 fcoe_fmax;
5209
5210         u32 val;
5211
5212         /* Validate FCoE settings passed */
5213         switch (settings->fcoe_filt_num) {
5214         case I40E_HASH_FILTER_SIZE_1K:
5215         case I40E_HASH_FILTER_SIZE_2K:
5216         case I40E_HASH_FILTER_SIZE_4K:
5217         case I40E_HASH_FILTER_SIZE_8K:
5218         case I40E_HASH_FILTER_SIZE_16K:
5219         case I40E_HASH_FILTER_SIZE_32K:
5220                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5221                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5222                 break;
5223         default:
5224                 return I40E_ERR_PARAM;
5225         }
5226
5227         switch (settings->fcoe_cntx_num) {
5228         case I40E_DMA_CNTX_SIZE_512:
5229         case I40E_DMA_CNTX_SIZE_1K:
5230         case I40E_DMA_CNTX_SIZE_2K:
5231         case I40E_DMA_CNTX_SIZE_4K:
5232                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5233                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5234                 break;
5235         default:
5236                 return I40E_ERR_PARAM;
5237         }
5238
5239         /* Validate PE settings passed */
5240         switch (settings->pe_filt_num) {
5241         case I40E_HASH_FILTER_SIZE_1K:
5242         case I40E_HASH_FILTER_SIZE_2K:
5243         case I40E_HASH_FILTER_SIZE_4K:
5244         case I40E_HASH_FILTER_SIZE_8K:
5245         case I40E_HASH_FILTER_SIZE_16K:
5246         case I40E_HASH_FILTER_SIZE_32K:
5247         case I40E_HASH_FILTER_SIZE_64K:
5248         case I40E_HASH_FILTER_SIZE_128K:
5249         case I40E_HASH_FILTER_SIZE_256K:
5250         case I40E_HASH_FILTER_SIZE_512K:
5251         case I40E_HASH_FILTER_SIZE_1M:
5252                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5253                 pe_filt_size <<= (u32)settings->pe_filt_num;
5254                 break;
5255         default:
5256                 return I40E_ERR_PARAM;
5257         }
5258
5259         switch (settings->pe_cntx_num) {
5260         case I40E_DMA_CNTX_SIZE_512:
5261         case I40E_DMA_CNTX_SIZE_1K:
5262         case I40E_DMA_CNTX_SIZE_2K:
5263         case I40E_DMA_CNTX_SIZE_4K:
5264         case I40E_DMA_CNTX_SIZE_8K:
5265         case I40E_DMA_CNTX_SIZE_16K:
5266         case I40E_DMA_CNTX_SIZE_32K:
5267         case I40E_DMA_CNTX_SIZE_64K:
5268         case I40E_DMA_CNTX_SIZE_128K:
5269         case I40E_DMA_CNTX_SIZE_256K:
5270                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5271                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5272                 break;
5273         default:
5274                 return I40E_ERR_PARAM;
5275         }
5276
5277         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5278         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5279         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5280                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5281         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
5282                 return I40E_ERR_INVALID_SIZE;
5283
5284         return I40E_SUCCESS;
5285 }
5286
5287 /**
5288  * i40e_set_filter_control
5289  * @hw: pointer to the hardware structure
5290  * @settings: Filter control settings
5291  *
5292  * Set the Queue Filters for PE/FCoE and enable filters required
5293  * for a single PF. It is expected that these settings are programmed
5294  * at the driver initialization time.
5295  **/
5296 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5297                                 struct i40e_filter_control_settings *settings)
5298 {
5299         enum i40e_status_code ret = I40E_SUCCESS;
5300         u32 hash_lut_size = 0;
5301         u32 val;
5302
5303         if (!settings)
5304                 return I40E_ERR_PARAM;
5305
5306         /* Validate the input settings */
5307         ret = i40e_validate_filter_settings(hw, settings);
5308         if (ret)
5309                 return ret;
5310
5311         /* Read the PF Queue Filter control register */
5312         val = rd32(hw, I40E_PFQF_CTL_0);
5313
5314         /* Program required PE hash buckets for the PF */
5315         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5316         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5317                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5318         /* Program required PE contexts for the PF */
5319         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5320         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5321                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5322
5323         /* Program required FCoE hash buckets for the PF */
5324         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5325         val |= ((u32)settings->fcoe_filt_num <<
5326                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5327                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5328         /* Program required FCoE DDP contexts for the PF */
5329         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5330         val |= ((u32)settings->fcoe_cntx_num <<
5331                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5332                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5333
5334         /* Program Hash LUT size for the PF */
5335         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5336         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5337                 hash_lut_size = 1;
5338         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5339                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5340
5341         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5342         if (settings->enable_fdir)
5343                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5344         if (settings->enable_ethtype)
5345                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5346         if (settings->enable_macvlan)
5347                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5348
5349         wr32(hw, I40E_PFQF_CTL_0, val);
5350
5351         return I40E_SUCCESS;
5352 }
5353
5354 /**
5355  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5356  * @hw: pointer to the hw struct
5357  * @mac_addr: MAC address to use in the filter
5358  * @ethtype: Ethertype to use in the filter
5359  * @flags: Flags that needs to be applied to the filter
5360  * @vsi_seid: seid of the control VSI
5361  * @queue: VSI queue number to send the packet to
5362  * @is_add: Add control packet filter if True else remove
5363  * @stats: Structure to hold information on control filter counts
5364  * @cmd_details: pointer to command details structure or NULL
5365  *
5366  * This command will Add or Remove control packet filter for a control VSI.
5367  * In return it will update the total number of perfect filter count in
5368  * the stats member.
5369  **/
5370 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5371                                 u8 *mac_addr, u16 ethtype, u16 flags,
5372                                 u16 vsi_seid, u16 queue, bool is_add,
5373                                 struct i40e_control_filter_stats *stats,
5374                                 struct i40e_asq_cmd_details *cmd_details)
5375 {
5376         struct i40e_aq_desc desc;
5377         struct i40e_aqc_add_remove_control_packet_filter *cmd =
5378                 (struct i40e_aqc_add_remove_control_packet_filter *)
5379                 &desc.params.raw;
5380         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5381                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5382                 &desc.params.raw;
5383         enum i40e_status_code status;
5384
5385         if (vsi_seid == 0)
5386                 return I40E_ERR_PARAM;
5387
5388         if (is_add) {
5389                 i40e_fill_default_direct_cmd_desc(&desc,
5390                                 i40e_aqc_opc_add_control_packet_filter);
5391                 cmd->queue = CPU_TO_LE16(queue);
5392         } else {
5393                 i40e_fill_default_direct_cmd_desc(&desc,
5394                                 i40e_aqc_opc_remove_control_packet_filter);
5395         }
5396
5397         if (mac_addr)
5398                 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
5399                             I40E_NONDMA_TO_NONDMA);
5400
5401         cmd->etype = CPU_TO_LE16(ethtype);
5402         cmd->flags = CPU_TO_LE16(flags);
5403         cmd->seid = CPU_TO_LE16(vsi_seid);
5404
5405         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5406
5407         if (!status && stats) {
5408                 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5409                 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5410                 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5411                 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5412         }
5413
5414         return status;
5415 }
5416
5417 /**
5418  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5419  * @hw: pointer to the hw struct
5420  * @seid: VSI seid to add ethertype filter from
5421  **/
5422 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5423 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5424                                                     u16 seid)
5425 {
5426         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5427                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5428                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5429         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5430         enum i40e_status_code status;
5431
5432         status = i40e_aq_add_rem_control_packet_filter(hw, 0, ethtype, flag,
5433                                                        seid, 0, true, NULL,
5434                                                        NULL);
5435         if (status)
5436                 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5437 }
5438
5439 /**
5440  * i40e_aq_add_cloud_filters
5441  * @hw: pointer to the hardware structure
5442  * @seid: VSI seid to add cloud filters from
5443  * @filters: Buffer which contains the filters to be added
5444  * @filter_count: number of filters contained in the buffer
5445  *
5446  * Set the cloud filters for a given VSI.  The contents of the
5447  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5448  * in by the caller of the function.
5449  *
5450  **/
5451 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5452         u16 seid,
5453         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5454         u8 filter_count)
5455 {
5456         struct i40e_aq_desc desc;
5457         struct i40e_aqc_add_remove_cloud_filters *cmd =
5458         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5459         u16 buff_len;
5460         enum i40e_status_code status;
5461
5462         i40e_fill_default_direct_cmd_desc(&desc,
5463                                           i40e_aqc_opc_add_cloud_filters);
5464
5465         buff_len = filter_count * sizeof(*filters);
5466         desc.datalen = CPU_TO_LE16(buff_len);
5467         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5468         cmd->num_filters = filter_count;
5469         cmd->seid = CPU_TO_LE16(seid);
5470
5471         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5472
5473         return status;
5474 }
5475
5476 /**
5477  * i40e_aq_remove_cloud_filters
5478  * @hw: pointer to the hardware structure
5479  * @seid: VSI seid to remove cloud filters from
5480  * @filters: Buffer which contains the filters to be removed
5481  * @filter_count: number of filters contained in the buffer
5482  *
5483  * Remove the cloud filters for a given VSI.  The contents of the
5484  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5485  * in by the caller of the function.
5486  *
5487  **/
5488 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5489                 u16 seid,
5490                 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5491                 u8 filter_count)
5492 {
5493         struct i40e_aq_desc desc;
5494         struct i40e_aqc_add_remove_cloud_filters *cmd =
5495         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5496         enum i40e_status_code status;
5497         u16 buff_len;
5498
5499         i40e_fill_default_direct_cmd_desc(&desc,
5500                                           i40e_aqc_opc_remove_cloud_filters);
5501
5502         buff_len = filter_count * sizeof(*filters);
5503         desc.datalen = CPU_TO_LE16(buff_len);
5504         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5505         cmd->num_filters = filter_count;
5506         cmd->seid = CPU_TO_LE16(seid);
5507
5508         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5509
5510         return status;
5511 }
5512
5513 /**
5514  * i40e_aq_alternate_write
5515  * @hw: pointer to the hardware structure
5516  * @reg_addr0: address of first dword to be read
5517  * @reg_val0: value to be written under 'reg_addr0'
5518  * @reg_addr1: address of second dword to be read
5519  * @reg_val1: value to be written under 'reg_addr1'
5520  *
5521  * Write one or two dwords to alternate structure. Fields are indicated
5522  * by 'reg_addr0' and 'reg_addr1' register numbers.
5523  *
5524  **/
5525 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5526                                 u32 reg_addr0, u32 reg_val0,
5527                                 u32 reg_addr1, u32 reg_val1)
5528 {
5529         struct i40e_aq_desc desc;
5530         struct i40e_aqc_alternate_write *cmd_resp =
5531                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5532         enum i40e_status_code status;
5533
5534         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5535         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5536         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5537         cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5538         cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5539
5540         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5541
5542         return status;
5543 }
5544
5545 /**
5546  * i40e_aq_alternate_write_indirect
5547  * @hw: pointer to the hardware structure
5548  * @addr: address of a first register to be modified
5549  * @dw_count: number of alternate structure fields to write
5550  * @buffer: pointer to the command buffer
5551  *
5552  * Write 'dw_count' dwords from 'buffer' to alternate structure
5553  * starting at 'addr'.
5554  *
5555  **/
5556 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5557                                 u32 addr, u32 dw_count, void *buffer)
5558 {
5559         struct i40e_aq_desc desc;
5560         struct i40e_aqc_alternate_ind_write *cmd_resp =
5561                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5562         enum i40e_status_code status;
5563
5564         if (buffer == NULL)
5565                 return I40E_ERR_PARAM;
5566
5567         /* Indirect command */
5568         i40e_fill_default_direct_cmd_desc(&desc,
5569                                          i40e_aqc_opc_alternate_write_indirect);
5570
5571         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5572         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5573         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5574                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5575
5576         cmd_resp->address = CPU_TO_LE32(addr);
5577         cmd_resp->length = CPU_TO_LE32(dw_count);
5578
5579         status = i40e_asq_send_command(hw, &desc, buffer,
5580                                        I40E_LO_DWORD(4*dw_count), NULL);
5581
5582         return status;
5583 }
5584
5585 /**
5586  * i40e_aq_alternate_read
5587  * @hw: pointer to the hardware structure
5588  * @reg_addr0: address of first dword to be read
5589  * @reg_val0: pointer for data read from 'reg_addr0'
5590  * @reg_addr1: address of second dword to be read
5591  * @reg_val1: pointer for data read from 'reg_addr1'
5592  *
5593  * Read one or two dwords from alternate structure. Fields are indicated
5594  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5595  * is not passed then only register at 'reg_addr0' is read.
5596  *
5597  **/
5598 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5599                                 u32 reg_addr0, u32 *reg_val0,
5600                                 u32 reg_addr1, u32 *reg_val1)
5601 {
5602         struct i40e_aq_desc desc;
5603         struct i40e_aqc_alternate_write *cmd_resp =
5604                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5605         enum i40e_status_code status;
5606
5607         if (reg_val0 == NULL)
5608                 return I40E_ERR_PARAM;
5609
5610         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5611         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5612         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5613
5614         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5615
5616         if (status == I40E_SUCCESS) {
5617                 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5618
5619                 if (reg_val1 != NULL)
5620                         *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5621         }
5622
5623         return status;
5624 }
5625
5626 /**
5627  * i40e_aq_alternate_read_indirect
5628  * @hw: pointer to the hardware structure
5629  * @addr: address of the alternate structure field
5630  * @dw_count: number of alternate structure fields to read
5631  * @buffer: pointer to the command buffer
5632  *
5633  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5634  * place them in 'buffer'. The buffer should be allocated by caller.
5635  *
5636  **/
5637 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5638                                 u32 addr, u32 dw_count, void *buffer)
5639 {
5640         struct i40e_aq_desc desc;
5641         struct i40e_aqc_alternate_ind_write *cmd_resp =
5642                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5643         enum i40e_status_code status;
5644
5645         if (buffer == NULL)
5646                 return I40E_ERR_PARAM;
5647
5648         /* Indirect command */
5649         i40e_fill_default_direct_cmd_desc(&desc,
5650                 i40e_aqc_opc_alternate_read_indirect);
5651
5652         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5653         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5654         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5655                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5656
5657         cmd_resp->address = CPU_TO_LE32(addr);
5658         cmd_resp->length = CPU_TO_LE32(dw_count);
5659
5660         status = i40e_asq_send_command(hw, &desc, buffer,
5661                                        I40E_LO_DWORD(4*dw_count), NULL);
5662
5663         return status;
5664 }
5665
5666 /**
5667  *  i40e_aq_alternate_clear
5668  *  @hw: pointer to the HW structure.
5669  *
5670  *  Clear the alternate structures of the port from which the function
5671  *  is called.
5672  *
5673  **/
5674 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5675 {
5676         struct i40e_aq_desc desc;
5677         enum i40e_status_code status;
5678
5679         i40e_fill_default_direct_cmd_desc(&desc,
5680                                           i40e_aqc_opc_alternate_clear_port);
5681
5682         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5683
5684         return status;
5685 }
5686
5687 /**
5688  *  i40e_aq_alternate_write_done
5689  *  @hw: pointer to the HW structure.
5690  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
5691  *  @reset_needed: indicates the SW should trigger GLOBAL reset
5692  *
5693  *  Indicates to the FW that alternate structures have been changed.
5694  *
5695  **/
5696 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
5697                 u8 bios_mode, bool *reset_needed)
5698 {
5699         struct i40e_aq_desc desc;
5700         struct i40e_aqc_alternate_write_done *cmd =
5701                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5702         enum i40e_status_code status;
5703
5704         if (reset_needed == NULL)
5705                 return I40E_ERR_PARAM;
5706
5707         i40e_fill_default_direct_cmd_desc(&desc,
5708                                           i40e_aqc_opc_alternate_write_done);
5709
5710         cmd->cmd_flags = CPU_TO_LE16(bios_mode);
5711
5712         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5713         if (!status && reset_needed)
5714                 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
5715                                  I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
5716
5717         return status;
5718 }
5719
5720 /**
5721  *  i40e_aq_set_oem_mode
5722  *  @hw: pointer to the HW structure.
5723  *  @oem_mode: the OEM mode to be used
5724  *
5725  *  Sets the device to a specific operating mode. Currently the only supported
5726  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
5727  *
5728  **/
5729 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
5730                 u8 oem_mode)
5731 {
5732         struct i40e_aq_desc desc;
5733         struct i40e_aqc_alternate_write_done *cmd =
5734                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5735         enum i40e_status_code status;
5736
5737         i40e_fill_default_direct_cmd_desc(&desc,
5738                                           i40e_aqc_opc_alternate_set_mode);
5739
5740         cmd->cmd_flags = CPU_TO_LE16(oem_mode);
5741
5742         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5743
5744         return status;
5745 }
5746
5747 /**
5748  * i40e_aq_resume_port_tx
5749  * @hw: pointer to the hardware structure
5750  * @cmd_details: pointer to command details structure or NULL
5751  *
5752  * Resume port's Tx traffic
5753  **/
5754 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
5755                                 struct i40e_asq_cmd_details *cmd_details)
5756 {
5757         struct i40e_aq_desc desc;
5758         enum i40e_status_code status;
5759
5760         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
5761
5762         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5763
5764         return status;
5765 }
5766
5767 /**
5768  * i40e_set_pci_config_data - store PCI bus info
5769  * @hw: pointer to hardware structure
5770  * @link_status: the link status word from PCI config space
5771  *
5772  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
5773  **/
5774 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
5775 {
5776         hw->bus.type = i40e_bus_type_pci_express;
5777
5778         switch (link_status & I40E_PCI_LINK_WIDTH) {
5779         case I40E_PCI_LINK_WIDTH_1:
5780                 hw->bus.width = i40e_bus_width_pcie_x1;
5781                 break;
5782         case I40E_PCI_LINK_WIDTH_2:
5783                 hw->bus.width = i40e_bus_width_pcie_x2;
5784                 break;
5785         case I40E_PCI_LINK_WIDTH_4:
5786                 hw->bus.width = i40e_bus_width_pcie_x4;
5787                 break;
5788         case I40E_PCI_LINK_WIDTH_8:
5789                 hw->bus.width = i40e_bus_width_pcie_x8;
5790                 break;
5791         default:
5792                 hw->bus.width = i40e_bus_width_unknown;
5793                 break;
5794         }
5795
5796         switch (link_status & I40E_PCI_LINK_SPEED) {
5797         case I40E_PCI_LINK_SPEED_2500:
5798                 hw->bus.speed = i40e_bus_speed_2500;
5799                 break;
5800         case I40E_PCI_LINK_SPEED_5000:
5801                 hw->bus.speed = i40e_bus_speed_5000;
5802                 break;
5803         case I40E_PCI_LINK_SPEED_8000:
5804                 hw->bus.speed = i40e_bus_speed_8000;
5805                 break;
5806         default:
5807                 hw->bus.speed = i40e_bus_speed_unknown;
5808                 break;
5809         }
5810 }
5811
5812 /**
5813  * i40e_aq_debug_dump
5814  * @hw: pointer to the hardware structure
5815  * @cluster_id: specific cluster to dump
5816  * @table_id: table id within cluster
5817  * @start_index: index of line in the block to read
5818  * @buff_size: dump buffer size
5819  * @buff: dump buffer
5820  * @ret_buff_size: actual buffer size returned
5821  * @ret_next_table: next block to read
5822  * @ret_next_index: next index to read
5823  *
5824  * Dump internal FW/HW data for debug purposes.
5825  *
5826  **/
5827 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
5828                                 u8 table_id, u32 start_index, u16 buff_size,
5829                                 void *buff, u16 *ret_buff_size,
5830                                 u8 *ret_next_table, u32 *ret_next_index,
5831                                 struct i40e_asq_cmd_details *cmd_details)
5832 {
5833         struct i40e_aq_desc desc;
5834         struct i40e_aqc_debug_dump_internals *cmd =
5835                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5836         struct i40e_aqc_debug_dump_internals *resp =
5837                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5838         enum i40e_status_code status;
5839
5840         if (buff_size == 0 || !buff)
5841                 return I40E_ERR_PARAM;
5842
5843         i40e_fill_default_direct_cmd_desc(&desc,
5844                                           i40e_aqc_opc_debug_dump_internals);
5845         /* Indirect Command */
5846         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5847         if (buff_size > I40E_AQ_LARGE_BUF)
5848                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5849
5850         cmd->cluster_id = cluster_id;
5851         cmd->table_id = table_id;
5852         cmd->idx = CPU_TO_LE32(start_index);
5853
5854         desc.datalen = CPU_TO_LE16(buff_size);
5855
5856         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5857         if (!status) {
5858                 if (ret_buff_size != NULL)
5859                         *ret_buff_size = LE16_TO_CPU(desc.datalen);
5860                 if (ret_next_table != NULL)
5861                         *ret_next_table = resp->table_id;
5862                 if (ret_next_index != NULL)
5863                         *ret_next_index = LE32_TO_CPU(resp->idx);
5864         }
5865
5866         return status;
5867 }
5868
5869 /**
5870  * i40e_read_bw_from_alt_ram
5871  * @hw: pointer to the hardware structure
5872  * @max_bw: pointer for max_bw read
5873  * @min_bw: pointer for min_bw read
5874  * @min_valid: pointer for bool that is true if min_bw is a valid value
5875  * @max_valid: pointer for bool that is true if max_bw is a valid value
5876  *
5877  * Read bw from the alternate ram for the given pf
5878  **/
5879 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
5880                                         u32 *max_bw, u32 *min_bw,
5881                                         bool *min_valid, bool *max_valid)
5882 {
5883         enum i40e_status_code status;
5884         u32 max_bw_addr, min_bw_addr;
5885
5886         /* Calculate the address of the min/max bw registers */
5887         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5888                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
5889                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5890         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5891                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
5892                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5893
5894         /* Read the bandwidths from alt ram */
5895         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
5896                                         min_bw_addr, min_bw);
5897
5898         if (*min_bw & I40E_ALT_BW_VALID_MASK)
5899                 *min_valid = true;
5900         else
5901                 *min_valid = false;
5902
5903         if (*max_bw & I40E_ALT_BW_VALID_MASK)
5904                 *max_valid = true;
5905         else
5906                 *max_valid = false;
5907
5908         return status;
5909 }
5910
5911 /**
5912  * i40e_aq_configure_partition_bw
5913  * @hw: pointer to the hardware structure
5914  * @bw_data: Buffer holding valid pfs and bw limits
5915  * @cmd_details: pointer to command details
5916  *
5917  * Configure partitions guaranteed/max bw
5918  **/
5919 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
5920                         struct i40e_aqc_configure_partition_bw_data *bw_data,
5921                         struct i40e_asq_cmd_details *cmd_details)
5922 {
5923         enum i40e_status_code status;
5924         struct i40e_aq_desc desc;
5925         u16 bwd_size = sizeof(*bw_data);
5926
5927         i40e_fill_default_direct_cmd_desc(&desc,
5928                                 i40e_aqc_opc_configure_partition_bw);
5929
5930         /* Indirect command */
5931         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5932         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5933
5934         if (bwd_size > I40E_AQ_LARGE_BUF)
5935                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5936
5937         desc.datalen = CPU_TO_LE16(bwd_size);
5938
5939         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
5940
5941         return status;
5942 }
5943 #endif /* PF_DRIVER */
5944 #ifdef VF_DRIVER
5945
5946 /**
5947  * i40e_aq_send_msg_to_pf
5948  * @hw: pointer to the hardware structure
5949  * @v_opcode: opcodes for VF-PF communication
5950  * @v_retval: return error code
5951  * @msg: pointer to the msg buffer
5952  * @msglen: msg length
5953  * @cmd_details: pointer to command details
5954  *
5955  * Send message to PF driver using admin queue. By default, this message
5956  * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
5957  * completion before returning.
5958  **/
5959 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
5960                                 enum i40e_virtchnl_ops v_opcode,
5961                                 enum i40e_status_code v_retval,
5962                                 u8 *msg, u16 msglen,
5963                                 struct i40e_asq_cmd_details *cmd_details)
5964 {
5965         struct i40e_aq_desc desc;
5966         struct i40e_asq_cmd_details details;
5967         enum i40e_status_code status;
5968
5969         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
5970         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
5971         desc.cookie_high = CPU_TO_LE32(v_opcode);
5972         desc.cookie_low = CPU_TO_LE32(v_retval);
5973         if (msglen) {
5974                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
5975                                                 | I40E_AQ_FLAG_RD));
5976                 if (msglen > I40E_AQ_LARGE_BUF)
5977                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5978                 desc.datalen = CPU_TO_LE16(msglen);
5979         }
5980         if (!cmd_details) {
5981                 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
5982                 details.async = true;
5983                 cmd_details = &details;
5984         }
5985         status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
5986                                        msglen, cmd_details);
5987         return status;
5988 }
5989
5990 /**
5991  * i40e_vf_parse_hw_config
5992  * @hw: pointer to the hardware structure
5993  * @msg: pointer to the virtual channel VF resource structure
5994  *
5995  * Given a VF resource message from the PF, populate the hw struct
5996  * with appropriate information.
5997  **/
5998 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
5999                              struct i40e_virtchnl_vf_resource *msg)
6000 {
6001         struct i40e_virtchnl_vsi_resource *vsi_res;
6002         int i;
6003
6004         vsi_res = &msg->vsi_res[0];
6005
6006         hw->dev_caps.num_vsis = msg->num_vsis;
6007         hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
6008         hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
6009         hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
6010         hw->dev_caps.dcb = msg->vf_offload_flags &
6011                            I40E_VIRTCHNL_VF_OFFLOAD_L2;
6012         hw->dev_caps.fcoe = (msg->vf_offload_flags &
6013                              I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
6014         hw->dev_caps.iwarp = (msg->vf_offload_flags &
6015                               I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
6016         for (i = 0; i < msg->num_vsis; i++) {
6017                 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
6018                         i40e_memcpy(hw->mac.perm_addr,
6019                                     vsi_res->default_mac_addr,
6020                                     I40E_ETH_LENGTH_OF_ADDRESS,
6021                                     I40E_NONDMA_TO_NONDMA);
6022                         i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
6023                                     I40E_ETH_LENGTH_OF_ADDRESS,
6024                                     I40E_NONDMA_TO_NONDMA);
6025                 }
6026                 vsi_res++;
6027         }
6028 }
6029
6030 /**
6031  * i40e_vf_reset
6032  * @hw: pointer to the hardware structure
6033  *
6034  * Send a VF_RESET message to the PF. Does not wait for response from PF
6035  * as none will be forthcoming. Immediately after calling this function,
6036  * the admin queue should be shut down and (optionally) reinitialized.
6037  **/
6038 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
6039 {
6040         return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
6041                                       I40E_SUCCESS, NULL, 0, NULL);
6042 }
6043 #endif /* VF_DRIVER */
6044 #ifdef X722_SUPPORT
6045
6046 /**
6047  * i40e_aq_set_arp_proxy_config
6048  * @hw: pointer to the HW structure
6049  * @proxy_config - pointer to proxy config command table struct
6050  * @cmd_details: pointer to command details
6051  *
6052  * Set ARP offload parameters from pre-populated
6053  * i40e_aqc_arp_proxy_data struct
6054  **/
6055 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
6056                                 struct i40e_aqc_arp_proxy_data *proxy_config,
6057                                 struct i40e_asq_cmd_details *cmd_details)
6058 {
6059         struct i40e_aq_desc desc;
6060         enum i40e_status_code status;
6061
6062         if (!proxy_config)
6063                 return I40E_ERR_PARAM;
6064
6065         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
6066
6067         desc.params.external.addr_high =
6068                                   CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
6069         desc.params.external.addr_low =
6070                                   CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
6071
6072         status = i40e_asq_send_command(hw, &desc, proxy_config,
6073                                        sizeof(struct i40e_aqc_arp_proxy_data),
6074                                        cmd_details);
6075
6076         return status;
6077 }
6078
6079 /**
6080  * i40e_aq_opc_set_ns_proxy_table_entry
6081  * @hw: pointer to the HW structure
6082  * @ns_proxy_table_entry: pointer to NS table entry command struct
6083  * @cmd_details: pointer to command details
6084  *
6085  * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
6086  * from pre-populated i40e_aqc_ns_proxy_data struct
6087  **/
6088 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
6089                         struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
6090                         struct i40e_asq_cmd_details *cmd_details)
6091 {
6092         struct i40e_aq_desc desc;
6093         enum i40e_status_code status;
6094
6095         if (!ns_proxy_table_entry)
6096                 return I40E_ERR_PARAM;
6097
6098         i40e_fill_default_direct_cmd_desc(&desc,
6099                                 i40e_aqc_opc_set_ns_proxy_table_entry);
6100
6101         desc.params.external.addr_high =
6102                 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
6103         desc.params.external.addr_low =
6104                 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
6105
6106         status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
6107                                        sizeof(struct i40e_aqc_ns_proxy_data),
6108                                        cmd_details);
6109
6110         return status;
6111 }
6112
6113 /**
6114  * i40e_aq_set_clear_wol_filter
6115  * @hw: pointer to the hw struct
6116  * @filter_index: index of filter to modify (0-7)
6117  * @filter: buffer containing filter to be set
6118  * @set_filter: true to set filter, false to clear filter
6119  * @no_wol_tco: if true, pass through packets cannot cause wake-up
6120  *              if false, pass through packets may cause wake-up
6121  * @filter_valid: true if filter action is valid
6122  * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
6123  * @cmd_details: pointer to command details structure or NULL
6124  *
6125  * Set or clear WoL filter for port attached to the PF
6126  **/
6127 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
6128                                 u8 filter_index,
6129                                 struct i40e_aqc_set_wol_filter_data *filter,
6130                                 bool set_filter, bool no_wol_tco,
6131                                 bool filter_valid, bool no_wol_tco_valid,
6132                                 struct i40e_asq_cmd_details *cmd_details)
6133 {
6134         struct i40e_aq_desc desc;
6135         struct i40e_aqc_set_wol_filter *cmd =
6136                 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
6137         enum i40e_status_code status;
6138         u16 cmd_flags = 0;
6139         u16 valid_flags = 0;
6140         u16 buff_len = 0;
6141
6142         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
6143
6144         if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
6145                 return  I40E_ERR_PARAM;
6146         cmd->filter_index = CPU_TO_LE16(filter_index);
6147
6148         if (set_filter) {
6149                 if (!filter)
6150                         return  I40E_ERR_PARAM;
6151                 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
6152                 buff_len = sizeof(*filter);
6153         }
6154         if (no_wol_tco)
6155                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
6156         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
6157
6158         if (filter_valid)
6159                 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
6160         if (no_wol_tco_valid)
6161                 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
6162         cmd->valid_flags = CPU_TO_LE16(valid_flags);
6163
6164         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
6165         cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
6166
6167         status = i40e_asq_send_command(hw, &desc, filter,
6168                                        buff_len, cmd_details);
6169
6170         return status;
6171 }
6172
6173 /**
6174  * i40e_aq_get_wake_event_reason
6175  * @hw: pointer to the hw struct
6176  * @wake_reason: return value, index of matching filter
6177  * @cmd_details: pointer to command details structure or NULL
6178  *
6179  * Get information for the reason of a Wake Up event
6180  **/
6181 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
6182                                 u16 *wake_reason,
6183                                 struct i40e_asq_cmd_details *cmd_details)
6184 {
6185         struct i40e_aq_desc desc;
6186         struct i40e_aqc_get_wake_reason_completion *resp =
6187                 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
6188         enum i40e_status_code status;
6189
6190         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
6191
6192         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6193
6194         if (status == I40E_SUCCESS)
6195                 *wake_reason = LE16_TO_CPU(resp->wake_reason);
6196
6197         return status;
6198 }
6199
6200 #endif /* X722_SUPPORT */