1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2018
6 #include "i40e_adminq.h"
7 #include "i40e_prototype.h"
11 * i40e_set_mac_type - Sets MAC type
12 * @hw: pointer to the HW structure
14 * This function sets the mac type of the adapter based on the
15 * vendor ID and device ID stored in the hw structure.
17 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
18 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
20 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
23 enum i40e_status_code status = I40E_SUCCESS;
25 DEBUGFUNC("i40e_set_mac_type\n");
27 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
28 switch (hw->device_id) {
29 case I40E_DEV_ID_SFP_XL710:
30 case I40E_DEV_ID_QEMU:
31 case I40E_DEV_ID_KX_B:
32 case I40E_DEV_ID_KX_C:
33 case I40E_DEV_ID_QSFP_A:
34 case I40E_DEV_ID_QSFP_B:
35 case I40E_DEV_ID_QSFP_C:
36 case I40E_DEV_ID_10G_BASE_T:
37 case I40E_DEV_ID_10G_BASE_T4:
38 case I40E_DEV_ID_10G_BASE_T_BC:
39 case I40E_DEV_ID_10G_B:
40 case I40E_DEV_ID_10G_SFP:
41 case I40E_DEV_ID_20G_KR2:
42 case I40E_DEV_ID_20G_KR2_A:
43 case I40E_DEV_ID_25G_B:
44 case I40E_DEV_ID_25G_SFP28:
45 case I40E_DEV_ID_X710_N3000:
46 case I40E_DEV_ID_XXV710_N3000:
47 hw->mac.type = I40E_MAC_XL710;
49 #ifdef X722_A0_SUPPORT
50 case I40E_DEV_ID_X722_A0:
52 case I40E_DEV_ID_KX_X722:
53 case I40E_DEV_ID_QSFP_X722:
54 case I40E_DEV_ID_SFP_X722:
55 case I40E_DEV_ID_1G_BASE_T_X722:
56 case I40E_DEV_ID_10G_BASE_T_X722:
57 case I40E_DEV_ID_SFP_I_X722:
58 hw->mac.type = I40E_MAC_X722;
60 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
61 case I40E_DEV_ID_X722_VF:
62 #ifdef X722_A0_SUPPORT
63 case I40E_DEV_ID_X722_A0_VF:
65 hw->mac.type = I40E_MAC_X722_VF;
67 #endif /* INTEGRATED_VF || VF_DRIVER */
68 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
70 case I40E_DEV_ID_VF_HV:
71 case I40E_DEV_ID_ADAPTIVE_VF:
72 hw->mac.type = I40E_MAC_VF;
76 hw->mac.type = I40E_MAC_GENERIC;
80 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
83 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
84 hw->mac.type, status);
89 * i40e_aq_str - convert AQ err code to a string
90 * @hw: pointer to the HW structure
91 * @aq_err: the AQ error code to convert
93 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
98 case I40E_AQ_RC_EPERM:
99 return "I40E_AQ_RC_EPERM";
100 case I40E_AQ_RC_ENOENT:
101 return "I40E_AQ_RC_ENOENT";
102 case I40E_AQ_RC_ESRCH:
103 return "I40E_AQ_RC_ESRCH";
104 case I40E_AQ_RC_EINTR:
105 return "I40E_AQ_RC_EINTR";
107 return "I40E_AQ_RC_EIO";
108 case I40E_AQ_RC_ENXIO:
109 return "I40E_AQ_RC_ENXIO";
110 case I40E_AQ_RC_E2BIG:
111 return "I40E_AQ_RC_E2BIG";
112 case I40E_AQ_RC_EAGAIN:
113 return "I40E_AQ_RC_EAGAIN";
114 case I40E_AQ_RC_ENOMEM:
115 return "I40E_AQ_RC_ENOMEM";
116 case I40E_AQ_RC_EACCES:
117 return "I40E_AQ_RC_EACCES";
118 case I40E_AQ_RC_EFAULT:
119 return "I40E_AQ_RC_EFAULT";
120 case I40E_AQ_RC_EBUSY:
121 return "I40E_AQ_RC_EBUSY";
122 case I40E_AQ_RC_EEXIST:
123 return "I40E_AQ_RC_EEXIST";
124 case I40E_AQ_RC_EINVAL:
125 return "I40E_AQ_RC_EINVAL";
126 case I40E_AQ_RC_ENOTTY:
127 return "I40E_AQ_RC_ENOTTY";
128 case I40E_AQ_RC_ENOSPC:
129 return "I40E_AQ_RC_ENOSPC";
130 case I40E_AQ_RC_ENOSYS:
131 return "I40E_AQ_RC_ENOSYS";
132 case I40E_AQ_RC_ERANGE:
133 return "I40E_AQ_RC_ERANGE";
134 case I40E_AQ_RC_EFLUSHED:
135 return "I40E_AQ_RC_EFLUSHED";
136 case I40E_AQ_RC_BAD_ADDR:
137 return "I40E_AQ_RC_BAD_ADDR";
138 case I40E_AQ_RC_EMODE:
139 return "I40E_AQ_RC_EMODE";
140 case I40E_AQ_RC_EFBIG:
141 return "I40E_AQ_RC_EFBIG";
144 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
149 * i40e_stat_str - convert status err code to a string
150 * @hw: pointer to the HW structure
151 * @stat_err: the status error code to convert
153 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
159 return "I40E_ERR_NVM";
160 case I40E_ERR_NVM_CHECKSUM:
161 return "I40E_ERR_NVM_CHECKSUM";
163 return "I40E_ERR_PHY";
164 case I40E_ERR_CONFIG:
165 return "I40E_ERR_CONFIG";
167 return "I40E_ERR_PARAM";
168 case I40E_ERR_MAC_TYPE:
169 return "I40E_ERR_MAC_TYPE";
170 case I40E_ERR_UNKNOWN_PHY:
171 return "I40E_ERR_UNKNOWN_PHY";
172 case I40E_ERR_LINK_SETUP:
173 return "I40E_ERR_LINK_SETUP";
174 case I40E_ERR_ADAPTER_STOPPED:
175 return "I40E_ERR_ADAPTER_STOPPED";
176 case I40E_ERR_INVALID_MAC_ADDR:
177 return "I40E_ERR_INVALID_MAC_ADDR";
178 case I40E_ERR_DEVICE_NOT_SUPPORTED:
179 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
180 case I40E_ERR_MASTER_REQUESTS_PENDING:
181 return "I40E_ERR_MASTER_REQUESTS_PENDING";
182 case I40E_ERR_INVALID_LINK_SETTINGS:
183 return "I40E_ERR_INVALID_LINK_SETTINGS";
184 case I40E_ERR_AUTONEG_NOT_COMPLETE:
185 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
186 case I40E_ERR_RESET_FAILED:
187 return "I40E_ERR_RESET_FAILED";
188 case I40E_ERR_SWFW_SYNC:
189 return "I40E_ERR_SWFW_SYNC";
190 case I40E_ERR_NO_AVAILABLE_VSI:
191 return "I40E_ERR_NO_AVAILABLE_VSI";
192 case I40E_ERR_NO_MEMORY:
193 return "I40E_ERR_NO_MEMORY";
194 case I40E_ERR_BAD_PTR:
195 return "I40E_ERR_BAD_PTR";
196 case I40E_ERR_RING_FULL:
197 return "I40E_ERR_RING_FULL";
198 case I40E_ERR_INVALID_PD_ID:
199 return "I40E_ERR_INVALID_PD_ID";
200 case I40E_ERR_INVALID_QP_ID:
201 return "I40E_ERR_INVALID_QP_ID";
202 case I40E_ERR_INVALID_CQ_ID:
203 return "I40E_ERR_INVALID_CQ_ID";
204 case I40E_ERR_INVALID_CEQ_ID:
205 return "I40E_ERR_INVALID_CEQ_ID";
206 case I40E_ERR_INVALID_AEQ_ID:
207 return "I40E_ERR_INVALID_AEQ_ID";
208 case I40E_ERR_INVALID_SIZE:
209 return "I40E_ERR_INVALID_SIZE";
210 case I40E_ERR_INVALID_ARP_INDEX:
211 return "I40E_ERR_INVALID_ARP_INDEX";
212 case I40E_ERR_INVALID_FPM_FUNC_ID:
213 return "I40E_ERR_INVALID_FPM_FUNC_ID";
214 case I40E_ERR_QP_INVALID_MSG_SIZE:
215 return "I40E_ERR_QP_INVALID_MSG_SIZE";
216 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
217 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
218 case I40E_ERR_INVALID_FRAG_COUNT:
219 return "I40E_ERR_INVALID_FRAG_COUNT";
220 case I40E_ERR_QUEUE_EMPTY:
221 return "I40E_ERR_QUEUE_EMPTY";
222 case I40E_ERR_INVALID_ALIGNMENT:
223 return "I40E_ERR_INVALID_ALIGNMENT";
224 case I40E_ERR_FLUSHED_QUEUE:
225 return "I40E_ERR_FLUSHED_QUEUE";
226 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
227 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
228 case I40E_ERR_INVALID_IMM_DATA_SIZE:
229 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
230 case I40E_ERR_TIMEOUT:
231 return "I40E_ERR_TIMEOUT";
232 case I40E_ERR_OPCODE_MISMATCH:
233 return "I40E_ERR_OPCODE_MISMATCH";
234 case I40E_ERR_CQP_COMPL_ERROR:
235 return "I40E_ERR_CQP_COMPL_ERROR";
236 case I40E_ERR_INVALID_VF_ID:
237 return "I40E_ERR_INVALID_VF_ID";
238 case I40E_ERR_INVALID_HMCFN_ID:
239 return "I40E_ERR_INVALID_HMCFN_ID";
240 case I40E_ERR_BACKING_PAGE_ERROR:
241 return "I40E_ERR_BACKING_PAGE_ERROR";
242 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
243 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
244 case I40E_ERR_INVALID_PBLE_INDEX:
245 return "I40E_ERR_INVALID_PBLE_INDEX";
246 case I40E_ERR_INVALID_SD_INDEX:
247 return "I40E_ERR_INVALID_SD_INDEX";
248 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
249 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
250 case I40E_ERR_INVALID_SD_TYPE:
251 return "I40E_ERR_INVALID_SD_TYPE";
252 case I40E_ERR_MEMCPY_FAILED:
253 return "I40E_ERR_MEMCPY_FAILED";
254 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
255 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
256 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
257 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
258 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
259 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
260 case I40E_ERR_SRQ_ENABLED:
261 return "I40E_ERR_SRQ_ENABLED";
262 case I40E_ERR_ADMIN_QUEUE_ERROR:
263 return "I40E_ERR_ADMIN_QUEUE_ERROR";
264 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
265 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
266 case I40E_ERR_BUF_TOO_SHORT:
267 return "I40E_ERR_BUF_TOO_SHORT";
268 case I40E_ERR_ADMIN_QUEUE_FULL:
269 return "I40E_ERR_ADMIN_QUEUE_FULL";
270 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
271 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
272 case I40E_ERR_BAD_IWARP_CQE:
273 return "I40E_ERR_BAD_IWARP_CQE";
274 case I40E_ERR_NVM_BLANK_MODE:
275 return "I40E_ERR_NVM_BLANK_MODE";
276 case I40E_ERR_NOT_IMPLEMENTED:
277 return "I40E_ERR_NOT_IMPLEMENTED";
278 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
279 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
280 case I40E_ERR_DIAG_TEST_FAILED:
281 return "I40E_ERR_DIAG_TEST_FAILED";
282 case I40E_ERR_NOT_READY:
283 return "I40E_ERR_NOT_READY";
284 case I40E_NOT_SUPPORTED:
285 return "I40E_NOT_SUPPORTED";
286 case I40E_ERR_FIRMWARE_API_VERSION:
287 return "I40E_ERR_FIRMWARE_API_VERSION";
288 case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR:
289 return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR";
292 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
298 * @hw: debug mask related to admin queue
300 * @desc: pointer to admin queue descriptor
301 * @buffer: pointer to command buffer
302 * @buf_len: max length of buffer
304 * Dumps debug log about adminq command with descriptor contents.
306 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
307 void *buffer, u16 buf_len)
309 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
310 u32 effective_mask = hw->debug_mask & mask;
311 u8 *buf = (u8 *)buffer;
315 if (!effective_mask || !desc)
318 len = LE16_TO_CPU(aq_desc->datalen);
320 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
321 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
322 LE16_TO_CPU(aq_desc->opcode),
323 LE16_TO_CPU(aq_desc->flags),
324 LE16_TO_CPU(aq_desc->datalen),
325 LE16_TO_CPU(aq_desc->retval));
326 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
327 "\tcookie (h,l) 0x%08X 0x%08X\n",
328 LE32_TO_CPU(aq_desc->cookie_high),
329 LE32_TO_CPU(aq_desc->cookie_low));
330 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
331 "\tparam (0,1) 0x%08X 0x%08X\n",
332 LE32_TO_CPU(aq_desc->params.internal.param0),
333 LE32_TO_CPU(aq_desc->params.internal.param1));
334 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
335 "\taddr (h,l) 0x%08X 0x%08X\n",
336 LE32_TO_CPU(aq_desc->params.external.addr_high),
337 LE32_TO_CPU(aq_desc->params.external.addr_low));
339 if (buffer && (buf_len != 0) && (len != 0) &&
340 (effective_mask & I40E_DEBUG_AQ_DESC_BUFFER)) {
341 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
344 /* write the full 16-byte chunks */
345 for (i = 0; i < (len - 16); i += 16)
347 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
348 i, buf[i], buf[i+1], buf[i+2], buf[i+3],
349 buf[i+4], buf[i+5], buf[i+6], buf[i+7],
350 buf[i+8], buf[i+9], buf[i+10], buf[i+11],
351 buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
352 /* the most we could have left is 16 bytes, pad with zeros */
358 memset(d_buf, 0, sizeof(d_buf));
359 for (j = 0; i < len; j++, i++)
362 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
363 i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
364 d_buf[4], d_buf[5], d_buf[6], d_buf[7],
365 d_buf[8], d_buf[9], d_buf[10], d_buf[11],
366 d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
372 * i40e_check_asq_alive
373 * @hw: pointer to the hw struct
375 * Returns true if Queue is enabled else false.
377 bool i40e_check_asq_alive(struct i40e_hw *hw)
383 return !!(rd32(hw, hw->aq.asq.len) &
384 I40E_PF_ATQLEN_ATQENABLE_MASK);
386 return !!(rd32(hw, hw->aq.asq.len) &
387 I40E_PF_ATQLEN_ATQENABLE_MASK);
388 #endif /* INTEGRATED_VF */
389 #endif /* PF_DRIVER */
393 return !!(rd32(hw, hw->aq.asq.len) &
394 I40E_VF_ATQLEN1_ATQENABLE_MASK);
396 return !!(rd32(hw, hw->aq.asq.len) &
397 I40E_VF_ATQLEN1_ATQENABLE_MASK);
398 #endif /* INTEGRATED_VF */
399 #endif /* VF_DRIVER */
404 * i40e_aq_queue_shutdown
405 * @hw: pointer to the hw struct
406 * @unloading: is the driver unloading itself
408 * Tell the Firmware that we're shutting down the AdminQ and whether
409 * or not the driver is unloading as well.
411 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
414 struct i40e_aq_desc desc;
415 struct i40e_aqc_queue_shutdown *cmd =
416 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
417 enum i40e_status_code status;
419 i40e_fill_default_direct_cmd_desc(&desc,
420 i40e_aqc_opc_queue_shutdown);
423 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
424 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
430 * i40e_aq_get_set_rss_lut
431 * @hw: pointer to the hardware structure
432 * @vsi_id: vsi fw index
433 * @pf_lut: for PF table set true, for VSI table set false
434 * @lut: pointer to the lut buffer provided by the caller
435 * @lut_size: size of the lut buffer
436 * @set: set true to set the table, false to get the table
438 * Internal function to get or set RSS look up table
440 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
441 u16 vsi_id, bool pf_lut,
442 u8 *lut, u16 lut_size,
445 enum i40e_status_code status;
446 struct i40e_aq_desc desc;
447 struct i40e_aqc_get_set_rss_lut *cmd_resp =
448 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
451 i40e_fill_default_direct_cmd_desc(&desc,
452 i40e_aqc_opc_set_rss_lut);
454 i40e_fill_default_direct_cmd_desc(&desc,
455 i40e_aqc_opc_get_rss_lut);
457 /* Indirect command */
458 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
459 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
462 CPU_TO_LE16((u16)((vsi_id <<
463 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
464 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
465 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
468 cmd_resp->flags |= CPU_TO_LE16((u16)
469 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
470 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
471 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
473 cmd_resp->flags |= CPU_TO_LE16((u16)
474 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
475 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
476 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
478 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
484 * i40e_aq_get_rss_lut
485 * @hw: pointer to the hardware structure
486 * @vsi_id: vsi fw index
487 * @pf_lut: for PF table set true, for VSI table set false
488 * @lut: pointer to the lut buffer provided by the caller
489 * @lut_size: size of the lut buffer
491 * get the RSS lookup table, PF or VSI type
493 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
494 bool pf_lut, u8 *lut, u16 lut_size)
496 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
501 * i40e_aq_set_rss_lut
502 * @hw: pointer to the hardware structure
503 * @vsi_id: vsi fw index
504 * @pf_lut: for PF table set true, for VSI table set false
505 * @lut: pointer to the lut buffer provided by the caller
506 * @lut_size: size of the lut buffer
508 * set the RSS lookup table, PF or VSI type
510 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
511 bool pf_lut, u8 *lut, u16 lut_size)
513 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
517 * i40e_aq_get_set_rss_key
518 * @hw: pointer to the hw struct
519 * @vsi_id: vsi fw index
520 * @key: pointer to key info struct
521 * @set: set true to set the key, false to get the key
523 * get the RSS key per VSI
525 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
527 struct i40e_aqc_get_set_rss_key_data *key,
530 enum i40e_status_code status;
531 struct i40e_aq_desc desc;
532 struct i40e_aqc_get_set_rss_key *cmd_resp =
533 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
534 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
537 i40e_fill_default_direct_cmd_desc(&desc,
538 i40e_aqc_opc_set_rss_key);
540 i40e_fill_default_direct_cmd_desc(&desc,
541 i40e_aqc_opc_get_rss_key);
543 /* Indirect command */
544 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
545 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
548 CPU_TO_LE16((u16)((vsi_id <<
549 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
550 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
551 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
553 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
559 * i40e_aq_get_rss_key
560 * @hw: pointer to the hw struct
561 * @vsi_id: vsi fw index
562 * @key: pointer to key info struct
565 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
567 struct i40e_aqc_get_set_rss_key_data *key)
569 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
573 * i40e_aq_set_rss_key
574 * @hw: pointer to the hw struct
575 * @vsi_id: vsi fw index
576 * @key: pointer to key info struct
578 * set the RSS key per VSI
580 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
582 struct i40e_aqc_get_set_rss_key_data *key)
584 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
587 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
588 * hardware to a bit-field that can be used by SW to more easily determine the
591 * Macros are used to shorten the table lines and make this table human
594 * We store the PTYPE in the top byte of the bit field - this is just so that
595 * we can check that the table doesn't have a row missing, as the index into
596 * the table should be the PTYPE.
600 * IF NOT i40e_ptype_lookup[ptype].known
603 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
604 * Use the rest of the fields to look at the tunnels, inner protocols, etc
606 * Use the enum i40e_rx_l2_ptype to decode the packet type
610 /* macro to make the table lines short */
611 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
614 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
615 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
616 I40E_RX_PTYPE_##OUTER_FRAG, \
617 I40E_RX_PTYPE_TUNNEL_##T, \
618 I40E_RX_PTYPE_TUNNEL_END_##TE, \
619 I40E_RX_PTYPE_##TEF, \
620 I40E_RX_PTYPE_INNER_PROT_##I, \
621 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
623 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
624 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
626 /* shorter macros makes the table fit but are terse */
627 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
628 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
629 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
631 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
632 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
633 /* L2 Packet types */
634 I40E_PTT_UNUSED_ENTRY(0),
635 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
636 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
637 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
638 I40E_PTT_UNUSED_ENTRY(4),
639 I40E_PTT_UNUSED_ENTRY(5),
640 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
641 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
642 I40E_PTT_UNUSED_ENTRY(8),
643 I40E_PTT_UNUSED_ENTRY(9),
644 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
645 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
646 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
647 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
648 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
649 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
650 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
651 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
652 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
653 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
654 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
655 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
657 /* Non Tunneled IPv4 */
658 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
659 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
660 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
661 I40E_PTT_UNUSED_ENTRY(25),
662 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
663 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
664 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
667 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
668 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
669 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
670 I40E_PTT_UNUSED_ENTRY(32),
671 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
672 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
673 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
676 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
677 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
678 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
679 I40E_PTT_UNUSED_ENTRY(39),
680 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
681 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
682 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
684 /* IPv4 --> GRE/NAT */
685 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
687 /* IPv4 --> GRE/NAT --> IPv4 */
688 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
689 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
690 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
691 I40E_PTT_UNUSED_ENTRY(47),
692 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
693 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
694 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
696 /* IPv4 --> GRE/NAT --> IPv6 */
697 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
698 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
699 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
700 I40E_PTT_UNUSED_ENTRY(54),
701 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
702 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
703 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
705 /* IPv4 --> GRE/NAT --> MAC */
706 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
708 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
709 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
710 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
711 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
712 I40E_PTT_UNUSED_ENTRY(62),
713 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
714 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
715 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
717 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
718 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
719 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
720 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
721 I40E_PTT_UNUSED_ENTRY(69),
722 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
723 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
724 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
726 /* IPv4 --> GRE/NAT --> MAC/VLAN */
727 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
729 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
730 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
731 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
732 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
733 I40E_PTT_UNUSED_ENTRY(77),
734 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
735 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
736 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
738 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
739 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
740 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
741 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
742 I40E_PTT_UNUSED_ENTRY(84),
743 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
744 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
745 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
747 /* Non Tunneled IPv6 */
748 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
749 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
750 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4),
751 I40E_PTT_UNUSED_ENTRY(91),
752 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
753 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
754 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
757 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
758 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
759 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
760 I40E_PTT_UNUSED_ENTRY(98),
761 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
762 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
763 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
766 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
767 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
768 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
769 I40E_PTT_UNUSED_ENTRY(105),
770 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
771 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
772 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
774 /* IPv6 --> GRE/NAT */
775 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
777 /* IPv6 --> GRE/NAT -> IPv4 */
778 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
779 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
780 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
781 I40E_PTT_UNUSED_ENTRY(113),
782 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
783 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
784 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
786 /* IPv6 --> GRE/NAT -> IPv6 */
787 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
788 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
789 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
790 I40E_PTT_UNUSED_ENTRY(120),
791 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
792 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
793 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
795 /* IPv6 --> GRE/NAT -> MAC */
796 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
798 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
799 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
800 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
801 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
802 I40E_PTT_UNUSED_ENTRY(128),
803 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
804 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
805 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
807 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
808 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
809 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
810 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
811 I40E_PTT_UNUSED_ENTRY(135),
812 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
813 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
814 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
816 /* IPv6 --> GRE/NAT -> MAC/VLAN */
817 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
819 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
820 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
821 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
822 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
823 I40E_PTT_UNUSED_ENTRY(143),
824 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
825 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
826 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
828 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
829 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
830 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
831 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
832 I40E_PTT_UNUSED_ENTRY(150),
833 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
834 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
835 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
838 I40E_PTT_UNUSED_ENTRY(154),
839 I40E_PTT_UNUSED_ENTRY(155),
840 I40E_PTT_UNUSED_ENTRY(156),
841 I40E_PTT_UNUSED_ENTRY(157),
842 I40E_PTT_UNUSED_ENTRY(158),
843 I40E_PTT_UNUSED_ENTRY(159),
845 I40E_PTT_UNUSED_ENTRY(160),
846 I40E_PTT_UNUSED_ENTRY(161),
847 I40E_PTT_UNUSED_ENTRY(162),
848 I40E_PTT_UNUSED_ENTRY(163),
849 I40E_PTT_UNUSED_ENTRY(164),
850 I40E_PTT_UNUSED_ENTRY(165),
851 I40E_PTT_UNUSED_ENTRY(166),
852 I40E_PTT_UNUSED_ENTRY(167),
853 I40E_PTT_UNUSED_ENTRY(168),
854 I40E_PTT_UNUSED_ENTRY(169),
856 I40E_PTT_UNUSED_ENTRY(170),
857 I40E_PTT_UNUSED_ENTRY(171),
858 I40E_PTT_UNUSED_ENTRY(172),
859 I40E_PTT_UNUSED_ENTRY(173),
860 I40E_PTT_UNUSED_ENTRY(174),
861 I40E_PTT_UNUSED_ENTRY(175),
862 I40E_PTT_UNUSED_ENTRY(176),
863 I40E_PTT_UNUSED_ENTRY(177),
864 I40E_PTT_UNUSED_ENTRY(178),
865 I40E_PTT_UNUSED_ENTRY(179),
867 I40E_PTT_UNUSED_ENTRY(180),
868 I40E_PTT_UNUSED_ENTRY(181),
869 I40E_PTT_UNUSED_ENTRY(182),
870 I40E_PTT_UNUSED_ENTRY(183),
871 I40E_PTT_UNUSED_ENTRY(184),
872 I40E_PTT_UNUSED_ENTRY(185),
873 I40E_PTT_UNUSED_ENTRY(186),
874 I40E_PTT_UNUSED_ENTRY(187),
875 I40E_PTT_UNUSED_ENTRY(188),
876 I40E_PTT_UNUSED_ENTRY(189),
878 I40E_PTT_UNUSED_ENTRY(190),
879 I40E_PTT_UNUSED_ENTRY(191),
880 I40E_PTT_UNUSED_ENTRY(192),
881 I40E_PTT_UNUSED_ENTRY(193),
882 I40E_PTT_UNUSED_ENTRY(194),
883 I40E_PTT_UNUSED_ENTRY(195),
884 I40E_PTT_UNUSED_ENTRY(196),
885 I40E_PTT_UNUSED_ENTRY(197),
886 I40E_PTT_UNUSED_ENTRY(198),
887 I40E_PTT_UNUSED_ENTRY(199),
889 I40E_PTT_UNUSED_ENTRY(200),
890 I40E_PTT_UNUSED_ENTRY(201),
891 I40E_PTT_UNUSED_ENTRY(202),
892 I40E_PTT_UNUSED_ENTRY(203),
893 I40E_PTT_UNUSED_ENTRY(204),
894 I40E_PTT_UNUSED_ENTRY(205),
895 I40E_PTT_UNUSED_ENTRY(206),
896 I40E_PTT_UNUSED_ENTRY(207),
897 I40E_PTT_UNUSED_ENTRY(208),
898 I40E_PTT_UNUSED_ENTRY(209),
900 I40E_PTT_UNUSED_ENTRY(210),
901 I40E_PTT_UNUSED_ENTRY(211),
902 I40E_PTT_UNUSED_ENTRY(212),
903 I40E_PTT_UNUSED_ENTRY(213),
904 I40E_PTT_UNUSED_ENTRY(214),
905 I40E_PTT_UNUSED_ENTRY(215),
906 I40E_PTT_UNUSED_ENTRY(216),
907 I40E_PTT_UNUSED_ENTRY(217),
908 I40E_PTT_UNUSED_ENTRY(218),
909 I40E_PTT_UNUSED_ENTRY(219),
911 I40E_PTT_UNUSED_ENTRY(220),
912 I40E_PTT_UNUSED_ENTRY(221),
913 I40E_PTT_UNUSED_ENTRY(222),
914 I40E_PTT_UNUSED_ENTRY(223),
915 I40E_PTT_UNUSED_ENTRY(224),
916 I40E_PTT_UNUSED_ENTRY(225),
917 I40E_PTT_UNUSED_ENTRY(226),
918 I40E_PTT_UNUSED_ENTRY(227),
919 I40E_PTT_UNUSED_ENTRY(228),
920 I40E_PTT_UNUSED_ENTRY(229),
922 I40E_PTT_UNUSED_ENTRY(230),
923 I40E_PTT_UNUSED_ENTRY(231),
924 I40E_PTT_UNUSED_ENTRY(232),
925 I40E_PTT_UNUSED_ENTRY(233),
926 I40E_PTT_UNUSED_ENTRY(234),
927 I40E_PTT_UNUSED_ENTRY(235),
928 I40E_PTT_UNUSED_ENTRY(236),
929 I40E_PTT_UNUSED_ENTRY(237),
930 I40E_PTT_UNUSED_ENTRY(238),
931 I40E_PTT_UNUSED_ENTRY(239),
933 I40E_PTT_UNUSED_ENTRY(240),
934 I40E_PTT_UNUSED_ENTRY(241),
935 I40E_PTT_UNUSED_ENTRY(242),
936 I40E_PTT_UNUSED_ENTRY(243),
937 I40E_PTT_UNUSED_ENTRY(244),
938 I40E_PTT_UNUSED_ENTRY(245),
939 I40E_PTT_UNUSED_ENTRY(246),
940 I40E_PTT_UNUSED_ENTRY(247),
941 I40E_PTT_UNUSED_ENTRY(248),
942 I40E_PTT_UNUSED_ENTRY(249),
944 I40E_PTT_UNUSED_ENTRY(250),
945 I40E_PTT_UNUSED_ENTRY(251),
946 I40E_PTT_UNUSED_ENTRY(252),
947 I40E_PTT_UNUSED_ENTRY(253),
948 I40E_PTT_UNUSED_ENTRY(254),
949 I40E_PTT_UNUSED_ENTRY(255)
954 * i40e_validate_mac_addr - Validate unicast MAC address
955 * @mac_addr: pointer to MAC address
957 * Tests a MAC address to ensure it is a valid Individual Address
959 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
961 enum i40e_status_code status = I40E_SUCCESS;
963 DEBUGFUNC("i40e_validate_mac_addr");
965 /* Broadcast addresses ARE multicast addresses
966 * Make sure it is not a multicast address
967 * Reject the zero address
969 if (I40E_IS_MULTICAST(mac_addr) ||
970 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
971 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
972 status = I40E_ERR_INVALID_MAC_ADDR;
979 * i40e_init_shared_code - Initialize the shared code
980 * @hw: pointer to hardware structure
982 * This assigns the MAC type and PHY code and inits the NVM.
983 * Does not touch the hardware. This function must be called prior to any
984 * other function in the shared code. The i40e_hw structure should be
985 * memset to 0 prior to calling this function. The following fields in
986 * hw structure should be filled in prior to calling this function:
987 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
988 * subsystem_vendor_id, and revision_id
990 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
992 enum i40e_status_code status = I40E_SUCCESS;
993 u32 port, ari, func_rid;
995 DEBUGFUNC("i40e_init_shared_code");
997 i40e_set_mac_type(hw);
999 switch (hw->mac.type) {
1000 case I40E_MAC_XL710:
1004 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1007 hw->phy.get_link_info = true;
1009 /* Determine port number and PF number*/
1010 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1011 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1012 hw->port = (u8)port;
1013 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1014 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1015 func_rid = rd32(hw, I40E_PF_FUNC_RID);
1017 hw->pf_id = (u8)(func_rid & 0xff);
1019 hw->pf_id = (u8)(func_rid & 0x7);
1021 if (hw->mac.type == I40E_MAC_X722)
1022 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE |
1023 I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK;
1024 /* NVMUpdate features structure initialization */
1025 hw->nvmupd_features.major = I40E_NVMUPD_FEATURES_API_VER_MAJOR;
1026 hw->nvmupd_features.minor = I40E_NVMUPD_FEATURES_API_VER_MINOR;
1027 hw->nvmupd_features.size = sizeof(hw->nvmupd_features);
1028 i40e_memset(hw->nvmupd_features.features, 0x0,
1029 I40E_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN *
1030 sizeof(*hw->nvmupd_features.features),
1033 /* No features supported at the moment */
1034 hw->nvmupd_features.features[0] = 0;
1036 status = i40e_init_nvm(hw);
1041 * i40e_aq_mac_address_read - Retrieve the MAC addresses
1042 * @hw: pointer to the hw struct
1043 * @flags: a return indicator of what addresses were added to the addr store
1044 * @addrs: the requestor's mac addr store
1045 * @cmd_details: pointer to command details structure or NULL
1047 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1049 struct i40e_aqc_mac_address_read_data *addrs,
1050 struct i40e_asq_cmd_details *cmd_details)
1052 struct i40e_aq_desc desc;
1053 struct i40e_aqc_mac_address_read *cmd_data =
1054 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1055 enum i40e_status_code status;
1057 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1058 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1060 status = i40e_asq_send_command(hw, &desc, addrs,
1061 sizeof(*addrs), cmd_details);
1062 *flags = LE16_TO_CPU(cmd_data->command_flags);
1068 * i40e_aq_mac_address_write - Change the MAC addresses
1069 * @hw: pointer to the hw struct
1070 * @flags: indicates which MAC to be written
1071 * @mac_addr: address to write
1072 * @cmd_details: pointer to command details structure or NULL
1074 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1075 u16 flags, u8 *mac_addr,
1076 struct i40e_asq_cmd_details *cmd_details)
1078 struct i40e_aq_desc desc;
1079 struct i40e_aqc_mac_address_write *cmd_data =
1080 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1081 enum i40e_status_code status;
1083 i40e_fill_default_direct_cmd_desc(&desc,
1084 i40e_aqc_opc_mac_address_write);
1085 cmd_data->command_flags = CPU_TO_LE16(flags);
1086 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1087 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1088 ((u32)mac_addr[3] << 16) |
1089 ((u32)mac_addr[4] << 8) |
1092 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1098 * i40e_get_mac_addr - get MAC address
1099 * @hw: pointer to the HW structure
1100 * @mac_addr: pointer to MAC address
1102 * Reads the adapter's MAC address from register
1104 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1106 struct i40e_aqc_mac_address_read_data addrs;
1107 enum i40e_status_code status;
1110 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1112 if (flags & I40E_AQC_LAN_ADDR_VALID)
1113 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1114 I40E_NONDMA_TO_NONDMA);
1120 * i40e_get_port_mac_addr - get Port MAC address
1121 * @hw: pointer to the HW structure
1122 * @mac_addr: pointer to Port MAC address
1124 * Reads the adapter's Port MAC address
1126 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1128 struct i40e_aqc_mac_address_read_data addrs;
1129 enum i40e_status_code status;
1132 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1136 if (flags & I40E_AQC_PORT_ADDR_VALID)
1137 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1138 I40E_NONDMA_TO_NONDMA);
1140 status = I40E_ERR_INVALID_MAC_ADDR;
1146 * i40e_pre_tx_queue_cfg - pre tx queue configure
1147 * @hw: pointer to the HW structure
1148 * @queue: target pf queue index
1149 * @enable: state change request
1151 * Handles hw requirement to indicate intention to enable
1152 * or disable target queue.
1154 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1156 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1160 if (abs_queue_idx >= 128) {
1161 reg_block = abs_queue_idx / 128;
1162 abs_queue_idx %= 128;
1165 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1166 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1167 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1170 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1172 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1174 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1178 * i40e_get_san_mac_addr - get SAN MAC address
1179 * @hw: pointer to the HW structure
1180 * @mac_addr: pointer to SAN MAC address
1182 * Reads the adapter's SAN MAC address from NVM
1184 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1187 struct i40e_aqc_mac_address_read_data addrs;
1188 enum i40e_status_code status;
1191 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1195 if (flags & I40E_AQC_SAN_ADDR_VALID)
1196 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac),
1197 I40E_NONDMA_TO_NONDMA);
1199 status = I40E_ERR_INVALID_MAC_ADDR;
1205 * i40e_read_pba_string - Reads part number string from EEPROM
1206 * @hw: pointer to hardware structure
1207 * @pba_num: stores the part number string from the EEPROM
1208 * @pba_num_size: part number string buffer length
1210 * Reads the part number string from the EEPROM.
1212 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1215 enum i40e_status_code status = I40E_SUCCESS;
1221 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1222 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1223 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1227 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1228 if (status != I40E_SUCCESS) {
1229 DEBUGOUT("Failed to read PBA Block pointer.\n");
1233 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1234 if (status != I40E_SUCCESS) {
1235 DEBUGOUT("Failed to read PBA Block size.\n");
1239 /* Subtract one to get PBA word count (PBA Size word is included in
1243 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1244 DEBUGOUT("Buffer to small for PBA data.\n");
1245 return I40E_ERR_PARAM;
1248 for (i = 0; i < pba_size; i++) {
1249 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1250 if (status != I40E_SUCCESS) {
1251 DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1255 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1256 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1258 pba_num[(pba_size * 2)] = '\0';
1264 * i40e_get_media_type - Gets media type
1265 * @hw: pointer to the hardware structure
1267 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1269 enum i40e_media_type media;
1271 switch (hw->phy.link_info.phy_type) {
1272 case I40E_PHY_TYPE_10GBASE_SR:
1273 case I40E_PHY_TYPE_10GBASE_LR:
1274 case I40E_PHY_TYPE_1000BASE_SX:
1275 case I40E_PHY_TYPE_1000BASE_LX:
1276 case I40E_PHY_TYPE_40GBASE_SR4:
1277 case I40E_PHY_TYPE_40GBASE_LR4:
1278 case I40E_PHY_TYPE_25GBASE_LR:
1279 case I40E_PHY_TYPE_25GBASE_SR:
1280 media = I40E_MEDIA_TYPE_FIBER;
1282 case I40E_PHY_TYPE_100BASE_TX:
1283 case I40E_PHY_TYPE_1000BASE_T:
1284 case I40E_PHY_TYPE_2_5GBASE_T:
1285 case I40E_PHY_TYPE_5GBASE_T:
1286 case I40E_PHY_TYPE_10GBASE_T:
1287 media = I40E_MEDIA_TYPE_BASET;
1289 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1290 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1291 case I40E_PHY_TYPE_10GBASE_CR1:
1292 case I40E_PHY_TYPE_40GBASE_CR4:
1293 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1294 case I40E_PHY_TYPE_40GBASE_AOC:
1295 case I40E_PHY_TYPE_10GBASE_AOC:
1296 case I40E_PHY_TYPE_25GBASE_CR:
1297 case I40E_PHY_TYPE_25GBASE_AOC:
1298 case I40E_PHY_TYPE_25GBASE_ACC:
1299 media = I40E_MEDIA_TYPE_DA;
1301 case I40E_PHY_TYPE_1000BASE_KX:
1302 case I40E_PHY_TYPE_10GBASE_KX4:
1303 case I40E_PHY_TYPE_10GBASE_KR:
1304 case I40E_PHY_TYPE_40GBASE_KR4:
1305 case I40E_PHY_TYPE_20GBASE_KR2:
1306 case I40E_PHY_TYPE_25GBASE_KR:
1307 media = I40E_MEDIA_TYPE_BACKPLANE;
1309 case I40E_PHY_TYPE_SGMII:
1310 case I40E_PHY_TYPE_XAUI:
1311 case I40E_PHY_TYPE_XFI:
1312 case I40E_PHY_TYPE_XLAUI:
1313 case I40E_PHY_TYPE_XLPPI:
1315 media = I40E_MEDIA_TYPE_UNKNOWN;
1323 * i40e_poll_globr - Poll for Global Reset completion
1324 * @hw: pointer to the hardware structure
1325 * @retry_limit: how many times to retry before failure
1327 STATIC enum i40e_status_code i40e_poll_globr(struct i40e_hw *hw,
1332 for (cnt = 0; cnt < retry_limit; cnt++) {
1333 reg = rd32(hw, I40E_GLGEN_RSTAT);
1334 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1335 return I40E_SUCCESS;
1336 i40e_msec_delay(100);
1339 DEBUGOUT("Global reset failed.\n");
1340 DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg);
1342 return I40E_ERR_RESET_FAILED;
1345 #define I40E_PF_RESET_WAIT_COUNT 200
1347 * i40e_pf_reset - Reset the PF
1348 * @hw: pointer to the hardware structure
1350 * Assuming someone else has triggered a global reset,
1351 * assure the global reset is complete and then reset the PF
1353 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1360 /* Poll for Global Reset steady state in case of recent GRST.
1361 * The grst delay value is in 100ms units, and we'll wait a
1362 * couple counts longer to be sure we don't just miss the end.
1364 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1365 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1366 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1368 grst_del = min(grst_del * 20, 160U);
1370 for (cnt = 0; cnt < grst_del; cnt++) {
1371 reg = rd32(hw, I40E_GLGEN_RSTAT);
1372 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1374 i40e_msec_delay(100);
1376 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1377 DEBUGOUT("Global reset polling failed to complete.\n");
1378 return I40E_ERR_RESET_FAILED;
1381 /* Now Wait for the FW to be ready */
1382 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1383 reg = rd32(hw, I40E_GLNVM_ULD);
1384 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1385 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1386 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1387 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1388 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1391 i40e_msec_delay(10);
1393 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1394 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1395 DEBUGOUT("wait for FW Reset complete timedout\n");
1396 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1397 return I40E_ERR_RESET_FAILED;
1400 /* If there was a Global Reset in progress when we got here,
1401 * we don't need to do the PF Reset
1406 reg = rd32(hw, I40E_PFGEN_CTRL);
1407 wr32(hw, I40E_PFGEN_CTRL,
1408 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1409 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1410 reg = rd32(hw, I40E_PFGEN_CTRL);
1411 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1413 reg2 = rd32(hw, I40E_GLGEN_RSTAT);
1414 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK)
1418 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1419 if (i40e_poll_globr(hw, grst_del) != I40E_SUCCESS)
1420 return I40E_ERR_RESET_FAILED;
1421 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1422 DEBUGOUT("PF reset polling failed to complete.\n");
1423 return I40E_ERR_RESET_FAILED;
1427 i40e_clear_pxe_mode(hw);
1430 return I40E_SUCCESS;
1434 * i40e_clear_hw - clear out any left over hw state
1435 * @hw: pointer to the hw struct
1437 * Clear queues and interrupts, typically called at init time,
1438 * but after the capabilities have been found so we know how many
1439 * queues and msix vectors have been allocated.
1441 void i40e_clear_hw(struct i40e_hw *hw)
1443 u32 num_queues, base_queue;
1451 /* get number of interrupts, queues, and vfs */
1452 val = rd32(hw, I40E_GLPCI_CNF2);
1453 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1454 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1455 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1456 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1458 val = rd32(hw, I40E_PFLAN_QALLOC);
1459 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1460 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1461 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1462 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1463 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1464 num_queues = (j - base_queue) + 1;
1468 val = rd32(hw, I40E_PF_VT_PFALLOC);
1469 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1470 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1471 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1472 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1473 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1474 num_vfs = (j - i) + 1;
1478 /* stop all the interrupts */
1479 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1480 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1481 for (i = 0; i < num_pf_int - 2; i++)
1482 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1484 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1485 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1486 wr32(hw, I40E_PFINT_LNKLST0, val);
1487 for (i = 0; i < num_pf_int - 2; i++)
1488 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1489 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1490 for (i = 0; i < num_vfs; i++)
1491 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1492 for (i = 0; i < num_vf_int - 2; i++)
1493 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1495 /* warn the HW of the coming Tx disables */
1496 for (i = 0; i < num_queues; i++) {
1497 u32 abs_queue_idx = base_queue + i;
1500 if (abs_queue_idx >= 128) {
1501 reg_block = abs_queue_idx / 128;
1502 abs_queue_idx %= 128;
1505 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1506 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1507 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1508 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1510 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1512 i40e_usec_delay(400);
1514 /* stop all the queues */
1515 for (i = 0; i < num_queues; i++) {
1516 wr32(hw, I40E_QINT_TQCTL(i), 0);
1517 wr32(hw, I40E_QTX_ENA(i), 0);
1518 wr32(hw, I40E_QINT_RQCTL(i), 0);
1519 wr32(hw, I40E_QRX_ENA(i), 0);
1522 /* short wait for all queue disables to settle */
1523 i40e_usec_delay(50);
1527 * i40e_clear_pxe_mode - clear pxe operations mode
1528 * @hw: pointer to the hw struct
1530 * Make sure all PXE mode settings are cleared, including things
1531 * like descriptor fetch/write-back mode.
1533 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1535 if (i40e_check_asq_alive(hw))
1536 i40e_aq_clear_pxe_mode(hw, NULL);
1540 * i40e_led_is_mine - helper to find matching led
1541 * @hw: pointer to the hw struct
1542 * @idx: index into GPIO registers
1544 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1546 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1551 if (!hw->func_caps.led[idx])
1554 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1555 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1556 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1558 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1559 * if it is not our port then ignore
1561 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1568 #define I40E_COMBINED_ACTIVITY 0xA
1569 #define I40E_FILTER_ACTIVITY 0xE
1570 #define I40E_LINK_ACTIVITY 0xC
1571 #define I40E_MAC_ACTIVITY 0xD
1572 #define I40E_LED0 22
1575 * i40e_led_get - return current on/off mode
1576 * @hw: pointer to the hw struct
1578 * The value returned is the 'mode' field as defined in the
1579 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1580 * values are variations of possible behaviors relating to
1581 * blink, link, and wire.
1583 u32 i40e_led_get(struct i40e_hw *hw)
1585 u32 current_mode = 0;
1589 /* as per the documentation GPIO 22-29 are the LED
1590 * GPIO pins named LED0..LED7
1592 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1593 u32 gpio_val = i40e_led_is_mine(hw, i);
1598 /* ignore gpio LED src mode entries related to the activity
1601 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1602 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1603 switch (current_mode) {
1604 case I40E_COMBINED_ACTIVITY:
1605 case I40E_FILTER_ACTIVITY:
1606 case I40E_MAC_ACTIVITY:
1607 case I40E_LINK_ACTIVITY:
1613 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1614 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1622 * i40e_led_set - set new on/off mode
1623 * @hw: pointer to the hw struct
1624 * @mode: 0=off, 0xf=on (else see manual for mode details)
1625 * @blink: true if the LED should blink when on, false if steady
1627 * if this function is used to turn on the blink it should
1628 * be used to disable the blink when restoring the original state.
1630 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1632 u32 current_mode = 0;
1635 if (mode & 0xfffffff0)
1636 DEBUGOUT1("invalid mode passed in %X\n", mode);
1638 /* as per the documentation GPIO 22-29 are the LED
1639 * GPIO pins named LED0..LED7
1641 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1642 u32 gpio_val = i40e_led_is_mine(hw, i);
1647 /* ignore gpio LED src mode entries related to the activity
1650 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1651 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1652 switch (current_mode) {
1653 case I40E_COMBINED_ACTIVITY:
1654 case I40E_FILTER_ACTIVITY:
1655 case I40E_MAC_ACTIVITY:
1656 case I40E_LINK_ACTIVITY:
1662 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1663 /* this & is a bit of paranoia, but serves as a range check */
1664 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1665 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1668 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1670 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1672 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1677 /* Admin command wrappers */
1680 * i40e_aq_get_phy_capabilities
1681 * @hw: pointer to the hw struct
1682 * @abilities: structure for PHY capabilities to be filled
1683 * @qualified_modules: report Qualified Modules
1684 * @report_init: report init capabilities (active are default)
1685 * @cmd_details: pointer to command details structure or NULL
1687 * Returns the various PHY abilities supported on the Port.
1689 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1690 bool qualified_modules, bool report_init,
1691 struct i40e_aq_get_phy_abilities_resp *abilities,
1692 struct i40e_asq_cmd_details *cmd_details)
1694 struct i40e_aq_desc desc;
1695 enum i40e_status_code status;
1696 u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0;
1697 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1700 return I40E_ERR_PARAM;
1703 i40e_fill_default_direct_cmd_desc(&desc,
1704 i40e_aqc_opc_get_phy_abilities);
1706 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1707 if (abilities_size > I40E_AQ_LARGE_BUF)
1708 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1710 if (qualified_modules)
1711 desc.params.external.param0 |=
1712 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1715 desc.params.external.param0 |=
1716 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1718 status = i40e_asq_send_command(hw, &desc, abilities,
1719 abilities_size, cmd_details);
1721 if (status != I40E_SUCCESS)
1724 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) {
1725 status = I40E_ERR_UNKNOWN_PHY;
1727 } else if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) {
1730 status = I40E_ERR_TIMEOUT;
1732 } while ((hw->aq.asq_last_status != I40E_AQ_RC_OK) &&
1733 (total_delay < max_delay));
1735 if (status != I40E_SUCCESS)
1739 if (hw->mac.type == I40E_MAC_XL710 &&
1740 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1741 hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
1742 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1744 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1745 hw->phy.phy_types |=
1746 ((u64)abilities->phy_type_ext << 32);
1754 * i40e_aq_set_phy_config
1755 * @hw: pointer to the hw struct
1756 * @config: structure with PHY configuration to be set
1757 * @cmd_details: pointer to command details structure or NULL
1759 * Set the various PHY configuration parameters
1760 * supported on the Port.One or more of the Set PHY config parameters may be
1761 * ignored in an MFP mode as the PF may not have the privilege to set some
1762 * of the PHY Config parameters. This status will be indicated by the
1765 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1766 struct i40e_aq_set_phy_config *config,
1767 struct i40e_asq_cmd_details *cmd_details)
1769 struct i40e_aq_desc desc;
1770 struct i40e_aq_set_phy_config *cmd =
1771 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1772 enum i40e_status_code status;
1775 return I40E_ERR_PARAM;
1777 i40e_fill_default_direct_cmd_desc(&desc,
1778 i40e_aqc_opc_set_phy_config);
1782 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1789 * @hw: pointer to the hw struct
1790 * @aq_failures: buffer to return AdminQ failure information
1791 * @atomic_restart: whether to enable atomic link restart
1793 * Set the requested flow control mode using set_phy_config.
1795 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1796 bool atomic_restart)
1798 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1799 struct i40e_aq_get_phy_abilities_resp abilities;
1800 struct i40e_aq_set_phy_config config;
1801 enum i40e_status_code status;
1802 u8 pause_mask = 0x0;
1808 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1809 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1811 case I40E_FC_RX_PAUSE:
1812 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1814 case I40E_FC_TX_PAUSE:
1815 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1821 /* Get the current phy config */
1822 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1825 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1829 memset(&config, 0, sizeof(config));
1830 /* clear the old pause settings */
1831 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1832 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1833 /* set the new abilities */
1834 config.abilities |= pause_mask;
1835 /* If the abilities have changed, then set the new config */
1836 if (config.abilities != abilities.abilities) {
1837 /* Auto restart link so settings take effect */
1839 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1840 /* Copy over all the old settings */
1841 config.phy_type = abilities.phy_type;
1842 config.phy_type_ext = abilities.phy_type_ext;
1843 config.link_speed = abilities.link_speed;
1844 config.eee_capability = abilities.eee_capability;
1845 config.eeer = abilities.eeer_val;
1846 config.low_power_ctrl = abilities.d3_lpan;
1847 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1848 I40E_AQ_PHY_FEC_CONFIG_MASK;
1849 status = i40e_aq_set_phy_config(hw, &config, NULL);
1852 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1854 /* Update the link info */
1855 status = i40e_update_link_info(hw);
1857 /* Wait a little bit (on 40G cards it sometimes takes a really
1858 * long time for link to come back from the atomic reset)
1861 i40e_msec_delay(1000);
1862 status = i40e_update_link_info(hw);
1865 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1871 * i40e_aq_set_mac_config
1872 * @hw: pointer to the hw struct
1873 * @max_frame_size: Maximum Frame Size to be supported by the port
1874 * @crc_en: Tell HW to append a CRC to outgoing frames
1875 * @pacing: Pacing configurations
1876 * @cmd_details: pointer to command details structure or NULL
1878 * Configure MAC settings for frame size, jumbo frame support and the
1879 * addition of a CRC by the hardware.
1881 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1883 bool crc_en, u16 pacing,
1884 struct i40e_asq_cmd_details *cmd_details)
1886 struct i40e_aq_desc desc;
1887 struct i40e_aq_set_mac_config *cmd =
1888 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1889 enum i40e_status_code status;
1891 if (max_frame_size == 0)
1892 return I40E_ERR_PARAM;
1894 i40e_fill_default_direct_cmd_desc(&desc,
1895 i40e_aqc_opc_set_mac_config);
1897 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1898 cmd->params = ((u8)pacing & 0x0F) << 3;
1900 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1902 #define I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD 0x7FFF
1903 cmd->fc_refresh_threshold =
1904 CPU_TO_LE16(I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD);
1906 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1912 * i40e_aq_clear_pxe_mode
1913 * @hw: pointer to the hw struct
1914 * @cmd_details: pointer to command details structure or NULL
1916 * Tell the firmware that the driver is taking over from PXE
1918 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1919 struct i40e_asq_cmd_details *cmd_details)
1921 enum i40e_status_code status;
1922 struct i40e_aq_desc desc;
1923 struct i40e_aqc_clear_pxe *cmd =
1924 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1926 i40e_fill_default_direct_cmd_desc(&desc,
1927 i40e_aqc_opc_clear_pxe_mode);
1931 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1933 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1939 * i40e_aq_set_link_restart_an
1940 * @hw: pointer to the hw struct
1941 * @enable_link: if true: enable link, if false: disable link
1942 * @cmd_details: pointer to command details structure or NULL
1944 * Sets up the link and restarts the Auto-Negotiation over the link.
1946 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1947 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1949 struct i40e_aq_desc desc;
1950 struct i40e_aqc_set_link_restart_an *cmd =
1951 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1952 enum i40e_status_code status;
1954 i40e_fill_default_direct_cmd_desc(&desc,
1955 i40e_aqc_opc_set_link_restart_an);
1957 cmd->command = I40E_AQ_PHY_RESTART_AN;
1959 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1961 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1963 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1969 * i40e_aq_get_link_info
1970 * @hw: pointer to the hw struct
1971 * @enable_lse: enable/disable LinkStatusEvent reporting
1972 * @link: pointer to link status structure - optional
1973 * @cmd_details: pointer to command details structure or NULL
1975 * Returns the link status of the adapter.
1977 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1978 bool enable_lse, struct i40e_link_status *link,
1979 struct i40e_asq_cmd_details *cmd_details)
1981 struct i40e_aq_desc desc;
1982 struct i40e_aqc_get_link_status *resp =
1983 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1984 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1985 enum i40e_status_code status;
1986 bool tx_pause, rx_pause;
1989 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1992 command_flags = I40E_AQ_LSE_ENABLE;
1994 command_flags = I40E_AQ_LSE_DISABLE;
1995 resp->command_flags = CPU_TO_LE16(command_flags);
1997 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1999 if (status != I40E_SUCCESS)
2000 goto aq_get_link_info_exit;
2002 /* save off old link status information */
2003 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
2004 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
2006 /* update link status */
2007 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
2008 hw->phy.media_type = i40e_get_media_type(hw);
2009 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
2010 hw_link_info->link_info = resp->link_info;
2011 hw_link_info->an_info = resp->an_info;
2012 hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
2013 I40E_AQ_CONFIG_FEC_RS_ENA);
2014 hw_link_info->ext_info = resp->ext_info;
2015 hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
2016 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
2017 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
2019 /* update fc info */
2020 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
2021 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
2022 if (tx_pause & rx_pause)
2023 hw->fc.current_mode = I40E_FC_FULL;
2025 hw->fc.current_mode = I40E_FC_TX_PAUSE;
2027 hw->fc.current_mode = I40E_FC_RX_PAUSE;
2029 hw->fc.current_mode = I40E_FC_NONE;
2031 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
2032 hw_link_info->crc_enable = true;
2034 hw_link_info->crc_enable = false;
2036 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
2037 hw_link_info->lse_enable = true;
2039 hw_link_info->lse_enable = false;
2041 if ((hw->mac.type == I40E_MAC_XL710) &&
2042 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
2043 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
2044 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
2046 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
2047 hw->aq.api_min_ver >= 7) {
2050 i40e_memcpy(&tmp, resp->link_type, sizeof(tmp),
2051 I40E_NONDMA_TO_NONDMA);
2052 hw->phy.phy_types = LE32_TO_CPU(tmp);
2053 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
2056 /* save link status information */
2058 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
2059 I40E_NONDMA_TO_NONDMA);
2061 /* flag cleared so helper functions don't call AQ again */
2062 hw->phy.get_link_info = false;
2064 aq_get_link_info_exit:
2069 * i40e_aq_set_phy_int_mask
2070 * @hw: pointer to the hw struct
2071 * @mask: interrupt mask to be set
2072 * @cmd_details: pointer to command details structure or NULL
2074 * Set link interrupt mask.
2076 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2078 struct i40e_asq_cmd_details *cmd_details)
2080 struct i40e_aq_desc desc;
2081 struct i40e_aqc_set_phy_int_mask *cmd =
2082 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2083 enum i40e_status_code status;
2085 i40e_fill_default_direct_cmd_desc(&desc,
2086 i40e_aqc_opc_set_phy_int_mask);
2088 cmd->event_mask = CPU_TO_LE16(mask);
2090 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2096 * i40e_aq_get_local_advt_reg
2097 * @hw: pointer to the hw struct
2098 * @advt_reg: local AN advertisement register value
2099 * @cmd_details: pointer to command details structure or NULL
2101 * Get the Local AN advertisement register value.
2103 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2105 struct i40e_asq_cmd_details *cmd_details)
2107 struct i40e_aq_desc desc;
2108 struct i40e_aqc_an_advt_reg *resp =
2109 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2110 enum i40e_status_code status;
2112 i40e_fill_default_direct_cmd_desc(&desc,
2113 i40e_aqc_opc_get_local_advt_reg);
2115 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2117 if (status != I40E_SUCCESS)
2118 goto aq_get_local_advt_reg_exit;
2120 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2121 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2123 aq_get_local_advt_reg_exit:
2128 * i40e_aq_set_local_advt_reg
2129 * @hw: pointer to the hw struct
2130 * @advt_reg: local AN advertisement register value
2131 * @cmd_details: pointer to command details structure or NULL
2133 * Get the Local AN advertisement register value.
2135 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2137 struct i40e_asq_cmd_details *cmd_details)
2139 struct i40e_aq_desc desc;
2140 struct i40e_aqc_an_advt_reg *cmd =
2141 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2142 enum i40e_status_code status;
2144 i40e_fill_default_direct_cmd_desc(&desc,
2145 i40e_aqc_opc_get_local_advt_reg);
2147 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2148 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2150 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2156 * i40e_aq_get_partner_advt
2157 * @hw: pointer to the hw struct
2158 * @advt_reg: AN partner advertisement register value
2159 * @cmd_details: pointer to command details structure or NULL
2161 * Get the link partner AN advertisement register value.
2163 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2165 struct i40e_asq_cmd_details *cmd_details)
2167 struct i40e_aq_desc desc;
2168 struct i40e_aqc_an_advt_reg *resp =
2169 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2170 enum i40e_status_code status;
2172 i40e_fill_default_direct_cmd_desc(&desc,
2173 i40e_aqc_opc_get_partner_advt);
2175 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2177 if (status != I40E_SUCCESS)
2178 goto aq_get_partner_advt_exit;
2180 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2181 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2183 aq_get_partner_advt_exit:
2188 * i40e_aq_set_lb_modes
2189 * @hw: pointer to the hw struct
2190 * @lb_modes: loopback mode to be set
2191 * @cmd_details: pointer to command details structure or NULL
2193 * Sets loopback modes.
2195 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2197 struct i40e_asq_cmd_details *cmd_details)
2199 struct i40e_aq_desc desc;
2200 struct i40e_aqc_set_lb_mode *cmd =
2201 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2202 enum i40e_status_code status;
2204 i40e_fill_default_direct_cmd_desc(&desc,
2205 i40e_aqc_opc_set_lb_modes);
2207 cmd->lb_mode = CPU_TO_LE16(lb_modes);
2209 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2215 * i40e_aq_set_phy_debug
2216 * @hw: pointer to the hw struct
2217 * @cmd_flags: debug command flags
2218 * @cmd_details: pointer to command details structure or NULL
2220 * Reset the external PHY.
2222 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2223 struct i40e_asq_cmd_details *cmd_details)
2225 struct i40e_aq_desc desc;
2226 struct i40e_aqc_set_phy_debug *cmd =
2227 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2228 enum i40e_status_code status;
2230 i40e_fill_default_direct_cmd_desc(&desc,
2231 i40e_aqc_opc_set_phy_debug);
2233 cmd->command_flags = cmd_flags;
2235 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2242 * @hw: pointer to the hw struct
2243 * @vsi_ctx: pointer to a vsi context struct
2244 * @cmd_details: pointer to command details structure or NULL
2246 * Add a VSI context to the hardware.
2248 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2249 struct i40e_vsi_context *vsi_ctx,
2250 struct i40e_asq_cmd_details *cmd_details)
2252 struct i40e_aq_desc desc;
2253 struct i40e_aqc_add_get_update_vsi *cmd =
2254 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2255 struct i40e_aqc_add_get_update_vsi_completion *resp =
2256 (struct i40e_aqc_add_get_update_vsi_completion *)
2258 enum i40e_status_code status;
2260 i40e_fill_default_direct_cmd_desc(&desc,
2261 i40e_aqc_opc_add_vsi);
2263 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2264 cmd->connection_type = vsi_ctx->connection_type;
2265 cmd->vf_id = vsi_ctx->vf_num;
2266 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2268 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2270 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2271 sizeof(vsi_ctx->info), cmd_details);
2273 if (status != I40E_SUCCESS)
2274 goto aq_add_vsi_exit;
2276 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2277 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2278 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2279 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2286 * i40e_aq_set_default_vsi
2287 * @hw: pointer to the hw struct
2289 * @cmd_details: pointer to command details structure or NULL
2291 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2293 struct i40e_asq_cmd_details *cmd_details)
2295 struct i40e_aq_desc desc;
2296 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2297 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2299 enum i40e_status_code status;
2301 i40e_fill_default_direct_cmd_desc(&desc,
2302 i40e_aqc_opc_set_vsi_promiscuous_modes);
2304 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2305 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2306 cmd->seid = CPU_TO_LE16(seid);
2308 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2314 * i40e_aq_clear_default_vsi
2315 * @hw: pointer to the hw struct
2317 * @cmd_details: pointer to command details structure or NULL
2319 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2321 struct i40e_asq_cmd_details *cmd_details)
2323 struct i40e_aq_desc desc;
2324 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2325 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2327 enum i40e_status_code status;
2329 i40e_fill_default_direct_cmd_desc(&desc,
2330 i40e_aqc_opc_set_vsi_promiscuous_modes);
2332 cmd->promiscuous_flags = CPU_TO_LE16(0);
2333 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2334 cmd->seid = CPU_TO_LE16(seid);
2336 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2342 * i40e_aq_set_vsi_unicast_promiscuous
2343 * @hw: pointer to the hw struct
2345 * @set: set unicast promiscuous enable/disable
2346 * @cmd_details: pointer to command details structure or NULL
2347 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2349 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2351 struct i40e_asq_cmd_details *cmd_details,
2352 bool rx_only_promisc)
2354 struct i40e_aq_desc desc;
2355 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2356 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2357 enum i40e_status_code status;
2360 i40e_fill_default_direct_cmd_desc(&desc,
2361 i40e_aqc_opc_set_vsi_promiscuous_modes);
2364 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2365 if (rx_only_promisc &&
2366 (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2367 (hw->aq.api_maj_ver > 1)))
2368 flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2371 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2373 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2374 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2375 (hw->aq.api_maj_ver > 1))
2376 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2378 cmd->seid = CPU_TO_LE16(seid);
2379 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2385 * i40e_aq_set_vsi_multicast_promiscuous
2386 * @hw: pointer to the hw struct
2388 * @set: set multicast promiscuous enable/disable
2389 * @cmd_details: pointer to command details structure or NULL
2391 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2392 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2394 struct i40e_aq_desc desc;
2395 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2396 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2397 enum i40e_status_code status;
2400 i40e_fill_default_direct_cmd_desc(&desc,
2401 i40e_aqc_opc_set_vsi_promiscuous_modes);
2404 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2406 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2408 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2410 cmd->seid = CPU_TO_LE16(seid);
2411 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2417 * i40e_aq_set_vsi_full_promiscuous
2418 * @hw: pointer to the hw struct
2420 * @set: set promiscuous enable/disable
2421 * @cmd_details: pointer to command details structure or NULL
2423 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw,
2425 struct i40e_asq_cmd_details *cmd_details)
2427 struct i40e_aq_desc desc;
2428 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2429 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2430 enum i40e_status_code status;
2433 i40e_fill_default_direct_cmd_desc(&desc,
2434 i40e_aqc_opc_set_vsi_promiscuous_modes);
2437 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST |
2438 I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2439 I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2441 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2443 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST |
2444 I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2445 I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2447 cmd->seid = CPU_TO_LE16(seid);
2448 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2454 * i40e_aq_set_vsi_mc_promisc_on_vlan
2455 * @hw: pointer to the hw struct
2457 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2458 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2459 * @cmd_details: pointer to command details structure or NULL
2461 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2462 u16 seid, bool enable, u16 vid,
2463 struct i40e_asq_cmd_details *cmd_details)
2465 struct i40e_aq_desc desc;
2466 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2467 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2468 enum i40e_status_code status;
2471 i40e_fill_default_direct_cmd_desc(&desc,
2472 i40e_aqc_opc_set_vsi_promiscuous_modes);
2475 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2477 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2478 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2479 cmd->seid = CPU_TO_LE16(seid);
2480 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2482 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2488 * i40e_aq_set_vsi_uc_promisc_on_vlan
2489 * @hw: pointer to the hw struct
2491 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2492 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2493 * @cmd_details: pointer to command details structure or NULL
2495 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2496 u16 seid, bool enable, u16 vid,
2497 struct i40e_asq_cmd_details *cmd_details)
2499 struct i40e_aq_desc desc;
2500 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2501 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2502 enum i40e_status_code status;
2505 i40e_fill_default_direct_cmd_desc(&desc,
2506 i40e_aqc_opc_set_vsi_promiscuous_modes);
2509 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2511 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2512 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2513 cmd->seid = CPU_TO_LE16(seid);
2514 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2516 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2522 * i40e_aq_set_vsi_bc_promisc_on_vlan
2523 * @hw: pointer to the hw struct
2525 * @enable: set broadcast promiscuous enable/disable for a given VLAN
2526 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2527 * @cmd_details: pointer to command details structure or NULL
2529 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2530 u16 seid, bool enable, u16 vid,
2531 struct i40e_asq_cmd_details *cmd_details)
2533 struct i40e_aq_desc desc;
2534 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2535 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2536 enum i40e_status_code status;
2539 i40e_fill_default_direct_cmd_desc(&desc,
2540 i40e_aqc_opc_set_vsi_promiscuous_modes);
2543 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2545 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2546 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2547 cmd->seid = CPU_TO_LE16(seid);
2548 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2550 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2556 * i40e_aq_set_vsi_broadcast
2557 * @hw: pointer to the hw struct
2559 * @set_filter: true to set filter, false to clear filter
2560 * @cmd_details: pointer to command details structure or NULL
2562 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2564 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2565 u16 seid, bool set_filter,
2566 struct i40e_asq_cmd_details *cmd_details)
2568 struct i40e_aq_desc desc;
2569 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2570 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2571 enum i40e_status_code status;
2573 i40e_fill_default_direct_cmd_desc(&desc,
2574 i40e_aqc_opc_set_vsi_promiscuous_modes);
2577 cmd->promiscuous_flags
2578 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2580 cmd->promiscuous_flags
2581 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2583 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2584 cmd->seid = CPU_TO_LE16(seid);
2585 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2591 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2592 * @hw: pointer to the hw struct
2594 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2595 * @cmd_details: pointer to command details structure or NULL
2597 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2598 u16 seid, bool enable,
2599 struct i40e_asq_cmd_details *cmd_details)
2601 struct i40e_aq_desc desc;
2602 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2603 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2604 enum i40e_status_code status;
2607 i40e_fill_default_direct_cmd_desc(&desc,
2608 i40e_aqc_opc_set_vsi_promiscuous_modes);
2610 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2612 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2613 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2614 cmd->seid = CPU_TO_LE16(seid);
2616 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2622 * i40e_get_vsi_params - get VSI configuration info
2623 * @hw: pointer to the hw struct
2624 * @vsi_ctx: pointer to a vsi context struct
2625 * @cmd_details: pointer to command details structure or NULL
2627 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2628 struct i40e_vsi_context *vsi_ctx,
2629 struct i40e_asq_cmd_details *cmd_details)
2631 struct i40e_aq_desc desc;
2632 struct i40e_aqc_add_get_update_vsi *cmd =
2633 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2634 struct i40e_aqc_add_get_update_vsi_completion *resp =
2635 (struct i40e_aqc_add_get_update_vsi_completion *)
2637 enum i40e_status_code status;
2639 UNREFERENCED_1PARAMETER(cmd_details);
2640 i40e_fill_default_direct_cmd_desc(&desc,
2641 i40e_aqc_opc_get_vsi_parameters);
2643 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2645 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2647 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2648 sizeof(vsi_ctx->info), NULL);
2650 if (status != I40E_SUCCESS)
2651 goto aq_get_vsi_params_exit;
2653 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2654 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2655 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2656 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2658 aq_get_vsi_params_exit:
2663 * i40e_aq_update_vsi_params
2664 * @hw: pointer to the hw struct
2665 * @vsi_ctx: pointer to a vsi context struct
2666 * @cmd_details: pointer to command details structure or NULL
2668 * Update a VSI context.
2670 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2671 struct i40e_vsi_context *vsi_ctx,
2672 struct i40e_asq_cmd_details *cmd_details)
2674 struct i40e_aq_desc desc;
2675 struct i40e_aqc_add_get_update_vsi *cmd =
2676 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2677 struct i40e_aqc_add_get_update_vsi_completion *resp =
2678 (struct i40e_aqc_add_get_update_vsi_completion *)
2680 enum i40e_status_code status;
2682 i40e_fill_default_direct_cmd_desc(&desc,
2683 i40e_aqc_opc_update_vsi_parameters);
2684 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2686 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2688 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2689 sizeof(vsi_ctx->info), cmd_details);
2691 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2692 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2698 * i40e_aq_get_switch_config
2699 * @hw: pointer to the hardware structure
2700 * @buf: pointer to the result buffer
2701 * @buf_size: length of input buffer
2702 * @start_seid: seid to start for the report, 0 == beginning
2703 * @cmd_details: pointer to command details structure or NULL
2705 * Fill the buf with switch configuration returned from AdminQ command
2707 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2708 struct i40e_aqc_get_switch_config_resp *buf,
2709 u16 buf_size, u16 *start_seid,
2710 struct i40e_asq_cmd_details *cmd_details)
2712 struct i40e_aq_desc desc;
2713 struct i40e_aqc_switch_seid *scfg =
2714 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2715 enum i40e_status_code status;
2717 i40e_fill_default_direct_cmd_desc(&desc,
2718 i40e_aqc_opc_get_switch_config);
2719 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2720 if (buf_size > I40E_AQ_LARGE_BUF)
2721 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2722 scfg->seid = CPU_TO_LE16(*start_seid);
2724 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2725 *start_seid = LE16_TO_CPU(scfg->seid);
2731 * i40e_aq_set_switch_config
2732 * @hw: pointer to the hardware structure
2733 * @flags: bit flag values to set
2734 * @mode: cloud filter mode
2735 * @valid_flags: which bit flags to set
2736 * @cmd_details: pointer to command details structure or NULL
2738 * Set switch configuration bits
2740 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2741 u16 flags, u16 valid_flags, u8 mode,
2742 struct i40e_asq_cmd_details *cmd_details)
2744 struct i40e_aq_desc desc;
2745 struct i40e_aqc_set_switch_config *scfg =
2746 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2747 enum i40e_status_code status;
2749 i40e_fill_default_direct_cmd_desc(&desc,
2750 i40e_aqc_opc_set_switch_config);
2751 scfg->flags = CPU_TO_LE16(flags);
2752 scfg->valid_flags = CPU_TO_LE16(valid_flags);
2754 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
2755 scfg->switch_tag = CPU_TO_LE16(hw->switch_tag);
2756 scfg->first_tag = CPU_TO_LE16(hw->first_tag);
2757 scfg->second_tag = CPU_TO_LE16(hw->second_tag);
2759 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2765 * i40e_aq_get_firmware_version
2766 * @hw: pointer to the hw struct
2767 * @fw_major_version: firmware major version
2768 * @fw_minor_version: firmware minor version
2769 * @fw_build: firmware build number
2770 * @api_major_version: major queue version
2771 * @api_minor_version: minor queue version
2772 * @cmd_details: pointer to command details structure or NULL
2774 * Get the firmware version from the admin queue commands
2776 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2777 u16 *fw_major_version, u16 *fw_minor_version,
2779 u16 *api_major_version, u16 *api_minor_version,
2780 struct i40e_asq_cmd_details *cmd_details)
2782 struct i40e_aq_desc desc;
2783 struct i40e_aqc_get_version *resp =
2784 (struct i40e_aqc_get_version *)&desc.params.raw;
2785 enum i40e_status_code status;
2787 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2789 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2791 if (status == I40E_SUCCESS) {
2792 if (fw_major_version != NULL)
2793 *fw_major_version = LE16_TO_CPU(resp->fw_major);
2794 if (fw_minor_version != NULL)
2795 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2796 if (fw_build != NULL)
2797 *fw_build = LE32_TO_CPU(resp->fw_build);
2798 if (api_major_version != NULL)
2799 *api_major_version = LE16_TO_CPU(resp->api_major);
2800 if (api_minor_version != NULL)
2801 *api_minor_version = LE16_TO_CPU(resp->api_minor);
2803 /* A workaround to fix the API version in SW */
2804 if (api_major_version && api_minor_version &&
2805 fw_major_version && fw_minor_version &&
2806 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2807 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2808 (*fw_major_version > 4)))
2809 *api_minor_version = 2;
2816 * i40e_aq_send_driver_version
2817 * @hw: pointer to the hw struct
2818 * @dv: driver's major, minor version
2819 * @cmd_details: pointer to command details structure or NULL
2821 * Send the driver version to the firmware
2823 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2824 struct i40e_driver_version *dv,
2825 struct i40e_asq_cmd_details *cmd_details)
2827 struct i40e_aq_desc desc;
2828 struct i40e_aqc_driver_version *cmd =
2829 (struct i40e_aqc_driver_version *)&desc.params.raw;
2830 enum i40e_status_code status;
2834 return I40E_ERR_PARAM;
2836 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2838 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2839 cmd->driver_major_ver = dv->major_version;
2840 cmd->driver_minor_ver = dv->minor_version;
2841 cmd->driver_build_ver = dv->build_version;
2842 cmd->driver_subbuild_ver = dv->subbuild_version;
2845 while (len < sizeof(dv->driver_string) &&
2846 (dv->driver_string[len] < 0x80) &&
2847 dv->driver_string[len])
2849 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2856 * i40e_get_link_status - get status of the HW network link
2857 * @hw: pointer to the hw struct
2858 * @link_up: pointer to bool (true/false = linkup/linkdown)
2860 * Variable link_up true if link is up, false if link is down.
2861 * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2863 * Side effect: LinkStatusEvent reporting becomes enabled
2865 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2867 enum i40e_status_code status = I40E_SUCCESS;
2869 if (hw->phy.get_link_info) {
2870 status = i40e_update_link_info(hw);
2872 if (status != I40E_SUCCESS)
2873 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2877 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2883 * i40e_updatelink_status - update status of the HW network link
2884 * @hw: pointer to the hw struct
2886 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2888 struct i40e_aq_get_phy_abilities_resp abilities;
2889 enum i40e_status_code status = I40E_SUCCESS;
2891 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2895 /* extra checking needed to ensure link info to user is timely */
2896 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2897 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2898 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2899 status = i40e_aq_get_phy_capabilities(hw, false, false,
2904 hw->phy.link_info.req_fec_info =
2905 abilities.fec_cfg_curr_mod_ext_info &
2906 (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS);
2908 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2909 sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2916 * i40e_get_link_speed
2917 * @hw: pointer to the hw struct
2919 * Returns the link speed of the adapter.
2921 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2923 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2924 enum i40e_status_code status = I40E_SUCCESS;
2926 if (hw->phy.get_link_info) {
2927 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2929 if (status != I40E_SUCCESS)
2930 goto i40e_link_speed_exit;
2933 speed = hw->phy.link_info.link_speed;
2935 i40e_link_speed_exit:
2940 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2941 * @hw: pointer to the hw struct
2942 * @uplink_seid: the MAC or other gizmo SEID
2943 * @downlink_seid: the VSI SEID
2944 * @enabled_tc: bitmap of TCs to be enabled
2945 * @default_port: true for default port VSI, false for control port
2946 * @veb_seid: pointer to where to put the resulting VEB SEID
2947 * @enable_stats: true to turn on VEB stats
2948 * @cmd_details: pointer to command details structure or NULL
2950 * This asks the FW to add a VEB between the uplink and downlink
2951 * elements. If the uplink SEID is 0, this will be a floating VEB.
2953 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2954 u16 downlink_seid, u8 enabled_tc,
2955 bool default_port, u16 *veb_seid,
2957 struct i40e_asq_cmd_details *cmd_details)
2959 struct i40e_aq_desc desc;
2960 struct i40e_aqc_add_veb *cmd =
2961 (struct i40e_aqc_add_veb *)&desc.params.raw;
2962 struct i40e_aqc_add_veb_completion *resp =
2963 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2964 enum i40e_status_code status;
2967 /* SEIDs need to either both be set or both be 0 for floating VEB */
2968 if (!!uplink_seid != !!downlink_seid)
2969 return I40E_ERR_PARAM;
2971 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2973 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2974 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2975 cmd->enable_tcs = enabled_tc;
2977 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2979 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2981 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2983 /* reverse logic here: set the bitflag to disable the stats */
2985 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2987 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2989 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2991 if (!status && veb_seid)
2992 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2998 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2999 * @hw: pointer to the hw struct
3000 * @veb_seid: the SEID of the VEB to query
3001 * @switch_id: the uplink switch id
3002 * @floating: set to true if the VEB is floating
3003 * @statistic_index: index of the stats counter block for this VEB
3004 * @vebs_used: number of VEB's used by function
3005 * @vebs_free: total VEB's not reserved by any function
3006 * @cmd_details: pointer to command details structure or NULL
3008 * This retrieves the parameters for a particular VEB, specified by
3009 * uplink_seid, and returns them to the caller.
3011 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
3012 u16 veb_seid, u16 *switch_id,
3013 bool *floating, u16 *statistic_index,
3014 u16 *vebs_used, u16 *vebs_free,
3015 struct i40e_asq_cmd_details *cmd_details)
3017 struct i40e_aq_desc desc;
3018 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
3019 (struct i40e_aqc_get_veb_parameters_completion *)
3021 enum i40e_status_code status;
3024 return I40E_ERR_PARAM;
3026 i40e_fill_default_direct_cmd_desc(&desc,
3027 i40e_aqc_opc_get_veb_parameters);
3028 cmd_resp->seid = CPU_TO_LE16(veb_seid);
3030 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3035 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
3036 if (statistic_index)
3037 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
3039 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
3041 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
3043 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
3045 if (flags & I40E_AQC_ADD_VEB_FLOATING)
3056 * i40e_aq_add_macvlan
3057 * @hw: pointer to the hw struct
3058 * @seid: VSI for the mac address
3059 * @mv_list: list of macvlans to be added
3060 * @count: length of the list
3061 * @cmd_details: pointer to command details structure or NULL
3063 * Add MAC/VLAN addresses to the HW filtering
3065 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
3066 struct i40e_aqc_add_macvlan_element_data *mv_list,
3067 u16 count, struct i40e_asq_cmd_details *cmd_details)
3069 struct i40e_aq_desc desc;
3070 struct i40e_aqc_macvlan *cmd =
3071 (struct i40e_aqc_macvlan *)&desc.params.raw;
3072 enum i40e_status_code status;
3076 if (count == 0 || !mv_list || !hw)
3077 return I40E_ERR_PARAM;
3079 buf_size = count * sizeof(*mv_list);
3081 /* prep the rest of the request */
3082 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
3083 cmd->num_addresses = CPU_TO_LE16(count);
3084 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3088 for (i = 0; i < count; i++)
3089 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
3091 CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
3093 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3094 if (buf_size > I40E_AQ_LARGE_BUF)
3095 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3097 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3104 * i40e_aq_remove_macvlan
3105 * @hw: pointer to the hw struct
3106 * @seid: VSI for the mac address
3107 * @mv_list: list of macvlans to be removed
3108 * @count: length of the list
3109 * @cmd_details: pointer to command details structure or NULL
3111 * Remove MAC/VLAN addresses from the HW filtering
3113 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
3114 struct i40e_aqc_remove_macvlan_element_data *mv_list,
3115 u16 count, struct i40e_asq_cmd_details *cmd_details)
3117 struct i40e_aq_desc desc;
3118 struct i40e_aqc_macvlan *cmd =
3119 (struct i40e_aqc_macvlan *)&desc.params.raw;
3120 enum i40e_status_code status;
3123 if (count == 0 || !mv_list || !hw)
3124 return I40E_ERR_PARAM;
3126 buf_size = count * sizeof(*mv_list);
3128 /* prep the rest of the request */
3129 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
3130 cmd->num_addresses = CPU_TO_LE16(count);
3131 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3135 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3136 if (buf_size > I40E_AQ_LARGE_BUF)
3137 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3139 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3146 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3147 * @hw: pointer to the hw struct
3148 * @opcode: AQ opcode for add or delete mirror rule
3149 * @sw_seid: Switch SEID (to which rule refers)
3150 * @rule_type: Rule Type (ingress/egress/VLAN)
3151 * @id: Destination VSI SEID or Rule ID
3152 * @count: length of the list
3153 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3154 * @cmd_details: pointer to command details structure or NULL
3155 * @rule_id: Rule ID returned from FW
3156 * @rules_used: Number of rules used in internal switch
3157 * @rules_free: Number of rules free in internal switch
3159 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3160 * VEBs/VEPA elements only
3162 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3163 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3164 u16 count, __le16 *mr_list,
3165 struct i40e_asq_cmd_details *cmd_details,
3166 u16 *rule_id, u16 *rules_used, u16 *rules_free)
3168 struct i40e_aq_desc desc;
3169 struct i40e_aqc_add_delete_mirror_rule *cmd =
3170 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3171 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3172 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3173 enum i40e_status_code status;
3176 buf_size = count * sizeof(*mr_list);
3178 /* prep the rest of the request */
3179 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3180 cmd->seid = CPU_TO_LE16(sw_seid);
3181 cmd->rule_type = CPU_TO_LE16(rule_type &
3182 I40E_AQC_MIRROR_RULE_TYPE_MASK);
3183 cmd->num_entries = CPU_TO_LE16(count);
3184 /* Dest VSI for add, rule_id for delete */
3185 cmd->destination = CPU_TO_LE16(id);
3187 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3189 if (buf_size > I40E_AQ_LARGE_BUF)
3190 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3193 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3195 if (status == I40E_SUCCESS ||
3196 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3198 *rule_id = LE16_TO_CPU(resp->rule_id);
3200 *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3202 *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3208 * i40e_aq_add_mirrorrule - add a mirror rule
3209 * @hw: pointer to the hw struct
3210 * @sw_seid: Switch SEID (to which rule refers)
3211 * @rule_type: Rule Type (ingress/egress/VLAN)
3212 * @dest_vsi: SEID of VSI to which packets will be mirrored
3213 * @count: length of the list
3214 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3215 * @cmd_details: pointer to command details structure or NULL
3216 * @rule_id: Rule ID returned from FW
3217 * @rules_used: Number of rules used in internal switch
3218 * @rules_free: Number of rules free in internal switch
3220 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3222 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3223 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3224 struct i40e_asq_cmd_details *cmd_details,
3225 u16 *rule_id, u16 *rules_used, u16 *rules_free)
3227 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3228 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3229 if (count == 0 || !mr_list)
3230 return I40E_ERR_PARAM;
3233 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3234 rule_type, dest_vsi, count, mr_list,
3235 cmd_details, rule_id, rules_used, rules_free);
3239 * i40e_aq_delete_mirrorrule - delete a mirror rule
3240 * @hw: pointer to the hw struct
3241 * @sw_seid: Switch SEID (to which rule refers)
3242 * @rule_type: Rule Type (ingress/egress/VLAN)
3243 * @count: length of the list
3244 * @rule_id: Rule ID that is returned in the receive desc as part of
3246 * @mr_list: list of mirrored VLAN IDs to be removed
3247 * @cmd_details: pointer to command details structure or NULL
3248 * @rules_used: Number of rules used in internal switch
3249 * @rules_free: Number of rules free in internal switch
3251 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3253 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3254 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3255 struct i40e_asq_cmd_details *cmd_details,
3256 u16 *rules_used, u16 *rules_free)
3258 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3259 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3260 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3261 * mirroring. For other rule_type, count and rule_type should
3264 if (count == 0 || !mr_list)
3265 return I40E_ERR_PARAM;
3268 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3269 rule_type, rule_id, count, mr_list,
3270 cmd_details, NULL, rules_used, rules_free);
3274 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3275 * @hw: pointer to the hw struct
3276 * @seid: VSI for the vlan filters
3277 * @v_list: list of vlan filters to be added
3278 * @count: length of the list
3279 * @cmd_details: pointer to command details structure or NULL
3281 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3282 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3283 u8 count, struct i40e_asq_cmd_details *cmd_details)
3285 struct i40e_aq_desc desc;
3286 struct i40e_aqc_macvlan *cmd =
3287 (struct i40e_aqc_macvlan *)&desc.params.raw;
3288 enum i40e_status_code status;
3291 if (count == 0 || !v_list || !hw)
3292 return I40E_ERR_PARAM;
3294 buf_size = count * sizeof(*v_list);
3296 /* prep the rest of the request */
3297 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3298 cmd->num_addresses = CPU_TO_LE16(count);
3299 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3303 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3304 if (buf_size > I40E_AQ_LARGE_BUF)
3305 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3307 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3314 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3315 * @hw: pointer to the hw struct
3316 * @seid: VSI for the vlan filters
3317 * @v_list: list of macvlans to be removed
3318 * @count: length of the list
3319 * @cmd_details: pointer to command details structure or NULL
3321 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3322 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3323 u8 count, struct i40e_asq_cmd_details *cmd_details)
3325 struct i40e_aq_desc desc;
3326 struct i40e_aqc_macvlan *cmd =
3327 (struct i40e_aqc_macvlan *)&desc.params.raw;
3328 enum i40e_status_code status;
3331 if (count == 0 || !v_list || !hw)
3332 return I40E_ERR_PARAM;
3334 buf_size = count * sizeof(*v_list);
3336 /* prep the rest of the request */
3337 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3338 cmd->num_addresses = CPU_TO_LE16(count);
3339 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3343 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3344 if (buf_size > I40E_AQ_LARGE_BUF)
3345 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3347 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3354 * i40e_aq_send_msg_to_vf
3355 * @hw: pointer to the hardware structure
3356 * @vfid: vf id to send msg
3357 * @v_opcode: opcodes for VF-PF communication
3358 * @v_retval: return error code
3359 * @msg: pointer to the msg buffer
3360 * @msglen: msg length
3361 * @cmd_details: pointer to command details
3365 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3366 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3367 struct i40e_asq_cmd_details *cmd_details)
3369 struct i40e_aq_desc desc;
3370 struct i40e_aqc_pf_vf_message *cmd =
3371 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3372 enum i40e_status_code status;
3374 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3375 cmd->id = CPU_TO_LE32(vfid);
3376 desc.cookie_high = CPU_TO_LE32(v_opcode);
3377 desc.cookie_low = CPU_TO_LE32(v_retval);
3378 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3380 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3382 if (msglen > I40E_AQ_LARGE_BUF)
3383 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3384 desc.datalen = CPU_TO_LE16(msglen);
3386 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3392 * i40e_aq_debug_read_register
3393 * @hw: pointer to the hw struct
3394 * @reg_addr: register address
3395 * @reg_val: register value
3396 * @cmd_details: pointer to command details structure or NULL
3398 * Read the register using the admin queue commands
3400 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3401 u32 reg_addr, u64 *reg_val,
3402 struct i40e_asq_cmd_details *cmd_details)
3404 struct i40e_aq_desc desc;
3405 struct i40e_aqc_debug_reg_read_write *cmd_resp =
3406 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3407 enum i40e_status_code status;
3409 if (reg_val == NULL)
3410 return I40E_ERR_PARAM;
3412 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3414 cmd_resp->address = CPU_TO_LE32(reg_addr);
3416 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3418 if (status == I40E_SUCCESS) {
3419 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3420 (u64)LE32_TO_CPU(cmd_resp->value_low);
3427 * i40e_aq_debug_write_register
3428 * @hw: pointer to the hw struct
3429 * @reg_addr: register address
3430 * @reg_val: register value
3431 * @cmd_details: pointer to command details structure or NULL
3433 * Write to a register using the admin queue commands
3435 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3436 u32 reg_addr, u64 reg_val,
3437 struct i40e_asq_cmd_details *cmd_details)
3439 struct i40e_aq_desc desc;
3440 struct i40e_aqc_debug_reg_read_write *cmd =
3441 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3442 enum i40e_status_code status;
3444 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3446 cmd->address = CPU_TO_LE32(reg_addr);
3447 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3448 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3450 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3456 * i40e_aq_request_resource
3457 * @hw: pointer to the hw struct
3458 * @resource: resource id
3459 * @access: access type
3460 * @sdp_number: resource number
3461 * @timeout: the maximum time in ms that the driver may hold the resource
3462 * @cmd_details: pointer to command details structure or NULL
3464 * requests common resource using the admin queue commands
3466 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3467 enum i40e_aq_resources_ids resource,
3468 enum i40e_aq_resource_access_type access,
3469 u8 sdp_number, u64 *timeout,
3470 struct i40e_asq_cmd_details *cmd_details)
3472 struct i40e_aq_desc desc;
3473 struct i40e_aqc_request_resource *cmd_resp =
3474 (struct i40e_aqc_request_resource *)&desc.params.raw;
3475 enum i40e_status_code status;
3477 DEBUGFUNC("i40e_aq_request_resource");
3479 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3481 cmd_resp->resource_id = CPU_TO_LE16(resource);
3482 cmd_resp->access_type = CPU_TO_LE16(access);
3483 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3485 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3486 /* The completion specifies the maximum time in ms that the driver
3487 * may hold the resource in the Timeout field.
3488 * If the resource is held by someone else, the command completes with
3489 * busy return value and the timeout field indicates the maximum time
3490 * the current owner of the resource has to free it.
3492 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3493 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3499 * i40e_aq_release_resource
3500 * @hw: pointer to the hw struct
3501 * @resource: resource id
3502 * @sdp_number: resource number
3503 * @cmd_details: pointer to command details structure or NULL
3505 * release common resource using the admin queue commands
3507 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3508 enum i40e_aq_resources_ids resource,
3510 struct i40e_asq_cmd_details *cmd_details)
3512 struct i40e_aq_desc desc;
3513 struct i40e_aqc_request_resource *cmd =
3514 (struct i40e_aqc_request_resource *)&desc.params.raw;
3515 enum i40e_status_code status;
3517 DEBUGFUNC("i40e_aq_release_resource");
3519 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3521 cmd->resource_id = CPU_TO_LE16(resource);
3522 cmd->resource_number = CPU_TO_LE32(sdp_number);
3524 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3531 * @hw: pointer to the hw struct
3532 * @module_pointer: module pointer location in words from the NVM beginning
3533 * @offset: byte offset from the module beginning
3534 * @length: length of the section to be read (in bytes from the offset)
3535 * @data: command buffer (size [bytes] = length)
3536 * @last_command: tells if this is the last command in a series
3537 * @cmd_details: pointer to command details structure or NULL
3539 * Read the NVM using the admin queue commands
3541 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3542 u32 offset, u16 length, void *data,
3544 struct i40e_asq_cmd_details *cmd_details)
3546 struct i40e_aq_desc desc;
3547 struct i40e_aqc_nvm_update *cmd =
3548 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3549 enum i40e_status_code status;
3551 DEBUGFUNC("i40e_aq_read_nvm");
3553 /* In offset the highest byte must be zeroed. */
3554 if (offset & 0xFF000000) {
3555 status = I40E_ERR_PARAM;
3556 goto i40e_aq_read_nvm_exit;
3559 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3561 /* If this is the last command in a series, set the proper flag. */
3563 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3564 cmd->module_pointer = module_pointer;
3565 cmd->offset = CPU_TO_LE32(offset);
3566 cmd->length = CPU_TO_LE16(length);
3568 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3569 if (length > I40E_AQ_LARGE_BUF)
3570 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3572 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3574 i40e_aq_read_nvm_exit:
3579 * i40e_aq_read_nvm_config - read an nvm config block
3580 * @hw: pointer to the hw struct
3581 * @cmd_flags: NVM access admin command bits
3582 * @field_id: field or feature id
3583 * @data: buffer for result
3584 * @buf_size: buffer size
3585 * @element_count: pointer to count of elements read by FW
3586 * @cmd_details: pointer to command details structure or NULL
3588 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3589 u8 cmd_flags, u32 field_id, void *data,
3590 u16 buf_size, u16 *element_count,
3591 struct i40e_asq_cmd_details *cmd_details)
3593 struct i40e_aq_desc desc;
3594 struct i40e_aqc_nvm_config_read *cmd =
3595 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3596 enum i40e_status_code status;
3598 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3599 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3600 if (buf_size > I40E_AQ_LARGE_BUF)
3601 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3603 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3604 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3605 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3606 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3608 cmd->element_id_msw = 0;
3610 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3612 if (!status && element_count)
3613 *element_count = LE16_TO_CPU(cmd->element_count);
3619 * i40e_aq_write_nvm_config - write an nvm config block
3620 * @hw: pointer to the hw struct
3621 * @cmd_flags: NVM access admin command bits
3622 * @data: buffer for result
3623 * @buf_size: buffer size
3624 * @element_count: count of elements to be written
3625 * @cmd_details: pointer to command details structure or NULL
3627 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3628 u8 cmd_flags, void *data, u16 buf_size,
3630 struct i40e_asq_cmd_details *cmd_details)
3632 struct i40e_aq_desc desc;
3633 struct i40e_aqc_nvm_config_write *cmd =
3634 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3635 enum i40e_status_code status;
3637 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3638 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3639 if (buf_size > I40E_AQ_LARGE_BUF)
3640 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3642 cmd->element_count = CPU_TO_LE16(element_count);
3643 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3644 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3650 * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3651 * @hw: pointer to the hw struct
3652 * @buff: buffer for result
3653 * @buff_size: buffer size
3654 * @cmd_details: pointer to command details structure or NULL
3656 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3657 void *buff, u16 buff_size,
3658 struct i40e_asq_cmd_details *cmd_details)
3660 struct i40e_aq_desc desc;
3661 enum i40e_status_code status;
3663 UNREFERENCED_2PARAMETER(buff, buff_size);
3665 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3666 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3667 if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3668 status = I40E_ERR_NOT_IMPLEMENTED;
3675 * @hw: pointer to the hw struct
3676 * @module_pointer: module pointer location in words from the NVM beginning
3677 * @offset: offset in the module (expressed in 4 KB from module's beginning)
3678 * @length: length of the section to be erased (expressed in 4 KB)
3679 * @last_command: tells if this is the last command in a series
3680 * @cmd_details: pointer to command details structure or NULL
3682 * Erase the NVM sector using the admin queue commands
3684 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3685 u32 offset, u16 length, bool last_command,
3686 struct i40e_asq_cmd_details *cmd_details)
3688 struct i40e_aq_desc desc;
3689 struct i40e_aqc_nvm_update *cmd =
3690 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3691 enum i40e_status_code status;
3693 DEBUGFUNC("i40e_aq_erase_nvm");
3695 /* In offset the highest byte must be zeroed. */
3696 if (offset & 0xFF000000) {
3697 status = I40E_ERR_PARAM;
3698 goto i40e_aq_erase_nvm_exit;
3701 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3703 /* If this is the last command in a series, set the proper flag. */
3705 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3706 cmd->module_pointer = module_pointer;
3707 cmd->offset = CPU_TO_LE32(offset);
3708 cmd->length = CPU_TO_LE16(length);
3710 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3712 i40e_aq_erase_nvm_exit:
3717 * i40e_parse_discover_capabilities
3718 * @hw: pointer to the hw struct
3719 * @buff: pointer to a buffer containing device/function capability records
3720 * @cap_count: number of capability records in the list
3721 * @list_type_opc: type of capabilities list to parse
3723 * Parse the device/function capabilities list.
3725 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3727 enum i40e_admin_queue_opc list_type_opc)
3729 struct i40e_aqc_list_capabilities_element_resp *cap;
3730 u32 valid_functions, num_functions;
3731 u32 number, logical_id, phys_id;
3732 struct i40e_hw_capabilities *p;
3733 enum i40e_status_code status;
3734 u16 id, ocp_cfg_word0;
3738 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3740 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3741 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3742 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3743 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3747 for (i = 0; i < cap_count; i++, cap++) {
3748 id = LE16_TO_CPU(cap->id);
3749 number = LE32_TO_CPU(cap->number);
3750 logical_id = LE32_TO_CPU(cap->logical_id);
3751 phys_id = LE32_TO_CPU(cap->phys_id);
3752 major_rev = cap->major_rev;
3755 case I40E_AQ_CAP_ID_SWITCH_MODE:
3756 p->switch_mode = number;
3757 i40e_debug(hw, I40E_DEBUG_INIT,
3758 "HW Capability: Switch mode = %d\n",
3761 case I40E_AQ_CAP_ID_MNG_MODE:
3762 p->management_mode = number;
3763 if (major_rev > 1) {
3764 p->mng_protocols_over_mctp = logical_id;
3765 i40e_debug(hw, I40E_DEBUG_INIT,
3766 "HW Capability: Protocols over MCTP = %d\n",
3767 p->mng_protocols_over_mctp);
3769 p->mng_protocols_over_mctp = 0;
3771 i40e_debug(hw, I40E_DEBUG_INIT,
3772 "HW Capability: Management Mode = %d\n",
3773 p->management_mode);
3775 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3776 p->npar_enable = number;
3777 i40e_debug(hw, I40E_DEBUG_INIT,
3778 "HW Capability: NPAR enable = %d\n",
3781 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3783 i40e_debug(hw, I40E_DEBUG_INIT,
3784 "HW Capability: OS2BMC = %d\n", p->os2bmc);
3786 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3787 p->valid_functions = number;
3788 i40e_debug(hw, I40E_DEBUG_INIT,
3789 "HW Capability: Valid Functions = %d\n",
3790 p->valid_functions);
3792 case I40E_AQ_CAP_ID_SRIOV:
3794 p->sr_iov_1_1 = true;
3795 i40e_debug(hw, I40E_DEBUG_INIT,
3796 "HW Capability: SR-IOV = %d\n",
3799 case I40E_AQ_CAP_ID_VF:
3800 p->num_vfs = number;
3801 p->vf_base_id = logical_id;
3802 i40e_debug(hw, I40E_DEBUG_INIT,
3803 "HW Capability: VF count = %d\n",
3805 i40e_debug(hw, I40E_DEBUG_INIT,
3806 "HW Capability: VF base_id = %d\n",
3809 case I40E_AQ_CAP_ID_VMDQ:
3812 i40e_debug(hw, I40E_DEBUG_INIT,
3813 "HW Capability: VMDQ = %d\n", p->vmdq);
3815 case I40E_AQ_CAP_ID_8021QBG:
3817 p->evb_802_1_qbg = true;
3818 i40e_debug(hw, I40E_DEBUG_INIT,
3819 "HW Capability: 802.1Qbg = %d\n", number);
3821 case I40E_AQ_CAP_ID_8021QBR:
3823 p->evb_802_1_qbh = true;
3824 i40e_debug(hw, I40E_DEBUG_INIT,
3825 "HW Capability: 802.1Qbh = %d\n", number);
3827 case I40E_AQ_CAP_ID_VSI:
3828 p->num_vsis = number;
3829 i40e_debug(hw, I40E_DEBUG_INIT,
3830 "HW Capability: VSI count = %d\n",
3833 case I40E_AQ_CAP_ID_DCB:
3836 p->enabled_tcmap = logical_id;
3839 i40e_debug(hw, I40E_DEBUG_INIT,
3840 "HW Capability: DCB = %d\n", p->dcb);
3841 i40e_debug(hw, I40E_DEBUG_INIT,
3842 "HW Capability: TC Mapping = %d\n",
3844 i40e_debug(hw, I40E_DEBUG_INIT,
3845 "HW Capability: TC Max = %d\n", p->maxtc);
3847 case I40E_AQ_CAP_ID_FCOE:
3850 i40e_debug(hw, I40E_DEBUG_INIT,
3851 "HW Capability: FCOE = %d\n", p->fcoe);
3853 case I40E_AQ_CAP_ID_ISCSI:
3856 i40e_debug(hw, I40E_DEBUG_INIT,
3857 "HW Capability: iSCSI = %d\n", p->iscsi);
3859 case I40E_AQ_CAP_ID_RSS:
3861 p->rss_table_size = number;
3862 p->rss_table_entry_width = logical_id;
3863 i40e_debug(hw, I40E_DEBUG_INIT,
3864 "HW Capability: RSS = %d\n", p->rss);
3865 i40e_debug(hw, I40E_DEBUG_INIT,
3866 "HW Capability: RSS table size = %d\n",
3868 i40e_debug(hw, I40E_DEBUG_INIT,
3869 "HW Capability: RSS table width = %d\n",
3870 p->rss_table_entry_width);
3872 case I40E_AQ_CAP_ID_RXQ:
3873 p->num_rx_qp = number;
3874 p->base_queue = phys_id;
3875 i40e_debug(hw, I40E_DEBUG_INIT,
3876 "HW Capability: Rx QP = %d\n", number);
3877 i40e_debug(hw, I40E_DEBUG_INIT,
3878 "HW Capability: base_queue = %d\n",
3881 case I40E_AQ_CAP_ID_TXQ:
3882 p->num_tx_qp = number;
3883 p->base_queue = phys_id;
3884 i40e_debug(hw, I40E_DEBUG_INIT,
3885 "HW Capability: Tx QP = %d\n", number);
3886 i40e_debug(hw, I40E_DEBUG_INIT,
3887 "HW Capability: base_queue = %d\n",
3890 case I40E_AQ_CAP_ID_MSIX:
3891 p->num_msix_vectors = number;
3892 i40e_debug(hw, I40E_DEBUG_INIT,
3893 "HW Capability: MSIX vector count = %d\n",
3894 p->num_msix_vectors);
3896 case I40E_AQ_CAP_ID_VF_MSIX:
3897 p->num_msix_vectors_vf = number;
3898 i40e_debug(hw, I40E_DEBUG_INIT,
3899 "HW Capability: MSIX VF vector count = %d\n",
3900 p->num_msix_vectors_vf);
3902 case I40E_AQ_CAP_ID_FLEX10:
3903 if (major_rev == 1) {
3905 p->flex10_enable = true;
3906 p->flex10_capable = true;
3909 /* Capability revision >= 2 */
3911 p->flex10_enable = true;
3913 p->flex10_capable = true;
3915 p->flex10_mode = logical_id;
3916 p->flex10_status = phys_id;
3917 i40e_debug(hw, I40E_DEBUG_INIT,
3918 "HW Capability: Flex10 mode = %d\n",
3920 i40e_debug(hw, I40E_DEBUG_INIT,
3921 "HW Capability: Flex10 status = %d\n",
3924 case I40E_AQ_CAP_ID_CEM:
3927 i40e_debug(hw, I40E_DEBUG_INIT,
3928 "HW Capability: CEM = %d\n", p->mgmt_cem);
3930 case I40E_AQ_CAP_ID_IWARP:
3933 i40e_debug(hw, I40E_DEBUG_INIT,
3934 "HW Capability: iWARP = %d\n", p->iwarp);
3936 case I40E_AQ_CAP_ID_LED:
3937 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3938 p->led[phys_id] = true;
3939 i40e_debug(hw, I40E_DEBUG_INIT,
3940 "HW Capability: LED - PIN %d\n", phys_id);
3942 case I40E_AQ_CAP_ID_SDP:
3943 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3944 p->sdp[phys_id] = true;
3945 i40e_debug(hw, I40E_DEBUG_INIT,
3946 "HW Capability: SDP - PIN %d\n", phys_id);
3948 case I40E_AQ_CAP_ID_MDIO:
3950 p->mdio_port_num = phys_id;
3951 p->mdio_port_mode = logical_id;
3953 i40e_debug(hw, I40E_DEBUG_INIT,
3954 "HW Capability: MDIO port number = %d\n",
3956 i40e_debug(hw, I40E_DEBUG_INIT,
3957 "HW Capability: MDIO port mode = %d\n",
3960 case I40E_AQ_CAP_ID_1588:
3962 p->ieee_1588 = true;
3963 i40e_debug(hw, I40E_DEBUG_INIT,
3964 "HW Capability: IEEE 1588 = %d\n",
3967 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3969 p->fd_filters_guaranteed = number;
3970 p->fd_filters_best_effort = logical_id;
3971 i40e_debug(hw, I40E_DEBUG_INIT,
3972 "HW Capability: Flow Director = 1\n");
3973 i40e_debug(hw, I40E_DEBUG_INIT,
3974 "HW Capability: Guaranteed FD filters = %d\n",
3975 p->fd_filters_guaranteed);
3977 case I40E_AQ_CAP_ID_WSR_PROT:
3978 p->wr_csr_prot = (u64)number;
3979 p->wr_csr_prot |= (u64)logical_id << 32;
3980 i40e_debug(hw, I40E_DEBUG_INIT,
3981 "HW Capability: wr_csr_prot = 0x%llX\n\n",
3982 (p->wr_csr_prot & 0xffff));
3984 case I40E_AQ_CAP_ID_NVM_MGMT:
3985 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3986 p->sec_rev_disabled = true;
3987 if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3988 p->update_disabled = true;
3990 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3991 hw->num_wol_proxy_filters = (u16)number;
3992 hw->wol_proxy_vsi_seid = (u16)logical_id;
3993 p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3994 if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3995 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3997 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3998 p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3999 i40e_debug(hw, I40E_DEBUG_INIT,
4000 "HW Capability: WOL proxy filters = %d\n",
4001 hw->num_wol_proxy_filters);
4009 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
4011 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
4014 /* count the enabled ports (aka the "not disabled" ports) */
4016 for (i = 0; i < 4; i++) {
4017 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
4020 /* use AQ read to get the physical register offset instead
4021 * of the port relative offset
4023 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
4024 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
4028 /* OCP cards case: if a mezz is removed the ethernet port is at
4029 * disabled state in PRTGEN_CNF register. Additional NVM read is
4030 * needed in order to check if we are dealing with OCP card.
4031 * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting
4032 * physical ports results in wrong partition id calculation and thus
4033 * not supporting WoL.
4035 if (hw->mac.type == I40E_MAC_X722) {
4036 if (i40e_acquire_nvm(hw, I40E_RESOURCE_READ) == I40E_SUCCESS) {
4037 status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR,
4038 2 * I40E_SR_OCP_CFG_WORD0,
4039 sizeof(ocp_cfg_word0),
4040 &ocp_cfg_word0, true, NULL);
4041 if (status == I40E_SUCCESS &&
4042 (ocp_cfg_word0 & I40E_SR_OCP_ENABLED))
4044 i40e_release_nvm(hw);
4048 valid_functions = p->valid_functions;
4050 while (valid_functions) {
4051 if (valid_functions & 1)
4053 valid_functions >>= 1;
4056 /* partition id is 1-based, and functions are evenly spread
4057 * across the ports as partitions
4059 if (hw->num_ports != 0) {
4060 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
4061 hw->num_partitions = num_functions / hw->num_ports;
4064 /* additional HW specific goodies that might
4065 * someday be HW version specific
4067 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
4071 * i40e_aq_discover_capabilities
4072 * @hw: pointer to the hw struct
4073 * @buff: a virtual buffer to hold the capabilities
4074 * @buff_size: Size of the virtual buffer
4075 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
4076 * @list_type_opc: capabilities type to discover - pass in the command opcode
4077 * @cmd_details: pointer to command details structure or NULL
4079 * Get the device capabilities descriptions from the firmware
4081 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
4082 void *buff, u16 buff_size, u16 *data_size,
4083 enum i40e_admin_queue_opc list_type_opc,
4084 struct i40e_asq_cmd_details *cmd_details)
4086 struct i40e_aqc_list_capabilites *cmd;
4087 struct i40e_aq_desc desc;
4088 enum i40e_status_code status = I40E_SUCCESS;
4090 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
4092 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
4093 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
4094 status = I40E_ERR_PARAM;
4098 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
4100 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4101 if (buff_size > I40E_AQ_LARGE_BUF)
4102 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4104 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4105 *data_size = LE16_TO_CPU(desc.datalen);
4110 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
4118 * i40e_aq_update_nvm
4119 * @hw: pointer to the hw struct
4120 * @module_pointer: module pointer location in words from the NVM beginning
4121 * @offset: byte offset from the module beginning
4122 * @length: length of the section to be written (in bytes from the offset)
4123 * @data: command buffer (size [bytes] = length)
4124 * @last_command: tells if this is the last command in a series
4125 * @preservation_flags: Preservation mode flags
4126 * @cmd_details: pointer to command details structure or NULL
4128 * Update the NVM using the admin queue commands
4130 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
4131 u32 offset, u16 length, void *data,
4132 bool last_command, u8 preservation_flags,
4133 struct i40e_asq_cmd_details *cmd_details)
4135 struct i40e_aq_desc desc;
4136 struct i40e_aqc_nvm_update *cmd =
4137 (struct i40e_aqc_nvm_update *)&desc.params.raw;
4138 enum i40e_status_code status;
4140 DEBUGFUNC("i40e_aq_update_nvm");
4142 /* In offset the highest byte must be zeroed. */
4143 if (offset & 0xFF000000) {
4144 status = I40E_ERR_PARAM;
4145 goto i40e_aq_update_nvm_exit;
4148 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4150 /* If this is the last command in a series, set the proper flag. */
4152 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
4153 if (hw->mac.type == I40E_MAC_X722) {
4154 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED)
4155 cmd->command_flags |=
4156 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED <<
4157 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4158 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL)
4159 cmd->command_flags |=
4160 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL <<
4161 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4163 cmd->module_pointer = module_pointer;
4164 cmd->offset = CPU_TO_LE32(offset);
4165 cmd->length = CPU_TO_LE16(length);
4167 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4168 if (length > I40E_AQ_LARGE_BUF)
4169 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4171 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
4173 i40e_aq_update_nvm_exit:
4178 * i40e_aq_rearrange_nvm
4179 * @hw: pointer to the hw struct
4180 * @rearrange_nvm: defines direction of rearrangement
4181 * @cmd_details: pointer to command details structure or NULL
4183 * Rearrange NVM structure, available only for transition FW
4185 enum i40e_status_code i40e_aq_rearrange_nvm(struct i40e_hw *hw,
4187 struct i40e_asq_cmd_details *cmd_details)
4189 struct i40e_aqc_nvm_update *cmd;
4190 enum i40e_status_code status;
4191 struct i40e_aq_desc desc;
4193 DEBUGFUNC("i40e_aq_rearrange_nvm");
4195 cmd = (struct i40e_aqc_nvm_update *)&desc.params.raw;
4197 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4199 rearrange_nvm &= (I40E_AQ_NVM_REARRANGE_TO_FLAT |
4200 I40E_AQ_NVM_REARRANGE_TO_STRUCT);
4202 if (!rearrange_nvm) {
4203 status = I40E_ERR_PARAM;
4204 goto i40e_aq_rearrange_nvm_exit;
4207 cmd->command_flags |= rearrange_nvm;
4208 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4210 i40e_aq_rearrange_nvm_exit:
4215 * i40e_aq_nvm_progress
4216 * @hw: pointer to the hw struct
4217 * @progress: pointer to progress returned from AQ
4218 * @cmd_details: pointer to command details structure or NULL
4220 * Gets progress of flash rearrangement process
4222 enum i40e_status_code i40e_aq_nvm_progress(struct i40e_hw *hw, u8 *progress,
4223 struct i40e_asq_cmd_details *cmd_details)
4225 enum i40e_status_code status;
4226 struct i40e_aq_desc desc;
4228 DEBUGFUNC("i40e_aq_nvm_progress");
4230 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_progress);
4231 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4232 *progress = desc.params.raw[0];
4237 * i40e_aq_get_lldp_mib
4238 * @hw: pointer to the hw struct
4239 * @bridge_type: type of bridge requested
4240 * @mib_type: Local, Remote or both Local and Remote MIBs
4241 * @buff: pointer to a user supplied buffer to store the MIB block
4242 * @buff_size: size of the buffer (in bytes)
4243 * @local_len : length of the returned Local LLDP MIB
4244 * @remote_len: length of the returned Remote LLDP MIB
4245 * @cmd_details: pointer to command details structure or NULL
4247 * Requests the complete LLDP MIB (entire packet).
4249 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4250 u8 mib_type, void *buff, u16 buff_size,
4251 u16 *local_len, u16 *remote_len,
4252 struct i40e_asq_cmd_details *cmd_details)
4254 struct i40e_aq_desc desc;
4255 struct i40e_aqc_lldp_get_mib *cmd =
4256 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4257 struct i40e_aqc_lldp_get_mib *resp =
4258 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4259 enum i40e_status_code status;
4261 if (buff_size == 0 || !buff)
4262 return I40E_ERR_PARAM;
4264 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4265 /* Indirect Command */
4266 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4268 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4269 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4270 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4272 desc.datalen = CPU_TO_LE16(buff_size);
4274 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4275 if (buff_size > I40E_AQ_LARGE_BUF)
4276 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4278 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4280 if (local_len != NULL)
4281 *local_len = LE16_TO_CPU(resp->local_len);
4282 if (remote_len != NULL)
4283 *remote_len = LE16_TO_CPU(resp->remote_len);
4290 * i40e_aq_set_lldp_mib - Set the LLDP MIB
4291 * @hw: pointer to the hw struct
4292 * @mib_type: Local, Remote or both Local and Remote MIBs
4293 * @buff: pointer to a user supplied buffer to store the MIB block
4294 * @buff_size: size of the buffer (in bytes)
4295 * @cmd_details: pointer to command details structure or NULL
4299 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4300 u8 mib_type, void *buff, u16 buff_size,
4301 struct i40e_asq_cmd_details *cmd_details)
4303 struct i40e_aq_desc desc;
4304 struct i40e_aqc_lldp_set_local_mib *cmd =
4305 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4306 enum i40e_status_code status;
4308 if (buff_size == 0 || !buff)
4309 return I40E_ERR_PARAM;
4311 i40e_fill_default_direct_cmd_desc(&desc,
4312 i40e_aqc_opc_lldp_set_local_mib);
4313 /* Indirect Command */
4314 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4315 if (buff_size > I40E_AQ_LARGE_BUF)
4316 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4317 desc.datalen = CPU_TO_LE16(buff_size);
4319 cmd->type = mib_type;
4320 cmd->length = CPU_TO_LE16(buff_size);
4321 cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)buff));
4322 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4324 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4329 * i40e_aq_cfg_lldp_mib_change_event
4330 * @hw: pointer to the hw struct
4331 * @enable_update: Enable or Disable event posting
4332 * @cmd_details: pointer to command details structure or NULL
4334 * Enable or Disable posting of an event on ARQ when LLDP MIB
4335 * associated with the interface changes
4337 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4339 struct i40e_asq_cmd_details *cmd_details)
4341 struct i40e_aq_desc desc;
4342 struct i40e_aqc_lldp_update_mib *cmd =
4343 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4344 enum i40e_status_code status;
4346 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4349 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4351 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4357 * i40e_aq_restore_lldp
4358 * @hw: pointer to the hw struct
4359 * @setting: pointer to factory setting variable or NULL
4360 * @restore: True if factory settings should be restored
4361 * @cmd_details: pointer to command details structure or NULL
4363 * Restore LLDP Agent factory settings if @restore set to True. In other case
4364 * only returns factory setting in AQ response.
4366 enum i40e_status_code
4367 i40e_aq_restore_lldp(struct i40e_hw *hw, u8 *setting, bool restore,
4368 struct i40e_asq_cmd_details *cmd_details)
4370 struct i40e_aq_desc desc;
4371 struct i40e_aqc_lldp_restore *cmd =
4372 (struct i40e_aqc_lldp_restore *)&desc.params.raw;
4373 enum i40e_status_code status;
4375 if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)) {
4376 i40e_debug(hw, I40E_DEBUG_ALL,
4377 "Restore LLDP not supported by current FW version.\n");
4378 return I40E_ERR_DEVICE_NOT_SUPPORTED;
4381 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_restore);
4384 cmd->command |= I40E_AQ_LLDP_AGENT_RESTORE;
4386 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4389 *setting = cmd->command & 1;
4396 * @hw: pointer to the hw struct
4397 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4398 * @persist: True if stop of LLDP should be persistent across power cycles
4399 * @cmd_details: pointer to command details structure or NULL
4401 * Stop or Shutdown the embedded LLDP Agent
4403 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4405 struct i40e_asq_cmd_details *cmd_details)
4407 struct i40e_aq_desc desc;
4408 struct i40e_aqc_lldp_stop *cmd =
4409 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4410 enum i40e_status_code status;
4412 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4415 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4418 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)
4419 cmd->command |= I40E_AQ_LLDP_AGENT_STOP_PERSIST;
4421 i40e_debug(hw, I40E_DEBUG_ALL,
4422 "Persistent Stop LLDP not supported by current FW version.\n");
4425 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4431 * i40e_aq_start_lldp
4432 * @hw: pointer to the hw struct
4433 * @persist: True if start of LLDP should be persistent across power cycles
4434 * @cmd_details: pointer to command details structure or NULL
4436 * Start the embedded LLDP Agent on all ports.
4438 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4440 struct i40e_asq_cmd_details *cmd_details)
4442 struct i40e_aq_desc desc;
4443 struct i40e_aqc_lldp_start *cmd =
4444 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4445 enum i40e_status_code status;
4447 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4449 cmd->command = I40E_AQ_LLDP_AGENT_START;
4452 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)
4453 cmd->command |= I40E_AQ_LLDP_AGENT_START_PERSIST;
4455 i40e_debug(hw, I40E_DEBUG_ALL,
4456 "Persistent Start LLDP not supported by current FW version.\n");
4459 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4465 * i40e_aq_set_dcb_parameters
4466 * @hw: pointer to the hw struct
4467 * @cmd_details: pointer to command details structure or NULL
4468 * @dcb_enable: True if DCB configuration needs to be applied
4471 enum i40e_status_code
4472 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable,
4473 struct i40e_asq_cmd_details *cmd_details)
4475 struct i40e_aq_desc desc;
4476 struct i40e_aqc_set_dcb_parameters *cmd =
4477 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw;
4478 enum i40e_status_code status;
4480 if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_STOPPABLE))
4481 return I40E_ERR_DEVICE_NOT_SUPPORTED;
4483 i40e_fill_default_direct_cmd_desc(&desc,
4484 i40e_aqc_opc_set_dcb_parameters);
4487 cmd->valid_flags = I40E_DCB_VALID;
4488 cmd->command = I40E_AQ_DCB_SET_AGENT;
4490 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4496 * i40e_aq_get_cee_dcb_config
4497 * @hw: pointer to the hw struct
4498 * @buff: response buffer that stores CEE operational configuration
4499 * @buff_size: size of the buffer passed
4500 * @cmd_details: pointer to command details structure or NULL
4502 * Get CEE DCBX mode operational configuration from firmware
4504 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4505 void *buff, u16 buff_size,
4506 struct i40e_asq_cmd_details *cmd_details)
4508 struct i40e_aq_desc desc;
4509 enum i40e_status_code status;
4511 if (buff_size == 0 || !buff)
4512 return I40E_ERR_PARAM;
4514 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4516 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4517 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4524 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4525 * @hw: pointer to the hw struct
4526 * @start_agent: True if DCBx Agent needs to be Started
4527 * False if DCBx Agent needs to be Stopped
4528 * @cmd_details: pointer to command details structure or NULL
4530 * Start/Stop the embedded dcbx Agent
4532 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4534 struct i40e_asq_cmd_details *cmd_details)
4536 struct i40e_aq_desc desc;
4537 struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4538 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4540 enum i40e_status_code status;
4542 i40e_fill_default_direct_cmd_desc(&desc,
4543 i40e_aqc_opc_lldp_stop_start_spec_agent);
4546 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4548 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4554 * i40e_aq_add_udp_tunnel
4555 * @hw: pointer to the hw struct
4556 * @udp_port: the UDP port to add in Host byte order
4557 * @protocol_index: protocol index type
4558 * @filter_index: pointer to filter index
4559 * @cmd_details: pointer to command details structure or NULL
4561 * Note: Firmware expects the udp_port value to be in Little Endian format,
4562 * and this function will call CPU_TO_LE16 to convert from Host byte order to
4563 * Little Endian order.
4565 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4566 u16 udp_port, u8 protocol_index,
4568 struct i40e_asq_cmd_details *cmd_details)
4570 struct i40e_aq_desc desc;
4571 struct i40e_aqc_add_udp_tunnel *cmd =
4572 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4573 struct i40e_aqc_del_udp_tunnel_completion *resp =
4574 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4575 enum i40e_status_code status;
4577 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4579 cmd->udp_port = CPU_TO_LE16(udp_port);
4580 cmd->protocol_type = protocol_index;
4582 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4584 if (!status && filter_index)
4585 *filter_index = resp->index;
4591 * i40e_aq_del_udp_tunnel
4592 * @hw: pointer to the hw struct
4593 * @index: filter index
4594 * @cmd_details: pointer to command details structure or NULL
4596 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4597 struct i40e_asq_cmd_details *cmd_details)
4599 struct i40e_aq_desc desc;
4600 struct i40e_aqc_remove_udp_tunnel *cmd =
4601 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4602 enum i40e_status_code status;
4604 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4608 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4614 * i40e_aq_get_switch_resource_alloc (0x0204)
4615 * @hw: pointer to the hw struct
4616 * @num_entries: pointer to u8 to store the number of resource entries returned
4617 * @buf: pointer to a user supplied buffer. This buffer must be large enough
4618 * to store the resource information for all resource types. Each
4619 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
4620 * @count: size, in bytes, of the buffer provided
4621 * @cmd_details: pointer to command details structure or NULL
4623 * Query the resources allocated to a function.
4625 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4627 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4629 struct i40e_asq_cmd_details *cmd_details)
4631 struct i40e_aq_desc desc;
4632 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4633 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4634 enum i40e_status_code status;
4635 u16 length = count * sizeof(*buf);
4637 i40e_fill_default_direct_cmd_desc(&desc,
4638 i40e_aqc_opc_get_switch_resource_alloc);
4640 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4641 if (length > I40E_AQ_LARGE_BUF)
4642 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4644 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4646 if (!status && num_entries)
4647 *num_entries = cmd_resp->num_entries;
4653 * i40e_aq_delete_element - Delete switch element
4654 * @hw: pointer to the hw struct
4655 * @seid: the SEID to delete from the switch
4656 * @cmd_details: pointer to command details structure or NULL
4658 * This deletes a switch element from the switch.
4660 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4661 struct i40e_asq_cmd_details *cmd_details)
4663 struct i40e_aq_desc desc;
4664 struct i40e_aqc_switch_seid *cmd =
4665 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4666 enum i40e_status_code status;
4669 return I40E_ERR_PARAM;
4671 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4673 cmd->seid = CPU_TO_LE16(seid);
4675 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4681 * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4682 * @hw: pointer to the hw struct
4683 * @flags: component flags
4684 * @mac_seid: uplink seid (MAC SEID)
4685 * @vsi_seid: connected vsi seid
4686 * @ret_seid: seid of create pv component
4688 * This instantiates an i40e port virtualizer with specified flags.
4689 * Depending on specified flags the port virtualizer can act as a
4690 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4692 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4693 u16 mac_seid, u16 vsi_seid,
4696 struct i40e_aq_desc desc;
4697 struct i40e_aqc_add_update_pv *cmd =
4698 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4699 struct i40e_aqc_add_update_pv_completion *resp =
4700 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4701 enum i40e_status_code status;
4704 return I40E_ERR_PARAM;
4706 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4707 cmd->command_flags = CPU_TO_LE16(flags);
4708 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4709 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4711 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4712 if (!status && ret_seid)
4713 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4719 * i40e_aq_add_tag - Add an S/E-tag
4720 * @hw: pointer to the hw struct
4721 * @direct_to_queue: should s-tag direct flow to a specific queue
4722 * @vsi_seid: VSI SEID to use this tag
4723 * @tag: value of the tag
4724 * @queue_num: queue number, only valid is direct_to_queue is true
4725 * @tags_used: return value, number of tags in use by this PF
4726 * @tags_free: return value, number of unallocated tags
4727 * @cmd_details: pointer to command details structure or NULL
4729 * This associates an S- or E-tag to a VSI in the switch complex. It returns
4730 * the number of tags allocated by the PF, and the number of unallocated
4733 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4734 u16 vsi_seid, u16 tag, u16 queue_num,
4735 u16 *tags_used, u16 *tags_free,
4736 struct i40e_asq_cmd_details *cmd_details)
4738 struct i40e_aq_desc desc;
4739 struct i40e_aqc_add_tag *cmd =
4740 (struct i40e_aqc_add_tag *)&desc.params.raw;
4741 struct i40e_aqc_add_remove_tag_completion *resp =
4742 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4743 enum i40e_status_code status;
4746 return I40E_ERR_PARAM;
4748 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4750 cmd->seid = CPU_TO_LE16(vsi_seid);
4751 cmd->tag = CPU_TO_LE16(tag);
4752 if (direct_to_queue) {
4753 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4754 cmd->queue_number = CPU_TO_LE16(queue_num);
4757 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4760 if (tags_used != NULL)
4761 *tags_used = LE16_TO_CPU(resp->tags_used);
4762 if (tags_free != NULL)
4763 *tags_free = LE16_TO_CPU(resp->tags_free);
4770 * i40e_aq_remove_tag - Remove an S- or E-tag
4771 * @hw: pointer to the hw struct
4772 * @vsi_seid: VSI SEID this tag is associated with
4773 * @tag: value of the S-tag to delete
4774 * @tags_used: return value, number of tags in use by this PF
4775 * @tags_free: return value, number of unallocated tags
4776 * @cmd_details: pointer to command details structure or NULL
4778 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
4779 * the number of tags allocated by the PF, and the number of unallocated
4782 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4783 u16 tag, u16 *tags_used, u16 *tags_free,
4784 struct i40e_asq_cmd_details *cmd_details)
4786 struct i40e_aq_desc desc;
4787 struct i40e_aqc_remove_tag *cmd =
4788 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4789 struct i40e_aqc_add_remove_tag_completion *resp =
4790 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4791 enum i40e_status_code status;
4794 return I40E_ERR_PARAM;
4796 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4798 cmd->seid = CPU_TO_LE16(vsi_seid);
4799 cmd->tag = CPU_TO_LE16(tag);
4801 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4804 if (tags_used != NULL)
4805 *tags_used = LE16_TO_CPU(resp->tags_used);
4806 if (tags_free != NULL)
4807 *tags_free = LE16_TO_CPU(resp->tags_free);
4814 * i40e_aq_add_mcast_etag - Add a multicast E-tag
4815 * @hw: pointer to the hw struct
4816 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4817 * @etag: value of E-tag to add
4818 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4819 * @buf: address of indirect buffer
4820 * @tags_used: return value, number of E-tags in use by this port
4821 * @tags_free: return value, number of unallocated M-tags
4822 * @cmd_details: pointer to command details structure or NULL
4824 * This associates a multicast E-tag to a port virtualizer. It will return
4825 * the number of tags allocated by the PF, and the number of unallocated
4828 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4829 * num_tags_in_buf long.
4831 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4832 u16 etag, u8 num_tags_in_buf, void *buf,
4833 u16 *tags_used, u16 *tags_free,
4834 struct i40e_asq_cmd_details *cmd_details)
4836 struct i40e_aq_desc desc;
4837 struct i40e_aqc_add_remove_mcast_etag *cmd =
4838 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4839 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4840 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4841 enum i40e_status_code status;
4842 u16 length = sizeof(u16) * num_tags_in_buf;
4844 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4845 return I40E_ERR_PARAM;
4847 i40e_fill_default_direct_cmd_desc(&desc,
4848 i40e_aqc_opc_add_multicast_etag);
4850 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4851 cmd->etag = CPU_TO_LE16(etag);
4852 cmd->num_unicast_etags = num_tags_in_buf;
4854 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4855 if (length > I40E_AQ_LARGE_BUF)
4856 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4858 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4861 if (tags_used != NULL)
4862 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4863 if (tags_free != NULL)
4864 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4871 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4872 * @hw: pointer to the hw struct
4873 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4874 * @etag: value of the E-tag to remove
4875 * @tags_used: return value, number of tags in use by this port
4876 * @tags_free: return value, number of unallocated tags
4877 * @cmd_details: pointer to command details structure or NULL
4879 * This deletes an E-tag from the port virtualizer. It will return
4880 * the number of tags allocated by the port, and the number of unallocated
4883 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4884 u16 etag, u16 *tags_used, u16 *tags_free,
4885 struct i40e_asq_cmd_details *cmd_details)
4887 struct i40e_aq_desc desc;
4888 struct i40e_aqc_add_remove_mcast_etag *cmd =
4889 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4890 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4891 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4892 enum i40e_status_code status;
4896 return I40E_ERR_PARAM;
4898 i40e_fill_default_direct_cmd_desc(&desc,
4899 i40e_aqc_opc_remove_multicast_etag);
4901 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4902 cmd->etag = CPU_TO_LE16(etag);
4904 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4907 if (tags_used != NULL)
4908 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4909 if (tags_free != NULL)
4910 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4917 * i40e_aq_update_tag - Update an S/E-tag
4918 * @hw: pointer to the hw struct
4919 * @vsi_seid: VSI SEID using this S-tag
4920 * @old_tag: old tag value
4921 * @new_tag: new tag value
4922 * @tags_used: return value, number of tags in use by this PF
4923 * @tags_free: return value, number of unallocated tags
4924 * @cmd_details: pointer to command details structure or NULL
4926 * This updates the value of the tag currently attached to this VSI
4927 * in the switch complex. It will return the number of tags allocated
4928 * by the PF, and the number of unallocated tags available.
4930 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4931 u16 old_tag, u16 new_tag, u16 *tags_used,
4933 struct i40e_asq_cmd_details *cmd_details)
4935 struct i40e_aq_desc desc;
4936 struct i40e_aqc_update_tag *cmd =
4937 (struct i40e_aqc_update_tag *)&desc.params.raw;
4938 struct i40e_aqc_update_tag_completion *resp =
4939 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4940 enum i40e_status_code status;
4943 return I40E_ERR_PARAM;
4945 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4947 cmd->seid = CPU_TO_LE16(vsi_seid);
4948 cmd->old_tag = CPU_TO_LE16(old_tag);
4949 cmd->new_tag = CPU_TO_LE16(new_tag);
4951 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4954 if (tags_used != NULL)
4955 *tags_used = LE16_TO_CPU(resp->tags_used);
4956 if (tags_free != NULL)
4957 *tags_free = LE16_TO_CPU(resp->tags_free);
4964 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4965 * @hw: pointer to the hw struct
4966 * @tcmap: TC map for request/release any ignore PFC condition
4967 * @request: request or release ignore PFC condition
4968 * @tcmap_ret: return TCs for which PFC is currently ignored
4969 * @cmd_details: pointer to command details structure or NULL
4971 * This sends out request/release to ignore PFC condition for a TC.
4972 * It will return the TCs for which PFC is currently ignored.
4974 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4975 bool request, u8 *tcmap_ret,
4976 struct i40e_asq_cmd_details *cmd_details)
4978 struct i40e_aq_desc desc;
4979 struct i40e_aqc_pfc_ignore *cmd_resp =
4980 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4981 enum i40e_status_code status;
4983 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4986 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4988 cmd_resp->tc_bitmap = tcmap;
4990 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4993 if (tcmap_ret != NULL)
4994 *tcmap_ret = cmd_resp->tc_bitmap;
5001 * i40e_aq_dcb_updated - DCB Updated Command
5002 * @hw: pointer to the hw struct
5003 * @cmd_details: pointer to command details structure or NULL
5005 * When LLDP is handled in PF this command is used by the PF
5006 * to notify EMP that a DCB setting is modified.
5007 * When LLDP is handled in EMP this command is used by the PF
5008 * to notify EMP whenever one of the following parameters get
5010 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
5011 * - PCIRTT in PRTDCB_GENC.PCIRTT
5012 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
5013 * EMP will return when the shared RPB settings have been
5014 * recomputed and modified. The retval field in the descriptor
5015 * will be set to 0 when RPB is modified.
5017 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
5018 struct i40e_asq_cmd_details *cmd_details)
5020 struct i40e_aq_desc desc;
5021 enum i40e_status_code status;
5023 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
5025 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5031 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
5032 * @hw: pointer to the hw struct
5033 * @seid: defines the SEID of the switch for which the stats are requested
5034 * @vlan_id: the VLAN ID for which the statistics are requested
5035 * @stat_index: index of the statistics counters block assigned to this VLAN
5036 * @cmd_details: pointer to command details structure or NULL
5038 * XL710 supports 128 smonVlanStats counters.This command is used to
5039 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
5042 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
5043 u16 vlan_id, u16 *stat_index,
5044 struct i40e_asq_cmd_details *cmd_details)
5046 struct i40e_aq_desc desc;
5047 struct i40e_aqc_add_remove_statistics *cmd_resp =
5048 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5049 enum i40e_status_code status;
5051 if ((seid == 0) || (stat_index == NULL))
5052 return I40E_ERR_PARAM;
5054 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
5056 cmd_resp->seid = CPU_TO_LE16(seid);
5057 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
5059 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5061 if (!status && stat_index)
5062 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
5068 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
5069 * @hw: pointer to the hw struct
5070 * @seid: defines the SEID of the switch for which the stats are requested
5071 * @vlan_id: the VLAN ID for which the statistics are requested
5072 * @stat_index: index of the statistics counters block assigned to this VLAN
5073 * @cmd_details: pointer to command details structure or NULL
5075 * XL710 supports 128 smonVlanStats counters.This command is used to
5076 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
5079 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
5080 u16 vlan_id, u16 stat_index,
5081 struct i40e_asq_cmd_details *cmd_details)
5083 struct i40e_aq_desc desc;
5084 struct i40e_aqc_add_remove_statistics *cmd =
5085 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5086 enum i40e_status_code status;
5089 return I40E_ERR_PARAM;
5091 i40e_fill_default_direct_cmd_desc(&desc,
5092 i40e_aqc_opc_remove_statistics);
5094 cmd->seid = CPU_TO_LE16(seid);
5095 cmd->vlan = CPU_TO_LE16(vlan_id);
5096 cmd->stat_index = CPU_TO_LE16(stat_index);
5098 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5104 * i40e_aq_set_port_parameters - set physical port parameters.
5105 * @hw: pointer to the hw struct
5106 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
5107 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
5108 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
5109 * @double_vlan: if set double VLAN is enabled
5110 * @cmd_details: pointer to command details structure or NULL
5112 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
5113 u16 bad_frame_vsi, bool save_bad_pac,
5114 bool pad_short_pac, bool double_vlan,
5115 struct i40e_asq_cmd_details *cmd_details)
5117 struct i40e_aqc_set_port_parameters *cmd;
5118 enum i40e_status_code status;
5119 struct i40e_aq_desc desc;
5120 u16 command_flags = 0;
5122 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
5124 i40e_fill_default_direct_cmd_desc(&desc,
5125 i40e_aqc_opc_set_port_parameters);
5127 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
5129 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
5131 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
5133 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
5134 cmd->command_flags = CPU_TO_LE16(command_flags);
5136 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5142 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
5143 * @hw: pointer to the hw struct
5144 * @seid: seid for the physical port/switching component/vsi
5145 * @buff: Indirect buffer to hold data parameters and response
5146 * @buff_size: Indirect buffer size
5147 * @opcode: Tx scheduler AQ command opcode
5148 * @cmd_details: pointer to command details structure or NULL
5150 * Generic command handler for Tx scheduler AQ commands
5152 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
5153 void *buff, u16 buff_size,
5154 enum i40e_admin_queue_opc opcode,
5155 struct i40e_asq_cmd_details *cmd_details)
5157 struct i40e_aq_desc desc;
5158 struct i40e_aqc_tx_sched_ind *cmd =
5159 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
5160 enum i40e_status_code status;
5161 bool cmd_param_flag = false;
5164 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
5165 case i40e_aqc_opc_configure_vsi_tc_bw:
5166 case i40e_aqc_opc_enable_switching_comp_ets:
5167 case i40e_aqc_opc_modify_switching_comp_ets:
5168 case i40e_aqc_opc_disable_switching_comp_ets:
5169 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
5170 case i40e_aqc_opc_configure_switching_comp_bw_config:
5171 cmd_param_flag = true;
5173 case i40e_aqc_opc_query_vsi_bw_config:
5174 case i40e_aqc_opc_query_vsi_ets_sla_config:
5175 case i40e_aqc_opc_query_switching_comp_ets_config:
5176 case i40e_aqc_opc_query_port_ets_config:
5177 case i40e_aqc_opc_query_switching_comp_bw_config:
5178 cmd_param_flag = false;
5181 return I40E_ERR_PARAM;
5184 i40e_fill_default_direct_cmd_desc(&desc, opcode);
5186 /* Indirect command */
5187 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5189 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5190 if (buff_size > I40E_AQ_LARGE_BUF)
5191 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5193 desc.datalen = CPU_TO_LE16(buff_size);
5195 cmd->vsi_seid = CPU_TO_LE16(seid);
5197 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5203 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5204 * @hw: pointer to the hw struct
5206 * @credit: BW limit credits (0 = disabled)
5207 * @max_credit: Max BW limit credits
5208 * @cmd_details: pointer to command details structure or NULL
5210 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5211 u16 seid, u16 credit, u8 max_credit,
5212 struct i40e_asq_cmd_details *cmd_details)
5214 struct i40e_aq_desc desc;
5215 struct i40e_aqc_configure_vsi_bw_limit *cmd =
5216 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5217 enum i40e_status_code status;
5219 i40e_fill_default_direct_cmd_desc(&desc,
5220 i40e_aqc_opc_configure_vsi_bw_limit);
5222 cmd->vsi_seid = CPU_TO_LE16(seid);
5223 cmd->credit = CPU_TO_LE16(credit);
5224 cmd->max_credit = max_credit;
5226 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5232 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5233 * @hw: pointer to the hw struct
5234 * @seid: switching component seid
5235 * @credit: BW limit credits (0 = disabled)
5236 * @max_bw: Max BW limit credits
5237 * @cmd_details: pointer to command details structure or NULL
5239 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5240 u16 seid, u16 credit, u8 max_bw,
5241 struct i40e_asq_cmd_details *cmd_details)
5243 struct i40e_aq_desc desc;
5244 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5245 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5246 enum i40e_status_code status;
5248 i40e_fill_default_direct_cmd_desc(&desc,
5249 i40e_aqc_opc_configure_switching_comp_bw_limit);
5251 cmd->seid = CPU_TO_LE16(seid);
5252 cmd->credit = CPU_TO_LE16(credit);
5253 cmd->max_bw = max_bw;
5255 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5261 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5262 * @hw: pointer to the hw struct
5264 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5265 * @cmd_details: pointer to command details structure or NULL
5267 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5269 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5270 struct i40e_asq_cmd_details *cmd_details)
5272 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5273 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5278 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5279 * @hw: pointer to the hw struct
5281 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5282 * @cmd_details: pointer to command details structure or NULL
5284 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5286 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5287 struct i40e_asq_cmd_details *cmd_details)
5289 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5290 i40e_aqc_opc_configure_vsi_tc_bw,
5295 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5296 * @hw: pointer to the hw struct
5297 * @seid: seid of the switching component connected to Physical Port
5298 * @ets_data: Buffer holding ETS parameters
5299 * @opcode: Tx scheduler AQ command opcode
5300 * @cmd_details: pointer to command details structure or NULL
5302 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5304 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5305 enum i40e_admin_queue_opc opcode,
5306 struct i40e_asq_cmd_details *cmd_details)
5308 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5309 sizeof(*ets_data), opcode, cmd_details);
5313 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5314 * @hw: pointer to the hw struct
5315 * @seid: seid of the switching component
5316 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5317 * @cmd_details: pointer to command details structure or NULL
5319 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5321 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5322 struct i40e_asq_cmd_details *cmd_details)
5324 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5325 i40e_aqc_opc_configure_switching_comp_bw_config,
5330 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5331 * @hw: pointer to the hw struct
5332 * @seid: seid of the switching component
5333 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5334 * @cmd_details: pointer to command details structure or NULL
5336 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5337 struct i40e_hw *hw, u16 seid,
5338 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5339 struct i40e_asq_cmd_details *cmd_details)
5341 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5342 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5347 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5348 * @hw: pointer to the hw struct
5349 * @seid: seid of the VSI
5350 * @bw_data: Buffer to hold VSI BW configuration
5351 * @cmd_details: pointer to command details structure or NULL
5353 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5355 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5356 struct i40e_asq_cmd_details *cmd_details)
5358 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5359 i40e_aqc_opc_query_vsi_bw_config,
5364 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5365 * @hw: pointer to the hw struct
5366 * @seid: seid of the VSI
5367 * @bw_data: Buffer to hold VSI BW configuration per TC
5368 * @cmd_details: pointer to command details structure or NULL
5370 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5372 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5373 struct i40e_asq_cmd_details *cmd_details)
5375 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5376 i40e_aqc_opc_query_vsi_ets_sla_config,
5381 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5382 * @hw: pointer to the hw struct
5383 * @seid: seid of the switching component
5384 * @bw_data: Buffer to hold switching component's per TC BW config
5385 * @cmd_details: pointer to command details structure or NULL
5387 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5389 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5390 struct i40e_asq_cmd_details *cmd_details)
5392 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5393 i40e_aqc_opc_query_switching_comp_ets_config,
5398 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5399 * @hw: pointer to the hw struct
5400 * @seid: seid of the VSI or switching component connected to Physical Port
5401 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5402 * @cmd_details: pointer to command details structure or NULL
5404 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5406 struct i40e_aqc_query_port_ets_config_resp *bw_data,
5407 struct i40e_asq_cmd_details *cmd_details)
5409 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5410 i40e_aqc_opc_query_port_ets_config,
5415 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5416 * @hw: pointer to the hw struct
5417 * @seid: seid of the switching component
5418 * @bw_data: Buffer to hold switching component's BW configuration
5419 * @cmd_details: pointer to command details structure or NULL
5421 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5423 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5424 struct i40e_asq_cmd_details *cmd_details)
5426 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5427 i40e_aqc_opc_query_switching_comp_bw_config,
5432 * i40e_validate_filter_settings
5433 * @hw: pointer to the hardware structure
5434 * @settings: Filter control settings
5436 * Check and validate the filter control settings passed.
5437 * The function checks for the valid filter/context sizes being
5438 * passed for FCoE and PE.
5440 * Returns I40E_SUCCESS if the values passed are valid and within
5441 * range else returns an error.
5443 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5444 struct i40e_filter_control_settings *settings)
5446 u32 fcoe_cntx_size, fcoe_filt_size;
5447 u32 pe_cntx_size, pe_filt_size;
5452 /* Validate FCoE settings passed */
5453 switch (settings->fcoe_filt_num) {
5454 case I40E_HASH_FILTER_SIZE_1K:
5455 case I40E_HASH_FILTER_SIZE_2K:
5456 case I40E_HASH_FILTER_SIZE_4K:
5457 case I40E_HASH_FILTER_SIZE_8K:
5458 case I40E_HASH_FILTER_SIZE_16K:
5459 case I40E_HASH_FILTER_SIZE_32K:
5460 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5461 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5464 return I40E_ERR_PARAM;
5467 switch (settings->fcoe_cntx_num) {
5468 case I40E_DMA_CNTX_SIZE_512:
5469 case I40E_DMA_CNTX_SIZE_1K:
5470 case I40E_DMA_CNTX_SIZE_2K:
5471 case I40E_DMA_CNTX_SIZE_4K:
5472 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5473 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5476 return I40E_ERR_PARAM;
5479 /* Validate PE settings passed */
5480 switch (settings->pe_filt_num) {
5481 case I40E_HASH_FILTER_SIZE_1K:
5482 case I40E_HASH_FILTER_SIZE_2K:
5483 case I40E_HASH_FILTER_SIZE_4K:
5484 case I40E_HASH_FILTER_SIZE_8K:
5485 case I40E_HASH_FILTER_SIZE_16K:
5486 case I40E_HASH_FILTER_SIZE_32K:
5487 case I40E_HASH_FILTER_SIZE_64K:
5488 case I40E_HASH_FILTER_SIZE_128K:
5489 case I40E_HASH_FILTER_SIZE_256K:
5490 case I40E_HASH_FILTER_SIZE_512K:
5491 case I40E_HASH_FILTER_SIZE_1M:
5492 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5493 pe_filt_size <<= (u32)settings->pe_filt_num;
5496 return I40E_ERR_PARAM;
5499 switch (settings->pe_cntx_num) {
5500 case I40E_DMA_CNTX_SIZE_512:
5501 case I40E_DMA_CNTX_SIZE_1K:
5502 case I40E_DMA_CNTX_SIZE_2K:
5503 case I40E_DMA_CNTX_SIZE_4K:
5504 case I40E_DMA_CNTX_SIZE_8K:
5505 case I40E_DMA_CNTX_SIZE_16K:
5506 case I40E_DMA_CNTX_SIZE_32K:
5507 case I40E_DMA_CNTX_SIZE_64K:
5508 case I40E_DMA_CNTX_SIZE_128K:
5509 case I40E_DMA_CNTX_SIZE_256K:
5510 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5511 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5514 return I40E_ERR_PARAM;
5517 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5518 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5519 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5520 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5521 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
5522 return I40E_ERR_INVALID_SIZE;
5524 return I40E_SUCCESS;
5528 * i40e_set_filter_control
5529 * @hw: pointer to the hardware structure
5530 * @settings: Filter control settings
5532 * Set the Queue Filters for PE/FCoE and enable filters required
5533 * for a single PF. It is expected that these settings are programmed
5534 * at the driver initialization time.
5536 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5537 struct i40e_filter_control_settings *settings)
5539 enum i40e_status_code ret = I40E_SUCCESS;
5540 u32 hash_lut_size = 0;
5544 return I40E_ERR_PARAM;
5546 /* Validate the input settings */
5547 ret = i40e_validate_filter_settings(hw, settings);
5551 /* Read the PF Queue Filter control register */
5552 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5554 /* Program required PE hash buckets for the PF */
5555 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5556 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5557 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5558 /* Program required PE contexts for the PF */
5559 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5560 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5561 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5563 /* Program required FCoE hash buckets for the PF */
5564 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5565 val |= ((u32)settings->fcoe_filt_num <<
5566 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5567 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5568 /* Program required FCoE DDP contexts for the PF */
5569 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5570 val |= ((u32)settings->fcoe_cntx_num <<
5571 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5572 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5574 /* Program Hash LUT size for the PF */
5575 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5576 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5578 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5579 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5581 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5582 if (settings->enable_fdir)
5583 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5584 if (settings->enable_ethtype)
5585 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5586 if (settings->enable_macvlan)
5587 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5589 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5591 return I40E_SUCCESS;
5595 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5596 * @hw: pointer to the hw struct
5597 * @mac_addr: MAC address to use in the filter
5598 * @ethtype: Ethertype to use in the filter
5599 * @flags: Flags that needs to be applied to the filter
5600 * @vsi_seid: seid of the control VSI
5601 * @queue: VSI queue number to send the packet to
5602 * @is_add: Add control packet filter if True else remove
5603 * @stats: Structure to hold information on control filter counts
5604 * @cmd_details: pointer to command details structure or NULL
5606 * This command will Add or Remove control packet filter for a control VSI.
5607 * In return it will update the total number of perfect filter count in
5610 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5611 u8 *mac_addr, u16 ethtype, u16 flags,
5612 u16 vsi_seid, u16 queue, bool is_add,
5613 struct i40e_control_filter_stats *stats,
5614 struct i40e_asq_cmd_details *cmd_details)
5616 struct i40e_aq_desc desc;
5617 struct i40e_aqc_add_remove_control_packet_filter *cmd =
5618 (struct i40e_aqc_add_remove_control_packet_filter *)
5620 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5621 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5623 enum i40e_status_code status;
5626 return I40E_ERR_PARAM;
5629 i40e_fill_default_direct_cmd_desc(&desc,
5630 i40e_aqc_opc_add_control_packet_filter);
5631 cmd->queue = CPU_TO_LE16(queue);
5633 i40e_fill_default_direct_cmd_desc(&desc,
5634 i40e_aqc_opc_remove_control_packet_filter);
5638 i40e_memcpy(cmd->mac, mac_addr, ETH_ALEN,
5639 I40E_NONDMA_TO_NONDMA);
5641 cmd->etype = CPU_TO_LE16(ethtype);
5642 cmd->flags = CPU_TO_LE16(flags);
5643 cmd->seid = CPU_TO_LE16(vsi_seid);
5645 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5647 if (!status && stats) {
5648 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5649 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5650 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5651 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5658 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5659 * @hw: pointer to the hw struct
5660 * @seid: VSI seid to add ethertype filter from
5662 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5665 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5666 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5667 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5668 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5669 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5670 enum i40e_status_code status;
5672 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5673 seid, 0, true, NULL,
5676 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5680 * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5681 * @filters: list of cloud filters
5682 * @filter_count: length of list
5684 * There's an issue in the device where the Geneve VNI layout needs
5685 * to be shifted 1 byte over from the VxLAN VNI
5687 STATIC void i40e_fix_up_geneve_vni(
5688 struct i40e_aqc_cloud_filters_element_data *filters,
5691 struct i40e_aqc_cloud_filters_element_data *f = filters;
5694 for (i = 0; i < filter_count; i++) {
5698 tnl_type = (LE16_TO_CPU(f[i].flags) &
5699 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5700 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5701 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5702 ti = LE32_TO_CPU(f[i].tenant_id);
5703 f[i].tenant_id = CPU_TO_LE32(ti << 8);
5709 * i40e_aq_add_cloud_filters
5710 * @hw: pointer to the hardware structure
5711 * @seid: VSI seid to add cloud filters from
5712 * @filters: Buffer which contains the filters to be added
5713 * @filter_count: number of filters contained in the buffer
5715 * Set the cloud filters for a given VSI. The contents of the
5716 * i40e_aqc_cloud_filters_element_data are filled
5717 * in by the caller of the function.
5720 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5722 struct i40e_aqc_cloud_filters_element_data *filters,
5725 struct i40e_aq_desc desc;
5726 struct i40e_aqc_add_remove_cloud_filters *cmd =
5727 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5728 enum i40e_status_code status;
5731 i40e_fill_default_direct_cmd_desc(&desc,
5732 i40e_aqc_opc_add_cloud_filters);
5734 buff_len = filter_count * sizeof(*filters);
5735 desc.datalen = CPU_TO_LE16(buff_len);
5736 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5737 cmd->num_filters = filter_count;
5738 cmd->seid = CPU_TO_LE16(seid);
5740 i40e_fix_up_geneve_vni(filters, filter_count);
5742 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5748 * i40e_aq_add_cloud_filters_bb
5749 * @hw: pointer to the hardware structure
5750 * @seid: VSI seid to add cloud filters from
5751 * @filters: Buffer which contains the filters in big buffer to be added
5752 * @filter_count: number of filters contained in the buffer
5754 * Set the cloud filters for a given VSI. The contents of the
5755 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5759 enum i40e_status_code
5760 i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5761 struct i40e_aqc_cloud_filters_element_bb *filters,
5764 struct i40e_aq_desc desc;
5765 struct i40e_aqc_add_remove_cloud_filters *cmd =
5766 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5767 enum i40e_status_code status;
5771 i40e_fill_default_direct_cmd_desc(&desc,
5772 i40e_aqc_opc_add_cloud_filters);
5774 buff_len = filter_count * sizeof(*filters);
5775 desc.datalen = CPU_TO_LE16(buff_len);
5776 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5777 cmd->num_filters = filter_count;
5778 cmd->seid = CPU_TO_LE16(seid);
5779 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5781 for (i = 0; i < filter_count; i++) {
5785 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5786 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5787 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5789 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5790 * one more byte further than normally used for Tenant ID in
5791 * other tunnel types.
5793 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5794 ti = LE32_TO_CPU(filters[i].element.tenant_id);
5795 filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5799 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5805 * i40e_aq_rem_cloud_filters
5806 * @hw: pointer to the hardware structure
5807 * @seid: VSI seid to remove cloud filters from
5808 * @filters: Buffer which contains the filters to be removed
5809 * @filter_count: number of filters contained in the buffer
5811 * Remove the cloud filters for a given VSI. The contents of the
5812 * i40e_aqc_cloud_filters_element_data are filled in by the caller
5816 enum i40e_status_code
5817 i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid,
5818 struct i40e_aqc_cloud_filters_element_data *filters,
5821 struct i40e_aq_desc desc;
5822 struct i40e_aqc_add_remove_cloud_filters *cmd =
5823 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5824 enum i40e_status_code status;
5827 i40e_fill_default_direct_cmd_desc(&desc,
5828 i40e_aqc_opc_remove_cloud_filters);
5830 buff_len = filter_count * sizeof(*filters);
5831 desc.datalen = CPU_TO_LE16(buff_len);
5832 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5833 cmd->num_filters = filter_count;
5834 cmd->seid = CPU_TO_LE16(seid);
5836 i40e_fix_up_geneve_vni(filters, filter_count);
5838 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5844 * i40e_aq_rem_cloud_filters_bb
5845 * @hw: pointer to the hardware structure
5846 * @seid: VSI seid to remove cloud filters from
5847 * @filters: Buffer which contains the filters in big buffer to be removed
5848 * @filter_count: number of filters contained in the buffer
5850 * Remove the big buffer cloud filters for a given VSI. The contents of the
5851 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5855 enum i40e_status_code
5856 i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5857 struct i40e_aqc_cloud_filters_element_bb *filters,
5860 struct i40e_aq_desc desc;
5861 struct i40e_aqc_add_remove_cloud_filters *cmd =
5862 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5863 enum i40e_status_code status;
5867 i40e_fill_default_direct_cmd_desc(&desc,
5868 i40e_aqc_opc_remove_cloud_filters);
5870 buff_len = filter_count * sizeof(*filters);
5871 desc.datalen = CPU_TO_LE16(buff_len);
5872 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5873 cmd->num_filters = filter_count;
5874 cmd->seid = CPU_TO_LE16(seid);
5875 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5877 for (i = 0; i < filter_count; i++) {
5881 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5882 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5883 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5885 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5886 * one more byte further than normally used for Tenant ID in
5887 * other tunnel types.
5889 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5890 ti = LE32_TO_CPU(filters[i].element.tenant_id);
5891 filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5895 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5901 * i40e_aq_replace_cloud_filters - Replace cloud filter command
5902 * @hw: pointer to the hw struct
5903 * @filters: pointer to the i40e_aqc_replace_cloud_filter_cmd struct
5904 * @cmd_buf: pointer to the i40e_aqc_replace_cloud_filter_cmd_buf struct
5908 i40e_status_code i40e_aq_replace_cloud_filters(struct i40e_hw *hw,
5909 struct i40e_aqc_replace_cloud_filters_cmd *filters,
5910 struct i40e_aqc_replace_cloud_filters_cmd_buf *cmd_buf)
5912 struct i40e_aq_desc desc;
5913 struct i40e_aqc_replace_cloud_filters_cmd *cmd =
5914 (struct i40e_aqc_replace_cloud_filters_cmd *)&desc.params.raw;
5915 enum i40e_status_code status = I40E_SUCCESS;
5918 /* X722 doesn't support this command */
5919 if (hw->mac.type == I40E_MAC_X722)
5920 return I40E_ERR_DEVICE_NOT_SUPPORTED;
5922 /* need FW version greater than 6.00 */
5923 if (hw->aq.fw_maj_ver < 6)
5924 return I40E_NOT_SUPPORTED;
5926 i40e_fill_default_direct_cmd_desc(&desc,
5927 i40e_aqc_opc_replace_cloud_filters);
5929 desc.datalen = CPU_TO_LE16(32);
5930 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5931 cmd->old_filter_type = filters->old_filter_type;
5932 cmd->new_filter_type = filters->new_filter_type;
5933 cmd->valid_flags = filters->valid_flags;
5934 cmd->tr_bit = filters->tr_bit;
5935 cmd->tr_bit2 = filters->tr_bit2;
5937 status = i40e_asq_send_command(hw, &desc, cmd_buf,
5938 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf), NULL);
5940 /* for get cloud filters command */
5941 for (i = 0; i < 32; i += 4) {
5942 cmd_buf->filters[i / 4].filter_type = cmd_buf->data[i];
5943 cmd_buf->filters[i / 4].input[0] = cmd_buf->data[i + 1];
5944 cmd_buf->filters[i / 4].input[1] = cmd_buf->data[i + 2];
5945 cmd_buf->filters[i / 4].input[2] = cmd_buf->data[i + 3];
5953 * i40e_aq_alternate_write
5954 * @hw: pointer to the hardware structure
5955 * @reg_addr0: address of first dword to be read
5956 * @reg_val0: value to be written under 'reg_addr0'
5957 * @reg_addr1: address of second dword to be read
5958 * @reg_val1: value to be written under 'reg_addr1'
5960 * Write one or two dwords to alternate structure. Fields are indicated
5961 * by 'reg_addr0' and 'reg_addr1' register numbers.
5964 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5965 u32 reg_addr0, u32 reg_val0,
5966 u32 reg_addr1, u32 reg_val1)
5968 struct i40e_aq_desc desc;
5969 struct i40e_aqc_alternate_write *cmd_resp =
5970 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5971 enum i40e_status_code status;
5973 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5974 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5975 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5976 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5977 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5979 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5985 * i40e_aq_alternate_write_indirect
5986 * @hw: pointer to the hardware structure
5987 * @addr: address of a first register to be modified
5988 * @dw_count: number of alternate structure fields to write
5989 * @buffer: pointer to the command buffer
5991 * Write 'dw_count' dwords from 'buffer' to alternate structure
5992 * starting at 'addr'.
5995 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5996 u32 addr, u32 dw_count, void *buffer)
5998 struct i40e_aq_desc desc;
5999 struct i40e_aqc_alternate_ind_write *cmd_resp =
6000 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
6001 enum i40e_status_code status;
6004 return I40E_ERR_PARAM;
6006 /* Indirect command */
6007 i40e_fill_default_direct_cmd_desc(&desc,
6008 i40e_aqc_opc_alternate_write_indirect);
6010 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6011 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6012 if (dw_count > (I40E_AQ_LARGE_BUF/4))
6013 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6015 cmd_resp->address = CPU_TO_LE32(addr);
6016 cmd_resp->length = CPU_TO_LE32(dw_count);
6018 status = i40e_asq_send_command(hw, &desc, buffer,
6019 I40E_LO_DWORD(4*dw_count), NULL);
6025 * i40e_aq_alternate_read
6026 * @hw: pointer to the hardware structure
6027 * @reg_addr0: address of first dword to be read
6028 * @reg_val0: pointer for data read from 'reg_addr0'
6029 * @reg_addr1: address of second dword to be read
6030 * @reg_val1: pointer for data read from 'reg_addr1'
6032 * Read one or two dwords from alternate structure. Fields are indicated
6033 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
6034 * is not passed then only register at 'reg_addr0' is read.
6037 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
6038 u32 reg_addr0, u32 *reg_val0,
6039 u32 reg_addr1, u32 *reg_val1)
6041 struct i40e_aq_desc desc;
6042 struct i40e_aqc_alternate_write *cmd_resp =
6043 (struct i40e_aqc_alternate_write *)&desc.params.raw;
6044 enum i40e_status_code status;
6046 if (reg_val0 == NULL)
6047 return I40E_ERR_PARAM;
6049 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
6050 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
6051 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
6053 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6055 if (status == I40E_SUCCESS) {
6056 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
6058 if (reg_val1 != NULL)
6059 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
6066 * i40e_aq_alternate_read_indirect
6067 * @hw: pointer to the hardware structure
6068 * @addr: address of the alternate structure field
6069 * @dw_count: number of alternate structure fields to read
6070 * @buffer: pointer to the command buffer
6072 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
6073 * place them in 'buffer'. The buffer should be allocated by caller.
6076 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
6077 u32 addr, u32 dw_count, void *buffer)
6079 struct i40e_aq_desc desc;
6080 struct i40e_aqc_alternate_ind_write *cmd_resp =
6081 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
6082 enum i40e_status_code status;
6085 return I40E_ERR_PARAM;
6087 /* Indirect command */
6088 i40e_fill_default_direct_cmd_desc(&desc,
6089 i40e_aqc_opc_alternate_read_indirect);
6091 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6092 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6093 if (dw_count > (I40E_AQ_LARGE_BUF/4))
6094 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6096 cmd_resp->address = CPU_TO_LE32(addr);
6097 cmd_resp->length = CPU_TO_LE32(dw_count);
6099 status = i40e_asq_send_command(hw, &desc, buffer,
6100 I40E_LO_DWORD(4*dw_count), NULL);
6106 * i40e_aq_alternate_clear
6107 * @hw: pointer to the HW structure.
6109 * Clear the alternate structures of the port from which the function
6113 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
6115 struct i40e_aq_desc desc;
6116 enum i40e_status_code status;
6118 i40e_fill_default_direct_cmd_desc(&desc,
6119 i40e_aqc_opc_alternate_clear_port);
6121 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6127 * i40e_aq_alternate_write_done
6128 * @hw: pointer to the HW structure.
6129 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
6130 * @reset_needed: indicates the SW should trigger GLOBAL reset
6132 * Indicates to the FW that alternate structures have been changed.
6135 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
6136 u8 bios_mode, bool *reset_needed)
6138 struct i40e_aq_desc desc;
6139 struct i40e_aqc_alternate_write_done *cmd =
6140 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6141 enum i40e_status_code status;
6143 if (reset_needed == NULL)
6144 return I40E_ERR_PARAM;
6146 i40e_fill_default_direct_cmd_desc(&desc,
6147 i40e_aqc_opc_alternate_write_done);
6149 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
6151 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6152 if (!status && reset_needed)
6153 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
6154 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
6160 * i40e_aq_set_oem_mode
6161 * @hw: pointer to the HW structure.
6162 * @oem_mode: the OEM mode to be used
6164 * Sets the device to a specific operating mode. Currently the only supported
6165 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
6168 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
6171 struct i40e_aq_desc desc;
6172 struct i40e_aqc_alternate_write_done *cmd =
6173 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6174 enum i40e_status_code status;
6176 i40e_fill_default_direct_cmd_desc(&desc,
6177 i40e_aqc_opc_alternate_set_mode);
6179 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
6181 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6187 * i40e_aq_resume_port_tx
6188 * @hw: pointer to the hardware structure
6189 * @cmd_details: pointer to command details structure or NULL
6191 * Resume port's Tx traffic
6193 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
6194 struct i40e_asq_cmd_details *cmd_details)
6196 struct i40e_aq_desc desc;
6197 enum i40e_status_code status;
6199 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
6201 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6207 * i40e_set_pci_config_data - store PCI bus info
6208 * @hw: pointer to hardware structure
6209 * @link_status: the link status word from PCI config space
6211 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
6213 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
6215 hw->bus.type = i40e_bus_type_pci_express;
6217 switch (link_status & I40E_PCI_LINK_WIDTH) {
6218 case I40E_PCI_LINK_WIDTH_1:
6219 hw->bus.width = i40e_bus_width_pcie_x1;
6221 case I40E_PCI_LINK_WIDTH_2:
6222 hw->bus.width = i40e_bus_width_pcie_x2;
6224 case I40E_PCI_LINK_WIDTH_4:
6225 hw->bus.width = i40e_bus_width_pcie_x4;
6227 case I40E_PCI_LINK_WIDTH_8:
6228 hw->bus.width = i40e_bus_width_pcie_x8;
6231 hw->bus.width = i40e_bus_width_unknown;
6235 switch (link_status & I40E_PCI_LINK_SPEED) {
6236 case I40E_PCI_LINK_SPEED_2500:
6237 hw->bus.speed = i40e_bus_speed_2500;
6239 case I40E_PCI_LINK_SPEED_5000:
6240 hw->bus.speed = i40e_bus_speed_5000;
6242 case I40E_PCI_LINK_SPEED_8000:
6243 hw->bus.speed = i40e_bus_speed_8000;
6246 hw->bus.speed = i40e_bus_speed_unknown;
6252 * i40e_aq_debug_dump
6253 * @hw: pointer to the hardware structure
6254 * @cluster_id: specific cluster to dump
6255 * @table_id: table id within cluster
6256 * @start_index: index of line in the block to read
6257 * @buff_size: dump buffer size
6258 * @buff: dump buffer
6259 * @ret_buff_size: actual buffer size returned
6260 * @ret_next_table: next block to read
6261 * @ret_next_index: next index to read
6262 * @cmd_details: pointer to command details structure or NULL
6264 * Dump internal FW/HW data for debug purposes.
6267 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
6268 u8 table_id, u32 start_index, u16 buff_size,
6269 void *buff, u16 *ret_buff_size,
6270 u8 *ret_next_table, u32 *ret_next_index,
6271 struct i40e_asq_cmd_details *cmd_details)
6273 struct i40e_aq_desc desc;
6274 struct i40e_aqc_debug_dump_internals *cmd =
6275 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6276 struct i40e_aqc_debug_dump_internals *resp =
6277 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6278 enum i40e_status_code status;
6280 if (buff_size == 0 || !buff)
6281 return I40E_ERR_PARAM;
6283 i40e_fill_default_direct_cmd_desc(&desc,
6284 i40e_aqc_opc_debug_dump_internals);
6285 /* Indirect Command */
6286 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6287 if (buff_size > I40E_AQ_LARGE_BUF)
6288 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6290 cmd->cluster_id = cluster_id;
6291 cmd->table_id = table_id;
6292 cmd->idx = CPU_TO_LE32(start_index);
6294 desc.datalen = CPU_TO_LE16(buff_size);
6296 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
6298 if (ret_buff_size != NULL)
6299 *ret_buff_size = LE16_TO_CPU(desc.datalen);
6300 if (ret_next_table != NULL)
6301 *ret_next_table = resp->table_id;
6302 if (ret_next_index != NULL)
6303 *ret_next_index = LE32_TO_CPU(resp->idx);
6312 * @hw: pointer to the hardware structure
6313 * @enable: state of Energy Efficient Ethernet mode to be set
6315 * Enables or disables Energy Efficient Ethernet (EEE) mode
6316 * accordingly to @enable parameter.
6318 enum i40e_status_code i40e_enable_eee(struct i40e_hw *hw, bool enable)
6320 struct i40e_aq_get_phy_abilities_resp abilities;
6321 struct i40e_aq_set_phy_config config;
6322 enum i40e_status_code status;
6323 __le16 eee_capability;
6325 /* Get initial PHY capabilities */
6326 status = i40e_aq_get_phy_capabilities(hw, false, true, &abilities,
6331 /* Check whether NIC configuration is compatible with Energy Efficient
6332 * Ethernet (EEE) mode.
6334 if (abilities.eee_capability == 0) {
6335 status = I40E_ERR_CONFIG;
6339 /* Cache initial EEE capability */
6340 eee_capability = abilities.eee_capability;
6342 /* Get current configuration */
6343 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
6348 /* Cache current configuration */
6349 config.phy_type = abilities.phy_type;
6350 config.link_speed = abilities.link_speed;
6351 config.abilities = abilities.abilities |
6352 I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
6353 config.eeer = abilities.eeer_val;
6354 config.low_power_ctrl = abilities.d3_lpan;
6355 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
6356 I40E_AQ_PHY_FEC_CONFIG_MASK;
6358 /* Set desired EEE state */
6360 config.eee_capability = eee_capability;
6361 config.eeer |= I40E_PRTPM_EEER_TX_LPI_EN_MASK;
6363 config.eee_capability = 0;
6364 config.eeer &= ~I40E_PRTPM_EEER_TX_LPI_EN_MASK;
6367 /* Save modified config */
6368 status = i40e_aq_set_phy_config(hw, &config, NULL);
6374 * i40e_read_bw_from_alt_ram
6375 * @hw: pointer to the hardware structure
6376 * @max_bw: pointer for max_bw read
6377 * @min_bw: pointer for min_bw read
6378 * @min_valid: pointer for bool that is true if min_bw is a valid value
6379 * @max_valid: pointer for bool that is true if max_bw is a valid value
6381 * Read bw from the alternate ram for the given pf
6383 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
6384 u32 *max_bw, u32 *min_bw,
6385 bool *min_valid, bool *max_valid)
6387 enum i40e_status_code status;
6388 u32 max_bw_addr, min_bw_addr;
6390 /* Calculate the address of the min/max bw registers */
6391 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6392 I40E_ALT_STRUCT_MAX_BW_OFFSET +
6393 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6394 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6395 I40E_ALT_STRUCT_MIN_BW_OFFSET +
6396 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6398 /* Read the bandwidths from alt ram */
6399 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
6400 min_bw_addr, min_bw);
6402 if (*min_bw & I40E_ALT_BW_VALID_MASK)
6407 if (*max_bw & I40E_ALT_BW_VALID_MASK)
6416 * i40e_aq_configure_partition_bw
6417 * @hw: pointer to the hardware structure
6418 * @bw_data: Buffer holding valid pfs and bw limits
6419 * @cmd_details: pointer to command details
6421 * Configure partitions guaranteed/max bw
6423 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6424 struct i40e_aqc_configure_partition_bw_data *bw_data,
6425 struct i40e_asq_cmd_details *cmd_details)
6427 enum i40e_status_code status;
6428 struct i40e_aq_desc desc;
6429 u16 bwd_size = sizeof(*bw_data);
6431 i40e_fill_default_direct_cmd_desc(&desc,
6432 i40e_aqc_opc_configure_partition_bw);
6434 /* Indirect command */
6435 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6436 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6438 desc.datalen = CPU_TO_LE16(bwd_size);
6440 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6446 * i40e_read_phy_register_clause22
6447 * @hw: pointer to the HW structure
6448 * @reg: register address in the page
6449 * @phy_addr: PHY address on MDIO interface
6450 * @value: PHY register value
6452 * Reads specified PHY register value
6454 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
6455 u16 reg, u8 phy_addr, u16 *value)
6457 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6458 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6462 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6463 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6464 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
6465 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6466 (I40E_GLGEN_MSCA_MDICMD_MASK);
6467 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6469 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6470 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6471 status = I40E_SUCCESS;
6474 i40e_usec_delay(10);
6479 i40e_debug(hw, I40E_DEBUG_PHY,
6480 "PHY: Can't write command to external PHY.\n");
6482 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6483 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6484 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6491 * i40e_write_phy_register_clause22
6492 * @hw: pointer to the HW structure
6493 * @reg: register address in the page
6494 * @phy_addr: PHY address on MDIO interface
6495 * @value: PHY register value
6497 * Writes specified PHY register value
6499 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6500 u16 reg, u8 phy_addr, u16 value)
6502 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6503 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6507 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6508 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6510 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6511 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6512 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6513 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6514 (I40E_GLGEN_MSCA_MDICMD_MASK);
6516 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6518 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6519 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6520 status = I40E_SUCCESS;
6523 i40e_usec_delay(10);
6531 * i40e_read_phy_register_clause45
6532 * @hw: pointer to the HW structure
6533 * @page: registers page number
6534 * @reg: register address in the page
6535 * @phy_addr: PHY address on MDIO interface
6536 * @value: PHY register value
6538 * Reads specified PHY register value
6540 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6541 u8 page, u16 reg, u8 phy_addr, u16 *value)
6543 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6546 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6548 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6549 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6550 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6551 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6552 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6553 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6554 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6555 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6557 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6558 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6559 status = I40E_SUCCESS;
6562 i40e_usec_delay(10);
6567 i40e_debug(hw, I40E_DEBUG_PHY,
6568 "PHY: Can't write command to external PHY.\n");
6572 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6573 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6574 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6575 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6576 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6577 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6578 status = I40E_ERR_TIMEOUT;
6580 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6582 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6583 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6584 status = I40E_SUCCESS;
6587 i40e_usec_delay(10);
6592 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6593 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6594 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6596 i40e_debug(hw, I40E_DEBUG_PHY,
6597 "PHY: Can't read register value from external PHY.\n");
6605 * i40e_write_phy_register_clause45
6606 * @hw: pointer to the HW structure
6607 * @page: registers page number
6608 * @reg: register address in the page
6609 * @phy_addr: PHY address on MDIO interface
6610 * @value: PHY register value
6612 * Writes value to specified PHY register
6614 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6615 u8 page, u16 reg, u8 phy_addr, u16 value)
6617 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6620 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6622 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6623 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6624 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6625 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6626 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6627 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6628 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6629 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6631 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6632 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6633 status = I40E_SUCCESS;
6636 i40e_usec_delay(10);
6640 i40e_debug(hw, I40E_DEBUG_PHY,
6641 "PHY: Can't write command to external PHY.\n");
6645 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6646 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6648 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6649 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6650 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6651 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6652 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6653 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6654 status = I40E_ERR_TIMEOUT;
6656 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6658 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6659 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6660 status = I40E_SUCCESS;
6663 i40e_usec_delay(10);
6672 * i40e_write_phy_register
6673 * @hw: pointer to the HW structure
6674 * @page: registers page number
6675 * @reg: register address in the page
6676 * @phy_addr: PHY address on MDIO interface
6677 * @value: PHY register value
6679 * Writes value to specified PHY register
6681 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6682 u8 page, u16 reg, u8 phy_addr, u16 value)
6684 enum i40e_status_code status;
6686 switch (hw->device_id) {
6687 case I40E_DEV_ID_1G_BASE_T_X722:
6688 status = i40e_write_phy_register_clause22(hw,
6689 reg, phy_addr, value);
6691 case I40E_DEV_ID_10G_BASE_T:
6692 case I40E_DEV_ID_10G_BASE_T4:
6693 case I40E_DEV_ID_10G_BASE_T_BC:
6694 case I40E_DEV_ID_10G_BASE_T_X722:
6695 case I40E_DEV_ID_25G_B:
6696 case I40E_DEV_ID_25G_SFP28:
6697 status = i40e_write_phy_register_clause45(hw,
6698 page, reg, phy_addr, value);
6701 status = I40E_ERR_UNKNOWN_PHY;
6709 * i40e_read_phy_register
6710 * @hw: pointer to the HW structure
6711 * @page: registers page number
6712 * @reg: register address in the page
6713 * @phy_addr: PHY address on MDIO interface
6714 * @value: PHY register value
6716 * Reads specified PHY register value
6718 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6719 u8 page, u16 reg, u8 phy_addr, u16 *value)
6721 enum i40e_status_code status;
6723 switch (hw->device_id) {
6724 case I40E_DEV_ID_1G_BASE_T_X722:
6725 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6728 case I40E_DEV_ID_10G_BASE_T:
6729 case I40E_DEV_ID_10G_BASE_T4:
6730 case I40E_DEV_ID_10G_BASE_T_X722:
6731 case I40E_DEV_ID_25G_B:
6732 case I40E_DEV_ID_25G_SFP28:
6733 status = i40e_read_phy_register_clause45(hw, page, reg,
6737 status = I40E_ERR_UNKNOWN_PHY;
6745 * i40e_get_phy_address
6746 * @hw: pointer to the HW structure
6747 * @dev_num: PHY port num that address we want
6749 * Gets PHY address for current port
6751 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6753 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6754 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6756 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6760 * i40e_blink_phy_led
6761 * @hw: pointer to the HW structure
6762 * @time: time how long led will blinks in secs
6763 * @interval: gap between LED on and off in msecs
6765 * Blinks PHY link LED
6767 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6768 u32 time, u32 interval)
6770 enum i40e_status_code status = I40E_SUCCESS;
6775 u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6779 i = rd32(hw, I40E_PFGEN_PORTNUM);
6780 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6781 phy_addr = i40e_get_phy_address(hw, port_num);
6783 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6785 status = i40e_read_phy_register_clause45(hw,
6786 I40E_PHY_COM_REG_PAGE,
6790 goto phy_blinking_end;
6792 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6794 status = i40e_write_phy_register_clause45(hw,
6795 I40E_PHY_COM_REG_PAGE,
6799 goto phy_blinking_end;
6804 if (time > 0 && interval > 0) {
6805 for (i = 0; i < time * 1000; i += interval) {
6806 status = i40e_read_phy_register_clause45(hw,
6807 I40E_PHY_COM_REG_PAGE,
6808 led_addr, phy_addr, &led_reg);
6810 goto restore_config;
6811 if (led_reg & I40E_PHY_LED_MANUAL_ON)
6814 led_reg = I40E_PHY_LED_MANUAL_ON;
6815 status = i40e_write_phy_register_clause45(hw,
6816 I40E_PHY_COM_REG_PAGE,
6817 led_addr, phy_addr, led_reg);
6819 goto restore_config;
6820 i40e_msec_delay(interval);
6825 status = i40e_write_phy_register_clause45(hw,
6826 I40E_PHY_COM_REG_PAGE,
6827 led_addr, phy_addr, led_ctl);
6834 * i40e_led_get_reg - read LED register
6835 * @hw: pointer to the HW structure
6836 * @led_addr: LED register address
6837 * @reg_val: read register value
6839 static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr,
6842 enum i40e_status_code status;
6846 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6847 status = i40e_aq_get_phy_register(hw,
6848 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6849 I40E_PHY_COM_REG_PAGE, true,
6850 I40E_PHY_LED_PROV_REG_1,
6853 phy_addr = i40e_get_phy_address(hw, hw->port);
6854 status = i40e_read_phy_register_clause45(hw,
6855 I40E_PHY_COM_REG_PAGE,
6863 * i40e_led_set_reg - write LED register
6864 * @hw: pointer to the HW structure
6865 * @led_addr: LED register address
6866 * @reg_val: register value to write
6868 static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr,
6871 enum i40e_status_code status;
6874 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6875 status = i40e_aq_set_phy_register(hw,
6876 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6877 I40E_PHY_COM_REG_PAGE, true,
6878 I40E_PHY_LED_PROV_REG_1,
6881 phy_addr = i40e_get_phy_address(hw, hw->port);
6882 status = i40e_write_phy_register_clause45(hw,
6883 I40E_PHY_COM_REG_PAGE,
6892 * i40e_led_get_phy - return current on/off mode
6893 * @hw: pointer to the hw struct
6894 * @led_addr: address of led register to use
6895 * @val: original value of register to use
6898 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6901 enum i40e_status_code status = I40E_SUCCESS;
6908 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6909 status = i40e_aq_get_phy_register(hw,
6910 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6911 I40E_PHY_COM_REG_PAGE, true,
6912 I40E_PHY_LED_PROV_REG_1,
6914 if (status == I40E_SUCCESS)
6915 *val = (u16)reg_val_aq;
6918 temp_addr = I40E_PHY_LED_PROV_REG_1;
6919 phy_addr = i40e_get_phy_address(hw, hw->port);
6920 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6922 status = i40e_read_phy_register_clause45(hw,
6923 I40E_PHY_COM_REG_PAGE,
6924 temp_addr, phy_addr,
6929 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6930 *led_addr = temp_addr;
6939 * @hw: pointer to the HW structure
6940 * @on: true or false
6941 * @led_addr: address of led register to use
6942 * @mode: original val plus bit for set or ignore
6944 * Set led's on or off when controlled by the PHY
6947 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6948 u16 led_addr, u32 mode)
6950 enum i40e_status_code status = I40E_SUCCESS;
6954 status = i40e_led_get_reg(hw, led_addr, &led_reg);
6958 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6960 status = i40e_led_set_reg(hw, led_addr, led_reg);
6964 status = i40e_led_get_reg(hw, led_addr, &led_reg);
6966 goto restore_config;
6968 led_reg = I40E_PHY_LED_MANUAL_ON;
6971 status = i40e_led_set_reg(hw, led_addr, led_reg);
6973 goto restore_config;
6974 if (mode & I40E_PHY_LED_MODE_ORIG) {
6975 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6976 status = i40e_led_set_reg(hw, led_addr, led_ctl);
6981 status = i40e_led_set_reg(hw, led_addr, led_ctl);
6984 #endif /* PF_DRIVER */
6987 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6988 * @hw: pointer to the hw struct
6989 * @reg_addr: register address
6990 * @reg_val: ptr to register value
6991 * @cmd_details: pointer to command details structure or NULL
6993 * Use the firmware to read the Rx control register,
6994 * especially useful if the Rx unit is under heavy pressure
6996 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6997 u32 reg_addr, u32 *reg_val,
6998 struct i40e_asq_cmd_details *cmd_details)
7000 struct i40e_aq_desc desc;
7001 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
7002 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
7003 enum i40e_status_code status;
7005 if (reg_val == NULL)
7006 return I40E_ERR_PARAM;
7008 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
7010 cmd_resp->address = CPU_TO_LE32(reg_addr);
7012 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7014 if (status == I40E_SUCCESS)
7015 *reg_val = LE32_TO_CPU(cmd_resp->value);
7021 * i40e_read_rx_ctl - read from an Rx control register
7022 * @hw: pointer to the hw struct
7023 * @reg_addr: register address
7025 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
7027 enum i40e_status_code status = I40E_SUCCESS;
7032 use_register = (((hw->aq.api_maj_ver == 1) &&
7033 (hw->aq.api_min_ver < 5)) ||
7034 (hw->mac.type == I40E_MAC_X722));
7035 if (!use_register) {
7037 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
7038 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
7045 /* if the AQ access failed, try the old-fashioned way */
7046 if (status || use_register)
7047 val = rd32(hw, reg_addr);
7053 * i40e_aq_rx_ctl_write_register
7054 * @hw: pointer to the hw struct
7055 * @reg_addr: register address
7056 * @reg_val: register value
7057 * @cmd_details: pointer to command details structure or NULL
7059 * Use the firmware to write to an Rx control register,
7060 * especially useful if the Rx unit is under heavy pressure
7062 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
7063 u32 reg_addr, u32 reg_val,
7064 struct i40e_asq_cmd_details *cmd_details)
7066 struct i40e_aq_desc desc;
7067 struct i40e_aqc_rx_ctl_reg_read_write *cmd =
7068 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
7069 enum i40e_status_code status;
7071 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
7073 cmd->address = CPU_TO_LE32(reg_addr);
7074 cmd->value = CPU_TO_LE32(reg_val);
7076 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7082 * i40e_write_rx_ctl - write to an Rx control register
7083 * @hw: pointer to the hw struct
7084 * @reg_addr: register address
7085 * @reg_val: register value
7087 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
7089 enum i40e_status_code status = I40E_SUCCESS;
7093 use_register = (((hw->aq.api_maj_ver == 1) &&
7094 (hw->aq.api_min_ver < 5)) ||
7095 (hw->mac.type == I40E_MAC_X722));
7096 if (!use_register) {
7098 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
7100 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
7107 /* if the AQ access failed, try the old-fashioned way */
7108 if (status || use_register)
7109 wr32(hw, reg_addr, reg_val);
7114 * i40e_aq_set_phy_register
7115 * @hw: pointer to the hw struct
7116 * @phy_select: select which phy should be accessed
7117 * @dev_addr: PHY device address
7118 * @page_change: enable auto page change
7119 * @reg_addr: PHY register address
7120 * @reg_val: new register value
7121 * @cmd_details: pointer to command details structure or NULL
7123 * Write the external PHY register.
7125 enum i40e_status_code i40e_aq_set_phy_register(struct i40e_hw *hw,
7126 u8 phy_select, u8 dev_addr, bool page_change,
7127 u32 reg_addr, u32 reg_val,
7128 struct i40e_asq_cmd_details *cmd_details)
7130 struct i40e_aq_desc desc;
7131 struct i40e_aqc_phy_register_access *cmd =
7132 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7133 enum i40e_status_code status;
7135 i40e_fill_default_direct_cmd_desc(&desc,
7136 i40e_aqc_opc_set_phy_register);
7138 cmd->phy_interface = phy_select;
7139 cmd->dev_addres = dev_addr;
7140 cmd->reg_address = CPU_TO_LE32(reg_addr);
7141 cmd->reg_value = CPU_TO_LE32(reg_val);
7144 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
7146 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7152 * i40e_aq_get_phy_register
7153 * @hw: pointer to the hw struct
7154 * @phy_select: select which phy should be accessed
7155 * @dev_addr: PHY device address
7156 * @page_change: enable auto page change
7157 * @reg_addr: PHY register address
7158 * @reg_val: read register value
7159 * @cmd_details: pointer to command details structure or NULL
7161 * Read the external PHY register.
7163 enum i40e_status_code i40e_aq_get_phy_register(struct i40e_hw *hw,
7164 u8 phy_select, u8 dev_addr, bool page_change,
7165 u32 reg_addr, u32 *reg_val,
7166 struct i40e_asq_cmd_details *cmd_details)
7168 struct i40e_aq_desc desc;
7169 struct i40e_aqc_phy_register_access *cmd =
7170 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7171 enum i40e_status_code status;
7173 i40e_fill_default_direct_cmd_desc(&desc,
7174 i40e_aqc_opc_get_phy_register);
7176 cmd->phy_interface = phy_select;
7177 cmd->dev_addres = dev_addr;
7178 cmd->reg_address = CPU_TO_LE32(reg_addr);
7181 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
7183 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7185 *reg_val = LE32_TO_CPU(cmd->reg_value);
7190 #endif /* PF_DRIVER */
7194 * i40e_aq_send_msg_to_pf
7195 * @hw: pointer to the hardware structure
7196 * @v_opcode: opcodes for VF-PF communication
7197 * @v_retval: return error code
7198 * @msg: pointer to the msg buffer
7199 * @msglen: msg length
7200 * @cmd_details: pointer to command details
7202 * Send message to PF driver using admin queue. By default, this message
7203 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
7204 * completion before returning.
7206 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
7207 enum virtchnl_ops v_opcode,
7208 enum i40e_status_code v_retval,
7209 u8 *msg, u16 msglen,
7210 struct i40e_asq_cmd_details *cmd_details)
7212 struct i40e_aq_desc desc;
7213 struct i40e_asq_cmd_details details;
7214 enum i40e_status_code status;
7216 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
7217 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
7218 desc.cookie_high = CPU_TO_LE32(v_opcode);
7219 desc.cookie_low = CPU_TO_LE32(v_retval);
7221 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
7222 | I40E_AQ_FLAG_RD));
7223 if (msglen > I40E_AQ_LARGE_BUF)
7224 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7225 desc.datalen = CPU_TO_LE16(msglen);
7228 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
7229 details.async = true;
7230 cmd_details = &details;
7232 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
7233 msglen, cmd_details);
7238 * i40e_vf_parse_hw_config
7239 * @hw: pointer to the hardware structure
7240 * @msg: pointer to the virtual channel VF resource structure
7242 * Given a VF resource message from the PF, populate the hw struct
7243 * with appropriate information.
7245 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
7246 struct virtchnl_vf_resource *msg)
7248 struct virtchnl_vsi_resource *vsi_res;
7251 vsi_res = &msg->vsi_res[0];
7253 hw->dev_caps.num_vsis = msg->num_vsis;
7254 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
7255 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
7256 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
7257 hw->dev_caps.dcb = msg->vf_cap_flags &
7258 VIRTCHNL_VF_OFFLOAD_L2;
7259 hw->dev_caps.iwarp = (msg->vf_cap_flags &
7260 VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
7261 for (i = 0; i < msg->num_vsis; i++) {
7262 if (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) {
7263 i40e_memcpy(hw->mac.perm_addr,
7264 vsi_res->default_mac_addr,
7266 I40E_NONDMA_TO_NONDMA);
7267 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
7269 I40E_NONDMA_TO_NONDMA);
7277 * @hw: pointer to the hardware structure
7279 * Send a VF_RESET message to the PF. Does not wait for response from PF
7280 * as none will be forthcoming. Immediately after calling this function,
7281 * the admin queue should be shut down and (optionally) reinitialized.
7283 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
7285 return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF,
7286 I40E_SUCCESS, NULL, 0, NULL);
7288 #endif /* VF_DRIVER */
7291 * i40e_aq_set_arp_proxy_config
7292 * @hw: pointer to the HW structure
7293 * @proxy_config: pointer to proxy config command table struct
7294 * @cmd_details: pointer to command details
7296 * Set ARP offload parameters from pre-populated
7297 * i40e_aqc_arp_proxy_data struct
7299 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
7300 struct i40e_aqc_arp_proxy_data *proxy_config,
7301 struct i40e_asq_cmd_details *cmd_details)
7303 struct i40e_aq_desc desc;
7304 enum i40e_status_code status;
7307 return I40E_ERR_PARAM;
7309 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
7311 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7312 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7313 desc.params.external.addr_high =
7314 CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
7315 desc.params.external.addr_low =
7316 CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
7317 desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_arp_proxy_data));
7319 status = i40e_asq_send_command(hw, &desc, proxy_config,
7320 sizeof(struct i40e_aqc_arp_proxy_data),
7327 * i40e_aq_opc_set_ns_proxy_table_entry
7328 * @hw: pointer to the HW structure
7329 * @ns_proxy_table_entry: pointer to NS table entry command struct
7330 * @cmd_details: pointer to command details
7332 * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
7333 * from pre-populated i40e_aqc_ns_proxy_data struct
7335 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
7336 struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
7337 struct i40e_asq_cmd_details *cmd_details)
7339 struct i40e_aq_desc desc;
7340 enum i40e_status_code status;
7342 if (!ns_proxy_table_entry)
7343 return I40E_ERR_PARAM;
7345 i40e_fill_default_direct_cmd_desc(&desc,
7346 i40e_aqc_opc_set_ns_proxy_table_entry);
7348 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7349 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7350 desc.params.external.addr_high =
7351 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
7352 desc.params.external.addr_low =
7353 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
7354 desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_ns_proxy_data));
7356 status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
7357 sizeof(struct i40e_aqc_ns_proxy_data),
7364 * i40e_aq_set_clear_wol_filter
7365 * @hw: pointer to the hw struct
7366 * @filter_index: index of filter to modify (0-7)
7367 * @filter: buffer containing filter to be set
7368 * @set_filter: true to set filter, false to clear filter
7369 * @no_wol_tco: if true, pass through packets cannot cause wake-up
7370 * if false, pass through packets may cause wake-up
7371 * @filter_valid: true if filter action is valid
7372 * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
7373 * @cmd_details: pointer to command details structure or NULL
7375 * Set or clear WoL filter for port attached to the PF
7377 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
7379 struct i40e_aqc_set_wol_filter_data *filter,
7380 bool set_filter, bool no_wol_tco,
7381 bool filter_valid, bool no_wol_tco_valid,
7382 struct i40e_asq_cmd_details *cmd_details)
7384 struct i40e_aq_desc desc;
7385 struct i40e_aqc_set_wol_filter *cmd =
7386 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
7387 enum i40e_status_code status;
7389 u16 valid_flags = 0;
7392 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
7394 if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
7395 return I40E_ERR_PARAM;
7396 cmd->filter_index = CPU_TO_LE16(filter_index);
7400 return I40E_ERR_PARAM;
7402 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
7403 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR;
7407 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
7408 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
7411 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
7412 if (no_wol_tco_valid)
7413 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
7414 cmd->valid_flags = CPU_TO_LE16(valid_flags);
7416 buff_len = sizeof(*filter);
7417 desc.datalen = CPU_TO_LE16(buff_len);
7419 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7420 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7422 cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
7423 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
7425 status = i40e_asq_send_command(hw, &desc, filter,
7426 buff_len, cmd_details);
7432 * i40e_aq_get_wake_event_reason
7433 * @hw: pointer to the hw struct
7434 * @wake_reason: return value, index of matching filter
7435 * @cmd_details: pointer to command details structure or NULL
7437 * Get information for the reason of a Wake Up event
7439 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
7441 struct i40e_asq_cmd_details *cmd_details)
7443 struct i40e_aq_desc desc;
7444 struct i40e_aqc_get_wake_reason_completion *resp =
7445 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
7446 enum i40e_status_code status;
7448 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
7450 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7452 if (status == I40E_SUCCESS)
7453 *wake_reason = LE16_TO_CPU(resp->wake_reason);
7459 * i40e_aq_clear_all_wol_filters
7460 * @hw: pointer to the hw struct
7461 * @cmd_details: pointer to command details structure or NULL
7463 * Get information for the reason of a Wake Up event
7465 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw,
7466 struct i40e_asq_cmd_details *cmd_details)
7468 struct i40e_aq_desc desc;
7469 enum i40e_status_code status;
7471 i40e_fill_default_direct_cmd_desc(&desc,
7472 i40e_aqc_opc_clear_all_wol_filters);
7474 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7480 * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
7481 * @hw: pointer to the hw struct
7482 * @buff: command buffer (size in bytes = buff_size)
7483 * @buff_size: buffer size in bytes
7484 * @track_id: package tracking id
7485 * @error_offset: returns error offset
7486 * @error_info: returns error information
7487 * @cmd_details: pointer to command details structure or NULL
7490 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
7491 u16 buff_size, u32 track_id,
7492 u32 *error_offset, u32 *error_info,
7493 struct i40e_asq_cmd_details *cmd_details)
7495 struct i40e_aq_desc desc;
7496 struct i40e_aqc_write_personalization_profile *cmd =
7497 (struct i40e_aqc_write_personalization_profile *)
7499 struct i40e_aqc_write_ddp_resp *resp;
7500 enum i40e_status_code status;
7502 i40e_fill_default_direct_cmd_desc(&desc,
7503 i40e_aqc_opc_write_personalization_profile);
7505 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
7506 if (buff_size > I40E_AQ_LARGE_BUF)
7507 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7509 desc.datalen = CPU_TO_LE16(buff_size);
7511 cmd->profile_track_id = CPU_TO_LE32(track_id);
7513 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7515 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
7517 *error_offset = LE32_TO_CPU(resp->error_offset);
7519 *error_info = LE32_TO_CPU(resp->error_info);
7526 * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
7527 * @hw: pointer to the hw struct
7528 * @buff: command buffer (size in bytes = buff_size)
7529 * @buff_size: buffer size in bytes
7530 * @flags: AdminQ command flags
7531 * @cmd_details: pointer to command details structure or NULL
7534 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
7535 u16 buff_size, u8 flags,
7536 struct i40e_asq_cmd_details *cmd_details)
7538 struct i40e_aq_desc desc;
7539 struct i40e_aqc_get_applied_profiles *cmd =
7540 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
7541 enum i40e_status_code status;
7543 i40e_fill_default_direct_cmd_desc(&desc,
7544 i40e_aqc_opc_get_personalization_profile_list);
7546 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7547 if (buff_size > I40E_AQ_LARGE_BUF)
7548 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7549 desc.datalen = CPU_TO_LE16(buff_size);
7553 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7559 * i40e_find_segment_in_package
7560 * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
7561 * @pkg_hdr: pointer to the package header to be searched
7563 * This function searches a package file for a particular segment type. On
7564 * success it returns a pointer to the segment header, otherwise it will
7567 struct i40e_generic_seg_header *
7568 i40e_find_segment_in_package(u32 segment_type,
7569 struct i40e_package_header *pkg_hdr)
7571 struct i40e_generic_seg_header *segment;
7574 /* Search all package segments for the requested segment type */
7575 for (i = 0; i < pkg_hdr->segment_count; i++) {
7577 (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
7578 pkg_hdr->segment_offset[i]);
7580 if (segment->type == segment_type)
7587 /* Get section table in profile */
7588 #define I40E_SECTION_TABLE(profile, sec_tbl) \
7590 struct i40e_profile_segment *p = (profile); \
7593 count = p->device_table_count; \
7594 nvm = (u32 *)&p->device_table[count]; \
7595 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \
7598 /* Get section header in profile */
7599 #define I40E_SECTION_HEADER(profile, offset) \
7600 (struct i40e_profile_section_header *)((u8 *)(profile) + (offset))
7603 * i40e_find_section_in_profile
7604 * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE)
7605 * @profile: pointer to the i40e segment header to be searched
7607 * This function searches i40e segment for a particular section type. On
7608 * success it returns a pointer to the section header, otherwise it will
7611 struct i40e_profile_section_header *
7612 i40e_find_section_in_profile(u32 section_type,
7613 struct i40e_profile_segment *profile)
7615 struct i40e_profile_section_header *sec;
7616 struct i40e_section_table *sec_tbl;
7620 if (profile->header.type != SEGMENT_TYPE_I40E)
7623 I40E_SECTION_TABLE(profile, sec_tbl);
7625 for (i = 0; i < sec_tbl->section_count; i++) {
7626 sec_off = sec_tbl->section_offset[i];
7627 sec = I40E_SECTION_HEADER(profile, sec_off);
7628 if (sec->section.type == section_type)
7636 * i40e_ddp_exec_aq_section - Execute generic AQ for DDP
7637 * @hw: pointer to the hw struct
7638 * @aq: command buffer containing all data to execute AQ
7641 i40e_status_code i40e_ddp_exec_aq_section(struct i40e_hw *hw,
7642 struct i40e_profile_aq_section *aq)
7644 enum i40e_status_code status;
7645 struct i40e_aq_desc desc;
7649 i40e_fill_default_direct_cmd_desc(&desc, aq->opcode);
7650 desc.flags |= CPU_TO_LE16(aq->flags);
7651 i40e_memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw),
7652 I40E_NONDMA_TO_NONDMA);
7654 msglen = aq->datalen;
7656 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
7658 if (msglen > I40E_AQ_LARGE_BUF)
7659 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7660 desc.datalen = CPU_TO_LE16(msglen);
7664 status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL);
7666 if (status != I40E_SUCCESS) {
7667 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7668 "unable to exec DDP AQ opcode %u, error %d\n",
7669 aq->opcode, status);
7673 /* copy returned desc to aq_buf */
7674 i40e_memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw),
7675 I40E_NONDMA_TO_NONDMA);
7677 return I40E_SUCCESS;
7681 * i40e_validate_profile
7682 * @hw: pointer to the hardware structure
7683 * @profile: pointer to the profile segment of the package to be validated
7684 * @track_id: package tracking id
7685 * @rollback: flag if the profile is for rollback.
7687 * Validates supported devices and profile's sections.
7689 STATIC enum i40e_status_code
7690 i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7691 u32 track_id, bool rollback)
7693 struct i40e_profile_section_header *sec = NULL;
7694 enum i40e_status_code status = I40E_SUCCESS;
7695 struct i40e_section_table *sec_tbl;
7701 if (track_id == I40E_DDP_TRACKID_INVALID) {
7702 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n");
7703 return I40E_NOT_SUPPORTED;
7706 dev_cnt = profile->device_table_count;
7707 for (i = 0; i < dev_cnt; i++) {
7708 vendor_dev_id = profile->device_table[i].vendor_dev_id;
7709 if ((vendor_dev_id >> 16) == I40E_INTEL_VENDOR_ID &&
7710 hw->device_id == (vendor_dev_id & 0xFFFF))
7713 if (dev_cnt && (i == dev_cnt)) {
7714 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7715 "Device doesn't support DDP\n");
7716 return I40E_ERR_DEVICE_NOT_SUPPORTED;
7719 I40E_SECTION_TABLE(profile, sec_tbl);
7721 /* Validate sections types */
7722 for (i = 0; i < sec_tbl->section_count; i++) {
7723 sec_off = sec_tbl->section_offset[i];
7724 sec = I40E_SECTION_HEADER(profile, sec_off);
7726 if (sec->section.type == SECTION_TYPE_MMIO ||
7727 sec->section.type == SECTION_TYPE_AQ ||
7728 sec->section.type == SECTION_TYPE_RB_AQ) {
7729 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7730 "Not a roll-back package\n");
7731 return I40E_NOT_SUPPORTED;
7734 if (sec->section.type == SECTION_TYPE_RB_AQ ||
7735 sec->section.type == SECTION_TYPE_RB_MMIO) {
7736 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7737 "Not an original package\n");
7738 return I40E_NOT_SUPPORTED;
7747 * i40e_write_profile
7748 * @hw: pointer to the hardware structure
7749 * @profile: pointer to the profile segment of the package to be downloaded
7750 * @track_id: package tracking id
7752 * Handles the download of a complete package.
7754 enum i40e_status_code
7755 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7758 enum i40e_status_code status = I40E_SUCCESS;
7759 struct i40e_section_table *sec_tbl;
7760 struct i40e_profile_section_header *sec = NULL;
7761 struct i40e_profile_aq_section *ddp_aq;
7762 u32 section_size = 0;
7763 u32 offset = 0, info = 0;
7767 status = i40e_validate_profile(hw, profile, track_id, false);
7771 I40E_SECTION_TABLE(profile, sec_tbl);
7773 for (i = 0; i < sec_tbl->section_count; i++) {
7774 sec_off = sec_tbl->section_offset[i];
7775 sec = I40E_SECTION_HEADER(profile, sec_off);
7776 /* Process generic admin command */
7777 if (sec->section.type == SECTION_TYPE_AQ) {
7778 ddp_aq = (struct i40e_profile_aq_section *)&sec[1];
7779 status = i40e_ddp_exec_aq_section(hw, ddp_aq);
7781 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7782 "Failed to execute aq: section %d, opcode %u\n",
7786 sec->section.type = SECTION_TYPE_RB_AQ;
7789 /* Skip any non-mmio sections */
7790 if (sec->section.type != SECTION_TYPE_MMIO)
7793 section_size = sec->section.size +
7794 sizeof(struct i40e_profile_section_header);
7796 /* Write MMIO section */
7797 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
7798 track_id, &offset, &info, NULL);
7800 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7801 "Failed to write profile: section %d, offset %d, info %d\n",
7810 * i40e_rollback_profile
7811 * @hw: pointer to the hardware structure
7812 * @profile: pointer to the profile segment of the package to be removed
7813 * @track_id: package tracking id
7815 * Rolls back previously loaded package.
7817 enum i40e_status_code
7818 i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7821 struct i40e_profile_section_header *sec = NULL;
7822 enum i40e_status_code status = I40E_SUCCESS;
7823 struct i40e_section_table *sec_tbl;
7824 u32 offset = 0, info = 0;
7825 u32 section_size = 0;
7829 status = i40e_validate_profile(hw, profile, track_id, true);
7833 I40E_SECTION_TABLE(profile, sec_tbl);
7835 /* For rollback write sections in reverse */
7836 for (i = sec_tbl->section_count - 1; i >= 0; i--) {
7837 sec_off = sec_tbl->section_offset[i];
7838 sec = I40E_SECTION_HEADER(profile, sec_off);
7840 /* Skip any non-rollback sections */
7841 if (sec->section.type != SECTION_TYPE_RB_MMIO)
7844 section_size = sec->section.size +
7845 sizeof(struct i40e_profile_section_header);
7847 /* Write roll-back MMIO section */
7848 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
7849 track_id, &offset, &info, NULL);
7851 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7852 "Failed to write profile: section %d, offset %d, info %d\n",
7861 * i40e_add_pinfo_to_list
7862 * @hw: pointer to the hardware structure
7863 * @profile: pointer to the profile segment of the package
7864 * @profile_info_sec: buffer for information section
7865 * @track_id: package tracking id
7867 * Register a profile to the list of loaded profiles.
7869 enum i40e_status_code
7870 i40e_add_pinfo_to_list(struct i40e_hw *hw,
7871 struct i40e_profile_segment *profile,
7872 u8 *profile_info_sec, u32 track_id)
7874 enum i40e_status_code status = I40E_SUCCESS;
7875 struct i40e_profile_section_header *sec = NULL;
7876 struct i40e_profile_info *pinfo;
7877 u32 offset = 0, info = 0;
7879 sec = (struct i40e_profile_section_header *)profile_info_sec;
7881 sec->data_end = sizeof(struct i40e_profile_section_header) +
7882 sizeof(struct i40e_profile_info);
7883 sec->section.type = SECTION_TYPE_INFO;
7884 sec->section.offset = sizeof(struct i40e_profile_section_header);
7885 sec->section.size = sizeof(struct i40e_profile_info);
7886 pinfo = (struct i40e_profile_info *)(profile_info_sec +
7887 sec->section.offset);
7888 pinfo->track_id = track_id;
7889 pinfo->version = profile->version;
7890 pinfo->op = I40E_DDP_ADD_TRACKID;
7891 i40e_memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE,
7892 I40E_NONDMA_TO_NONDMA);
7894 status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
7895 track_id, &offset, &info, NULL);