1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
8 #include "i40e_adminq.h"
9 #include "i40e_prototype.h"
13 * i40e_set_mac_type - Sets MAC type
14 * @hw: pointer to the HW structure
16 * This function sets the mac type of the adapter based on the
17 * vendor ID and device ID stored in the hw structure.
19 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
21 enum i40e_status_code status = I40E_SUCCESS;
23 DEBUGFUNC("i40e_set_mac_type\n");
25 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
26 switch (hw->device_id) {
27 case I40E_DEV_ID_SFP_XL710:
28 case I40E_DEV_ID_QEMU:
29 case I40E_DEV_ID_KX_B:
30 case I40E_DEV_ID_KX_C:
31 case I40E_DEV_ID_QSFP_A:
32 case I40E_DEV_ID_QSFP_B:
33 case I40E_DEV_ID_QSFP_C:
34 case I40E_DEV_ID_10G_BASE_T:
35 case I40E_DEV_ID_10G_BASE_T4:
36 case I40E_DEV_ID_10G_BASE_T_BC:
37 case I40E_DEV_ID_10G_B:
38 case I40E_DEV_ID_10G_SFP:
39 case I40E_DEV_ID_5G_BASE_T_BC:
40 case I40E_DEV_ID_20G_KR2:
41 case I40E_DEV_ID_20G_KR2_A:
42 case I40E_DEV_ID_25G_B:
43 case I40E_DEV_ID_25G_SFP28:
44 case I40E_DEV_ID_X710_N3000:
45 case I40E_DEV_ID_XXV710_N3000:
46 hw->mac.type = I40E_MAC_XL710;
48 #ifdef X722_A0_SUPPORT
49 case I40E_DEV_ID_X722_A0:
51 case I40E_DEV_ID_KX_X722:
52 case I40E_DEV_ID_QSFP_X722:
53 case I40E_DEV_ID_SFP_X722:
54 case I40E_DEV_ID_1G_BASE_T_X722:
55 case I40E_DEV_ID_10G_BASE_T_X722:
56 case I40E_DEV_ID_SFP_I_X722:
57 hw->mac.type = I40E_MAC_X722;
59 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
60 case I40E_DEV_ID_X722_VF:
61 #ifdef X722_A0_SUPPORT
62 case I40E_DEV_ID_X722_A0_VF:
64 hw->mac.type = I40E_MAC_X722_VF;
66 #endif /* INTEGRATED_VF || VF_DRIVER */
67 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
69 case I40E_DEV_ID_VF_HV:
70 case I40E_DEV_ID_ADAPTIVE_VF:
71 hw->mac.type = I40E_MAC_VF;
75 hw->mac.type = I40E_MAC_GENERIC;
79 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
82 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
83 hw->mac.type, status);
88 * i40e_aq_str - convert AQ err code to a string
89 * @hw: pointer to the HW structure
90 * @aq_err: the AQ error code to convert
92 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
97 case I40E_AQ_RC_EPERM:
98 return "I40E_AQ_RC_EPERM";
99 case I40E_AQ_RC_ENOENT:
100 return "I40E_AQ_RC_ENOENT";
101 case I40E_AQ_RC_ESRCH:
102 return "I40E_AQ_RC_ESRCH";
103 case I40E_AQ_RC_EINTR:
104 return "I40E_AQ_RC_EINTR";
106 return "I40E_AQ_RC_EIO";
107 case I40E_AQ_RC_ENXIO:
108 return "I40E_AQ_RC_ENXIO";
109 case I40E_AQ_RC_E2BIG:
110 return "I40E_AQ_RC_E2BIG";
111 case I40E_AQ_RC_EAGAIN:
112 return "I40E_AQ_RC_EAGAIN";
113 case I40E_AQ_RC_ENOMEM:
114 return "I40E_AQ_RC_ENOMEM";
115 case I40E_AQ_RC_EACCES:
116 return "I40E_AQ_RC_EACCES";
117 case I40E_AQ_RC_EFAULT:
118 return "I40E_AQ_RC_EFAULT";
119 case I40E_AQ_RC_EBUSY:
120 return "I40E_AQ_RC_EBUSY";
121 case I40E_AQ_RC_EEXIST:
122 return "I40E_AQ_RC_EEXIST";
123 case I40E_AQ_RC_EINVAL:
124 return "I40E_AQ_RC_EINVAL";
125 case I40E_AQ_RC_ENOTTY:
126 return "I40E_AQ_RC_ENOTTY";
127 case I40E_AQ_RC_ENOSPC:
128 return "I40E_AQ_RC_ENOSPC";
129 case I40E_AQ_RC_ENOSYS:
130 return "I40E_AQ_RC_ENOSYS";
131 case I40E_AQ_RC_ERANGE:
132 return "I40E_AQ_RC_ERANGE";
133 case I40E_AQ_RC_EFLUSHED:
134 return "I40E_AQ_RC_EFLUSHED";
135 case I40E_AQ_RC_BAD_ADDR:
136 return "I40E_AQ_RC_BAD_ADDR";
137 case I40E_AQ_RC_EMODE:
138 return "I40E_AQ_RC_EMODE";
139 case I40E_AQ_RC_EFBIG:
140 return "I40E_AQ_RC_EFBIG";
143 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
148 * i40e_stat_str - convert status err code to a string
149 * @hw: pointer to the HW structure
150 * @stat_err: the status error code to convert
152 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
158 return "I40E_ERR_NVM";
159 case I40E_ERR_NVM_CHECKSUM:
160 return "I40E_ERR_NVM_CHECKSUM";
162 return "I40E_ERR_PHY";
163 case I40E_ERR_CONFIG:
164 return "I40E_ERR_CONFIG";
166 return "I40E_ERR_PARAM";
167 case I40E_ERR_MAC_TYPE:
168 return "I40E_ERR_MAC_TYPE";
169 case I40E_ERR_UNKNOWN_PHY:
170 return "I40E_ERR_UNKNOWN_PHY";
171 case I40E_ERR_LINK_SETUP:
172 return "I40E_ERR_LINK_SETUP";
173 case I40E_ERR_ADAPTER_STOPPED:
174 return "I40E_ERR_ADAPTER_STOPPED";
175 case I40E_ERR_INVALID_MAC_ADDR:
176 return "I40E_ERR_INVALID_MAC_ADDR";
177 case I40E_ERR_DEVICE_NOT_SUPPORTED:
178 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
179 case I40E_ERR_MASTER_REQUESTS_PENDING:
180 return "I40E_ERR_MASTER_REQUESTS_PENDING";
181 case I40E_ERR_INVALID_LINK_SETTINGS:
182 return "I40E_ERR_INVALID_LINK_SETTINGS";
183 case I40E_ERR_AUTONEG_NOT_COMPLETE:
184 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
185 case I40E_ERR_RESET_FAILED:
186 return "I40E_ERR_RESET_FAILED";
187 case I40E_ERR_SWFW_SYNC:
188 return "I40E_ERR_SWFW_SYNC";
189 case I40E_ERR_NO_AVAILABLE_VSI:
190 return "I40E_ERR_NO_AVAILABLE_VSI";
191 case I40E_ERR_NO_MEMORY:
192 return "I40E_ERR_NO_MEMORY";
193 case I40E_ERR_BAD_PTR:
194 return "I40E_ERR_BAD_PTR";
195 case I40E_ERR_RING_FULL:
196 return "I40E_ERR_RING_FULL";
197 case I40E_ERR_INVALID_PD_ID:
198 return "I40E_ERR_INVALID_PD_ID";
199 case I40E_ERR_INVALID_QP_ID:
200 return "I40E_ERR_INVALID_QP_ID";
201 case I40E_ERR_INVALID_CQ_ID:
202 return "I40E_ERR_INVALID_CQ_ID";
203 case I40E_ERR_INVALID_CEQ_ID:
204 return "I40E_ERR_INVALID_CEQ_ID";
205 case I40E_ERR_INVALID_AEQ_ID:
206 return "I40E_ERR_INVALID_AEQ_ID";
207 case I40E_ERR_INVALID_SIZE:
208 return "I40E_ERR_INVALID_SIZE";
209 case I40E_ERR_INVALID_ARP_INDEX:
210 return "I40E_ERR_INVALID_ARP_INDEX";
211 case I40E_ERR_INVALID_FPM_FUNC_ID:
212 return "I40E_ERR_INVALID_FPM_FUNC_ID";
213 case I40E_ERR_QP_INVALID_MSG_SIZE:
214 return "I40E_ERR_QP_INVALID_MSG_SIZE";
215 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
216 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
217 case I40E_ERR_INVALID_FRAG_COUNT:
218 return "I40E_ERR_INVALID_FRAG_COUNT";
219 case I40E_ERR_QUEUE_EMPTY:
220 return "I40E_ERR_QUEUE_EMPTY";
221 case I40E_ERR_INVALID_ALIGNMENT:
222 return "I40E_ERR_INVALID_ALIGNMENT";
223 case I40E_ERR_FLUSHED_QUEUE:
224 return "I40E_ERR_FLUSHED_QUEUE";
225 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
226 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
227 case I40E_ERR_INVALID_IMM_DATA_SIZE:
228 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
229 case I40E_ERR_TIMEOUT:
230 return "I40E_ERR_TIMEOUT";
231 case I40E_ERR_OPCODE_MISMATCH:
232 return "I40E_ERR_OPCODE_MISMATCH";
233 case I40E_ERR_CQP_COMPL_ERROR:
234 return "I40E_ERR_CQP_COMPL_ERROR";
235 case I40E_ERR_INVALID_VF_ID:
236 return "I40E_ERR_INVALID_VF_ID";
237 case I40E_ERR_INVALID_HMCFN_ID:
238 return "I40E_ERR_INVALID_HMCFN_ID";
239 case I40E_ERR_BACKING_PAGE_ERROR:
240 return "I40E_ERR_BACKING_PAGE_ERROR";
241 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
242 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
243 case I40E_ERR_INVALID_PBLE_INDEX:
244 return "I40E_ERR_INVALID_PBLE_INDEX";
245 case I40E_ERR_INVALID_SD_INDEX:
246 return "I40E_ERR_INVALID_SD_INDEX";
247 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
248 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
249 case I40E_ERR_INVALID_SD_TYPE:
250 return "I40E_ERR_INVALID_SD_TYPE";
251 case I40E_ERR_MEMCPY_FAILED:
252 return "I40E_ERR_MEMCPY_FAILED";
253 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
254 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
255 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
256 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
257 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
258 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
259 case I40E_ERR_SRQ_ENABLED:
260 return "I40E_ERR_SRQ_ENABLED";
261 case I40E_ERR_ADMIN_QUEUE_ERROR:
262 return "I40E_ERR_ADMIN_QUEUE_ERROR";
263 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
264 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
265 case I40E_ERR_BUF_TOO_SHORT:
266 return "I40E_ERR_BUF_TOO_SHORT";
267 case I40E_ERR_ADMIN_QUEUE_FULL:
268 return "I40E_ERR_ADMIN_QUEUE_FULL";
269 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
270 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
271 case I40E_ERR_BAD_IWARP_CQE:
272 return "I40E_ERR_BAD_IWARP_CQE";
273 case I40E_ERR_NVM_BLANK_MODE:
274 return "I40E_ERR_NVM_BLANK_MODE";
275 case I40E_ERR_NOT_IMPLEMENTED:
276 return "I40E_ERR_NOT_IMPLEMENTED";
277 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
278 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
279 case I40E_ERR_DIAG_TEST_FAILED:
280 return "I40E_ERR_DIAG_TEST_FAILED";
281 case I40E_ERR_NOT_READY:
282 return "I40E_ERR_NOT_READY";
283 case I40E_NOT_SUPPORTED:
284 return "I40E_NOT_SUPPORTED";
285 case I40E_ERR_FIRMWARE_API_VERSION:
286 return "I40E_ERR_FIRMWARE_API_VERSION";
287 case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR:
288 return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR";
291 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
297 * @hw: debug mask related to admin queue
299 * @desc: pointer to admin queue descriptor
300 * @buffer: pointer to command buffer
301 * @buf_len: max length of buffer
303 * Dumps debug log about adminq command with descriptor contents.
305 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
306 void *buffer, u16 buf_len)
308 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
309 u32 effective_mask = hw->debug_mask & mask;
310 u8 *buf = (u8 *)buffer;
314 if (!effective_mask || !desc)
317 len = LE16_TO_CPU(aq_desc->datalen);
319 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
320 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
321 LE16_TO_CPU(aq_desc->opcode),
322 LE16_TO_CPU(aq_desc->flags),
323 LE16_TO_CPU(aq_desc->datalen),
324 LE16_TO_CPU(aq_desc->retval));
325 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
326 "\tcookie (h,l) 0x%08X 0x%08X\n",
327 LE32_TO_CPU(aq_desc->cookie_high),
328 LE32_TO_CPU(aq_desc->cookie_low));
329 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
330 "\tparam (0,1) 0x%08X 0x%08X\n",
331 LE32_TO_CPU(aq_desc->params.internal.param0),
332 LE32_TO_CPU(aq_desc->params.internal.param1));
333 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
334 "\taddr (h,l) 0x%08X 0x%08X\n",
335 LE32_TO_CPU(aq_desc->params.external.addr_high),
336 LE32_TO_CPU(aq_desc->params.external.addr_low));
338 if (buffer && (buf_len != 0) && (len != 0) &&
339 (effective_mask & I40E_DEBUG_AQ_DESC_BUFFER)) {
340 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
343 /* write the full 16-byte chunks */
344 for (i = 0; i < (len - 16); i += 16)
346 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
347 i, buf[i], buf[i+1], buf[i+2], buf[i+3],
348 buf[i+4], buf[i+5], buf[i+6], buf[i+7],
349 buf[i+8], buf[i+9], buf[i+10], buf[i+11],
350 buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
351 /* the most we could have left is 16 bytes, pad with zeros */
357 memset(d_buf, 0, sizeof(d_buf));
358 for (j = 0; i < len; j++, i++)
361 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
362 i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
363 d_buf[4], d_buf[5], d_buf[6], d_buf[7],
364 d_buf[8], d_buf[9], d_buf[10], d_buf[11],
365 d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
371 * i40e_check_asq_alive
372 * @hw: pointer to the hw struct
374 * Returns true if Queue is enabled else false.
376 bool i40e_check_asq_alive(struct i40e_hw *hw)
382 return !!(rd32(hw, hw->aq.asq.len) &
383 I40E_PF_ATQLEN_ATQENABLE_MASK);
385 return !!(rd32(hw, hw->aq.asq.len) &
386 I40E_PF_ATQLEN_ATQENABLE_MASK);
387 #endif /* INTEGRATED_VF */
388 #endif /* PF_DRIVER */
392 return !!(rd32(hw, hw->aq.asq.len) &
393 I40E_VF_ATQLEN1_ATQENABLE_MASK);
395 return !!(rd32(hw, hw->aq.asq.len) &
396 I40E_VF_ATQLEN1_ATQENABLE_MASK);
397 #endif /* INTEGRATED_VF */
398 #endif /* VF_DRIVER */
403 * i40e_aq_queue_shutdown
404 * @hw: pointer to the hw struct
405 * @unloading: is the driver unloading itself
407 * Tell the Firmware that we're shutting down the AdminQ and whether
408 * or not the driver is unloading as well.
410 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
413 struct i40e_aq_desc desc;
414 struct i40e_aqc_queue_shutdown *cmd =
415 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
416 enum i40e_status_code status;
418 i40e_fill_default_direct_cmd_desc(&desc,
419 i40e_aqc_opc_queue_shutdown);
422 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
423 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
429 * i40e_aq_get_set_rss_lut
430 * @hw: pointer to the hardware structure
431 * @vsi_id: vsi fw index
432 * @pf_lut: for PF table set true, for VSI table set false
433 * @lut: pointer to the lut buffer provided by the caller
434 * @lut_size: size of the lut buffer
435 * @set: set true to set the table, false to get the table
437 * Internal function to get or set RSS look up table
439 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
440 u16 vsi_id, bool pf_lut,
441 u8 *lut, u16 lut_size,
444 enum i40e_status_code status;
445 struct i40e_aq_desc desc;
446 struct i40e_aqc_get_set_rss_lut *cmd_resp =
447 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
450 i40e_fill_default_direct_cmd_desc(&desc,
451 i40e_aqc_opc_set_rss_lut);
453 i40e_fill_default_direct_cmd_desc(&desc,
454 i40e_aqc_opc_get_rss_lut);
456 /* Indirect command */
457 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
458 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
461 CPU_TO_LE16((u16)((vsi_id <<
462 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
463 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
464 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
467 cmd_resp->flags |= CPU_TO_LE16((u16)
468 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
469 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
470 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
472 cmd_resp->flags |= CPU_TO_LE16((u16)
473 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
474 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
475 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
477 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
483 * i40e_aq_get_rss_lut
484 * @hw: pointer to the hardware structure
485 * @vsi_id: vsi fw index
486 * @pf_lut: for PF table set true, for VSI table set false
487 * @lut: pointer to the lut buffer provided by the caller
488 * @lut_size: size of the lut buffer
490 * get the RSS lookup table, PF or VSI type
492 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
493 bool pf_lut, u8 *lut, u16 lut_size)
495 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
500 * i40e_aq_set_rss_lut
501 * @hw: pointer to the hardware structure
502 * @vsi_id: vsi fw index
503 * @pf_lut: for PF table set true, for VSI table set false
504 * @lut: pointer to the lut buffer provided by the caller
505 * @lut_size: size of the lut buffer
507 * set the RSS lookup table, PF or VSI type
509 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
510 bool pf_lut, u8 *lut, u16 lut_size)
512 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
516 * i40e_aq_get_set_rss_key
517 * @hw: pointer to the hw struct
518 * @vsi_id: vsi fw index
519 * @key: pointer to key info struct
520 * @set: set true to set the key, false to get the key
522 * get the RSS key per VSI
524 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
526 struct i40e_aqc_get_set_rss_key_data *key,
529 enum i40e_status_code status;
530 struct i40e_aq_desc desc;
531 struct i40e_aqc_get_set_rss_key *cmd_resp =
532 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
533 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
536 i40e_fill_default_direct_cmd_desc(&desc,
537 i40e_aqc_opc_set_rss_key);
539 i40e_fill_default_direct_cmd_desc(&desc,
540 i40e_aqc_opc_get_rss_key);
542 /* Indirect command */
543 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
544 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
547 CPU_TO_LE16((u16)((vsi_id <<
548 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
549 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
550 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
552 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
558 * i40e_aq_get_rss_key
559 * @hw: pointer to the hw struct
560 * @vsi_id: vsi fw index
561 * @key: pointer to key info struct
564 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
566 struct i40e_aqc_get_set_rss_key_data *key)
568 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
572 * i40e_aq_set_rss_key
573 * @hw: pointer to the hw struct
574 * @vsi_id: vsi fw index
575 * @key: pointer to key info struct
577 * set the RSS key per VSI
579 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
581 struct i40e_aqc_get_set_rss_key_data *key)
583 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
586 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
587 * hardware to a bit-field that can be used by SW to more easily determine the
590 * Macros are used to shorten the table lines and make this table human
593 * We store the PTYPE in the top byte of the bit field - this is just so that
594 * we can check that the table doesn't have a row missing, as the index into
595 * the table should be the PTYPE.
599 * IF NOT i40e_ptype_lookup[ptype].known
602 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
603 * Use the rest of the fields to look at the tunnels, inner protocols, etc
605 * Use the enum i40e_rx_l2_ptype to decode the packet type
609 /* macro to make the table lines short */
610 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
613 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
614 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
615 I40E_RX_PTYPE_##OUTER_FRAG, \
616 I40E_RX_PTYPE_TUNNEL_##T, \
617 I40E_RX_PTYPE_TUNNEL_END_##TE, \
618 I40E_RX_PTYPE_##TEF, \
619 I40E_RX_PTYPE_INNER_PROT_##I, \
620 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
622 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
623 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
625 /* shorter macros makes the table fit but are terse */
626 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
627 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
628 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
630 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
631 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
632 /* L2 Packet types */
633 I40E_PTT_UNUSED_ENTRY(0),
634 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
635 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
636 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
637 I40E_PTT_UNUSED_ENTRY(4),
638 I40E_PTT_UNUSED_ENTRY(5),
639 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
640 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
641 I40E_PTT_UNUSED_ENTRY(8),
642 I40E_PTT_UNUSED_ENTRY(9),
643 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
644 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
645 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
646 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
647 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
648 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
649 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
650 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
651 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
652 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
653 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
654 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
656 /* Non Tunneled IPv4 */
657 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
658 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
659 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
660 I40E_PTT_UNUSED_ENTRY(25),
661 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
662 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
663 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
666 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
667 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
668 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
669 I40E_PTT_UNUSED_ENTRY(32),
670 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
671 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
672 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
675 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
676 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
677 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
678 I40E_PTT_UNUSED_ENTRY(39),
679 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
680 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
681 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
683 /* IPv4 --> GRE/NAT */
684 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
686 /* IPv4 --> GRE/NAT --> IPv4 */
687 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
688 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
689 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
690 I40E_PTT_UNUSED_ENTRY(47),
691 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
692 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
693 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
695 /* IPv4 --> GRE/NAT --> IPv6 */
696 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
697 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
698 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
699 I40E_PTT_UNUSED_ENTRY(54),
700 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
701 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
702 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
704 /* IPv4 --> GRE/NAT --> MAC */
705 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
707 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
708 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
709 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
710 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
711 I40E_PTT_UNUSED_ENTRY(62),
712 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
713 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
714 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
716 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
717 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
718 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
719 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
720 I40E_PTT_UNUSED_ENTRY(69),
721 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
722 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
723 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
725 /* IPv4 --> GRE/NAT --> MAC/VLAN */
726 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
728 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
729 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
730 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
731 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
732 I40E_PTT_UNUSED_ENTRY(77),
733 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
734 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
735 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
737 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
738 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
739 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
740 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
741 I40E_PTT_UNUSED_ENTRY(84),
742 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
743 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
744 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
746 /* Non Tunneled IPv6 */
747 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
748 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
749 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4),
750 I40E_PTT_UNUSED_ENTRY(91),
751 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
752 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
753 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
756 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
757 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
758 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
759 I40E_PTT_UNUSED_ENTRY(98),
760 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
761 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
762 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
765 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
766 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
767 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
768 I40E_PTT_UNUSED_ENTRY(105),
769 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
770 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
771 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
773 /* IPv6 --> GRE/NAT */
774 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
776 /* IPv6 --> GRE/NAT -> IPv4 */
777 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
778 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
779 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
780 I40E_PTT_UNUSED_ENTRY(113),
781 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
782 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
783 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
785 /* IPv6 --> GRE/NAT -> IPv6 */
786 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
787 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
788 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
789 I40E_PTT_UNUSED_ENTRY(120),
790 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
791 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
792 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
794 /* IPv6 --> GRE/NAT -> MAC */
795 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
797 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
798 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
799 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
800 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
801 I40E_PTT_UNUSED_ENTRY(128),
802 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
803 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
804 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
806 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
807 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
808 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
809 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
810 I40E_PTT_UNUSED_ENTRY(135),
811 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
812 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
813 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
815 /* IPv6 --> GRE/NAT -> MAC/VLAN */
816 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
818 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
819 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
820 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
821 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
822 I40E_PTT_UNUSED_ENTRY(143),
823 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
824 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
825 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
827 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
828 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
829 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
830 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
831 I40E_PTT_UNUSED_ENTRY(150),
832 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
833 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
834 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
837 I40E_PTT_UNUSED_ENTRY(154),
838 I40E_PTT_UNUSED_ENTRY(155),
839 I40E_PTT_UNUSED_ENTRY(156),
840 I40E_PTT_UNUSED_ENTRY(157),
841 I40E_PTT_UNUSED_ENTRY(158),
842 I40E_PTT_UNUSED_ENTRY(159),
844 I40E_PTT_UNUSED_ENTRY(160),
845 I40E_PTT_UNUSED_ENTRY(161),
846 I40E_PTT_UNUSED_ENTRY(162),
847 I40E_PTT_UNUSED_ENTRY(163),
848 I40E_PTT_UNUSED_ENTRY(164),
849 I40E_PTT_UNUSED_ENTRY(165),
850 I40E_PTT_UNUSED_ENTRY(166),
851 I40E_PTT_UNUSED_ENTRY(167),
852 I40E_PTT_UNUSED_ENTRY(168),
853 I40E_PTT_UNUSED_ENTRY(169),
855 I40E_PTT_UNUSED_ENTRY(170),
856 I40E_PTT_UNUSED_ENTRY(171),
857 I40E_PTT_UNUSED_ENTRY(172),
858 I40E_PTT_UNUSED_ENTRY(173),
859 I40E_PTT_UNUSED_ENTRY(174),
860 I40E_PTT_UNUSED_ENTRY(175),
861 I40E_PTT_UNUSED_ENTRY(176),
862 I40E_PTT_UNUSED_ENTRY(177),
863 I40E_PTT_UNUSED_ENTRY(178),
864 I40E_PTT_UNUSED_ENTRY(179),
866 I40E_PTT_UNUSED_ENTRY(180),
867 I40E_PTT_UNUSED_ENTRY(181),
868 I40E_PTT_UNUSED_ENTRY(182),
869 I40E_PTT_UNUSED_ENTRY(183),
870 I40E_PTT_UNUSED_ENTRY(184),
871 I40E_PTT_UNUSED_ENTRY(185),
872 I40E_PTT_UNUSED_ENTRY(186),
873 I40E_PTT_UNUSED_ENTRY(187),
874 I40E_PTT_UNUSED_ENTRY(188),
875 I40E_PTT_UNUSED_ENTRY(189),
877 I40E_PTT_UNUSED_ENTRY(190),
878 I40E_PTT_UNUSED_ENTRY(191),
879 I40E_PTT_UNUSED_ENTRY(192),
880 I40E_PTT_UNUSED_ENTRY(193),
881 I40E_PTT_UNUSED_ENTRY(194),
882 I40E_PTT_UNUSED_ENTRY(195),
883 I40E_PTT_UNUSED_ENTRY(196),
884 I40E_PTT_UNUSED_ENTRY(197),
885 I40E_PTT_UNUSED_ENTRY(198),
886 I40E_PTT_UNUSED_ENTRY(199),
888 I40E_PTT_UNUSED_ENTRY(200),
889 I40E_PTT_UNUSED_ENTRY(201),
890 I40E_PTT_UNUSED_ENTRY(202),
891 I40E_PTT_UNUSED_ENTRY(203),
892 I40E_PTT_UNUSED_ENTRY(204),
893 I40E_PTT_UNUSED_ENTRY(205),
894 I40E_PTT_UNUSED_ENTRY(206),
895 I40E_PTT_UNUSED_ENTRY(207),
896 I40E_PTT_UNUSED_ENTRY(208),
897 I40E_PTT_UNUSED_ENTRY(209),
899 I40E_PTT_UNUSED_ENTRY(210),
900 I40E_PTT_UNUSED_ENTRY(211),
901 I40E_PTT_UNUSED_ENTRY(212),
902 I40E_PTT_UNUSED_ENTRY(213),
903 I40E_PTT_UNUSED_ENTRY(214),
904 I40E_PTT_UNUSED_ENTRY(215),
905 I40E_PTT_UNUSED_ENTRY(216),
906 I40E_PTT_UNUSED_ENTRY(217),
907 I40E_PTT_UNUSED_ENTRY(218),
908 I40E_PTT_UNUSED_ENTRY(219),
910 I40E_PTT_UNUSED_ENTRY(220),
911 I40E_PTT_UNUSED_ENTRY(221),
912 I40E_PTT_UNUSED_ENTRY(222),
913 I40E_PTT_UNUSED_ENTRY(223),
914 I40E_PTT_UNUSED_ENTRY(224),
915 I40E_PTT_UNUSED_ENTRY(225),
916 I40E_PTT_UNUSED_ENTRY(226),
917 I40E_PTT_UNUSED_ENTRY(227),
918 I40E_PTT_UNUSED_ENTRY(228),
919 I40E_PTT_UNUSED_ENTRY(229),
921 I40E_PTT_UNUSED_ENTRY(230),
922 I40E_PTT_UNUSED_ENTRY(231),
923 I40E_PTT_UNUSED_ENTRY(232),
924 I40E_PTT_UNUSED_ENTRY(233),
925 I40E_PTT_UNUSED_ENTRY(234),
926 I40E_PTT_UNUSED_ENTRY(235),
927 I40E_PTT_UNUSED_ENTRY(236),
928 I40E_PTT_UNUSED_ENTRY(237),
929 I40E_PTT_UNUSED_ENTRY(238),
930 I40E_PTT_UNUSED_ENTRY(239),
932 I40E_PTT_UNUSED_ENTRY(240),
933 I40E_PTT_UNUSED_ENTRY(241),
934 I40E_PTT_UNUSED_ENTRY(242),
935 I40E_PTT_UNUSED_ENTRY(243),
936 I40E_PTT_UNUSED_ENTRY(244),
937 I40E_PTT_UNUSED_ENTRY(245),
938 I40E_PTT_UNUSED_ENTRY(246),
939 I40E_PTT_UNUSED_ENTRY(247),
940 I40E_PTT_UNUSED_ENTRY(248),
941 I40E_PTT_UNUSED_ENTRY(249),
943 I40E_PTT_UNUSED_ENTRY(250),
944 I40E_PTT_UNUSED_ENTRY(251),
945 I40E_PTT_UNUSED_ENTRY(252),
946 I40E_PTT_UNUSED_ENTRY(253),
947 I40E_PTT_UNUSED_ENTRY(254),
948 I40E_PTT_UNUSED_ENTRY(255)
953 * i40e_validate_mac_addr - Validate unicast MAC address
954 * @mac_addr: pointer to MAC address
956 * Tests a MAC address to ensure it is a valid Individual Address
958 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
960 enum i40e_status_code status = I40E_SUCCESS;
962 DEBUGFUNC("i40e_validate_mac_addr");
964 /* Broadcast addresses ARE multicast addresses
965 * Make sure it is not a multicast address
966 * Reject the zero address
968 if (I40E_IS_MULTICAST(mac_addr) ||
969 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
970 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
971 status = I40E_ERR_INVALID_MAC_ADDR;
978 * i40e_init_shared_code - Initialize the shared code
979 * @hw: pointer to hardware structure
981 * This assigns the MAC type and PHY code and inits the NVM.
982 * Does not touch the hardware. This function must be called prior to any
983 * other function in the shared code. The i40e_hw structure should be
984 * memset to 0 prior to calling this function. The following fields in
985 * hw structure should be filled in prior to calling this function:
986 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
987 * subsystem_vendor_id, and revision_id
989 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
991 enum i40e_status_code status = I40E_SUCCESS;
992 u32 port, ari, func_rid;
994 DEBUGFUNC("i40e_init_shared_code");
996 i40e_set_mac_type(hw);
998 switch (hw->mac.type) {
1003 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1006 hw->phy.get_link_info = true;
1008 /* Determine port number and PF number*/
1009 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1010 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1011 hw->port = (u8)port;
1012 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1013 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1014 func_rid = rd32(hw, I40E_PF_FUNC_RID);
1016 hw->pf_id = (u8)(func_rid & 0xff);
1018 hw->pf_id = (u8)(func_rid & 0x7);
1020 if (hw->mac.type == I40E_MAC_X722)
1021 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE |
1022 I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK;
1023 /* NVMUpdate features structure initialization */
1024 hw->nvmupd_features.major = I40E_NVMUPD_FEATURES_API_VER_MAJOR;
1025 hw->nvmupd_features.minor = I40E_NVMUPD_FEATURES_API_VER_MINOR;
1026 hw->nvmupd_features.size = sizeof(hw->nvmupd_features);
1027 i40e_memset(hw->nvmupd_features.features, 0x0,
1028 I40E_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN *
1029 sizeof(*hw->nvmupd_features.features),
1032 /* No features supported at the moment */
1033 hw->nvmupd_features.features[0] = 0;
1035 status = i40e_init_nvm(hw);
1040 * i40e_aq_mac_address_read - Retrieve the MAC addresses
1041 * @hw: pointer to the hw struct
1042 * @flags: a return indicator of what addresses were added to the addr store
1043 * @addrs: the requestor's mac addr store
1044 * @cmd_details: pointer to command details structure or NULL
1046 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1048 struct i40e_aqc_mac_address_read_data *addrs,
1049 struct i40e_asq_cmd_details *cmd_details)
1051 struct i40e_aq_desc desc;
1052 struct i40e_aqc_mac_address_read *cmd_data =
1053 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1054 enum i40e_status_code status;
1056 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1057 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1059 status = i40e_asq_send_command(hw, &desc, addrs,
1060 sizeof(*addrs), cmd_details);
1061 *flags = LE16_TO_CPU(cmd_data->command_flags);
1067 * i40e_aq_mac_address_write - Change the MAC addresses
1068 * @hw: pointer to the hw struct
1069 * @flags: indicates which MAC to be written
1070 * @mac_addr: address to write
1071 * @cmd_details: pointer to command details structure or NULL
1073 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1074 u16 flags, u8 *mac_addr,
1075 struct i40e_asq_cmd_details *cmd_details)
1077 struct i40e_aq_desc desc;
1078 struct i40e_aqc_mac_address_write *cmd_data =
1079 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1080 enum i40e_status_code status;
1082 i40e_fill_default_direct_cmd_desc(&desc,
1083 i40e_aqc_opc_mac_address_write);
1084 cmd_data->command_flags = CPU_TO_LE16(flags);
1085 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1086 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1087 ((u32)mac_addr[3] << 16) |
1088 ((u32)mac_addr[4] << 8) |
1091 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1097 * i40e_get_mac_addr - get MAC address
1098 * @hw: pointer to the HW structure
1099 * @mac_addr: pointer to MAC address
1101 * Reads the adapter's MAC address from register
1103 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1105 struct i40e_aqc_mac_address_read_data addrs;
1106 enum i40e_status_code status;
1109 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1111 if (flags & I40E_AQC_LAN_ADDR_VALID)
1112 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1113 I40E_NONDMA_TO_NONDMA);
1119 * i40e_get_port_mac_addr - get Port MAC address
1120 * @hw: pointer to the HW structure
1121 * @mac_addr: pointer to Port MAC address
1123 * Reads the adapter's Port MAC address
1125 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1127 struct i40e_aqc_mac_address_read_data addrs;
1128 enum i40e_status_code status;
1131 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1135 if (flags & I40E_AQC_PORT_ADDR_VALID)
1136 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1137 I40E_NONDMA_TO_NONDMA);
1139 status = I40E_ERR_INVALID_MAC_ADDR;
1145 * i40e_pre_tx_queue_cfg - pre tx queue configure
1146 * @hw: pointer to the HW structure
1147 * @queue: target pf queue index
1148 * @enable: state change request
1150 * Handles hw requirement to indicate intention to enable
1151 * or disable target queue.
1153 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1155 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1159 if (abs_queue_idx >= 128) {
1160 reg_block = abs_queue_idx / 128;
1161 abs_queue_idx %= 128;
1164 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1165 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1166 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1169 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1171 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1173 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1177 * i40e_get_san_mac_addr - get SAN MAC address
1178 * @hw: pointer to the HW structure
1179 * @mac_addr: pointer to SAN MAC address
1181 * Reads the adapter's SAN MAC address from NVM
1183 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1186 struct i40e_aqc_mac_address_read_data addrs;
1187 enum i40e_status_code status;
1190 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1194 if (flags & I40E_AQC_SAN_ADDR_VALID)
1195 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac),
1196 I40E_NONDMA_TO_NONDMA);
1198 status = I40E_ERR_INVALID_MAC_ADDR;
1204 * i40e_read_pba_string - Reads part number string from EEPROM
1205 * @hw: pointer to hardware structure
1206 * @pba_num: stores the part number string from the EEPROM
1207 * @pba_num_size: part number string buffer length
1209 * Reads the part number string from the EEPROM.
1211 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1214 enum i40e_status_code status = I40E_SUCCESS;
1220 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1221 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1222 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1226 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1227 if (status != I40E_SUCCESS) {
1228 DEBUGOUT("Failed to read PBA Block pointer.\n");
1232 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1233 if (status != I40E_SUCCESS) {
1234 DEBUGOUT("Failed to read PBA Block size.\n");
1238 /* Subtract one to get PBA word count (PBA Size word is included in
1242 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1243 DEBUGOUT("Buffer to small for PBA data.\n");
1244 return I40E_ERR_PARAM;
1247 for (i = 0; i < pba_size; i++) {
1248 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1249 if (status != I40E_SUCCESS) {
1250 DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1254 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1255 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1257 pba_num[(pba_size * 2)] = '\0';
1263 * i40e_get_media_type - Gets media type
1264 * @hw: pointer to the hardware structure
1266 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1268 enum i40e_media_type media;
1270 switch (hw->phy.link_info.phy_type) {
1271 case I40E_PHY_TYPE_10GBASE_SR:
1272 case I40E_PHY_TYPE_10GBASE_LR:
1273 case I40E_PHY_TYPE_1000BASE_SX:
1274 case I40E_PHY_TYPE_1000BASE_LX:
1275 case I40E_PHY_TYPE_40GBASE_SR4:
1276 case I40E_PHY_TYPE_40GBASE_LR4:
1277 case I40E_PHY_TYPE_25GBASE_LR:
1278 case I40E_PHY_TYPE_25GBASE_SR:
1279 media = I40E_MEDIA_TYPE_FIBER;
1281 case I40E_PHY_TYPE_100BASE_TX:
1282 case I40E_PHY_TYPE_1000BASE_T:
1283 case I40E_PHY_TYPE_2_5GBASE_T_LINK_STATUS:
1284 case I40E_PHY_TYPE_5GBASE_T_LINK_STATUS:
1285 case I40E_PHY_TYPE_10GBASE_T:
1286 media = I40E_MEDIA_TYPE_BASET;
1288 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1289 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1290 case I40E_PHY_TYPE_10GBASE_CR1:
1291 case I40E_PHY_TYPE_40GBASE_CR4:
1292 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1293 case I40E_PHY_TYPE_40GBASE_AOC:
1294 case I40E_PHY_TYPE_10GBASE_AOC:
1295 case I40E_PHY_TYPE_25GBASE_CR:
1296 case I40E_PHY_TYPE_25GBASE_AOC:
1297 case I40E_PHY_TYPE_25GBASE_ACC:
1298 media = I40E_MEDIA_TYPE_DA;
1300 case I40E_PHY_TYPE_1000BASE_KX:
1301 case I40E_PHY_TYPE_10GBASE_KX4:
1302 case I40E_PHY_TYPE_10GBASE_KR:
1303 case I40E_PHY_TYPE_40GBASE_KR4:
1304 case I40E_PHY_TYPE_20GBASE_KR2:
1305 case I40E_PHY_TYPE_25GBASE_KR:
1306 media = I40E_MEDIA_TYPE_BACKPLANE;
1308 case I40E_PHY_TYPE_SGMII:
1309 case I40E_PHY_TYPE_XAUI:
1310 case I40E_PHY_TYPE_XFI:
1311 case I40E_PHY_TYPE_XLAUI:
1312 case I40E_PHY_TYPE_XLPPI:
1314 media = I40E_MEDIA_TYPE_UNKNOWN;
1322 * i40e_poll_globr - Poll for Global Reset completion
1323 * @hw: pointer to the hardware structure
1324 * @retry_limit: how many times to retry before failure
1326 STATIC enum i40e_status_code i40e_poll_globr(struct i40e_hw *hw,
1331 for (cnt = 0; cnt < retry_limit; cnt++) {
1332 reg = rd32(hw, I40E_GLGEN_RSTAT);
1333 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1334 return I40E_SUCCESS;
1335 i40e_msec_delay(100);
1338 DEBUGOUT("Global reset failed.\n");
1339 DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg);
1341 return I40E_ERR_RESET_FAILED;
1344 #define I40E_PF_RESET_WAIT_COUNT 200
1346 * i40e_pf_reset - Reset the PF
1347 * @hw: pointer to the hardware structure
1349 * Assuming someone else has triggered a global reset,
1350 * assure the global reset is complete and then reset the PF
1352 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1359 /* Poll for Global Reset steady state in case of recent GRST.
1360 * The grst delay value is in 100ms units, and we'll wait a
1361 * couple counts longer to be sure we don't just miss the end.
1363 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1364 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1365 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1367 grst_del = min(grst_del * 20, 160U);
1369 for (cnt = 0; cnt < grst_del; cnt++) {
1370 reg = rd32(hw, I40E_GLGEN_RSTAT);
1371 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1373 i40e_msec_delay(100);
1375 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1376 DEBUGOUT("Global reset polling failed to complete.\n");
1377 return I40E_ERR_RESET_FAILED;
1380 /* Now Wait for the FW to be ready */
1381 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1382 reg = rd32(hw, I40E_GLNVM_ULD);
1383 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1384 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1385 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1386 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1387 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1390 i40e_msec_delay(10);
1392 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1393 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1394 DEBUGOUT("wait for FW Reset complete timedout\n");
1395 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1396 return I40E_ERR_RESET_FAILED;
1399 /* If there was a Global Reset in progress when we got here,
1400 * we don't need to do the PF Reset
1405 reg = rd32(hw, I40E_PFGEN_CTRL);
1406 wr32(hw, I40E_PFGEN_CTRL,
1407 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1408 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1409 reg = rd32(hw, I40E_PFGEN_CTRL);
1410 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1412 reg2 = rd32(hw, I40E_GLGEN_RSTAT);
1413 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK)
1417 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1418 if (i40e_poll_globr(hw, grst_del) != I40E_SUCCESS)
1419 return I40E_ERR_RESET_FAILED;
1420 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1421 DEBUGOUT("PF reset polling failed to complete.\n");
1422 return I40E_ERR_RESET_FAILED;
1426 i40e_clear_pxe_mode(hw);
1429 return I40E_SUCCESS;
1433 * i40e_clear_hw - clear out any left over hw state
1434 * @hw: pointer to the hw struct
1436 * Clear queues and interrupts, typically called at init time,
1437 * but after the capabilities have been found so we know how many
1438 * queues and msix vectors have been allocated.
1440 void i40e_clear_hw(struct i40e_hw *hw)
1442 u32 num_queues, base_queue;
1450 /* get number of interrupts, queues, and vfs */
1451 val = rd32(hw, I40E_GLPCI_CNF2);
1452 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1453 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1454 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1455 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1457 val = rd32(hw, I40E_PFLAN_QALLOC);
1458 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1459 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1460 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1461 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1462 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1463 num_queues = (j - base_queue) + 1;
1467 val = rd32(hw, I40E_PF_VT_PFALLOC);
1468 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1469 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1470 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1471 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1472 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1473 num_vfs = (j - i) + 1;
1477 /* stop all the interrupts */
1478 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1479 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1480 for (i = 0; i < num_pf_int - 2; i++)
1481 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1483 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1484 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1485 wr32(hw, I40E_PFINT_LNKLST0, val);
1486 for (i = 0; i < num_pf_int - 2; i++)
1487 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1488 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1489 for (i = 0; i < num_vfs; i++)
1490 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1491 for (i = 0; i < num_vf_int - 2; i++)
1492 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1494 /* warn the HW of the coming Tx disables */
1495 for (i = 0; i < num_queues; i++) {
1496 u32 abs_queue_idx = base_queue + i;
1499 if (abs_queue_idx >= 128) {
1500 reg_block = abs_queue_idx / 128;
1501 abs_queue_idx %= 128;
1504 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1505 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1506 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1507 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1509 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1511 i40e_usec_delay(400);
1513 /* stop all the queues */
1514 for (i = 0; i < num_queues; i++) {
1515 wr32(hw, I40E_QINT_TQCTL(i), 0);
1516 wr32(hw, I40E_QTX_ENA(i), 0);
1517 wr32(hw, I40E_QINT_RQCTL(i), 0);
1518 wr32(hw, I40E_QRX_ENA(i), 0);
1521 /* short wait for all queue disables to settle */
1522 i40e_usec_delay(50);
1526 * i40e_clear_pxe_mode - clear pxe operations mode
1527 * @hw: pointer to the hw struct
1529 * Make sure all PXE mode settings are cleared, including things
1530 * like descriptor fetch/write-back mode.
1532 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1534 if (i40e_check_asq_alive(hw))
1535 i40e_aq_clear_pxe_mode(hw, NULL);
1539 * i40e_led_is_mine - helper to find matching led
1540 * @hw: pointer to the hw struct
1541 * @idx: index into GPIO registers
1543 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1545 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1550 if (!I40E_IS_X710TL_DEVICE(hw->device_id) &&
1551 !hw->func_caps.led[idx])
1553 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1554 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1555 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1557 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1558 * if it is not our port then ignore
1560 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1567 #define I40E_COMBINED_ACTIVITY 0xA
1568 #define I40E_FILTER_ACTIVITY 0xE
1569 #define I40E_LINK_ACTIVITY 0xC
1570 #define I40E_MAC_ACTIVITY 0xD
1571 #define I40E_FW_LED BIT(4)
1572 #define I40E_LED_MODE_VALID (I40E_GLGEN_GPIO_CTL_LED_MODE_MASK >> \
1573 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT)
1575 #define I40E_LED0 22
1577 #define I40E_PIN_FUNC_SDP 0x0
1578 #define I40E_PIN_FUNC_LED 0x1
1581 * i40e_led_get - return current on/off mode
1582 * @hw: pointer to the hw struct
1584 * The value returned is the 'mode' field as defined in the
1585 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1586 * values are variations of possible behaviors relating to
1587 * blink, link, and wire.
1589 u32 i40e_led_get(struct i40e_hw *hw)
1591 u32 current_mode = 0;
1595 /* as per the documentation GPIO 22-29 are the LED
1596 * GPIO pins named LED0..LED7
1598 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1599 u32 gpio_val = i40e_led_is_mine(hw, i);
1604 /* ignore gpio LED src mode entries related to the activity
1607 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1608 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1609 switch (current_mode) {
1610 case I40E_COMBINED_ACTIVITY:
1611 case I40E_FILTER_ACTIVITY:
1612 case I40E_MAC_ACTIVITY:
1613 case I40E_LINK_ACTIVITY:
1619 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1620 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1628 * i40e_led_set - set new on/off mode
1629 * @hw: pointer to the hw struct
1630 * @mode: 0=off, 0xf=on (else see manual for mode details)
1631 * @blink: true if the LED should blink when on, false if steady
1633 * if this function is used to turn on the blink it should
1634 * be used to disable the blink when restoring the original state.
1636 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1638 u32 current_mode = 0;
1641 if (mode & ~I40E_LED_MODE_VALID) {
1642 DEBUGOUT1("invalid mode passed in %X\n", mode);
1646 /* as per the documentation GPIO 22-29 are the LED
1647 * GPIO pins named LED0..LED7
1649 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1650 u32 gpio_val = i40e_led_is_mine(hw, i);
1655 /* ignore gpio LED src mode entries related to the activity
1658 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1659 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1660 switch (current_mode) {
1661 case I40E_COMBINED_ACTIVITY:
1662 case I40E_FILTER_ACTIVITY:
1663 case I40E_MAC_ACTIVITY:
1664 case I40E_LINK_ACTIVITY:
1670 if (I40E_IS_X710TL_DEVICE(hw->device_id)) {
1673 if (mode & I40E_FW_LED)
1674 pin_func = I40E_PIN_FUNC_SDP;
1676 pin_func = I40E_PIN_FUNC_LED;
1678 gpio_val &= ~I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK;
1679 gpio_val |= ((pin_func <<
1680 I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT) &
1681 I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK);
1683 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1684 /* this & is a bit of paranoia, but serves as a range check */
1685 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1686 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1689 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1691 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1693 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1698 /* Admin command wrappers */
1701 * i40e_aq_get_phy_capabilities
1702 * @hw: pointer to the hw struct
1703 * @abilities: structure for PHY capabilities to be filled
1704 * @qualified_modules: report Qualified Modules
1705 * @report_init: report init capabilities (active are default)
1706 * @cmd_details: pointer to command details structure or NULL
1708 * Returns the various PHY abilities supported on the Port.
1710 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1711 bool qualified_modules, bool report_init,
1712 struct i40e_aq_get_phy_abilities_resp *abilities,
1713 struct i40e_asq_cmd_details *cmd_details)
1715 struct i40e_aq_desc desc;
1716 enum i40e_status_code status;
1717 u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0;
1718 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1721 return I40E_ERR_PARAM;
1724 i40e_fill_default_direct_cmd_desc(&desc,
1725 i40e_aqc_opc_get_phy_abilities);
1727 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1728 if (abilities_size > I40E_AQ_LARGE_BUF)
1729 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1731 if (qualified_modules)
1732 desc.params.external.param0 |=
1733 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1736 desc.params.external.param0 |=
1737 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1739 status = i40e_asq_send_command(hw, &desc, abilities,
1740 abilities_size, cmd_details);
1742 switch (hw->aq.asq_last_status) {
1743 case I40E_AQ_RC_EIO:
1744 status = I40E_ERR_UNKNOWN_PHY;
1746 case I40E_AQ_RC_EAGAIN:
1749 status = I40E_ERR_TIMEOUT;
1751 /* also covers I40E_AQ_RC_OK */
1756 } while ((hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) &&
1757 (total_delay < max_delay));
1759 if (status != I40E_SUCCESS)
1763 if (hw->mac.type == I40E_MAC_XL710 &&
1764 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1765 hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
1766 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1768 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1769 hw->phy.phy_types |=
1770 ((u64)abilities->phy_type_ext << 32);
1778 * i40e_aq_set_phy_config
1779 * @hw: pointer to the hw struct
1780 * @config: structure with PHY configuration to be set
1781 * @cmd_details: pointer to command details structure or NULL
1783 * Set the various PHY configuration parameters
1784 * supported on the Port.One or more of the Set PHY config parameters may be
1785 * ignored in an MFP mode as the PF may not have the privilege to set some
1786 * of the PHY Config parameters. This status will be indicated by the
1789 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1790 struct i40e_aq_set_phy_config *config,
1791 struct i40e_asq_cmd_details *cmd_details)
1793 struct i40e_aq_desc desc;
1794 struct i40e_aq_set_phy_config *cmd =
1795 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1796 enum i40e_status_code status;
1799 return I40E_ERR_PARAM;
1801 i40e_fill_default_direct_cmd_desc(&desc,
1802 i40e_aqc_opc_set_phy_config);
1806 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1813 * @hw: pointer to the hw struct
1814 * @aq_failures: buffer to return AdminQ failure information
1815 * @atomic_restart: whether to enable atomic link restart
1817 * Set the requested flow control mode using set_phy_config.
1819 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1820 bool atomic_restart)
1822 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1823 struct i40e_aq_get_phy_abilities_resp abilities;
1824 struct i40e_aq_set_phy_config config;
1825 enum i40e_status_code status;
1826 u8 pause_mask = 0x0;
1832 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1833 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1835 case I40E_FC_RX_PAUSE:
1836 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1838 case I40E_FC_TX_PAUSE:
1839 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1845 /* Get the current phy config */
1846 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1849 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1853 memset(&config, 0, sizeof(config));
1854 /* clear the old pause settings */
1855 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1856 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1857 /* set the new abilities */
1858 config.abilities |= pause_mask;
1859 /* If the abilities have changed, then set the new config */
1860 if (config.abilities != abilities.abilities) {
1861 /* Auto restart link so settings take effect */
1863 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1864 /* Copy over all the old settings */
1865 config.phy_type = abilities.phy_type;
1866 config.phy_type_ext = abilities.phy_type_ext;
1867 config.link_speed = abilities.link_speed;
1868 config.eee_capability = abilities.eee_capability;
1869 config.eeer = abilities.eeer_val;
1870 config.low_power_ctrl = abilities.d3_lpan;
1871 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1872 I40E_AQ_PHY_FEC_CONFIG_MASK;
1873 status = i40e_aq_set_phy_config(hw, &config, NULL);
1876 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1878 /* Update the link info */
1879 status = i40e_update_link_info(hw);
1881 /* Wait a little bit (on 40G cards it sometimes takes a really
1882 * long time for link to come back from the atomic reset)
1885 i40e_msec_delay(1000);
1886 status = i40e_update_link_info(hw);
1889 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1895 * i40e_aq_set_mac_config
1896 * @hw: pointer to the hw struct
1897 * @max_frame_size: Maximum Frame Size to be supported by the port
1898 * @crc_en: Tell HW to append a CRC to outgoing frames
1899 * @pacing: Pacing configurations
1900 * @auto_drop_blocking_packets: Tell HW to drop packets if TC queue is blocked
1901 * @cmd_details: pointer to command details structure or NULL
1903 * Configure MAC settings for frame size, jumbo frame support and the
1904 * addition of a CRC by the hardware.
1906 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1908 bool crc_en, u16 pacing,
1909 bool auto_drop_blocking_packets,
1910 struct i40e_asq_cmd_details *cmd_details)
1912 struct i40e_aq_desc desc;
1913 struct i40e_aq_set_mac_config *cmd =
1914 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1915 enum i40e_status_code status;
1917 if (max_frame_size == 0)
1918 return I40E_ERR_PARAM;
1920 i40e_fill_default_direct_cmd_desc(&desc,
1921 i40e_aqc_opc_set_mac_config);
1923 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1924 cmd->params = ((u8)pacing & 0x0F) << 3;
1926 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1928 if (auto_drop_blocking_packets) {
1929 if (hw->flags & I40E_HW_FLAG_DROP_MODE)
1931 I40E_AQ_SET_MAC_CONFIG_DROP_BLOCKING_PACKET_EN;
1933 i40e_debug(hw, I40E_DEBUG_ALL,
1934 "This FW api version does not support drop mode.\n");
1937 #define I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD 0x7FFF
1938 cmd->fc_refresh_threshold =
1939 CPU_TO_LE16(I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD);
1941 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1947 * i40e_aq_clear_pxe_mode
1948 * @hw: pointer to the hw struct
1949 * @cmd_details: pointer to command details structure or NULL
1951 * Tell the firmware that the driver is taking over from PXE
1953 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1954 struct i40e_asq_cmd_details *cmd_details)
1956 enum i40e_status_code status;
1957 struct i40e_aq_desc desc;
1958 struct i40e_aqc_clear_pxe *cmd =
1959 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1961 i40e_fill_default_direct_cmd_desc(&desc,
1962 i40e_aqc_opc_clear_pxe_mode);
1966 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1968 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1974 * i40e_aq_set_link_restart_an
1975 * @hw: pointer to the hw struct
1976 * @enable_link: if true: enable link, if false: disable link
1977 * @cmd_details: pointer to command details structure or NULL
1979 * Sets up the link and restarts the Auto-Negotiation over the link.
1981 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1982 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1984 struct i40e_aq_desc desc;
1985 struct i40e_aqc_set_link_restart_an *cmd =
1986 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1987 enum i40e_status_code status;
1989 i40e_fill_default_direct_cmd_desc(&desc,
1990 i40e_aqc_opc_set_link_restart_an);
1992 cmd->command = I40E_AQ_PHY_RESTART_AN;
1994 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1996 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1998 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2004 * i40e_aq_get_link_info
2005 * @hw: pointer to the hw struct
2006 * @enable_lse: enable/disable LinkStatusEvent reporting
2007 * @link: pointer to link status structure - optional
2008 * @cmd_details: pointer to command details structure or NULL
2010 * Returns the link status of the adapter.
2012 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
2013 bool enable_lse, struct i40e_link_status *link,
2014 struct i40e_asq_cmd_details *cmd_details)
2016 struct i40e_aq_desc desc;
2017 struct i40e_aqc_get_link_status *resp =
2018 (struct i40e_aqc_get_link_status *)&desc.params.raw;
2019 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
2020 enum i40e_status_code status;
2021 bool tx_pause, rx_pause;
2024 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
2027 command_flags = I40E_AQ_LSE_ENABLE;
2029 command_flags = I40E_AQ_LSE_DISABLE;
2030 resp->command_flags = CPU_TO_LE16(command_flags);
2032 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2034 if (status != I40E_SUCCESS)
2035 goto aq_get_link_info_exit;
2037 /* save off old link status information */
2038 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
2039 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
2041 /* update link status */
2042 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
2043 hw->phy.media_type = i40e_get_media_type(hw);
2044 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
2045 hw_link_info->link_info = resp->link_info;
2046 hw_link_info->an_info = resp->an_info;
2047 hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
2048 I40E_AQ_CONFIG_FEC_RS_ENA);
2049 hw_link_info->ext_info = resp->ext_info;
2050 hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
2051 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
2052 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
2054 /* update fc info */
2055 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
2056 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
2057 if (tx_pause & rx_pause)
2058 hw->fc.current_mode = I40E_FC_FULL;
2060 hw->fc.current_mode = I40E_FC_TX_PAUSE;
2062 hw->fc.current_mode = I40E_FC_RX_PAUSE;
2064 hw->fc.current_mode = I40E_FC_NONE;
2066 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
2067 hw_link_info->crc_enable = true;
2069 hw_link_info->crc_enable = false;
2071 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
2072 hw_link_info->lse_enable = true;
2074 hw_link_info->lse_enable = false;
2076 if ((hw->mac.type == I40E_MAC_XL710) &&
2077 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
2078 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
2079 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
2081 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE &&
2082 hw->mac.type != I40E_MAC_X722) {
2085 i40e_memcpy(&tmp, resp->link_type, sizeof(tmp),
2086 I40E_NONDMA_TO_NONDMA);
2087 hw->phy.phy_types = LE32_TO_CPU(tmp);
2088 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
2091 /* save link status information */
2093 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
2094 I40E_NONDMA_TO_NONDMA);
2096 /* flag cleared so helper functions don't call AQ again */
2097 hw->phy.get_link_info = false;
2099 aq_get_link_info_exit:
2104 * i40e_aq_set_phy_int_mask
2105 * @hw: pointer to the hw struct
2106 * @mask: interrupt mask to be set
2107 * @cmd_details: pointer to command details structure or NULL
2109 * Set link interrupt mask.
2111 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2113 struct i40e_asq_cmd_details *cmd_details)
2115 struct i40e_aq_desc desc;
2116 struct i40e_aqc_set_phy_int_mask *cmd =
2117 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2118 enum i40e_status_code status;
2120 i40e_fill_default_direct_cmd_desc(&desc,
2121 i40e_aqc_opc_set_phy_int_mask);
2123 cmd->event_mask = CPU_TO_LE16(mask);
2125 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2131 * i40e_aq_get_local_advt_reg
2132 * @hw: pointer to the hw struct
2133 * @advt_reg: local AN advertisement register value
2134 * @cmd_details: pointer to command details structure or NULL
2136 * Get the Local AN advertisement register value.
2138 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2140 struct i40e_asq_cmd_details *cmd_details)
2142 struct i40e_aq_desc desc;
2143 struct i40e_aqc_an_advt_reg *resp =
2144 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2145 enum i40e_status_code status;
2147 i40e_fill_default_direct_cmd_desc(&desc,
2148 i40e_aqc_opc_get_local_advt_reg);
2150 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2152 if (status != I40E_SUCCESS)
2153 goto aq_get_local_advt_reg_exit;
2155 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2156 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2158 aq_get_local_advt_reg_exit:
2163 * i40e_aq_set_local_advt_reg
2164 * @hw: pointer to the hw struct
2165 * @advt_reg: local AN advertisement register value
2166 * @cmd_details: pointer to command details structure or NULL
2168 * Get the Local AN advertisement register value.
2170 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2172 struct i40e_asq_cmd_details *cmd_details)
2174 struct i40e_aq_desc desc;
2175 struct i40e_aqc_an_advt_reg *cmd =
2176 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2177 enum i40e_status_code status;
2179 i40e_fill_default_direct_cmd_desc(&desc,
2180 i40e_aqc_opc_get_local_advt_reg);
2182 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2183 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2185 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2191 * i40e_aq_get_partner_advt
2192 * @hw: pointer to the hw struct
2193 * @advt_reg: AN partner advertisement register value
2194 * @cmd_details: pointer to command details structure or NULL
2196 * Get the link partner AN advertisement register value.
2198 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2200 struct i40e_asq_cmd_details *cmd_details)
2202 struct i40e_aq_desc desc;
2203 struct i40e_aqc_an_advt_reg *resp =
2204 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2205 enum i40e_status_code status;
2207 i40e_fill_default_direct_cmd_desc(&desc,
2208 i40e_aqc_opc_get_partner_advt);
2210 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2212 if (status != I40E_SUCCESS)
2213 goto aq_get_partner_advt_exit;
2215 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2216 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2218 aq_get_partner_advt_exit:
2223 * i40e_aq_set_lb_modes
2224 * @hw: pointer to the hw struct
2225 * @lb_modes: loopback mode to be set
2226 * @cmd_details: pointer to command details structure or NULL
2228 * Sets loopback modes.
2230 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2232 struct i40e_asq_cmd_details *cmd_details)
2234 struct i40e_aq_desc desc;
2235 struct i40e_aqc_set_lb_mode *cmd =
2236 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2237 enum i40e_status_code status;
2239 i40e_fill_default_direct_cmd_desc(&desc,
2240 i40e_aqc_opc_set_lb_modes);
2242 cmd->lb_mode = CPU_TO_LE16(lb_modes);
2244 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2250 * i40e_aq_set_phy_debug
2251 * @hw: pointer to the hw struct
2252 * @cmd_flags: debug command flags
2253 * @cmd_details: pointer to command details structure or NULL
2255 * Reset the external PHY.
2257 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2258 struct i40e_asq_cmd_details *cmd_details)
2260 struct i40e_aq_desc desc;
2261 struct i40e_aqc_set_phy_debug *cmd =
2262 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2263 enum i40e_status_code status;
2265 i40e_fill_default_direct_cmd_desc(&desc,
2266 i40e_aqc_opc_set_phy_debug);
2268 cmd->command_flags = cmd_flags;
2270 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2277 * @hw: pointer to the hw struct
2278 * @maj: api major value
2279 * @min: api minor value
2281 * Assert whether current HW api version is greater/equal than provided.
2283 static bool i40e_hw_ver_ge(struct i40e_hw *hw, u16 maj, u16 min)
2285 if (hw->aq.api_maj_ver > maj ||
2286 (hw->aq.api_maj_ver == maj && hw->aq.api_min_ver >= min))
2293 * @hw: pointer to the hw struct
2294 * @vsi_ctx: pointer to a vsi context struct
2295 * @cmd_details: pointer to command details structure or NULL
2297 * Add a VSI context to the hardware.
2299 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2300 struct i40e_vsi_context *vsi_ctx,
2301 struct i40e_asq_cmd_details *cmd_details)
2303 struct i40e_aq_desc desc;
2304 struct i40e_aqc_add_get_update_vsi *cmd =
2305 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2306 struct i40e_aqc_add_get_update_vsi_completion *resp =
2307 (struct i40e_aqc_add_get_update_vsi_completion *)
2309 enum i40e_status_code status;
2311 i40e_fill_default_direct_cmd_desc(&desc,
2312 i40e_aqc_opc_add_vsi);
2314 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2315 cmd->connection_type = vsi_ctx->connection_type;
2316 cmd->vf_id = vsi_ctx->vf_num;
2317 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2319 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2321 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2322 sizeof(vsi_ctx->info), cmd_details);
2324 if (status != I40E_SUCCESS)
2325 goto aq_add_vsi_exit;
2327 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2328 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2329 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2330 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2337 * i40e_aq_set_default_vsi
2338 * @hw: pointer to the hw struct
2340 * @cmd_details: pointer to command details structure or NULL
2342 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2344 struct i40e_asq_cmd_details *cmd_details)
2346 struct i40e_aq_desc desc;
2347 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2348 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2350 enum i40e_status_code status;
2352 i40e_fill_default_direct_cmd_desc(&desc,
2353 i40e_aqc_opc_set_vsi_promiscuous_modes);
2355 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2356 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2357 cmd->seid = CPU_TO_LE16(seid);
2359 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2365 * i40e_aq_clear_default_vsi
2366 * @hw: pointer to the hw struct
2368 * @cmd_details: pointer to command details structure or NULL
2370 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2372 struct i40e_asq_cmd_details *cmd_details)
2374 struct i40e_aq_desc desc;
2375 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2376 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2378 enum i40e_status_code status;
2380 i40e_fill_default_direct_cmd_desc(&desc,
2381 i40e_aqc_opc_set_vsi_promiscuous_modes);
2383 cmd->promiscuous_flags = CPU_TO_LE16(0);
2384 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2385 cmd->seid = CPU_TO_LE16(seid);
2387 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2393 * i40e_aq_set_vsi_unicast_promiscuous
2394 * @hw: pointer to the hw struct
2396 * @set: set unicast promiscuous enable/disable
2397 * @cmd_details: pointer to command details structure or NULL
2398 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2400 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2402 struct i40e_asq_cmd_details *cmd_details,
2403 bool rx_only_promisc)
2405 struct i40e_aq_desc desc;
2406 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2407 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2408 enum i40e_status_code status;
2411 i40e_fill_default_direct_cmd_desc(&desc,
2412 i40e_aqc_opc_set_vsi_promiscuous_modes);
2415 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2416 if (rx_only_promisc && i40e_hw_ver_ge(hw, 1, 5))
2417 flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY;
2420 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2422 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2423 if (i40e_hw_ver_ge(hw, 1, 5))
2425 CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY);
2427 cmd->seid = CPU_TO_LE16(seid);
2428 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2434 * i40e_aq_set_vsi_multicast_promiscuous
2435 * @hw: pointer to the hw struct
2437 * @set: set multicast promiscuous enable/disable
2438 * @cmd_details: pointer to command details structure or NULL
2440 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2441 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2443 struct i40e_aq_desc desc;
2444 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2445 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2446 enum i40e_status_code status;
2449 i40e_fill_default_direct_cmd_desc(&desc,
2450 i40e_aqc_opc_set_vsi_promiscuous_modes);
2453 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2455 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2457 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2459 cmd->seid = CPU_TO_LE16(seid);
2460 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2466 * i40e_aq_set_vsi_full_promiscuous
2467 * @hw: pointer to the hw struct
2469 * @set: set promiscuous enable/disable
2470 * @cmd_details: pointer to command details structure or NULL
2472 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw,
2474 struct i40e_asq_cmd_details *cmd_details)
2476 struct i40e_aq_desc desc;
2477 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2478 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2479 enum i40e_status_code status;
2482 i40e_fill_default_direct_cmd_desc(&desc,
2483 i40e_aqc_opc_set_vsi_promiscuous_modes);
2486 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST |
2487 I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2488 I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2490 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2492 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST |
2493 I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2494 I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2496 cmd->seid = CPU_TO_LE16(seid);
2497 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2503 * i40e_aq_set_vsi_mc_promisc_on_vlan
2504 * @hw: pointer to the hw struct
2506 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2507 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2508 * @cmd_details: pointer to command details structure or NULL
2510 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2511 u16 seid, bool enable, u16 vid,
2512 struct i40e_asq_cmd_details *cmd_details)
2514 struct i40e_aq_desc desc;
2515 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2516 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2517 enum i40e_status_code status;
2520 i40e_fill_default_direct_cmd_desc(&desc,
2521 i40e_aqc_opc_set_vsi_promiscuous_modes);
2524 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2526 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2527 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2528 cmd->seid = CPU_TO_LE16(seid);
2529 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2531 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2537 * i40e_aq_set_vsi_uc_promisc_on_vlan
2538 * @hw: pointer to the hw struct
2540 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2541 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2542 * @cmd_details: pointer to command details structure or NULL
2544 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2545 u16 seid, bool enable, u16 vid,
2546 struct i40e_asq_cmd_details *cmd_details)
2548 struct i40e_aq_desc desc;
2549 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2550 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2551 enum i40e_status_code status;
2554 i40e_fill_default_direct_cmd_desc(&desc,
2555 i40e_aqc_opc_set_vsi_promiscuous_modes);
2558 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2559 if (i40e_hw_ver_ge(hw, 1, 5))
2560 flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY;
2563 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2564 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2565 if (i40e_hw_ver_ge(hw, 1, 5))
2567 CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY);
2568 cmd->seid = CPU_TO_LE16(seid);
2569 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2571 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2577 * i40e_aq_set_vsi_bc_promisc_on_vlan
2578 * @hw: pointer to the hw struct
2580 * @enable: set broadcast promiscuous enable/disable for a given VLAN
2581 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2582 * @cmd_details: pointer to command details structure or NULL
2584 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2585 u16 seid, bool enable, u16 vid,
2586 struct i40e_asq_cmd_details *cmd_details)
2588 struct i40e_aq_desc desc;
2589 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2590 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2591 enum i40e_status_code status;
2594 i40e_fill_default_direct_cmd_desc(&desc,
2595 i40e_aqc_opc_set_vsi_promiscuous_modes);
2598 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2600 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2601 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2602 cmd->seid = CPU_TO_LE16(seid);
2603 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2605 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2611 * i40e_aq_set_vsi_broadcast
2612 * @hw: pointer to the hw struct
2614 * @set_filter: true to set filter, false to clear filter
2615 * @cmd_details: pointer to command details structure or NULL
2617 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2619 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2620 u16 seid, bool set_filter,
2621 struct i40e_asq_cmd_details *cmd_details)
2623 struct i40e_aq_desc desc;
2624 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2625 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2626 enum i40e_status_code status;
2628 i40e_fill_default_direct_cmd_desc(&desc,
2629 i40e_aqc_opc_set_vsi_promiscuous_modes);
2632 cmd->promiscuous_flags
2633 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2635 cmd->promiscuous_flags
2636 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2638 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2639 cmd->seid = CPU_TO_LE16(seid);
2640 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2646 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2647 * @hw: pointer to the hw struct
2649 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2650 * @cmd_details: pointer to command details structure or NULL
2652 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2653 u16 seid, bool enable,
2654 struct i40e_asq_cmd_details *cmd_details)
2656 struct i40e_aq_desc desc;
2657 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2658 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2659 enum i40e_status_code status;
2662 i40e_fill_default_direct_cmd_desc(&desc,
2663 i40e_aqc_opc_set_vsi_promiscuous_modes);
2665 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2667 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2668 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2669 cmd->seid = CPU_TO_LE16(seid);
2671 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2677 * i40e_get_vsi_params - get VSI configuration info
2678 * @hw: pointer to the hw struct
2679 * @vsi_ctx: pointer to a vsi context struct
2680 * @cmd_details: pointer to command details structure or NULL
2682 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2683 struct i40e_vsi_context *vsi_ctx,
2684 struct i40e_asq_cmd_details *cmd_details)
2686 struct i40e_aq_desc desc;
2687 struct i40e_aqc_add_get_update_vsi *cmd =
2688 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2689 struct i40e_aqc_add_get_update_vsi_completion *resp =
2690 (struct i40e_aqc_add_get_update_vsi_completion *)
2692 enum i40e_status_code status;
2694 UNREFERENCED_1PARAMETER(cmd_details);
2695 i40e_fill_default_direct_cmd_desc(&desc,
2696 i40e_aqc_opc_get_vsi_parameters);
2698 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2700 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2702 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2703 sizeof(vsi_ctx->info), NULL);
2705 if (status != I40E_SUCCESS)
2706 goto aq_get_vsi_params_exit;
2708 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2709 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2710 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2711 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2713 aq_get_vsi_params_exit:
2718 * i40e_aq_update_vsi_params
2719 * @hw: pointer to the hw struct
2720 * @vsi_ctx: pointer to a vsi context struct
2721 * @cmd_details: pointer to command details structure or NULL
2723 * Update a VSI context.
2725 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2726 struct i40e_vsi_context *vsi_ctx,
2727 struct i40e_asq_cmd_details *cmd_details)
2729 struct i40e_aq_desc desc;
2730 struct i40e_aqc_add_get_update_vsi *cmd =
2731 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2732 struct i40e_aqc_add_get_update_vsi_completion *resp =
2733 (struct i40e_aqc_add_get_update_vsi_completion *)
2735 enum i40e_status_code status;
2737 i40e_fill_default_direct_cmd_desc(&desc,
2738 i40e_aqc_opc_update_vsi_parameters);
2739 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2741 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2743 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2744 sizeof(vsi_ctx->info), cmd_details);
2746 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2747 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2753 * i40e_aq_get_switch_config
2754 * @hw: pointer to the hardware structure
2755 * @buf: pointer to the result buffer
2756 * @buf_size: length of input buffer
2757 * @start_seid: seid to start for the report, 0 == beginning
2758 * @cmd_details: pointer to command details structure or NULL
2760 * Fill the buf with switch configuration returned from AdminQ command
2762 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2763 struct i40e_aqc_get_switch_config_resp *buf,
2764 u16 buf_size, u16 *start_seid,
2765 struct i40e_asq_cmd_details *cmd_details)
2767 struct i40e_aq_desc desc;
2768 struct i40e_aqc_switch_seid *scfg =
2769 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2770 enum i40e_status_code status;
2772 i40e_fill_default_direct_cmd_desc(&desc,
2773 i40e_aqc_opc_get_switch_config);
2774 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2775 if (buf_size > I40E_AQ_LARGE_BUF)
2776 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2777 scfg->seid = CPU_TO_LE16(*start_seid);
2779 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2780 *start_seid = LE16_TO_CPU(scfg->seid);
2786 * i40e_aq_set_switch_config
2787 * @hw: pointer to the hardware structure
2788 * @flags: bit flag values to set
2789 * @mode: cloud filter mode
2790 * @valid_flags: which bit flags to set
2791 * @cmd_details: pointer to command details structure or NULL
2793 * Set switch configuration bits
2795 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2796 u16 flags, u16 valid_flags, u8 mode,
2797 struct i40e_asq_cmd_details *cmd_details)
2799 struct i40e_aq_desc desc;
2800 struct i40e_aqc_set_switch_config *scfg =
2801 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2802 enum i40e_status_code status;
2804 i40e_fill_default_direct_cmd_desc(&desc,
2805 i40e_aqc_opc_set_switch_config);
2806 scfg->flags = CPU_TO_LE16(flags);
2807 scfg->valid_flags = CPU_TO_LE16(valid_flags);
2809 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
2810 scfg->switch_tag = CPU_TO_LE16(hw->switch_tag);
2811 scfg->first_tag = CPU_TO_LE16(hw->first_tag);
2812 scfg->second_tag = CPU_TO_LE16(hw->second_tag);
2814 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2820 * i40e_aq_get_firmware_version
2821 * @hw: pointer to the hw struct
2822 * @fw_major_version: firmware major version
2823 * @fw_minor_version: firmware minor version
2824 * @fw_build: firmware build number
2825 * @api_major_version: major queue version
2826 * @api_minor_version: minor queue version
2827 * @cmd_details: pointer to command details structure or NULL
2829 * Get the firmware version from the admin queue commands
2831 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2832 u16 *fw_major_version, u16 *fw_minor_version,
2834 u16 *api_major_version, u16 *api_minor_version,
2835 struct i40e_asq_cmd_details *cmd_details)
2837 struct i40e_aq_desc desc;
2838 struct i40e_aqc_get_version *resp =
2839 (struct i40e_aqc_get_version *)&desc.params.raw;
2840 enum i40e_status_code status;
2842 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2844 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2846 if (status == I40E_SUCCESS) {
2847 if (fw_major_version != NULL)
2848 *fw_major_version = LE16_TO_CPU(resp->fw_major);
2849 if (fw_minor_version != NULL)
2850 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2851 if (fw_build != NULL)
2852 *fw_build = LE32_TO_CPU(resp->fw_build);
2853 if (api_major_version != NULL)
2854 *api_major_version = LE16_TO_CPU(resp->api_major);
2855 if (api_minor_version != NULL)
2856 *api_minor_version = LE16_TO_CPU(resp->api_minor);
2858 /* A workaround to fix the API version in SW */
2859 if (api_major_version && api_minor_version &&
2860 fw_major_version && fw_minor_version &&
2861 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2862 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2863 (*fw_major_version > 4)))
2864 *api_minor_version = 2;
2871 * i40e_aq_send_driver_version
2872 * @hw: pointer to the hw struct
2873 * @dv: driver's major, minor version
2874 * @cmd_details: pointer to command details structure or NULL
2876 * Send the driver version to the firmware
2878 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2879 struct i40e_driver_version *dv,
2880 struct i40e_asq_cmd_details *cmd_details)
2882 struct i40e_aq_desc desc;
2883 struct i40e_aqc_driver_version *cmd =
2884 (struct i40e_aqc_driver_version *)&desc.params.raw;
2885 enum i40e_status_code status;
2889 return I40E_ERR_PARAM;
2891 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2893 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2894 cmd->driver_major_ver = dv->major_version;
2895 cmd->driver_minor_ver = dv->minor_version;
2896 cmd->driver_build_ver = dv->build_version;
2897 cmd->driver_subbuild_ver = dv->subbuild_version;
2900 while (len < sizeof(dv->driver_string) &&
2901 (dv->driver_string[len] < 0x80) &&
2902 dv->driver_string[len])
2904 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2911 * i40e_get_link_status - get status of the HW network link
2912 * @hw: pointer to the hw struct
2913 * @link_up: pointer to bool (true/false = linkup/linkdown)
2915 * Variable link_up true if link is up, false if link is down.
2916 * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2918 * Side effect: LinkStatusEvent reporting becomes enabled
2920 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2922 enum i40e_status_code status = I40E_SUCCESS;
2924 if (hw->phy.get_link_info) {
2925 status = i40e_update_link_info(hw);
2927 if (status != I40E_SUCCESS)
2928 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2932 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2938 * i40e_updatelink_status - update status of the HW network link
2939 * @hw: pointer to the hw struct
2941 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2943 struct i40e_aq_get_phy_abilities_resp abilities;
2944 enum i40e_status_code status = I40E_SUCCESS;
2946 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2950 /* extra checking needed to ensure link info to user is timely */
2951 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2952 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2953 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2954 status = i40e_aq_get_phy_capabilities(hw, false, false,
2959 if (abilities.fec_cfg_curr_mod_ext_info &
2960 I40E_AQ_ENABLE_FEC_AUTO)
2961 hw->phy.link_info.req_fec_info =
2962 (I40E_AQ_REQUEST_FEC_KR |
2963 I40E_AQ_REQUEST_FEC_RS);
2965 hw->phy.link_info.req_fec_info =
2966 abilities.fec_cfg_curr_mod_ext_info &
2967 (I40E_AQ_REQUEST_FEC_KR |
2968 I40E_AQ_REQUEST_FEC_RS);
2970 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2971 sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2978 * i40e_get_link_speed
2979 * @hw: pointer to the hw struct
2981 * Returns the link speed of the adapter.
2983 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2985 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2986 enum i40e_status_code status = I40E_SUCCESS;
2988 if (hw->phy.get_link_info) {
2989 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2991 if (status != I40E_SUCCESS)
2992 goto i40e_link_speed_exit;
2995 speed = hw->phy.link_info.link_speed;
2997 i40e_link_speed_exit:
3002 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
3003 * @hw: pointer to the hw struct
3004 * @uplink_seid: the MAC or other gizmo SEID
3005 * @downlink_seid: the VSI SEID
3006 * @enabled_tc: bitmap of TCs to be enabled
3007 * @default_port: true for default port VSI, false for control port
3008 * @veb_seid: pointer to where to put the resulting VEB SEID
3009 * @enable_stats: true to turn on VEB stats
3010 * @cmd_details: pointer to command details structure or NULL
3012 * This asks the FW to add a VEB between the uplink and downlink
3013 * elements. If the uplink SEID is 0, this will be a floating VEB.
3015 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
3016 u16 downlink_seid, u8 enabled_tc,
3017 bool default_port, u16 *veb_seid,
3019 struct i40e_asq_cmd_details *cmd_details)
3021 struct i40e_aq_desc desc;
3022 struct i40e_aqc_add_veb *cmd =
3023 (struct i40e_aqc_add_veb *)&desc.params.raw;
3024 struct i40e_aqc_add_veb_completion *resp =
3025 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
3026 enum i40e_status_code status;
3029 /* SEIDs need to either both be set or both be 0 for floating VEB */
3030 if (!!uplink_seid != !!downlink_seid)
3031 return I40E_ERR_PARAM;
3033 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
3035 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
3036 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
3037 cmd->enable_tcs = enabled_tc;
3039 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
3041 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
3043 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
3045 /* reverse logic here: set the bitflag to disable the stats */
3047 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
3049 cmd->veb_flags = CPU_TO_LE16(veb_flags);
3051 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3053 if (!status && veb_seid)
3054 *veb_seid = LE16_TO_CPU(resp->veb_seid);
3060 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
3061 * @hw: pointer to the hw struct
3062 * @veb_seid: the SEID of the VEB to query
3063 * @switch_id: the uplink switch id
3064 * @floating: set to true if the VEB is floating
3065 * @statistic_index: index of the stats counter block for this VEB
3066 * @vebs_used: number of VEB's used by function
3067 * @vebs_free: total VEB's not reserved by any function
3068 * @cmd_details: pointer to command details structure or NULL
3070 * This retrieves the parameters for a particular VEB, specified by
3071 * uplink_seid, and returns them to the caller.
3073 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
3074 u16 veb_seid, u16 *switch_id,
3075 bool *floating, u16 *statistic_index,
3076 u16 *vebs_used, u16 *vebs_free,
3077 struct i40e_asq_cmd_details *cmd_details)
3079 struct i40e_aq_desc desc;
3080 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
3081 (struct i40e_aqc_get_veb_parameters_completion *)
3083 enum i40e_status_code status;
3086 return I40E_ERR_PARAM;
3088 i40e_fill_default_direct_cmd_desc(&desc,
3089 i40e_aqc_opc_get_veb_parameters);
3090 cmd_resp->seid = CPU_TO_LE16(veb_seid);
3092 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3097 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
3098 if (statistic_index)
3099 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
3101 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
3103 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
3105 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
3107 if (flags & I40E_AQC_ADD_VEB_FLOATING)
3118 * i40e_prepare_add_macvlan
3119 * @mv_list: list of macvlans to be added
3120 * @desc: pointer to AQ descriptor structure
3121 * @count: length of the list
3122 * @seid: VSI for the mac address
3124 * Internal helper function that prepares the add macvlan request
3125 * and returns the buffer size.
3128 i40e_prepare_add_macvlan(struct i40e_aqc_add_macvlan_element_data *mv_list,
3129 struct i40e_aq_desc *desc, u16 count, u16 seid)
3131 struct i40e_aqc_macvlan *cmd =
3132 (struct i40e_aqc_macvlan *)&desc->params.raw;
3136 buf_size = count * sizeof(*mv_list);
3138 /* prep the rest of the request */
3139 i40e_fill_default_direct_cmd_desc(desc, i40e_aqc_opc_add_macvlan);
3140 cmd->num_addresses = CPU_TO_LE16(count);
3141 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3145 for (i = 0; i < count; i++)
3146 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
3148 CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
3150 desc->flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3151 if (buf_size > I40E_AQ_LARGE_BUF)
3152 desc->flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3158 * i40e_aq_add_macvlan
3159 * @hw: pointer to the hw struct
3160 * @seid: VSI for the mac address
3161 * @mv_list: list of macvlans to be added
3162 * @count: length of the list
3163 * @cmd_details: pointer to command details structure or NULL
3165 * Add MAC/VLAN addresses to the HW filtering
3167 enum i40e_status_code
3168 i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
3169 struct i40e_aqc_add_macvlan_element_data *mv_list,
3170 u16 count, struct i40e_asq_cmd_details *cmd_details)
3172 struct i40e_aq_desc desc;
3173 enum i40e_status_code status;
3176 if (count == 0 || !mv_list || !hw)
3177 return I40E_ERR_PARAM;
3179 buf_size = i40e_prepare_add_macvlan(mv_list, &desc, count, seid);
3181 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3188 * i40e_aq_add_macvlan_v2
3189 * @hw: pointer to the hw struct
3190 * @seid: VSI for the mac address
3191 * @mv_list: list of macvlans to be added
3192 * @count: length of the list
3193 * @cmd_details: pointer to command details structure or NULL
3194 * @aq_status: pointer to Admin Queue status return value
3196 * Add MAC/VLAN addresses to the HW filtering.
3197 * The _v2 version returns the last Admin Queue status in aq_status
3198 * to avoid race conditions in access to hw->aq.asq_last_status.
3199 * It also calls _v2 versions of asq_send_command functions to
3200 * get the aq_status on the stack.
3202 enum i40e_status_code
3203 i40e_aq_add_macvlan_v2(struct i40e_hw *hw, u16 seid,
3204 struct i40e_aqc_add_macvlan_element_data *mv_list,
3205 u16 count, struct i40e_asq_cmd_details *cmd_details,
3206 enum i40e_admin_queue_err *aq_status)
3208 struct i40e_aq_desc desc;
3209 enum i40e_status_code status;
3212 if (count == 0 || !mv_list || !hw)
3213 return I40E_ERR_PARAM;
3215 buf_size = i40e_prepare_add_macvlan(mv_list, &desc, count, seid);
3217 status = i40e_asq_send_command_v2(hw, &desc, mv_list, buf_size,
3218 cmd_details, aq_status);
3224 * i40e_aq_remove_macvlan
3225 * @hw: pointer to the hw struct
3226 * @seid: VSI for the mac address
3227 * @mv_list: list of macvlans to be removed
3228 * @count: length of the list
3229 * @cmd_details: pointer to command details structure or NULL
3231 * Remove MAC/VLAN addresses from the HW filtering
3233 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
3234 struct i40e_aqc_remove_macvlan_element_data *mv_list,
3235 u16 count, struct i40e_asq_cmd_details *cmd_details)
3237 struct i40e_aq_desc desc;
3238 struct i40e_aqc_macvlan *cmd =
3239 (struct i40e_aqc_macvlan *)&desc.params.raw;
3240 enum i40e_status_code status;
3243 if (count == 0 || !mv_list || !hw)
3244 return I40E_ERR_PARAM;
3246 buf_size = count * sizeof(*mv_list);
3248 /* prep the rest of the request */
3249 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
3250 cmd->num_addresses = CPU_TO_LE16(count);
3251 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3255 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3256 if (buf_size > I40E_AQ_LARGE_BUF)
3257 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3259 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3266 * i40e_aq_remove_macvlan_v2
3267 * @hw: pointer to the hw struct
3268 * @seid: VSI for the mac address
3269 * @mv_list: list of macvlans to be removed
3270 * @count: length of the list
3271 * @cmd_details: pointer to command details structure or NULL
3272 * @aq_status: pointer to Admin Queue status return value
3274 * Remove MAC/VLAN addresses from the HW filtering.
3275 * The _v2 version returns the last Admin Queue status in aq_status
3276 * to avoid race conditions in access to hw->aq.asq_last_status.
3277 * It also calls _v2 versions of asq_send_command functions to
3278 * get the aq_status on the stack.
3280 enum i40e_status_code
3281 i40e_aq_remove_macvlan_v2(struct i40e_hw *hw, u16 seid,
3282 struct i40e_aqc_remove_macvlan_element_data *mv_list,
3283 u16 count, struct i40e_asq_cmd_details *cmd_details,
3284 enum i40e_admin_queue_err *aq_status)
3286 struct i40e_aq_desc desc;
3287 struct i40e_aqc_macvlan *cmd =
3288 (struct i40e_aqc_macvlan *)&desc.params.raw;
3289 enum i40e_status_code status;
3292 if (count == 0 || !mv_list || !hw)
3293 return I40E_ERR_PARAM;
3295 buf_size = count * sizeof(*mv_list);
3297 /* prep the rest of the request */
3298 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
3299 cmd->num_addresses = CPU_TO_LE16(count);
3300 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3304 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3305 if (buf_size > I40E_AQ_LARGE_BUF)
3306 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3308 status = i40e_asq_send_command_v2(hw, &desc, mv_list, buf_size,
3309 cmd_details, aq_status);
3315 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3316 * @hw: pointer to the hw struct
3317 * @opcode: AQ opcode for add or delete mirror rule
3318 * @sw_seid: Switch SEID (to which rule refers)
3319 * @rule_type: Rule Type (ingress/egress/VLAN)
3320 * @id: Destination VSI SEID or Rule ID
3321 * @count: length of the list
3322 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3323 * @cmd_details: pointer to command details structure or NULL
3324 * @rule_id: Rule ID returned from FW
3325 * @rules_used: Number of rules used in internal switch
3326 * @rules_free: Number of rules free in internal switch
3328 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3329 * VEBs/VEPA elements only
3331 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3332 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3333 u16 count, __le16 *mr_list,
3334 struct i40e_asq_cmd_details *cmd_details,
3335 u16 *rule_id, u16 *rules_used, u16 *rules_free)
3337 struct i40e_aq_desc desc;
3338 struct i40e_aqc_add_delete_mirror_rule *cmd =
3339 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3340 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3341 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3342 enum i40e_status_code status;
3345 buf_size = count * sizeof(*mr_list);
3347 /* prep the rest of the request */
3348 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3349 cmd->seid = CPU_TO_LE16(sw_seid);
3350 cmd->rule_type = CPU_TO_LE16(rule_type &
3351 I40E_AQC_MIRROR_RULE_TYPE_MASK);
3352 cmd->num_entries = CPU_TO_LE16(count);
3353 /* Dest VSI for add, rule_id for delete */
3354 cmd->destination = CPU_TO_LE16(id);
3356 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3358 if (buf_size > I40E_AQ_LARGE_BUF)
3359 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3362 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3364 if (status == I40E_SUCCESS ||
3365 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3367 *rule_id = LE16_TO_CPU(resp->rule_id);
3369 *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3371 *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3377 * i40e_aq_add_mirrorrule - add a mirror rule
3378 * @hw: pointer to the hw struct
3379 * @sw_seid: Switch SEID (to which rule refers)
3380 * @rule_type: Rule Type (ingress/egress/VLAN)
3381 * @dest_vsi: SEID of VSI to which packets will be mirrored
3382 * @count: length of the list
3383 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3384 * @cmd_details: pointer to command details structure or NULL
3385 * @rule_id: Rule ID returned from FW
3386 * @rules_used: Number of rules used in internal switch
3387 * @rules_free: Number of rules free in internal switch
3389 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3391 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3392 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3393 struct i40e_asq_cmd_details *cmd_details,
3394 u16 *rule_id, u16 *rules_used, u16 *rules_free)
3396 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3397 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3398 if (count == 0 || !mr_list)
3399 return I40E_ERR_PARAM;
3402 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3403 rule_type, dest_vsi, count, mr_list,
3404 cmd_details, rule_id, rules_used, rules_free);
3408 * i40e_aq_delete_mirrorrule - delete a mirror rule
3409 * @hw: pointer to the hw struct
3410 * @sw_seid: Switch SEID (to which rule refers)
3411 * @rule_type: Rule Type (ingress/egress/VLAN)
3412 * @count: length of the list
3413 * @rule_id: Rule ID that is returned in the receive desc as part of
3415 * @mr_list: list of mirrored VLAN IDs to be removed
3416 * @cmd_details: pointer to command details structure or NULL
3417 * @rules_used: Number of rules used in internal switch
3418 * @rules_free: Number of rules free in internal switch
3420 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3422 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3423 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3424 struct i40e_asq_cmd_details *cmd_details,
3425 u16 *rules_used, u16 *rules_free)
3427 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3428 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3429 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3430 * mirroring. For other rule_type, count and rule_type should
3433 if (count == 0 || !mr_list)
3434 return I40E_ERR_PARAM;
3437 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3438 rule_type, rule_id, count, mr_list,
3439 cmd_details, NULL, rules_used, rules_free);
3443 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3444 * @hw: pointer to the hw struct
3445 * @seid: VSI for the vlan filters
3446 * @v_list: list of vlan filters to be added
3447 * @count: length of the list
3448 * @cmd_details: pointer to command details structure or NULL
3450 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3451 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3452 u8 count, struct i40e_asq_cmd_details *cmd_details)
3454 struct i40e_aq_desc desc;
3455 struct i40e_aqc_macvlan *cmd =
3456 (struct i40e_aqc_macvlan *)&desc.params.raw;
3457 enum i40e_status_code status;
3460 if (count == 0 || !v_list || !hw)
3461 return I40E_ERR_PARAM;
3463 buf_size = count * sizeof(*v_list);
3465 /* prep the rest of the request */
3466 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3467 cmd->num_addresses = CPU_TO_LE16(count);
3468 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3472 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3473 if (buf_size > I40E_AQ_LARGE_BUF)
3474 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3476 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3483 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3484 * @hw: pointer to the hw struct
3485 * @seid: VSI for the vlan filters
3486 * @v_list: list of macvlans to be removed
3487 * @count: length of the list
3488 * @cmd_details: pointer to command details structure or NULL
3490 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3491 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3492 u8 count, struct i40e_asq_cmd_details *cmd_details)
3494 struct i40e_aq_desc desc;
3495 struct i40e_aqc_macvlan *cmd =
3496 (struct i40e_aqc_macvlan *)&desc.params.raw;
3497 enum i40e_status_code status;
3500 if (count == 0 || !v_list || !hw)
3501 return I40E_ERR_PARAM;
3503 buf_size = count * sizeof(*v_list);
3505 /* prep the rest of the request */
3506 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3507 cmd->num_addresses = CPU_TO_LE16(count);
3508 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3512 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3513 if (buf_size > I40E_AQ_LARGE_BUF)
3514 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3516 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3523 * i40e_aq_send_msg_to_vf
3524 * @hw: pointer to the hardware structure
3525 * @vfid: vf id to send msg
3526 * @v_opcode: opcodes for VF-PF communication
3527 * @v_retval: return error code
3528 * @msg: pointer to the msg buffer
3529 * @msglen: msg length
3530 * @cmd_details: pointer to command details
3534 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3535 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3536 struct i40e_asq_cmd_details *cmd_details)
3538 struct i40e_aq_desc desc;
3539 struct i40e_aqc_pf_vf_message *cmd =
3540 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3541 enum i40e_status_code status;
3543 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3544 cmd->id = CPU_TO_LE32(vfid);
3545 desc.cookie_high = CPU_TO_LE32(v_opcode);
3546 desc.cookie_low = CPU_TO_LE32(v_retval);
3547 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3549 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3551 if (msglen > I40E_AQ_LARGE_BUF)
3552 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3553 desc.datalen = CPU_TO_LE16(msglen);
3555 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3561 * i40e_aq_debug_read_register
3562 * @hw: pointer to the hw struct
3563 * @reg_addr: register address
3564 * @reg_val: register value
3565 * @cmd_details: pointer to command details structure or NULL
3567 * Read the register using the admin queue commands
3569 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3570 u32 reg_addr, u64 *reg_val,
3571 struct i40e_asq_cmd_details *cmd_details)
3573 struct i40e_aq_desc desc;
3574 struct i40e_aqc_debug_reg_read_write *cmd_resp =
3575 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3576 enum i40e_status_code status;
3578 if (reg_val == NULL)
3579 return I40E_ERR_PARAM;
3581 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3583 cmd_resp->address = CPU_TO_LE32(reg_addr);
3585 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3587 if (status == I40E_SUCCESS) {
3588 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3589 (u64)LE32_TO_CPU(cmd_resp->value_low);
3596 * i40e_aq_debug_write_register
3597 * @hw: pointer to the hw struct
3598 * @reg_addr: register address
3599 * @reg_val: register value
3600 * @cmd_details: pointer to command details structure or NULL
3602 * Write to a register using the admin queue commands
3604 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3605 u32 reg_addr, u64 reg_val,
3606 struct i40e_asq_cmd_details *cmd_details)
3608 struct i40e_aq_desc desc;
3609 struct i40e_aqc_debug_reg_read_write *cmd =
3610 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3611 enum i40e_status_code status;
3613 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3615 cmd->address = CPU_TO_LE32(reg_addr);
3616 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3617 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3619 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3625 * i40e_aq_request_resource
3626 * @hw: pointer to the hw struct
3627 * @resource: resource id
3628 * @access: access type
3629 * @sdp_number: resource number
3630 * @timeout: the maximum time in ms that the driver may hold the resource
3631 * @cmd_details: pointer to command details structure or NULL
3633 * requests common resource using the admin queue commands
3635 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3636 enum i40e_aq_resources_ids resource,
3637 enum i40e_aq_resource_access_type access,
3638 u8 sdp_number, u64 *timeout,
3639 struct i40e_asq_cmd_details *cmd_details)
3641 struct i40e_aq_desc desc;
3642 struct i40e_aqc_request_resource *cmd_resp =
3643 (struct i40e_aqc_request_resource *)&desc.params.raw;
3644 enum i40e_status_code status;
3646 DEBUGFUNC("i40e_aq_request_resource");
3648 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3650 cmd_resp->resource_id = CPU_TO_LE16(resource);
3651 cmd_resp->access_type = CPU_TO_LE16(access);
3652 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3654 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3655 /* The completion specifies the maximum time in ms that the driver
3656 * may hold the resource in the Timeout field.
3657 * If the resource is held by someone else, the command completes with
3658 * busy return value and the timeout field indicates the maximum time
3659 * the current owner of the resource has to free it.
3661 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3662 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3668 * i40e_aq_release_resource
3669 * @hw: pointer to the hw struct
3670 * @resource: resource id
3671 * @sdp_number: resource number
3672 * @cmd_details: pointer to command details structure or NULL
3674 * release common resource using the admin queue commands
3676 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3677 enum i40e_aq_resources_ids resource,
3679 struct i40e_asq_cmd_details *cmd_details)
3681 struct i40e_aq_desc desc;
3682 struct i40e_aqc_request_resource *cmd =
3683 (struct i40e_aqc_request_resource *)&desc.params.raw;
3684 enum i40e_status_code status;
3686 DEBUGFUNC("i40e_aq_release_resource");
3688 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3690 cmd->resource_id = CPU_TO_LE16(resource);
3691 cmd->resource_number = CPU_TO_LE32(sdp_number);
3693 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3700 * @hw: pointer to the hw struct
3701 * @module_pointer: module pointer location in words from the NVM beginning
3702 * @offset: byte offset from the module beginning
3703 * @length: length of the section to be read (in bytes from the offset)
3704 * @data: command buffer (size [bytes] = length)
3705 * @last_command: tells if this is the last command in a series
3706 * @cmd_details: pointer to command details structure or NULL
3708 * Read the NVM using the admin queue commands
3710 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3711 u32 offset, u16 length, void *data,
3713 struct i40e_asq_cmd_details *cmd_details)
3715 struct i40e_aq_desc desc;
3716 struct i40e_aqc_nvm_update *cmd =
3717 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3718 enum i40e_status_code status;
3720 DEBUGFUNC("i40e_aq_read_nvm");
3722 /* In offset the highest byte must be zeroed. */
3723 if (offset & 0xFF000000) {
3724 status = I40E_ERR_PARAM;
3725 goto i40e_aq_read_nvm_exit;
3728 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3730 /* If this is the last command in a series, set the proper flag. */
3732 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3733 cmd->module_pointer = module_pointer;
3734 cmd->offset = CPU_TO_LE32(offset);
3735 cmd->length = CPU_TO_LE16(length);
3737 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3738 if (length > I40E_AQ_LARGE_BUF)
3739 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3741 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3743 i40e_aq_read_nvm_exit:
3748 * i40e_aq_read_nvm_config - read an nvm config block
3749 * @hw: pointer to the hw struct
3750 * @cmd_flags: NVM access admin command bits
3751 * @field_id: field or feature id
3752 * @data: buffer for result
3753 * @buf_size: buffer size
3754 * @element_count: pointer to count of elements read by FW
3755 * @cmd_details: pointer to command details structure or NULL
3757 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3758 u8 cmd_flags, u32 field_id, void *data,
3759 u16 buf_size, u16 *element_count,
3760 struct i40e_asq_cmd_details *cmd_details)
3762 struct i40e_aq_desc desc;
3763 struct i40e_aqc_nvm_config_read *cmd =
3764 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3765 enum i40e_status_code status;
3767 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3768 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3769 if (buf_size > I40E_AQ_LARGE_BUF)
3770 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3772 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3773 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3774 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3775 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3777 cmd->element_id_msw = 0;
3779 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3781 if (!status && element_count)
3782 *element_count = LE16_TO_CPU(cmd->element_count);
3788 * i40e_aq_write_nvm_config - write an nvm config block
3789 * @hw: pointer to the hw struct
3790 * @cmd_flags: NVM access admin command bits
3791 * @data: buffer for result
3792 * @buf_size: buffer size
3793 * @element_count: count of elements to be written
3794 * @cmd_details: pointer to command details structure or NULL
3796 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3797 u8 cmd_flags, void *data, u16 buf_size,
3799 struct i40e_asq_cmd_details *cmd_details)
3801 struct i40e_aq_desc desc;
3802 struct i40e_aqc_nvm_config_write *cmd =
3803 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3804 enum i40e_status_code status;
3806 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3807 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3808 if (buf_size > I40E_AQ_LARGE_BUF)
3809 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3811 cmd->element_count = CPU_TO_LE16(element_count);
3812 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3813 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3819 * i40e_aq_nvm_update_in_process
3820 * @hw: pointer to the hw struct
3821 * @update_flow_state: True indicates that update flow starts, false that ends
3822 * @cmd_details: pointer to command details structure or NULL
3824 * Indicate NVM update in process.
3826 enum i40e_status_code
3827 i40e_aq_nvm_update_in_process(struct i40e_hw *hw,
3828 bool update_flow_state,
3829 struct i40e_asq_cmd_details *cmd_details)
3831 struct i40e_aq_desc desc;
3832 struct i40e_aqc_nvm_update_in_process *cmd =
3833 (struct i40e_aqc_nvm_update_in_process *)&desc.params.raw;
3834 enum i40e_status_code status;
3836 i40e_fill_default_direct_cmd_desc(&desc,
3837 i40e_aqc_opc_nvm_update_in_process);
3839 cmd->command = I40E_AQ_UPDATE_FLOW_END;
3841 if (update_flow_state)
3842 cmd->command |= I40E_AQ_UPDATE_FLOW_START;
3844 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3850 * i40e_aq_min_rollback_rev_update - triggers an ow after update
3851 * @hw: pointer to the hw struct
3852 * @mode: opt-in mode, 1b for single module update, 0b for bulk update
3853 * @module: module to be updated. Ignored if mode is 0b
3854 * @min_rrev: value of the new minimal version. Ignored if mode is 0b
3855 * @cmd_details: pointer to command details structure or NULL
3857 enum i40e_status_code
3858 i40e_aq_min_rollback_rev_update(struct i40e_hw *hw, u8 mode, u8 module,
3860 struct i40e_asq_cmd_details *cmd_details)
3862 struct i40e_aq_desc desc;
3863 struct i40e_aqc_rollback_revision_update *cmd =
3864 (struct i40e_aqc_rollback_revision_update *)&desc.params.raw;
3865 enum i40e_status_code status;
3867 i40e_fill_default_direct_cmd_desc(&desc,
3868 i40e_aqc_opc_rollback_revision_update);
3869 cmd->optin_mode = mode;
3870 cmd->module_selected = module;
3871 cmd->min_rrev = min_rrev;
3873 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3879 * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3880 * @hw: pointer to the hw struct
3881 * @buff: buffer for result
3882 * @buff_size: buffer size
3883 * @cmd_details: pointer to command details structure or NULL
3885 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3886 void *buff, u16 buff_size,
3887 struct i40e_asq_cmd_details *cmd_details)
3889 struct i40e_aq_desc desc;
3890 enum i40e_status_code status;
3892 UNREFERENCED_2PARAMETER(buff, buff_size);
3894 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3895 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3896 if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3897 status = I40E_ERR_NOT_IMPLEMENTED;
3904 * @hw: pointer to the hw struct
3905 * @module_pointer: module pointer location in words from the NVM beginning
3906 * @offset: offset in the module (expressed in 4 KB from module's beginning)
3907 * @length: length of the section to be erased (expressed in 4 KB)
3908 * @last_command: tells if this is the last command in a series
3909 * @cmd_details: pointer to command details structure or NULL
3911 * Erase the NVM sector using the admin queue commands
3913 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3914 u32 offset, u16 length, bool last_command,
3915 struct i40e_asq_cmd_details *cmd_details)
3917 struct i40e_aq_desc desc;
3918 struct i40e_aqc_nvm_update *cmd =
3919 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3920 enum i40e_status_code status;
3922 DEBUGFUNC("i40e_aq_erase_nvm");
3924 /* In offset the highest byte must be zeroed. */
3925 if (offset & 0xFF000000) {
3926 status = I40E_ERR_PARAM;
3927 goto i40e_aq_erase_nvm_exit;
3930 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3932 /* If this is the last command in a series, set the proper flag. */
3934 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3935 cmd->module_pointer = module_pointer;
3936 cmd->offset = CPU_TO_LE32(offset);
3937 cmd->length = CPU_TO_LE16(length);
3939 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3941 i40e_aq_erase_nvm_exit:
3946 * i40e_parse_discover_capabilities
3947 * @hw: pointer to the hw struct
3948 * @buff: pointer to a buffer containing device/function capability records
3949 * @cap_count: number of capability records in the list
3950 * @list_type_opc: type of capabilities list to parse
3952 * Parse the device/function capabilities list.
3954 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3956 enum i40e_admin_queue_opc list_type_opc)
3958 struct i40e_aqc_list_capabilities_element_resp *cap;
3959 u32 valid_functions, num_functions;
3960 u32 number, logical_id, phys_id;
3961 struct i40e_hw_capabilities *p;
3962 enum i40e_status_code status;
3963 u16 id, ocp_cfg_word0;
3967 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3969 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3970 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3971 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3972 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3976 for (i = 0; i < cap_count; i++, cap++) {
3977 id = LE16_TO_CPU(cap->id);
3978 number = LE32_TO_CPU(cap->number);
3979 logical_id = LE32_TO_CPU(cap->logical_id);
3980 phys_id = LE32_TO_CPU(cap->phys_id);
3981 major_rev = cap->major_rev;
3984 case I40E_AQ_CAP_ID_SWITCH_MODE:
3985 p->switch_mode = number;
3986 i40e_debug(hw, I40E_DEBUG_INIT,
3987 "HW Capability: Switch mode = %d\n",
3990 case I40E_AQ_CAP_ID_MNG_MODE:
3991 p->management_mode = number;
3992 if (major_rev > 1) {
3993 p->mng_protocols_over_mctp = logical_id;
3994 i40e_debug(hw, I40E_DEBUG_INIT,
3995 "HW Capability: Protocols over MCTP = %d\n",
3996 p->mng_protocols_over_mctp);
3998 p->mng_protocols_over_mctp = 0;
4000 i40e_debug(hw, I40E_DEBUG_INIT,
4001 "HW Capability: Management Mode = %d\n",
4002 p->management_mode);
4004 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
4005 p->npar_enable = number;
4006 i40e_debug(hw, I40E_DEBUG_INIT,
4007 "HW Capability: NPAR enable = %d\n",
4010 case I40E_AQ_CAP_ID_OS2BMC_CAP:
4012 i40e_debug(hw, I40E_DEBUG_INIT,
4013 "HW Capability: OS2BMC = %d\n", p->os2bmc);
4015 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
4016 p->valid_functions = number;
4017 i40e_debug(hw, I40E_DEBUG_INIT,
4018 "HW Capability: Valid Functions = %d\n",
4019 p->valid_functions);
4021 case I40E_AQ_CAP_ID_SRIOV:
4023 p->sr_iov_1_1 = true;
4024 i40e_debug(hw, I40E_DEBUG_INIT,
4025 "HW Capability: SR-IOV = %d\n",
4028 case I40E_AQ_CAP_ID_VF:
4029 p->num_vfs = number;
4030 p->vf_base_id = logical_id;
4031 i40e_debug(hw, I40E_DEBUG_INIT,
4032 "HW Capability: VF count = %d\n",
4034 i40e_debug(hw, I40E_DEBUG_INIT,
4035 "HW Capability: VF base_id = %d\n",
4038 case I40E_AQ_CAP_ID_VMDQ:
4041 i40e_debug(hw, I40E_DEBUG_INIT,
4042 "HW Capability: VMDQ = %d\n", p->vmdq);
4044 case I40E_AQ_CAP_ID_8021QBG:
4046 p->evb_802_1_qbg = true;
4047 i40e_debug(hw, I40E_DEBUG_INIT,
4048 "HW Capability: 802.1Qbg = %d\n", number);
4050 case I40E_AQ_CAP_ID_8021QBR:
4052 p->evb_802_1_qbh = true;
4053 i40e_debug(hw, I40E_DEBUG_INIT,
4054 "HW Capability: 802.1Qbh = %d\n", number);
4056 case I40E_AQ_CAP_ID_VSI:
4057 p->num_vsis = number;
4058 i40e_debug(hw, I40E_DEBUG_INIT,
4059 "HW Capability: VSI count = %d\n",
4062 case I40E_AQ_CAP_ID_DCB:
4065 p->enabled_tcmap = logical_id;
4068 i40e_debug(hw, I40E_DEBUG_INIT,
4069 "HW Capability: DCB = %d\n", p->dcb);
4070 i40e_debug(hw, I40E_DEBUG_INIT,
4071 "HW Capability: TC Mapping = %d\n",
4073 i40e_debug(hw, I40E_DEBUG_INIT,
4074 "HW Capability: TC Max = %d\n", p->maxtc);
4076 case I40E_AQ_CAP_ID_FCOE:
4079 i40e_debug(hw, I40E_DEBUG_INIT,
4080 "HW Capability: FCOE = %d\n", p->fcoe);
4082 case I40E_AQ_CAP_ID_ISCSI:
4085 i40e_debug(hw, I40E_DEBUG_INIT,
4086 "HW Capability: iSCSI = %d\n", p->iscsi);
4088 case I40E_AQ_CAP_ID_RSS:
4090 p->rss_table_size = number;
4091 p->rss_table_entry_width = logical_id;
4092 i40e_debug(hw, I40E_DEBUG_INIT,
4093 "HW Capability: RSS = %d\n", p->rss);
4094 i40e_debug(hw, I40E_DEBUG_INIT,
4095 "HW Capability: RSS table size = %d\n",
4097 i40e_debug(hw, I40E_DEBUG_INIT,
4098 "HW Capability: RSS table width = %d\n",
4099 p->rss_table_entry_width);
4101 case I40E_AQ_CAP_ID_RXQ:
4102 p->num_rx_qp = number;
4103 p->base_queue = phys_id;
4104 i40e_debug(hw, I40E_DEBUG_INIT,
4105 "HW Capability: Rx QP = %d\n", number);
4106 i40e_debug(hw, I40E_DEBUG_INIT,
4107 "HW Capability: base_queue = %d\n",
4110 case I40E_AQ_CAP_ID_TXQ:
4111 p->num_tx_qp = number;
4112 p->base_queue = phys_id;
4113 i40e_debug(hw, I40E_DEBUG_INIT,
4114 "HW Capability: Tx QP = %d\n", number);
4115 i40e_debug(hw, I40E_DEBUG_INIT,
4116 "HW Capability: base_queue = %d\n",
4119 case I40E_AQ_CAP_ID_MSIX:
4120 p->num_msix_vectors = number;
4121 i40e_debug(hw, I40E_DEBUG_INIT,
4122 "HW Capability: MSIX vector count = %d\n",
4123 p->num_msix_vectors);
4125 case I40E_AQ_CAP_ID_VF_MSIX:
4126 p->num_msix_vectors_vf = number;
4127 i40e_debug(hw, I40E_DEBUG_INIT,
4128 "HW Capability: MSIX VF vector count = %d\n",
4129 p->num_msix_vectors_vf);
4131 case I40E_AQ_CAP_ID_FLEX10:
4132 if (major_rev == 1) {
4134 p->flex10_enable = true;
4135 p->flex10_capable = true;
4138 /* Capability revision >= 2 */
4140 p->flex10_enable = true;
4142 p->flex10_capable = true;
4144 p->flex10_mode = logical_id;
4145 p->flex10_status = phys_id;
4146 i40e_debug(hw, I40E_DEBUG_INIT,
4147 "HW Capability: Flex10 mode = %d\n",
4149 i40e_debug(hw, I40E_DEBUG_INIT,
4150 "HW Capability: Flex10 status = %d\n",
4153 case I40E_AQ_CAP_ID_CEM:
4156 i40e_debug(hw, I40E_DEBUG_INIT,
4157 "HW Capability: CEM = %d\n", p->mgmt_cem);
4159 case I40E_AQ_CAP_ID_IWARP:
4162 i40e_debug(hw, I40E_DEBUG_INIT,
4163 "HW Capability: iWARP = %d\n", p->iwarp);
4165 case I40E_AQ_CAP_ID_LED:
4166 if (phys_id < I40E_HW_CAP_MAX_GPIO)
4167 p->led[phys_id] = true;
4168 i40e_debug(hw, I40E_DEBUG_INIT,
4169 "HW Capability: LED - PIN %d\n", phys_id);
4171 case I40E_AQ_CAP_ID_SDP:
4172 if (phys_id < I40E_HW_CAP_MAX_GPIO)
4173 p->sdp[phys_id] = true;
4174 i40e_debug(hw, I40E_DEBUG_INIT,
4175 "HW Capability: SDP - PIN %d\n", phys_id);
4177 case I40E_AQ_CAP_ID_MDIO:
4179 p->mdio_port_num = phys_id;
4180 p->mdio_port_mode = logical_id;
4182 i40e_debug(hw, I40E_DEBUG_INIT,
4183 "HW Capability: MDIO port number = %d\n",
4185 i40e_debug(hw, I40E_DEBUG_INIT,
4186 "HW Capability: MDIO port mode = %d\n",
4189 case I40E_AQ_CAP_ID_1588:
4191 p->ieee_1588 = true;
4192 i40e_debug(hw, I40E_DEBUG_INIT,
4193 "HW Capability: IEEE 1588 = %d\n",
4196 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
4198 p->fd_filters_guaranteed = number;
4199 p->fd_filters_best_effort = logical_id;
4200 i40e_debug(hw, I40E_DEBUG_INIT,
4201 "HW Capability: Flow Director = 1\n");
4202 i40e_debug(hw, I40E_DEBUG_INIT,
4203 "HW Capability: Guaranteed FD filters = %d\n",
4204 p->fd_filters_guaranteed);
4206 case I40E_AQ_CAP_ID_WSR_PROT:
4207 p->wr_csr_prot = (u64)number;
4208 p->wr_csr_prot |= (u64)logical_id << 32;
4209 i40e_debug(hw, I40E_DEBUG_INIT,
4210 "HW Capability: wr_csr_prot = 0x%" PRIX64 "\n\n",
4211 (p->wr_csr_prot & 0xffff));
4213 case I40E_AQ_CAP_ID_DIS_UNUSED_PORTS:
4214 p->dis_unused_ports = (bool)number;
4215 i40e_debug(hw, I40E_DEBUG_INIT,
4216 "HW Capability: dis_unused_ports = %d\n\n",
4217 p->dis_unused_ports);
4219 case I40E_AQ_CAP_ID_NVM_MGMT:
4220 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
4221 p->sec_rev_disabled = true;
4222 if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
4223 p->update_disabled = true;
4225 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
4226 hw->num_wol_proxy_filters = (u16)number;
4227 hw->wol_proxy_vsi_seid = (u16)logical_id;
4228 p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
4229 if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
4230 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
4232 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
4233 p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
4234 i40e_debug(hw, I40E_DEBUG_INIT,
4235 "HW Capability: WOL proxy filters = %d\n",
4236 hw->num_wol_proxy_filters);
4244 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
4246 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
4249 /* count the enabled ports (aka the "not disabled" ports) */
4251 for (i = 0; i < 4; i++) {
4252 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
4255 /* use AQ read to get the physical register offset instead
4256 * of the port relative offset
4258 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
4259 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
4263 /* OCP cards case: if a mezz is removed the ethernet port is at
4264 * disabled state in PRTGEN_CNF register. Additional NVM read is
4265 * needed in order to check if we are dealing with OCP card.
4266 * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting
4267 * physical ports results in wrong partition id calculation and thus
4268 * not supporting WoL.
4270 if (hw->mac.type == I40E_MAC_X722) {
4271 if (i40e_acquire_nvm(hw, I40E_RESOURCE_READ) == I40E_SUCCESS) {
4272 status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR,
4273 2 * I40E_SR_OCP_CFG_WORD0,
4274 sizeof(ocp_cfg_word0),
4275 &ocp_cfg_word0, true, NULL);
4276 if (status == I40E_SUCCESS &&
4277 (ocp_cfg_word0 & I40E_SR_OCP_ENABLED))
4279 i40e_release_nvm(hw);
4283 valid_functions = p->valid_functions;
4285 while (valid_functions) {
4286 if (valid_functions & 1)
4288 valid_functions >>= 1;
4291 /* partition id is 1-based, and functions are evenly spread
4292 * across the ports as partitions
4294 if (hw->num_ports != 0) {
4295 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
4296 hw->num_partitions = num_functions / hw->num_ports;
4299 /* additional HW specific goodies that might
4300 * someday be HW version specific
4302 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
4306 * i40e_aq_discover_capabilities
4307 * @hw: pointer to the hw struct
4308 * @buff: a virtual buffer to hold the capabilities
4309 * @buff_size: Size of the virtual buffer
4310 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
4311 * @list_type_opc: capabilities type to discover - pass in the command opcode
4312 * @cmd_details: pointer to command details structure or NULL
4314 * Get the device capabilities descriptions from the firmware
4316 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
4317 void *buff, u16 buff_size, u16 *data_size,
4318 enum i40e_admin_queue_opc list_type_opc,
4319 struct i40e_asq_cmd_details *cmd_details)
4321 struct i40e_aqc_list_capabilites *cmd;
4322 struct i40e_aq_desc desc;
4323 enum i40e_status_code status = I40E_SUCCESS;
4325 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
4327 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
4328 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
4329 status = I40E_ERR_PARAM;
4333 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
4335 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4336 if (buff_size > I40E_AQ_LARGE_BUF)
4337 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4339 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4340 *data_size = LE16_TO_CPU(desc.datalen);
4345 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
4353 * i40e_aq_update_nvm
4354 * @hw: pointer to the hw struct
4355 * @module_pointer: module pointer location in words from the NVM beginning
4356 * @offset: byte offset from the module beginning
4357 * @length: length of the section to be written (in bytes from the offset)
4358 * @data: command buffer (size [bytes] = length)
4359 * @last_command: tells if this is the last command in a series
4360 * @preservation_flags: Preservation mode flags
4361 * @cmd_details: pointer to command details structure or NULL
4363 * Update the NVM using the admin queue commands
4365 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
4366 u32 offset, u16 length, void *data,
4367 bool last_command, u8 preservation_flags,
4368 struct i40e_asq_cmd_details *cmd_details)
4370 struct i40e_aq_desc desc;
4371 struct i40e_aqc_nvm_update *cmd =
4372 (struct i40e_aqc_nvm_update *)&desc.params.raw;
4373 enum i40e_status_code status;
4375 DEBUGFUNC("i40e_aq_update_nvm");
4377 /* In offset the highest byte must be zeroed. */
4378 if (offset & 0xFF000000) {
4379 status = I40E_ERR_PARAM;
4380 goto i40e_aq_update_nvm_exit;
4383 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4385 /* If this is the last command in a series, set the proper flag. */
4387 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
4388 if (hw->mac.type == I40E_MAC_X722) {
4389 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED)
4390 cmd->command_flags |=
4391 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED <<
4392 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4393 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL)
4394 cmd->command_flags |=
4395 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL <<
4396 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4398 cmd->module_pointer = module_pointer;
4399 cmd->offset = CPU_TO_LE32(offset);
4400 cmd->length = CPU_TO_LE16(length);
4402 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4403 if (length > I40E_AQ_LARGE_BUF)
4404 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4406 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
4408 i40e_aq_update_nvm_exit:
4413 * i40e_aq_rearrange_nvm
4414 * @hw: pointer to the hw struct
4415 * @rearrange_nvm: defines direction of rearrangement
4416 * @cmd_details: pointer to command details structure or NULL
4418 * Rearrange NVM structure, available only for transition FW
4420 enum i40e_status_code i40e_aq_rearrange_nvm(struct i40e_hw *hw,
4422 struct i40e_asq_cmd_details *cmd_details)
4424 struct i40e_aqc_nvm_update *cmd;
4425 enum i40e_status_code status;
4426 struct i40e_aq_desc desc;
4428 DEBUGFUNC("i40e_aq_rearrange_nvm");
4430 cmd = (struct i40e_aqc_nvm_update *)&desc.params.raw;
4432 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4434 rearrange_nvm &= (I40E_AQ_NVM_REARRANGE_TO_FLAT |
4435 I40E_AQ_NVM_REARRANGE_TO_STRUCT);
4437 if (!rearrange_nvm) {
4438 status = I40E_ERR_PARAM;
4439 goto i40e_aq_rearrange_nvm_exit;
4442 cmd->command_flags |= rearrange_nvm;
4443 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4445 i40e_aq_rearrange_nvm_exit:
4450 * i40e_aq_get_lldp_mib
4451 * @hw: pointer to the hw struct
4452 * @bridge_type: type of bridge requested
4453 * @mib_type: Local, Remote or both Local and Remote MIBs
4454 * @buff: pointer to a user supplied buffer to store the MIB block
4455 * @buff_size: size of the buffer (in bytes)
4456 * @local_len : length of the returned Local LLDP MIB
4457 * @remote_len: length of the returned Remote LLDP MIB
4458 * @cmd_details: pointer to command details structure or NULL
4460 * Requests the complete LLDP MIB (entire packet).
4462 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4463 u8 mib_type, void *buff, u16 buff_size,
4464 u16 *local_len, u16 *remote_len,
4465 struct i40e_asq_cmd_details *cmd_details)
4467 struct i40e_aq_desc desc;
4468 struct i40e_aqc_lldp_get_mib *cmd =
4469 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4470 struct i40e_aqc_lldp_get_mib *resp =
4471 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4472 enum i40e_status_code status;
4474 if (buff_size == 0 || !buff)
4475 return I40E_ERR_PARAM;
4477 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4478 /* Indirect Command */
4479 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4481 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4482 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4483 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4485 desc.datalen = CPU_TO_LE16(buff_size);
4487 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4488 if (buff_size > I40E_AQ_LARGE_BUF)
4489 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4491 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4493 if (local_len != NULL)
4494 *local_len = LE16_TO_CPU(resp->local_len);
4495 if (remote_len != NULL)
4496 *remote_len = LE16_TO_CPU(resp->remote_len);
4503 * i40e_aq_set_lldp_mib - Set the LLDP MIB
4504 * @hw: pointer to the hw struct
4505 * @mib_type: Local, Remote or both Local and Remote MIBs
4506 * @buff: pointer to a user supplied buffer to store the MIB block
4507 * @buff_size: size of the buffer (in bytes)
4508 * @cmd_details: pointer to command details structure or NULL
4512 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4513 u8 mib_type, void *buff, u16 buff_size,
4514 struct i40e_asq_cmd_details *cmd_details)
4516 struct i40e_aq_desc desc;
4517 struct i40e_aqc_lldp_set_local_mib *cmd =
4518 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4519 enum i40e_status_code status;
4521 if (buff_size == 0 || !buff)
4522 return I40E_ERR_PARAM;
4524 i40e_fill_default_direct_cmd_desc(&desc,
4525 i40e_aqc_opc_lldp_set_local_mib);
4526 /* Indirect Command */
4527 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4528 if (buff_size > I40E_AQ_LARGE_BUF)
4529 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4530 desc.datalen = CPU_TO_LE16(buff_size);
4532 cmd->type = mib_type;
4533 cmd->length = CPU_TO_LE16(buff_size);
4534 cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)buff));
4535 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4537 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4542 * i40e_aq_cfg_lldp_mib_change_event
4543 * @hw: pointer to the hw struct
4544 * @enable_update: Enable or Disable event posting
4545 * @cmd_details: pointer to command details structure or NULL
4547 * Enable or Disable posting of an event on ARQ when LLDP MIB
4548 * associated with the interface changes
4550 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4552 struct i40e_asq_cmd_details *cmd_details)
4554 struct i40e_aq_desc desc;
4555 struct i40e_aqc_lldp_update_mib *cmd =
4556 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4557 enum i40e_status_code status;
4559 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4562 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4564 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4570 * i40e_aq_restore_lldp
4571 * @hw: pointer to the hw struct
4572 * @setting: pointer to factory setting variable or NULL
4573 * @restore: True if factory settings should be restored
4574 * @cmd_details: pointer to command details structure or NULL
4576 * Restore LLDP Agent factory settings if @restore set to True. In other case
4577 * only returns factory setting in AQ response.
4579 enum i40e_status_code
4580 i40e_aq_restore_lldp(struct i40e_hw *hw, u8 *setting, bool restore,
4581 struct i40e_asq_cmd_details *cmd_details)
4583 struct i40e_aq_desc desc;
4584 struct i40e_aqc_lldp_restore *cmd =
4585 (struct i40e_aqc_lldp_restore *)&desc.params.raw;
4586 enum i40e_status_code status;
4588 if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)) {
4589 i40e_debug(hw, I40E_DEBUG_ALL,
4590 "Restore LLDP not supported by current FW version.\n");
4591 return I40E_ERR_DEVICE_NOT_SUPPORTED;
4594 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_restore);
4597 cmd->command |= I40E_AQ_LLDP_AGENT_RESTORE;
4599 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4602 *setting = cmd->command & 1;
4609 * @hw: pointer to the hw struct
4610 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4611 * @persist: True if stop of LLDP should be persistent across power cycles
4612 * @cmd_details: pointer to command details structure or NULL
4614 * Stop or Shutdown the embedded LLDP Agent
4616 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4618 struct i40e_asq_cmd_details *cmd_details)
4620 struct i40e_aq_desc desc;
4621 struct i40e_aqc_lldp_stop *cmd =
4622 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4623 enum i40e_status_code status;
4625 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4628 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4631 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)
4632 cmd->command |= I40E_AQ_LLDP_AGENT_STOP_PERSIST;
4634 i40e_debug(hw, I40E_DEBUG_ALL,
4635 "Persistent Stop LLDP not supported by current FW version.\n");
4638 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4644 * i40e_aq_start_lldp
4645 * @hw: pointer to the hw struct
4646 * @persist: True if start of LLDP should be persistent across power cycles
4647 * @cmd_details: pointer to command details structure or NULL
4649 * Start the embedded LLDP Agent on all ports.
4651 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4653 struct i40e_asq_cmd_details *cmd_details)
4655 struct i40e_aq_desc desc;
4656 struct i40e_aqc_lldp_start *cmd =
4657 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4658 enum i40e_status_code status;
4660 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4662 cmd->command = I40E_AQ_LLDP_AGENT_START;
4665 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)
4666 cmd->command |= I40E_AQ_LLDP_AGENT_START_PERSIST;
4668 i40e_debug(hw, I40E_DEBUG_ALL,
4669 "Persistent Start LLDP not supported by current FW version.\n");
4672 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4678 * i40e_aq_set_dcb_parameters
4679 * @hw: pointer to the hw struct
4680 * @cmd_details: pointer to command details structure or NULL
4681 * @dcb_enable: True if DCB configuration needs to be applied
4684 enum i40e_status_code
4685 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable,
4686 struct i40e_asq_cmd_details *cmd_details)
4688 struct i40e_aq_desc desc;
4689 struct i40e_aqc_set_dcb_parameters *cmd =
4690 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw;
4691 enum i40e_status_code status;
4693 if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_STOPPABLE))
4694 return I40E_ERR_DEVICE_NOT_SUPPORTED;
4696 i40e_fill_default_direct_cmd_desc(&desc,
4697 i40e_aqc_opc_set_dcb_parameters);
4700 cmd->valid_flags = I40E_DCB_VALID;
4701 cmd->command = I40E_AQ_DCB_SET_AGENT;
4703 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4709 * i40e_aq_get_cee_dcb_config
4710 * @hw: pointer to the hw struct
4711 * @buff: response buffer that stores CEE operational configuration
4712 * @buff_size: size of the buffer passed
4713 * @cmd_details: pointer to command details structure or NULL
4715 * Get CEE DCBX mode operational configuration from firmware
4717 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4718 void *buff, u16 buff_size,
4719 struct i40e_asq_cmd_details *cmd_details)
4721 struct i40e_aq_desc desc;
4722 enum i40e_status_code status;
4724 if (buff_size == 0 || !buff)
4725 return I40E_ERR_PARAM;
4727 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4729 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4730 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4737 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4738 * @hw: pointer to the hw struct
4739 * @start_agent: True if DCBx Agent needs to be Started
4740 * False if DCBx Agent needs to be Stopped
4741 * @cmd_details: pointer to command details structure or NULL
4743 * Start/Stop the embedded dcbx Agent
4745 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4747 struct i40e_asq_cmd_details *cmd_details)
4749 struct i40e_aq_desc desc;
4750 struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4751 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4753 enum i40e_status_code status;
4755 i40e_fill_default_direct_cmd_desc(&desc,
4756 i40e_aqc_opc_lldp_stop_start_spec_agent);
4759 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4761 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4767 * i40e_aq_add_udp_tunnel
4768 * @hw: pointer to the hw struct
4769 * @udp_port: the UDP port to add in Host byte order
4770 * @protocol_index: protocol index type
4771 * @filter_index: pointer to filter index
4772 * @cmd_details: pointer to command details structure or NULL
4774 * Note: Firmware expects the udp_port value to be in Little Endian format,
4775 * and this function will call CPU_TO_LE16 to convert from Host byte order to
4776 * Little Endian order.
4778 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4779 u16 udp_port, u8 protocol_index,
4781 struct i40e_asq_cmd_details *cmd_details)
4783 struct i40e_aq_desc desc;
4784 struct i40e_aqc_add_udp_tunnel *cmd =
4785 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4786 struct i40e_aqc_del_udp_tunnel_completion *resp =
4787 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4788 enum i40e_status_code status;
4790 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4792 cmd->udp_port = CPU_TO_LE16(udp_port);
4793 cmd->protocol_type = protocol_index;
4795 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4797 if (!status && filter_index)
4798 *filter_index = resp->index;
4804 * i40e_aq_del_udp_tunnel
4805 * @hw: pointer to the hw struct
4806 * @index: filter index
4807 * @cmd_details: pointer to command details structure or NULL
4809 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4810 struct i40e_asq_cmd_details *cmd_details)
4812 struct i40e_aq_desc desc;
4813 struct i40e_aqc_remove_udp_tunnel *cmd =
4814 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4815 enum i40e_status_code status;
4817 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4821 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4827 * i40e_aq_get_switch_resource_alloc (0x0204)
4828 * @hw: pointer to the hw struct
4829 * @num_entries: pointer to u8 to store the number of resource entries returned
4830 * @buf: pointer to a user supplied buffer. This buffer must be large enough
4831 * to store the resource information for all resource types. Each
4832 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
4833 * @count: size, in bytes, of the buffer provided
4834 * @cmd_details: pointer to command details structure or NULL
4836 * Query the resources allocated to a function.
4838 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4840 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4842 struct i40e_asq_cmd_details *cmd_details)
4844 struct i40e_aq_desc desc;
4845 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4846 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4847 enum i40e_status_code status;
4848 u16 length = count * sizeof(*buf);
4850 i40e_fill_default_direct_cmd_desc(&desc,
4851 i40e_aqc_opc_get_switch_resource_alloc);
4853 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4854 if (length > I40E_AQ_LARGE_BUF)
4855 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4857 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4859 if (!status && num_entries)
4860 *num_entries = cmd_resp->num_entries;
4866 * i40e_aq_delete_element - Delete switch element
4867 * @hw: pointer to the hw struct
4868 * @seid: the SEID to delete from the switch
4869 * @cmd_details: pointer to command details structure or NULL
4871 * This deletes a switch element from the switch.
4873 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4874 struct i40e_asq_cmd_details *cmd_details)
4876 struct i40e_aq_desc desc;
4877 struct i40e_aqc_switch_seid *cmd =
4878 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4879 enum i40e_status_code status;
4882 return I40E_ERR_PARAM;
4884 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4886 cmd->seid = CPU_TO_LE16(seid);
4888 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4894 * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4895 * @hw: pointer to the hw struct
4896 * @flags: component flags
4897 * @mac_seid: uplink seid (MAC SEID)
4898 * @vsi_seid: connected vsi seid
4899 * @ret_seid: seid of create pv component
4901 * This instantiates an i40e port virtualizer with specified flags.
4902 * Depending on specified flags the port virtualizer can act as a
4903 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4905 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4906 u16 mac_seid, u16 vsi_seid,
4909 struct i40e_aq_desc desc;
4910 struct i40e_aqc_add_update_pv *cmd =
4911 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4912 struct i40e_aqc_add_update_pv_completion *resp =
4913 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4914 enum i40e_status_code status;
4917 return I40E_ERR_PARAM;
4919 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4920 cmd->command_flags = CPU_TO_LE16(flags);
4921 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4922 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4924 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4925 if (!status && ret_seid)
4926 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4932 * i40e_aq_add_tag - Add an S/E-tag
4933 * @hw: pointer to the hw struct
4934 * @direct_to_queue: should s-tag direct flow to a specific queue
4935 * @vsi_seid: VSI SEID to use this tag
4936 * @tag: value of the tag
4937 * @queue_num: queue number, only valid is direct_to_queue is true
4938 * @tags_used: return value, number of tags in use by this PF
4939 * @tags_free: return value, number of unallocated tags
4940 * @cmd_details: pointer to command details structure or NULL
4942 * This associates an S- or E-tag to a VSI in the switch complex. It returns
4943 * the number of tags allocated by the PF, and the number of unallocated
4946 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4947 u16 vsi_seid, u16 tag, u16 queue_num,
4948 u16 *tags_used, u16 *tags_free,
4949 struct i40e_asq_cmd_details *cmd_details)
4951 struct i40e_aq_desc desc;
4952 struct i40e_aqc_add_tag *cmd =
4953 (struct i40e_aqc_add_tag *)&desc.params.raw;
4954 struct i40e_aqc_add_remove_tag_completion *resp =
4955 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4956 enum i40e_status_code status;
4959 return I40E_ERR_PARAM;
4961 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4963 cmd->seid = CPU_TO_LE16(vsi_seid);
4964 cmd->tag = CPU_TO_LE16(tag);
4965 if (direct_to_queue) {
4966 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4967 cmd->queue_number = CPU_TO_LE16(queue_num);
4970 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4973 if (tags_used != NULL)
4974 *tags_used = LE16_TO_CPU(resp->tags_used);
4975 if (tags_free != NULL)
4976 *tags_free = LE16_TO_CPU(resp->tags_free);
4983 * i40e_aq_remove_tag - Remove an S- or E-tag
4984 * @hw: pointer to the hw struct
4985 * @vsi_seid: VSI SEID this tag is associated with
4986 * @tag: value of the S-tag to delete
4987 * @tags_used: return value, number of tags in use by this PF
4988 * @tags_free: return value, number of unallocated tags
4989 * @cmd_details: pointer to command details structure or NULL
4991 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
4992 * the number of tags allocated by the PF, and the number of unallocated
4995 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4996 u16 tag, u16 *tags_used, u16 *tags_free,
4997 struct i40e_asq_cmd_details *cmd_details)
4999 struct i40e_aq_desc desc;
5000 struct i40e_aqc_remove_tag *cmd =
5001 (struct i40e_aqc_remove_tag *)&desc.params.raw;
5002 struct i40e_aqc_add_remove_tag_completion *resp =
5003 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
5004 enum i40e_status_code status;
5007 return I40E_ERR_PARAM;
5009 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
5011 cmd->seid = CPU_TO_LE16(vsi_seid);
5012 cmd->tag = CPU_TO_LE16(tag);
5014 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5017 if (tags_used != NULL)
5018 *tags_used = LE16_TO_CPU(resp->tags_used);
5019 if (tags_free != NULL)
5020 *tags_free = LE16_TO_CPU(resp->tags_free);
5027 * i40e_aq_add_mcast_etag - Add a multicast E-tag
5028 * @hw: pointer to the hw struct
5029 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
5030 * @etag: value of E-tag to add
5031 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
5032 * @buf: address of indirect buffer
5033 * @tags_used: return value, number of E-tags in use by this port
5034 * @tags_free: return value, number of unallocated M-tags
5035 * @cmd_details: pointer to command details structure or NULL
5037 * This associates a multicast E-tag to a port virtualizer. It will return
5038 * the number of tags allocated by the PF, and the number of unallocated
5041 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
5042 * num_tags_in_buf long.
5044 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
5045 u16 etag, u8 num_tags_in_buf, void *buf,
5046 u16 *tags_used, u16 *tags_free,
5047 struct i40e_asq_cmd_details *cmd_details)
5049 struct i40e_aq_desc desc;
5050 struct i40e_aqc_add_remove_mcast_etag *cmd =
5051 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
5052 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
5053 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
5054 enum i40e_status_code status;
5055 u16 length = sizeof(u16) * num_tags_in_buf;
5057 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
5058 return I40E_ERR_PARAM;
5060 i40e_fill_default_direct_cmd_desc(&desc,
5061 i40e_aqc_opc_add_multicast_etag);
5063 cmd->pv_seid = CPU_TO_LE16(pv_seid);
5064 cmd->etag = CPU_TO_LE16(etag);
5065 cmd->num_unicast_etags = num_tags_in_buf;
5067 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5069 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
5072 if (tags_used != NULL)
5073 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
5074 if (tags_free != NULL)
5075 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
5082 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
5083 * @hw: pointer to the hw struct
5084 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
5085 * @etag: value of the E-tag to remove
5086 * @tags_used: return value, number of tags in use by this port
5087 * @tags_free: return value, number of unallocated tags
5088 * @cmd_details: pointer to command details structure or NULL
5090 * This deletes an E-tag from the port virtualizer. It will return
5091 * the number of tags allocated by the port, and the number of unallocated
5094 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
5095 u16 etag, u16 *tags_used, u16 *tags_free,
5096 struct i40e_asq_cmd_details *cmd_details)
5098 struct i40e_aq_desc desc;
5099 struct i40e_aqc_add_remove_mcast_etag *cmd =
5100 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
5101 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
5102 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
5103 enum i40e_status_code status;
5107 return I40E_ERR_PARAM;
5109 i40e_fill_default_direct_cmd_desc(&desc,
5110 i40e_aqc_opc_remove_multicast_etag);
5112 cmd->pv_seid = CPU_TO_LE16(pv_seid);
5113 cmd->etag = CPU_TO_LE16(etag);
5115 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5118 if (tags_used != NULL)
5119 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
5120 if (tags_free != NULL)
5121 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
5128 * i40e_aq_update_tag - Update an S/E-tag
5129 * @hw: pointer to the hw struct
5130 * @vsi_seid: VSI SEID using this S-tag
5131 * @old_tag: old tag value
5132 * @new_tag: new tag value
5133 * @tags_used: return value, number of tags in use by this PF
5134 * @tags_free: return value, number of unallocated tags
5135 * @cmd_details: pointer to command details structure or NULL
5137 * This updates the value of the tag currently attached to this VSI
5138 * in the switch complex. It will return the number of tags allocated
5139 * by the PF, and the number of unallocated tags available.
5141 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
5142 u16 old_tag, u16 new_tag, u16 *tags_used,
5144 struct i40e_asq_cmd_details *cmd_details)
5146 struct i40e_aq_desc desc;
5147 struct i40e_aqc_update_tag *cmd =
5148 (struct i40e_aqc_update_tag *)&desc.params.raw;
5149 struct i40e_aqc_update_tag_completion *resp =
5150 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
5151 enum i40e_status_code status;
5154 return I40E_ERR_PARAM;
5156 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
5158 cmd->seid = CPU_TO_LE16(vsi_seid);
5159 cmd->old_tag = CPU_TO_LE16(old_tag);
5160 cmd->new_tag = CPU_TO_LE16(new_tag);
5162 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5165 if (tags_used != NULL)
5166 *tags_used = LE16_TO_CPU(resp->tags_used);
5167 if (tags_free != NULL)
5168 *tags_free = LE16_TO_CPU(resp->tags_free);
5175 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
5176 * @hw: pointer to the hw struct
5177 * @tcmap: TC map for request/release any ignore PFC condition
5178 * @request: request or release ignore PFC condition
5179 * @tcmap_ret: return TCs for which PFC is currently ignored
5180 * @cmd_details: pointer to command details structure or NULL
5182 * This sends out request/release to ignore PFC condition for a TC.
5183 * It will return the TCs for which PFC is currently ignored.
5185 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
5186 bool request, u8 *tcmap_ret,
5187 struct i40e_asq_cmd_details *cmd_details)
5189 struct i40e_aq_desc desc;
5190 struct i40e_aqc_pfc_ignore *cmd_resp =
5191 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
5192 enum i40e_status_code status;
5194 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
5197 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
5199 cmd_resp->tc_bitmap = tcmap;
5201 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5204 if (tcmap_ret != NULL)
5205 *tcmap_ret = cmd_resp->tc_bitmap;
5212 * i40e_aq_dcb_updated - DCB Updated Command
5213 * @hw: pointer to the hw struct
5214 * @cmd_details: pointer to command details structure or NULL
5216 * When LLDP is handled in PF this command is used by the PF
5217 * to notify EMP that a DCB setting is modified.
5218 * When LLDP is handled in EMP this command is used by the PF
5219 * to notify EMP whenever one of the following parameters get
5221 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
5222 * - PCIRTT in PRTDCB_GENC.PCIRTT
5223 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
5224 * EMP will return when the shared RPB settings have been
5225 * recomputed and modified. The retval field in the descriptor
5226 * will be set to 0 when RPB is modified.
5228 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
5229 struct i40e_asq_cmd_details *cmd_details)
5231 struct i40e_aq_desc desc;
5232 enum i40e_status_code status;
5234 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
5236 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5242 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
5243 * @hw: pointer to the hw struct
5244 * @seid: defines the SEID of the switch for which the stats are requested
5245 * @vlan_id: the VLAN ID for which the statistics are requested
5246 * @stat_index: index of the statistics counters block assigned to this VLAN
5247 * @cmd_details: pointer to command details structure or NULL
5249 * XL710 supports 128 smonVlanStats counters.This command is used to
5250 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
5253 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
5254 u16 vlan_id, u16 *stat_index,
5255 struct i40e_asq_cmd_details *cmd_details)
5257 struct i40e_aq_desc desc;
5258 struct i40e_aqc_add_remove_statistics *cmd_resp =
5259 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5260 enum i40e_status_code status;
5262 if ((seid == 0) || (stat_index == NULL))
5263 return I40E_ERR_PARAM;
5265 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
5267 cmd_resp->seid = CPU_TO_LE16(seid);
5268 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
5270 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5272 if (!status && stat_index)
5273 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
5279 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
5280 * @hw: pointer to the hw struct
5281 * @seid: defines the SEID of the switch for which the stats are requested
5282 * @vlan_id: the VLAN ID for which the statistics are requested
5283 * @stat_index: index of the statistics counters block assigned to this VLAN
5284 * @cmd_details: pointer to command details structure or NULL
5286 * XL710 supports 128 smonVlanStats counters.This command is used to
5287 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
5290 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
5291 u16 vlan_id, u16 stat_index,
5292 struct i40e_asq_cmd_details *cmd_details)
5294 struct i40e_aq_desc desc;
5295 struct i40e_aqc_add_remove_statistics *cmd =
5296 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5297 enum i40e_status_code status;
5300 return I40E_ERR_PARAM;
5302 i40e_fill_default_direct_cmd_desc(&desc,
5303 i40e_aqc_opc_remove_statistics);
5305 cmd->seid = CPU_TO_LE16(seid);
5306 cmd->vlan = CPU_TO_LE16(vlan_id);
5307 cmd->stat_index = CPU_TO_LE16(stat_index);
5309 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5315 * i40e_aq_set_port_parameters - set physical port parameters.
5316 * @hw: pointer to the hw struct
5317 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
5318 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
5319 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
5320 * @double_vlan: if set double VLAN is enabled
5321 * @cmd_details: pointer to command details structure or NULL
5323 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
5324 u16 bad_frame_vsi, bool save_bad_pac,
5325 bool pad_short_pac, bool double_vlan,
5326 struct i40e_asq_cmd_details *cmd_details)
5328 struct i40e_aqc_set_port_parameters *cmd;
5329 enum i40e_status_code status;
5330 struct i40e_aq_desc desc;
5331 u16 command_flags = 0;
5333 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
5335 i40e_fill_default_direct_cmd_desc(&desc,
5336 i40e_aqc_opc_set_port_parameters);
5338 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
5340 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
5342 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
5344 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
5345 cmd->command_flags = CPU_TO_LE16(command_flags);
5347 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5353 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
5354 * @hw: pointer to the hw struct
5355 * @seid: seid for the physical port/switching component/vsi
5356 * @buff: Indirect buffer to hold data parameters and response
5357 * @buff_size: Indirect buffer size
5358 * @opcode: Tx scheduler AQ command opcode
5359 * @cmd_details: pointer to command details structure or NULL
5361 * Generic command handler for Tx scheduler AQ commands
5363 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
5364 void *buff, u16 buff_size,
5365 enum i40e_admin_queue_opc opcode,
5366 struct i40e_asq_cmd_details *cmd_details)
5368 struct i40e_aq_desc desc;
5369 struct i40e_aqc_tx_sched_ind *cmd =
5370 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
5371 enum i40e_status_code status;
5372 bool cmd_param_flag = false;
5375 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
5376 case i40e_aqc_opc_configure_vsi_tc_bw:
5377 case i40e_aqc_opc_enable_switching_comp_ets:
5378 case i40e_aqc_opc_modify_switching_comp_ets:
5379 case i40e_aqc_opc_disable_switching_comp_ets:
5380 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
5381 case i40e_aqc_opc_configure_switching_comp_bw_config:
5382 cmd_param_flag = true;
5384 case i40e_aqc_opc_query_vsi_bw_config:
5385 case i40e_aqc_opc_query_vsi_ets_sla_config:
5386 case i40e_aqc_opc_query_switching_comp_ets_config:
5387 case i40e_aqc_opc_query_port_ets_config:
5388 case i40e_aqc_opc_query_switching_comp_bw_config:
5389 cmd_param_flag = false;
5392 return I40E_ERR_PARAM;
5395 i40e_fill_default_direct_cmd_desc(&desc, opcode);
5397 /* Indirect command */
5398 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5400 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5401 if (buff_size > I40E_AQ_LARGE_BUF)
5402 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5404 desc.datalen = CPU_TO_LE16(buff_size);
5406 cmd->vsi_seid = CPU_TO_LE16(seid);
5408 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5414 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5415 * @hw: pointer to the hw struct
5417 * @credit: BW limit credits (0 = disabled)
5418 * @max_credit: Max BW limit credits
5419 * @cmd_details: pointer to command details structure or NULL
5421 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5422 u16 seid, u16 credit, u8 max_credit,
5423 struct i40e_asq_cmd_details *cmd_details)
5425 struct i40e_aq_desc desc;
5426 struct i40e_aqc_configure_vsi_bw_limit *cmd =
5427 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5428 enum i40e_status_code status;
5430 i40e_fill_default_direct_cmd_desc(&desc,
5431 i40e_aqc_opc_configure_vsi_bw_limit);
5433 cmd->vsi_seid = CPU_TO_LE16(seid);
5434 cmd->credit = CPU_TO_LE16(credit);
5435 cmd->max_credit = max_credit;
5437 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5443 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5444 * @hw: pointer to the hw struct
5445 * @seid: switching component seid
5446 * @credit: BW limit credits (0 = disabled)
5447 * @max_bw: Max BW limit credits
5448 * @cmd_details: pointer to command details structure or NULL
5450 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5451 u16 seid, u16 credit, u8 max_bw,
5452 struct i40e_asq_cmd_details *cmd_details)
5454 struct i40e_aq_desc desc;
5455 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5456 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5457 enum i40e_status_code status;
5459 i40e_fill_default_direct_cmd_desc(&desc,
5460 i40e_aqc_opc_configure_switching_comp_bw_limit);
5462 cmd->seid = CPU_TO_LE16(seid);
5463 cmd->credit = CPU_TO_LE16(credit);
5464 cmd->max_bw = max_bw;
5466 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5472 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5473 * @hw: pointer to the hw struct
5475 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5476 * @cmd_details: pointer to command details structure or NULL
5478 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5480 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5481 struct i40e_asq_cmd_details *cmd_details)
5483 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5484 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5489 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5490 * @hw: pointer to the hw struct
5492 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5493 * @cmd_details: pointer to command details structure or NULL
5495 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5497 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5498 struct i40e_asq_cmd_details *cmd_details)
5500 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5501 i40e_aqc_opc_configure_vsi_tc_bw,
5506 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5507 * @hw: pointer to the hw struct
5508 * @seid: seid of the switching component connected to Physical Port
5509 * @ets_data: Buffer holding ETS parameters
5510 * @opcode: Tx scheduler AQ command opcode
5511 * @cmd_details: pointer to command details structure or NULL
5513 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5515 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5516 enum i40e_admin_queue_opc opcode,
5517 struct i40e_asq_cmd_details *cmd_details)
5519 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5520 sizeof(*ets_data), opcode, cmd_details);
5524 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5525 * @hw: pointer to the hw struct
5526 * @seid: seid of the switching component
5527 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5528 * @cmd_details: pointer to command details structure or NULL
5530 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5532 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5533 struct i40e_asq_cmd_details *cmd_details)
5535 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5536 i40e_aqc_opc_configure_switching_comp_bw_config,
5541 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5542 * @hw: pointer to the hw struct
5543 * @seid: seid of the switching component
5544 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5545 * @cmd_details: pointer to command details structure or NULL
5547 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5548 struct i40e_hw *hw, u16 seid,
5549 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5550 struct i40e_asq_cmd_details *cmd_details)
5552 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5553 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5558 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5559 * @hw: pointer to the hw struct
5560 * @seid: seid of the VSI
5561 * @bw_data: Buffer to hold VSI BW configuration
5562 * @cmd_details: pointer to command details structure or NULL
5564 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5566 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5567 struct i40e_asq_cmd_details *cmd_details)
5569 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5570 i40e_aqc_opc_query_vsi_bw_config,
5575 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5576 * @hw: pointer to the hw struct
5577 * @seid: seid of the VSI
5578 * @bw_data: Buffer to hold VSI BW configuration per TC
5579 * @cmd_details: pointer to command details structure or NULL
5581 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5583 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5584 struct i40e_asq_cmd_details *cmd_details)
5586 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5587 i40e_aqc_opc_query_vsi_ets_sla_config,
5592 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5593 * @hw: pointer to the hw struct
5594 * @seid: seid of the switching component
5595 * @bw_data: Buffer to hold switching component's per TC BW config
5596 * @cmd_details: pointer to command details structure or NULL
5598 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5600 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5601 struct i40e_asq_cmd_details *cmd_details)
5603 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5604 i40e_aqc_opc_query_switching_comp_ets_config,
5609 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5610 * @hw: pointer to the hw struct
5611 * @seid: seid of the VSI or switching component connected to Physical Port
5612 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5613 * @cmd_details: pointer to command details structure or NULL
5615 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5617 struct i40e_aqc_query_port_ets_config_resp *bw_data,
5618 struct i40e_asq_cmd_details *cmd_details)
5620 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5621 i40e_aqc_opc_query_port_ets_config,
5626 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5627 * @hw: pointer to the hw struct
5628 * @seid: seid of the switching component
5629 * @bw_data: Buffer to hold switching component's BW configuration
5630 * @cmd_details: pointer to command details structure or NULL
5632 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5634 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5635 struct i40e_asq_cmd_details *cmd_details)
5637 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5638 i40e_aqc_opc_query_switching_comp_bw_config,
5643 * i40e_validate_filter_settings
5644 * @hw: pointer to the hardware structure
5645 * @settings: Filter control settings
5647 * Check and validate the filter control settings passed.
5648 * The function checks for the valid filter/context sizes being
5649 * passed for FCoE and PE.
5651 * Returns I40E_SUCCESS if the values passed are valid and within
5652 * range else returns an error.
5654 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5655 struct i40e_filter_control_settings *settings)
5657 u32 fcoe_cntx_size, fcoe_filt_size;
5658 u32 pe_cntx_size, pe_filt_size;
5663 /* Validate FCoE settings passed */
5664 switch (settings->fcoe_filt_num) {
5665 case I40E_HASH_FILTER_SIZE_1K:
5666 case I40E_HASH_FILTER_SIZE_2K:
5667 case I40E_HASH_FILTER_SIZE_4K:
5668 case I40E_HASH_FILTER_SIZE_8K:
5669 case I40E_HASH_FILTER_SIZE_16K:
5670 case I40E_HASH_FILTER_SIZE_32K:
5671 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5672 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5675 return I40E_ERR_PARAM;
5678 switch (settings->fcoe_cntx_num) {
5679 case I40E_DMA_CNTX_SIZE_512:
5680 case I40E_DMA_CNTX_SIZE_1K:
5681 case I40E_DMA_CNTX_SIZE_2K:
5682 case I40E_DMA_CNTX_SIZE_4K:
5683 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5684 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5687 return I40E_ERR_PARAM;
5690 /* Validate PE settings passed */
5691 switch (settings->pe_filt_num) {
5692 case I40E_HASH_FILTER_SIZE_1K:
5693 case I40E_HASH_FILTER_SIZE_2K:
5694 case I40E_HASH_FILTER_SIZE_4K:
5695 case I40E_HASH_FILTER_SIZE_8K:
5696 case I40E_HASH_FILTER_SIZE_16K:
5697 case I40E_HASH_FILTER_SIZE_32K:
5698 case I40E_HASH_FILTER_SIZE_64K:
5699 case I40E_HASH_FILTER_SIZE_128K:
5700 case I40E_HASH_FILTER_SIZE_256K:
5701 case I40E_HASH_FILTER_SIZE_512K:
5702 case I40E_HASH_FILTER_SIZE_1M:
5703 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5704 pe_filt_size <<= (u32)settings->pe_filt_num;
5707 return I40E_ERR_PARAM;
5710 switch (settings->pe_cntx_num) {
5711 case I40E_DMA_CNTX_SIZE_512:
5712 case I40E_DMA_CNTX_SIZE_1K:
5713 case I40E_DMA_CNTX_SIZE_2K:
5714 case I40E_DMA_CNTX_SIZE_4K:
5715 case I40E_DMA_CNTX_SIZE_8K:
5716 case I40E_DMA_CNTX_SIZE_16K:
5717 case I40E_DMA_CNTX_SIZE_32K:
5718 case I40E_DMA_CNTX_SIZE_64K:
5719 case I40E_DMA_CNTX_SIZE_128K:
5720 case I40E_DMA_CNTX_SIZE_256K:
5721 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5722 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5725 return I40E_ERR_PARAM;
5728 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5729 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5730 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5731 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5732 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
5733 return I40E_ERR_INVALID_SIZE;
5735 return I40E_SUCCESS;
5739 * i40e_set_filter_control
5740 * @hw: pointer to the hardware structure
5741 * @settings: Filter control settings
5743 * Set the Queue Filters for PE/FCoE and enable filters required
5744 * for a single PF. It is expected that these settings are programmed
5745 * at the driver initialization time.
5747 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5748 struct i40e_filter_control_settings *settings)
5750 enum i40e_status_code ret = I40E_SUCCESS;
5751 u32 hash_lut_size = 0;
5755 return I40E_ERR_PARAM;
5757 /* Validate the input settings */
5758 ret = i40e_validate_filter_settings(hw, settings);
5762 /* Read the PF Queue Filter control register */
5763 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5765 /* Program required PE hash buckets for the PF */
5766 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5767 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5768 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5769 /* Program required PE contexts for the PF */
5770 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5771 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5772 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5774 /* Program required FCoE hash buckets for the PF */
5775 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5776 val |= ((u32)settings->fcoe_filt_num <<
5777 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5778 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5779 /* Program required FCoE DDP contexts for the PF */
5780 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5781 val |= ((u32)settings->fcoe_cntx_num <<
5782 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5783 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5785 /* Program Hash LUT size for the PF */
5786 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5787 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5789 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5790 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5792 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5793 if (settings->enable_fdir)
5794 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5795 if (settings->enable_ethtype)
5796 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5797 if (settings->enable_macvlan)
5798 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5800 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5802 return I40E_SUCCESS;
5806 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5807 * @hw: pointer to the hw struct
5808 * @mac_addr: MAC address to use in the filter
5809 * @ethtype: Ethertype to use in the filter
5810 * @flags: Flags that needs to be applied to the filter
5811 * @vsi_seid: seid of the control VSI
5812 * @queue: VSI queue number to send the packet to
5813 * @is_add: Add control packet filter if True else remove
5814 * @stats: Structure to hold information on control filter counts
5815 * @cmd_details: pointer to command details structure or NULL
5817 * This command will Add or Remove control packet filter for a control VSI.
5818 * In return it will update the total number of perfect filter count in
5821 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5822 u8 *mac_addr, u16 ethtype, u16 flags,
5823 u16 vsi_seid, u16 queue, bool is_add,
5824 struct i40e_control_filter_stats *stats,
5825 struct i40e_asq_cmd_details *cmd_details)
5827 struct i40e_aq_desc desc;
5828 struct i40e_aqc_add_remove_control_packet_filter *cmd =
5829 (struct i40e_aqc_add_remove_control_packet_filter *)
5831 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5832 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5834 enum i40e_status_code status;
5837 return I40E_ERR_PARAM;
5840 i40e_fill_default_direct_cmd_desc(&desc,
5841 i40e_aqc_opc_add_control_packet_filter);
5842 cmd->queue = CPU_TO_LE16(queue);
5844 i40e_fill_default_direct_cmd_desc(&desc,
5845 i40e_aqc_opc_remove_control_packet_filter);
5849 i40e_memcpy(cmd->mac, mac_addr, ETH_ALEN,
5850 I40E_NONDMA_TO_NONDMA);
5852 cmd->etype = CPU_TO_LE16(ethtype);
5853 cmd->flags = CPU_TO_LE16(flags);
5854 cmd->seid = CPU_TO_LE16(vsi_seid);
5856 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5858 if (!status && stats) {
5859 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5860 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5861 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5862 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5869 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5870 * @hw: pointer to the hw struct
5871 * @seid: VSI seid to add ethertype filter from
5873 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5876 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5877 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5878 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5879 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5880 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5881 enum i40e_status_code status;
5883 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5884 seid, 0, true, NULL,
5887 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5891 * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5892 * @filters: list of cloud filters
5893 * @filter_count: length of list
5895 * There's an issue in the device where the Geneve VNI layout needs
5896 * to be shifted 1 byte over from the VxLAN VNI
5898 STATIC void i40e_fix_up_geneve_vni(
5899 struct i40e_aqc_cloud_filters_element_data *filters,
5902 struct i40e_aqc_cloud_filters_element_data *f = filters;
5905 for (i = 0; i < filter_count; i++) {
5909 tnl_type = (LE16_TO_CPU(f[i].flags) &
5910 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5911 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5912 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5913 ti = LE32_TO_CPU(f[i].tenant_id);
5914 f[i].tenant_id = CPU_TO_LE32(ti << 8);
5920 * i40e_aq_add_cloud_filters
5921 * @hw: pointer to the hardware structure
5922 * @seid: VSI seid to add cloud filters from
5923 * @filters: Buffer which contains the filters to be added
5924 * @filter_count: number of filters contained in the buffer
5926 * Set the cloud filters for a given VSI. The contents of the
5927 * i40e_aqc_cloud_filters_element_data are filled
5928 * in by the caller of the function.
5931 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5933 struct i40e_aqc_cloud_filters_element_data *filters,
5936 struct i40e_aq_desc desc;
5937 struct i40e_aqc_add_remove_cloud_filters *cmd =
5938 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5939 enum i40e_status_code status;
5942 i40e_fill_default_direct_cmd_desc(&desc,
5943 i40e_aqc_opc_add_cloud_filters);
5945 buff_len = filter_count * sizeof(*filters);
5946 desc.datalen = CPU_TO_LE16(buff_len);
5947 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5948 cmd->num_filters = filter_count;
5949 cmd->seid = CPU_TO_LE16(seid);
5951 i40e_fix_up_geneve_vni(filters, filter_count);
5953 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5959 * i40e_aq_add_cloud_filters_bb
5960 * @hw: pointer to the hardware structure
5961 * @seid: VSI seid to add cloud filters from
5962 * @filters: Buffer which contains the filters in big buffer to be added
5963 * @filter_count: number of filters contained in the buffer
5965 * Set the cloud filters for a given VSI. The contents of the
5966 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5970 enum i40e_status_code
5971 i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5972 struct i40e_aqc_cloud_filters_element_bb *filters,
5975 struct i40e_aq_desc desc;
5976 struct i40e_aqc_add_remove_cloud_filters *cmd =
5977 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5978 enum i40e_status_code status;
5982 i40e_fill_default_direct_cmd_desc(&desc,
5983 i40e_aqc_opc_add_cloud_filters);
5985 buff_len = filter_count * sizeof(*filters);
5986 desc.datalen = CPU_TO_LE16(buff_len);
5987 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5988 cmd->num_filters = filter_count;
5989 cmd->seid = CPU_TO_LE16(seid);
5990 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5992 for (i = 0; i < filter_count; i++) {
5996 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5997 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5998 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
6000 /* Due to hardware eccentricities, the VNI for Geneve is shifted
6001 * one more byte further than normally used for Tenant ID in
6002 * other tunnel types.
6004 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
6005 ti = LE32_TO_CPU(filters[i].element.tenant_id);
6006 filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
6010 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
6016 * i40e_aq_rem_cloud_filters
6017 * @hw: pointer to the hardware structure
6018 * @seid: VSI seid to remove cloud filters from
6019 * @filters: Buffer which contains the filters to be removed
6020 * @filter_count: number of filters contained in the buffer
6022 * Remove the cloud filters for a given VSI. The contents of the
6023 * i40e_aqc_cloud_filters_element_data are filled in by the caller
6027 enum i40e_status_code
6028 i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid,
6029 struct i40e_aqc_cloud_filters_element_data *filters,
6032 struct i40e_aq_desc desc;
6033 struct i40e_aqc_add_remove_cloud_filters *cmd =
6034 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
6035 enum i40e_status_code status;
6038 i40e_fill_default_direct_cmd_desc(&desc,
6039 i40e_aqc_opc_remove_cloud_filters);
6041 buff_len = filter_count * sizeof(*filters);
6042 desc.datalen = CPU_TO_LE16(buff_len);
6043 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
6044 cmd->num_filters = filter_count;
6045 cmd->seid = CPU_TO_LE16(seid);
6047 i40e_fix_up_geneve_vni(filters, filter_count);
6049 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
6055 * i40e_aq_rem_cloud_filters_bb
6056 * @hw: pointer to the hardware structure
6057 * @seid: VSI seid to remove cloud filters from
6058 * @filters: Buffer which contains the filters in big buffer to be removed
6059 * @filter_count: number of filters contained in the buffer
6061 * Remove the big buffer cloud filters for a given VSI. The contents of the
6062 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
6066 enum i40e_status_code
6067 i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
6068 struct i40e_aqc_cloud_filters_element_bb *filters,
6071 struct i40e_aq_desc desc;
6072 struct i40e_aqc_add_remove_cloud_filters *cmd =
6073 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
6074 enum i40e_status_code status;
6078 i40e_fill_default_direct_cmd_desc(&desc,
6079 i40e_aqc_opc_remove_cloud_filters);
6081 buff_len = filter_count * sizeof(*filters);
6082 desc.datalen = CPU_TO_LE16(buff_len);
6083 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
6084 cmd->num_filters = filter_count;
6085 cmd->seid = CPU_TO_LE16(seid);
6086 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
6088 for (i = 0; i < filter_count; i++) {
6092 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
6093 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
6094 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
6096 /* Due to hardware eccentricities, the VNI for Geneve is shifted
6097 * one more byte further than normally used for Tenant ID in
6098 * other tunnel types.
6100 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
6101 ti = LE32_TO_CPU(filters[i].element.tenant_id);
6102 filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
6106 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
6112 * i40e_aq_replace_cloud_filters - Replace cloud filter command
6113 * @hw: pointer to the hw struct
6114 * @filters: pointer to the i40e_aqc_replace_cloud_filter_cmd struct
6115 * @cmd_buf: pointer to the i40e_aqc_replace_cloud_filter_cmd_buf struct
6119 i40e_status_code i40e_aq_replace_cloud_filters(struct i40e_hw *hw,
6120 struct i40e_aqc_replace_cloud_filters_cmd *filters,
6121 struct i40e_aqc_replace_cloud_filters_cmd_buf *cmd_buf)
6123 struct i40e_aq_desc desc;
6124 struct i40e_aqc_replace_cloud_filters_cmd *cmd =
6125 (struct i40e_aqc_replace_cloud_filters_cmd *)&desc.params.raw;
6126 enum i40e_status_code status = I40E_SUCCESS;
6129 /* X722 doesn't support this command */
6130 if (hw->mac.type == I40E_MAC_X722)
6131 return I40E_ERR_DEVICE_NOT_SUPPORTED;
6133 /* need FW version greater than 6.00 */
6134 if (hw->aq.fw_maj_ver < 6)
6135 return I40E_NOT_SUPPORTED;
6137 i40e_fill_default_direct_cmd_desc(&desc,
6138 i40e_aqc_opc_replace_cloud_filters);
6140 desc.datalen = CPU_TO_LE16(32);
6141 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
6142 cmd->old_filter_type = filters->old_filter_type;
6143 cmd->new_filter_type = filters->new_filter_type;
6144 cmd->valid_flags = filters->valid_flags;
6145 cmd->tr_bit = filters->tr_bit;
6146 cmd->tr_bit2 = filters->tr_bit2;
6148 status = i40e_asq_send_command(hw, &desc, cmd_buf,
6149 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf), NULL);
6151 /* for get cloud filters command */
6152 for (i = 0; i < 32; i += 4) {
6153 cmd_buf->filters[i / 4].filter_type = cmd_buf->data[i];
6154 cmd_buf->filters[i / 4].input[0] = cmd_buf->data[i + 1];
6155 cmd_buf->filters[i / 4].input[1] = cmd_buf->data[i + 2];
6156 cmd_buf->filters[i / 4].input[2] = cmd_buf->data[i + 3];
6164 * i40e_aq_alternate_write
6165 * @hw: pointer to the hardware structure
6166 * @reg_addr0: address of first dword to be read
6167 * @reg_val0: value to be written under 'reg_addr0'
6168 * @reg_addr1: address of second dword to be read
6169 * @reg_val1: value to be written under 'reg_addr1'
6171 * Write one or two dwords to alternate structure. Fields are indicated
6172 * by 'reg_addr0' and 'reg_addr1' register numbers.
6175 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
6176 u32 reg_addr0, u32 reg_val0,
6177 u32 reg_addr1, u32 reg_val1)
6179 struct i40e_aq_desc desc;
6180 struct i40e_aqc_alternate_write *cmd_resp =
6181 (struct i40e_aqc_alternate_write *)&desc.params.raw;
6182 enum i40e_status_code status;
6184 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
6185 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
6186 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
6187 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
6188 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
6190 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6196 * i40e_aq_alternate_write_indirect
6197 * @hw: pointer to the hardware structure
6198 * @addr: address of a first register to be modified
6199 * @dw_count: number of alternate structure fields to write
6200 * @buffer: pointer to the command buffer
6202 * Write 'dw_count' dwords from 'buffer' to alternate structure
6203 * starting at 'addr'.
6206 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
6207 u32 addr, u32 dw_count, void *buffer)
6209 struct i40e_aq_desc desc;
6210 struct i40e_aqc_alternate_ind_write *cmd_resp =
6211 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
6212 enum i40e_status_code status;
6215 return I40E_ERR_PARAM;
6217 /* Indirect command */
6218 i40e_fill_default_direct_cmd_desc(&desc,
6219 i40e_aqc_opc_alternate_write_indirect);
6221 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6222 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6223 if (dw_count > (I40E_AQ_LARGE_BUF/4))
6224 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6226 cmd_resp->address = CPU_TO_LE32(addr);
6227 cmd_resp->length = CPU_TO_LE32(dw_count);
6229 status = i40e_asq_send_command(hw, &desc, buffer,
6230 I40E_LO_DWORD(4*dw_count), NULL);
6236 * i40e_aq_alternate_read
6237 * @hw: pointer to the hardware structure
6238 * @reg_addr0: address of first dword to be read
6239 * @reg_val0: pointer for data read from 'reg_addr0'
6240 * @reg_addr1: address of second dword to be read
6241 * @reg_val1: pointer for data read from 'reg_addr1'
6243 * Read one or two dwords from alternate structure. Fields are indicated
6244 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
6245 * is not passed then only register at 'reg_addr0' is read.
6248 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
6249 u32 reg_addr0, u32 *reg_val0,
6250 u32 reg_addr1, u32 *reg_val1)
6252 struct i40e_aq_desc desc;
6253 struct i40e_aqc_alternate_write *cmd_resp =
6254 (struct i40e_aqc_alternate_write *)&desc.params.raw;
6255 enum i40e_status_code status;
6257 if (reg_val0 == NULL)
6258 return I40E_ERR_PARAM;
6260 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
6261 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
6262 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
6264 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6266 if (status == I40E_SUCCESS) {
6267 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
6269 if (reg_val1 != NULL)
6270 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
6277 * i40e_aq_alternate_read_indirect
6278 * @hw: pointer to the hardware structure
6279 * @addr: address of the alternate structure field
6280 * @dw_count: number of alternate structure fields to read
6281 * @buffer: pointer to the command buffer
6283 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
6284 * place them in 'buffer'. The buffer should be allocated by caller.
6287 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
6288 u32 addr, u32 dw_count, void *buffer)
6290 struct i40e_aq_desc desc;
6291 struct i40e_aqc_alternate_ind_write *cmd_resp =
6292 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
6293 enum i40e_status_code status;
6296 return I40E_ERR_PARAM;
6298 /* Indirect command */
6299 i40e_fill_default_direct_cmd_desc(&desc,
6300 i40e_aqc_opc_alternate_read_indirect);
6302 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6303 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6304 if (dw_count > (I40E_AQ_LARGE_BUF/4))
6305 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6307 cmd_resp->address = CPU_TO_LE32(addr);
6308 cmd_resp->length = CPU_TO_LE32(dw_count);
6310 status = i40e_asq_send_command(hw, &desc, buffer,
6311 I40E_LO_DWORD(4*dw_count), NULL);
6317 * i40e_aq_alternate_clear
6318 * @hw: pointer to the HW structure.
6320 * Clear the alternate structures of the port from which the function
6324 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
6326 struct i40e_aq_desc desc;
6327 enum i40e_status_code status;
6329 i40e_fill_default_direct_cmd_desc(&desc,
6330 i40e_aqc_opc_alternate_clear_port);
6332 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6338 * i40e_aq_alternate_write_done
6339 * @hw: pointer to the HW structure.
6340 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
6341 * @reset_needed: indicates the SW should trigger GLOBAL reset
6343 * Indicates to the FW that alternate structures have been changed.
6346 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
6347 u8 bios_mode, bool *reset_needed)
6349 struct i40e_aq_desc desc;
6350 struct i40e_aqc_alternate_write_done *cmd =
6351 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6352 enum i40e_status_code status;
6354 if (reset_needed == NULL)
6355 return I40E_ERR_PARAM;
6357 i40e_fill_default_direct_cmd_desc(&desc,
6358 i40e_aqc_opc_alternate_write_done);
6360 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
6362 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6363 if (!status && reset_needed)
6364 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
6365 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
6371 * i40e_aq_set_oem_mode
6372 * @hw: pointer to the HW structure.
6373 * @oem_mode: the OEM mode to be used
6375 * Sets the device to a specific operating mode. Currently the only supported
6376 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
6379 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
6382 struct i40e_aq_desc desc;
6383 struct i40e_aqc_alternate_write_done *cmd =
6384 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6385 enum i40e_status_code status;
6387 i40e_fill_default_direct_cmd_desc(&desc,
6388 i40e_aqc_opc_alternate_set_mode);
6390 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
6392 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6398 * i40e_aq_resume_port_tx
6399 * @hw: pointer to the hardware structure
6400 * @cmd_details: pointer to command details structure or NULL
6402 * Resume port's Tx traffic
6404 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
6405 struct i40e_asq_cmd_details *cmd_details)
6407 struct i40e_aq_desc desc;
6408 enum i40e_status_code status;
6410 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
6412 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6418 * i40e_set_pci_config_data - store PCI bus info
6419 * @hw: pointer to hardware structure
6420 * @link_status: the link status word from PCI config space
6422 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
6424 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
6426 hw->bus.type = i40e_bus_type_pci_express;
6428 switch (link_status & I40E_PCI_LINK_WIDTH) {
6429 case I40E_PCI_LINK_WIDTH_1:
6430 hw->bus.width = i40e_bus_width_pcie_x1;
6432 case I40E_PCI_LINK_WIDTH_2:
6433 hw->bus.width = i40e_bus_width_pcie_x2;
6435 case I40E_PCI_LINK_WIDTH_4:
6436 hw->bus.width = i40e_bus_width_pcie_x4;
6438 case I40E_PCI_LINK_WIDTH_8:
6439 hw->bus.width = i40e_bus_width_pcie_x8;
6442 hw->bus.width = i40e_bus_width_unknown;
6446 switch (link_status & I40E_PCI_LINK_SPEED) {
6447 case I40E_PCI_LINK_SPEED_2500:
6448 hw->bus.speed = i40e_bus_speed_2500;
6450 case I40E_PCI_LINK_SPEED_5000:
6451 hw->bus.speed = i40e_bus_speed_5000;
6453 case I40E_PCI_LINK_SPEED_8000:
6454 hw->bus.speed = i40e_bus_speed_8000;
6457 hw->bus.speed = i40e_bus_speed_unknown;
6463 * i40e_aq_debug_dump
6464 * @hw: pointer to the hardware structure
6465 * @cluster_id: specific cluster to dump
6466 * @table_id: table id within cluster
6467 * @start_index: index of line in the block to read
6468 * @buff_size: dump buffer size
6469 * @buff: dump buffer
6470 * @ret_buff_size: actual buffer size returned
6471 * @ret_next_table: next block to read
6472 * @ret_next_index: next index to read
6473 * @cmd_details: pointer to command details structure or NULL
6475 * Dump internal FW/HW data for debug purposes.
6478 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
6479 u8 table_id, u32 start_index, u16 buff_size,
6480 void *buff, u16 *ret_buff_size,
6481 u8 *ret_next_table, u32 *ret_next_index,
6482 struct i40e_asq_cmd_details *cmd_details)
6484 struct i40e_aq_desc desc;
6485 struct i40e_aqc_debug_dump_internals *cmd =
6486 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6487 struct i40e_aqc_debug_dump_internals *resp =
6488 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6489 enum i40e_status_code status;
6491 if (buff_size == 0 || !buff)
6492 return I40E_ERR_PARAM;
6494 i40e_fill_default_direct_cmd_desc(&desc,
6495 i40e_aqc_opc_debug_dump_internals);
6496 /* Indirect Command */
6497 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6498 if (buff_size > I40E_AQ_LARGE_BUF)
6499 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6501 cmd->cluster_id = cluster_id;
6502 cmd->table_id = table_id;
6503 cmd->idx = CPU_TO_LE32(start_index);
6505 desc.datalen = CPU_TO_LE16(buff_size);
6507 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
6509 if (ret_buff_size != NULL)
6510 *ret_buff_size = LE16_TO_CPU(desc.datalen);
6511 if (ret_next_table != NULL)
6512 *ret_next_table = resp->table_id;
6513 if (ret_next_index != NULL)
6514 *ret_next_index = LE32_TO_CPU(resp->idx);
6523 * @hw: pointer to the hardware structure
6524 * @enable: state of Energy Efficient Ethernet mode to be set
6526 * Enables or disables Energy Efficient Ethernet (EEE) mode
6527 * accordingly to @enable parameter.
6529 enum i40e_status_code i40e_enable_eee(struct i40e_hw *hw, bool enable)
6531 struct i40e_aq_get_phy_abilities_resp abilities;
6532 struct i40e_aq_set_phy_config config;
6533 enum i40e_status_code status;
6534 __le16 eee_capability;
6536 /* Get initial PHY capabilities */
6537 status = i40e_aq_get_phy_capabilities(hw, false, true, &abilities,
6542 /* Check whether NIC configuration is compatible with Energy Efficient
6543 * Ethernet (EEE) mode.
6545 if (abilities.eee_capability == 0) {
6546 status = I40E_ERR_CONFIG;
6550 /* Cache initial EEE capability */
6551 eee_capability = abilities.eee_capability;
6553 /* Get current configuration */
6554 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
6559 /* Cache current configuration */
6560 config.phy_type = abilities.phy_type;
6561 config.phy_type_ext = abilities.phy_type_ext;
6562 config.link_speed = abilities.link_speed;
6563 config.abilities = abilities.abilities |
6564 I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
6565 config.eeer = abilities.eeer_val;
6566 config.low_power_ctrl = abilities.d3_lpan;
6567 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
6568 I40E_AQ_PHY_FEC_CONFIG_MASK;
6570 /* Set desired EEE state */
6572 config.eee_capability = eee_capability;
6573 config.eeer |= I40E_PRTPM_EEER_TX_LPI_EN_MASK;
6575 config.eee_capability = 0;
6576 config.eeer &= ~I40E_PRTPM_EEER_TX_LPI_EN_MASK;
6579 /* Save modified config */
6580 status = i40e_aq_set_phy_config(hw, &config, NULL);
6586 * i40e_read_bw_from_alt_ram
6587 * @hw: pointer to the hardware structure
6588 * @max_bw: pointer for max_bw read
6589 * @min_bw: pointer for min_bw read
6590 * @min_valid: pointer for bool that is true if min_bw is a valid value
6591 * @max_valid: pointer for bool that is true if max_bw is a valid value
6593 * Read bw from the alternate ram for the given pf
6595 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
6596 u32 *max_bw, u32 *min_bw,
6597 bool *min_valid, bool *max_valid)
6599 enum i40e_status_code status;
6600 u32 max_bw_addr, min_bw_addr;
6602 /* Calculate the address of the min/max bw registers */
6603 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6604 I40E_ALT_STRUCT_MAX_BW_OFFSET +
6605 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6606 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6607 I40E_ALT_STRUCT_MIN_BW_OFFSET +
6608 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6610 /* Read the bandwidths from alt ram */
6611 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
6612 min_bw_addr, min_bw);
6614 if (*min_bw & I40E_ALT_BW_VALID_MASK)
6619 if (*max_bw & I40E_ALT_BW_VALID_MASK)
6628 * i40e_aq_configure_partition_bw
6629 * @hw: pointer to the hardware structure
6630 * @bw_data: Buffer holding valid pfs and bw limits
6631 * @cmd_details: pointer to command details
6633 * Configure partitions guaranteed/max bw
6635 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6636 struct i40e_aqc_configure_partition_bw_data *bw_data,
6637 struct i40e_asq_cmd_details *cmd_details)
6639 enum i40e_status_code status;
6640 struct i40e_aq_desc desc;
6641 u16 bwd_size = sizeof(*bw_data);
6643 i40e_fill_default_direct_cmd_desc(&desc,
6644 i40e_aqc_opc_configure_partition_bw);
6646 /* Indirect command */
6647 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6648 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6650 desc.datalen = CPU_TO_LE16(bwd_size);
6652 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6658 * i40e_read_phy_register_clause22
6659 * @hw: pointer to the HW structure
6660 * @reg: register address in the page
6661 * @phy_addr: PHY address on MDIO interface
6662 * @value: PHY register value
6664 * Reads specified PHY register value
6666 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
6667 u16 reg, u8 phy_addr, u16 *value)
6669 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6670 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6674 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6675 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6676 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
6677 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6678 (I40E_GLGEN_MSCA_MDICMD_MASK);
6679 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6681 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6682 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6683 status = I40E_SUCCESS;
6686 i40e_usec_delay(10);
6691 i40e_debug(hw, I40E_DEBUG_PHY,
6692 "PHY: Can't write command to external PHY.\n");
6694 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6695 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6696 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6703 * i40e_write_phy_register_clause22
6704 * @hw: pointer to the HW structure
6705 * @reg: register address in the page
6706 * @phy_addr: PHY address on MDIO interface
6707 * @value: PHY register value
6709 * Writes specified PHY register value
6711 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6712 u16 reg, u8 phy_addr, u16 value)
6714 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6715 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6719 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6720 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6722 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6723 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6724 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6725 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6726 (I40E_GLGEN_MSCA_MDICMD_MASK);
6728 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6730 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6731 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6732 status = I40E_SUCCESS;
6735 i40e_usec_delay(10);
6743 * i40e_read_phy_register_clause45
6744 * @hw: pointer to the HW structure
6745 * @page: registers page number
6746 * @reg: register address in the page
6747 * @phy_addr: PHY address on MDIO interface
6748 * @value: PHY register value
6750 * Reads specified PHY register value
6752 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6753 u8 page, u16 reg, u8 phy_addr, u16 *value)
6755 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6758 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6760 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6761 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6762 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6763 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6764 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6765 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6766 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6767 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6769 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6770 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6771 status = I40E_SUCCESS;
6774 i40e_usec_delay(10);
6779 i40e_debug(hw, I40E_DEBUG_PHY,
6780 "PHY: Can't write command to external PHY.\n");
6784 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6785 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6786 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6787 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6788 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6789 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6790 status = I40E_ERR_TIMEOUT;
6792 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6794 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6795 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6796 status = I40E_SUCCESS;
6799 i40e_usec_delay(10);
6804 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6805 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6806 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6808 i40e_debug(hw, I40E_DEBUG_PHY,
6809 "PHY: Can't read register value from external PHY.\n");
6817 * i40e_write_phy_register_clause45
6818 * @hw: pointer to the HW structure
6819 * @page: registers page number
6820 * @reg: register address in the page
6821 * @phy_addr: PHY address on MDIO interface
6822 * @value: PHY register value
6824 * Writes value to specified PHY register
6826 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6827 u8 page, u16 reg, u8 phy_addr, u16 value)
6829 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6832 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6834 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6835 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6836 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6837 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6838 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6839 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6840 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6841 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6843 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6844 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6845 status = I40E_SUCCESS;
6848 i40e_usec_delay(10);
6852 i40e_debug(hw, I40E_DEBUG_PHY,
6853 "PHY: Can't write command to external PHY.\n");
6857 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6858 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6860 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6861 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6862 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6863 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6864 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6865 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6866 status = I40E_ERR_TIMEOUT;
6868 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6870 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6871 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6872 status = I40E_SUCCESS;
6875 i40e_usec_delay(10);
6884 * i40e_write_phy_register
6885 * @hw: pointer to the HW structure
6886 * @page: registers page number
6887 * @reg: register address in the page
6888 * @phy_addr: PHY address on MDIO interface
6889 * @value: PHY register value
6891 * Writes value to specified PHY register
6893 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6894 u8 page, u16 reg, u8 phy_addr, u16 value)
6896 enum i40e_status_code status;
6898 switch (hw->device_id) {
6899 case I40E_DEV_ID_1G_BASE_T_X722:
6900 status = i40e_write_phy_register_clause22(hw,
6901 reg, phy_addr, value);
6903 case I40E_DEV_ID_10G_BASE_T:
6904 case I40E_DEV_ID_10G_BASE_T4:
6905 case I40E_DEV_ID_10G_BASE_T_BC:
6906 case I40E_DEV_ID_5G_BASE_T_BC:
6907 case I40E_DEV_ID_10G_BASE_T_X722:
6908 case I40E_DEV_ID_25G_B:
6909 case I40E_DEV_ID_25G_SFP28:
6910 status = i40e_write_phy_register_clause45(hw,
6911 page, reg, phy_addr, value);
6914 status = I40E_ERR_UNKNOWN_PHY;
6922 * i40e_read_phy_register
6923 * @hw: pointer to the HW structure
6924 * @page: registers page number
6925 * @reg: register address in the page
6926 * @phy_addr: PHY address on MDIO interface
6927 * @value: PHY register value
6929 * Reads specified PHY register value
6931 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6932 u8 page, u16 reg, u8 phy_addr, u16 *value)
6934 enum i40e_status_code status;
6936 switch (hw->device_id) {
6937 case I40E_DEV_ID_1G_BASE_T_X722:
6938 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6941 case I40E_DEV_ID_10G_BASE_T:
6942 case I40E_DEV_ID_10G_BASE_T4:
6943 case I40E_DEV_ID_5G_BASE_T_BC:
6944 case I40E_DEV_ID_10G_BASE_T_X722:
6945 case I40E_DEV_ID_25G_B:
6946 case I40E_DEV_ID_25G_SFP28:
6947 status = i40e_read_phy_register_clause45(hw, page, reg,
6951 status = I40E_ERR_UNKNOWN_PHY;
6959 * i40e_get_phy_address
6960 * @hw: pointer to the HW structure
6961 * @dev_num: PHY port num that address we want
6963 * Gets PHY address for current port
6965 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6967 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6968 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6970 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6974 * i40e_blink_phy_led
6975 * @hw: pointer to the HW structure
6976 * @time: time how long led will blinks in secs
6977 * @interval: gap between LED on and off in msecs
6979 * Blinks PHY link LED
6981 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6982 u32 time, u32 interval)
6984 enum i40e_status_code status = I40E_SUCCESS;
6989 u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6993 i = rd32(hw, I40E_PFGEN_PORTNUM);
6994 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6995 phy_addr = i40e_get_phy_address(hw, port_num);
6997 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6999 status = i40e_read_phy_register_clause45(hw,
7000 I40E_PHY_COM_REG_PAGE,
7004 goto phy_blinking_end;
7006 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
7008 status = i40e_write_phy_register_clause45(hw,
7009 I40E_PHY_COM_REG_PAGE,
7013 goto phy_blinking_end;
7018 if (time > 0 && interval > 0) {
7019 for (i = 0; i < time * 1000; i += interval) {
7020 status = i40e_read_phy_register_clause45(hw,
7021 I40E_PHY_COM_REG_PAGE,
7022 led_addr, phy_addr, &led_reg);
7024 goto restore_config;
7025 if (led_reg & I40E_PHY_LED_MANUAL_ON)
7028 led_reg = I40E_PHY_LED_MANUAL_ON;
7029 status = i40e_write_phy_register_clause45(hw,
7030 I40E_PHY_COM_REG_PAGE,
7031 led_addr, phy_addr, led_reg);
7033 goto restore_config;
7034 i40e_msec_delay(interval);
7039 status = i40e_write_phy_register_clause45(hw,
7040 I40E_PHY_COM_REG_PAGE,
7041 led_addr, phy_addr, led_ctl);
7048 * i40e_led_get_reg - read LED register
7049 * @hw: pointer to the HW structure
7050 * @led_addr: LED register address
7051 * @reg_val: read register value
7053 enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr,
7056 enum i40e_status_code status;
7060 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
7061 status = i40e_aq_get_phy_register(hw,
7062 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
7063 I40E_PHY_COM_REG_PAGE, true,
7064 I40E_PHY_LED_PROV_REG_1,
7067 phy_addr = i40e_get_phy_address(hw, hw->port);
7068 status = i40e_read_phy_register_clause45(hw,
7069 I40E_PHY_COM_REG_PAGE,
7077 * i40e_led_set_reg - write LED register
7078 * @hw: pointer to the HW structure
7079 * @led_addr: LED register address
7080 * @reg_val: register value to write
7082 enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr,
7085 enum i40e_status_code status;
7088 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
7089 status = i40e_aq_set_phy_register(hw,
7090 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
7091 I40E_PHY_COM_REG_PAGE, true,
7092 I40E_PHY_LED_PROV_REG_1,
7095 phy_addr = i40e_get_phy_address(hw, hw->port);
7096 status = i40e_write_phy_register_clause45(hw,
7097 I40E_PHY_COM_REG_PAGE,
7106 * i40e_led_get_phy - return current on/off mode
7107 * @hw: pointer to the hw struct
7108 * @led_addr: address of led register to use
7109 * @val: original value of register to use
7112 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
7115 enum i40e_status_code status = I40E_SUCCESS;
7122 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
7123 status = i40e_aq_get_phy_register(hw,
7124 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
7125 I40E_PHY_COM_REG_PAGE, true,
7126 I40E_PHY_LED_PROV_REG_1,
7128 if (status == I40E_SUCCESS)
7129 *val = (u16)reg_val_aq;
7132 temp_addr = I40E_PHY_LED_PROV_REG_1;
7133 phy_addr = i40e_get_phy_address(hw, hw->port);
7134 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
7136 status = i40e_read_phy_register_clause45(hw,
7137 I40E_PHY_COM_REG_PAGE,
7138 temp_addr, phy_addr,
7143 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
7144 *led_addr = temp_addr;
7153 * @hw: pointer to the HW structure
7154 * @on: true or false
7155 * @led_addr: address of led register to use
7156 * @mode: original val plus bit for set or ignore
7158 * Set led's on or off when controlled by the PHY
7161 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
7162 u16 led_addr, u32 mode)
7164 enum i40e_status_code status = I40E_SUCCESS;
7168 status = i40e_led_get_reg(hw, led_addr, &led_reg);
7172 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
7174 status = i40e_led_set_reg(hw, led_addr, led_reg);
7178 status = i40e_led_get_reg(hw, led_addr, &led_reg);
7180 goto restore_config;
7182 led_reg = I40E_PHY_LED_MANUAL_ON;
7185 status = i40e_led_set_reg(hw, led_addr, led_reg);
7187 goto restore_config;
7188 if (mode & I40E_PHY_LED_MODE_ORIG) {
7189 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
7190 status = i40e_led_set_reg(hw, led_addr, led_ctl);
7195 status = i40e_led_set_reg(hw, led_addr, led_ctl);
7198 #endif /* PF_DRIVER */
7200 * i40e_get_phy_lpi_status - read LPI status from PHY or MAC register
7201 * @hw: pointer to the hw struct
7202 * @stat: pointer to structure with status of rx and tx lpi
7204 * Read LPI state directly from external PHY register or from MAC
7205 * register, depending on device ID and current link speed.
7207 enum i40e_status_code i40e_get_phy_lpi_status(struct i40e_hw *hw,
7208 struct i40e_hw_port_stats *stat)
7210 enum i40e_status_code ret = I40E_SUCCESS;
7215 stat->rx_lpi_status = 0;
7216 stat->tx_lpi_status = 0;
7219 (hw->device_id == I40E_DEV_ID_10G_BASE_T_BC ||
7220 hw->device_id == I40E_DEV_ID_5G_BASE_T_BC) &&
7221 (hw->phy.link_info.link_speed == I40E_LINK_SPEED_2_5GB ||
7222 hw->phy.link_info.link_speed == I40E_LINK_SPEED_5GB);
7224 hw->device_id == I40E_DEV_ID_1G_BASE_T_X722;
7226 if (eee_bcm_phy || eee_mrvl_phy) {
7227 /* read Clause 45 PCS Status 1 register */
7228 ret = i40e_aq_get_phy_register(hw,
7229 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
7230 I40E_BCM_PHY_PCS_STATUS1_PAGE,
7232 I40E_BCM_PHY_PCS_STATUS1_REG,
7235 if (ret != I40E_SUCCESS)
7238 stat->rx_lpi_status = !!(val & I40E_BCM_PHY_PCS_STATUS1_RX_LPI);
7239 stat->tx_lpi_status = !!(val & I40E_BCM_PHY_PCS_STATUS1_TX_LPI);
7244 val = rd32(hw, I40E_PRTPM_EEE_STAT);
7245 stat->rx_lpi_status = (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
7246 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
7247 stat->tx_lpi_status = (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
7248 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
7254 * i40e_get_lpi_counters - read LPI counters from EEE statistics
7255 * @hw: pointer to the hw struct
7256 * @tx_counter: pointer to memory for TX LPI counter
7257 * @rx_counter: pointer to memory for RX LPI counter
7258 * @is_clear: returns true if counters are clear after read
7260 * Read Low Power Idle (LPI) mode counters from Energy Efficient
7261 * Ethernet (EEE) statistics.
7263 enum i40e_status_code i40e_get_lpi_counters(struct i40e_hw *hw,
7264 u32 *tx_counter, u32 *rx_counter,
7267 /* only X710-T*L requires special handling of counters
7268 * for other devices we just read the MAC registers
7270 if ((hw->device_id == I40E_DEV_ID_10G_BASE_T_BC ||
7271 hw->device_id == I40E_DEV_ID_5G_BASE_T_BC) &&
7272 hw->phy.link_info.link_speed != I40E_LINK_SPEED_1GB) {
7273 enum i40e_status_code retval;
7277 retval = i40e_aq_run_phy_activity(hw,
7278 I40E_AQ_RUN_PHY_ACT_ID_USR_DFND,
7279 I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_STAT,
7280 &cmd_status, tx_counter, rx_counter, NULL);
7282 if (!retval && cmd_status != I40E_AQ_RUN_PHY_ACT_CMD_STAT_SUCC)
7283 retval = I40E_ERR_ADMIN_QUEUE_ERROR;
7289 *tx_counter = rd32(hw, I40E_PRTPM_TLPIC);
7290 *rx_counter = rd32(hw, I40E_PRTPM_RLPIC);
7292 return I40E_SUCCESS;
7296 * i40e_get_lpi_duration - read LPI time duration from EEE statistics
7297 * @hw: pointer to the hw struct
7298 * @stat: pointer to structure with status of rx and tx lpi
7299 * @tx_duration: pointer to memory for TX LPI time duration
7300 * @rx_duration: pointer to memory for RX LPI time duration
7302 * Read Low Power Idle (LPI) mode time duration from Energy Efficient
7303 * Ethernet (EEE) statistics.
7305 enum i40e_status_code i40e_get_lpi_duration(struct i40e_hw *hw,
7306 struct i40e_hw_port_stats *stat,
7307 u64 *tx_duration, u64 *rx_duration)
7309 u32 tx_time_dur, rx_time_dur;
7310 enum i40e_status_code retval;
7313 if (hw->device_id != I40E_DEV_ID_10G_BASE_T_BC &&
7314 hw->device_id != I40E_DEV_ID_5G_BASE_T_BC)
7315 return I40E_ERR_NOT_IMPLEMENTED;
7317 retval = i40e_aq_run_phy_activity
7318 (hw, I40E_AQ_RUN_PHY_ACT_ID_USR_DFND,
7319 I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_DUR,
7320 &cmd_status, &tx_time_dur, &rx_time_dur, NULL);
7324 if ((cmd_status & I40E_AQ_RUN_PHY_ACT_CMD_STAT_MASK) !=
7325 I40E_AQ_RUN_PHY_ACT_CMD_STAT_SUCC)
7326 return I40E_ERR_ADMIN_QUEUE_ERROR;
7328 if (hw->phy.link_info.link_speed == I40E_LINK_SPEED_1GB &&
7329 !tx_time_dur && !rx_time_dur &&
7330 stat->tx_lpi_status && stat->rx_lpi_status) {
7331 retval = i40e_aq_run_phy_activity
7332 (hw, I40E_AQ_RUN_PHY_ACT_ID_USR_DFND,
7333 I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_STAT_DUR,
7335 &tx_time_dur, &rx_time_dur, NULL);
7339 if ((cmd_status & I40E_AQ_RUN_PHY_ACT_CMD_STAT_MASK) !=
7340 I40E_AQ_RUN_PHY_ACT_CMD_STAT_SUCC)
7341 return I40E_ERR_ADMIN_QUEUE_ERROR;
7346 *tx_duration = tx_time_dur;
7347 *rx_duration = rx_time_dur;
7353 * i40e_lpi_stat_update - update LPI counters with values relative to offset
7354 * @hw: pointer to the hw struct
7355 * @offset_loaded: flag indicating need of writing current value to offset
7356 * @tx_offset: pointer to offset of TX LPI counter
7357 * @tx_stat: pointer to value of TX LPI counter
7358 * @rx_offset: pointer to offset of RX LPI counter
7359 * @rx_stat: pointer to value of RX LPI counter
7361 * Update Low Power Idle (LPI) mode counters while having regard to passed
7364 enum i40e_status_code i40e_lpi_stat_update(struct i40e_hw *hw,
7365 bool offset_loaded, u64 *tx_offset,
7366 u64 *tx_stat, u64 *rx_offset,
7369 enum i40e_status_code retval;
7370 u32 tx_counter, rx_counter;
7373 retval = i40e_get_lpi_counters(hw, &tx_counter, &rx_counter, &is_clear);
7378 *tx_stat += tx_counter;
7379 *rx_stat += rx_counter;
7381 if (!offset_loaded) {
7382 *tx_offset = tx_counter;
7383 *rx_offset = rx_counter;
7386 *tx_stat = (tx_counter >= *tx_offset) ?
7387 (u32)(tx_counter - *tx_offset) :
7388 (u32)((tx_counter + BIT_ULL(32)) - *tx_offset);
7389 *rx_stat = (rx_counter >= *rx_offset) ?
7390 (u32)(rx_counter - *rx_offset) :
7391 (u32)((rx_counter + BIT_ULL(32)) - *rx_offset);
7398 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
7399 * @hw: pointer to the hw struct
7400 * @reg_addr: register address
7401 * @reg_val: ptr to register value
7402 * @cmd_details: pointer to command details structure or NULL
7404 * Use the firmware to read the Rx control register,
7405 * especially useful if the Rx unit is under heavy pressure
7407 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
7408 u32 reg_addr, u32 *reg_val,
7409 struct i40e_asq_cmd_details *cmd_details)
7411 struct i40e_aq_desc desc;
7412 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
7413 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
7414 enum i40e_status_code status;
7416 if (reg_val == NULL)
7417 return I40E_ERR_PARAM;
7419 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
7421 cmd_resp->address = CPU_TO_LE32(reg_addr);
7423 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7425 if (status == I40E_SUCCESS)
7426 *reg_val = LE32_TO_CPU(cmd_resp->value);
7432 * i40e_read_rx_ctl - read from an Rx control register
7433 * @hw: pointer to the hw struct
7434 * @reg_addr: register address
7436 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
7438 enum i40e_status_code status = I40E_SUCCESS;
7443 use_register = (((hw->aq.api_maj_ver == 1) &&
7444 (hw->aq.api_min_ver < 5)) ||
7445 (hw->mac.type == I40E_MAC_X722));
7446 if (!use_register) {
7448 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
7449 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
7456 /* if the AQ access failed, try the old-fashioned way */
7457 if (status || use_register)
7458 val = rd32(hw, reg_addr);
7464 * i40e_aq_rx_ctl_write_register
7465 * @hw: pointer to the hw struct
7466 * @reg_addr: register address
7467 * @reg_val: register value
7468 * @cmd_details: pointer to command details structure or NULL
7470 * Use the firmware to write to an Rx control register,
7471 * especially useful if the Rx unit is under heavy pressure
7473 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
7474 u32 reg_addr, u32 reg_val,
7475 struct i40e_asq_cmd_details *cmd_details)
7477 struct i40e_aq_desc desc;
7478 struct i40e_aqc_rx_ctl_reg_read_write *cmd =
7479 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
7480 enum i40e_status_code status;
7482 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
7484 cmd->address = CPU_TO_LE32(reg_addr);
7485 cmd->value = CPU_TO_LE32(reg_val);
7487 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7493 * i40e_write_rx_ctl - write to an Rx control register
7494 * @hw: pointer to the hw struct
7495 * @reg_addr: register address
7496 * @reg_val: register value
7498 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
7500 enum i40e_status_code status = I40E_SUCCESS;
7504 use_register = (((hw->aq.api_maj_ver == 1) &&
7505 (hw->aq.api_min_ver < 5)) ||
7506 (hw->mac.type == I40E_MAC_X722));
7507 if (!use_register) {
7509 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
7511 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
7518 /* if the AQ access failed, try the old-fashioned way */
7519 if (status || use_register)
7520 wr32(hw, reg_addr, reg_val);
7524 * i40e_mdio_if_number_selection - MDIO I/F number selection
7525 * @hw: pointer to the hw struct
7526 * @set_mdio: use MDIO I/F number specified by mdio_num
7527 * @mdio_num: MDIO I/F number
7528 * @cmd: pointer to PHY Register command structure
7531 i40e_mdio_if_number_selection(struct i40e_hw *hw, bool set_mdio, u8 mdio_num,
7532 struct i40e_aqc_phy_register_access *cmd)
7534 if (set_mdio && cmd->phy_interface == I40E_AQ_PHY_REG_ACCESS_EXTERNAL) {
7535 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_EXTENDED)
7537 I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER |
7539 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT) &
7540 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK);
7542 i40e_debug(hw, I40E_DEBUG_PHY,
7543 "MDIO I/F number selection not supported by current FW version.\n");
7548 * i40e_aq_set_phy_register_ext
7549 * @hw: pointer to the hw struct
7550 * @phy_select: select which phy should be accessed
7551 * @dev_addr: PHY device address
7552 * @page_change: enable auto page change
7553 * @set_mdio: use MDIO I/F number specified by mdio_num
7554 * @mdio_num: MDIO I/F number
7555 * @reg_addr: PHY register address
7556 * @reg_val: new register value
7557 * @cmd_details: pointer to command details structure or NULL
7559 * Write the external PHY register.
7560 * NOTE: In common cases MDIO I/F number should not be changed, thats why you
7561 * may use simple wrapper i40e_aq_set_phy_register.
7563 enum i40e_status_code
7564 i40e_aq_set_phy_register_ext(struct i40e_hw *hw,
7565 u8 phy_select, u8 dev_addr, bool page_change,
7566 bool set_mdio, u8 mdio_num,
7567 u32 reg_addr, u32 reg_val,
7568 struct i40e_asq_cmd_details *cmd_details)
7570 struct i40e_aq_desc desc;
7571 struct i40e_aqc_phy_register_access *cmd =
7572 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7573 enum i40e_status_code status;
7575 i40e_fill_default_direct_cmd_desc(&desc,
7576 i40e_aqc_opc_set_phy_register);
7578 cmd->phy_interface = phy_select;
7579 cmd->dev_addres = dev_addr;
7580 cmd->reg_address = CPU_TO_LE32(reg_addr);
7581 cmd->reg_value = CPU_TO_LE32(reg_val);
7584 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
7586 i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd);
7588 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7594 * i40e_aq_get_phy_register_ext
7595 * @hw: pointer to the hw struct
7596 * @phy_select: select which phy should be accessed
7597 * @dev_addr: PHY device address
7598 * @page_change: enable auto page change
7599 * @set_mdio: use MDIO I/F number specified by mdio_num
7600 * @mdio_num: MDIO I/F number
7601 * @reg_addr: PHY register address
7602 * @reg_val: read register value
7603 * @cmd_details: pointer to command details structure or NULL
7605 * Read the external PHY register.
7606 * NOTE: In common cases MDIO I/F number should not be changed, thats why you
7607 * may use simple wrapper i40e_aq_get_phy_register.
7609 enum i40e_status_code
7610 i40e_aq_get_phy_register_ext(struct i40e_hw *hw,
7611 u8 phy_select, u8 dev_addr, bool page_change,
7612 bool set_mdio, u8 mdio_num,
7613 u32 reg_addr, u32 *reg_val,
7614 struct i40e_asq_cmd_details *cmd_details)
7616 struct i40e_aq_desc desc;
7617 struct i40e_aqc_phy_register_access *cmd =
7618 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7619 enum i40e_status_code status;
7621 i40e_fill_default_direct_cmd_desc(&desc,
7622 i40e_aqc_opc_get_phy_register);
7624 cmd->phy_interface = phy_select;
7625 cmd->dev_addres = dev_addr;
7626 cmd->reg_address = CPU_TO_LE32(reg_addr);
7629 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
7631 i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd);
7633 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7635 *reg_val = LE32_TO_CPU(cmd->reg_value);
7641 * i40e_aq_run_phy_activity
7642 * @hw: pointer to the hw struct
7643 * @activity_id: ID of DNL activity to run
7644 * @dnl_opcode: opcode passed to DNL script
7645 * @cmd_status: pointer to memory to write return value of DNL script
7646 * @data0: pointer to memory for first 4 bytes of data returned by DNL script
7647 * @data1: pointer to memory for last 4 bytes of data returned by DNL script
7648 * @cmd_details: pointer to command details structure or NULL
7650 * Run DNL admin command.
7652 enum i40e_status_code
7653 i40e_aq_run_phy_activity(struct i40e_hw *hw, u16 activity_id, u32 dnl_opcode,
7654 u32 *cmd_status, u32 *data0, u32 *data1,
7655 struct i40e_asq_cmd_details *cmd_details)
7657 struct i40e_aqc_run_phy_activity *cmd;
7658 enum i40e_status_code retval;
7659 struct i40e_aq_desc desc;
7661 cmd = (struct i40e_aqc_run_phy_activity *)&desc.params.raw;
7663 if (!cmd_status || !data0 || !data1) {
7664 retval = I40E_ERR_PARAM;
7668 i40e_fill_default_direct_cmd_desc(&desc,
7669 i40e_aqc_opc_run_phy_activity);
7671 cmd->activity_id = CPU_TO_LE16(activity_id);
7672 cmd->params.cmd.dnl_opcode = CPU_TO_LE32(dnl_opcode);
7674 retval = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7678 *cmd_status = LE32_TO_CPU(cmd->params.resp.cmd_status);
7679 *data0 = LE32_TO_CPU(cmd->params.resp.data0);
7680 *data1 = LE32_TO_CPU(cmd->params.resp.data1);
7688 * i40e_aq_send_msg_to_pf
7689 * @hw: pointer to the hardware structure
7690 * @v_opcode: opcodes for VF-PF communication
7691 * @v_retval: return error code
7692 * @msg: pointer to the msg buffer
7693 * @msglen: msg length
7694 * @cmd_details: pointer to command details
7696 * Send message to PF driver using admin queue. By default, this message
7697 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
7698 * completion before returning.
7700 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
7701 enum virtchnl_ops v_opcode,
7702 enum i40e_status_code v_retval,
7703 u8 *msg, u16 msglen,
7704 struct i40e_asq_cmd_details *cmd_details)
7706 struct i40e_aq_desc desc;
7707 struct i40e_asq_cmd_details details;
7708 enum i40e_status_code status;
7710 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
7711 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
7712 desc.cookie_high = CPU_TO_LE32(v_opcode);
7713 desc.cookie_low = CPU_TO_LE32(v_retval);
7715 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
7716 | I40E_AQ_FLAG_RD));
7717 if (msglen > I40E_AQ_LARGE_BUF)
7718 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7719 desc.datalen = CPU_TO_LE16(msglen);
7722 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
7723 details.async = true;
7724 cmd_details = &details;
7726 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
7727 msglen, cmd_details);
7732 * i40e_vf_parse_hw_config
7733 * @hw: pointer to the hardware structure
7734 * @msg: pointer to the virtual channel VF resource structure
7736 * Given a VF resource message from the PF, populate the hw struct
7737 * with appropriate information.
7739 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
7740 struct virtchnl_vf_resource *msg)
7742 struct virtchnl_vsi_resource *vsi_res;
7745 vsi_res = &msg->vsi_res[0];
7747 hw->dev_caps.num_vsis = msg->num_vsis;
7748 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
7749 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
7750 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
7751 hw->dev_caps.dcb = msg->vf_cap_flags &
7752 VIRTCHNL_VF_OFFLOAD_L2;
7753 hw->dev_caps.iwarp = (msg->vf_cap_flags &
7754 VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
7755 for (i = 0; i < msg->num_vsis; i++) {
7756 if (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) {
7757 i40e_memcpy(hw->mac.perm_addr,
7758 vsi_res->default_mac_addr,
7760 I40E_NONDMA_TO_NONDMA);
7761 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
7763 I40E_NONDMA_TO_NONDMA);
7771 * @hw: pointer to the hardware structure
7773 * Send a VF_RESET message to the PF. Does not wait for response from PF
7774 * as none will be forthcoming. Immediately after calling this function,
7775 * the admin queue should be shut down and (optionally) reinitialized.
7777 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
7779 return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF,
7780 I40E_SUCCESS, NULL, 0, NULL);
7782 #endif /* VF_DRIVER */
7785 * i40e_aq_set_arp_proxy_config
7786 * @hw: pointer to the HW structure
7787 * @proxy_config: pointer to proxy config command table struct
7788 * @cmd_details: pointer to command details
7790 * Set ARP offload parameters from pre-populated
7791 * i40e_aqc_arp_proxy_data struct
7793 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
7794 struct i40e_aqc_arp_proxy_data *proxy_config,
7795 struct i40e_asq_cmd_details *cmd_details)
7797 struct i40e_aq_desc desc;
7798 enum i40e_status_code status;
7801 return I40E_ERR_PARAM;
7803 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
7805 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7806 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7807 desc.params.external.addr_high =
7808 CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
7809 desc.params.external.addr_low =
7810 CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
7811 desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_arp_proxy_data));
7813 status = i40e_asq_send_command(hw, &desc, proxy_config,
7814 sizeof(struct i40e_aqc_arp_proxy_data),
7821 * i40e_aq_opc_set_ns_proxy_table_entry
7822 * @hw: pointer to the HW structure
7823 * @ns_proxy_table_entry: pointer to NS table entry command struct
7824 * @cmd_details: pointer to command details
7826 * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
7827 * from pre-populated i40e_aqc_ns_proxy_data struct
7829 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
7830 struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
7831 struct i40e_asq_cmd_details *cmd_details)
7833 struct i40e_aq_desc desc;
7834 enum i40e_status_code status;
7836 if (!ns_proxy_table_entry)
7837 return I40E_ERR_PARAM;
7839 i40e_fill_default_direct_cmd_desc(&desc,
7840 i40e_aqc_opc_set_ns_proxy_table_entry);
7842 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7843 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7844 desc.params.external.addr_high =
7845 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
7846 desc.params.external.addr_low =
7847 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
7848 desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_ns_proxy_data));
7850 status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
7851 sizeof(struct i40e_aqc_ns_proxy_data),
7858 * i40e_aq_set_clear_wol_filter
7859 * @hw: pointer to the hw struct
7860 * @filter_index: index of filter to modify (0-7)
7861 * @filter: buffer containing filter to be set
7862 * @set_filter: true to set filter, false to clear filter
7863 * @no_wol_tco: if true, pass through packets cannot cause wake-up
7864 * if false, pass through packets may cause wake-up
7865 * @filter_valid: true if filter action is valid
7866 * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
7867 * @cmd_details: pointer to command details structure or NULL
7869 * Set or clear WoL filter for port attached to the PF
7871 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
7873 struct i40e_aqc_set_wol_filter_data *filter,
7874 bool set_filter, bool no_wol_tco,
7875 bool filter_valid, bool no_wol_tco_valid,
7876 struct i40e_asq_cmd_details *cmd_details)
7878 struct i40e_aq_desc desc;
7879 struct i40e_aqc_set_wol_filter *cmd =
7880 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
7881 enum i40e_status_code status;
7883 u16 valid_flags = 0;
7886 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
7888 if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
7889 return I40E_ERR_PARAM;
7890 cmd->filter_index = CPU_TO_LE16(filter_index);
7894 return I40E_ERR_PARAM;
7896 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
7897 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR;
7901 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
7902 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
7905 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
7906 if (no_wol_tco_valid)
7907 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
7908 cmd->valid_flags = CPU_TO_LE16(valid_flags);
7910 buff_len = sizeof(*filter);
7911 desc.datalen = CPU_TO_LE16(buff_len);
7913 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7914 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7916 cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
7917 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
7919 status = i40e_asq_send_command(hw, &desc, filter,
7920 buff_len, cmd_details);
7926 * i40e_aq_get_wake_event_reason
7927 * @hw: pointer to the hw struct
7928 * @wake_reason: return value, index of matching filter
7929 * @cmd_details: pointer to command details structure or NULL
7931 * Get information for the reason of a Wake Up event
7933 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
7935 struct i40e_asq_cmd_details *cmd_details)
7937 struct i40e_aq_desc desc;
7938 struct i40e_aqc_get_wake_reason_completion *resp =
7939 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
7940 enum i40e_status_code status;
7942 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
7944 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7946 if (status == I40E_SUCCESS)
7947 *wake_reason = LE16_TO_CPU(resp->wake_reason);
7953 * i40e_aq_clear_all_wol_filters
7954 * @hw: pointer to the hw struct
7955 * @cmd_details: pointer to command details structure or NULL
7957 * Get information for the reason of a Wake Up event
7959 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw,
7960 struct i40e_asq_cmd_details *cmd_details)
7962 struct i40e_aq_desc desc;
7963 enum i40e_status_code status;
7965 i40e_fill_default_direct_cmd_desc(&desc,
7966 i40e_aqc_opc_clear_all_wol_filters);
7968 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7974 * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
7975 * @hw: pointer to the hw struct
7976 * @buff: command buffer (size in bytes = buff_size)
7977 * @buff_size: buffer size in bytes
7978 * @track_id: package tracking id
7979 * @error_offset: returns error offset
7980 * @error_info: returns error information
7981 * @cmd_details: pointer to command details structure or NULL
7984 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
7985 u16 buff_size, u32 track_id,
7986 u32 *error_offset, u32 *error_info,
7987 struct i40e_asq_cmd_details *cmd_details)
7989 struct i40e_aq_desc desc;
7990 struct i40e_aqc_write_personalization_profile *cmd =
7991 (struct i40e_aqc_write_personalization_profile *)
7993 struct i40e_aqc_write_ddp_resp *resp;
7994 enum i40e_status_code status;
7996 i40e_fill_default_direct_cmd_desc(&desc,
7997 i40e_aqc_opc_write_personalization_profile);
7999 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
8000 if (buff_size > I40E_AQ_LARGE_BUF)
8001 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
8003 desc.datalen = CPU_TO_LE16(buff_size);
8005 cmd->profile_track_id = CPU_TO_LE32(track_id);
8007 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
8009 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
8011 *error_offset = LE32_TO_CPU(resp->error_offset);
8013 *error_info = LE32_TO_CPU(resp->error_info);
8020 * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
8021 * @hw: pointer to the hw struct
8022 * @buff: command buffer (size in bytes = buff_size)
8023 * @buff_size: buffer size in bytes
8024 * @flags: AdminQ command flags
8025 * @cmd_details: pointer to command details structure or NULL
8028 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
8029 u16 buff_size, u8 flags,
8030 struct i40e_asq_cmd_details *cmd_details)
8032 struct i40e_aq_desc desc;
8033 struct i40e_aqc_get_applied_profiles *cmd =
8034 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
8035 enum i40e_status_code status;
8037 i40e_fill_default_direct_cmd_desc(&desc,
8038 i40e_aqc_opc_get_personalization_profile_list);
8040 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
8041 if (buff_size > I40E_AQ_LARGE_BUF)
8042 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
8043 desc.datalen = CPU_TO_LE16(buff_size);
8047 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
8053 * i40e_find_segment_in_package
8054 * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
8055 * @pkg_hdr: pointer to the package header to be searched
8057 * This function searches a package file for a particular segment type. On
8058 * success it returns a pointer to the segment header, otherwise it will
8061 struct i40e_generic_seg_header *
8062 i40e_find_segment_in_package(u32 segment_type,
8063 struct i40e_package_header *pkg_hdr)
8065 struct i40e_generic_seg_header *segment;
8068 /* Search all package segments for the requested segment type */
8069 for (i = 0; i < pkg_hdr->segment_count; i++) {
8071 (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
8072 pkg_hdr->segment_offset[i]);
8074 if (segment->type == segment_type)
8081 /* Get section table in profile */
8082 #define I40E_SECTION_TABLE(profile, sec_tbl) \
8084 struct i40e_profile_segment *p = (profile); \
8087 count = p->device_table_count; \
8088 nvm = (u32 *)&p->device_table[count]; \
8089 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \
8092 /* Get section header in profile */
8093 #define I40E_SECTION_HEADER(profile, offset) \
8094 (struct i40e_profile_section_header *)((u8 *)(profile) + (offset))
8097 * i40e_find_section_in_profile
8098 * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE)
8099 * @profile: pointer to the i40e segment header to be searched
8101 * This function searches i40e segment for a particular section type. On
8102 * success it returns a pointer to the section header, otherwise it will
8105 struct i40e_profile_section_header *
8106 i40e_find_section_in_profile(u32 section_type,
8107 struct i40e_profile_segment *profile)
8109 struct i40e_profile_section_header *sec;
8110 struct i40e_section_table *sec_tbl;
8114 if (profile->header.type != SEGMENT_TYPE_I40E)
8117 I40E_SECTION_TABLE(profile, sec_tbl);
8119 for (i = 0; i < sec_tbl->section_count; i++) {
8120 sec_off = sec_tbl->section_offset[i];
8121 sec = I40E_SECTION_HEADER(profile, sec_off);
8122 if (sec->section.type == section_type)
8130 * i40e_ddp_exec_aq_section - Execute generic AQ for DDP
8131 * @hw: pointer to the hw struct
8132 * @aq: command buffer containing all data to execute AQ
8135 i40e_status_code i40e_ddp_exec_aq_section(struct i40e_hw *hw,
8136 struct i40e_profile_aq_section *aq)
8138 enum i40e_status_code status;
8139 struct i40e_aq_desc desc;
8143 i40e_fill_default_direct_cmd_desc(&desc, aq->opcode);
8144 desc.flags |= CPU_TO_LE16(aq->flags);
8145 i40e_memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw),
8146 I40E_NONDMA_TO_NONDMA);
8148 msglen = aq->datalen;
8150 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
8152 if (msglen > I40E_AQ_LARGE_BUF)
8153 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
8154 desc.datalen = CPU_TO_LE16(msglen);
8158 status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL);
8160 if (status != I40E_SUCCESS) {
8161 i40e_debug(hw, I40E_DEBUG_PACKAGE,
8162 "unable to exec DDP AQ opcode %u, error %d\n",
8163 aq->opcode, status);
8167 /* copy returned desc to aq_buf */
8168 i40e_memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw),
8169 I40E_NONDMA_TO_NONDMA);
8171 return I40E_SUCCESS;
8175 * i40e_validate_profile
8176 * @hw: pointer to the hardware structure
8177 * @profile: pointer to the profile segment of the package to be validated
8178 * @track_id: package tracking id
8179 * @rollback: flag if the profile is for rollback.
8181 * Validates supported devices and profile's sections.
8183 STATIC enum i40e_status_code
8184 i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
8185 u32 track_id, bool rollback)
8187 struct i40e_profile_section_header *sec = NULL;
8188 enum i40e_status_code status = I40E_SUCCESS;
8189 struct i40e_section_table *sec_tbl;
8195 if (track_id == I40E_DDP_TRACKID_INVALID) {
8196 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n");
8197 return I40E_NOT_SUPPORTED;
8200 dev_cnt = profile->device_table_count;
8201 for (i = 0; i < dev_cnt; i++) {
8202 vendor_dev_id = profile->device_table[i].vendor_dev_id;
8203 if ((vendor_dev_id >> 16) == I40E_INTEL_VENDOR_ID &&
8204 hw->device_id == (vendor_dev_id & 0xFFFF))
8207 if (dev_cnt && (i == dev_cnt)) {
8208 i40e_debug(hw, I40E_DEBUG_PACKAGE,
8209 "Device doesn't support DDP\n");
8210 return I40E_ERR_DEVICE_NOT_SUPPORTED;
8213 I40E_SECTION_TABLE(profile, sec_tbl);
8215 /* Validate sections types */
8216 for (i = 0; i < sec_tbl->section_count; i++) {
8217 sec_off = sec_tbl->section_offset[i];
8218 sec = I40E_SECTION_HEADER(profile, sec_off);
8220 if (sec->section.type == SECTION_TYPE_MMIO ||
8221 sec->section.type == SECTION_TYPE_AQ ||
8222 sec->section.type == SECTION_TYPE_RB_AQ) {
8223 i40e_debug(hw, I40E_DEBUG_PACKAGE,
8224 "Not a roll-back package\n");
8225 return I40E_NOT_SUPPORTED;
8228 if (sec->section.type == SECTION_TYPE_RB_AQ ||
8229 sec->section.type == SECTION_TYPE_RB_MMIO) {
8230 i40e_debug(hw, I40E_DEBUG_PACKAGE,
8231 "Not an original package\n");
8232 return I40E_NOT_SUPPORTED;
8241 * i40e_write_profile
8242 * @hw: pointer to the hardware structure
8243 * @profile: pointer to the profile segment of the package to be downloaded
8244 * @track_id: package tracking id
8246 * Handles the download of a complete package.
8248 enum i40e_status_code
8249 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
8252 enum i40e_status_code status = I40E_SUCCESS;
8253 struct i40e_section_table *sec_tbl;
8254 struct i40e_profile_section_header *sec = NULL;
8255 struct i40e_profile_aq_section *ddp_aq;
8256 u32 section_size = 0;
8257 u32 offset = 0, info = 0;
8261 status = i40e_validate_profile(hw, profile, track_id, false);
8265 I40E_SECTION_TABLE(profile, sec_tbl);
8267 for (i = 0; i < sec_tbl->section_count; i++) {
8268 sec_off = sec_tbl->section_offset[i];
8269 sec = I40E_SECTION_HEADER(profile, sec_off);
8270 /* Process generic admin command */
8271 if (sec->section.type == SECTION_TYPE_AQ) {
8272 ddp_aq = (struct i40e_profile_aq_section *)&sec[1];
8273 status = i40e_ddp_exec_aq_section(hw, ddp_aq);
8275 i40e_debug(hw, I40E_DEBUG_PACKAGE,
8276 "Failed to execute aq: section %d, opcode %u\n",
8280 sec->section.type = SECTION_TYPE_RB_AQ;
8283 /* Skip any non-mmio sections */
8284 if (sec->section.type != SECTION_TYPE_MMIO)
8287 section_size = sec->section.size +
8288 sizeof(struct i40e_profile_section_header);
8290 /* Write MMIO section */
8291 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
8292 track_id, &offset, &info, NULL);
8294 i40e_debug(hw, I40E_DEBUG_PACKAGE,
8295 "Failed to write profile: section %d, offset %d, info %d\n",
8304 * i40e_rollback_profile
8305 * @hw: pointer to the hardware structure
8306 * @profile: pointer to the profile segment of the package to be removed
8307 * @track_id: package tracking id
8309 * Rolls back previously loaded package.
8311 enum i40e_status_code
8312 i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
8315 struct i40e_profile_section_header *sec = NULL;
8316 enum i40e_status_code status = I40E_SUCCESS;
8317 struct i40e_section_table *sec_tbl;
8318 u32 offset = 0, info = 0;
8319 u32 section_size = 0;
8323 status = i40e_validate_profile(hw, profile, track_id, true);
8327 I40E_SECTION_TABLE(profile, sec_tbl);
8329 /* For rollback write sections in reverse */
8330 for (i = sec_tbl->section_count - 1; i >= 0; i--) {
8331 sec_off = sec_tbl->section_offset[i];
8332 sec = I40E_SECTION_HEADER(profile, sec_off);
8334 /* Skip any non-rollback sections */
8335 if (sec->section.type != SECTION_TYPE_RB_MMIO)
8338 section_size = sec->section.size +
8339 sizeof(struct i40e_profile_section_header);
8341 /* Write roll-back MMIO section */
8342 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
8343 track_id, &offset, &info, NULL);
8345 i40e_debug(hw, I40E_DEBUG_PACKAGE,
8346 "Failed to write profile: section %d, offset %d, info %d\n",
8355 * i40e_add_pinfo_to_list
8356 * @hw: pointer to the hardware structure
8357 * @profile: pointer to the profile segment of the package
8358 * @profile_info_sec: buffer for information section
8359 * @track_id: package tracking id
8361 * Register a profile to the list of loaded profiles.
8363 enum i40e_status_code
8364 i40e_add_pinfo_to_list(struct i40e_hw *hw,
8365 struct i40e_profile_segment *profile,
8366 u8 *profile_info_sec, u32 track_id)
8368 enum i40e_status_code status = I40E_SUCCESS;
8369 struct i40e_profile_section_header *sec = NULL;
8370 struct i40e_profile_info *pinfo;
8371 u32 offset = 0, info = 0;
8373 sec = (struct i40e_profile_section_header *)profile_info_sec;
8375 sec->data_end = sizeof(struct i40e_profile_section_header) +
8376 sizeof(struct i40e_profile_info);
8377 sec->section.type = SECTION_TYPE_INFO;
8378 sec->section.offset = sizeof(struct i40e_profile_section_header);
8379 sec->section.size = sizeof(struct i40e_profile_info);
8380 pinfo = (struct i40e_profile_info *)(profile_info_sec +
8381 sec->section.offset);
8382 pinfo->track_id = track_id;
8383 pinfo->version = profile->version;
8384 pinfo->op = I40E_DDP_ADD_TRACKID;
8385 i40e_memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE,
8386 I40E_NONDMA_TO_NONDMA);
8388 status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
8389 track_id, &offset, &info, NULL);