1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2018
6 #include "i40e_adminq.h"
7 #include "i40e_prototype.h"
11 * i40e_set_mac_type - Sets MAC type
12 * @hw: pointer to the HW structure
14 * This function sets the mac type of the adapter based on the
15 * vendor ID and device ID stored in the hw structure.
17 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
19 enum i40e_status_code status = I40E_SUCCESS;
21 DEBUGFUNC("i40e_set_mac_type\n");
23 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
24 switch (hw->device_id) {
25 case I40E_DEV_ID_SFP_XL710:
26 case I40E_DEV_ID_QEMU:
27 case I40E_DEV_ID_KX_B:
28 case I40E_DEV_ID_KX_C:
29 case I40E_DEV_ID_QSFP_A:
30 case I40E_DEV_ID_QSFP_B:
31 case I40E_DEV_ID_QSFP_C:
32 case I40E_DEV_ID_10G_BASE_T:
33 case I40E_DEV_ID_10G_BASE_T4:
34 case I40E_DEV_ID_10G_BASE_T_BC:
35 case I40E_DEV_ID_10G_B:
36 case I40E_DEV_ID_10G_SFP:
37 case I40E_DEV_ID_20G_KR2:
38 case I40E_DEV_ID_20G_KR2_A:
39 case I40E_DEV_ID_25G_B:
40 case I40E_DEV_ID_25G_SFP28:
41 case I40E_DEV_ID_X710_N3000:
42 case I40E_DEV_ID_XXV710_N3000:
43 hw->mac.type = I40E_MAC_XL710;
45 #ifdef X722_A0_SUPPORT
46 case I40E_DEV_ID_X722_A0:
48 case I40E_DEV_ID_KX_X722:
49 case I40E_DEV_ID_QSFP_X722:
50 case I40E_DEV_ID_SFP_X722:
51 case I40E_DEV_ID_1G_BASE_T_X722:
52 case I40E_DEV_ID_10G_BASE_T_X722:
53 case I40E_DEV_ID_SFP_I_X722:
54 hw->mac.type = I40E_MAC_X722;
56 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
57 case I40E_DEV_ID_X722_VF:
58 #ifdef X722_A0_SUPPORT
59 case I40E_DEV_ID_X722_A0_VF:
61 hw->mac.type = I40E_MAC_X722_VF;
63 #endif /* INTEGRATED_VF || VF_DRIVER */
64 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
66 case I40E_DEV_ID_VF_HV:
67 case I40E_DEV_ID_ADAPTIVE_VF:
68 hw->mac.type = I40E_MAC_VF;
72 hw->mac.type = I40E_MAC_GENERIC;
76 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
79 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
80 hw->mac.type, status);
85 * i40e_aq_str - convert AQ err code to a string
86 * @hw: pointer to the HW structure
87 * @aq_err: the AQ error code to convert
89 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
94 case I40E_AQ_RC_EPERM:
95 return "I40E_AQ_RC_EPERM";
96 case I40E_AQ_RC_ENOENT:
97 return "I40E_AQ_RC_ENOENT";
98 case I40E_AQ_RC_ESRCH:
99 return "I40E_AQ_RC_ESRCH";
100 case I40E_AQ_RC_EINTR:
101 return "I40E_AQ_RC_EINTR";
103 return "I40E_AQ_RC_EIO";
104 case I40E_AQ_RC_ENXIO:
105 return "I40E_AQ_RC_ENXIO";
106 case I40E_AQ_RC_E2BIG:
107 return "I40E_AQ_RC_E2BIG";
108 case I40E_AQ_RC_EAGAIN:
109 return "I40E_AQ_RC_EAGAIN";
110 case I40E_AQ_RC_ENOMEM:
111 return "I40E_AQ_RC_ENOMEM";
112 case I40E_AQ_RC_EACCES:
113 return "I40E_AQ_RC_EACCES";
114 case I40E_AQ_RC_EFAULT:
115 return "I40E_AQ_RC_EFAULT";
116 case I40E_AQ_RC_EBUSY:
117 return "I40E_AQ_RC_EBUSY";
118 case I40E_AQ_RC_EEXIST:
119 return "I40E_AQ_RC_EEXIST";
120 case I40E_AQ_RC_EINVAL:
121 return "I40E_AQ_RC_EINVAL";
122 case I40E_AQ_RC_ENOTTY:
123 return "I40E_AQ_RC_ENOTTY";
124 case I40E_AQ_RC_ENOSPC:
125 return "I40E_AQ_RC_ENOSPC";
126 case I40E_AQ_RC_ENOSYS:
127 return "I40E_AQ_RC_ENOSYS";
128 case I40E_AQ_RC_ERANGE:
129 return "I40E_AQ_RC_ERANGE";
130 case I40E_AQ_RC_EFLUSHED:
131 return "I40E_AQ_RC_EFLUSHED";
132 case I40E_AQ_RC_BAD_ADDR:
133 return "I40E_AQ_RC_BAD_ADDR";
134 case I40E_AQ_RC_EMODE:
135 return "I40E_AQ_RC_EMODE";
136 case I40E_AQ_RC_EFBIG:
137 return "I40E_AQ_RC_EFBIG";
140 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
145 * i40e_stat_str - convert status err code to a string
146 * @hw: pointer to the HW structure
147 * @stat_err: the status error code to convert
149 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
155 return "I40E_ERR_NVM";
156 case I40E_ERR_NVM_CHECKSUM:
157 return "I40E_ERR_NVM_CHECKSUM";
159 return "I40E_ERR_PHY";
160 case I40E_ERR_CONFIG:
161 return "I40E_ERR_CONFIG";
163 return "I40E_ERR_PARAM";
164 case I40E_ERR_MAC_TYPE:
165 return "I40E_ERR_MAC_TYPE";
166 case I40E_ERR_UNKNOWN_PHY:
167 return "I40E_ERR_UNKNOWN_PHY";
168 case I40E_ERR_LINK_SETUP:
169 return "I40E_ERR_LINK_SETUP";
170 case I40E_ERR_ADAPTER_STOPPED:
171 return "I40E_ERR_ADAPTER_STOPPED";
172 case I40E_ERR_INVALID_MAC_ADDR:
173 return "I40E_ERR_INVALID_MAC_ADDR";
174 case I40E_ERR_DEVICE_NOT_SUPPORTED:
175 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
176 case I40E_ERR_MASTER_REQUESTS_PENDING:
177 return "I40E_ERR_MASTER_REQUESTS_PENDING";
178 case I40E_ERR_INVALID_LINK_SETTINGS:
179 return "I40E_ERR_INVALID_LINK_SETTINGS";
180 case I40E_ERR_AUTONEG_NOT_COMPLETE:
181 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
182 case I40E_ERR_RESET_FAILED:
183 return "I40E_ERR_RESET_FAILED";
184 case I40E_ERR_SWFW_SYNC:
185 return "I40E_ERR_SWFW_SYNC";
186 case I40E_ERR_NO_AVAILABLE_VSI:
187 return "I40E_ERR_NO_AVAILABLE_VSI";
188 case I40E_ERR_NO_MEMORY:
189 return "I40E_ERR_NO_MEMORY";
190 case I40E_ERR_BAD_PTR:
191 return "I40E_ERR_BAD_PTR";
192 case I40E_ERR_RING_FULL:
193 return "I40E_ERR_RING_FULL";
194 case I40E_ERR_INVALID_PD_ID:
195 return "I40E_ERR_INVALID_PD_ID";
196 case I40E_ERR_INVALID_QP_ID:
197 return "I40E_ERR_INVALID_QP_ID";
198 case I40E_ERR_INVALID_CQ_ID:
199 return "I40E_ERR_INVALID_CQ_ID";
200 case I40E_ERR_INVALID_CEQ_ID:
201 return "I40E_ERR_INVALID_CEQ_ID";
202 case I40E_ERR_INVALID_AEQ_ID:
203 return "I40E_ERR_INVALID_AEQ_ID";
204 case I40E_ERR_INVALID_SIZE:
205 return "I40E_ERR_INVALID_SIZE";
206 case I40E_ERR_INVALID_ARP_INDEX:
207 return "I40E_ERR_INVALID_ARP_INDEX";
208 case I40E_ERR_INVALID_FPM_FUNC_ID:
209 return "I40E_ERR_INVALID_FPM_FUNC_ID";
210 case I40E_ERR_QP_INVALID_MSG_SIZE:
211 return "I40E_ERR_QP_INVALID_MSG_SIZE";
212 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
213 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
214 case I40E_ERR_INVALID_FRAG_COUNT:
215 return "I40E_ERR_INVALID_FRAG_COUNT";
216 case I40E_ERR_QUEUE_EMPTY:
217 return "I40E_ERR_QUEUE_EMPTY";
218 case I40E_ERR_INVALID_ALIGNMENT:
219 return "I40E_ERR_INVALID_ALIGNMENT";
220 case I40E_ERR_FLUSHED_QUEUE:
221 return "I40E_ERR_FLUSHED_QUEUE";
222 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
223 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
224 case I40E_ERR_INVALID_IMM_DATA_SIZE:
225 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
226 case I40E_ERR_TIMEOUT:
227 return "I40E_ERR_TIMEOUT";
228 case I40E_ERR_OPCODE_MISMATCH:
229 return "I40E_ERR_OPCODE_MISMATCH";
230 case I40E_ERR_CQP_COMPL_ERROR:
231 return "I40E_ERR_CQP_COMPL_ERROR";
232 case I40E_ERR_INVALID_VF_ID:
233 return "I40E_ERR_INVALID_VF_ID";
234 case I40E_ERR_INVALID_HMCFN_ID:
235 return "I40E_ERR_INVALID_HMCFN_ID";
236 case I40E_ERR_BACKING_PAGE_ERROR:
237 return "I40E_ERR_BACKING_PAGE_ERROR";
238 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
239 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
240 case I40E_ERR_INVALID_PBLE_INDEX:
241 return "I40E_ERR_INVALID_PBLE_INDEX";
242 case I40E_ERR_INVALID_SD_INDEX:
243 return "I40E_ERR_INVALID_SD_INDEX";
244 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
245 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
246 case I40E_ERR_INVALID_SD_TYPE:
247 return "I40E_ERR_INVALID_SD_TYPE";
248 case I40E_ERR_MEMCPY_FAILED:
249 return "I40E_ERR_MEMCPY_FAILED";
250 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
251 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
252 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
253 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
254 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
255 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
256 case I40E_ERR_SRQ_ENABLED:
257 return "I40E_ERR_SRQ_ENABLED";
258 case I40E_ERR_ADMIN_QUEUE_ERROR:
259 return "I40E_ERR_ADMIN_QUEUE_ERROR";
260 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
261 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
262 case I40E_ERR_BUF_TOO_SHORT:
263 return "I40E_ERR_BUF_TOO_SHORT";
264 case I40E_ERR_ADMIN_QUEUE_FULL:
265 return "I40E_ERR_ADMIN_QUEUE_FULL";
266 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
267 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
268 case I40E_ERR_BAD_IWARP_CQE:
269 return "I40E_ERR_BAD_IWARP_CQE";
270 case I40E_ERR_NVM_BLANK_MODE:
271 return "I40E_ERR_NVM_BLANK_MODE";
272 case I40E_ERR_NOT_IMPLEMENTED:
273 return "I40E_ERR_NOT_IMPLEMENTED";
274 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
275 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
276 case I40E_ERR_DIAG_TEST_FAILED:
277 return "I40E_ERR_DIAG_TEST_FAILED";
278 case I40E_ERR_NOT_READY:
279 return "I40E_ERR_NOT_READY";
280 case I40E_NOT_SUPPORTED:
281 return "I40E_NOT_SUPPORTED";
282 case I40E_ERR_FIRMWARE_API_VERSION:
283 return "I40E_ERR_FIRMWARE_API_VERSION";
284 case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR:
285 return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR";
288 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
294 * @hw: debug mask related to admin queue
296 * @desc: pointer to admin queue descriptor
297 * @buffer: pointer to command buffer
298 * @buf_len: max length of buffer
300 * Dumps debug log about adminq command with descriptor contents.
302 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
303 void *buffer, u16 buf_len)
305 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
306 u32 effective_mask = hw->debug_mask & mask;
307 u8 *buf = (u8 *)buffer;
311 if (!effective_mask || !desc)
314 len = LE16_TO_CPU(aq_desc->datalen);
316 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
317 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
318 LE16_TO_CPU(aq_desc->opcode),
319 LE16_TO_CPU(aq_desc->flags),
320 LE16_TO_CPU(aq_desc->datalen),
321 LE16_TO_CPU(aq_desc->retval));
322 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
323 "\tcookie (h,l) 0x%08X 0x%08X\n",
324 LE32_TO_CPU(aq_desc->cookie_high),
325 LE32_TO_CPU(aq_desc->cookie_low));
326 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
327 "\tparam (0,1) 0x%08X 0x%08X\n",
328 LE32_TO_CPU(aq_desc->params.internal.param0),
329 LE32_TO_CPU(aq_desc->params.internal.param1));
330 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
331 "\taddr (h,l) 0x%08X 0x%08X\n",
332 LE32_TO_CPU(aq_desc->params.external.addr_high),
333 LE32_TO_CPU(aq_desc->params.external.addr_low));
335 if (buffer && (buf_len != 0) && (len != 0) &&
336 (effective_mask & I40E_DEBUG_AQ_DESC_BUFFER)) {
337 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
340 /* write the full 16-byte chunks */
341 for (i = 0; i < (len - 16); i += 16)
343 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
344 i, buf[i], buf[i+1], buf[i+2], buf[i+3],
345 buf[i+4], buf[i+5], buf[i+6], buf[i+7],
346 buf[i+8], buf[i+9], buf[i+10], buf[i+11],
347 buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
348 /* the most we could have left is 16 bytes, pad with zeros */
354 memset(d_buf, 0, sizeof(d_buf));
355 for (j = 0; i < len; j++, i++)
358 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
359 i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
360 d_buf[4], d_buf[5], d_buf[6], d_buf[7],
361 d_buf[8], d_buf[9], d_buf[10], d_buf[11],
362 d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
368 * i40e_check_asq_alive
369 * @hw: pointer to the hw struct
371 * Returns true if Queue is enabled else false.
373 bool i40e_check_asq_alive(struct i40e_hw *hw)
379 return !!(rd32(hw, hw->aq.asq.len) &
380 I40E_PF_ATQLEN_ATQENABLE_MASK);
382 return !!(rd32(hw, hw->aq.asq.len) &
383 I40E_PF_ATQLEN_ATQENABLE_MASK);
384 #endif /* INTEGRATED_VF */
385 #endif /* PF_DRIVER */
389 return !!(rd32(hw, hw->aq.asq.len) &
390 I40E_VF_ATQLEN1_ATQENABLE_MASK);
392 return !!(rd32(hw, hw->aq.asq.len) &
393 I40E_VF_ATQLEN1_ATQENABLE_MASK);
394 #endif /* INTEGRATED_VF */
395 #endif /* VF_DRIVER */
400 * i40e_aq_queue_shutdown
401 * @hw: pointer to the hw struct
402 * @unloading: is the driver unloading itself
404 * Tell the Firmware that we're shutting down the AdminQ and whether
405 * or not the driver is unloading as well.
407 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
410 struct i40e_aq_desc desc;
411 struct i40e_aqc_queue_shutdown *cmd =
412 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
413 enum i40e_status_code status;
415 i40e_fill_default_direct_cmd_desc(&desc,
416 i40e_aqc_opc_queue_shutdown);
419 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
420 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
426 * i40e_aq_get_set_rss_lut
427 * @hw: pointer to the hardware structure
428 * @vsi_id: vsi fw index
429 * @pf_lut: for PF table set true, for VSI table set false
430 * @lut: pointer to the lut buffer provided by the caller
431 * @lut_size: size of the lut buffer
432 * @set: set true to set the table, false to get the table
434 * Internal function to get or set RSS look up table
436 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
437 u16 vsi_id, bool pf_lut,
438 u8 *lut, u16 lut_size,
441 enum i40e_status_code status;
442 struct i40e_aq_desc desc;
443 struct i40e_aqc_get_set_rss_lut *cmd_resp =
444 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
447 i40e_fill_default_direct_cmd_desc(&desc,
448 i40e_aqc_opc_set_rss_lut);
450 i40e_fill_default_direct_cmd_desc(&desc,
451 i40e_aqc_opc_get_rss_lut);
453 /* Indirect command */
454 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
455 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
458 CPU_TO_LE16((u16)((vsi_id <<
459 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
460 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
461 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
464 cmd_resp->flags |= CPU_TO_LE16((u16)
465 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
466 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
467 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
469 cmd_resp->flags |= CPU_TO_LE16((u16)
470 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
471 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
472 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
474 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
480 * i40e_aq_get_rss_lut
481 * @hw: pointer to the hardware structure
482 * @vsi_id: vsi fw index
483 * @pf_lut: for PF table set true, for VSI table set false
484 * @lut: pointer to the lut buffer provided by the caller
485 * @lut_size: size of the lut buffer
487 * get the RSS lookup table, PF or VSI type
489 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
490 bool pf_lut, u8 *lut, u16 lut_size)
492 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
497 * i40e_aq_set_rss_lut
498 * @hw: pointer to the hardware structure
499 * @vsi_id: vsi fw index
500 * @pf_lut: for PF table set true, for VSI table set false
501 * @lut: pointer to the lut buffer provided by the caller
502 * @lut_size: size of the lut buffer
504 * set the RSS lookup table, PF or VSI type
506 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
507 bool pf_lut, u8 *lut, u16 lut_size)
509 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
513 * i40e_aq_get_set_rss_key
514 * @hw: pointer to the hw struct
515 * @vsi_id: vsi fw index
516 * @key: pointer to key info struct
517 * @set: set true to set the key, false to get the key
519 * get the RSS key per VSI
521 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
523 struct i40e_aqc_get_set_rss_key_data *key,
526 enum i40e_status_code status;
527 struct i40e_aq_desc desc;
528 struct i40e_aqc_get_set_rss_key *cmd_resp =
529 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
530 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
533 i40e_fill_default_direct_cmd_desc(&desc,
534 i40e_aqc_opc_set_rss_key);
536 i40e_fill_default_direct_cmd_desc(&desc,
537 i40e_aqc_opc_get_rss_key);
539 /* Indirect command */
540 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
541 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
544 CPU_TO_LE16((u16)((vsi_id <<
545 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
546 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
547 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
549 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
555 * i40e_aq_get_rss_key
556 * @hw: pointer to the hw struct
557 * @vsi_id: vsi fw index
558 * @key: pointer to key info struct
561 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
563 struct i40e_aqc_get_set_rss_key_data *key)
565 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
569 * i40e_aq_set_rss_key
570 * @hw: pointer to the hw struct
571 * @vsi_id: vsi fw index
572 * @key: pointer to key info struct
574 * set the RSS key per VSI
576 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
578 struct i40e_aqc_get_set_rss_key_data *key)
580 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
583 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
584 * hardware to a bit-field that can be used by SW to more easily determine the
587 * Macros are used to shorten the table lines and make this table human
590 * We store the PTYPE in the top byte of the bit field - this is just so that
591 * we can check that the table doesn't have a row missing, as the index into
592 * the table should be the PTYPE.
596 * IF NOT i40e_ptype_lookup[ptype].known
599 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
600 * Use the rest of the fields to look at the tunnels, inner protocols, etc
602 * Use the enum i40e_rx_l2_ptype to decode the packet type
606 /* macro to make the table lines short */
607 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
610 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
611 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
612 I40E_RX_PTYPE_##OUTER_FRAG, \
613 I40E_RX_PTYPE_TUNNEL_##T, \
614 I40E_RX_PTYPE_TUNNEL_END_##TE, \
615 I40E_RX_PTYPE_##TEF, \
616 I40E_RX_PTYPE_INNER_PROT_##I, \
617 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
619 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
620 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
622 /* shorter macros makes the table fit but are terse */
623 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
624 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
625 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
627 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
628 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
629 /* L2 Packet types */
630 I40E_PTT_UNUSED_ENTRY(0),
631 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
632 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
633 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
634 I40E_PTT_UNUSED_ENTRY(4),
635 I40E_PTT_UNUSED_ENTRY(5),
636 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
637 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
638 I40E_PTT_UNUSED_ENTRY(8),
639 I40E_PTT_UNUSED_ENTRY(9),
640 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
641 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
642 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
643 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
644 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
645 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
646 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
647 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
648 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
649 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
650 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
651 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
653 /* Non Tunneled IPv4 */
654 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
655 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
656 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
657 I40E_PTT_UNUSED_ENTRY(25),
658 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
659 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
660 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
663 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
664 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
665 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
666 I40E_PTT_UNUSED_ENTRY(32),
667 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
668 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
669 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
672 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
673 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
674 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
675 I40E_PTT_UNUSED_ENTRY(39),
676 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
677 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
678 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
680 /* IPv4 --> GRE/NAT */
681 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
683 /* IPv4 --> GRE/NAT --> IPv4 */
684 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
685 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
686 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
687 I40E_PTT_UNUSED_ENTRY(47),
688 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
689 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
690 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
692 /* IPv4 --> GRE/NAT --> IPv6 */
693 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
694 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
695 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
696 I40E_PTT_UNUSED_ENTRY(54),
697 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
698 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
699 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
701 /* IPv4 --> GRE/NAT --> MAC */
702 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
704 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
705 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
706 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
707 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
708 I40E_PTT_UNUSED_ENTRY(62),
709 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
710 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
711 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
713 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
714 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
715 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
716 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
717 I40E_PTT_UNUSED_ENTRY(69),
718 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
719 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
720 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
722 /* IPv4 --> GRE/NAT --> MAC/VLAN */
723 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
725 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
726 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
727 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
728 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
729 I40E_PTT_UNUSED_ENTRY(77),
730 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
731 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
732 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
734 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
735 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
736 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
737 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
738 I40E_PTT_UNUSED_ENTRY(84),
739 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
740 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
741 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
743 /* Non Tunneled IPv6 */
744 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
745 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
746 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4),
747 I40E_PTT_UNUSED_ENTRY(91),
748 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
749 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
750 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
753 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
754 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
755 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
756 I40E_PTT_UNUSED_ENTRY(98),
757 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
758 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
759 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
762 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
763 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
764 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
765 I40E_PTT_UNUSED_ENTRY(105),
766 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
767 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
768 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
770 /* IPv6 --> GRE/NAT */
771 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
773 /* IPv6 --> GRE/NAT -> IPv4 */
774 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
775 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
776 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
777 I40E_PTT_UNUSED_ENTRY(113),
778 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
779 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
780 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
782 /* IPv6 --> GRE/NAT -> IPv6 */
783 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
784 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
785 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
786 I40E_PTT_UNUSED_ENTRY(120),
787 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
788 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
789 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
791 /* IPv6 --> GRE/NAT -> MAC */
792 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
794 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
795 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
796 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
797 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
798 I40E_PTT_UNUSED_ENTRY(128),
799 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
800 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
801 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
803 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
804 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
805 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
806 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
807 I40E_PTT_UNUSED_ENTRY(135),
808 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
809 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
810 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
812 /* IPv6 --> GRE/NAT -> MAC/VLAN */
813 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
815 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
816 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
817 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
818 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
819 I40E_PTT_UNUSED_ENTRY(143),
820 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
821 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
822 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
824 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
825 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
826 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
827 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
828 I40E_PTT_UNUSED_ENTRY(150),
829 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
830 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
831 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
834 I40E_PTT_UNUSED_ENTRY(154),
835 I40E_PTT_UNUSED_ENTRY(155),
836 I40E_PTT_UNUSED_ENTRY(156),
837 I40E_PTT_UNUSED_ENTRY(157),
838 I40E_PTT_UNUSED_ENTRY(158),
839 I40E_PTT_UNUSED_ENTRY(159),
841 I40E_PTT_UNUSED_ENTRY(160),
842 I40E_PTT_UNUSED_ENTRY(161),
843 I40E_PTT_UNUSED_ENTRY(162),
844 I40E_PTT_UNUSED_ENTRY(163),
845 I40E_PTT_UNUSED_ENTRY(164),
846 I40E_PTT_UNUSED_ENTRY(165),
847 I40E_PTT_UNUSED_ENTRY(166),
848 I40E_PTT_UNUSED_ENTRY(167),
849 I40E_PTT_UNUSED_ENTRY(168),
850 I40E_PTT_UNUSED_ENTRY(169),
852 I40E_PTT_UNUSED_ENTRY(170),
853 I40E_PTT_UNUSED_ENTRY(171),
854 I40E_PTT_UNUSED_ENTRY(172),
855 I40E_PTT_UNUSED_ENTRY(173),
856 I40E_PTT_UNUSED_ENTRY(174),
857 I40E_PTT_UNUSED_ENTRY(175),
858 I40E_PTT_UNUSED_ENTRY(176),
859 I40E_PTT_UNUSED_ENTRY(177),
860 I40E_PTT_UNUSED_ENTRY(178),
861 I40E_PTT_UNUSED_ENTRY(179),
863 I40E_PTT_UNUSED_ENTRY(180),
864 I40E_PTT_UNUSED_ENTRY(181),
865 I40E_PTT_UNUSED_ENTRY(182),
866 I40E_PTT_UNUSED_ENTRY(183),
867 I40E_PTT_UNUSED_ENTRY(184),
868 I40E_PTT_UNUSED_ENTRY(185),
869 I40E_PTT_UNUSED_ENTRY(186),
870 I40E_PTT_UNUSED_ENTRY(187),
871 I40E_PTT_UNUSED_ENTRY(188),
872 I40E_PTT_UNUSED_ENTRY(189),
874 I40E_PTT_UNUSED_ENTRY(190),
875 I40E_PTT_UNUSED_ENTRY(191),
876 I40E_PTT_UNUSED_ENTRY(192),
877 I40E_PTT_UNUSED_ENTRY(193),
878 I40E_PTT_UNUSED_ENTRY(194),
879 I40E_PTT_UNUSED_ENTRY(195),
880 I40E_PTT_UNUSED_ENTRY(196),
881 I40E_PTT_UNUSED_ENTRY(197),
882 I40E_PTT_UNUSED_ENTRY(198),
883 I40E_PTT_UNUSED_ENTRY(199),
885 I40E_PTT_UNUSED_ENTRY(200),
886 I40E_PTT_UNUSED_ENTRY(201),
887 I40E_PTT_UNUSED_ENTRY(202),
888 I40E_PTT_UNUSED_ENTRY(203),
889 I40E_PTT_UNUSED_ENTRY(204),
890 I40E_PTT_UNUSED_ENTRY(205),
891 I40E_PTT_UNUSED_ENTRY(206),
892 I40E_PTT_UNUSED_ENTRY(207),
893 I40E_PTT_UNUSED_ENTRY(208),
894 I40E_PTT_UNUSED_ENTRY(209),
896 I40E_PTT_UNUSED_ENTRY(210),
897 I40E_PTT_UNUSED_ENTRY(211),
898 I40E_PTT_UNUSED_ENTRY(212),
899 I40E_PTT_UNUSED_ENTRY(213),
900 I40E_PTT_UNUSED_ENTRY(214),
901 I40E_PTT_UNUSED_ENTRY(215),
902 I40E_PTT_UNUSED_ENTRY(216),
903 I40E_PTT_UNUSED_ENTRY(217),
904 I40E_PTT_UNUSED_ENTRY(218),
905 I40E_PTT_UNUSED_ENTRY(219),
907 I40E_PTT_UNUSED_ENTRY(220),
908 I40E_PTT_UNUSED_ENTRY(221),
909 I40E_PTT_UNUSED_ENTRY(222),
910 I40E_PTT_UNUSED_ENTRY(223),
911 I40E_PTT_UNUSED_ENTRY(224),
912 I40E_PTT_UNUSED_ENTRY(225),
913 I40E_PTT_UNUSED_ENTRY(226),
914 I40E_PTT_UNUSED_ENTRY(227),
915 I40E_PTT_UNUSED_ENTRY(228),
916 I40E_PTT_UNUSED_ENTRY(229),
918 I40E_PTT_UNUSED_ENTRY(230),
919 I40E_PTT_UNUSED_ENTRY(231),
920 I40E_PTT_UNUSED_ENTRY(232),
921 I40E_PTT_UNUSED_ENTRY(233),
922 I40E_PTT_UNUSED_ENTRY(234),
923 I40E_PTT_UNUSED_ENTRY(235),
924 I40E_PTT_UNUSED_ENTRY(236),
925 I40E_PTT_UNUSED_ENTRY(237),
926 I40E_PTT_UNUSED_ENTRY(238),
927 I40E_PTT_UNUSED_ENTRY(239),
929 I40E_PTT_UNUSED_ENTRY(240),
930 I40E_PTT_UNUSED_ENTRY(241),
931 I40E_PTT_UNUSED_ENTRY(242),
932 I40E_PTT_UNUSED_ENTRY(243),
933 I40E_PTT_UNUSED_ENTRY(244),
934 I40E_PTT_UNUSED_ENTRY(245),
935 I40E_PTT_UNUSED_ENTRY(246),
936 I40E_PTT_UNUSED_ENTRY(247),
937 I40E_PTT_UNUSED_ENTRY(248),
938 I40E_PTT_UNUSED_ENTRY(249),
940 I40E_PTT_UNUSED_ENTRY(250),
941 I40E_PTT_UNUSED_ENTRY(251),
942 I40E_PTT_UNUSED_ENTRY(252),
943 I40E_PTT_UNUSED_ENTRY(253),
944 I40E_PTT_UNUSED_ENTRY(254),
945 I40E_PTT_UNUSED_ENTRY(255)
950 * i40e_validate_mac_addr - Validate unicast MAC address
951 * @mac_addr: pointer to MAC address
953 * Tests a MAC address to ensure it is a valid Individual Address
955 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
957 enum i40e_status_code status = I40E_SUCCESS;
959 DEBUGFUNC("i40e_validate_mac_addr");
961 /* Broadcast addresses ARE multicast addresses
962 * Make sure it is not a multicast address
963 * Reject the zero address
965 if (I40E_IS_MULTICAST(mac_addr) ||
966 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
967 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
968 status = I40E_ERR_INVALID_MAC_ADDR;
975 * i40e_init_shared_code - Initialize the shared code
976 * @hw: pointer to hardware structure
978 * This assigns the MAC type and PHY code and inits the NVM.
979 * Does not touch the hardware. This function must be called prior to any
980 * other function in the shared code. The i40e_hw structure should be
981 * memset to 0 prior to calling this function. The following fields in
982 * hw structure should be filled in prior to calling this function:
983 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
984 * subsystem_vendor_id, and revision_id
986 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
988 enum i40e_status_code status = I40E_SUCCESS;
989 u32 port, ari, func_rid;
991 DEBUGFUNC("i40e_init_shared_code");
993 i40e_set_mac_type(hw);
995 switch (hw->mac.type) {
1000 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1003 hw->phy.get_link_info = true;
1005 /* Determine port number and PF number*/
1006 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1007 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1008 hw->port = (u8)port;
1009 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1010 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1011 func_rid = rd32(hw, I40E_PF_FUNC_RID);
1013 hw->pf_id = (u8)(func_rid & 0xff);
1015 hw->pf_id = (u8)(func_rid & 0x7);
1017 if (hw->mac.type == I40E_MAC_X722)
1018 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE |
1019 I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK;
1020 /* NVMUpdate features structure initialization */
1021 hw->nvmupd_features.major = I40E_NVMUPD_FEATURES_API_VER_MAJOR;
1022 hw->nvmupd_features.minor = I40E_NVMUPD_FEATURES_API_VER_MINOR;
1023 hw->nvmupd_features.size = sizeof(hw->nvmupd_features);
1024 i40e_memset(hw->nvmupd_features.features, 0x0,
1025 I40E_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN *
1026 sizeof(*hw->nvmupd_features.features),
1029 /* No features supported at the moment */
1030 hw->nvmupd_features.features[0] = 0;
1032 status = i40e_init_nvm(hw);
1037 * i40e_aq_mac_address_read - Retrieve the MAC addresses
1038 * @hw: pointer to the hw struct
1039 * @flags: a return indicator of what addresses were added to the addr store
1040 * @addrs: the requestor's mac addr store
1041 * @cmd_details: pointer to command details structure or NULL
1043 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1045 struct i40e_aqc_mac_address_read_data *addrs,
1046 struct i40e_asq_cmd_details *cmd_details)
1048 struct i40e_aq_desc desc;
1049 struct i40e_aqc_mac_address_read *cmd_data =
1050 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1051 enum i40e_status_code status;
1053 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1054 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1056 status = i40e_asq_send_command(hw, &desc, addrs,
1057 sizeof(*addrs), cmd_details);
1058 *flags = LE16_TO_CPU(cmd_data->command_flags);
1064 * i40e_aq_mac_address_write - Change the MAC addresses
1065 * @hw: pointer to the hw struct
1066 * @flags: indicates which MAC to be written
1067 * @mac_addr: address to write
1068 * @cmd_details: pointer to command details structure or NULL
1070 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1071 u16 flags, u8 *mac_addr,
1072 struct i40e_asq_cmd_details *cmd_details)
1074 struct i40e_aq_desc desc;
1075 struct i40e_aqc_mac_address_write *cmd_data =
1076 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1077 enum i40e_status_code status;
1079 i40e_fill_default_direct_cmd_desc(&desc,
1080 i40e_aqc_opc_mac_address_write);
1081 cmd_data->command_flags = CPU_TO_LE16(flags);
1082 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1083 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1084 ((u32)mac_addr[3] << 16) |
1085 ((u32)mac_addr[4] << 8) |
1088 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1094 * i40e_get_mac_addr - get MAC address
1095 * @hw: pointer to the HW structure
1096 * @mac_addr: pointer to MAC address
1098 * Reads the adapter's MAC address from register
1100 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1102 struct i40e_aqc_mac_address_read_data addrs;
1103 enum i40e_status_code status;
1106 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1108 if (flags & I40E_AQC_LAN_ADDR_VALID)
1109 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1110 I40E_NONDMA_TO_NONDMA);
1116 * i40e_get_port_mac_addr - get Port MAC address
1117 * @hw: pointer to the HW structure
1118 * @mac_addr: pointer to Port MAC address
1120 * Reads the adapter's Port MAC address
1122 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1124 struct i40e_aqc_mac_address_read_data addrs;
1125 enum i40e_status_code status;
1128 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1132 if (flags & I40E_AQC_PORT_ADDR_VALID)
1133 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1134 I40E_NONDMA_TO_NONDMA);
1136 status = I40E_ERR_INVALID_MAC_ADDR;
1142 * i40e_pre_tx_queue_cfg - pre tx queue configure
1143 * @hw: pointer to the HW structure
1144 * @queue: target pf queue index
1145 * @enable: state change request
1147 * Handles hw requirement to indicate intention to enable
1148 * or disable target queue.
1150 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1152 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1156 if (abs_queue_idx >= 128) {
1157 reg_block = abs_queue_idx / 128;
1158 abs_queue_idx %= 128;
1161 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1162 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1163 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1166 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1168 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1170 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1174 * i40e_get_san_mac_addr - get SAN MAC address
1175 * @hw: pointer to the HW structure
1176 * @mac_addr: pointer to SAN MAC address
1178 * Reads the adapter's SAN MAC address from NVM
1180 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1183 struct i40e_aqc_mac_address_read_data addrs;
1184 enum i40e_status_code status;
1187 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1191 if (flags & I40E_AQC_SAN_ADDR_VALID)
1192 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac),
1193 I40E_NONDMA_TO_NONDMA);
1195 status = I40E_ERR_INVALID_MAC_ADDR;
1201 * i40e_read_pba_string - Reads part number string from EEPROM
1202 * @hw: pointer to hardware structure
1203 * @pba_num: stores the part number string from the EEPROM
1204 * @pba_num_size: part number string buffer length
1206 * Reads the part number string from the EEPROM.
1208 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1211 enum i40e_status_code status = I40E_SUCCESS;
1217 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1218 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1219 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1223 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1224 if (status != I40E_SUCCESS) {
1225 DEBUGOUT("Failed to read PBA Block pointer.\n");
1229 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1230 if (status != I40E_SUCCESS) {
1231 DEBUGOUT("Failed to read PBA Block size.\n");
1235 /* Subtract one to get PBA word count (PBA Size word is included in
1239 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1240 DEBUGOUT("Buffer to small for PBA data.\n");
1241 return I40E_ERR_PARAM;
1244 for (i = 0; i < pba_size; i++) {
1245 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1246 if (status != I40E_SUCCESS) {
1247 DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1251 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1252 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1254 pba_num[(pba_size * 2)] = '\0';
1260 * i40e_get_media_type - Gets media type
1261 * @hw: pointer to the hardware structure
1263 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1265 enum i40e_media_type media;
1267 switch (hw->phy.link_info.phy_type) {
1268 case I40E_PHY_TYPE_10GBASE_SR:
1269 case I40E_PHY_TYPE_10GBASE_LR:
1270 case I40E_PHY_TYPE_1000BASE_SX:
1271 case I40E_PHY_TYPE_1000BASE_LX:
1272 case I40E_PHY_TYPE_40GBASE_SR4:
1273 case I40E_PHY_TYPE_40GBASE_LR4:
1274 case I40E_PHY_TYPE_25GBASE_LR:
1275 case I40E_PHY_TYPE_25GBASE_SR:
1276 media = I40E_MEDIA_TYPE_FIBER;
1278 case I40E_PHY_TYPE_100BASE_TX:
1279 case I40E_PHY_TYPE_1000BASE_T:
1280 case I40E_PHY_TYPE_2_5GBASE_T:
1281 case I40E_PHY_TYPE_5GBASE_T:
1282 case I40E_PHY_TYPE_10GBASE_T:
1283 media = I40E_MEDIA_TYPE_BASET;
1285 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1286 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1287 case I40E_PHY_TYPE_10GBASE_CR1:
1288 case I40E_PHY_TYPE_40GBASE_CR4:
1289 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1290 case I40E_PHY_TYPE_40GBASE_AOC:
1291 case I40E_PHY_TYPE_10GBASE_AOC:
1292 case I40E_PHY_TYPE_25GBASE_CR:
1293 case I40E_PHY_TYPE_25GBASE_AOC:
1294 case I40E_PHY_TYPE_25GBASE_ACC:
1295 media = I40E_MEDIA_TYPE_DA;
1297 case I40E_PHY_TYPE_1000BASE_KX:
1298 case I40E_PHY_TYPE_10GBASE_KX4:
1299 case I40E_PHY_TYPE_10GBASE_KR:
1300 case I40E_PHY_TYPE_40GBASE_KR4:
1301 case I40E_PHY_TYPE_20GBASE_KR2:
1302 case I40E_PHY_TYPE_25GBASE_KR:
1303 media = I40E_MEDIA_TYPE_BACKPLANE;
1305 case I40E_PHY_TYPE_SGMII:
1306 case I40E_PHY_TYPE_XAUI:
1307 case I40E_PHY_TYPE_XFI:
1308 case I40E_PHY_TYPE_XLAUI:
1309 case I40E_PHY_TYPE_XLPPI:
1311 media = I40E_MEDIA_TYPE_UNKNOWN;
1319 * i40e_poll_globr - Poll for Global Reset completion
1320 * @hw: pointer to the hardware structure
1321 * @retry_limit: how many times to retry before failure
1323 STATIC enum i40e_status_code i40e_poll_globr(struct i40e_hw *hw,
1328 for (cnt = 0; cnt < retry_limit; cnt++) {
1329 reg = rd32(hw, I40E_GLGEN_RSTAT);
1330 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1331 return I40E_SUCCESS;
1332 i40e_msec_delay(100);
1335 DEBUGOUT("Global reset failed.\n");
1336 DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg);
1338 return I40E_ERR_RESET_FAILED;
1341 #define I40E_PF_RESET_WAIT_COUNT 200
1343 * i40e_pf_reset - Reset the PF
1344 * @hw: pointer to the hardware structure
1346 * Assuming someone else has triggered a global reset,
1347 * assure the global reset is complete and then reset the PF
1349 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1356 /* Poll for Global Reset steady state in case of recent GRST.
1357 * The grst delay value is in 100ms units, and we'll wait a
1358 * couple counts longer to be sure we don't just miss the end.
1360 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1361 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1362 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1364 grst_del = min(grst_del * 20, 160U);
1366 for (cnt = 0; cnt < grst_del; cnt++) {
1367 reg = rd32(hw, I40E_GLGEN_RSTAT);
1368 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1370 i40e_msec_delay(100);
1372 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1373 DEBUGOUT("Global reset polling failed to complete.\n");
1374 return I40E_ERR_RESET_FAILED;
1377 /* Now Wait for the FW to be ready */
1378 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1379 reg = rd32(hw, I40E_GLNVM_ULD);
1380 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1381 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1382 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1383 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1384 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1387 i40e_msec_delay(10);
1389 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1390 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1391 DEBUGOUT("wait for FW Reset complete timedout\n");
1392 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1393 return I40E_ERR_RESET_FAILED;
1396 /* If there was a Global Reset in progress when we got here,
1397 * we don't need to do the PF Reset
1402 reg = rd32(hw, I40E_PFGEN_CTRL);
1403 wr32(hw, I40E_PFGEN_CTRL,
1404 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1405 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1406 reg = rd32(hw, I40E_PFGEN_CTRL);
1407 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1409 reg2 = rd32(hw, I40E_GLGEN_RSTAT);
1410 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK)
1414 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1415 if (i40e_poll_globr(hw, grst_del) != I40E_SUCCESS)
1416 return I40E_ERR_RESET_FAILED;
1417 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1418 DEBUGOUT("PF reset polling failed to complete.\n");
1419 return I40E_ERR_RESET_FAILED;
1423 i40e_clear_pxe_mode(hw);
1426 return I40E_SUCCESS;
1430 * i40e_clear_hw - clear out any left over hw state
1431 * @hw: pointer to the hw struct
1433 * Clear queues and interrupts, typically called at init time,
1434 * but after the capabilities have been found so we know how many
1435 * queues and msix vectors have been allocated.
1437 void i40e_clear_hw(struct i40e_hw *hw)
1439 u32 num_queues, base_queue;
1447 /* get number of interrupts, queues, and vfs */
1448 val = rd32(hw, I40E_GLPCI_CNF2);
1449 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1450 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1451 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1452 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1454 val = rd32(hw, I40E_PFLAN_QALLOC);
1455 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1456 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1457 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1458 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1459 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1460 num_queues = (j - base_queue) + 1;
1464 val = rd32(hw, I40E_PF_VT_PFALLOC);
1465 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1466 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1467 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1468 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1469 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1470 num_vfs = (j - i) + 1;
1474 /* stop all the interrupts */
1475 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1476 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1477 for (i = 0; i < num_pf_int - 2; i++)
1478 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1480 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1481 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1482 wr32(hw, I40E_PFINT_LNKLST0, val);
1483 for (i = 0; i < num_pf_int - 2; i++)
1484 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1485 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1486 for (i = 0; i < num_vfs; i++)
1487 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1488 for (i = 0; i < num_vf_int - 2; i++)
1489 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1491 /* warn the HW of the coming Tx disables */
1492 for (i = 0; i < num_queues; i++) {
1493 u32 abs_queue_idx = base_queue + i;
1496 if (abs_queue_idx >= 128) {
1497 reg_block = abs_queue_idx / 128;
1498 abs_queue_idx %= 128;
1501 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1502 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1503 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1504 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1506 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1508 i40e_usec_delay(400);
1510 /* stop all the queues */
1511 for (i = 0; i < num_queues; i++) {
1512 wr32(hw, I40E_QINT_TQCTL(i), 0);
1513 wr32(hw, I40E_QTX_ENA(i), 0);
1514 wr32(hw, I40E_QINT_RQCTL(i), 0);
1515 wr32(hw, I40E_QRX_ENA(i), 0);
1518 /* short wait for all queue disables to settle */
1519 i40e_usec_delay(50);
1523 * i40e_clear_pxe_mode - clear pxe operations mode
1524 * @hw: pointer to the hw struct
1526 * Make sure all PXE mode settings are cleared, including things
1527 * like descriptor fetch/write-back mode.
1529 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1531 if (i40e_check_asq_alive(hw))
1532 i40e_aq_clear_pxe_mode(hw, NULL);
1536 * i40e_led_is_mine - helper to find matching led
1537 * @hw: pointer to the hw struct
1538 * @idx: index into GPIO registers
1540 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1542 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1547 if (!hw->func_caps.led[idx])
1550 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1551 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1552 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1554 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1555 * if it is not our port then ignore
1557 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1564 #define I40E_COMBINED_ACTIVITY 0xA
1565 #define I40E_FILTER_ACTIVITY 0xE
1566 #define I40E_LINK_ACTIVITY 0xC
1567 #define I40E_MAC_ACTIVITY 0xD
1568 #define I40E_LED0 22
1571 * i40e_led_get - return current on/off mode
1572 * @hw: pointer to the hw struct
1574 * The value returned is the 'mode' field as defined in the
1575 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1576 * values are variations of possible behaviors relating to
1577 * blink, link, and wire.
1579 u32 i40e_led_get(struct i40e_hw *hw)
1581 u32 current_mode = 0;
1585 /* as per the documentation GPIO 22-29 are the LED
1586 * GPIO pins named LED0..LED7
1588 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1589 u32 gpio_val = i40e_led_is_mine(hw, i);
1594 /* ignore gpio LED src mode entries related to the activity
1597 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1598 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1599 switch (current_mode) {
1600 case I40E_COMBINED_ACTIVITY:
1601 case I40E_FILTER_ACTIVITY:
1602 case I40E_MAC_ACTIVITY:
1603 case I40E_LINK_ACTIVITY:
1609 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1610 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1618 * i40e_led_set - set new on/off mode
1619 * @hw: pointer to the hw struct
1620 * @mode: 0=off, 0xf=on (else see manual for mode details)
1621 * @blink: true if the LED should blink when on, false if steady
1623 * if this function is used to turn on the blink it should
1624 * be used to disable the blink when restoring the original state.
1626 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1628 u32 current_mode = 0;
1631 if (mode & 0xfffffff0)
1632 DEBUGOUT1("invalid mode passed in %X\n", mode);
1634 /* as per the documentation GPIO 22-29 are the LED
1635 * GPIO pins named LED0..LED7
1637 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1638 u32 gpio_val = i40e_led_is_mine(hw, i);
1643 /* ignore gpio LED src mode entries related to the activity
1646 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1647 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1648 switch (current_mode) {
1649 case I40E_COMBINED_ACTIVITY:
1650 case I40E_FILTER_ACTIVITY:
1651 case I40E_MAC_ACTIVITY:
1652 case I40E_LINK_ACTIVITY:
1658 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1659 /* this & is a bit of paranoia, but serves as a range check */
1660 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1661 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1664 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1666 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1668 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1673 /* Admin command wrappers */
1676 * i40e_aq_get_phy_capabilities
1677 * @hw: pointer to the hw struct
1678 * @abilities: structure for PHY capabilities to be filled
1679 * @qualified_modules: report Qualified Modules
1680 * @report_init: report init capabilities (active are default)
1681 * @cmd_details: pointer to command details structure or NULL
1683 * Returns the various PHY abilities supported on the Port.
1685 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1686 bool qualified_modules, bool report_init,
1687 struct i40e_aq_get_phy_abilities_resp *abilities,
1688 struct i40e_asq_cmd_details *cmd_details)
1690 struct i40e_aq_desc desc;
1691 enum i40e_status_code status;
1692 u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0;
1693 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1696 return I40E_ERR_PARAM;
1699 i40e_fill_default_direct_cmd_desc(&desc,
1700 i40e_aqc_opc_get_phy_abilities);
1702 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1703 if (abilities_size > I40E_AQ_LARGE_BUF)
1704 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1706 if (qualified_modules)
1707 desc.params.external.param0 |=
1708 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1711 desc.params.external.param0 |=
1712 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1714 status = i40e_asq_send_command(hw, &desc, abilities,
1715 abilities_size, cmd_details);
1717 switch (hw->aq.asq_last_status) {
1718 case I40E_AQ_RC_EIO:
1719 status = I40E_ERR_UNKNOWN_PHY;
1721 case I40E_AQ_RC_EAGAIN:
1724 status = I40E_ERR_TIMEOUT;
1726 /* also covers I40E_AQ_RC_OK */
1731 } while ((hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) &&
1732 (total_delay < max_delay));
1734 if (status != I40E_SUCCESS)
1738 if (hw->mac.type == I40E_MAC_XL710 &&
1739 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1740 hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
1741 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1743 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1744 hw->phy.phy_types |=
1745 ((u64)abilities->phy_type_ext << 32);
1753 * i40e_aq_set_phy_config
1754 * @hw: pointer to the hw struct
1755 * @config: structure with PHY configuration to be set
1756 * @cmd_details: pointer to command details structure or NULL
1758 * Set the various PHY configuration parameters
1759 * supported on the Port.One or more of the Set PHY config parameters may be
1760 * ignored in an MFP mode as the PF may not have the privilege to set some
1761 * of the PHY Config parameters. This status will be indicated by the
1764 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1765 struct i40e_aq_set_phy_config *config,
1766 struct i40e_asq_cmd_details *cmd_details)
1768 struct i40e_aq_desc desc;
1769 struct i40e_aq_set_phy_config *cmd =
1770 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1771 enum i40e_status_code status;
1774 return I40E_ERR_PARAM;
1776 i40e_fill_default_direct_cmd_desc(&desc,
1777 i40e_aqc_opc_set_phy_config);
1781 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1788 * @hw: pointer to the hw struct
1789 * @aq_failures: buffer to return AdminQ failure information
1790 * @atomic_restart: whether to enable atomic link restart
1792 * Set the requested flow control mode using set_phy_config.
1794 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1795 bool atomic_restart)
1797 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1798 struct i40e_aq_get_phy_abilities_resp abilities;
1799 struct i40e_aq_set_phy_config config;
1800 enum i40e_status_code status;
1801 u8 pause_mask = 0x0;
1807 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1808 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1810 case I40E_FC_RX_PAUSE:
1811 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1813 case I40E_FC_TX_PAUSE:
1814 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1820 /* Get the current phy config */
1821 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1824 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1828 memset(&config, 0, sizeof(config));
1829 /* clear the old pause settings */
1830 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1831 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1832 /* set the new abilities */
1833 config.abilities |= pause_mask;
1834 /* If the abilities have changed, then set the new config */
1835 if (config.abilities != abilities.abilities) {
1836 /* Auto restart link so settings take effect */
1838 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1839 /* Copy over all the old settings */
1840 config.phy_type = abilities.phy_type;
1841 config.phy_type_ext = abilities.phy_type_ext;
1842 config.link_speed = abilities.link_speed;
1843 config.eee_capability = abilities.eee_capability;
1844 config.eeer = abilities.eeer_val;
1845 config.low_power_ctrl = abilities.d3_lpan;
1846 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1847 I40E_AQ_PHY_FEC_CONFIG_MASK;
1848 status = i40e_aq_set_phy_config(hw, &config, NULL);
1851 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1853 /* Update the link info */
1854 status = i40e_update_link_info(hw);
1856 /* Wait a little bit (on 40G cards it sometimes takes a really
1857 * long time for link to come back from the atomic reset)
1860 i40e_msec_delay(1000);
1861 status = i40e_update_link_info(hw);
1864 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1870 * i40e_aq_set_mac_config
1871 * @hw: pointer to the hw struct
1872 * @max_frame_size: Maximum Frame Size to be supported by the port
1873 * @crc_en: Tell HW to append a CRC to outgoing frames
1874 * @pacing: Pacing configurations
1875 * @auto_drop_blocking_packets: Tell HW to drop packets if TC queue is blocked
1876 * @cmd_details: pointer to command details structure or NULL
1878 * Configure MAC settings for frame size, jumbo frame support and the
1879 * addition of a CRC by the hardware.
1881 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1883 bool crc_en, u16 pacing,
1884 bool auto_drop_blocking_packets,
1885 struct i40e_asq_cmd_details *cmd_details)
1887 struct i40e_aq_desc desc;
1888 struct i40e_aq_set_mac_config *cmd =
1889 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1890 enum i40e_status_code status;
1892 if (max_frame_size == 0)
1893 return I40E_ERR_PARAM;
1895 i40e_fill_default_direct_cmd_desc(&desc,
1896 i40e_aqc_opc_set_mac_config);
1898 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1899 cmd->params = ((u8)pacing & 0x0F) << 3;
1901 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1903 if (auto_drop_blocking_packets) {
1904 if (hw->flags & I40E_HW_FLAG_DROP_MODE)
1906 I40E_AQ_SET_MAC_CONFIG_DROP_BLOCKING_PACKET_EN;
1908 i40e_debug(hw, I40E_DEBUG_ALL,
1909 "This FW api version does not support drop mode.\n");
1912 #define I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD 0x7FFF
1913 cmd->fc_refresh_threshold =
1914 CPU_TO_LE16(I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD);
1916 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1922 * i40e_aq_clear_pxe_mode
1923 * @hw: pointer to the hw struct
1924 * @cmd_details: pointer to command details structure or NULL
1926 * Tell the firmware that the driver is taking over from PXE
1928 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1929 struct i40e_asq_cmd_details *cmd_details)
1931 enum i40e_status_code status;
1932 struct i40e_aq_desc desc;
1933 struct i40e_aqc_clear_pxe *cmd =
1934 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1936 i40e_fill_default_direct_cmd_desc(&desc,
1937 i40e_aqc_opc_clear_pxe_mode);
1941 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1943 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1949 * i40e_aq_set_link_restart_an
1950 * @hw: pointer to the hw struct
1951 * @enable_link: if true: enable link, if false: disable link
1952 * @cmd_details: pointer to command details structure or NULL
1954 * Sets up the link and restarts the Auto-Negotiation over the link.
1956 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1957 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1959 struct i40e_aq_desc desc;
1960 struct i40e_aqc_set_link_restart_an *cmd =
1961 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1962 enum i40e_status_code status;
1964 i40e_fill_default_direct_cmd_desc(&desc,
1965 i40e_aqc_opc_set_link_restart_an);
1967 cmd->command = I40E_AQ_PHY_RESTART_AN;
1969 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1971 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1973 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1979 * i40e_aq_get_link_info
1980 * @hw: pointer to the hw struct
1981 * @enable_lse: enable/disable LinkStatusEvent reporting
1982 * @link: pointer to link status structure - optional
1983 * @cmd_details: pointer to command details structure or NULL
1985 * Returns the link status of the adapter.
1987 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1988 bool enable_lse, struct i40e_link_status *link,
1989 struct i40e_asq_cmd_details *cmd_details)
1991 struct i40e_aq_desc desc;
1992 struct i40e_aqc_get_link_status *resp =
1993 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1994 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1995 enum i40e_status_code status;
1996 bool tx_pause, rx_pause;
1999 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
2002 command_flags = I40E_AQ_LSE_ENABLE;
2004 command_flags = I40E_AQ_LSE_DISABLE;
2005 resp->command_flags = CPU_TO_LE16(command_flags);
2007 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2009 if (status != I40E_SUCCESS)
2010 goto aq_get_link_info_exit;
2012 /* save off old link status information */
2013 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
2014 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
2016 /* update link status */
2017 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
2018 hw->phy.media_type = i40e_get_media_type(hw);
2019 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
2020 hw_link_info->link_info = resp->link_info;
2021 hw_link_info->an_info = resp->an_info;
2022 hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
2023 I40E_AQ_CONFIG_FEC_RS_ENA);
2024 hw_link_info->ext_info = resp->ext_info;
2025 hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
2026 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
2027 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
2029 /* update fc info */
2030 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
2031 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
2032 if (tx_pause & rx_pause)
2033 hw->fc.current_mode = I40E_FC_FULL;
2035 hw->fc.current_mode = I40E_FC_TX_PAUSE;
2037 hw->fc.current_mode = I40E_FC_RX_PAUSE;
2039 hw->fc.current_mode = I40E_FC_NONE;
2041 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
2042 hw_link_info->crc_enable = true;
2044 hw_link_info->crc_enable = false;
2046 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
2047 hw_link_info->lse_enable = true;
2049 hw_link_info->lse_enable = false;
2051 if ((hw->mac.type == I40E_MAC_XL710) &&
2052 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
2053 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
2054 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
2056 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE &&
2057 hw->mac.type != I40E_MAC_X722) {
2060 i40e_memcpy(&tmp, resp->link_type, sizeof(tmp),
2061 I40E_NONDMA_TO_NONDMA);
2062 hw->phy.phy_types = LE32_TO_CPU(tmp);
2063 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
2066 /* save link status information */
2068 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
2069 I40E_NONDMA_TO_NONDMA);
2071 /* flag cleared so helper functions don't call AQ again */
2072 hw->phy.get_link_info = false;
2074 aq_get_link_info_exit:
2079 * i40e_aq_set_phy_int_mask
2080 * @hw: pointer to the hw struct
2081 * @mask: interrupt mask to be set
2082 * @cmd_details: pointer to command details structure or NULL
2084 * Set link interrupt mask.
2086 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2088 struct i40e_asq_cmd_details *cmd_details)
2090 struct i40e_aq_desc desc;
2091 struct i40e_aqc_set_phy_int_mask *cmd =
2092 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2093 enum i40e_status_code status;
2095 i40e_fill_default_direct_cmd_desc(&desc,
2096 i40e_aqc_opc_set_phy_int_mask);
2098 cmd->event_mask = CPU_TO_LE16(mask);
2100 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2106 * i40e_aq_get_local_advt_reg
2107 * @hw: pointer to the hw struct
2108 * @advt_reg: local AN advertisement register value
2109 * @cmd_details: pointer to command details structure or NULL
2111 * Get the Local AN advertisement register value.
2113 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2115 struct i40e_asq_cmd_details *cmd_details)
2117 struct i40e_aq_desc desc;
2118 struct i40e_aqc_an_advt_reg *resp =
2119 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2120 enum i40e_status_code status;
2122 i40e_fill_default_direct_cmd_desc(&desc,
2123 i40e_aqc_opc_get_local_advt_reg);
2125 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2127 if (status != I40E_SUCCESS)
2128 goto aq_get_local_advt_reg_exit;
2130 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2131 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2133 aq_get_local_advt_reg_exit:
2138 * i40e_aq_set_local_advt_reg
2139 * @hw: pointer to the hw struct
2140 * @advt_reg: local AN advertisement register value
2141 * @cmd_details: pointer to command details structure or NULL
2143 * Get the Local AN advertisement register value.
2145 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2147 struct i40e_asq_cmd_details *cmd_details)
2149 struct i40e_aq_desc desc;
2150 struct i40e_aqc_an_advt_reg *cmd =
2151 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2152 enum i40e_status_code status;
2154 i40e_fill_default_direct_cmd_desc(&desc,
2155 i40e_aqc_opc_get_local_advt_reg);
2157 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2158 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2160 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2166 * i40e_aq_get_partner_advt
2167 * @hw: pointer to the hw struct
2168 * @advt_reg: AN partner advertisement register value
2169 * @cmd_details: pointer to command details structure or NULL
2171 * Get the link partner AN advertisement register value.
2173 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2175 struct i40e_asq_cmd_details *cmd_details)
2177 struct i40e_aq_desc desc;
2178 struct i40e_aqc_an_advt_reg *resp =
2179 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2180 enum i40e_status_code status;
2182 i40e_fill_default_direct_cmd_desc(&desc,
2183 i40e_aqc_opc_get_partner_advt);
2185 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2187 if (status != I40E_SUCCESS)
2188 goto aq_get_partner_advt_exit;
2190 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2191 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2193 aq_get_partner_advt_exit:
2198 * i40e_aq_set_lb_modes
2199 * @hw: pointer to the hw struct
2200 * @lb_modes: loopback mode to be set
2201 * @cmd_details: pointer to command details structure or NULL
2203 * Sets loopback modes.
2205 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2207 struct i40e_asq_cmd_details *cmd_details)
2209 struct i40e_aq_desc desc;
2210 struct i40e_aqc_set_lb_mode *cmd =
2211 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2212 enum i40e_status_code status;
2214 i40e_fill_default_direct_cmd_desc(&desc,
2215 i40e_aqc_opc_set_lb_modes);
2217 cmd->lb_mode = CPU_TO_LE16(lb_modes);
2219 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2225 * i40e_aq_set_phy_debug
2226 * @hw: pointer to the hw struct
2227 * @cmd_flags: debug command flags
2228 * @cmd_details: pointer to command details structure or NULL
2230 * Reset the external PHY.
2232 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2233 struct i40e_asq_cmd_details *cmd_details)
2235 struct i40e_aq_desc desc;
2236 struct i40e_aqc_set_phy_debug *cmd =
2237 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2238 enum i40e_status_code status;
2240 i40e_fill_default_direct_cmd_desc(&desc,
2241 i40e_aqc_opc_set_phy_debug);
2243 cmd->command_flags = cmd_flags;
2245 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2252 * @hw: pointer to the hw struct
2253 * @vsi_ctx: pointer to a vsi context struct
2254 * @cmd_details: pointer to command details structure or NULL
2256 * Add a VSI context to the hardware.
2258 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2259 struct i40e_vsi_context *vsi_ctx,
2260 struct i40e_asq_cmd_details *cmd_details)
2262 struct i40e_aq_desc desc;
2263 struct i40e_aqc_add_get_update_vsi *cmd =
2264 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2265 struct i40e_aqc_add_get_update_vsi_completion *resp =
2266 (struct i40e_aqc_add_get_update_vsi_completion *)
2268 enum i40e_status_code status;
2270 i40e_fill_default_direct_cmd_desc(&desc,
2271 i40e_aqc_opc_add_vsi);
2273 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2274 cmd->connection_type = vsi_ctx->connection_type;
2275 cmd->vf_id = vsi_ctx->vf_num;
2276 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2278 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2280 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2281 sizeof(vsi_ctx->info), cmd_details);
2283 if (status != I40E_SUCCESS)
2284 goto aq_add_vsi_exit;
2286 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2287 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2288 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2289 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2296 * i40e_aq_set_default_vsi
2297 * @hw: pointer to the hw struct
2299 * @cmd_details: pointer to command details structure or NULL
2301 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2303 struct i40e_asq_cmd_details *cmd_details)
2305 struct i40e_aq_desc desc;
2306 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2307 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2309 enum i40e_status_code status;
2311 i40e_fill_default_direct_cmd_desc(&desc,
2312 i40e_aqc_opc_set_vsi_promiscuous_modes);
2314 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2315 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2316 cmd->seid = CPU_TO_LE16(seid);
2318 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2324 * i40e_aq_clear_default_vsi
2325 * @hw: pointer to the hw struct
2327 * @cmd_details: pointer to command details structure or NULL
2329 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2331 struct i40e_asq_cmd_details *cmd_details)
2333 struct i40e_aq_desc desc;
2334 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2335 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2337 enum i40e_status_code status;
2339 i40e_fill_default_direct_cmd_desc(&desc,
2340 i40e_aqc_opc_set_vsi_promiscuous_modes);
2342 cmd->promiscuous_flags = CPU_TO_LE16(0);
2343 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2344 cmd->seid = CPU_TO_LE16(seid);
2346 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2352 * i40e_aq_set_vsi_unicast_promiscuous
2353 * @hw: pointer to the hw struct
2355 * @set: set unicast promiscuous enable/disable
2356 * @cmd_details: pointer to command details structure or NULL
2357 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2359 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2361 struct i40e_asq_cmd_details *cmd_details,
2362 bool rx_only_promisc)
2364 struct i40e_aq_desc desc;
2365 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2366 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2367 enum i40e_status_code status;
2370 i40e_fill_default_direct_cmd_desc(&desc,
2371 i40e_aqc_opc_set_vsi_promiscuous_modes);
2374 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2375 if (rx_only_promisc &&
2376 (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2377 (hw->aq.api_maj_ver > 1)))
2378 flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2381 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2383 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2384 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2385 (hw->aq.api_maj_ver > 1))
2386 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2388 cmd->seid = CPU_TO_LE16(seid);
2389 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2395 * i40e_aq_set_vsi_multicast_promiscuous
2396 * @hw: pointer to the hw struct
2398 * @set: set multicast promiscuous enable/disable
2399 * @cmd_details: pointer to command details structure or NULL
2401 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2402 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2404 struct i40e_aq_desc desc;
2405 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2406 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2407 enum i40e_status_code status;
2410 i40e_fill_default_direct_cmd_desc(&desc,
2411 i40e_aqc_opc_set_vsi_promiscuous_modes);
2414 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2416 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2418 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2420 cmd->seid = CPU_TO_LE16(seid);
2421 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2427 * i40e_aq_set_vsi_full_promiscuous
2428 * @hw: pointer to the hw struct
2430 * @set: set promiscuous enable/disable
2431 * @cmd_details: pointer to command details structure or NULL
2433 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw,
2435 struct i40e_asq_cmd_details *cmd_details)
2437 struct i40e_aq_desc desc;
2438 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2439 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2440 enum i40e_status_code status;
2443 i40e_fill_default_direct_cmd_desc(&desc,
2444 i40e_aqc_opc_set_vsi_promiscuous_modes);
2447 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST |
2448 I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2449 I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2451 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2453 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST |
2454 I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2455 I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2457 cmd->seid = CPU_TO_LE16(seid);
2458 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2464 * i40e_aq_set_vsi_mc_promisc_on_vlan
2465 * @hw: pointer to the hw struct
2467 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2468 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2469 * @cmd_details: pointer to command details structure or NULL
2471 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2472 u16 seid, bool enable, u16 vid,
2473 struct i40e_asq_cmd_details *cmd_details)
2475 struct i40e_aq_desc desc;
2476 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2477 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2478 enum i40e_status_code status;
2481 i40e_fill_default_direct_cmd_desc(&desc,
2482 i40e_aqc_opc_set_vsi_promiscuous_modes);
2485 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2487 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2488 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2489 cmd->seid = CPU_TO_LE16(seid);
2490 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2492 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2498 * i40e_aq_set_vsi_uc_promisc_on_vlan
2499 * @hw: pointer to the hw struct
2501 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2502 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2503 * @cmd_details: pointer to command details structure or NULL
2505 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2506 u16 seid, bool enable, u16 vid,
2507 struct i40e_asq_cmd_details *cmd_details)
2509 struct i40e_aq_desc desc;
2510 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2511 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2512 enum i40e_status_code status;
2515 i40e_fill_default_direct_cmd_desc(&desc,
2516 i40e_aqc_opc_set_vsi_promiscuous_modes);
2519 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2521 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2522 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2523 cmd->seid = CPU_TO_LE16(seid);
2524 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2526 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2532 * i40e_aq_set_vsi_bc_promisc_on_vlan
2533 * @hw: pointer to the hw struct
2535 * @enable: set broadcast promiscuous enable/disable for a given VLAN
2536 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2537 * @cmd_details: pointer to command details structure or NULL
2539 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2540 u16 seid, bool enable, u16 vid,
2541 struct i40e_asq_cmd_details *cmd_details)
2543 struct i40e_aq_desc desc;
2544 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2545 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2546 enum i40e_status_code status;
2549 i40e_fill_default_direct_cmd_desc(&desc,
2550 i40e_aqc_opc_set_vsi_promiscuous_modes);
2553 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2555 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2556 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2557 cmd->seid = CPU_TO_LE16(seid);
2558 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2560 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2566 * i40e_aq_set_vsi_broadcast
2567 * @hw: pointer to the hw struct
2569 * @set_filter: true to set filter, false to clear filter
2570 * @cmd_details: pointer to command details structure or NULL
2572 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2574 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2575 u16 seid, bool set_filter,
2576 struct i40e_asq_cmd_details *cmd_details)
2578 struct i40e_aq_desc desc;
2579 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2580 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2581 enum i40e_status_code status;
2583 i40e_fill_default_direct_cmd_desc(&desc,
2584 i40e_aqc_opc_set_vsi_promiscuous_modes);
2587 cmd->promiscuous_flags
2588 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2590 cmd->promiscuous_flags
2591 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2593 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2594 cmd->seid = CPU_TO_LE16(seid);
2595 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2601 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2602 * @hw: pointer to the hw struct
2604 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2605 * @cmd_details: pointer to command details structure or NULL
2607 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2608 u16 seid, bool enable,
2609 struct i40e_asq_cmd_details *cmd_details)
2611 struct i40e_aq_desc desc;
2612 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2613 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2614 enum i40e_status_code status;
2617 i40e_fill_default_direct_cmd_desc(&desc,
2618 i40e_aqc_opc_set_vsi_promiscuous_modes);
2620 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2622 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2623 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2624 cmd->seid = CPU_TO_LE16(seid);
2626 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2632 * i40e_get_vsi_params - get VSI configuration info
2633 * @hw: pointer to the hw struct
2634 * @vsi_ctx: pointer to a vsi context struct
2635 * @cmd_details: pointer to command details structure or NULL
2637 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2638 struct i40e_vsi_context *vsi_ctx,
2639 struct i40e_asq_cmd_details *cmd_details)
2641 struct i40e_aq_desc desc;
2642 struct i40e_aqc_add_get_update_vsi *cmd =
2643 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2644 struct i40e_aqc_add_get_update_vsi_completion *resp =
2645 (struct i40e_aqc_add_get_update_vsi_completion *)
2647 enum i40e_status_code status;
2649 UNREFERENCED_1PARAMETER(cmd_details);
2650 i40e_fill_default_direct_cmd_desc(&desc,
2651 i40e_aqc_opc_get_vsi_parameters);
2653 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2655 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2657 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2658 sizeof(vsi_ctx->info), NULL);
2660 if (status != I40E_SUCCESS)
2661 goto aq_get_vsi_params_exit;
2663 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2664 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2665 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2666 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2668 aq_get_vsi_params_exit:
2673 * i40e_aq_update_vsi_params
2674 * @hw: pointer to the hw struct
2675 * @vsi_ctx: pointer to a vsi context struct
2676 * @cmd_details: pointer to command details structure or NULL
2678 * Update a VSI context.
2680 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2681 struct i40e_vsi_context *vsi_ctx,
2682 struct i40e_asq_cmd_details *cmd_details)
2684 struct i40e_aq_desc desc;
2685 struct i40e_aqc_add_get_update_vsi *cmd =
2686 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2687 struct i40e_aqc_add_get_update_vsi_completion *resp =
2688 (struct i40e_aqc_add_get_update_vsi_completion *)
2690 enum i40e_status_code status;
2692 i40e_fill_default_direct_cmd_desc(&desc,
2693 i40e_aqc_opc_update_vsi_parameters);
2694 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2696 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2698 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2699 sizeof(vsi_ctx->info), cmd_details);
2701 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2702 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2708 * i40e_aq_get_switch_config
2709 * @hw: pointer to the hardware structure
2710 * @buf: pointer to the result buffer
2711 * @buf_size: length of input buffer
2712 * @start_seid: seid to start for the report, 0 == beginning
2713 * @cmd_details: pointer to command details structure or NULL
2715 * Fill the buf with switch configuration returned from AdminQ command
2717 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2718 struct i40e_aqc_get_switch_config_resp *buf,
2719 u16 buf_size, u16 *start_seid,
2720 struct i40e_asq_cmd_details *cmd_details)
2722 struct i40e_aq_desc desc;
2723 struct i40e_aqc_switch_seid *scfg =
2724 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2725 enum i40e_status_code status;
2727 i40e_fill_default_direct_cmd_desc(&desc,
2728 i40e_aqc_opc_get_switch_config);
2729 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2730 if (buf_size > I40E_AQ_LARGE_BUF)
2731 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2732 scfg->seid = CPU_TO_LE16(*start_seid);
2734 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2735 *start_seid = LE16_TO_CPU(scfg->seid);
2741 * i40e_aq_set_switch_config
2742 * @hw: pointer to the hardware structure
2743 * @flags: bit flag values to set
2744 * @mode: cloud filter mode
2745 * @valid_flags: which bit flags to set
2746 * @cmd_details: pointer to command details structure or NULL
2748 * Set switch configuration bits
2750 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2751 u16 flags, u16 valid_flags, u8 mode,
2752 struct i40e_asq_cmd_details *cmd_details)
2754 struct i40e_aq_desc desc;
2755 struct i40e_aqc_set_switch_config *scfg =
2756 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2757 enum i40e_status_code status;
2759 i40e_fill_default_direct_cmd_desc(&desc,
2760 i40e_aqc_opc_set_switch_config);
2761 scfg->flags = CPU_TO_LE16(flags);
2762 scfg->valid_flags = CPU_TO_LE16(valid_flags);
2764 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
2765 scfg->switch_tag = CPU_TO_LE16(hw->switch_tag);
2766 scfg->first_tag = CPU_TO_LE16(hw->first_tag);
2767 scfg->second_tag = CPU_TO_LE16(hw->second_tag);
2769 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2775 * i40e_aq_get_firmware_version
2776 * @hw: pointer to the hw struct
2777 * @fw_major_version: firmware major version
2778 * @fw_minor_version: firmware minor version
2779 * @fw_build: firmware build number
2780 * @api_major_version: major queue version
2781 * @api_minor_version: minor queue version
2782 * @cmd_details: pointer to command details structure or NULL
2784 * Get the firmware version from the admin queue commands
2786 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2787 u16 *fw_major_version, u16 *fw_minor_version,
2789 u16 *api_major_version, u16 *api_minor_version,
2790 struct i40e_asq_cmd_details *cmd_details)
2792 struct i40e_aq_desc desc;
2793 struct i40e_aqc_get_version *resp =
2794 (struct i40e_aqc_get_version *)&desc.params.raw;
2795 enum i40e_status_code status;
2797 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2799 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2801 if (status == I40E_SUCCESS) {
2802 if (fw_major_version != NULL)
2803 *fw_major_version = LE16_TO_CPU(resp->fw_major);
2804 if (fw_minor_version != NULL)
2805 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2806 if (fw_build != NULL)
2807 *fw_build = LE32_TO_CPU(resp->fw_build);
2808 if (api_major_version != NULL)
2809 *api_major_version = LE16_TO_CPU(resp->api_major);
2810 if (api_minor_version != NULL)
2811 *api_minor_version = LE16_TO_CPU(resp->api_minor);
2813 /* A workaround to fix the API version in SW */
2814 if (api_major_version && api_minor_version &&
2815 fw_major_version && fw_minor_version &&
2816 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2817 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2818 (*fw_major_version > 4)))
2819 *api_minor_version = 2;
2826 * i40e_aq_send_driver_version
2827 * @hw: pointer to the hw struct
2828 * @dv: driver's major, minor version
2829 * @cmd_details: pointer to command details structure or NULL
2831 * Send the driver version to the firmware
2833 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2834 struct i40e_driver_version *dv,
2835 struct i40e_asq_cmd_details *cmd_details)
2837 struct i40e_aq_desc desc;
2838 struct i40e_aqc_driver_version *cmd =
2839 (struct i40e_aqc_driver_version *)&desc.params.raw;
2840 enum i40e_status_code status;
2844 return I40E_ERR_PARAM;
2846 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2848 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2849 cmd->driver_major_ver = dv->major_version;
2850 cmd->driver_minor_ver = dv->minor_version;
2851 cmd->driver_build_ver = dv->build_version;
2852 cmd->driver_subbuild_ver = dv->subbuild_version;
2855 while (len < sizeof(dv->driver_string) &&
2856 (dv->driver_string[len] < 0x80) &&
2857 dv->driver_string[len])
2859 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2866 * i40e_get_link_status - get status of the HW network link
2867 * @hw: pointer to the hw struct
2868 * @link_up: pointer to bool (true/false = linkup/linkdown)
2870 * Variable link_up true if link is up, false if link is down.
2871 * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2873 * Side effect: LinkStatusEvent reporting becomes enabled
2875 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2877 enum i40e_status_code status = I40E_SUCCESS;
2879 if (hw->phy.get_link_info) {
2880 status = i40e_update_link_info(hw);
2882 if (status != I40E_SUCCESS)
2883 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2887 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2893 * i40e_updatelink_status - update status of the HW network link
2894 * @hw: pointer to the hw struct
2896 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2898 struct i40e_aq_get_phy_abilities_resp abilities;
2899 enum i40e_status_code status = I40E_SUCCESS;
2901 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2905 /* extra checking needed to ensure link info to user is timely */
2906 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2907 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2908 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2909 status = i40e_aq_get_phy_capabilities(hw, false, false,
2914 if (abilities.fec_cfg_curr_mod_ext_info &
2915 I40E_AQ_ENABLE_FEC_AUTO)
2916 hw->phy.link_info.req_fec_info =
2917 (I40E_AQ_REQUEST_FEC_KR |
2918 I40E_AQ_REQUEST_FEC_RS);
2920 hw->phy.link_info.req_fec_info =
2921 abilities.fec_cfg_curr_mod_ext_info &
2922 (I40E_AQ_REQUEST_FEC_KR |
2923 I40E_AQ_REQUEST_FEC_RS);
2925 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2926 sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2933 * i40e_get_link_speed
2934 * @hw: pointer to the hw struct
2936 * Returns the link speed of the adapter.
2938 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2940 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2941 enum i40e_status_code status = I40E_SUCCESS;
2943 if (hw->phy.get_link_info) {
2944 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2946 if (status != I40E_SUCCESS)
2947 goto i40e_link_speed_exit;
2950 speed = hw->phy.link_info.link_speed;
2952 i40e_link_speed_exit:
2957 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2958 * @hw: pointer to the hw struct
2959 * @uplink_seid: the MAC or other gizmo SEID
2960 * @downlink_seid: the VSI SEID
2961 * @enabled_tc: bitmap of TCs to be enabled
2962 * @default_port: true for default port VSI, false for control port
2963 * @veb_seid: pointer to where to put the resulting VEB SEID
2964 * @enable_stats: true to turn on VEB stats
2965 * @cmd_details: pointer to command details structure or NULL
2967 * This asks the FW to add a VEB between the uplink and downlink
2968 * elements. If the uplink SEID is 0, this will be a floating VEB.
2970 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2971 u16 downlink_seid, u8 enabled_tc,
2972 bool default_port, u16 *veb_seid,
2974 struct i40e_asq_cmd_details *cmd_details)
2976 struct i40e_aq_desc desc;
2977 struct i40e_aqc_add_veb *cmd =
2978 (struct i40e_aqc_add_veb *)&desc.params.raw;
2979 struct i40e_aqc_add_veb_completion *resp =
2980 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2981 enum i40e_status_code status;
2984 /* SEIDs need to either both be set or both be 0 for floating VEB */
2985 if (!!uplink_seid != !!downlink_seid)
2986 return I40E_ERR_PARAM;
2988 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2990 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2991 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2992 cmd->enable_tcs = enabled_tc;
2994 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2996 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2998 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
3000 /* reverse logic here: set the bitflag to disable the stats */
3002 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
3004 cmd->veb_flags = CPU_TO_LE16(veb_flags);
3006 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3008 if (!status && veb_seid)
3009 *veb_seid = LE16_TO_CPU(resp->veb_seid);
3015 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
3016 * @hw: pointer to the hw struct
3017 * @veb_seid: the SEID of the VEB to query
3018 * @switch_id: the uplink switch id
3019 * @floating: set to true if the VEB is floating
3020 * @statistic_index: index of the stats counter block for this VEB
3021 * @vebs_used: number of VEB's used by function
3022 * @vebs_free: total VEB's not reserved by any function
3023 * @cmd_details: pointer to command details structure or NULL
3025 * This retrieves the parameters for a particular VEB, specified by
3026 * uplink_seid, and returns them to the caller.
3028 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
3029 u16 veb_seid, u16 *switch_id,
3030 bool *floating, u16 *statistic_index,
3031 u16 *vebs_used, u16 *vebs_free,
3032 struct i40e_asq_cmd_details *cmd_details)
3034 struct i40e_aq_desc desc;
3035 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
3036 (struct i40e_aqc_get_veb_parameters_completion *)
3038 enum i40e_status_code status;
3041 return I40E_ERR_PARAM;
3043 i40e_fill_default_direct_cmd_desc(&desc,
3044 i40e_aqc_opc_get_veb_parameters);
3045 cmd_resp->seid = CPU_TO_LE16(veb_seid);
3047 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3052 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
3053 if (statistic_index)
3054 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
3056 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
3058 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
3060 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
3062 if (flags & I40E_AQC_ADD_VEB_FLOATING)
3073 * i40e_aq_add_macvlan
3074 * @hw: pointer to the hw struct
3075 * @seid: VSI for the mac address
3076 * @mv_list: list of macvlans to be added
3077 * @count: length of the list
3078 * @cmd_details: pointer to command details structure or NULL
3080 * Add MAC/VLAN addresses to the HW filtering
3082 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
3083 struct i40e_aqc_add_macvlan_element_data *mv_list,
3084 u16 count, struct i40e_asq_cmd_details *cmd_details)
3086 struct i40e_aq_desc desc;
3087 struct i40e_aqc_macvlan *cmd =
3088 (struct i40e_aqc_macvlan *)&desc.params.raw;
3089 enum i40e_status_code status;
3093 if (count == 0 || !mv_list || !hw)
3094 return I40E_ERR_PARAM;
3096 buf_size = count * sizeof(*mv_list);
3098 /* prep the rest of the request */
3099 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
3100 cmd->num_addresses = CPU_TO_LE16(count);
3101 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3105 for (i = 0; i < count; i++)
3106 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
3108 CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
3110 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3111 if (buf_size > I40E_AQ_LARGE_BUF)
3112 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3114 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3121 * i40e_aq_remove_macvlan
3122 * @hw: pointer to the hw struct
3123 * @seid: VSI for the mac address
3124 * @mv_list: list of macvlans to be removed
3125 * @count: length of the list
3126 * @cmd_details: pointer to command details structure or NULL
3128 * Remove MAC/VLAN addresses from the HW filtering
3130 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
3131 struct i40e_aqc_remove_macvlan_element_data *mv_list,
3132 u16 count, struct i40e_asq_cmd_details *cmd_details)
3134 struct i40e_aq_desc desc;
3135 struct i40e_aqc_macvlan *cmd =
3136 (struct i40e_aqc_macvlan *)&desc.params.raw;
3137 enum i40e_status_code status;
3140 if (count == 0 || !mv_list || !hw)
3141 return I40E_ERR_PARAM;
3143 buf_size = count * sizeof(*mv_list);
3145 /* prep the rest of the request */
3146 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
3147 cmd->num_addresses = CPU_TO_LE16(count);
3148 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3152 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3153 if (buf_size > I40E_AQ_LARGE_BUF)
3154 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3156 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3163 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3164 * @hw: pointer to the hw struct
3165 * @opcode: AQ opcode for add or delete mirror rule
3166 * @sw_seid: Switch SEID (to which rule refers)
3167 * @rule_type: Rule Type (ingress/egress/VLAN)
3168 * @id: Destination VSI SEID or Rule ID
3169 * @count: length of the list
3170 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3171 * @cmd_details: pointer to command details structure or NULL
3172 * @rule_id: Rule ID returned from FW
3173 * @rules_used: Number of rules used in internal switch
3174 * @rules_free: Number of rules free in internal switch
3176 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3177 * VEBs/VEPA elements only
3179 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3180 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3181 u16 count, __le16 *mr_list,
3182 struct i40e_asq_cmd_details *cmd_details,
3183 u16 *rule_id, u16 *rules_used, u16 *rules_free)
3185 struct i40e_aq_desc desc;
3186 struct i40e_aqc_add_delete_mirror_rule *cmd =
3187 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3188 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3189 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3190 enum i40e_status_code status;
3193 buf_size = count * sizeof(*mr_list);
3195 /* prep the rest of the request */
3196 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3197 cmd->seid = CPU_TO_LE16(sw_seid);
3198 cmd->rule_type = CPU_TO_LE16(rule_type &
3199 I40E_AQC_MIRROR_RULE_TYPE_MASK);
3200 cmd->num_entries = CPU_TO_LE16(count);
3201 /* Dest VSI for add, rule_id for delete */
3202 cmd->destination = CPU_TO_LE16(id);
3204 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3206 if (buf_size > I40E_AQ_LARGE_BUF)
3207 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3210 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3212 if (status == I40E_SUCCESS ||
3213 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3215 *rule_id = LE16_TO_CPU(resp->rule_id);
3217 *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3219 *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3225 * i40e_aq_add_mirrorrule - add a mirror rule
3226 * @hw: pointer to the hw struct
3227 * @sw_seid: Switch SEID (to which rule refers)
3228 * @rule_type: Rule Type (ingress/egress/VLAN)
3229 * @dest_vsi: SEID of VSI to which packets will be mirrored
3230 * @count: length of the list
3231 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3232 * @cmd_details: pointer to command details structure or NULL
3233 * @rule_id: Rule ID returned from FW
3234 * @rules_used: Number of rules used in internal switch
3235 * @rules_free: Number of rules free in internal switch
3237 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3239 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3240 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3241 struct i40e_asq_cmd_details *cmd_details,
3242 u16 *rule_id, u16 *rules_used, u16 *rules_free)
3244 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3245 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3246 if (count == 0 || !mr_list)
3247 return I40E_ERR_PARAM;
3250 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3251 rule_type, dest_vsi, count, mr_list,
3252 cmd_details, rule_id, rules_used, rules_free);
3256 * i40e_aq_delete_mirrorrule - delete a mirror rule
3257 * @hw: pointer to the hw struct
3258 * @sw_seid: Switch SEID (to which rule refers)
3259 * @rule_type: Rule Type (ingress/egress/VLAN)
3260 * @count: length of the list
3261 * @rule_id: Rule ID that is returned in the receive desc as part of
3263 * @mr_list: list of mirrored VLAN IDs to be removed
3264 * @cmd_details: pointer to command details structure or NULL
3265 * @rules_used: Number of rules used in internal switch
3266 * @rules_free: Number of rules free in internal switch
3268 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3270 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3271 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3272 struct i40e_asq_cmd_details *cmd_details,
3273 u16 *rules_used, u16 *rules_free)
3275 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3276 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3277 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3278 * mirroring. For other rule_type, count and rule_type should
3281 if (count == 0 || !mr_list)
3282 return I40E_ERR_PARAM;
3285 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3286 rule_type, rule_id, count, mr_list,
3287 cmd_details, NULL, rules_used, rules_free);
3291 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3292 * @hw: pointer to the hw struct
3293 * @seid: VSI for the vlan filters
3294 * @v_list: list of vlan filters to be added
3295 * @count: length of the list
3296 * @cmd_details: pointer to command details structure or NULL
3298 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3299 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3300 u8 count, struct i40e_asq_cmd_details *cmd_details)
3302 struct i40e_aq_desc desc;
3303 struct i40e_aqc_macvlan *cmd =
3304 (struct i40e_aqc_macvlan *)&desc.params.raw;
3305 enum i40e_status_code status;
3308 if (count == 0 || !v_list || !hw)
3309 return I40E_ERR_PARAM;
3311 buf_size = count * sizeof(*v_list);
3313 /* prep the rest of the request */
3314 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3315 cmd->num_addresses = CPU_TO_LE16(count);
3316 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3320 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3321 if (buf_size > I40E_AQ_LARGE_BUF)
3322 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3324 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3331 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3332 * @hw: pointer to the hw struct
3333 * @seid: VSI for the vlan filters
3334 * @v_list: list of macvlans to be removed
3335 * @count: length of the list
3336 * @cmd_details: pointer to command details structure or NULL
3338 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3339 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3340 u8 count, struct i40e_asq_cmd_details *cmd_details)
3342 struct i40e_aq_desc desc;
3343 struct i40e_aqc_macvlan *cmd =
3344 (struct i40e_aqc_macvlan *)&desc.params.raw;
3345 enum i40e_status_code status;
3348 if (count == 0 || !v_list || !hw)
3349 return I40E_ERR_PARAM;
3351 buf_size = count * sizeof(*v_list);
3353 /* prep the rest of the request */
3354 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3355 cmd->num_addresses = CPU_TO_LE16(count);
3356 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3360 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3361 if (buf_size > I40E_AQ_LARGE_BUF)
3362 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3364 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3371 * i40e_aq_send_msg_to_vf
3372 * @hw: pointer to the hardware structure
3373 * @vfid: vf id to send msg
3374 * @v_opcode: opcodes for VF-PF communication
3375 * @v_retval: return error code
3376 * @msg: pointer to the msg buffer
3377 * @msglen: msg length
3378 * @cmd_details: pointer to command details
3382 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3383 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3384 struct i40e_asq_cmd_details *cmd_details)
3386 struct i40e_aq_desc desc;
3387 struct i40e_aqc_pf_vf_message *cmd =
3388 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3389 enum i40e_status_code status;
3391 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3392 cmd->id = CPU_TO_LE32(vfid);
3393 desc.cookie_high = CPU_TO_LE32(v_opcode);
3394 desc.cookie_low = CPU_TO_LE32(v_retval);
3395 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3397 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3399 if (msglen > I40E_AQ_LARGE_BUF)
3400 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3401 desc.datalen = CPU_TO_LE16(msglen);
3403 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3409 * i40e_aq_debug_read_register
3410 * @hw: pointer to the hw struct
3411 * @reg_addr: register address
3412 * @reg_val: register value
3413 * @cmd_details: pointer to command details structure or NULL
3415 * Read the register using the admin queue commands
3417 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3418 u32 reg_addr, u64 *reg_val,
3419 struct i40e_asq_cmd_details *cmd_details)
3421 struct i40e_aq_desc desc;
3422 struct i40e_aqc_debug_reg_read_write *cmd_resp =
3423 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3424 enum i40e_status_code status;
3426 if (reg_val == NULL)
3427 return I40E_ERR_PARAM;
3429 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3431 cmd_resp->address = CPU_TO_LE32(reg_addr);
3433 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3435 if (status == I40E_SUCCESS) {
3436 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3437 (u64)LE32_TO_CPU(cmd_resp->value_low);
3444 * i40e_aq_debug_write_register
3445 * @hw: pointer to the hw struct
3446 * @reg_addr: register address
3447 * @reg_val: register value
3448 * @cmd_details: pointer to command details structure or NULL
3450 * Write to a register using the admin queue commands
3452 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3453 u32 reg_addr, u64 reg_val,
3454 struct i40e_asq_cmd_details *cmd_details)
3456 struct i40e_aq_desc desc;
3457 struct i40e_aqc_debug_reg_read_write *cmd =
3458 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3459 enum i40e_status_code status;
3461 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3463 cmd->address = CPU_TO_LE32(reg_addr);
3464 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3465 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3467 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3473 * i40e_aq_request_resource
3474 * @hw: pointer to the hw struct
3475 * @resource: resource id
3476 * @access: access type
3477 * @sdp_number: resource number
3478 * @timeout: the maximum time in ms that the driver may hold the resource
3479 * @cmd_details: pointer to command details structure or NULL
3481 * requests common resource using the admin queue commands
3483 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3484 enum i40e_aq_resources_ids resource,
3485 enum i40e_aq_resource_access_type access,
3486 u8 sdp_number, u64 *timeout,
3487 struct i40e_asq_cmd_details *cmd_details)
3489 struct i40e_aq_desc desc;
3490 struct i40e_aqc_request_resource *cmd_resp =
3491 (struct i40e_aqc_request_resource *)&desc.params.raw;
3492 enum i40e_status_code status;
3494 DEBUGFUNC("i40e_aq_request_resource");
3496 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3498 cmd_resp->resource_id = CPU_TO_LE16(resource);
3499 cmd_resp->access_type = CPU_TO_LE16(access);
3500 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3502 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3503 /* The completion specifies the maximum time in ms that the driver
3504 * may hold the resource in the Timeout field.
3505 * If the resource is held by someone else, the command completes with
3506 * busy return value and the timeout field indicates the maximum time
3507 * the current owner of the resource has to free it.
3509 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3510 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3516 * i40e_aq_release_resource
3517 * @hw: pointer to the hw struct
3518 * @resource: resource id
3519 * @sdp_number: resource number
3520 * @cmd_details: pointer to command details structure or NULL
3522 * release common resource using the admin queue commands
3524 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3525 enum i40e_aq_resources_ids resource,
3527 struct i40e_asq_cmd_details *cmd_details)
3529 struct i40e_aq_desc desc;
3530 struct i40e_aqc_request_resource *cmd =
3531 (struct i40e_aqc_request_resource *)&desc.params.raw;
3532 enum i40e_status_code status;
3534 DEBUGFUNC("i40e_aq_release_resource");
3536 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3538 cmd->resource_id = CPU_TO_LE16(resource);
3539 cmd->resource_number = CPU_TO_LE32(sdp_number);
3541 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3548 * @hw: pointer to the hw struct
3549 * @module_pointer: module pointer location in words from the NVM beginning
3550 * @offset: byte offset from the module beginning
3551 * @length: length of the section to be read (in bytes from the offset)
3552 * @data: command buffer (size [bytes] = length)
3553 * @last_command: tells if this is the last command in a series
3554 * @cmd_details: pointer to command details structure or NULL
3556 * Read the NVM using the admin queue commands
3558 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3559 u32 offset, u16 length, void *data,
3561 struct i40e_asq_cmd_details *cmd_details)
3563 struct i40e_aq_desc desc;
3564 struct i40e_aqc_nvm_update *cmd =
3565 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3566 enum i40e_status_code status;
3568 DEBUGFUNC("i40e_aq_read_nvm");
3570 /* In offset the highest byte must be zeroed. */
3571 if (offset & 0xFF000000) {
3572 status = I40E_ERR_PARAM;
3573 goto i40e_aq_read_nvm_exit;
3576 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3578 /* If this is the last command in a series, set the proper flag. */
3580 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3581 cmd->module_pointer = module_pointer;
3582 cmd->offset = CPU_TO_LE32(offset);
3583 cmd->length = CPU_TO_LE16(length);
3585 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3586 if (length > I40E_AQ_LARGE_BUF)
3587 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3589 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3591 i40e_aq_read_nvm_exit:
3596 * i40e_aq_read_nvm_config - read an nvm config block
3597 * @hw: pointer to the hw struct
3598 * @cmd_flags: NVM access admin command bits
3599 * @field_id: field or feature id
3600 * @data: buffer for result
3601 * @buf_size: buffer size
3602 * @element_count: pointer to count of elements read by FW
3603 * @cmd_details: pointer to command details structure or NULL
3605 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3606 u8 cmd_flags, u32 field_id, void *data,
3607 u16 buf_size, u16 *element_count,
3608 struct i40e_asq_cmd_details *cmd_details)
3610 struct i40e_aq_desc desc;
3611 struct i40e_aqc_nvm_config_read *cmd =
3612 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3613 enum i40e_status_code status;
3615 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3616 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3617 if (buf_size > I40E_AQ_LARGE_BUF)
3618 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3620 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3621 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3622 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3623 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3625 cmd->element_id_msw = 0;
3627 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3629 if (!status && element_count)
3630 *element_count = LE16_TO_CPU(cmd->element_count);
3636 * i40e_aq_write_nvm_config - write an nvm config block
3637 * @hw: pointer to the hw struct
3638 * @cmd_flags: NVM access admin command bits
3639 * @data: buffer for result
3640 * @buf_size: buffer size
3641 * @element_count: count of elements to be written
3642 * @cmd_details: pointer to command details structure or NULL
3644 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3645 u8 cmd_flags, void *data, u16 buf_size,
3647 struct i40e_asq_cmd_details *cmd_details)
3649 struct i40e_aq_desc desc;
3650 struct i40e_aqc_nvm_config_write *cmd =
3651 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3652 enum i40e_status_code status;
3654 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3655 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3656 if (buf_size > I40E_AQ_LARGE_BUF)
3657 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3659 cmd->element_count = CPU_TO_LE16(element_count);
3660 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3661 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3667 * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3668 * @hw: pointer to the hw struct
3669 * @buff: buffer for result
3670 * @buff_size: buffer size
3671 * @cmd_details: pointer to command details structure or NULL
3673 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3674 void *buff, u16 buff_size,
3675 struct i40e_asq_cmd_details *cmd_details)
3677 struct i40e_aq_desc desc;
3678 enum i40e_status_code status;
3680 UNREFERENCED_2PARAMETER(buff, buff_size);
3682 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3683 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3684 if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3685 status = I40E_ERR_NOT_IMPLEMENTED;
3692 * @hw: pointer to the hw struct
3693 * @module_pointer: module pointer location in words from the NVM beginning
3694 * @offset: offset in the module (expressed in 4 KB from module's beginning)
3695 * @length: length of the section to be erased (expressed in 4 KB)
3696 * @last_command: tells if this is the last command in a series
3697 * @cmd_details: pointer to command details structure or NULL
3699 * Erase the NVM sector using the admin queue commands
3701 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3702 u32 offset, u16 length, bool last_command,
3703 struct i40e_asq_cmd_details *cmd_details)
3705 struct i40e_aq_desc desc;
3706 struct i40e_aqc_nvm_update *cmd =
3707 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3708 enum i40e_status_code status;
3710 DEBUGFUNC("i40e_aq_erase_nvm");
3712 /* In offset the highest byte must be zeroed. */
3713 if (offset & 0xFF000000) {
3714 status = I40E_ERR_PARAM;
3715 goto i40e_aq_erase_nvm_exit;
3718 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3720 /* If this is the last command in a series, set the proper flag. */
3722 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3723 cmd->module_pointer = module_pointer;
3724 cmd->offset = CPU_TO_LE32(offset);
3725 cmd->length = CPU_TO_LE16(length);
3727 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3729 i40e_aq_erase_nvm_exit:
3734 * i40e_parse_discover_capabilities
3735 * @hw: pointer to the hw struct
3736 * @buff: pointer to a buffer containing device/function capability records
3737 * @cap_count: number of capability records in the list
3738 * @list_type_opc: type of capabilities list to parse
3740 * Parse the device/function capabilities list.
3742 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3744 enum i40e_admin_queue_opc list_type_opc)
3746 struct i40e_aqc_list_capabilities_element_resp *cap;
3747 u32 valid_functions, num_functions;
3748 u32 number, logical_id, phys_id;
3749 struct i40e_hw_capabilities *p;
3750 enum i40e_status_code status;
3751 u16 id, ocp_cfg_word0;
3755 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3757 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3758 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3759 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3760 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3764 for (i = 0; i < cap_count; i++, cap++) {
3765 id = LE16_TO_CPU(cap->id);
3766 number = LE32_TO_CPU(cap->number);
3767 logical_id = LE32_TO_CPU(cap->logical_id);
3768 phys_id = LE32_TO_CPU(cap->phys_id);
3769 major_rev = cap->major_rev;
3772 case I40E_AQ_CAP_ID_SWITCH_MODE:
3773 p->switch_mode = number;
3774 i40e_debug(hw, I40E_DEBUG_INIT,
3775 "HW Capability: Switch mode = %d\n",
3778 case I40E_AQ_CAP_ID_MNG_MODE:
3779 p->management_mode = number;
3780 if (major_rev > 1) {
3781 p->mng_protocols_over_mctp = logical_id;
3782 i40e_debug(hw, I40E_DEBUG_INIT,
3783 "HW Capability: Protocols over MCTP = %d\n",
3784 p->mng_protocols_over_mctp);
3786 p->mng_protocols_over_mctp = 0;
3788 i40e_debug(hw, I40E_DEBUG_INIT,
3789 "HW Capability: Management Mode = %d\n",
3790 p->management_mode);
3792 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3793 p->npar_enable = number;
3794 i40e_debug(hw, I40E_DEBUG_INIT,
3795 "HW Capability: NPAR enable = %d\n",
3798 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3800 i40e_debug(hw, I40E_DEBUG_INIT,
3801 "HW Capability: OS2BMC = %d\n", p->os2bmc);
3803 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3804 p->valid_functions = number;
3805 i40e_debug(hw, I40E_DEBUG_INIT,
3806 "HW Capability: Valid Functions = %d\n",
3807 p->valid_functions);
3809 case I40E_AQ_CAP_ID_SRIOV:
3811 p->sr_iov_1_1 = true;
3812 i40e_debug(hw, I40E_DEBUG_INIT,
3813 "HW Capability: SR-IOV = %d\n",
3816 case I40E_AQ_CAP_ID_VF:
3817 p->num_vfs = number;
3818 p->vf_base_id = logical_id;
3819 i40e_debug(hw, I40E_DEBUG_INIT,
3820 "HW Capability: VF count = %d\n",
3822 i40e_debug(hw, I40E_DEBUG_INIT,
3823 "HW Capability: VF base_id = %d\n",
3826 case I40E_AQ_CAP_ID_VMDQ:
3829 i40e_debug(hw, I40E_DEBUG_INIT,
3830 "HW Capability: VMDQ = %d\n", p->vmdq);
3832 case I40E_AQ_CAP_ID_8021QBG:
3834 p->evb_802_1_qbg = true;
3835 i40e_debug(hw, I40E_DEBUG_INIT,
3836 "HW Capability: 802.1Qbg = %d\n", number);
3838 case I40E_AQ_CAP_ID_8021QBR:
3840 p->evb_802_1_qbh = true;
3841 i40e_debug(hw, I40E_DEBUG_INIT,
3842 "HW Capability: 802.1Qbh = %d\n", number);
3844 case I40E_AQ_CAP_ID_VSI:
3845 p->num_vsis = number;
3846 i40e_debug(hw, I40E_DEBUG_INIT,
3847 "HW Capability: VSI count = %d\n",
3850 case I40E_AQ_CAP_ID_DCB:
3853 p->enabled_tcmap = logical_id;
3856 i40e_debug(hw, I40E_DEBUG_INIT,
3857 "HW Capability: DCB = %d\n", p->dcb);
3858 i40e_debug(hw, I40E_DEBUG_INIT,
3859 "HW Capability: TC Mapping = %d\n",
3861 i40e_debug(hw, I40E_DEBUG_INIT,
3862 "HW Capability: TC Max = %d\n", p->maxtc);
3864 case I40E_AQ_CAP_ID_FCOE:
3867 i40e_debug(hw, I40E_DEBUG_INIT,
3868 "HW Capability: FCOE = %d\n", p->fcoe);
3870 case I40E_AQ_CAP_ID_ISCSI:
3873 i40e_debug(hw, I40E_DEBUG_INIT,
3874 "HW Capability: iSCSI = %d\n", p->iscsi);
3876 case I40E_AQ_CAP_ID_RSS:
3878 p->rss_table_size = number;
3879 p->rss_table_entry_width = logical_id;
3880 i40e_debug(hw, I40E_DEBUG_INIT,
3881 "HW Capability: RSS = %d\n", p->rss);
3882 i40e_debug(hw, I40E_DEBUG_INIT,
3883 "HW Capability: RSS table size = %d\n",
3885 i40e_debug(hw, I40E_DEBUG_INIT,
3886 "HW Capability: RSS table width = %d\n",
3887 p->rss_table_entry_width);
3889 case I40E_AQ_CAP_ID_RXQ:
3890 p->num_rx_qp = number;
3891 p->base_queue = phys_id;
3892 i40e_debug(hw, I40E_DEBUG_INIT,
3893 "HW Capability: Rx QP = %d\n", number);
3894 i40e_debug(hw, I40E_DEBUG_INIT,
3895 "HW Capability: base_queue = %d\n",
3898 case I40E_AQ_CAP_ID_TXQ:
3899 p->num_tx_qp = number;
3900 p->base_queue = phys_id;
3901 i40e_debug(hw, I40E_DEBUG_INIT,
3902 "HW Capability: Tx QP = %d\n", number);
3903 i40e_debug(hw, I40E_DEBUG_INIT,
3904 "HW Capability: base_queue = %d\n",
3907 case I40E_AQ_CAP_ID_MSIX:
3908 p->num_msix_vectors = number;
3909 i40e_debug(hw, I40E_DEBUG_INIT,
3910 "HW Capability: MSIX vector count = %d\n",
3911 p->num_msix_vectors);
3913 case I40E_AQ_CAP_ID_VF_MSIX:
3914 p->num_msix_vectors_vf = number;
3915 i40e_debug(hw, I40E_DEBUG_INIT,
3916 "HW Capability: MSIX VF vector count = %d\n",
3917 p->num_msix_vectors_vf);
3919 case I40E_AQ_CAP_ID_FLEX10:
3920 if (major_rev == 1) {
3922 p->flex10_enable = true;
3923 p->flex10_capable = true;
3926 /* Capability revision >= 2 */
3928 p->flex10_enable = true;
3930 p->flex10_capable = true;
3932 p->flex10_mode = logical_id;
3933 p->flex10_status = phys_id;
3934 i40e_debug(hw, I40E_DEBUG_INIT,
3935 "HW Capability: Flex10 mode = %d\n",
3937 i40e_debug(hw, I40E_DEBUG_INIT,
3938 "HW Capability: Flex10 status = %d\n",
3941 case I40E_AQ_CAP_ID_CEM:
3944 i40e_debug(hw, I40E_DEBUG_INIT,
3945 "HW Capability: CEM = %d\n", p->mgmt_cem);
3947 case I40E_AQ_CAP_ID_IWARP:
3950 i40e_debug(hw, I40E_DEBUG_INIT,
3951 "HW Capability: iWARP = %d\n", p->iwarp);
3953 case I40E_AQ_CAP_ID_LED:
3954 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3955 p->led[phys_id] = true;
3956 i40e_debug(hw, I40E_DEBUG_INIT,
3957 "HW Capability: LED - PIN %d\n", phys_id);
3959 case I40E_AQ_CAP_ID_SDP:
3960 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3961 p->sdp[phys_id] = true;
3962 i40e_debug(hw, I40E_DEBUG_INIT,
3963 "HW Capability: SDP - PIN %d\n", phys_id);
3965 case I40E_AQ_CAP_ID_MDIO:
3967 p->mdio_port_num = phys_id;
3968 p->mdio_port_mode = logical_id;
3970 i40e_debug(hw, I40E_DEBUG_INIT,
3971 "HW Capability: MDIO port number = %d\n",
3973 i40e_debug(hw, I40E_DEBUG_INIT,
3974 "HW Capability: MDIO port mode = %d\n",
3977 case I40E_AQ_CAP_ID_1588:
3979 p->ieee_1588 = true;
3980 i40e_debug(hw, I40E_DEBUG_INIT,
3981 "HW Capability: IEEE 1588 = %d\n",
3984 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3986 p->fd_filters_guaranteed = number;
3987 p->fd_filters_best_effort = logical_id;
3988 i40e_debug(hw, I40E_DEBUG_INIT,
3989 "HW Capability: Flow Director = 1\n");
3990 i40e_debug(hw, I40E_DEBUG_INIT,
3991 "HW Capability: Guaranteed FD filters = %d\n",
3992 p->fd_filters_guaranteed);
3994 case I40E_AQ_CAP_ID_WSR_PROT:
3995 p->wr_csr_prot = (u64)number;
3996 p->wr_csr_prot |= (u64)logical_id << 32;
3997 i40e_debug(hw, I40E_DEBUG_INIT,
3998 "HW Capability: wr_csr_prot = 0x%llX\n\n",
3999 (p->wr_csr_prot & 0xffff));
4001 case I40E_AQ_CAP_ID_NVM_MGMT:
4002 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
4003 p->sec_rev_disabled = true;
4004 if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
4005 p->update_disabled = true;
4007 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
4008 hw->num_wol_proxy_filters = (u16)number;
4009 hw->wol_proxy_vsi_seid = (u16)logical_id;
4010 p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
4011 if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
4012 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
4014 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
4015 p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
4016 i40e_debug(hw, I40E_DEBUG_INIT,
4017 "HW Capability: WOL proxy filters = %d\n",
4018 hw->num_wol_proxy_filters);
4026 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
4028 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
4031 /* count the enabled ports (aka the "not disabled" ports) */
4033 for (i = 0; i < 4; i++) {
4034 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
4037 /* use AQ read to get the physical register offset instead
4038 * of the port relative offset
4040 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
4041 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
4045 /* OCP cards case: if a mezz is removed the ethernet port is at
4046 * disabled state in PRTGEN_CNF register. Additional NVM read is
4047 * needed in order to check if we are dealing with OCP card.
4048 * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting
4049 * physical ports results in wrong partition id calculation and thus
4050 * not supporting WoL.
4052 if (hw->mac.type == I40E_MAC_X722) {
4053 if (i40e_acquire_nvm(hw, I40E_RESOURCE_READ) == I40E_SUCCESS) {
4054 status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR,
4055 2 * I40E_SR_OCP_CFG_WORD0,
4056 sizeof(ocp_cfg_word0),
4057 &ocp_cfg_word0, true, NULL);
4058 if (status == I40E_SUCCESS &&
4059 (ocp_cfg_word0 & I40E_SR_OCP_ENABLED))
4061 i40e_release_nvm(hw);
4065 valid_functions = p->valid_functions;
4067 while (valid_functions) {
4068 if (valid_functions & 1)
4070 valid_functions >>= 1;
4073 /* partition id is 1-based, and functions are evenly spread
4074 * across the ports as partitions
4076 if (hw->num_ports != 0) {
4077 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
4078 hw->num_partitions = num_functions / hw->num_ports;
4081 /* additional HW specific goodies that might
4082 * someday be HW version specific
4084 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
4088 * i40e_aq_discover_capabilities
4089 * @hw: pointer to the hw struct
4090 * @buff: a virtual buffer to hold the capabilities
4091 * @buff_size: Size of the virtual buffer
4092 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
4093 * @list_type_opc: capabilities type to discover - pass in the command opcode
4094 * @cmd_details: pointer to command details structure or NULL
4096 * Get the device capabilities descriptions from the firmware
4098 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
4099 void *buff, u16 buff_size, u16 *data_size,
4100 enum i40e_admin_queue_opc list_type_opc,
4101 struct i40e_asq_cmd_details *cmd_details)
4103 struct i40e_aqc_list_capabilites *cmd;
4104 struct i40e_aq_desc desc;
4105 enum i40e_status_code status = I40E_SUCCESS;
4107 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
4109 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
4110 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
4111 status = I40E_ERR_PARAM;
4115 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
4117 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4118 if (buff_size > I40E_AQ_LARGE_BUF)
4119 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4121 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4122 *data_size = LE16_TO_CPU(desc.datalen);
4127 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
4135 * i40e_aq_update_nvm
4136 * @hw: pointer to the hw struct
4137 * @module_pointer: module pointer location in words from the NVM beginning
4138 * @offset: byte offset from the module beginning
4139 * @length: length of the section to be written (in bytes from the offset)
4140 * @data: command buffer (size [bytes] = length)
4141 * @last_command: tells if this is the last command in a series
4142 * @preservation_flags: Preservation mode flags
4143 * @cmd_details: pointer to command details structure or NULL
4145 * Update the NVM using the admin queue commands
4147 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
4148 u32 offset, u16 length, void *data,
4149 bool last_command, u8 preservation_flags,
4150 struct i40e_asq_cmd_details *cmd_details)
4152 struct i40e_aq_desc desc;
4153 struct i40e_aqc_nvm_update *cmd =
4154 (struct i40e_aqc_nvm_update *)&desc.params.raw;
4155 enum i40e_status_code status;
4157 DEBUGFUNC("i40e_aq_update_nvm");
4159 /* In offset the highest byte must be zeroed. */
4160 if (offset & 0xFF000000) {
4161 status = I40E_ERR_PARAM;
4162 goto i40e_aq_update_nvm_exit;
4165 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4167 /* If this is the last command in a series, set the proper flag. */
4169 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
4170 if (hw->mac.type == I40E_MAC_X722) {
4171 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED)
4172 cmd->command_flags |=
4173 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED <<
4174 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4175 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL)
4176 cmd->command_flags |=
4177 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL <<
4178 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4180 cmd->module_pointer = module_pointer;
4181 cmd->offset = CPU_TO_LE32(offset);
4182 cmd->length = CPU_TO_LE16(length);
4184 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4185 if (length > I40E_AQ_LARGE_BUF)
4186 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4188 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
4190 i40e_aq_update_nvm_exit:
4195 * i40e_aq_rearrange_nvm
4196 * @hw: pointer to the hw struct
4197 * @rearrange_nvm: defines direction of rearrangement
4198 * @cmd_details: pointer to command details structure or NULL
4200 * Rearrange NVM structure, available only for transition FW
4202 enum i40e_status_code i40e_aq_rearrange_nvm(struct i40e_hw *hw,
4204 struct i40e_asq_cmd_details *cmd_details)
4206 struct i40e_aqc_nvm_update *cmd;
4207 enum i40e_status_code status;
4208 struct i40e_aq_desc desc;
4210 DEBUGFUNC("i40e_aq_rearrange_nvm");
4212 cmd = (struct i40e_aqc_nvm_update *)&desc.params.raw;
4214 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4216 rearrange_nvm &= (I40E_AQ_NVM_REARRANGE_TO_FLAT |
4217 I40E_AQ_NVM_REARRANGE_TO_STRUCT);
4219 if (!rearrange_nvm) {
4220 status = I40E_ERR_PARAM;
4221 goto i40e_aq_rearrange_nvm_exit;
4224 cmd->command_flags |= rearrange_nvm;
4225 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4227 i40e_aq_rearrange_nvm_exit:
4232 * i40e_aq_nvm_progress
4233 * @hw: pointer to the hw struct
4234 * @progress: pointer to progress returned from AQ
4235 * @cmd_details: pointer to command details structure or NULL
4237 * Gets progress of flash rearrangement process
4239 enum i40e_status_code i40e_aq_nvm_progress(struct i40e_hw *hw, u8 *progress,
4240 struct i40e_asq_cmd_details *cmd_details)
4242 enum i40e_status_code status;
4243 struct i40e_aq_desc desc;
4245 DEBUGFUNC("i40e_aq_nvm_progress");
4247 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_progress);
4248 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4249 *progress = desc.params.raw[0];
4254 * i40e_aq_get_lldp_mib
4255 * @hw: pointer to the hw struct
4256 * @bridge_type: type of bridge requested
4257 * @mib_type: Local, Remote or both Local and Remote MIBs
4258 * @buff: pointer to a user supplied buffer to store the MIB block
4259 * @buff_size: size of the buffer (in bytes)
4260 * @local_len : length of the returned Local LLDP MIB
4261 * @remote_len: length of the returned Remote LLDP MIB
4262 * @cmd_details: pointer to command details structure or NULL
4264 * Requests the complete LLDP MIB (entire packet).
4266 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4267 u8 mib_type, void *buff, u16 buff_size,
4268 u16 *local_len, u16 *remote_len,
4269 struct i40e_asq_cmd_details *cmd_details)
4271 struct i40e_aq_desc desc;
4272 struct i40e_aqc_lldp_get_mib *cmd =
4273 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4274 struct i40e_aqc_lldp_get_mib *resp =
4275 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4276 enum i40e_status_code status;
4278 if (buff_size == 0 || !buff)
4279 return I40E_ERR_PARAM;
4281 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4282 /* Indirect Command */
4283 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4285 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4286 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4287 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4289 desc.datalen = CPU_TO_LE16(buff_size);
4291 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4292 if (buff_size > I40E_AQ_LARGE_BUF)
4293 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4295 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4297 if (local_len != NULL)
4298 *local_len = LE16_TO_CPU(resp->local_len);
4299 if (remote_len != NULL)
4300 *remote_len = LE16_TO_CPU(resp->remote_len);
4307 * i40e_aq_set_lldp_mib - Set the LLDP MIB
4308 * @hw: pointer to the hw struct
4309 * @mib_type: Local, Remote or both Local and Remote MIBs
4310 * @buff: pointer to a user supplied buffer to store the MIB block
4311 * @buff_size: size of the buffer (in bytes)
4312 * @cmd_details: pointer to command details structure or NULL
4316 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4317 u8 mib_type, void *buff, u16 buff_size,
4318 struct i40e_asq_cmd_details *cmd_details)
4320 struct i40e_aq_desc desc;
4321 struct i40e_aqc_lldp_set_local_mib *cmd =
4322 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4323 enum i40e_status_code status;
4325 if (buff_size == 0 || !buff)
4326 return I40E_ERR_PARAM;
4328 i40e_fill_default_direct_cmd_desc(&desc,
4329 i40e_aqc_opc_lldp_set_local_mib);
4330 /* Indirect Command */
4331 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4332 if (buff_size > I40E_AQ_LARGE_BUF)
4333 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4334 desc.datalen = CPU_TO_LE16(buff_size);
4336 cmd->type = mib_type;
4337 cmd->length = CPU_TO_LE16(buff_size);
4338 cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)buff));
4339 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4341 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4346 * i40e_aq_cfg_lldp_mib_change_event
4347 * @hw: pointer to the hw struct
4348 * @enable_update: Enable or Disable event posting
4349 * @cmd_details: pointer to command details structure or NULL
4351 * Enable or Disable posting of an event on ARQ when LLDP MIB
4352 * associated with the interface changes
4354 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4356 struct i40e_asq_cmd_details *cmd_details)
4358 struct i40e_aq_desc desc;
4359 struct i40e_aqc_lldp_update_mib *cmd =
4360 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4361 enum i40e_status_code status;
4363 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4366 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4368 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4374 * i40e_aq_restore_lldp
4375 * @hw: pointer to the hw struct
4376 * @setting: pointer to factory setting variable or NULL
4377 * @restore: True if factory settings should be restored
4378 * @cmd_details: pointer to command details structure or NULL
4380 * Restore LLDP Agent factory settings if @restore set to True. In other case
4381 * only returns factory setting in AQ response.
4383 enum i40e_status_code
4384 i40e_aq_restore_lldp(struct i40e_hw *hw, u8 *setting, bool restore,
4385 struct i40e_asq_cmd_details *cmd_details)
4387 struct i40e_aq_desc desc;
4388 struct i40e_aqc_lldp_restore *cmd =
4389 (struct i40e_aqc_lldp_restore *)&desc.params.raw;
4390 enum i40e_status_code status;
4392 if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)) {
4393 i40e_debug(hw, I40E_DEBUG_ALL,
4394 "Restore LLDP not supported by current FW version.\n");
4395 return I40E_ERR_DEVICE_NOT_SUPPORTED;
4398 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_restore);
4401 cmd->command |= I40E_AQ_LLDP_AGENT_RESTORE;
4403 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4406 *setting = cmd->command & 1;
4413 * @hw: pointer to the hw struct
4414 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4415 * @persist: True if stop of LLDP should be persistent across power cycles
4416 * @cmd_details: pointer to command details structure or NULL
4418 * Stop or Shutdown the embedded LLDP Agent
4420 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4422 struct i40e_asq_cmd_details *cmd_details)
4424 struct i40e_aq_desc desc;
4425 struct i40e_aqc_lldp_stop *cmd =
4426 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4427 enum i40e_status_code status;
4429 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4432 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4435 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)
4436 cmd->command |= I40E_AQ_LLDP_AGENT_STOP_PERSIST;
4438 i40e_debug(hw, I40E_DEBUG_ALL,
4439 "Persistent Stop LLDP not supported by current FW version.\n");
4442 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4448 * i40e_aq_start_lldp
4449 * @hw: pointer to the hw struct
4450 * @persist: True if start of LLDP should be persistent across power cycles
4451 * @cmd_details: pointer to command details structure or NULL
4453 * Start the embedded LLDP Agent on all ports.
4455 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4457 struct i40e_asq_cmd_details *cmd_details)
4459 struct i40e_aq_desc desc;
4460 struct i40e_aqc_lldp_start *cmd =
4461 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4462 enum i40e_status_code status;
4464 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4466 cmd->command = I40E_AQ_LLDP_AGENT_START;
4469 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)
4470 cmd->command |= I40E_AQ_LLDP_AGENT_START_PERSIST;
4472 i40e_debug(hw, I40E_DEBUG_ALL,
4473 "Persistent Start LLDP not supported by current FW version.\n");
4476 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4482 * i40e_aq_set_dcb_parameters
4483 * @hw: pointer to the hw struct
4484 * @cmd_details: pointer to command details structure or NULL
4485 * @dcb_enable: True if DCB configuration needs to be applied
4488 enum i40e_status_code
4489 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable,
4490 struct i40e_asq_cmd_details *cmd_details)
4492 struct i40e_aq_desc desc;
4493 struct i40e_aqc_set_dcb_parameters *cmd =
4494 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw;
4495 enum i40e_status_code status;
4497 if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_STOPPABLE))
4498 return I40E_ERR_DEVICE_NOT_SUPPORTED;
4500 i40e_fill_default_direct_cmd_desc(&desc,
4501 i40e_aqc_opc_set_dcb_parameters);
4504 cmd->valid_flags = I40E_DCB_VALID;
4505 cmd->command = I40E_AQ_DCB_SET_AGENT;
4507 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4513 * i40e_aq_get_cee_dcb_config
4514 * @hw: pointer to the hw struct
4515 * @buff: response buffer that stores CEE operational configuration
4516 * @buff_size: size of the buffer passed
4517 * @cmd_details: pointer to command details structure or NULL
4519 * Get CEE DCBX mode operational configuration from firmware
4521 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4522 void *buff, u16 buff_size,
4523 struct i40e_asq_cmd_details *cmd_details)
4525 struct i40e_aq_desc desc;
4526 enum i40e_status_code status;
4528 if (buff_size == 0 || !buff)
4529 return I40E_ERR_PARAM;
4531 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4533 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4534 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4541 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4542 * @hw: pointer to the hw struct
4543 * @start_agent: True if DCBx Agent needs to be Started
4544 * False if DCBx Agent needs to be Stopped
4545 * @cmd_details: pointer to command details structure or NULL
4547 * Start/Stop the embedded dcbx Agent
4549 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4551 struct i40e_asq_cmd_details *cmd_details)
4553 struct i40e_aq_desc desc;
4554 struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4555 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4557 enum i40e_status_code status;
4559 i40e_fill_default_direct_cmd_desc(&desc,
4560 i40e_aqc_opc_lldp_stop_start_spec_agent);
4563 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4565 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4571 * i40e_aq_add_udp_tunnel
4572 * @hw: pointer to the hw struct
4573 * @udp_port: the UDP port to add in Host byte order
4574 * @protocol_index: protocol index type
4575 * @filter_index: pointer to filter index
4576 * @cmd_details: pointer to command details structure or NULL
4578 * Note: Firmware expects the udp_port value to be in Little Endian format,
4579 * and this function will call CPU_TO_LE16 to convert from Host byte order to
4580 * Little Endian order.
4582 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4583 u16 udp_port, u8 protocol_index,
4585 struct i40e_asq_cmd_details *cmd_details)
4587 struct i40e_aq_desc desc;
4588 struct i40e_aqc_add_udp_tunnel *cmd =
4589 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4590 struct i40e_aqc_del_udp_tunnel_completion *resp =
4591 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4592 enum i40e_status_code status;
4594 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4596 cmd->udp_port = CPU_TO_LE16(udp_port);
4597 cmd->protocol_type = protocol_index;
4599 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4601 if (!status && filter_index)
4602 *filter_index = resp->index;
4608 * i40e_aq_del_udp_tunnel
4609 * @hw: pointer to the hw struct
4610 * @index: filter index
4611 * @cmd_details: pointer to command details structure or NULL
4613 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4614 struct i40e_asq_cmd_details *cmd_details)
4616 struct i40e_aq_desc desc;
4617 struct i40e_aqc_remove_udp_tunnel *cmd =
4618 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4619 enum i40e_status_code status;
4621 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4625 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4631 * i40e_aq_get_switch_resource_alloc (0x0204)
4632 * @hw: pointer to the hw struct
4633 * @num_entries: pointer to u8 to store the number of resource entries returned
4634 * @buf: pointer to a user supplied buffer. This buffer must be large enough
4635 * to store the resource information for all resource types. Each
4636 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
4637 * @count: size, in bytes, of the buffer provided
4638 * @cmd_details: pointer to command details structure or NULL
4640 * Query the resources allocated to a function.
4642 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4644 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4646 struct i40e_asq_cmd_details *cmd_details)
4648 struct i40e_aq_desc desc;
4649 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4650 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4651 enum i40e_status_code status;
4652 u16 length = count * sizeof(*buf);
4654 i40e_fill_default_direct_cmd_desc(&desc,
4655 i40e_aqc_opc_get_switch_resource_alloc);
4657 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4658 if (length > I40E_AQ_LARGE_BUF)
4659 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4661 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4663 if (!status && num_entries)
4664 *num_entries = cmd_resp->num_entries;
4670 * i40e_aq_delete_element - Delete switch element
4671 * @hw: pointer to the hw struct
4672 * @seid: the SEID to delete from the switch
4673 * @cmd_details: pointer to command details structure or NULL
4675 * This deletes a switch element from the switch.
4677 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4678 struct i40e_asq_cmd_details *cmd_details)
4680 struct i40e_aq_desc desc;
4681 struct i40e_aqc_switch_seid *cmd =
4682 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4683 enum i40e_status_code status;
4686 return I40E_ERR_PARAM;
4688 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4690 cmd->seid = CPU_TO_LE16(seid);
4692 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4698 * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4699 * @hw: pointer to the hw struct
4700 * @flags: component flags
4701 * @mac_seid: uplink seid (MAC SEID)
4702 * @vsi_seid: connected vsi seid
4703 * @ret_seid: seid of create pv component
4705 * This instantiates an i40e port virtualizer with specified flags.
4706 * Depending on specified flags the port virtualizer can act as a
4707 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4709 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4710 u16 mac_seid, u16 vsi_seid,
4713 struct i40e_aq_desc desc;
4714 struct i40e_aqc_add_update_pv *cmd =
4715 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4716 struct i40e_aqc_add_update_pv_completion *resp =
4717 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4718 enum i40e_status_code status;
4721 return I40E_ERR_PARAM;
4723 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4724 cmd->command_flags = CPU_TO_LE16(flags);
4725 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4726 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4728 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4729 if (!status && ret_seid)
4730 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4736 * i40e_aq_add_tag - Add an S/E-tag
4737 * @hw: pointer to the hw struct
4738 * @direct_to_queue: should s-tag direct flow to a specific queue
4739 * @vsi_seid: VSI SEID to use this tag
4740 * @tag: value of the tag
4741 * @queue_num: queue number, only valid is direct_to_queue is true
4742 * @tags_used: return value, number of tags in use by this PF
4743 * @tags_free: return value, number of unallocated tags
4744 * @cmd_details: pointer to command details structure or NULL
4746 * This associates an S- or E-tag to a VSI in the switch complex. It returns
4747 * the number of tags allocated by the PF, and the number of unallocated
4750 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4751 u16 vsi_seid, u16 tag, u16 queue_num,
4752 u16 *tags_used, u16 *tags_free,
4753 struct i40e_asq_cmd_details *cmd_details)
4755 struct i40e_aq_desc desc;
4756 struct i40e_aqc_add_tag *cmd =
4757 (struct i40e_aqc_add_tag *)&desc.params.raw;
4758 struct i40e_aqc_add_remove_tag_completion *resp =
4759 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4760 enum i40e_status_code status;
4763 return I40E_ERR_PARAM;
4765 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4767 cmd->seid = CPU_TO_LE16(vsi_seid);
4768 cmd->tag = CPU_TO_LE16(tag);
4769 if (direct_to_queue) {
4770 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4771 cmd->queue_number = CPU_TO_LE16(queue_num);
4774 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4777 if (tags_used != NULL)
4778 *tags_used = LE16_TO_CPU(resp->tags_used);
4779 if (tags_free != NULL)
4780 *tags_free = LE16_TO_CPU(resp->tags_free);
4787 * i40e_aq_remove_tag - Remove an S- or E-tag
4788 * @hw: pointer to the hw struct
4789 * @vsi_seid: VSI SEID this tag is associated with
4790 * @tag: value of the S-tag to delete
4791 * @tags_used: return value, number of tags in use by this PF
4792 * @tags_free: return value, number of unallocated tags
4793 * @cmd_details: pointer to command details structure or NULL
4795 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
4796 * the number of tags allocated by the PF, and the number of unallocated
4799 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4800 u16 tag, u16 *tags_used, u16 *tags_free,
4801 struct i40e_asq_cmd_details *cmd_details)
4803 struct i40e_aq_desc desc;
4804 struct i40e_aqc_remove_tag *cmd =
4805 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4806 struct i40e_aqc_add_remove_tag_completion *resp =
4807 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4808 enum i40e_status_code status;
4811 return I40E_ERR_PARAM;
4813 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4815 cmd->seid = CPU_TO_LE16(vsi_seid);
4816 cmd->tag = CPU_TO_LE16(tag);
4818 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4821 if (tags_used != NULL)
4822 *tags_used = LE16_TO_CPU(resp->tags_used);
4823 if (tags_free != NULL)
4824 *tags_free = LE16_TO_CPU(resp->tags_free);
4831 * i40e_aq_add_mcast_etag - Add a multicast E-tag
4832 * @hw: pointer to the hw struct
4833 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4834 * @etag: value of E-tag to add
4835 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4836 * @buf: address of indirect buffer
4837 * @tags_used: return value, number of E-tags in use by this port
4838 * @tags_free: return value, number of unallocated M-tags
4839 * @cmd_details: pointer to command details structure or NULL
4841 * This associates a multicast E-tag to a port virtualizer. It will return
4842 * the number of tags allocated by the PF, and the number of unallocated
4845 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4846 * num_tags_in_buf long.
4848 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4849 u16 etag, u8 num_tags_in_buf, void *buf,
4850 u16 *tags_used, u16 *tags_free,
4851 struct i40e_asq_cmd_details *cmd_details)
4853 struct i40e_aq_desc desc;
4854 struct i40e_aqc_add_remove_mcast_etag *cmd =
4855 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4856 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4857 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4858 enum i40e_status_code status;
4859 u16 length = sizeof(u16) * num_tags_in_buf;
4861 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4862 return I40E_ERR_PARAM;
4864 i40e_fill_default_direct_cmd_desc(&desc,
4865 i40e_aqc_opc_add_multicast_etag);
4867 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4868 cmd->etag = CPU_TO_LE16(etag);
4869 cmd->num_unicast_etags = num_tags_in_buf;
4871 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4873 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4876 if (tags_used != NULL)
4877 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4878 if (tags_free != NULL)
4879 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4886 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4887 * @hw: pointer to the hw struct
4888 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4889 * @etag: value of the E-tag to remove
4890 * @tags_used: return value, number of tags in use by this port
4891 * @tags_free: return value, number of unallocated tags
4892 * @cmd_details: pointer to command details structure or NULL
4894 * This deletes an E-tag from the port virtualizer. It will return
4895 * the number of tags allocated by the port, and the number of unallocated
4898 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4899 u16 etag, u16 *tags_used, u16 *tags_free,
4900 struct i40e_asq_cmd_details *cmd_details)
4902 struct i40e_aq_desc desc;
4903 struct i40e_aqc_add_remove_mcast_etag *cmd =
4904 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4905 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4906 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4907 enum i40e_status_code status;
4911 return I40E_ERR_PARAM;
4913 i40e_fill_default_direct_cmd_desc(&desc,
4914 i40e_aqc_opc_remove_multicast_etag);
4916 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4917 cmd->etag = CPU_TO_LE16(etag);
4919 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4922 if (tags_used != NULL)
4923 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4924 if (tags_free != NULL)
4925 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4932 * i40e_aq_update_tag - Update an S/E-tag
4933 * @hw: pointer to the hw struct
4934 * @vsi_seid: VSI SEID using this S-tag
4935 * @old_tag: old tag value
4936 * @new_tag: new tag value
4937 * @tags_used: return value, number of tags in use by this PF
4938 * @tags_free: return value, number of unallocated tags
4939 * @cmd_details: pointer to command details structure or NULL
4941 * This updates the value of the tag currently attached to this VSI
4942 * in the switch complex. It will return the number of tags allocated
4943 * by the PF, and the number of unallocated tags available.
4945 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4946 u16 old_tag, u16 new_tag, u16 *tags_used,
4948 struct i40e_asq_cmd_details *cmd_details)
4950 struct i40e_aq_desc desc;
4951 struct i40e_aqc_update_tag *cmd =
4952 (struct i40e_aqc_update_tag *)&desc.params.raw;
4953 struct i40e_aqc_update_tag_completion *resp =
4954 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4955 enum i40e_status_code status;
4958 return I40E_ERR_PARAM;
4960 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4962 cmd->seid = CPU_TO_LE16(vsi_seid);
4963 cmd->old_tag = CPU_TO_LE16(old_tag);
4964 cmd->new_tag = CPU_TO_LE16(new_tag);
4966 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4969 if (tags_used != NULL)
4970 *tags_used = LE16_TO_CPU(resp->tags_used);
4971 if (tags_free != NULL)
4972 *tags_free = LE16_TO_CPU(resp->tags_free);
4979 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4980 * @hw: pointer to the hw struct
4981 * @tcmap: TC map for request/release any ignore PFC condition
4982 * @request: request or release ignore PFC condition
4983 * @tcmap_ret: return TCs for which PFC is currently ignored
4984 * @cmd_details: pointer to command details structure or NULL
4986 * This sends out request/release to ignore PFC condition for a TC.
4987 * It will return the TCs for which PFC is currently ignored.
4989 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4990 bool request, u8 *tcmap_ret,
4991 struct i40e_asq_cmd_details *cmd_details)
4993 struct i40e_aq_desc desc;
4994 struct i40e_aqc_pfc_ignore *cmd_resp =
4995 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4996 enum i40e_status_code status;
4998 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
5001 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
5003 cmd_resp->tc_bitmap = tcmap;
5005 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5008 if (tcmap_ret != NULL)
5009 *tcmap_ret = cmd_resp->tc_bitmap;
5016 * i40e_aq_dcb_updated - DCB Updated Command
5017 * @hw: pointer to the hw struct
5018 * @cmd_details: pointer to command details structure or NULL
5020 * When LLDP is handled in PF this command is used by the PF
5021 * to notify EMP that a DCB setting is modified.
5022 * When LLDP is handled in EMP this command is used by the PF
5023 * to notify EMP whenever one of the following parameters get
5025 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
5026 * - PCIRTT in PRTDCB_GENC.PCIRTT
5027 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
5028 * EMP will return when the shared RPB settings have been
5029 * recomputed and modified. The retval field in the descriptor
5030 * will be set to 0 when RPB is modified.
5032 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
5033 struct i40e_asq_cmd_details *cmd_details)
5035 struct i40e_aq_desc desc;
5036 enum i40e_status_code status;
5038 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
5040 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5046 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
5047 * @hw: pointer to the hw struct
5048 * @seid: defines the SEID of the switch for which the stats are requested
5049 * @vlan_id: the VLAN ID for which the statistics are requested
5050 * @stat_index: index of the statistics counters block assigned to this VLAN
5051 * @cmd_details: pointer to command details structure or NULL
5053 * XL710 supports 128 smonVlanStats counters.This command is used to
5054 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
5057 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
5058 u16 vlan_id, u16 *stat_index,
5059 struct i40e_asq_cmd_details *cmd_details)
5061 struct i40e_aq_desc desc;
5062 struct i40e_aqc_add_remove_statistics *cmd_resp =
5063 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5064 enum i40e_status_code status;
5066 if ((seid == 0) || (stat_index == NULL))
5067 return I40E_ERR_PARAM;
5069 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
5071 cmd_resp->seid = CPU_TO_LE16(seid);
5072 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
5074 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5076 if (!status && stat_index)
5077 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
5083 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
5084 * @hw: pointer to the hw struct
5085 * @seid: defines the SEID of the switch for which the stats are requested
5086 * @vlan_id: the VLAN ID for which the statistics are requested
5087 * @stat_index: index of the statistics counters block assigned to this VLAN
5088 * @cmd_details: pointer to command details structure or NULL
5090 * XL710 supports 128 smonVlanStats counters.This command is used to
5091 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
5094 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
5095 u16 vlan_id, u16 stat_index,
5096 struct i40e_asq_cmd_details *cmd_details)
5098 struct i40e_aq_desc desc;
5099 struct i40e_aqc_add_remove_statistics *cmd =
5100 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5101 enum i40e_status_code status;
5104 return I40E_ERR_PARAM;
5106 i40e_fill_default_direct_cmd_desc(&desc,
5107 i40e_aqc_opc_remove_statistics);
5109 cmd->seid = CPU_TO_LE16(seid);
5110 cmd->vlan = CPU_TO_LE16(vlan_id);
5111 cmd->stat_index = CPU_TO_LE16(stat_index);
5113 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5119 * i40e_aq_set_port_parameters - set physical port parameters.
5120 * @hw: pointer to the hw struct
5121 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
5122 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
5123 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
5124 * @double_vlan: if set double VLAN is enabled
5125 * @cmd_details: pointer to command details structure or NULL
5127 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
5128 u16 bad_frame_vsi, bool save_bad_pac,
5129 bool pad_short_pac, bool double_vlan,
5130 struct i40e_asq_cmd_details *cmd_details)
5132 struct i40e_aqc_set_port_parameters *cmd;
5133 enum i40e_status_code status;
5134 struct i40e_aq_desc desc;
5135 u16 command_flags = 0;
5137 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
5139 i40e_fill_default_direct_cmd_desc(&desc,
5140 i40e_aqc_opc_set_port_parameters);
5142 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
5144 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
5146 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
5148 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
5149 cmd->command_flags = CPU_TO_LE16(command_flags);
5151 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5157 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
5158 * @hw: pointer to the hw struct
5159 * @seid: seid for the physical port/switching component/vsi
5160 * @buff: Indirect buffer to hold data parameters and response
5161 * @buff_size: Indirect buffer size
5162 * @opcode: Tx scheduler AQ command opcode
5163 * @cmd_details: pointer to command details structure or NULL
5165 * Generic command handler for Tx scheduler AQ commands
5167 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
5168 void *buff, u16 buff_size,
5169 enum i40e_admin_queue_opc opcode,
5170 struct i40e_asq_cmd_details *cmd_details)
5172 struct i40e_aq_desc desc;
5173 struct i40e_aqc_tx_sched_ind *cmd =
5174 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
5175 enum i40e_status_code status;
5176 bool cmd_param_flag = false;
5179 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
5180 case i40e_aqc_opc_configure_vsi_tc_bw:
5181 case i40e_aqc_opc_enable_switching_comp_ets:
5182 case i40e_aqc_opc_modify_switching_comp_ets:
5183 case i40e_aqc_opc_disable_switching_comp_ets:
5184 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
5185 case i40e_aqc_opc_configure_switching_comp_bw_config:
5186 cmd_param_flag = true;
5188 case i40e_aqc_opc_query_vsi_bw_config:
5189 case i40e_aqc_opc_query_vsi_ets_sla_config:
5190 case i40e_aqc_opc_query_switching_comp_ets_config:
5191 case i40e_aqc_opc_query_port_ets_config:
5192 case i40e_aqc_opc_query_switching_comp_bw_config:
5193 cmd_param_flag = false;
5196 return I40E_ERR_PARAM;
5199 i40e_fill_default_direct_cmd_desc(&desc, opcode);
5201 /* Indirect command */
5202 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5204 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5205 if (buff_size > I40E_AQ_LARGE_BUF)
5206 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5208 desc.datalen = CPU_TO_LE16(buff_size);
5210 cmd->vsi_seid = CPU_TO_LE16(seid);
5212 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5218 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5219 * @hw: pointer to the hw struct
5221 * @credit: BW limit credits (0 = disabled)
5222 * @max_credit: Max BW limit credits
5223 * @cmd_details: pointer to command details structure or NULL
5225 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5226 u16 seid, u16 credit, u8 max_credit,
5227 struct i40e_asq_cmd_details *cmd_details)
5229 struct i40e_aq_desc desc;
5230 struct i40e_aqc_configure_vsi_bw_limit *cmd =
5231 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5232 enum i40e_status_code status;
5234 i40e_fill_default_direct_cmd_desc(&desc,
5235 i40e_aqc_opc_configure_vsi_bw_limit);
5237 cmd->vsi_seid = CPU_TO_LE16(seid);
5238 cmd->credit = CPU_TO_LE16(credit);
5239 cmd->max_credit = max_credit;
5241 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5247 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5248 * @hw: pointer to the hw struct
5249 * @seid: switching component seid
5250 * @credit: BW limit credits (0 = disabled)
5251 * @max_bw: Max BW limit credits
5252 * @cmd_details: pointer to command details structure or NULL
5254 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5255 u16 seid, u16 credit, u8 max_bw,
5256 struct i40e_asq_cmd_details *cmd_details)
5258 struct i40e_aq_desc desc;
5259 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5260 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5261 enum i40e_status_code status;
5263 i40e_fill_default_direct_cmd_desc(&desc,
5264 i40e_aqc_opc_configure_switching_comp_bw_limit);
5266 cmd->seid = CPU_TO_LE16(seid);
5267 cmd->credit = CPU_TO_LE16(credit);
5268 cmd->max_bw = max_bw;
5270 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5276 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5277 * @hw: pointer to the hw struct
5279 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5280 * @cmd_details: pointer to command details structure or NULL
5282 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5284 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5285 struct i40e_asq_cmd_details *cmd_details)
5287 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5288 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5293 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5294 * @hw: pointer to the hw struct
5296 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5297 * @cmd_details: pointer to command details structure or NULL
5299 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5301 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5302 struct i40e_asq_cmd_details *cmd_details)
5304 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5305 i40e_aqc_opc_configure_vsi_tc_bw,
5310 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5311 * @hw: pointer to the hw struct
5312 * @seid: seid of the switching component connected to Physical Port
5313 * @ets_data: Buffer holding ETS parameters
5314 * @opcode: Tx scheduler AQ command opcode
5315 * @cmd_details: pointer to command details structure or NULL
5317 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5319 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5320 enum i40e_admin_queue_opc opcode,
5321 struct i40e_asq_cmd_details *cmd_details)
5323 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5324 sizeof(*ets_data), opcode, cmd_details);
5328 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5329 * @hw: pointer to the hw struct
5330 * @seid: seid of the switching component
5331 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5332 * @cmd_details: pointer to command details structure or NULL
5334 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5336 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5337 struct i40e_asq_cmd_details *cmd_details)
5339 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5340 i40e_aqc_opc_configure_switching_comp_bw_config,
5345 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5346 * @hw: pointer to the hw struct
5347 * @seid: seid of the switching component
5348 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5349 * @cmd_details: pointer to command details structure or NULL
5351 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5352 struct i40e_hw *hw, u16 seid,
5353 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5354 struct i40e_asq_cmd_details *cmd_details)
5356 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5357 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5362 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5363 * @hw: pointer to the hw struct
5364 * @seid: seid of the VSI
5365 * @bw_data: Buffer to hold VSI BW configuration
5366 * @cmd_details: pointer to command details structure or NULL
5368 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5370 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5371 struct i40e_asq_cmd_details *cmd_details)
5373 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5374 i40e_aqc_opc_query_vsi_bw_config,
5379 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5380 * @hw: pointer to the hw struct
5381 * @seid: seid of the VSI
5382 * @bw_data: Buffer to hold VSI BW configuration per TC
5383 * @cmd_details: pointer to command details structure or NULL
5385 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5387 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5388 struct i40e_asq_cmd_details *cmd_details)
5390 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5391 i40e_aqc_opc_query_vsi_ets_sla_config,
5396 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5397 * @hw: pointer to the hw struct
5398 * @seid: seid of the switching component
5399 * @bw_data: Buffer to hold switching component's per TC BW config
5400 * @cmd_details: pointer to command details structure or NULL
5402 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5404 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5405 struct i40e_asq_cmd_details *cmd_details)
5407 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5408 i40e_aqc_opc_query_switching_comp_ets_config,
5413 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5414 * @hw: pointer to the hw struct
5415 * @seid: seid of the VSI or switching component connected to Physical Port
5416 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5417 * @cmd_details: pointer to command details structure or NULL
5419 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5421 struct i40e_aqc_query_port_ets_config_resp *bw_data,
5422 struct i40e_asq_cmd_details *cmd_details)
5424 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5425 i40e_aqc_opc_query_port_ets_config,
5430 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5431 * @hw: pointer to the hw struct
5432 * @seid: seid of the switching component
5433 * @bw_data: Buffer to hold switching component's BW configuration
5434 * @cmd_details: pointer to command details structure or NULL
5436 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5438 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5439 struct i40e_asq_cmd_details *cmd_details)
5441 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5442 i40e_aqc_opc_query_switching_comp_bw_config,
5447 * i40e_validate_filter_settings
5448 * @hw: pointer to the hardware structure
5449 * @settings: Filter control settings
5451 * Check and validate the filter control settings passed.
5452 * The function checks for the valid filter/context sizes being
5453 * passed for FCoE and PE.
5455 * Returns I40E_SUCCESS if the values passed are valid and within
5456 * range else returns an error.
5458 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5459 struct i40e_filter_control_settings *settings)
5461 u32 fcoe_cntx_size, fcoe_filt_size;
5462 u32 pe_cntx_size, pe_filt_size;
5467 /* Validate FCoE settings passed */
5468 switch (settings->fcoe_filt_num) {
5469 case I40E_HASH_FILTER_SIZE_1K:
5470 case I40E_HASH_FILTER_SIZE_2K:
5471 case I40E_HASH_FILTER_SIZE_4K:
5472 case I40E_HASH_FILTER_SIZE_8K:
5473 case I40E_HASH_FILTER_SIZE_16K:
5474 case I40E_HASH_FILTER_SIZE_32K:
5475 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5476 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5479 return I40E_ERR_PARAM;
5482 switch (settings->fcoe_cntx_num) {
5483 case I40E_DMA_CNTX_SIZE_512:
5484 case I40E_DMA_CNTX_SIZE_1K:
5485 case I40E_DMA_CNTX_SIZE_2K:
5486 case I40E_DMA_CNTX_SIZE_4K:
5487 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5488 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5491 return I40E_ERR_PARAM;
5494 /* Validate PE settings passed */
5495 switch (settings->pe_filt_num) {
5496 case I40E_HASH_FILTER_SIZE_1K:
5497 case I40E_HASH_FILTER_SIZE_2K:
5498 case I40E_HASH_FILTER_SIZE_4K:
5499 case I40E_HASH_FILTER_SIZE_8K:
5500 case I40E_HASH_FILTER_SIZE_16K:
5501 case I40E_HASH_FILTER_SIZE_32K:
5502 case I40E_HASH_FILTER_SIZE_64K:
5503 case I40E_HASH_FILTER_SIZE_128K:
5504 case I40E_HASH_FILTER_SIZE_256K:
5505 case I40E_HASH_FILTER_SIZE_512K:
5506 case I40E_HASH_FILTER_SIZE_1M:
5507 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5508 pe_filt_size <<= (u32)settings->pe_filt_num;
5511 return I40E_ERR_PARAM;
5514 switch (settings->pe_cntx_num) {
5515 case I40E_DMA_CNTX_SIZE_512:
5516 case I40E_DMA_CNTX_SIZE_1K:
5517 case I40E_DMA_CNTX_SIZE_2K:
5518 case I40E_DMA_CNTX_SIZE_4K:
5519 case I40E_DMA_CNTX_SIZE_8K:
5520 case I40E_DMA_CNTX_SIZE_16K:
5521 case I40E_DMA_CNTX_SIZE_32K:
5522 case I40E_DMA_CNTX_SIZE_64K:
5523 case I40E_DMA_CNTX_SIZE_128K:
5524 case I40E_DMA_CNTX_SIZE_256K:
5525 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5526 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5529 return I40E_ERR_PARAM;
5532 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5533 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5534 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5535 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5536 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
5537 return I40E_ERR_INVALID_SIZE;
5539 return I40E_SUCCESS;
5543 * i40e_set_filter_control
5544 * @hw: pointer to the hardware structure
5545 * @settings: Filter control settings
5547 * Set the Queue Filters for PE/FCoE and enable filters required
5548 * for a single PF. It is expected that these settings are programmed
5549 * at the driver initialization time.
5551 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5552 struct i40e_filter_control_settings *settings)
5554 enum i40e_status_code ret = I40E_SUCCESS;
5555 u32 hash_lut_size = 0;
5559 return I40E_ERR_PARAM;
5561 /* Validate the input settings */
5562 ret = i40e_validate_filter_settings(hw, settings);
5566 /* Read the PF Queue Filter control register */
5567 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5569 /* Program required PE hash buckets for the PF */
5570 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5571 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5572 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5573 /* Program required PE contexts for the PF */
5574 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5575 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5576 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5578 /* Program required FCoE hash buckets for the PF */
5579 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5580 val |= ((u32)settings->fcoe_filt_num <<
5581 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5582 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5583 /* Program required FCoE DDP contexts for the PF */
5584 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5585 val |= ((u32)settings->fcoe_cntx_num <<
5586 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5587 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5589 /* Program Hash LUT size for the PF */
5590 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5591 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5593 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5594 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5596 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5597 if (settings->enable_fdir)
5598 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5599 if (settings->enable_ethtype)
5600 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5601 if (settings->enable_macvlan)
5602 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5604 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5606 return I40E_SUCCESS;
5610 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5611 * @hw: pointer to the hw struct
5612 * @mac_addr: MAC address to use in the filter
5613 * @ethtype: Ethertype to use in the filter
5614 * @flags: Flags that needs to be applied to the filter
5615 * @vsi_seid: seid of the control VSI
5616 * @queue: VSI queue number to send the packet to
5617 * @is_add: Add control packet filter if True else remove
5618 * @stats: Structure to hold information on control filter counts
5619 * @cmd_details: pointer to command details structure or NULL
5621 * This command will Add or Remove control packet filter for a control VSI.
5622 * In return it will update the total number of perfect filter count in
5625 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5626 u8 *mac_addr, u16 ethtype, u16 flags,
5627 u16 vsi_seid, u16 queue, bool is_add,
5628 struct i40e_control_filter_stats *stats,
5629 struct i40e_asq_cmd_details *cmd_details)
5631 struct i40e_aq_desc desc;
5632 struct i40e_aqc_add_remove_control_packet_filter *cmd =
5633 (struct i40e_aqc_add_remove_control_packet_filter *)
5635 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5636 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5638 enum i40e_status_code status;
5641 return I40E_ERR_PARAM;
5644 i40e_fill_default_direct_cmd_desc(&desc,
5645 i40e_aqc_opc_add_control_packet_filter);
5646 cmd->queue = CPU_TO_LE16(queue);
5648 i40e_fill_default_direct_cmd_desc(&desc,
5649 i40e_aqc_opc_remove_control_packet_filter);
5653 i40e_memcpy(cmd->mac, mac_addr, ETH_ALEN,
5654 I40E_NONDMA_TO_NONDMA);
5656 cmd->etype = CPU_TO_LE16(ethtype);
5657 cmd->flags = CPU_TO_LE16(flags);
5658 cmd->seid = CPU_TO_LE16(vsi_seid);
5660 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5662 if (!status && stats) {
5663 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5664 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5665 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5666 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5673 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5674 * @hw: pointer to the hw struct
5675 * @seid: VSI seid to add ethertype filter from
5677 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5680 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5681 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5682 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5683 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5684 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5685 enum i40e_status_code status;
5687 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5688 seid, 0, true, NULL,
5691 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5695 * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5696 * @filters: list of cloud filters
5697 * @filter_count: length of list
5699 * There's an issue in the device where the Geneve VNI layout needs
5700 * to be shifted 1 byte over from the VxLAN VNI
5702 STATIC void i40e_fix_up_geneve_vni(
5703 struct i40e_aqc_cloud_filters_element_data *filters,
5706 struct i40e_aqc_cloud_filters_element_data *f = filters;
5709 for (i = 0; i < filter_count; i++) {
5713 tnl_type = (LE16_TO_CPU(f[i].flags) &
5714 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5715 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5716 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5717 ti = LE32_TO_CPU(f[i].tenant_id);
5718 f[i].tenant_id = CPU_TO_LE32(ti << 8);
5724 * i40e_aq_add_cloud_filters
5725 * @hw: pointer to the hardware structure
5726 * @seid: VSI seid to add cloud filters from
5727 * @filters: Buffer which contains the filters to be added
5728 * @filter_count: number of filters contained in the buffer
5730 * Set the cloud filters for a given VSI. The contents of the
5731 * i40e_aqc_cloud_filters_element_data are filled
5732 * in by the caller of the function.
5735 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5737 struct i40e_aqc_cloud_filters_element_data *filters,
5740 struct i40e_aq_desc desc;
5741 struct i40e_aqc_add_remove_cloud_filters *cmd =
5742 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5743 enum i40e_status_code status;
5746 i40e_fill_default_direct_cmd_desc(&desc,
5747 i40e_aqc_opc_add_cloud_filters);
5749 buff_len = filter_count * sizeof(*filters);
5750 desc.datalen = CPU_TO_LE16(buff_len);
5751 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5752 cmd->num_filters = filter_count;
5753 cmd->seid = CPU_TO_LE16(seid);
5755 i40e_fix_up_geneve_vni(filters, filter_count);
5757 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5763 * i40e_aq_add_cloud_filters_bb
5764 * @hw: pointer to the hardware structure
5765 * @seid: VSI seid to add cloud filters from
5766 * @filters: Buffer which contains the filters in big buffer to be added
5767 * @filter_count: number of filters contained in the buffer
5769 * Set the cloud filters for a given VSI. The contents of the
5770 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5774 enum i40e_status_code
5775 i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5776 struct i40e_aqc_cloud_filters_element_bb *filters,
5779 struct i40e_aq_desc desc;
5780 struct i40e_aqc_add_remove_cloud_filters *cmd =
5781 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5782 enum i40e_status_code status;
5786 i40e_fill_default_direct_cmd_desc(&desc,
5787 i40e_aqc_opc_add_cloud_filters);
5789 buff_len = filter_count * sizeof(*filters);
5790 desc.datalen = CPU_TO_LE16(buff_len);
5791 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5792 cmd->num_filters = filter_count;
5793 cmd->seid = CPU_TO_LE16(seid);
5794 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5796 for (i = 0; i < filter_count; i++) {
5800 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5801 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5802 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5804 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5805 * one more byte further than normally used for Tenant ID in
5806 * other tunnel types.
5808 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5809 ti = LE32_TO_CPU(filters[i].element.tenant_id);
5810 filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5814 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5820 * i40e_aq_rem_cloud_filters
5821 * @hw: pointer to the hardware structure
5822 * @seid: VSI seid to remove cloud filters from
5823 * @filters: Buffer which contains the filters to be removed
5824 * @filter_count: number of filters contained in the buffer
5826 * Remove the cloud filters for a given VSI. The contents of the
5827 * i40e_aqc_cloud_filters_element_data are filled in by the caller
5831 enum i40e_status_code
5832 i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid,
5833 struct i40e_aqc_cloud_filters_element_data *filters,
5836 struct i40e_aq_desc desc;
5837 struct i40e_aqc_add_remove_cloud_filters *cmd =
5838 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5839 enum i40e_status_code status;
5842 i40e_fill_default_direct_cmd_desc(&desc,
5843 i40e_aqc_opc_remove_cloud_filters);
5845 buff_len = filter_count * sizeof(*filters);
5846 desc.datalen = CPU_TO_LE16(buff_len);
5847 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5848 cmd->num_filters = filter_count;
5849 cmd->seid = CPU_TO_LE16(seid);
5851 i40e_fix_up_geneve_vni(filters, filter_count);
5853 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5859 * i40e_aq_rem_cloud_filters_bb
5860 * @hw: pointer to the hardware structure
5861 * @seid: VSI seid to remove cloud filters from
5862 * @filters: Buffer which contains the filters in big buffer to be removed
5863 * @filter_count: number of filters contained in the buffer
5865 * Remove the big buffer cloud filters for a given VSI. The contents of the
5866 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5870 enum i40e_status_code
5871 i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5872 struct i40e_aqc_cloud_filters_element_bb *filters,
5875 struct i40e_aq_desc desc;
5876 struct i40e_aqc_add_remove_cloud_filters *cmd =
5877 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5878 enum i40e_status_code status;
5882 i40e_fill_default_direct_cmd_desc(&desc,
5883 i40e_aqc_opc_remove_cloud_filters);
5885 buff_len = filter_count * sizeof(*filters);
5886 desc.datalen = CPU_TO_LE16(buff_len);
5887 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5888 cmd->num_filters = filter_count;
5889 cmd->seid = CPU_TO_LE16(seid);
5890 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5892 for (i = 0; i < filter_count; i++) {
5896 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5897 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5898 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5900 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5901 * one more byte further than normally used for Tenant ID in
5902 * other tunnel types.
5904 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5905 ti = LE32_TO_CPU(filters[i].element.tenant_id);
5906 filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5910 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5916 * i40e_aq_replace_cloud_filters - Replace cloud filter command
5917 * @hw: pointer to the hw struct
5918 * @filters: pointer to the i40e_aqc_replace_cloud_filter_cmd struct
5919 * @cmd_buf: pointer to the i40e_aqc_replace_cloud_filter_cmd_buf struct
5923 i40e_status_code i40e_aq_replace_cloud_filters(struct i40e_hw *hw,
5924 struct i40e_aqc_replace_cloud_filters_cmd *filters,
5925 struct i40e_aqc_replace_cloud_filters_cmd_buf *cmd_buf)
5927 struct i40e_aq_desc desc;
5928 struct i40e_aqc_replace_cloud_filters_cmd *cmd =
5929 (struct i40e_aqc_replace_cloud_filters_cmd *)&desc.params.raw;
5930 enum i40e_status_code status = I40E_SUCCESS;
5933 /* X722 doesn't support this command */
5934 if (hw->mac.type == I40E_MAC_X722)
5935 return I40E_ERR_DEVICE_NOT_SUPPORTED;
5937 /* need FW version greater than 6.00 */
5938 if (hw->aq.fw_maj_ver < 6)
5939 return I40E_NOT_SUPPORTED;
5941 i40e_fill_default_direct_cmd_desc(&desc,
5942 i40e_aqc_opc_replace_cloud_filters);
5944 desc.datalen = CPU_TO_LE16(32);
5945 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5946 cmd->old_filter_type = filters->old_filter_type;
5947 cmd->new_filter_type = filters->new_filter_type;
5948 cmd->valid_flags = filters->valid_flags;
5949 cmd->tr_bit = filters->tr_bit;
5950 cmd->tr_bit2 = filters->tr_bit2;
5952 status = i40e_asq_send_command(hw, &desc, cmd_buf,
5953 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf), NULL);
5955 /* for get cloud filters command */
5956 for (i = 0; i < 32; i += 4) {
5957 cmd_buf->filters[i / 4].filter_type = cmd_buf->data[i];
5958 cmd_buf->filters[i / 4].input[0] = cmd_buf->data[i + 1];
5959 cmd_buf->filters[i / 4].input[1] = cmd_buf->data[i + 2];
5960 cmd_buf->filters[i / 4].input[2] = cmd_buf->data[i + 3];
5968 * i40e_aq_alternate_write
5969 * @hw: pointer to the hardware structure
5970 * @reg_addr0: address of first dword to be read
5971 * @reg_val0: value to be written under 'reg_addr0'
5972 * @reg_addr1: address of second dword to be read
5973 * @reg_val1: value to be written under 'reg_addr1'
5975 * Write one or two dwords to alternate structure. Fields are indicated
5976 * by 'reg_addr0' and 'reg_addr1' register numbers.
5979 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5980 u32 reg_addr0, u32 reg_val0,
5981 u32 reg_addr1, u32 reg_val1)
5983 struct i40e_aq_desc desc;
5984 struct i40e_aqc_alternate_write *cmd_resp =
5985 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5986 enum i40e_status_code status;
5988 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5989 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5990 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5991 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5992 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5994 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6000 * i40e_aq_alternate_write_indirect
6001 * @hw: pointer to the hardware structure
6002 * @addr: address of a first register to be modified
6003 * @dw_count: number of alternate structure fields to write
6004 * @buffer: pointer to the command buffer
6006 * Write 'dw_count' dwords from 'buffer' to alternate structure
6007 * starting at 'addr'.
6010 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
6011 u32 addr, u32 dw_count, void *buffer)
6013 struct i40e_aq_desc desc;
6014 struct i40e_aqc_alternate_ind_write *cmd_resp =
6015 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
6016 enum i40e_status_code status;
6019 return I40E_ERR_PARAM;
6021 /* Indirect command */
6022 i40e_fill_default_direct_cmd_desc(&desc,
6023 i40e_aqc_opc_alternate_write_indirect);
6025 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6026 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6027 if (dw_count > (I40E_AQ_LARGE_BUF/4))
6028 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6030 cmd_resp->address = CPU_TO_LE32(addr);
6031 cmd_resp->length = CPU_TO_LE32(dw_count);
6033 status = i40e_asq_send_command(hw, &desc, buffer,
6034 I40E_LO_DWORD(4*dw_count), NULL);
6040 * i40e_aq_alternate_read
6041 * @hw: pointer to the hardware structure
6042 * @reg_addr0: address of first dword to be read
6043 * @reg_val0: pointer for data read from 'reg_addr0'
6044 * @reg_addr1: address of second dword to be read
6045 * @reg_val1: pointer for data read from 'reg_addr1'
6047 * Read one or two dwords from alternate structure. Fields are indicated
6048 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
6049 * is not passed then only register at 'reg_addr0' is read.
6052 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
6053 u32 reg_addr0, u32 *reg_val0,
6054 u32 reg_addr1, u32 *reg_val1)
6056 struct i40e_aq_desc desc;
6057 struct i40e_aqc_alternate_write *cmd_resp =
6058 (struct i40e_aqc_alternate_write *)&desc.params.raw;
6059 enum i40e_status_code status;
6061 if (reg_val0 == NULL)
6062 return I40E_ERR_PARAM;
6064 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
6065 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
6066 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
6068 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6070 if (status == I40E_SUCCESS) {
6071 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
6073 if (reg_val1 != NULL)
6074 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
6081 * i40e_aq_alternate_read_indirect
6082 * @hw: pointer to the hardware structure
6083 * @addr: address of the alternate structure field
6084 * @dw_count: number of alternate structure fields to read
6085 * @buffer: pointer to the command buffer
6087 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
6088 * place them in 'buffer'. The buffer should be allocated by caller.
6091 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
6092 u32 addr, u32 dw_count, void *buffer)
6094 struct i40e_aq_desc desc;
6095 struct i40e_aqc_alternate_ind_write *cmd_resp =
6096 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
6097 enum i40e_status_code status;
6100 return I40E_ERR_PARAM;
6102 /* Indirect command */
6103 i40e_fill_default_direct_cmd_desc(&desc,
6104 i40e_aqc_opc_alternate_read_indirect);
6106 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6107 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6108 if (dw_count > (I40E_AQ_LARGE_BUF/4))
6109 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6111 cmd_resp->address = CPU_TO_LE32(addr);
6112 cmd_resp->length = CPU_TO_LE32(dw_count);
6114 status = i40e_asq_send_command(hw, &desc, buffer,
6115 I40E_LO_DWORD(4*dw_count), NULL);
6121 * i40e_aq_alternate_clear
6122 * @hw: pointer to the HW structure.
6124 * Clear the alternate structures of the port from which the function
6128 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
6130 struct i40e_aq_desc desc;
6131 enum i40e_status_code status;
6133 i40e_fill_default_direct_cmd_desc(&desc,
6134 i40e_aqc_opc_alternate_clear_port);
6136 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6142 * i40e_aq_alternate_write_done
6143 * @hw: pointer to the HW structure.
6144 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
6145 * @reset_needed: indicates the SW should trigger GLOBAL reset
6147 * Indicates to the FW that alternate structures have been changed.
6150 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
6151 u8 bios_mode, bool *reset_needed)
6153 struct i40e_aq_desc desc;
6154 struct i40e_aqc_alternate_write_done *cmd =
6155 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6156 enum i40e_status_code status;
6158 if (reset_needed == NULL)
6159 return I40E_ERR_PARAM;
6161 i40e_fill_default_direct_cmd_desc(&desc,
6162 i40e_aqc_opc_alternate_write_done);
6164 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
6166 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6167 if (!status && reset_needed)
6168 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
6169 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
6175 * i40e_aq_set_oem_mode
6176 * @hw: pointer to the HW structure.
6177 * @oem_mode: the OEM mode to be used
6179 * Sets the device to a specific operating mode. Currently the only supported
6180 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
6183 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
6186 struct i40e_aq_desc desc;
6187 struct i40e_aqc_alternate_write_done *cmd =
6188 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6189 enum i40e_status_code status;
6191 i40e_fill_default_direct_cmd_desc(&desc,
6192 i40e_aqc_opc_alternate_set_mode);
6194 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
6196 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6202 * i40e_aq_resume_port_tx
6203 * @hw: pointer to the hardware structure
6204 * @cmd_details: pointer to command details structure or NULL
6206 * Resume port's Tx traffic
6208 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
6209 struct i40e_asq_cmd_details *cmd_details)
6211 struct i40e_aq_desc desc;
6212 enum i40e_status_code status;
6214 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
6216 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6222 * i40e_set_pci_config_data - store PCI bus info
6223 * @hw: pointer to hardware structure
6224 * @link_status: the link status word from PCI config space
6226 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
6228 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
6230 hw->bus.type = i40e_bus_type_pci_express;
6232 switch (link_status & I40E_PCI_LINK_WIDTH) {
6233 case I40E_PCI_LINK_WIDTH_1:
6234 hw->bus.width = i40e_bus_width_pcie_x1;
6236 case I40E_PCI_LINK_WIDTH_2:
6237 hw->bus.width = i40e_bus_width_pcie_x2;
6239 case I40E_PCI_LINK_WIDTH_4:
6240 hw->bus.width = i40e_bus_width_pcie_x4;
6242 case I40E_PCI_LINK_WIDTH_8:
6243 hw->bus.width = i40e_bus_width_pcie_x8;
6246 hw->bus.width = i40e_bus_width_unknown;
6250 switch (link_status & I40E_PCI_LINK_SPEED) {
6251 case I40E_PCI_LINK_SPEED_2500:
6252 hw->bus.speed = i40e_bus_speed_2500;
6254 case I40E_PCI_LINK_SPEED_5000:
6255 hw->bus.speed = i40e_bus_speed_5000;
6257 case I40E_PCI_LINK_SPEED_8000:
6258 hw->bus.speed = i40e_bus_speed_8000;
6261 hw->bus.speed = i40e_bus_speed_unknown;
6267 * i40e_aq_debug_dump
6268 * @hw: pointer to the hardware structure
6269 * @cluster_id: specific cluster to dump
6270 * @table_id: table id within cluster
6271 * @start_index: index of line in the block to read
6272 * @buff_size: dump buffer size
6273 * @buff: dump buffer
6274 * @ret_buff_size: actual buffer size returned
6275 * @ret_next_table: next block to read
6276 * @ret_next_index: next index to read
6277 * @cmd_details: pointer to command details structure or NULL
6279 * Dump internal FW/HW data for debug purposes.
6282 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
6283 u8 table_id, u32 start_index, u16 buff_size,
6284 void *buff, u16 *ret_buff_size,
6285 u8 *ret_next_table, u32 *ret_next_index,
6286 struct i40e_asq_cmd_details *cmd_details)
6288 struct i40e_aq_desc desc;
6289 struct i40e_aqc_debug_dump_internals *cmd =
6290 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6291 struct i40e_aqc_debug_dump_internals *resp =
6292 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6293 enum i40e_status_code status;
6295 if (buff_size == 0 || !buff)
6296 return I40E_ERR_PARAM;
6298 i40e_fill_default_direct_cmd_desc(&desc,
6299 i40e_aqc_opc_debug_dump_internals);
6300 /* Indirect Command */
6301 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6302 if (buff_size > I40E_AQ_LARGE_BUF)
6303 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6305 cmd->cluster_id = cluster_id;
6306 cmd->table_id = table_id;
6307 cmd->idx = CPU_TO_LE32(start_index);
6309 desc.datalen = CPU_TO_LE16(buff_size);
6311 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
6313 if (ret_buff_size != NULL)
6314 *ret_buff_size = LE16_TO_CPU(desc.datalen);
6315 if (ret_next_table != NULL)
6316 *ret_next_table = resp->table_id;
6317 if (ret_next_index != NULL)
6318 *ret_next_index = LE32_TO_CPU(resp->idx);
6327 * @hw: pointer to the hardware structure
6328 * @enable: state of Energy Efficient Ethernet mode to be set
6330 * Enables or disables Energy Efficient Ethernet (EEE) mode
6331 * accordingly to @enable parameter.
6333 enum i40e_status_code i40e_enable_eee(struct i40e_hw *hw, bool enable)
6335 struct i40e_aq_get_phy_abilities_resp abilities;
6336 struct i40e_aq_set_phy_config config;
6337 enum i40e_status_code status;
6338 __le16 eee_capability;
6340 /* Get initial PHY capabilities */
6341 status = i40e_aq_get_phy_capabilities(hw, false, true, &abilities,
6346 /* Check whether NIC configuration is compatible with Energy Efficient
6347 * Ethernet (EEE) mode.
6349 if (abilities.eee_capability == 0) {
6350 status = I40E_ERR_CONFIG;
6354 /* Cache initial EEE capability */
6355 eee_capability = abilities.eee_capability;
6357 /* Get current configuration */
6358 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
6363 /* Cache current configuration */
6364 config.phy_type = abilities.phy_type;
6365 config.link_speed = abilities.link_speed;
6366 config.abilities = abilities.abilities |
6367 I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
6368 config.eeer = abilities.eeer_val;
6369 config.low_power_ctrl = abilities.d3_lpan;
6370 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
6371 I40E_AQ_PHY_FEC_CONFIG_MASK;
6373 /* Set desired EEE state */
6375 config.eee_capability = eee_capability;
6376 config.eeer |= I40E_PRTPM_EEER_TX_LPI_EN_MASK;
6378 config.eee_capability = 0;
6379 config.eeer &= ~I40E_PRTPM_EEER_TX_LPI_EN_MASK;
6382 /* Save modified config */
6383 status = i40e_aq_set_phy_config(hw, &config, NULL);
6389 * i40e_read_bw_from_alt_ram
6390 * @hw: pointer to the hardware structure
6391 * @max_bw: pointer for max_bw read
6392 * @min_bw: pointer for min_bw read
6393 * @min_valid: pointer for bool that is true if min_bw is a valid value
6394 * @max_valid: pointer for bool that is true if max_bw is a valid value
6396 * Read bw from the alternate ram for the given pf
6398 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
6399 u32 *max_bw, u32 *min_bw,
6400 bool *min_valid, bool *max_valid)
6402 enum i40e_status_code status;
6403 u32 max_bw_addr, min_bw_addr;
6405 /* Calculate the address of the min/max bw registers */
6406 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6407 I40E_ALT_STRUCT_MAX_BW_OFFSET +
6408 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6409 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6410 I40E_ALT_STRUCT_MIN_BW_OFFSET +
6411 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6413 /* Read the bandwidths from alt ram */
6414 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
6415 min_bw_addr, min_bw);
6417 if (*min_bw & I40E_ALT_BW_VALID_MASK)
6422 if (*max_bw & I40E_ALT_BW_VALID_MASK)
6431 * i40e_aq_configure_partition_bw
6432 * @hw: pointer to the hardware structure
6433 * @bw_data: Buffer holding valid pfs and bw limits
6434 * @cmd_details: pointer to command details
6436 * Configure partitions guaranteed/max bw
6438 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6439 struct i40e_aqc_configure_partition_bw_data *bw_data,
6440 struct i40e_asq_cmd_details *cmd_details)
6442 enum i40e_status_code status;
6443 struct i40e_aq_desc desc;
6444 u16 bwd_size = sizeof(*bw_data);
6446 i40e_fill_default_direct_cmd_desc(&desc,
6447 i40e_aqc_opc_configure_partition_bw);
6449 /* Indirect command */
6450 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6451 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6453 desc.datalen = CPU_TO_LE16(bwd_size);
6455 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6461 * i40e_read_phy_register_clause22
6462 * @hw: pointer to the HW structure
6463 * @reg: register address in the page
6464 * @phy_addr: PHY address on MDIO interface
6465 * @value: PHY register value
6467 * Reads specified PHY register value
6469 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
6470 u16 reg, u8 phy_addr, u16 *value)
6472 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6473 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6477 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6478 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6479 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
6480 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6481 (I40E_GLGEN_MSCA_MDICMD_MASK);
6482 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6484 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6485 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6486 status = I40E_SUCCESS;
6489 i40e_usec_delay(10);
6494 i40e_debug(hw, I40E_DEBUG_PHY,
6495 "PHY: Can't write command to external PHY.\n");
6497 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6498 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6499 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6506 * i40e_write_phy_register_clause22
6507 * @hw: pointer to the HW structure
6508 * @reg: register address in the page
6509 * @phy_addr: PHY address on MDIO interface
6510 * @value: PHY register value
6512 * Writes specified PHY register value
6514 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6515 u16 reg, u8 phy_addr, u16 value)
6517 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6518 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6522 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6523 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6525 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6526 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6527 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6528 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6529 (I40E_GLGEN_MSCA_MDICMD_MASK);
6531 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6533 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6534 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6535 status = I40E_SUCCESS;
6538 i40e_usec_delay(10);
6546 * i40e_read_phy_register_clause45
6547 * @hw: pointer to the HW structure
6548 * @page: registers page number
6549 * @reg: register address in the page
6550 * @phy_addr: PHY address on MDIO interface
6551 * @value: PHY register value
6553 * Reads specified PHY register value
6555 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6556 u8 page, u16 reg, u8 phy_addr, u16 *value)
6558 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6561 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6563 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6564 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6565 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6566 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6567 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6568 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6569 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6570 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6572 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6573 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6574 status = I40E_SUCCESS;
6577 i40e_usec_delay(10);
6582 i40e_debug(hw, I40E_DEBUG_PHY,
6583 "PHY: Can't write command to external PHY.\n");
6587 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6588 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6589 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6590 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6591 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6592 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6593 status = I40E_ERR_TIMEOUT;
6595 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6597 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6598 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6599 status = I40E_SUCCESS;
6602 i40e_usec_delay(10);
6607 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6608 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6609 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6611 i40e_debug(hw, I40E_DEBUG_PHY,
6612 "PHY: Can't read register value from external PHY.\n");
6620 * i40e_write_phy_register_clause45
6621 * @hw: pointer to the HW structure
6622 * @page: registers page number
6623 * @reg: register address in the page
6624 * @phy_addr: PHY address on MDIO interface
6625 * @value: PHY register value
6627 * Writes value to specified PHY register
6629 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6630 u8 page, u16 reg, u8 phy_addr, u16 value)
6632 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6635 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6637 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6638 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6639 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6640 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6641 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6642 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6643 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6644 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6646 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6647 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6648 status = I40E_SUCCESS;
6651 i40e_usec_delay(10);
6655 i40e_debug(hw, I40E_DEBUG_PHY,
6656 "PHY: Can't write command to external PHY.\n");
6660 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6661 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6663 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6664 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6665 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6666 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6667 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6668 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6669 status = I40E_ERR_TIMEOUT;
6671 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6673 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6674 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6675 status = I40E_SUCCESS;
6678 i40e_usec_delay(10);
6687 * i40e_write_phy_register
6688 * @hw: pointer to the HW structure
6689 * @page: registers page number
6690 * @reg: register address in the page
6691 * @phy_addr: PHY address on MDIO interface
6692 * @value: PHY register value
6694 * Writes value to specified PHY register
6696 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6697 u8 page, u16 reg, u8 phy_addr, u16 value)
6699 enum i40e_status_code status;
6701 switch (hw->device_id) {
6702 case I40E_DEV_ID_1G_BASE_T_X722:
6703 status = i40e_write_phy_register_clause22(hw,
6704 reg, phy_addr, value);
6706 case I40E_DEV_ID_10G_BASE_T:
6707 case I40E_DEV_ID_10G_BASE_T4:
6708 case I40E_DEV_ID_10G_BASE_T_BC:
6709 case I40E_DEV_ID_10G_BASE_T_X722:
6710 case I40E_DEV_ID_25G_B:
6711 case I40E_DEV_ID_25G_SFP28:
6712 status = i40e_write_phy_register_clause45(hw,
6713 page, reg, phy_addr, value);
6716 status = I40E_ERR_UNKNOWN_PHY;
6724 * i40e_read_phy_register
6725 * @hw: pointer to the HW structure
6726 * @page: registers page number
6727 * @reg: register address in the page
6728 * @phy_addr: PHY address on MDIO interface
6729 * @value: PHY register value
6731 * Reads specified PHY register value
6733 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6734 u8 page, u16 reg, u8 phy_addr, u16 *value)
6736 enum i40e_status_code status;
6738 switch (hw->device_id) {
6739 case I40E_DEV_ID_1G_BASE_T_X722:
6740 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6743 case I40E_DEV_ID_10G_BASE_T:
6744 case I40E_DEV_ID_10G_BASE_T4:
6745 case I40E_DEV_ID_10G_BASE_T_X722:
6746 case I40E_DEV_ID_25G_B:
6747 case I40E_DEV_ID_25G_SFP28:
6748 status = i40e_read_phy_register_clause45(hw, page, reg,
6752 status = I40E_ERR_UNKNOWN_PHY;
6760 * i40e_get_phy_address
6761 * @hw: pointer to the HW structure
6762 * @dev_num: PHY port num that address we want
6764 * Gets PHY address for current port
6766 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6768 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6769 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6771 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6775 * i40e_blink_phy_led
6776 * @hw: pointer to the HW structure
6777 * @time: time how long led will blinks in secs
6778 * @interval: gap between LED on and off in msecs
6780 * Blinks PHY link LED
6782 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6783 u32 time, u32 interval)
6785 enum i40e_status_code status = I40E_SUCCESS;
6790 u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6794 i = rd32(hw, I40E_PFGEN_PORTNUM);
6795 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6796 phy_addr = i40e_get_phy_address(hw, port_num);
6798 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6800 status = i40e_read_phy_register_clause45(hw,
6801 I40E_PHY_COM_REG_PAGE,
6805 goto phy_blinking_end;
6807 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6809 status = i40e_write_phy_register_clause45(hw,
6810 I40E_PHY_COM_REG_PAGE,
6814 goto phy_blinking_end;
6819 if (time > 0 && interval > 0) {
6820 for (i = 0; i < time * 1000; i += interval) {
6821 status = i40e_read_phy_register_clause45(hw,
6822 I40E_PHY_COM_REG_PAGE,
6823 led_addr, phy_addr, &led_reg);
6825 goto restore_config;
6826 if (led_reg & I40E_PHY_LED_MANUAL_ON)
6829 led_reg = I40E_PHY_LED_MANUAL_ON;
6830 status = i40e_write_phy_register_clause45(hw,
6831 I40E_PHY_COM_REG_PAGE,
6832 led_addr, phy_addr, led_reg);
6834 goto restore_config;
6835 i40e_msec_delay(interval);
6840 status = i40e_write_phy_register_clause45(hw,
6841 I40E_PHY_COM_REG_PAGE,
6842 led_addr, phy_addr, led_ctl);
6849 * i40e_led_get_reg - read LED register
6850 * @hw: pointer to the HW structure
6851 * @led_addr: LED register address
6852 * @reg_val: read register value
6854 enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr,
6857 enum i40e_status_code status;
6861 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6862 status = i40e_aq_get_phy_register(hw,
6863 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6864 I40E_PHY_COM_REG_PAGE, true,
6865 I40E_PHY_LED_PROV_REG_1,
6868 phy_addr = i40e_get_phy_address(hw, hw->port);
6869 status = i40e_read_phy_register_clause45(hw,
6870 I40E_PHY_COM_REG_PAGE,
6878 * i40e_led_set_reg - write LED register
6879 * @hw: pointer to the HW structure
6880 * @led_addr: LED register address
6881 * @reg_val: register value to write
6883 enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr,
6886 enum i40e_status_code status;
6889 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6890 status = i40e_aq_set_phy_register(hw,
6891 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6892 I40E_PHY_COM_REG_PAGE, true,
6893 I40E_PHY_LED_PROV_REG_1,
6896 phy_addr = i40e_get_phy_address(hw, hw->port);
6897 status = i40e_write_phy_register_clause45(hw,
6898 I40E_PHY_COM_REG_PAGE,
6907 * i40e_led_get_phy - return current on/off mode
6908 * @hw: pointer to the hw struct
6909 * @led_addr: address of led register to use
6910 * @val: original value of register to use
6913 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6916 enum i40e_status_code status = I40E_SUCCESS;
6923 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6924 status = i40e_aq_get_phy_register(hw,
6925 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6926 I40E_PHY_COM_REG_PAGE, true,
6927 I40E_PHY_LED_PROV_REG_1,
6929 if (status == I40E_SUCCESS)
6930 *val = (u16)reg_val_aq;
6933 temp_addr = I40E_PHY_LED_PROV_REG_1;
6934 phy_addr = i40e_get_phy_address(hw, hw->port);
6935 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6937 status = i40e_read_phy_register_clause45(hw,
6938 I40E_PHY_COM_REG_PAGE,
6939 temp_addr, phy_addr,
6944 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6945 *led_addr = temp_addr;
6954 * @hw: pointer to the HW structure
6955 * @on: true or false
6956 * @led_addr: address of led register to use
6957 * @mode: original val plus bit for set or ignore
6959 * Set led's on or off when controlled by the PHY
6962 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6963 u16 led_addr, u32 mode)
6965 enum i40e_status_code status = I40E_SUCCESS;
6969 status = i40e_led_get_reg(hw, led_addr, &led_reg);
6973 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6975 status = i40e_led_set_reg(hw, led_addr, led_reg);
6979 status = i40e_led_get_reg(hw, led_addr, &led_reg);
6981 goto restore_config;
6983 led_reg = I40E_PHY_LED_MANUAL_ON;
6986 status = i40e_led_set_reg(hw, led_addr, led_reg);
6988 goto restore_config;
6989 if (mode & I40E_PHY_LED_MODE_ORIG) {
6990 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6991 status = i40e_led_set_reg(hw, led_addr, led_ctl);
6996 status = i40e_led_set_reg(hw, led_addr, led_ctl);
6999 #endif /* PF_DRIVER */
7001 * i40e_get_phy_lpi_status - read LPI status from PHY or MAC register
7002 * @hw: pointer to the hw struct
7003 * @stat: pointer to structure with status of rx and tx lpi
7005 * Read LPI state directly from external PHY register or from MAC
7006 * register, depending on device ID and current link speed.
7008 enum i40e_status_code i40e_get_phy_lpi_status(struct i40e_hw *hw,
7009 struct i40e_hw_port_stats *stat)
7011 enum i40e_status_code ret = I40E_SUCCESS;
7014 stat->rx_lpi_status = 0;
7015 stat->tx_lpi_status = 0;
7017 if (hw->device_id == I40E_DEV_ID_10G_BASE_T_BC &&
7018 (hw->phy.link_info.link_speed == I40E_LINK_SPEED_2_5GB ||
7019 hw->phy.link_info.link_speed == I40E_LINK_SPEED_5GB)) {
7020 ret = i40e_aq_get_phy_register(hw,
7021 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
7022 I40E_BCM_PHY_PCS_STATUS1_PAGE,
7024 I40E_BCM_PHY_PCS_STATUS1_REG,
7027 if (ret != I40E_SUCCESS)
7030 stat->rx_lpi_status = !!(val & I40E_BCM_PHY_PCS_STATUS1_RX_LPI);
7031 stat->tx_lpi_status = !!(val & I40E_BCM_PHY_PCS_STATUS1_TX_LPI);
7036 val = rd32(hw, I40E_PRTPM_EEE_STAT);
7037 stat->rx_lpi_status = (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
7038 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
7039 stat->tx_lpi_status = (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
7040 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
7046 * i40e_get_lpi_counters - read LPI counters from EEE statistics
7047 * @hw: pointer to the hw struct
7048 * @tx_counter: pointer to memory for TX LPI counter
7049 * @rx_counter: pointer to memory for RX LPI counter
7050 * @is_clear: returns true if counters are clear after read
7052 * Read Low Power Idle (LPI) mode counters from Energy Efficient
7053 * Ethernet (EEE) statistics.
7055 enum i40e_status_code i40e_get_lpi_counters(struct i40e_hw *hw,
7056 u32 *tx_counter, u32 *rx_counter,
7059 /* only X710-T*L requires special handling of counters
7060 * for other devices we just read the MAC registers
7062 if (hw->device_id == I40E_DEV_ID_10G_BASE_T_BC &&
7063 hw->phy.link_info.link_speed != I40E_LINK_SPEED_1GB) {
7064 enum i40e_status_code retval;
7068 retval = i40e_aq_run_phy_activity(hw,
7069 I40E_AQ_RUN_PHY_ACT_ID_USR_DFND,
7070 I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_STAT,
7071 &cmd_status, tx_counter, rx_counter, NULL);
7073 if (cmd_status != I40E_AQ_RUN_PHY_ACT_CMD_STAT_SUCC)
7074 retval = I40E_ERR_ADMIN_QUEUE_ERROR;
7080 *tx_counter = rd32(hw, I40E_PRTPM_TLPIC);
7081 *rx_counter = rd32(hw, I40E_PRTPM_RLPIC);
7083 return I40E_SUCCESS;
7087 * i40e_get_lpi_duration - read LPI time duration from EEE statistics
7088 * @hw: pointer to the hw struct
7089 * @stat: pointer to structure with status of rx and tx lpi
7090 * @tx_duration: pointer to memory for TX LPI time duration
7091 * @rx_duration: pointer to memory for RX LPI time duration
7093 * Read Low Power Idle (LPI) mode time duration from Energy Efficient
7094 * Ethernet (EEE) statistics.
7096 enum i40e_status_code i40e_get_lpi_duration(struct i40e_hw *hw,
7097 struct i40e_hw_port_stats *stat,
7098 u64 *tx_duration, u64 *rx_duration)
7100 u32 tx_time_dur, rx_time_dur;
7101 enum i40e_status_code retval;
7104 if (hw->device_id != I40E_DEV_ID_10G_BASE_T_BC)
7105 return I40E_ERR_NOT_IMPLEMENTED;
7107 retval = i40e_aq_run_phy_activity
7108 (hw, I40E_AQ_RUN_PHY_ACT_ID_USR_DFND,
7109 I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_DUR,
7110 &cmd_status, &tx_time_dur, &rx_time_dur, NULL);
7114 if ((cmd_status & I40E_AQ_RUN_PHY_ACT_CMD_STAT_MASK) !=
7115 I40E_AQ_RUN_PHY_ACT_CMD_STAT_SUCC)
7116 return I40E_ERR_ADMIN_QUEUE_ERROR;
7118 if (hw->phy.link_info.link_speed == I40E_LINK_SPEED_1GB &&
7119 !tx_time_dur && !rx_time_dur &&
7120 stat->tx_lpi_status && stat->rx_lpi_status) {
7121 retval = i40e_aq_run_phy_activity
7122 (hw, I40E_AQ_RUN_PHY_ACT_ID_USR_DFND,
7123 I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_STAT_DUR,
7125 &tx_time_dur, &rx_time_dur, NULL);
7129 if ((cmd_status & I40E_AQ_RUN_PHY_ACT_CMD_STAT_MASK) !=
7130 I40E_AQ_RUN_PHY_ACT_CMD_STAT_SUCC)
7131 return I40E_ERR_ADMIN_QUEUE_ERROR;
7136 *tx_duration = tx_time_dur;
7137 *rx_duration = rx_time_dur;
7143 * i40e_lpi_stat_update - update LPI counters with values relative to offset
7144 * @hw: pointer to the hw struct
7145 * @offset_loaded: flag indicating need of writing current value to offset
7146 * @tx_offset: pointer to offset of TX LPI counter
7147 * @tx_stat: pointer to value of TX LPI counter
7148 * @rx_offset: pointer to offset of RX LPI counter
7149 * @rx_stat: pointer to value of RX LPI counter
7151 * Update Low Power Idle (LPI) mode counters while having regard to passed
7154 enum i40e_status_code i40e_lpi_stat_update(struct i40e_hw *hw,
7155 bool offset_loaded, u64 *tx_offset,
7156 u64 *tx_stat, u64 *rx_offset,
7159 enum i40e_status_code retval;
7160 u32 tx_counter, rx_counter;
7163 retval = i40e_get_lpi_counters(hw, &tx_counter, &rx_counter, &is_clear);
7168 *tx_stat += tx_counter;
7169 *rx_stat += rx_counter;
7171 if (!offset_loaded) {
7172 *tx_offset = tx_counter;
7173 *rx_offset = rx_counter;
7176 *tx_stat = (tx_counter >= *tx_offset) ?
7177 (u32)(tx_counter - *tx_offset) :
7178 (u32)((tx_counter + BIT_ULL(32)) - *tx_offset);
7179 *rx_stat = (rx_counter >= *rx_offset) ?
7180 (u32)(rx_counter - *rx_offset) :
7181 (u32)((rx_counter + BIT_ULL(32)) - *rx_offset);
7188 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
7189 * @hw: pointer to the hw struct
7190 * @reg_addr: register address
7191 * @reg_val: ptr to register value
7192 * @cmd_details: pointer to command details structure or NULL
7194 * Use the firmware to read the Rx control register,
7195 * especially useful if the Rx unit is under heavy pressure
7197 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
7198 u32 reg_addr, u32 *reg_val,
7199 struct i40e_asq_cmd_details *cmd_details)
7201 struct i40e_aq_desc desc;
7202 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
7203 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
7204 enum i40e_status_code status;
7206 if (reg_val == NULL)
7207 return I40E_ERR_PARAM;
7209 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
7211 cmd_resp->address = CPU_TO_LE32(reg_addr);
7213 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7215 if (status == I40E_SUCCESS)
7216 *reg_val = LE32_TO_CPU(cmd_resp->value);
7222 * i40e_read_rx_ctl - read from an Rx control register
7223 * @hw: pointer to the hw struct
7224 * @reg_addr: register address
7226 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
7228 enum i40e_status_code status = I40E_SUCCESS;
7233 use_register = (((hw->aq.api_maj_ver == 1) &&
7234 (hw->aq.api_min_ver < 5)) ||
7235 (hw->mac.type == I40E_MAC_X722));
7236 if (!use_register) {
7238 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
7239 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
7246 /* if the AQ access failed, try the old-fashioned way */
7247 if (status || use_register)
7248 val = rd32(hw, reg_addr);
7254 * i40e_aq_rx_ctl_write_register
7255 * @hw: pointer to the hw struct
7256 * @reg_addr: register address
7257 * @reg_val: register value
7258 * @cmd_details: pointer to command details structure or NULL
7260 * Use the firmware to write to an Rx control register,
7261 * especially useful if the Rx unit is under heavy pressure
7263 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
7264 u32 reg_addr, u32 reg_val,
7265 struct i40e_asq_cmd_details *cmd_details)
7267 struct i40e_aq_desc desc;
7268 struct i40e_aqc_rx_ctl_reg_read_write *cmd =
7269 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
7270 enum i40e_status_code status;
7272 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
7274 cmd->address = CPU_TO_LE32(reg_addr);
7275 cmd->value = CPU_TO_LE32(reg_val);
7277 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7283 * i40e_write_rx_ctl - write to an Rx control register
7284 * @hw: pointer to the hw struct
7285 * @reg_addr: register address
7286 * @reg_val: register value
7288 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
7290 enum i40e_status_code status = I40E_SUCCESS;
7294 use_register = (((hw->aq.api_maj_ver == 1) &&
7295 (hw->aq.api_min_ver < 5)) ||
7296 (hw->mac.type == I40E_MAC_X722));
7297 if (!use_register) {
7299 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
7301 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
7308 /* if the AQ access failed, try the old-fashioned way */
7309 if (status || use_register)
7310 wr32(hw, reg_addr, reg_val);
7314 * i40e_mdio_if_number_selection - MDIO I/F number selection
7315 * @hw: pointer to the hw struct
7316 * @set_mdio: use MDIO I/F number specified by mdio_num
7317 * @mdio_num: MDIO I/F number
7318 * @cmd: pointer to PHY Register command structure
7321 i40e_mdio_if_number_selection(struct i40e_hw *hw, bool set_mdio, u8 mdio_num,
7322 struct i40e_aqc_phy_register_access *cmd)
7324 if (set_mdio && cmd->phy_interface == I40E_AQ_PHY_REG_ACCESS_EXTERNAL) {
7325 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_EXTENDED)
7327 I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER |
7329 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT) &
7330 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK);
7332 i40e_debug(hw, I40E_DEBUG_PHY,
7333 "MDIO I/F number selection not supported by current FW version.\n");
7338 * i40e_aq_set_phy_register_ext
7339 * @hw: pointer to the hw struct
7340 * @phy_select: select which phy should be accessed
7341 * @dev_addr: PHY device address
7342 * @page_change: enable auto page change
7343 * @set_mdio: use MDIO I/F number specified by mdio_num
7344 * @mdio_num: MDIO I/F number
7345 * @reg_addr: PHY register address
7346 * @reg_val: new register value
7347 * @cmd_details: pointer to command details structure or NULL
7349 * Write the external PHY register.
7350 * NOTE: In common cases MDIO I/F number should not be changed, thats why you
7351 * may use simple wrapper i40e_aq_set_phy_register.
7353 enum i40e_status_code
7354 i40e_aq_set_phy_register_ext(struct i40e_hw *hw,
7355 u8 phy_select, u8 dev_addr, bool page_change,
7356 bool set_mdio, u8 mdio_num,
7357 u32 reg_addr, u32 reg_val,
7358 struct i40e_asq_cmd_details *cmd_details)
7360 struct i40e_aq_desc desc;
7361 struct i40e_aqc_phy_register_access *cmd =
7362 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7363 enum i40e_status_code status;
7365 i40e_fill_default_direct_cmd_desc(&desc,
7366 i40e_aqc_opc_set_phy_register);
7368 cmd->phy_interface = phy_select;
7369 cmd->dev_addres = dev_addr;
7370 cmd->reg_address = CPU_TO_LE32(reg_addr);
7371 cmd->reg_value = CPU_TO_LE32(reg_val);
7374 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
7376 i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd);
7378 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7384 * i40e_aq_get_phy_register_ext
7385 * @hw: pointer to the hw struct
7386 * @phy_select: select which phy should be accessed
7387 * @dev_addr: PHY device address
7388 * @page_change: enable auto page change
7389 * @set_mdio: use MDIO I/F number specified by mdio_num
7390 * @mdio_num: MDIO I/F number
7391 * @reg_addr: PHY register address
7392 * @reg_val: read register value
7393 * @cmd_details: pointer to command details structure or NULL
7395 * Read the external PHY register.
7396 * NOTE: In common cases MDIO I/F number should not be changed, thats why you
7397 * may use simple wrapper i40e_aq_get_phy_register.
7399 enum i40e_status_code
7400 i40e_aq_get_phy_register_ext(struct i40e_hw *hw,
7401 u8 phy_select, u8 dev_addr, bool page_change,
7402 bool set_mdio, u8 mdio_num,
7403 u32 reg_addr, u32 *reg_val,
7404 struct i40e_asq_cmd_details *cmd_details)
7406 struct i40e_aq_desc desc;
7407 struct i40e_aqc_phy_register_access *cmd =
7408 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7409 enum i40e_status_code status;
7411 i40e_fill_default_direct_cmd_desc(&desc,
7412 i40e_aqc_opc_get_phy_register);
7414 cmd->phy_interface = phy_select;
7415 cmd->dev_addres = dev_addr;
7416 cmd->reg_address = CPU_TO_LE32(reg_addr);
7419 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
7421 i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd);
7423 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7425 *reg_val = LE32_TO_CPU(cmd->reg_value);
7431 * i40e_aq_run_phy_activity
7432 * @hw: pointer to the hw struct
7433 * @activity_id: ID of DNL activity to run
7434 * @dnl_opcode: opcode passed to DNL script
7435 * @cmd_status: pointer to memory to write return value of DNL script
7436 * @data0: pointer to memory for first 4 bytes of data returned by DNL script
7437 * @data1: pointer to memory for last 4 bytes of data returned by DNL script
7438 * @cmd_details: pointer to command details structure or NULL
7440 * Run DNL admin command.
7442 enum i40e_status_code
7443 i40e_aq_run_phy_activity(struct i40e_hw *hw, u16 activity_id, u32 dnl_opcode,
7444 u32 *cmd_status, u32 *data0, u32 *data1,
7445 struct i40e_asq_cmd_details *cmd_details)
7447 struct i40e_aqc_run_phy_activity *cmd;
7448 enum i40e_status_code retval;
7449 struct i40e_aq_desc desc;
7451 cmd = (struct i40e_aqc_run_phy_activity *)&desc.params.raw;
7453 if (!cmd_status || !data0 || !data1) {
7454 retval = I40E_ERR_PARAM;
7458 i40e_fill_default_direct_cmd_desc(&desc,
7459 i40e_aqc_opc_run_phy_activity);
7461 cmd->activity_id = CPU_TO_LE16(activity_id);
7462 cmd->params.cmd.dnl_opcode = CPU_TO_LE32(dnl_opcode);
7464 retval = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7468 *cmd_status = LE32_TO_CPU(cmd->params.resp.cmd_status);
7469 *data0 = LE32_TO_CPU(cmd->params.resp.data0);
7470 *data1 = LE32_TO_CPU(cmd->params.resp.data1);
7478 * i40e_aq_send_msg_to_pf
7479 * @hw: pointer to the hardware structure
7480 * @v_opcode: opcodes for VF-PF communication
7481 * @v_retval: return error code
7482 * @msg: pointer to the msg buffer
7483 * @msglen: msg length
7484 * @cmd_details: pointer to command details
7486 * Send message to PF driver using admin queue. By default, this message
7487 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
7488 * completion before returning.
7490 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
7491 enum virtchnl_ops v_opcode,
7492 enum i40e_status_code v_retval,
7493 u8 *msg, u16 msglen,
7494 struct i40e_asq_cmd_details *cmd_details)
7496 struct i40e_aq_desc desc;
7497 struct i40e_asq_cmd_details details;
7498 enum i40e_status_code status;
7500 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
7501 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
7502 desc.cookie_high = CPU_TO_LE32(v_opcode);
7503 desc.cookie_low = CPU_TO_LE32(v_retval);
7505 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
7506 | I40E_AQ_FLAG_RD));
7507 if (msglen > I40E_AQ_LARGE_BUF)
7508 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7509 desc.datalen = CPU_TO_LE16(msglen);
7512 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
7513 details.async = true;
7514 cmd_details = &details;
7516 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
7517 msglen, cmd_details);
7522 * i40e_vf_parse_hw_config
7523 * @hw: pointer to the hardware structure
7524 * @msg: pointer to the virtual channel VF resource structure
7526 * Given a VF resource message from the PF, populate the hw struct
7527 * with appropriate information.
7529 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
7530 struct virtchnl_vf_resource *msg)
7532 struct virtchnl_vsi_resource *vsi_res;
7535 vsi_res = &msg->vsi_res[0];
7537 hw->dev_caps.num_vsis = msg->num_vsis;
7538 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
7539 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
7540 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
7541 hw->dev_caps.dcb = msg->vf_cap_flags &
7542 VIRTCHNL_VF_OFFLOAD_L2;
7543 hw->dev_caps.iwarp = (msg->vf_cap_flags &
7544 VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
7545 for (i = 0; i < msg->num_vsis; i++) {
7546 if (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) {
7547 i40e_memcpy(hw->mac.perm_addr,
7548 vsi_res->default_mac_addr,
7550 I40E_NONDMA_TO_NONDMA);
7551 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
7553 I40E_NONDMA_TO_NONDMA);
7561 * @hw: pointer to the hardware structure
7563 * Send a VF_RESET message to the PF. Does not wait for response from PF
7564 * as none will be forthcoming. Immediately after calling this function,
7565 * the admin queue should be shut down and (optionally) reinitialized.
7567 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
7569 return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF,
7570 I40E_SUCCESS, NULL, 0, NULL);
7572 #endif /* VF_DRIVER */
7575 * i40e_aq_set_arp_proxy_config
7576 * @hw: pointer to the HW structure
7577 * @proxy_config: pointer to proxy config command table struct
7578 * @cmd_details: pointer to command details
7580 * Set ARP offload parameters from pre-populated
7581 * i40e_aqc_arp_proxy_data struct
7583 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
7584 struct i40e_aqc_arp_proxy_data *proxy_config,
7585 struct i40e_asq_cmd_details *cmd_details)
7587 struct i40e_aq_desc desc;
7588 enum i40e_status_code status;
7591 return I40E_ERR_PARAM;
7593 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
7595 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7596 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7597 desc.params.external.addr_high =
7598 CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
7599 desc.params.external.addr_low =
7600 CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
7601 desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_arp_proxy_data));
7603 status = i40e_asq_send_command(hw, &desc, proxy_config,
7604 sizeof(struct i40e_aqc_arp_proxy_data),
7611 * i40e_aq_opc_set_ns_proxy_table_entry
7612 * @hw: pointer to the HW structure
7613 * @ns_proxy_table_entry: pointer to NS table entry command struct
7614 * @cmd_details: pointer to command details
7616 * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
7617 * from pre-populated i40e_aqc_ns_proxy_data struct
7619 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
7620 struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
7621 struct i40e_asq_cmd_details *cmd_details)
7623 struct i40e_aq_desc desc;
7624 enum i40e_status_code status;
7626 if (!ns_proxy_table_entry)
7627 return I40E_ERR_PARAM;
7629 i40e_fill_default_direct_cmd_desc(&desc,
7630 i40e_aqc_opc_set_ns_proxy_table_entry);
7632 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7633 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7634 desc.params.external.addr_high =
7635 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
7636 desc.params.external.addr_low =
7637 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
7638 desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_ns_proxy_data));
7640 status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
7641 sizeof(struct i40e_aqc_ns_proxy_data),
7648 * i40e_aq_set_clear_wol_filter
7649 * @hw: pointer to the hw struct
7650 * @filter_index: index of filter to modify (0-7)
7651 * @filter: buffer containing filter to be set
7652 * @set_filter: true to set filter, false to clear filter
7653 * @no_wol_tco: if true, pass through packets cannot cause wake-up
7654 * if false, pass through packets may cause wake-up
7655 * @filter_valid: true if filter action is valid
7656 * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
7657 * @cmd_details: pointer to command details structure or NULL
7659 * Set or clear WoL filter for port attached to the PF
7661 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
7663 struct i40e_aqc_set_wol_filter_data *filter,
7664 bool set_filter, bool no_wol_tco,
7665 bool filter_valid, bool no_wol_tco_valid,
7666 struct i40e_asq_cmd_details *cmd_details)
7668 struct i40e_aq_desc desc;
7669 struct i40e_aqc_set_wol_filter *cmd =
7670 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
7671 enum i40e_status_code status;
7673 u16 valid_flags = 0;
7676 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
7678 if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
7679 return I40E_ERR_PARAM;
7680 cmd->filter_index = CPU_TO_LE16(filter_index);
7684 return I40E_ERR_PARAM;
7686 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
7687 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR;
7691 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
7692 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
7695 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
7696 if (no_wol_tco_valid)
7697 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
7698 cmd->valid_flags = CPU_TO_LE16(valid_flags);
7700 buff_len = sizeof(*filter);
7701 desc.datalen = CPU_TO_LE16(buff_len);
7703 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7704 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7706 cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
7707 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
7709 status = i40e_asq_send_command(hw, &desc, filter,
7710 buff_len, cmd_details);
7716 * i40e_aq_get_wake_event_reason
7717 * @hw: pointer to the hw struct
7718 * @wake_reason: return value, index of matching filter
7719 * @cmd_details: pointer to command details structure or NULL
7721 * Get information for the reason of a Wake Up event
7723 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
7725 struct i40e_asq_cmd_details *cmd_details)
7727 struct i40e_aq_desc desc;
7728 struct i40e_aqc_get_wake_reason_completion *resp =
7729 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
7730 enum i40e_status_code status;
7732 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
7734 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7736 if (status == I40E_SUCCESS)
7737 *wake_reason = LE16_TO_CPU(resp->wake_reason);
7743 * i40e_aq_clear_all_wol_filters
7744 * @hw: pointer to the hw struct
7745 * @cmd_details: pointer to command details structure or NULL
7747 * Get information for the reason of a Wake Up event
7749 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw,
7750 struct i40e_asq_cmd_details *cmd_details)
7752 struct i40e_aq_desc desc;
7753 enum i40e_status_code status;
7755 i40e_fill_default_direct_cmd_desc(&desc,
7756 i40e_aqc_opc_clear_all_wol_filters);
7758 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7764 * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
7765 * @hw: pointer to the hw struct
7766 * @buff: command buffer (size in bytes = buff_size)
7767 * @buff_size: buffer size in bytes
7768 * @track_id: package tracking id
7769 * @error_offset: returns error offset
7770 * @error_info: returns error information
7771 * @cmd_details: pointer to command details structure or NULL
7774 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
7775 u16 buff_size, u32 track_id,
7776 u32 *error_offset, u32 *error_info,
7777 struct i40e_asq_cmd_details *cmd_details)
7779 struct i40e_aq_desc desc;
7780 struct i40e_aqc_write_personalization_profile *cmd =
7781 (struct i40e_aqc_write_personalization_profile *)
7783 struct i40e_aqc_write_ddp_resp *resp;
7784 enum i40e_status_code status;
7786 i40e_fill_default_direct_cmd_desc(&desc,
7787 i40e_aqc_opc_write_personalization_profile);
7789 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
7790 if (buff_size > I40E_AQ_LARGE_BUF)
7791 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7793 desc.datalen = CPU_TO_LE16(buff_size);
7795 cmd->profile_track_id = CPU_TO_LE32(track_id);
7797 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7799 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
7801 *error_offset = LE32_TO_CPU(resp->error_offset);
7803 *error_info = LE32_TO_CPU(resp->error_info);
7810 * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
7811 * @hw: pointer to the hw struct
7812 * @buff: command buffer (size in bytes = buff_size)
7813 * @buff_size: buffer size in bytes
7814 * @flags: AdminQ command flags
7815 * @cmd_details: pointer to command details structure or NULL
7818 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
7819 u16 buff_size, u8 flags,
7820 struct i40e_asq_cmd_details *cmd_details)
7822 struct i40e_aq_desc desc;
7823 struct i40e_aqc_get_applied_profiles *cmd =
7824 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
7825 enum i40e_status_code status;
7827 i40e_fill_default_direct_cmd_desc(&desc,
7828 i40e_aqc_opc_get_personalization_profile_list);
7830 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7831 if (buff_size > I40E_AQ_LARGE_BUF)
7832 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7833 desc.datalen = CPU_TO_LE16(buff_size);
7837 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7843 * i40e_find_segment_in_package
7844 * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
7845 * @pkg_hdr: pointer to the package header to be searched
7847 * This function searches a package file for a particular segment type. On
7848 * success it returns a pointer to the segment header, otherwise it will
7851 struct i40e_generic_seg_header *
7852 i40e_find_segment_in_package(u32 segment_type,
7853 struct i40e_package_header *pkg_hdr)
7855 struct i40e_generic_seg_header *segment;
7858 /* Search all package segments for the requested segment type */
7859 for (i = 0; i < pkg_hdr->segment_count; i++) {
7861 (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
7862 pkg_hdr->segment_offset[i]);
7864 if (segment->type == segment_type)
7871 /* Get section table in profile */
7872 #define I40E_SECTION_TABLE(profile, sec_tbl) \
7874 struct i40e_profile_segment *p = (profile); \
7877 count = p->device_table_count; \
7878 nvm = (u32 *)&p->device_table[count]; \
7879 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \
7882 /* Get section header in profile */
7883 #define I40E_SECTION_HEADER(profile, offset) \
7884 (struct i40e_profile_section_header *)((u8 *)(profile) + (offset))
7887 * i40e_find_section_in_profile
7888 * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE)
7889 * @profile: pointer to the i40e segment header to be searched
7891 * This function searches i40e segment for a particular section type. On
7892 * success it returns a pointer to the section header, otherwise it will
7895 struct i40e_profile_section_header *
7896 i40e_find_section_in_profile(u32 section_type,
7897 struct i40e_profile_segment *profile)
7899 struct i40e_profile_section_header *sec;
7900 struct i40e_section_table *sec_tbl;
7904 if (profile->header.type != SEGMENT_TYPE_I40E)
7907 I40E_SECTION_TABLE(profile, sec_tbl);
7909 for (i = 0; i < sec_tbl->section_count; i++) {
7910 sec_off = sec_tbl->section_offset[i];
7911 sec = I40E_SECTION_HEADER(profile, sec_off);
7912 if (sec->section.type == section_type)
7920 * i40e_ddp_exec_aq_section - Execute generic AQ for DDP
7921 * @hw: pointer to the hw struct
7922 * @aq: command buffer containing all data to execute AQ
7925 i40e_status_code i40e_ddp_exec_aq_section(struct i40e_hw *hw,
7926 struct i40e_profile_aq_section *aq)
7928 enum i40e_status_code status;
7929 struct i40e_aq_desc desc;
7933 i40e_fill_default_direct_cmd_desc(&desc, aq->opcode);
7934 desc.flags |= CPU_TO_LE16(aq->flags);
7935 i40e_memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw),
7936 I40E_NONDMA_TO_NONDMA);
7938 msglen = aq->datalen;
7940 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
7942 if (msglen > I40E_AQ_LARGE_BUF)
7943 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7944 desc.datalen = CPU_TO_LE16(msglen);
7948 status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL);
7950 if (status != I40E_SUCCESS) {
7951 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7952 "unable to exec DDP AQ opcode %u, error %d\n",
7953 aq->opcode, status);
7957 /* copy returned desc to aq_buf */
7958 i40e_memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw),
7959 I40E_NONDMA_TO_NONDMA);
7961 return I40E_SUCCESS;
7965 * i40e_validate_profile
7966 * @hw: pointer to the hardware structure
7967 * @profile: pointer to the profile segment of the package to be validated
7968 * @track_id: package tracking id
7969 * @rollback: flag if the profile is for rollback.
7971 * Validates supported devices and profile's sections.
7973 STATIC enum i40e_status_code
7974 i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7975 u32 track_id, bool rollback)
7977 struct i40e_profile_section_header *sec = NULL;
7978 enum i40e_status_code status = I40E_SUCCESS;
7979 struct i40e_section_table *sec_tbl;
7985 if (track_id == I40E_DDP_TRACKID_INVALID) {
7986 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n");
7987 return I40E_NOT_SUPPORTED;
7990 dev_cnt = profile->device_table_count;
7991 for (i = 0; i < dev_cnt; i++) {
7992 vendor_dev_id = profile->device_table[i].vendor_dev_id;
7993 if ((vendor_dev_id >> 16) == I40E_INTEL_VENDOR_ID &&
7994 hw->device_id == (vendor_dev_id & 0xFFFF))
7997 if (dev_cnt && (i == dev_cnt)) {
7998 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7999 "Device doesn't support DDP\n");
8000 return I40E_ERR_DEVICE_NOT_SUPPORTED;
8003 I40E_SECTION_TABLE(profile, sec_tbl);
8005 /* Validate sections types */
8006 for (i = 0; i < sec_tbl->section_count; i++) {
8007 sec_off = sec_tbl->section_offset[i];
8008 sec = I40E_SECTION_HEADER(profile, sec_off);
8010 if (sec->section.type == SECTION_TYPE_MMIO ||
8011 sec->section.type == SECTION_TYPE_AQ ||
8012 sec->section.type == SECTION_TYPE_RB_AQ) {
8013 i40e_debug(hw, I40E_DEBUG_PACKAGE,
8014 "Not a roll-back package\n");
8015 return I40E_NOT_SUPPORTED;
8018 if (sec->section.type == SECTION_TYPE_RB_AQ ||
8019 sec->section.type == SECTION_TYPE_RB_MMIO) {
8020 i40e_debug(hw, I40E_DEBUG_PACKAGE,
8021 "Not an original package\n");
8022 return I40E_NOT_SUPPORTED;
8031 * i40e_write_profile
8032 * @hw: pointer to the hardware structure
8033 * @profile: pointer to the profile segment of the package to be downloaded
8034 * @track_id: package tracking id
8036 * Handles the download of a complete package.
8038 enum i40e_status_code
8039 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
8042 enum i40e_status_code status = I40E_SUCCESS;
8043 struct i40e_section_table *sec_tbl;
8044 struct i40e_profile_section_header *sec = NULL;
8045 struct i40e_profile_aq_section *ddp_aq;
8046 u32 section_size = 0;
8047 u32 offset = 0, info = 0;
8051 status = i40e_validate_profile(hw, profile, track_id, false);
8055 I40E_SECTION_TABLE(profile, sec_tbl);
8057 for (i = 0; i < sec_tbl->section_count; i++) {
8058 sec_off = sec_tbl->section_offset[i];
8059 sec = I40E_SECTION_HEADER(profile, sec_off);
8060 /* Process generic admin command */
8061 if (sec->section.type == SECTION_TYPE_AQ) {
8062 ddp_aq = (struct i40e_profile_aq_section *)&sec[1];
8063 status = i40e_ddp_exec_aq_section(hw, ddp_aq);
8065 i40e_debug(hw, I40E_DEBUG_PACKAGE,
8066 "Failed to execute aq: section %d, opcode %u\n",
8070 sec->section.type = SECTION_TYPE_RB_AQ;
8073 /* Skip any non-mmio sections */
8074 if (sec->section.type != SECTION_TYPE_MMIO)
8077 section_size = sec->section.size +
8078 sizeof(struct i40e_profile_section_header);
8080 /* Write MMIO section */
8081 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
8082 track_id, &offset, &info, NULL);
8084 i40e_debug(hw, I40E_DEBUG_PACKAGE,
8085 "Failed to write profile: section %d, offset %d, info %d\n",
8094 * i40e_rollback_profile
8095 * @hw: pointer to the hardware structure
8096 * @profile: pointer to the profile segment of the package to be removed
8097 * @track_id: package tracking id
8099 * Rolls back previously loaded package.
8101 enum i40e_status_code
8102 i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
8105 struct i40e_profile_section_header *sec = NULL;
8106 enum i40e_status_code status = I40E_SUCCESS;
8107 struct i40e_section_table *sec_tbl;
8108 u32 offset = 0, info = 0;
8109 u32 section_size = 0;
8113 status = i40e_validate_profile(hw, profile, track_id, true);
8117 I40E_SECTION_TABLE(profile, sec_tbl);
8119 /* For rollback write sections in reverse */
8120 for (i = sec_tbl->section_count - 1; i >= 0; i--) {
8121 sec_off = sec_tbl->section_offset[i];
8122 sec = I40E_SECTION_HEADER(profile, sec_off);
8124 /* Skip any non-rollback sections */
8125 if (sec->section.type != SECTION_TYPE_RB_MMIO)
8128 section_size = sec->section.size +
8129 sizeof(struct i40e_profile_section_header);
8131 /* Write roll-back MMIO section */
8132 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
8133 track_id, &offset, &info, NULL);
8135 i40e_debug(hw, I40E_DEBUG_PACKAGE,
8136 "Failed to write profile: section %d, offset %d, info %d\n",
8145 * i40e_add_pinfo_to_list
8146 * @hw: pointer to the hardware structure
8147 * @profile: pointer to the profile segment of the package
8148 * @profile_info_sec: buffer for information section
8149 * @track_id: package tracking id
8151 * Register a profile to the list of loaded profiles.
8153 enum i40e_status_code
8154 i40e_add_pinfo_to_list(struct i40e_hw *hw,
8155 struct i40e_profile_segment *profile,
8156 u8 *profile_info_sec, u32 track_id)
8158 enum i40e_status_code status = I40E_SUCCESS;
8159 struct i40e_profile_section_header *sec = NULL;
8160 struct i40e_profile_info *pinfo;
8161 u32 offset = 0, info = 0;
8163 sec = (struct i40e_profile_section_header *)profile_info_sec;
8165 sec->data_end = sizeof(struct i40e_profile_section_header) +
8166 sizeof(struct i40e_profile_info);
8167 sec->section.type = SECTION_TYPE_INFO;
8168 sec->section.offset = sizeof(struct i40e_profile_section_header);
8169 sec->section.size = sizeof(struct i40e_profile_info);
8170 pinfo = (struct i40e_profile_info *)(profile_info_sec +
8171 sec->section.offset);
8172 pinfo->track_id = track_id;
8173 pinfo->version = profile->version;
8174 pinfo->op = I40E_DDP_ADD_TRACKID;
8175 i40e_memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE,
8176 I40E_NONDMA_TO_NONDMA);
8178 status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
8179 track_id, &offset, &info, NULL);