1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "i40e_type.h"
35 #include "i40e_adminq.h"
36 #include "i40e_prototype.h"
37 #include "i40e_virtchnl.h"
41 * i40e_set_mac_type - Sets MAC type
42 * @hw: pointer to the HW structure
44 * This function sets the mac type of the adapter based on the
45 * vendor ID and device ID stored in the hw structure.
47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
53 enum i40e_status_code status = I40E_SUCCESS;
55 DEBUGFUNC("i40e_set_mac_type\n");
57 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
58 switch (hw->device_id) {
59 case I40E_DEV_ID_SFP_XL710:
60 case I40E_DEV_ID_QEMU:
61 case I40E_DEV_ID_KX_B:
62 case I40E_DEV_ID_KX_C:
63 case I40E_DEV_ID_QSFP_A:
64 case I40E_DEV_ID_QSFP_B:
65 case I40E_DEV_ID_QSFP_C:
66 case I40E_DEV_ID_10G_BASE_T:
67 case I40E_DEV_ID_10G_BASE_T4:
68 case I40E_DEV_ID_20G_KR2:
69 case I40E_DEV_ID_20G_KR2_A:
70 case I40E_DEV_ID_25G_B:
71 case I40E_DEV_ID_25G_SFP28:
72 hw->mac.type = I40E_MAC_XL710;
75 #ifdef X722_A0_SUPPORT
76 case I40E_DEV_ID_X722_A0:
78 case I40E_DEV_ID_KX_X722:
79 case I40E_DEV_ID_QSFP_X722:
80 case I40E_DEV_ID_SFP_X722:
81 case I40E_DEV_ID_1G_BASE_T_X722:
82 case I40E_DEV_ID_10G_BASE_T_X722:
83 case I40E_DEV_ID_SFP_I_X722:
84 hw->mac.type = I40E_MAC_X722;
88 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
89 case I40E_DEV_ID_X722_VF:
90 case I40E_DEV_ID_X722_VF_HV:
91 #ifdef X722_A0_SUPPORT
92 case I40E_DEV_ID_X722_A0_VF:
94 hw->mac.type = I40E_MAC_X722_VF;
96 #endif /* INTEGRATED_VF || VF_DRIVER */
97 #endif /* X722_SUPPORT */
98 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
100 case I40E_DEV_ID_VF_HV:
101 hw->mac.type = I40E_MAC_VF;
105 hw->mac.type = I40E_MAC_GENERIC;
109 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
112 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
113 hw->mac.type, status);
117 #ifndef I40E_NDIS_SUPPORT
119 * i40e_aq_str - convert AQ err code to a string
120 * @hw: pointer to the HW structure
121 * @aq_err: the AQ error code to convert
123 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
128 case I40E_AQ_RC_EPERM:
129 return "I40E_AQ_RC_EPERM";
130 case I40E_AQ_RC_ENOENT:
131 return "I40E_AQ_RC_ENOENT";
132 case I40E_AQ_RC_ESRCH:
133 return "I40E_AQ_RC_ESRCH";
134 case I40E_AQ_RC_EINTR:
135 return "I40E_AQ_RC_EINTR";
137 return "I40E_AQ_RC_EIO";
138 case I40E_AQ_RC_ENXIO:
139 return "I40E_AQ_RC_ENXIO";
140 case I40E_AQ_RC_E2BIG:
141 return "I40E_AQ_RC_E2BIG";
142 case I40E_AQ_RC_EAGAIN:
143 return "I40E_AQ_RC_EAGAIN";
144 case I40E_AQ_RC_ENOMEM:
145 return "I40E_AQ_RC_ENOMEM";
146 case I40E_AQ_RC_EACCES:
147 return "I40E_AQ_RC_EACCES";
148 case I40E_AQ_RC_EFAULT:
149 return "I40E_AQ_RC_EFAULT";
150 case I40E_AQ_RC_EBUSY:
151 return "I40E_AQ_RC_EBUSY";
152 case I40E_AQ_RC_EEXIST:
153 return "I40E_AQ_RC_EEXIST";
154 case I40E_AQ_RC_EINVAL:
155 return "I40E_AQ_RC_EINVAL";
156 case I40E_AQ_RC_ENOTTY:
157 return "I40E_AQ_RC_ENOTTY";
158 case I40E_AQ_RC_ENOSPC:
159 return "I40E_AQ_RC_ENOSPC";
160 case I40E_AQ_RC_ENOSYS:
161 return "I40E_AQ_RC_ENOSYS";
162 case I40E_AQ_RC_ERANGE:
163 return "I40E_AQ_RC_ERANGE";
164 case I40E_AQ_RC_EFLUSHED:
165 return "I40E_AQ_RC_EFLUSHED";
166 case I40E_AQ_RC_BAD_ADDR:
167 return "I40E_AQ_RC_BAD_ADDR";
168 case I40E_AQ_RC_EMODE:
169 return "I40E_AQ_RC_EMODE";
170 case I40E_AQ_RC_EFBIG:
171 return "I40E_AQ_RC_EFBIG";
174 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
179 * i40e_stat_str - convert status err code to a string
180 * @hw: pointer to the HW structure
181 * @stat_err: the status error code to convert
183 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
189 return "I40E_ERR_NVM";
190 case I40E_ERR_NVM_CHECKSUM:
191 return "I40E_ERR_NVM_CHECKSUM";
193 return "I40E_ERR_PHY";
194 case I40E_ERR_CONFIG:
195 return "I40E_ERR_CONFIG";
197 return "I40E_ERR_PARAM";
198 case I40E_ERR_MAC_TYPE:
199 return "I40E_ERR_MAC_TYPE";
200 case I40E_ERR_UNKNOWN_PHY:
201 return "I40E_ERR_UNKNOWN_PHY";
202 case I40E_ERR_LINK_SETUP:
203 return "I40E_ERR_LINK_SETUP";
204 case I40E_ERR_ADAPTER_STOPPED:
205 return "I40E_ERR_ADAPTER_STOPPED";
206 case I40E_ERR_INVALID_MAC_ADDR:
207 return "I40E_ERR_INVALID_MAC_ADDR";
208 case I40E_ERR_DEVICE_NOT_SUPPORTED:
209 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
210 case I40E_ERR_MASTER_REQUESTS_PENDING:
211 return "I40E_ERR_MASTER_REQUESTS_PENDING";
212 case I40E_ERR_INVALID_LINK_SETTINGS:
213 return "I40E_ERR_INVALID_LINK_SETTINGS";
214 case I40E_ERR_AUTONEG_NOT_COMPLETE:
215 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
216 case I40E_ERR_RESET_FAILED:
217 return "I40E_ERR_RESET_FAILED";
218 case I40E_ERR_SWFW_SYNC:
219 return "I40E_ERR_SWFW_SYNC";
220 case I40E_ERR_NO_AVAILABLE_VSI:
221 return "I40E_ERR_NO_AVAILABLE_VSI";
222 case I40E_ERR_NO_MEMORY:
223 return "I40E_ERR_NO_MEMORY";
224 case I40E_ERR_BAD_PTR:
225 return "I40E_ERR_BAD_PTR";
226 case I40E_ERR_RING_FULL:
227 return "I40E_ERR_RING_FULL";
228 case I40E_ERR_INVALID_PD_ID:
229 return "I40E_ERR_INVALID_PD_ID";
230 case I40E_ERR_INVALID_QP_ID:
231 return "I40E_ERR_INVALID_QP_ID";
232 case I40E_ERR_INVALID_CQ_ID:
233 return "I40E_ERR_INVALID_CQ_ID";
234 case I40E_ERR_INVALID_CEQ_ID:
235 return "I40E_ERR_INVALID_CEQ_ID";
236 case I40E_ERR_INVALID_AEQ_ID:
237 return "I40E_ERR_INVALID_AEQ_ID";
238 case I40E_ERR_INVALID_SIZE:
239 return "I40E_ERR_INVALID_SIZE";
240 case I40E_ERR_INVALID_ARP_INDEX:
241 return "I40E_ERR_INVALID_ARP_INDEX";
242 case I40E_ERR_INVALID_FPM_FUNC_ID:
243 return "I40E_ERR_INVALID_FPM_FUNC_ID";
244 case I40E_ERR_QP_INVALID_MSG_SIZE:
245 return "I40E_ERR_QP_INVALID_MSG_SIZE";
246 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
247 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
248 case I40E_ERR_INVALID_FRAG_COUNT:
249 return "I40E_ERR_INVALID_FRAG_COUNT";
250 case I40E_ERR_QUEUE_EMPTY:
251 return "I40E_ERR_QUEUE_EMPTY";
252 case I40E_ERR_INVALID_ALIGNMENT:
253 return "I40E_ERR_INVALID_ALIGNMENT";
254 case I40E_ERR_FLUSHED_QUEUE:
255 return "I40E_ERR_FLUSHED_QUEUE";
256 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
257 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
258 case I40E_ERR_INVALID_IMM_DATA_SIZE:
259 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
260 case I40E_ERR_TIMEOUT:
261 return "I40E_ERR_TIMEOUT";
262 case I40E_ERR_OPCODE_MISMATCH:
263 return "I40E_ERR_OPCODE_MISMATCH";
264 case I40E_ERR_CQP_COMPL_ERROR:
265 return "I40E_ERR_CQP_COMPL_ERROR";
266 case I40E_ERR_INVALID_VF_ID:
267 return "I40E_ERR_INVALID_VF_ID";
268 case I40E_ERR_INVALID_HMCFN_ID:
269 return "I40E_ERR_INVALID_HMCFN_ID";
270 case I40E_ERR_BACKING_PAGE_ERROR:
271 return "I40E_ERR_BACKING_PAGE_ERROR";
272 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
273 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
274 case I40E_ERR_INVALID_PBLE_INDEX:
275 return "I40E_ERR_INVALID_PBLE_INDEX";
276 case I40E_ERR_INVALID_SD_INDEX:
277 return "I40E_ERR_INVALID_SD_INDEX";
278 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
279 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
280 case I40E_ERR_INVALID_SD_TYPE:
281 return "I40E_ERR_INVALID_SD_TYPE";
282 case I40E_ERR_MEMCPY_FAILED:
283 return "I40E_ERR_MEMCPY_FAILED";
284 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
285 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
286 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
287 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
288 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
289 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
290 case I40E_ERR_SRQ_ENABLED:
291 return "I40E_ERR_SRQ_ENABLED";
292 case I40E_ERR_ADMIN_QUEUE_ERROR:
293 return "I40E_ERR_ADMIN_QUEUE_ERROR";
294 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
295 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
296 case I40E_ERR_BUF_TOO_SHORT:
297 return "I40E_ERR_BUF_TOO_SHORT";
298 case I40E_ERR_ADMIN_QUEUE_FULL:
299 return "I40E_ERR_ADMIN_QUEUE_FULL";
300 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
301 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
302 case I40E_ERR_BAD_IWARP_CQE:
303 return "I40E_ERR_BAD_IWARP_CQE";
304 case I40E_ERR_NVM_BLANK_MODE:
305 return "I40E_ERR_NVM_BLANK_MODE";
306 case I40E_ERR_NOT_IMPLEMENTED:
307 return "I40E_ERR_NOT_IMPLEMENTED";
308 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
309 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
310 case I40E_ERR_DIAG_TEST_FAILED:
311 return "I40E_ERR_DIAG_TEST_FAILED";
312 case I40E_ERR_NOT_READY:
313 return "I40E_ERR_NOT_READY";
314 case I40E_NOT_SUPPORTED:
315 return "I40E_NOT_SUPPORTED";
316 case I40E_ERR_FIRMWARE_API_VERSION:
317 return "I40E_ERR_FIRMWARE_API_VERSION";
320 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
324 #endif /* I40E_NDIS_SUPPORT */
327 * @hw: debug mask related to admin queue
329 * @desc: pointer to admin queue descriptor
330 * @buffer: pointer to command buffer
331 * @buf_len: max length of buffer
333 * Dumps debug log about adminq command with descriptor contents.
335 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
336 void *buffer, u16 buf_len)
338 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
339 u16 len = LE16_TO_CPU(aq_desc->datalen);
340 u8 *buf = (u8 *)buffer;
343 if ((!(mask & hw->debug_mask)) || (desc == NULL))
347 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
348 LE16_TO_CPU(aq_desc->opcode),
349 LE16_TO_CPU(aq_desc->flags),
350 LE16_TO_CPU(aq_desc->datalen),
351 LE16_TO_CPU(aq_desc->retval));
352 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
353 LE32_TO_CPU(aq_desc->cookie_high),
354 LE32_TO_CPU(aq_desc->cookie_low));
355 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
356 LE32_TO_CPU(aq_desc->params.internal.param0),
357 LE32_TO_CPU(aq_desc->params.internal.param1));
358 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
359 LE32_TO_CPU(aq_desc->params.external.addr_high),
360 LE32_TO_CPU(aq_desc->params.external.addr_low));
362 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
363 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
366 /* write the full 16-byte chunks */
367 for (i = 0; i < (len - 16); i += 16)
369 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
370 i, buf[i], buf[i+1], buf[i+2], buf[i+3],
371 buf[i+4], buf[i+5], buf[i+6], buf[i+7],
372 buf[i+8], buf[i+9], buf[i+10], buf[i+11],
373 buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
374 /* the most we could have left is 16 bytes, pad with zeros */
380 memset(d_buf, 0, sizeof(d_buf));
381 for (j = 0; i < len; j++, i++)
384 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
385 i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
386 d_buf[4], d_buf[5], d_buf[6], d_buf[7],
387 d_buf[8], d_buf[9], d_buf[10], d_buf[11],
388 d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
394 * i40e_check_asq_alive
395 * @hw: pointer to the hw struct
397 * Returns true if Queue is enabled else false.
399 bool i40e_check_asq_alive(struct i40e_hw *hw)
405 return !!(rd32(hw, hw->aq.asq.len) &
406 I40E_PF_ATQLEN_ATQENABLE_MASK);
408 return !!(rd32(hw, hw->aq.asq.len) &
409 I40E_PF_ATQLEN_ATQENABLE_MASK);
410 #endif /* INTEGRATED_VF */
411 #endif /* PF_DRIVER */
415 return !!(rd32(hw, hw->aq.asq.len) &
416 I40E_VF_ATQLEN1_ATQENABLE_MASK);
418 return !!(rd32(hw, hw->aq.asq.len) &
419 I40E_VF_ATQLEN1_ATQENABLE_MASK);
420 #endif /* INTEGRATED_VF */
421 #endif /* VF_DRIVER */
426 * i40e_aq_queue_shutdown
427 * @hw: pointer to the hw struct
428 * @unloading: is the driver unloading itself
430 * Tell the Firmware that we're shutting down the AdminQ and whether
431 * or not the driver is unloading as well.
433 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
436 struct i40e_aq_desc desc;
437 struct i40e_aqc_queue_shutdown *cmd =
438 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
439 enum i40e_status_code status;
441 i40e_fill_default_direct_cmd_desc(&desc,
442 i40e_aqc_opc_queue_shutdown);
445 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
446 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
453 * i40e_aq_get_set_rss_lut
454 * @hw: pointer to the hardware structure
455 * @vsi_id: vsi fw index
456 * @pf_lut: for PF table set true, for VSI table set false
457 * @lut: pointer to the lut buffer provided by the caller
458 * @lut_size: size of the lut buffer
459 * @set: set true to set the table, false to get the table
461 * Internal function to get or set RSS look up table
463 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
464 u16 vsi_id, bool pf_lut,
465 u8 *lut, u16 lut_size,
468 enum i40e_status_code status;
469 struct i40e_aq_desc desc;
470 struct i40e_aqc_get_set_rss_lut *cmd_resp =
471 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
474 i40e_fill_default_direct_cmd_desc(&desc,
475 i40e_aqc_opc_set_rss_lut);
477 i40e_fill_default_direct_cmd_desc(&desc,
478 i40e_aqc_opc_get_rss_lut);
480 /* Indirect command */
481 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
482 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
485 CPU_TO_LE16((u16)((vsi_id <<
486 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
487 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
488 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
491 cmd_resp->flags |= CPU_TO_LE16((u16)
492 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
493 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
494 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
496 cmd_resp->flags |= CPU_TO_LE16((u16)
497 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
498 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
499 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
501 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
507 * i40e_aq_get_rss_lut
508 * @hw: pointer to the hardware structure
509 * @vsi_id: vsi fw index
510 * @pf_lut: for PF table set true, for VSI table set false
511 * @lut: pointer to the lut buffer provided by the caller
512 * @lut_size: size of the lut buffer
514 * get the RSS lookup table, PF or VSI type
516 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
517 bool pf_lut, u8 *lut, u16 lut_size)
519 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
524 * i40e_aq_set_rss_lut
525 * @hw: pointer to the hardware structure
526 * @vsi_id: vsi fw index
527 * @pf_lut: for PF table set true, for VSI table set false
528 * @lut: pointer to the lut buffer provided by the caller
529 * @lut_size: size of the lut buffer
531 * set the RSS lookup table, PF or VSI type
533 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
534 bool pf_lut, u8 *lut, u16 lut_size)
536 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
540 * i40e_aq_get_set_rss_key
541 * @hw: pointer to the hw struct
542 * @vsi_id: vsi fw index
543 * @key: pointer to key info struct
544 * @set: set true to set the key, false to get the key
546 * get the RSS key per VSI
548 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
550 struct i40e_aqc_get_set_rss_key_data *key,
553 enum i40e_status_code status;
554 struct i40e_aq_desc desc;
555 struct i40e_aqc_get_set_rss_key *cmd_resp =
556 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
557 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
560 i40e_fill_default_direct_cmd_desc(&desc,
561 i40e_aqc_opc_set_rss_key);
563 i40e_fill_default_direct_cmd_desc(&desc,
564 i40e_aqc_opc_get_rss_key);
566 /* Indirect command */
567 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
568 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
571 CPU_TO_LE16((u16)((vsi_id <<
572 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
573 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
574 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
576 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
582 * i40e_aq_get_rss_key
583 * @hw: pointer to the hw struct
584 * @vsi_id: vsi fw index
585 * @key: pointer to key info struct
588 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
590 struct i40e_aqc_get_set_rss_key_data *key)
592 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
596 * i40e_aq_set_rss_key
597 * @hw: pointer to the hw struct
598 * @vsi_id: vsi fw index
599 * @key: pointer to key info struct
601 * set the RSS key per VSI
603 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
605 struct i40e_aqc_get_set_rss_key_data *key)
607 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
609 #endif /* X722_SUPPORT */
611 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
612 * hardware to a bit-field that can be used by SW to more easily determine the
615 * Macros are used to shorten the table lines and make this table human
618 * We store the PTYPE in the top byte of the bit field - this is just so that
619 * we can check that the table doesn't have a row missing, as the index into
620 * the table should be the PTYPE.
624 * IF NOT i40e_ptype_lookup[ptype].known
627 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
628 * Use the rest of the fields to look at the tunnels, inner protocols, etc
630 * Use the enum i40e_rx_l2_ptype to decode the packet type
634 /* macro to make the table lines short */
635 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
638 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
639 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
640 I40E_RX_PTYPE_##OUTER_FRAG, \
641 I40E_RX_PTYPE_TUNNEL_##T, \
642 I40E_RX_PTYPE_TUNNEL_END_##TE, \
643 I40E_RX_PTYPE_##TEF, \
644 I40E_RX_PTYPE_INNER_PROT_##I, \
645 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
647 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
648 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
650 /* shorter macros makes the table fit but are terse */
651 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
652 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
653 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
655 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
656 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
657 /* L2 Packet types */
658 I40E_PTT_UNUSED_ENTRY(0),
659 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
660 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
661 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
662 I40E_PTT_UNUSED_ENTRY(4),
663 I40E_PTT_UNUSED_ENTRY(5),
664 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
665 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
666 I40E_PTT_UNUSED_ENTRY(8),
667 I40E_PTT_UNUSED_ENTRY(9),
668 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
669 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
670 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
671 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
672 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
673 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
674 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
675 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
676 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
677 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
678 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
679 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
681 /* Non Tunneled IPv4 */
682 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
683 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
684 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
685 I40E_PTT_UNUSED_ENTRY(25),
686 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
687 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
688 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
691 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
692 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
693 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
694 I40E_PTT_UNUSED_ENTRY(32),
695 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
696 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
697 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
700 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
701 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
702 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
703 I40E_PTT_UNUSED_ENTRY(39),
704 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
705 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
706 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
708 /* IPv4 --> GRE/NAT */
709 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
711 /* IPv4 --> GRE/NAT --> IPv4 */
712 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
713 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
714 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
715 I40E_PTT_UNUSED_ENTRY(47),
716 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
717 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
718 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
720 /* IPv4 --> GRE/NAT --> IPv6 */
721 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
722 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
723 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
724 I40E_PTT_UNUSED_ENTRY(54),
725 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
726 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
727 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
729 /* IPv4 --> GRE/NAT --> MAC */
730 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
732 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
733 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
734 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
735 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
736 I40E_PTT_UNUSED_ENTRY(62),
737 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
738 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
739 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
741 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
742 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
743 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
744 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
745 I40E_PTT_UNUSED_ENTRY(69),
746 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
747 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
748 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
750 /* IPv4 --> GRE/NAT --> MAC/VLAN */
751 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
753 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
754 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
755 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
756 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
757 I40E_PTT_UNUSED_ENTRY(77),
758 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
759 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
760 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
762 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
763 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
764 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
765 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
766 I40E_PTT_UNUSED_ENTRY(84),
767 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
768 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
769 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
771 /* Non Tunneled IPv6 */
772 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
773 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
774 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4),
775 I40E_PTT_UNUSED_ENTRY(91),
776 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
777 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
778 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
781 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
782 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
783 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
784 I40E_PTT_UNUSED_ENTRY(98),
785 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
786 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
787 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
790 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
791 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
792 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
793 I40E_PTT_UNUSED_ENTRY(105),
794 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
795 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
796 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
798 /* IPv6 --> GRE/NAT */
799 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
801 /* IPv6 --> GRE/NAT -> IPv4 */
802 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
803 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
804 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
805 I40E_PTT_UNUSED_ENTRY(113),
806 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
807 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
808 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
810 /* IPv6 --> GRE/NAT -> IPv6 */
811 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
812 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
813 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
814 I40E_PTT_UNUSED_ENTRY(120),
815 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
816 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
817 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
819 /* IPv6 --> GRE/NAT -> MAC */
820 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
822 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
823 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
824 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
825 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
826 I40E_PTT_UNUSED_ENTRY(128),
827 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
828 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
829 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
831 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
832 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
833 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
834 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
835 I40E_PTT_UNUSED_ENTRY(135),
836 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
837 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
838 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
840 /* IPv6 --> GRE/NAT -> MAC/VLAN */
841 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
843 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
844 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
845 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
846 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
847 I40E_PTT_UNUSED_ENTRY(143),
848 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
849 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
850 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
852 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
853 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
854 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
855 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
856 I40E_PTT_UNUSED_ENTRY(150),
857 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
858 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
859 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
862 I40E_PTT_UNUSED_ENTRY(154),
863 I40E_PTT_UNUSED_ENTRY(155),
864 I40E_PTT_UNUSED_ENTRY(156),
865 I40E_PTT_UNUSED_ENTRY(157),
866 I40E_PTT_UNUSED_ENTRY(158),
867 I40E_PTT_UNUSED_ENTRY(159),
869 I40E_PTT_UNUSED_ENTRY(160),
870 I40E_PTT_UNUSED_ENTRY(161),
871 I40E_PTT_UNUSED_ENTRY(162),
872 I40E_PTT_UNUSED_ENTRY(163),
873 I40E_PTT_UNUSED_ENTRY(164),
874 I40E_PTT_UNUSED_ENTRY(165),
875 I40E_PTT_UNUSED_ENTRY(166),
876 I40E_PTT_UNUSED_ENTRY(167),
877 I40E_PTT_UNUSED_ENTRY(168),
878 I40E_PTT_UNUSED_ENTRY(169),
880 I40E_PTT_UNUSED_ENTRY(170),
881 I40E_PTT_UNUSED_ENTRY(171),
882 I40E_PTT_UNUSED_ENTRY(172),
883 I40E_PTT_UNUSED_ENTRY(173),
884 I40E_PTT_UNUSED_ENTRY(174),
885 I40E_PTT_UNUSED_ENTRY(175),
886 I40E_PTT_UNUSED_ENTRY(176),
887 I40E_PTT_UNUSED_ENTRY(177),
888 I40E_PTT_UNUSED_ENTRY(178),
889 I40E_PTT_UNUSED_ENTRY(179),
891 I40E_PTT_UNUSED_ENTRY(180),
892 I40E_PTT_UNUSED_ENTRY(181),
893 I40E_PTT_UNUSED_ENTRY(182),
894 I40E_PTT_UNUSED_ENTRY(183),
895 I40E_PTT_UNUSED_ENTRY(184),
896 I40E_PTT_UNUSED_ENTRY(185),
897 I40E_PTT_UNUSED_ENTRY(186),
898 I40E_PTT_UNUSED_ENTRY(187),
899 I40E_PTT_UNUSED_ENTRY(188),
900 I40E_PTT_UNUSED_ENTRY(189),
902 I40E_PTT_UNUSED_ENTRY(190),
903 I40E_PTT_UNUSED_ENTRY(191),
904 I40E_PTT_UNUSED_ENTRY(192),
905 I40E_PTT_UNUSED_ENTRY(193),
906 I40E_PTT_UNUSED_ENTRY(194),
907 I40E_PTT_UNUSED_ENTRY(195),
908 I40E_PTT_UNUSED_ENTRY(196),
909 I40E_PTT_UNUSED_ENTRY(197),
910 I40E_PTT_UNUSED_ENTRY(198),
911 I40E_PTT_UNUSED_ENTRY(199),
913 I40E_PTT_UNUSED_ENTRY(200),
914 I40E_PTT_UNUSED_ENTRY(201),
915 I40E_PTT_UNUSED_ENTRY(202),
916 I40E_PTT_UNUSED_ENTRY(203),
917 I40E_PTT_UNUSED_ENTRY(204),
918 I40E_PTT_UNUSED_ENTRY(205),
919 I40E_PTT_UNUSED_ENTRY(206),
920 I40E_PTT_UNUSED_ENTRY(207),
921 I40E_PTT_UNUSED_ENTRY(208),
922 I40E_PTT_UNUSED_ENTRY(209),
924 I40E_PTT_UNUSED_ENTRY(210),
925 I40E_PTT_UNUSED_ENTRY(211),
926 I40E_PTT_UNUSED_ENTRY(212),
927 I40E_PTT_UNUSED_ENTRY(213),
928 I40E_PTT_UNUSED_ENTRY(214),
929 I40E_PTT_UNUSED_ENTRY(215),
930 I40E_PTT_UNUSED_ENTRY(216),
931 I40E_PTT_UNUSED_ENTRY(217),
932 I40E_PTT_UNUSED_ENTRY(218),
933 I40E_PTT_UNUSED_ENTRY(219),
935 I40E_PTT_UNUSED_ENTRY(220),
936 I40E_PTT_UNUSED_ENTRY(221),
937 I40E_PTT_UNUSED_ENTRY(222),
938 I40E_PTT_UNUSED_ENTRY(223),
939 I40E_PTT_UNUSED_ENTRY(224),
940 I40E_PTT_UNUSED_ENTRY(225),
941 I40E_PTT_UNUSED_ENTRY(226),
942 I40E_PTT_UNUSED_ENTRY(227),
943 I40E_PTT_UNUSED_ENTRY(228),
944 I40E_PTT_UNUSED_ENTRY(229),
946 I40E_PTT_UNUSED_ENTRY(230),
947 I40E_PTT_UNUSED_ENTRY(231),
948 I40E_PTT_UNUSED_ENTRY(232),
949 I40E_PTT_UNUSED_ENTRY(233),
950 I40E_PTT_UNUSED_ENTRY(234),
951 I40E_PTT_UNUSED_ENTRY(235),
952 I40E_PTT_UNUSED_ENTRY(236),
953 I40E_PTT_UNUSED_ENTRY(237),
954 I40E_PTT_UNUSED_ENTRY(238),
955 I40E_PTT_UNUSED_ENTRY(239),
957 I40E_PTT_UNUSED_ENTRY(240),
958 I40E_PTT_UNUSED_ENTRY(241),
959 I40E_PTT_UNUSED_ENTRY(242),
960 I40E_PTT_UNUSED_ENTRY(243),
961 I40E_PTT_UNUSED_ENTRY(244),
962 I40E_PTT_UNUSED_ENTRY(245),
963 I40E_PTT_UNUSED_ENTRY(246),
964 I40E_PTT_UNUSED_ENTRY(247),
965 I40E_PTT_UNUSED_ENTRY(248),
966 I40E_PTT_UNUSED_ENTRY(249),
968 I40E_PTT_UNUSED_ENTRY(250),
969 I40E_PTT_UNUSED_ENTRY(251),
970 I40E_PTT_UNUSED_ENTRY(252),
971 I40E_PTT_UNUSED_ENTRY(253),
972 I40E_PTT_UNUSED_ENTRY(254),
973 I40E_PTT_UNUSED_ENTRY(255)
978 * i40e_validate_mac_addr - Validate unicast MAC address
979 * @mac_addr: pointer to MAC address
981 * Tests a MAC address to ensure it is a valid Individual Address
983 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
985 enum i40e_status_code status = I40E_SUCCESS;
987 DEBUGFUNC("i40e_validate_mac_addr");
989 /* Broadcast addresses ARE multicast addresses
990 * Make sure it is not a multicast address
991 * Reject the zero address
993 if (I40E_IS_MULTICAST(mac_addr) ||
994 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
995 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
996 status = I40E_ERR_INVALID_MAC_ADDR;
1003 * i40e_init_shared_code - Initialize the shared code
1004 * @hw: pointer to hardware structure
1006 * This assigns the MAC type and PHY code and inits the NVM.
1007 * Does not touch the hardware. This function must be called prior to any
1008 * other function in the shared code. The i40e_hw structure should be
1009 * memset to 0 prior to calling this function. The following fields in
1010 * hw structure should be filled in prior to calling this function:
1011 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1012 * subsystem_vendor_id, and revision_id
1014 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
1016 enum i40e_status_code status = I40E_SUCCESS;
1017 u32 port, ari, func_rid;
1019 DEBUGFUNC("i40e_init_shared_code");
1021 i40e_set_mac_type(hw);
1023 switch (hw->mac.type) {
1024 case I40E_MAC_XL710:
1030 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1033 hw->phy.get_link_info = true;
1035 /* Determine port number and PF number*/
1036 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1037 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1038 hw->port = (u8)port;
1039 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1040 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1041 func_rid = rd32(hw, I40E_PF_FUNC_RID);
1043 hw->pf_id = (u8)(func_rid & 0xff);
1045 hw->pf_id = (u8)(func_rid & 0x7);
1048 if (hw->mac.type == I40E_MAC_X722)
1049 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
1052 status = i40e_init_nvm(hw);
1057 * i40e_aq_mac_address_read - Retrieve the MAC addresses
1058 * @hw: pointer to the hw struct
1059 * @flags: a return indicator of what addresses were added to the addr store
1060 * @addrs: the requestor's mac addr store
1061 * @cmd_details: pointer to command details structure or NULL
1063 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1065 struct i40e_aqc_mac_address_read_data *addrs,
1066 struct i40e_asq_cmd_details *cmd_details)
1068 struct i40e_aq_desc desc;
1069 struct i40e_aqc_mac_address_read *cmd_data =
1070 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1071 enum i40e_status_code status;
1073 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1074 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1076 status = i40e_asq_send_command(hw, &desc, addrs,
1077 sizeof(*addrs), cmd_details);
1078 *flags = LE16_TO_CPU(cmd_data->command_flags);
1084 * i40e_aq_mac_address_write - Change the MAC addresses
1085 * @hw: pointer to the hw struct
1086 * @flags: indicates which MAC to be written
1087 * @mac_addr: address to write
1088 * @cmd_details: pointer to command details structure or NULL
1090 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1091 u16 flags, u8 *mac_addr,
1092 struct i40e_asq_cmd_details *cmd_details)
1094 struct i40e_aq_desc desc;
1095 struct i40e_aqc_mac_address_write *cmd_data =
1096 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1097 enum i40e_status_code status;
1099 i40e_fill_default_direct_cmd_desc(&desc,
1100 i40e_aqc_opc_mac_address_write);
1101 cmd_data->command_flags = CPU_TO_LE16(flags);
1102 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1103 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1104 ((u32)mac_addr[3] << 16) |
1105 ((u32)mac_addr[4] << 8) |
1108 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1114 * i40e_get_mac_addr - get MAC address
1115 * @hw: pointer to the HW structure
1116 * @mac_addr: pointer to MAC address
1118 * Reads the adapter's MAC address from register
1120 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1122 struct i40e_aqc_mac_address_read_data addrs;
1123 enum i40e_status_code status;
1126 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1128 if (flags & I40E_AQC_LAN_ADDR_VALID)
1129 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
1135 * i40e_get_port_mac_addr - get Port MAC address
1136 * @hw: pointer to the HW structure
1137 * @mac_addr: pointer to Port MAC address
1139 * Reads the adapter's Port MAC address
1141 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1143 struct i40e_aqc_mac_address_read_data addrs;
1144 enum i40e_status_code status;
1147 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1151 if (flags & I40E_AQC_PORT_ADDR_VALID)
1152 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
1154 status = I40E_ERR_INVALID_MAC_ADDR;
1160 * i40e_pre_tx_queue_cfg - pre tx queue configure
1161 * @hw: pointer to the HW structure
1162 * @queue: target pf queue index
1163 * @enable: state change request
1165 * Handles hw requirement to indicate intention to enable
1166 * or disable target queue.
1168 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1170 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1174 if (abs_queue_idx >= 128) {
1175 reg_block = abs_queue_idx / 128;
1176 abs_queue_idx %= 128;
1179 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1180 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1181 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1184 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1186 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1188 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1192 * i40e_get_san_mac_addr - get SAN MAC address
1193 * @hw: pointer to the HW structure
1194 * @mac_addr: pointer to SAN MAC address
1196 * Reads the adapter's SAN MAC address from NVM
1198 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1201 struct i40e_aqc_mac_address_read_data addrs;
1202 enum i40e_status_code status;
1205 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1209 if (flags & I40E_AQC_SAN_ADDR_VALID)
1210 memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac));
1212 status = I40E_ERR_INVALID_MAC_ADDR;
1218 * i40e_read_pba_string - Reads part number string from EEPROM
1219 * @hw: pointer to hardware structure
1220 * @pba_num: stores the part number string from the EEPROM
1221 * @pba_num_size: part number string buffer length
1223 * Reads the part number string from the EEPROM.
1225 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1228 enum i40e_status_code status = I40E_SUCCESS;
1234 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1235 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1236 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1240 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1241 if (status != I40E_SUCCESS) {
1242 DEBUGOUT("Failed to read PBA Block pointer.\n");
1246 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1247 if (status != I40E_SUCCESS) {
1248 DEBUGOUT("Failed to read PBA Block size.\n");
1252 /* Subtract one to get PBA word count (PBA Size word is included in
1256 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1257 DEBUGOUT("Buffer to small for PBA data.\n");
1258 return I40E_ERR_PARAM;
1261 for (i = 0; i < pba_size; i++) {
1262 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1263 if (status != I40E_SUCCESS) {
1264 DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1268 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1269 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1271 pba_num[(pba_size * 2)] = '\0';
1277 * i40e_get_media_type - Gets media type
1278 * @hw: pointer to the hardware structure
1280 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1282 enum i40e_media_type media;
1284 switch (hw->phy.link_info.phy_type) {
1285 case I40E_PHY_TYPE_10GBASE_SR:
1286 case I40E_PHY_TYPE_10GBASE_LR:
1287 case I40E_PHY_TYPE_1000BASE_SX:
1288 case I40E_PHY_TYPE_1000BASE_LX:
1289 case I40E_PHY_TYPE_40GBASE_SR4:
1290 case I40E_PHY_TYPE_40GBASE_LR4:
1291 media = I40E_MEDIA_TYPE_FIBER;
1293 case I40E_PHY_TYPE_100BASE_TX:
1294 case I40E_PHY_TYPE_1000BASE_T:
1295 case I40E_PHY_TYPE_10GBASE_T:
1296 media = I40E_MEDIA_TYPE_BASET;
1298 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1299 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1300 case I40E_PHY_TYPE_10GBASE_CR1:
1301 case I40E_PHY_TYPE_40GBASE_CR4:
1302 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1303 case I40E_PHY_TYPE_40GBASE_AOC:
1304 case I40E_PHY_TYPE_10GBASE_AOC:
1305 media = I40E_MEDIA_TYPE_DA;
1307 case I40E_PHY_TYPE_1000BASE_KX:
1308 case I40E_PHY_TYPE_10GBASE_KX4:
1309 case I40E_PHY_TYPE_10GBASE_KR:
1310 case I40E_PHY_TYPE_40GBASE_KR4:
1311 case I40E_PHY_TYPE_20GBASE_KR2:
1312 media = I40E_MEDIA_TYPE_BACKPLANE;
1314 case I40E_PHY_TYPE_SGMII:
1315 case I40E_PHY_TYPE_XAUI:
1316 case I40E_PHY_TYPE_XFI:
1317 case I40E_PHY_TYPE_XLAUI:
1318 case I40E_PHY_TYPE_XLPPI:
1320 media = I40E_MEDIA_TYPE_UNKNOWN;
1327 #define I40E_PF_RESET_WAIT_COUNT 200
1329 * i40e_pf_reset - Reset the PF
1330 * @hw: pointer to the hardware structure
1332 * Assuming someone else has triggered a global reset,
1333 * assure the global reset is complete and then reset the PF
1335 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1342 /* Poll for Global Reset steady state in case of recent GRST.
1343 * The grst delay value is in 100ms units, and we'll wait a
1344 * couple counts longer to be sure we don't just miss the end.
1346 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1347 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1348 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1350 grst_del = grst_del * 20;
1352 for (cnt = 0; cnt < grst_del; cnt++) {
1353 reg = rd32(hw, I40E_GLGEN_RSTAT);
1354 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1356 i40e_msec_delay(100);
1358 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1359 DEBUGOUT("Global reset polling failed to complete.\n");
1360 return I40E_ERR_RESET_FAILED;
1363 /* Now Wait for the FW to be ready */
1364 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1365 reg = rd32(hw, I40E_GLNVM_ULD);
1366 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1367 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1368 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1369 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1370 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1373 i40e_msec_delay(10);
1375 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1376 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1377 DEBUGOUT("wait for FW Reset complete timedout\n");
1378 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1379 return I40E_ERR_RESET_FAILED;
1382 /* If there was a Global Reset in progress when we got here,
1383 * we don't need to do the PF Reset
1386 reg = rd32(hw, I40E_PFGEN_CTRL);
1387 wr32(hw, I40E_PFGEN_CTRL,
1388 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1389 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1390 reg = rd32(hw, I40E_PFGEN_CTRL);
1391 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1395 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1396 DEBUGOUT("PF reset polling failed to complete.\n");
1397 return I40E_ERR_RESET_FAILED;
1401 i40e_clear_pxe_mode(hw);
1404 return I40E_SUCCESS;
1408 * i40e_clear_hw - clear out any left over hw state
1409 * @hw: pointer to the hw struct
1411 * Clear queues and interrupts, typically called at init time,
1412 * but after the capabilities have been found so we know how many
1413 * queues and msix vectors have been allocated.
1415 void i40e_clear_hw(struct i40e_hw *hw)
1417 u32 num_queues, base_queue;
1425 /* get number of interrupts, queues, and vfs */
1426 val = rd32(hw, I40E_GLPCI_CNF2);
1427 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1428 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1429 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1430 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1432 val = rd32(hw, I40E_PFLAN_QALLOC);
1433 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1434 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1435 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1436 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1437 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1438 num_queues = (j - base_queue) + 1;
1442 val = rd32(hw, I40E_PF_VT_PFALLOC);
1443 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1444 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1445 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1446 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1447 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1448 num_vfs = (j - i) + 1;
1452 /* stop all the interrupts */
1453 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1454 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1455 for (i = 0; i < num_pf_int - 2; i++)
1456 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1458 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1459 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1460 wr32(hw, I40E_PFINT_LNKLST0, val);
1461 for (i = 0; i < num_pf_int - 2; i++)
1462 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1463 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1464 for (i = 0; i < num_vfs; i++)
1465 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1466 for (i = 0; i < num_vf_int - 2; i++)
1467 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1469 /* warn the HW of the coming Tx disables */
1470 for (i = 0; i < num_queues; i++) {
1471 u32 abs_queue_idx = base_queue + i;
1474 if (abs_queue_idx >= 128) {
1475 reg_block = abs_queue_idx / 128;
1476 abs_queue_idx %= 128;
1479 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1480 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1481 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1482 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1484 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1486 i40e_usec_delay(400);
1488 /* stop all the queues */
1489 for (i = 0; i < num_queues; i++) {
1490 wr32(hw, I40E_QINT_TQCTL(i), 0);
1491 wr32(hw, I40E_QTX_ENA(i), 0);
1492 wr32(hw, I40E_QINT_RQCTL(i), 0);
1493 wr32(hw, I40E_QRX_ENA(i), 0);
1496 /* short wait for all queue disables to settle */
1497 i40e_usec_delay(50);
1501 * i40e_clear_pxe_mode - clear pxe operations mode
1502 * @hw: pointer to the hw struct
1504 * Make sure all PXE mode settings are cleared, including things
1505 * like descriptor fetch/write-back mode.
1507 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1509 if (i40e_check_asq_alive(hw))
1510 i40e_aq_clear_pxe_mode(hw, NULL);
1514 * i40e_led_is_mine - helper to find matching led
1515 * @hw: pointer to the hw struct
1516 * @idx: index into GPIO registers
1518 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1520 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1525 if (!hw->func_caps.led[idx])
1528 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1529 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1530 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1532 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1533 * if it is not our port then ignore
1535 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1542 #define I40E_COMBINED_ACTIVITY 0xA
1543 #define I40E_FILTER_ACTIVITY 0xE
1544 #define I40E_LINK_ACTIVITY 0xC
1545 #define I40E_MAC_ACTIVITY 0xD
1546 #define I40E_LED0 22
1549 * i40e_led_get - return current on/off mode
1550 * @hw: pointer to the hw struct
1552 * The value returned is the 'mode' field as defined in the
1553 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1554 * values are variations of possible behaviors relating to
1555 * blink, link, and wire.
1557 u32 i40e_led_get(struct i40e_hw *hw)
1559 u32 current_mode = 0;
1563 /* as per the documentation GPIO 22-29 are the LED
1564 * GPIO pins named LED0..LED7
1566 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1567 u32 gpio_val = i40e_led_is_mine(hw, i);
1572 /* ignore gpio LED src mode entries related to the activity
1575 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1576 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1577 switch (current_mode) {
1578 case I40E_COMBINED_ACTIVITY:
1579 case I40E_FILTER_ACTIVITY:
1580 case I40E_MAC_ACTIVITY:
1586 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1587 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1595 * i40e_led_set - set new on/off mode
1596 * @hw: pointer to the hw struct
1597 * @mode: 0=off, 0xf=on (else see manual for mode details)
1598 * @blink: true if the LED should blink when on, false if steady
1600 * if this function is used to turn on the blink it should
1601 * be used to disable the blink when restoring the original state.
1603 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1605 u32 current_mode = 0;
1608 if (mode & 0xfffffff0)
1609 DEBUGOUT1("invalid mode passed in %X\n", mode);
1611 /* as per the documentation GPIO 22-29 are the LED
1612 * GPIO pins named LED0..LED7
1614 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1615 u32 gpio_val = i40e_led_is_mine(hw, i);
1620 /* ignore gpio LED src mode entries related to the activity
1623 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1624 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1625 switch (current_mode) {
1626 case I40E_COMBINED_ACTIVITY:
1627 case I40E_FILTER_ACTIVITY:
1628 case I40E_MAC_ACTIVITY:
1634 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1635 /* this & is a bit of paranoia, but serves as a range check */
1636 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1637 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1639 if (mode == I40E_LINK_ACTIVITY)
1643 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1645 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1647 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1652 /* Admin command wrappers */
1655 * i40e_aq_get_phy_capabilities
1656 * @hw: pointer to the hw struct
1657 * @abilities: structure for PHY capabilities to be filled
1658 * @qualified_modules: report Qualified Modules
1659 * @report_init: report init capabilities (active are default)
1660 * @cmd_details: pointer to command details structure or NULL
1662 * Returns the various PHY abilities supported on the Port.
1664 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1665 bool qualified_modules, bool report_init,
1666 struct i40e_aq_get_phy_abilities_resp *abilities,
1667 struct i40e_asq_cmd_details *cmd_details)
1669 struct i40e_aq_desc desc;
1670 enum i40e_status_code status;
1671 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1674 return I40E_ERR_PARAM;
1676 i40e_fill_default_direct_cmd_desc(&desc,
1677 i40e_aqc_opc_get_phy_abilities);
1679 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1680 if (abilities_size > I40E_AQ_LARGE_BUF)
1681 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1683 if (qualified_modules)
1684 desc.params.external.param0 |=
1685 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1688 desc.params.external.param0 |=
1689 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1691 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1694 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1695 status = I40E_ERR_UNKNOWN_PHY;
1698 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1699 hw->phy.phy_types |= ((u64)abilities->phy_type_ext << 32);
1706 * i40e_aq_set_phy_config
1707 * @hw: pointer to the hw struct
1708 * @config: structure with PHY configuration to be set
1709 * @cmd_details: pointer to command details structure or NULL
1711 * Set the various PHY configuration parameters
1712 * supported on the Port.One or more of the Set PHY config parameters may be
1713 * ignored in an MFP mode as the PF may not have the privilege to set some
1714 * of the PHY Config parameters. This status will be indicated by the
1717 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1718 struct i40e_aq_set_phy_config *config,
1719 struct i40e_asq_cmd_details *cmd_details)
1721 struct i40e_aq_desc desc;
1722 struct i40e_aq_set_phy_config *cmd =
1723 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1724 enum i40e_status_code status;
1727 return I40E_ERR_PARAM;
1729 i40e_fill_default_direct_cmd_desc(&desc,
1730 i40e_aqc_opc_set_phy_config);
1734 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1741 * @hw: pointer to the hw struct
1743 * Set the requested flow control mode using set_phy_config.
1745 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1746 bool atomic_restart)
1748 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1749 struct i40e_aq_get_phy_abilities_resp abilities;
1750 struct i40e_aq_set_phy_config config;
1751 enum i40e_status_code status;
1752 u8 pause_mask = 0x0;
1758 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1759 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1761 case I40E_FC_RX_PAUSE:
1762 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1764 case I40E_FC_TX_PAUSE:
1765 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1771 /* Get the current phy config */
1772 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1775 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1779 memset(&config, 0, sizeof(config));
1780 /* clear the old pause settings */
1781 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1782 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1783 /* set the new abilities */
1784 config.abilities |= pause_mask;
1785 /* If the abilities have changed, then set the new config */
1786 if (config.abilities != abilities.abilities) {
1787 /* Auto restart link so settings take effect */
1789 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1790 /* Copy over all the old settings */
1791 config.phy_type = abilities.phy_type;
1792 config.phy_type_ext = abilities.phy_type_ext;
1793 config.link_speed = abilities.link_speed;
1794 config.eee_capability = abilities.eee_capability;
1795 config.eeer = abilities.eeer_val;
1796 config.low_power_ctrl = abilities.d3_lpan;
1797 status = i40e_aq_set_phy_config(hw, &config, NULL);
1800 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1802 /* Update the link info */
1803 status = i40e_update_link_info(hw);
1805 /* Wait a little bit (on 40G cards it sometimes takes a really
1806 * long time for link to come back from the atomic reset)
1809 i40e_msec_delay(1000);
1810 status = i40e_update_link_info(hw);
1813 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1819 * i40e_aq_set_mac_config
1820 * @hw: pointer to the hw struct
1821 * @max_frame_size: Maximum Frame Size to be supported by the port
1822 * @crc_en: Tell HW to append a CRC to outgoing frames
1823 * @pacing: Pacing configurations
1824 * @cmd_details: pointer to command details structure or NULL
1826 * Configure MAC settings for frame size, jumbo frame support and the
1827 * addition of a CRC by the hardware.
1829 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1831 bool crc_en, u16 pacing,
1832 struct i40e_asq_cmd_details *cmd_details)
1834 struct i40e_aq_desc desc;
1835 struct i40e_aq_set_mac_config *cmd =
1836 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1837 enum i40e_status_code status;
1839 if (max_frame_size == 0)
1840 return I40E_ERR_PARAM;
1842 i40e_fill_default_direct_cmd_desc(&desc,
1843 i40e_aqc_opc_set_mac_config);
1845 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1846 cmd->params = ((u8)pacing & 0x0F) << 3;
1848 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1850 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1856 * i40e_aq_clear_pxe_mode
1857 * @hw: pointer to the hw struct
1858 * @cmd_details: pointer to command details structure or NULL
1860 * Tell the firmware that the driver is taking over from PXE
1862 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1863 struct i40e_asq_cmd_details *cmd_details)
1865 enum i40e_status_code status;
1866 struct i40e_aq_desc desc;
1867 struct i40e_aqc_clear_pxe *cmd =
1868 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1870 i40e_fill_default_direct_cmd_desc(&desc,
1871 i40e_aqc_opc_clear_pxe_mode);
1875 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1877 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1883 * i40e_aq_set_link_restart_an
1884 * @hw: pointer to the hw struct
1885 * @enable_link: if true: enable link, if false: disable link
1886 * @cmd_details: pointer to command details structure or NULL
1888 * Sets up the link and restarts the Auto-Negotiation over the link.
1890 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1891 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1893 struct i40e_aq_desc desc;
1894 struct i40e_aqc_set_link_restart_an *cmd =
1895 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1896 enum i40e_status_code status;
1898 i40e_fill_default_direct_cmd_desc(&desc,
1899 i40e_aqc_opc_set_link_restart_an);
1901 cmd->command = I40E_AQ_PHY_RESTART_AN;
1903 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1905 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1907 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1913 * i40e_aq_get_link_info
1914 * @hw: pointer to the hw struct
1915 * @enable_lse: enable/disable LinkStatusEvent reporting
1916 * @link: pointer to link status structure - optional
1917 * @cmd_details: pointer to command details structure or NULL
1919 * Returns the link status of the adapter.
1921 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1922 bool enable_lse, struct i40e_link_status *link,
1923 struct i40e_asq_cmd_details *cmd_details)
1925 struct i40e_aq_desc desc;
1926 struct i40e_aqc_get_link_status *resp =
1927 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1928 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1929 enum i40e_status_code status;
1930 bool tx_pause, rx_pause;
1933 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1936 command_flags = I40E_AQ_LSE_ENABLE;
1938 command_flags = I40E_AQ_LSE_DISABLE;
1939 resp->command_flags = CPU_TO_LE16(command_flags);
1941 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1943 if (status != I40E_SUCCESS)
1944 goto aq_get_link_info_exit;
1946 /* save off old link status information */
1947 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1948 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1950 /* update link status */
1951 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1952 hw->phy.media_type = i40e_get_media_type(hw);
1953 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1954 hw_link_info->link_info = resp->link_info;
1955 hw_link_info->an_info = resp->an_info;
1956 hw_link_info->ext_info = resp->ext_info;
1957 hw_link_info->loopback = resp->loopback;
1958 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1959 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1961 /* update fc info */
1962 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1963 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1964 if (tx_pause & rx_pause)
1965 hw->fc.current_mode = I40E_FC_FULL;
1967 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1969 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1971 hw->fc.current_mode = I40E_FC_NONE;
1973 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1974 hw_link_info->crc_enable = true;
1976 hw_link_info->crc_enable = false;
1978 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1979 hw_link_info->lse_enable = true;
1981 hw_link_info->lse_enable = false;
1983 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1984 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1985 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1987 /* save link status information */
1989 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1990 I40E_NONDMA_TO_NONDMA);
1992 /* flag cleared so helper functions don't call AQ again */
1993 hw->phy.get_link_info = false;
1995 aq_get_link_info_exit:
2000 * i40e_aq_set_phy_int_mask
2001 * @hw: pointer to the hw struct
2002 * @mask: interrupt mask to be set
2003 * @cmd_details: pointer to command details structure or NULL
2005 * Set link interrupt mask.
2007 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2009 struct i40e_asq_cmd_details *cmd_details)
2011 struct i40e_aq_desc desc;
2012 struct i40e_aqc_set_phy_int_mask *cmd =
2013 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2014 enum i40e_status_code status;
2016 i40e_fill_default_direct_cmd_desc(&desc,
2017 i40e_aqc_opc_set_phy_int_mask);
2019 cmd->event_mask = CPU_TO_LE16(mask);
2021 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2027 * i40e_aq_get_local_advt_reg
2028 * @hw: pointer to the hw struct
2029 * @advt_reg: local AN advertisement register value
2030 * @cmd_details: pointer to command details structure or NULL
2032 * Get the Local AN advertisement register value.
2034 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2036 struct i40e_asq_cmd_details *cmd_details)
2038 struct i40e_aq_desc desc;
2039 struct i40e_aqc_an_advt_reg *resp =
2040 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2041 enum i40e_status_code status;
2043 i40e_fill_default_direct_cmd_desc(&desc,
2044 i40e_aqc_opc_get_local_advt_reg);
2046 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2048 if (status != I40E_SUCCESS)
2049 goto aq_get_local_advt_reg_exit;
2051 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2052 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2054 aq_get_local_advt_reg_exit:
2059 * i40e_aq_set_local_advt_reg
2060 * @hw: pointer to the hw struct
2061 * @advt_reg: local AN advertisement register value
2062 * @cmd_details: pointer to command details structure or NULL
2064 * Get the Local AN advertisement register value.
2066 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2068 struct i40e_asq_cmd_details *cmd_details)
2070 struct i40e_aq_desc desc;
2071 struct i40e_aqc_an_advt_reg *cmd =
2072 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2073 enum i40e_status_code status;
2075 i40e_fill_default_direct_cmd_desc(&desc,
2076 i40e_aqc_opc_get_local_advt_reg);
2078 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2079 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2081 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2087 * i40e_aq_get_partner_advt
2088 * @hw: pointer to the hw struct
2089 * @advt_reg: AN partner advertisement register value
2090 * @cmd_details: pointer to command details structure or NULL
2092 * Get the link partner AN advertisement register value.
2094 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2096 struct i40e_asq_cmd_details *cmd_details)
2098 struct i40e_aq_desc desc;
2099 struct i40e_aqc_an_advt_reg *resp =
2100 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2101 enum i40e_status_code status;
2103 i40e_fill_default_direct_cmd_desc(&desc,
2104 i40e_aqc_opc_get_partner_advt);
2106 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2108 if (status != I40E_SUCCESS)
2109 goto aq_get_partner_advt_exit;
2111 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2112 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2114 aq_get_partner_advt_exit:
2119 * i40e_aq_set_lb_modes
2120 * @hw: pointer to the hw struct
2121 * @lb_modes: loopback mode to be set
2122 * @cmd_details: pointer to command details structure or NULL
2124 * Sets loopback modes.
2126 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2128 struct i40e_asq_cmd_details *cmd_details)
2130 struct i40e_aq_desc desc;
2131 struct i40e_aqc_set_lb_mode *cmd =
2132 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2133 enum i40e_status_code status;
2135 i40e_fill_default_direct_cmd_desc(&desc,
2136 i40e_aqc_opc_set_lb_modes);
2138 cmd->lb_mode = CPU_TO_LE16(lb_modes);
2140 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2146 * i40e_aq_set_phy_debug
2147 * @hw: pointer to the hw struct
2148 * @cmd_flags: debug command flags
2149 * @cmd_details: pointer to command details structure or NULL
2151 * Reset the external PHY.
2153 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2154 struct i40e_asq_cmd_details *cmd_details)
2156 struct i40e_aq_desc desc;
2157 struct i40e_aqc_set_phy_debug *cmd =
2158 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2159 enum i40e_status_code status;
2161 i40e_fill_default_direct_cmd_desc(&desc,
2162 i40e_aqc_opc_set_phy_debug);
2164 cmd->command_flags = cmd_flags;
2166 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2173 * @hw: pointer to the hw struct
2174 * @vsi_ctx: pointer to a vsi context struct
2175 * @cmd_details: pointer to command details structure or NULL
2177 * Add a VSI context to the hardware.
2179 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2180 struct i40e_vsi_context *vsi_ctx,
2181 struct i40e_asq_cmd_details *cmd_details)
2183 struct i40e_aq_desc desc;
2184 struct i40e_aqc_add_get_update_vsi *cmd =
2185 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2186 struct i40e_aqc_add_get_update_vsi_completion *resp =
2187 (struct i40e_aqc_add_get_update_vsi_completion *)
2189 enum i40e_status_code status;
2191 i40e_fill_default_direct_cmd_desc(&desc,
2192 i40e_aqc_opc_add_vsi);
2194 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2195 cmd->connection_type = vsi_ctx->connection_type;
2196 cmd->vf_id = vsi_ctx->vf_num;
2197 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2199 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2201 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2202 sizeof(vsi_ctx->info), cmd_details);
2204 if (status != I40E_SUCCESS)
2205 goto aq_add_vsi_exit;
2207 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2208 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2209 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2210 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2217 * i40e_aq_set_default_vsi
2218 * @hw: pointer to the hw struct
2220 * @cmd_details: pointer to command details structure or NULL
2222 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2224 struct i40e_asq_cmd_details *cmd_details)
2226 struct i40e_aq_desc desc;
2227 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2228 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2230 enum i40e_status_code status;
2232 i40e_fill_default_direct_cmd_desc(&desc,
2233 i40e_aqc_opc_set_vsi_promiscuous_modes);
2235 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2236 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2237 cmd->seid = CPU_TO_LE16(seid);
2239 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2245 * i40e_aq_clear_default_vsi
2246 * @hw: pointer to the hw struct
2248 * @cmd_details: pointer to command details structure or NULL
2250 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2252 struct i40e_asq_cmd_details *cmd_details)
2254 struct i40e_aq_desc desc;
2255 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2256 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2258 enum i40e_status_code status;
2260 i40e_fill_default_direct_cmd_desc(&desc,
2261 i40e_aqc_opc_set_vsi_promiscuous_modes);
2263 cmd->promiscuous_flags = CPU_TO_LE16(0);
2264 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2265 cmd->seid = CPU_TO_LE16(seid);
2267 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2273 * i40e_aq_set_vsi_unicast_promiscuous
2274 * @hw: pointer to the hw struct
2276 * @set: set unicast promiscuous enable/disable
2277 * @cmd_details: pointer to command details structure or NULL
2278 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2280 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2282 struct i40e_asq_cmd_details *cmd_details,
2283 bool rx_only_promisc)
2285 struct i40e_aq_desc desc;
2286 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2287 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2288 enum i40e_status_code status;
2291 i40e_fill_default_direct_cmd_desc(&desc,
2292 i40e_aqc_opc_set_vsi_promiscuous_modes);
2295 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2296 if (rx_only_promisc &&
2297 (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2298 (hw->aq.api_maj_ver > 1)))
2299 flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2302 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2304 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2305 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2306 (hw->aq.api_maj_ver > 1))
2307 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2309 cmd->seid = CPU_TO_LE16(seid);
2310 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2316 * i40e_aq_set_vsi_multicast_promiscuous
2317 * @hw: pointer to the hw struct
2319 * @set: set multicast promiscuous enable/disable
2320 * @cmd_details: pointer to command details structure or NULL
2322 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2323 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2325 struct i40e_aq_desc desc;
2326 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2327 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2328 enum i40e_status_code status;
2331 i40e_fill_default_direct_cmd_desc(&desc,
2332 i40e_aqc_opc_set_vsi_promiscuous_modes);
2335 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2337 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2339 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2341 cmd->seid = CPU_TO_LE16(seid);
2342 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2348 * i40e_aq_set_vsi_mc_promisc_on_vlan
2349 * @hw: pointer to the hw struct
2351 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2352 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2353 * @cmd_details: pointer to command details structure or NULL
2355 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2356 u16 seid, bool enable, u16 vid,
2357 struct i40e_asq_cmd_details *cmd_details)
2359 struct i40e_aq_desc desc;
2360 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2361 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2362 enum i40e_status_code status;
2365 i40e_fill_default_direct_cmd_desc(&desc,
2366 i40e_aqc_opc_set_vsi_promiscuous_modes);
2369 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2371 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2372 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2373 cmd->seid = CPU_TO_LE16(seid);
2374 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2376 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2382 * i40e_aq_set_vsi_uc_promisc_on_vlan
2383 * @hw: pointer to the hw struct
2385 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2386 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2387 * @cmd_details: pointer to command details structure or NULL
2389 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2390 u16 seid, bool enable, u16 vid,
2391 struct i40e_asq_cmd_details *cmd_details)
2393 struct i40e_aq_desc desc;
2394 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2395 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2396 enum i40e_status_code status;
2399 i40e_fill_default_direct_cmd_desc(&desc,
2400 i40e_aqc_opc_set_vsi_promiscuous_modes);
2403 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2405 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2406 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2407 cmd->seid = CPU_TO_LE16(seid);
2408 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2410 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2416 * i40e_aq_set_vsi_broadcast
2417 * @hw: pointer to the hw struct
2419 * @set_filter: true to set filter, false to clear filter
2420 * @cmd_details: pointer to command details structure or NULL
2422 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2424 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2425 u16 seid, bool set_filter,
2426 struct i40e_asq_cmd_details *cmd_details)
2428 struct i40e_aq_desc desc;
2429 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2430 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2431 enum i40e_status_code status;
2433 i40e_fill_default_direct_cmd_desc(&desc,
2434 i40e_aqc_opc_set_vsi_promiscuous_modes);
2437 cmd->promiscuous_flags
2438 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2440 cmd->promiscuous_flags
2441 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2443 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2444 cmd->seid = CPU_TO_LE16(seid);
2445 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2451 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2452 * @hw: pointer to the hw struct
2454 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2455 * @cmd_details: pointer to command details structure or NULL
2457 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2458 u16 seid, bool enable,
2459 struct i40e_asq_cmd_details *cmd_details)
2461 struct i40e_aq_desc desc;
2462 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2463 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2464 enum i40e_status_code status;
2467 i40e_fill_default_direct_cmd_desc(&desc,
2468 i40e_aqc_opc_set_vsi_promiscuous_modes);
2470 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2472 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2473 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2474 cmd->seid = CPU_TO_LE16(seid);
2476 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2482 * i40e_get_vsi_params - get VSI configuration info
2483 * @hw: pointer to the hw struct
2484 * @vsi_ctx: pointer to a vsi context struct
2485 * @cmd_details: pointer to command details structure or NULL
2487 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2488 struct i40e_vsi_context *vsi_ctx,
2489 struct i40e_asq_cmd_details *cmd_details)
2491 struct i40e_aq_desc desc;
2492 struct i40e_aqc_add_get_update_vsi *cmd =
2493 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2494 struct i40e_aqc_add_get_update_vsi_completion *resp =
2495 (struct i40e_aqc_add_get_update_vsi_completion *)
2497 enum i40e_status_code status;
2499 UNREFERENCED_1PARAMETER(cmd_details);
2500 i40e_fill_default_direct_cmd_desc(&desc,
2501 i40e_aqc_opc_get_vsi_parameters);
2503 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2505 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2507 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2508 sizeof(vsi_ctx->info), NULL);
2510 if (status != I40E_SUCCESS)
2511 goto aq_get_vsi_params_exit;
2513 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2514 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2515 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2516 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2518 aq_get_vsi_params_exit:
2523 * i40e_aq_update_vsi_params
2524 * @hw: pointer to the hw struct
2525 * @vsi_ctx: pointer to a vsi context struct
2526 * @cmd_details: pointer to command details structure or NULL
2528 * Update a VSI context.
2530 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2531 struct i40e_vsi_context *vsi_ctx,
2532 struct i40e_asq_cmd_details *cmd_details)
2534 struct i40e_aq_desc desc;
2535 struct i40e_aqc_add_get_update_vsi *cmd =
2536 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2537 struct i40e_aqc_add_get_update_vsi_completion *resp =
2538 (struct i40e_aqc_add_get_update_vsi_completion *)
2540 enum i40e_status_code status;
2542 i40e_fill_default_direct_cmd_desc(&desc,
2543 i40e_aqc_opc_update_vsi_parameters);
2544 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2546 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2548 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2549 sizeof(vsi_ctx->info), cmd_details);
2551 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2552 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2558 * i40e_aq_get_switch_config
2559 * @hw: pointer to the hardware structure
2560 * @buf: pointer to the result buffer
2561 * @buf_size: length of input buffer
2562 * @start_seid: seid to start for the report, 0 == beginning
2563 * @cmd_details: pointer to command details structure or NULL
2565 * Fill the buf with switch configuration returned from AdminQ command
2567 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2568 struct i40e_aqc_get_switch_config_resp *buf,
2569 u16 buf_size, u16 *start_seid,
2570 struct i40e_asq_cmd_details *cmd_details)
2572 struct i40e_aq_desc desc;
2573 struct i40e_aqc_switch_seid *scfg =
2574 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2575 enum i40e_status_code status;
2577 i40e_fill_default_direct_cmd_desc(&desc,
2578 i40e_aqc_opc_get_switch_config);
2579 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2580 if (buf_size > I40E_AQ_LARGE_BUF)
2581 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2582 scfg->seid = CPU_TO_LE16(*start_seid);
2584 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2585 *start_seid = LE16_TO_CPU(scfg->seid);
2591 * i40e_aq_set_switch_config
2592 * @hw: pointer to the hardware structure
2593 * @flags: bit flag values to set
2594 * @valid_flags: which bit flags to set
2595 * @cmd_details: pointer to command details structure or NULL
2597 * Set switch configuration bits
2599 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2600 u16 flags, u16 valid_flags,
2601 struct i40e_asq_cmd_details *cmd_details)
2603 struct i40e_aq_desc desc;
2604 struct i40e_aqc_set_switch_config *scfg =
2605 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2606 enum i40e_status_code status;
2608 i40e_fill_default_direct_cmd_desc(&desc,
2609 i40e_aqc_opc_set_switch_config);
2610 scfg->flags = CPU_TO_LE16(flags);
2611 scfg->valid_flags = CPU_TO_LE16(valid_flags);
2613 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2619 * i40e_aq_get_firmware_version
2620 * @hw: pointer to the hw struct
2621 * @fw_major_version: firmware major version
2622 * @fw_minor_version: firmware minor version
2623 * @fw_build: firmware build number
2624 * @api_major_version: major queue version
2625 * @api_minor_version: minor queue version
2626 * @cmd_details: pointer to command details structure or NULL
2628 * Get the firmware version from the admin queue commands
2630 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2631 u16 *fw_major_version, u16 *fw_minor_version,
2633 u16 *api_major_version, u16 *api_minor_version,
2634 struct i40e_asq_cmd_details *cmd_details)
2636 struct i40e_aq_desc desc;
2637 struct i40e_aqc_get_version *resp =
2638 (struct i40e_aqc_get_version *)&desc.params.raw;
2639 enum i40e_status_code status;
2641 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2643 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2645 if (status == I40E_SUCCESS) {
2646 if (fw_major_version != NULL)
2647 *fw_major_version = LE16_TO_CPU(resp->fw_major);
2648 if (fw_minor_version != NULL)
2649 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2650 if (fw_build != NULL)
2651 *fw_build = LE32_TO_CPU(resp->fw_build);
2652 if (api_major_version != NULL)
2653 *api_major_version = LE16_TO_CPU(resp->api_major);
2654 if (api_minor_version != NULL)
2655 *api_minor_version = LE16_TO_CPU(resp->api_minor);
2657 /* A workaround to fix the API version in SW */
2658 if (api_major_version && api_minor_version &&
2659 fw_major_version && fw_minor_version &&
2660 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2661 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2662 (*fw_major_version > 4)))
2663 *api_minor_version = 2;
2670 * i40e_aq_send_driver_version
2671 * @hw: pointer to the hw struct
2672 * @dv: driver's major, minor version
2673 * @cmd_details: pointer to command details structure or NULL
2675 * Send the driver version to the firmware
2677 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2678 struct i40e_driver_version *dv,
2679 struct i40e_asq_cmd_details *cmd_details)
2681 struct i40e_aq_desc desc;
2682 struct i40e_aqc_driver_version *cmd =
2683 (struct i40e_aqc_driver_version *)&desc.params.raw;
2684 enum i40e_status_code status;
2688 return I40E_ERR_PARAM;
2690 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2692 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2693 cmd->driver_major_ver = dv->major_version;
2694 cmd->driver_minor_ver = dv->minor_version;
2695 cmd->driver_build_ver = dv->build_version;
2696 cmd->driver_subbuild_ver = dv->subbuild_version;
2699 while (len < sizeof(dv->driver_string) &&
2700 (dv->driver_string[len] < 0x80) &&
2701 dv->driver_string[len])
2703 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2710 * i40e_get_link_status - get status of the HW network link
2711 * @hw: pointer to the hw struct
2712 * @link_up: pointer to bool (true/false = linkup/linkdown)
2714 * Variable link_up true if link is up, false if link is down.
2715 * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2717 * Side effect: LinkStatusEvent reporting becomes enabled
2719 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2721 enum i40e_status_code status = I40E_SUCCESS;
2723 if (hw->phy.get_link_info) {
2724 status = i40e_update_link_info(hw);
2726 if (status != I40E_SUCCESS)
2727 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2731 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2737 * i40e_updatelink_status - update status of the HW network link
2738 * @hw: pointer to the hw struct
2740 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2742 struct i40e_aq_get_phy_abilities_resp abilities;
2743 enum i40e_status_code status = I40E_SUCCESS;
2745 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2749 if (hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) {
2750 status = i40e_aq_get_phy_capabilities(hw, false, false,
2755 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2756 sizeof(hw->phy.link_info.module_type));
2763 * i40e_get_link_speed
2764 * @hw: pointer to the hw struct
2766 * Returns the link speed of the adapter.
2768 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2770 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2771 enum i40e_status_code status = I40E_SUCCESS;
2773 if (hw->phy.get_link_info) {
2774 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2776 if (status != I40E_SUCCESS)
2777 goto i40e_link_speed_exit;
2780 speed = hw->phy.link_info.link_speed;
2782 i40e_link_speed_exit:
2787 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2788 * @hw: pointer to the hw struct
2789 * @uplink_seid: the MAC or other gizmo SEID
2790 * @downlink_seid: the VSI SEID
2791 * @enabled_tc: bitmap of TCs to be enabled
2792 * @default_port: true for default port VSI, false for control port
2793 * @veb_seid: pointer to where to put the resulting VEB SEID
2794 * @enable_stats: true to turn on VEB stats
2795 * @cmd_details: pointer to command details structure or NULL
2797 * This asks the FW to add a VEB between the uplink and downlink
2798 * elements. If the uplink SEID is 0, this will be a floating VEB.
2800 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2801 u16 downlink_seid, u8 enabled_tc,
2802 bool default_port, u16 *veb_seid,
2804 struct i40e_asq_cmd_details *cmd_details)
2806 struct i40e_aq_desc desc;
2807 struct i40e_aqc_add_veb *cmd =
2808 (struct i40e_aqc_add_veb *)&desc.params.raw;
2809 struct i40e_aqc_add_veb_completion *resp =
2810 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2811 enum i40e_status_code status;
2814 /* SEIDs need to either both be set or both be 0 for floating VEB */
2815 if (!!uplink_seid != !!downlink_seid)
2816 return I40E_ERR_PARAM;
2818 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2820 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2821 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2822 cmd->enable_tcs = enabled_tc;
2824 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2826 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2828 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2830 /* reverse logic here: set the bitflag to disable the stats */
2832 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2834 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2836 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2838 if (!status && veb_seid)
2839 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2845 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2846 * @hw: pointer to the hw struct
2847 * @veb_seid: the SEID of the VEB to query
2848 * @switch_id: the uplink switch id
2849 * @floating: set to true if the VEB is floating
2850 * @statistic_index: index of the stats counter block for this VEB
2851 * @vebs_used: number of VEB's used by function
2852 * @vebs_free: total VEB's not reserved by any function
2853 * @cmd_details: pointer to command details structure or NULL
2855 * This retrieves the parameters for a particular VEB, specified by
2856 * uplink_seid, and returns them to the caller.
2858 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2859 u16 veb_seid, u16 *switch_id,
2860 bool *floating, u16 *statistic_index,
2861 u16 *vebs_used, u16 *vebs_free,
2862 struct i40e_asq_cmd_details *cmd_details)
2864 struct i40e_aq_desc desc;
2865 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2866 (struct i40e_aqc_get_veb_parameters_completion *)
2868 enum i40e_status_code status;
2871 return I40E_ERR_PARAM;
2873 i40e_fill_default_direct_cmd_desc(&desc,
2874 i40e_aqc_opc_get_veb_parameters);
2875 cmd_resp->seid = CPU_TO_LE16(veb_seid);
2877 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2882 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2883 if (statistic_index)
2884 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2886 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2888 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2890 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2892 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2903 * i40e_aq_add_macvlan
2904 * @hw: pointer to the hw struct
2905 * @seid: VSI for the mac address
2906 * @mv_list: list of macvlans to be added
2907 * @count: length of the list
2908 * @cmd_details: pointer to command details structure or NULL
2910 * Add MAC/VLAN addresses to the HW filtering
2912 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2913 struct i40e_aqc_add_macvlan_element_data *mv_list,
2914 u16 count, struct i40e_asq_cmd_details *cmd_details)
2916 struct i40e_aq_desc desc;
2917 struct i40e_aqc_macvlan *cmd =
2918 (struct i40e_aqc_macvlan *)&desc.params.raw;
2919 enum i40e_status_code status;
2923 if (count == 0 || !mv_list || !hw)
2924 return I40E_ERR_PARAM;
2926 buf_size = count * sizeof(*mv_list);
2928 /* prep the rest of the request */
2929 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2930 cmd->num_addresses = CPU_TO_LE16(count);
2931 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2935 for (i = 0; i < count; i++)
2936 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
2938 CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2940 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2941 if (buf_size > I40E_AQ_LARGE_BUF)
2942 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2944 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2951 * i40e_aq_remove_macvlan
2952 * @hw: pointer to the hw struct
2953 * @seid: VSI for the mac address
2954 * @mv_list: list of macvlans to be removed
2955 * @count: length of the list
2956 * @cmd_details: pointer to command details structure or NULL
2958 * Remove MAC/VLAN addresses from the HW filtering
2960 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2961 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2962 u16 count, struct i40e_asq_cmd_details *cmd_details)
2964 struct i40e_aq_desc desc;
2965 struct i40e_aqc_macvlan *cmd =
2966 (struct i40e_aqc_macvlan *)&desc.params.raw;
2967 enum i40e_status_code status;
2970 if (count == 0 || !mv_list || !hw)
2971 return I40E_ERR_PARAM;
2973 buf_size = count * sizeof(*mv_list);
2975 /* prep the rest of the request */
2976 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2977 cmd->num_addresses = CPU_TO_LE16(count);
2978 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2982 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2983 if (buf_size > I40E_AQ_LARGE_BUF)
2984 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2986 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2993 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
2994 * @hw: pointer to the hw struct
2995 * @opcode: AQ opcode for add or delete mirror rule
2996 * @sw_seid: Switch SEID (to which rule refers)
2997 * @rule_type: Rule Type (ingress/egress/VLAN)
2998 * @id: Destination VSI SEID or Rule ID
2999 * @count: length of the list
3000 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3001 * @cmd_details: pointer to command details structure or NULL
3002 * @rule_id: Rule ID returned from FW
3003 * @rule_used: Number of rules used in internal switch
3004 * @rule_free: Number of rules free in internal switch
3006 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3007 * VEBs/VEPA elements only
3009 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3010 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3011 u16 count, __le16 *mr_list,
3012 struct i40e_asq_cmd_details *cmd_details,
3013 u16 *rule_id, u16 *rules_used, u16 *rules_free)
3015 struct i40e_aq_desc desc;
3016 struct i40e_aqc_add_delete_mirror_rule *cmd =
3017 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3018 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3019 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3020 enum i40e_status_code status;
3023 buf_size = count * sizeof(*mr_list);
3025 /* prep the rest of the request */
3026 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3027 cmd->seid = CPU_TO_LE16(sw_seid);
3028 cmd->rule_type = CPU_TO_LE16(rule_type &
3029 I40E_AQC_MIRROR_RULE_TYPE_MASK);
3030 cmd->num_entries = CPU_TO_LE16(count);
3031 /* Dest VSI for add, rule_id for delete */
3032 cmd->destination = CPU_TO_LE16(id);
3034 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3036 if (buf_size > I40E_AQ_LARGE_BUF)
3037 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3040 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3042 if (status == I40E_SUCCESS ||
3043 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3045 *rule_id = LE16_TO_CPU(resp->rule_id);
3047 *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3049 *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3055 * i40e_aq_add_mirrorrule - add a mirror rule
3056 * @hw: pointer to the hw struct
3057 * @sw_seid: Switch SEID (to which rule refers)
3058 * @rule_type: Rule Type (ingress/egress/VLAN)
3059 * @dest_vsi: SEID of VSI to which packets will be mirrored
3060 * @count: length of the list
3061 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3062 * @cmd_details: pointer to command details structure or NULL
3063 * @rule_id: Rule ID returned from FW
3064 * @rule_used: Number of rules used in internal switch
3065 * @rule_free: Number of rules free in internal switch
3067 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3069 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3070 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3071 struct i40e_asq_cmd_details *cmd_details,
3072 u16 *rule_id, u16 *rules_used, u16 *rules_free)
3074 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3075 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3076 if (count == 0 || !mr_list)
3077 return I40E_ERR_PARAM;
3080 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3081 rule_type, dest_vsi, count, mr_list,
3082 cmd_details, rule_id, rules_used, rules_free);
3086 * i40e_aq_delete_mirrorrule - delete a mirror rule
3087 * @hw: pointer to the hw struct
3088 * @sw_seid: Switch SEID (to which rule refers)
3089 * @rule_type: Rule Type (ingress/egress/VLAN)
3090 * @count: length of the list
3091 * @rule_id: Rule ID that is returned in the receive desc as part of
3093 * @mr_list: list of mirrored VLAN IDs to be removed
3094 * @cmd_details: pointer to command details structure or NULL
3095 * @rule_used: Number of rules used in internal switch
3096 * @rule_free: Number of rules free in internal switch
3098 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3100 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3101 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3102 struct i40e_asq_cmd_details *cmd_details,
3103 u16 *rules_used, u16 *rules_free)
3105 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3106 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3107 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3108 * mirroring. For other rule_type, count and rule_type should
3111 if (count == 0 || !mr_list)
3112 return I40E_ERR_PARAM;
3115 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3116 rule_type, rule_id, count, mr_list,
3117 cmd_details, NULL, rules_used, rules_free);
3121 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3122 * @hw: pointer to the hw struct
3123 * @seid: VSI for the vlan filters
3124 * @v_list: list of vlan filters to be added
3125 * @count: length of the list
3126 * @cmd_details: pointer to command details structure or NULL
3128 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3129 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3130 u8 count, struct i40e_asq_cmd_details *cmd_details)
3132 struct i40e_aq_desc desc;
3133 struct i40e_aqc_macvlan *cmd =
3134 (struct i40e_aqc_macvlan *)&desc.params.raw;
3135 enum i40e_status_code status;
3138 if (count == 0 || !v_list || !hw)
3139 return I40E_ERR_PARAM;
3141 buf_size = count * sizeof(*v_list);
3143 /* prep the rest of the request */
3144 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3145 cmd->num_addresses = CPU_TO_LE16(count);
3146 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3150 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3151 if (buf_size > I40E_AQ_LARGE_BUF)
3152 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3154 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3161 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3162 * @hw: pointer to the hw struct
3163 * @seid: VSI for the vlan filters
3164 * @v_list: list of macvlans to be removed
3165 * @count: length of the list
3166 * @cmd_details: pointer to command details structure or NULL
3168 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3169 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3170 u8 count, struct i40e_asq_cmd_details *cmd_details)
3172 struct i40e_aq_desc desc;
3173 struct i40e_aqc_macvlan *cmd =
3174 (struct i40e_aqc_macvlan *)&desc.params.raw;
3175 enum i40e_status_code status;
3178 if (count == 0 || !v_list || !hw)
3179 return I40E_ERR_PARAM;
3181 buf_size = count * sizeof(*v_list);
3183 /* prep the rest of the request */
3184 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3185 cmd->num_addresses = CPU_TO_LE16(count);
3186 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3190 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3191 if (buf_size > I40E_AQ_LARGE_BUF)
3192 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3194 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3201 * i40e_aq_send_msg_to_vf
3202 * @hw: pointer to the hardware structure
3203 * @vfid: vf id to send msg
3204 * @v_opcode: opcodes for VF-PF communication
3205 * @v_retval: return error code
3206 * @msg: pointer to the msg buffer
3207 * @msglen: msg length
3208 * @cmd_details: pointer to command details
3212 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3213 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3214 struct i40e_asq_cmd_details *cmd_details)
3216 struct i40e_aq_desc desc;
3217 struct i40e_aqc_pf_vf_message *cmd =
3218 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3219 enum i40e_status_code status;
3221 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3222 cmd->id = CPU_TO_LE32(vfid);
3223 desc.cookie_high = CPU_TO_LE32(v_opcode);
3224 desc.cookie_low = CPU_TO_LE32(v_retval);
3225 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3227 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3229 if (msglen > I40E_AQ_LARGE_BUF)
3230 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3231 desc.datalen = CPU_TO_LE16(msglen);
3233 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3239 * i40e_aq_debug_read_register
3240 * @hw: pointer to the hw struct
3241 * @reg_addr: register address
3242 * @reg_val: register value
3243 * @cmd_details: pointer to command details structure or NULL
3245 * Read the register using the admin queue commands
3247 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3248 u32 reg_addr, u64 *reg_val,
3249 struct i40e_asq_cmd_details *cmd_details)
3251 struct i40e_aq_desc desc;
3252 struct i40e_aqc_debug_reg_read_write *cmd_resp =
3253 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3254 enum i40e_status_code status;
3256 if (reg_val == NULL)
3257 return I40E_ERR_PARAM;
3259 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3261 cmd_resp->address = CPU_TO_LE32(reg_addr);
3263 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3265 if (status == I40E_SUCCESS) {
3266 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3267 (u64)LE32_TO_CPU(cmd_resp->value_low);
3274 * i40e_aq_debug_write_register
3275 * @hw: pointer to the hw struct
3276 * @reg_addr: register address
3277 * @reg_val: register value
3278 * @cmd_details: pointer to command details structure or NULL
3280 * Write to a register using the admin queue commands
3282 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3283 u32 reg_addr, u64 reg_val,
3284 struct i40e_asq_cmd_details *cmd_details)
3286 struct i40e_aq_desc desc;
3287 struct i40e_aqc_debug_reg_read_write *cmd =
3288 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3289 enum i40e_status_code status;
3291 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3293 cmd->address = CPU_TO_LE32(reg_addr);
3294 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3295 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3297 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3303 * i40e_aq_request_resource
3304 * @hw: pointer to the hw struct
3305 * @resource: resource id
3306 * @access: access type
3307 * @sdp_number: resource number
3308 * @timeout: the maximum time in ms that the driver may hold the resource
3309 * @cmd_details: pointer to command details structure or NULL
3311 * requests common resource using the admin queue commands
3313 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3314 enum i40e_aq_resources_ids resource,
3315 enum i40e_aq_resource_access_type access,
3316 u8 sdp_number, u64 *timeout,
3317 struct i40e_asq_cmd_details *cmd_details)
3319 struct i40e_aq_desc desc;
3320 struct i40e_aqc_request_resource *cmd_resp =
3321 (struct i40e_aqc_request_resource *)&desc.params.raw;
3322 enum i40e_status_code status;
3324 DEBUGFUNC("i40e_aq_request_resource");
3326 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3328 cmd_resp->resource_id = CPU_TO_LE16(resource);
3329 cmd_resp->access_type = CPU_TO_LE16(access);
3330 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3332 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3333 /* The completion specifies the maximum time in ms that the driver
3334 * may hold the resource in the Timeout field.
3335 * If the resource is held by someone else, the command completes with
3336 * busy return value and the timeout field indicates the maximum time
3337 * the current owner of the resource has to free it.
3339 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3340 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3346 * i40e_aq_release_resource
3347 * @hw: pointer to the hw struct
3348 * @resource: resource id
3349 * @sdp_number: resource number
3350 * @cmd_details: pointer to command details structure or NULL
3352 * release common resource using the admin queue commands
3354 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3355 enum i40e_aq_resources_ids resource,
3357 struct i40e_asq_cmd_details *cmd_details)
3359 struct i40e_aq_desc desc;
3360 struct i40e_aqc_request_resource *cmd =
3361 (struct i40e_aqc_request_resource *)&desc.params.raw;
3362 enum i40e_status_code status;
3364 DEBUGFUNC("i40e_aq_release_resource");
3366 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3368 cmd->resource_id = CPU_TO_LE16(resource);
3369 cmd->resource_number = CPU_TO_LE32(sdp_number);
3371 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3378 * @hw: pointer to the hw struct
3379 * @module_pointer: module pointer location in words from the NVM beginning
3380 * @offset: byte offset from the module beginning
3381 * @length: length of the section to be read (in bytes from the offset)
3382 * @data: command buffer (size [bytes] = length)
3383 * @last_command: tells if this is the last command in a series
3384 * @cmd_details: pointer to command details structure or NULL
3386 * Read the NVM using the admin queue commands
3388 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3389 u32 offset, u16 length, void *data,
3391 struct i40e_asq_cmd_details *cmd_details)
3393 struct i40e_aq_desc desc;
3394 struct i40e_aqc_nvm_update *cmd =
3395 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3396 enum i40e_status_code status;
3398 DEBUGFUNC("i40e_aq_read_nvm");
3400 /* In offset the highest byte must be zeroed. */
3401 if (offset & 0xFF000000) {
3402 status = I40E_ERR_PARAM;
3403 goto i40e_aq_read_nvm_exit;
3406 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3408 /* If this is the last command in a series, set the proper flag. */
3410 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3411 cmd->module_pointer = module_pointer;
3412 cmd->offset = CPU_TO_LE32(offset);
3413 cmd->length = CPU_TO_LE16(length);
3415 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3416 if (length > I40E_AQ_LARGE_BUF)
3417 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3419 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3421 i40e_aq_read_nvm_exit:
3426 * i40e_aq_read_nvm_config - read an nvm config block
3427 * @hw: pointer to the hw struct
3428 * @cmd_flags: NVM access admin command bits
3429 * @field_id: field or feature id
3430 * @data: buffer for result
3431 * @buf_size: buffer size
3432 * @element_count: pointer to count of elements read by FW
3433 * @cmd_details: pointer to command details structure or NULL
3435 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3436 u8 cmd_flags, u32 field_id, void *data,
3437 u16 buf_size, u16 *element_count,
3438 struct i40e_asq_cmd_details *cmd_details)
3440 struct i40e_aq_desc desc;
3441 struct i40e_aqc_nvm_config_read *cmd =
3442 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3443 enum i40e_status_code status;
3445 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3446 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3447 if (buf_size > I40E_AQ_LARGE_BUF)
3448 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3450 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3451 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3452 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3453 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3455 cmd->element_id_msw = 0;
3457 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3459 if (!status && element_count)
3460 *element_count = LE16_TO_CPU(cmd->element_count);
3466 * i40e_aq_write_nvm_config - write an nvm config block
3467 * @hw: pointer to the hw struct
3468 * @cmd_flags: NVM access admin command bits
3469 * @data: buffer for result
3470 * @buf_size: buffer size
3471 * @element_count: count of elements to be written
3472 * @cmd_details: pointer to command details structure or NULL
3474 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3475 u8 cmd_flags, void *data, u16 buf_size,
3477 struct i40e_asq_cmd_details *cmd_details)
3479 struct i40e_aq_desc desc;
3480 struct i40e_aqc_nvm_config_write *cmd =
3481 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3482 enum i40e_status_code status;
3484 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3485 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3486 if (buf_size > I40E_AQ_LARGE_BUF)
3487 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3489 cmd->element_count = CPU_TO_LE16(element_count);
3490 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3491 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3497 * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3498 * @hw: pointer to the hw struct
3499 * @cmd_details: pointer to command details structure or NULL
3501 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3502 void *buff, u16 buff_size,
3503 struct i40e_asq_cmd_details *cmd_details)
3505 struct i40e_aq_desc desc;
3506 enum i40e_status_code status;
3508 UNREFERENCED_2PARAMETER(buff, buff_size);
3510 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3511 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3512 if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3513 status = I40E_ERR_NOT_IMPLEMENTED;
3520 * @hw: pointer to the hw struct
3521 * @module_pointer: module pointer location in words from the NVM beginning
3522 * @offset: offset in the module (expressed in 4 KB from module's beginning)
3523 * @length: length of the section to be erased (expressed in 4 KB)
3524 * @last_command: tells if this is the last command in a series
3525 * @cmd_details: pointer to command details structure or NULL
3527 * Erase the NVM sector using the admin queue commands
3529 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3530 u32 offset, u16 length, bool last_command,
3531 struct i40e_asq_cmd_details *cmd_details)
3533 struct i40e_aq_desc desc;
3534 struct i40e_aqc_nvm_update *cmd =
3535 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3536 enum i40e_status_code status;
3538 DEBUGFUNC("i40e_aq_erase_nvm");
3540 /* In offset the highest byte must be zeroed. */
3541 if (offset & 0xFF000000) {
3542 status = I40E_ERR_PARAM;
3543 goto i40e_aq_erase_nvm_exit;
3546 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3548 /* If this is the last command in a series, set the proper flag. */
3550 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3551 cmd->module_pointer = module_pointer;
3552 cmd->offset = CPU_TO_LE32(offset);
3553 cmd->length = CPU_TO_LE16(length);
3555 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3557 i40e_aq_erase_nvm_exit:
3562 * i40e_parse_discover_capabilities
3563 * @hw: pointer to the hw struct
3564 * @buff: pointer to a buffer containing device/function capability records
3565 * @cap_count: number of capability records in the list
3566 * @list_type_opc: type of capabilities list to parse
3568 * Parse the device/function capabilities list.
3570 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3572 enum i40e_admin_queue_opc list_type_opc)
3574 struct i40e_aqc_list_capabilities_element_resp *cap;
3575 u32 valid_functions, num_functions;
3576 u32 number, logical_id, phys_id;
3577 struct i40e_hw_capabilities *p;
3582 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3584 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3585 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3586 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3587 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3591 for (i = 0; i < cap_count; i++, cap++) {
3592 id = LE16_TO_CPU(cap->id);
3593 number = LE32_TO_CPU(cap->number);
3594 logical_id = LE32_TO_CPU(cap->logical_id);
3595 phys_id = LE32_TO_CPU(cap->phys_id);
3596 major_rev = cap->major_rev;
3599 case I40E_AQ_CAP_ID_SWITCH_MODE:
3600 p->switch_mode = number;
3601 i40e_debug(hw, I40E_DEBUG_INIT,
3602 "HW Capability: Switch mode = %d\n",
3605 case I40E_AQ_CAP_ID_MNG_MODE:
3606 p->management_mode = number;
3607 i40e_debug(hw, I40E_DEBUG_INIT,
3608 "HW Capability: Management Mode = %d\n",
3609 p->management_mode);
3611 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3612 p->npar_enable = number;
3613 i40e_debug(hw, I40E_DEBUG_INIT,
3614 "HW Capability: NPAR enable = %d\n",
3617 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3619 i40e_debug(hw, I40E_DEBUG_INIT,
3620 "HW Capability: OS2BMC = %d\n", p->os2bmc);
3622 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3623 p->valid_functions = number;
3624 i40e_debug(hw, I40E_DEBUG_INIT,
3625 "HW Capability: Valid Functions = %d\n",
3626 p->valid_functions);
3628 case I40E_AQ_CAP_ID_SRIOV:
3630 p->sr_iov_1_1 = true;
3631 i40e_debug(hw, I40E_DEBUG_INIT,
3632 "HW Capability: SR-IOV = %d\n",
3635 case I40E_AQ_CAP_ID_VF:
3636 p->num_vfs = number;
3637 p->vf_base_id = logical_id;
3638 i40e_debug(hw, I40E_DEBUG_INIT,
3639 "HW Capability: VF count = %d\n",
3641 i40e_debug(hw, I40E_DEBUG_INIT,
3642 "HW Capability: VF base_id = %d\n",
3645 case I40E_AQ_CAP_ID_VMDQ:
3648 i40e_debug(hw, I40E_DEBUG_INIT,
3649 "HW Capability: VMDQ = %d\n", p->vmdq);
3651 case I40E_AQ_CAP_ID_8021QBG:
3653 p->evb_802_1_qbg = true;
3654 i40e_debug(hw, I40E_DEBUG_INIT,
3655 "HW Capability: 802.1Qbg = %d\n", number);
3657 case I40E_AQ_CAP_ID_8021QBR:
3659 p->evb_802_1_qbh = true;
3660 i40e_debug(hw, I40E_DEBUG_INIT,
3661 "HW Capability: 802.1Qbh = %d\n", number);
3663 case I40E_AQ_CAP_ID_VSI:
3664 p->num_vsis = number;
3665 i40e_debug(hw, I40E_DEBUG_INIT,
3666 "HW Capability: VSI count = %d\n",
3669 case I40E_AQ_CAP_ID_DCB:
3672 p->enabled_tcmap = logical_id;
3675 i40e_debug(hw, I40E_DEBUG_INIT,
3676 "HW Capability: DCB = %d\n", p->dcb);
3677 i40e_debug(hw, I40E_DEBUG_INIT,
3678 "HW Capability: TC Mapping = %d\n",
3680 i40e_debug(hw, I40E_DEBUG_INIT,
3681 "HW Capability: TC Max = %d\n", p->maxtc);
3683 case I40E_AQ_CAP_ID_FCOE:
3686 i40e_debug(hw, I40E_DEBUG_INIT,
3687 "HW Capability: FCOE = %d\n", p->fcoe);
3689 case I40E_AQ_CAP_ID_ISCSI:
3692 i40e_debug(hw, I40E_DEBUG_INIT,
3693 "HW Capability: iSCSI = %d\n", p->iscsi);
3695 case I40E_AQ_CAP_ID_RSS:
3697 p->rss_table_size = number;
3698 p->rss_table_entry_width = logical_id;
3699 i40e_debug(hw, I40E_DEBUG_INIT,
3700 "HW Capability: RSS = %d\n", p->rss);
3701 i40e_debug(hw, I40E_DEBUG_INIT,
3702 "HW Capability: RSS table size = %d\n",
3704 i40e_debug(hw, I40E_DEBUG_INIT,
3705 "HW Capability: RSS table width = %d\n",
3706 p->rss_table_entry_width);
3708 case I40E_AQ_CAP_ID_RXQ:
3709 p->num_rx_qp = number;
3710 p->base_queue = phys_id;
3711 i40e_debug(hw, I40E_DEBUG_INIT,
3712 "HW Capability: Rx QP = %d\n", number);
3713 i40e_debug(hw, I40E_DEBUG_INIT,
3714 "HW Capability: base_queue = %d\n",
3717 case I40E_AQ_CAP_ID_TXQ:
3718 p->num_tx_qp = number;
3719 p->base_queue = phys_id;
3720 i40e_debug(hw, I40E_DEBUG_INIT,
3721 "HW Capability: Tx QP = %d\n", number);
3722 i40e_debug(hw, I40E_DEBUG_INIT,
3723 "HW Capability: base_queue = %d\n",
3726 case I40E_AQ_CAP_ID_MSIX:
3727 p->num_msix_vectors = number;
3728 i40e_debug(hw, I40E_DEBUG_INIT,
3729 "HW Capability: MSIX vector count = %d\n",
3730 p->num_msix_vectors);
3732 case I40E_AQ_CAP_ID_VF_MSIX:
3733 p->num_msix_vectors_vf = number;
3734 i40e_debug(hw, I40E_DEBUG_INIT,
3735 "HW Capability: MSIX VF vector count = %d\n",
3736 p->num_msix_vectors_vf);
3738 case I40E_AQ_CAP_ID_FLEX10:
3739 if (major_rev == 1) {
3741 p->flex10_enable = true;
3742 p->flex10_capable = true;
3745 /* Capability revision >= 2 */
3747 p->flex10_enable = true;
3749 p->flex10_capable = true;
3751 p->flex10_mode = logical_id;
3752 p->flex10_status = phys_id;
3753 i40e_debug(hw, I40E_DEBUG_INIT,
3754 "HW Capability: Flex10 mode = %d\n",
3756 i40e_debug(hw, I40E_DEBUG_INIT,
3757 "HW Capability: Flex10 status = %d\n",
3760 case I40E_AQ_CAP_ID_CEM:
3763 i40e_debug(hw, I40E_DEBUG_INIT,
3764 "HW Capability: CEM = %d\n", p->mgmt_cem);
3766 case I40E_AQ_CAP_ID_IWARP:
3769 i40e_debug(hw, I40E_DEBUG_INIT,
3770 "HW Capability: iWARP = %d\n", p->iwarp);
3772 case I40E_AQ_CAP_ID_LED:
3773 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3774 p->led[phys_id] = true;
3775 i40e_debug(hw, I40E_DEBUG_INIT,
3776 "HW Capability: LED - PIN %d\n", phys_id);
3778 case I40E_AQ_CAP_ID_SDP:
3779 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3780 p->sdp[phys_id] = true;
3781 i40e_debug(hw, I40E_DEBUG_INIT,
3782 "HW Capability: SDP - PIN %d\n", phys_id);
3784 case I40E_AQ_CAP_ID_MDIO:
3786 p->mdio_port_num = phys_id;
3787 p->mdio_port_mode = logical_id;
3789 i40e_debug(hw, I40E_DEBUG_INIT,
3790 "HW Capability: MDIO port number = %d\n",
3792 i40e_debug(hw, I40E_DEBUG_INIT,
3793 "HW Capability: MDIO port mode = %d\n",
3796 case I40E_AQ_CAP_ID_1588:
3798 p->ieee_1588 = true;
3799 i40e_debug(hw, I40E_DEBUG_INIT,
3800 "HW Capability: IEEE 1588 = %d\n",
3803 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3805 p->fd_filters_guaranteed = number;
3806 p->fd_filters_best_effort = logical_id;
3807 i40e_debug(hw, I40E_DEBUG_INIT,
3808 "HW Capability: Flow Director = 1\n");
3809 i40e_debug(hw, I40E_DEBUG_INIT,
3810 "HW Capability: Guaranteed FD filters = %d\n",
3811 p->fd_filters_guaranteed);
3813 case I40E_AQ_CAP_ID_WSR_PROT:
3814 p->wr_csr_prot = (u64)number;
3815 p->wr_csr_prot |= (u64)logical_id << 32;
3816 i40e_debug(hw, I40E_DEBUG_INIT,
3817 "HW Capability: wr_csr_prot = 0x%llX\n\n",
3818 (p->wr_csr_prot & 0xffff));
3820 case I40E_AQ_CAP_ID_NVM_MGMT:
3821 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3822 p->sec_rev_disabled = true;
3823 if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3824 p->update_disabled = true;
3827 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3828 hw->num_wol_proxy_filters = (u16)number;
3829 hw->wol_proxy_vsi_seid = (u16)logical_id;
3830 p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3831 if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3832 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3834 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3835 p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3836 p->proxy_support = p->proxy_support;
3837 i40e_debug(hw, I40E_DEBUG_INIT,
3838 "HW Capability: WOL proxy filters = %d\n",
3839 hw->num_wol_proxy_filters);
3848 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3850 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3853 /* count the enabled ports (aka the "not disabled" ports) */
3855 for (i = 0; i < 4; i++) {
3856 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3859 /* use AQ read to get the physical register offset instead
3860 * of the port relative offset
3862 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3863 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3867 valid_functions = p->valid_functions;
3869 while (valid_functions) {
3870 if (valid_functions & 1)
3872 valid_functions >>= 1;
3875 /* partition id is 1-based, and functions are evenly spread
3876 * across the ports as partitions
3878 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3879 hw->num_partitions = num_functions / hw->num_ports;
3881 /* additional HW specific goodies that might
3882 * someday be HW version specific
3884 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3888 * i40e_aq_discover_capabilities
3889 * @hw: pointer to the hw struct
3890 * @buff: a virtual buffer to hold the capabilities
3891 * @buff_size: Size of the virtual buffer
3892 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3893 * @list_type_opc: capabilities type to discover - pass in the command opcode
3894 * @cmd_details: pointer to command details structure or NULL
3896 * Get the device capabilities descriptions from the firmware
3898 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3899 void *buff, u16 buff_size, u16 *data_size,
3900 enum i40e_admin_queue_opc list_type_opc,
3901 struct i40e_asq_cmd_details *cmd_details)
3903 struct i40e_aqc_list_capabilites *cmd;
3904 struct i40e_aq_desc desc;
3905 enum i40e_status_code status = I40E_SUCCESS;
3907 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3909 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3910 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3911 status = I40E_ERR_PARAM;
3915 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3917 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3918 if (buff_size > I40E_AQ_LARGE_BUF)
3919 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3921 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3922 *data_size = LE16_TO_CPU(desc.datalen);
3927 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3935 * i40e_aq_update_nvm
3936 * @hw: pointer to the hw struct
3937 * @module_pointer: module pointer location in words from the NVM beginning
3938 * @offset: byte offset from the module beginning
3939 * @length: length of the section to be written (in bytes from the offset)
3940 * @data: command buffer (size [bytes] = length)
3941 * @last_command: tells if this is the last command in a series
3942 * @cmd_details: pointer to command details structure or NULL
3944 * Update the NVM using the admin queue commands
3946 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3947 u32 offset, u16 length, void *data,
3949 struct i40e_asq_cmd_details *cmd_details)
3951 struct i40e_aq_desc desc;
3952 struct i40e_aqc_nvm_update *cmd =
3953 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3954 enum i40e_status_code status;
3956 DEBUGFUNC("i40e_aq_update_nvm");
3958 /* In offset the highest byte must be zeroed. */
3959 if (offset & 0xFF000000) {
3960 status = I40E_ERR_PARAM;
3961 goto i40e_aq_update_nvm_exit;
3964 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3966 /* If this is the last command in a series, set the proper flag. */
3968 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3969 cmd->module_pointer = module_pointer;
3970 cmd->offset = CPU_TO_LE32(offset);
3971 cmd->length = CPU_TO_LE16(length);
3973 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3974 if (length > I40E_AQ_LARGE_BUF)
3975 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3977 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3979 i40e_aq_update_nvm_exit:
3984 * i40e_aq_get_lldp_mib
3985 * @hw: pointer to the hw struct
3986 * @bridge_type: type of bridge requested
3987 * @mib_type: Local, Remote or both Local and Remote MIBs
3988 * @buff: pointer to a user supplied buffer to store the MIB block
3989 * @buff_size: size of the buffer (in bytes)
3990 * @local_len : length of the returned Local LLDP MIB
3991 * @remote_len: length of the returned Remote LLDP MIB
3992 * @cmd_details: pointer to command details structure or NULL
3994 * Requests the complete LLDP MIB (entire packet).
3996 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3997 u8 mib_type, void *buff, u16 buff_size,
3998 u16 *local_len, u16 *remote_len,
3999 struct i40e_asq_cmd_details *cmd_details)
4001 struct i40e_aq_desc desc;
4002 struct i40e_aqc_lldp_get_mib *cmd =
4003 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4004 struct i40e_aqc_lldp_get_mib *resp =
4005 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4006 enum i40e_status_code status;
4008 if (buff_size == 0 || !buff)
4009 return I40E_ERR_PARAM;
4011 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4012 /* Indirect Command */
4013 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4015 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4016 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4017 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4019 desc.datalen = CPU_TO_LE16(buff_size);
4021 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4022 if (buff_size > I40E_AQ_LARGE_BUF)
4023 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4025 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4027 if (local_len != NULL)
4028 *local_len = LE16_TO_CPU(resp->local_len);
4029 if (remote_len != NULL)
4030 *remote_len = LE16_TO_CPU(resp->remote_len);
4037 * i40e_aq_set_lldp_mib - Set the LLDP MIB
4038 * @hw: pointer to the hw struct
4039 * @mib_type: Local, Remote or both Local and Remote MIBs
4040 * @buff: pointer to a user supplied buffer to store the MIB block
4041 * @buff_size: size of the buffer (in bytes)
4042 * @cmd_details: pointer to command details structure or NULL
4046 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4047 u8 mib_type, void *buff, u16 buff_size,
4048 struct i40e_asq_cmd_details *cmd_details)
4050 struct i40e_aq_desc desc;
4051 struct i40e_aqc_lldp_set_local_mib *cmd =
4052 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4053 enum i40e_status_code status;
4055 if (buff_size == 0 || !buff)
4056 return I40E_ERR_PARAM;
4058 i40e_fill_default_direct_cmd_desc(&desc,
4059 i40e_aqc_opc_lldp_set_local_mib);
4060 /* Indirect Command */
4061 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4062 if (buff_size > I40E_AQ_LARGE_BUF)
4063 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4064 desc.datalen = CPU_TO_LE16(buff_size);
4066 cmd->type = mib_type;
4067 cmd->length = CPU_TO_LE16(buff_size);
4068 cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4069 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4071 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4076 * i40e_aq_cfg_lldp_mib_change_event
4077 * @hw: pointer to the hw struct
4078 * @enable_update: Enable or Disable event posting
4079 * @cmd_details: pointer to command details structure or NULL
4081 * Enable or Disable posting of an event on ARQ when LLDP MIB
4082 * associated with the interface changes
4084 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4086 struct i40e_asq_cmd_details *cmd_details)
4088 struct i40e_aq_desc desc;
4089 struct i40e_aqc_lldp_update_mib *cmd =
4090 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4091 enum i40e_status_code status;
4093 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4096 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4098 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4104 * i40e_aq_add_lldp_tlv
4105 * @hw: pointer to the hw struct
4106 * @bridge_type: type of bridge
4107 * @buff: buffer with TLV to add
4108 * @buff_size: length of the buffer
4109 * @tlv_len: length of the TLV to be added
4110 * @mib_len: length of the LLDP MIB returned in response
4111 * @cmd_details: pointer to command details structure or NULL
4113 * Add the specified TLV to LLDP Local MIB for the given bridge type,
4114 * it is responsibility of the caller to make sure that the TLV is not
4115 * already present in the LLDPDU.
4116 * In return firmware will write the complete LLDP MIB with the newly
4117 * added TLV in the response buffer.
4119 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4120 void *buff, u16 buff_size, u16 tlv_len,
4122 struct i40e_asq_cmd_details *cmd_details)
4124 struct i40e_aq_desc desc;
4125 struct i40e_aqc_lldp_add_tlv *cmd =
4126 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4127 enum i40e_status_code status;
4129 if (buff_size == 0 || !buff || tlv_len == 0)
4130 return I40E_ERR_PARAM;
4132 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4134 /* Indirect Command */
4135 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4136 if (buff_size > I40E_AQ_LARGE_BUF)
4137 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4138 desc.datalen = CPU_TO_LE16(buff_size);
4140 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4141 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4142 cmd->len = CPU_TO_LE16(tlv_len);
4144 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4146 if (mib_len != NULL)
4147 *mib_len = LE16_TO_CPU(desc.datalen);
4154 * i40e_aq_update_lldp_tlv
4155 * @hw: pointer to the hw struct
4156 * @bridge_type: type of bridge
4157 * @buff: buffer with TLV to update
4158 * @buff_size: size of the buffer holding original and updated TLVs
4159 * @old_len: Length of the Original TLV
4160 * @new_len: Length of the Updated TLV
4161 * @offset: offset of the updated TLV in the buff
4162 * @mib_len: length of the returned LLDP MIB
4163 * @cmd_details: pointer to command details structure or NULL
4165 * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4166 * Firmware will place the complete LLDP MIB in response buffer with the
4169 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4170 u8 bridge_type, void *buff, u16 buff_size,
4171 u16 old_len, u16 new_len, u16 offset,
4173 struct i40e_asq_cmd_details *cmd_details)
4175 struct i40e_aq_desc desc;
4176 struct i40e_aqc_lldp_update_tlv *cmd =
4177 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4178 enum i40e_status_code status;
4180 if (buff_size == 0 || !buff || offset == 0 ||
4181 old_len == 0 || new_len == 0)
4182 return I40E_ERR_PARAM;
4184 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4186 /* Indirect Command */
4187 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4188 if (buff_size > I40E_AQ_LARGE_BUF)
4189 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4190 desc.datalen = CPU_TO_LE16(buff_size);
4192 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4193 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4194 cmd->old_len = CPU_TO_LE16(old_len);
4195 cmd->new_offset = CPU_TO_LE16(offset);
4196 cmd->new_len = CPU_TO_LE16(new_len);
4198 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4200 if (mib_len != NULL)
4201 *mib_len = LE16_TO_CPU(desc.datalen);
4208 * i40e_aq_delete_lldp_tlv
4209 * @hw: pointer to the hw struct
4210 * @bridge_type: type of bridge
4211 * @buff: pointer to a user supplied buffer that has the TLV
4212 * @buff_size: length of the buffer
4213 * @tlv_len: length of the TLV to be deleted
4214 * @mib_len: length of the returned LLDP MIB
4215 * @cmd_details: pointer to command details structure or NULL
4217 * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4218 * The firmware places the entire LLDP MIB in the response buffer.
4220 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4221 u8 bridge_type, void *buff, u16 buff_size,
4222 u16 tlv_len, u16 *mib_len,
4223 struct i40e_asq_cmd_details *cmd_details)
4225 struct i40e_aq_desc desc;
4226 struct i40e_aqc_lldp_add_tlv *cmd =
4227 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4228 enum i40e_status_code status;
4230 if (buff_size == 0 || !buff)
4231 return I40E_ERR_PARAM;
4233 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4235 /* Indirect Command */
4236 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4237 if (buff_size > I40E_AQ_LARGE_BUF)
4238 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4239 desc.datalen = CPU_TO_LE16(buff_size);
4240 cmd->len = CPU_TO_LE16(tlv_len);
4241 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4242 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4244 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4246 if (mib_len != NULL)
4247 *mib_len = LE16_TO_CPU(desc.datalen);
4255 * @hw: pointer to the hw struct
4256 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4257 * @cmd_details: pointer to command details structure or NULL
4259 * Stop or Shutdown the embedded LLDP Agent
4261 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4262 struct i40e_asq_cmd_details *cmd_details)
4264 struct i40e_aq_desc desc;
4265 struct i40e_aqc_lldp_stop *cmd =
4266 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4267 enum i40e_status_code status;
4269 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4272 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4274 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4280 * i40e_aq_start_lldp
4281 * @hw: pointer to the hw struct
4282 * @cmd_details: pointer to command details structure or NULL
4284 * Start the embedded LLDP Agent on all ports.
4286 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4287 struct i40e_asq_cmd_details *cmd_details)
4289 struct i40e_aq_desc desc;
4290 struct i40e_aqc_lldp_start *cmd =
4291 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4292 enum i40e_status_code status;
4294 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4296 cmd->command = I40E_AQ_LLDP_AGENT_START;
4298 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4304 * i40e_aq_get_cee_dcb_config
4305 * @hw: pointer to the hw struct
4306 * @buff: response buffer that stores CEE operational configuration
4307 * @buff_size: size of the buffer passed
4308 * @cmd_details: pointer to command details structure or NULL
4310 * Get CEE DCBX mode operational configuration from firmware
4312 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4313 void *buff, u16 buff_size,
4314 struct i40e_asq_cmd_details *cmd_details)
4316 struct i40e_aq_desc desc;
4317 enum i40e_status_code status;
4319 if (buff_size == 0 || !buff)
4320 return I40E_ERR_PARAM;
4322 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4324 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4325 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4332 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4333 * @hw: pointer to the hw struct
4334 * @start_agent: True if DCBx Agent needs to be Started
4335 * False if DCBx Agent needs to be Stopped
4336 * @cmd_details: pointer to command details structure or NULL
4338 * Start/Stop the embedded dcbx Agent
4340 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4342 struct i40e_asq_cmd_details *cmd_details)
4344 struct i40e_aq_desc desc;
4345 struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4346 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4348 enum i40e_status_code status;
4350 i40e_fill_default_direct_cmd_desc(&desc,
4351 i40e_aqc_opc_lldp_stop_start_spec_agent);
4354 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4356 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4362 * i40e_aq_add_udp_tunnel
4363 * @hw: pointer to the hw struct
4364 * @udp_port: the UDP port to add
4365 * @header_len: length of the tunneling header length in DWords
4366 * @protocol_index: protocol index type
4367 * @filter_index: pointer to filter index
4368 * @cmd_details: pointer to command details structure or NULL
4370 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4371 u16 udp_port, u8 protocol_index,
4373 struct i40e_asq_cmd_details *cmd_details)
4375 struct i40e_aq_desc desc;
4376 struct i40e_aqc_add_udp_tunnel *cmd =
4377 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4378 struct i40e_aqc_del_udp_tunnel_completion *resp =
4379 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4380 enum i40e_status_code status;
4382 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4384 cmd->udp_port = CPU_TO_LE16(udp_port);
4385 cmd->protocol_type = protocol_index;
4387 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4389 if (!status && filter_index)
4390 *filter_index = resp->index;
4396 * i40e_aq_del_udp_tunnel
4397 * @hw: pointer to the hw struct
4398 * @index: filter index
4399 * @cmd_details: pointer to command details structure or NULL
4401 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4402 struct i40e_asq_cmd_details *cmd_details)
4404 struct i40e_aq_desc desc;
4405 struct i40e_aqc_remove_udp_tunnel *cmd =
4406 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4407 enum i40e_status_code status;
4409 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4413 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4419 * i40e_aq_get_switch_resource_alloc (0x0204)
4420 * @hw: pointer to the hw struct
4421 * @num_entries: pointer to u8 to store the number of resource entries returned
4422 * @buf: pointer to a user supplied buffer. This buffer must be large enough
4423 * to store the resource information for all resource types. Each
4424 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
4425 * @count: size, in bytes, of the buffer provided
4426 * @cmd_details: pointer to command details structure or NULL
4428 * Query the resources allocated to a function.
4430 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4432 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4434 struct i40e_asq_cmd_details *cmd_details)
4436 struct i40e_aq_desc desc;
4437 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4438 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4439 enum i40e_status_code status;
4440 u16 length = count * sizeof(*buf);
4442 i40e_fill_default_direct_cmd_desc(&desc,
4443 i40e_aqc_opc_get_switch_resource_alloc);
4445 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4446 if (length > I40E_AQ_LARGE_BUF)
4447 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4449 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4451 if (!status && num_entries)
4452 *num_entries = cmd_resp->num_entries;
4458 * i40e_aq_delete_element - Delete switch element
4459 * @hw: pointer to the hw struct
4460 * @seid: the SEID to delete from the switch
4461 * @cmd_details: pointer to command details structure or NULL
4463 * This deletes a switch element from the switch.
4465 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4466 struct i40e_asq_cmd_details *cmd_details)
4468 struct i40e_aq_desc desc;
4469 struct i40e_aqc_switch_seid *cmd =
4470 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4471 enum i40e_status_code status;
4474 return I40E_ERR_PARAM;
4476 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4478 cmd->seid = CPU_TO_LE16(seid);
4480 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4486 * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4487 * @hw: pointer to the hw struct
4488 * @flags: component flags
4489 * @mac_seid: uplink seid (MAC SEID)
4490 * @vsi_seid: connected vsi seid
4491 * @ret_seid: seid of create pv component
4493 * This instantiates an i40e port virtualizer with specified flags.
4494 * Depending on specified flags the port virtualizer can act as a
4495 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4497 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4498 u16 mac_seid, u16 vsi_seid,
4501 struct i40e_aq_desc desc;
4502 struct i40e_aqc_add_update_pv *cmd =
4503 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4504 struct i40e_aqc_add_update_pv_completion *resp =
4505 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4506 enum i40e_status_code status;
4509 return I40E_ERR_PARAM;
4511 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4512 cmd->command_flags = CPU_TO_LE16(flags);
4513 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4514 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4516 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4517 if (!status && ret_seid)
4518 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4524 * i40e_aq_add_tag - Add an S/E-tag
4525 * @hw: pointer to the hw struct
4526 * @direct_to_queue: should s-tag direct flow to a specific queue
4527 * @vsi_seid: VSI SEID to use this tag
4528 * @tag: value of the tag
4529 * @queue_num: queue number, only valid is direct_to_queue is true
4530 * @tags_used: return value, number of tags in use by this PF
4531 * @tags_free: return value, number of unallocated tags
4532 * @cmd_details: pointer to command details structure or NULL
4534 * This associates an S- or E-tag to a VSI in the switch complex. It returns
4535 * the number of tags allocated by the PF, and the number of unallocated
4538 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4539 u16 vsi_seid, u16 tag, u16 queue_num,
4540 u16 *tags_used, u16 *tags_free,
4541 struct i40e_asq_cmd_details *cmd_details)
4543 struct i40e_aq_desc desc;
4544 struct i40e_aqc_add_tag *cmd =
4545 (struct i40e_aqc_add_tag *)&desc.params.raw;
4546 struct i40e_aqc_add_remove_tag_completion *resp =
4547 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4548 enum i40e_status_code status;
4551 return I40E_ERR_PARAM;
4553 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4555 cmd->seid = CPU_TO_LE16(vsi_seid);
4556 cmd->tag = CPU_TO_LE16(tag);
4557 if (direct_to_queue) {
4558 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4559 cmd->queue_number = CPU_TO_LE16(queue_num);
4562 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4565 if (tags_used != NULL)
4566 *tags_used = LE16_TO_CPU(resp->tags_used);
4567 if (tags_free != NULL)
4568 *tags_free = LE16_TO_CPU(resp->tags_free);
4575 * i40e_aq_remove_tag - Remove an S- or E-tag
4576 * @hw: pointer to the hw struct
4577 * @vsi_seid: VSI SEID this tag is associated with
4578 * @tag: value of the S-tag to delete
4579 * @tags_used: return value, number of tags in use by this PF
4580 * @tags_free: return value, number of unallocated tags
4581 * @cmd_details: pointer to command details structure or NULL
4583 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
4584 * the number of tags allocated by the PF, and the number of unallocated
4587 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4588 u16 tag, u16 *tags_used, u16 *tags_free,
4589 struct i40e_asq_cmd_details *cmd_details)
4591 struct i40e_aq_desc desc;
4592 struct i40e_aqc_remove_tag *cmd =
4593 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4594 struct i40e_aqc_add_remove_tag_completion *resp =
4595 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4596 enum i40e_status_code status;
4599 return I40E_ERR_PARAM;
4601 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4603 cmd->seid = CPU_TO_LE16(vsi_seid);
4604 cmd->tag = CPU_TO_LE16(tag);
4606 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4609 if (tags_used != NULL)
4610 *tags_used = LE16_TO_CPU(resp->tags_used);
4611 if (tags_free != NULL)
4612 *tags_free = LE16_TO_CPU(resp->tags_free);
4619 * i40e_aq_add_mcast_etag - Add a multicast E-tag
4620 * @hw: pointer to the hw struct
4621 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4622 * @etag: value of E-tag to add
4623 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4624 * @buf: address of indirect buffer
4625 * @tags_used: return value, number of E-tags in use by this port
4626 * @tags_free: return value, number of unallocated M-tags
4627 * @cmd_details: pointer to command details structure or NULL
4629 * This associates a multicast E-tag to a port virtualizer. It will return
4630 * the number of tags allocated by the PF, and the number of unallocated
4633 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4634 * num_tags_in_buf long.
4636 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4637 u16 etag, u8 num_tags_in_buf, void *buf,
4638 u16 *tags_used, u16 *tags_free,
4639 struct i40e_asq_cmd_details *cmd_details)
4641 struct i40e_aq_desc desc;
4642 struct i40e_aqc_add_remove_mcast_etag *cmd =
4643 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4644 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4645 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4646 enum i40e_status_code status;
4647 u16 length = sizeof(u16) * num_tags_in_buf;
4649 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4650 return I40E_ERR_PARAM;
4652 i40e_fill_default_direct_cmd_desc(&desc,
4653 i40e_aqc_opc_add_multicast_etag);
4655 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4656 cmd->etag = CPU_TO_LE16(etag);
4657 cmd->num_unicast_etags = num_tags_in_buf;
4659 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4660 if (length > I40E_AQ_LARGE_BUF)
4661 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4663 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4666 if (tags_used != NULL)
4667 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4668 if (tags_free != NULL)
4669 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4676 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4677 * @hw: pointer to the hw struct
4678 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4679 * @etag: value of the E-tag to remove
4680 * @tags_used: return value, number of tags in use by this port
4681 * @tags_free: return value, number of unallocated tags
4682 * @cmd_details: pointer to command details structure or NULL
4684 * This deletes an E-tag from the port virtualizer. It will return
4685 * the number of tags allocated by the port, and the number of unallocated
4688 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4689 u16 etag, u16 *tags_used, u16 *tags_free,
4690 struct i40e_asq_cmd_details *cmd_details)
4692 struct i40e_aq_desc desc;
4693 struct i40e_aqc_add_remove_mcast_etag *cmd =
4694 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4695 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4696 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4697 enum i40e_status_code status;
4701 return I40E_ERR_PARAM;
4703 i40e_fill_default_direct_cmd_desc(&desc,
4704 i40e_aqc_opc_remove_multicast_etag);
4706 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4707 cmd->etag = CPU_TO_LE16(etag);
4709 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4712 if (tags_used != NULL)
4713 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4714 if (tags_free != NULL)
4715 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4722 * i40e_aq_update_tag - Update an S/E-tag
4723 * @hw: pointer to the hw struct
4724 * @vsi_seid: VSI SEID using this S-tag
4725 * @old_tag: old tag value
4726 * @new_tag: new tag value
4727 * @tags_used: return value, number of tags in use by this PF
4728 * @tags_free: return value, number of unallocated tags
4729 * @cmd_details: pointer to command details structure or NULL
4731 * This updates the value of the tag currently attached to this VSI
4732 * in the switch complex. It will return the number of tags allocated
4733 * by the PF, and the number of unallocated tags available.
4735 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4736 u16 old_tag, u16 new_tag, u16 *tags_used,
4738 struct i40e_asq_cmd_details *cmd_details)
4740 struct i40e_aq_desc desc;
4741 struct i40e_aqc_update_tag *cmd =
4742 (struct i40e_aqc_update_tag *)&desc.params.raw;
4743 struct i40e_aqc_update_tag_completion *resp =
4744 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4745 enum i40e_status_code status;
4748 return I40E_ERR_PARAM;
4750 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4752 cmd->seid = CPU_TO_LE16(vsi_seid);
4753 cmd->old_tag = CPU_TO_LE16(old_tag);
4754 cmd->new_tag = CPU_TO_LE16(new_tag);
4756 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4759 if (tags_used != NULL)
4760 *tags_used = LE16_TO_CPU(resp->tags_used);
4761 if (tags_free != NULL)
4762 *tags_free = LE16_TO_CPU(resp->tags_free);
4769 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4770 * @hw: pointer to the hw struct
4771 * @tcmap: TC map for request/release any ignore PFC condition
4772 * @request: request or release ignore PFC condition
4773 * @tcmap_ret: return TCs for which PFC is currently ignored
4774 * @cmd_details: pointer to command details structure or NULL
4776 * This sends out request/release to ignore PFC condition for a TC.
4777 * It will return the TCs for which PFC is currently ignored.
4779 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4780 bool request, u8 *tcmap_ret,
4781 struct i40e_asq_cmd_details *cmd_details)
4783 struct i40e_aq_desc desc;
4784 struct i40e_aqc_pfc_ignore *cmd_resp =
4785 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4786 enum i40e_status_code status;
4788 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4791 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4793 cmd_resp->tc_bitmap = tcmap;
4795 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4798 if (tcmap_ret != NULL)
4799 *tcmap_ret = cmd_resp->tc_bitmap;
4806 * i40e_aq_dcb_updated - DCB Updated Command
4807 * @hw: pointer to the hw struct
4808 * @cmd_details: pointer to command details structure or NULL
4810 * When LLDP is handled in PF this command is used by the PF
4811 * to notify EMP that a DCB setting is modified.
4812 * When LLDP is handled in EMP this command is used by the PF
4813 * to notify EMP whenever one of the following parameters get
4815 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4816 * - PCIRTT in PRTDCB_GENC.PCIRTT
4817 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4818 * EMP will return when the shared RPB settings have been
4819 * recomputed and modified. The retval field in the descriptor
4820 * will be set to 0 when RPB is modified.
4822 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4823 struct i40e_asq_cmd_details *cmd_details)
4825 struct i40e_aq_desc desc;
4826 enum i40e_status_code status;
4828 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4830 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4836 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4837 * @hw: pointer to the hw struct
4838 * @seid: defines the SEID of the switch for which the stats are requested
4839 * @vlan_id: the VLAN ID for which the statistics are requested
4840 * @stat_index: index of the statistics counters block assigned to this VLAN
4841 * @cmd_details: pointer to command details structure or NULL
4843 * XL710 supports 128 smonVlanStats counters.This command is used to
4844 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4847 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4848 u16 vlan_id, u16 *stat_index,
4849 struct i40e_asq_cmd_details *cmd_details)
4851 struct i40e_aq_desc desc;
4852 struct i40e_aqc_add_remove_statistics *cmd_resp =
4853 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4854 enum i40e_status_code status;
4856 if ((seid == 0) || (stat_index == NULL))
4857 return I40E_ERR_PARAM;
4859 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4861 cmd_resp->seid = CPU_TO_LE16(seid);
4862 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4864 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4866 if (!status && stat_index)
4867 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4873 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4874 * @hw: pointer to the hw struct
4875 * @seid: defines the SEID of the switch for which the stats are requested
4876 * @vlan_id: the VLAN ID for which the statistics are requested
4877 * @stat_index: index of the statistics counters block assigned to this VLAN
4878 * @cmd_details: pointer to command details structure or NULL
4880 * XL710 supports 128 smonVlanStats counters.This command is used to
4881 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4884 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4885 u16 vlan_id, u16 stat_index,
4886 struct i40e_asq_cmd_details *cmd_details)
4888 struct i40e_aq_desc desc;
4889 struct i40e_aqc_add_remove_statistics *cmd =
4890 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4891 enum i40e_status_code status;
4894 return I40E_ERR_PARAM;
4896 i40e_fill_default_direct_cmd_desc(&desc,
4897 i40e_aqc_opc_remove_statistics);
4899 cmd->seid = CPU_TO_LE16(seid);
4900 cmd->vlan = CPU_TO_LE16(vlan_id);
4901 cmd->stat_index = CPU_TO_LE16(stat_index);
4903 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4909 * i40e_aq_set_port_parameters - set physical port parameters.
4910 * @hw: pointer to the hw struct
4911 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4912 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4913 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4914 * @double_vlan: if set double VLAN is enabled
4915 * @cmd_details: pointer to command details structure or NULL
4917 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4918 u16 bad_frame_vsi, bool save_bad_pac,
4919 bool pad_short_pac, bool double_vlan,
4920 struct i40e_asq_cmd_details *cmd_details)
4922 struct i40e_aqc_set_port_parameters *cmd;
4923 enum i40e_status_code status;
4924 struct i40e_aq_desc desc;
4925 u16 command_flags = 0;
4927 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4929 i40e_fill_default_direct_cmd_desc(&desc,
4930 i40e_aqc_opc_set_port_parameters);
4932 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4934 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4936 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4938 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4939 cmd->command_flags = CPU_TO_LE16(command_flags);
4941 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4947 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
4948 * @hw: pointer to the hw struct
4949 * @seid: seid for the physical port/switching component/vsi
4950 * @buff: Indirect buffer to hold data parameters and response
4951 * @buff_size: Indirect buffer size
4952 * @opcode: Tx scheduler AQ command opcode
4953 * @cmd_details: pointer to command details structure or NULL
4955 * Generic command handler for Tx scheduler AQ commands
4957 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
4958 void *buff, u16 buff_size,
4959 enum i40e_admin_queue_opc opcode,
4960 struct i40e_asq_cmd_details *cmd_details)
4962 struct i40e_aq_desc desc;
4963 struct i40e_aqc_tx_sched_ind *cmd =
4964 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4965 enum i40e_status_code status;
4966 bool cmd_param_flag = false;
4969 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
4970 case i40e_aqc_opc_configure_vsi_tc_bw:
4971 case i40e_aqc_opc_enable_switching_comp_ets:
4972 case i40e_aqc_opc_modify_switching_comp_ets:
4973 case i40e_aqc_opc_disable_switching_comp_ets:
4974 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
4975 case i40e_aqc_opc_configure_switching_comp_bw_config:
4976 cmd_param_flag = true;
4978 case i40e_aqc_opc_query_vsi_bw_config:
4979 case i40e_aqc_opc_query_vsi_ets_sla_config:
4980 case i40e_aqc_opc_query_switching_comp_ets_config:
4981 case i40e_aqc_opc_query_port_ets_config:
4982 case i40e_aqc_opc_query_switching_comp_bw_config:
4983 cmd_param_flag = false;
4986 return I40E_ERR_PARAM;
4989 i40e_fill_default_direct_cmd_desc(&desc, opcode);
4991 /* Indirect command */
4992 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4994 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4995 if (buff_size > I40E_AQ_LARGE_BUF)
4996 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4998 desc.datalen = CPU_TO_LE16(buff_size);
5000 cmd->vsi_seid = CPU_TO_LE16(seid);
5002 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5008 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5009 * @hw: pointer to the hw struct
5011 * @credit: BW limit credits (0 = disabled)
5012 * @max_credit: Max BW limit credits
5013 * @cmd_details: pointer to command details structure or NULL
5015 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5016 u16 seid, u16 credit, u8 max_credit,
5017 struct i40e_asq_cmd_details *cmd_details)
5019 struct i40e_aq_desc desc;
5020 struct i40e_aqc_configure_vsi_bw_limit *cmd =
5021 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5022 enum i40e_status_code status;
5024 i40e_fill_default_direct_cmd_desc(&desc,
5025 i40e_aqc_opc_configure_vsi_bw_limit);
5027 cmd->vsi_seid = CPU_TO_LE16(seid);
5028 cmd->credit = CPU_TO_LE16(credit);
5029 cmd->max_credit = max_credit;
5031 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5037 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5038 * @hw: pointer to the hw struct
5039 * @seid: switching component seid
5040 * @credit: BW limit credits (0 = disabled)
5041 * @max_bw: Max BW limit credits
5042 * @cmd_details: pointer to command details structure or NULL
5044 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5045 u16 seid, u16 credit, u8 max_bw,
5046 struct i40e_asq_cmd_details *cmd_details)
5048 struct i40e_aq_desc desc;
5049 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5050 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5051 enum i40e_status_code status;
5053 i40e_fill_default_direct_cmd_desc(&desc,
5054 i40e_aqc_opc_configure_switching_comp_bw_limit);
5056 cmd->seid = CPU_TO_LE16(seid);
5057 cmd->credit = CPU_TO_LE16(credit);
5058 cmd->max_bw = max_bw;
5060 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5066 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5067 * @hw: pointer to the hw struct
5069 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5070 * @cmd_details: pointer to command details structure or NULL
5072 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5074 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5075 struct i40e_asq_cmd_details *cmd_details)
5077 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5078 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5083 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5084 * @hw: pointer to the hw struct
5086 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5087 * @cmd_details: pointer to command details structure or NULL
5089 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5091 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5092 struct i40e_asq_cmd_details *cmd_details)
5094 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5095 i40e_aqc_opc_configure_vsi_tc_bw,
5100 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5101 * @hw: pointer to the hw struct
5102 * @seid: seid of the switching component connected to Physical Port
5103 * @ets_data: Buffer holding ETS parameters
5104 * @cmd_details: pointer to command details structure or NULL
5106 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5108 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5109 enum i40e_admin_queue_opc opcode,
5110 struct i40e_asq_cmd_details *cmd_details)
5112 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5113 sizeof(*ets_data), opcode, cmd_details);
5117 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5118 * @hw: pointer to the hw struct
5119 * @seid: seid of the switching component
5120 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5121 * @cmd_details: pointer to command details structure or NULL
5123 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5125 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5126 struct i40e_asq_cmd_details *cmd_details)
5128 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5129 i40e_aqc_opc_configure_switching_comp_bw_config,
5134 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5135 * @hw: pointer to the hw struct
5136 * @seid: seid of the switching component
5137 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5138 * @cmd_details: pointer to command details structure or NULL
5140 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5141 struct i40e_hw *hw, u16 seid,
5142 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5143 struct i40e_asq_cmd_details *cmd_details)
5145 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5146 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5151 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5152 * @hw: pointer to the hw struct
5153 * @seid: seid of the VSI
5154 * @bw_data: Buffer to hold VSI BW configuration
5155 * @cmd_details: pointer to command details structure or NULL
5157 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5159 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5160 struct i40e_asq_cmd_details *cmd_details)
5162 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5163 i40e_aqc_opc_query_vsi_bw_config,
5168 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5169 * @hw: pointer to the hw struct
5170 * @seid: seid of the VSI
5171 * @bw_data: Buffer to hold VSI BW configuration per TC
5172 * @cmd_details: pointer to command details structure or NULL
5174 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5176 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5177 struct i40e_asq_cmd_details *cmd_details)
5179 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5180 i40e_aqc_opc_query_vsi_ets_sla_config,
5185 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5186 * @hw: pointer to the hw struct
5187 * @seid: seid of the switching component
5188 * @bw_data: Buffer to hold switching component's per TC BW config
5189 * @cmd_details: pointer to command details structure or NULL
5191 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5193 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5194 struct i40e_asq_cmd_details *cmd_details)
5196 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5197 i40e_aqc_opc_query_switching_comp_ets_config,
5202 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5203 * @hw: pointer to the hw struct
5204 * @seid: seid of the VSI or switching component connected to Physical Port
5205 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5206 * @cmd_details: pointer to command details structure or NULL
5208 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5210 struct i40e_aqc_query_port_ets_config_resp *bw_data,
5211 struct i40e_asq_cmd_details *cmd_details)
5213 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5214 i40e_aqc_opc_query_port_ets_config,
5219 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5220 * @hw: pointer to the hw struct
5221 * @seid: seid of the switching component
5222 * @bw_data: Buffer to hold switching component's BW configuration
5223 * @cmd_details: pointer to command details structure or NULL
5225 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5227 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5228 struct i40e_asq_cmd_details *cmd_details)
5230 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5231 i40e_aqc_opc_query_switching_comp_bw_config,
5236 * i40e_validate_filter_settings
5237 * @hw: pointer to the hardware structure
5238 * @settings: Filter control settings
5240 * Check and validate the filter control settings passed.
5241 * The function checks for the valid filter/context sizes being
5242 * passed for FCoE and PE.
5244 * Returns I40E_SUCCESS if the values passed are valid and within
5245 * range else returns an error.
5247 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5248 struct i40e_filter_control_settings *settings)
5250 u32 fcoe_cntx_size, fcoe_filt_size;
5251 u32 pe_cntx_size, pe_filt_size;
5256 /* Validate FCoE settings passed */
5257 switch (settings->fcoe_filt_num) {
5258 case I40E_HASH_FILTER_SIZE_1K:
5259 case I40E_HASH_FILTER_SIZE_2K:
5260 case I40E_HASH_FILTER_SIZE_4K:
5261 case I40E_HASH_FILTER_SIZE_8K:
5262 case I40E_HASH_FILTER_SIZE_16K:
5263 case I40E_HASH_FILTER_SIZE_32K:
5264 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5265 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5268 return I40E_ERR_PARAM;
5271 switch (settings->fcoe_cntx_num) {
5272 case I40E_DMA_CNTX_SIZE_512:
5273 case I40E_DMA_CNTX_SIZE_1K:
5274 case I40E_DMA_CNTX_SIZE_2K:
5275 case I40E_DMA_CNTX_SIZE_4K:
5276 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5277 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5280 return I40E_ERR_PARAM;
5283 /* Validate PE settings passed */
5284 switch (settings->pe_filt_num) {
5285 case I40E_HASH_FILTER_SIZE_1K:
5286 case I40E_HASH_FILTER_SIZE_2K:
5287 case I40E_HASH_FILTER_SIZE_4K:
5288 case I40E_HASH_FILTER_SIZE_8K:
5289 case I40E_HASH_FILTER_SIZE_16K:
5290 case I40E_HASH_FILTER_SIZE_32K:
5291 case I40E_HASH_FILTER_SIZE_64K:
5292 case I40E_HASH_FILTER_SIZE_128K:
5293 case I40E_HASH_FILTER_SIZE_256K:
5294 case I40E_HASH_FILTER_SIZE_512K:
5295 case I40E_HASH_FILTER_SIZE_1M:
5296 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5297 pe_filt_size <<= (u32)settings->pe_filt_num;
5300 return I40E_ERR_PARAM;
5303 switch (settings->pe_cntx_num) {
5304 case I40E_DMA_CNTX_SIZE_512:
5305 case I40E_DMA_CNTX_SIZE_1K:
5306 case I40E_DMA_CNTX_SIZE_2K:
5307 case I40E_DMA_CNTX_SIZE_4K:
5308 case I40E_DMA_CNTX_SIZE_8K:
5309 case I40E_DMA_CNTX_SIZE_16K:
5310 case I40E_DMA_CNTX_SIZE_32K:
5311 case I40E_DMA_CNTX_SIZE_64K:
5312 case I40E_DMA_CNTX_SIZE_128K:
5313 case I40E_DMA_CNTX_SIZE_256K:
5314 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5315 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5318 return I40E_ERR_PARAM;
5321 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5322 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5323 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5324 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5325 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
5326 return I40E_ERR_INVALID_SIZE;
5328 return I40E_SUCCESS;
5332 * i40e_set_filter_control
5333 * @hw: pointer to the hardware structure
5334 * @settings: Filter control settings
5336 * Set the Queue Filters for PE/FCoE and enable filters required
5337 * for a single PF. It is expected that these settings are programmed
5338 * at the driver initialization time.
5340 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5341 struct i40e_filter_control_settings *settings)
5343 enum i40e_status_code ret = I40E_SUCCESS;
5344 u32 hash_lut_size = 0;
5348 return I40E_ERR_PARAM;
5350 /* Validate the input settings */
5351 ret = i40e_validate_filter_settings(hw, settings);
5355 /* Read the PF Queue Filter control register */
5356 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5358 /* Program required PE hash buckets for the PF */
5359 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5360 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5361 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5362 /* Program required PE contexts for the PF */
5363 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5364 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5365 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5367 /* Program required FCoE hash buckets for the PF */
5368 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5369 val |= ((u32)settings->fcoe_filt_num <<
5370 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5371 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5372 /* Program required FCoE DDP contexts for the PF */
5373 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5374 val |= ((u32)settings->fcoe_cntx_num <<
5375 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5376 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5378 /* Program Hash LUT size for the PF */
5379 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5380 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5382 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5383 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5385 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5386 if (settings->enable_fdir)
5387 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5388 if (settings->enable_ethtype)
5389 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5390 if (settings->enable_macvlan)
5391 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5393 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5395 return I40E_SUCCESS;
5399 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5400 * @hw: pointer to the hw struct
5401 * @mac_addr: MAC address to use in the filter
5402 * @ethtype: Ethertype to use in the filter
5403 * @flags: Flags that needs to be applied to the filter
5404 * @vsi_seid: seid of the control VSI
5405 * @queue: VSI queue number to send the packet to
5406 * @is_add: Add control packet filter if True else remove
5407 * @stats: Structure to hold information on control filter counts
5408 * @cmd_details: pointer to command details structure or NULL
5410 * This command will Add or Remove control packet filter for a control VSI.
5411 * In return it will update the total number of perfect filter count in
5414 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5415 u8 *mac_addr, u16 ethtype, u16 flags,
5416 u16 vsi_seid, u16 queue, bool is_add,
5417 struct i40e_control_filter_stats *stats,
5418 struct i40e_asq_cmd_details *cmd_details)
5420 struct i40e_aq_desc desc;
5421 struct i40e_aqc_add_remove_control_packet_filter *cmd =
5422 (struct i40e_aqc_add_remove_control_packet_filter *)
5424 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5425 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5427 enum i40e_status_code status;
5430 return I40E_ERR_PARAM;
5433 i40e_fill_default_direct_cmd_desc(&desc,
5434 i40e_aqc_opc_add_control_packet_filter);
5435 cmd->queue = CPU_TO_LE16(queue);
5437 i40e_fill_default_direct_cmd_desc(&desc,
5438 i40e_aqc_opc_remove_control_packet_filter);
5442 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
5443 I40E_NONDMA_TO_NONDMA);
5445 cmd->etype = CPU_TO_LE16(ethtype);
5446 cmd->flags = CPU_TO_LE16(flags);
5447 cmd->seid = CPU_TO_LE16(vsi_seid);
5449 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5451 if (!status && stats) {
5452 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5453 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5454 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5455 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5462 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5463 * @hw: pointer to the hw struct
5464 * @seid: VSI seid to add ethertype filter from
5466 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5467 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5470 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5471 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5472 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5473 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5474 enum i40e_status_code status;
5476 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5477 seid, 0, true, NULL,
5480 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5484 * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5485 * @filters: list of cloud filters
5486 * @filter_count: length of list
5488 * There's an issue in the device where the Geneve VNI layout needs
5489 * to be shifted 1 byte over from the VxLAN VNI
5491 STATIC void i40e_fix_up_geneve_vni(
5492 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5495 struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters;
5498 for (i = 0; i < filter_count; i++) {
5502 tnl_type = (LE16_TO_CPU(f[i].flags) &
5503 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5504 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5505 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5506 ti = LE32_TO_CPU(f[i].tenant_id);
5507 f[i].tenant_id = CPU_TO_LE32(ti << 8);
5513 * i40e_aq_add_cloud_filters
5514 * @hw: pointer to the hardware structure
5515 * @seid: VSI seid to add cloud filters from
5516 * @filters: Buffer which contains the filters to be added
5517 * @filter_count: number of filters contained in the buffer
5519 * Set the cloud filters for a given VSI. The contents of the
5520 * i40e_aqc_add_remove_cloud_filters_element_data are filled
5521 * in by the caller of the function.
5524 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5526 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5529 struct i40e_aq_desc desc;
5530 struct i40e_aqc_add_remove_cloud_filters *cmd =
5531 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5532 enum i40e_status_code status;
5535 i40e_fill_default_direct_cmd_desc(&desc,
5536 i40e_aqc_opc_add_cloud_filters);
5538 buff_len = filter_count * sizeof(*filters);
5539 desc.datalen = CPU_TO_LE16(buff_len);
5540 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5541 cmd->num_filters = filter_count;
5542 cmd->seid = CPU_TO_LE16(seid);
5544 i40e_fix_up_geneve_vni(filters, filter_count);
5546 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5552 * i40e_aq_remove_cloud_filters
5553 * @hw: pointer to the hardware structure
5554 * @seid: VSI seid to remove cloud filters from
5555 * @filters: Buffer which contains the filters to be removed
5556 * @filter_count: number of filters contained in the buffer
5558 * Remove the cloud filters for a given VSI. The contents of the
5559 * i40e_aqc_add_remove_cloud_filters_element_data are filled
5560 * in by the caller of the function.
5563 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5565 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5568 struct i40e_aq_desc desc;
5569 struct i40e_aqc_add_remove_cloud_filters *cmd =
5570 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5571 enum i40e_status_code status;
5574 i40e_fill_default_direct_cmd_desc(&desc,
5575 i40e_aqc_opc_remove_cloud_filters);
5577 buff_len = filter_count * sizeof(*filters);
5578 desc.datalen = CPU_TO_LE16(buff_len);
5579 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5580 cmd->num_filters = filter_count;
5581 cmd->seid = CPU_TO_LE16(seid);
5583 i40e_fix_up_geneve_vni(filters, filter_count);
5585 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5591 * i40e_aq_alternate_write
5592 * @hw: pointer to the hardware structure
5593 * @reg_addr0: address of first dword to be read
5594 * @reg_val0: value to be written under 'reg_addr0'
5595 * @reg_addr1: address of second dword to be read
5596 * @reg_val1: value to be written under 'reg_addr1'
5598 * Write one or two dwords to alternate structure. Fields are indicated
5599 * by 'reg_addr0' and 'reg_addr1' register numbers.
5602 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5603 u32 reg_addr0, u32 reg_val0,
5604 u32 reg_addr1, u32 reg_val1)
5606 struct i40e_aq_desc desc;
5607 struct i40e_aqc_alternate_write *cmd_resp =
5608 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5609 enum i40e_status_code status;
5611 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5612 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5613 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5614 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5615 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5617 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5623 * i40e_aq_alternate_write_indirect
5624 * @hw: pointer to the hardware structure
5625 * @addr: address of a first register to be modified
5626 * @dw_count: number of alternate structure fields to write
5627 * @buffer: pointer to the command buffer
5629 * Write 'dw_count' dwords from 'buffer' to alternate structure
5630 * starting at 'addr'.
5633 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5634 u32 addr, u32 dw_count, void *buffer)
5636 struct i40e_aq_desc desc;
5637 struct i40e_aqc_alternate_ind_write *cmd_resp =
5638 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5639 enum i40e_status_code status;
5642 return I40E_ERR_PARAM;
5644 /* Indirect command */
5645 i40e_fill_default_direct_cmd_desc(&desc,
5646 i40e_aqc_opc_alternate_write_indirect);
5648 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5649 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5650 if (dw_count > (I40E_AQ_LARGE_BUF/4))
5651 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5653 cmd_resp->address = CPU_TO_LE32(addr);
5654 cmd_resp->length = CPU_TO_LE32(dw_count);
5656 status = i40e_asq_send_command(hw, &desc, buffer,
5657 I40E_LO_DWORD(4*dw_count), NULL);
5663 * i40e_aq_alternate_read
5664 * @hw: pointer to the hardware structure
5665 * @reg_addr0: address of first dword to be read
5666 * @reg_val0: pointer for data read from 'reg_addr0'
5667 * @reg_addr1: address of second dword to be read
5668 * @reg_val1: pointer for data read from 'reg_addr1'
5670 * Read one or two dwords from alternate structure. Fields are indicated
5671 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5672 * is not passed then only register at 'reg_addr0' is read.
5675 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5676 u32 reg_addr0, u32 *reg_val0,
5677 u32 reg_addr1, u32 *reg_val1)
5679 struct i40e_aq_desc desc;
5680 struct i40e_aqc_alternate_write *cmd_resp =
5681 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5682 enum i40e_status_code status;
5684 if (reg_val0 == NULL)
5685 return I40E_ERR_PARAM;
5687 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5688 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5689 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5691 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5693 if (status == I40E_SUCCESS) {
5694 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5696 if (reg_val1 != NULL)
5697 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5704 * i40e_aq_alternate_read_indirect
5705 * @hw: pointer to the hardware structure
5706 * @addr: address of the alternate structure field
5707 * @dw_count: number of alternate structure fields to read
5708 * @buffer: pointer to the command buffer
5710 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5711 * place them in 'buffer'. The buffer should be allocated by caller.
5714 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5715 u32 addr, u32 dw_count, void *buffer)
5717 struct i40e_aq_desc desc;
5718 struct i40e_aqc_alternate_ind_write *cmd_resp =
5719 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5720 enum i40e_status_code status;
5723 return I40E_ERR_PARAM;
5725 /* Indirect command */
5726 i40e_fill_default_direct_cmd_desc(&desc,
5727 i40e_aqc_opc_alternate_read_indirect);
5729 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5730 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5731 if (dw_count > (I40E_AQ_LARGE_BUF/4))
5732 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5734 cmd_resp->address = CPU_TO_LE32(addr);
5735 cmd_resp->length = CPU_TO_LE32(dw_count);
5737 status = i40e_asq_send_command(hw, &desc, buffer,
5738 I40E_LO_DWORD(4*dw_count), NULL);
5744 * i40e_aq_alternate_clear
5745 * @hw: pointer to the HW structure.
5747 * Clear the alternate structures of the port from which the function
5751 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5753 struct i40e_aq_desc desc;
5754 enum i40e_status_code status;
5756 i40e_fill_default_direct_cmd_desc(&desc,
5757 i40e_aqc_opc_alternate_clear_port);
5759 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5765 * i40e_aq_alternate_write_done
5766 * @hw: pointer to the HW structure.
5767 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
5768 * @reset_needed: indicates the SW should trigger GLOBAL reset
5770 * Indicates to the FW that alternate structures have been changed.
5773 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
5774 u8 bios_mode, bool *reset_needed)
5776 struct i40e_aq_desc desc;
5777 struct i40e_aqc_alternate_write_done *cmd =
5778 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5779 enum i40e_status_code status;
5781 if (reset_needed == NULL)
5782 return I40E_ERR_PARAM;
5784 i40e_fill_default_direct_cmd_desc(&desc,
5785 i40e_aqc_opc_alternate_write_done);
5787 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
5789 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5790 if (!status && reset_needed)
5791 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
5792 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
5798 * i40e_aq_set_oem_mode
5799 * @hw: pointer to the HW structure.
5800 * @oem_mode: the OEM mode to be used
5802 * Sets the device to a specific operating mode. Currently the only supported
5803 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
5806 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
5809 struct i40e_aq_desc desc;
5810 struct i40e_aqc_alternate_write_done *cmd =
5811 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5812 enum i40e_status_code status;
5814 i40e_fill_default_direct_cmd_desc(&desc,
5815 i40e_aqc_opc_alternate_set_mode);
5817 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
5819 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5825 * i40e_aq_resume_port_tx
5826 * @hw: pointer to the hardware structure
5827 * @cmd_details: pointer to command details structure or NULL
5829 * Resume port's Tx traffic
5831 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
5832 struct i40e_asq_cmd_details *cmd_details)
5834 struct i40e_aq_desc desc;
5835 enum i40e_status_code status;
5837 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
5839 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5845 * i40e_set_pci_config_data - store PCI bus info
5846 * @hw: pointer to hardware structure
5847 * @link_status: the link status word from PCI config space
5849 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
5851 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
5853 hw->bus.type = i40e_bus_type_pci_express;
5855 switch (link_status & I40E_PCI_LINK_WIDTH) {
5856 case I40E_PCI_LINK_WIDTH_1:
5857 hw->bus.width = i40e_bus_width_pcie_x1;
5859 case I40E_PCI_LINK_WIDTH_2:
5860 hw->bus.width = i40e_bus_width_pcie_x2;
5862 case I40E_PCI_LINK_WIDTH_4:
5863 hw->bus.width = i40e_bus_width_pcie_x4;
5865 case I40E_PCI_LINK_WIDTH_8:
5866 hw->bus.width = i40e_bus_width_pcie_x8;
5869 hw->bus.width = i40e_bus_width_unknown;
5873 switch (link_status & I40E_PCI_LINK_SPEED) {
5874 case I40E_PCI_LINK_SPEED_2500:
5875 hw->bus.speed = i40e_bus_speed_2500;
5877 case I40E_PCI_LINK_SPEED_5000:
5878 hw->bus.speed = i40e_bus_speed_5000;
5880 case I40E_PCI_LINK_SPEED_8000:
5881 hw->bus.speed = i40e_bus_speed_8000;
5884 hw->bus.speed = i40e_bus_speed_unknown;
5890 * i40e_aq_debug_dump
5891 * @hw: pointer to the hardware structure
5892 * @cluster_id: specific cluster to dump
5893 * @table_id: table id within cluster
5894 * @start_index: index of line in the block to read
5895 * @buff_size: dump buffer size
5896 * @buff: dump buffer
5897 * @ret_buff_size: actual buffer size returned
5898 * @ret_next_table: next block to read
5899 * @ret_next_index: next index to read
5901 * Dump internal FW/HW data for debug purposes.
5904 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
5905 u8 table_id, u32 start_index, u16 buff_size,
5906 void *buff, u16 *ret_buff_size,
5907 u8 *ret_next_table, u32 *ret_next_index,
5908 struct i40e_asq_cmd_details *cmd_details)
5910 struct i40e_aq_desc desc;
5911 struct i40e_aqc_debug_dump_internals *cmd =
5912 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5913 struct i40e_aqc_debug_dump_internals *resp =
5914 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5915 enum i40e_status_code status;
5917 if (buff_size == 0 || !buff)
5918 return I40E_ERR_PARAM;
5920 i40e_fill_default_direct_cmd_desc(&desc,
5921 i40e_aqc_opc_debug_dump_internals);
5922 /* Indirect Command */
5923 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5924 if (buff_size > I40E_AQ_LARGE_BUF)
5925 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5927 cmd->cluster_id = cluster_id;
5928 cmd->table_id = table_id;
5929 cmd->idx = CPU_TO_LE32(start_index);
5931 desc.datalen = CPU_TO_LE16(buff_size);
5933 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5935 if (ret_buff_size != NULL)
5936 *ret_buff_size = LE16_TO_CPU(desc.datalen);
5937 if (ret_next_table != NULL)
5938 *ret_next_table = resp->table_id;
5939 if (ret_next_index != NULL)
5940 *ret_next_index = LE32_TO_CPU(resp->idx);
5947 * i40e_read_bw_from_alt_ram
5948 * @hw: pointer to the hardware structure
5949 * @max_bw: pointer for max_bw read
5950 * @min_bw: pointer for min_bw read
5951 * @min_valid: pointer for bool that is true if min_bw is a valid value
5952 * @max_valid: pointer for bool that is true if max_bw is a valid value
5954 * Read bw from the alternate ram for the given pf
5956 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
5957 u32 *max_bw, u32 *min_bw,
5958 bool *min_valid, bool *max_valid)
5960 enum i40e_status_code status;
5961 u32 max_bw_addr, min_bw_addr;
5963 /* Calculate the address of the min/max bw registers */
5964 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5965 I40E_ALT_STRUCT_MAX_BW_OFFSET +
5966 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5967 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5968 I40E_ALT_STRUCT_MIN_BW_OFFSET +
5969 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5971 /* Read the bandwidths from alt ram */
5972 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
5973 min_bw_addr, min_bw);
5975 if (*min_bw & I40E_ALT_BW_VALID_MASK)
5980 if (*max_bw & I40E_ALT_BW_VALID_MASK)
5989 * i40e_aq_configure_partition_bw
5990 * @hw: pointer to the hardware structure
5991 * @bw_data: Buffer holding valid pfs and bw limits
5992 * @cmd_details: pointer to command details
5994 * Configure partitions guaranteed/max bw
5996 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
5997 struct i40e_aqc_configure_partition_bw_data *bw_data,
5998 struct i40e_asq_cmd_details *cmd_details)
6000 enum i40e_status_code status;
6001 struct i40e_aq_desc desc;
6002 u16 bwd_size = sizeof(*bw_data);
6004 i40e_fill_default_direct_cmd_desc(&desc,
6005 i40e_aqc_opc_configure_partition_bw);
6007 /* Indirect command */
6008 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6009 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6011 if (bwd_size > I40E_AQ_LARGE_BUF)
6012 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6014 desc.datalen = CPU_TO_LE16(bwd_size);
6016 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6022 * i40e_read_phy_register
6023 * @hw: pointer to the HW structure
6024 * @page: registers page number
6025 * @reg: register address in the page
6026 * @phy_adr: PHY address on MDIO interface
6027 * @value: PHY register value
6029 * Reads specified PHY register value
6031 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6032 u8 page, u16 reg, u8 phy_addr,
6035 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6038 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6040 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6041 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6042 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6043 (I40E_MDIO_OPCODE_ADDRESS) |
6044 (I40E_MDIO_STCODE) |
6045 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6046 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6047 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6049 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6050 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6051 status = I40E_SUCCESS;
6054 i40e_usec_delay(10);
6059 i40e_debug(hw, I40E_DEBUG_PHY,
6060 "PHY: Can't write command to external PHY.\n");
6064 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6065 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6066 (I40E_MDIO_OPCODE_READ) |
6067 (I40E_MDIO_STCODE) |
6068 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6069 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6070 status = I40E_ERR_TIMEOUT;
6072 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6074 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6075 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6076 status = I40E_SUCCESS;
6079 i40e_usec_delay(10);
6084 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6085 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6086 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6088 i40e_debug(hw, I40E_DEBUG_PHY,
6089 "PHY: Can't read register value from external PHY.\n");
6097 * i40e_write_phy_register
6098 * @hw: pointer to the HW structure
6099 * @page: registers page number
6100 * @reg: register address in the page
6101 * @phy_adr: PHY address on MDIO interface
6102 * @value: PHY register value
6104 * Writes value to specified PHY register
6106 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6107 u8 page, u16 reg, u8 phy_addr,
6110 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6113 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6115 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6116 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6117 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6118 (I40E_MDIO_OPCODE_ADDRESS) |
6119 (I40E_MDIO_STCODE) |
6120 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6121 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6122 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6124 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6125 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6126 status = I40E_SUCCESS;
6129 i40e_usec_delay(10);
6133 i40e_debug(hw, I40E_DEBUG_PHY,
6134 "PHY: Can't write command to external PHY.\n");
6138 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6139 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6141 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6142 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6143 (I40E_MDIO_OPCODE_WRITE) |
6144 (I40E_MDIO_STCODE) |
6145 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6146 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6147 status = I40E_ERR_TIMEOUT;
6149 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6151 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6152 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6153 status = I40E_SUCCESS;
6156 i40e_usec_delay(10);
6165 * i40e_get_phy_address
6166 * @hw: pointer to the HW structure
6167 * @dev_num: PHY port num that address we want
6168 * @phy_addr: Returned PHY address
6170 * Gets PHY address for current port
6172 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6174 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6175 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6177 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6181 * i40e_blink_phy_led
6182 * @hw: pointer to the HW structure
6183 * @time: time how long led will blinks in secs
6184 * @interval: gap between LED on and off in msecs
6186 * Blinks PHY link LED
6188 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6189 u32 time, u32 interval)
6191 enum i40e_status_code status = I40E_SUCCESS;
6196 u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6200 i = rd32(hw, I40E_PFGEN_PORTNUM);
6201 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6202 phy_addr = i40e_get_phy_address(hw, port_num);
6204 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6206 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6207 led_addr, phy_addr, &led_reg);
6209 goto phy_blinking_end;
6211 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6213 status = i40e_write_phy_register(hw,
6214 I40E_PHY_COM_REG_PAGE,
6218 goto phy_blinking_end;
6223 if (time > 0 && interval > 0) {
6224 for (i = 0; i < time * 1000; i += interval) {
6225 status = i40e_read_phy_register(hw,
6226 I40E_PHY_COM_REG_PAGE,
6230 goto restore_config;
6231 if (led_reg & I40E_PHY_LED_MANUAL_ON)
6234 led_reg = I40E_PHY_LED_MANUAL_ON;
6235 status = i40e_write_phy_register(hw,
6236 I40E_PHY_COM_REG_PAGE,
6240 goto restore_config;
6241 i40e_msec_delay(interval);
6246 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6254 * i40e_led_get_phy - return current on/off mode
6255 * @hw: pointer to the hw struct
6256 * @led_addr: address of led register to use
6257 * @val: original value of register to use
6260 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6263 enum i40e_status_code status = I40E_SUCCESS;
6271 temp_addr = I40E_PHY_LED_PROV_REG_1;
6272 i = rd32(hw, I40E_PFGEN_PORTNUM);
6273 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6274 phy_addr = i40e_get_phy_address(hw, port_num);
6276 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6278 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6279 temp_addr, phy_addr, ®_val);
6283 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6284 *led_addr = temp_addr;
6293 * @hw: pointer to the HW structure
6294 * @on: true or false
6295 * @mode: original val plus bit for set or ignore
6296 * Set led's on or off when controlled by the PHY
6299 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6300 u16 led_addr, u32 mode)
6302 enum i40e_status_code status = I40E_SUCCESS;
6309 i = rd32(hw, I40E_PFGEN_PORTNUM);
6310 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6311 phy_addr = i40e_get_phy_address(hw, port_num);
6313 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6314 phy_addr, &led_reg);
6318 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6320 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6321 led_addr, phy_addr, led_reg);
6325 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6326 led_addr, phy_addr, &led_reg);
6328 goto restore_config;
6330 led_reg = I40E_PHY_LED_MANUAL_ON;
6333 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6334 led_addr, phy_addr, led_reg);
6336 goto restore_config;
6337 if (mode & I40E_PHY_LED_MODE_ORIG) {
6338 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6339 status = i40e_write_phy_register(hw,
6340 I40E_PHY_COM_REG_PAGE,
6341 led_addr, phy_addr, led_ctl);
6345 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6349 #endif /* PF_DRIVER */
6352 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6353 * @hw: pointer to the hw struct
6354 * @reg_addr: register address
6355 * @reg_val: ptr to register value
6356 * @cmd_details: pointer to command details structure or NULL
6358 * Use the firmware to read the Rx control register,
6359 * especially useful if the Rx unit is under heavy pressure
6361 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6362 u32 reg_addr, u32 *reg_val,
6363 struct i40e_asq_cmd_details *cmd_details)
6365 struct i40e_aq_desc desc;
6366 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
6367 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6368 enum i40e_status_code status;
6370 if (reg_val == NULL)
6371 return I40E_ERR_PARAM;
6373 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
6375 cmd_resp->address = CPU_TO_LE32(reg_addr);
6377 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6379 if (status == I40E_SUCCESS)
6380 *reg_val = LE32_TO_CPU(cmd_resp->value);
6386 * i40e_read_rx_ctl - read from an Rx control register
6387 * @hw: pointer to the hw struct
6388 * @reg_addr: register address
6390 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
6392 enum i40e_status_code status = I40E_SUCCESS;
6397 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6398 if (!use_register) {
6400 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
6401 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6408 /* if the AQ access failed, try the old-fashioned way */
6409 if (status || use_register)
6410 val = rd32(hw, reg_addr);
6416 * i40e_aq_rx_ctl_write_register
6417 * @hw: pointer to the hw struct
6418 * @reg_addr: register address
6419 * @reg_val: register value
6420 * @cmd_details: pointer to command details structure or NULL
6422 * Use the firmware to write to an Rx control register,
6423 * especially useful if the Rx unit is under heavy pressure
6425 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
6426 u32 reg_addr, u32 reg_val,
6427 struct i40e_asq_cmd_details *cmd_details)
6429 struct i40e_aq_desc desc;
6430 struct i40e_aqc_rx_ctl_reg_read_write *cmd =
6431 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6432 enum i40e_status_code status;
6434 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
6436 cmd->address = CPU_TO_LE32(reg_addr);
6437 cmd->value = CPU_TO_LE32(reg_val);
6439 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6445 * i40e_write_rx_ctl - write to an Rx control register
6446 * @hw: pointer to the hw struct
6447 * @reg_addr: register address
6448 * @reg_val: register value
6450 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
6452 enum i40e_status_code status = I40E_SUCCESS;
6456 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6457 if (!use_register) {
6459 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
6461 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6468 /* if the AQ access failed, try the old-fashioned way */
6469 if (status || use_register)
6470 wr32(hw, reg_addr, reg_val);
6475 * i40e_aq_send_msg_to_pf
6476 * @hw: pointer to the hardware structure
6477 * @v_opcode: opcodes for VF-PF communication
6478 * @v_retval: return error code
6479 * @msg: pointer to the msg buffer
6480 * @msglen: msg length
6481 * @cmd_details: pointer to command details
6483 * Send message to PF driver using admin queue. By default, this message
6484 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
6485 * completion before returning.
6487 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
6488 enum i40e_virtchnl_ops v_opcode,
6489 enum i40e_status_code v_retval,
6490 u8 *msg, u16 msglen,
6491 struct i40e_asq_cmd_details *cmd_details)
6493 struct i40e_aq_desc desc;
6494 struct i40e_asq_cmd_details details;
6495 enum i40e_status_code status;
6497 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
6498 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
6499 desc.cookie_high = CPU_TO_LE32(v_opcode);
6500 desc.cookie_low = CPU_TO_LE32(v_retval);
6502 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
6503 | I40E_AQ_FLAG_RD));
6504 if (msglen > I40E_AQ_LARGE_BUF)
6505 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6506 desc.datalen = CPU_TO_LE16(msglen);
6509 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
6510 details.async = true;
6511 cmd_details = &details;
6513 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
6514 msglen, cmd_details);
6519 * i40e_vf_parse_hw_config
6520 * @hw: pointer to the hardware structure
6521 * @msg: pointer to the virtual channel VF resource structure
6523 * Given a VF resource message from the PF, populate the hw struct
6524 * with appropriate information.
6526 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
6527 struct i40e_virtchnl_vf_resource *msg)
6529 struct i40e_virtchnl_vsi_resource *vsi_res;
6532 vsi_res = &msg->vsi_res[0];
6534 hw->dev_caps.num_vsis = msg->num_vsis;
6535 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
6536 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
6537 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
6538 hw->dev_caps.dcb = msg->vf_offload_flags &
6539 I40E_VIRTCHNL_VF_OFFLOAD_L2;
6540 hw->dev_caps.fcoe = (msg->vf_offload_flags &
6541 I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
6542 hw->dev_caps.iwarp = (msg->vf_offload_flags &
6543 I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
6544 for (i = 0; i < msg->num_vsis; i++) {
6545 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
6546 i40e_memcpy(hw->mac.perm_addr,
6547 vsi_res->default_mac_addr,
6548 I40E_ETH_LENGTH_OF_ADDRESS,
6549 I40E_NONDMA_TO_NONDMA);
6550 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
6551 I40E_ETH_LENGTH_OF_ADDRESS,
6552 I40E_NONDMA_TO_NONDMA);
6560 * @hw: pointer to the hardware structure
6562 * Send a VF_RESET message to the PF. Does not wait for response from PF
6563 * as none will be forthcoming. Immediately after calling this function,
6564 * the admin queue should be shut down and (optionally) reinitialized.
6566 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
6568 return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
6569 I40E_SUCCESS, NULL, 0, NULL);
6571 #endif /* VF_DRIVER */
6575 * i40e_aq_set_arp_proxy_config
6576 * @hw: pointer to the HW structure
6577 * @proxy_config - pointer to proxy config command table struct
6578 * @cmd_details: pointer to command details
6580 * Set ARP offload parameters from pre-populated
6581 * i40e_aqc_arp_proxy_data struct
6583 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
6584 struct i40e_aqc_arp_proxy_data *proxy_config,
6585 struct i40e_asq_cmd_details *cmd_details)
6587 struct i40e_aq_desc desc;
6588 enum i40e_status_code status;
6591 return I40E_ERR_PARAM;
6593 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
6595 desc.params.external.addr_high =
6596 CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
6597 desc.params.external.addr_low =
6598 CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
6600 status = i40e_asq_send_command(hw, &desc, proxy_config,
6601 sizeof(struct i40e_aqc_arp_proxy_data),
6608 * i40e_aq_opc_set_ns_proxy_table_entry
6609 * @hw: pointer to the HW structure
6610 * @ns_proxy_table_entry: pointer to NS table entry command struct
6611 * @cmd_details: pointer to command details
6613 * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
6614 * from pre-populated i40e_aqc_ns_proxy_data struct
6616 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
6617 struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
6618 struct i40e_asq_cmd_details *cmd_details)
6620 struct i40e_aq_desc desc;
6621 enum i40e_status_code status;
6623 if (!ns_proxy_table_entry)
6624 return I40E_ERR_PARAM;
6626 i40e_fill_default_direct_cmd_desc(&desc,
6627 i40e_aqc_opc_set_ns_proxy_table_entry);
6629 desc.params.external.addr_high =
6630 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
6631 desc.params.external.addr_low =
6632 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
6634 status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
6635 sizeof(struct i40e_aqc_ns_proxy_data),
6642 * i40e_aq_set_clear_wol_filter
6643 * @hw: pointer to the hw struct
6644 * @filter_index: index of filter to modify (0-7)
6645 * @filter: buffer containing filter to be set
6646 * @set_filter: true to set filter, false to clear filter
6647 * @no_wol_tco: if true, pass through packets cannot cause wake-up
6648 * if false, pass through packets may cause wake-up
6649 * @filter_valid: true if filter action is valid
6650 * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
6651 * @cmd_details: pointer to command details structure or NULL
6653 * Set or clear WoL filter for port attached to the PF
6655 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
6657 struct i40e_aqc_set_wol_filter_data *filter,
6658 bool set_filter, bool no_wol_tco,
6659 bool filter_valid, bool no_wol_tco_valid,
6660 struct i40e_asq_cmd_details *cmd_details)
6662 struct i40e_aq_desc desc;
6663 struct i40e_aqc_set_wol_filter *cmd =
6664 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
6665 enum i40e_status_code status;
6667 u16 valid_flags = 0;
6670 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
6672 if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
6673 return I40E_ERR_PARAM;
6674 cmd->filter_index = CPU_TO_LE16(filter_index);
6678 return I40E_ERR_PARAM;
6679 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
6680 buff_len = sizeof(*filter);
6683 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
6684 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
6687 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
6688 if (no_wol_tco_valid)
6689 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
6690 cmd->valid_flags = CPU_TO_LE16(valid_flags);
6692 cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
6693 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
6695 status = i40e_asq_send_command(hw, &desc, filter,
6696 buff_len, cmd_details);
6702 * i40e_aq_get_wake_event_reason
6703 * @hw: pointer to the hw struct
6704 * @wake_reason: return value, index of matching filter
6705 * @cmd_details: pointer to command details structure or NULL
6707 * Get information for the reason of a Wake Up event
6709 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
6711 struct i40e_asq_cmd_details *cmd_details)
6713 struct i40e_aq_desc desc;
6714 struct i40e_aqc_get_wake_reason_completion *resp =
6715 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
6716 enum i40e_status_code status;
6718 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
6720 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6722 if (status == I40E_SUCCESS)
6723 *wake_reason = LE16_TO_CPU(resp->wake_reason);
6728 #endif /* X722_SUPPORT */