1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "i40e_type.h"
35 #include "i40e_adminq.h"
36 #include "i40e_prototype.h"
37 #include "i40e_virtchnl.h"
41 * i40e_set_mac_type - Sets MAC type
42 * @hw: pointer to the HW structure
44 * This function sets the mac type of the adapter based on the
45 * vendor ID and device ID stored in the hw structure.
47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
53 enum i40e_status_code status = I40E_SUCCESS;
55 DEBUGFUNC("i40e_set_mac_type\n");
57 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
58 switch (hw->device_id) {
59 case I40E_DEV_ID_SFP_XL710:
60 case I40E_DEV_ID_QEMU:
61 case I40E_DEV_ID_KX_A:
62 case I40E_DEV_ID_KX_B:
63 case I40E_DEV_ID_KX_C:
64 case I40E_DEV_ID_QSFP_A:
65 case I40E_DEV_ID_QSFP_B:
66 case I40E_DEV_ID_QSFP_C:
67 case I40E_DEV_ID_10G_BASE_T:
68 case I40E_DEV_ID_10G_BASE_T4:
69 case I40E_DEV_ID_20G_KR2:
70 case I40E_DEV_ID_20G_KR2_A:
71 hw->mac.type = I40E_MAC_XL710;
74 case I40E_DEV_ID_VF_HV:
75 hw->mac.type = I40E_MAC_VF;
78 hw->mac.type = I40E_MAC_GENERIC;
82 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
85 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
86 hw->mac.type, status);
90 #ifndef I40E_NDIS_SUPPORT
92 * i40e_aq_str - convert AQ err code to a string
93 * @hw: pointer to the HW structure
94 * @aq_err: the AQ error code to convert
96 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
101 case I40E_AQ_RC_EPERM:
102 return "I40E_AQ_RC_EPERM";
103 case I40E_AQ_RC_ENOENT:
104 return "I40E_AQ_RC_ENOENT";
105 case I40E_AQ_RC_ESRCH:
106 return "I40E_AQ_RC_ESRCH";
107 case I40E_AQ_RC_EINTR:
108 return "I40E_AQ_RC_EINTR";
110 return "I40E_AQ_RC_EIO";
111 case I40E_AQ_RC_ENXIO:
112 return "I40E_AQ_RC_ENXIO";
113 case I40E_AQ_RC_E2BIG:
114 return "I40E_AQ_RC_E2BIG";
115 case I40E_AQ_RC_EAGAIN:
116 return "I40E_AQ_RC_EAGAIN";
117 case I40E_AQ_RC_ENOMEM:
118 return "I40E_AQ_RC_ENOMEM";
119 case I40E_AQ_RC_EACCES:
120 return "I40E_AQ_RC_EACCES";
121 case I40E_AQ_RC_EFAULT:
122 return "I40E_AQ_RC_EFAULT";
123 case I40E_AQ_RC_EBUSY:
124 return "I40E_AQ_RC_EBUSY";
125 case I40E_AQ_RC_EEXIST:
126 return "I40E_AQ_RC_EEXIST";
127 case I40E_AQ_RC_EINVAL:
128 return "I40E_AQ_RC_EINVAL";
129 case I40E_AQ_RC_ENOTTY:
130 return "I40E_AQ_RC_ENOTTY";
131 case I40E_AQ_RC_ENOSPC:
132 return "I40E_AQ_RC_ENOSPC";
133 case I40E_AQ_RC_ENOSYS:
134 return "I40E_AQ_RC_ENOSYS";
135 case I40E_AQ_RC_ERANGE:
136 return "I40E_AQ_RC_ERANGE";
137 case I40E_AQ_RC_EFLUSHED:
138 return "I40E_AQ_RC_EFLUSHED";
139 case I40E_AQ_RC_BAD_ADDR:
140 return "I40E_AQ_RC_BAD_ADDR";
141 case I40E_AQ_RC_EMODE:
142 return "I40E_AQ_RC_EMODE";
143 case I40E_AQ_RC_EFBIG:
144 return "I40E_AQ_RC_EFBIG";
147 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
152 * i40e_stat_str - convert status err code to a string
153 * @hw: pointer to the HW structure
154 * @stat_err: the status error code to convert
156 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
162 return "I40E_ERR_NVM";
163 case I40E_ERR_NVM_CHECKSUM:
164 return "I40E_ERR_NVM_CHECKSUM";
166 return "I40E_ERR_PHY";
167 case I40E_ERR_CONFIG:
168 return "I40E_ERR_CONFIG";
170 return "I40E_ERR_PARAM";
171 case I40E_ERR_MAC_TYPE:
172 return "I40E_ERR_MAC_TYPE";
173 case I40E_ERR_UNKNOWN_PHY:
174 return "I40E_ERR_UNKNOWN_PHY";
175 case I40E_ERR_LINK_SETUP:
176 return "I40E_ERR_LINK_SETUP";
177 case I40E_ERR_ADAPTER_STOPPED:
178 return "I40E_ERR_ADAPTER_STOPPED";
179 case I40E_ERR_INVALID_MAC_ADDR:
180 return "I40E_ERR_INVALID_MAC_ADDR";
181 case I40E_ERR_DEVICE_NOT_SUPPORTED:
182 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
183 case I40E_ERR_MASTER_REQUESTS_PENDING:
184 return "I40E_ERR_MASTER_REQUESTS_PENDING";
185 case I40E_ERR_INVALID_LINK_SETTINGS:
186 return "I40E_ERR_INVALID_LINK_SETTINGS";
187 case I40E_ERR_AUTONEG_NOT_COMPLETE:
188 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
189 case I40E_ERR_RESET_FAILED:
190 return "I40E_ERR_RESET_FAILED";
191 case I40E_ERR_SWFW_SYNC:
192 return "I40E_ERR_SWFW_SYNC";
193 case I40E_ERR_NO_AVAILABLE_VSI:
194 return "I40E_ERR_NO_AVAILABLE_VSI";
195 case I40E_ERR_NO_MEMORY:
196 return "I40E_ERR_NO_MEMORY";
197 case I40E_ERR_BAD_PTR:
198 return "I40E_ERR_BAD_PTR";
199 case I40E_ERR_RING_FULL:
200 return "I40E_ERR_RING_FULL";
201 case I40E_ERR_INVALID_PD_ID:
202 return "I40E_ERR_INVALID_PD_ID";
203 case I40E_ERR_INVALID_QP_ID:
204 return "I40E_ERR_INVALID_QP_ID";
205 case I40E_ERR_INVALID_CQ_ID:
206 return "I40E_ERR_INVALID_CQ_ID";
207 case I40E_ERR_INVALID_CEQ_ID:
208 return "I40E_ERR_INVALID_CEQ_ID";
209 case I40E_ERR_INVALID_AEQ_ID:
210 return "I40E_ERR_INVALID_AEQ_ID";
211 case I40E_ERR_INVALID_SIZE:
212 return "I40E_ERR_INVALID_SIZE";
213 case I40E_ERR_INVALID_ARP_INDEX:
214 return "I40E_ERR_INVALID_ARP_INDEX";
215 case I40E_ERR_INVALID_FPM_FUNC_ID:
216 return "I40E_ERR_INVALID_FPM_FUNC_ID";
217 case I40E_ERR_QP_INVALID_MSG_SIZE:
218 return "I40E_ERR_QP_INVALID_MSG_SIZE";
219 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
220 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
221 case I40E_ERR_INVALID_FRAG_COUNT:
222 return "I40E_ERR_INVALID_FRAG_COUNT";
223 case I40E_ERR_QUEUE_EMPTY:
224 return "I40E_ERR_QUEUE_EMPTY";
225 case I40E_ERR_INVALID_ALIGNMENT:
226 return "I40E_ERR_INVALID_ALIGNMENT";
227 case I40E_ERR_FLUSHED_QUEUE:
228 return "I40E_ERR_FLUSHED_QUEUE";
229 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
230 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
231 case I40E_ERR_INVALID_IMM_DATA_SIZE:
232 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
233 case I40E_ERR_TIMEOUT:
234 return "I40E_ERR_TIMEOUT";
235 case I40E_ERR_OPCODE_MISMATCH:
236 return "I40E_ERR_OPCODE_MISMATCH";
237 case I40E_ERR_CQP_COMPL_ERROR:
238 return "I40E_ERR_CQP_COMPL_ERROR";
239 case I40E_ERR_INVALID_VF_ID:
240 return "I40E_ERR_INVALID_VF_ID";
241 case I40E_ERR_INVALID_HMCFN_ID:
242 return "I40E_ERR_INVALID_HMCFN_ID";
243 case I40E_ERR_BACKING_PAGE_ERROR:
244 return "I40E_ERR_BACKING_PAGE_ERROR";
245 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
246 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
247 case I40E_ERR_INVALID_PBLE_INDEX:
248 return "I40E_ERR_INVALID_PBLE_INDEX";
249 case I40E_ERR_INVALID_SD_INDEX:
250 return "I40E_ERR_INVALID_SD_INDEX";
251 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
252 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
253 case I40E_ERR_INVALID_SD_TYPE:
254 return "I40E_ERR_INVALID_SD_TYPE";
255 case I40E_ERR_MEMCPY_FAILED:
256 return "I40E_ERR_MEMCPY_FAILED";
257 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
258 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
259 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
260 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
261 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
262 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
263 case I40E_ERR_SRQ_ENABLED:
264 return "I40E_ERR_SRQ_ENABLED";
265 case I40E_ERR_ADMIN_QUEUE_ERROR:
266 return "I40E_ERR_ADMIN_QUEUE_ERROR";
267 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
268 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
269 case I40E_ERR_BUF_TOO_SHORT:
270 return "I40E_ERR_BUF_TOO_SHORT";
271 case I40E_ERR_ADMIN_QUEUE_FULL:
272 return "I40E_ERR_ADMIN_QUEUE_FULL";
273 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
274 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
275 case I40E_ERR_BAD_IWARP_CQE:
276 return "I40E_ERR_BAD_IWARP_CQE";
277 case I40E_ERR_NVM_BLANK_MODE:
278 return "I40E_ERR_NVM_BLANK_MODE";
279 case I40E_ERR_NOT_IMPLEMENTED:
280 return "I40E_ERR_NOT_IMPLEMENTED";
281 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
282 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
283 case I40E_ERR_DIAG_TEST_FAILED:
284 return "I40E_ERR_DIAG_TEST_FAILED";
285 case I40E_ERR_NOT_READY:
286 return "I40E_ERR_NOT_READY";
287 case I40E_NOT_SUPPORTED:
288 return "I40E_NOT_SUPPORTED";
289 case I40E_ERR_FIRMWARE_API_VERSION:
290 return "I40E_ERR_FIRMWARE_API_VERSION";
293 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
297 #endif /* I40E_NDIS_SUPPORT */
300 * @hw: debug mask related to admin queue
302 * @desc: pointer to admin queue descriptor
303 * @buffer: pointer to command buffer
304 * @buf_len: max length of buffer
306 * Dumps debug log about adminq command with descriptor contents.
308 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
309 void *buffer, u16 buf_len)
311 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
312 u16 len = LE16_TO_CPU(aq_desc->datalen);
313 u8 *buf = (u8 *)buffer;
316 if ((!(mask & hw->debug_mask)) || (desc == NULL))
320 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
321 LE16_TO_CPU(aq_desc->opcode),
322 LE16_TO_CPU(aq_desc->flags),
323 LE16_TO_CPU(aq_desc->datalen),
324 LE16_TO_CPU(aq_desc->retval));
325 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
326 LE32_TO_CPU(aq_desc->cookie_high),
327 LE32_TO_CPU(aq_desc->cookie_low));
328 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
329 LE32_TO_CPU(aq_desc->params.internal.param0),
330 LE32_TO_CPU(aq_desc->params.internal.param1));
331 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
332 LE32_TO_CPU(aq_desc->params.external.addr_high),
333 LE32_TO_CPU(aq_desc->params.external.addr_low));
335 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
336 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
339 /* write the full 16-byte chunks */
340 for (i = 0; i < (len - 16); i += 16)
342 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
343 i, buf[i], buf[i+1], buf[i+2], buf[i+3],
344 buf[i+4], buf[i+5], buf[i+6], buf[i+7],
345 buf[i+8], buf[i+9], buf[i+10], buf[i+11],
346 buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
347 /* the most we could have left is 16 bytes, pad with zeros */
352 memset(d_buf, 0, sizeof(d_buf));
353 for (j = 0; i < len; j++, i++)
356 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
357 i, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
358 d_buf[4], d_buf[5], d_buf[6], d_buf[7],
359 d_buf[8], d_buf[9], d_buf[10], d_buf[11],
360 d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
366 * i40e_check_asq_alive
367 * @hw: pointer to the hw struct
369 * Returns true if Queue is enabled else false.
371 bool i40e_check_asq_alive(struct i40e_hw *hw)
377 return !!(rd32(hw, hw->aq.asq.len) &
378 I40E_PF_ATQLEN_ATQENABLE_MASK);
380 return !!(rd32(hw, hw->aq.asq.len) &
381 I40E_PF_ATQLEN_ATQENABLE_MASK);
382 #endif /* INTEGRATED_VF */
383 #endif /* PF_DRIVER */
387 return !!(rd32(hw, hw->aq.asq.len) &
388 I40E_VF_ATQLEN1_ATQENABLE_MASK);
390 return !!(rd32(hw, hw->aq.asq.len) &
391 I40E_VF_ATQLEN1_ATQENABLE_MASK);
392 #endif /* INTEGRATED_VF */
393 #endif /* VF_DRIVER */
398 * i40e_aq_queue_shutdown
399 * @hw: pointer to the hw struct
400 * @unloading: is the driver unloading itself
402 * Tell the Firmware that we're shutting down the AdminQ and whether
403 * or not the driver is unloading as well.
405 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
408 struct i40e_aq_desc desc;
409 struct i40e_aqc_queue_shutdown *cmd =
410 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
411 enum i40e_status_code status;
413 i40e_fill_default_direct_cmd_desc(&desc,
414 i40e_aqc_opc_queue_shutdown);
417 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
418 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
423 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
424 * hardware to a bit-field that can be used by SW to more easily determine the
427 * Macros are used to shorten the table lines and make this table human
430 * We store the PTYPE in the top byte of the bit field - this is just so that
431 * we can check that the table doesn't have a row missing, as the index into
432 * the table should be the PTYPE.
436 * IF NOT i40e_ptype_lookup[ptype].known
439 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
440 * Use the rest of the fields to look at the tunnels, inner protocols, etc
442 * Use the enum i40e_rx_l2_ptype to decode the packet type
446 /* macro to make the table lines short */
447 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
450 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
451 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
452 I40E_RX_PTYPE_##OUTER_FRAG, \
453 I40E_RX_PTYPE_TUNNEL_##T, \
454 I40E_RX_PTYPE_TUNNEL_END_##TE, \
455 I40E_RX_PTYPE_##TEF, \
456 I40E_RX_PTYPE_INNER_PROT_##I, \
457 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
459 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
460 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
462 /* shorter macros makes the table fit but are terse */
463 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
464 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
465 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
467 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
468 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
469 /* L2 Packet types */
470 I40E_PTT_UNUSED_ENTRY(0),
471 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
472 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
473 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
474 I40E_PTT_UNUSED_ENTRY(4),
475 I40E_PTT_UNUSED_ENTRY(5),
476 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
477 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
478 I40E_PTT_UNUSED_ENTRY(8),
479 I40E_PTT_UNUSED_ENTRY(9),
480 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
481 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
482 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
483 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
484 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
485 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
486 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
487 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
488 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
489 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
490 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
491 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
493 /* Non Tunneled IPv4 */
494 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
495 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
496 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
497 I40E_PTT_UNUSED_ENTRY(25),
498 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
499 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
500 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
503 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
504 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
505 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
506 I40E_PTT_UNUSED_ENTRY(32),
507 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
508 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
509 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
512 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
513 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
514 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
515 I40E_PTT_UNUSED_ENTRY(39),
516 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
517 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
518 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
520 /* IPv4 --> GRE/NAT */
521 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
523 /* IPv4 --> GRE/NAT --> IPv4 */
524 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
525 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
526 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
527 I40E_PTT_UNUSED_ENTRY(47),
528 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
529 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
530 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
532 /* IPv4 --> GRE/NAT --> IPv6 */
533 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
534 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
535 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
536 I40E_PTT_UNUSED_ENTRY(54),
537 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
538 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
539 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
541 /* IPv4 --> GRE/NAT --> MAC */
542 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
544 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
545 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
546 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
547 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
548 I40E_PTT_UNUSED_ENTRY(62),
549 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
550 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
551 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
553 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
554 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
555 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
556 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
557 I40E_PTT_UNUSED_ENTRY(69),
558 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
559 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
560 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
562 /* IPv4 --> GRE/NAT --> MAC/VLAN */
563 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
565 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
566 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
567 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
568 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
569 I40E_PTT_UNUSED_ENTRY(77),
570 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
571 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
572 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
574 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
575 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
576 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
577 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
578 I40E_PTT_UNUSED_ENTRY(84),
579 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
580 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
581 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
583 /* Non Tunneled IPv6 */
584 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
585 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
586 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
587 I40E_PTT_UNUSED_ENTRY(91),
588 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
589 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
590 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
593 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
594 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
595 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
596 I40E_PTT_UNUSED_ENTRY(98),
597 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
598 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
599 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
602 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
603 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
604 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
605 I40E_PTT_UNUSED_ENTRY(105),
606 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
607 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
608 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
610 /* IPv6 --> GRE/NAT */
611 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
613 /* IPv6 --> GRE/NAT -> IPv4 */
614 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
615 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
616 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
617 I40E_PTT_UNUSED_ENTRY(113),
618 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
619 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
620 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
622 /* IPv6 --> GRE/NAT -> IPv6 */
623 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
624 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
625 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
626 I40E_PTT_UNUSED_ENTRY(120),
627 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
628 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
629 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
631 /* IPv6 --> GRE/NAT -> MAC */
632 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
634 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
635 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
636 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
637 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
638 I40E_PTT_UNUSED_ENTRY(128),
639 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
640 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
641 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
643 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
644 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
645 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
646 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
647 I40E_PTT_UNUSED_ENTRY(135),
648 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
649 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
650 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
652 /* IPv6 --> GRE/NAT -> MAC/VLAN */
653 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
655 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
656 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
657 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
658 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
659 I40E_PTT_UNUSED_ENTRY(143),
660 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
661 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
662 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
664 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
665 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
666 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
667 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
668 I40E_PTT_UNUSED_ENTRY(150),
669 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
670 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
671 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
674 I40E_PTT_UNUSED_ENTRY(154),
675 I40E_PTT_UNUSED_ENTRY(155),
676 I40E_PTT_UNUSED_ENTRY(156),
677 I40E_PTT_UNUSED_ENTRY(157),
678 I40E_PTT_UNUSED_ENTRY(158),
679 I40E_PTT_UNUSED_ENTRY(159),
681 I40E_PTT_UNUSED_ENTRY(160),
682 I40E_PTT_UNUSED_ENTRY(161),
683 I40E_PTT_UNUSED_ENTRY(162),
684 I40E_PTT_UNUSED_ENTRY(163),
685 I40E_PTT_UNUSED_ENTRY(164),
686 I40E_PTT_UNUSED_ENTRY(165),
687 I40E_PTT_UNUSED_ENTRY(166),
688 I40E_PTT_UNUSED_ENTRY(167),
689 I40E_PTT_UNUSED_ENTRY(168),
690 I40E_PTT_UNUSED_ENTRY(169),
692 I40E_PTT_UNUSED_ENTRY(170),
693 I40E_PTT_UNUSED_ENTRY(171),
694 I40E_PTT_UNUSED_ENTRY(172),
695 I40E_PTT_UNUSED_ENTRY(173),
696 I40E_PTT_UNUSED_ENTRY(174),
697 I40E_PTT_UNUSED_ENTRY(175),
698 I40E_PTT_UNUSED_ENTRY(176),
699 I40E_PTT_UNUSED_ENTRY(177),
700 I40E_PTT_UNUSED_ENTRY(178),
701 I40E_PTT_UNUSED_ENTRY(179),
703 I40E_PTT_UNUSED_ENTRY(180),
704 I40E_PTT_UNUSED_ENTRY(181),
705 I40E_PTT_UNUSED_ENTRY(182),
706 I40E_PTT_UNUSED_ENTRY(183),
707 I40E_PTT_UNUSED_ENTRY(184),
708 I40E_PTT_UNUSED_ENTRY(185),
709 I40E_PTT_UNUSED_ENTRY(186),
710 I40E_PTT_UNUSED_ENTRY(187),
711 I40E_PTT_UNUSED_ENTRY(188),
712 I40E_PTT_UNUSED_ENTRY(189),
714 I40E_PTT_UNUSED_ENTRY(190),
715 I40E_PTT_UNUSED_ENTRY(191),
716 I40E_PTT_UNUSED_ENTRY(192),
717 I40E_PTT_UNUSED_ENTRY(193),
718 I40E_PTT_UNUSED_ENTRY(194),
719 I40E_PTT_UNUSED_ENTRY(195),
720 I40E_PTT_UNUSED_ENTRY(196),
721 I40E_PTT_UNUSED_ENTRY(197),
722 I40E_PTT_UNUSED_ENTRY(198),
723 I40E_PTT_UNUSED_ENTRY(199),
725 I40E_PTT_UNUSED_ENTRY(200),
726 I40E_PTT_UNUSED_ENTRY(201),
727 I40E_PTT_UNUSED_ENTRY(202),
728 I40E_PTT_UNUSED_ENTRY(203),
729 I40E_PTT_UNUSED_ENTRY(204),
730 I40E_PTT_UNUSED_ENTRY(205),
731 I40E_PTT_UNUSED_ENTRY(206),
732 I40E_PTT_UNUSED_ENTRY(207),
733 I40E_PTT_UNUSED_ENTRY(208),
734 I40E_PTT_UNUSED_ENTRY(209),
736 I40E_PTT_UNUSED_ENTRY(210),
737 I40E_PTT_UNUSED_ENTRY(211),
738 I40E_PTT_UNUSED_ENTRY(212),
739 I40E_PTT_UNUSED_ENTRY(213),
740 I40E_PTT_UNUSED_ENTRY(214),
741 I40E_PTT_UNUSED_ENTRY(215),
742 I40E_PTT_UNUSED_ENTRY(216),
743 I40E_PTT_UNUSED_ENTRY(217),
744 I40E_PTT_UNUSED_ENTRY(218),
745 I40E_PTT_UNUSED_ENTRY(219),
747 I40E_PTT_UNUSED_ENTRY(220),
748 I40E_PTT_UNUSED_ENTRY(221),
749 I40E_PTT_UNUSED_ENTRY(222),
750 I40E_PTT_UNUSED_ENTRY(223),
751 I40E_PTT_UNUSED_ENTRY(224),
752 I40E_PTT_UNUSED_ENTRY(225),
753 I40E_PTT_UNUSED_ENTRY(226),
754 I40E_PTT_UNUSED_ENTRY(227),
755 I40E_PTT_UNUSED_ENTRY(228),
756 I40E_PTT_UNUSED_ENTRY(229),
758 I40E_PTT_UNUSED_ENTRY(230),
759 I40E_PTT_UNUSED_ENTRY(231),
760 I40E_PTT_UNUSED_ENTRY(232),
761 I40E_PTT_UNUSED_ENTRY(233),
762 I40E_PTT_UNUSED_ENTRY(234),
763 I40E_PTT_UNUSED_ENTRY(235),
764 I40E_PTT_UNUSED_ENTRY(236),
765 I40E_PTT_UNUSED_ENTRY(237),
766 I40E_PTT_UNUSED_ENTRY(238),
767 I40E_PTT_UNUSED_ENTRY(239),
769 I40E_PTT_UNUSED_ENTRY(240),
770 I40E_PTT_UNUSED_ENTRY(241),
771 I40E_PTT_UNUSED_ENTRY(242),
772 I40E_PTT_UNUSED_ENTRY(243),
773 I40E_PTT_UNUSED_ENTRY(244),
774 I40E_PTT_UNUSED_ENTRY(245),
775 I40E_PTT_UNUSED_ENTRY(246),
776 I40E_PTT_UNUSED_ENTRY(247),
777 I40E_PTT_UNUSED_ENTRY(248),
778 I40E_PTT_UNUSED_ENTRY(249),
780 I40E_PTT_UNUSED_ENTRY(250),
781 I40E_PTT_UNUSED_ENTRY(251),
782 I40E_PTT_UNUSED_ENTRY(252),
783 I40E_PTT_UNUSED_ENTRY(253),
784 I40E_PTT_UNUSED_ENTRY(254),
785 I40E_PTT_UNUSED_ENTRY(255)
790 * i40e_validate_mac_addr - Validate unicast MAC address
791 * @mac_addr: pointer to MAC address
793 * Tests a MAC address to ensure it is a valid Individual Address
795 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
797 enum i40e_status_code status = I40E_SUCCESS;
799 DEBUGFUNC("i40e_validate_mac_addr");
801 /* Broadcast addresses ARE multicast addresses
802 * Make sure it is not a multicast address
803 * Reject the zero address
805 if (I40E_IS_MULTICAST(mac_addr) ||
806 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
807 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
808 status = I40E_ERR_INVALID_MAC_ADDR;
815 * i40e_init_shared_code - Initialize the shared code
816 * @hw: pointer to hardware structure
818 * This assigns the MAC type and PHY code and inits the NVM.
819 * Does not touch the hardware. This function must be called prior to any
820 * other function in the shared code. The i40e_hw structure should be
821 * memset to 0 prior to calling this function. The following fields in
822 * hw structure should be filled in prior to calling this function:
823 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
824 * subsystem_vendor_id, and revision_id
826 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
828 enum i40e_status_code status = I40E_SUCCESS;
829 u32 port, ari, func_rid;
831 DEBUGFUNC("i40e_init_shared_code");
833 i40e_set_mac_type(hw);
835 switch (hw->mac.type) {
839 return I40E_ERR_DEVICE_NOT_SUPPORTED;
842 hw->phy.get_link_info = true;
844 /* Determine port number and PF number*/
845 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
846 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
848 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
849 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
850 func_rid = rd32(hw, I40E_PF_FUNC_RID);
852 hw->pf_id = (u8)(func_rid & 0xff);
854 hw->pf_id = (u8)(func_rid & 0x7);
856 status = i40e_init_nvm(hw);
861 * i40e_aq_mac_address_read - Retrieve the MAC addresses
862 * @hw: pointer to the hw struct
863 * @flags: a return indicator of what addresses were added to the addr store
864 * @addrs: the requestor's mac addr store
865 * @cmd_details: pointer to command details structure or NULL
867 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
869 struct i40e_aqc_mac_address_read_data *addrs,
870 struct i40e_asq_cmd_details *cmd_details)
872 struct i40e_aq_desc desc;
873 struct i40e_aqc_mac_address_read *cmd_data =
874 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
875 enum i40e_status_code status;
877 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
878 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
880 status = i40e_asq_send_command(hw, &desc, addrs,
881 sizeof(*addrs), cmd_details);
882 *flags = LE16_TO_CPU(cmd_data->command_flags);
888 * i40e_aq_mac_address_write - Change the MAC addresses
889 * @hw: pointer to the hw struct
890 * @flags: indicates which MAC to be written
891 * @mac_addr: address to write
892 * @cmd_details: pointer to command details structure or NULL
894 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
895 u16 flags, u8 *mac_addr,
896 struct i40e_asq_cmd_details *cmd_details)
898 struct i40e_aq_desc desc;
899 struct i40e_aqc_mac_address_write *cmd_data =
900 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
901 enum i40e_status_code status;
903 i40e_fill_default_direct_cmd_desc(&desc,
904 i40e_aqc_opc_mac_address_write);
905 cmd_data->command_flags = CPU_TO_LE16(flags);
906 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
907 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
908 ((u32)mac_addr[3] << 16) |
909 ((u32)mac_addr[4] << 8) |
912 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
918 * i40e_get_mac_addr - get MAC address
919 * @hw: pointer to the HW structure
920 * @mac_addr: pointer to MAC address
922 * Reads the adapter's MAC address from register
924 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
926 struct i40e_aqc_mac_address_read_data addrs;
927 enum i40e_status_code status;
930 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
932 if (flags & I40E_AQC_LAN_ADDR_VALID)
933 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
939 * i40e_get_port_mac_addr - get Port MAC address
940 * @hw: pointer to the HW structure
941 * @mac_addr: pointer to Port MAC address
943 * Reads the adapter's Port MAC address
945 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
947 struct i40e_aqc_mac_address_read_data addrs;
948 enum i40e_status_code status;
951 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
955 if (flags & I40E_AQC_PORT_ADDR_VALID)
956 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
958 status = I40E_ERR_INVALID_MAC_ADDR;
964 * i40e_pre_tx_queue_cfg - pre tx queue configure
965 * @hw: pointer to the HW structure
966 * @queue: target pf queue index
967 * @enable: state change request
969 * Handles hw requirement to indicate intention to enable
970 * or disable target queue.
972 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
974 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
978 if (abs_queue_idx >= 128) {
979 reg_block = abs_queue_idx / 128;
980 abs_queue_idx %= 128;
983 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
984 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
985 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
988 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
990 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
992 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
996 * i40e_read_pba_string - Reads part number string from EEPROM
997 * @hw: pointer to hardware structure
998 * @pba_num: stores the part number string from the EEPROM
999 * @pba_num_size: part number string buffer length
1001 * Reads the part number string from the EEPROM.
1003 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1006 enum i40e_status_code status = I40E_SUCCESS;
1012 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1013 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1014 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1018 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1019 if (status != I40E_SUCCESS) {
1020 DEBUGOUT("Failed to read PBA Block pointer.\n");
1024 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1025 if (status != I40E_SUCCESS) {
1026 DEBUGOUT("Failed to read PBA Block size.\n");
1030 /* Subtract one to get PBA word count (PBA Size word is included in
1034 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1035 DEBUGOUT("Buffer to small for PBA data.\n");
1036 return I40E_ERR_PARAM;
1039 for (i = 0; i < pba_size; i++) {
1040 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1041 if (status != I40E_SUCCESS) {
1042 DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1046 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1047 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1049 pba_num[(pba_size * 2)] = '\0';
1055 * i40e_get_media_type - Gets media type
1056 * @hw: pointer to the hardware structure
1058 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1060 enum i40e_media_type media;
1062 switch (hw->phy.link_info.phy_type) {
1063 case I40E_PHY_TYPE_10GBASE_SR:
1064 case I40E_PHY_TYPE_10GBASE_LR:
1065 case I40E_PHY_TYPE_1000BASE_SX:
1066 case I40E_PHY_TYPE_1000BASE_LX:
1067 case I40E_PHY_TYPE_40GBASE_SR4:
1068 case I40E_PHY_TYPE_40GBASE_LR4:
1069 media = I40E_MEDIA_TYPE_FIBER;
1071 case I40E_PHY_TYPE_100BASE_TX:
1072 case I40E_PHY_TYPE_1000BASE_T:
1073 case I40E_PHY_TYPE_10GBASE_T:
1074 media = I40E_MEDIA_TYPE_BASET;
1076 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1077 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1078 case I40E_PHY_TYPE_10GBASE_CR1:
1079 case I40E_PHY_TYPE_40GBASE_CR4:
1080 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1081 case I40E_PHY_TYPE_40GBASE_AOC:
1082 case I40E_PHY_TYPE_10GBASE_AOC:
1083 media = I40E_MEDIA_TYPE_DA;
1085 case I40E_PHY_TYPE_1000BASE_KX:
1086 case I40E_PHY_TYPE_10GBASE_KX4:
1087 case I40E_PHY_TYPE_10GBASE_KR:
1088 case I40E_PHY_TYPE_40GBASE_KR4:
1089 case I40E_PHY_TYPE_20GBASE_KR2:
1090 media = I40E_MEDIA_TYPE_BACKPLANE;
1092 case I40E_PHY_TYPE_SGMII:
1093 case I40E_PHY_TYPE_XAUI:
1094 case I40E_PHY_TYPE_XFI:
1095 case I40E_PHY_TYPE_XLAUI:
1096 case I40E_PHY_TYPE_XLPPI:
1098 media = I40E_MEDIA_TYPE_UNKNOWN;
1105 #define I40E_PF_RESET_WAIT_COUNT 200
1107 * i40e_pf_reset - Reset the PF
1108 * @hw: pointer to the hardware structure
1110 * Assuming someone else has triggered a global reset,
1111 * assure the global reset is complete and then reset the PF
1113 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1120 /* Poll for Global Reset steady state in case of recent GRST.
1121 * The grst delay value is in 100ms units, and we'll wait a
1122 * couple counts longer to be sure we don't just miss the end.
1124 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1125 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1126 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1127 for (cnt = 0; cnt < grst_del + 2; cnt++) {
1128 reg = rd32(hw, I40E_GLGEN_RSTAT);
1129 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1131 i40e_msec_delay(100);
1133 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1134 DEBUGOUT("Global reset polling failed to complete.\n");
1135 return I40E_ERR_RESET_FAILED;
1138 /* Now Wait for the FW to be ready */
1139 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1140 reg = rd32(hw, I40E_GLNVM_ULD);
1141 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1142 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1143 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1144 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1145 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1148 i40e_msec_delay(10);
1150 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1151 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1152 DEBUGOUT("wait for FW Reset complete timedout\n");
1153 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1154 return I40E_ERR_RESET_FAILED;
1157 /* If there was a Global Reset in progress when we got here,
1158 * we don't need to do the PF Reset
1161 reg = rd32(hw, I40E_PFGEN_CTRL);
1162 wr32(hw, I40E_PFGEN_CTRL,
1163 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1164 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1165 reg = rd32(hw, I40E_PFGEN_CTRL);
1166 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1170 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1171 DEBUGOUT("PF reset polling failed to complete.\n");
1172 return I40E_ERR_RESET_FAILED;
1176 i40e_clear_pxe_mode(hw);
1179 return I40E_SUCCESS;
1183 * i40e_clear_hw - clear out any left over hw state
1184 * @hw: pointer to the hw struct
1186 * Clear queues and interrupts, typically called at init time,
1187 * but after the capabilities have been found so we know how many
1188 * queues and msix vectors have been allocated.
1190 void i40e_clear_hw(struct i40e_hw *hw)
1192 u32 num_queues, base_queue;
1200 /* get number of interrupts, queues, and vfs */
1201 val = rd32(hw, I40E_GLPCI_CNF2);
1202 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1203 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1204 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1205 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1207 val = rd32(hw, I40E_PFLAN_QALLOC);
1208 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1209 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1210 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1211 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1212 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1213 num_queues = (j - base_queue) + 1;
1217 val = rd32(hw, I40E_PF_VT_PFALLOC);
1218 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1219 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1220 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1221 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1222 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1223 num_vfs = (j - i) + 1;
1227 /* stop all the interrupts */
1228 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1229 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1230 for (i = 0; i < num_pf_int - 2; i++)
1231 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1233 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1234 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1235 wr32(hw, I40E_PFINT_LNKLST0, val);
1236 for (i = 0; i < num_pf_int - 2; i++)
1237 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1238 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1239 for (i = 0; i < num_vfs; i++)
1240 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1241 for (i = 0; i < num_vf_int - 2; i++)
1242 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1244 /* warn the HW of the coming Tx disables */
1245 for (i = 0; i < num_queues; i++) {
1246 u32 abs_queue_idx = base_queue + i;
1249 if (abs_queue_idx >= 128) {
1250 reg_block = abs_queue_idx / 128;
1251 abs_queue_idx %= 128;
1254 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1255 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1256 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1257 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1259 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1261 i40e_usec_delay(400);
1263 /* stop all the queues */
1264 for (i = 0; i < num_queues; i++) {
1265 wr32(hw, I40E_QINT_TQCTL(i), 0);
1266 wr32(hw, I40E_QTX_ENA(i), 0);
1267 wr32(hw, I40E_QINT_RQCTL(i), 0);
1268 wr32(hw, I40E_QRX_ENA(i), 0);
1271 /* short wait for all queue disables to settle */
1272 i40e_usec_delay(50);
1276 * i40e_clear_pxe_mode - clear pxe operations mode
1277 * @hw: pointer to the hw struct
1279 * Make sure all PXE mode settings are cleared, including things
1280 * like descriptor fetch/write-back mode.
1282 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1284 if (i40e_check_asq_alive(hw))
1285 i40e_aq_clear_pxe_mode(hw, NULL);
1289 * i40e_led_is_mine - helper to find matching led
1290 * @hw: pointer to the hw struct
1291 * @idx: index into GPIO registers
1293 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1295 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1300 if (!hw->func_caps.led[idx])
1303 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1304 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1305 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1307 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1308 * if it is not our port then ignore
1310 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1317 #define I40E_COMBINED_ACTIVITY 0xA
1318 #define I40E_FILTER_ACTIVITY 0xE
1319 #define I40E_LINK_ACTIVITY 0xC
1320 #define I40E_MAC_ACTIVITY 0xD
1321 #define I40E_LED0 22
1324 * i40e_led_get - return current on/off mode
1325 * @hw: pointer to the hw struct
1327 * The value returned is the 'mode' field as defined in the
1328 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1329 * values are variations of possible behaviors relating to
1330 * blink, link, and wire.
1332 u32 i40e_led_get(struct i40e_hw *hw)
1334 u32 current_mode = 0;
1338 /* as per the documentation GPIO 22-29 are the LED
1339 * GPIO pins named LED0..LED7
1341 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1342 u32 gpio_val = i40e_led_is_mine(hw, i);
1347 /* ignore gpio LED src mode entries related to the activity LEDs */
1348 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1349 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1350 switch (current_mode) {
1351 case I40E_COMBINED_ACTIVITY:
1352 case I40E_FILTER_ACTIVITY:
1353 case I40E_MAC_ACTIVITY:
1359 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1360 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1368 * i40e_led_set - set new on/off mode
1369 * @hw: pointer to the hw struct
1370 * @mode: 0=off, 0xf=on (else see manual for mode details)
1371 * @blink: true if the LED should blink when on, false if steady
1373 * if this function is used to turn on the blink it should
1374 * be used to disable the blink when restoring the original state.
1376 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1378 u32 current_mode = 0;
1381 if (mode & 0xfffffff0)
1382 DEBUGOUT1("invalid mode passed in %X\n", mode);
1384 /* as per the documentation GPIO 22-29 are the LED
1385 * GPIO pins named LED0..LED7
1387 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1388 u32 gpio_val = i40e_led_is_mine(hw, i);
1393 /* ignore gpio LED src mode entries related to the activity LEDs */
1394 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1395 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1396 switch (current_mode) {
1397 case I40E_COMBINED_ACTIVITY:
1398 case I40E_FILTER_ACTIVITY:
1399 case I40E_MAC_ACTIVITY:
1405 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1406 /* this & is a bit of paranoia, but serves as a range check */
1407 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1408 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1410 if (mode == I40E_LINK_ACTIVITY)
1414 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1416 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1418 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1423 /* Admin command wrappers */
1426 * i40e_aq_get_phy_capabilities
1427 * @hw: pointer to the hw struct
1428 * @abilities: structure for PHY capabilities to be filled
1429 * @qualified_modules: report Qualified Modules
1430 * @report_init: report init capabilities (active are default)
1431 * @cmd_details: pointer to command details structure or NULL
1433 * Returns the various PHY abilities supported on the Port.
1435 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1436 bool qualified_modules, bool report_init,
1437 struct i40e_aq_get_phy_abilities_resp *abilities,
1438 struct i40e_asq_cmd_details *cmd_details)
1440 struct i40e_aq_desc desc;
1441 enum i40e_status_code status;
1442 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1445 return I40E_ERR_PARAM;
1447 i40e_fill_default_direct_cmd_desc(&desc,
1448 i40e_aqc_opc_get_phy_abilities);
1450 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1451 if (abilities_size > I40E_AQ_LARGE_BUF)
1452 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1454 if (qualified_modules)
1455 desc.params.external.param0 |=
1456 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1459 desc.params.external.param0 |=
1460 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1462 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1465 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1466 status = I40E_ERR_UNKNOWN_PHY;
1472 * i40e_aq_set_phy_config
1473 * @hw: pointer to the hw struct
1474 * @config: structure with PHY configuration to be set
1475 * @cmd_details: pointer to command details structure or NULL
1477 * Set the various PHY configuration parameters
1478 * supported on the Port.One or more of the Set PHY config parameters may be
1479 * ignored in an MFP mode as the PF may not have the privilege to set some
1480 * of the PHY Config parameters. This status will be indicated by the
1483 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1484 struct i40e_aq_set_phy_config *config,
1485 struct i40e_asq_cmd_details *cmd_details)
1487 struct i40e_aq_desc desc;
1488 struct i40e_aq_set_phy_config *cmd =
1489 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1490 enum i40e_status_code status;
1493 return I40E_ERR_PARAM;
1495 i40e_fill_default_direct_cmd_desc(&desc,
1496 i40e_aqc_opc_set_phy_config);
1500 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1507 * @hw: pointer to the hw struct
1509 * Set the requested flow control mode using set_phy_config.
1511 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1512 bool atomic_restart)
1514 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1515 struct i40e_aq_get_phy_abilities_resp abilities;
1516 struct i40e_aq_set_phy_config config;
1517 enum i40e_status_code status;
1518 u8 pause_mask = 0x0;
1524 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1525 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1527 case I40E_FC_RX_PAUSE:
1528 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1530 case I40E_FC_TX_PAUSE:
1531 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1537 /* Get the current phy config */
1538 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1541 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1545 memset(&config, 0, sizeof(config));
1546 /* clear the old pause settings */
1547 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1548 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1549 /* set the new abilities */
1550 config.abilities |= pause_mask;
1551 /* If the abilities have changed, then set the new config */
1552 if (config.abilities != abilities.abilities) {
1553 /* Auto restart link so settings take effect */
1555 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1556 /* Copy over all the old settings */
1557 config.phy_type = abilities.phy_type;
1558 config.link_speed = abilities.link_speed;
1559 config.eee_capability = abilities.eee_capability;
1560 config.eeer = abilities.eeer_val;
1561 config.low_power_ctrl = abilities.d3_lpan;
1562 status = i40e_aq_set_phy_config(hw, &config, NULL);
1565 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1567 /* Update the link info */
1568 status = i40e_update_link_info(hw);
1570 /* Wait a little bit (on 40G cards it sometimes takes a really
1571 * long time for link to come back from the atomic reset)
1574 i40e_msec_delay(1000);
1575 status = i40e_update_link_info(hw);
1578 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1584 * i40e_aq_set_mac_config
1585 * @hw: pointer to the hw struct
1586 * @max_frame_size: Maximum Frame Size to be supported by the port
1587 * @crc_en: Tell HW to append a CRC to outgoing frames
1588 * @pacing: Pacing configurations
1589 * @cmd_details: pointer to command details structure or NULL
1591 * Configure MAC settings for frame size, jumbo frame support and the
1592 * addition of a CRC by the hardware.
1594 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1596 bool crc_en, u16 pacing,
1597 struct i40e_asq_cmd_details *cmd_details)
1599 struct i40e_aq_desc desc;
1600 struct i40e_aq_set_mac_config *cmd =
1601 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1602 enum i40e_status_code status;
1604 if (max_frame_size == 0)
1605 return I40E_ERR_PARAM;
1607 i40e_fill_default_direct_cmd_desc(&desc,
1608 i40e_aqc_opc_set_mac_config);
1610 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1611 cmd->params = ((u8)pacing & 0x0F) << 3;
1613 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1615 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1621 * i40e_aq_clear_pxe_mode
1622 * @hw: pointer to the hw struct
1623 * @cmd_details: pointer to command details structure or NULL
1625 * Tell the firmware that the driver is taking over from PXE
1627 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1628 struct i40e_asq_cmd_details *cmd_details)
1630 enum i40e_status_code status;
1631 struct i40e_aq_desc desc;
1632 struct i40e_aqc_clear_pxe *cmd =
1633 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1635 i40e_fill_default_direct_cmd_desc(&desc,
1636 i40e_aqc_opc_clear_pxe_mode);
1640 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1642 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1648 * i40e_aq_set_link_restart_an
1649 * @hw: pointer to the hw struct
1650 * @enable_link: if true: enable link, if false: disable link
1651 * @cmd_details: pointer to command details structure or NULL
1653 * Sets up the link and restarts the Auto-Negotiation over the link.
1655 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1656 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1658 struct i40e_aq_desc desc;
1659 struct i40e_aqc_set_link_restart_an *cmd =
1660 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1661 enum i40e_status_code status;
1663 i40e_fill_default_direct_cmd_desc(&desc,
1664 i40e_aqc_opc_set_link_restart_an);
1666 cmd->command = I40E_AQ_PHY_RESTART_AN;
1668 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1670 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1672 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1678 * i40e_aq_get_link_info
1679 * @hw: pointer to the hw struct
1680 * @enable_lse: enable/disable LinkStatusEvent reporting
1681 * @link: pointer to link status structure - optional
1682 * @cmd_details: pointer to command details structure or NULL
1684 * Returns the link status of the adapter.
1686 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1687 bool enable_lse, struct i40e_link_status *link,
1688 struct i40e_asq_cmd_details *cmd_details)
1690 struct i40e_aq_desc desc;
1691 struct i40e_aqc_get_link_status *resp =
1692 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1693 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1694 enum i40e_status_code status;
1695 bool tx_pause, rx_pause;
1698 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1701 command_flags = I40E_AQ_LSE_ENABLE;
1703 command_flags = I40E_AQ_LSE_DISABLE;
1704 resp->command_flags = CPU_TO_LE16(command_flags);
1706 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1708 if (status != I40E_SUCCESS)
1709 goto aq_get_link_info_exit;
1711 /* save off old link status information */
1712 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1713 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1715 /* update link status */
1716 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1717 hw->phy.media_type = i40e_get_media_type(hw);
1718 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1719 hw_link_info->link_info = resp->link_info;
1720 hw_link_info->an_info = resp->an_info;
1721 hw_link_info->ext_info = resp->ext_info;
1722 hw_link_info->loopback = resp->loopback;
1723 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1724 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1726 /* update fc info */
1727 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1728 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1729 if (tx_pause & rx_pause)
1730 hw->fc.current_mode = I40E_FC_FULL;
1732 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1734 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1736 hw->fc.current_mode = I40E_FC_NONE;
1738 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1739 hw_link_info->crc_enable = true;
1741 hw_link_info->crc_enable = false;
1743 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1744 hw_link_info->lse_enable = true;
1746 hw_link_info->lse_enable = false;
1748 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1749 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1750 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1752 /* save link status information */
1754 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1755 I40E_NONDMA_TO_NONDMA);
1757 /* flag cleared so helper functions don't call AQ again */
1758 hw->phy.get_link_info = false;
1760 aq_get_link_info_exit:
1765 * i40e_aq_set_phy_int_mask
1766 * @hw: pointer to the hw struct
1767 * @mask: interrupt mask to be set
1768 * @cmd_details: pointer to command details structure or NULL
1770 * Set link interrupt mask.
1772 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1774 struct i40e_asq_cmd_details *cmd_details)
1776 struct i40e_aq_desc desc;
1777 struct i40e_aqc_set_phy_int_mask *cmd =
1778 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1779 enum i40e_status_code status;
1781 i40e_fill_default_direct_cmd_desc(&desc,
1782 i40e_aqc_opc_set_phy_int_mask);
1784 cmd->event_mask = CPU_TO_LE16(mask);
1786 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1792 * i40e_aq_get_local_advt_reg
1793 * @hw: pointer to the hw struct
1794 * @advt_reg: local AN advertisement register value
1795 * @cmd_details: pointer to command details structure or NULL
1797 * Get the Local AN advertisement register value.
1799 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
1801 struct i40e_asq_cmd_details *cmd_details)
1803 struct i40e_aq_desc desc;
1804 struct i40e_aqc_an_advt_reg *resp =
1805 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1806 enum i40e_status_code status;
1808 i40e_fill_default_direct_cmd_desc(&desc,
1809 i40e_aqc_opc_get_local_advt_reg);
1811 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1813 if (status != I40E_SUCCESS)
1814 goto aq_get_local_advt_reg_exit;
1816 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1817 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1819 aq_get_local_advt_reg_exit:
1824 * i40e_aq_set_local_advt_reg
1825 * @hw: pointer to the hw struct
1826 * @advt_reg: local AN advertisement register value
1827 * @cmd_details: pointer to command details structure or NULL
1829 * Get the Local AN advertisement register value.
1831 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
1833 struct i40e_asq_cmd_details *cmd_details)
1835 struct i40e_aq_desc desc;
1836 struct i40e_aqc_an_advt_reg *cmd =
1837 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1838 enum i40e_status_code status;
1840 i40e_fill_default_direct_cmd_desc(&desc,
1841 i40e_aqc_opc_get_local_advt_reg);
1843 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
1844 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
1846 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1852 * i40e_aq_get_partner_advt
1853 * @hw: pointer to the hw struct
1854 * @advt_reg: AN partner advertisement register value
1855 * @cmd_details: pointer to command details structure or NULL
1857 * Get the link partner AN advertisement register value.
1859 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
1861 struct i40e_asq_cmd_details *cmd_details)
1863 struct i40e_aq_desc desc;
1864 struct i40e_aqc_an_advt_reg *resp =
1865 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1866 enum i40e_status_code status;
1868 i40e_fill_default_direct_cmd_desc(&desc,
1869 i40e_aqc_opc_get_partner_advt);
1871 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1873 if (status != I40E_SUCCESS)
1874 goto aq_get_partner_advt_exit;
1876 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1877 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1879 aq_get_partner_advt_exit:
1884 * i40e_aq_set_lb_modes
1885 * @hw: pointer to the hw struct
1886 * @lb_modes: loopback mode to be set
1887 * @cmd_details: pointer to command details structure or NULL
1889 * Sets loopback modes.
1891 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
1893 struct i40e_asq_cmd_details *cmd_details)
1895 struct i40e_aq_desc desc;
1896 struct i40e_aqc_set_lb_mode *cmd =
1897 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
1898 enum i40e_status_code status;
1900 i40e_fill_default_direct_cmd_desc(&desc,
1901 i40e_aqc_opc_set_lb_modes);
1903 cmd->lb_mode = CPU_TO_LE16(lb_modes);
1905 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1911 * i40e_aq_set_phy_debug
1912 * @hw: pointer to the hw struct
1913 * @cmd_flags: debug command flags
1914 * @cmd_details: pointer to command details structure or NULL
1916 * Reset the external PHY.
1918 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1919 struct i40e_asq_cmd_details *cmd_details)
1921 struct i40e_aq_desc desc;
1922 struct i40e_aqc_set_phy_debug *cmd =
1923 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1924 enum i40e_status_code status;
1926 i40e_fill_default_direct_cmd_desc(&desc,
1927 i40e_aqc_opc_set_phy_debug);
1929 cmd->command_flags = cmd_flags;
1931 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1938 * @hw: pointer to the hw struct
1939 * @vsi_ctx: pointer to a vsi context struct
1940 * @cmd_details: pointer to command details structure or NULL
1942 * Add a VSI context to the hardware.
1944 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
1945 struct i40e_vsi_context *vsi_ctx,
1946 struct i40e_asq_cmd_details *cmd_details)
1948 struct i40e_aq_desc desc;
1949 struct i40e_aqc_add_get_update_vsi *cmd =
1950 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1951 struct i40e_aqc_add_get_update_vsi_completion *resp =
1952 (struct i40e_aqc_add_get_update_vsi_completion *)
1954 enum i40e_status_code status;
1956 i40e_fill_default_direct_cmd_desc(&desc,
1957 i40e_aqc_opc_add_vsi);
1959 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
1960 cmd->connection_type = vsi_ctx->connection_type;
1961 cmd->vf_id = vsi_ctx->vf_num;
1962 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
1964 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1966 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1967 sizeof(vsi_ctx->info), cmd_details);
1969 if (status != I40E_SUCCESS)
1970 goto aq_add_vsi_exit;
1972 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
1973 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
1974 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
1975 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
1982 * i40e_aq_set_default_vsi
1983 * @hw: pointer to the hw struct
1985 * @cmd_details: pointer to command details structure or NULL
1987 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
1989 struct i40e_asq_cmd_details *cmd_details)
1991 struct i40e_aq_desc desc;
1992 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1993 (struct i40e_aqc_set_vsi_promiscuous_modes *)
1995 enum i40e_status_code status;
1997 i40e_fill_default_direct_cmd_desc(&desc,
1998 i40e_aqc_opc_set_vsi_promiscuous_modes);
2000 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2001 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2002 cmd->seid = CPU_TO_LE16(seid);
2004 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2010 * i40e_aq_set_vsi_unicast_promiscuous
2011 * @hw: pointer to the hw struct
2013 * @set: set unicast promiscuous enable/disable
2014 * @cmd_details: pointer to command details structure or NULL
2016 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2018 struct i40e_asq_cmd_details *cmd_details)
2020 struct i40e_aq_desc desc;
2021 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2022 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2023 enum i40e_status_code status;
2026 i40e_fill_default_direct_cmd_desc(&desc,
2027 i40e_aqc_opc_set_vsi_promiscuous_modes);
2030 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2032 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2034 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2036 cmd->seid = CPU_TO_LE16(seid);
2037 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2043 * i40e_aq_set_vsi_multicast_promiscuous
2044 * @hw: pointer to the hw struct
2046 * @set: set multicast promiscuous enable/disable
2047 * @cmd_details: pointer to command details structure or NULL
2049 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2050 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2052 struct i40e_aq_desc desc;
2053 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2054 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2055 enum i40e_status_code status;
2058 i40e_fill_default_direct_cmd_desc(&desc,
2059 i40e_aqc_opc_set_vsi_promiscuous_modes);
2062 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2064 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2066 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2068 cmd->seid = CPU_TO_LE16(seid);
2069 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2075 * i40e_aq_set_vsi_mc_promisc_on_vlan
2076 * @hw: pointer to the hw struct
2078 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2079 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2080 * @cmd_details: pointer to command details structure or NULL
2082 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2083 u16 seid, bool enable, u16 vid,
2084 struct i40e_asq_cmd_details *cmd_details)
2086 struct i40e_aq_desc desc;
2087 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2088 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2089 enum i40e_status_code status;
2092 i40e_fill_default_direct_cmd_desc(&desc,
2093 i40e_aqc_opc_set_vsi_promiscuous_modes);
2096 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2098 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2099 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2100 cmd->seid = CPU_TO_LE16(seid);
2101 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2103 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2109 * i40e_aq_set_vsi_uc_promisc_on_vlan
2110 * @hw: pointer to the hw struct
2112 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2113 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2114 * @cmd_details: pointer to command details structure or NULL
2116 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2117 u16 seid, bool enable, u16 vid,
2118 struct i40e_asq_cmd_details *cmd_details)
2120 struct i40e_aq_desc desc;
2121 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2122 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2123 enum i40e_status_code status;
2126 i40e_fill_default_direct_cmd_desc(&desc,
2127 i40e_aqc_opc_set_vsi_promiscuous_modes);
2130 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2132 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2133 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2134 cmd->seid = CPU_TO_LE16(seid);
2135 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2137 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2143 * i40e_aq_set_vsi_broadcast
2144 * @hw: pointer to the hw struct
2146 * @set_filter: true to set filter, false to clear filter
2147 * @cmd_details: pointer to command details structure or NULL
2149 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2151 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2152 u16 seid, bool set_filter,
2153 struct i40e_asq_cmd_details *cmd_details)
2155 struct i40e_aq_desc desc;
2156 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2157 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2158 enum i40e_status_code status;
2160 i40e_fill_default_direct_cmd_desc(&desc,
2161 i40e_aqc_opc_set_vsi_promiscuous_modes);
2164 cmd->promiscuous_flags
2165 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2167 cmd->promiscuous_flags
2168 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2170 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2171 cmd->seid = CPU_TO_LE16(seid);
2172 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2178 * i40e_get_vsi_params - get VSI configuration info
2179 * @hw: pointer to the hw struct
2180 * @vsi_ctx: pointer to a vsi context struct
2181 * @cmd_details: pointer to command details structure or NULL
2183 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2184 struct i40e_vsi_context *vsi_ctx,
2185 struct i40e_asq_cmd_details *cmd_details)
2187 struct i40e_aq_desc desc;
2188 struct i40e_aqc_add_get_update_vsi *cmd =
2189 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2190 struct i40e_aqc_add_get_update_vsi_completion *resp =
2191 (struct i40e_aqc_add_get_update_vsi_completion *)
2193 enum i40e_status_code status;
2195 UNREFERENCED_1PARAMETER(cmd_details);
2196 i40e_fill_default_direct_cmd_desc(&desc,
2197 i40e_aqc_opc_get_vsi_parameters);
2199 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2201 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2203 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2204 sizeof(vsi_ctx->info), NULL);
2206 if (status != I40E_SUCCESS)
2207 goto aq_get_vsi_params_exit;
2209 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2210 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2211 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2212 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2214 aq_get_vsi_params_exit:
2219 * i40e_aq_update_vsi_params
2220 * @hw: pointer to the hw struct
2221 * @vsi_ctx: pointer to a vsi context struct
2222 * @cmd_details: pointer to command details structure or NULL
2224 * Update a VSI context.
2226 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2227 struct i40e_vsi_context *vsi_ctx,
2228 struct i40e_asq_cmd_details *cmd_details)
2230 struct i40e_aq_desc desc;
2231 struct i40e_aqc_add_get_update_vsi *cmd =
2232 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2233 enum i40e_status_code status;
2235 i40e_fill_default_direct_cmd_desc(&desc,
2236 i40e_aqc_opc_update_vsi_parameters);
2237 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2239 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2241 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2242 sizeof(vsi_ctx->info), cmd_details);
2248 * i40e_aq_get_switch_config
2249 * @hw: pointer to the hardware structure
2250 * @buf: pointer to the result buffer
2251 * @buf_size: length of input buffer
2252 * @start_seid: seid to start for the report, 0 == beginning
2253 * @cmd_details: pointer to command details structure or NULL
2255 * Fill the buf with switch configuration returned from AdminQ command
2257 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2258 struct i40e_aqc_get_switch_config_resp *buf,
2259 u16 buf_size, u16 *start_seid,
2260 struct i40e_asq_cmd_details *cmd_details)
2262 struct i40e_aq_desc desc;
2263 struct i40e_aqc_switch_seid *scfg =
2264 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2265 enum i40e_status_code status;
2267 i40e_fill_default_direct_cmd_desc(&desc,
2268 i40e_aqc_opc_get_switch_config);
2269 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2270 if (buf_size > I40E_AQ_LARGE_BUF)
2271 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2272 scfg->seid = CPU_TO_LE16(*start_seid);
2274 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2275 *start_seid = LE16_TO_CPU(scfg->seid);
2281 * i40e_aq_get_firmware_version
2282 * @hw: pointer to the hw struct
2283 * @fw_major_version: firmware major version
2284 * @fw_minor_version: firmware minor version
2285 * @fw_build: firmware build number
2286 * @api_major_version: major queue version
2287 * @api_minor_version: minor queue version
2288 * @cmd_details: pointer to command details structure or NULL
2290 * Get the firmware version from the admin queue commands
2292 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2293 u16 *fw_major_version, u16 *fw_minor_version,
2295 u16 *api_major_version, u16 *api_minor_version,
2296 struct i40e_asq_cmd_details *cmd_details)
2298 struct i40e_aq_desc desc;
2299 struct i40e_aqc_get_version *resp =
2300 (struct i40e_aqc_get_version *)&desc.params.raw;
2301 enum i40e_status_code status;
2303 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2305 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2307 if (status == I40E_SUCCESS) {
2308 if (fw_major_version != NULL)
2309 *fw_major_version = LE16_TO_CPU(resp->fw_major);
2310 if (fw_minor_version != NULL)
2311 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2312 if (fw_build != NULL)
2313 *fw_build = LE32_TO_CPU(resp->fw_build);
2314 if (api_major_version != NULL)
2315 *api_major_version = LE16_TO_CPU(resp->api_major);
2316 if (api_minor_version != NULL)
2317 *api_minor_version = LE16_TO_CPU(resp->api_minor);
2319 /* A workaround to fix the API version in SW */
2320 if (api_major_version && api_minor_version &&
2321 fw_major_version && fw_minor_version &&
2322 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2323 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2324 (*fw_major_version > 4)))
2325 *api_minor_version = 2;
2332 * i40e_aq_send_driver_version
2333 * @hw: pointer to the hw struct
2334 * @dv: driver's major, minor version
2335 * @cmd_details: pointer to command details structure or NULL
2337 * Send the driver version to the firmware
2339 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2340 struct i40e_driver_version *dv,
2341 struct i40e_asq_cmd_details *cmd_details)
2343 struct i40e_aq_desc desc;
2344 struct i40e_aqc_driver_version *cmd =
2345 (struct i40e_aqc_driver_version *)&desc.params.raw;
2346 enum i40e_status_code status;
2350 return I40E_ERR_PARAM;
2352 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2354 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2355 cmd->driver_major_ver = dv->major_version;
2356 cmd->driver_minor_ver = dv->minor_version;
2357 cmd->driver_build_ver = dv->build_version;
2358 cmd->driver_subbuild_ver = dv->subbuild_version;
2361 while (len < sizeof(dv->driver_string) &&
2362 (dv->driver_string[len] < 0x80) &&
2363 dv->driver_string[len])
2365 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2372 * i40e_get_link_status - get status of the HW network link
2373 * @hw: pointer to the hw struct
2374 * @link_up: pointer to bool (true/false = linkup/linkdown)
2376 * Variable link_up true if link is up, false if link is down.
2377 * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2379 * Side effect: LinkStatusEvent reporting becomes enabled
2381 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2383 enum i40e_status_code status = I40E_SUCCESS;
2385 if (hw->phy.get_link_info) {
2386 status = i40e_update_link_info(hw);
2388 if (status != I40E_SUCCESS)
2389 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2393 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2399 * i40e_updatelink_status - update status of the HW network link
2400 * @hw: pointer to the hw struct
2402 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2404 struct i40e_aq_get_phy_abilities_resp abilities;
2405 enum i40e_status_code status = I40E_SUCCESS;
2407 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2411 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
2416 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2417 sizeof(hw->phy.link_info.module_type));
2423 * i40e_get_link_speed
2424 * @hw: pointer to the hw struct
2426 * Returns the link speed of the adapter.
2428 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2430 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2431 enum i40e_status_code status = I40E_SUCCESS;
2433 if (hw->phy.get_link_info) {
2434 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2436 if (status != I40E_SUCCESS)
2437 goto i40e_link_speed_exit;
2440 speed = hw->phy.link_info.link_speed;
2442 i40e_link_speed_exit:
2447 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2448 * @hw: pointer to the hw struct
2449 * @uplink_seid: the MAC or other gizmo SEID
2450 * @downlink_seid: the VSI SEID
2451 * @enabled_tc: bitmap of TCs to be enabled
2452 * @default_port: true for default port VSI, false for control port
2453 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
2454 * @veb_seid: pointer to where to put the resulting VEB SEID
2455 * @cmd_details: pointer to command details structure or NULL
2457 * This asks the FW to add a VEB between the uplink and downlink
2458 * elements. If the uplink SEID is 0, this will be a floating VEB.
2460 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2461 u16 downlink_seid, u8 enabled_tc,
2462 bool default_port, bool enable_l2_filtering,
2464 struct i40e_asq_cmd_details *cmd_details)
2466 struct i40e_aq_desc desc;
2467 struct i40e_aqc_add_veb *cmd =
2468 (struct i40e_aqc_add_veb *)&desc.params.raw;
2469 struct i40e_aqc_add_veb_completion *resp =
2470 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2471 enum i40e_status_code status;
2474 /* SEIDs need to either both be set or both be 0 for floating VEB */
2475 if (!!uplink_seid != !!downlink_seid)
2476 return I40E_ERR_PARAM;
2478 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2480 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2481 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2482 cmd->enable_tcs = enabled_tc;
2484 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2486 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2488 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2490 if (enable_l2_filtering)
2491 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
2493 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2495 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2497 if (!status && veb_seid)
2498 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2504 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2505 * @hw: pointer to the hw struct
2506 * @veb_seid: the SEID of the VEB to query
2507 * @switch_id: the uplink switch id
2508 * @floating: set to true if the VEB is floating
2509 * @statistic_index: index of the stats counter block for this VEB
2510 * @vebs_used: number of VEB's used by function
2511 * @vebs_free: total VEB's not reserved by any function
2512 * @cmd_details: pointer to command details structure or NULL
2514 * This retrieves the parameters for a particular VEB, specified by
2515 * uplink_seid, and returns them to the caller.
2517 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2518 u16 veb_seid, u16 *switch_id,
2519 bool *floating, u16 *statistic_index,
2520 u16 *vebs_used, u16 *vebs_free,
2521 struct i40e_asq_cmd_details *cmd_details)
2523 struct i40e_aq_desc desc;
2524 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2525 (struct i40e_aqc_get_veb_parameters_completion *)
2527 enum i40e_status_code status;
2530 return I40E_ERR_PARAM;
2532 i40e_fill_default_direct_cmd_desc(&desc,
2533 i40e_aqc_opc_get_veb_parameters);
2534 cmd_resp->seid = CPU_TO_LE16(veb_seid);
2536 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2541 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2542 if (statistic_index)
2543 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2545 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2547 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2549 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2550 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2561 * i40e_aq_add_macvlan
2562 * @hw: pointer to the hw struct
2563 * @seid: VSI for the mac address
2564 * @mv_list: list of macvlans to be added
2565 * @count: length of the list
2566 * @cmd_details: pointer to command details structure or NULL
2568 * Add MAC/VLAN addresses to the HW filtering
2570 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2571 struct i40e_aqc_add_macvlan_element_data *mv_list,
2572 u16 count, struct i40e_asq_cmd_details *cmd_details)
2574 struct i40e_aq_desc desc;
2575 struct i40e_aqc_macvlan *cmd =
2576 (struct i40e_aqc_macvlan *)&desc.params.raw;
2577 enum i40e_status_code status;
2580 if (count == 0 || !mv_list || !hw)
2581 return I40E_ERR_PARAM;
2583 buf_size = count * sizeof(*mv_list);
2585 /* prep the rest of the request */
2586 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2587 cmd->num_addresses = CPU_TO_LE16(count);
2588 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2592 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2593 if (buf_size > I40E_AQ_LARGE_BUF)
2594 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2596 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2603 * i40e_aq_remove_macvlan
2604 * @hw: pointer to the hw struct
2605 * @seid: VSI for the mac address
2606 * @mv_list: list of macvlans to be removed
2607 * @count: length of the list
2608 * @cmd_details: pointer to command details structure or NULL
2610 * Remove MAC/VLAN addresses from the HW filtering
2612 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2613 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2614 u16 count, struct i40e_asq_cmd_details *cmd_details)
2616 struct i40e_aq_desc desc;
2617 struct i40e_aqc_macvlan *cmd =
2618 (struct i40e_aqc_macvlan *)&desc.params.raw;
2619 enum i40e_status_code status;
2622 if (count == 0 || !mv_list || !hw)
2623 return I40E_ERR_PARAM;
2625 buf_size = count * sizeof(*mv_list);
2627 /* prep the rest of the request */
2628 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2629 cmd->num_addresses = CPU_TO_LE16(count);
2630 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2634 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2635 if (buf_size > I40E_AQ_LARGE_BUF)
2636 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2638 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2645 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
2646 * @hw: pointer to the hw struct
2647 * @seid: VSI for the vlan filters
2648 * @v_list: list of vlan filters to be added
2649 * @count: length of the list
2650 * @cmd_details: pointer to command details structure or NULL
2652 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
2653 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2654 u8 count, struct i40e_asq_cmd_details *cmd_details)
2656 struct i40e_aq_desc desc;
2657 struct i40e_aqc_macvlan *cmd =
2658 (struct i40e_aqc_macvlan *)&desc.params.raw;
2659 enum i40e_status_code status;
2662 if (count == 0 || !v_list || !hw)
2663 return I40E_ERR_PARAM;
2665 buf_size = count * sizeof(*v_list);
2667 /* prep the rest of the request */
2668 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
2669 cmd->num_addresses = CPU_TO_LE16(count);
2670 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2674 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2675 if (buf_size > I40E_AQ_LARGE_BUF)
2676 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2678 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2685 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
2686 * @hw: pointer to the hw struct
2687 * @seid: VSI for the vlan filters
2688 * @v_list: list of macvlans to be removed
2689 * @count: length of the list
2690 * @cmd_details: pointer to command details structure or NULL
2692 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
2693 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2694 u8 count, struct i40e_asq_cmd_details *cmd_details)
2696 struct i40e_aq_desc desc;
2697 struct i40e_aqc_macvlan *cmd =
2698 (struct i40e_aqc_macvlan *)&desc.params.raw;
2699 enum i40e_status_code status;
2702 if (count == 0 || !v_list || !hw)
2703 return I40E_ERR_PARAM;
2705 buf_size = count * sizeof(*v_list);
2707 /* prep the rest of the request */
2708 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
2709 cmd->num_addresses = CPU_TO_LE16(count);
2710 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2714 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2715 if (buf_size > I40E_AQ_LARGE_BUF)
2716 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2718 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2725 * i40e_aq_send_msg_to_vf
2726 * @hw: pointer to the hardware structure
2727 * @vfid: vf id to send msg
2728 * @v_opcode: opcodes for VF-PF communication
2729 * @v_retval: return error code
2730 * @msg: pointer to the msg buffer
2731 * @msglen: msg length
2732 * @cmd_details: pointer to command details
2736 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2737 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2738 struct i40e_asq_cmd_details *cmd_details)
2740 struct i40e_aq_desc desc;
2741 struct i40e_aqc_pf_vf_message *cmd =
2742 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2743 enum i40e_status_code status;
2745 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2746 cmd->id = CPU_TO_LE32(vfid);
2747 desc.cookie_high = CPU_TO_LE32(v_opcode);
2748 desc.cookie_low = CPU_TO_LE32(v_retval);
2749 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
2751 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
2753 if (msglen > I40E_AQ_LARGE_BUF)
2754 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2755 desc.datalen = CPU_TO_LE16(msglen);
2757 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2763 * i40e_aq_debug_read_register
2764 * @hw: pointer to the hw struct
2765 * @reg_addr: register address
2766 * @reg_val: register value
2767 * @cmd_details: pointer to command details structure or NULL
2769 * Read the register using the admin queue commands
2771 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
2772 u32 reg_addr, u64 *reg_val,
2773 struct i40e_asq_cmd_details *cmd_details)
2775 struct i40e_aq_desc desc;
2776 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2777 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2778 enum i40e_status_code status;
2780 if (reg_val == NULL)
2781 return I40E_ERR_PARAM;
2783 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2785 cmd_resp->address = CPU_TO_LE32(reg_addr);
2787 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2789 if (status == I40E_SUCCESS) {
2790 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
2791 (u64)LE32_TO_CPU(cmd_resp->value_low);
2798 * i40e_aq_debug_write_register
2799 * @hw: pointer to the hw struct
2800 * @reg_addr: register address
2801 * @reg_val: register value
2802 * @cmd_details: pointer to command details structure or NULL
2804 * Write to a register using the admin queue commands
2806 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
2807 u32 reg_addr, u64 reg_val,
2808 struct i40e_asq_cmd_details *cmd_details)
2810 struct i40e_aq_desc desc;
2811 struct i40e_aqc_debug_reg_read_write *cmd =
2812 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2813 enum i40e_status_code status;
2815 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2817 cmd->address = CPU_TO_LE32(reg_addr);
2818 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
2819 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
2821 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2827 * i40e_aq_get_hmc_resource_profile
2828 * @hw: pointer to the hw struct
2829 * @profile: type of profile the HMC is to be set as
2830 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2831 * @cmd_details: pointer to command details structure or NULL
2833 * query the HMC profile of the device.
2835 enum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw,
2836 enum i40e_aq_hmc_profile *profile,
2837 u8 *pe_vf_enabled_count,
2838 struct i40e_asq_cmd_details *cmd_details)
2840 struct i40e_aq_desc desc;
2841 struct i40e_aq_get_set_hmc_resource_profile *resp =
2842 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2843 enum i40e_status_code status;
2845 i40e_fill_default_direct_cmd_desc(&desc,
2846 i40e_aqc_opc_query_hmc_resource_profile);
2847 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2849 *profile = (enum i40e_aq_hmc_profile)(resp->pm_profile &
2850 I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK);
2851 *pe_vf_enabled_count = resp->pe_vf_enabled &
2852 I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK;
2858 * i40e_aq_set_hmc_resource_profile
2859 * @hw: pointer to the hw struct
2860 * @profile: type of profile the HMC is to be set as
2861 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2862 * @cmd_details: pointer to command details structure or NULL
2864 * set the HMC profile of the device.
2866 enum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2867 enum i40e_aq_hmc_profile profile,
2868 u8 pe_vf_enabled_count,
2869 struct i40e_asq_cmd_details *cmd_details)
2871 struct i40e_aq_desc desc;
2872 struct i40e_aq_get_set_hmc_resource_profile *cmd =
2873 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2874 enum i40e_status_code status;
2876 i40e_fill_default_direct_cmd_desc(&desc,
2877 i40e_aqc_opc_set_hmc_resource_profile);
2879 cmd->pm_profile = (u8)profile;
2880 cmd->pe_vf_enabled = pe_vf_enabled_count;
2882 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2888 * i40e_aq_request_resource
2889 * @hw: pointer to the hw struct
2890 * @resource: resource id
2891 * @access: access type
2892 * @sdp_number: resource number
2893 * @timeout: the maximum time in ms that the driver may hold the resource
2894 * @cmd_details: pointer to command details structure or NULL
2896 * requests common resource using the admin queue commands
2898 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
2899 enum i40e_aq_resources_ids resource,
2900 enum i40e_aq_resource_access_type access,
2901 u8 sdp_number, u64 *timeout,
2902 struct i40e_asq_cmd_details *cmd_details)
2904 struct i40e_aq_desc desc;
2905 struct i40e_aqc_request_resource *cmd_resp =
2906 (struct i40e_aqc_request_resource *)&desc.params.raw;
2907 enum i40e_status_code status;
2909 DEBUGFUNC("i40e_aq_request_resource");
2911 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2913 cmd_resp->resource_id = CPU_TO_LE16(resource);
2914 cmd_resp->access_type = CPU_TO_LE16(access);
2915 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
2917 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2918 /* The completion specifies the maximum time in ms that the driver
2919 * may hold the resource in the Timeout field.
2920 * If the resource is held by someone else, the command completes with
2921 * busy return value and the timeout field indicates the maximum time
2922 * the current owner of the resource has to free it.
2924 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2925 *timeout = LE32_TO_CPU(cmd_resp->timeout);
2931 * i40e_aq_release_resource
2932 * @hw: pointer to the hw struct
2933 * @resource: resource id
2934 * @sdp_number: resource number
2935 * @cmd_details: pointer to command details structure or NULL
2937 * release common resource using the admin queue commands
2939 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
2940 enum i40e_aq_resources_ids resource,
2942 struct i40e_asq_cmd_details *cmd_details)
2944 struct i40e_aq_desc desc;
2945 struct i40e_aqc_request_resource *cmd =
2946 (struct i40e_aqc_request_resource *)&desc.params.raw;
2947 enum i40e_status_code status;
2949 DEBUGFUNC("i40e_aq_release_resource");
2951 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2953 cmd->resource_id = CPU_TO_LE16(resource);
2954 cmd->resource_number = CPU_TO_LE32(sdp_number);
2956 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2963 * @hw: pointer to the hw struct
2964 * @module_pointer: module pointer location in words from the NVM beginning
2965 * @offset: byte offset from the module beginning
2966 * @length: length of the section to be read (in bytes from the offset)
2967 * @data: command buffer (size [bytes] = length)
2968 * @last_command: tells if this is the last command in a series
2969 * @cmd_details: pointer to command details structure or NULL
2971 * Read the NVM using the admin queue commands
2973 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2974 u32 offset, u16 length, void *data,
2976 struct i40e_asq_cmd_details *cmd_details)
2978 struct i40e_aq_desc desc;
2979 struct i40e_aqc_nvm_update *cmd =
2980 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2981 enum i40e_status_code status;
2983 DEBUGFUNC("i40e_aq_read_nvm");
2985 /* In offset the highest byte must be zeroed. */
2986 if (offset & 0xFF000000) {
2987 status = I40E_ERR_PARAM;
2988 goto i40e_aq_read_nvm_exit;
2991 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2993 /* If this is the last command in a series, set the proper flag. */
2995 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2996 cmd->module_pointer = module_pointer;
2997 cmd->offset = CPU_TO_LE32(offset);
2998 cmd->length = CPU_TO_LE16(length);
3000 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3001 if (length > I40E_AQ_LARGE_BUF)
3002 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3004 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3006 i40e_aq_read_nvm_exit:
3011 * i40e_aq_read_nvm_config - read an nvm config block
3012 * @hw: pointer to the hw struct
3013 * @cmd_flags: NVM access admin command bits
3014 * @field_id: field or feature id
3015 * @data: buffer for result
3016 * @buf_size: buffer size
3017 * @element_count: pointer to count of elements read by FW
3018 * @cmd_details: pointer to command details structure or NULL
3020 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3021 u8 cmd_flags, u32 field_id, void *data,
3022 u16 buf_size, u16 *element_count,
3023 struct i40e_asq_cmd_details *cmd_details)
3025 struct i40e_aq_desc desc;
3026 struct i40e_aqc_nvm_config_read *cmd =
3027 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3028 enum i40e_status_code status;
3030 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3031 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3032 if (buf_size > I40E_AQ_LARGE_BUF)
3033 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3035 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3036 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3037 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3038 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3040 cmd->element_id_msw = 0;
3042 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3044 if (!status && element_count)
3045 *element_count = LE16_TO_CPU(cmd->element_count);
3051 * i40e_aq_write_nvm_config - write an nvm config block
3052 * @hw: pointer to the hw struct
3053 * @cmd_flags: NVM access admin command bits
3054 * @data: buffer for result
3055 * @buf_size: buffer size
3056 * @element_count: count of elements to be written
3057 * @cmd_details: pointer to command details structure or NULL
3059 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3060 u8 cmd_flags, void *data, u16 buf_size,
3062 struct i40e_asq_cmd_details *cmd_details)
3064 struct i40e_aq_desc desc;
3065 struct i40e_aqc_nvm_config_write *cmd =
3066 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3067 enum i40e_status_code status;
3069 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3070 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3071 if (buf_size > I40E_AQ_LARGE_BUF)
3072 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3074 cmd->element_count = CPU_TO_LE16(element_count);
3075 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3076 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3082 * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3083 * @hw: pointer to the hw struct
3084 * @cmd_details: pointer to command details structure or NULL
3086 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3087 void *buff, u16 buff_size,
3088 struct i40e_asq_cmd_details *cmd_details)
3090 struct i40e_aq_desc desc;
3091 enum i40e_status_code status;
3093 UNREFERENCED_2PARAMETER(buff, buff_size);
3095 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3096 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3097 if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3098 status = I40E_ERR_NOT_IMPLEMENTED;
3105 * @hw: pointer to the hw struct
3106 * @module_pointer: module pointer location in words from the NVM beginning
3107 * @offset: offset in the module (expressed in 4 KB from module's beginning)
3108 * @length: length of the section to be erased (expressed in 4 KB)
3109 * @last_command: tells if this is the last command in a series
3110 * @cmd_details: pointer to command details structure or NULL
3112 * Erase the NVM sector using the admin queue commands
3114 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3115 u32 offset, u16 length, bool last_command,
3116 struct i40e_asq_cmd_details *cmd_details)
3118 struct i40e_aq_desc desc;
3119 struct i40e_aqc_nvm_update *cmd =
3120 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3121 enum i40e_status_code status;
3123 DEBUGFUNC("i40e_aq_erase_nvm");
3125 /* In offset the highest byte must be zeroed. */
3126 if (offset & 0xFF000000) {
3127 status = I40E_ERR_PARAM;
3128 goto i40e_aq_erase_nvm_exit;
3131 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3133 /* If this is the last command in a series, set the proper flag. */
3135 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3136 cmd->module_pointer = module_pointer;
3137 cmd->offset = CPU_TO_LE32(offset);
3138 cmd->length = CPU_TO_LE16(length);
3140 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3142 i40e_aq_erase_nvm_exit:
3146 #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
3147 #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
3148 #define I40E_DEV_FUNC_CAP_NPAR 0x03
3149 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04
3150 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
3151 #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
3152 #define I40E_DEV_FUNC_CAP_VF 0x13
3153 #define I40E_DEV_FUNC_CAP_VMDQ 0x14
3154 #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
3155 #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
3156 #define I40E_DEV_FUNC_CAP_VSI 0x17
3157 #define I40E_DEV_FUNC_CAP_DCB 0x18
3158 #define I40E_DEV_FUNC_CAP_FCOE 0x21
3159 #define I40E_DEV_FUNC_CAP_ISCSI 0x22
3160 #define I40E_DEV_FUNC_CAP_RSS 0x40
3161 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
3162 #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
3163 #define I40E_DEV_FUNC_CAP_MSIX 0x43
3164 #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
3165 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
3166 #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
3167 #define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1
3168 #define I40E_DEV_FUNC_CAP_CEM 0xF2
3169 #define I40E_DEV_FUNC_CAP_IWARP 0x51
3170 #define I40E_DEV_FUNC_CAP_LED 0x61
3171 #define I40E_DEV_FUNC_CAP_SDP 0x62
3172 #define I40E_DEV_FUNC_CAP_MDIO 0x63
3175 * i40e_parse_discover_capabilities
3176 * @hw: pointer to the hw struct
3177 * @buff: pointer to a buffer containing device/function capability records
3178 * @cap_count: number of capability records in the list
3179 * @list_type_opc: type of capabilities list to parse
3181 * Parse the device/function capabilities list.
3183 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3185 enum i40e_admin_queue_opc list_type_opc)
3187 struct i40e_aqc_list_capabilities_element_resp *cap;
3188 u32 valid_functions, num_functions;
3189 u32 number, logical_id, phys_id;
3190 struct i40e_hw_capabilities *p;
3194 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3196 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3197 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3198 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3199 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3203 for (i = 0; i < cap_count; i++, cap++) {
3204 id = LE16_TO_CPU(cap->id);
3205 number = LE32_TO_CPU(cap->number);
3206 logical_id = LE32_TO_CPU(cap->logical_id);
3207 phys_id = LE32_TO_CPU(cap->phys_id);
3210 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
3211 p->switch_mode = number;
3213 case I40E_DEV_FUNC_CAP_MGMT_MODE:
3214 p->management_mode = number;
3216 case I40E_DEV_FUNC_CAP_NPAR:
3217 p->npar_enable = number;
3219 case I40E_DEV_FUNC_CAP_OS2BMC:
3222 case I40E_DEV_FUNC_CAP_VALID_FUNC:
3223 p->valid_functions = number;
3225 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
3227 p->sr_iov_1_1 = true;
3229 case I40E_DEV_FUNC_CAP_VF:
3230 p->num_vfs = number;
3231 p->vf_base_id = logical_id;
3233 case I40E_DEV_FUNC_CAP_VMDQ:
3237 case I40E_DEV_FUNC_CAP_802_1_QBG:
3239 p->evb_802_1_qbg = true;
3241 case I40E_DEV_FUNC_CAP_802_1_QBH:
3243 p->evb_802_1_qbh = true;
3245 case I40E_DEV_FUNC_CAP_VSI:
3246 p->num_vsis = number;
3248 case I40E_DEV_FUNC_CAP_DCB:
3251 p->enabled_tcmap = logical_id;
3255 case I40E_DEV_FUNC_CAP_FCOE:
3259 case I40E_DEV_FUNC_CAP_ISCSI:
3263 case I40E_DEV_FUNC_CAP_RSS:
3265 p->rss_table_size = number;
3266 p->rss_table_entry_width = logical_id;
3268 case I40E_DEV_FUNC_CAP_RX_QUEUES:
3269 p->num_rx_qp = number;
3270 p->base_queue = phys_id;
3272 case I40E_DEV_FUNC_CAP_TX_QUEUES:
3273 p->num_tx_qp = number;
3274 p->base_queue = phys_id;
3276 case I40E_DEV_FUNC_CAP_MSIX:
3277 p->num_msix_vectors = number;
3279 case I40E_DEV_FUNC_CAP_MSIX_VF:
3280 p->num_msix_vectors_vf = number;
3282 case I40E_DEV_FUNC_CAP_MFP_MODE_1:
3284 p->mfp_mode_1 = true;
3286 case I40E_DEV_FUNC_CAP_CEM:
3290 case I40E_DEV_FUNC_CAP_IWARP:
3294 case I40E_DEV_FUNC_CAP_LED:
3295 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3296 p->led[phys_id] = true;
3298 case I40E_DEV_FUNC_CAP_SDP:
3299 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3300 p->sdp[phys_id] = true;
3302 case I40E_DEV_FUNC_CAP_MDIO:
3304 p->mdio_port_num = phys_id;
3305 p->mdio_port_mode = logical_id;
3308 case I40E_DEV_FUNC_CAP_IEEE_1588:
3310 p->ieee_1588 = true;
3312 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
3314 p->fd_filters_guaranteed = number;
3315 p->fd_filters_best_effort = logical_id;
3322 #ifdef I40E_FCOE_ENA
3323 /* Software override ensuring FCoE is disabled if npar or mfp
3324 * mode because it is not supported in these modes.
3326 if (p->npar_enable || p->mfp_mode_1)
3329 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3333 /* count the enabled ports (aka the "not disabled" ports) */
3335 for (i = 0; i < 4; i++) {
3336 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3339 /* use AQ read to get the physical register offset instead
3340 * of the port relative offset
3342 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3343 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3347 valid_functions = p->valid_functions;
3349 while (valid_functions) {
3350 if (valid_functions & 1)
3352 valid_functions >>= 1;
3355 /* partition id is 1-based, and functions are evenly spread
3356 * across the ports as partitions
3358 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3359 hw->num_partitions = num_functions / hw->num_ports;
3361 /* additional HW specific goodies that might
3362 * someday be HW version specific
3364 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3368 * i40e_aq_discover_capabilities
3369 * @hw: pointer to the hw struct
3370 * @buff: a virtual buffer to hold the capabilities
3371 * @buff_size: Size of the virtual buffer
3372 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3373 * @list_type_opc: capabilities type to discover - pass in the command opcode
3374 * @cmd_details: pointer to command details structure or NULL
3376 * Get the device capabilities descriptions from the firmware
3378 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3379 void *buff, u16 buff_size, u16 *data_size,
3380 enum i40e_admin_queue_opc list_type_opc,
3381 struct i40e_asq_cmd_details *cmd_details)
3383 struct i40e_aqc_list_capabilites *cmd;
3384 struct i40e_aq_desc desc;
3385 enum i40e_status_code status = I40E_SUCCESS;
3387 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3389 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3390 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3391 status = I40E_ERR_PARAM;
3395 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3397 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3398 if (buff_size > I40E_AQ_LARGE_BUF)
3399 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3401 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3402 *data_size = LE16_TO_CPU(desc.datalen);
3407 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3415 * i40e_aq_update_nvm
3416 * @hw: pointer to the hw struct
3417 * @module_pointer: module pointer location in words from the NVM beginning
3418 * @offset: byte offset from the module beginning
3419 * @length: length of the section to be written (in bytes from the offset)
3420 * @data: command buffer (size [bytes] = length)
3421 * @last_command: tells if this is the last command in a series
3422 * @cmd_details: pointer to command details structure or NULL
3424 * Update the NVM using the admin queue commands
3426 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3427 u32 offset, u16 length, void *data,
3429 struct i40e_asq_cmd_details *cmd_details)
3431 struct i40e_aq_desc desc;
3432 struct i40e_aqc_nvm_update *cmd =
3433 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3434 enum i40e_status_code status;
3436 DEBUGFUNC("i40e_aq_update_nvm");
3438 /* In offset the highest byte must be zeroed. */
3439 if (offset & 0xFF000000) {
3440 status = I40E_ERR_PARAM;
3441 goto i40e_aq_update_nvm_exit;
3444 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3446 /* If this is the last command in a series, set the proper flag. */
3448 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3449 cmd->module_pointer = module_pointer;
3450 cmd->offset = CPU_TO_LE32(offset);
3451 cmd->length = CPU_TO_LE16(length);
3453 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3454 if (length > I40E_AQ_LARGE_BUF)
3455 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3457 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3459 i40e_aq_update_nvm_exit:
3464 * i40e_aq_get_lldp_mib
3465 * @hw: pointer to the hw struct
3466 * @bridge_type: type of bridge requested
3467 * @mib_type: Local, Remote or both Local and Remote MIBs
3468 * @buff: pointer to a user supplied buffer to store the MIB block
3469 * @buff_size: size of the buffer (in bytes)
3470 * @local_len : length of the returned Local LLDP MIB
3471 * @remote_len: length of the returned Remote LLDP MIB
3472 * @cmd_details: pointer to command details structure or NULL
3474 * Requests the complete LLDP MIB (entire packet).
3476 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3477 u8 mib_type, void *buff, u16 buff_size,
3478 u16 *local_len, u16 *remote_len,
3479 struct i40e_asq_cmd_details *cmd_details)
3481 struct i40e_aq_desc desc;
3482 struct i40e_aqc_lldp_get_mib *cmd =
3483 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3484 struct i40e_aqc_lldp_get_mib *resp =
3485 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3486 enum i40e_status_code status;
3488 if (buff_size == 0 || !buff)
3489 return I40E_ERR_PARAM;
3491 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3492 /* Indirect Command */
3493 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3495 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3496 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3497 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3499 desc.datalen = CPU_TO_LE16(buff_size);
3501 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3502 if (buff_size > I40E_AQ_LARGE_BUF)
3503 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3505 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3507 if (local_len != NULL)
3508 *local_len = LE16_TO_CPU(resp->local_len);
3509 if (remote_len != NULL)
3510 *remote_len = LE16_TO_CPU(resp->remote_len);
3517 * i40e_aq_set_lldp_mib - Set the LLDP MIB
3518 * @hw: pointer to the hw struct
3519 * @mib_type: Local, Remote or both Local and Remote MIBs
3520 * @buff: pointer to a user supplied buffer to store the MIB block
3521 * @buff_size: size of the buffer (in bytes)
3522 * @cmd_details: pointer to command details structure or NULL
3526 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
3527 u8 mib_type, void *buff, u16 buff_size,
3528 struct i40e_asq_cmd_details *cmd_details)
3530 struct i40e_aq_desc desc;
3531 struct i40e_aqc_lldp_set_local_mib *cmd =
3532 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
3533 enum i40e_status_code status;
3535 if (buff_size == 0 || !buff)
3536 return I40E_ERR_PARAM;
3538 i40e_fill_default_direct_cmd_desc(&desc,
3539 i40e_aqc_opc_lldp_set_local_mib);
3540 /* Indirect Command */
3541 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3542 if (buff_size > I40E_AQ_LARGE_BUF)
3543 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3544 desc.datalen = CPU_TO_LE16(buff_size);
3546 cmd->type = mib_type;
3547 cmd->length = CPU_TO_LE16(buff_size);
3548 cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
3549 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
3551 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3556 * i40e_aq_cfg_lldp_mib_change_event
3557 * @hw: pointer to the hw struct
3558 * @enable_update: Enable or Disable event posting
3559 * @cmd_details: pointer to command details structure or NULL
3561 * Enable or Disable posting of an event on ARQ when LLDP MIB
3562 * associated with the interface changes
3564 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3566 struct i40e_asq_cmd_details *cmd_details)
3568 struct i40e_aq_desc desc;
3569 struct i40e_aqc_lldp_update_mib *cmd =
3570 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3571 enum i40e_status_code status;
3573 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3576 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3578 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3584 * i40e_aq_add_lldp_tlv
3585 * @hw: pointer to the hw struct
3586 * @bridge_type: type of bridge
3587 * @buff: buffer with TLV to add
3588 * @buff_size: length of the buffer
3589 * @tlv_len: length of the TLV to be added
3590 * @mib_len: length of the LLDP MIB returned in response
3591 * @cmd_details: pointer to command details structure or NULL
3593 * Add the specified TLV to LLDP Local MIB for the given bridge type,
3594 * it is responsibility of the caller to make sure that the TLV is not
3595 * already present in the LLDPDU.
3596 * In return firmware will write the complete LLDP MIB with the newly
3597 * added TLV in the response buffer.
3599 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
3600 void *buff, u16 buff_size, u16 tlv_len,
3602 struct i40e_asq_cmd_details *cmd_details)
3604 struct i40e_aq_desc desc;
3605 struct i40e_aqc_lldp_add_tlv *cmd =
3606 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3607 enum i40e_status_code status;
3609 if (buff_size == 0 || !buff || tlv_len == 0)
3610 return I40E_ERR_PARAM;
3612 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
3614 /* Indirect Command */
3615 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3616 if (buff_size > I40E_AQ_LARGE_BUF)
3617 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3618 desc.datalen = CPU_TO_LE16(buff_size);
3620 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3621 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3622 cmd->len = CPU_TO_LE16(tlv_len);
3624 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3626 if (mib_len != NULL)
3627 *mib_len = LE16_TO_CPU(desc.datalen);
3634 * i40e_aq_update_lldp_tlv
3635 * @hw: pointer to the hw struct
3636 * @bridge_type: type of bridge
3637 * @buff: buffer with TLV to update
3638 * @buff_size: size of the buffer holding original and updated TLVs
3639 * @old_len: Length of the Original TLV
3640 * @new_len: Length of the Updated TLV
3641 * @offset: offset of the updated TLV in the buff
3642 * @mib_len: length of the returned LLDP MIB
3643 * @cmd_details: pointer to command details structure or NULL
3645 * Update the specified TLV to the LLDP Local MIB for the given bridge type.
3646 * Firmware will place the complete LLDP MIB in response buffer with the
3649 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
3650 u8 bridge_type, void *buff, u16 buff_size,
3651 u16 old_len, u16 new_len, u16 offset,
3653 struct i40e_asq_cmd_details *cmd_details)
3655 struct i40e_aq_desc desc;
3656 struct i40e_aqc_lldp_update_tlv *cmd =
3657 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
3658 enum i40e_status_code status;
3660 if (buff_size == 0 || !buff || offset == 0 ||
3661 old_len == 0 || new_len == 0)
3662 return I40E_ERR_PARAM;
3664 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
3666 /* Indirect Command */
3667 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3668 if (buff_size > I40E_AQ_LARGE_BUF)
3669 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3670 desc.datalen = CPU_TO_LE16(buff_size);
3672 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3673 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3674 cmd->old_len = CPU_TO_LE16(old_len);
3675 cmd->new_offset = CPU_TO_LE16(offset);
3676 cmd->new_len = CPU_TO_LE16(new_len);
3678 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3680 if (mib_len != NULL)
3681 *mib_len = LE16_TO_CPU(desc.datalen);
3688 * i40e_aq_delete_lldp_tlv
3689 * @hw: pointer to the hw struct
3690 * @bridge_type: type of bridge
3691 * @buff: pointer to a user supplied buffer that has the TLV
3692 * @buff_size: length of the buffer
3693 * @tlv_len: length of the TLV to be deleted
3694 * @mib_len: length of the returned LLDP MIB
3695 * @cmd_details: pointer to command details structure or NULL
3697 * Delete the specified TLV from LLDP Local MIB for the given bridge type.
3698 * The firmware places the entire LLDP MIB in the response buffer.
3700 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
3701 u8 bridge_type, void *buff, u16 buff_size,
3702 u16 tlv_len, u16 *mib_len,
3703 struct i40e_asq_cmd_details *cmd_details)
3705 struct i40e_aq_desc desc;
3706 struct i40e_aqc_lldp_add_tlv *cmd =
3707 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3708 enum i40e_status_code status;
3710 if (buff_size == 0 || !buff)
3711 return I40E_ERR_PARAM;
3713 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
3715 /* Indirect Command */
3716 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3717 if (buff_size > I40E_AQ_LARGE_BUF)
3718 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3719 desc.datalen = CPU_TO_LE16(buff_size);
3720 cmd->len = CPU_TO_LE16(tlv_len);
3721 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3722 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3724 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3726 if (mib_len != NULL)
3727 *mib_len = LE16_TO_CPU(desc.datalen);
3735 * @hw: pointer to the hw struct
3736 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3737 * @cmd_details: pointer to command details structure or NULL
3739 * Stop or Shutdown the embedded LLDP Agent
3741 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3742 struct i40e_asq_cmd_details *cmd_details)
3744 struct i40e_aq_desc desc;
3745 struct i40e_aqc_lldp_stop *cmd =
3746 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3747 enum i40e_status_code status;
3749 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3752 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3754 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3760 * i40e_aq_start_lldp
3761 * @hw: pointer to the hw struct
3762 * @cmd_details: pointer to command details structure or NULL
3764 * Start the embedded LLDP Agent on all ports.
3766 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
3767 struct i40e_asq_cmd_details *cmd_details)
3769 struct i40e_aq_desc desc;
3770 struct i40e_aqc_lldp_start *cmd =
3771 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3772 enum i40e_status_code status;
3774 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3776 cmd->command = I40E_AQ_LLDP_AGENT_START;
3778 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3784 * i40e_aq_get_cee_dcb_config
3785 * @hw: pointer to the hw struct
3786 * @buff: response buffer that stores CEE operational configuration
3787 * @buff_size: size of the buffer passed
3788 * @cmd_details: pointer to command details structure or NULL
3790 * Get CEE DCBX mode operational configuration from firmware
3792 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3793 void *buff, u16 buff_size,
3794 struct i40e_asq_cmd_details *cmd_details)
3796 struct i40e_aq_desc desc;
3797 enum i40e_status_code status;
3799 if (buff_size == 0 || !buff)
3800 return I40E_ERR_PARAM;
3802 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3804 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3805 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3812 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
3813 * @hw: pointer to the hw struct
3814 * @start_agent: True if DCBx Agent needs to be Started
3815 * False if DCBx Agent needs to be Stopped
3816 * @cmd_details: pointer to command details structure or NULL
3818 * Start/Stop the embedded dcbx Agent
3820 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
3822 struct i40e_asq_cmd_details *cmd_details)
3824 struct i40e_aq_desc desc;
3825 struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
3826 (struct i40e_aqc_lldp_stop_start_specific_agent *)
3828 enum i40e_status_code status;
3830 i40e_fill_default_direct_cmd_desc(&desc,
3831 i40e_aqc_opc_lldp_stop_start_spec_agent);
3834 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
3836 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3842 * i40e_aq_add_udp_tunnel
3843 * @hw: pointer to the hw struct
3844 * @udp_port: the UDP port to add
3845 * @header_len: length of the tunneling header length in DWords
3846 * @protocol_index: protocol index type
3847 * @filter_index: pointer to filter index
3848 * @cmd_details: pointer to command details structure or NULL
3850 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3851 u16 udp_port, u8 protocol_index,
3853 struct i40e_asq_cmd_details *cmd_details)
3855 struct i40e_aq_desc desc;
3856 struct i40e_aqc_add_udp_tunnel *cmd =
3857 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3858 struct i40e_aqc_del_udp_tunnel_completion *resp =
3859 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3860 enum i40e_status_code status;
3862 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3864 cmd->udp_port = CPU_TO_LE16(udp_port);
3865 cmd->protocol_type = protocol_index;
3867 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3869 if (!status && filter_index)
3870 *filter_index = resp->index;
3876 * i40e_aq_del_udp_tunnel
3877 * @hw: pointer to the hw struct
3878 * @index: filter index
3879 * @cmd_details: pointer to command details structure or NULL
3881 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3882 struct i40e_asq_cmd_details *cmd_details)
3884 struct i40e_aq_desc desc;
3885 struct i40e_aqc_remove_udp_tunnel *cmd =
3886 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3887 enum i40e_status_code status;
3889 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3893 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3899 * i40e_aq_get_switch_resource_alloc (0x0204)
3900 * @hw: pointer to the hw struct
3901 * @num_entries: pointer to u8 to store the number of resource entries returned
3902 * @buf: pointer to a user supplied buffer. This buffer must be large enough
3903 * to store the resource information for all resource types. Each
3904 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
3905 * @count: size, in bytes, of the buffer provided
3906 * @cmd_details: pointer to command details structure or NULL
3908 * Query the resources allocated to a function.
3910 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
3912 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
3914 struct i40e_asq_cmd_details *cmd_details)
3916 struct i40e_aq_desc desc;
3917 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
3918 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
3919 enum i40e_status_code status;
3920 u16 length = count * sizeof(*buf);
3922 i40e_fill_default_direct_cmd_desc(&desc,
3923 i40e_aqc_opc_get_switch_resource_alloc);
3925 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3926 if (length > I40E_AQ_LARGE_BUF)
3927 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3929 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
3931 if (!status && num_entries)
3932 *num_entries = cmd_resp->num_entries;
3938 * i40e_aq_delete_element - Delete switch element
3939 * @hw: pointer to the hw struct
3940 * @seid: the SEID to delete from the switch
3941 * @cmd_details: pointer to command details structure or NULL
3943 * This deletes a switch element from the switch.
3945 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3946 struct i40e_asq_cmd_details *cmd_details)
3948 struct i40e_aq_desc desc;
3949 struct i40e_aqc_switch_seid *cmd =
3950 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3951 enum i40e_status_code status;
3954 return I40E_ERR_PARAM;
3956 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3958 cmd->seid = CPU_TO_LE16(seid);
3960 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3966 * i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port
3967 * @hw: pointer to the hw struct
3968 * @flags: component flags
3969 * @mac_seid: uplink seid (MAC SEID)
3970 * @vsi_seid: connected vsi seid
3971 * @ret_seid: seid of create pv component
3973 * This instantiates an i40e port virtualizer with specified flags.
3974 * Depending on specified flags the port virtualizer can act as a
3975 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
3977 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
3978 u16 mac_seid, u16 vsi_seid,
3981 struct i40e_aq_desc desc;
3982 struct i40e_aqc_add_update_pv *cmd =
3983 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
3984 struct i40e_aqc_add_update_pv_completion *resp =
3985 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
3986 enum i40e_status_code status;
3989 return I40E_ERR_PARAM;
3991 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
3992 cmd->command_flags = CPU_TO_LE16(flags);
3993 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
3994 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
3996 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
3997 if (!status && ret_seid)
3998 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4004 * i40e_aq_add_tag - Add an S/E-tag
4005 * @hw: pointer to the hw struct
4006 * @direct_to_queue: should s-tag direct flow to a specific queue
4007 * @vsi_seid: VSI SEID to use this tag
4008 * @tag: value of the tag
4009 * @queue_num: queue number, only valid is direct_to_queue is true
4010 * @tags_used: return value, number of tags in use by this PF
4011 * @tags_free: return value, number of unallocated tags
4012 * @cmd_details: pointer to command details structure or NULL
4014 * This associates an S- or E-tag to a VSI in the switch complex. It returns
4015 * the number of tags allocated by the PF, and the number of unallocated
4018 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4019 u16 vsi_seid, u16 tag, u16 queue_num,
4020 u16 *tags_used, u16 *tags_free,
4021 struct i40e_asq_cmd_details *cmd_details)
4023 struct i40e_aq_desc desc;
4024 struct i40e_aqc_add_tag *cmd =
4025 (struct i40e_aqc_add_tag *)&desc.params.raw;
4026 struct i40e_aqc_add_remove_tag_completion *resp =
4027 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4028 enum i40e_status_code status;
4031 return I40E_ERR_PARAM;
4033 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4035 cmd->seid = CPU_TO_LE16(vsi_seid);
4036 cmd->tag = CPU_TO_LE16(tag);
4037 if (direct_to_queue) {
4038 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4039 cmd->queue_number = CPU_TO_LE16(queue_num);
4042 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4045 if (tags_used != NULL)
4046 *tags_used = LE16_TO_CPU(resp->tags_used);
4047 if (tags_free != NULL)
4048 *tags_free = LE16_TO_CPU(resp->tags_free);
4055 * i40e_aq_remove_tag - Remove an S- or E-tag
4056 * @hw: pointer to the hw struct
4057 * @vsi_seid: VSI SEID this tag is associated with
4058 * @tag: value of the S-tag to delete
4059 * @tags_used: return value, number of tags in use by this PF
4060 * @tags_free: return value, number of unallocated tags
4061 * @cmd_details: pointer to command details structure or NULL
4063 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
4064 * the number of tags allocated by the PF, and the number of unallocated
4067 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4068 u16 tag, u16 *tags_used, u16 *tags_free,
4069 struct i40e_asq_cmd_details *cmd_details)
4071 struct i40e_aq_desc desc;
4072 struct i40e_aqc_remove_tag *cmd =
4073 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4074 struct i40e_aqc_add_remove_tag_completion *resp =
4075 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4076 enum i40e_status_code status;
4079 return I40E_ERR_PARAM;
4081 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4083 cmd->seid = CPU_TO_LE16(vsi_seid);
4084 cmd->tag = CPU_TO_LE16(tag);
4086 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4089 if (tags_used != NULL)
4090 *tags_used = LE16_TO_CPU(resp->tags_used);
4091 if (tags_free != NULL)
4092 *tags_free = LE16_TO_CPU(resp->tags_free);
4099 * i40e_aq_add_mcast_etag - Add a multicast E-tag
4100 * @hw: pointer to the hw struct
4101 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4102 * @etag: value of E-tag to add
4103 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4104 * @buf: address of indirect buffer
4105 * @tags_used: return value, number of E-tags in use by this port
4106 * @tags_free: return value, number of unallocated M-tags
4107 * @cmd_details: pointer to command details structure or NULL
4109 * This associates a multicast E-tag to a port virtualizer. It will return
4110 * the number of tags allocated by the PF, and the number of unallocated
4113 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4114 * num_tags_in_buf long.
4116 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4117 u16 etag, u8 num_tags_in_buf, void *buf,
4118 u16 *tags_used, u16 *tags_free,
4119 struct i40e_asq_cmd_details *cmd_details)
4121 struct i40e_aq_desc desc;
4122 struct i40e_aqc_add_remove_mcast_etag *cmd =
4123 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4124 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4125 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4126 enum i40e_status_code status;
4127 u16 length = sizeof(u16) * num_tags_in_buf;
4129 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4130 return I40E_ERR_PARAM;
4132 i40e_fill_default_direct_cmd_desc(&desc,
4133 i40e_aqc_opc_add_multicast_etag);
4135 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4136 cmd->etag = CPU_TO_LE16(etag);
4137 cmd->num_unicast_etags = num_tags_in_buf;
4139 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4140 if (length > I40E_AQ_LARGE_BUF)
4141 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4143 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4146 if (tags_used != NULL)
4147 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4148 if (tags_free != NULL)
4149 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4156 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4157 * @hw: pointer to the hw struct
4158 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4159 * @etag: value of the E-tag to remove
4160 * @tags_used: return value, number of tags in use by this port
4161 * @tags_free: return value, number of unallocated tags
4162 * @cmd_details: pointer to command details structure or NULL
4164 * This deletes an E-tag from the port virtualizer. It will return
4165 * the number of tags allocated by the port, and the number of unallocated
4168 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4169 u16 etag, u16 *tags_used, u16 *tags_free,
4170 struct i40e_asq_cmd_details *cmd_details)
4172 struct i40e_aq_desc desc;
4173 struct i40e_aqc_add_remove_mcast_etag *cmd =
4174 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4175 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4176 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4177 enum i40e_status_code status;
4181 return I40E_ERR_PARAM;
4183 i40e_fill_default_direct_cmd_desc(&desc,
4184 i40e_aqc_opc_remove_multicast_etag);
4186 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4187 cmd->etag = CPU_TO_LE16(etag);
4189 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4192 if (tags_used != NULL)
4193 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4194 if (tags_free != NULL)
4195 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4202 * i40e_aq_update_tag - Update an S/E-tag
4203 * @hw: pointer to the hw struct
4204 * @vsi_seid: VSI SEID using this S-tag
4205 * @old_tag: old tag value
4206 * @new_tag: new tag value
4207 * @tags_used: return value, number of tags in use by this PF
4208 * @tags_free: return value, number of unallocated tags
4209 * @cmd_details: pointer to command details structure or NULL
4211 * This updates the value of the tag currently attached to this VSI
4212 * in the switch complex. It will return the number of tags allocated
4213 * by the PF, and the number of unallocated tags available.
4215 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4216 u16 old_tag, u16 new_tag, u16 *tags_used,
4218 struct i40e_asq_cmd_details *cmd_details)
4220 struct i40e_aq_desc desc;
4221 struct i40e_aqc_update_tag *cmd =
4222 (struct i40e_aqc_update_tag *)&desc.params.raw;
4223 struct i40e_aqc_update_tag_completion *resp =
4224 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4225 enum i40e_status_code status;
4228 return I40E_ERR_PARAM;
4230 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4232 cmd->seid = CPU_TO_LE16(vsi_seid);
4233 cmd->old_tag = CPU_TO_LE16(old_tag);
4234 cmd->new_tag = CPU_TO_LE16(new_tag);
4236 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4239 if (tags_used != NULL)
4240 *tags_used = LE16_TO_CPU(resp->tags_used);
4241 if (tags_free != NULL)
4242 *tags_free = LE16_TO_CPU(resp->tags_free);
4249 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4250 * @hw: pointer to the hw struct
4251 * @tcmap: TC map for request/release any ignore PFC condition
4252 * @request: request or release ignore PFC condition
4253 * @tcmap_ret: return TCs for which PFC is currently ignored
4254 * @cmd_details: pointer to command details structure or NULL
4256 * This sends out request/release to ignore PFC condition for a TC.
4257 * It will return the TCs for which PFC is currently ignored.
4259 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4260 bool request, u8 *tcmap_ret,
4261 struct i40e_asq_cmd_details *cmd_details)
4263 struct i40e_aq_desc desc;
4264 struct i40e_aqc_pfc_ignore *cmd_resp =
4265 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4266 enum i40e_status_code status;
4268 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4271 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4273 cmd_resp->tc_bitmap = tcmap;
4275 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4278 if (tcmap_ret != NULL)
4279 *tcmap_ret = cmd_resp->tc_bitmap;
4286 * i40e_aq_dcb_updated - DCB Updated Command
4287 * @hw: pointer to the hw struct
4288 * @cmd_details: pointer to command details structure or NULL
4290 * When LLDP is handled in PF this command is used by the PF
4291 * to notify EMP that a DCB setting is modified.
4292 * When LLDP is handled in EMP this command is used by the PF
4293 * to notify EMP whenever one of the following parameters get
4295 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4296 * - PCIRTT in PRTDCB_GENC.PCIRTT
4297 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4298 * EMP will return when the shared RPB settings have been
4299 * recomputed and modified. The retval field in the descriptor
4300 * will be set to 0 when RPB is modified.
4302 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4303 struct i40e_asq_cmd_details *cmd_details)
4305 struct i40e_aq_desc desc;
4306 enum i40e_status_code status;
4308 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4310 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4316 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4317 * @hw: pointer to the hw struct
4318 * @seid: defines the SEID of the switch for which the stats are requested
4319 * @vlan_id: the VLAN ID for which the statistics are requested
4320 * @stat_index: index of the statistics counters block assigned to this VLAN
4321 * @cmd_details: pointer to command details structure or NULL
4323 * XL710 supports 128 smonVlanStats counters.This command is used to
4324 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4327 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4328 u16 vlan_id, u16 *stat_index,
4329 struct i40e_asq_cmd_details *cmd_details)
4331 struct i40e_aq_desc desc;
4332 struct i40e_aqc_add_remove_statistics *cmd_resp =
4333 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4334 enum i40e_status_code status;
4336 if ((seid == 0) || (stat_index == NULL))
4337 return I40E_ERR_PARAM;
4339 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4341 cmd_resp->seid = CPU_TO_LE16(seid);
4342 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4344 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4346 if (!status && stat_index)
4347 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4353 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4354 * @hw: pointer to the hw struct
4355 * @seid: defines the SEID of the switch for which the stats are requested
4356 * @vlan_id: the VLAN ID for which the statistics are requested
4357 * @stat_index: index of the statistics counters block assigned to this VLAN
4358 * @cmd_details: pointer to command details structure or NULL
4360 * XL710 supports 128 smonVlanStats counters.This command is used to
4361 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4364 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4365 u16 vlan_id, u16 stat_index,
4366 struct i40e_asq_cmd_details *cmd_details)
4368 struct i40e_aq_desc desc;
4369 struct i40e_aqc_add_remove_statistics *cmd =
4370 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4371 enum i40e_status_code status;
4374 return I40E_ERR_PARAM;
4376 i40e_fill_default_direct_cmd_desc(&desc,
4377 i40e_aqc_opc_remove_statistics);
4379 cmd->seid = CPU_TO_LE16(seid);
4380 cmd->vlan = CPU_TO_LE16(vlan_id);
4381 cmd->stat_index = CPU_TO_LE16(stat_index);
4383 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4389 * i40e_aq_set_port_parameters - set physical port parameters.
4390 * @hw: pointer to the hw struct
4391 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4392 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4393 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4394 * @double_vlan: if set double VLAN is enabled
4395 * @cmd_details: pointer to command details structure or NULL
4397 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4398 u16 bad_frame_vsi, bool save_bad_pac,
4399 bool pad_short_pac, bool double_vlan,
4400 struct i40e_asq_cmd_details *cmd_details)
4402 struct i40e_aqc_set_port_parameters *cmd;
4403 enum i40e_status_code status;
4404 struct i40e_aq_desc desc;
4405 u16 command_flags = 0;
4407 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4409 i40e_fill_default_direct_cmd_desc(&desc,
4410 i40e_aqc_opc_set_port_parameters);
4412 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4414 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4416 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4418 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4419 cmd->command_flags = CPU_TO_LE16(command_flags);
4421 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4427 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
4428 * @hw: pointer to the hw struct
4429 * @seid: seid for the physical port/switching component/vsi
4430 * @buff: Indirect buffer to hold data parameters and response
4431 * @buff_size: Indirect buffer size
4432 * @opcode: Tx scheduler AQ command opcode
4433 * @cmd_details: pointer to command details structure or NULL
4435 * Generic command handler for Tx scheduler AQ commands
4437 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
4438 void *buff, u16 buff_size,
4439 enum i40e_admin_queue_opc opcode,
4440 struct i40e_asq_cmd_details *cmd_details)
4442 struct i40e_aq_desc desc;
4443 struct i40e_aqc_tx_sched_ind *cmd =
4444 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4445 enum i40e_status_code status;
4446 bool cmd_param_flag = false;
4449 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
4450 case i40e_aqc_opc_configure_vsi_tc_bw:
4451 case i40e_aqc_opc_enable_switching_comp_ets:
4452 case i40e_aqc_opc_modify_switching_comp_ets:
4453 case i40e_aqc_opc_disable_switching_comp_ets:
4454 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
4455 case i40e_aqc_opc_configure_switching_comp_bw_config:
4456 cmd_param_flag = true;
4458 case i40e_aqc_opc_query_vsi_bw_config:
4459 case i40e_aqc_opc_query_vsi_ets_sla_config:
4460 case i40e_aqc_opc_query_switching_comp_ets_config:
4461 case i40e_aqc_opc_query_port_ets_config:
4462 case i40e_aqc_opc_query_switching_comp_bw_config:
4463 cmd_param_flag = false;
4466 return I40E_ERR_PARAM;
4469 i40e_fill_default_direct_cmd_desc(&desc, opcode);
4471 /* Indirect command */
4472 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4474 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4475 if (buff_size > I40E_AQ_LARGE_BUF)
4476 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4478 desc.datalen = CPU_TO_LE16(buff_size);
4480 cmd->vsi_seid = CPU_TO_LE16(seid);
4482 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4488 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
4489 * @hw: pointer to the hw struct
4491 * @credit: BW limit credits (0 = disabled)
4492 * @max_credit: Max BW limit credits
4493 * @cmd_details: pointer to command details structure or NULL
4495 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
4496 u16 seid, u16 credit, u8 max_credit,
4497 struct i40e_asq_cmd_details *cmd_details)
4499 struct i40e_aq_desc desc;
4500 struct i40e_aqc_configure_vsi_bw_limit *cmd =
4501 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
4502 enum i40e_status_code status;
4504 i40e_fill_default_direct_cmd_desc(&desc,
4505 i40e_aqc_opc_configure_vsi_bw_limit);
4507 cmd->vsi_seid = CPU_TO_LE16(seid);
4508 cmd->credit = CPU_TO_LE16(credit);
4509 cmd->max_credit = max_credit;
4511 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4517 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
4518 * @hw: pointer to the hw struct
4519 * @seid: switching component seid
4520 * @credit: BW limit credits (0 = disabled)
4521 * @max_bw: Max BW limit credits
4522 * @cmd_details: pointer to command details structure or NULL
4524 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
4525 u16 seid, u16 credit, u8 max_bw,
4526 struct i40e_asq_cmd_details *cmd_details)
4528 struct i40e_aq_desc desc;
4529 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
4530 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
4531 enum i40e_status_code status;
4533 i40e_fill_default_direct_cmd_desc(&desc,
4534 i40e_aqc_opc_configure_switching_comp_bw_limit);
4536 cmd->seid = CPU_TO_LE16(seid);
4537 cmd->credit = CPU_TO_LE16(credit);
4538 cmd->max_bw = max_bw;
4540 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4546 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
4547 * @hw: pointer to the hw struct
4549 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4550 * @cmd_details: pointer to command details structure or NULL
4552 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
4554 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
4555 struct i40e_asq_cmd_details *cmd_details)
4557 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4558 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
4563 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
4564 * @hw: pointer to the hw struct
4566 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
4567 * @cmd_details: pointer to command details structure or NULL
4569 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
4571 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
4572 struct i40e_asq_cmd_details *cmd_details)
4574 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4575 i40e_aqc_opc_configure_vsi_tc_bw,
4580 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
4581 * @hw: pointer to the hw struct
4582 * @seid: seid of the switching component connected to Physical Port
4583 * @ets_data: Buffer holding ETS parameters
4584 * @cmd_details: pointer to command details structure or NULL
4586 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
4588 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
4589 enum i40e_admin_queue_opc opcode,
4590 struct i40e_asq_cmd_details *cmd_details)
4592 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
4593 sizeof(*ets_data), opcode, cmd_details);
4597 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
4598 * @hw: pointer to the hw struct
4599 * @seid: seid of the switching component
4600 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
4601 * @cmd_details: pointer to command details structure or NULL
4603 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
4605 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
4606 struct i40e_asq_cmd_details *cmd_details)
4608 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4609 i40e_aqc_opc_configure_switching_comp_bw_config,
4614 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
4615 * @hw: pointer to the hw struct
4616 * @seid: seid of the switching component
4617 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4618 * @cmd_details: pointer to command details structure or NULL
4620 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
4621 struct i40e_hw *hw, u16 seid,
4622 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
4623 struct i40e_asq_cmd_details *cmd_details)
4625 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4626 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
4631 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
4632 * @hw: pointer to the hw struct
4633 * @seid: seid of the VSI
4634 * @bw_data: Buffer to hold VSI BW configuration
4635 * @cmd_details: pointer to command details structure or NULL
4637 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
4639 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
4640 struct i40e_asq_cmd_details *cmd_details)
4642 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4643 i40e_aqc_opc_query_vsi_bw_config,
4648 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
4649 * @hw: pointer to the hw struct
4650 * @seid: seid of the VSI
4651 * @bw_data: Buffer to hold VSI BW configuration per TC
4652 * @cmd_details: pointer to command details structure or NULL
4654 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
4656 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
4657 struct i40e_asq_cmd_details *cmd_details)
4659 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4660 i40e_aqc_opc_query_vsi_ets_sla_config,
4665 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
4666 * @hw: pointer to the hw struct
4667 * @seid: seid of the switching component
4668 * @bw_data: Buffer to hold switching component's per TC BW config
4669 * @cmd_details: pointer to command details structure or NULL
4671 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
4673 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
4674 struct i40e_asq_cmd_details *cmd_details)
4676 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4677 i40e_aqc_opc_query_switching_comp_ets_config,
4682 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
4683 * @hw: pointer to the hw struct
4684 * @seid: seid of the VSI or switching component connected to Physical Port
4685 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
4686 * @cmd_details: pointer to command details structure or NULL
4688 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
4690 struct i40e_aqc_query_port_ets_config_resp *bw_data,
4691 struct i40e_asq_cmd_details *cmd_details)
4693 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4694 i40e_aqc_opc_query_port_ets_config,
4699 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
4700 * @hw: pointer to the hw struct
4701 * @seid: seid of the switching component
4702 * @bw_data: Buffer to hold switching component's BW configuration
4703 * @cmd_details: pointer to command details structure or NULL
4705 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
4707 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
4708 struct i40e_asq_cmd_details *cmd_details)
4710 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4711 i40e_aqc_opc_query_switching_comp_bw_config,
4716 * i40e_validate_filter_settings
4717 * @hw: pointer to the hardware structure
4718 * @settings: Filter control settings
4720 * Check and validate the filter control settings passed.
4721 * The function checks for the valid filter/context sizes being
4722 * passed for FCoE and PE.
4724 * Returns I40E_SUCCESS if the values passed are valid and within
4725 * range else returns an error.
4727 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
4728 struct i40e_filter_control_settings *settings)
4730 u32 fcoe_cntx_size, fcoe_filt_size;
4731 u32 pe_cntx_size, pe_filt_size;
4736 /* Validate FCoE settings passed */
4737 switch (settings->fcoe_filt_num) {
4738 case I40E_HASH_FILTER_SIZE_1K:
4739 case I40E_HASH_FILTER_SIZE_2K:
4740 case I40E_HASH_FILTER_SIZE_4K:
4741 case I40E_HASH_FILTER_SIZE_8K:
4742 case I40E_HASH_FILTER_SIZE_16K:
4743 case I40E_HASH_FILTER_SIZE_32K:
4744 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4745 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
4748 return I40E_ERR_PARAM;
4751 switch (settings->fcoe_cntx_num) {
4752 case I40E_DMA_CNTX_SIZE_512:
4753 case I40E_DMA_CNTX_SIZE_1K:
4754 case I40E_DMA_CNTX_SIZE_2K:
4755 case I40E_DMA_CNTX_SIZE_4K:
4756 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4757 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
4760 return I40E_ERR_PARAM;
4763 /* Validate PE settings passed */
4764 switch (settings->pe_filt_num) {
4765 case I40E_HASH_FILTER_SIZE_1K:
4766 case I40E_HASH_FILTER_SIZE_2K:
4767 case I40E_HASH_FILTER_SIZE_4K:
4768 case I40E_HASH_FILTER_SIZE_8K:
4769 case I40E_HASH_FILTER_SIZE_16K:
4770 case I40E_HASH_FILTER_SIZE_32K:
4771 case I40E_HASH_FILTER_SIZE_64K:
4772 case I40E_HASH_FILTER_SIZE_128K:
4773 case I40E_HASH_FILTER_SIZE_256K:
4774 case I40E_HASH_FILTER_SIZE_512K:
4775 case I40E_HASH_FILTER_SIZE_1M:
4776 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4777 pe_filt_size <<= (u32)settings->pe_filt_num;
4780 return I40E_ERR_PARAM;
4783 switch (settings->pe_cntx_num) {
4784 case I40E_DMA_CNTX_SIZE_512:
4785 case I40E_DMA_CNTX_SIZE_1K:
4786 case I40E_DMA_CNTX_SIZE_2K:
4787 case I40E_DMA_CNTX_SIZE_4K:
4788 case I40E_DMA_CNTX_SIZE_8K:
4789 case I40E_DMA_CNTX_SIZE_16K:
4790 case I40E_DMA_CNTX_SIZE_32K:
4791 case I40E_DMA_CNTX_SIZE_64K:
4792 case I40E_DMA_CNTX_SIZE_128K:
4793 case I40E_DMA_CNTX_SIZE_256K:
4794 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4795 pe_cntx_size <<= (u32)settings->pe_cntx_num;
4798 return I40E_ERR_PARAM;
4801 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
4802 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
4803 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
4804 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
4805 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
4806 return I40E_ERR_INVALID_SIZE;
4808 return I40E_SUCCESS;
4812 * i40e_set_filter_control
4813 * @hw: pointer to the hardware structure
4814 * @settings: Filter control settings
4816 * Set the Queue Filters for PE/FCoE and enable filters required
4817 * for a single PF. It is expected that these settings are programmed
4818 * at the driver initialization time.
4820 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
4821 struct i40e_filter_control_settings *settings)
4823 enum i40e_status_code ret = I40E_SUCCESS;
4824 u32 hash_lut_size = 0;
4828 return I40E_ERR_PARAM;
4830 /* Validate the input settings */
4831 ret = i40e_validate_filter_settings(hw, settings);
4835 /* Read the PF Queue Filter control register */
4836 val = rd32(hw, I40E_PFQF_CTL_0);
4838 /* Program required PE hash buckets for the PF */
4839 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
4840 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
4841 I40E_PFQF_CTL_0_PEHSIZE_MASK;
4842 /* Program required PE contexts for the PF */
4843 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
4844 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
4845 I40E_PFQF_CTL_0_PEDSIZE_MASK;
4847 /* Program required FCoE hash buckets for the PF */
4848 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4849 val |= ((u32)settings->fcoe_filt_num <<
4850 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
4851 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4852 /* Program required FCoE DDP contexts for the PF */
4853 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4854 val |= ((u32)settings->fcoe_cntx_num <<
4855 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
4856 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4858 /* Program Hash LUT size for the PF */
4859 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4860 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
4862 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
4863 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4865 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
4866 if (settings->enable_fdir)
4867 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
4868 if (settings->enable_ethtype)
4869 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
4870 if (settings->enable_macvlan)
4871 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
4873 wr32(hw, I40E_PFQF_CTL_0, val);
4875 return I40E_SUCCESS;
4879 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
4880 * @hw: pointer to the hw struct
4881 * @mac_addr: MAC address to use in the filter
4882 * @ethtype: Ethertype to use in the filter
4883 * @flags: Flags that needs to be applied to the filter
4884 * @vsi_seid: seid of the control VSI
4885 * @queue: VSI queue number to send the packet to
4886 * @is_add: Add control packet filter if True else remove
4887 * @stats: Structure to hold information on control filter counts
4888 * @cmd_details: pointer to command details structure or NULL
4890 * This command will Add or Remove control packet filter for a control VSI.
4891 * In return it will update the total number of perfect filter count in
4894 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
4895 u8 *mac_addr, u16 ethtype, u16 flags,
4896 u16 vsi_seid, u16 queue, bool is_add,
4897 struct i40e_control_filter_stats *stats,
4898 struct i40e_asq_cmd_details *cmd_details)
4900 struct i40e_aq_desc desc;
4901 struct i40e_aqc_add_remove_control_packet_filter *cmd =
4902 (struct i40e_aqc_add_remove_control_packet_filter *)
4904 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
4905 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
4907 enum i40e_status_code status;
4910 return I40E_ERR_PARAM;
4913 i40e_fill_default_direct_cmd_desc(&desc,
4914 i40e_aqc_opc_add_control_packet_filter);
4915 cmd->queue = CPU_TO_LE16(queue);
4917 i40e_fill_default_direct_cmd_desc(&desc,
4918 i40e_aqc_opc_remove_control_packet_filter);
4922 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
4923 I40E_NONDMA_TO_NONDMA);
4925 cmd->etype = CPU_TO_LE16(ethtype);
4926 cmd->flags = CPU_TO_LE16(flags);
4927 cmd->seid = CPU_TO_LE16(vsi_seid);
4929 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4931 if (!status && stats) {
4932 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
4933 stats->etype_used = LE16_TO_CPU(resp->etype_used);
4934 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
4935 stats->etype_free = LE16_TO_CPU(resp->etype_free);
4942 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
4943 * @hw: pointer to the hw struct
4944 * @seid: VSI seid to add ethertype filter from
4946 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
4947 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
4950 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
4951 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
4952 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
4953 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
4954 enum i40e_status_code status;
4956 status = i40e_aq_add_rem_control_packet_filter(hw, 0, ethtype, flag,
4957 seid, 0, true, NULL,
4960 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
4964 * i40e_aq_add_cloud_filters
4965 * @hw: pointer to the hardware structure
4966 * @seid: VSI seid to add cloud filters from
4967 * @filters: Buffer which contains the filters to be added
4968 * @filter_count: number of filters contained in the buffer
4970 * Set the cloud filters for a given VSI. The contents of the
4971 * i40e_aqc_add_remove_cloud_filters_element_data are filled
4972 * in by the caller of the function.
4975 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
4977 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
4980 struct i40e_aq_desc desc;
4981 struct i40e_aqc_add_remove_cloud_filters *cmd =
4982 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
4984 enum i40e_status_code status;
4986 i40e_fill_default_direct_cmd_desc(&desc,
4987 i40e_aqc_opc_add_cloud_filters);
4989 buff_len = filter_count * sizeof(*filters);
4990 desc.datalen = CPU_TO_LE16(buff_len);
4991 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4992 cmd->num_filters = filter_count;
4993 cmd->seid = CPU_TO_LE16(seid);
4995 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5001 * i40e_aq_remove_cloud_filters
5002 * @hw: pointer to the hardware structure
5003 * @seid: VSI seid to remove cloud filters from
5004 * @filters: Buffer which contains the filters to be removed
5005 * @filter_count: number of filters contained in the buffer
5007 * Remove the cloud filters for a given VSI. The contents of the
5008 * i40e_aqc_add_remove_cloud_filters_element_data are filled
5009 * in by the caller of the function.
5012 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5014 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5017 struct i40e_aq_desc desc;
5018 struct i40e_aqc_add_remove_cloud_filters *cmd =
5019 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5020 enum i40e_status_code status;
5023 i40e_fill_default_direct_cmd_desc(&desc,
5024 i40e_aqc_opc_remove_cloud_filters);
5026 buff_len = filter_count * sizeof(*filters);
5027 desc.datalen = CPU_TO_LE16(buff_len);
5028 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5029 cmd->num_filters = filter_count;
5030 cmd->seid = CPU_TO_LE16(seid);
5032 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5038 * i40e_aq_alternate_write
5039 * @hw: pointer to the hardware structure
5040 * @reg_addr0: address of first dword to be read
5041 * @reg_val0: value to be written under 'reg_addr0'
5042 * @reg_addr1: address of second dword to be read
5043 * @reg_val1: value to be written under 'reg_addr1'
5045 * Write one or two dwords to alternate structure. Fields are indicated
5046 * by 'reg_addr0' and 'reg_addr1' register numbers.
5049 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5050 u32 reg_addr0, u32 reg_val0,
5051 u32 reg_addr1, u32 reg_val1)
5053 struct i40e_aq_desc desc;
5054 struct i40e_aqc_alternate_write *cmd_resp =
5055 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5056 enum i40e_status_code status;
5058 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5059 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5060 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5061 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5062 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5064 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5070 * i40e_aq_alternate_write_indirect
5071 * @hw: pointer to the hardware structure
5072 * @addr: address of a first register to be modified
5073 * @dw_count: number of alternate structure fields to write
5074 * @buffer: pointer to the command buffer
5076 * Write 'dw_count' dwords from 'buffer' to alternate structure
5077 * starting at 'addr'.
5080 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5081 u32 addr, u32 dw_count, void *buffer)
5083 struct i40e_aq_desc desc;
5084 struct i40e_aqc_alternate_ind_write *cmd_resp =
5085 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5086 enum i40e_status_code status;
5089 return I40E_ERR_PARAM;
5091 /* Indirect command */
5092 i40e_fill_default_direct_cmd_desc(&desc,
5093 i40e_aqc_opc_alternate_write_indirect);
5095 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5096 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5097 if (dw_count > (I40E_AQ_LARGE_BUF/4))
5098 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5100 cmd_resp->address = CPU_TO_LE32(addr);
5101 cmd_resp->length = CPU_TO_LE32(dw_count);
5102 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_WORD((u64)buffer));
5103 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
5105 status = i40e_asq_send_command(hw, &desc, buffer,
5106 I40E_LO_DWORD(4*dw_count), NULL);
5112 * i40e_aq_alternate_read
5113 * @hw: pointer to the hardware structure
5114 * @reg_addr0: address of first dword to be read
5115 * @reg_val0: pointer for data read from 'reg_addr0'
5116 * @reg_addr1: address of second dword to be read
5117 * @reg_val1: pointer for data read from 'reg_addr1'
5119 * Read one or two dwords from alternate structure. Fields are indicated
5120 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5121 * is not passed then only register at 'reg_addr0' is read.
5124 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5125 u32 reg_addr0, u32 *reg_val0,
5126 u32 reg_addr1, u32 *reg_val1)
5128 struct i40e_aq_desc desc;
5129 struct i40e_aqc_alternate_write *cmd_resp =
5130 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5131 enum i40e_status_code status;
5133 if (reg_val0 == NULL)
5134 return I40E_ERR_PARAM;
5136 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5137 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5138 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5140 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5142 if (status == I40E_SUCCESS) {
5143 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5145 if (reg_val1 != NULL)
5146 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5153 * i40e_aq_alternate_read_indirect
5154 * @hw: pointer to the hardware structure
5155 * @addr: address of the alternate structure field
5156 * @dw_count: number of alternate structure fields to read
5157 * @buffer: pointer to the command buffer
5159 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5160 * place them in 'buffer'. The buffer should be allocated by caller.
5163 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5164 u32 addr, u32 dw_count, void *buffer)
5166 struct i40e_aq_desc desc;
5167 struct i40e_aqc_alternate_ind_write *cmd_resp =
5168 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5169 enum i40e_status_code status;
5172 return I40E_ERR_PARAM;
5174 /* Indirect command */
5175 i40e_fill_default_direct_cmd_desc(&desc,
5176 i40e_aqc_opc_alternate_read_indirect);
5178 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5179 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5180 if (dw_count > (I40E_AQ_LARGE_BUF/4))
5181 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5183 cmd_resp->address = CPU_TO_LE32(addr);
5184 cmd_resp->length = CPU_TO_LE32(dw_count);
5185 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_DWORD((u64)buffer));
5186 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
5188 status = i40e_asq_send_command(hw, &desc, buffer,
5189 I40E_LO_DWORD(4*dw_count), NULL);
5195 * i40e_aq_alternate_clear
5196 * @hw: pointer to the HW structure.
5198 * Clear the alternate structures of the port from which the function
5202 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5204 struct i40e_aq_desc desc;
5205 enum i40e_status_code status;
5207 i40e_fill_default_direct_cmd_desc(&desc,
5208 i40e_aqc_opc_alternate_clear_port);
5210 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5216 * i40e_aq_alternate_write_done
5217 * @hw: pointer to the HW structure.
5218 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
5219 * @reset_needed: indicates the SW should trigger GLOBAL reset
5221 * Indicates to the FW that alternate structures have been changed.
5224 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
5225 u8 bios_mode, bool *reset_needed)
5227 struct i40e_aq_desc desc;
5228 struct i40e_aqc_alternate_write_done *cmd =
5229 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5230 enum i40e_status_code status;
5232 if (reset_needed == NULL)
5233 return I40E_ERR_PARAM;
5235 i40e_fill_default_direct_cmd_desc(&desc,
5236 i40e_aqc_opc_alternate_write_done);
5238 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
5240 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5241 if (!status && reset_needed)
5242 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
5243 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
5249 * i40e_aq_set_oem_mode
5250 * @hw: pointer to the HW structure.
5251 * @oem_mode: the OEM mode to be used
5253 * Sets the device to a specific operating mode. Currently the only supported
5254 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
5257 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
5260 struct i40e_aq_desc desc;
5261 struct i40e_aqc_alternate_write_done *cmd =
5262 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5263 enum i40e_status_code status;
5265 i40e_fill_default_direct_cmd_desc(&desc,
5266 i40e_aqc_opc_alternate_set_mode);
5268 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
5270 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5276 * i40e_aq_resume_port_tx
5277 * @hw: pointer to the hardware structure
5278 * @cmd_details: pointer to command details structure or NULL
5280 * Resume port's Tx traffic
5282 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
5283 struct i40e_asq_cmd_details *cmd_details)
5285 struct i40e_aq_desc desc;
5286 enum i40e_status_code status;
5288 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
5290 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5296 * i40e_set_pci_config_data - store PCI bus info
5297 * @hw: pointer to hardware structure
5298 * @link_status: the link status word from PCI config space
5300 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
5302 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
5304 hw->bus.type = i40e_bus_type_pci_express;
5306 switch (link_status & I40E_PCI_LINK_WIDTH) {
5307 case I40E_PCI_LINK_WIDTH_1:
5308 hw->bus.width = i40e_bus_width_pcie_x1;
5310 case I40E_PCI_LINK_WIDTH_2:
5311 hw->bus.width = i40e_bus_width_pcie_x2;
5313 case I40E_PCI_LINK_WIDTH_4:
5314 hw->bus.width = i40e_bus_width_pcie_x4;
5316 case I40E_PCI_LINK_WIDTH_8:
5317 hw->bus.width = i40e_bus_width_pcie_x8;
5320 hw->bus.width = i40e_bus_width_unknown;
5324 switch (link_status & I40E_PCI_LINK_SPEED) {
5325 case I40E_PCI_LINK_SPEED_2500:
5326 hw->bus.speed = i40e_bus_speed_2500;
5328 case I40E_PCI_LINK_SPEED_5000:
5329 hw->bus.speed = i40e_bus_speed_5000;
5331 case I40E_PCI_LINK_SPEED_8000:
5332 hw->bus.speed = i40e_bus_speed_8000;
5335 hw->bus.speed = i40e_bus_speed_unknown;
5341 * i40e_aq_debug_dump
5342 * @hw: pointer to the hardware structure
5343 * @cluster_id: specific cluster to dump
5344 * @table_id: table id within cluster
5345 * @start_index: index of line in the block to read
5346 * @buff_size: dump buffer size
5347 * @buff: dump buffer
5348 * @ret_buff_size: actual buffer size returned
5349 * @ret_next_table: next block to read
5350 * @ret_next_index: next index to read
5352 * Dump internal FW/HW data for debug purposes.
5355 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
5356 u8 table_id, u32 start_index, u16 buff_size,
5357 void *buff, u16 *ret_buff_size,
5358 u8 *ret_next_table, u32 *ret_next_index,
5359 struct i40e_asq_cmd_details *cmd_details)
5361 struct i40e_aq_desc desc;
5362 struct i40e_aqc_debug_dump_internals *cmd =
5363 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5364 struct i40e_aqc_debug_dump_internals *resp =
5365 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5366 enum i40e_status_code status;
5368 if (buff_size == 0 || !buff)
5369 return I40E_ERR_PARAM;
5371 i40e_fill_default_direct_cmd_desc(&desc,
5372 i40e_aqc_opc_debug_dump_internals);
5373 /* Indirect Command */
5374 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5375 if (buff_size > I40E_AQ_LARGE_BUF)
5376 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5378 cmd->cluster_id = cluster_id;
5379 cmd->table_id = table_id;
5380 cmd->idx = CPU_TO_LE32(start_index);
5382 desc.datalen = CPU_TO_LE16(buff_size);
5384 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5386 if (ret_buff_size != NULL)
5387 *ret_buff_size = LE16_TO_CPU(desc.datalen);
5388 if (ret_next_table != NULL)
5389 *ret_next_table = resp->table_id;
5390 if (ret_next_index != NULL)
5391 *ret_next_index = LE32_TO_CPU(resp->idx);
5398 * i40e_read_bw_from_alt_ram
5399 * @hw: pointer to the hardware structure
5400 * @max_bw: pointer for max_bw read
5401 * @min_bw: pointer for min_bw read
5402 * @min_valid: pointer for bool that is true if min_bw is a valid value
5403 * @max_valid: pointer for bool that is true if max_bw is a valid value
5405 * Read bw from the alternate ram for the given pf
5407 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
5408 u32 *max_bw, u32 *min_bw,
5409 bool *min_valid, bool *max_valid)
5411 enum i40e_status_code status;
5412 u32 max_bw_addr, min_bw_addr;
5414 /* Calculate the address of the min/max bw registers */
5415 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5416 I40E_ALT_STRUCT_MAX_BW_OFFSET +
5417 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
5418 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5419 I40E_ALT_STRUCT_MIN_BW_OFFSET +
5420 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
5422 /* Read the bandwidths from alt ram */
5423 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
5424 min_bw_addr, min_bw);
5426 if (*min_bw & I40E_ALT_BW_VALID_MASK)
5431 if (*max_bw & I40E_ALT_BW_VALID_MASK)
5440 * i40e_aq_configure_partition_bw
5441 * @hw: pointer to the hardware structure
5442 * @bw_data: Buffer holding valid pfs and bw limits
5443 * @cmd_details: pointer to command details
5445 * Configure partitions guaranteed/max bw
5447 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
5448 struct i40e_aqc_configure_partition_bw_data *bw_data,
5449 struct i40e_asq_cmd_details *cmd_details)
5451 enum i40e_status_code status;
5452 struct i40e_aq_desc desc;
5453 u16 bwd_size = sizeof(*bw_data);
5455 i40e_fill_default_direct_cmd_desc(&desc,
5456 i40e_aqc_opc_configure_partition_bw);
5458 /* Indirect command */
5459 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5460 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5462 if (bwd_size > I40E_AQ_LARGE_BUF)
5463 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5465 desc.datalen = CPU_TO_LE16(bwd_size);
5467 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
5471 #endif /* PF_DRIVER */
5475 * i40e_aq_send_msg_to_pf
5476 * @hw: pointer to the hardware structure
5477 * @v_opcode: opcodes for VF-PF communication
5478 * @v_retval: return error code
5479 * @msg: pointer to the msg buffer
5480 * @msglen: msg length
5481 * @cmd_details: pointer to command details
5483 * Send message to PF driver using admin queue. By default, this message
5484 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
5485 * completion before returning.
5487 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
5488 enum i40e_virtchnl_ops v_opcode,
5489 enum i40e_status_code v_retval,
5490 u8 *msg, u16 msglen,
5491 struct i40e_asq_cmd_details *cmd_details)
5493 struct i40e_aq_desc desc;
5494 struct i40e_asq_cmd_details details;
5495 enum i40e_status_code status;
5497 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
5498 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
5499 desc.cookie_high = CPU_TO_LE32(v_opcode);
5500 desc.cookie_low = CPU_TO_LE32(v_retval);
5502 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
5503 | I40E_AQ_FLAG_RD));
5504 if (msglen > I40E_AQ_LARGE_BUF)
5505 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5506 desc.datalen = CPU_TO_LE16(msglen);
5509 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
5510 details.async = true;
5511 cmd_details = &details;
5513 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
5514 msglen, cmd_details);
5519 * i40e_vf_parse_hw_config
5520 * @hw: pointer to the hardware structure
5521 * @msg: pointer to the virtual channel VF resource structure
5523 * Given a VF resource message from the PF, populate the hw struct
5524 * with appropriate information.
5526 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
5527 struct i40e_virtchnl_vf_resource *msg)
5529 struct i40e_virtchnl_vsi_resource *vsi_res;
5532 vsi_res = &msg->vsi_res[0];
5534 hw->dev_caps.num_vsis = msg->num_vsis;
5535 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
5536 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
5537 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
5538 hw->dev_caps.dcb = msg->vf_offload_flags &
5539 I40E_VIRTCHNL_VF_OFFLOAD_L2;
5540 hw->dev_caps.fcoe = (msg->vf_offload_flags &
5541 I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
5542 hw->dev_caps.iwarp = (msg->vf_offload_flags &
5543 I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
5544 for (i = 0; i < msg->num_vsis; i++) {
5545 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
5546 i40e_memcpy(hw->mac.perm_addr,
5547 vsi_res->default_mac_addr,
5548 I40E_ETH_LENGTH_OF_ADDRESS,
5549 I40E_NONDMA_TO_NONDMA);
5550 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
5551 I40E_ETH_LENGTH_OF_ADDRESS,
5552 I40E_NONDMA_TO_NONDMA);
5560 * @hw: pointer to the hardware structure
5562 * Send a VF_RESET message to the PF. Does not wait for response from PF
5563 * as none will be forthcoming. Immediately after calling this function,
5564 * the admin queue should be shut down and (optionally) reinitialized.
5566 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
5568 return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
5569 I40E_SUCCESS, NULL, 0, NULL);
5571 #endif /* VF_DRIVER */