1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "i40e_type.h"
35 #include "i40e_adminq.h"
36 #include "i40e_prototype.h"
37 #include "i40e_virtchnl.h"
41 * i40e_set_mac_type - Sets MAC type
42 * @hw: pointer to the HW structure
44 * This function sets the mac type of the adapter based on the
45 * vendor ID and device ID stored in the hw structure.
47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
53 enum i40e_status_code status = I40E_SUCCESS;
55 DEBUGFUNC("i40e_set_mac_type\n");
57 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
58 switch (hw->device_id) {
59 case I40E_DEV_ID_SFP_XL710:
60 case I40E_DEV_ID_QEMU:
61 case I40E_DEV_ID_KX_A:
62 case I40E_DEV_ID_KX_B:
63 case I40E_DEV_ID_KX_C:
64 case I40E_DEV_ID_QSFP_A:
65 case I40E_DEV_ID_QSFP_B:
66 case I40E_DEV_ID_QSFP_C:
67 case I40E_DEV_ID_10G_BASE_T:
68 case I40E_DEV_ID_10G_BASE_T4:
69 case I40E_DEV_ID_20G_KR2:
70 case I40E_DEV_ID_20G_KR2_A:
71 hw->mac.type = I40E_MAC_XL710;
74 #ifdef X722_A0_SUPPORT
75 case I40E_DEV_ID_X722_A0:
77 case I40E_DEV_ID_SFP_X722:
78 case I40E_DEV_ID_1G_BASE_T_X722:
79 case I40E_DEV_ID_10G_BASE_T_X722:
80 hw->mac.type = I40E_MAC_X722;
84 case I40E_DEV_ID_X722_VF:
85 case I40E_DEV_ID_X722_VF_HV:
86 hw->mac.type = I40E_MAC_X722_VF;
90 case I40E_DEV_ID_VF_HV:
91 hw->mac.type = I40E_MAC_VF;
94 hw->mac.type = I40E_MAC_GENERIC;
98 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
101 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
102 hw->mac.type, status);
106 #ifndef I40E_NDIS_SUPPORT
108 * i40e_aq_str - convert AQ err code to a string
109 * @hw: pointer to the HW structure
110 * @aq_err: the AQ error code to convert
112 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
117 case I40E_AQ_RC_EPERM:
118 return "I40E_AQ_RC_EPERM";
119 case I40E_AQ_RC_ENOENT:
120 return "I40E_AQ_RC_ENOENT";
121 case I40E_AQ_RC_ESRCH:
122 return "I40E_AQ_RC_ESRCH";
123 case I40E_AQ_RC_EINTR:
124 return "I40E_AQ_RC_EINTR";
126 return "I40E_AQ_RC_EIO";
127 case I40E_AQ_RC_ENXIO:
128 return "I40E_AQ_RC_ENXIO";
129 case I40E_AQ_RC_E2BIG:
130 return "I40E_AQ_RC_E2BIG";
131 case I40E_AQ_RC_EAGAIN:
132 return "I40E_AQ_RC_EAGAIN";
133 case I40E_AQ_RC_ENOMEM:
134 return "I40E_AQ_RC_ENOMEM";
135 case I40E_AQ_RC_EACCES:
136 return "I40E_AQ_RC_EACCES";
137 case I40E_AQ_RC_EFAULT:
138 return "I40E_AQ_RC_EFAULT";
139 case I40E_AQ_RC_EBUSY:
140 return "I40E_AQ_RC_EBUSY";
141 case I40E_AQ_RC_EEXIST:
142 return "I40E_AQ_RC_EEXIST";
143 case I40E_AQ_RC_EINVAL:
144 return "I40E_AQ_RC_EINVAL";
145 case I40E_AQ_RC_ENOTTY:
146 return "I40E_AQ_RC_ENOTTY";
147 case I40E_AQ_RC_ENOSPC:
148 return "I40E_AQ_RC_ENOSPC";
149 case I40E_AQ_RC_ENOSYS:
150 return "I40E_AQ_RC_ENOSYS";
151 case I40E_AQ_RC_ERANGE:
152 return "I40E_AQ_RC_ERANGE";
153 case I40E_AQ_RC_EFLUSHED:
154 return "I40E_AQ_RC_EFLUSHED";
155 case I40E_AQ_RC_BAD_ADDR:
156 return "I40E_AQ_RC_BAD_ADDR";
157 case I40E_AQ_RC_EMODE:
158 return "I40E_AQ_RC_EMODE";
159 case I40E_AQ_RC_EFBIG:
160 return "I40E_AQ_RC_EFBIG";
163 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
168 * i40e_stat_str - convert status err code to a string
169 * @hw: pointer to the HW structure
170 * @stat_err: the status error code to convert
172 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
178 return "I40E_ERR_NVM";
179 case I40E_ERR_NVM_CHECKSUM:
180 return "I40E_ERR_NVM_CHECKSUM";
182 return "I40E_ERR_PHY";
183 case I40E_ERR_CONFIG:
184 return "I40E_ERR_CONFIG";
186 return "I40E_ERR_PARAM";
187 case I40E_ERR_MAC_TYPE:
188 return "I40E_ERR_MAC_TYPE";
189 case I40E_ERR_UNKNOWN_PHY:
190 return "I40E_ERR_UNKNOWN_PHY";
191 case I40E_ERR_LINK_SETUP:
192 return "I40E_ERR_LINK_SETUP";
193 case I40E_ERR_ADAPTER_STOPPED:
194 return "I40E_ERR_ADAPTER_STOPPED";
195 case I40E_ERR_INVALID_MAC_ADDR:
196 return "I40E_ERR_INVALID_MAC_ADDR";
197 case I40E_ERR_DEVICE_NOT_SUPPORTED:
198 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
199 case I40E_ERR_MASTER_REQUESTS_PENDING:
200 return "I40E_ERR_MASTER_REQUESTS_PENDING";
201 case I40E_ERR_INVALID_LINK_SETTINGS:
202 return "I40E_ERR_INVALID_LINK_SETTINGS";
203 case I40E_ERR_AUTONEG_NOT_COMPLETE:
204 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
205 case I40E_ERR_RESET_FAILED:
206 return "I40E_ERR_RESET_FAILED";
207 case I40E_ERR_SWFW_SYNC:
208 return "I40E_ERR_SWFW_SYNC";
209 case I40E_ERR_NO_AVAILABLE_VSI:
210 return "I40E_ERR_NO_AVAILABLE_VSI";
211 case I40E_ERR_NO_MEMORY:
212 return "I40E_ERR_NO_MEMORY";
213 case I40E_ERR_BAD_PTR:
214 return "I40E_ERR_BAD_PTR";
215 case I40E_ERR_RING_FULL:
216 return "I40E_ERR_RING_FULL";
217 case I40E_ERR_INVALID_PD_ID:
218 return "I40E_ERR_INVALID_PD_ID";
219 case I40E_ERR_INVALID_QP_ID:
220 return "I40E_ERR_INVALID_QP_ID";
221 case I40E_ERR_INVALID_CQ_ID:
222 return "I40E_ERR_INVALID_CQ_ID";
223 case I40E_ERR_INVALID_CEQ_ID:
224 return "I40E_ERR_INVALID_CEQ_ID";
225 case I40E_ERR_INVALID_AEQ_ID:
226 return "I40E_ERR_INVALID_AEQ_ID";
227 case I40E_ERR_INVALID_SIZE:
228 return "I40E_ERR_INVALID_SIZE";
229 case I40E_ERR_INVALID_ARP_INDEX:
230 return "I40E_ERR_INVALID_ARP_INDEX";
231 case I40E_ERR_INVALID_FPM_FUNC_ID:
232 return "I40E_ERR_INVALID_FPM_FUNC_ID";
233 case I40E_ERR_QP_INVALID_MSG_SIZE:
234 return "I40E_ERR_QP_INVALID_MSG_SIZE";
235 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
236 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
237 case I40E_ERR_INVALID_FRAG_COUNT:
238 return "I40E_ERR_INVALID_FRAG_COUNT";
239 case I40E_ERR_QUEUE_EMPTY:
240 return "I40E_ERR_QUEUE_EMPTY";
241 case I40E_ERR_INVALID_ALIGNMENT:
242 return "I40E_ERR_INVALID_ALIGNMENT";
243 case I40E_ERR_FLUSHED_QUEUE:
244 return "I40E_ERR_FLUSHED_QUEUE";
245 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
246 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
247 case I40E_ERR_INVALID_IMM_DATA_SIZE:
248 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
249 case I40E_ERR_TIMEOUT:
250 return "I40E_ERR_TIMEOUT";
251 case I40E_ERR_OPCODE_MISMATCH:
252 return "I40E_ERR_OPCODE_MISMATCH";
253 case I40E_ERR_CQP_COMPL_ERROR:
254 return "I40E_ERR_CQP_COMPL_ERROR";
255 case I40E_ERR_INVALID_VF_ID:
256 return "I40E_ERR_INVALID_VF_ID";
257 case I40E_ERR_INVALID_HMCFN_ID:
258 return "I40E_ERR_INVALID_HMCFN_ID";
259 case I40E_ERR_BACKING_PAGE_ERROR:
260 return "I40E_ERR_BACKING_PAGE_ERROR";
261 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
262 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
263 case I40E_ERR_INVALID_PBLE_INDEX:
264 return "I40E_ERR_INVALID_PBLE_INDEX";
265 case I40E_ERR_INVALID_SD_INDEX:
266 return "I40E_ERR_INVALID_SD_INDEX";
267 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
268 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
269 case I40E_ERR_INVALID_SD_TYPE:
270 return "I40E_ERR_INVALID_SD_TYPE";
271 case I40E_ERR_MEMCPY_FAILED:
272 return "I40E_ERR_MEMCPY_FAILED";
273 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
274 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
275 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
276 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
277 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
278 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
279 case I40E_ERR_SRQ_ENABLED:
280 return "I40E_ERR_SRQ_ENABLED";
281 case I40E_ERR_ADMIN_QUEUE_ERROR:
282 return "I40E_ERR_ADMIN_QUEUE_ERROR";
283 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
284 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
285 case I40E_ERR_BUF_TOO_SHORT:
286 return "I40E_ERR_BUF_TOO_SHORT";
287 case I40E_ERR_ADMIN_QUEUE_FULL:
288 return "I40E_ERR_ADMIN_QUEUE_FULL";
289 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
290 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
291 case I40E_ERR_BAD_IWARP_CQE:
292 return "I40E_ERR_BAD_IWARP_CQE";
293 case I40E_ERR_NVM_BLANK_MODE:
294 return "I40E_ERR_NVM_BLANK_MODE";
295 case I40E_ERR_NOT_IMPLEMENTED:
296 return "I40E_ERR_NOT_IMPLEMENTED";
297 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
298 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
299 case I40E_ERR_DIAG_TEST_FAILED:
300 return "I40E_ERR_DIAG_TEST_FAILED";
301 case I40E_ERR_NOT_READY:
302 return "I40E_ERR_NOT_READY";
303 case I40E_NOT_SUPPORTED:
304 return "I40E_NOT_SUPPORTED";
305 case I40E_ERR_FIRMWARE_API_VERSION:
306 return "I40E_ERR_FIRMWARE_API_VERSION";
309 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
313 #endif /* I40E_NDIS_SUPPORT */
316 * @hw: debug mask related to admin queue
318 * @desc: pointer to admin queue descriptor
319 * @buffer: pointer to command buffer
320 * @buf_len: max length of buffer
322 * Dumps debug log about adminq command with descriptor contents.
324 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
325 void *buffer, u16 buf_len)
327 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
328 u16 len = LE16_TO_CPU(aq_desc->datalen);
329 u8 *buf = (u8 *)buffer;
332 if ((!(mask & hw->debug_mask)) || (desc == NULL))
336 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
337 LE16_TO_CPU(aq_desc->opcode),
338 LE16_TO_CPU(aq_desc->flags),
339 LE16_TO_CPU(aq_desc->datalen),
340 LE16_TO_CPU(aq_desc->retval));
341 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
342 LE32_TO_CPU(aq_desc->cookie_high),
343 LE32_TO_CPU(aq_desc->cookie_low));
344 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
345 LE32_TO_CPU(aq_desc->params.internal.param0),
346 LE32_TO_CPU(aq_desc->params.internal.param1));
347 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
348 LE32_TO_CPU(aq_desc->params.external.addr_high),
349 LE32_TO_CPU(aq_desc->params.external.addr_low));
351 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
352 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
355 /* write the full 16-byte chunks */
356 for (i = 0; i < (len - 16); i += 16)
358 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
359 i, buf[i], buf[i+1], buf[i+2], buf[i+3],
360 buf[i+4], buf[i+5], buf[i+6], buf[i+7],
361 buf[i+8], buf[i+9], buf[i+10], buf[i+11],
362 buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
363 /* the most we could have left is 16 bytes, pad with zeros */
368 memset(d_buf, 0, sizeof(d_buf));
369 for (j = 0; i < len; j++, i++)
372 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
373 i, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
374 d_buf[4], d_buf[5], d_buf[6], d_buf[7],
375 d_buf[8], d_buf[9], d_buf[10], d_buf[11],
376 d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
382 * i40e_check_asq_alive
383 * @hw: pointer to the hw struct
385 * Returns true if Queue is enabled else false.
387 bool i40e_check_asq_alive(struct i40e_hw *hw)
393 return !!(rd32(hw, hw->aq.asq.len) &
394 I40E_PF_ATQLEN_ATQENABLE_MASK);
396 return !!(rd32(hw, hw->aq.asq.len) &
397 I40E_PF_ATQLEN_ATQENABLE_MASK);
398 #endif /* INTEGRATED_VF */
399 #endif /* PF_DRIVER */
403 return !!(rd32(hw, hw->aq.asq.len) &
404 I40E_VF_ATQLEN1_ATQENABLE_MASK);
406 return !!(rd32(hw, hw->aq.asq.len) &
407 I40E_VF_ATQLEN1_ATQENABLE_MASK);
408 #endif /* INTEGRATED_VF */
409 #endif /* VF_DRIVER */
414 * i40e_aq_queue_shutdown
415 * @hw: pointer to the hw struct
416 * @unloading: is the driver unloading itself
418 * Tell the Firmware that we're shutting down the AdminQ and whether
419 * or not the driver is unloading as well.
421 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
424 struct i40e_aq_desc desc;
425 struct i40e_aqc_queue_shutdown *cmd =
426 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
427 enum i40e_status_code status;
429 i40e_fill_default_direct_cmd_desc(&desc,
430 i40e_aqc_opc_queue_shutdown);
433 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
434 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
441 * i40e_aq_get_set_rss_lut
442 * @hw: pointer to the hardware structure
443 * @vsi_id: vsi fw index
444 * @pf_lut: for PF table set true, for VSI table set false
445 * @lut: pointer to the lut buffer provided by the caller
446 * @lut_size: size of the lut buffer
447 * @set: set true to set the table, false to get the table
449 * Internal function to get or set RSS look up table
451 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
452 u16 vsi_id, bool pf_lut,
453 u8 *lut, u16 lut_size,
456 enum i40e_status_code status;
457 struct i40e_aq_desc desc;
458 struct i40e_aqc_get_set_rss_lut *cmd_resp =
459 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
462 i40e_fill_default_direct_cmd_desc(&desc,
463 i40e_aqc_opc_set_rss_lut);
465 i40e_fill_default_direct_cmd_desc(&desc,
466 i40e_aqc_opc_get_rss_lut);
468 /* Indirect command */
469 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
470 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
473 CPU_TO_LE16((u16)((vsi_id <<
474 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
475 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
476 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
479 cmd_resp->flags |= CPU_TO_LE16((u16)
480 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
481 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
482 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
484 cmd_resp->flags |= CPU_TO_LE16((u16)
485 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
486 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
487 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
489 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
495 * i40e_aq_get_rss_lut
496 * @hw: pointer to the hardware structure
497 * @vsi_id: vsi fw index
498 * @pf_lut: for PF table set true, for VSI table set false
499 * @lut: pointer to the lut buffer provided by the caller
500 * @lut_size: size of the lut buffer
502 * get the RSS lookup table, PF or VSI type
504 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
505 bool pf_lut, u8 *lut, u16 lut_size)
507 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
512 * i40e_aq_set_rss_lut
513 * @hw: pointer to the hardware structure
514 * @vsi_id: vsi fw index
515 * @pf_lut: for PF table set true, for VSI table set false
516 * @lut: pointer to the lut buffer provided by the caller
517 * @lut_size: size of the lut buffer
519 * set the RSS lookup table, PF or VSI type
521 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
522 bool pf_lut, u8 *lut, u16 lut_size)
524 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
528 * i40e_aq_get_set_rss_key
529 * @hw: pointer to the hw struct
530 * @vsi_id: vsi fw index
531 * @key: pointer to key info struct
532 * @set: set true to set the key, false to get the key
534 * get the RSS key per VSI
536 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
538 struct i40e_aqc_get_set_rss_key_data *key,
541 enum i40e_status_code status;
542 struct i40e_aq_desc desc;
543 struct i40e_aqc_get_set_rss_key *cmd_resp =
544 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
545 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
548 i40e_fill_default_direct_cmd_desc(&desc,
549 i40e_aqc_opc_set_rss_key);
551 i40e_fill_default_direct_cmd_desc(&desc,
552 i40e_aqc_opc_get_rss_key);
554 /* Indirect command */
555 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
556 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
559 CPU_TO_LE16((u16)((vsi_id <<
560 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
561 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
562 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
564 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
570 * i40e_aq_get_rss_key
571 * @hw: pointer to the hw struct
572 * @vsi_id: vsi fw index
573 * @key: pointer to key info struct
576 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
578 struct i40e_aqc_get_set_rss_key_data *key)
580 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
584 * i40e_aq_set_rss_key
585 * @hw: pointer to the hw struct
586 * @vsi_id: vsi fw index
587 * @key: pointer to key info struct
589 * set the RSS key per VSI
591 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
593 struct i40e_aqc_get_set_rss_key_data *key)
595 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
597 #endif /* X722_SUPPORT */
599 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
600 * hardware to a bit-field that can be used by SW to more easily determine the
603 * Macros are used to shorten the table lines and make this table human
606 * We store the PTYPE in the top byte of the bit field - this is just so that
607 * we can check that the table doesn't have a row missing, as the index into
608 * the table should be the PTYPE.
612 * IF NOT i40e_ptype_lookup[ptype].known
615 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
616 * Use the rest of the fields to look at the tunnels, inner protocols, etc
618 * Use the enum i40e_rx_l2_ptype to decode the packet type
622 /* macro to make the table lines short */
623 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
626 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
627 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
628 I40E_RX_PTYPE_##OUTER_FRAG, \
629 I40E_RX_PTYPE_TUNNEL_##T, \
630 I40E_RX_PTYPE_TUNNEL_END_##TE, \
631 I40E_RX_PTYPE_##TEF, \
632 I40E_RX_PTYPE_INNER_PROT_##I, \
633 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
635 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
636 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
638 /* shorter macros makes the table fit but are terse */
639 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
640 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
641 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
643 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
644 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
645 /* L2 Packet types */
646 I40E_PTT_UNUSED_ENTRY(0),
647 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
648 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
649 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
650 I40E_PTT_UNUSED_ENTRY(4),
651 I40E_PTT_UNUSED_ENTRY(5),
652 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
653 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
654 I40E_PTT_UNUSED_ENTRY(8),
655 I40E_PTT_UNUSED_ENTRY(9),
656 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
657 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
658 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
659 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
660 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
661 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
662 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
663 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
664 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
665 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
666 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
667 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
669 /* Non Tunneled IPv4 */
670 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
671 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
672 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
673 I40E_PTT_UNUSED_ENTRY(25),
674 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
675 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
676 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
679 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
680 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
681 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
682 I40E_PTT_UNUSED_ENTRY(32),
683 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
684 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
685 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
688 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
689 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
690 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
691 I40E_PTT_UNUSED_ENTRY(39),
692 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
693 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
694 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
696 /* IPv4 --> GRE/NAT */
697 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
699 /* IPv4 --> GRE/NAT --> IPv4 */
700 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
701 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
702 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
703 I40E_PTT_UNUSED_ENTRY(47),
704 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
705 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
706 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
708 /* IPv4 --> GRE/NAT --> IPv6 */
709 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
710 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
711 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
712 I40E_PTT_UNUSED_ENTRY(54),
713 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
714 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
715 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
717 /* IPv4 --> GRE/NAT --> MAC */
718 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
720 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
721 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
722 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
723 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
724 I40E_PTT_UNUSED_ENTRY(62),
725 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
726 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
727 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
729 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
730 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
731 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
732 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
733 I40E_PTT_UNUSED_ENTRY(69),
734 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
735 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
736 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
738 /* IPv4 --> GRE/NAT --> MAC/VLAN */
739 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
741 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
742 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
743 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
744 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
745 I40E_PTT_UNUSED_ENTRY(77),
746 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
747 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
748 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
750 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
751 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
752 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
753 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
754 I40E_PTT_UNUSED_ENTRY(84),
755 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
756 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
757 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
759 /* Non Tunneled IPv6 */
760 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
761 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
762 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
763 I40E_PTT_UNUSED_ENTRY(91),
764 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
765 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
766 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
769 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
770 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
771 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
772 I40E_PTT_UNUSED_ENTRY(98),
773 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
774 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
775 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
778 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
779 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
780 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
781 I40E_PTT_UNUSED_ENTRY(105),
782 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
783 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
784 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
786 /* IPv6 --> GRE/NAT */
787 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
789 /* IPv6 --> GRE/NAT -> IPv4 */
790 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
791 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
792 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
793 I40E_PTT_UNUSED_ENTRY(113),
794 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
795 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
796 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
798 /* IPv6 --> GRE/NAT -> IPv6 */
799 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
800 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
801 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
802 I40E_PTT_UNUSED_ENTRY(120),
803 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
804 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
805 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
807 /* IPv6 --> GRE/NAT -> MAC */
808 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
810 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
811 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
812 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
813 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
814 I40E_PTT_UNUSED_ENTRY(128),
815 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
816 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
817 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
819 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
820 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
821 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
822 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
823 I40E_PTT_UNUSED_ENTRY(135),
824 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
825 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
826 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
828 /* IPv6 --> GRE/NAT -> MAC/VLAN */
829 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
831 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
832 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
833 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
834 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
835 I40E_PTT_UNUSED_ENTRY(143),
836 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
837 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
838 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
840 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
841 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
842 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
843 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
844 I40E_PTT_UNUSED_ENTRY(150),
845 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
846 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
847 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
850 I40E_PTT_UNUSED_ENTRY(154),
851 I40E_PTT_UNUSED_ENTRY(155),
852 I40E_PTT_UNUSED_ENTRY(156),
853 I40E_PTT_UNUSED_ENTRY(157),
854 I40E_PTT_UNUSED_ENTRY(158),
855 I40E_PTT_UNUSED_ENTRY(159),
857 I40E_PTT_UNUSED_ENTRY(160),
858 I40E_PTT_UNUSED_ENTRY(161),
859 I40E_PTT_UNUSED_ENTRY(162),
860 I40E_PTT_UNUSED_ENTRY(163),
861 I40E_PTT_UNUSED_ENTRY(164),
862 I40E_PTT_UNUSED_ENTRY(165),
863 I40E_PTT_UNUSED_ENTRY(166),
864 I40E_PTT_UNUSED_ENTRY(167),
865 I40E_PTT_UNUSED_ENTRY(168),
866 I40E_PTT_UNUSED_ENTRY(169),
868 I40E_PTT_UNUSED_ENTRY(170),
869 I40E_PTT_UNUSED_ENTRY(171),
870 I40E_PTT_UNUSED_ENTRY(172),
871 I40E_PTT_UNUSED_ENTRY(173),
872 I40E_PTT_UNUSED_ENTRY(174),
873 I40E_PTT_UNUSED_ENTRY(175),
874 I40E_PTT_UNUSED_ENTRY(176),
875 I40E_PTT_UNUSED_ENTRY(177),
876 I40E_PTT_UNUSED_ENTRY(178),
877 I40E_PTT_UNUSED_ENTRY(179),
879 I40E_PTT_UNUSED_ENTRY(180),
880 I40E_PTT_UNUSED_ENTRY(181),
881 I40E_PTT_UNUSED_ENTRY(182),
882 I40E_PTT_UNUSED_ENTRY(183),
883 I40E_PTT_UNUSED_ENTRY(184),
884 I40E_PTT_UNUSED_ENTRY(185),
885 I40E_PTT_UNUSED_ENTRY(186),
886 I40E_PTT_UNUSED_ENTRY(187),
887 I40E_PTT_UNUSED_ENTRY(188),
888 I40E_PTT_UNUSED_ENTRY(189),
890 I40E_PTT_UNUSED_ENTRY(190),
891 I40E_PTT_UNUSED_ENTRY(191),
892 I40E_PTT_UNUSED_ENTRY(192),
893 I40E_PTT_UNUSED_ENTRY(193),
894 I40E_PTT_UNUSED_ENTRY(194),
895 I40E_PTT_UNUSED_ENTRY(195),
896 I40E_PTT_UNUSED_ENTRY(196),
897 I40E_PTT_UNUSED_ENTRY(197),
898 I40E_PTT_UNUSED_ENTRY(198),
899 I40E_PTT_UNUSED_ENTRY(199),
901 I40E_PTT_UNUSED_ENTRY(200),
902 I40E_PTT_UNUSED_ENTRY(201),
903 I40E_PTT_UNUSED_ENTRY(202),
904 I40E_PTT_UNUSED_ENTRY(203),
905 I40E_PTT_UNUSED_ENTRY(204),
906 I40E_PTT_UNUSED_ENTRY(205),
907 I40E_PTT_UNUSED_ENTRY(206),
908 I40E_PTT_UNUSED_ENTRY(207),
909 I40E_PTT_UNUSED_ENTRY(208),
910 I40E_PTT_UNUSED_ENTRY(209),
912 I40E_PTT_UNUSED_ENTRY(210),
913 I40E_PTT_UNUSED_ENTRY(211),
914 I40E_PTT_UNUSED_ENTRY(212),
915 I40E_PTT_UNUSED_ENTRY(213),
916 I40E_PTT_UNUSED_ENTRY(214),
917 I40E_PTT_UNUSED_ENTRY(215),
918 I40E_PTT_UNUSED_ENTRY(216),
919 I40E_PTT_UNUSED_ENTRY(217),
920 I40E_PTT_UNUSED_ENTRY(218),
921 I40E_PTT_UNUSED_ENTRY(219),
923 I40E_PTT_UNUSED_ENTRY(220),
924 I40E_PTT_UNUSED_ENTRY(221),
925 I40E_PTT_UNUSED_ENTRY(222),
926 I40E_PTT_UNUSED_ENTRY(223),
927 I40E_PTT_UNUSED_ENTRY(224),
928 I40E_PTT_UNUSED_ENTRY(225),
929 I40E_PTT_UNUSED_ENTRY(226),
930 I40E_PTT_UNUSED_ENTRY(227),
931 I40E_PTT_UNUSED_ENTRY(228),
932 I40E_PTT_UNUSED_ENTRY(229),
934 I40E_PTT_UNUSED_ENTRY(230),
935 I40E_PTT_UNUSED_ENTRY(231),
936 I40E_PTT_UNUSED_ENTRY(232),
937 I40E_PTT_UNUSED_ENTRY(233),
938 I40E_PTT_UNUSED_ENTRY(234),
939 I40E_PTT_UNUSED_ENTRY(235),
940 I40E_PTT_UNUSED_ENTRY(236),
941 I40E_PTT_UNUSED_ENTRY(237),
942 I40E_PTT_UNUSED_ENTRY(238),
943 I40E_PTT_UNUSED_ENTRY(239),
945 I40E_PTT_UNUSED_ENTRY(240),
946 I40E_PTT_UNUSED_ENTRY(241),
947 I40E_PTT_UNUSED_ENTRY(242),
948 I40E_PTT_UNUSED_ENTRY(243),
949 I40E_PTT_UNUSED_ENTRY(244),
950 I40E_PTT_UNUSED_ENTRY(245),
951 I40E_PTT_UNUSED_ENTRY(246),
952 I40E_PTT_UNUSED_ENTRY(247),
953 I40E_PTT_UNUSED_ENTRY(248),
954 I40E_PTT_UNUSED_ENTRY(249),
956 I40E_PTT_UNUSED_ENTRY(250),
957 I40E_PTT_UNUSED_ENTRY(251),
958 I40E_PTT_UNUSED_ENTRY(252),
959 I40E_PTT_UNUSED_ENTRY(253),
960 I40E_PTT_UNUSED_ENTRY(254),
961 I40E_PTT_UNUSED_ENTRY(255)
966 * i40e_validate_mac_addr - Validate unicast MAC address
967 * @mac_addr: pointer to MAC address
969 * Tests a MAC address to ensure it is a valid Individual Address
971 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
973 enum i40e_status_code status = I40E_SUCCESS;
975 DEBUGFUNC("i40e_validate_mac_addr");
977 /* Broadcast addresses ARE multicast addresses
978 * Make sure it is not a multicast address
979 * Reject the zero address
981 if (I40E_IS_MULTICAST(mac_addr) ||
982 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
983 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
984 status = I40E_ERR_INVALID_MAC_ADDR;
991 * i40e_init_shared_code - Initialize the shared code
992 * @hw: pointer to hardware structure
994 * This assigns the MAC type and PHY code and inits the NVM.
995 * Does not touch the hardware. This function must be called prior to any
996 * other function in the shared code. The i40e_hw structure should be
997 * memset to 0 prior to calling this function. The following fields in
998 * hw structure should be filled in prior to calling this function:
999 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1000 * subsystem_vendor_id, and revision_id
1002 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
1004 enum i40e_status_code status = I40E_SUCCESS;
1005 u32 port, ari, func_rid;
1007 DEBUGFUNC("i40e_init_shared_code");
1009 i40e_set_mac_type(hw);
1011 switch (hw->mac.type) {
1012 case I40E_MAC_XL710:
1018 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1021 hw->phy.get_link_info = true;
1023 /* Determine port number and PF number*/
1024 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1025 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1026 hw->port = (u8)port;
1027 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1028 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1029 func_rid = rd32(hw, I40E_PF_FUNC_RID);
1031 hw->pf_id = (u8)(func_rid & 0xff);
1033 hw->pf_id = (u8)(func_rid & 0x7);
1035 status = i40e_init_nvm(hw);
1040 * i40e_aq_mac_address_read - Retrieve the MAC addresses
1041 * @hw: pointer to the hw struct
1042 * @flags: a return indicator of what addresses were added to the addr store
1043 * @addrs: the requestor's mac addr store
1044 * @cmd_details: pointer to command details structure or NULL
1046 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1048 struct i40e_aqc_mac_address_read_data *addrs,
1049 struct i40e_asq_cmd_details *cmd_details)
1051 struct i40e_aq_desc desc;
1052 struct i40e_aqc_mac_address_read *cmd_data =
1053 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1054 enum i40e_status_code status;
1056 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1057 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1059 status = i40e_asq_send_command(hw, &desc, addrs,
1060 sizeof(*addrs), cmd_details);
1061 *flags = LE16_TO_CPU(cmd_data->command_flags);
1067 * i40e_aq_mac_address_write - Change the MAC addresses
1068 * @hw: pointer to the hw struct
1069 * @flags: indicates which MAC to be written
1070 * @mac_addr: address to write
1071 * @cmd_details: pointer to command details structure or NULL
1073 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1074 u16 flags, u8 *mac_addr,
1075 struct i40e_asq_cmd_details *cmd_details)
1077 struct i40e_aq_desc desc;
1078 struct i40e_aqc_mac_address_write *cmd_data =
1079 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1080 enum i40e_status_code status;
1082 i40e_fill_default_direct_cmd_desc(&desc,
1083 i40e_aqc_opc_mac_address_write);
1084 cmd_data->command_flags = CPU_TO_LE16(flags);
1085 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1086 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1087 ((u32)mac_addr[3] << 16) |
1088 ((u32)mac_addr[4] << 8) |
1091 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1097 * i40e_get_mac_addr - get MAC address
1098 * @hw: pointer to the HW structure
1099 * @mac_addr: pointer to MAC address
1101 * Reads the adapter's MAC address from register
1103 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1105 struct i40e_aqc_mac_address_read_data addrs;
1106 enum i40e_status_code status;
1109 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1111 if (flags & I40E_AQC_LAN_ADDR_VALID)
1112 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
1118 * i40e_get_port_mac_addr - get Port MAC address
1119 * @hw: pointer to the HW structure
1120 * @mac_addr: pointer to Port MAC address
1122 * Reads the adapter's Port MAC address
1124 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1126 struct i40e_aqc_mac_address_read_data addrs;
1127 enum i40e_status_code status;
1130 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1134 if (flags & I40E_AQC_PORT_ADDR_VALID)
1135 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
1137 status = I40E_ERR_INVALID_MAC_ADDR;
1143 * i40e_pre_tx_queue_cfg - pre tx queue configure
1144 * @hw: pointer to the HW structure
1145 * @queue: target pf queue index
1146 * @enable: state change request
1148 * Handles hw requirement to indicate intention to enable
1149 * or disable target queue.
1151 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1153 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1157 if (abs_queue_idx >= 128) {
1158 reg_block = abs_queue_idx / 128;
1159 abs_queue_idx %= 128;
1162 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1163 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1164 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1167 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1169 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1171 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1175 * i40e_read_pba_string - Reads part number string from EEPROM
1176 * @hw: pointer to hardware structure
1177 * @pba_num: stores the part number string from the EEPROM
1178 * @pba_num_size: part number string buffer length
1180 * Reads the part number string from the EEPROM.
1182 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1185 enum i40e_status_code status = I40E_SUCCESS;
1191 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1192 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1193 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1197 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1198 if (status != I40E_SUCCESS) {
1199 DEBUGOUT("Failed to read PBA Block pointer.\n");
1203 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1204 if (status != I40E_SUCCESS) {
1205 DEBUGOUT("Failed to read PBA Block size.\n");
1209 /* Subtract one to get PBA word count (PBA Size word is included in
1213 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1214 DEBUGOUT("Buffer to small for PBA data.\n");
1215 return I40E_ERR_PARAM;
1218 for (i = 0; i < pba_size; i++) {
1219 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1220 if (status != I40E_SUCCESS) {
1221 DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1225 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1226 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1228 pba_num[(pba_size * 2)] = '\0';
1234 * i40e_get_media_type - Gets media type
1235 * @hw: pointer to the hardware structure
1237 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1239 enum i40e_media_type media;
1241 switch (hw->phy.link_info.phy_type) {
1242 case I40E_PHY_TYPE_10GBASE_SR:
1243 case I40E_PHY_TYPE_10GBASE_LR:
1244 case I40E_PHY_TYPE_1000BASE_SX:
1245 case I40E_PHY_TYPE_1000BASE_LX:
1246 case I40E_PHY_TYPE_40GBASE_SR4:
1247 case I40E_PHY_TYPE_40GBASE_LR4:
1248 media = I40E_MEDIA_TYPE_FIBER;
1250 case I40E_PHY_TYPE_100BASE_TX:
1251 case I40E_PHY_TYPE_1000BASE_T:
1252 case I40E_PHY_TYPE_10GBASE_T:
1253 media = I40E_MEDIA_TYPE_BASET;
1255 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1256 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1257 case I40E_PHY_TYPE_10GBASE_CR1:
1258 case I40E_PHY_TYPE_40GBASE_CR4:
1259 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1260 case I40E_PHY_TYPE_40GBASE_AOC:
1261 case I40E_PHY_TYPE_10GBASE_AOC:
1262 media = I40E_MEDIA_TYPE_DA;
1264 case I40E_PHY_TYPE_1000BASE_KX:
1265 case I40E_PHY_TYPE_10GBASE_KX4:
1266 case I40E_PHY_TYPE_10GBASE_KR:
1267 case I40E_PHY_TYPE_40GBASE_KR4:
1268 case I40E_PHY_TYPE_20GBASE_KR2:
1269 media = I40E_MEDIA_TYPE_BACKPLANE;
1271 case I40E_PHY_TYPE_SGMII:
1272 case I40E_PHY_TYPE_XAUI:
1273 case I40E_PHY_TYPE_XFI:
1274 case I40E_PHY_TYPE_XLAUI:
1275 case I40E_PHY_TYPE_XLPPI:
1277 media = I40E_MEDIA_TYPE_UNKNOWN;
1284 #define I40E_PF_RESET_WAIT_COUNT 200
1286 * i40e_pf_reset - Reset the PF
1287 * @hw: pointer to the hardware structure
1289 * Assuming someone else has triggered a global reset,
1290 * assure the global reset is complete and then reset the PF
1292 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1299 /* Poll for Global Reset steady state in case of recent GRST.
1300 * The grst delay value is in 100ms units, and we'll wait a
1301 * couple counts longer to be sure we don't just miss the end.
1303 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1304 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1305 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1306 #ifdef I40E_ESS_SUPPORT
1307 /* It can take upto 15 secs for GRST steady state */
1308 grst_del = grst_del * 20; /* bump it to 16 secs max to be safe */
1310 for (cnt = 0; cnt < grst_del + 10; cnt++) {
1311 reg = rd32(hw, I40E_GLGEN_RSTAT);
1312 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1314 i40e_msec_delay(100);
1316 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1317 DEBUGOUT("Global reset polling failed to complete.\n");
1318 return I40E_ERR_RESET_FAILED;
1321 /* Now Wait for the FW to be ready */
1322 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1323 reg = rd32(hw, I40E_GLNVM_ULD);
1324 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1325 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1326 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1327 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1328 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1331 i40e_msec_delay(10);
1333 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1334 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1335 DEBUGOUT("wait for FW Reset complete timedout\n");
1336 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1337 return I40E_ERR_RESET_FAILED;
1340 /* If there was a Global Reset in progress when we got here,
1341 * we don't need to do the PF Reset
1344 reg = rd32(hw, I40E_PFGEN_CTRL);
1345 wr32(hw, I40E_PFGEN_CTRL,
1346 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1347 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1348 reg = rd32(hw, I40E_PFGEN_CTRL);
1349 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1353 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1354 DEBUGOUT("PF reset polling failed to complete.\n");
1355 return I40E_ERR_RESET_FAILED;
1359 i40e_clear_pxe_mode(hw);
1362 return I40E_SUCCESS;
1366 * i40e_clear_hw - clear out any left over hw state
1367 * @hw: pointer to the hw struct
1369 * Clear queues and interrupts, typically called at init time,
1370 * but after the capabilities have been found so we know how many
1371 * queues and msix vectors have been allocated.
1373 void i40e_clear_hw(struct i40e_hw *hw)
1375 u32 num_queues, base_queue;
1383 /* get number of interrupts, queues, and vfs */
1384 val = rd32(hw, I40E_GLPCI_CNF2);
1385 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1386 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1387 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1388 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1390 val = rd32(hw, I40E_PFLAN_QALLOC);
1391 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1392 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1393 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1394 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1395 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1396 num_queues = (j - base_queue) + 1;
1400 val = rd32(hw, I40E_PF_VT_PFALLOC);
1401 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1402 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1403 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1404 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1405 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1406 num_vfs = (j - i) + 1;
1410 /* stop all the interrupts */
1411 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1412 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1413 for (i = 0; i < num_pf_int - 2; i++)
1414 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1416 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1417 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1418 wr32(hw, I40E_PFINT_LNKLST0, val);
1419 for (i = 0; i < num_pf_int - 2; i++)
1420 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1421 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1422 for (i = 0; i < num_vfs; i++)
1423 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1424 for (i = 0; i < num_vf_int - 2; i++)
1425 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1427 /* warn the HW of the coming Tx disables */
1428 for (i = 0; i < num_queues; i++) {
1429 u32 abs_queue_idx = base_queue + i;
1432 if (abs_queue_idx >= 128) {
1433 reg_block = abs_queue_idx / 128;
1434 abs_queue_idx %= 128;
1437 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1438 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1439 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1440 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1442 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1444 i40e_usec_delay(400);
1446 /* stop all the queues */
1447 for (i = 0; i < num_queues; i++) {
1448 wr32(hw, I40E_QINT_TQCTL(i), 0);
1449 wr32(hw, I40E_QTX_ENA(i), 0);
1450 wr32(hw, I40E_QINT_RQCTL(i), 0);
1451 wr32(hw, I40E_QRX_ENA(i), 0);
1454 /* short wait for all queue disables to settle */
1455 i40e_usec_delay(50);
1459 * i40e_clear_pxe_mode - clear pxe operations mode
1460 * @hw: pointer to the hw struct
1462 * Make sure all PXE mode settings are cleared, including things
1463 * like descriptor fetch/write-back mode.
1465 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1467 if (i40e_check_asq_alive(hw))
1468 i40e_aq_clear_pxe_mode(hw, NULL);
1472 * i40e_led_is_mine - helper to find matching led
1473 * @hw: pointer to the hw struct
1474 * @idx: index into GPIO registers
1476 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1478 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1483 if (!hw->func_caps.led[idx])
1486 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1487 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1488 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1490 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1491 * if it is not our port then ignore
1493 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1500 #define I40E_COMBINED_ACTIVITY 0xA
1501 #define I40E_FILTER_ACTIVITY 0xE
1502 #define I40E_LINK_ACTIVITY 0xC
1503 #define I40E_MAC_ACTIVITY 0xD
1504 #define I40E_LED0 22
1507 * i40e_led_get - return current on/off mode
1508 * @hw: pointer to the hw struct
1510 * The value returned is the 'mode' field as defined in the
1511 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1512 * values are variations of possible behaviors relating to
1513 * blink, link, and wire.
1515 u32 i40e_led_get(struct i40e_hw *hw)
1517 u32 current_mode = 0;
1521 /* as per the documentation GPIO 22-29 are the LED
1522 * GPIO pins named LED0..LED7
1524 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1525 u32 gpio_val = i40e_led_is_mine(hw, i);
1530 /* ignore gpio LED src mode entries related to the activity LEDs */
1531 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1532 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1533 switch (current_mode) {
1534 case I40E_COMBINED_ACTIVITY:
1535 case I40E_FILTER_ACTIVITY:
1536 case I40E_MAC_ACTIVITY:
1542 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1543 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1551 * i40e_led_set - set new on/off mode
1552 * @hw: pointer to the hw struct
1553 * @mode: 0=off, 0xf=on (else see manual for mode details)
1554 * @blink: true if the LED should blink when on, false if steady
1556 * if this function is used to turn on the blink it should
1557 * be used to disable the blink when restoring the original state.
1559 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1561 u32 current_mode = 0;
1564 if (mode & 0xfffffff0)
1565 DEBUGOUT1("invalid mode passed in %X\n", mode);
1567 /* as per the documentation GPIO 22-29 are the LED
1568 * GPIO pins named LED0..LED7
1570 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1571 u32 gpio_val = i40e_led_is_mine(hw, i);
1576 /* ignore gpio LED src mode entries related to the activity LEDs */
1577 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1578 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1579 switch (current_mode) {
1580 case I40E_COMBINED_ACTIVITY:
1581 case I40E_FILTER_ACTIVITY:
1582 case I40E_MAC_ACTIVITY:
1588 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1589 /* this & is a bit of paranoia, but serves as a range check */
1590 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1591 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1593 if (mode == I40E_LINK_ACTIVITY)
1597 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1599 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1601 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1606 /* Admin command wrappers */
1609 * i40e_aq_get_phy_capabilities
1610 * @hw: pointer to the hw struct
1611 * @abilities: structure for PHY capabilities to be filled
1612 * @qualified_modules: report Qualified Modules
1613 * @report_init: report init capabilities (active are default)
1614 * @cmd_details: pointer to command details structure or NULL
1616 * Returns the various PHY abilities supported on the Port.
1618 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1619 bool qualified_modules, bool report_init,
1620 struct i40e_aq_get_phy_abilities_resp *abilities,
1621 struct i40e_asq_cmd_details *cmd_details)
1623 struct i40e_aq_desc desc;
1624 enum i40e_status_code status;
1625 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1628 return I40E_ERR_PARAM;
1630 i40e_fill_default_direct_cmd_desc(&desc,
1631 i40e_aqc_opc_get_phy_abilities);
1633 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1634 if (abilities_size > I40E_AQ_LARGE_BUF)
1635 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1637 if (qualified_modules)
1638 desc.params.external.param0 |=
1639 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1642 desc.params.external.param0 |=
1643 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1645 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1648 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1649 status = I40E_ERR_UNKNOWN_PHY;
1652 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1658 * i40e_aq_set_phy_config
1659 * @hw: pointer to the hw struct
1660 * @config: structure with PHY configuration to be set
1661 * @cmd_details: pointer to command details structure or NULL
1663 * Set the various PHY configuration parameters
1664 * supported on the Port.One or more of the Set PHY config parameters may be
1665 * ignored in an MFP mode as the PF may not have the privilege to set some
1666 * of the PHY Config parameters. This status will be indicated by the
1669 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1670 struct i40e_aq_set_phy_config *config,
1671 struct i40e_asq_cmd_details *cmd_details)
1673 struct i40e_aq_desc desc;
1674 struct i40e_aq_set_phy_config *cmd =
1675 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1676 enum i40e_status_code status;
1679 return I40E_ERR_PARAM;
1681 i40e_fill_default_direct_cmd_desc(&desc,
1682 i40e_aqc_opc_set_phy_config);
1686 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1693 * @hw: pointer to the hw struct
1695 * Set the requested flow control mode using set_phy_config.
1697 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1698 bool atomic_restart)
1700 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1701 struct i40e_aq_get_phy_abilities_resp abilities;
1702 struct i40e_aq_set_phy_config config;
1703 enum i40e_status_code status;
1704 u8 pause_mask = 0x0;
1710 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1711 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1713 case I40E_FC_RX_PAUSE:
1714 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1716 case I40E_FC_TX_PAUSE:
1717 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1723 /* Get the current phy config */
1724 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1727 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1731 memset(&config, 0, sizeof(config));
1732 /* clear the old pause settings */
1733 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1734 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1735 /* set the new abilities */
1736 config.abilities |= pause_mask;
1737 /* If the abilities have changed, then set the new config */
1738 if (config.abilities != abilities.abilities) {
1739 /* Auto restart link so settings take effect */
1741 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1742 /* Copy over all the old settings */
1743 config.phy_type = abilities.phy_type;
1744 config.link_speed = abilities.link_speed;
1745 config.eee_capability = abilities.eee_capability;
1746 config.eeer = abilities.eeer_val;
1747 config.low_power_ctrl = abilities.d3_lpan;
1748 status = i40e_aq_set_phy_config(hw, &config, NULL);
1751 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1753 /* Update the link info */
1754 status = i40e_update_link_info(hw);
1756 /* Wait a little bit (on 40G cards it sometimes takes a really
1757 * long time for link to come back from the atomic reset)
1760 i40e_msec_delay(1000);
1761 status = i40e_update_link_info(hw);
1764 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1770 * i40e_aq_set_mac_config
1771 * @hw: pointer to the hw struct
1772 * @max_frame_size: Maximum Frame Size to be supported by the port
1773 * @crc_en: Tell HW to append a CRC to outgoing frames
1774 * @pacing: Pacing configurations
1775 * @cmd_details: pointer to command details structure or NULL
1777 * Configure MAC settings for frame size, jumbo frame support and the
1778 * addition of a CRC by the hardware.
1780 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1782 bool crc_en, u16 pacing,
1783 struct i40e_asq_cmd_details *cmd_details)
1785 struct i40e_aq_desc desc;
1786 struct i40e_aq_set_mac_config *cmd =
1787 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1788 enum i40e_status_code status;
1790 if (max_frame_size == 0)
1791 return I40E_ERR_PARAM;
1793 i40e_fill_default_direct_cmd_desc(&desc,
1794 i40e_aqc_opc_set_mac_config);
1796 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1797 cmd->params = ((u8)pacing & 0x0F) << 3;
1799 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1801 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1807 * i40e_aq_clear_pxe_mode
1808 * @hw: pointer to the hw struct
1809 * @cmd_details: pointer to command details structure or NULL
1811 * Tell the firmware that the driver is taking over from PXE
1813 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1814 struct i40e_asq_cmd_details *cmd_details)
1816 enum i40e_status_code status;
1817 struct i40e_aq_desc desc;
1818 struct i40e_aqc_clear_pxe *cmd =
1819 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1821 i40e_fill_default_direct_cmd_desc(&desc,
1822 i40e_aqc_opc_clear_pxe_mode);
1826 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1828 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1834 * i40e_aq_set_link_restart_an
1835 * @hw: pointer to the hw struct
1836 * @enable_link: if true: enable link, if false: disable link
1837 * @cmd_details: pointer to command details structure or NULL
1839 * Sets up the link and restarts the Auto-Negotiation over the link.
1841 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1842 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1844 struct i40e_aq_desc desc;
1845 struct i40e_aqc_set_link_restart_an *cmd =
1846 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1847 enum i40e_status_code status;
1849 i40e_fill_default_direct_cmd_desc(&desc,
1850 i40e_aqc_opc_set_link_restart_an);
1852 cmd->command = I40E_AQ_PHY_RESTART_AN;
1854 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1856 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1858 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1864 * i40e_aq_get_link_info
1865 * @hw: pointer to the hw struct
1866 * @enable_lse: enable/disable LinkStatusEvent reporting
1867 * @link: pointer to link status structure - optional
1868 * @cmd_details: pointer to command details structure or NULL
1870 * Returns the link status of the adapter.
1872 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1873 bool enable_lse, struct i40e_link_status *link,
1874 struct i40e_asq_cmd_details *cmd_details)
1876 struct i40e_aq_desc desc;
1877 struct i40e_aqc_get_link_status *resp =
1878 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1879 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1880 enum i40e_status_code status;
1881 bool tx_pause, rx_pause;
1884 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1887 command_flags = I40E_AQ_LSE_ENABLE;
1889 command_flags = I40E_AQ_LSE_DISABLE;
1890 resp->command_flags = CPU_TO_LE16(command_flags);
1892 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1894 if (status != I40E_SUCCESS)
1895 goto aq_get_link_info_exit;
1897 /* save off old link status information */
1898 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1899 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1901 /* update link status */
1902 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1903 hw->phy.media_type = i40e_get_media_type(hw);
1904 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1905 hw_link_info->link_info = resp->link_info;
1906 hw_link_info->an_info = resp->an_info;
1907 hw_link_info->ext_info = resp->ext_info;
1908 hw_link_info->loopback = resp->loopback;
1909 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1910 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1912 /* update fc info */
1913 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1914 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1915 if (tx_pause & rx_pause)
1916 hw->fc.current_mode = I40E_FC_FULL;
1918 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1920 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1922 hw->fc.current_mode = I40E_FC_NONE;
1924 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1925 hw_link_info->crc_enable = true;
1927 hw_link_info->crc_enable = false;
1929 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1930 hw_link_info->lse_enable = true;
1932 hw_link_info->lse_enable = false;
1934 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1935 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1936 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1938 /* save link status information */
1940 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1941 I40E_NONDMA_TO_NONDMA);
1943 /* flag cleared so helper functions don't call AQ again */
1944 hw->phy.get_link_info = false;
1946 aq_get_link_info_exit:
1951 * i40e_aq_set_phy_int_mask
1952 * @hw: pointer to the hw struct
1953 * @mask: interrupt mask to be set
1954 * @cmd_details: pointer to command details structure or NULL
1956 * Set link interrupt mask.
1958 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1960 struct i40e_asq_cmd_details *cmd_details)
1962 struct i40e_aq_desc desc;
1963 struct i40e_aqc_set_phy_int_mask *cmd =
1964 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1965 enum i40e_status_code status;
1967 i40e_fill_default_direct_cmd_desc(&desc,
1968 i40e_aqc_opc_set_phy_int_mask);
1970 cmd->event_mask = CPU_TO_LE16(mask);
1972 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1978 * i40e_aq_get_local_advt_reg
1979 * @hw: pointer to the hw struct
1980 * @advt_reg: local AN advertisement register value
1981 * @cmd_details: pointer to command details structure or NULL
1983 * Get the Local AN advertisement register value.
1985 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
1987 struct i40e_asq_cmd_details *cmd_details)
1989 struct i40e_aq_desc desc;
1990 struct i40e_aqc_an_advt_reg *resp =
1991 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1992 enum i40e_status_code status;
1994 i40e_fill_default_direct_cmd_desc(&desc,
1995 i40e_aqc_opc_get_local_advt_reg);
1997 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1999 if (status != I40E_SUCCESS)
2000 goto aq_get_local_advt_reg_exit;
2002 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2003 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2005 aq_get_local_advt_reg_exit:
2010 * i40e_aq_set_local_advt_reg
2011 * @hw: pointer to the hw struct
2012 * @advt_reg: local AN advertisement register value
2013 * @cmd_details: pointer to command details structure or NULL
2015 * Get the Local AN advertisement register value.
2017 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2019 struct i40e_asq_cmd_details *cmd_details)
2021 struct i40e_aq_desc desc;
2022 struct i40e_aqc_an_advt_reg *cmd =
2023 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2024 enum i40e_status_code status;
2026 i40e_fill_default_direct_cmd_desc(&desc,
2027 i40e_aqc_opc_get_local_advt_reg);
2029 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2030 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2032 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2038 * i40e_aq_get_partner_advt
2039 * @hw: pointer to the hw struct
2040 * @advt_reg: AN partner advertisement register value
2041 * @cmd_details: pointer to command details structure or NULL
2043 * Get the link partner AN advertisement register value.
2045 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2047 struct i40e_asq_cmd_details *cmd_details)
2049 struct i40e_aq_desc desc;
2050 struct i40e_aqc_an_advt_reg *resp =
2051 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2052 enum i40e_status_code status;
2054 i40e_fill_default_direct_cmd_desc(&desc,
2055 i40e_aqc_opc_get_partner_advt);
2057 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2059 if (status != I40E_SUCCESS)
2060 goto aq_get_partner_advt_exit;
2062 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2063 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2065 aq_get_partner_advt_exit:
2070 * i40e_aq_set_lb_modes
2071 * @hw: pointer to the hw struct
2072 * @lb_modes: loopback mode to be set
2073 * @cmd_details: pointer to command details structure or NULL
2075 * Sets loopback modes.
2077 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2079 struct i40e_asq_cmd_details *cmd_details)
2081 struct i40e_aq_desc desc;
2082 struct i40e_aqc_set_lb_mode *cmd =
2083 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2084 enum i40e_status_code status;
2086 i40e_fill_default_direct_cmd_desc(&desc,
2087 i40e_aqc_opc_set_lb_modes);
2089 cmd->lb_mode = CPU_TO_LE16(lb_modes);
2091 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2097 * i40e_aq_set_phy_debug
2098 * @hw: pointer to the hw struct
2099 * @cmd_flags: debug command flags
2100 * @cmd_details: pointer to command details structure or NULL
2102 * Reset the external PHY.
2104 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2105 struct i40e_asq_cmd_details *cmd_details)
2107 struct i40e_aq_desc desc;
2108 struct i40e_aqc_set_phy_debug *cmd =
2109 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2110 enum i40e_status_code status;
2112 i40e_fill_default_direct_cmd_desc(&desc,
2113 i40e_aqc_opc_set_phy_debug);
2115 cmd->command_flags = cmd_flags;
2117 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2124 * @hw: pointer to the hw struct
2125 * @vsi_ctx: pointer to a vsi context struct
2126 * @cmd_details: pointer to command details structure or NULL
2128 * Add a VSI context to the hardware.
2130 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2131 struct i40e_vsi_context *vsi_ctx,
2132 struct i40e_asq_cmd_details *cmd_details)
2134 struct i40e_aq_desc desc;
2135 struct i40e_aqc_add_get_update_vsi *cmd =
2136 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2137 struct i40e_aqc_add_get_update_vsi_completion *resp =
2138 (struct i40e_aqc_add_get_update_vsi_completion *)
2140 enum i40e_status_code status;
2142 i40e_fill_default_direct_cmd_desc(&desc,
2143 i40e_aqc_opc_add_vsi);
2145 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2146 cmd->connection_type = vsi_ctx->connection_type;
2147 cmd->vf_id = vsi_ctx->vf_num;
2148 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2150 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2152 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2153 sizeof(vsi_ctx->info), cmd_details);
2155 if (status != I40E_SUCCESS)
2156 goto aq_add_vsi_exit;
2158 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2159 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2160 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2161 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2168 * i40e_aq_set_default_vsi
2169 * @hw: pointer to the hw struct
2171 * @cmd_details: pointer to command details structure or NULL
2173 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2175 struct i40e_asq_cmd_details *cmd_details)
2177 struct i40e_aq_desc desc;
2178 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2179 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2181 enum i40e_status_code status;
2183 i40e_fill_default_direct_cmd_desc(&desc,
2184 i40e_aqc_opc_set_vsi_promiscuous_modes);
2186 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2187 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2188 cmd->seid = CPU_TO_LE16(seid);
2190 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2196 * i40e_aq_set_vsi_unicast_promiscuous
2197 * @hw: pointer to the hw struct
2199 * @set: set unicast promiscuous enable/disable
2200 * @cmd_details: pointer to command details structure or NULL
2202 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2204 struct i40e_asq_cmd_details *cmd_details)
2206 struct i40e_aq_desc desc;
2207 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2208 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2209 enum i40e_status_code status;
2212 i40e_fill_default_direct_cmd_desc(&desc,
2213 i40e_aqc_opc_set_vsi_promiscuous_modes);
2216 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2218 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2220 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2222 cmd->seid = CPU_TO_LE16(seid);
2223 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2229 * i40e_aq_set_vsi_multicast_promiscuous
2230 * @hw: pointer to the hw struct
2232 * @set: set multicast promiscuous enable/disable
2233 * @cmd_details: pointer to command details structure or NULL
2235 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2236 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2238 struct i40e_aq_desc desc;
2239 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2240 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2241 enum i40e_status_code status;
2244 i40e_fill_default_direct_cmd_desc(&desc,
2245 i40e_aqc_opc_set_vsi_promiscuous_modes);
2248 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2250 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2252 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2254 cmd->seid = CPU_TO_LE16(seid);
2255 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2261 * i40e_aq_set_vsi_mc_promisc_on_vlan
2262 * @hw: pointer to the hw struct
2264 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2265 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2266 * @cmd_details: pointer to command details structure or NULL
2268 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2269 u16 seid, bool enable, u16 vid,
2270 struct i40e_asq_cmd_details *cmd_details)
2272 struct i40e_aq_desc desc;
2273 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2274 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2275 enum i40e_status_code status;
2278 i40e_fill_default_direct_cmd_desc(&desc,
2279 i40e_aqc_opc_set_vsi_promiscuous_modes);
2282 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2284 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2285 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2286 cmd->seid = CPU_TO_LE16(seid);
2287 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2289 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2295 * i40e_aq_set_vsi_uc_promisc_on_vlan
2296 * @hw: pointer to the hw struct
2298 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2299 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2300 * @cmd_details: pointer to command details structure or NULL
2302 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2303 u16 seid, bool enable, u16 vid,
2304 struct i40e_asq_cmd_details *cmd_details)
2306 struct i40e_aq_desc desc;
2307 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2308 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2309 enum i40e_status_code status;
2312 i40e_fill_default_direct_cmd_desc(&desc,
2313 i40e_aqc_opc_set_vsi_promiscuous_modes);
2316 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2318 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2319 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2320 cmd->seid = CPU_TO_LE16(seid);
2321 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2323 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2329 * i40e_aq_set_vsi_broadcast
2330 * @hw: pointer to the hw struct
2332 * @set_filter: true to set filter, false to clear filter
2333 * @cmd_details: pointer to command details structure or NULL
2335 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2337 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2338 u16 seid, bool set_filter,
2339 struct i40e_asq_cmd_details *cmd_details)
2341 struct i40e_aq_desc desc;
2342 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2343 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2344 enum i40e_status_code status;
2346 i40e_fill_default_direct_cmd_desc(&desc,
2347 i40e_aqc_opc_set_vsi_promiscuous_modes);
2350 cmd->promiscuous_flags
2351 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2353 cmd->promiscuous_flags
2354 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2356 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2357 cmd->seid = CPU_TO_LE16(seid);
2358 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2364 * i40e_get_vsi_params - get VSI configuration info
2365 * @hw: pointer to the hw struct
2366 * @vsi_ctx: pointer to a vsi context struct
2367 * @cmd_details: pointer to command details structure or NULL
2369 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2370 struct i40e_vsi_context *vsi_ctx,
2371 struct i40e_asq_cmd_details *cmd_details)
2373 struct i40e_aq_desc desc;
2374 struct i40e_aqc_add_get_update_vsi *cmd =
2375 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2376 struct i40e_aqc_add_get_update_vsi_completion *resp =
2377 (struct i40e_aqc_add_get_update_vsi_completion *)
2379 enum i40e_status_code status;
2381 UNREFERENCED_1PARAMETER(cmd_details);
2382 i40e_fill_default_direct_cmd_desc(&desc,
2383 i40e_aqc_opc_get_vsi_parameters);
2385 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2387 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2389 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2390 sizeof(vsi_ctx->info), NULL);
2392 if (status != I40E_SUCCESS)
2393 goto aq_get_vsi_params_exit;
2395 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2396 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2397 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2398 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2400 aq_get_vsi_params_exit:
2405 * i40e_aq_update_vsi_params
2406 * @hw: pointer to the hw struct
2407 * @vsi_ctx: pointer to a vsi context struct
2408 * @cmd_details: pointer to command details structure or NULL
2410 * Update a VSI context.
2412 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2413 struct i40e_vsi_context *vsi_ctx,
2414 struct i40e_asq_cmd_details *cmd_details)
2416 struct i40e_aq_desc desc;
2417 struct i40e_aqc_add_get_update_vsi *cmd =
2418 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2419 enum i40e_status_code status;
2421 i40e_fill_default_direct_cmd_desc(&desc,
2422 i40e_aqc_opc_update_vsi_parameters);
2423 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2425 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2427 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2428 sizeof(vsi_ctx->info), cmd_details);
2434 * i40e_aq_get_switch_config
2435 * @hw: pointer to the hardware structure
2436 * @buf: pointer to the result buffer
2437 * @buf_size: length of input buffer
2438 * @start_seid: seid to start for the report, 0 == beginning
2439 * @cmd_details: pointer to command details structure or NULL
2441 * Fill the buf with switch configuration returned from AdminQ command
2443 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2444 struct i40e_aqc_get_switch_config_resp *buf,
2445 u16 buf_size, u16 *start_seid,
2446 struct i40e_asq_cmd_details *cmd_details)
2448 struct i40e_aq_desc desc;
2449 struct i40e_aqc_switch_seid *scfg =
2450 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2451 enum i40e_status_code status;
2453 i40e_fill_default_direct_cmd_desc(&desc,
2454 i40e_aqc_opc_get_switch_config);
2455 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2456 if (buf_size > I40E_AQ_LARGE_BUF)
2457 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2458 scfg->seid = CPU_TO_LE16(*start_seid);
2460 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2461 *start_seid = LE16_TO_CPU(scfg->seid);
2467 * i40e_aq_get_firmware_version
2468 * @hw: pointer to the hw struct
2469 * @fw_major_version: firmware major version
2470 * @fw_minor_version: firmware minor version
2471 * @fw_build: firmware build number
2472 * @api_major_version: major queue version
2473 * @api_minor_version: minor queue version
2474 * @cmd_details: pointer to command details structure or NULL
2476 * Get the firmware version from the admin queue commands
2478 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2479 u16 *fw_major_version, u16 *fw_minor_version,
2481 u16 *api_major_version, u16 *api_minor_version,
2482 struct i40e_asq_cmd_details *cmd_details)
2484 struct i40e_aq_desc desc;
2485 struct i40e_aqc_get_version *resp =
2486 (struct i40e_aqc_get_version *)&desc.params.raw;
2487 enum i40e_status_code status;
2489 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2491 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2493 if (status == I40E_SUCCESS) {
2494 if (fw_major_version != NULL)
2495 *fw_major_version = LE16_TO_CPU(resp->fw_major);
2496 if (fw_minor_version != NULL)
2497 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2498 if (fw_build != NULL)
2499 *fw_build = LE32_TO_CPU(resp->fw_build);
2500 if (api_major_version != NULL)
2501 *api_major_version = LE16_TO_CPU(resp->api_major);
2502 if (api_minor_version != NULL)
2503 *api_minor_version = LE16_TO_CPU(resp->api_minor);
2505 /* A workaround to fix the API version in SW */
2506 if (api_major_version && api_minor_version &&
2507 fw_major_version && fw_minor_version &&
2508 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2509 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2510 (*fw_major_version > 4)))
2511 *api_minor_version = 2;
2518 * i40e_aq_send_driver_version
2519 * @hw: pointer to the hw struct
2520 * @dv: driver's major, minor version
2521 * @cmd_details: pointer to command details structure or NULL
2523 * Send the driver version to the firmware
2525 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2526 struct i40e_driver_version *dv,
2527 struct i40e_asq_cmd_details *cmd_details)
2529 struct i40e_aq_desc desc;
2530 struct i40e_aqc_driver_version *cmd =
2531 (struct i40e_aqc_driver_version *)&desc.params.raw;
2532 enum i40e_status_code status;
2536 return I40E_ERR_PARAM;
2538 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2540 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2541 cmd->driver_major_ver = dv->major_version;
2542 cmd->driver_minor_ver = dv->minor_version;
2543 cmd->driver_build_ver = dv->build_version;
2544 cmd->driver_subbuild_ver = dv->subbuild_version;
2547 while (len < sizeof(dv->driver_string) &&
2548 (dv->driver_string[len] < 0x80) &&
2549 dv->driver_string[len])
2551 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2558 * i40e_get_link_status - get status of the HW network link
2559 * @hw: pointer to the hw struct
2560 * @link_up: pointer to bool (true/false = linkup/linkdown)
2562 * Variable link_up true if link is up, false if link is down.
2563 * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2565 * Side effect: LinkStatusEvent reporting becomes enabled
2567 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2569 enum i40e_status_code status = I40E_SUCCESS;
2571 if (hw->phy.get_link_info) {
2572 status = i40e_update_link_info(hw);
2574 if (status != I40E_SUCCESS)
2575 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2579 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2585 * i40e_updatelink_status - update status of the HW network link
2586 * @hw: pointer to the hw struct
2588 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2590 struct i40e_aq_get_phy_abilities_resp abilities;
2591 enum i40e_status_code status = I40E_SUCCESS;
2593 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2597 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
2602 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2603 sizeof(hw->phy.link_info.module_type));
2609 * i40e_get_link_speed
2610 * @hw: pointer to the hw struct
2612 * Returns the link speed of the adapter.
2614 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2616 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2617 enum i40e_status_code status = I40E_SUCCESS;
2619 if (hw->phy.get_link_info) {
2620 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2622 if (status != I40E_SUCCESS)
2623 goto i40e_link_speed_exit;
2626 speed = hw->phy.link_info.link_speed;
2628 i40e_link_speed_exit:
2633 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2634 * @hw: pointer to the hw struct
2635 * @uplink_seid: the MAC or other gizmo SEID
2636 * @downlink_seid: the VSI SEID
2637 * @enabled_tc: bitmap of TCs to be enabled
2638 * @default_port: true for default port VSI, false for control port
2639 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
2640 * @veb_seid: pointer to where to put the resulting VEB SEID
2641 * @cmd_details: pointer to command details structure or NULL
2643 * This asks the FW to add a VEB between the uplink and downlink
2644 * elements. If the uplink SEID is 0, this will be a floating VEB.
2646 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2647 u16 downlink_seid, u8 enabled_tc,
2648 bool default_port, bool enable_l2_filtering,
2650 struct i40e_asq_cmd_details *cmd_details)
2652 struct i40e_aq_desc desc;
2653 struct i40e_aqc_add_veb *cmd =
2654 (struct i40e_aqc_add_veb *)&desc.params.raw;
2655 struct i40e_aqc_add_veb_completion *resp =
2656 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2657 enum i40e_status_code status;
2660 /* SEIDs need to either both be set or both be 0 for floating VEB */
2661 if (!!uplink_seid != !!downlink_seid)
2662 return I40E_ERR_PARAM;
2664 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2666 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2667 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2668 cmd->enable_tcs = enabled_tc;
2670 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2672 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2674 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2676 if (enable_l2_filtering)
2677 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
2679 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2681 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2683 if (!status && veb_seid)
2684 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2690 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2691 * @hw: pointer to the hw struct
2692 * @veb_seid: the SEID of the VEB to query
2693 * @switch_id: the uplink switch id
2694 * @floating: set to true if the VEB is floating
2695 * @statistic_index: index of the stats counter block for this VEB
2696 * @vebs_used: number of VEB's used by function
2697 * @vebs_free: total VEB's not reserved by any function
2698 * @cmd_details: pointer to command details structure or NULL
2700 * This retrieves the parameters for a particular VEB, specified by
2701 * uplink_seid, and returns them to the caller.
2703 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2704 u16 veb_seid, u16 *switch_id,
2705 bool *floating, u16 *statistic_index,
2706 u16 *vebs_used, u16 *vebs_free,
2707 struct i40e_asq_cmd_details *cmd_details)
2709 struct i40e_aq_desc desc;
2710 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2711 (struct i40e_aqc_get_veb_parameters_completion *)
2713 enum i40e_status_code status;
2716 return I40E_ERR_PARAM;
2718 i40e_fill_default_direct_cmd_desc(&desc,
2719 i40e_aqc_opc_get_veb_parameters);
2720 cmd_resp->seid = CPU_TO_LE16(veb_seid);
2722 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2727 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2728 if (statistic_index)
2729 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2731 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2733 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2735 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2736 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2747 * i40e_aq_add_macvlan
2748 * @hw: pointer to the hw struct
2749 * @seid: VSI for the mac address
2750 * @mv_list: list of macvlans to be added
2751 * @count: length of the list
2752 * @cmd_details: pointer to command details structure or NULL
2754 * Add MAC/VLAN addresses to the HW filtering
2756 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2757 struct i40e_aqc_add_macvlan_element_data *mv_list,
2758 u16 count, struct i40e_asq_cmd_details *cmd_details)
2760 struct i40e_aq_desc desc;
2761 struct i40e_aqc_macvlan *cmd =
2762 (struct i40e_aqc_macvlan *)&desc.params.raw;
2763 enum i40e_status_code status;
2766 if (count == 0 || !mv_list || !hw)
2767 return I40E_ERR_PARAM;
2769 buf_size = count * sizeof(*mv_list);
2771 /* prep the rest of the request */
2772 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2773 cmd->num_addresses = CPU_TO_LE16(count);
2774 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2778 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2779 if (buf_size > I40E_AQ_LARGE_BUF)
2780 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2782 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2789 * i40e_aq_remove_macvlan
2790 * @hw: pointer to the hw struct
2791 * @seid: VSI for the mac address
2792 * @mv_list: list of macvlans to be removed
2793 * @count: length of the list
2794 * @cmd_details: pointer to command details structure or NULL
2796 * Remove MAC/VLAN addresses from the HW filtering
2798 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2799 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2800 u16 count, struct i40e_asq_cmd_details *cmd_details)
2802 struct i40e_aq_desc desc;
2803 struct i40e_aqc_macvlan *cmd =
2804 (struct i40e_aqc_macvlan *)&desc.params.raw;
2805 enum i40e_status_code status;
2808 if (count == 0 || !mv_list || !hw)
2809 return I40E_ERR_PARAM;
2811 buf_size = count * sizeof(*mv_list);
2813 /* prep the rest of the request */
2814 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2815 cmd->num_addresses = CPU_TO_LE16(count);
2816 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2820 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2821 if (buf_size > I40E_AQ_LARGE_BUF)
2822 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2824 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2831 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
2832 * @hw: pointer to the hw struct
2833 * @seid: VSI for the vlan filters
2834 * @v_list: list of vlan filters to be added
2835 * @count: length of the list
2836 * @cmd_details: pointer to command details structure or NULL
2838 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
2839 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2840 u8 count, struct i40e_asq_cmd_details *cmd_details)
2842 struct i40e_aq_desc desc;
2843 struct i40e_aqc_macvlan *cmd =
2844 (struct i40e_aqc_macvlan *)&desc.params.raw;
2845 enum i40e_status_code status;
2848 if (count == 0 || !v_list || !hw)
2849 return I40E_ERR_PARAM;
2851 buf_size = count * sizeof(*v_list);
2853 /* prep the rest of the request */
2854 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
2855 cmd->num_addresses = CPU_TO_LE16(count);
2856 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2860 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2861 if (buf_size > I40E_AQ_LARGE_BUF)
2862 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2864 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2871 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
2872 * @hw: pointer to the hw struct
2873 * @seid: VSI for the vlan filters
2874 * @v_list: list of macvlans to be removed
2875 * @count: length of the list
2876 * @cmd_details: pointer to command details structure or NULL
2878 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
2879 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2880 u8 count, struct i40e_asq_cmd_details *cmd_details)
2882 struct i40e_aq_desc desc;
2883 struct i40e_aqc_macvlan *cmd =
2884 (struct i40e_aqc_macvlan *)&desc.params.raw;
2885 enum i40e_status_code status;
2888 if (count == 0 || !v_list || !hw)
2889 return I40E_ERR_PARAM;
2891 buf_size = count * sizeof(*v_list);
2893 /* prep the rest of the request */
2894 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
2895 cmd->num_addresses = CPU_TO_LE16(count);
2896 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2900 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2901 if (buf_size > I40E_AQ_LARGE_BUF)
2902 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2904 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2911 * i40e_aq_send_msg_to_vf
2912 * @hw: pointer to the hardware structure
2913 * @vfid: vf id to send msg
2914 * @v_opcode: opcodes for VF-PF communication
2915 * @v_retval: return error code
2916 * @msg: pointer to the msg buffer
2917 * @msglen: msg length
2918 * @cmd_details: pointer to command details
2922 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2923 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2924 struct i40e_asq_cmd_details *cmd_details)
2926 struct i40e_aq_desc desc;
2927 struct i40e_aqc_pf_vf_message *cmd =
2928 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2929 enum i40e_status_code status;
2931 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2932 cmd->id = CPU_TO_LE32(vfid);
2933 desc.cookie_high = CPU_TO_LE32(v_opcode);
2934 desc.cookie_low = CPU_TO_LE32(v_retval);
2935 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
2937 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
2939 if (msglen > I40E_AQ_LARGE_BUF)
2940 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2941 desc.datalen = CPU_TO_LE16(msglen);
2943 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2949 * i40e_aq_debug_read_register
2950 * @hw: pointer to the hw struct
2951 * @reg_addr: register address
2952 * @reg_val: register value
2953 * @cmd_details: pointer to command details structure or NULL
2955 * Read the register using the admin queue commands
2957 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
2958 u32 reg_addr, u64 *reg_val,
2959 struct i40e_asq_cmd_details *cmd_details)
2961 struct i40e_aq_desc desc;
2962 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2963 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2964 enum i40e_status_code status;
2966 if (reg_val == NULL)
2967 return I40E_ERR_PARAM;
2969 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2971 cmd_resp->address = CPU_TO_LE32(reg_addr);
2973 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2975 if (status == I40E_SUCCESS) {
2976 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
2977 (u64)LE32_TO_CPU(cmd_resp->value_low);
2984 * i40e_aq_debug_write_register
2985 * @hw: pointer to the hw struct
2986 * @reg_addr: register address
2987 * @reg_val: register value
2988 * @cmd_details: pointer to command details structure or NULL
2990 * Write to a register using the admin queue commands
2992 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
2993 u32 reg_addr, u64 reg_val,
2994 struct i40e_asq_cmd_details *cmd_details)
2996 struct i40e_aq_desc desc;
2997 struct i40e_aqc_debug_reg_read_write *cmd =
2998 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2999 enum i40e_status_code status;
3001 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3003 cmd->address = CPU_TO_LE32(reg_addr);
3004 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3005 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3007 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3013 * i40e_aq_get_hmc_resource_profile
3014 * @hw: pointer to the hw struct
3015 * @profile: type of profile the HMC is to be set as
3016 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
3017 * @cmd_details: pointer to command details structure or NULL
3019 * query the HMC profile of the device.
3021 enum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw,
3022 enum i40e_aq_hmc_profile *profile,
3023 u8 *pe_vf_enabled_count,
3024 struct i40e_asq_cmd_details *cmd_details)
3026 struct i40e_aq_desc desc;
3027 struct i40e_aq_get_set_hmc_resource_profile *resp =
3028 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
3029 enum i40e_status_code status;
3031 i40e_fill_default_direct_cmd_desc(&desc,
3032 i40e_aqc_opc_query_hmc_resource_profile);
3033 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3035 *profile = (enum i40e_aq_hmc_profile)(resp->pm_profile &
3036 I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK);
3037 *pe_vf_enabled_count = resp->pe_vf_enabled &
3038 I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK;
3044 * i40e_aq_set_hmc_resource_profile
3045 * @hw: pointer to the hw struct
3046 * @profile: type of profile the HMC is to be set as
3047 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
3048 * @cmd_details: pointer to command details structure or NULL
3050 * set the HMC profile of the device.
3052 enum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
3053 enum i40e_aq_hmc_profile profile,
3054 u8 pe_vf_enabled_count,
3055 struct i40e_asq_cmd_details *cmd_details)
3057 struct i40e_aq_desc desc;
3058 struct i40e_aq_get_set_hmc_resource_profile *cmd =
3059 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
3060 enum i40e_status_code status;
3062 i40e_fill_default_direct_cmd_desc(&desc,
3063 i40e_aqc_opc_set_hmc_resource_profile);
3065 cmd->pm_profile = (u8)profile;
3066 cmd->pe_vf_enabled = pe_vf_enabled_count;
3068 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3074 * i40e_aq_request_resource
3075 * @hw: pointer to the hw struct
3076 * @resource: resource id
3077 * @access: access type
3078 * @sdp_number: resource number
3079 * @timeout: the maximum time in ms that the driver may hold the resource
3080 * @cmd_details: pointer to command details structure or NULL
3082 * requests common resource using the admin queue commands
3084 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3085 enum i40e_aq_resources_ids resource,
3086 enum i40e_aq_resource_access_type access,
3087 u8 sdp_number, u64 *timeout,
3088 struct i40e_asq_cmd_details *cmd_details)
3090 struct i40e_aq_desc desc;
3091 struct i40e_aqc_request_resource *cmd_resp =
3092 (struct i40e_aqc_request_resource *)&desc.params.raw;
3093 enum i40e_status_code status;
3095 DEBUGFUNC("i40e_aq_request_resource");
3097 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3099 cmd_resp->resource_id = CPU_TO_LE16(resource);
3100 cmd_resp->access_type = CPU_TO_LE16(access);
3101 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3103 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3104 /* The completion specifies the maximum time in ms that the driver
3105 * may hold the resource in the Timeout field.
3106 * If the resource is held by someone else, the command completes with
3107 * busy return value and the timeout field indicates the maximum time
3108 * the current owner of the resource has to free it.
3110 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3111 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3117 * i40e_aq_release_resource
3118 * @hw: pointer to the hw struct
3119 * @resource: resource id
3120 * @sdp_number: resource number
3121 * @cmd_details: pointer to command details structure or NULL
3123 * release common resource using the admin queue commands
3125 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3126 enum i40e_aq_resources_ids resource,
3128 struct i40e_asq_cmd_details *cmd_details)
3130 struct i40e_aq_desc desc;
3131 struct i40e_aqc_request_resource *cmd =
3132 (struct i40e_aqc_request_resource *)&desc.params.raw;
3133 enum i40e_status_code status;
3135 DEBUGFUNC("i40e_aq_release_resource");
3137 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3139 cmd->resource_id = CPU_TO_LE16(resource);
3140 cmd->resource_number = CPU_TO_LE32(sdp_number);
3142 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3149 * @hw: pointer to the hw struct
3150 * @module_pointer: module pointer location in words from the NVM beginning
3151 * @offset: byte offset from the module beginning
3152 * @length: length of the section to be read (in bytes from the offset)
3153 * @data: command buffer (size [bytes] = length)
3154 * @last_command: tells if this is the last command in a series
3155 * @cmd_details: pointer to command details structure or NULL
3157 * Read the NVM using the admin queue commands
3159 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3160 u32 offset, u16 length, void *data,
3162 struct i40e_asq_cmd_details *cmd_details)
3164 struct i40e_aq_desc desc;
3165 struct i40e_aqc_nvm_update *cmd =
3166 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3167 enum i40e_status_code status;
3169 DEBUGFUNC("i40e_aq_read_nvm");
3171 /* In offset the highest byte must be zeroed. */
3172 if (offset & 0xFF000000) {
3173 status = I40E_ERR_PARAM;
3174 goto i40e_aq_read_nvm_exit;
3177 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3179 /* If this is the last command in a series, set the proper flag. */
3181 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3182 cmd->module_pointer = module_pointer;
3183 cmd->offset = CPU_TO_LE32(offset);
3184 cmd->length = CPU_TO_LE16(length);
3186 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3187 if (length > I40E_AQ_LARGE_BUF)
3188 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3190 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3192 i40e_aq_read_nvm_exit:
3197 * i40e_aq_read_nvm_config - read an nvm config block
3198 * @hw: pointer to the hw struct
3199 * @cmd_flags: NVM access admin command bits
3200 * @field_id: field or feature id
3201 * @data: buffer for result
3202 * @buf_size: buffer size
3203 * @element_count: pointer to count of elements read by FW
3204 * @cmd_details: pointer to command details structure or NULL
3206 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3207 u8 cmd_flags, u32 field_id, void *data,
3208 u16 buf_size, u16 *element_count,
3209 struct i40e_asq_cmd_details *cmd_details)
3211 struct i40e_aq_desc desc;
3212 struct i40e_aqc_nvm_config_read *cmd =
3213 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3214 enum i40e_status_code status;
3216 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3217 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3218 if (buf_size > I40E_AQ_LARGE_BUF)
3219 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3221 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3222 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3223 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3224 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3226 cmd->element_id_msw = 0;
3228 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3230 if (!status && element_count)
3231 *element_count = LE16_TO_CPU(cmd->element_count);
3237 * i40e_aq_write_nvm_config - write an nvm config block
3238 * @hw: pointer to the hw struct
3239 * @cmd_flags: NVM access admin command bits
3240 * @data: buffer for result
3241 * @buf_size: buffer size
3242 * @element_count: count of elements to be written
3243 * @cmd_details: pointer to command details structure or NULL
3245 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3246 u8 cmd_flags, void *data, u16 buf_size,
3248 struct i40e_asq_cmd_details *cmd_details)
3250 struct i40e_aq_desc desc;
3251 struct i40e_aqc_nvm_config_write *cmd =
3252 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3253 enum i40e_status_code status;
3255 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3256 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3257 if (buf_size > I40E_AQ_LARGE_BUF)
3258 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3260 cmd->element_count = CPU_TO_LE16(element_count);
3261 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3262 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3268 * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3269 * @hw: pointer to the hw struct
3270 * @cmd_details: pointer to command details structure or NULL
3272 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3273 void *buff, u16 buff_size,
3274 struct i40e_asq_cmd_details *cmd_details)
3276 struct i40e_aq_desc desc;
3277 enum i40e_status_code status;
3279 UNREFERENCED_2PARAMETER(buff, buff_size);
3281 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3282 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3283 if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3284 status = I40E_ERR_NOT_IMPLEMENTED;
3291 * @hw: pointer to the hw struct
3292 * @module_pointer: module pointer location in words from the NVM beginning
3293 * @offset: offset in the module (expressed in 4 KB from module's beginning)
3294 * @length: length of the section to be erased (expressed in 4 KB)
3295 * @last_command: tells if this is the last command in a series
3296 * @cmd_details: pointer to command details structure or NULL
3298 * Erase the NVM sector using the admin queue commands
3300 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3301 u32 offset, u16 length, bool last_command,
3302 struct i40e_asq_cmd_details *cmd_details)
3304 struct i40e_aq_desc desc;
3305 struct i40e_aqc_nvm_update *cmd =
3306 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3307 enum i40e_status_code status;
3309 DEBUGFUNC("i40e_aq_erase_nvm");
3311 /* In offset the highest byte must be zeroed. */
3312 if (offset & 0xFF000000) {
3313 status = I40E_ERR_PARAM;
3314 goto i40e_aq_erase_nvm_exit;
3317 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3319 /* If this is the last command in a series, set the proper flag. */
3321 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3322 cmd->module_pointer = module_pointer;
3323 cmd->offset = CPU_TO_LE32(offset);
3324 cmd->length = CPU_TO_LE16(length);
3326 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3328 i40e_aq_erase_nvm_exit:
3332 #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
3333 #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
3334 #define I40E_DEV_FUNC_CAP_NPAR 0x03
3335 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04
3336 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
3337 #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
3338 #define I40E_DEV_FUNC_CAP_VF 0x13
3339 #define I40E_DEV_FUNC_CAP_VMDQ 0x14
3340 #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
3341 #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
3342 #define I40E_DEV_FUNC_CAP_VSI 0x17
3343 #define I40E_DEV_FUNC_CAP_DCB 0x18
3344 #define I40E_DEV_FUNC_CAP_FCOE 0x21
3345 #define I40E_DEV_FUNC_CAP_ISCSI 0x22
3346 #define I40E_DEV_FUNC_CAP_RSS 0x40
3347 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
3348 #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
3349 #define I40E_DEV_FUNC_CAP_MSIX 0x43
3350 #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
3351 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
3352 #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
3353 #define I40E_DEV_FUNC_CAP_FLEX10 0xF1
3354 #define I40E_DEV_FUNC_CAP_CEM 0xF2
3355 #define I40E_DEV_FUNC_CAP_IWARP 0x51
3356 #define I40E_DEV_FUNC_CAP_LED 0x61
3357 #define I40E_DEV_FUNC_CAP_SDP 0x62
3358 #define I40E_DEV_FUNC_CAP_MDIO 0x63
3361 * i40e_parse_discover_capabilities
3362 * @hw: pointer to the hw struct
3363 * @buff: pointer to a buffer containing device/function capability records
3364 * @cap_count: number of capability records in the list
3365 * @list_type_opc: type of capabilities list to parse
3367 * Parse the device/function capabilities list.
3369 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3371 enum i40e_admin_queue_opc list_type_opc)
3373 struct i40e_aqc_list_capabilities_element_resp *cap;
3374 u32 valid_functions, num_functions;
3375 u32 number, logical_id, phys_id;
3376 struct i40e_hw_capabilities *p;
3381 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3383 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3384 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3385 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3386 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3390 for (i = 0; i < cap_count; i++, cap++) {
3391 id = LE16_TO_CPU(cap->id);
3392 number = LE32_TO_CPU(cap->number);
3393 logical_id = LE32_TO_CPU(cap->logical_id);
3394 phys_id = LE32_TO_CPU(cap->phys_id);
3395 major_rev = cap->major_rev;
3398 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
3399 p->switch_mode = number;
3401 case I40E_DEV_FUNC_CAP_MGMT_MODE:
3402 p->management_mode = number;
3404 case I40E_DEV_FUNC_CAP_NPAR:
3405 p->npar_enable = number;
3407 case I40E_DEV_FUNC_CAP_OS2BMC:
3410 case I40E_DEV_FUNC_CAP_VALID_FUNC:
3411 p->valid_functions = number;
3413 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
3415 p->sr_iov_1_1 = true;
3417 case I40E_DEV_FUNC_CAP_VF:
3418 p->num_vfs = number;
3419 p->vf_base_id = logical_id;
3421 case I40E_DEV_FUNC_CAP_VMDQ:
3425 case I40E_DEV_FUNC_CAP_802_1_QBG:
3427 p->evb_802_1_qbg = true;
3429 case I40E_DEV_FUNC_CAP_802_1_QBH:
3431 p->evb_802_1_qbh = true;
3433 case I40E_DEV_FUNC_CAP_VSI:
3434 p->num_vsis = number;
3436 case I40E_DEV_FUNC_CAP_DCB:
3439 p->enabled_tcmap = logical_id;
3443 case I40E_DEV_FUNC_CAP_FCOE:
3447 case I40E_DEV_FUNC_CAP_ISCSI:
3451 case I40E_DEV_FUNC_CAP_RSS:
3453 p->rss_table_size = number;
3454 p->rss_table_entry_width = logical_id;
3456 case I40E_DEV_FUNC_CAP_RX_QUEUES:
3457 p->num_rx_qp = number;
3458 p->base_queue = phys_id;
3460 case I40E_DEV_FUNC_CAP_TX_QUEUES:
3461 p->num_tx_qp = number;
3462 p->base_queue = phys_id;
3464 case I40E_DEV_FUNC_CAP_MSIX:
3465 p->num_msix_vectors = number;
3467 case I40E_DEV_FUNC_CAP_MSIX_VF:
3468 p->num_msix_vectors_vf = number;
3470 case I40E_DEV_FUNC_CAP_FLEX10:
3471 if (major_rev == 1) {
3473 p->flex10_enable = true;
3474 p->flex10_capable = true;
3477 /* Capability revision >= 2 */
3479 p->flex10_enable = true;
3481 p->flex10_capable = true;
3483 p->flex10_mode = logical_id;
3484 p->flex10_status = phys_id;
3486 case I40E_DEV_FUNC_CAP_CEM:
3490 case I40E_DEV_FUNC_CAP_IWARP:
3494 case I40E_DEV_FUNC_CAP_LED:
3495 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3496 p->led[phys_id] = true;
3498 case I40E_DEV_FUNC_CAP_SDP:
3499 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3500 p->sdp[phys_id] = true;
3502 case I40E_DEV_FUNC_CAP_MDIO:
3504 p->mdio_port_num = phys_id;
3505 p->mdio_port_mode = logical_id;
3508 case I40E_DEV_FUNC_CAP_IEEE_1588:
3510 p->ieee_1588 = true;
3512 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
3514 p->fd_filters_guaranteed = number;
3515 p->fd_filters_best_effort = logical_id;
3523 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3525 #ifdef I40E_FCOE_ENA
3526 /* Software override ensuring FCoE is disabled if npar or mfp
3527 * mode because it is not supported in these modes.
3529 if (p->npar_enable || p->flex10_enable)
3532 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3536 /* count the enabled ports (aka the "not disabled" ports) */
3538 for (i = 0; i < 4; i++) {
3539 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3542 /* use AQ read to get the physical register offset instead
3543 * of the port relative offset
3545 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3546 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3550 valid_functions = p->valid_functions;
3552 while (valid_functions) {
3553 if (valid_functions & 1)
3555 valid_functions >>= 1;
3558 /* partition id is 1-based, and functions are evenly spread
3559 * across the ports as partitions
3561 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3562 hw->num_partitions = num_functions / hw->num_ports;
3564 /* additional HW specific goodies that might
3565 * someday be HW version specific
3567 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3571 * i40e_aq_discover_capabilities
3572 * @hw: pointer to the hw struct
3573 * @buff: a virtual buffer to hold the capabilities
3574 * @buff_size: Size of the virtual buffer
3575 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3576 * @list_type_opc: capabilities type to discover - pass in the command opcode
3577 * @cmd_details: pointer to command details structure or NULL
3579 * Get the device capabilities descriptions from the firmware
3581 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3582 void *buff, u16 buff_size, u16 *data_size,
3583 enum i40e_admin_queue_opc list_type_opc,
3584 struct i40e_asq_cmd_details *cmd_details)
3586 struct i40e_aqc_list_capabilites *cmd;
3587 struct i40e_aq_desc desc;
3588 enum i40e_status_code status = I40E_SUCCESS;
3590 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3592 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3593 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3594 status = I40E_ERR_PARAM;
3598 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3600 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3601 if (buff_size > I40E_AQ_LARGE_BUF)
3602 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3604 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3605 *data_size = LE16_TO_CPU(desc.datalen);
3610 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3618 * i40e_aq_update_nvm
3619 * @hw: pointer to the hw struct
3620 * @module_pointer: module pointer location in words from the NVM beginning
3621 * @offset: byte offset from the module beginning
3622 * @length: length of the section to be written (in bytes from the offset)
3623 * @data: command buffer (size [bytes] = length)
3624 * @last_command: tells if this is the last command in a series
3625 * @cmd_details: pointer to command details structure or NULL
3627 * Update the NVM using the admin queue commands
3629 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3630 u32 offset, u16 length, void *data,
3632 struct i40e_asq_cmd_details *cmd_details)
3634 struct i40e_aq_desc desc;
3635 struct i40e_aqc_nvm_update *cmd =
3636 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3637 enum i40e_status_code status;
3639 DEBUGFUNC("i40e_aq_update_nvm");
3641 /* In offset the highest byte must be zeroed. */
3642 if (offset & 0xFF000000) {
3643 status = I40E_ERR_PARAM;
3644 goto i40e_aq_update_nvm_exit;
3647 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3649 /* If this is the last command in a series, set the proper flag. */
3651 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3652 cmd->module_pointer = module_pointer;
3653 cmd->offset = CPU_TO_LE32(offset);
3654 cmd->length = CPU_TO_LE16(length);
3656 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3657 if (length > I40E_AQ_LARGE_BUF)
3658 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3660 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3662 i40e_aq_update_nvm_exit:
3667 * i40e_aq_get_lldp_mib
3668 * @hw: pointer to the hw struct
3669 * @bridge_type: type of bridge requested
3670 * @mib_type: Local, Remote or both Local and Remote MIBs
3671 * @buff: pointer to a user supplied buffer to store the MIB block
3672 * @buff_size: size of the buffer (in bytes)
3673 * @local_len : length of the returned Local LLDP MIB
3674 * @remote_len: length of the returned Remote LLDP MIB
3675 * @cmd_details: pointer to command details structure or NULL
3677 * Requests the complete LLDP MIB (entire packet).
3679 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3680 u8 mib_type, void *buff, u16 buff_size,
3681 u16 *local_len, u16 *remote_len,
3682 struct i40e_asq_cmd_details *cmd_details)
3684 struct i40e_aq_desc desc;
3685 struct i40e_aqc_lldp_get_mib *cmd =
3686 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3687 struct i40e_aqc_lldp_get_mib *resp =
3688 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3689 enum i40e_status_code status;
3691 if (buff_size == 0 || !buff)
3692 return I40E_ERR_PARAM;
3694 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3695 /* Indirect Command */
3696 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3698 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3699 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3700 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3702 desc.datalen = CPU_TO_LE16(buff_size);
3704 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3705 if (buff_size > I40E_AQ_LARGE_BUF)
3706 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3708 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3710 if (local_len != NULL)
3711 *local_len = LE16_TO_CPU(resp->local_len);
3712 if (remote_len != NULL)
3713 *remote_len = LE16_TO_CPU(resp->remote_len);
3720 * i40e_aq_set_lldp_mib - Set the LLDP MIB
3721 * @hw: pointer to the hw struct
3722 * @mib_type: Local, Remote or both Local and Remote MIBs
3723 * @buff: pointer to a user supplied buffer to store the MIB block
3724 * @buff_size: size of the buffer (in bytes)
3725 * @cmd_details: pointer to command details structure or NULL
3729 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
3730 u8 mib_type, void *buff, u16 buff_size,
3731 struct i40e_asq_cmd_details *cmd_details)
3733 struct i40e_aq_desc desc;
3734 struct i40e_aqc_lldp_set_local_mib *cmd =
3735 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
3736 enum i40e_status_code status;
3738 if (buff_size == 0 || !buff)
3739 return I40E_ERR_PARAM;
3741 i40e_fill_default_direct_cmd_desc(&desc,
3742 i40e_aqc_opc_lldp_set_local_mib);
3743 /* Indirect Command */
3744 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3745 if (buff_size > I40E_AQ_LARGE_BUF)
3746 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3747 desc.datalen = CPU_TO_LE16(buff_size);
3749 cmd->type = mib_type;
3750 cmd->length = CPU_TO_LE16(buff_size);
3751 cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
3752 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
3754 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3759 * i40e_aq_cfg_lldp_mib_change_event
3760 * @hw: pointer to the hw struct
3761 * @enable_update: Enable or Disable event posting
3762 * @cmd_details: pointer to command details structure or NULL
3764 * Enable or Disable posting of an event on ARQ when LLDP MIB
3765 * associated with the interface changes
3767 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3769 struct i40e_asq_cmd_details *cmd_details)
3771 struct i40e_aq_desc desc;
3772 struct i40e_aqc_lldp_update_mib *cmd =
3773 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3774 enum i40e_status_code status;
3776 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3779 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3781 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3787 * i40e_aq_add_lldp_tlv
3788 * @hw: pointer to the hw struct
3789 * @bridge_type: type of bridge
3790 * @buff: buffer with TLV to add
3791 * @buff_size: length of the buffer
3792 * @tlv_len: length of the TLV to be added
3793 * @mib_len: length of the LLDP MIB returned in response
3794 * @cmd_details: pointer to command details structure or NULL
3796 * Add the specified TLV to LLDP Local MIB for the given bridge type,
3797 * it is responsibility of the caller to make sure that the TLV is not
3798 * already present in the LLDPDU.
3799 * In return firmware will write the complete LLDP MIB with the newly
3800 * added TLV in the response buffer.
3802 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
3803 void *buff, u16 buff_size, u16 tlv_len,
3805 struct i40e_asq_cmd_details *cmd_details)
3807 struct i40e_aq_desc desc;
3808 struct i40e_aqc_lldp_add_tlv *cmd =
3809 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3810 enum i40e_status_code status;
3812 if (buff_size == 0 || !buff || tlv_len == 0)
3813 return I40E_ERR_PARAM;
3815 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
3817 /* Indirect Command */
3818 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3819 if (buff_size > I40E_AQ_LARGE_BUF)
3820 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3821 desc.datalen = CPU_TO_LE16(buff_size);
3823 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3824 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3825 cmd->len = CPU_TO_LE16(tlv_len);
3827 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3829 if (mib_len != NULL)
3830 *mib_len = LE16_TO_CPU(desc.datalen);
3837 * i40e_aq_update_lldp_tlv
3838 * @hw: pointer to the hw struct
3839 * @bridge_type: type of bridge
3840 * @buff: buffer with TLV to update
3841 * @buff_size: size of the buffer holding original and updated TLVs
3842 * @old_len: Length of the Original TLV
3843 * @new_len: Length of the Updated TLV
3844 * @offset: offset of the updated TLV in the buff
3845 * @mib_len: length of the returned LLDP MIB
3846 * @cmd_details: pointer to command details structure or NULL
3848 * Update the specified TLV to the LLDP Local MIB for the given bridge type.
3849 * Firmware will place the complete LLDP MIB in response buffer with the
3852 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
3853 u8 bridge_type, void *buff, u16 buff_size,
3854 u16 old_len, u16 new_len, u16 offset,
3856 struct i40e_asq_cmd_details *cmd_details)
3858 struct i40e_aq_desc desc;
3859 struct i40e_aqc_lldp_update_tlv *cmd =
3860 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
3861 enum i40e_status_code status;
3863 if (buff_size == 0 || !buff || offset == 0 ||
3864 old_len == 0 || new_len == 0)
3865 return I40E_ERR_PARAM;
3867 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
3869 /* Indirect Command */
3870 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3871 if (buff_size > I40E_AQ_LARGE_BUF)
3872 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3873 desc.datalen = CPU_TO_LE16(buff_size);
3875 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3876 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3877 cmd->old_len = CPU_TO_LE16(old_len);
3878 cmd->new_offset = CPU_TO_LE16(offset);
3879 cmd->new_len = CPU_TO_LE16(new_len);
3881 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3883 if (mib_len != NULL)
3884 *mib_len = LE16_TO_CPU(desc.datalen);
3891 * i40e_aq_delete_lldp_tlv
3892 * @hw: pointer to the hw struct
3893 * @bridge_type: type of bridge
3894 * @buff: pointer to a user supplied buffer that has the TLV
3895 * @buff_size: length of the buffer
3896 * @tlv_len: length of the TLV to be deleted
3897 * @mib_len: length of the returned LLDP MIB
3898 * @cmd_details: pointer to command details structure or NULL
3900 * Delete the specified TLV from LLDP Local MIB for the given bridge type.
3901 * The firmware places the entire LLDP MIB in the response buffer.
3903 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
3904 u8 bridge_type, void *buff, u16 buff_size,
3905 u16 tlv_len, u16 *mib_len,
3906 struct i40e_asq_cmd_details *cmd_details)
3908 struct i40e_aq_desc desc;
3909 struct i40e_aqc_lldp_add_tlv *cmd =
3910 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3911 enum i40e_status_code status;
3913 if (buff_size == 0 || !buff)
3914 return I40E_ERR_PARAM;
3916 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
3918 /* Indirect Command */
3919 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3920 if (buff_size > I40E_AQ_LARGE_BUF)
3921 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3922 desc.datalen = CPU_TO_LE16(buff_size);
3923 cmd->len = CPU_TO_LE16(tlv_len);
3924 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3925 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3927 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3929 if (mib_len != NULL)
3930 *mib_len = LE16_TO_CPU(desc.datalen);
3938 * @hw: pointer to the hw struct
3939 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3940 * @cmd_details: pointer to command details structure or NULL
3942 * Stop or Shutdown the embedded LLDP Agent
3944 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3945 struct i40e_asq_cmd_details *cmd_details)
3947 struct i40e_aq_desc desc;
3948 struct i40e_aqc_lldp_stop *cmd =
3949 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3950 enum i40e_status_code status;
3952 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3955 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3957 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3963 * i40e_aq_start_lldp
3964 * @hw: pointer to the hw struct
3965 * @cmd_details: pointer to command details structure or NULL
3967 * Start the embedded LLDP Agent on all ports.
3969 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
3970 struct i40e_asq_cmd_details *cmd_details)
3972 struct i40e_aq_desc desc;
3973 struct i40e_aqc_lldp_start *cmd =
3974 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3975 enum i40e_status_code status;
3977 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3979 cmd->command = I40E_AQ_LLDP_AGENT_START;
3981 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3987 * i40e_aq_get_cee_dcb_config
3988 * @hw: pointer to the hw struct
3989 * @buff: response buffer that stores CEE operational configuration
3990 * @buff_size: size of the buffer passed
3991 * @cmd_details: pointer to command details structure or NULL
3993 * Get CEE DCBX mode operational configuration from firmware
3995 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3996 void *buff, u16 buff_size,
3997 struct i40e_asq_cmd_details *cmd_details)
3999 struct i40e_aq_desc desc;
4000 enum i40e_status_code status;
4002 if (buff_size == 0 || !buff)
4003 return I40E_ERR_PARAM;
4005 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4007 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4008 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4015 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4016 * @hw: pointer to the hw struct
4017 * @start_agent: True if DCBx Agent needs to be Started
4018 * False if DCBx Agent needs to be Stopped
4019 * @cmd_details: pointer to command details structure or NULL
4021 * Start/Stop the embedded dcbx Agent
4023 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4025 struct i40e_asq_cmd_details *cmd_details)
4027 struct i40e_aq_desc desc;
4028 struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4029 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4031 enum i40e_status_code status;
4033 i40e_fill_default_direct_cmd_desc(&desc,
4034 i40e_aqc_opc_lldp_stop_start_spec_agent);
4037 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4039 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4045 * i40e_aq_add_udp_tunnel
4046 * @hw: pointer to the hw struct
4047 * @udp_port: the UDP port to add
4048 * @header_len: length of the tunneling header length in DWords
4049 * @protocol_index: protocol index type
4050 * @filter_index: pointer to filter index
4051 * @cmd_details: pointer to command details structure or NULL
4053 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4054 u16 udp_port, u8 protocol_index,
4056 struct i40e_asq_cmd_details *cmd_details)
4058 struct i40e_aq_desc desc;
4059 struct i40e_aqc_add_udp_tunnel *cmd =
4060 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4061 struct i40e_aqc_del_udp_tunnel_completion *resp =
4062 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4063 enum i40e_status_code status;
4065 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4067 cmd->udp_port = CPU_TO_LE16(udp_port);
4068 cmd->protocol_type = protocol_index;
4070 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4072 if (!status && filter_index)
4073 *filter_index = resp->index;
4079 * i40e_aq_del_udp_tunnel
4080 * @hw: pointer to the hw struct
4081 * @index: filter index
4082 * @cmd_details: pointer to command details structure or NULL
4084 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4085 struct i40e_asq_cmd_details *cmd_details)
4087 struct i40e_aq_desc desc;
4088 struct i40e_aqc_remove_udp_tunnel *cmd =
4089 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4090 enum i40e_status_code status;
4092 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4096 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4102 * i40e_aq_get_switch_resource_alloc (0x0204)
4103 * @hw: pointer to the hw struct
4104 * @num_entries: pointer to u8 to store the number of resource entries returned
4105 * @buf: pointer to a user supplied buffer. This buffer must be large enough
4106 * to store the resource information for all resource types. Each
4107 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
4108 * @count: size, in bytes, of the buffer provided
4109 * @cmd_details: pointer to command details structure or NULL
4111 * Query the resources allocated to a function.
4113 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4115 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4117 struct i40e_asq_cmd_details *cmd_details)
4119 struct i40e_aq_desc desc;
4120 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4121 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4122 enum i40e_status_code status;
4123 u16 length = count * sizeof(*buf);
4125 i40e_fill_default_direct_cmd_desc(&desc,
4126 i40e_aqc_opc_get_switch_resource_alloc);
4128 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4129 if (length > I40E_AQ_LARGE_BUF)
4130 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4132 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4134 if (!status && num_entries)
4135 *num_entries = cmd_resp->num_entries;
4141 * i40e_aq_delete_element - Delete switch element
4142 * @hw: pointer to the hw struct
4143 * @seid: the SEID to delete from the switch
4144 * @cmd_details: pointer to command details structure or NULL
4146 * This deletes a switch element from the switch.
4148 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4149 struct i40e_asq_cmd_details *cmd_details)
4151 struct i40e_aq_desc desc;
4152 struct i40e_aqc_switch_seid *cmd =
4153 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4154 enum i40e_status_code status;
4157 return I40E_ERR_PARAM;
4159 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4161 cmd->seid = CPU_TO_LE16(seid);
4163 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4169 * i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4170 * @hw: pointer to the hw struct
4171 * @flags: component flags
4172 * @mac_seid: uplink seid (MAC SEID)
4173 * @vsi_seid: connected vsi seid
4174 * @ret_seid: seid of create pv component
4176 * This instantiates an i40e port virtualizer with specified flags.
4177 * Depending on specified flags the port virtualizer can act as a
4178 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4180 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4181 u16 mac_seid, u16 vsi_seid,
4184 struct i40e_aq_desc desc;
4185 struct i40e_aqc_add_update_pv *cmd =
4186 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4187 struct i40e_aqc_add_update_pv_completion *resp =
4188 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4189 enum i40e_status_code status;
4192 return I40E_ERR_PARAM;
4194 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4195 cmd->command_flags = CPU_TO_LE16(flags);
4196 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4197 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4199 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4200 if (!status && ret_seid)
4201 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4207 * i40e_aq_add_tag - Add an S/E-tag
4208 * @hw: pointer to the hw struct
4209 * @direct_to_queue: should s-tag direct flow to a specific queue
4210 * @vsi_seid: VSI SEID to use this tag
4211 * @tag: value of the tag
4212 * @queue_num: queue number, only valid is direct_to_queue is true
4213 * @tags_used: return value, number of tags in use by this PF
4214 * @tags_free: return value, number of unallocated tags
4215 * @cmd_details: pointer to command details structure or NULL
4217 * This associates an S- or E-tag to a VSI in the switch complex. It returns
4218 * the number of tags allocated by the PF, and the number of unallocated
4221 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4222 u16 vsi_seid, u16 tag, u16 queue_num,
4223 u16 *tags_used, u16 *tags_free,
4224 struct i40e_asq_cmd_details *cmd_details)
4226 struct i40e_aq_desc desc;
4227 struct i40e_aqc_add_tag *cmd =
4228 (struct i40e_aqc_add_tag *)&desc.params.raw;
4229 struct i40e_aqc_add_remove_tag_completion *resp =
4230 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4231 enum i40e_status_code status;
4234 return I40E_ERR_PARAM;
4236 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4238 cmd->seid = CPU_TO_LE16(vsi_seid);
4239 cmd->tag = CPU_TO_LE16(tag);
4240 if (direct_to_queue) {
4241 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4242 cmd->queue_number = CPU_TO_LE16(queue_num);
4245 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4248 if (tags_used != NULL)
4249 *tags_used = LE16_TO_CPU(resp->tags_used);
4250 if (tags_free != NULL)
4251 *tags_free = LE16_TO_CPU(resp->tags_free);
4258 * i40e_aq_remove_tag - Remove an S- or E-tag
4259 * @hw: pointer to the hw struct
4260 * @vsi_seid: VSI SEID this tag is associated with
4261 * @tag: value of the S-tag to delete
4262 * @tags_used: return value, number of tags in use by this PF
4263 * @tags_free: return value, number of unallocated tags
4264 * @cmd_details: pointer to command details structure or NULL
4266 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
4267 * the number of tags allocated by the PF, and the number of unallocated
4270 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4271 u16 tag, u16 *tags_used, u16 *tags_free,
4272 struct i40e_asq_cmd_details *cmd_details)
4274 struct i40e_aq_desc desc;
4275 struct i40e_aqc_remove_tag *cmd =
4276 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4277 struct i40e_aqc_add_remove_tag_completion *resp =
4278 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4279 enum i40e_status_code status;
4282 return I40E_ERR_PARAM;
4284 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4286 cmd->seid = CPU_TO_LE16(vsi_seid);
4287 cmd->tag = CPU_TO_LE16(tag);
4289 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4292 if (tags_used != NULL)
4293 *tags_used = LE16_TO_CPU(resp->tags_used);
4294 if (tags_free != NULL)
4295 *tags_free = LE16_TO_CPU(resp->tags_free);
4302 * i40e_aq_add_mcast_etag - Add a multicast E-tag
4303 * @hw: pointer to the hw struct
4304 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4305 * @etag: value of E-tag to add
4306 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4307 * @buf: address of indirect buffer
4308 * @tags_used: return value, number of E-tags in use by this port
4309 * @tags_free: return value, number of unallocated M-tags
4310 * @cmd_details: pointer to command details structure or NULL
4312 * This associates a multicast E-tag to a port virtualizer. It will return
4313 * the number of tags allocated by the PF, and the number of unallocated
4316 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4317 * num_tags_in_buf long.
4319 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4320 u16 etag, u8 num_tags_in_buf, void *buf,
4321 u16 *tags_used, u16 *tags_free,
4322 struct i40e_asq_cmd_details *cmd_details)
4324 struct i40e_aq_desc desc;
4325 struct i40e_aqc_add_remove_mcast_etag *cmd =
4326 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4327 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4328 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4329 enum i40e_status_code status;
4330 u16 length = sizeof(u16) * num_tags_in_buf;
4332 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4333 return I40E_ERR_PARAM;
4335 i40e_fill_default_direct_cmd_desc(&desc,
4336 i40e_aqc_opc_add_multicast_etag);
4338 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4339 cmd->etag = CPU_TO_LE16(etag);
4340 cmd->num_unicast_etags = num_tags_in_buf;
4342 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4343 if (length > I40E_AQ_LARGE_BUF)
4344 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4346 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4349 if (tags_used != NULL)
4350 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4351 if (tags_free != NULL)
4352 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4359 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4360 * @hw: pointer to the hw struct
4361 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4362 * @etag: value of the E-tag to remove
4363 * @tags_used: return value, number of tags in use by this port
4364 * @tags_free: return value, number of unallocated tags
4365 * @cmd_details: pointer to command details structure or NULL
4367 * This deletes an E-tag from the port virtualizer. It will return
4368 * the number of tags allocated by the port, and the number of unallocated
4371 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4372 u16 etag, u16 *tags_used, u16 *tags_free,
4373 struct i40e_asq_cmd_details *cmd_details)
4375 struct i40e_aq_desc desc;
4376 struct i40e_aqc_add_remove_mcast_etag *cmd =
4377 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4378 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4379 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4380 enum i40e_status_code status;
4384 return I40E_ERR_PARAM;
4386 i40e_fill_default_direct_cmd_desc(&desc,
4387 i40e_aqc_opc_remove_multicast_etag);
4389 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4390 cmd->etag = CPU_TO_LE16(etag);
4392 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4395 if (tags_used != NULL)
4396 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4397 if (tags_free != NULL)
4398 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4405 * i40e_aq_update_tag - Update an S/E-tag
4406 * @hw: pointer to the hw struct
4407 * @vsi_seid: VSI SEID using this S-tag
4408 * @old_tag: old tag value
4409 * @new_tag: new tag value
4410 * @tags_used: return value, number of tags in use by this PF
4411 * @tags_free: return value, number of unallocated tags
4412 * @cmd_details: pointer to command details structure or NULL
4414 * This updates the value of the tag currently attached to this VSI
4415 * in the switch complex. It will return the number of tags allocated
4416 * by the PF, and the number of unallocated tags available.
4418 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4419 u16 old_tag, u16 new_tag, u16 *tags_used,
4421 struct i40e_asq_cmd_details *cmd_details)
4423 struct i40e_aq_desc desc;
4424 struct i40e_aqc_update_tag *cmd =
4425 (struct i40e_aqc_update_tag *)&desc.params.raw;
4426 struct i40e_aqc_update_tag_completion *resp =
4427 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4428 enum i40e_status_code status;
4431 return I40E_ERR_PARAM;
4433 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4435 cmd->seid = CPU_TO_LE16(vsi_seid);
4436 cmd->old_tag = CPU_TO_LE16(old_tag);
4437 cmd->new_tag = CPU_TO_LE16(new_tag);
4439 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4442 if (tags_used != NULL)
4443 *tags_used = LE16_TO_CPU(resp->tags_used);
4444 if (tags_free != NULL)
4445 *tags_free = LE16_TO_CPU(resp->tags_free);
4452 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4453 * @hw: pointer to the hw struct
4454 * @tcmap: TC map for request/release any ignore PFC condition
4455 * @request: request or release ignore PFC condition
4456 * @tcmap_ret: return TCs for which PFC is currently ignored
4457 * @cmd_details: pointer to command details structure or NULL
4459 * This sends out request/release to ignore PFC condition for a TC.
4460 * It will return the TCs for which PFC is currently ignored.
4462 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4463 bool request, u8 *tcmap_ret,
4464 struct i40e_asq_cmd_details *cmd_details)
4466 struct i40e_aq_desc desc;
4467 struct i40e_aqc_pfc_ignore *cmd_resp =
4468 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4469 enum i40e_status_code status;
4471 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4474 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4476 cmd_resp->tc_bitmap = tcmap;
4478 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4481 if (tcmap_ret != NULL)
4482 *tcmap_ret = cmd_resp->tc_bitmap;
4489 * i40e_aq_dcb_updated - DCB Updated Command
4490 * @hw: pointer to the hw struct
4491 * @cmd_details: pointer to command details structure or NULL
4493 * When LLDP is handled in PF this command is used by the PF
4494 * to notify EMP that a DCB setting is modified.
4495 * When LLDP is handled in EMP this command is used by the PF
4496 * to notify EMP whenever one of the following parameters get
4498 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4499 * - PCIRTT in PRTDCB_GENC.PCIRTT
4500 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4501 * EMP will return when the shared RPB settings have been
4502 * recomputed and modified. The retval field in the descriptor
4503 * will be set to 0 when RPB is modified.
4505 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4506 struct i40e_asq_cmd_details *cmd_details)
4508 struct i40e_aq_desc desc;
4509 enum i40e_status_code status;
4511 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4513 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4519 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4520 * @hw: pointer to the hw struct
4521 * @seid: defines the SEID of the switch for which the stats are requested
4522 * @vlan_id: the VLAN ID for which the statistics are requested
4523 * @stat_index: index of the statistics counters block assigned to this VLAN
4524 * @cmd_details: pointer to command details structure or NULL
4526 * XL710 supports 128 smonVlanStats counters.This command is used to
4527 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4530 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4531 u16 vlan_id, u16 *stat_index,
4532 struct i40e_asq_cmd_details *cmd_details)
4534 struct i40e_aq_desc desc;
4535 struct i40e_aqc_add_remove_statistics *cmd_resp =
4536 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4537 enum i40e_status_code status;
4539 if ((seid == 0) || (stat_index == NULL))
4540 return I40E_ERR_PARAM;
4542 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4544 cmd_resp->seid = CPU_TO_LE16(seid);
4545 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4547 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4549 if (!status && stat_index)
4550 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4556 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4557 * @hw: pointer to the hw struct
4558 * @seid: defines the SEID of the switch for which the stats are requested
4559 * @vlan_id: the VLAN ID for which the statistics are requested
4560 * @stat_index: index of the statistics counters block assigned to this VLAN
4561 * @cmd_details: pointer to command details structure or NULL
4563 * XL710 supports 128 smonVlanStats counters.This command is used to
4564 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4567 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4568 u16 vlan_id, u16 stat_index,
4569 struct i40e_asq_cmd_details *cmd_details)
4571 struct i40e_aq_desc desc;
4572 struct i40e_aqc_add_remove_statistics *cmd =
4573 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4574 enum i40e_status_code status;
4577 return I40E_ERR_PARAM;
4579 i40e_fill_default_direct_cmd_desc(&desc,
4580 i40e_aqc_opc_remove_statistics);
4582 cmd->seid = CPU_TO_LE16(seid);
4583 cmd->vlan = CPU_TO_LE16(vlan_id);
4584 cmd->stat_index = CPU_TO_LE16(stat_index);
4586 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4592 * i40e_aq_set_port_parameters - set physical port parameters.
4593 * @hw: pointer to the hw struct
4594 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4595 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4596 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4597 * @double_vlan: if set double VLAN is enabled
4598 * @cmd_details: pointer to command details structure or NULL
4600 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4601 u16 bad_frame_vsi, bool save_bad_pac,
4602 bool pad_short_pac, bool double_vlan,
4603 struct i40e_asq_cmd_details *cmd_details)
4605 struct i40e_aqc_set_port_parameters *cmd;
4606 enum i40e_status_code status;
4607 struct i40e_aq_desc desc;
4608 u16 command_flags = 0;
4610 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4612 i40e_fill_default_direct_cmd_desc(&desc,
4613 i40e_aqc_opc_set_port_parameters);
4615 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4617 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4619 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4621 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4622 cmd->command_flags = CPU_TO_LE16(command_flags);
4624 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4630 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
4631 * @hw: pointer to the hw struct
4632 * @seid: seid for the physical port/switching component/vsi
4633 * @buff: Indirect buffer to hold data parameters and response
4634 * @buff_size: Indirect buffer size
4635 * @opcode: Tx scheduler AQ command opcode
4636 * @cmd_details: pointer to command details structure or NULL
4638 * Generic command handler for Tx scheduler AQ commands
4640 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
4641 void *buff, u16 buff_size,
4642 enum i40e_admin_queue_opc opcode,
4643 struct i40e_asq_cmd_details *cmd_details)
4645 struct i40e_aq_desc desc;
4646 struct i40e_aqc_tx_sched_ind *cmd =
4647 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4648 enum i40e_status_code status;
4649 bool cmd_param_flag = false;
4652 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
4653 case i40e_aqc_opc_configure_vsi_tc_bw:
4654 case i40e_aqc_opc_enable_switching_comp_ets:
4655 case i40e_aqc_opc_modify_switching_comp_ets:
4656 case i40e_aqc_opc_disable_switching_comp_ets:
4657 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
4658 case i40e_aqc_opc_configure_switching_comp_bw_config:
4659 cmd_param_flag = true;
4661 case i40e_aqc_opc_query_vsi_bw_config:
4662 case i40e_aqc_opc_query_vsi_ets_sla_config:
4663 case i40e_aqc_opc_query_switching_comp_ets_config:
4664 case i40e_aqc_opc_query_port_ets_config:
4665 case i40e_aqc_opc_query_switching_comp_bw_config:
4666 cmd_param_flag = false;
4669 return I40E_ERR_PARAM;
4672 i40e_fill_default_direct_cmd_desc(&desc, opcode);
4674 /* Indirect command */
4675 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4677 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4678 if (buff_size > I40E_AQ_LARGE_BUF)
4679 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4681 desc.datalen = CPU_TO_LE16(buff_size);
4683 cmd->vsi_seid = CPU_TO_LE16(seid);
4685 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4691 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
4692 * @hw: pointer to the hw struct
4694 * @credit: BW limit credits (0 = disabled)
4695 * @max_credit: Max BW limit credits
4696 * @cmd_details: pointer to command details structure or NULL
4698 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
4699 u16 seid, u16 credit, u8 max_credit,
4700 struct i40e_asq_cmd_details *cmd_details)
4702 struct i40e_aq_desc desc;
4703 struct i40e_aqc_configure_vsi_bw_limit *cmd =
4704 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
4705 enum i40e_status_code status;
4707 i40e_fill_default_direct_cmd_desc(&desc,
4708 i40e_aqc_opc_configure_vsi_bw_limit);
4710 cmd->vsi_seid = CPU_TO_LE16(seid);
4711 cmd->credit = CPU_TO_LE16(credit);
4712 cmd->max_credit = max_credit;
4714 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4720 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
4721 * @hw: pointer to the hw struct
4722 * @seid: switching component seid
4723 * @credit: BW limit credits (0 = disabled)
4724 * @max_bw: Max BW limit credits
4725 * @cmd_details: pointer to command details structure or NULL
4727 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
4728 u16 seid, u16 credit, u8 max_bw,
4729 struct i40e_asq_cmd_details *cmd_details)
4731 struct i40e_aq_desc desc;
4732 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
4733 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
4734 enum i40e_status_code status;
4736 i40e_fill_default_direct_cmd_desc(&desc,
4737 i40e_aqc_opc_configure_switching_comp_bw_limit);
4739 cmd->seid = CPU_TO_LE16(seid);
4740 cmd->credit = CPU_TO_LE16(credit);
4741 cmd->max_bw = max_bw;
4743 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4749 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
4750 * @hw: pointer to the hw struct
4752 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4753 * @cmd_details: pointer to command details structure or NULL
4755 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
4757 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
4758 struct i40e_asq_cmd_details *cmd_details)
4760 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4761 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
4766 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
4767 * @hw: pointer to the hw struct
4769 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
4770 * @cmd_details: pointer to command details structure or NULL
4772 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
4774 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
4775 struct i40e_asq_cmd_details *cmd_details)
4777 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4778 i40e_aqc_opc_configure_vsi_tc_bw,
4783 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
4784 * @hw: pointer to the hw struct
4785 * @seid: seid of the switching component connected to Physical Port
4786 * @ets_data: Buffer holding ETS parameters
4787 * @cmd_details: pointer to command details structure or NULL
4789 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
4791 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
4792 enum i40e_admin_queue_opc opcode,
4793 struct i40e_asq_cmd_details *cmd_details)
4795 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
4796 sizeof(*ets_data), opcode, cmd_details);
4800 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
4801 * @hw: pointer to the hw struct
4802 * @seid: seid of the switching component
4803 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
4804 * @cmd_details: pointer to command details structure or NULL
4806 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
4808 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
4809 struct i40e_asq_cmd_details *cmd_details)
4811 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4812 i40e_aqc_opc_configure_switching_comp_bw_config,
4817 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
4818 * @hw: pointer to the hw struct
4819 * @seid: seid of the switching component
4820 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4821 * @cmd_details: pointer to command details structure or NULL
4823 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
4824 struct i40e_hw *hw, u16 seid,
4825 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
4826 struct i40e_asq_cmd_details *cmd_details)
4828 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4829 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
4834 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
4835 * @hw: pointer to the hw struct
4836 * @seid: seid of the VSI
4837 * @bw_data: Buffer to hold VSI BW configuration
4838 * @cmd_details: pointer to command details structure or NULL
4840 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
4842 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
4843 struct i40e_asq_cmd_details *cmd_details)
4845 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4846 i40e_aqc_opc_query_vsi_bw_config,
4851 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
4852 * @hw: pointer to the hw struct
4853 * @seid: seid of the VSI
4854 * @bw_data: Buffer to hold VSI BW configuration per TC
4855 * @cmd_details: pointer to command details structure or NULL
4857 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
4859 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
4860 struct i40e_asq_cmd_details *cmd_details)
4862 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4863 i40e_aqc_opc_query_vsi_ets_sla_config,
4868 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
4869 * @hw: pointer to the hw struct
4870 * @seid: seid of the switching component
4871 * @bw_data: Buffer to hold switching component's per TC BW config
4872 * @cmd_details: pointer to command details structure or NULL
4874 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
4876 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
4877 struct i40e_asq_cmd_details *cmd_details)
4879 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4880 i40e_aqc_opc_query_switching_comp_ets_config,
4885 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
4886 * @hw: pointer to the hw struct
4887 * @seid: seid of the VSI or switching component connected to Physical Port
4888 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
4889 * @cmd_details: pointer to command details structure or NULL
4891 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
4893 struct i40e_aqc_query_port_ets_config_resp *bw_data,
4894 struct i40e_asq_cmd_details *cmd_details)
4896 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4897 i40e_aqc_opc_query_port_ets_config,
4902 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
4903 * @hw: pointer to the hw struct
4904 * @seid: seid of the switching component
4905 * @bw_data: Buffer to hold switching component's BW configuration
4906 * @cmd_details: pointer to command details structure or NULL
4908 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
4910 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
4911 struct i40e_asq_cmd_details *cmd_details)
4913 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4914 i40e_aqc_opc_query_switching_comp_bw_config,
4919 * i40e_validate_filter_settings
4920 * @hw: pointer to the hardware structure
4921 * @settings: Filter control settings
4923 * Check and validate the filter control settings passed.
4924 * The function checks for the valid filter/context sizes being
4925 * passed for FCoE and PE.
4927 * Returns I40E_SUCCESS if the values passed are valid and within
4928 * range else returns an error.
4930 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
4931 struct i40e_filter_control_settings *settings)
4933 u32 fcoe_cntx_size, fcoe_filt_size;
4934 u32 pe_cntx_size, pe_filt_size;
4939 /* Validate FCoE settings passed */
4940 switch (settings->fcoe_filt_num) {
4941 case I40E_HASH_FILTER_SIZE_1K:
4942 case I40E_HASH_FILTER_SIZE_2K:
4943 case I40E_HASH_FILTER_SIZE_4K:
4944 case I40E_HASH_FILTER_SIZE_8K:
4945 case I40E_HASH_FILTER_SIZE_16K:
4946 case I40E_HASH_FILTER_SIZE_32K:
4947 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4948 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
4951 return I40E_ERR_PARAM;
4954 switch (settings->fcoe_cntx_num) {
4955 case I40E_DMA_CNTX_SIZE_512:
4956 case I40E_DMA_CNTX_SIZE_1K:
4957 case I40E_DMA_CNTX_SIZE_2K:
4958 case I40E_DMA_CNTX_SIZE_4K:
4959 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4960 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
4963 return I40E_ERR_PARAM;
4966 /* Validate PE settings passed */
4967 switch (settings->pe_filt_num) {
4968 case I40E_HASH_FILTER_SIZE_1K:
4969 case I40E_HASH_FILTER_SIZE_2K:
4970 case I40E_HASH_FILTER_SIZE_4K:
4971 case I40E_HASH_FILTER_SIZE_8K:
4972 case I40E_HASH_FILTER_SIZE_16K:
4973 case I40E_HASH_FILTER_SIZE_32K:
4974 case I40E_HASH_FILTER_SIZE_64K:
4975 case I40E_HASH_FILTER_SIZE_128K:
4976 case I40E_HASH_FILTER_SIZE_256K:
4977 case I40E_HASH_FILTER_SIZE_512K:
4978 case I40E_HASH_FILTER_SIZE_1M:
4979 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4980 pe_filt_size <<= (u32)settings->pe_filt_num;
4983 return I40E_ERR_PARAM;
4986 switch (settings->pe_cntx_num) {
4987 case I40E_DMA_CNTX_SIZE_512:
4988 case I40E_DMA_CNTX_SIZE_1K:
4989 case I40E_DMA_CNTX_SIZE_2K:
4990 case I40E_DMA_CNTX_SIZE_4K:
4991 case I40E_DMA_CNTX_SIZE_8K:
4992 case I40E_DMA_CNTX_SIZE_16K:
4993 case I40E_DMA_CNTX_SIZE_32K:
4994 case I40E_DMA_CNTX_SIZE_64K:
4995 case I40E_DMA_CNTX_SIZE_128K:
4996 case I40E_DMA_CNTX_SIZE_256K:
4997 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4998 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5001 return I40E_ERR_PARAM;
5004 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5005 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5006 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5007 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5008 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
5009 return I40E_ERR_INVALID_SIZE;
5011 return I40E_SUCCESS;
5015 * i40e_set_filter_control
5016 * @hw: pointer to the hardware structure
5017 * @settings: Filter control settings
5019 * Set the Queue Filters for PE/FCoE and enable filters required
5020 * for a single PF. It is expected that these settings are programmed
5021 * at the driver initialization time.
5023 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5024 struct i40e_filter_control_settings *settings)
5026 enum i40e_status_code ret = I40E_SUCCESS;
5027 u32 hash_lut_size = 0;
5031 return I40E_ERR_PARAM;
5033 /* Validate the input settings */
5034 ret = i40e_validate_filter_settings(hw, settings);
5038 /* Read the PF Queue Filter control register */
5039 val = rd32(hw, I40E_PFQF_CTL_0);
5041 /* Program required PE hash buckets for the PF */
5042 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5043 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5044 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5045 /* Program required PE contexts for the PF */
5046 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5047 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5048 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5050 /* Program required FCoE hash buckets for the PF */
5051 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5052 val |= ((u32)settings->fcoe_filt_num <<
5053 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5054 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5055 /* Program required FCoE DDP contexts for the PF */
5056 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5057 val |= ((u32)settings->fcoe_cntx_num <<
5058 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5059 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5061 /* Program Hash LUT size for the PF */
5062 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5063 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5065 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5066 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5068 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5069 if (settings->enable_fdir)
5070 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5071 if (settings->enable_ethtype)
5072 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5073 if (settings->enable_macvlan)
5074 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5076 wr32(hw, I40E_PFQF_CTL_0, val);
5078 return I40E_SUCCESS;
5082 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5083 * @hw: pointer to the hw struct
5084 * @mac_addr: MAC address to use in the filter
5085 * @ethtype: Ethertype to use in the filter
5086 * @flags: Flags that needs to be applied to the filter
5087 * @vsi_seid: seid of the control VSI
5088 * @queue: VSI queue number to send the packet to
5089 * @is_add: Add control packet filter if True else remove
5090 * @stats: Structure to hold information on control filter counts
5091 * @cmd_details: pointer to command details structure or NULL
5093 * This command will Add or Remove control packet filter for a control VSI.
5094 * In return it will update the total number of perfect filter count in
5097 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5098 u8 *mac_addr, u16 ethtype, u16 flags,
5099 u16 vsi_seid, u16 queue, bool is_add,
5100 struct i40e_control_filter_stats *stats,
5101 struct i40e_asq_cmd_details *cmd_details)
5103 struct i40e_aq_desc desc;
5104 struct i40e_aqc_add_remove_control_packet_filter *cmd =
5105 (struct i40e_aqc_add_remove_control_packet_filter *)
5107 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5108 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5110 enum i40e_status_code status;
5113 return I40E_ERR_PARAM;
5116 i40e_fill_default_direct_cmd_desc(&desc,
5117 i40e_aqc_opc_add_control_packet_filter);
5118 cmd->queue = CPU_TO_LE16(queue);
5120 i40e_fill_default_direct_cmd_desc(&desc,
5121 i40e_aqc_opc_remove_control_packet_filter);
5125 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
5126 I40E_NONDMA_TO_NONDMA);
5128 cmd->etype = CPU_TO_LE16(ethtype);
5129 cmd->flags = CPU_TO_LE16(flags);
5130 cmd->seid = CPU_TO_LE16(vsi_seid);
5132 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5134 if (!status && stats) {
5135 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5136 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5137 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5138 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5145 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5146 * @hw: pointer to the hw struct
5147 * @seid: VSI seid to add ethertype filter from
5149 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5150 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5153 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5154 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5155 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5156 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5157 enum i40e_status_code status;
5159 status = i40e_aq_add_rem_control_packet_filter(hw, 0, ethtype, flag,
5160 seid, 0, true, NULL,
5163 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5167 * i40e_aq_add_cloud_filters
5168 * @hw: pointer to the hardware structure
5169 * @seid: VSI seid to add cloud filters from
5170 * @filters: Buffer which contains the filters to be added
5171 * @filter_count: number of filters contained in the buffer
5173 * Set the cloud filters for a given VSI. The contents of the
5174 * i40e_aqc_add_remove_cloud_filters_element_data are filled
5175 * in by the caller of the function.
5178 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5180 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5183 struct i40e_aq_desc desc;
5184 struct i40e_aqc_add_remove_cloud_filters *cmd =
5185 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5187 enum i40e_status_code status;
5189 i40e_fill_default_direct_cmd_desc(&desc,
5190 i40e_aqc_opc_add_cloud_filters);
5192 buff_len = filter_count * sizeof(*filters);
5193 desc.datalen = CPU_TO_LE16(buff_len);
5194 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5195 cmd->num_filters = filter_count;
5196 cmd->seid = CPU_TO_LE16(seid);
5198 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5204 * i40e_aq_remove_cloud_filters
5205 * @hw: pointer to the hardware structure
5206 * @seid: VSI seid to remove cloud filters from
5207 * @filters: Buffer which contains the filters to be removed
5208 * @filter_count: number of filters contained in the buffer
5210 * Remove the cloud filters for a given VSI. The contents of the
5211 * i40e_aqc_add_remove_cloud_filters_element_data are filled
5212 * in by the caller of the function.
5215 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5217 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5220 struct i40e_aq_desc desc;
5221 struct i40e_aqc_add_remove_cloud_filters *cmd =
5222 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5223 enum i40e_status_code status;
5226 i40e_fill_default_direct_cmd_desc(&desc,
5227 i40e_aqc_opc_remove_cloud_filters);
5229 buff_len = filter_count * sizeof(*filters);
5230 desc.datalen = CPU_TO_LE16(buff_len);
5231 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5232 cmd->num_filters = filter_count;
5233 cmd->seid = CPU_TO_LE16(seid);
5235 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5241 * i40e_aq_alternate_write
5242 * @hw: pointer to the hardware structure
5243 * @reg_addr0: address of first dword to be read
5244 * @reg_val0: value to be written under 'reg_addr0'
5245 * @reg_addr1: address of second dword to be read
5246 * @reg_val1: value to be written under 'reg_addr1'
5248 * Write one or two dwords to alternate structure. Fields are indicated
5249 * by 'reg_addr0' and 'reg_addr1' register numbers.
5252 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5253 u32 reg_addr0, u32 reg_val0,
5254 u32 reg_addr1, u32 reg_val1)
5256 struct i40e_aq_desc desc;
5257 struct i40e_aqc_alternate_write *cmd_resp =
5258 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5259 enum i40e_status_code status;
5261 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5262 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5263 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5264 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5265 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5267 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5273 * i40e_aq_alternate_write_indirect
5274 * @hw: pointer to the hardware structure
5275 * @addr: address of a first register to be modified
5276 * @dw_count: number of alternate structure fields to write
5277 * @buffer: pointer to the command buffer
5279 * Write 'dw_count' dwords from 'buffer' to alternate structure
5280 * starting at 'addr'.
5283 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5284 u32 addr, u32 dw_count, void *buffer)
5286 struct i40e_aq_desc desc;
5287 struct i40e_aqc_alternate_ind_write *cmd_resp =
5288 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5289 enum i40e_status_code status;
5292 return I40E_ERR_PARAM;
5294 /* Indirect command */
5295 i40e_fill_default_direct_cmd_desc(&desc,
5296 i40e_aqc_opc_alternate_write_indirect);
5298 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5299 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5300 if (dw_count > (I40E_AQ_LARGE_BUF/4))
5301 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5303 cmd_resp->address = CPU_TO_LE32(addr);
5304 cmd_resp->length = CPU_TO_LE32(dw_count);
5306 status = i40e_asq_send_command(hw, &desc, buffer,
5307 I40E_LO_DWORD(4*dw_count), NULL);
5313 * i40e_aq_alternate_read
5314 * @hw: pointer to the hardware structure
5315 * @reg_addr0: address of first dword to be read
5316 * @reg_val0: pointer for data read from 'reg_addr0'
5317 * @reg_addr1: address of second dword to be read
5318 * @reg_val1: pointer for data read from 'reg_addr1'
5320 * Read one or two dwords from alternate structure. Fields are indicated
5321 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5322 * is not passed then only register at 'reg_addr0' is read.
5325 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5326 u32 reg_addr0, u32 *reg_val0,
5327 u32 reg_addr1, u32 *reg_val1)
5329 struct i40e_aq_desc desc;
5330 struct i40e_aqc_alternate_write *cmd_resp =
5331 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5332 enum i40e_status_code status;
5334 if (reg_val0 == NULL)
5335 return I40E_ERR_PARAM;
5337 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5338 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5339 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5341 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5343 if (status == I40E_SUCCESS) {
5344 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5346 if (reg_val1 != NULL)
5347 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5354 * i40e_aq_alternate_read_indirect
5355 * @hw: pointer to the hardware structure
5356 * @addr: address of the alternate structure field
5357 * @dw_count: number of alternate structure fields to read
5358 * @buffer: pointer to the command buffer
5360 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5361 * place them in 'buffer'. The buffer should be allocated by caller.
5364 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5365 u32 addr, u32 dw_count, void *buffer)
5367 struct i40e_aq_desc desc;
5368 struct i40e_aqc_alternate_ind_write *cmd_resp =
5369 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5370 enum i40e_status_code status;
5373 return I40E_ERR_PARAM;
5375 /* Indirect command */
5376 i40e_fill_default_direct_cmd_desc(&desc,
5377 i40e_aqc_opc_alternate_read_indirect);
5379 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5380 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5381 if (dw_count > (I40E_AQ_LARGE_BUF/4))
5382 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5384 cmd_resp->address = CPU_TO_LE32(addr);
5385 cmd_resp->length = CPU_TO_LE32(dw_count);
5387 status = i40e_asq_send_command(hw, &desc, buffer,
5388 I40E_LO_DWORD(4*dw_count), NULL);
5394 * i40e_aq_alternate_clear
5395 * @hw: pointer to the HW structure.
5397 * Clear the alternate structures of the port from which the function
5401 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5403 struct i40e_aq_desc desc;
5404 enum i40e_status_code status;
5406 i40e_fill_default_direct_cmd_desc(&desc,
5407 i40e_aqc_opc_alternate_clear_port);
5409 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5415 * i40e_aq_alternate_write_done
5416 * @hw: pointer to the HW structure.
5417 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
5418 * @reset_needed: indicates the SW should trigger GLOBAL reset
5420 * Indicates to the FW that alternate structures have been changed.
5423 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
5424 u8 bios_mode, bool *reset_needed)
5426 struct i40e_aq_desc desc;
5427 struct i40e_aqc_alternate_write_done *cmd =
5428 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5429 enum i40e_status_code status;
5431 if (reset_needed == NULL)
5432 return I40E_ERR_PARAM;
5434 i40e_fill_default_direct_cmd_desc(&desc,
5435 i40e_aqc_opc_alternate_write_done);
5437 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
5439 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5440 if (!status && reset_needed)
5441 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
5442 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
5448 * i40e_aq_set_oem_mode
5449 * @hw: pointer to the HW structure.
5450 * @oem_mode: the OEM mode to be used
5452 * Sets the device to a specific operating mode. Currently the only supported
5453 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
5456 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
5459 struct i40e_aq_desc desc;
5460 struct i40e_aqc_alternate_write_done *cmd =
5461 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5462 enum i40e_status_code status;
5464 i40e_fill_default_direct_cmd_desc(&desc,
5465 i40e_aqc_opc_alternate_set_mode);
5467 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
5469 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5475 * i40e_aq_resume_port_tx
5476 * @hw: pointer to the hardware structure
5477 * @cmd_details: pointer to command details structure or NULL
5479 * Resume port's Tx traffic
5481 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
5482 struct i40e_asq_cmd_details *cmd_details)
5484 struct i40e_aq_desc desc;
5485 enum i40e_status_code status;
5487 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
5489 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5495 * i40e_set_pci_config_data - store PCI bus info
5496 * @hw: pointer to hardware structure
5497 * @link_status: the link status word from PCI config space
5499 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
5501 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
5503 hw->bus.type = i40e_bus_type_pci_express;
5505 switch (link_status & I40E_PCI_LINK_WIDTH) {
5506 case I40E_PCI_LINK_WIDTH_1:
5507 hw->bus.width = i40e_bus_width_pcie_x1;
5509 case I40E_PCI_LINK_WIDTH_2:
5510 hw->bus.width = i40e_bus_width_pcie_x2;
5512 case I40E_PCI_LINK_WIDTH_4:
5513 hw->bus.width = i40e_bus_width_pcie_x4;
5515 case I40E_PCI_LINK_WIDTH_8:
5516 hw->bus.width = i40e_bus_width_pcie_x8;
5519 hw->bus.width = i40e_bus_width_unknown;
5523 switch (link_status & I40E_PCI_LINK_SPEED) {
5524 case I40E_PCI_LINK_SPEED_2500:
5525 hw->bus.speed = i40e_bus_speed_2500;
5527 case I40E_PCI_LINK_SPEED_5000:
5528 hw->bus.speed = i40e_bus_speed_5000;
5530 case I40E_PCI_LINK_SPEED_8000:
5531 hw->bus.speed = i40e_bus_speed_8000;
5534 hw->bus.speed = i40e_bus_speed_unknown;
5540 * i40e_aq_debug_dump
5541 * @hw: pointer to the hardware structure
5542 * @cluster_id: specific cluster to dump
5543 * @table_id: table id within cluster
5544 * @start_index: index of line in the block to read
5545 * @buff_size: dump buffer size
5546 * @buff: dump buffer
5547 * @ret_buff_size: actual buffer size returned
5548 * @ret_next_table: next block to read
5549 * @ret_next_index: next index to read
5551 * Dump internal FW/HW data for debug purposes.
5554 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
5555 u8 table_id, u32 start_index, u16 buff_size,
5556 void *buff, u16 *ret_buff_size,
5557 u8 *ret_next_table, u32 *ret_next_index,
5558 struct i40e_asq_cmd_details *cmd_details)
5560 struct i40e_aq_desc desc;
5561 struct i40e_aqc_debug_dump_internals *cmd =
5562 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5563 struct i40e_aqc_debug_dump_internals *resp =
5564 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5565 enum i40e_status_code status;
5567 if (buff_size == 0 || !buff)
5568 return I40E_ERR_PARAM;
5570 i40e_fill_default_direct_cmd_desc(&desc,
5571 i40e_aqc_opc_debug_dump_internals);
5572 /* Indirect Command */
5573 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5574 if (buff_size > I40E_AQ_LARGE_BUF)
5575 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5577 cmd->cluster_id = cluster_id;
5578 cmd->table_id = table_id;
5579 cmd->idx = CPU_TO_LE32(start_index);
5581 desc.datalen = CPU_TO_LE16(buff_size);
5583 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5585 if (ret_buff_size != NULL)
5586 *ret_buff_size = LE16_TO_CPU(desc.datalen);
5587 if (ret_next_table != NULL)
5588 *ret_next_table = resp->table_id;
5589 if (ret_next_index != NULL)
5590 *ret_next_index = LE32_TO_CPU(resp->idx);
5597 * i40e_read_bw_from_alt_ram
5598 * @hw: pointer to the hardware structure
5599 * @max_bw: pointer for max_bw read
5600 * @min_bw: pointer for min_bw read
5601 * @min_valid: pointer for bool that is true if min_bw is a valid value
5602 * @max_valid: pointer for bool that is true if max_bw is a valid value
5604 * Read bw from the alternate ram for the given pf
5606 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
5607 u32 *max_bw, u32 *min_bw,
5608 bool *min_valid, bool *max_valid)
5610 enum i40e_status_code status;
5611 u32 max_bw_addr, min_bw_addr;
5613 /* Calculate the address of the min/max bw registers */
5614 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5615 I40E_ALT_STRUCT_MAX_BW_OFFSET +
5616 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
5617 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5618 I40E_ALT_STRUCT_MIN_BW_OFFSET +
5619 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
5621 /* Read the bandwidths from alt ram */
5622 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
5623 min_bw_addr, min_bw);
5625 if (*min_bw & I40E_ALT_BW_VALID_MASK)
5630 if (*max_bw & I40E_ALT_BW_VALID_MASK)
5639 * i40e_aq_configure_partition_bw
5640 * @hw: pointer to the hardware structure
5641 * @bw_data: Buffer holding valid pfs and bw limits
5642 * @cmd_details: pointer to command details
5644 * Configure partitions guaranteed/max bw
5646 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
5647 struct i40e_aqc_configure_partition_bw_data *bw_data,
5648 struct i40e_asq_cmd_details *cmd_details)
5650 enum i40e_status_code status;
5651 struct i40e_aq_desc desc;
5652 u16 bwd_size = sizeof(*bw_data);
5654 i40e_fill_default_direct_cmd_desc(&desc,
5655 i40e_aqc_opc_configure_partition_bw);
5657 /* Indirect command */
5658 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5659 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5661 if (bwd_size > I40E_AQ_LARGE_BUF)
5662 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5664 desc.datalen = CPU_TO_LE16(bwd_size);
5666 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
5670 #endif /* PF_DRIVER */
5674 * i40e_aq_send_msg_to_pf
5675 * @hw: pointer to the hardware structure
5676 * @v_opcode: opcodes for VF-PF communication
5677 * @v_retval: return error code
5678 * @msg: pointer to the msg buffer
5679 * @msglen: msg length
5680 * @cmd_details: pointer to command details
5682 * Send message to PF driver using admin queue. By default, this message
5683 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
5684 * completion before returning.
5686 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
5687 enum i40e_virtchnl_ops v_opcode,
5688 enum i40e_status_code v_retval,
5689 u8 *msg, u16 msglen,
5690 struct i40e_asq_cmd_details *cmd_details)
5692 struct i40e_aq_desc desc;
5693 struct i40e_asq_cmd_details details;
5694 enum i40e_status_code status;
5696 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
5697 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
5698 desc.cookie_high = CPU_TO_LE32(v_opcode);
5699 desc.cookie_low = CPU_TO_LE32(v_retval);
5701 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
5702 | I40E_AQ_FLAG_RD));
5703 if (msglen > I40E_AQ_LARGE_BUF)
5704 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5705 desc.datalen = CPU_TO_LE16(msglen);
5708 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
5709 details.async = true;
5710 cmd_details = &details;
5712 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
5713 msglen, cmd_details);
5718 * i40e_vf_parse_hw_config
5719 * @hw: pointer to the hardware structure
5720 * @msg: pointer to the virtual channel VF resource structure
5722 * Given a VF resource message from the PF, populate the hw struct
5723 * with appropriate information.
5725 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
5726 struct i40e_virtchnl_vf_resource *msg)
5728 struct i40e_virtchnl_vsi_resource *vsi_res;
5731 vsi_res = &msg->vsi_res[0];
5733 hw->dev_caps.num_vsis = msg->num_vsis;
5734 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
5735 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
5736 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
5737 hw->dev_caps.dcb = msg->vf_offload_flags &
5738 I40E_VIRTCHNL_VF_OFFLOAD_L2;
5739 hw->dev_caps.fcoe = (msg->vf_offload_flags &
5740 I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
5741 hw->dev_caps.iwarp = (msg->vf_offload_flags &
5742 I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
5743 for (i = 0; i < msg->num_vsis; i++) {
5744 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
5745 i40e_memcpy(hw->mac.perm_addr,
5746 vsi_res->default_mac_addr,
5747 I40E_ETH_LENGTH_OF_ADDRESS,
5748 I40E_NONDMA_TO_NONDMA);
5749 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
5750 I40E_ETH_LENGTH_OF_ADDRESS,
5751 I40E_NONDMA_TO_NONDMA);
5759 * @hw: pointer to the hardware structure
5761 * Send a VF_RESET message to the PF. Does not wait for response from PF
5762 * as none will be forthcoming. Immediately after calling this function,
5763 * the admin queue should be shut down and (optionally) reinitialized.
5765 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
5767 return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
5768 I40E_SUCCESS, NULL, 0, NULL);
5770 #endif /* VF_DRIVER */
5774 * i40e_aq_set_arp_proxy_config
5775 * @hw: pointer to the HW structure
5776 * @proxy_config - pointer to proxy config command table struct
5777 * @cmd_details: pointer to command details
5779 * Set ARP offload parameters from pre-populated
5780 * i40e_aqc_arp_proxy_data struct
5782 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
5783 struct i40e_aqc_arp_proxy_data *proxy_config,
5784 struct i40e_asq_cmd_details *cmd_details)
5786 struct i40e_aq_desc desc;
5787 struct i40e_aqc_set_proxy_config *cmd =
5788 (struct i40e_aqc_set_proxy_config *) &desc.params.raw;
5789 enum i40e_status_code status;
5792 return I40E_ERR_PARAM;
5794 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
5796 cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
5797 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
5799 status = i40e_asq_send_command(hw, &desc, proxy_config,
5800 sizeof(struct i40e_aqc_arp_proxy_data),
5807 * i40e_aq_opc_set_ns_proxy_table_entry
5808 * @hw: pointer to the HW structure
5809 * @ns_proxy_table_entry: pointer to NS table entry command struct
5810 * @cmd_details: pointer to command details
5812 * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
5813 * from pre-populated i40e_aqc_ns_proxy_data struct
5815 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
5816 struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
5817 struct i40e_asq_cmd_details *cmd_details)
5819 struct i40e_aq_desc desc;
5820 struct i40e_aqc_set_ns_proxy_table_entry *cmd =
5821 (struct i40e_aqc_set_ns_proxy_table_entry *) &desc.params.raw;
5822 enum i40e_status_code status;
5824 if (!ns_proxy_table_entry)
5825 return I40E_ERR_PARAM;
5827 i40e_fill_default_direct_cmd_desc(&desc,
5828 i40e_aqc_opc_set_ns_proxy_table_entry);
5831 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
5833 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
5835 status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
5836 sizeof(struct i40e_aqc_ns_proxy_data),
5842 #endif /* X722_SUPPORT */