drivers/net/i40e/base/i40e_common.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "i40e_type.h"
  35 #include "i40e_adminq.h"
  36 #include "i40e_prototype.h"
  37 #include "i40e_virtchnl.h"
  38
  39
  40 /**
  41  * i40e_set_mac_type - Sets MAC type
  42  * @hw: pointer to the HW structure
  43  *
  44  * This function sets the mac type of the adapter based on the
  45  * vendor ID and device ID stored in the hw structure.
  46  **/
  47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  49 #else
  50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  51 #endif
  52 {
  53         enum i40e_status_code status = I40E_SUCCESS;
  54
  55         DEBUGFUNC("i40e_set_mac_type\n");
  56
  57         if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
  58                 switch (hw->device_id) {
  59                 case I40E_DEV_ID_SFP_XL710:
  60                 case I40E_DEV_ID_QEMU:
  61                 case I40E_DEV_ID_KX_B:
  62                 case I40E_DEV_ID_KX_C:
  63                 case I40E_DEV_ID_QSFP_A:
  64                 case I40E_DEV_ID_QSFP_B:
  65                 case I40E_DEV_ID_QSFP_C:
  66                 case I40E_DEV_ID_10G_BASE_T:
  67                 case I40E_DEV_ID_10G_BASE_T4:
  68                 case I40E_DEV_ID_20G_KR2:
  69                 case I40E_DEV_ID_20G_KR2_A:
  70                 case I40E_DEV_ID_25G_B:
  71                 case I40E_DEV_ID_25G_SFP28:
  72                         hw->mac.type = I40E_MAC_XL710;
  73                         break;
  74 #ifdef X722_SUPPORT
  75 #ifdef X722_A0_SUPPORT
  76                 case I40E_DEV_ID_X722_A0:
  77 #endif
  78                 case I40E_DEV_ID_KX_X722:
  79                 case I40E_DEV_ID_QSFP_X722:
  80                 case I40E_DEV_ID_SFP_X722:
  81                 case I40E_DEV_ID_1G_BASE_T_X722:
  82                 case I40E_DEV_ID_10G_BASE_T_X722:
  83                 case I40E_DEV_ID_SFP_I_X722:
  84                         hw->mac.type = I40E_MAC_X722;
  85                         break;
  86 #endif
  87 #ifdef X722_SUPPORT
  88 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  89                 case I40E_DEV_ID_X722_VF:
  90 #ifdef X722_A0_SUPPORT
  91                 case I40E_DEV_ID_X722_A0_VF:
  92 #endif
  93                         hw->mac.type = I40E_MAC_X722_VF;
  94                         break;
  95 #endif /* INTEGRATED_VF || VF_DRIVER */
  96 #endif /* X722_SUPPORT */
  97 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  98                 case I40E_DEV_ID_VF:
  99                 case I40E_DEV_ID_VF_HV:
 100                         hw->mac.type = I40E_MAC_VF;
 101                         break;
 102 #endif
 103                 default:
 104                         hw->mac.type = I40E_MAC_GENERIC;
 105                         break;
 106                 }
 107         } else {
 108                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
 109         }
 110
 111         DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
 112                   hw->mac.type, status);
 113         return status;
 114 }
 115
 116 #ifndef I40E_NDIS_SUPPORT
 117 /**
 118  * i40e_aq_str - convert AQ err code to a string
 119  * @hw: pointer to the HW structure
 120  * @aq_err: the AQ error code to convert
 121  **/
 122 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
 123 {
 124         switch (aq_err) {
 125         case I40E_AQ_RC_OK:
 126                 return "OK";
 127         case I40E_AQ_RC_EPERM:
 128                 return "I40E_AQ_RC_EPERM";
 129         case I40E_AQ_RC_ENOENT:
 130                 return "I40E_AQ_RC_ENOENT";
 131         case I40E_AQ_RC_ESRCH:
 132                 return "I40E_AQ_RC_ESRCH";
 133         case I40E_AQ_RC_EINTR:
 134                 return "I40E_AQ_RC_EINTR";
 135         case I40E_AQ_RC_EIO:
 136                 return "I40E_AQ_RC_EIO";
 137         case I40E_AQ_RC_ENXIO:
 138                 return "I40E_AQ_RC_ENXIO";
 139         case I40E_AQ_RC_E2BIG:
 140                 return "I40E_AQ_RC_E2BIG";
 141         case I40E_AQ_RC_EAGAIN:
 142                 return "I40E_AQ_RC_EAGAIN";
 143         case I40E_AQ_RC_ENOMEM:
 144                 return "I40E_AQ_RC_ENOMEM";
 145         case I40E_AQ_RC_EACCES:
 146                 return "I40E_AQ_RC_EACCES";
 147         case I40E_AQ_RC_EFAULT:
 148                 return "I40E_AQ_RC_EFAULT";
 149         case I40E_AQ_RC_EBUSY:
 150                 return "I40E_AQ_RC_EBUSY";
 151         case I40E_AQ_RC_EEXIST:
 152                 return "I40E_AQ_RC_EEXIST";
 153         case I40E_AQ_RC_EINVAL:
 154                 return "I40E_AQ_RC_EINVAL";
 155         case I40E_AQ_RC_ENOTTY:
 156                 return "I40E_AQ_RC_ENOTTY";
 157         case I40E_AQ_RC_ENOSPC:
 158                 return "I40E_AQ_RC_ENOSPC";
 159         case I40E_AQ_RC_ENOSYS:
 160                 return "I40E_AQ_RC_ENOSYS";
 161         case I40E_AQ_RC_ERANGE:
 162                 return "I40E_AQ_RC_ERANGE";
 163         case I40E_AQ_RC_EFLUSHED:
 164                 return "I40E_AQ_RC_EFLUSHED";
 165         case I40E_AQ_RC_BAD_ADDR:
 166                 return "I40E_AQ_RC_BAD_ADDR";
 167         case I40E_AQ_RC_EMODE:
 168                 return "I40E_AQ_RC_EMODE";
 169         case I40E_AQ_RC_EFBIG:
 170                 return "I40E_AQ_RC_EFBIG";
 171         }
 172
 173         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 174         return hw->err_str;
 175 }
 176
 177 /**
 178  * i40e_stat_str - convert status err code to a string
 179  * @hw: pointer to the HW structure
 180  * @stat_err: the status error code to convert
 181  **/
 182 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
 183 {
 184         switch (stat_err) {
 185         case I40E_SUCCESS:
 186                 return "OK";
 187         case I40E_ERR_NVM:
 188                 return "I40E_ERR_NVM";
 189         case I40E_ERR_NVM_CHECKSUM:
 190                 return "I40E_ERR_NVM_CHECKSUM";
 191         case I40E_ERR_PHY:
 192                 return "I40E_ERR_PHY";
 193         case I40E_ERR_CONFIG:
 194                 return "I40E_ERR_CONFIG";
 195         case I40E_ERR_PARAM:
 196                 return "I40E_ERR_PARAM";
 197         case I40E_ERR_MAC_TYPE:
 198                 return "I40E_ERR_MAC_TYPE";
 199         case I40E_ERR_UNKNOWN_PHY:
 200                 return "I40E_ERR_UNKNOWN_PHY";
 201         case I40E_ERR_LINK_SETUP:
 202                 return "I40E_ERR_LINK_SETUP";
 203         case I40E_ERR_ADAPTER_STOPPED:
 204                 return "I40E_ERR_ADAPTER_STOPPED";
 205         case I40E_ERR_INVALID_MAC_ADDR:
 206                 return "I40E_ERR_INVALID_MAC_ADDR";
 207         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 208                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 209         case I40E_ERR_MASTER_REQUESTS_PENDING:
 210                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 211         case I40E_ERR_INVALID_LINK_SETTINGS:
 212                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 213         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 214                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 215         case I40E_ERR_RESET_FAILED:
 216                 return "I40E_ERR_RESET_FAILED";
 217         case I40E_ERR_SWFW_SYNC:
 218                 return "I40E_ERR_SWFW_SYNC";
 219         case I40E_ERR_NO_AVAILABLE_VSI:
 220                 return "I40E_ERR_NO_AVAILABLE_VSI";
 221         case I40E_ERR_NO_MEMORY:
 222                 return "I40E_ERR_NO_MEMORY";
 223         case I40E_ERR_BAD_PTR:
 224                 return "I40E_ERR_BAD_PTR";
 225         case I40E_ERR_RING_FULL:
 226                 return "I40E_ERR_RING_FULL";
 227         case I40E_ERR_INVALID_PD_ID:
 228                 return "I40E_ERR_INVALID_PD_ID";
 229         case I40E_ERR_INVALID_QP_ID:
 230                 return "I40E_ERR_INVALID_QP_ID";
 231         case I40E_ERR_INVALID_CQ_ID:
 232                 return "I40E_ERR_INVALID_CQ_ID";
 233         case I40E_ERR_INVALID_CEQ_ID:
 234                 return "I40E_ERR_INVALID_CEQ_ID";
 235         case I40E_ERR_INVALID_AEQ_ID:
 236                 return "I40E_ERR_INVALID_AEQ_ID";
 237         case I40E_ERR_INVALID_SIZE:
 238                 return "I40E_ERR_INVALID_SIZE";
 239         case I40E_ERR_INVALID_ARP_INDEX:
 240                 return "I40E_ERR_INVALID_ARP_INDEX";
 241         case I40E_ERR_INVALID_FPM_FUNC_ID:
 242                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 243         case I40E_ERR_QP_INVALID_MSG_SIZE:
 244                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 245         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 246                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 247         case I40E_ERR_INVALID_FRAG_COUNT:
 248                 return "I40E_ERR_INVALID_FRAG_COUNT";
 249         case I40E_ERR_QUEUE_EMPTY:
 250                 return "I40E_ERR_QUEUE_EMPTY";
 251         case I40E_ERR_INVALID_ALIGNMENT:
 252                 return "I40E_ERR_INVALID_ALIGNMENT";
 253         case I40E_ERR_FLUSHED_QUEUE:
 254                 return "I40E_ERR_FLUSHED_QUEUE";
 255         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 256                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 257         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 258                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 259         case I40E_ERR_TIMEOUT:
 260                 return "I40E_ERR_TIMEOUT";
 261         case I40E_ERR_OPCODE_MISMATCH:
 262                 return "I40E_ERR_OPCODE_MISMATCH";
 263         case I40E_ERR_CQP_COMPL_ERROR:
 264                 return "I40E_ERR_CQP_COMPL_ERROR";
 265         case I40E_ERR_INVALID_VF_ID:
 266                 return "I40E_ERR_INVALID_VF_ID";
 267         case I40E_ERR_INVALID_HMCFN_ID:
 268                 return "I40E_ERR_INVALID_HMCFN_ID";
 269         case I40E_ERR_BACKING_PAGE_ERROR:
 270                 return "I40E_ERR_BACKING_PAGE_ERROR";
 271         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 272                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 273         case I40E_ERR_INVALID_PBLE_INDEX:
 274                 return "I40E_ERR_INVALID_PBLE_INDEX";
 275         case I40E_ERR_INVALID_SD_INDEX:
 276                 return "I40E_ERR_INVALID_SD_INDEX";
 277         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 278                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 279         case I40E_ERR_INVALID_SD_TYPE:
 280                 return "I40E_ERR_INVALID_SD_TYPE";
 281         case I40E_ERR_MEMCPY_FAILED:
 282                 return "I40E_ERR_MEMCPY_FAILED";
 283         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 284                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 285         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 286                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 287         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 288                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 289         case I40E_ERR_SRQ_ENABLED:
 290                 return "I40E_ERR_SRQ_ENABLED";
 291         case I40E_ERR_ADMIN_QUEUE_ERROR:
 292                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 293         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 294                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 295         case I40E_ERR_BUF_TOO_SHORT:
 296                 return "I40E_ERR_BUF_TOO_SHORT";
 297         case I40E_ERR_ADMIN_QUEUE_FULL:
 298                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 299         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 300                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 301         case I40E_ERR_BAD_IWARP_CQE:
 302                 return "I40E_ERR_BAD_IWARP_CQE";
 303         case I40E_ERR_NVM_BLANK_MODE:
 304                 return "I40E_ERR_NVM_BLANK_MODE";
 305         case I40E_ERR_NOT_IMPLEMENTED:
 306                 return "I40E_ERR_NOT_IMPLEMENTED";
 307         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 308                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 309         case I40E_ERR_DIAG_TEST_FAILED:
 310                 return "I40E_ERR_DIAG_TEST_FAILED";
 311         case I40E_ERR_NOT_READY:
 312                 return "I40E_ERR_NOT_READY";
 313         case I40E_NOT_SUPPORTED:
 314                 return "I40E_NOT_SUPPORTED";
 315         case I40E_ERR_FIRMWARE_API_VERSION:
 316                 return "I40E_ERR_FIRMWARE_API_VERSION";
 317         }
 318
 319         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 320         return hw->err_str;
 321 }
 322
 323 #endif /* I40E_NDIS_SUPPORT */
 324 /**
 325  * i40e_debug_aq
 326  * @hw: debug mask related to admin queue
 327  * @mask: debug mask
 328  * @desc: pointer to admin queue descriptor
 329  * @buffer: pointer to command buffer
 330  * @buf_len: max length of buffer
 331  *
 332  * Dumps debug log about adminq command with descriptor contents.
 333  **/
 334 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 335                    void *buffer, u16 buf_len)
 336 {
 337         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 338         u16 len = LE16_TO_CPU(aq_desc->datalen);
 339         u8 *buf = (u8 *)buffer;
 340         u16 i = 0;
 341
 342         if ((!(mask & hw->debug_mask)) || (desc == NULL))
 343                 return;
 344
 345         i40e_debug(hw, mask,
 346                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 347                    LE16_TO_CPU(aq_desc->opcode),
 348                    LE16_TO_CPU(aq_desc->flags),
 349                    LE16_TO_CPU(aq_desc->datalen),
 350                    LE16_TO_CPU(aq_desc->retval));
 351         i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
 352                    LE32_TO_CPU(aq_desc->cookie_high),
 353                    LE32_TO_CPU(aq_desc->cookie_low));
 354         i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
 355                    LE32_TO_CPU(aq_desc->params.internal.param0),
 356                    LE32_TO_CPU(aq_desc->params.internal.param1));
 357         i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
 358                    LE32_TO_CPU(aq_desc->params.external.addr_high),
 359                    LE32_TO_CPU(aq_desc->params.external.addr_low));
 360
 361         if ((buffer != NULL) && (aq_desc->datalen != 0)) {
 362                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 363                 if (buf_len < len)
 364                         len = buf_len;
 365                 /* write the full 16-byte chunks */
 366                 for (i = 0; i < (len - 16); i += 16)
 367                         i40e_debug(hw, mask,
 368                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 369                                    i, buf[i], buf[i+1], buf[i+2], buf[i+3],
 370                                    buf[i+4], buf[i+5], buf[i+6], buf[i+7],
 371                                    buf[i+8], buf[i+9], buf[i+10], buf[i+11],
 372                                    buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
 373                 /* the most we could have left is 16 bytes, pad with zeros */
 374                 if (i < len) {
 375                         char d_buf[16];
 376                         int j, i_sav;
 377
 378                         i_sav = i;
 379                         memset(d_buf, 0, sizeof(d_buf));
 380                         for (j = 0; i < len; j++, i++)
 381                                 d_buf[j] = buf[i];
 382                         i40e_debug(hw, mask,
 383                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 384                                    i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
 385                                    d_buf[4], d_buf[5], d_buf[6], d_buf[7],
 386                                    d_buf[8], d_buf[9], d_buf[10], d_buf[11],
 387                                    d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
 388                 }
 389         }
 390 }
 391
 392 /**
 393  * i40e_check_asq_alive
 394  * @hw: pointer to the hw struct
 395  *
 396  * Returns true if Queue is enabled else false.
 397  **/
 398 bool i40e_check_asq_alive(struct i40e_hw *hw)
 399 {
 400         if (hw->aq.asq.len)
 401 #ifdef PF_DRIVER
 402 #ifdef INTEGRATED_VF
 403                 if (!i40e_is_vf(hw))
 404                         return !!(rd32(hw, hw->aq.asq.len) &
 405                                 I40E_PF_ATQLEN_ATQENABLE_MASK);
 406 #else
 407                 return !!(rd32(hw, hw->aq.asq.len) &
 408                         I40E_PF_ATQLEN_ATQENABLE_MASK);
 409 #endif /* INTEGRATED_VF */
 410 #endif /* PF_DRIVER */
 411 #ifdef VF_DRIVER
 412 #ifdef INTEGRATED_VF
 413                 if (i40e_is_vf(hw))
 414                         return !!(rd32(hw, hw->aq.asq.len) &
 415                                 I40E_VF_ATQLEN1_ATQENABLE_MASK);
 416 #else
 417                 return !!(rd32(hw, hw->aq.asq.len) &
 418                         I40E_VF_ATQLEN1_ATQENABLE_MASK);
 419 #endif /* INTEGRATED_VF */
 420 #endif /* VF_DRIVER */
 421         return false;
 422 }
 423
 424 /**
 425  * i40e_aq_queue_shutdown
 426  * @hw: pointer to the hw struct
 427  * @unloading: is the driver unloading itself
 428  *
 429  * Tell the Firmware that we're shutting down the AdminQ and whether
 430  * or not the driver is unloading as well.
 431  **/
 432 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
 433                                              bool unloading)
 434 {
 435         struct i40e_aq_desc desc;
 436         struct i40e_aqc_queue_shutdown *cmd =
 437                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 438         enum i40e_status_code status;
 439
 440         i40e_fill_default_direct_cmd_desc(&desc,
 441                                           i40e_aqc_opc_queue_shutdown);
 442
 443         if (unloading)
 444                 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
 445         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 446
 447         return status;
 448 }
 449 #ifdef X722_SUPPORT
 450
 451 /**
 452  * i40e_aq_get_set_rss_lut
 453  * @hw: pointer to the hardware structure
 454  * @vsi_id: vsi fw index
 455  * @pf_lut: for PF table set true, for VSI table set false
 456  * @lut: pointer to the lut buffer provided by the caller
 457  * @lut_size: size of the lut buffer
 458  * @set: set true to set the table, false to get the table
 459  *
 460  * Internal function to get or set RSS look up table
 461  **/
 462 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 463                                                      u16 vsi_id, bool pf_lut,
 464                                                      u8 *lut, u16 lut_size,
 465                                                      bool set)
 466 {
 467         enum i40e_status_code status;
 468         struct i40e_aq_desc desc;
 469         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 470                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 471
 472         if (set)
 473                 i40e_fill_default_direct_cmd_desc(&desc,
 474                                                   i40e_aqc_opc_set_rss_lut);
 475         else
 476                 i40e_fill_default_direct_cmd_desc(&desc,
 477                                                   i40e_aqc_opc_get_rss_lut);
 478
 479         /* Indirect command */
 480         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 481         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 482
 483         cmd_resp->vsi_id =
 484                         CPU_TO_LE16((u16)((vsi_id <<
 485                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 486                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 487         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 488
 489         if (pf_lut)
 490                 cmd_resp->flags |= CPU_TO_LE16((u16)
 491                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 492                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 493                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 494         else
 495                 cmd_resp->flags |= CPU_TO_LE16((u16)
 496                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 497                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 498                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 499
 500         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 501
 502         return status;
 503 }
 504
 505 /**
 506  * i40e_aq_get_rss_lut
 507  * @hw: pointer to the hardware structure
 508  * @vsi_id: vsi fw index
 509  * @pf_lut: for PF table set true, for VSI table set false
 510  * @lut: pointer to the lut buffer provided by the caller
 511  * @lut_size: size of the lut buffer
 512  *
 513  * get the RSS lookup table, PF or VSI type
 514  **/
 515 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 516                                           bool pf_lut, u8 *lut, u16 lut_size)
 517 {
 518         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 519                                        false);
 520 }
 521
 522 /**
 523  * i40e_aq_set_rss_lut
 524  * @hw: pointer to the hardware structure
 525  * @vsi_id: vsi fw index
 526  * @pf_lut: for PF table set true, for VSI table set false
 527  * @lut: pointer to the lut buffer provided by the caller
 528  * @lut_size: size of the lut buffer
 529  *
 530  * set the RSS lookup table, PF or VSI type
 531  **/
 532 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 533                                           bool pf_lut, u8 *lut, u16 lut_size)
 534 {
 535         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
 536 }
 537
 538 /**
 539  * i40e_aq_get_set_rss_key
 540  * @hw: pointer to the hw struct
 541  * @vsi_id: vsi fw index
 542  * @key: pointer to key info struct
 543  * @set: set true to set the key, false to get the key
 544  *
 545  * get the RSS key per VSI
 546  **/
 547 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 548                                       u16 vsi_id,
 549                                       struct i40e_aqc_get_set_rss_key_data *key,
 550                                       bool set)
 551 {
 552         enum i40e_status_code status;
 553         struct i40e_aq_desc desc;
 554         struct i40e_aqc_get_set_rss_key *cmd_resp =
 555                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 556         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 557
 558         if (set)
 559                 i40e_fill_default_direct_cmd_desc(&desc,
 560                                                   i40e_aqc_opc_set_rss_key);
 561         else
 562                 i40e_fill_default_direct_cmd_desc(&desc,
 563                                                   i40e_aqc_opc_get_rss_key);
 564
 565         /* Indirect command */
 566         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 567         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 568
 569         cmd_resp->vsi_id =
 570                         CPU_TO_LE16((u16)((vsi_id <<
 571                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 572                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 573         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 574
 575         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 576
 577         return status;
 578 }
 579
 580 /**
 581  * i40e_aq_get_rss_key
 582  * @hw: pointer to the hw struct
 583  * @vsi_id: vsi fw index
 584  * @key: pointer to key info struct
 585  *
 586  **/
 587 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
 588                                       u16 vsi_id,
 589                                       struct i40e_aqc_get_set_rss_key_data *key)
 590 {
 591         return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
 592 }
 593
 594 /**
 595  * i40e_aq_set_rss_key
 596  * @hw: pointer to the hw struct
 597  * @vsi_id: vsi fw index
 598  * @key: pointer to key info struct
 599  *
 600  * set the RSS key per VSI
 601  **/
 602 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
 603                                       u16 vsi_id,
 604                                       struct i40e_aqc_get_set_rss_key_data *key)
 605 {
 606         return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
 607 }
 608 #endif /* X722_SUPPORT */
 609
 610 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 611  * hardware to a bit-field that can be used by SW to more easily determine the
 612  * packet type.
 613  *
 614  * Macros are used to shorten the table lines and make this table human
 615  * readable.
 616  *
 617  * We store the PTYPE in the top byte of the bit field - this is just so that
 618  * we can check that the table doesn't have a row missing, as the index into
 619  * the table should be the PTYPE.
 620  *
 621  * Typical work flow:
 622  *
 623  * IF NOT i40e_ptype_lookup[ptype].known
 624  * THEN
 625  *      Packet is unknown
 626  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 627  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 628  * ELSE
 629  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 630  * ENDIF
 631  */
 632
 633 /* macro to make the table lines short */
 634 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 635         {       PTYPE, \
 636                 1, \
 637                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 638                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 639                 I40E_RX_PTYPE_##OUTER_FRAG, \
 640                 I40E_RX_PTYPE_TUNNEL_##T, \
 641                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 642                 I40E_RX_PTYPE_##TEF, \
 643                 I40E_RX_PTYPE_INNER_PROT_##I, \
 644                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 645
 646 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 647                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 648
 649 /* shorter macros makes the table fit but are terse */
 650 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 651 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 652 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 653
 654 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 655 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 656         /* L2 Packet types */
 657         I40E_PTT_UNUSED_ENTRY(0),
 658         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 659         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 660         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 661         I40E_PTT_UNUSED_ENTRY(4),
 662         I40E_PTT_UNUSED_ENTRY(5),
 663         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 664         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 665         I40E_PTT_UNUSED_ENTRY(8),
 666         I40E_PTT_UNUSED_ENTRY(9),
 667         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 668         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 669         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 670         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 671         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 672         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 673         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 674         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 675         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 676         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 677         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 678         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 679
 680         /* Non Tunneled IPv4 */
 681         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 682         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 683         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 684         I40E_PTT_UNUSED_ENTRY(25),
 685         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 686         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 687         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 688
 689         /* IPv4 --> IPv4 */
 690         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 691         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 692         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 693         I40E_PTT_UNUSED_ENTRY(32),
 694         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 695         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 696         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 697
 698         /* IPv4 --> IPv6 */
 699         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 700         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 701         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 702         I40E_PTT_UNUSED_ENTRY(39),
 703         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 704         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 705         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 706
 707         /* IPv4 --> GRE/NAT */
 708         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 709
 710         /* IPv4 --> GRE/NAT --> IPv4 */
 711         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 712         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 713         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 714         I40E_PTT_UNUSED_ENTRY(47),
 715         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 716         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 717         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 718
 719         /* IPv4 --> GRE/NAT --> IPv6 */
 720         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 721         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 722         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 723         I40E_PTT_UNUSED_ENTRY(54),
 724         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 725         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 726         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 727
 728         /* IPv4 --> GRE/NAT --> MAC */
 729         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 730
 731         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 732         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 733         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 734         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 735         I40E_PTT_UNUSED_ENTRY(62),
 736         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 737         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 738         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 739
 740         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 741         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 742         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 743         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 744         I40E_PTT_UNUSED_ENTRY(69),
 745         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 746         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 747         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 748
 749         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 750         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 751
 752         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 753         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 754         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 755         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 756         I40E_PTT_UNUSED_ENTRY(77),
 757         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 758         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 759         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 760
 761         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 762         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 763         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 764         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 765         I40E_PTT_UNUSED_ENTRY(84),
 766         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 767         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 768         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 769
 770         /* Non Tunneled IPv6 */
 771         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 772         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 773         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
 774         I40E_PTT_UNUSED_ENTRY(91),
 775         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 776         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 777         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 778
 779         /* IPv6 --> IPv4 */
 780         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 781         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 782         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 783         I40E_PTT_UNUSED_ENTRY(98),
 784         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 785         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 786         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 787
 788         /* IPv6 --> IPv6 */
 789         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 790         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 791         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 792         I40E_PTT_UNUSED_ENTRY(105),
 793         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 794         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 795         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 796
 797         /* IPv6 --> GRE/NAT */
 798         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 799
 800         /* IPv6 --> GRE/NAT -> IPv4 */
 801         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 802         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 803         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 804         I40E_PTT_UNUSED_ENTRY(113),
 805         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 806         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 807         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 808
 809         /* IPv6 --> GRE/NAT -> IPv6 */
 810         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 811         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 812         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 813         I40E_PTT_UNUSED_ENTRY(120),
 814         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 815         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 816         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 817
 818         /* IPv6 --> GRE/NAT -> MAC */
 819         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 820
 821         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 822         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 823         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 824         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 825         I40E_PTT_UNUSED_ENTRY(128),
 826         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 827         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 828         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 829
 830         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 831         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 832         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 833         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 834         I40E_PTT_UNUSED_ENTRY(135),
 835         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 836         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 837         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 838
 839         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 840         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 841
 842         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 843         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 844         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 845         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 846         I40E_PTT_UNUSED_ENTRY(143),
 847         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 848         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 849         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 850
 851         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 852         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 853         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 854         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 855         I40E_PTT_UNUSED_ENTRY(150),
 856         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 857         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 858         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 859
 860         /* unused entries */
 861         I40E_PTT_UNUSED_ENTRY(154),
 862         I40E_PTT_UNUSED_ENTRY(155),
 863         I40E_PTT_UNUSED_ENTRY(156),
 864         I40E_PTT_UNUSED_ENTRY(157),
 865         I40E_PTT_UNUSED_ENTRY(158),
 866         I40E_PTT_UNUSED_ENTRY(159),
 867
 868         I40E_PTT_UNUSED_ENTRY(160),
 869         I40E_PTT_UNUSED_ENTRY(161),
 870         I40E_PTT_UNUSED_ENTRY(162),
 871         I40E_PTT_UNUSED_ENTRY(163),
 872         I40E_PTT_UNUSED_ENTRY(164),
 873         I40E_PTT_UNUSED_ENTRY(165),
 874         I40E_PTT_UNUSED_ENTRY(166),
 875         I40E_PTT_UNUSED_ENTRY(167),
 876         I40E_PTT_UNUSED_ENTRY(168),
 877         I40E_PTT_UNUSED_ENTRY(169),
 878
 879         I40E_PTT_UNUSED_ENTRY(170),
 880         I40E_PTT_UNUSED_ENTRY(171),
 881         I40E_PTT_UNUSED_ENTRY(172),
 882         I40E_PTT_UNUSED_ENTRY(173),
 883         I40E_PTT_UNUSED_ENTRY(174),
 884         I40E_PTT_UNUSED_ENTRY(175),
 885         I40E_PTT_UNUSED_ENTRY(176),
 886         I40E_PTT_UNUSED_ENTRY(177),
 887         I40E_PTT_UNUSED_ENTRY(178),
 888         I40E_PTT_UNUSED_ENTRY(179),
 889
 890         I40E_PTT_UNUSED_ENTRY(180),
 891         I40E_PTT_UNUSED_ENTRY(181),
 892         I40E_PTT_UNUSED_ENTRY(182),
 893         I40E_PTT_UNUSED_ENTRY(183),
 894         I40E_PTT_UNUSED_ENTRY(184),
 895         I40E_PTT_UNUSED_ENTRY(185),
 896         I40E_PTT_UNUSED_ENTRY(186),
 897         I40E_PTT_UNUSED_ENTRY(187),
 898         I40E_PTT_UNUSED_ENTRY(188),
 899         I40E_PTT_UNUSED_ENTRY(189),
 900
 901         I40E_PTT_UNUSED_ENTRY(190),
 902         I40E_PTT_UNUSED_ENTRY(191),
 903         I40E_PTT_UNUSED_ENTRY(192),
 904         I40E_PTT_UNUSED_ENTRY(193),
 905         I40E_PTT_UNUSED_ENTRY(194),
 906         I40E_PTT_UNUSED_ENTRY(195),
 907         I40E_PTT_UNUSED_ENTRY(196),
 908         I40E_PTT_UNUSED_ENTRY(197),
 909         I40E_PTT_UNUSED_ENTRY(198),
 910         I40E_PTT_UNUSED_ENTRY(199),
 911
 912         I40E_PTT_UNUSED_ENTRY(200),
 913         I40E_PTT_UNUSED_ENTRY(201),
 914         I40E_PTT_UNUSED_ENTRY(202),
 915         I40E_PTT_UNUSED_ENTRY(203),
 916         I40E_PTT_UNUSED_ENTRY(204),
 917         I40E_PTT_UNUSED_ENTRY(205),
 918         I40E_PTT_UNUSED_ENTRY(206),
 919         I40E_PTT_UNUSED_ENTRY(207),
 920         I40E_PTT_UNUSED_ENTRY(208),
 921         I40E_PTT_UNUSED_ENTRY(209),
 922
 923         I40E_PTT_UNUSED_ENTRY(210),
 924         I40E_PTT_UNUSED_ENTRY(211),
 925         I40E_PTT_UNUSED_ENTRY(212),
 926         I40E_PTT_UNUSED_ENTRY(213),
 927         I40E_PTT_UNUSED_ENTRY(214),
 928         I40E_PTT_UNUSED_ENTRY(215),
 929         I40E_PTT_UNUSED_ENTRY(216),
 930         I40E_PTT_UNUSED_ENTRY(217),
 931         I40E_PTT_UNUSED_ENTRY(218),
 932         I40E_PTT_UNUSED_ENTRY(219),
 933
 934         I40E_PTT_UNUSED_ENTRY(220),
 935         I40E_PTT_UNUSED_ENTRY(221),
 936         I40E_PTT_UNUSED_ENTRY(222),
 937         I40E_PTT_UNUSED_ENTRY(223),
 938         I40E_PTT_UNUSED_ENTRY(224),
 939         I40E_PTT_UNUSED_ENTRY(225),
 940         I40E_PTT_UNUSED_ENTRY(226),
 941         I40E_PTT_UNUSED_ENTRY(227),
 942         I40E_PTT_UNUSED_ENTRY(228),
 943         I40E_PTT_UNUSED_ENTRY(229),
 944
 945         I40E_PTT_UNUSED_ENTRY(230),
 946         I40E_PTT_UNUSED_ENTRY(231),
 947         I40E_PTT_UNUSED_ENTRY(232),
 948         I40E_PTT_UNUSED_ENTRY(233),
 949         I40E_PTT_UNUSED_ENTRY(234),
 950         I40E_PTT_UNUSED_ENTRY(235),
 951         I40E_PTT_UNUSED_ENTRY(236),
 952         I40E_PTT_UNUSED_ENTRY(237),
 953         I40E_PTT_UNUSED_ENTRY(238),
 954         I40E_PTT_UNUSED_ENTRY(239),
 955
 956         I40E_PTT_UNUSED_ENTRY(240),
 957         I40E_PTT_UNUSED_ENTRY(241),
 958         I40E_PTT_UNUSED_ENTRY(242),
 959         I40E_PTT_UNUSED_ENTRY(243),
 960         I40E_PTT_UNUSED_ENTRY(244),
 961         I40E_PTT_UNUSED_ENTRY(245),
 962         I40E_PTT_UNUSED_ENTRY(246),
 963         I40E_PTT_UNUSED_ENTRY(247),
 964         I40E_PTT_UNUSED_ENTRY(248),
 965         I40E_PTT_UNUSED_ENTRY(249),
 966
 967         I40E_PTT_UNUSED_ENTRY(250),
 968         I40E_PTT_UNUSED_ENTRY(251),
 969         I40E_PTT_UNUSED_ENTRY(252),
 970         I40E_PTT_UNUSED_ENTRY(253),
 971         I40E_PTT_UNUSED_ENTRY(254),
 972         I40E_PTT_UNUSED_ENTRY(255)
 973 };
 974
 975
 976 /**
 977  * i40e_validate_mac_addr - Validate unicast MAC address
 978  * @mac_addr: pointer to MAC address
 979  *
 980  * Tests a MAC address to ensure it is a valid Individual Address
 981  **/
 982 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
 983 {
 984         enum i40e_status_code status = I40E_SUCCESS;
 985
 986         DEBUGFUNC("i40e_validate_mac_addr");
 987
 988         /* Broadcast addresses ARE multicast addresses
 989          * Make sure it is not a multicast address
 990          * Reject the zero address
 991          */
 992         if (I40E_IS_MULTICAST(mac_addr) ||
 993             (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
 994               mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
 995                 status = I40E_ERR_INVALID_MAC_ADDR;
 996
 997         return status;
 998 }
 999 #ifdef PF_DRIVER
1000
1001 /**
1002  * i40e_init_shared_code - Initialize the shared code
1003  * @hw: pointer to hardware structure
1004  *
1005  * This assigns the MAC type and PHY code and inits the NVM.
1006  * Does not touch the hardware. This function must be called prior to any
1007  * other function in the shared code. The i40e_hw structure should be
1008  * memset to 0 prior to calling this function.  The following fields in
1009  * hw structure should be filled in prior to calling this function:
1010  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1011  * subsystem_vendor_id, and revision_id
1012  **/
1013 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
1014 {
1015         enum i40e_status_code status = I40E_SUCCESS;
1016         u32 port, ari, func_rid;
1017
1018         DEBUGFUNC("i40e_init_shared_code");
1019
1020         i40e_set_mac_type(hw);
1021
1022         switch (hw->mac.type) {
1023         case I40E_MAC_XL710:
1024 #ifdef X722_SUPPORT
1025         case I40E_MAC_X722:
1026 #endif
1027                 break;
1028         default:
1029                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1030         }
1031
1032         hw->phy.get_link_info = true;
1033
1034         /* Determine port number and PF number*/
1035         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1036                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1037         hw->port = (u8)port;
1038         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1039                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1040         func_rid = rd32(hw, I40E_PF_FUNC_RID);
1041         if (ari)
1042                 hw->pf_id = (u8)(func_rid & 0xff);
1043         else
1044                 hw->pf_id = (u8)(func_rid & 0x7);
1045
1046 #ifdef X722_SUPPORT
1047         if (hw->mac.type == I40E_MAC_X722)
1048                 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
1049
1050 #endif
1051         status = i40e_init_nvm(hw);
1052         return status;
1053 }
1054
1055 /**
1056  * i40e_aq_mac_address_read - Retrieve the MAC addresses
1057  * @hw: pointer to the hw struct
1058  * @flags: a return indicator of what addresses were added to the addr store
1059  * @addrs: the requestor's mac addr store
1060  * @cmd_details: pointer to command details structure or NULL
1061  **/
1062 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1063                                    u16 *flags,
1064                                    struct i40e_aqc_mac_address_read_data *addrs,
1065                                    struct i40e_asq_cmd_details *cmd_details)
1066 {
1067         struct i40e_aq_desc desc;
1068         struct i40e_aqc_mac_address_read *cmd_data =
1069                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1070         enum i40e_status_code status;
1071
1072         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1073         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1074
1075         status = i40e_asq_send_command(hw, &desc, addrs,
1076                                        sizeof(*addrs), cmd_details);
1077         *flags = LE16_TO_CPU(cmd_data->command_flags);
1078
1079         return status;
1080 }
1081
1082 /**
1083  * i40e_aq_mac_address_write - Change the MAC addresses
1084  * @hw: pointer to the hw struct
1085  * @flags: indicates which MAC to be written
1086  * @mac_addr: address to write
1087  * @cmd_details: pointer to command details structure or NULL
1088  **/
1089 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1090                                     u16 flags, u8 *mac_addr,
1091                                     struct i40e_asq_cmd_details *cmd_details)
1092 {
1093         struct i40e_aq_desc desc;
1094         struct i40e_aqc_mac_address_write *cmd_data =
1095                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1096         enum i40e_status_code status;
1097
1098         i40e_fill_default_direct_cmd_desc(&desc,
1099                                           i40e_aqc_opc_mac_address_write);
1100         cmd_data->command_flags = CPU_TO_LE16(flags);
1101         cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1102         cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1103                                         ((u32)mac_addr[3] << 16) |
1104                                         ((u32)mac_addr[4] << 8) |
1105                                         mac_addr[5]);
1106
1107         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1108
1109         return status;
1110 }
1111
1112 /**
1113  * i40e_get_mac_addr - get MAC address
1114  * @hw: pointer to the HW structure
1115  * @mac_addr: pointer to MAC address
1116  *
1117  * Reads the adapter's MAC address from register
1118  **/
1119 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1120 {
1121         struct i40e_aqc_mac_address_read_data addrs;
1122         enum i40e_status_code status;
1123         u16 flags = 0;
1124
1125         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1126
1127         if (flags & I40E_AQC_LAN_ADDR_VALID)
1128                 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1129                         I40E_NONDMA_TO_NONDMA);
1130
1131         return status;
1132 }
1133
1134 /**
1135  * i40e_get_port_mac_addr - get Port MAC address
1136  * @hw: pointer to the HW structure
1137  * @mac_addr: pointer to Port MAC address
1138  *
1139  * Reads the adapter's Port MAC address
1140  **/
1141 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1142 {
1143         struct i40e_aqc_mac_address_read_data addrs;
1144         enum i40e_status_code status;
1145         u16 flags = 0;
1146
1147         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1148         if (status)
1149                 return status;
1150
1151         if (flags & I40E_AQC_PORT_ADDR_VALID)
1152                 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1153                         I40E_NONDMA_TO_NONDMA);
1154         else
1155                 status = I40E_ERR_INVALID_MAC_ADDR;
1156
1157         return status;
1158 }
1159
1160 /**
1161  * i40e_pre_tx_queue_cfg - pre tx queue configure
1162  * @hw: pointer to the HW structure
1163  * @queue: target pf queue index
1164  * @enable: state change request
1165  *
1166  * Handles hw requirement to indicate intention to enable
1167  * or disable target queue.
1168  **/
1169 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1170 {
1171         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1172         u32 reg_block = 0;
1173         u32 reg_val;
1174
1175         if (abs_queue_idx >= 128) {
1176                 reg_block = abs_queue_idx / 128;
1177                 abs_queue_idx %= 128;
1178         }
1179
1180         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1181         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1182         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1183
1184         if (enable)
1185                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1186         else
1187                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1188
1189         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1190 }
1191
1192 /**
1193  * i40e_get_san_mac_addr - get SAN MAC address
1194  * @hw: pointer to the HW structure
1195  * @mac_addr: pointer to SAN MAC address
1196  *
1197  * Reads the adapter's SAN MAC address from NVM
1198  **/
1199 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1200                                             u8 *mac_addr)
1201 {
1202         struct i40e_aqc_mac_address_read_data addrs;
1203         enum i40e_status_code status;
1204         u16 flags = 0;
1205
1206         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1207         if (status)
1208                 return status;
1209
1210         if (flags & I40E_AQC_SAN_ADDR_VALID)
1211                 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac),
1212                         I40E_NONDMA_TO_NONDMA);
1213         else
1214                 status = I40E_ERR_INVALID_MAC_ADDR;
1215
1216         return status;
1217 }
1218
1219 /**
1220  *  i40e_read_pba_string - Reads part number string from EEPROM
1221  *  @hw: pointer to hardware structure
1222  *  @pba_num: stores the part number string from the EEPROM
1223  *  @pba_num_size: part number string buffer length
1224  *
1225  *  Reads the part number string from the EEPROM.
1226  **/
1227 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1228                                             u32 pba_num_size)
1229 {
1230         enum i40e_status_code status = I40E_SUCCESS;
1231         u16 pba_word = 0;
1232         u16 pba_size = 0;
1233         u16 pba_ptr = 0;
1234         u16 i = 0;
1235
1236         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1237         if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1238                 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1239                 return status;
1240         }
1241
1242         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1243         if (status != I40E_SUCCESS) {
1244                 DEBUGOUT("Failed to read PBA Block pointer.\n");
1245                 return status;
1246         }
1247
1248         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1249         if (status != I40E_SUCCESS) {
1250                 DEBUGOUT("Failed to read PBA Block size.\n");
1251                 return status;
1252         }
1253
1254         /* Subtract one to get PBA word count (PBA Size word is included in
1255          * total size)
1256          */
1257         pba_size--;
1258         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1259                 DEBUGOUT("Buffer to small for PBA data.\n");
1260                 return I40E_ERR_PARAM;
1261         }
1262
1263         for (i = 0; i < pba_size; i++) {
1264                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1265                 if (status != I40E_SUCCESS) {
1266                         DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1267                         return status;
1268                 }
1269
1270                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1271                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1272         }
1273         pba_num[(pba_size * 2)] = '\0';
1274
1275         return status;
1276 }
1277
1278 /**
1279  * i40e_get_media_type - Gets media type
1280  * @hw: pointer to the hardware structure
1281  **/
1282 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1283 {
1284         enum i40e_media_type media;
1285
1286         switch (hw->phy.link_info.phy_type) {
1287         case I40E_PHY_TYPE_10GBASE_SR:
1288         case I40E_PHY_TYPE_10GBASE_LR:
1289         case I40E_PHY_TYPE_1000BASE_SX:
1290         case I40E_PHY_TYPE_1000BASE_LX:
1291         case I40E_PHY_TYPE_40GBASE_SR4:
1292         case I40E_PHY_TYPE_40GBASE_LR4:
1293         case I40E_PHY_TYPE_25GBASE_LR:
1294         case I40E_PHY_TYPE_25GBASE_SR:
1295                 media = I40E_MEDIA_TYPE_FIBER;
1296                 break;
1297         case I40E_PHY_TYPE_100BASE_TX:
1298         case I40E_PHY_TYPE_1000BASE_T:
1299         case I40E_PHY_TYPE_10GBASE_T:
1300                 media = I40E_MEDIA_TYPE_BASET;
1301                 break;
1302         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1303         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1304         case I40E_PHY_TYPE_10GBASE_CR1:
1305         case I40E_PHY_TYPE_40GBASE_CR4:
1306         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1307         case I40E_PHY_TYPE_40GBASE_AOC:
1308         case I40E_PHY_TYPE_10GBASE_AOC:
1309         case I40E_PHY_TYPE_25GBASE_CR:
1310                 media = I40E_MEDIA_TYPE_DA;
1311                 break;
1312         case I40E_PHY_TYPE_1000BASE_KX:
1313         case I40E_PHY_TYPE_10GBASE_KX4:
1314         case I40E_PHY_TYPE_10GBASE_KR:
1315         case I40E_PHY_TYPE_40GBASE_KR4:
1316         case I40E_PHY_TYPE_20GBASE_KR2:
1317         case I40E_PHY_TYPE_25GBASE_KR:
1318                 media = I40E_MEDIA_TYPE_BACKPLANE;
1319                 break;
1320         case I40E_PHY_TYPE_SGMII:
1321         case I40E_PHY_TYPE_XAUI:
1322         case I40E_PHY_TYPE_XFI:
1323         case I40E_PHY_TYPE_XLAUI:
1324         case I40E_PHY_TYPE_XLPPI:
1325         default:
1326                 media = I40E_MEDIA_TYPE_UNKNOWN;
1327                 break;
1328         }
1329
1330         return media;
1331 }
1332
1333 #define I40E_PF_RESET_WAIT_COUNT        200
1334 /**
1335  * i40e_pf_reset - Reset the PF
1336  * @hw: pointer to the hardware structure
1337  *
1338  * Assuming someone else has triggered a global reset,
1339  * assure the global reset is complete and then reset the PF
1340  **/
1341 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1342 {
1343         u32 cnt = 0;
1344         u32 cnt1 = 0;
1345         u32 reg = 0;
1346         u32 grst_del;
1347
1348         /* Poll for Global Reset steady state in case of recent GRST.
1349          * The grst delay value is in 100ms units, and we'll wait a
1350          * couple counts longer to be sure we don't just miss the end.
1351          */
1352         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1353                         I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1354                         I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1355
1356         grst_del = grst_del * 20;
1357
1358         for (cnt = 0; cnt < grst_del; cnt++) {
1359                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1360                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1361                         break;
1362                 i40e_msec_delay(100);
1363         }
1364         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1365                 DEBUGOUT("Global reset polling failed to complete.\n");
1366                 return I40E_ERR_RESET_FAILED;
1367         }
1368
1369         /* Now Wait for the FW to be ready */
1370         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1371                 reg = rd32(hw, I40E_GLNVM_ULD);
1372                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1373                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1374                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1375                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1376                         DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1377                         break;
1378                 }
1379                 i40e_msec_delay(10);
1380         }
1381         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1382                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1383                 DEBUGOUT("wait for FW Reset complete timedout\n");
1384                 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1385                 return I40E_ERR_RESET_FAILED;
1386         }
1387
1388         /* If there was a Global Reset in progress when we got here,
1389          * we don't need to do the PF Reset
1390          */
1391         if (!cnt) {
1392                 reg = rd32(hw, I40E_PFGEN_CTRL);
1393                 wr32(hw, I40E_PFGEN_CTRL,
1394                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1395                 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1396                         reg = rd32(hw, I40E_PFGEN_CTRL);
1397                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1398                                 break;
1399                         i40e_msec_delay(1);
1400                 }
1401                 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1402                         DEBUGOUT("PF reset polling failed to complete.\n");
1403                         return I40E_ERR_RESET_FAILED;
1404                 }
1405         }
1406
1407         i40e_clear_pxe_mode(hw);
1408
1409
1410         return I40E_SUCCESS;
1411 }
1412
1413 /**
1414  * i40e_clear_hw - clear out any left over hw state
1415  * @hw: pointer to the hw struct
1416  *
1417  * Clear queues and interrupts, typically called at init time,
1418  * but after the capabilities have been found so we know how many
1419  * queues and msix vectors have been allocated.
1420  **/
1421 void i40e_clear_hw(struct i40e_hw *hw)
1422 {
1423         u32 num_queues, base_queue;
1424         u32 num_pf_int;
1425         u32 num_vf_int;
1426         u32 num_vfs;
1427         u32 i, j;
1428         u32 val;
1429         u32 eol = 0x7ff;
1430
1431         /* get number of interrupts, queues, and vfs */
1432         val = rd32(hw, I40E_GLPCI_CNF2);
1433         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1434                         I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1435         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1436                         I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1437
1438         val = rd32(hw, I40E_PFLAN_QALLOC);
1439         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1440                         I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1441         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1442                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1443         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1444                 num_queues = (j - base_queue) + 1;
1445         else
1446                 num_queues = 0;
1447
1448         val = rd32(hw, I40E_PF_VT_PFALLOC);
1449         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1450                         I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1451         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1452                         I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1453         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1454                 num_vfs = (j - i) + 1;
1455         else
1456                 num_vfs = 0;
1457
1458         /* stop all the interrupts */
1459         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1460         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1461         for (i = 0; i < num_pf_int - 2; i++)
1462                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1463
1464         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1465         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1466         wr32(hw, I40E_PFINT_LNKLST0, val);
1467         for (i = 0; i < num_pf_int - 2; i++)
1468                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1469         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1470         for (i = 0; i < num_vfs; i++)
1471                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1472         for (i = 0; i < num_vf_int - 2; i++)
1473                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1474
1475         /* warn the HW of the coming Tx disables */
1476         for (i = 0; i < num_queues; i++) {
1477                 u32 abs_queue_idx = base_queue + i;
1478                 u32 reg_block = 0;
1479
1480                 if (abs_queue_idx >= 128) {
1481                         reg_block = abs_queue_idx / 128;
1482                         abs_queue_idx %= 128;
1483                 }
1484
1485                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1486                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1487                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1488                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1489
1490                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1491         }
1492         i40e_usec_delay(400);
1493
1494         /* stop all the queues */
1495         for (i = 0; i < num_queues; i++) {
1496                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1497                 wr32(hw, I40E_QTX_ENA(i), 0);
1498                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1499                 wr32(hw, I40E_QRX_ENA(i), 0);
1500         }
1501
1502         /* short wait for all queue disables to settle */
1503         i40e_usec_delay(50);
1504 }
1505
1506 /**
1507  * i40e_clear_pxe_mode - clear pxe operations mode
1508  * @hw: pointer to the hw struct
1509  *
1510  * Make sure all PXE mode settings are cleared, including things
1511  * like descriptor fetch/write-back mode.
1512  **/
1513 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1514 {
1515         if (i40e_check_asq_alive(hw))
1516                 i40e_aq_clear_pxe_mode(hw, NULL);
1517 }
1518
1519 /**
1520  * i40e_led_is_mine - helper to find matching led
1521  * @hw: pointer to the hw struct
1522  * @idx: index into GPIO registers
1523  *
1524  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1525  */
1526 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1527 {
1528         u32 gpio_val = 0;
1529         u32 port;
1530
1531         if (!hw->func_caps.led[idx])
1532                 return 0;
1533
1534         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1535         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1536                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1537
1538         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1539          * if it is not our port then ignore
1540          */
1541         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1542             (port != hw->port))
1543                 return 0;
1544
1545         return gpio_val;
1546 }
1547
1548 #define I40E_COMBINED_ACTIVITY 0xA
1549 #define I40E_FILTER_ACTIVITY 0xE
1550 #define I40E_LINK_ACTIVITY 0xC
1551 #define I40E_MAC_ACTIVITY 0xD
1552 #define I40E_LED0 22
1553
1554 /**
1555  * i40e_led_get - return current on/off mode
1556  * @hw: pointer to the hw struct
1557  *
1558  * The value returned is the 'mode' field as defined in the
1559  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1560  * values are variations of possible behaviors relating to
1561  * blink, link, and wire.
1562  **/
1563 u32 i40e_led_get(struct i40e_hw *hw)
1564 {
1565         u32 current_mode = 0;
1566         u32 mode = 0;
1567         int i;
1568
1569         /* as per the documentation GPIO 22-29 are the LED
1570          * GPIO pins named LED0..LED7
1571          */
1572         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1573                 u32 gpio_val = i40e_led_is_mine(hw, i);
1574
1575                 if (!gpio_val)
1576                         continue;
1577
1578                 /* ignore gpio LED src mode entries related to the activity
1579                  *  LEDs
1580                  */
1581                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1582                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1583                 switch (current_mode) {
1584                 case I40E_COMBINED_ACTIVITY:
1585                 case I40E_FILTER_ACTIVITY:
1586                 case I40E_MAC_ACTIVITY:
1587                         continue;
1588                 default:
1589                         break;
1590                 }
1591
1592                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1593                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1594                 break;
1595         }
1596
1597         return mode;
1598 }
1599
1600 /**
1601  * i40e_led_set - set new on/off mode
1602  * @hw: pointer to the hw struct
1603  * @mode: 0=off, 0xf=on (else see manual for mode details)
1604  * @blink: true if the LED should blink when on, false if steady
1605  *
1606  * if this function is used to turn on the blink it should
1607  * be used to disable the blink when restoring the original state.
1608  **/
1609 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1610 {
1611         u32 current_mode = 0;
1612         int i;
1613
1614         if (mode & 0xfffffff0)
1615                 DEBUGOUT1("invalid mode passed in %X\n", mode);
1616
1617         /* as per the documentation GPIO 22-29 are the LED
1618          * GPIO pins named LED0..LED7
1619          */
1620         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1621                 u32 gpio_val = i40e_led_is_mine(hw, i);
1622
1623                 if (!gpio_val)
1624                         continue;
1625
1626                 /* ignore gpio LED src mode entries related to the activity
1627                  * LEDs
1628                  */
1629                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1630                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1631                 switch (current_mode) {
1632                 case I40E_COMBINED_ACTIVITY:
1633                 case I40E_FILTER_ACTIVITY:
1634                 case I40E_MAC_ACTIVITY:
1635                         continue;
1636                 default:
1637                         break;
1638                 }
1639
1640                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1641                 /* this & is a bit of paranoia, but serves as a range check */
1642                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1643                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1644
1645                 if (mode == I40E_LINK_ACTIVITY)
1646                         blink = false;
1647
1648                 if (blink)
1649                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1650                 else
1651                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1652
1653                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1654                 break;
1655         }
1656 }
1657
1658 /* Admin command wrappers */
1659
1660 /**
1661  * i40e_aq_get_phy_capabilities
1662  * @hw: pointer to the hw struct
1663  * @abilities: structure for PHY capabilities to be filled
1664  * @qualified_modules: report Qualified Modules
1665  * @report_init: report init capabilities (active are default)
1666  * @cmd_details: pointer to command details structure or NULL
1667  *
1668  * Returns the various PHY abilities supported on the Port.
1669  **/
1670 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1671                         bool qualified_modules, bool report_init,
1672                         struct i40e_aq_get_phy_abilities_resp *abilities,
1673                         struct i40e_asq_cmd_details *cmd_details)
1674 {
1675         struct i40e_aq_desc desc;
1676         enum i40e_status_code status;
1677         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1678
1679         if (!abilities)
1680                 return I40E_ERR_PARAM;
1681
1682         i40e_fill_default_direct_cmd_desc(&desc,
1683                                           i40e_aqc_opc_get_phy_abilities);
1684
1685         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1686         if (abilities_size > I40E_AQ_LARGE_BUF)
1687                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1688
1689         if (qualified_modules)
1690                 desc.params.external.param0 |=
1691                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1692
1693         if (report_init)
1694                 desc.params.external.param0 |=
1695                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1696
1697         status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1698                                     cmd_details);
1699
1700         if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1701                 status = I40E_ERR_UNKNOWN_PHY;
1702
1703         if (report_init) {
1704                 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1705                 hw->phy.phy_types |= ((u64)abilities->phy_type_ext << 32);
1706         }
1707
1708         return status;
1709 }
1710
1711 /**
1712  * i40e_aq_set_phy_config
1713  * @hw: pointer to the hw struct
1714  * @config: structure with PHY configuration to be set
1715  * @cmd_details: pointer to command details structure or NULL
1716  *
1717  * Set the various PHY configuration parameters
1718  * supported on the Port.One or more of the Set PHY config parameters may be
1719  * ignored in an MFP mode as the PF may not have the privilege to set some
1720  * of the PHY Config parameters. This status will be indicated by the
1721  * command response.
1722  **/
1723 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1724                                 struct i40e_aq_set_phy_config *config,
1725                                 struct i40e_asq_cmd_details *cmd_details)
1726 {
1727         struct i40e_aq_desc desc;
1728         struct i40e_aq_set_phy_config *cmd =
1729                 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1730         enum i40e_status_code status;
1731
1732         if (!config)
1733                 return I40E_ERR_PARAM;
1734
1735         i40e_fill_default_direct_cmd_desc(&desc,
1736                                           i40e_aqc_opc_set_phy_config);
1737
1738         *cmd = *config;
1739
1740         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1741
1742         return status;
1743 }
1744
1745 /**
1746  * i40e_set_fc
1747  * @hw: pointer to the hw struct
1748  *
1749  * Set the requested flow control mode using set_phy_config.
1750  **/
1751 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1752                                   bool atomic_restart)
1753 {
1754         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1755         struct i40e_aq_get_phy_abilities_resp abilities;
1756         struct i40e_aq_set_phy_config config;
1757         enum i40e_status_code status;
1758         u8 pause_mask = 0x0;
1759
1760         *aq_failures = 0x0;
1761
1762         switch (fc_mode) {
1763         case I40E_FC_FULL:
1764                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1765                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1766                 break;
1767         case I40E_FC_RX_PAUSE:
1768                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1769                 break;
1770         case I40E_FC_TX_PAUSE:
1771                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1772                 break;
1773         default:
1774                 break;
1775         }
1776
1777         /* Get the current phy config */
1778         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1779                                               NULL);
1780         if (status) {
1781                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1782                 return status;
1783         }
1784
1785         memset(&config, 0, sizeof(config));
1786         /* clear the old pause settings */
1787         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1788                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1789         /* set the new abilities */
1790         config.abilities |= pause_mask;
1791         /* If the abilities have changed, then set the new config */
1792         if (config.abilities != abilities.abilities) {
1793                 /* Auto restart link so settings take effect */
1794                 if (atomic_restart)
1795                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1796                 /* Copy over all the old settings */
1797                 config.phy_type = abilities.phy_type;
1798                 config.phy_type_ext = abilities.phy_type_ext;
1799                 config.link_speed = abilities.link_speed;
1800                 config.eee_capability = abilities.eee_capability;
1801                 config.eeer = abilities.eeer_val;
1802                 config.low_power_ctrl = abilities.d3_lpan;
1803                 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1804                                     I40E_AQ_PHY_FEC_CONFIG_MASK;
1805                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1806
1807                 if (status)
1808                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1809         }
1810         /* Update the link info */
1811         status = i40e_update_link_info(hw);
1812         if (status) {
1813                 /* Wait a little bit (on 40G cards it sometimes takes a really
1814                  * long time for link to come back from the atomic reset)
1815                  * and try once more
1816                  */
1817                 i40e_msec_delay(1000);
1818                 status = i40e_update_link_info(hw);
1819         }
1820         if (status)
1821                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1822
1823         return status;
1824 }
1825
1826 /**
1827  * i40e_aq_set_mac_config
1828  * @hw: pointer to the hw struct
1829  * @max_frame_size: Maximum Frame Size to be supported by the port
1830  * @crc_en: Tell HW to append a CRC to outgoing frames
1831  * @pacing: Pacing configurations
1832  * @cmd_details: pointer to command details structure or NULL
1833  *
1834  * Configure MAC settings for frame size, jumbo frame support and the
1835  * addition of a CRC by the hardware.
1836  **/
1837 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1838                                 u16 max_frame_size,
1839                                 bool crc_en, u16 pacing,
1840                                 struct i40e_asq_cmd_details *cmd_details)
1841 {
1842         struct i40e_aq_desc desc;
1843         struct i40e_aq_set_mac_config *cmd =
1844                 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1845         enum i40e_status_code status;
1846
1847         if (max_frame_size == 0)
1848                 return I40E_ERR_PARAM;
1849
1850         i40e_fill_default_direct_cmd_desc(&desc,
1851                                           i40e_aqc_opc_set_mac_config);
1852
1853         cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1854         cmd->params = ((u8)pacing & 0x0F) << 3;
1855         if (crc_en)
1856                 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1857
1858         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1859
1860         return status;
1861 }
1862
1863 /**
1864  * i40e_aq_clear_pxe_mode
1865  * @hw: pointer to the hw struct
1866  * @cmd_details: pointer to command details structure or NULL
1867  *
1868  * Tell the firmware that the driver is taking over from PXE
1869  **/
1870 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1871                         struct i40e_asq_cmd_details *cmd_details)
1872 {
1873         enum i40e_status_code status;
1874         struct i40e_aq_desc desc;
1875         struct i40e_aqc_clear_pxe *cmd =
1876                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1877
1878         i40e_fill_default_direct_cmd_desc(&desc,
1879                                           i40e_aqc_opc_clear_pxe_mode);
1880
1881         cmd->rx_cnt = 0x2;
1882
1883         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1884
1885         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1886
1887         return status;
1888 }
1889
1890 /**
1891  * i40e_aq_set_link_restart_an
1892  * @hw: pointer to the hw struct
1893  * @enable_link: if true: enable link, if false: disable link
1894  * @cmd_details: pointer to command details structure or NULL
1895  *
1896  * Sets up the link and restarts the Auto-Negotiation over the link.
1897  **/
1898 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1899                 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1900 {
1901         struct i40e_aq_desc desc;
1902         struct i40e_aqc_set_link_restart_an *cmd =
1903                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1904         enum i40e_status_code status;
1905
1906         i40e_fill_default_direct_cmd_desc(&desc,
1907                                           i40e_aqc_opc_set_link_restart_an);
1908
1909         cmd->command = I40E_AQ_PHY_RESTART_AN;
1910         if (enable_link)
1911                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1912         else
1913                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1914
1915         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1916
1917         return status;
1918 }
1919
1920 /**
1921  * i40e_aq_get_link_info
1922  * @hw: pointer to the hw struct
1923  * @enable_lse: enable/disable LinkStatusEvent reporting
1924  * @link: pointer to link status structure - optional
1925  * @cmd_details: pointer to command details structure or NULL
1926  *
1927  * Returns the link status of the adapter.
1928  **/
1929 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1930                                 bool enable_lse, struct i40e_link_status *link,
1931                                 struct i40e_asq_cmd_details *cmd_details)
1932 {
1933         struct i40e_aq_desc desc;
1934         struct i40e_aqc_get_link_status *resp =
1935                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1936         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1937         enum i40e_status_code status;
1938         bool tx_pause, rx_pause;
1939         u16 command_flags;
1940
1941         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1942
1943         if (enable_lse)
1944                 command_flags = I40E_AQ_LSE_ENABLE;
1945         else
1946                 command_flags = I40E_AQ_LSE_DISABLE;
1947         resp->command_flags = CPU_TO_LE16(command_flags);
1948
1949         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1950
1951         if (status != I40E_SUCCESS)
1952                 goto aq_get_link_info_exit;
1953
1954         /* save off old link status information */
1955         i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1956                     sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1957
1958         /* update link status */
1959         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1960         hw->phy.media_type = i40e_get_media_type(hw);
1961         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1962         hw_link_info->link_info = resp->link_info;
1963         hw_link_info->an_info = resp->an_info;
1964         hw_link_info->ext_info = resp->ext_info;
1965         hw_link_info->loopback = resp->loopback;
1966         hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1967         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1968
1969         /* update fc info */
1970         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1971         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1972         if (tx_pause & rx_pause)
1973                 hw->fc.current_mode = I40E_FC_FULL;
1974         else if (tx_pause)
1975                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1976         else if (rx_pause)
1977                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1978         else
1979                 hw->fc.current_mode = I40E_FC_NONE;
1980
1981         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1982                 hw_link_info->crc_enable = true;
1983         else
1984                 hw_link_info->crc_enable = false;
1985
1986         if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
1987                 hw_link_info->lse_enable = true;
1988         else
1989                 hw_link_info->lse_enable = false;
1990
1991         if ((hw->mac.type == I40E_MAC_XL710) &&
1992             (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1993              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1994                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1995
1996         /* save link status information */
1997         if (link)
1998                 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1999                             I40E_NONDMA_TO_NONDMA);
2000
2001         /* flag cleared so helper functions don't call AQ again */
2002         hw->phy.get_link_info = false;
2003
2004 aq_get_link_info_exit:
2005         return status;
2006 }
2007
2008 /**
2009  * i40e_aq_set_phy_int_mask
2010  * @hw: pointer to the hw struct
2011  * @mask: interrupt mask to be set
2012  * @cmd_details: pointer to command details structure or NULL
2013  *
2014  * Set link interrupt mask.
2015  **/
2016 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2017                                 u16 mask,
2018                                 struct i40e_asq_cmd_details *cmd_details)
2019 {
2020         struct i40e_aq_desc desc;
2021         struct i40e_aqc_set_phy_int_mask *cmd =
2022                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2023         enum i40e_status_code status;
2024
2025         i40e_fill_default_direct_cmd_desc(&desc,
2026                                           i40e_aqc_opc_set_phy_int_mask);
2027
2028         cmd->event_mask = CPU_TO_LE16(mask);
2029
2030         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2031
2032         return status;
2033 }
2034
2035 /**
2036  * i40e_aq_get_local_advt_reg
2037  * @hw: pointer to the hw struct
2038  * @advt_reg: local AN advertisement register value
2039  * @cmd_details: pointer to command details structure or NULL
2040  *
2041  * Get the Local AN advertisement register value.
2042  **/
2043 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2044                                 u64 *advt_reg,
2045                                 struct i40e_asq_cmd_details *cmd_details)
2046 {
2047         struct i40e_aq_desc desc;
2048         struct i40e_aqc_an_advt_reg *resp =
2049                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2050         enum i40e_status_code status;
2051
2052         i40e_fill_default_direct_cmd_desc(&desc,
2053                                           i40e_aqc_opc_get_local_advt_reg);
2054
2055         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2056
2057         if (status != I40E_SUCCESS)
2058                 goto aq_get_local_advt_reg_exit;
2059
2060         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2061         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2062
2063 aq_get_local_advt_reg_exit:
2064         return status;
2065 }
2066
2067 /**
2068  * i40e_aq_set_local_advt_reg
2069  * @hw: pointer to the hw struct
2070  * @advt_reg: local AN advertisement register value
2071  * @cmd_details: pointer to command details structure or NULL
2072  *
2073  * Get the Local AN advertisement register value.
2074  **/
2075 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2076                                 u64 advt_reg,
2077                                 struct i40e_asq_cmd_details *cmd_details)
2078 {
2079         struct i40e_aq_desc desc;
2080         struct i40e_aqc_an_advt_reg *cmd =
2081                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2082         enum i40e_status_code status;
2083
2084         i40e_fill_default_direct_cmd_desc(&desc,
2085                                           i40e_aqc_opc_get_local_advt_reg);
2086
2087         cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2088         cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2089
2090         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2091
2092         return status;
2093 }
2094
2095 /**
2096  * i40e_aq_get_partner_advt
2097  * @hw: pointer to the hw struct
2098  * @advt_reg: AN partner advertisement register value
2099  * @cmd_details: pointer to command details structure or NULL
2100  *
2101  * Get the link partner AN advertisement register value.
2102  **/
2103 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2104                                 u64 *advt_reg,
2105                                 struct i40e_asq_cmd_details *cmd_details)
2106 {
2107         struct i40e_aq_desc desc;
2108         struct i40e_aqc_an_advt_reg *resp =
2109                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2110         enum i40e_status_code status;
2111
2112         i40e_fill_default_direct_cmd_desc(&desc,
2113                                           i40e_aqc_opc_get_partner_advt);
2114
2115         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2116
2117         if (status != I40E_SUCCESS)
2118                 goto aq_get_partner_advt_exit;
2119
2120         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2121         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2122
2123 aq_get_partner_advt_exit:
2124         return status;
2125 }
2126
2127 /**
2128  * i40e_aq_set_lb_modes
2129  * @hw: pointer to the hw struct
2130  * @lb_modes: loopback mode to be set
2131  * @cmd_details: pointer to command details structure or NULL
2132  *
2133  * Sets loopback modes.
2134  **/
2135 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2136                                 u16 lb_modes,
2137                                 struct i40e_asq_cmd_details *cmd_details)
2138 {
2139         struct i40e_aq_desc desc;
2140         struct i40e_aqc_set_lb_mode *cmd =
2141                 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2142         enum i40e_status_code status;
2143
2144         i40e_fill_default_direct_cmd_desc(&desc,
2145                                           i40e_aqc_opc_set_lb_modes);
2146
2147         cmd->lb_mode = CPU_TO_LE16(lb_modes);
2148
2149         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2150
2151         return status;
2152 }
2153
2154 /**
2155  * i40e_aq_set_phy_debug
2156  * @hw: pointer to the hw struct
2157  * @cmd_flags: debug command flags
2158  * @cmd_details: pointer to command details structure or NULL
2159  *
2160  * Reset the external PHY.
2161  **/
2162 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2163                                 struct i40e_asq_cmd_details *cmd_details)
2164 {
2165         struct i40e_aq_desc desc;
2166         struct i40e_aqc_set_phy_debug *cmd =
2167                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2168         enum i40e_status_code status;
2169
2170         i40e_fill_default_direct_cmd_desc(&desc,
2171                                           i40e_aqc_opc_set_phy_debug);
2172
2173         cmd->command_flags = cmd_flags;
2174
2175         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2176
2177         return status;
2178 }
2179
2180 /**
2181  * i40e_aq_add_vsi
2182  * @hw: pointer to the hw struct
2183  * @vsi_ctx: pointer to a vsi context struct
2184  * @cmd_details: pointer to command details structure or NULL
2185  *
2186  * Add a VSI context to the hardware.
2187 **/
2188 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2189                                 struct i40e_vsi_context *vsi_ctx,
2190                                 struct i40e_asq_cmd_details *cmd_details)
2191 {
2192         struct i40e_aq_desc desc;
2193         struct i40e_aqc_add_get_update_vsi *cmd =
2194                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2195         struct i40e_aqc_add_get_update_vsi_completion *resp =
2196                 (struct i40e_aqc_add_get_update_vsi_completion *)
2197                 &desc.params.raw;
2198         enum i40e_status_code status;
2199
2200         i40e_fill_default_direct_cmd_desc(&desc,
2201                                           i40e_aqc_opc_add_vsi);
2202
2203         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2204         cmd->connection_type = vsi_ctx->connection_type;
2205         cmd->vf_id = vsi_ctx->vf_num;
2206         cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2207
2208         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2209
2210         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2211                                     sizeof(vsi_ctx->info), cmd_details);
2212
2213         if (status != I40E_SUCCESS)
2214                 goto aq_add_vsi_exit;
2215
2216         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2217         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2218         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2219         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2220
2221 aq_add_vsi_exit:
2222         return status;
2223 }
2224
2225 /**
2226  * i40e_aq_set_default_vsi
2227  * @hw: pointer to the hw struct
2228  * @seid: vsi number
2229  * @cmd_details: pointer to command details structure or NULL
2230  **/
2231 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2232                                 u16 seid,
2233                                 struct i40e_asq_cmd_details *cmd_details)
2234 {
2235         struct i40e_aq_desc desc;
2236         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2237                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2238                 &desc.params.raw;
2239         enum i40e_status_code status;
2240
2241         i40e_fill_default_direct_cmd_desc(&desc,
2242                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2243
2244         cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2245         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2246         cmd->seid = CPU_TO_LE16(seid);
2247
2248         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2249
2250         return status;
2251 }
2252
2253 /**
2254  * i40e_aq_clear_default_vsi
2255  * @hw: pointer to the hw struct
2256  * @seid: vsi number
2257  * @cmd_details: pointer to command details structure or NULL
2258  **/
2259 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2260                                 u16 seid,
2261                                 struct i40e_asq_cmd_details *cmd_details)
2262 {
2263         struct i40e_aq_desc desc;
2264         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2265                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2266                 &desc.params.raw;
2267         enum i40e_status_code status;
2268
2269         i40e_fill_default_direct_cmd_desc(&desc,
2270                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2271
2272         cmd->promiscuous_flags = CPU_TO_LE16(0);
2273         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2274         cmd->seid = CPU_TO_LE16(seid);
2275
2276         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2277
2278         return status;
2279 }
2280
2281 /**
2282  * i40e_aq_set_vsi_unicast_promiscuous
2283  * @hw: pointer to the hw struct
2284  * @seid: vsi number
2285  * @set: set unicast promiscuous enable/disable
2286  * @cmd_details: pointer to command details structure or NULL
2287  * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2288  **/
2289 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2290                                 u16 seid, bool set,
2291                                 struct i40e_asq_cmd_details *cmd_details,
2292                                 bool rx_only_promisc)
2293 {
2294         struct i40e_aq_desc desc;
2295         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2296                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2297         enum i40e_status_code status;
2298         u16 flags = 0;
2299
2300         i40e_fill_default_direct_cmd_desc(&desc,
2301                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2302
2303         if (set) {
2304                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2305                 if (rx_only_promisc &&
2306                     (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2307                      (hw->aq.api_maj_ver > 1)))
2308                         flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2309         }
2310
2311         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2312
2313         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2314         if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2315              (hw->aq.api_maj_ver > 1))
2316                 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2317
2318         cmd->seid = CPU_TO_LE16(seid);
2319         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2320
2321         return status;
2322 }
2323
2324 /**
2325  * i40e_aq_set_vsi_multicast_promiscuous
2326  * @hw: pointer to the hw struct
2327  * @seid: vsi number
2328  * @set: set multicast promiscuous enable/disable
2329  * @cmd_details: pointer to command details structure or NULL
2330  **/
2331 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2332                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2333 {
2334         struct i40e_aq_desc desc;
2335         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2336                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2337         enum i40e_status_code status;
2338         u16 flags = 0;
2339
2340         i40e_fill_default_direct_cmd_desc(&desc,
2341                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2342
2343         if (set)
2344                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2345
2346         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2347
2348         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2349
2350         cmd->seid = CPU_TO_LE16(seid);
2351         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2352
2353         return status;
2354 }
2355
2356 /**
2357 * i40e_aq_set_vsi_full_promiscuous
2358 * @hw: pointer to the hw struct
2359 * @seid: VSI number
2360 * @set: set promiscuous enable/disable
2361 * @cmd_details: pointer to command details structure or NULL
2362 **/
2363 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw,
2364                                 u16 seid, bool set,
2365                                 struct i40e_asq_cmd_details *cmd_details)
2366 {
2367         struct i40e_aq_desc desc;
2368         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2369                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2370         enum i40e_status_code status;
2371         u16 flags = 0;
2372
2373         i40e_fill_default_direct_cmd_desc(&desc,
2374                 i40e_aqc_opc_set_vsi_promiscuous_modes);
2375
2376         if (set)
2377                 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2378                         I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2379                         I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2380
2381         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2382
2383         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2384                                        I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2385                                        I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2386
2387         cmd->seid = CPU_TO_LE16(seid);
2388         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2389
2390         return status;
2391 }
2392
2393 /**
2394  * i40e_aq_set_vsi_mc_promisc_on_vlan
2395  * @hw: pointer to the hw struct
2396  * @seid: vsi number
2397  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2398  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2399  * @cmd_details: pointer to command details structure or NULL
2400  **/
2401 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2402                                 u16 seid, bool enable, u16 vid,
2403                                 struct i40e_asq_cmd_details *cmd_details)
2404 {
2405         struct i40e_aq_desc desc;
2406         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2407                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2408         enum i40e_status_code status;
2409         u16 flags = 0;
2410
2411         i40e_fill_default_direct_cmd_desc(&desc,
2412                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2413
2414         if (enable)
2415                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2416
2417         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2418         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2419         cmd->seid = CPU_TO_LE16(seid);
2420         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2421
2422         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2423
2424         return status;
2425 }
2426
2427 /**
2428  * i40e_aq_set_vsi_uc_promisc_on_vlan
2429  * @hw: pointer to the hw struct
2430  * @seid: vsi number
2431  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2432  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2433  * @cmd_details: pointer to command details structure or NULL
2434  **/
2435 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2436                                 u16 seid, bool enable, u16 vid,
2437                                 struct i40e_asq_cmd_details *cmd_details)
2438 {
2439         struct i40e_aq_desc desc;
2440         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2441                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2442         enum i40e_status_code status;
2443         u16 flags = 0;
2444
2445         i40e_fill_default_direct_cmd_desc(&desc,
2446                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2447
2448         if (enable)
2449                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2450
2451         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2452         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2453         cmd->seid = CPU_TO_LE16(seid);
2454         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2455
2456         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2457
2458         return status;
2459 }
2460
2461 /**
2462  * i40e_aq_set_vsi_broadcast
2463  * @hw: pointer to the hw struct
2464  * @seid: vsi number
2465  * @set_filter: true to set filter, false to clear filter
2466  * @cmd_details: pointer to command details structure or NULL
2467  *
2468  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2469  **/
2470 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2471                                 u16 seid, bool set_filter,
2472                                 struct i40e_asq_cmd_details *cmd_details)
2473 {
2474         struct i40e_aq_desc desc;
2475         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2476                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2477         enum i40e_status_code status;
2478
2479         i40e_fill_default_direct_cmd_desc(&desc,
2480                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2481
2482         if (set_filter)
2483                 cmd->promiscuous_flags
2484                             |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2485         else
2486                 cmd->promiscuous_flags
2487                             &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2488
2489         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2490         cmd->seid = CPU_TO_LE16(seid);
2491         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2492
2493         return status;
2494 }
2495
2496 /**
2497  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2498  * @hw: pointer to the hw struct
2499  * @seid: vsi number
2500  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2501  * @cmd_details: pointer to command details structure or NULL
2502  **/
2503 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2504                                 u16 seid, bool enable,
2505                                 struct i40e_asq_cmd_details *cmd_details)
2506 {
2507         struct i40e_aq_desc desc;
2508         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2509                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2510         enum i40e_status_code status;
2511         u16 flags = 0;
2512
2513         i40e_fill_default_direct_cmd_desc(&desc,
2514                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2515         if (enable)
2516                 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2517
2518         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2519         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2520         cmd->seid = CPU_TO_LE16(seid);
2521
2522         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2523
2524         return status;
2525 }
2526
2527 /**
2528  * i40e_get_vsi_params - get VSI configuration info
2529  * @hw: pointer to the hw struct
2530  * @vsi_ctx: pointer to a vsi context struct
2531  * @cmd_details: pointer to command details structure or NULL
2532  **/
2533 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2534                                 struct i40e_vsi_context *vsi_ctx,
2535                                 struct i40e_asq_cmd_details *cmd_details)
2536 {
2537         struct i40e_aq_desc desc;
2538         struct i40e_aqc_add_get_update_vsi *cmd =
2539                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2540         struct i40e_aqc_add_get_update_vsi_completion *resp =
2541                 (struct i40e_aqc_add_get_update_vsi_completion *)
2542                 &desc.params.raw;
2543         enum i40e_status_code status;
2544
2545         UNREFERENCED_1PARAMETER(cmd_details);
2546         i40e_fill_default_direct_cmd_desc(&desc,
2547                                           i40e_aqc_opc_get_vsi_parameters);
2548
2549         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2550
2551         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2552
2553         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2554                                     sizeof(vsi_ctx->info), NULL);
2555
2556         if (status != I40E_SUCCESS)
2557                 goto aq_get_vsi_params_exit;
2558
2559         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2560         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2561         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2562         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2563
2564 aq_get_vsi_params_exit:
2565         return status;
2566 }
2567
2568 /**
2569  * i40e_aq_update_vsi_params
2570  * @hw: pointer to the hw struct
2571  * @vsi_ctx: pointer to a vsi context struct
2572  * @cmd_details: pointer to command details structure or NULL
2573  *
2574  * Update a VSI context.
2575  **/
2576 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2577                                 struct i40e_vsi_context *vsi_ctx,
2578                                 struct i40e_asq_cmd_details *cmd_details)
2579 {
2580         struct i40e_aq_desc desc;
2581         struct i40e_aqc_add_get_update_vsi *cmd =
2582                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2583         struct i40e_aqc_add_get_update_vsi_completion *resp =
2584                 (struct i40e_aqc_add_get_update_vsi_completion *)
2585                 &desc.params.raw;
2586         enum i40e_status_code status;
2587
2588         i40e_fill_default_direct_cmd_desc(&desc,
2589                                           i40e_aqc_opc_update_vsi_parameters);
2590         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2591
2592         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2593
2594         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2595                                     sizeof(vsi_ctx->info), cmd_details);
2596
2597         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2598         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2599
2600         return status;
2601 }
2602
2603 /**
2604  * i40e_aq_get_switch_config
2605  * @hw: pointer to the hardware structure
2606  * @buf: pointer to the result buffer
2607  * @buf_size: length of input buffer
2608  * @start_seid: seid to start for the report, 0 == beginning
2609  * @cmd_details: pointer to command details structure or NULL
2610  *
2611  * Fill the buf with switch configuration returned from AdminQ command
2612  **/
2613 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2614                                 struct i40e_aqc_get_switch_config_resp *buf,
2615                                 u16 buf_size, u16 *start_seid,
2616                                 struct i40e_asq_cmd_details *cmd_details)
2617 {
2618         struct i40e_aq_desc desc;
2619         struct i40e_aqc_switch_seid *scfg =
2620                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2621         enum i40e_status_code status;
2622
2623         i40e_fill_default_direct_cmd_desc(&desc,
2624                                           i40e_aqc_opc_get_switch_config);
2625         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2626         if (buf_size > I40E_AQ_LARGE_BUF)
2627                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2628         scfg->seid = CPU_TO_LE16(*start_seid);
2629
2630         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2631         *start_seid = LE16_TO_CPU(scfg->seid);
2632
2633         return status;
2634 }
2635
2636 /**
2637  * i40e_aq_set_switch_config
2638  * @hw: pointer to the hardware structure
2639  * @flags: bit flag values to set
2640  * @valid_flags: which bit flags to set
2641  * @cmd_details: pointer to command details structure or NULL
2642  *
2643  * Set switch configuration bits
2644  **/
2645 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2646                                 u16 flags, u16 valid_flags,
2647                                 struct i40e_asq_cmd_details *cmd_details)
2648 {
2649         struct i40e_aq_desc desc;
2650         struct i40e_aqc_set_switch_config *scfg =
2651                 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2652         enum i40e_status_code status;
2653
2654         i40e_fill_default_direct_cmd_desc(&desc,
2655                                           i40e_aqc_opc_set_switch_config);
2656         scfg->flags = CPU_TO_LE16(flags);
2657         scfg->valid_flags = CPU_TO_LE16(valid_flags);
2658
2659         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2660
2661         return status;
2662 }
2663
2664 /**
2665  * i40e_aq_get_firmware_version
2666  * @hw: pointer to the hw struct
2667  * @fw_major_version: firmware major version
2668  * @fw_minor_version: firmware minor version
2669  * @fw_build: firmware build number
2670  * @api_major_version: major queue version
2671  * @api_minor_version: minor queue version
2672  * @cmd_details: pointer to command details structure or NULL
2673  *
2674  * Get the firmware version from the admin queue commands
2675  **/
2676 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2677                                 u16 *fw_major_version, u16 *fw_minor_version,
2678                                 u32 *fw_build,
2679                                 u16 *api_major_version, u16 *api_minor_version,
2680                                 struct i40e_asq_cmd_details *cmd_details)
2681 {
2682         struct i40e_aq_desc desc;
2683         struct i40e_aqc_get_version *resp =
2684                 (struct i40e_aqc_get_version *)&desc.params.raw;
2685         enum i40e_status_code status;
2686
2687         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2688
2689         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2690
2691         if (status == I40E_SUCCESS) {
2692                 if (fw_major_version != NULL)
2693                         *fw_major_version = LE16_TO_CPU(resp->fw_major);
2694                 if (fw_minor_version != NULL)
2695                         *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2696                 if (fw_build != NULL)
2697                         *fw_build = LE32_TO_CPU(resp->fw_build);
2698                 if (api_major_version != NULL)
2699                         *api_major_version = LE16_TO_CPU(resp->api_major);
2700                 if (api_minor_version != NULL)
2701                         *api_minor_version = LE16_TO_CPU(resp->api_minor);
2702
2703                 /* A workaround to fix the API version in SW */
2704                 if (api_major_version && api_minor_version &&
2705                     fw_major_version && fw_minor_version &&
2706                     ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2707                     (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2708                      (*fw_major_version > 4)))
2709                         *api_minor_version = 2;
2710         }
2711
2712         return status;
2713 }
2714
2715 /**
2716  * i40e_aq_send_driver_version
2717  * @hw: pointer to the hw struct
2718  * @dv: driver's major, minor version
2719  * @cmd_details: pointer to command details structure or NULL
2720  *
2721  * Send the driver version to the firmware
2722  **/
2723 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2724                                 struct i40e_driver_version *dv,
2725                                 struct i40e_asq_cmd_details *cmd_details)
2726 {
2727         struct i40e_aq_desc desc;
2728         struct i40e_aqc_driver_version *cmd =
2729                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2730         enum i40e_status_code status;
2731         u16 len;
2732
2733         if (dv == NULL)
2734                 return I40E_ERR_PARAM;
2735
2736         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2737
2738         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2739         cmd->driver_major_ver = dv->major_version;
2740         cmd->driver_minor_ver = dv->minor_version;
2741         cmd->driver_build_ver = dv->build_version;
2742         cmd->driver_subbuild_ver = dv->subbuild_version;
2743
2744         len = 0;
2745         while (len < sizeof(dv->driver_string) &&
2746                (dv->driver_string[len] < 0x80) &&
2747                dv->driver_string[len])
2748                 len++;
2749         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2750                                        len, cmd_details);
2751
2752         return status;
2753 }
2754
2755 /**
2756  * i40e_get_link_status - get status of the HW network link
2757  * @hw: pointer to the hw struct
2758  * @link_up: pointer to bool (true/false = linkup/linkdown)
2759  *
2760  * Variable link_up true if link is up, false if link is down.
2761  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2762  *
2763  * Side effect: LinkStatusEvent reporting becomes enabled
2764  **/
2765 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2766 {
2767         enum i40e_status_code status = I40E_SUCCESS;
2768
2769         if (hw->phy.get_link_info) {
2770                 status = i40e_update_link_info(hw);
2771
2772                 if (status != I40E_SUCCESS)
2773                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2774                                    status);
2775         }
2776
2777         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2778
2779         return status;
2780 }
2781
2782 /**
2783  * i40e_updatelink_status - update status of the HW network link
2784  * @hw: pointer to the hw struct
2785  **/
2786 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2787 {
2788         struct i40e_aq_get_phy_abilities_resp abilities;
2789         enum i40e_status_code status = I40E_SUCCESS;
2790
2791         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2792         if (status)
2793                 return status;
2794
2795         /* extra checking needed to ensure link info to user is timely */
2796         if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2797             ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2798              !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2799                 status = i40e_aq_get_phy_capabilities(hw, false, false,
2800                                                       &abilities, NULL);
2801                 if (status)
2802                         return status;
2803
2804                 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2805                         sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2806         }
2807         return status;
2808 }
2809
2810
2811 /**
2812  * i40e_get_link_speed
2813  * @hw: pointer to the hw struct
2814  *
2815  * Returns the link speed of the adapter.
2816  **/
2817 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2818 {
2819         enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2820         enum i40e_status_code status = I40E_SUCCESS;
2821
2822         if (hw->phy.get_link_info) {
2823                 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2824
2825                 if (status != I40E_SUCCESS)
2826                         goto i40e_link_speed_exit;
2827         }
2828
2829         speed = hw->phy.link_info.link_speed;
2830
2831 i40e_link_speed_exit:
2832         return speed;
2833 }
2834
2835 /**
2836  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2837  * @hw: pointer to the hw struct
2838  * @uplink_seid: the MAC or other gizmo SEID
2839  * @downlink_seid: the VSI SEID
2840  * @enabled_tc: bitmap of TCs to be enabled
2841  * @default_port: true for default port VSI, false for control port
2842  * @veb_seid: pointer to where to put the resulting VEB SEID
2843  * @enable_stats: true to turn on VEB stats
2844  * @cmd_details: pointer to command details structure or NULL
2845  *
2846  * This asks the FW to add a VEB between the uplink and downlink
2847  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2848  **/
2849 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2850                                 u16 downlink_seid, u8 enabled_tc,
2851                                 bool default_port, u16 *veb_seid,
2852                                 bool enable_stats,
2853                                 struct i40e_asq_cmd_details *cmd_details)
2854 {
2855         struct i40e_aq_desc desc;
2856         struct i40e_aqc_add_veb *cmd =
2857                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2858         struct i40e_aqc_add_veb_completion *resp =
2859                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2860         enum i40e_status_code status;
2861         u16 veb_flags = 0;
2862
2863         /* SEIDs need to either both be set or both be 0 for floating VEB */
2864         if (!!uplink_seid != !!downlink_seid)
2865                 return I40E_ERR_PARAM;
2866
2867         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2868
2869         cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2870         cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2871         cmd->enable_tcs = enabled_tc;
2872         if (!uplink_seid)
2873                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2874         if (default_port)
2875                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2876         else
2877                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2878
2879         /* reverse logic here: set the bitflag to disable the stats */
2880         if (!enable_stats)
2881                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2882
2883         cmd->veb_flags = CPU_TO_LE16(veb_flags);
2884
2885         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2886
2887         if (!status && veb_seid)
2888                 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2889
2890         return status;
2891 }
2892
2893 /**
2894  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2895  * @hw: pointer to the hw struct
2896  * @veb_seid: the SEID of the VEB to query
2897  * @switch_id: the uplink switch id
2898  * @floating: set to true if the VEB is floating
2899  * @statistic_index: index of the stats counter block for this VEB
2900  * @vebs_used: number of VEB's used by function
2901  * @vebs_free: total VEB's not reserved by any function
2902  * @cmd_details: pointer to command details structure or NULL
2903  *
2904  * This retrieves the parameters for a particular VEB, specified by
2905  * uplink_seid, and returns them to the caller.
2906  **/
2907 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2908                                 u16 veb_seid, u16 *switch_id,
2909                                 bool *floating, u16 *statistic_index,
2910                                 u16 *vebs_used, u16 *vebs_free,
2911                                 struct i40e_asq_cmd_details *cmd_details)
2912 {
2913         struct i40e_aq_desc desc;
2914         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2915                 (struct i40e_aqc_get_veb_parameters_completion *)
2916                 &desc.params.raw;
2917         enum i40e_status_code status;
2918
2919         if (veb_seid == 0)
2920                 return I40E_ERR_PARAM;
2921
2922         i40e_fill_default_direct_cmd_desc(&desc,
2923                                           i40e_aqc_opc_get_veb_parameters);
2924         cmd_resp->seid = CPU_TO_LE16(veb_seid);
2925
2926         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2927         if (status)
2928                 goto get_veb_exit;
2929
2930         if (switch_id)
2931                 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2932         if (statistic_index)
2933                 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2934         if (vebs_used)
2935                 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2936         if (vebs_free)
2937                 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2938         if (floating) {
2939                 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2940
2941                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2942                         *floating = true;
2943                 else
2944                         *floating = false;
2945         }
2946
2947 get_veb_exit:
2948         return status;
2949 }
2950
2951 /**
2952  * i40e_aq_add_macvlan
2953  * @hw: pointer to the hw struct
2954  * @seid: VSI for the mac address
2955  * @mv_list: list of macvlans to be added
2956  * @count: length of the list
2957  * @cmd_details: pointer to command details structure or NULL
2958  *
2959  * Add MAC/VLAN addresses to the HW filtering
2960  **/
2961 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2962                         struct i40e_aqc_add_macvlan_element_data *mv_list,
2963                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2964 {
2965         struct i40e_aq_desc desc;
2966         struct i40e_aqc_macvlan *cmd =
2967                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2968         enum i40e_status_code status;
2969         u16 buf_size;
2970         int i;
2971
2972         if (count == 0 || !mv_list || !hw)
2973                 return I40E_ERR_PARAM;
2974
2975         buf_size = count * sizeof(*mv_list);
2976
2977         /* prep the rest of the request */
2978         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2979         cmd->num_addresses = CPU_TO_LE16(count);
2980         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2981         cmd->seid[1] = 0;
2982         cmd->seid[2] = 0;
2983
2984         for (i = 0; i < count; i++)
2985                 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
2986                         mv_list[i].flags |=
2987                             CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2988
2989         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2990         if (buf_size > I40E_AQ_LARGE_BUF)
2991                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2992
2993         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2994                                        cmd_details);
2995
2996         return status;
2997 }
2998
2999 /**
3000  * i40e_aq_remove_macvlan
3001  * @hw: pointer to the hw struct
3002  * @seid: VSI for the mac address
3003  * @mv_list: list of macvlans to be removed
3004  * @count: length of the list
3005  * @cmd_details: pointer to command details structure or NULL
3006  *
3007  * Remove MAC/VLAN addresses from the HW filtering
3008  **/
3009 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
3010                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
3011                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3012 {
3013         struct i40e_aq_desc desc;
3014         struct i40e_aqc_macvlan *cmd =
3015                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3016         enum i40e_status_code status;
3017         u16 buf_size;
3018
3019         if (count == 0 || !mv_list || !hw)
3020                 return I40E_ERR_PARAM;
3021
3022         buf_size = count * sizeof(*mv_list);
3023
3024         /* prep the rest of the request */
3025         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
3026         cmd->num_addresses = CPU_TO_LE16(count);
3027         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3028         cmd->seid[1] = 0;
3029         cmd->seid[2] = 0;
3030
3031         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3032         if (buf_size > I40E_AQ_LARGE_BUF)
3033                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3034
3035         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3036                                        cmd_details);
3037
3038         return status;
3039 }
3040
3041 /**
3042  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3043  * @hw: pointer to the hw struct
3044  * @opcode: AQ opcode for add or delete mirror rule
3045  * @sw_seid: Switch SEID (to which rule refers)
3046  * @rule_type: Rule Type (ingress/egress/VLAN)
3047  * @id: Destination VSI SEID or Rule ID
3048  * @count: length of the list
3049  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3050  * @cmd_details: pointer to command details structure or NULL
3051  * @rule_id: Rule ID returned from FW
3052  * @rule_used: Number of rules used in internal switch
3053  * @rule_free: Number of rules free in internal switch
3054  *
3055  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3056  * VEBs/VEPA elements only
3057  **/
3058 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3059                         u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3060                         u16 count, __le16 *mr_list,
3061                         struct i40e_asq_cmd_details *cmd_details,
3062                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3063 {
3064         struct i40e_aq_desc desc;
3065         struct i40e_aqc_add_delete_mirror_rule *cmd =
3066                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3067         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3068         (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3069         enum i40e_status_code status;
3070         u16 buf_size;
3071
3072         buf_size = count * sizeof(*mr_list);
3073
3074         /* prep the rest of the request */
3075         i40e_fill_default_direct_cmd_desc(&desc, opcode);
3076         cmd->seid = CPU_TO_LE16(sw_seid);
3077         cmd->rule_type = CPU_TO_LE16(rule_type &
3078                                      I40E_AQC_MIRROR_RULE_TYPE_MASK);
3079         cmd->num_entries = CPU_TO_LE16(count);
3080         /* Dest VSI for add, rule_id for delete */
3081         cmd->destination = CPU_TO_LE16(id);
3082         if (mr_list) {
3083                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3084                                                 I40E_AQ_FLAG_RD));
3085                 if (buf_size > I40E_AQ_LARGE_BUF)
3086                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3087         }
3088
3089         status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3090                                        cmd_details);
3091         if (status == I40E_SUCCESS ||
3092             hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3093                 if (rule_id)
3094                         *rule_id = LE16_TO_CPU(resp->rule_id);
3095                 if (rules_used)
3096                         *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3097                 if (rules_free)
3098                         *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3099         }
3100         return status;
3101 }
3102
3103 /**
3104  * i40e_aq_add_mirrorrule - add a mirror rule
3105  * @hw: pointer to the hw struct
3106  * @sw_seid: Switch SEID (to which rule refers)
3107  * @rule_type: Rule Type (ingress/egress/VLAN)
3108  * @dest_vsi: SEID of VSI to which packets will be mirrored
3109  * @count: length of the list
3110  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3111  * @cmd_details: pointer to command details structure or NULL
3112  * @rule_id: Rule ID returned from FW
3113  * @rule_used: Number of rules used in internal switch
3114  * @rule_free: Number of rules free in internal switch
3115  *
3116  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3117  **/
3118 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3119                         u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3120                         struct i40e_asq_cmd_details *cmd_details,
3121                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3122 {
3123         if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3124             rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3125                 if (count == 0 || !mr_list)
3126                         return I40E_ERR_PARAM;
3127         }
3128
3129         return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3130                                   rule_type, dest_vsi, count, mr_list,
3131                                   cmd_details, rule_id, rules_used, rules_free);
3132 }
3133
3134 /**
3135  * i40e_aq_delete_mirrorrule - delete a mirror rule
3136  * @hw: pointer to the hw struct
3137  * @sw_seid: Switch SEID (to which rule refers)
3138  * @rule_type: Rule Type (ingress/egress/VLAN)
3139  * @count: length of the list
3140  * @rule_id: Rule ID that is returned in the receive desc as part of
3141  *              add_mirrorrule.
3142  * @mr_list: list of mirrored VLAN IDs to be removed
3143  * @cmd_details: pointer to command details structure or NULL
3144  * @rule_used: Number of rules used in internal switch
3145  * @rule_free: Number of rules free in internal switch
3146  *
3147  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3148  **/
3149 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3150                         u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3151                         struct i40e_asq_cmd_details *cmd_details,
3152                         u16 *rules_used, u16 *rules_free)
3153 {
3154         /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3155         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3156                 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3157                  * mirroring. For other rule_type, count and rule_type should
3158                  * not matter.
3159                  */
3160                 if (count == 0 || !mr_list)
3161                         return I40E_ERR_PARAM;
3162         }
3163
3164         return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3165                                   rule_type, rule_id, count, mr_list,
3166                                   cmd_details, NULL, rules_used, rules_free);
3167 }
3168
3169 /**
3170  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3171  * @hw: pointer to the hw struct
3172  * @seid: VSI for the vlan filters
3173  * @v_list: list of vlan filters to be added
3174  * @count: length of the list
3175  * @cmd_details: pointer to command details structure or NULL
3176  **/
3177 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3178                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3179                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3180 {
3181         struct i40e_aq_desc desc;
3182         struct i40e_aqc_macvlan *cmd =
3183                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3184         enum i40e_status_code status;
3185         u16 buf_size;
3186
3187         if (count == 0 || !v_list || !hw)
3188                 return I40E_ERR_PARAM;
3189
3190         buf_size = count * sizeof(*v_list);
3191
3192         /* prep the rest of the request */
3193         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3194         cmd->num_addresses = CPU_TO_LE16(count);
3195         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3196         cmd->seid[1] = 0;
3197         cmd->seid[2] = 0;
3198
3199         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3200         if (buf_size > I40E_AQ_LARGE_BUF)
3201                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3202
3203         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3204                                        cmd_details);
3205
3206         return status;
3207 }
3208
3209 /**
3210  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3211  * @hw: pointer to the hw struct
3212  * @seid: VSI for the vlan filters
3213  * @v_list: list of macvlans to be removed
3214  * @count: length of the list
3215  * @cmd_details: pointer to command details structure or NULL
3216  **/
3217 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3218                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3219                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3220 {
3221         struct i40e_aq_desc desc;
3222         struct i40e_aqc_macvlan *cmd =
3223                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3224         enum i40e_status_code status;
3225         u16 buf_size;
3226
3227         if (count == 0 || !v_list || !hw)
3228                 return I40E_ERR_PARAM;
3229
3230         buf_size = count * sizeof(*v_list);
3231
3232         /* prep the rest of the request */
3233         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3234         cmd->num_addresses = CPU_TO_LE16(count);
3235         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3236         cmd->seid[1] = 0;
3237         cmd->seid[2] = 0;
3238
3239         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3240         if (buf_size > I40E_AQ_LARGE_BUF)
3241                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3242
3243         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3244                                        cmd_details);
3245
3246         return status;
3247 }
3248
3249 /**
3250  * i40e_aq_send_msg_to_vf
3251  * @hw: pointer to the hardware structure
3252  * @vfid: vf id to send msg
3253  * @v_opcode: opcodes for VF-PF communication
3254  * @v_retval: return error code
3255  * @msg: pointer to the msg buffer
3256  * @msglen: msg length
3257  * @cmd_details: pointer to command details
3258  *
3259  * send msg to vf
3260  **/
3261 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3262                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3263                                 struct i40e_asq_cmd_details *cmd_details)
3264 {
3265         struct i40e_aq_desc desc;
3266         struct i40e_aqc_pf_vf_message *cmd =
3267                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3268         enum i40e_status_code status;
3269
3270         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3271         cmd->id = CPU_TO_LE32(vfid);
3272         desc.cookie_high = CPU_TO_LE32(v_opcode);
3273         desc.cookie_low = CPU_TO_LE32(v_retval);
3274         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3275         if (msglen) {
3276                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3277                                                 I40E_AQ_FLAG_RD));
3278                 if (msglen > I40E_AQ_LARGE_BUF)
3279                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3280                 desc.datalen = CPU_TO_LE16(msglen);
3281         }
3282         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3283
3284         return status;
3285 }
3286
3287 /**
3288  * i40e_aq_debug_read_register
3289  * @hw: pointer to the hw struct
3290  * @reg_addr: register address
3291  * @reg_val: register value
3292  * @cmd_details: pointer to command details structure or NULL
3293  *
3294  * Read the register using the admin queue commands
3295  **/
3296 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3297                                 u32 reg_addr, u64 *reg_val,
3298                                 struct i40e_asq_cmd_details *cmd_details)
3299 {
3300         struct i40e_aq_desc desc;
3301         struct i40e_aqc_debug_reg_read_write *cmd_resp =
3302                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3303         enum i40e_status_code status;
3304
3305         if (reg_val == NULL)
3306                 return I40E_ERR_PARAM;
3307
3308         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3309
3310         cmd_resp->address = CPU_TO_LE32(reg_addr);
3311
3312         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3313
3314         if (status == I40E_SUCCESS) {
3315                 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3316                            (u64)LE32_TO_CPU(cmd_resp->value_low);
3317         }
3318
3319         return status;
3320 }
3321
3322 /**
3323  * i40e_aq_debug_write_register
3324  * @hw: pointer to the hw struct
3325  * @reg_addr: register address
3326  * @reg_val: register value
3327  * @cmd_details: pointer to command details structure or NULL
3328  *
3329  * Write to a register using the admin queue commands
3330  **/
3331 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3332                                 u32 reg_addr, u64 reg_val,
3333                                 struct i40e_asq_cmd_details *cmd_details)
3334 {
3335         struct i40e_aq_desc desc;
3336         struct i40e_aqc_debug_reg_read_write *cmd =
3337                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3338         enum i40e_status_code status;
3339
3340         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3341
3342         cmd->address = CPU_TO_LE32(reg_addr);
3343         cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3344         cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3345
3346         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3347
3348         return status;
3349 }
3350
3351 /**
3352  * i40e_aq_request_resource
3353  * @hw: pointer to the hw struct
3354  * @resource: resource id
3355  * @access: access type
3356  * @sdp_number: resource number
3357  * @timeout: the maximum time in ms that the driver may hold the resource
3358  * @cmd_details: pointer to command details structure or NULL
3359  *
3360  * requests common resource using the admin queue commands
3361  **/
3362 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3363                                 enum i40e_aq_resources_ids resource,
3364                                 enum i40e_aq_resource_access_type access,
3365                                 u8 sdp_number, u64 *timeout,
3366                                 struct i40e_asq_cmd_details *cmd_details)
3367 {
3368         struct i40e_aq_desc desc;
3369         struct i40e_aqc_request_resource *cmd_resp =
3370                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3371         enum i40e_status_code status;
3372
3373         DEBUGFUNC("i40e_aq_request_resource");
3374
3375         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3376
3377         cmd_resp->resource_id = CPU_TO_LE16(resource);
3378         cmd_resp->access_type = CPU_TO_LE16(access);
3379         cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3380
3381         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3382         /* The completion specifies the maximum time in ms that the driver
3383          * may hold the resource in the Timeout field.
3384          * If the resource is held by someone else, the command completes with
3385          * busy return value and the timeout field indicates the maximum time
3386          * the current owner of the resource has to free it.
3387          */
3388         if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3389                 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3390
3391         return status;
3392 }
3393
3394 /**
3395  * i40e_aq_release_resource
3396  * @hw: pointer to the hw struct
3397  * @resource: resource id
3398  * @sdp_number: resource number
3399  * @cmd_details: pointer to command details structure or NULL
3400  *
3401  * release common resource using the admin queue commands
3402  **/
3403 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3404                                 enum i40e_aq_resources_ids resource,
3405                                 u8 sdp_number,
3406                                 struct i40e_asq_cmd_details *cmd_details)
3407 {
3408         struct i40e_aq_desc desc;
3409         struct i40e_aqc_request_resource *cmd =
3410                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3411         enum i40e_status_code status;
3412
3413         DEBUGFUNC("i40e_aq_release_resource");
3414
3415         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3416
3417         cmd->resource_id = CPU_TO_LE16(resource);
3418         cmd->resource_number = CPU_TO_LE32(sdp_number);
3419
3420         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3421
3422         return status;
3423 }
3424
3425 /**
3426  * i40e_aq_read_nvm
3427  * @hw: pointer to the hw struct
3428  * @module_pointer: module pointer location in words from the NVM beginning
3429  * @offset: byte offset from the module beginning
3430  * @length: length of the section to be read (in bytes from the offset)
3431  * @data: command buffer (size [bytes] = length)
3432  * @last_command: tells if this is the last command in a series
3433  * @cmd_details: pointer to command details structure or NULL
3434  *
3435  * Read the NVM using the admin queue commands
3436  **/
3437 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3438                                 u32 offset, u16 length, void *data,
3439                                 bool last_command,
3440                                 struct i40e_asq_cmd_details *cmd_details)
3441 {
3442         struct i40e_aq_desc desc;
3443         struct i40e_aqc_nvm_update *cmd =
3444                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3445         enum i40e_status_code status;
3446
3447         DEBUGFUNC("i40e_aq_read_nvm");
3448
3449         /* In offset the highest byte must be zeroed. */
3450         if (offset & 0xFF000000) {
3451                 status = I40E_ERR_PARAM;
3452                 goto i40e_aq_read_nvm_exit;
3453         }
3454
3455         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3456
3457         /* If this is the last command in a series, set the proper flag. */
3458         if (last_command)
3459                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3460         cmd->module_pointer = module_pointer;
3461         cmd->offset = CPU_TO_LE32(offset);
3462         cmd->length = CPU_TO_LE16(length);
3463
3464         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3465         if (length > I40E_AQ_LARGE_BUF)
3466                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3467
3468         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3469
3470 i40e_aq_read_nvm_exit:
3471         return status;
3472 }
3473
3474 /**
3475  * i40e_aq_read_nvm_config - read an nvm config block
3476  * @hw: pointer to the hw struct
3477  * @cmd_flags: NVM access admin command bits
3478  * @field_id: field or feature id
3479  * @data: buffer for result
3480  * @buf_size: buffer size
3481  * @element_count: pointer to count of elements read by FW
3482  * @cmd_details: pointer to command details structure or NULL
3483  **/
3484 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3485                                 u8 cmd_flags, u32 field_id, void *data,
3486                                 u16 buf_size, u16 *element_count,
3487                                 struct i40e_asq_cmd_details *cmd_details)
3488 {
3489         struct i40e_aq_desc desc;
3490         struct i40e_aqc_nvm_config_read *cmd =
3491                 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3492         enum i40e_status_code status;
3493
3494         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3495         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3496         if (buf_size > I40E_AQ_LARGE_BUF)
3497                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3498
3499         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3500         cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3501         if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3502                 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3503         else
3504                 cmd->element_id_msw = 0;
3505
3506         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3507
3508         if (!status && element_count)
3509                 *element_count = LE16_TO_CPU(cmd->element_count);
3510
3511         return status;
3512 }
3513
3514 /**
3515  * i40e_aq_write_nvm_config - write an nvm config block
3516  * @hw: pointer to the hw struct
3517  * @cmd_flags: NVM access admin command bits
3518  * @data: buffer for result
3519  * @buf_size: buffer size
3520  * @element_count: count of elements to be written
3521  * @cmd_details: pointer to command details structure or NULL
3522  **/
3523 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3524                                 u8 cmd_flags, void *data, u16 buf_size,
3525                                 u16 element_count,
3526                                 struct i40e_asq_cmd_details *cmd_details)
3527 {
3528         struct i40e_aq_desc desc;
3529         struct i40e_aqc_nvm_config_write *cmd =
3530                 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3531         enum i40e_status_code status;
3532
3533         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3534         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3535         if (buf_size > I40E_AQ_LARGE_BUF)
3536                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3537
3538         cmd->element_count = CPU_TO_LE16(element_count);
3539         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3540         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3541
3542         return status;
3543 }
3544
3545 /**
3546  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3547  * @hw: pointer to the hw struct
3548  * @cmd_details: pointer to command details structure or NULL
3549  **/
3550 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3551                                 void *buff, u16 buff_size,
3552                                 struct i40e_asq_cmd_details *cmd_details)
3553 {
3554         struct i40e_aq_desc desc;
3555         enum i40e_status_code status;
3556
3557         UNREFERENCED_2PARAMETER(buff, buff_size);
3558
3559         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3560         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3561         if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3562                 status = I40E_ERR_NOT_IMPLEMENTED;
3563
3564         return status;
3565 }
3566
3567 /**
3568  * i40e_aq_erase_nvm
3569  * @hw: pointer to the hw struct
3570  * @module_pointer: module pointer location in words from the NVM beginning
3571  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3572  * @length: length of the section to be erased (expressed in 4 KB)
3573  * @last_command: tells if this is the last command in a series
3574  * @cmd_details: pointer to command details structure or NULL
3575  *
3576  * Erase the NVM sector using the admin queue commands
3577  **/
3578 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3579                                 u32 offset, u16 length, bool last_command,
3580                                 struct i40e_asq_cmd_details *cmd_details)
3581 {
3582         struct i40e_aq_desc desc;
3583         struct i40e_aqc_nvm_update *cmd =
3584                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3585         enum i40e_status_code status;
3586
3587         DEBUGFUNC("i40e_aq_erase_nvm");
3588
3589         /* In offset the highest byte must be zeroed. */
3590         if (offset & 0xFF000000) {
3591                 status = I40E_ERR_PARAM;
3592                 goto i40e_aq_erase_nvm_exit;
3593         }
3594
3595         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3596
3597         /* If this is the last command in a series, set the proper flag. */
3598         if (last_command)
3599                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3600         cmd->module_pointer = module_pointer;
3601         cmd->offset = CPU_TO_LE32(offset);
3602         cmd->length = CPU_TO_LE16(length);
3603
3604         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3605
3606 i40e_aq_erase_nvm_exit:
3607         return status;
3608 }
3609
3610 /**
3611  * i40e_parse_discover_capabilities
3612  * @hw: pointer to the hw struct
3613  * @buff: pointer to a buffer containing device/function capability records
3614  * @cap_count: number of capability records in the list
3615  * @list_type_opc: type of capabilities list to parse
3616  *
3617  * Parse the device/function capabilities list.
3618  **/
3619 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3620                                      u32 cap_count,
3621                                      enum i40e_admin_queue_opc list_type_opc)
3622 {
3623         struct i40e_aqc_list_capabilities_element_resp *cap;
3624         u32 valid_functions, num_functions;
3625         u32 number, logical_id, phys_id;
3626         struct i40e_hw_capabilities *p;
3627         u8 major_rev;
3628         u32 i = 0;
3629         u16 id;
3630
3631         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3632
3633         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3634                 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3635         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3636                 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3637         else
3638                 return;
3639
3640         for (i = 0; i < cap_count; i++, cap++) {
3641                 id = LE16_TO_CPU(cap->id);
3642                 number = LE32_TO_CPU(cap->number);
3643                 logical_id = LE32_TO_CPU(cap->logical_id);
3644                 phys_id = LE32_TO_CPU(cap->phys_id);
3645                 major_rev = cap->major_rev;
3646
3647                 switch (id) {
3648                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3649                         p->switch_mode = number;
3650                         i40e_debug(hw, I40E_DEBUG_INIT,
3651                                    "HW Capability: Switch mode = %d\n",
3652                                    p->switch_mode);
3653                         break;
3654                 case I40E_AQ_CAP_ID_MNG_MODE:
3655                         p->management_mode = number;
3656                         if (major_rev > 1) {
3657                                 p->mng_protocols_over_mctp = logical_id;
3658                                 i40e_debug(hw, I40E_DEBUG_INIT,
3659                                            "HW Capability: Protocols over MCTP = %d\n",
3660                                            p->mng_protocols_over_mctp);
3661                         } else {
3662                                 p->mng_protocols_over_mctp = 0;
3663                         }
3664                         i40e_debug(hw, I40E_DEBUG_INIT,
3665                                    "HW Capability: Management Mode = %d\n",
3666                                    p->management_mode);
3667                         break;
3668                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3669                         p->npar_enable = number;
3670                         i40e_debug(hw, I40E_DEBUG_INIT,
3671                                    "HW Capability: NPAR enable = %d\n",
3672                                    p->npar_enable);
3673                         break;
3674                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3675                         p->os2bmc = number;
3676                         i40e_debug(hw, I40E_DEBUG_INIT,
3677                                    "HW Capability: OS2BMC = %d\n", p->os2bmc);
3678                         break;
3679                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3680                         p->valid_functions = number;
3681                         i40e_debug(hw, I40E_DEBUG_INIT,
3682                                    "HW Capability: Valid Functions = %d\n",
3683                                    p->valid_functions);
3684                         break;
3685                 case I40E_AQ_CAP_ID_SRIOV:
3686                         if (number == 1)
3687                                 p->sr_iov_1_1 = true;
3688                         i40e_debug(hw, I40E_DEBUG_INIT,
3689                                    "HW Capability: SR-IOV = %d\n",
3690                                    p->sr_iov_1_1);
3691                         break;
3692                 case I40E_AQ_CAP_ID_VF:
3693                         p->num_vfs = number;
3694                         p->vf_base_id = logical_id;
3695                         i40e_debug(hw, I40E_DEBUG_INIT,
3696                                    "HW Capability: VF count = %d\n",
3697                                    p->num_vfs);
3698                         i40e_debug(hw, I40E_DEBUG_INIT,
3699                                    "HW Capability: VF base_id = %d\n",
3700                                    p->vf_base_id);
3701                         break;
3702                 case I40E_AQ_CAP_ID_VMDQ:
3703                         if (number == 1)
3704                                 p->vmdq = true;
3705                         i40e_debug(hw, I40E_DEBUG_INIT,
3706                                    "HW Capability: VMDQ = %d\n", p->vmdq);
3707                         break;
3708                 case I40E_AQ_CAP_ID_8021QBG:
3709                         if (number == 1)
3710                                 p->evb_802_1_qbg = true;
3711                         i40e_debug(hw, I40E_DEBUG_INIT,
3712                                    "HW Capability: 802.1Qbg = %d\n", number);
3713                         break;
3714                 case I40E_AQ_CAP_ID_8021QBR:
3715                         if (number == 1)
3716                                 p->evb_802_1_qbh = true;
3717                         i40e_debug(hw, I40E_DEBUG_INIT,
3718                                    "HW Capability: 802.1Qbh = %d\n", number);
3719                         break;
3720                 case I40E_AQ_CAP_ID_VSI:
3721                         p->num_vsis = number;
3722                         i40e_debug(hw, I40E_DEBUG_INIT,
3723                                    "HW Capability: VSI count = %d\n",
3724                                    p->num_vsis);
3725                         break;
3726                 case I40E_AQ_CAP_ID_DCB:
3727                         if (number == 1) {
3728                                 p->dcb = true;
3729                                 p->enabled_tcmap = logical_id;
3730                                 p->maxtc = phys_id;
3731                         }
3732                         i40e_debug(hw, I40E_DEBUG_INIT,
3733                                    "HW Capability: DCB = %d\n", p->dcb);
3734                         i40e_debug(hw, I40E_DEBUG_INIT,
3735                                    "HW Capability: TC Mapping = %d\n",
3736                                    logical_id);
3737                         i40e_debug(hw, I40E_DEBUG_INIT,
3738                                    "HW Capability: TC Max = %d\n", p->maxtc);
3739                         break;
3740                 case I40E_AQ_CAP_ID_FCOE:
3741                         if (number == 1)
3742                                 p->fcoe = true;
3743                         i40e_debug(hw, I40E_DEBUG_INIT,
3744                                    "HW Capability: FCOE = %d\n", p->fcoe);
3745                         break;
3746                 case I40E_AQ_CAP_ID_ISCSI:
3747                         if (number == 1)
3748                                 p->iscsi = true;
3749                         i40e_debug(hw, I40E_DEBUG_INIT,
3750                                    "HW Capability: iSCSI = %d\n", p->iscsi);
3751                         break;
3752                 case I40E_AQ_CAP_ID_RSS:
3753                         p->rss = true;
3754                         p->rss_table_size = number;
3755                         p->rss_table_entry_width = logical_id;
3756                         i40e_debug(hw, I40E_DEBUG_INIT,
3757                                    "HW Capability: RSS = %d\n", p->rss);
3758                         i40e_debug(hw, I40E_DEBUG_INIT,
3759                                    "HW Capability: RSS table size = %d\n",
3760                                    p->rss_table_size);
3761                         i40e_debug(hw, I40E_DEBUG_INIT,
3762                                    "HW Capability: RSS table width = %d\n",
3763                                    p->rss_table_entry_width);
3764                         break;
3765                 case I40E_AQ_CAP_ID_RXQ:
3766                         p->num_rx_qp = number;
3767                         p->base_queue = phys_id;
3768                         i40e_debug(hw, I40E_DEBUG_INIT,
3769                                    "HW Capability: Rx QP = %d\n", number);
3770                         i40e_debug(hw, I40E_DEBUG_INIT,
3771                                    "HW Capability: base_queue = %d\n",
3772                                    p->base_queue);
3773                         break;
3774                 case I40E_AQ_CAP_ID_TXQ:
3775                         p->num_tx_qp = number;
3776                         p->base_queue = phys_id;
3777                         i40e_debug(hw, I40E_DEBUG_INIT,
3778                                    "HW Capability: Tx QP = %d\n", number);
3779                         i40e_debug(hw, I40E_DEBUG_INIT,
3780                                    "HW Capability: base_queue = %d\n",
3781                                    p->base_queue);
3782                         break;
3783                 case I40E_AQ_CAP_ID_MSIX:
3784                         p->num_msix_vectors = number;
3785                         i40e_debug(hw, I40E_DEBUG_INIT,
3786                                    "HW Capability: MSIX vector count = %d\n",
3787                                    p->num_msix_vectors);
3788                         break;
3789                 case I40E_AQ_CAP_ID_VF_MSIX:
3790                         p->num_msix_vectors_vf = number;
3791                         i40e_debug(hw, I40E_DEBUG_INIT,
3792                                    "HW Capability: MSIX VF vector count = %d\n",
3793                                    p->num_msix_vectors_vf);
3794                         break;
3795                 case I40E_AQ_CAP_ID_FLEX10:
3796                         if (major_rev == 1) {
3797                                 if (number == 1) {
3798                                         p->flex10_enable = true;
3799                                         p->flex10_capable = true;
3800                                 }
3801                         } else {
3802                                 /* Capability revision >= 2 */
3803                                 if (number & 1)
3804                                         p->flex10_enable = true;
3805                                 if (number & 2)
3806                                         p->flex10_capable = true;
3807                         }
3808                         p->flex10_mode = logical_id;
3809                         p->flex10_status = phys_id;
3810                         i40e_debug(hw, I40E_DEBUG_INIT,
3811                                    "HW Capability: Flex10 mode = %d\n",
3812                                    p->flex10_mode);
3813                         i40e_debug(hw, I40E_DEBUG_INIT,
3814                                    "HW Capability: Flex10 status = %d\n",
3815                                    p->flex10_status);
3816                         break;
3817                 case I40E_AQ_CAP_ID_CEM:
3818                         if (number == 1)
3819                                 p->mgmt_cem = true;
3820                         i40e_debug(hw, I40E_DEBUG_INIT,
3821                                    "HW Capability: CEM = %d\n", p->mgmt_cem);
3822                         break;
3823                 case I40E_AQ_CAP_ID_IWARP:
3824                         if (number == 1)
3825                                 p->iwarp = true;
3826                         i40e_debug(hw, I40E_DEBUG_INIT,
3827                                    "HW Capability: iWARP = %d\n", p->iwarp);
3828                         break;
3829                 case I40E_AQ_CAP_ID_LED:
3830                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3831                                 p->led[phys_id] = true;
3832                         i40e_debug(hw, I40E_DEBUG_INIT,
3833                                    "HW Capability: LED - PIN %d\n", phys_id);
3834                         break;
3835                 case I40E_AQ_CAP_ID_SDP:
3836                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3837                                 p->sdp[phys_id] = true;
3838                         i40e_debug(hw, I40E_DEBUG_INIT,
3839                                    "HW Capability: SDP - PIN %d\n", phys_id);
3840                         break;
3841                 case I40E_AQ_CAP_ID_MDIO:
3842                         if (number == 1) {
3843                                 p->mdio_port_num = phys_id;
3844                                 p->mdio_port_mode = logical_id;
3845                         }
3846                         i40e_debug(hw, I40E_DEBUG_INIT,
3847                                    "HW Capability: MDIO port number = %d\n",
3848                                    p->mdio_port_num);
3849                         i40e_debug(hw, I40E_DEBUG_INIT,
3850                                    "HW Capability: MDIO port mode = %d\n",
3851                                    p->mdio_port_mode);
3852                         break;
3853                 case I40E_AQ_CAP_ID_1588:
3854                         if (number == 1)
3855                                 p->ieee_1588 = true;
3856                         i40e_debug(hw, I40E_DEBUG_INIT,
3857                                    "HW Capability: IEEE 1588 = %d\n",
3858                                    p->ieee_1588);
3859                         break;
3860                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3861                         p->fd = true;
3862                         p->fd_filters_guaranteed = number;
3863                         p->fd_filters_best_effort = logical_id;
3864                         i40e_debug(hw, I40E_DEBUG_INIT,
3865                                    "HW Capability: Flow Director = 1\n");
3866                         i40e_debug(hw, I40E_DEBUG_INIT,
3867                                    "HW Capability: Guaranteed FD filters = %d\n",
3868                                    p->fd_filters_guaranteed);
3869                         break;
3870                 case I40E_AQ_CAP_ID_WSR_PROT:
3871                         p->wr_csr_prot = (u64)number;
3872                         p->wr_csr_prot |= (u64)logical_id << 32;
3873                         i40e_debug(hw, I40E_DEBUG_INIT,
3874                                    "HW Capability: wr_csr_prot = 0x%llX\n\n",
3875                                    (p->wr_csr_prot & 0xffff));
3876                         break;
3877                 case I40E_AQ_CAP_ID_NVM_MGMT:
3878                         if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3879                                 p->sec_rev_disabled = true;
3880                         if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3881                                 p->update_disabled = true;
3882                         break;
3883 #ifdef X722_SUPPORT
3884                 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3885                         hw->num_wol_proxy_filters = (u16)number;
3886                         hw->wol_proxy_vsi_seid = (u16)logical_id;
3887                         p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3888                         if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3889                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3890                         else
3891                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3892                         p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3893                         i40e_debug(hw, I40E_DEBUG_INIT,
3894                                    "HW Capability: WOL proxy filters = %d\n",
3895                                    hw->num_wol_proxy_filters);
3896                         break;
3897 #endif
3898                 default:
3899                         break;
3900                 }
3901         }
3902
3903         if (p->fcoe)
3904                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3905
3906         /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3907         p->fcoe = false;
3908
3909         /* count the enabled ports (aka the "not disabled" ports) */
3910         hw->num_ports = 0;
3911         for (i = 0; i < 4; i++) {
3912                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3913                 u64 port_cfg = 0;
3914
3915                 /* use AQ read to get the physical register offset instead
3916                  * of the port relative offset
3917                  */
3918                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3919                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3920                         hw->num_ports++;
3921         }
3922
3923         valid_functions = p->valid_functions;
3924         num_functions = 0;
3925         while (valid_functions) {
3926                 if (valid_functions & 1)
3927                         num_functions++;
3928                 valid_functions >>= 1;
3929         }
3930
3931         /* partition id is 1-based, and functions are evenly spread
3932          * across the ports as partitions
3933          */
3934         hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3935         hw->num_partitions = num_functions / hw->num_ports;
3936
3937         /* additional HW specific goodies that might
3938          * someday be HW version specific
3939          */
3940         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3941 }
3942
3943 /**
3944  * i40e_aq_discover_capabilities
3945  * @hw: pointer to the hw struct
3946  * @buff: a virtual buffer to hold the capabilities
3947  * @buff_size: Size of the virtual buffer
3948  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3949  * @list_type_opc: capabilities type to discover - pass in the command opcode
3950  * @cmd_details: pointer to command details structure or NULL
3951  *
3952  * Get the device capabilities descriptions from the firmware
3953  **/
3954 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3955                                 void *buff, u16 buff_size, u16 *data_size,
3956                                 enum i40e_admin_queue_opc list_type_opc,
3957                                 struct i40e_asq_cmd_details *cmd_details)
3958 {
3959         struct i40e_aqc_list_capabilites *cmd;
3960         struct i40e_aq_desc desc;
3961         enum i40e_status_code status = I40E_SUCCESS;
3962
3963         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3964
3965         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3966                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3967                 status = I40E_ERR_PARAM;
3968                 goto exit;
3969         }
3970
3971         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3972
3973         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3974         if (buff_size > I40E_AQ_LARGE_BUF)
3975                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3976
3977         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3978         *data_size = LE16_TO_CPU(desc.datalen);
3979
3980         if (status)
3981                 goto exit;
3982
3983         i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3984                                          list_type_opc);
3985
3986 exit:
3987         return status;
3988 }
3989
3990 /**
3991  * i40e_aq_update_nvm
3992  * @hw: pointer to the hw struct
3993  * @module_pointer: module pointer location in words from the NVM beginning
3994  * @offset: byte offset from the module beginning
3995  * @length: length of the section to be written (in bytes from the offset)
3996  * @data: command buffer (size [bytes] = length)
3997  * @last_command: tells if this is the last command in a series
3998  * @cmd_details: pointer to command details structure or NULL
3999  *
4000  * Update the NVM using the admin queue commands
4001  **/
4002 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
4003                                 u32 offset, u16 length, void *data,
4004                                 bool last_command,
4005                                 struct i40e_asq_cmd_details *cmd_details)
4006 {
4007         struct i40e_aq_desc desc;
4008         struct i40e_aqc_nvm_update *cmd =
4009                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
4010         enum i40e_status_code status;
4011
4012         DEBUGFUNC("i40e_aq_update_nvm");
4013
4014         /* In offset the highest byte must be zeroed. */
4015         if (offset & 0xFF000000) {
4016                 status = I40E_ERR_PARAM;
4017                 goto i40e_aq_update_nvm_exit;
4018         }
4019
4020         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4021
4022         /* If this is the last command in a series, set the proper flag. */
4023         if (last_command)
4024                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
4025         cmd->module_pointer = module_pointer;
4026         cmd->offset = CPU_TO_LE32(offset);
4027         cmd->length = CPU_TO_LE16(length);
4028
4029         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4030         if (length > I40E_AQ_LARGE_BUF)
4031                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4032
4033         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
4034
4035 i40e_aq_update_nvm_exit:
4036         return status;
4037 }
4038
4039 /**
4040  * i40e_aq_get_lldp_mib
4041  * @hw: pointer to the hw struct
4042  * @bridge_type: type of bridge requested
4043  * @mib_type: Local, Remote or both Local and Remote MIBs
4044  * @buff: pointer to a user supplied buffer to store the MIB block
4045  * @buff_size: size of the buffer (in bytes)
4046  * @local_len : length of the returned Local LLDP MIB
4047  * @remote_len: length of the returned Remote LLDP MIB
4048  * @cmd_details: pointer to command details structure or NULL
4049  *
4050  * Requests the complete LLDP MIB (entire packet).
4051  **/
4052 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4053                                 u8 mib_type, void *buff, u16 buff_size,
4054                                 u16 *local_len, u16 *remote_len,
4055                                 struct i40e_asq_cmd_details *cmd_details)
4056 {
4057         struct i40e_aq_desc desc;
4058         struct i40e_aqc_lldp_get_mib *cmd =
4059                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4060         struct i40e_aqc_lldp_get_mib *resp =
4061                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4062         enum i40e_status_code status;
4063
4064         if (buff_size == 0 || !buff)
4065                 return I40E_ERR_PARAM;
4066
4067         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4068         /* Indirect Command */
4069         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4070
4071         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4072         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4073                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4074
4075         desc.datalen = CPU_TO_LE16(buff_size);
4076
4077         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4078         if (buff_size > I40E_AQ_LARGE_BUF)
4079                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4080
4081         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4082         if (!status) {
4083                 if (local_len != NULL)
4084                         *local_len = LE16_TO_CPU(resp->local_len);
4085                 if (remote_len != NULL)
4086                         *remote_len = LE16_TO_CPU(resp->remote_len);
4087         }
4088
4089         return status;
4090 }
4091
4092  /**
4093  * i40e_aq_set_lldp_mib - Set the LLDP MIB
4094  * @hw: pointer to the hw struct
4095  * @mib_type: Local, Remote or both Local and Remote MIBs
4096  * @buff: pointer to a user supplied buffer to store the MIB block
4097  * @buff_size: size of the buffer (in bytes)
4098  * @cmd_details: pointer to command details structure or NULL
4099  *
4100  * Set the LLDP MIB.
4101  **/
4102 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4103                                 u8 mib_type, void *buff, u16 buff_size,
4104                                 struct i40e_asq_cmd_details *cmd_details)
4105 {
4106         struct i40e_aq_desc desc;
4107         struct i40e_aqc_lldp_set_local_mib *cmd =
4108                 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4109         enum i40e_status_code status;
4110
4111         if (buff_size == 0 || !buff)
4112                 return I40E_ERR_PARAM;
4113
4114         i40e_fill_default_direct_cmd_desc(&desc,
4115                                 i40e_aqc_opc_lldp_set_local_mib);
4116         /* Indirect Command */
4117         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4118         if (buff_size > I40E_AQ_LARGE_BUF)
4119                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4120         desc.datalen = CPU_TO_LE16(buff_size);
4121
4122         cmd->type = mib_type;
4123         cmd->length = CPU_TO_LE16(buff_size);
4124         cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4125         cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4126
4127         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4128         return status;
4129 }
4130
4131 /**
4132  * i40e_aq_cfg_lldp_mib_change_event
4133  * @hw: pointer to the hw struct
4134  * @enable_update: Enable or Disable event posting
4135  * @cmd_details: pointer to command details structure or NULL
4136  *
4137  * Enable or Disable posting of an event on ARQ when LLDP MIB
4138  * associated with the interface changes
4139  **/
4140 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4141                                 bool enable_update,
4142                                 struct i40e_asq_cmd_details *cmd_details)
4143 {
4144         struct i40e_aq_desc desc;
4145         struct i40e_aqc_lldp_update_mib *cmd =
4146                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4147         enum i40e_status_code status;
4148
4149         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4150
4151         if (!enable_update)
4152                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4153
4154         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4155
4156         return status;
4157 }
4158
4159 /**
4160  * i40e_aq_add_lldp_tlv
4161  * @hw: pointer to the hw struct
4162  * @bridge_type: type of bridge
4163  * @buff: buffer with TLV to add
4164  * @buff_size: length of the buffer
4165  * @tlv_len: length of the TLV to be added
4166  * @mib_len: length of the LLDP MIB returned in response
4167  * @cmd_details: pointer to command details structure or NULL
4168  *
4169  * Add the specified TLV to LLDP Local MIB for the given bridge type,
4170  * it is responsibility of the caller to make sure that the TLV is not
4171  * already present in the LLDPDU.
4172  * In return firmware will write the complete LLDP MIB with the newly
4173  * added TLV in the response buffer.
4174  **/
4175 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4176                                 void *buff, u16 buff_size, u16 tlv_len,
4177                                 u16 *mib_len,
4178                                 struct i40e_asq_cmd_details *cmd_details)
4179 {
4180         struct i40e_aq_desc desc;
4181         struct i40e_aqc_lldp_add_tlv *cmd =
4182                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4183         enum i40e_status_code status;
4184
4185         if (buff_size == 0 || !buff || tlv_len == 0)
4186                 return I40E_ERR_PARAM;
4187
4188         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4189
4190         /* Indirect Command */
4191         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4192         if (buff_size > I40E_AQ_LARGE_BUF)
4193                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4194         desc.datalen = CPU_TO_LE16(buff_size);
4195
4196         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4197                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4198         cmd->len = CPU_TO_LE16(tlv_len);
4199
4200         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4201         if (!status) {
4202                 if (mib_len != NULL)
4203                         *mib_len = LE16_TO_CPU(desc.datalen);
4204         }
4205
4206         return status;
4207 }
4208
4209 /**
4210  * i40e_aq_update_lldp_tlv
4211  * @hw: pointer to the hw struct
4212  * @bridge_type: type of bridge
4213  * @buff: buffer with TLV to update
4214  * @buff_size: size of the buffer holding original and updated TLVs
4215  * @old_len: Length of the Original TLV
4216  * @new_len: Length of the Updated TLV
4217  * @offset: offset of the updated TLV in the buff
4218  * @mib_len: length of the returned LLDP MIB
4219  * @cmd_details: pointer to command details structure or NULL
4220  *
4221  * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4222  * Firmware will place the complete LLDP MIB in response buffer with the
4223  * updated TLV.
4224  **/
4225 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4226                                 u8 bridge_type, void *buff, u16 buff_size,
4227                                 u16 old_len, u16 new_len, u16 offset,
4228                                 u16 *mib_len,
4229                                 struct i40e_asq_cmd_details *cmd_details)
4230 {
4231         struct i40e_aq_desc desc;
4232         struct i40e_aqc_lldp_update_tlv *cmd =
4233                 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4234         enum i40e_status_code status;
4235
4236         if (buff_size == 0 || !buff || offset == 0 ||
4237             old_len == 0 || new_len == 0)
4238                 return I40E_ERR_PARAM;
4239
4240         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4241
4242         /* Indirect Command */
4243         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4244         if (buff_size > I40E_AQ_LARGE_BUF)
4245                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4246         desc.datalen = CPU_TO_LE16(buff_size);
4247
4248         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4249                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4250         cmd->old_len = CPU_TO_LE16(old_len);
4251         cmd->new_offset = CPU_TO_LE16(offset);
4252         cmd->new_len = CPU_TO_LE16(new_len);
4253
4254         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4255         if (!status) {
4256                 if (mib_len != NULL)
4257                         *mib_len = LE16_TO_CPU(desc.datalen);
4258         }
4259
4260         return status;
4261 }
4262
4263 /**
4264  * i40e_aq_delete_lldp_tlv
4265  * @hw: pointer to the hw struct
4266  * @bridge_type: type of bridge
4267  * @buff: pointer to a user supplied buffer that has the TLV
4268  * @buff_size: length of the buffer
4269  * @tlv_len: length of the TLV to be deleted
4270  * @mib_len: length of the returned LLDP MIB
4271  * @cmd_details: pointer to command details structure or NULL
4272  *
4273  * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4274  * The firmware places the entire LLDP MIB in the response buffer.
4275  **/
4276 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4277                                 u8 bridge_type, void *buff, u16 buff_size,
4278                                 u16 tlv_len, u16 *mib_len,
4279                                 struct i40e_asq_cmd_details *cmd_details)
4280 {
4281         struct i40e_aq_desc desc;
4282         struct i40e_aqc_lldp_add_tlv *cmd =
4283                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4284         enum i40e_status_code status;
4285
4286         if (buff_size == 0 || !buff)
4287                 return I40E_ERR_PARAM;
4288
4289         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4290
4291         /* Indirect Command */
4292         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4293         if (buff_size > I40E_AQ_LARGE_BUF)
4294                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4295         desc.datalen = CPU_TO_LE16(buff_size);
4296         cmd->len = CPU_TO_LE16(tlv_len);
4297         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4298                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4299
4300         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4301         if (!status) {
4302                 if (mib_len != NULL)
4303                         *mib_len = LE16_TO_CPU(desc.datalen);
4304         }
4305
4306         return status;
4307 }
4308
4309 /**
4310  * i40e_aq_stop_lldp
4311  * @hw: pointer to the hw struct
4312  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4313  * @cmd_details: pointer to command details structure or NULL
4314  *
4315  * Stop or Shutdown the embedded LLDP Agent
4316  **/
4317 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4318                                 struct i40e_asq_cmd_details *cmd_details)
4319 {
4320         struct i40e_aq_desc desc;
4321         struct i40e_aqc_lldp_stop *cmd =
4322                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4323         enum i40e_status_code status;
4324
4325         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4326
4327         if (shutdown_agent)
4328                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4329
4330         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4331
4332         return status;
4333 }
4334
4335 /**
4336  * i40e_aq_start_lldp
4337  * @hw: pointer to the hw struct
4338  * @cmd_details: pointer to command details structure or NULL
4339  *
4340  * Start the embedded LLDP Agent on all ports.
4341  **/
4342 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4343                                 struct i40e_asq_cmd_details *cmd_details)
4344 {
4345         struct i40e_aq_desc desc;
4346         struct i40e_aqc_lldp_start *cmd =
4347                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4348         enum i40e_status_code status;
4349
4350         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4351
4352         cmd->command = I40E_AQ_LLDP_AGENT_START;
4353
4354         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4355
4356         return status;
4357 }
4358
4359 /**
4360  * i40e_aq_get_cee_dcb_config
4361  * @hw: pointer to the hw struct
4362  * @buff: response buffer that stores CEE operational configuration
4363  * @buff_size: size of the buffer passed
4364  * @cmd_details: pointer to command details structure or NULL
4365  *
4366  * Get CEE DCBX mode operational configuration from firmware
4367  **/
4368 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4369                                 void *buff, u16 buff_size,
4370                                 struct i40e_asq_cmd_details *cmd_details)
4371 {
4372         struct i40e_aq_desc desc;
4373         enum i40e_status_code status;
4374
4375         if (buff_size == 0 || !buff)
4376                 return I40E_ERR_PARAM;
4377
4378         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4379
4380         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4381         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4382                                        cmd_details);
4383
4384         return status;
4385 }
4386
4387 /**
4388  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4389  * @hw: pointer to the hw struct
4390  * @start_agent: True if DCBx Agent needs to be Started
4391  *                              False if DCBx Agent needs to be Stopped
4392  * @cmd_details: pointer to command details structure or NULL
4393  *
4394  * Start/Stop the embedded dcbx Agent
4395  **/
4396 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4397                                 bool start_agent,
4398                                 struct i40e_asq_cmd_details *cmd_details)
4399 {
4400         struct i40e_aq_desc desc;
4401         struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4402                 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4403                                 &desc.params.raw;
4404         enum i40e_status_code status;
4405
4406         i40e_fill_default_direct_cmd_desc(&desc,
4407                                 i40e_aqc_opc_lldp_stop_start_spec_agent);
4408
4409         if (start_agent)
4410                 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4411
4412         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4413
4414         return status;
4415 }
4416
4417 /**
4418  * i40e_aq_add_udp_tunnel
4419  * @hw: pointer to the hw struct
4420  * @udp_port: the UDP port to add
4421  * @header_len: length of the tunneling header length in DWords
4422  * @protocol_index: protocol index type
4423  * @filter_index: pointer to filter index
4424  * @cmd_details: pointer to command details structure or NULL
4425  **/
4426 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4427                                 u16 udp_port, u8 protocol_index,
4428                                 u8 *filter_index,
4429                                 struct i40e_asq_cmd_details *cmd_details)
4430 {
4431         struct i40e_aq_desc desc;
4432         struct i40e_aqc_add_udp_tunnel *cmd =
4433                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4434         struct i40e_aqc_del_udp_tunnel_completion *resp =
4435                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4436         enum i40e_status_code status;
4437
4438         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4439
4440         cmd->udp_port = CPU_TO_LE16(udp_port);
4441         cmd->protocol_type = protocol_index;
4442
4443         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4444
4445         if (!status && filter_index)
4446                 *filter_index = resp->index;
4447
4448         return status;
4449 }
4450
4451 /**
4452  * i40e_aq_del_udp_tunnel
4453  * @hw: pointer to the hw struct
4454  * @index: filter index
4455  * @cmd_details: pointer to command details structure or NULL
4456  **/
4457 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4458                                 struct i40e_asq_cmd_details *cmd_details)
4459 {
4460         struct i40e_aq_desc desc;
4461         struct i40e_aqc_remove_udp_tunnel *cmd =
4462                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4463         enum i40e_status_code status;
4464
4465         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4466
4467         cmd->index = index;
4468
4469         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4470
4471         return status;
4472 }
4473
4474 /**
4475  * i40e_aq_get_switch_resource_alloc (0x0204)
4476  * @hw: pointer to the hw struct
4477  * @num_entries: pointer to u8 to store the number of resource entries returned
4478  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
4479  *        to store the resource information for all resource types.  Each
4480  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
4481  * @count: size, in bytes, of the buffer provided
4482  * @cmd_details: pointer to command details structure or NULL
4483  *
4484  * Query the resources allocated to a function.
4485  **/
4486 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4487                         u8 *num_entries,
4488                         struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4489                         u16 count,
4490                         struct i40e_asq_cmd_details *cmd_details)
4491 {
4492         struct i40e_aq_desc desc;
4493         struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4494                 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4495         enum i40e_status_code status;
4496         u16 length = count * sizeof(*buf);
4497
4498         i40e_fill_default_direct_cmd_desc(&desc,
4499                                         i40e_aqc_opc_get_switch_resource_alloc);
4500
4501         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4502         if (length > I40E_AQ_LARGE_BUF)
4503                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4504
4505         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4506
4507         if (!status && num_entries)
4508                 *num_entries = cmd_resp->num_entries;
4509
4510         return status;
4511 }
4512
4513 /**
4514  * i40e_aq_delete_element - Delete switch element
4515  * @hw: pointer to the hw struct
4516  * @seid: the SEID to delete from the switch
4517  * @cmd_details: pointer to command details structure or NULL
4518  *
4519  * This deletes a switch element from the switch.
4520  **/
4521 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4522                                 struct i40e_asq_cmd_details *cmd_details)
4523 {
4524         struct i40e_aq_desc desc;
4525         struct i40e_aqc_switch_seid *cmd =
4526                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4527         enum i40e_status_code status;
4528
4529         if (seid == 0)
4530                 return I40E_ERR_PARAM;
4531
4532         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4533
4534         cmd->seid = CPU_TO_LE16(seid);
4535
4536         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4537
4538         return status;
4539 }
4540
4541 /**
4542  * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4543  * @hw: pointer to the hw struct
4544  * @flags: component flags
4545  * @mac_seid: uplink seid (MAC SEID)
4546  * @vsi_seid: connected vsi seid
4547  * @ret_seid: seid of create pv component
4548  *
4549  * This instantiates an i40e port virtualizer with specified flags.
4550  * Depending on specified flags the port virtualizer can act as a
4551  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4552  */
4553 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4554                                        u16 mac_seid, u16 vsi_seid,
4555                                        u16 *ret_seid)
4556 {
4557         struct i40e_aq_desc desc;
4558         struct i40e_aqc_add_update_pv *cmd =
4559                 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4560         struct i40e_aqc_add_update_pv_completion *resp =
4561                 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4562         enum i40e_status_code status;
4563
4564         if (vsi_seid == 0)
4565                 return I40E_ERR_PARAM;
4566
4567         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4568         cmd->command_flags = CPU_TO_LE16(flags);
4569         cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4570         cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4571
4572         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4573         if (!status && ret_seid)
4574                 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4575
4576         return status;
4577 }
4578
4579 /**
4580  * i40e_aq_add_tag - Add an S/E-tag
4581  * @hw: pointer to the hw struct
4582  * @direct_to_queue: should s-tag direct flow to a specific queue
4583  * @vsi_seid: VSI SEID to use this tag
4584  * @tag: value of the tag
4585  * @queue_num: queue number, only valid is direct_to_queue is true
4586  * @tags_used: return value, number of tags in use by this PF
4587  * @tags_free: return value, number of unallocated tags
4588  * @cmd_details: pointer to command details structure or NULL
4589  *
4590  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4591  * the number of tags allocated by the PF, and the number of unallocated
4592  * tags available.
4593  **/
4594 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4595                                 u16 vsi_seid, u16 tag, u16 queue_num,
4596                                 u16 *tags_used, u16 *tags_free,
4597                                 struct i40e_asq_cmd_details *cmd_details)
4598 {
4599         struct i40e_aq_desc desc;
4600         struct i40e_aqc_add_tag *cmd =
4601                 (struct i40e_aqc_add_tag *)&desc.params.raw;
4602         struct i40e_aqc_add_remove_tag_completion *resp =
4603                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4604         enum i40e_status_code status;
4605
4606         if (vsi_seid == 0)
4607                 return I40E_ERR_PARAM;
4608
4609         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4610
4611         cmd->seid = CPU_TO_LE16(vsi_seid);
4612         cmd->tag = CPU_TO_LE16(tag);
4613         if (direct_to_queue) {
4614                 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4615                 cmd->queue_number = CPU_TO_LE16(queue_num);
4616         }
4617
4618         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4619
4620         if (!status) {
4621                 if (tags_used != NULL)
4622                         *tags_used = LE16_TO_CPU(resp->tags_used);
4623                 if (tags_free != NULL)
4624                         *tags_free = LE16_TO_CPU(resp->tags_free);
4625         }
4626
4627         return status;
4628 }
4629
4630 /**
4631  * i40e_aq_remove_tag - Remove an S- or E-tag
4632  * @hw: pointer to the hw struct
4633  * @vsi_seid: VSI SEID this tag is associated with
4634  * @tag: value of the S-tag to delete
4635  * @tags_used: return value, number of tags in use by this PF
4636  * @tags_free: return value, number of unallocated tags
4637  * @cmd_details: pointer to command details structure or NULL
4638  *
4639  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4640  * the number of tags allocated by the PF, and the number of unallocated
4641  * tags available.
4642  **/
4643 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4644                                 u16 tag, u16 *tags_used, u16 *tags_free,
4645                                 struct i40e_asq_cmd_details *cmd_details)
4646 {
4647         struct i40e_aq_desc desc;
4648         struct i40e_aqc_remove_tag *cmd =
4649                 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4650         struct i40e_aqc_add_remove_tag_completion *resp =
4651                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4652         enum i40e_status_code status;
4653
4654         if (vsi_seid == 0)
4655                 return I40E_ERR_PARAM;
4656
4657         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4658
4659         cmd->seid = CPU_TO_LE16(vsi_seid);
4660         cmd->tag = CPU_TO_LE16(tag);
4661
4662         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4663
4664         if (!status) {
4665                 if (tags_used != NULL)
4666                         *tags_used = LE16_TO_CPU(resp->tags_used);
4667                 if (tags_free != NULL)
4668                         *tags_free = LE16_TO_CPU(resp->tags_free);
4669         }
4670
4671         return status;
4672 }
4673
4674 /**
4675  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4676  * @hw: pointer to the hw struct
4677  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4678  * @etag: value of E-tag to add
4679  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4680  * @buf: address of indirect buffer
4681  * @tags_used: return value, number of E-tags in use by this port
4682  * @tags_free: return value, number of unallocated M-tags
4683  * @cmd_details: pointer to command details structure or NULL
4684  *
4685  * This associates a multicast E-tag to a port virtualizer.  It will return
4686  * the number of tags allocated by the PF, and the number of unallocated
4687  * tags available.
4688  *
4689  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4690  * num_tags_in_buf long.
4691  **/
4692 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4693                                 u16 etag, u8 num_tags_in_buf, void *buf,
4694                                 u16 *tags_used, u16 *tags_free,
4695                                 struct i40e_asq_cmd_details *cmd_details)
4696 {
4697         struct i40e_aq_desc desc;
4698         struct i40e_aqc_add_remove_mcast_etag *cmd =
4699                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4700         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4701            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4702         enum i40e_status_code status;
4703         u16 length = sizeof(u16) * num_tags_in_buf;
4704
4705         if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4706                 return I40E_ERR_PARAM;
4707
4708         i40e_fill_default_direct_cmd_desc(&desc,
4709                                           i40e_aqc_opc_add_multicast_etag);
4710
4711         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4712         cmd->etag = CPU_TO_LE16(etag);
4713         cmd->num_unicast_etags = num_tags_in_buf;
4714
4715         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4716         if (length > I40E_AQ_LARGE_BUF)
4717                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4718
4719         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4720
4721         if (!status) {
4722                 if (tags_used != NULL)
4723                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4724                 if (tags_free != NULL)
4725                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4726         }
4727
4728         return status;
4729 }
4730
4731 /**
4732  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4733  * @hw: pointer to the hw struct
4734  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4735  * @etag: value of the E-tag to remove
4736  * @tags_used: return value, number of tags in use by this port
4737  * @tags_free: return value, number of unallocated tags
4738  * @cmd_details: pointer to command details structure or NULL
4739  *
4740  * This deletes an E-tag from the port virtualizer.  It will return
4741  * the number of tags allocated by the port, and the number of unallocated
4742  * tags available.
4743  **/
4744 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4745                                 u16 etag, u16 *tags_used, u16 *tags_free,
4746                                 struct i40e_asq_cmd_details *cmd_details)
4747 {
4748         struct i40e_aq_desc desc;
4749         struct i40e_aqc_add_remove_mcast_etag *cmd =
4750                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4751         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4752            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4753         enum i40e_status_code status;
4754
4755
4756         if (pv_seid == 0)
4757                 return I40E_ERR_PARAM;
4758
4759         i40e_fill_default_direct_cmd_desc(&desc,
4760                                           i40e_aqc_opc_remove_multicast_etag);
4761
4762         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4763         cmd->etag = CPU_TO_LE16(etag);
4764
4765         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4766
4767         if (!status) {
4768                 if (tags_used != NULL)
4769                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4770                 if (tags_free != NULL)
4771                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4772         }
4773
4774         return status;
4775 }
4776
4777 /**
4778  * i40e_aq_update_tag - Update an S/E-tag
4779  * @hw: pointer to the hw struct
4780  * @vsi_seid: VSI SEID using this S-tag
4781  * @old_tag: old tag value
4782  * @new_tag: new tag value
4783  * @tags_used: return value, number of tags in use by this PF
4784  * @tags_free: return value, number of unallocated tags
4785  * @cmd_details: pointer to command details structure or NULL
4786  *
4787  * This updates the value of the tag currently attached to this VSI
4788  * in the switch complex.  It will return the number of tags allocated
4789  * by the PF, and the number of unallocated tags available.
4790  **/
4791 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4792                                 u16 old_tag, u16 new_tag, u16 *tags_used,
4793                                 u16 *tags_free,
4794                                 struct i40e_asq_cmd_details *cmd_details)
4795 {
4796         struct i40e_aq_desc desc;
4797         struct i40e_aqc_update_tag *cmd =
4798                 (struct i40e_aqc_update_tag *)&desc.params.raw;
4799         struct i40e_aqc_update_tag_completion *resp =
4800                 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4801         enum i40e_status_code status;
4802
4803         if (vsi_seid == 0)
4804                 return I40E_ERR_PARAM;
4805
4806         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4807
4808         cmd->seid = CPU_TO_LE16(vsi_seid);
4809         cmd->old_tag = CPU_TO_LE16(old_tag);
4810         cmd->new_tag = CPU_TO_LE16(new_tag);
4811
4812         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4813
4814         if (!status) {
4815                 if (tags_used != NULL)
4816                         *tags_used = LE16_TO_CPU(resp->tags_used);
4817                 if (tags_free != NULL)
4818                         *tags_free = LE16_TO_CPU(resp->tags_free);
4819         }
4820
4821         return status;
4822 }
4823
4824 /**
4825  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4826  * @hw: pointer to the hw struct
4827  * @tcmap: TC map for request/release any ignore PFC condition
4828  * @request: request or release ignore PFC condition
4829  * @tcmap_ret: return TCs for which PFC is currently ignored
4830  * @cmd_details: pointer to command details structure or NULL
4831  *
4832  * This sends out request/release to ignore PFC condition for a TC.
4833  * It will return the TCs for which PFC is currently ignored.
4834  **/
4835 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4836                                 bool request, u8 *tcmap_ret,
4837                                 struct i40e_asq_cmd_details *cmd_details)
4838 {
4839         struct i40e_aq_desc desc;
4840         struct i40e_aqc_pfc_ignore *cmd_resp =
4841                 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4842         enum i40e_status_code status;
4843
4844         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4845
4846         if (request)
4847                 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4848
4849         cmd_resp->tc_bitmap = tcmap;
4850
4851         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4852
4853         if (!status) {
4854                 if (tcmap_ret != NULL)
4855                         *tcmap_ret = cmd_resp->tc_bitmap;
4856         }
4857
4858         return status;
4859 }
4860
4861 /**
4862  * i40e_aq_dcb_updated - DCB Updated Command
4863  * @hw: pointer to the hw struct
4864  * @cmd_details: pointer to command details structure or NULL
4865  *
4866  * When LLDP is handled in PF this command is used by the PF
4867  * to notify EMP that a DCB setting is modified.
4868  * When LLDP is handled in EMP this command is used by the PF
4869  * to notify EMP whenever one of the following parameters get
4870  * modified:
4871  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4872  *   - PCIRTT in PRTDCB_GENC.PCIRTT
4873  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4874  * EMP will return when the shared RPB settings have been
4875  * recomputed and modified. The retval field in the descriptor
4876  * will be set to 0 when RPB is modified.
4877  **/
4878 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4879                                 struct i40e_asq_cmd_details *cmd_details)
4880 {
4881         struct i40e_aq_desc desc;
4882         enum i40e_status_code status;
4883
4884         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4885
4886         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4887
4888         return status;
4889 }
4890
4891 /**
4892  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4893  * @hw: pointer to the hw struct
4894  * @seid: defines the SEID of the switch for which the stats are requested
4895  * @vlan_id: the VLAN ID for which the statistics are requested
4896  * @stat_index: index of the statistics counters block assigned to this VLAN
4897  * @cmd_details: pointer to command details structure or NULL
4898  *
4899  * XL710 supports 128 smonVlanStats counters.This command is used to
4900  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4901  * switch.
4902  **/
4903 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4904                                 u16 vlan_id, u16 *stat_index,
4905                                 struct i40e_asq_cmd_details *cmd_details)
4906 {
4907         struct i40e_aq_desc desc;
4908         struct i40e_aqc_add_remove_statistics *cmd_resp =
4909                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4910         enum i40e_status_code status;
4911
4912         if ((seid == 0) || (stat_index == NULL))
4913                 return I40E_ERR_PARAM;
4914
4915         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4916
4917         cmd_resp->seid = CPU_TO_LE16(seid);
4918         cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4919
4920         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4921
4922         if (!status && stat_index)
4923                 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4924
4925         return status;
4926 }
4927
4928 /**
4929  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4930  * @hw: pointer to the hw struct
4931  * @seid: defines the SEID of the switch for which the stats are requested
4932  * @vlan_id: the VLAN ID for which the statistics are requested
4933  * @stat_index: index of the statistics counters block assigned to this VLAN
4934  * @cmd_details: pointer to command details structure or NULL
4935  *
4936  * XL710 supports 128 smonVlanStats counters.This command is used to
4937  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4938  * switch.
4939  **/
4940 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4941                                 u16 vlan_id, u16 stat_index,
4942                                 struct i40e_asq_cmd_details *cmd_details)
4943 {
4944         struct i40e_aq_desc desc;
4945         struct i40e_aqc_add_remove_statistics *cmd =
4946                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4947         enum i40e_status_code status;
4948
4949         if (seid == 0)
4950                 return I40E_ERR_PARAM;
4951
4952         i40e_fill_default_direct_cmd_desc(&desc,
4953                                           i40e_aqc_opc_remove_statistics);
4954
4955         cmd->seid = CPU_TO_LE16(seid);
4956         cmd->vlan  = CPU_TO_LE16(vlan_id);
4957         cmd->stat_index = CPU_TO_LE16(stat_index);
4958
4959         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4960
4961         return status;
4962 }
4963
4964 /**
4965  * i40e_aq_set_port_parameters - set physical port parameters.
4966  * @hw: pointer to the hw struct
4967  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4968  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4969  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4970  * @double_vlan: if set double VLAN is enabled
4971  * @cmd_details: pointer to command details structure or NULL
4972  **/
4973 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4974                                 u16 bad_frame_vsi, bool save_bad_pac,
4975                                 bool pad_short_pac, bool double_vlan,
4976                                 struct i40e_asq_cmd_details *cmd_details)
4977 {
4978         struct i40e_aqc_set_port_parameters *cmd;
4979         enum i40e_status_code status;
4980         struct i40e_aq_desc desc;
4981         u16 command_flags = 0;
4982
4983         cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4984
4985         i40e_fill_default_direct_cmd_desc(&desc,
4986                                           i40e_aqc_opc_set_port_parameters);
4987
4988         cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4989         if (save_bad_pac)
4990                 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4991         if (pad_short_pac)
4992                 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4993         if (double_vlan)
4994                 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4995         cmd->command_flags = CPU_TO_LE16(command_flags);
4996
4997         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4998
4999         return status;
5000 }
5001
5002 /**
5003  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
5004  * @hw: pointer to the hw struct
5005  * @seid: seid for the physical port/switching component/vsi
5006  * @buff: Indirect buffer to hold data parameters and response
5007  * @buff_size: Indirect buffer size
5008  * @opcode: Tx scheduler AQ command opcode
5009  * @cmd_details: pointer to command details structure or NULL
5010  *
5011  * Generic command handler for Tx scheduler AQ commands
5012  **/
5013 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
5014                                 void *buff, u16 buff_size,
5015                                  enum i40e_admin_queue_opc opcode,
5016                                 struct i40e_asq_cmd_details *cmd_details)
5017 {
5018         struct i40e_aq_desc desc;
5019         struct i40e_aqc_tx_sched_ind *cmd =
5020                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
5021         enum i40e_status_code status;
5022         bool cmd_param_flag = false;
5023
5024         switch (opcode) {
5025         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
5026         case i40e_aqc_opc_configure_vsi_tc_bw:
5027         case i40e_aqc_opc_enable_switching_comp_ets:
5028         case i40e_aqc_opc_modify_switching_comp_ets:
5029         case i40e_aqc_opc_disable_switching_comp_ets:
5030         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
5031         case i40e_aqc_opc_configure_switching_comp_bw_config:
5032                 cmd_param_flag = true;
5033                 break;
5034         case i40e_aqc_opc_query_vsi_bw_config:
5035         case i40e_aqc_opc_query_vsi_ets_sla_config:
5036         case i40e_aqc_opc_query_switching_comp_ets_config:
5037         case i40e_aqc_opc_query_port_ets_config:
5038         case i40e_aqc_opc_query_switching_comp_bw_config:
5039                 cmd_param_flag = false;
5040                 break;
5041         default:
5042                 return I40E_ERR_PARAM;
5043         }
5044
5045         i40e_fill_default_direct_cmd_desc(&desc, opcode);
5046
5047         /* Indirect command */
5048         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5049         if (cmd_param_flag)
5050                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5051         if (buff_size > I40E_AQ_LARGE_BUF)
5052                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5053
5054         desc.datalen = CPU_TO_LE16(buff_size);
5055
5056         cmd->vsi_seid = CPU_TO_LE16(seid);
5057
5058         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5059
5060         return status;
5061 }
5062
5063 /**
5064  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5065  * @hw: pointer to the hw struct
5066  * @seid: VSI seid
5067  * @credit: BW limit credits (0 = disabled)
5068  * @max_credit: Max BW limit credits
5069  * @cmd_details: pointer to command details structure or NULL
5070  **/
5071 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5072                                 u16 seid, u16 credit, u8 max_credit,
5073                                 struct i40e_asq_cmd_details *cmd_details)
5074 {
5075         struct i40e_aq_desc desc;
5076         struct i40e_aqc_configure_vsi_bw_limit *cmd =
5077                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5078         enum i40e_status_code status;
5079
5080         i40e_fill_default_direct_cmd_desc(&desc,
5081                                           i40e_aqc_opc_configure_vsi_bw_limit);
5082
5083         cmd->vsi_seid = CPU_TO_LE16(seid);
5084         cmd->credit = CPU_TO_LE16(credit);
5085         cmd->max_credit = max_credit;
5086
5087         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5088
5089         return status;
5090 }
5091
5092 /**
5093  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5094  * @hw: pointer to the hw struct
5095  * @seid: switching component seid
5096  * @credit: BW limit credits (0 = disabled)
5097  * @max_bw: Max BW limit credits
5098  * @cmd_details: pointer to command details structure or NULL
5099  **/
5100 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5101                                 u16 seid, u16 credit, u8 max_bw,
5102                                 struct i40e_asq_cmd_details *cmd_details)
5103 {
5104         struct i40e_aq_desc desc;
5105         struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5106           (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5107         enum i40e_status_code status;
5108
5109         i40e_fill_default_direct_cmd_desc(&desc,
5110                                 i40e_aqc_opc_configure_switching_comp_bw_limit);
5111
5112         cmd->seid = CPU_TO_LE16(seid);
5113         cmd->credit = CPU_TO_LE16(credit);
5114         cmd->max_bw = max_bw;
5115
5116         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5117
5118         return status;
5119 }
5120
5121 /**
5122  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5123  * @hw: pointer to the hw struct
5124  * @seid: VSI seid
5125  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5126  * @cmd_details: pointer to command details structure or NULL
5127  **/
5128 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5129                         u16 seid,
5130                         struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5131                         struct i40e_asq_cmd_details *cmd_details)
5132 {
5133         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5134                                     i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5135                                     cmd_details);
5136 }
5137
5138 /**
5139  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5140  * @hw: pointer to the hw struct
5141  * @seid: VSI seid
5142  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5143  * @cmd_details: pointer to command details structure or NULL
5144  **/
5145 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5146                         u16 seid,
5147                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5148                         struct i40e_asq_cmd_details *cmd_details)
5149 {
5150         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5151                                     i40e_aqc_opc_configure_vsi_tc_bw,
5152                                     cmd_details);
5153 }
5154
5155 /**
5156  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5157  * @hw: pointer to the hw struct
5158  * @seid: seid of the switching component connected to Physical Port
5159  * @ets_data: Buffer holding ETS parameters
5160  * @cmd_details: pointer to command details structure or NULL
5161  **/
5162 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5163                 u16 seid,
5164                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5165                 enum i40e_admin_queue_opc opcode,
5166                 struct i40e_asq_cmd_details *cmd_details)
5167 {
5168         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5169                                     sizeof(*ets_data), opcode, cmd_details);
5170 }
5171
5172 /**
5173  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5174  * @hw: pointer to the hw struct
5175  * @seid: seid of the switching component
5176  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5177  * @cmd_details: pointer to command details structure or NULL
5178  **/
5179 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5180         u16 seid,
5181         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5182         struct i40e_asq_cmd_details *cmd_details)
5183 {
5184         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5185                             i40e_aqc_opc_configure_switching_comp_bw_config,
5186                             cmd_details);
5187 }
5188
5189 /**
5190  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5191  * @hw: pointer to the hw struct
5192  * @seid: seid of the switching component
5193  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5194  * @cmd_details: pointer to command details structure or NULL
5195  **/
5196 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5197         struct i40e_hw *hw, u16 seid,
5198         struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5199         struct i40e_asq_cmd_details *cmd_details)
5200 {
5201         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5202                             i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5203                             cmd_details);
5204 }
5205
5206 /**
5207  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5208  * @hw: pointer to the hw struct
5209  * @seid: seid of the VSI
5210  * @bw_data: Buffer to hold VSI BW configuration
5211  * @cmd_details: pointer to command details structure or NULL
5212  **/
5213 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5214                         u16 seid,
5215                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5216                         struct i40e_asq_cmd_details *cmd_details)
5217 {
5218         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5219                                     i40e_aqc_opc_query_vsi_bw_config,
5220                                     cmd_details);
5221 }
5222
5223 /**
5224  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5225  * @hw: pointer to the hw struct
5226  * @seid: seid of the VSI
5227  * @bw_data: Buffer to hold VSI BW configuration per TC
5228  * @cmd_details: pointer to command details structure or NULL
5229  **/
5230 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5231                         u16 seid,
5232                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5233                         struct i40e_asq_cmd_details *cmd_details)
5234 {
5235         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5236                                     i40e_aqc_opc_query_vsi_ets_sla_config,
5237                                     cmd_details);
5238 }
5239
5240 /**
5241  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5242  * @hw: pointer to the hw struct
5243  * @seid: seid of the switching component
5244  * @bw_data: Buffer to hold switching component's per TC BW config
5245  * @cmd_details: pointer to command details structure or NULL
5246  **/
5247 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5248                 u16 seid,
5249                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5250                 struct i40e_asq_cmd_details *cmd_details)
5251 {
5252         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5253                                    i40e_aqc_opc_query_switching_comp_ets_config,
5254                                    cmd_details);
5255 }
5256
5257 /**
5258  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5259  * @hw: pointer to the hw struct
5260  * @seid: seid of the VSI or switching component connected to Physical Port
5261  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5262  * @cmd_details: pointer to command details structure or NULL
5263  **/
5264 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5265                         u16 seid,
5266                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
5267                         struct i40e_asq_cmd_details *cmd_details)
5268 {
5269         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5270                                     i40e_aqc_opc_query_port_ets_config,
5271                                     cmd_details);
5272 }
5273
5274 /**
5275  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5276  * @hw: pointer to the hw struct
5277  * @seid: seid of the switching component
5278  * @bw_data: Buffer to hold switching component's BW configuration
5279  * @cmd_details: pointer to command details structure or NULL
5280  **/
5281 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5282                 u16 seid,
5283                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5284                 struct i40e_asq_cmd_details *cmd_details)
5285 {
5286         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5287                                     i40e_aqc_opc_query_switching_comp_bw_config,
5288                                     cmd_details);
5289 }
5290
5291 /**
5292  * i40e_validate_filter_settings
5293  * @hw: pointer to the hardware structure
5294  * @settings: Filter control settings
5295  *
5296  * Check and validate the filter control settings passed.
5297  * The function checks for the valid filter/context sizes being
5298  * passed for FCoE and PE.
5299  *
5300  * Returns I40E_SUCCESS if the values passed are valid and within
5301  * range else returns an error.
5302  **/
5303 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5304                                 struct i40e_filter_control_settings *settings)
5305 {
5306         u32 fcoe_cntx_size, fcoe_filt_size;
5307         u32 pe_cntx_size, pe_filt_size;
5308         u32 fcoe_fmax;
5309
5310         u32 val;
5311
5312         /* Validate FCoE settings passed */
5313         switch (settings->fcoe_filt_num) {
5314         case I40E_HASH_FILTER_SIZE_1K:
5315         case I40E_HASH_FILTER_SIZE_2K:
5316         case I40E_HASH_FILTER_SIZE_4K:
5317         case I40E_HASH_FILTER_SIZE_8K:
5318         case I40E_HASH_FILTER_SIZE_16K:
5319         case I40E_HASH_FILTER_SIZE_32K:
5320                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5321                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5322                 break;
5323         default:
5324                 return I40E_ERR_PARAM;
5325         }
5326
5327         switch (settings->fcoe_cntx_num) {
5328         case I40E_DMA_CNTX_SIZE_512:
5329         case I40E_DMA_CNTX_SIZE_1K:
5330         case I40E_DMA_CNTX_SIZE_2K:
5331         case I40E_DMA_CNTX_SIZE_4K:
5332                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5333                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5334                 break;
5335         default:
5336                 return I40E_ERR_PARAM;
5337         }
5338
5339         /* Validate PE settings passed */
5340         switch (settings->pe_filt_num) {
5341         case I40E_HASH_FILTER_SIZE_1K:
5342         case I40E_HASH_FILTER_SIZE_2K:
5343         case I40E_HASH_FILTER_SIZE_4K:
5344         case I40E_HASH_FILTER_SIZE_8K:
5345         case I40E_HASH_FILTER_SIZE_16K:
5346         case I40E_HASH_FILTER_SIZE_32K:
5347         case I40E_HASH_FILTER_SIZE_64K:
5348         case I40E_HASH_FILTER_SIZE_128K:
5349         case I40E_HASH_FILTER_SIZE_256K:
5350         case I40E_HASH_FILTER_SIZE_512K:
5351         case I40E_HASH_FILTER_SIZE_1M:
5352                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5353                 pe_filt_size <<= (u32)settings->pe_filt_num;
5354                 break;
5355         default:
5356                 return I40E_ERR_PARAM;
5357         }
5358
5359         switch (settings->pe_cntx_num) {
5360         case I40E_DMA_CNTX_SIZE_512:
5361         case I40E_DMA_CNTX_SIZE_1K:
5362         case I40E_DMA_CNTX_SIZE_2K:
5363         case I40E_DMA_CNTX_SIZE_4K:
5364         case I40E_DMA_CNTX_SIZE_8K:
5365         case I40E_DMA_CNTX_SIZE_16K:
5366         case I40E_DMA_CNTX_SIZE_32K:
5367         case I40E_DMA_CNTX_SIZE_64K:
5368         case I40E_DMA_CNTX_SIZE_128K:
5369         case I40E_DMA_CNTX_SIZE_256K:
5370                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5371                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5372                 break;
5373         default:
5374                 return I40E_ERR_PARAM;
5375         }
5376
5377         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5378         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5379         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5380                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5381         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
5382                 return I40E_ERR_INVALID_SIZE;
5383
5384         return I40E_SUCCESS;
5385 }
5386
5387 /**
5388  * i40e_set_filter_control
5389  * @hw: pointer to the hardware structure
5390  * @settings: Filter control settings
5391  *
5392  * Set the Queue Filters for PE/FCoE and enable filters required
5393  * for a single PF. It is expected that these settings are programmed
5394  * at the driver initialization time.
5395  **/
5396 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5397                                 struct i40e_filter_control_settings *settings)
5398 {
5399         enum i40e_status_code ret = I40E_SUCCESS;
5400         u32 hash_lut_size = 0;
5401         u32 val;
5402
5403         if (!settings)
5404                 return I40E_ERR_PARAM;
5405
5406         /* Validate the input settings */
5407         ret = i40e_validate_filter_settings(hw, settings);
5408         if (ret)
5409                 return ret;
5410
5411         /* Read the PF Queue Filter control register */
5412         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5413
5414         /* Program required PE hash buckets for the PF */
5415         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5416         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5417                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5418         /* Program required PE contexts for the PF */
5419         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5420         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5421                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5422
5423         /* Program required FCoE hash buckets for the PF */
5424         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5425         val |= ((u32)settings->fcoe_filt_num <<
5426                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5427                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5428         /* Program required FCoE DDP contexts for the PF */
5429         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5430         val |= ((u32)settings->fcoe_cntx_num <<
5431                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5432                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5433
5434         /* Program Hash LUT size for the PF */
5435         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5436         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5437                 hash_lut_size = 1;
5438         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5439                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5440
5441         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5442         if (settings->enable_fdir)
5443                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5444         if (settings->enable_ethtype)
5445                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5446         if (settings->enable_macvlan)
5447                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5448
5449         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5450
5451         return I40E_SUCCESS;
5452 }
5453
5454 /**
5455  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5456  * @hw: pointer to the hw struct
5457  * @mac_addr: MAC address to use in the filter
5458  * @ethtype: Ethertype to use in the filter
5459  * @flags: Flags that needs to be applied to the filter
5460  * @vsi_seid: seid of the control VSI
5461  * @queue: VSI queue number to send the packet to
5462  * @is_add: Add control packet filter if True else remove
5463  * @stats: Structure to hold information on control filter counts
5464  * @cmd_details: pointer to command details structure or NULL
5465  *
5466  * This command will Add or Remove control packet filter for a control VSI.
5467  * In return it will update the total number of perfect filter count in
5468  * the stats member.
5469  **/
5470 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5471                                 u8 *mac_addr, u16 ethtype, u16 flags,
5472                                 u16 vsi_seid, u16 queue, bool is_add,
5473                                 struct i40e_control_filter_stats *stats,
5474                                 struct i40e_asq_cmd_details *cmd_details)
5475 {
5476         struct i40e_aq_desc desc;
5477         struct i40e_aqc_add_remove_control_packet_filter *cmd =
5478                 (struct i40e_aqc_add_remove_control_packet_filter *)
5479                 &desc.params.raw;
5480         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5481                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5482                 &desc.params.raw;
5483         enum i40e_status_code status;
5484
5485         if (vsi_seid == 0)
5486                 return I40E_ERR_PARAM;
5487
5488         if (is_add) {
5489                 i40e_fill_default_direct_cmd_desc(&desc,
5490                                 i40e_aqc_opc_add_control_packet_filter);
5491                 cmd->queue = CPU_TO_LE16(queue);
5492         } else {
5493                 i40e_fill_default_direct_cmd_desc(&desc,
5494                                 i40e_aqc_opc_remove_control_packet_filter);
5495         }
5496
5497         if (mac_addr)
5498                 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
5499                             I40E_NONDMA_TO_NONDMA);
5500
5501         cmd->etype = CPU_TO_LE16(ethtype);
5502         cmd->flags = CPU_TO_LE16(flags);
5503         cmd->seid = CPU_TO_LE16(vsi_seid);
5504
5505         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5506
5507         if (!status && stats) {
5508                 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5509                 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5510                 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5511                 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5512         }
5513
5514         return status;
5515 }
5516
5517 /**
5518  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5519  * @hw: pointer to the hw struct
5520  * @seid: VSI seid to add ethertype filter from
5521  **/
5522 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5523 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5524                                                     u16 seid)
5525 {
5526         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5527                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5528                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5529         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5530         enum i40e_status_code status;
5531
5532         status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5533                                                        seid, 0, true, NULL,
5534                                                        NULL);
5535         if (status)
5536                 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5537 }
5538
5539 /**
5540  * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5541  * @filters: list of cloud filters
5542  * @filter_count: length of list
5543  *
5544  * There's an issue in the device where the Geneve VNI layout needs
5545  * to be shifted 1 byte over from the VxLAN VNI
5546  **/
5547 STATIC void i40e_fix_up_geneve_vni(
5548         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5549         u8 filter_count)
5550 {
5551         struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters;
5552         int i;
5553
5554         for (i = 0; i < filter_count; i++) {
5555                 u16 tnl_type;
5556                 u32 ti;
5557
5558                 tnl_type = (LE16_TO_CPU(f[i].flags) &
5559                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5560                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5561                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5562                         ti = LE32_TO_CPU(f[i].tenant_id);
5563                         f[i].tenant_id = CPU_TO_LE32(ti << 8);
5564                 }
5565         }
5566 }
5567
5568 /**
5569  * i40e_aq_add_cloud_filters
5570  * @hw: pointer to the hardware structure
5571  * @seid: VSI seid to add cloud filters from
5572  * @filters: Buffer which contains the filters to be added
5573  * @filter_count: number of filters contained in the buffer
5574  *
5575  * Set the cloud filters for a given VSI.  The contents of the
5576  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5577  * in by the caller of the function.
5578  *
5579  **/
5580 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5581         u16 seid,
5582         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5583         u8 filter_count)
5584 {
5585         struct i40e_aq_desc desc;
5586         struct i40e_aqc_add_remove_cloud_filters *cmd =
5587         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5588         enum i40e_status_code status;
5589         u16 buff_len;
5590
5591         i40e_fill_default_direct_cmd_desc(&desc,
5592                                           i40e_aqc_opc_add_cloud_filters);
5593
5594         buff_len = filter_count * sizeof(*filters);
5595         desc.datalen = CPU_TO_LE16(buff_len);
5596         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5597         cmd->num_filters = filter_count;
5598         cmd->seid = CPU_TO_LE16(seid);
5599
5600         i40e_fix_up_geneve_vni(filters, filter_count);
5601
5602         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5603
5604         return status;
5605 }
5606
5607 /**
5608  * i40e_aq_remove_cloud_filters
5609  * @hw: pointer to the hardware structure
5610  * @seid: VSI seid to remove cloud filters from
5611  * @filters: Buffer which contains the filters to be removed
5612  * @filter_count: number of filters contained in the buffer
5613  *
5614  * Remove the cloud filters for a given VSI.  The contents of the
5615  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5616  * in by the caller of the function.
5617  *
5618  **/
5619 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5620                 u16 seid,
5621                 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5622                 u8 filter_count)
5623 {
5624         struct i40e_aq_desc desc;
5625         struct i40e_aqc_add_remove_cloud_filters *cmd =
5626         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5627         enum i40e_status_code status;
5628         u16 buff_len;
5629
5630         i40e_fill_default_direct_cmd_desc(&desc,
5631                                           i40e_aqc_opc_remove_cloud_filters);
5632
5633         buff_len = filter_count * sizeof(*filters);
5634         desc.datalen = CPU_TO_LE16(buff_len);
5635         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5636         cmd->num_filters = filter_count;
5637         cmd->seid = CPU_TO_LE16(seid);
5638
5639         i40e_fix_up_geneve_vni(filters, filter_count);
5640
5641         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5642
5643         return status;
5644 }
5645
5646 /**
5647  * i40e_aq_alternate_write
5648  * @hw: pointer to the hardware structure
5649  * @reg_addr0: address of first dword to be read
5650  * @reg_val0: value to be written under 'reg_addr0'
5651  * @reg_addr1: address of second dword to be read
5652  * @reg_val1: value to be written under 'reg_addr1'
5653  *
5654  * Write one or two dwords to alternate structure. Fields are indicated
5655  * by 'reg_addr0' and 'reg_addr1' register numbers.
5656  *
5657  **/
5658 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5659                                 u32 reg_addr0, u32 reg_val0,
5660                                 u32 reg_addr1, u32 reg_val1)
5661 {
5662         struct i40e_aq_desc desc;
5663         struct i40e_aqc_alternate_write *cmd_resp =
5664                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5665         enum i40e_status_code status;
5666
5667         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5668         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5669         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5670         cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5671         cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5672
5673         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5674
5675         return status;
5676 }
5677
5678 /**
5679  * i40e_aq_alternate_write_indirect
5680  * @hw: pointer to the hardware structure
5681  * @addr: address of a first register to be modified
5682  * @dw_count: number of alternate structure fields to write
5683  * @buffer: pointer to the command buffer
5684  *
5685  * Write 'dw_count' dwords from 'buffer' to alternate structure
5686  * starting at 'addr'.
5687  *
5688  **/
5689 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5690                                 u32 addr, u32 dw_count, void *buffer)
5691 {
5692         struct i40e_aq_desc desc;
5693         struct i40e_aqc_alternate_ind_write *cmd_resp =
5694                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5695         enum i40e_status_code status;
5696
5697         if (buffer == NULL)
5698                 return I40E_ERR_PARAM;
5699
5700         /* Indirect command */
5701         i40e_fill_default_direct_cmd_desc(&desc,
5702                                          i40e_aqc_opc_alternate_write_indirect);
5703
5704         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5705         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5706         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5707                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5708
5709         cmd_resp->address = CPU_TO_LE32(addr);
5710         cmd_resp->length = CPU_TO_LE32(dw_count);
5711
5712         status = i40e_asq_send_command(hw, &desc, buffer,
5713                                        I40E_LO_DWORD(4*dw_count), NULL);
5714
5715         return status;
5716 }
5717
5718 /**
5719  * i40e_aq_alternate_read
5720  * @hw: pointer to the hardware structure
5721  * @reg_addr0: address of first dword to be read
5722  * @reg_val0: pointer for data read from 'reg_addr0'
5723  * @reg_addr1: address of second dword to be read
5724  * @reg_val1: pointer for data read from 'reg_addr1'
5725  *
5726  * Read one or two dwords from alternate structure. Fields are indicated
5727  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5728  * is not passed then only register at 'reg_addr0' is read.
5729  *
5730  **/
5731 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5732                                 u32 reg_addr0, u32 *reg_val0,
5733                                 u32 reg_addr1, u32 *reg_val1)
5734 {
5735         struct i40e_aq_desc desc;
5736         struct i40e_aqc_alternate_write *cmd_resp =
5737                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5738         enum i40e_status_code status;
5739
5740         if (reg_val0 == NULL)
5741                 return I40E_ERR_PARAM;
5742
5743         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5744         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5745         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5746
5747         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5748
5749         if (status == I40E_SUCCESS) {
5750                 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5751
5752                 if (reg_val1 != NULL)
5753                         *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5754         }
5755
5756         return status;
5757 }
5758
5759 /**
5760  * i40e_aq_alternate_read_indirect
5761  * @hw: pointer to the hardware structure
5762  * @addr: address of the alternate structure field
5763  * @dw_count: number of alternate structure fields to read
5764  * @buffer: pointer to the command buffer
5765  *
5766  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5767  * place them in 'buffer'. The buffer should be allocated by caller.
5768  *
5769  **/
5770 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5771                                 u32 addr, u32 dw_count, void *buffer)
5772 {
5773         struct i40e_aq_desc desc;
5774         struct i40e_aqc_alternate_ind_write *cmd_resp =
5775                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5776         enum i40e_status_code status;
5777
5778         if (buffer == NULL)
5779                 return I40E_ERR_PARAM;
5780
5781         /* Indirect command */
5782         i40e_fill_default_direct_cmd_desc(&desc,
5783                 i40e_aqc_opc_alternate_read_indirect);
5784
5785         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5786         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5787         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5788                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5789
5790         cmd_resp->address = CPU_TO_LE32(addr);
5791         cmd_resp->length = CPU_TO_LE32(dw_count);
5792
5793         status = i40e_asq_send_command(hw, &desc, buffer,
5794                                        I40E_LO_DWORD(4*dw_count), NULL);
5795
5796         return status;
5797 }
5798
5799 /**
5800  *  i40e_aq_alternate_clear
5801  *  @hw: pointer to the HW structure.
5802  *
5803  *  Clear the alternate structures of the port from which the function
5804  *  is called.
5805  *
5806  **/
5807 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5808 {
5809         struct i40e_aq_desc desc;
5810         enum i40e_status_code status;
5811
5812         i40e_fill_default_direct_cmd_desc(&desc,
5813                                           i40e_aqc_opc_alternate_clear_port);
5814
5815         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5816
5817         return status;
5818 }
5819
5820 /**
5821  *  i40e_aq_alternate_write_done
5822  *  @hw: pointer to the HW structure.
5823  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
5824  *  @reset_needed: indicates the SW should trigger GLOBAL reset
5825  *
5826  *  Indicates to the FW that alternate structures have been changed.
5827  *
5828  **/
5829 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
5830                 u8 bios_mode, bool *reset_needed)
5831 {
5832         struct i40e_aq_desc desc;
5833         struct i40e_aqc_alternate_write_done *cmd =
5834                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5835         enum i40e_status_code status;
5836
5837         if (reset_needed == NULL)
5838                 return I40E_ERR_PARAM;
5839
5840         i40e_fill_default_direct_cmd_desc(&desc,
5841                                           i40e_aqc_opc_alternate_write_done);
5842
5843         cmd->cmd_flags = CPU_TO_LE16(bios_mode);
5844
5845         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5846         if (!status && reset_needed)
5847                 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
5848                                  I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
5849
5850         return status;
5851 }
5852
5853 /**
5854  *  i40e_aq_set_oem_mode
5855  *  @hw: pointer to the HW structure.
5856  *  @oem_mode: the OEM mode to be used
5857  *
5858  *  Sets the device to a specific operating mode. Currently the only supported
5859  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
5860  *
5861  **/
5862 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
5863                 u8 oem_mode)
5864 {
5865         struct i40e_aq_desc desc;
5866         struct i40e_aqc_alternate_write_done *cmd =
5867                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5868         enum i40e_status_code status;
5869
5870         i40e_fill_default_direct_cmd_desc(&desc,
5871                                           i40e_aqc_opc_alternate_set_mode);
5872
5873         cmd->cmd_flags = CPU_TO_LE16(oem_mode);
5874
5875         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5876
5877         return status;
5878 }
5879
5880 /**
5881  * i40e_aq_resume_port_tx
5882  * @hw: pointer to the hardware structure
5883  * @cmd_details: pointer to command details structure or NULL
5884  *
5885  * Resume port's Tx traffic
5886  **/
5887 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
5888                                 struct i40e_asq_cmd_details *cmd_details)
5889 {
5890         struct i40e_aq_desc desc;
5891         enum i40e_status_code status;
5892
5893         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
5894
5895         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5896
5897         return status;
5898 }
5899
5900 /**
5901  * i40e_set_pci_config_data - store PCI bus info
5902  * @hw: pointer to hardware structure
5903  * @link_status: the link status word from PCI config space
5904  *
5905  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
5906  **/
5907 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
5908 {
5909         hw->bus.type = i40e_bus_type_pci_express;
5910
5911         switch (link_status & I40E_PCI_LINK_WIDTH) {
5912         case I40E_PCI_LINK_WIDTH_1:
5913                 hw->bus.width = i40e_bus_width_pcie_x1;
5914                 break;
5915         case I40E_PCI_LINK_WIDTH_2:
5916                 hw->bus.width = i40e_bus_width_pcie_x2;
5917                 break;
5918         case I40E_PCI_LINK_WIDTH_4:
5919                 hw->bus.width = i40e_bus_width_pcie_x4;
5920                 break;
5921         case I40E_PCI_LINK_WIDTH_8:
5922                 hw->bus.width = i40e_bus_width_pcie_x8;
5923                 break;
5924         default:
5925                 hw->bus.width = i40e_bus_width_unknown;
5926                 break;
5927         }
5928
5929         switch (link_status & I40E_PCI_LINK_SPEED) {
5930         case I40E_PCI_LINK_SPEED_2500:
5931                 hw->bus.speed = i40e_bus_speed_2500;
5932                 break;
5933         case I40E_PCI_LINK_SPEED_5000:
5934                 hw->bus.speed = i40e_bus_speed_5000;
5935                 break;
5936         case I40E_PCI_LINK_SPEED_8000:
5937                 hw->bus.speed = i40e_bus_speed_8000;
5938                 break;
5939         default:
5940                 hw->bus.speed = i40e_bus_speed_unknown;
5941                 break;
5942         }
5943 }
5944
5945 /**
5946  * i40e_aq_debug_dump
5947  * @hw: pointer to the hardware structure
5948  * @cluster_id: specific cluster to dump
5949  * @table_id: table id within cluster
5950  * @start_index: index of line in the block to read
5951  * @buff_size: dump buffer size
5952  * @buff: dump buffer
5953  * @ret_buff_size: actual buffer size returned
5954  * @ret_next_table: next block to read
5955  * @ret_next_index: next index to read
5956  *
5957  * Dump internal FW/HW data for debug purposes.
5958  *
5959  **/
5960 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
5961                                 u8 table_id, u32 start_index, u16 buff_size,
5962                                 void *buff, u16 *ret_buff_size,
5963                                 u8 *ret_next_table, u32 *ret_next_index,
5964                                 struct i40e_asq_cmd_details *cmd_details)
5965 {
5966         struct i40e_aq_desc desc;
5967         struct i40e_aqc_debug_dump_internals *cmd =
5968                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5969         struct i40e_aqc_debug_dump_internals *resp =
5970                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5971         enum i40e_status_code status;
5972
5973         if (buff_size == 0 || !buff)
5974                 return I40E_ERR_PARAM;
5975
5976         i40e_fill_default_direct_cmd_desc(&desc,
5977                                           i40e_aqc_opc_debug_dump_internals);
5978         /* Indirect Command */
5979         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5980         if (buff_size > I40E_AQ_LARGE_BUF)
5981                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5982
5983         cmd->cluster_id = cluster_id;
5984         cmd->table_id = table_id;
5985         cmd->idx = CPU_TO_LE32(start_index);
5986
5987         desc.datalen = CPU_TO_LE16(buff_size);
5988
5989         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5990         if (!status) {
5991                 if (ret_buff_size != NULL)
5992                         *ret_buff_size = LE16_TO_CPU(desc.datalen);
5993                 if (ret_next_table != NULL)
5994                         *ret_next_table = resp->table_id;
5995                 if (ret_next_index != NULL)
5996                         *ret_next_index = LE32_TO_CPU(resp->idx);
5997         }
5998
5999         return status;
6000 }
6001
6002 /**
6003  * i40e_read_bw_from_alt_ram
6004  * @hw: pointer to the hardware structure
6005  * @max_bw: pointer for max_bw read
6006  * @min_bw: pointer for min_bw read
6007  * @min_valid: pointer for bool that is true if min_bw is a valid value
6008  * @max_valid: pointer for bool that is true if max_bw is a valid value
6009  *
6010  * Read bw from the alternate ram for the given pf
6011  **/
6012 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
6013                                         u32 *max_bw, u32 *min_bw,
6014                                         bool *min_valid, bool *max_valid)
6015 {
6016         enum i40e_status_code status;
6017         u32 max_bw_addr, min_bw_addr;
6018
6019         /* Calculate the address of the min/max bw registers */
6020         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6021                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
6022                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6023         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6024                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
6025                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6026
6027         /* Read the bandwidths from alt ram */
6028         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
6029                                         min_bw_addr, min_bw);
6030
6031         if (*min_bw & I40E_ALT_BW_VALID_MASK)
6032                 *min_valid = true;
6033         else
6034                 *min_valid = false;
6035
6036         if (*max_bw & I40E_ALT_BW_VALID_MASK)
6037                 *max_valid = true;
6038         else
6039                 *max_valid = false;
6040
6041         return status;
6042 }
6043
6044 /**
6045  * i40e_aq_configure_partition_bw
6046  * @hw: pointer to the hardware structure
6047  * @bw_data: Buffer holding valid pfs and bw limits
6048  * @cmd_details: pointer to command details
6049  *
6050  * Configure partitions guaranteed/max bw
6051  **/
6052 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6053                         struct i40e_aqc_configure_partition_bw_data *bw_data,
6054                         struct i40e_asq_cmd_details *cmd_details)
6055 {
6056         enum i40e_status_code status;
6057         struct i40e_aq_desc desc;
6058         u16 bwd_size = sizeof(*bw_data);
6059
6060         i40e_fill_default_direct_cmd_desc(&desc,
6061                                 i40e_aqc_opc_configure_partition_bw);
6062
6063         /* Indirect command */
6064         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6065         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6066
6067         desc.datalen = CPU_TO_LE16(bwd_size);
6068
6069         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6070
6071         return status;
6072 }
6073
6074 /**
6075  * i40e_read_phy_register_clause22
6076  * @hw: pointer to the HW structure
6077  * @reg: register address in the page
6078  * @phy_adr: PHY address on MDIO interface
6079  * @value: PHY register value
6080  *
6081  * Reads specified PHY register value
6082  **/
6083 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
6084                                         u16 reg, u8 phy_addr, u16 *value)
6085 {
6086         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6087         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6088         u32 command = 0;
6089         u16 retry = 1000;
6090
6091         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6092                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6093                   (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
6094                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6095                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6096         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6097         do {
6098                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6099                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6100                         status = I40E_SUCCESS;
6101                         break;
6102                 }
6103                 i40e_usec_delay(10);
6104                 retry--;
6105         } while (retry);
6106
6107         if (status) {
6108                 i40e_debug(hw, I40E_DEBUG_PHY,
6109                            "PHY: Can't write command to external PHY.\n");
6110         } else {
6111                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6112                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6113                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6114         }
6115
6116         return status;
6117 }
6118
6119 /**
6120  * i40e_write_phy_register_clause22
6121  * @hw: pointer to the HW structure
6122  * @reg: register address in the page
6123  * @phy_adr: PHY address on MDIO interface
6124  * @value: PHY register value
6125  *
6126  * Writes specified PHY register value
6127  **/
6128 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6129                                         u16 reg, u8 phy_addr, u16 value)
6130 {
6131         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6132         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6133         u32 command  = 0;
6134         u16 retry = 1000;
6135
6136         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6137         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6138
6139         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6140                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6141                   (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6142                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6143                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6144
6145         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6146         do {
6147                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6148                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6149                         status = I40E_SUCCESS;
6150                         break;
6151                 }
6152                 i40e_usec_delay(10);
6153                 retry--;
6154         } while (retry);
6155
6156         return status;
6157 }
6158
6159 /**
6160  * i40e_read_phy_register_clause45
6161  * @hw: pointer to the HW structure
6162  * @page: registers page number
6163  * @reg: register address in the page
6164  * @phy_adr: PHY address on MDIO interface
6165  * @value: PHY register value
6166  *
6167  * Reads specified PHY register value
6168  **/
6169 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6170                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6171 {
6172         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6173         u32 command  = 0;
6174         u16 retry = 1000;
6175         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6176
6177         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6178                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6179                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6180                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6181                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6182                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6183                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6184         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6185         do {
6186                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6187                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6188                         status = I40E_SUCCESS;
6189                         break;
6190                 }
6191                 i40e_usec_delay(10);
6192                 retry--;
6193         } while (retry);
6194
6195         if (status) {
6196                 i40e_debug(hw, I40E_DEBUG_PHY,
6197                            "PHY: Can't write command to external PHY.\n");
6198                 goto phy_read_end;
6199         }
6200
6201         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6202                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6203                   (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6204                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6205                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6206                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6207         status = I40E_ERR_TIMEOUT;
6208         retry = 1000;
6209         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6210         do {
6211                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6212                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6213                         status = I40E_SUCCESS;
6214                         break;
6215                 }
6216                 i40e_usec_delay(10);
6217                 retry--;
6218         } while (retry);
6219
6220         if (!status) {
6221                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6222                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6223                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6224         } else {
6225                 i40e_debug(hw, I40E_DEBUG_PHY,
6226                            "PHY: Can't read register value from external PHY.\n");
6227         }
6228
6229 phy_read_end:
6230         return status;
6231 }
6232
6233 /**
6234  * i40e_write_phy_register_clause45
6235  * @hw: pointer to the HW structure
6236  * @page: registers page number
6237  * @reg: register address in the page
6238  * @phy_adr: PHY address on MDIO interface
6239  * @value: PHY register value
6240  *
6241  * Writes value to specified PHY register
6242  **/
6243 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6244                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6245 {
6246         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6247         u32 command  = 0;
6248         u16 retry = 1000;
6249         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6250
6251         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6252                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6253                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6254                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6255                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6256                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6257                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6258         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6259         do {
6260                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6261                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6262                         status = I40E_SUCCESS;
6263                         break;
6264                 }
6265                 i40e_usec_delay(10);
6266                 retry--;
6267         } while (retry);
6268         if (status) {
6269                 i40e_debug(hw, I40E_DEBUG_PHY,
6270                            "PHY: Can't write command to external PHY.\n");
6271                 goto phy_write_end;
6272         }
6273
6274         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6275         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6276
6277         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6278                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6279                   (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6280                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6281                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6282                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6283         status = I40E_ERR_TIMEOUT;
6284         retry = 1000;
6285         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6286         do {
6287                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6288                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6289                         status = I40E_SUCCESS;
6290                         break;
6291                 }
6292                 i40e_usec_delay(10);
6293                 retry--;
6294         } while (retry);
6295
6296 phy_write_end:
6297         return status;
6298 }
6299
6300 /**
6301  * i40e_write_phy_register
6302  * @hw: pointer to the HW structure
6303  * @page: registers page number
6304  * @reg: register address in the page
6305  * @phy_adr: PHY address on MDIO interface
6306  * @value: PHY register value
6307  *
6308  * Writes value to specified PHY register
6309  **/
6310 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6311                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6312 {
6313         enum i40e_status_code status;
6314
6315         switch (hw->device_id) {
6316         case I40E_DEV_ID_1G_BASE_T_X722:
6317                 status = i40e_write_phy_register_clause22(hw,
6318                         reg, phy_addr, value);
6319                 break;
6320         case I40E_DEV_ID_10G_BASE_T:
6321         case I40E_DEV_ID_10G_BASE_T4:
6322         case I40E_DEV_ID_10G_BASE_T_X722:
6323         case I40E_DEV_ID_25G_B:
6324         case I40E_DEV_ID_25G_SFP28:
6325                 status = i40e_write_phy_register_clause45(hw,
6326                         page, reg, phy_addr, value);
6327                 break;
6328         default:
6329                 status = I40E_ERR_UNKNOWN_PHY;
6330                 break;
6331         }
6332
6333         return status;
6334 }
6335
6336 /**
6337  * i40e_read_phy_register
6338  * @hw: pointer to the HW structure
6339  * @page: registers page number
6340  * @reg: register address in the page
6341  * @phy_adr: PHY address on MDIO interface
6342  * @value: PHY register value
6343  *
6344  * Reads specified PHY register value
6345  **/
6346 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6347                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6348 {
6349         enum i40e_status_code status;
6350
6351         switch (hw->device_id) {
6352         case I40E_DEV_ID_1G_BASE_T_X722:
6353                 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6354                                                          value);
6355                 break;
6356         case I40E_DEV_ID_10G_BASE_T:
6357         case I40E_DEV_ID_10G_BASE_T4:
6358         case I40E_DEV_ID_10G_BASE_T_X722:
6359         case I40E_DEV_ID_25G_B:
6360         case I40E_DEV_ID_25G_SFP28:
6361                 status = i40e_read_phy_register_clause45(hw, page, reg,
6362                                                          phy_addr, value);
6363                 break;
6364         default:
6365                 status = I40E_ERR_UNKNOWN_PHY;
6366                 break;
6367         }
6368
6369         return status;
6370 }
6371
6372 /**
6373  * i40e_get_phy_address
6374  * @hw: pointer to the HW structure
6375  * @dev_num: PHY port num that address we want
6376  * @phy_addr: Returned PHY address
6377  *
6378  * Gets PHY address for current port
6379  **/
6380 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6381 {
6382         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6383         u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6384
6385         return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6386 }
6387
6388 /**
6389  * i40e_blink_phy_led
6390  * @hw: pointer to the HW structure
6391  * @time: time how long led will blinks in secs
6392  * @interval: gap between LED on and off in msecs
6393  *
6394  * Blinks PHY link LED
6395  **/
6396 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6397                                               u32 time, u32 interval)
6398 {
6399         enum i40e_status_code status = I40E_SUCCESS;
6400         u32 i;
6401         u16 led_ctl = 0;
6402         u16 gpio_led_port;
6403         u16 led_reg;
6404         u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6405         u8 phy_addr = 0;
6406         u8 port_num;
6407
6408         i = rd32(hw, I40E_PFGEN_PORTNUM);
6409         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6410         phy_addr = i40e_get_phy_address(hw, port_num);
6411
6412         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6413              led_addr++) {
6414                 status = i40e_read_phy_register_clause45(hw,
6415                                                          I40E_PHY_COM_REG_PAGE,
6416                                                          led_addr, phy_addr,
6417                                                          &led_reg);
6418                 if (status)
6419                         goto phy_blinking_end;
6420                 led_ctl = led_reg;
6421                 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6422                         led_reg = 0;
6423                         status = i40e_write_phy_register_clause45(hw,
6424                                                          I40E_PHY_COM_REG_PAGE,
6425                                                          led_addr, phy_addr,
6426                                                          led_reg);
6427                         if (status)
6428                                 goto phy_blinking_end;
6429                         break;
6430                 }
6431         }
6432
6433         if (time > 0 && interval > 0) {
6434                 for (i = 0; i < time * 1000; i += interval) {
6435                         status = i40e_read_phy_register_clause45(hw,
6436                                                 I40E_PHY_COM_REG_PAGE,
6437                                                 led_addr, phy_addr, &led_reg);
6438                         if (status)
6439                                 goto restore_config;
6440                         if (led_reg & I40E_PHY_LED_MANUAL_ON)
6441                                 led_reg = 0;
6442                         else
6443                                 led_reg = I40E_PHY_LED_MANUAL_ON;
6444                         status = i40e_write_phy_register_clause45(hw,
6445                                                 I40E_PHY_COM_REG_PAGE,
6446                                                 led_addr, phy_addr, led_reg);
6447                         if (status)
6448                                 goto restore_config;
6449                         i40e_msec_delay(interval);
6450                 }
6451         }
6452
6453 restore_config:
6454         status = i40e_write_phy_register_clause45(hw,
6455                                                   I40E_PHY_COM_REG_PAGE,
6456                                                   led_addr, phy_addr, led_ctl);
6457
6458 phy_blinking_end:
6459         return status;
6460 }
6461
6462 /**
6463  * i40e_led_get_phy - return current on/off mode
6464  * @hw: pointer to the hw struct
6465  * @led_addr: address of led register to use
6466  * @val: original value of register to use
6467  *
6468  **/
6469 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6470                                        u16 *val)
6471 {
6472         enum i40e_status_code status = I40E_SUCCESS;
6473         u16 gpio_led_port;
6474         u8 phy_addr = 0;
6475         u16 reg_val;
6476         u16 temp_addr;
6477         u8 port_num;
6478         u32 i;
6479
6480         temp_addr = I40E_PHY_LED_PROV_REG_1;
6481         i = rd32(hw, I40E_PFGEN_PORTNUM);
6482         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6483         phy_addr = i40e_get_phy_address(hw, port_num);
6484
6485         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6486              temp_addr++) {
6487                 status = i40e_read_phy_register_clause45(hw,
6488                                                          I40E_PHY_COM_REG_PAGE,
6489                                                          temp_addr, phy_addr,
6490                                                          &reg_val);
6491                 if (status)
6492                         return status;
6493                 *val = reg_val;
6494                 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6495                         *led_addr = temp_addr;
6496                         break;
6497                 }
6498         }
6499         return status;
6500 }
6501
6502 /**
6503  * i40e_led_set_phy
6504  * @hw: pointer to the HW structure
6505  * @on: true or false
6506  * @mode: original val plus bit for set or ignore
6507  * Set led's on or off when controlled by the PHY
6508  *
6509  **/
6510 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6511                                        u16 led_addr, u32 mode)
6512 {
6513         enum i40e_status_code status = I40E_SUCCESS;
6514         u16 led_ctl = 0;
6515         u16 led_reg = 0;
6516         u8 phy_addr = 0;
6517         u8 port_num;
6518         u32 i;
6519
6520         i = rd32(hw, I40E_PFGEN_PORTNUM);
6521         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6522         phy_addr = i40e_get_phy_address(hw, port_num);
6523         status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6524                                                  led_addr, phy_addr, &led_reg);
6525         if (status)
6526                 return status;
6527         led_ctl = led_reg;
6528         if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6529                 led_reg = 0;
6530                 status = i40e_write_phy_register_clause45(hw,
6531                                                           I40E_PHY_COM_REG_PAGE,
6532                                                           led_addr, phy_addr,
6533                                                           led_reg);
6534                 if (status)
6535                         return status;
6536         }
6537         status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6538                                                  led_addr, phy_addr, &led_reg);
6539         if (status)
6540                 goto restore_config;
6541         if (on)
6542                 led_reg = I40E_PHY_LED_MANUAL_ON;
6543         else
6544                 led_reg = 0;
6545         status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6546                                                   led_addr, phy_addr, led_reg);
6547         if (status)
6548                 goto restore_config;
6549         if (mode & I40E_PHY_LED_MODE_ORIG) {
6550                 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6551                 status = i40e_write_phy_register_clause45(hw,
6552                                                  I40E_PHY_COM_REG_PAGE,
6553                                                  led_addr, phy_addr, led_ctl);
6554         }
6555         return status;
6556 restore_config:
6557         status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6558                                                   led_addr, phy_addr, led_ctl);
6559         return status;
6560 }
6561 #endif /* PF_DRIVER */
6562
6563 /**
6564  * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6565  * @hw: pointer to the hw struct
6566  * @reg_addr: register address
6567  * @reg_val: ptr to register value
6568  * @cmd_details: pointer to command details structure or NULL
6569  *
6570  * Use the firmware to read the Rx control register,
6571  * especially useful if the Rx unit is under heavy pressure
6572  **/
6573 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6574                                 u32 reg_addr, u32 *reg_val,
6575                                 struct i40e_asq_cmd_details *cmd_details)
6576 {
6577         struct i40e_aq_desc desc;
6578         struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
6579                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6580         enum i40e_status_code status;
6581
6582         if (reg_val == NULL)
6583                 return I40E_ERR_PARAM;
6584
6585         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
6586
6587         cmd_resp->address = CPU_TO_LE32(reg_addr);
6588
6589         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6590
6591         if (status == I40E_SUCCESS)
6592                 *reg_val = LE32_TO_CPU(cmd_resp->value);
6593
6594         return status;
6595 }
6596
6597 /**
6598  * i40e_read_rx_ctl - read from an Rx control register
6599  * @hw: pointer to the hw struct
6600  * @reg_addr: register address
6601  **/
6602 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
6603 {
6604         enum i40e_status_code status = I40E_SUCCESS;
6605         bool use_register;
6606         int retry = 5;
6607         u32 val = 0;
6608
6609         use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6610         if (!use_register) {
6611 do_retry:
6612                 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
6613                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6614                         i40e_msec_delay(1);
6615                         retry--;
6616                         goto do_retry;
6617                 }
6618         }
6619
6620         /* if the AQ access failed, try the old-fashioned way */
6621         if (status || use_register)
6622                 val = rd32(hw, reg_addr);
6623
6624         return val;
6625 }
6626
6627 /**
6628  * i40e_aq_rx_ctl_write_register
6629  * @hw: pointer to the hw struct
6630  * @reg_addr: register address
6631  * @reg_val: register value
6632  * @cmd_details: pointer to command details structure or NULL
6633  *
6634  * Use the firmware to write to an Rx control register,
6635  * especially useful if the Rx unit is under heavy pressure
6636  **/
6637 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
6638                                 u32 reg_addr, u32 reg_val,
6639                                 struct i40e_asq_cmd_details *cmd_details)
6640 {
6641         struct i40e_aq_desc desc;
6642         struct i40e_aqc_rx_ctl_reg_read_write *cmd =
6643                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6644         enum i40e_status_code status;
6645
6646         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
6647
6648         cmd->address = CPU_TO_LE32(reg_addr);
6649         cmd->value = CPU_TO_LE32(reg_val);
6650
6651         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6652
6653         return status;
6654 }
6655
6656 /**
6657  * i40e_write_rx_ctl - write to an Rx control register
6658  * @hw: pointer to the hw struct
6659  * @reg_addr: register address
6660  * @reg_val: register value
6661  **/
6662 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
6663 {
6664         enum i40e_status_code status = I40E_SUCCESS;
6665         bool use_register;
6666         int retry = 5;
6667
6668         use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6669         if (!use_register) {
6670 do_retry:
6671                 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
6672                                                        reg_val, NULL);
6673                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6674                         i40e_msec_delay(1);
6675                         retry--;
6676                         goto do_retry;
6677                 }
6678         }
6679
6680         /* if the AQ access failed, try the old-fashioned way */
6681         if (status || use_register)
6682                 wr32(hw, reg_addr, reg_val);
6683 }
6684 #ifdef VF_DRIVER
6685
6686 /**
6687  * i40e_aq_send_msg_to_pf
6688  * @hw: pointer to the hardware structure
6689  * @v_opcode: opcodes for VF-PF communication
6690  * @v_retval: return error code
6691  * @msg: pointer to the msg buffer
6692  * @msglen: msg length
6693  * @cmd_details: pointer to command details
6694  *
6695  * Send message to PF driver using admin queue. By default, this message
6696  * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
6697  * completion before returning.
6698  **/
6699 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
6700                                 enum i40e_virtchnl_ops v_opcode,
6701                                 enum i40e_status_code v_retval,
6702                                 u8 *msg, u16 msglen,
6703                                 struct i40e_asq_cmd_details *cmd_details)
6704 {
6705         struct i40e_aq_desc desc;
6706         struct i40e_asq_cmd_details details;
6707         enum i40e_status_code status;
6708
6709         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
6710         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
6711         desc.cookie_high = CPU_TO_LE32(v_opcode);
6712         desc.cookie_low = CPU_TO_LE32(v_retval);
6713         if (msglen) {
6714                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
6715                                                 | I40E_AQ_FLAG_RD));
6716                 if (msglen > I40E_AQ_LARGE_BUF)
6717                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6718                 desc.datalen = CPU_TO_LE16(msglen);
6719         }
6720         if (!cmd_details) {
6721                 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
6722                 details.async = true;
6723                 cmd_details = &details;
6724         }
6725         status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
6726                                        msglen, cmd_details);
6727         return status;
6728 }
6729
6730 /**
6731  * i40e_vf_parse_hw_config
6732  * @hw: pointer to the hardware structure
6733  * @msg: pointer to the virtual channel VF resource structure
6734  *
6735  * Given a VF resource message from the PF, populate the hw struct
6736  * with appropriate information.
6737  **/
6738 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
6739                              struct i40e_virtchnl_vf_resource *msg)
6740 {
6741         struct i40e_virtchnl_vsi_resource *vsi_res;
6742         int i;
6743
6744         vsi_res = &msg->vsi_res[0];
6745
6746         hw->dev_caps.num_vsis = msg->num_vsis;
6747         hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
6748         hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
6749         hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
6750         hw->dev_caps.dcb = msg->vf_offload_flags &
6751                            I40E_VIRTCHNL_VF_OFFLOAD_L2;
6752         hw->dev_caps.fcoe = (msg->vf_offload_flags &
6753                              I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
6754         hw->dev_caps.iwarp = (msg->vf_offload_flags &
6755                               I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
6756         for (i = 0; i < msg->num_vsis; i++) {
6757                 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
6758                         i40e_memcpy(hw->mac.perm_addr,
6759                                     vsi_res->default_mac_addr,
6760                                     I40E_ETH_LENGTH_OF_ADDRESS,
6761                                     I40E_NONDMA_TO_NONDMA);
6762                         i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
6763                                     I40E_ETH_LENGTH_OF_ADDRESS,
6764                                     I40E_NONDMA_TO_NONDMA);
6765                 }
6766                 vsi_res++;
6767         }
6768 }
6769
6770 /**
6771  * i40e_vf_reset
6772  * @hw: pointer to the hardware structure
6773  *
6774  * Send a VF_RESET message to the PF. Does not wait for response from PF
6775  * as none will be forthcoming. Immediately after calling this function,
6776  * the admin queue should be shut down and (optionally) reinitialized.
6777  **/
6778 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
6779 {
6780         return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
6781                                       I40E_SUCCESS, NULL, 0, NULL);
6782 }
6783 #endif /* VF_DRIVER */
6784 #ifdef X722_SUPPORT
6785
6786 /**
6787  * i40e_aq_set_arp_proxy_config
6788  * @hw: pointer to the HW structure
6789  * @proxy_config - pointer to proxy config command table struct
6790  * @cmd_details: pointer to command details
6791  *
6792  * Set ARP offload parameters from pre-populated
6793  * i40e_aqc_arp_proxy_data struct
6794  **/
6795 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
6796                                 struct i40e_aqc_arp_proxy_data *proxy_config,
6797                                 struct i40e_asq_cmd_details *cmd_details)
6798 {
6799         struct i40e_aq_desc desc;
6800         enum i40e_status_code status;
6801
6802         if (!proxy_config)
6803                 return I40E_ERR_PARAM;
6804
6805         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
6806
6807         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6808         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6809         desc.params.external.addr_high =
6810                                   CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
6811         desc.params.external.addr_low =
6812                                   CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
6813         desc.datalen = sizeof(struct i40e_aqc_arp_proxy_data);
6814
6815         status = i40e_asq_send_command(hw, &desc, proxy_config,
6816                                        sizeof(struct i40e_aqc_arp_proxy_data),
6817                                        cmd_details);
6818
6819         return status;
6820 }
6821
6822 /**
6823  * i40e_aq_opc_set_ns_proxy_table_entry
6824  * @hw: pointer to the HW structure
6825  * @ns_proxy_table_entry: pointer to NS table entry command struct
6826  * @cmd_details: pointer to command details
6827  *
6828  * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
6829  * from pre-populated i40e_aqc_ns_proxy_data struct
6830  **/
6831 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
6832                         struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
6833                         struct i40e_asq_cmd_details *cmd_details)
6834 {
6835         struct i40e_aq_desc desc;
6836         enum i40e_status_code status;
6837
6838         if (!ns_proxy_table_entry)
6839                 return I40E_ERR_PARAM;
6840
6841         i40e_fill_default_direct_cmd_desc(&desc,
6842                                 i40e_aqc_opc_set_ns_proxy_table_entry);
6843
6844         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6845         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6846         desc.params.external.addr_high =
6847                 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
6848         desc.params.external.addr_low =
6849                 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
6850         desc.datalen = sizeof(struct i40e_aqc_ns_proxy_data);
6851
6852         status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
6853                                        sizeof(struct i40e_aqc_ns_proxy_data),
6854                                        cmd_details);
6855
6856         return status;
6857 }
6858
6859 /**
6860  * i40e_aq_set_clear_wol_filter
6861  * @hw: pointer to the hw struct
6862  * @filter_index: index of filter to modify (0-7)
6863  * @filter: buffer containing filter to be set
6864  * @set_filter: true to set filter, false to clear filter
6865  * @no_wol_tco: if true, pass through packets cannot cause wake-up
6866  *              if false, pass through packets may cause wake-up
6867  * @filter_valid: true if filter action is valid
6868  * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
6869  * @cmd_details: pointer to command details structure or NULL
6870  *
6871  * Set or clear WoL filter for port attached to the PF
6872  **/
6873 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
6874                                 u8 filter_index,
6875                                 struct i40e_aqc_set_wol_filter_data *filter,
6876                                 bool set_filter, bool no_wol_tco,
6877                                 bool filter_valid, bool no_wol_tco_valid,
6878                                 struct i40e_asq_cmd_details *cmd_details)
6879 {
6880         struct i40e_aq_desc desc;
6881         struct i40e_aqc_set_wol_filter *cmd =
6882                 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
6883         enum i40e_status_code status;
6884         u16 cmd_flags = 0;
6885         u16 valid_flags = 0;
6886         u16 buff_len = 0;
6887
6888         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
6889
6890         if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
6891                 return  I40E_ERR_PARAM;
6892         cmd->filter_index = CPU_TO_LE16(filter_index);
6893
6894         if (set_filter) {
6895                 if (!filter)
6896                         return  I40E_ERR_PARAM;
6897
6898                 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
6899                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR;
6900         }
6901
6902         if (no_wol_tco)
6903                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
6904         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
6905
6906         if (filter_valid)
6907                 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
6908         if (no_wol_tco_valid)
6909                 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
6910         cmd->valid_flags = CPU_TO_LE16(valid_flags);
6911
6912         buff_len = sizeof(*filter);
6913         desc.datalen = buff_len;
6914
6915         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6916         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6917
6918         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
6919         cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
6920
6921         status = i40e_asq_send_command(hw, &desc, filter,
6922                                        buff_len, cmd_details);
6923
6924         return status;
6925 }
6926
6927 /**
6928  * i40e_aq_get_wake_event_reason
6929  * @hw: pointer to the hw struct
6930  * @wake_reason: return value, index of matching filter
6931  * @cmd_details: pointer to command details structure or NULL
6932  *
6933  * Get information for the reason of a Wake Up event
6934  **/
6935 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
6936                                 u16 *wake_reason,
6937                                 struct i40e_asq_cmd_details *cmd_details)
6938 {
6939         struct i40e_aq_desc desc;
6940         struct i40e_aqc_get_wake_reason_completion *resp =
6941                 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
6942         enum i40e_status_code status;
6943
6944         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
6945
6946         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6947
6948         if (status == I40E_SUCCESS)
6949                 *wake_reason = LE16_TO_CPU(resp->wake_reason);
6950
6951         return status;
6952 }
6953
6954 /**
6955 * i40e_aq_clear_all_wol_filters
6956 * @hw: pointer to the hw struct
6957 * @cmd_details: pointer to command details structure or NULL
6958 *
6959 * Get information for the reason of a Wake Up event
6960 **/
6961 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw,
6962         struct i40e_asq_cmd_details *cmd_details)
6963 {
6964         struct i40e_aq_desc desc;
6965         enum i40e_status_code status;
6966
6967         i40e_fill_default_direct_cmd_desc(&desc,
6968                                           i40e_aqc_opc_clear_all_wol_filters);
6969
6970         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6971
6972         return status;
6973 }
6974 #endif /* X722_SUPPORT */