1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2018
6 #include "i40e_adminq.h"
7 #include "i40e_prototype.h"
11 * i40e_set_mac_type - Sets MAC type
12 * @hw: pointer to the HW structure
14 * This function sets the mac type of the adapter based on the
15 * vendor ID and device ID stored in the hw structure.
17 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
18 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
20 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
23 enum i40e_status_code status = I40E_SUCCESS;
25 DEBUGFUNC("i40e_set_mac_type\n");
27 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
28 switch (hw->device_id) {
29 case I40E_DEV_ID_SFP_XL710:
30 case I40E_DEV_ID_QEMU:
31 case I40E_DEV_ID_KX_B:
32 case I40E_DEV_ID_KX_C:
33 case I40E_DEV_ID_QSFP_A:
34 case I40E_DEV_ID_QSFP_B:
35 case I40E_DEV_ID_QSFP_C:
36 case I40E_DEV_ID_10G_BASE_T:
37 case I40E_DEV_ID_10G_BASE_T4:
38 case I40E_DEV_ID_20G_KR2:
39 case I40E_DEV_ID_20G_KR2_A:
40 case I40E_DEV_ID_25G_B:
41 case I40E_DEV_ID_25G_SFP28:
42 hw->mac.type = I40E_MAC_XL710;
44 #ifdef X722_A0_SUPPORT
45 case I40E_DEV_ID_X722_A0:
47 case I40E_DEV_ID_KX_X722:
48 case I40E_DEV_ID_QSFP_X722:
49 case I40E_DEV_ID_SFP_X722:
50 case I40E_DEV_ID_1G_BASE_T_X722:
51 case I40E_DEV_ID_10G_BASE_T_X722:
52 case I40E_DEV_ID_SFP_I_X722:
53 hw->mac.type = I40E_MAC_X722;
55 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
56 case I40E_DEV_ID_X722_VF:
57 #ifdef X722_A0_SUPPORT
58 case I40E_DEV_ID_X722_A0_VF:
60 hw->mac.type = I40E_MAC_X722_VF;
62 #endif /* INTEGRATED_VF || VF_DRIVER */
63 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
65 case I40E_DEV_ID_VF_HV:
66 case I40E_DEV_ID_ADAPTIVE_VF:
67 hw->mac.type = I40E_MAC_VF;
71 hw->mac.type = I40E_MAC_GENERIC;
75 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
78 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
79 hw->mac.type, status);
84 * i40e_aq_str - convert AQ err code to a string
85 * @hw: pointer to the HW structure
86 * @aq_err: the AQ error code to convert
88 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
93 case I40E_AQ_RC_EPERM:
94 return "I40E_AQ_RC_EPERM";
95 case I40E_AQ_RC_ENOENT:
96 return "I40E_AQ_RC_ENOENT";
97 case I40E_AQ_RC_ESRCH:
98 return "I40E_AQ_RC_ESRCH";
99 case I40E_AQ_RC_EINTR:
100 return "I40E_AQ_RC_EINTR";
102 return "I40E_AQ_RC_EIO";
103 case I40E_AQ_RC_ENXIO:
104 return "I40E_AQ_RC_ENXIO";
105 case I40E_AQ_RC_E2BIG:
106 return "I40E_AQ_RC_E2BIG";
107 case I40E_AQ_RC_EAGAIN:
108 return "I40E_AQ_RC_EAGAIN";
109 case I40E_AQ_RC_ENOMEM:
110 return "I40E_AQ_RC_ENOMEM";
111 case I40E_AQ_RC_EACCES:
112 return "I40E_AQ_RC_EACCES";
113 case I40E_AQ_RC_EFAULT:
114 return "I40E_AQ_RC_EFAULT";
115 case I40E_AQ_RC_EBUSY:
116 return "I40E_AQ_RC_EBUSY";
117 case I40E_AQ_RC_EEXIST:
118 return "I40E_AQ_RC_EEXIST";
119 case I40E_AQ_RC_EINVAL:
120 return "I40E_AQ_RC_EINVAL";
121 case I40E_AQ_RC_ENOTTY:
122 return "I40E_AQ_RC_ENOTTY";
123 case I40E_AQ_RC_ENOSPC:
124 return "I40E_AQ_RC_ENOSPC";
125 case I40E_AQ_RC_ENOSYS:
126 return "I40E_AQ_RC_ENOSYS";
127 case I40E_AQ_RC_ERANGE:
128 return "I40E_AQ_RC_ERANGE";
129 case I40E_AQ_RC_EFLUSHED:
130 return "I40E_AQ_RC_EFLUSHED";
131 case I40E_AQ_RC_BAD_ADDR:
132 return "I40E_AQ_RC_BAD_ADDR";
133 case I40E_AQ_RC_EMODE:
134 return "I40E_AQ_RC_EMODE";
135 case I40E_AQ_RC_EFBIG:
136 return "I40E_AQ_RC_EFBIG";
139 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
144 * i40e_stat_str - convert status err code to a string
145 * @hw: pointer to the HW structure
146 * @stat_err: the status error code to convert
148 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
154 return "I40E_ERR_NVM";
155 case I40E_ERR_NVM_CHECKSUM:
156 return "I40E_ERR_NVM_CHECKSUM";
158 return "I40E_ERR_PHY";
159 case I40E_ERR_CONFIG:
160 return "I40E_ERR_CONFIG";
162 return "I40E_ERR_PARAM";
163 case I40E_ERR_MAC_TYPE:
164 return "I40E_ERR_MAC_TYPE";
165 case I40E_ERR_UNKNOWN_PHY:
166 return "I40E_ERR_UNKNOWN_PHY";
167 case I40E_ERR_LINK_SETUP:
168 return "I40E_ERR_LINK_SETUP";
169 case I40E_ERR_ADAPTER_STOPPED:
170 return "I40E_ERR_ADAPTER_STOPPED";
171 case I40E_ERR_INVALID_MAC_ADDR:
172 return "I40E_ERR_INVALID_MAC_ADDR";
173 case I40E_ERR_DEVICE_NOT_SUPPORTED:
174 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
175 case I40E_ERR_MASTER_REQUESTS_PENDING:
176 return "I40E_ERR_MASTER_REQUESTS_PENDING";
177 case I40E_ERR_INVALID_LINK_SETTINGS:
178 return "I40E_ERR_INVALID_LINK_SETTINGS";
179 case I40E_ERR_AUTONEG_NOT_COMPLETE:
180 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
181 case I40E_ERR_RESET_FAILED:
182 return "I40E_ERR_RESET_FAILED";
183 case I40E_ERR_SWFW_SYNC:
184 return "I40E_ERR_SWFW_SYNC";
185 case I40E_ERR_NO_AVAILABLE_VSI:
186 return "I40E_ERR_NO_AVAILABLE_VSI";
187 case I40E_ERR_NO_MEMORY:
188 return "I40E_ERR_NO_MEMORY";
189 case I40E_ERR_BAD_PTR:
190 return "I40E_ERR_BAD_PTR";
191 case I40E_ERR_RING_FULL:
192 return "I40E_ERR_RING_FULL";
193 case I40E_ERR_INVALID_PD_ID:
194 return "I40E_ERR_INVALID_PD_ID";
195 case I40E_ERR_INVALID_QP_ID:
196 return "I40E_ERR_INVALID_QP_ID";
197 case I40E_ERR_INVALID_CQ_ID:
198 return "I40E_ERR_INVALID_CQ_ID";
199 case I40E_ERR_INVALID_CEQ_ID:
200 return "I40E_ERR_INVALID_CEQ_ID";
201 case I40E_ERR_INVALID_AEQ_ID:
202 return "I40E_ERR_INVALID_AEQ_ID";
203 case I40E_ERR_INVALID_SIZE:
204 return "I40E_ERR_INVALID_SIZE";
205 case I40E_ERR_INVALID_ARP_INDEX:
206 return "I40E_ERR_INVALID_ARP_INDEX";
207 case I40E_ERR_INVALID_FPM_FUNC_ID:
208 return "I40E_ERR_INVALID_FPM_FUNC_ID";
209 case I40E_ERR_QP_INVALID_MSG_SIZE:
210 return "I40E_ERR_QP_INVALID_MSG_SIZE";
211 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
212 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
213 case I40E_ERR_INVALID_FRAG_COUNT:
214 return "I40E_ERR_INVALID_FRAG_COUNT";
215 case I40E_ERR_QUEUE_EMPTY:
216 return "I40E_ERR_QUEUE_EMPTY";
217 case I40E_ERR_INVALID_ALIGNMENT:
218 return "I40E_ERR_INVALID_ALIGNMENT";
219 case I40E_ERR_FLUSHED_QUEUE:
220 return "I40E_ERR_FLUSHED_QUEUE";
221 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
222 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
223 case I40E_ERR_INVALID_IMM_DATA_SIZE:
224 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
225 case I40E_ERR_TIMEOUT:
226 return "I40E_ERR_TIMEOUT";
227 case I40E_ERR_OPCODE_MISMATCH:
228 return "I40E_ERR_OPCODE_MISMATCH";
229 case I40E_ERR_CQP_COMPL_ERROR:
230 return "I40E_ERR_CQP_COMPL_ERROR";
231 case I40E_ERR_INVALID_VF_ID:
232 return "I40E_ERR_INVALID_VF_ID";
233 case I40E_ERR_INVALID_HMCFN_ID:
234 return "I40E_ERR_INVALID_HMCFN_ID";
235 case I40E_ERR_BACKING_PAGE_ERROR:
236 return "I40E_ERR_BACKING_PAGE_ERROR";
237 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
238 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
239 case I40E_ERR_INVALID_PBLE_INDEX:
240 return "I40E_ERR_INVALID_PBLE_INDEX";
241 case I40E_ERR_INVALID_SD_INDEX:
242 return "I40E_ERR_INVALID_SD_INDEX";
243 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
244 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
245 case I40E_ERR_INVALID_SD_TYPE:
246 return "I40E_ERR_INVALID_SD_TYPE";
247 case I40E_ERR_MEMCPY_FAILED:
248 return "I40E_ERR_MEMCPY_FAILED";
249 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
250 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
251 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
252 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
253 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
254 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
255 case I40E_ERR_SRQ_ENABLED:
256 return "I40E_ERR_SRQ_ENABLED";
257 case I40E_ERR_ADMIN_QUEUE_ERROR:
258 return "I40E_ERR_ADMIN_QUEUE_ERROR";
259 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
260 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
261 case I40E_ERR_BUF_TOO_SHORT:
262 return "I40E_ERR_BUF_TOO_SHORT";
263 case I40E_ERR_ADMIN_QUEUE_FULL:
264 return "I40E_ERR_ADMIN_QUEUE_FULL";
265 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
266 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
267 case I40E_ERR_BAD_IWARP_CQE:
268 return "I40E_ERR_BAD_IWARP_CQE";
269 case I40E_ERR_NVM_BLANK_MODE:
270 return "I40E_ERR_NVM_BLANK_MODE";
271 case I40E_ERR_NOT_IMPLEMENTED:
272 return "I40E_ERR_NOT_IMPLEMENTED";
273 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
274 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
275 case I40E_ERR_DIAG_TEST_FAILED:
276 return "I40E_ERR_DIAG_TEST_FAILED";
277 case I40E_ERR_NOT_READY:
278 return "I40E_ERR_NOT_READY";
279 case I40E_NOT_SUPPORTED:
280 return "I40E_NOT_SUPPORTED";
281 case I40E_ERR_FIRMWARE_API_VERSION:
282 return "I40E_ERR_FIRMWARE_API_VERSION";
283 case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR:
284 return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR";
287 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
293 * @hw: debug mask related to admin queue
295 * @desc: pointer to admin queue descriptor
296 * @buffer: pointer to command buffer
297 * @buf_len: max length of buffer
299 * Dumps debug log about adminq command with descriptor contents.
301 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
302 void *buffer, u16 buf_len)
304 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
305 u8 *buf = (u8 *)buffer;
309 if ((!(mask & hw->debug_mask)) || (desc == NULL))
312 len = LE16_TO_CPU(aq_desc->datalen);
315 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
316 LE16_TO_CPU(aq_desc->opcode),
317 LE16_TO_CPU(aq_desc->flags),
318 LE16_TO_CPU(aq_desc->datalen),
319 LE16_TO_CPU(aq_desc->retval));
320 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
321 LE32_TO_CPU(aq_desc->cookie_high),
322 LE32_TO_CPU(aq_desc->cookie_low));
323 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
324 LE32_TO_CPU(aq_desc->params.internal.param0),
325 LE32_TO_CPU(aq_desc->params.internal.param1));
326 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
327 LE32_TO_CPU(aq_desc->params.external.addr_high),
328 LE32_TO_CPU(aq_desc->params.external.addr_low));
330 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
331 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
334 /* write the full 16-byte chunks */
335 for (i = 0; i < (len - 16); i += 16)
337 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
338 i, buf[i], buf[i+1], buf[i+2], buf[i+3],
339 buf[i+4], buf[i+5], buf[i+6], buf[i+7],
340 buf[i+8], buf[i+9], buf[i+10], buf[i+11],
341 buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
342 /* the most we could have left is 16 bytes, pad with zeros */
348 memset(d_buf, 0, sizeof(d_buf));
349 for (j = 0; i < len; j++, i++)
352 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
353 i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
354 d_buf[4], d_buf[5], d_buf[6], d_buf[7],
355 d_buf[8], d_buf[9], d_buf[10], d_buf[11],
356 d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
362 * i40e_check_asq_alive
363 * @hw: pointer to the hw struct
365 * Returns true if Queue is enabled else false.
367 bool i40e_check_asq_alive(struct i40e_hw *hw)
373 return !!(rd32(hw, hw->aq.asq.len) &
374 I40E_PF_ATQLEN_ATQENABLE_MASK);
376 return !!(rd32(hw, hw->aq.asq.len) &
377 I40E_PF_ATQLEN_ATQENABLE_MASK);
378 #endif /* INTEGRATED_VF */
379 #endif /* PF_DRIVER */
383 return !!(rd32(hw, hw->aq.asq.len) &
384 I40E_VF_ATQLEN1_ATQENABLE_MASK);
386 return !!(rd32(hw, hw->aq.asq.len) &
387 I40E_VF_ATQLEN1_ATQENABLE_MASK);
388 #endif /* INTEGRATED_VF */
389 #endif /* VF_DRIVER */
394 * i40e_aq_queue_shutdown
395 * @hw: pointer to the hw struct
396 * @unloading: is the driver unloading itself
398 * Tell the Firmware that we're shutting down the AdminQ and whether
399 * or not the driver is unloading as well.
401 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
404 struct i40e_aq_desc desc;
405 struct i40e_aqc_queue_shutdown *cmd =
406 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
407 enum i40e_status_code status;
409 i40e_fill_default_direct_cmd_desc(&desc,
410 i40e_aqc_opc_queue_shutdown);
413 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
414 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
420 * i40e_aq_get_set_rss_lut
421 * @hw: pointer to the hardware structure
422 * @vsi_id: vsi fw index
423 * @pf_lut: for PF table set true, for VSI table set false
424 * @lut: pointer to the lut buffer provided by the caller
425 * @lut_size: size of the lut buffer
426 * @set: set true to set the table, false to get the table
428 * Internal function to get or set RSS look up table
430 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
431 u16 vsi_id, bool pf_lut,
432 u8 *lut, u16 lut_size,
435 enum i40e_status_code status;
436 struct i40e_aq_desc desc;
437 struct i40e_aqc_get_set_rss_lut *cmd_resp =
438 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
441 i40e_fill_default_direct_cmd_desc(&desc,
442 i40e_aqc_opc_set_rss_lut);
444 i40e_fill_default_direct_cmd_desc(&desc,
445 i40e_aqc_opc_get_rss_lut);
447 /* Indirect command */
448 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
449 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
452 CPU_TO_LE16((u16)((vsi_id <<
453 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
454 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
455 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
458 cmd_resp->flags |= CPU_TO_LE16((u16)
459 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
460 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
461 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
463 cmd_resp->flags |= CPU_TO_LE16((u16)
464 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
465 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
466 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
468 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
474 * i40e_aq_get_rss_lut
475 * @hw: pointer to the hardware structure
476 * @vsi_id: vsi fw index
477 * @pf_lut: for PF table set true, for VSI table set false
478 * @lut: pointer to the lut buffer provided by the caller
479 * @lut_size: size of the lut buffer
481 * get the RSS lookup table, PF or VSI type
483 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
484 bool pf_lut, u8 *lut, u16 lut_size)
486 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
491 * i40e_aq_set_rss_lut
492 * @hw: pointer to the hardware structure
493 * @vsi_id: vsi fw index
494 * @pf_lut: for PF table set true, for VSI table set false
495 * @lut: pointer to the lut buffer provided by the caller
496 * @lut_size: size of the lut buffer
498 * set the RSS lookup table, PF or VSI type
500 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
501 bool pf_lut, u8 *lut, u16 lut_size)
503 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
507 * i40e_aq_get_set_rss_key
508 * @hw: pointer to the hw struct
509 * @vsi_id: vsi fw index
510 * @key: pointer to key info struct
511 * @set: set true to set the key, false to get the key
513 * get the RSS key per VSI
515 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
517 struct i40e_aqc_get_set_rss_key_data *key,
520 enum i40e_status_code status;
521 struct i40e_aq_desc desc;
522 struct i40e_aqc_get_set_rss_key *cmd_resp =
523 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
524 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
527 i40e_fill_default_direct_cmd_desc(&desc,
528 i40e_aqc_opc_set_rss_key);
530 i40e_fill_default_direct_cmd_desc(&desc,
531 i40e_aqc_opc_get_rss_key);
533 /* Indirect command */
534 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
535 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
538 CPU_TO_LE16((u16)((vsi_id <<
539 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
540 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
541 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
543 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
549 * i40e_aq_get_rss_key
550 * @hw: pointer to the hw struct
551 * @vsi_id: vsi fw index
552 * @key: pointer to key info struct
555 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
557 struct i40e_aqc_get_set_rss_key_data *key)
559 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
563 * i40e_aq_set_rss_key
564 * @hw: pointer to the hw struct
565 * @vsi_id: vsi fw index
566 * @key: pointer to key info struct
568 * set the RSS key per VSI
570 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
572 struct i40e_aqc_get_set_rss_key_data *key)
574 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
577 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
578 * hardware to a bit-field that can be used by SW to more easily determine the
581 * Macros are used to shorten the table lines and make this table human
584 * We store the PTYPE in the top byte of the bit field - this is just so that
585 * we can check that the table doesn't have a row missing, as the index into
586 * the table should be the PTYPE.
590 * IF NOT i40e_ptype_lookup[ptype].known
593 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
594 * Use the rest of the fields to look at the tunnels, inner protocols, etc
596 * Use the enum i40e_rx_l2_ptype to decode the packet type
600 /* macro to make the table lines short */
601 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
604 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
605 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
606 I40E_RX_PTYPE_##OUTER_FRAG, \
607 I40E_RX_PTYPE_TUNNEL_##T, \
608 I40E_RX_PTYPE_TUNNEL_END_##TE, \
609 I40E_RX_PTYPE_##TEF, \
610 I40E_RX_PTYPE_INNER_PROT_##I, \
611 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
613 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
614 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
616 /* shorter macros makes the table fit but are terse */
617 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
618 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
619 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
621 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
622 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
623 /* L2 Packet types */
624 I40E_PTT_UNUSED_ENTRY(0),
625 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
626 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
627 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
628 I40E_PTT_UNUSED_ENTRY(4),
629 I40E_PTT_UNUSED_ENTRY(5),
630 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
631 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
632 I40E_PTT_UNUSED_ENTRY(8),
633 I40E_PTT_UNUSED_ENTRY(9),
634 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
635 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
636 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
637 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
638 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
639 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
640 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
641 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
642 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
643 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
644 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
645 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
647 /* Non Tunneled IPv4 */
648 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
649 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
650 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
651 I40E_PTT_UNUSED_ENTRY(25),
652 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
653 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
654 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
657 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
658 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
659 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
660 I40E_PTT_UNUSED_ENTRY(32),
661 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
662 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
663 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
666 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
667 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
668 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
669 I40E_PTT_UNUSED_ENTRY(39),
670 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
671 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
672 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
674 /* IPv4 --> GRE/NAT */
675 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
677 /* IPv4 --> GRE/NAT --> IPv4 */
678 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
679 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
680 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
681 I40E_PTT_UNUSED_ENTRY(47),
682 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
683 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
684 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
686 /* IPv4 --> GRE/NAT --> IPv6 */
687 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
688 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
689 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
690 I40E_PTT_UNUSED_ENTRY(54),
691 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
692 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
693 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
695 /* IPv4 --> GRE/NAT --> MAC */
696 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
698 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
699 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
700 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
701 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
702 I40E_PTT_UNUSED_ENTRY(62),
703 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
704 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
705 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
707 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
708 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
709 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
710 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
711 I40E_PTT_UNUSED_ENTRY(69),
712 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
713 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
714 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
716 /* IPv4 --> GRE/NAT --> MAC/VLAN */
717 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
719 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
720 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
721 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
722 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
723 I40E_PTT_UNUSED_ENTRY(77),
724 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
725 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
726 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
728 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
729 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
730 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
731 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
732 I40E_PTT_UNUSED_ENTRY(84),
733 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
734 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
735 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
737 /* Non Tunneled IPv6 */
738 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
739 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
740 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4),
741 I40E_PTT_UNUSED_ENTRY(91),
742 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
743 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
744 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
747 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
748 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
749 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
750 I40E_PTT_UNUSED_ENTRY(98),
751 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
752 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
753 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
756 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
757 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
758 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
759 I40E_PTT_UNUSED_ENTRY(105),
760 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
761 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
762 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
764 /* IPv6 --> GRE/NAT */
765 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
767 /* IPv6 --> GRE/NAT -> IPv4 */
768 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
769 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
770 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
771 I40E_PTT_UNUSED_ENTRY(113),
772 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
773 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
774 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
776 /* IPv6 --> GRE/NAT -> IPv6 */
777 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
778 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
779 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
780 I40E_PTT_UNUSED_ENTRY(120),
781 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
782 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
783 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
785 /* IPv6 --> GRE/NAT -> MAC */
786 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
788 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
789 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
790 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
791 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
792 I40E_PTT_UNUSED_ENTRY(128),
793 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
794 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
795 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
797 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
798 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
799 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
800 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
801 I40E_PTT_UNUSED_ENTRY(135),
802 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
803 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
804 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
806 /* IPv6 --> GRE/NAT -> MAC/VLAN */
807 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
809 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
810 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
811 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
812 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
813 I40E_PTT_UNUSED_ENTRY(143),
814 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
815 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
816 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
818 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
819 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
820 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
821 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
822 I40E_PTT_UNUSED_ENTRY(150),
823 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
824 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
825 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
828 I40E_PTT_UNUSED_ENTRY(154),
829 I40E_PTT_UNUSED_ENTRY(155),
830 I40E_PTT_UNUSED_ENTRY(156),
831 I40E_PTT_UNUSED_ENTRY(157),
832 I40E_PTT_UNUSED_ENTRY(158),
833 I40E_PTT_UNUSED_ENTRY(159),
835 I40E_PTT_UNUSED_ENTRY(160),
836 I40E_PTT_UNUSED_ENTRY(161),
837 I40E_PTT_UNUSED_ENTRY(162),
838 I40E_PTT_UNUSED_ENTRY(163),
839 I40E_PTT_UNUSED_ENTRY(164),
840 I40E_PTT_UNUSED_ENTRY(165),
841 I40E_PTT_UNUSED_ENTRY(166),
842 I40E_PTT_UNUSED_ENTRY(167),
843 I40E_PTT_UNUSED_ENTRY(168),
844 I40E_PTT_UNUSED_ENTRY(169),
846 I40E_PTT_UNUSED_ENTRY(170),
847 I40E_PTT_UNUSED_ENTRY(171),
848 I40E_PTT_UNUSED_ENTRY(172),
849 I40E_PTT_UNUSED_ENTRY(173),
850 I40E_PTT_UNUSED_ENTRY(174),
851 I40E_PTT_UNUSED_ENTRY(175),
852 I40E_PTT_UNUSED_ENTRY(176),
853 I40E_PTT_UNUSED_ENTRY(177),
854 I40E_PTT_UNUSED_ENTRY(178),
855 I40E_PTT_UNUSED_ENTRY(179),
857 I40E_PTT_UNUSED_ENTRY(180),
858 I40E_PTT_UNUSED_ENTRY(181),
859 I40E_PTT_UNUSED_ENTRY(182),
860 I40E_PTT_UNUSED_ENTRY(183),
861 I40E_PTT_UNUSED_ENTRY(184),
862 I40E_PTT_UNUSED_ENTRY(185),
863 I40E_PTT_UNUSED_ENTRY(186),
864 I40E_PTT_UNUSED_ENTRY(187),
865 I40E_PTT_UNUSED_ENTRY(188),
866 I40E_PTT_UNUSED_ENTRY(189),
868 I40E_PTT_UNUSED_ENTRY(190),
869 I40E_PTT_UNUSED_ENTRY(191),
870 I40E_PTT_UNUSED_ENTRY(192),
871 I40E_PTT_UNUSED_ENTRY(193),
872 I40E_PTT_UNUSED_ENTRY(194),
873 I40E_PTT_UNUSED_ENTRY(195),
874 I40E_PTT_UNUSED_ENTRY(196),
875 I40E_PTT_UNUSED_ENTRY(197),
876 I40E_PTT_UNUSED_ENTRY(198),
877 I40E_PTT_UNUSED_ENTRY(199),
879 I40E_PTT_UNUSED_ENTRY(200),
880 I40E_PTT_UNUSED_ENTRY(201),
881 I40E_PTT_UNUSED_ENTRY(202),
882 I40E_PTT_UNUSED_ENTRY(203),
883 I40E_PTT_UNUSED_ENTRY(204),
884 I40E_PTT_UNUSED_ENTRY(205),
885 I40E_PTT_UNUSED_ENTRY(206),
886 I40E_PTT_UNUSED_ENTRY(207),
887 I40E_PTT_UNUSED_ENTRY(208),
888 I40E_PTT_UNUSED_ENTRY(209),
890 I40E_PTT_UNUSED_ENTRY(210),
891 I40E_PTT_UNUSED_ENTRY(211),
892 I40E_PTT_UNUSED_ENTRY(212),
893 I40E_PTT_UNUSED_ENTRY(213),
894 I40E_PTT_UNUSED_ENTRY(214),
895 I40E_PTT_UNUSED_ENTRY(215),
896 I40E_PTT_UNUSED_ENTRY(216),
897 I40E_PTT_UNUSED_ENTRY(217),
898 I40E_PTT_UNUSED_ENTRY(218),
899 I40E_PTT_UNUSED_ENTRY(219),
901 I40E_PTT_UNUSED_ENTRY(220),
902 I40E_PTT_UNUSED_ENTRY(221),
903 I40E_PTT_UNUSED_ENTRY(222),
904 I40E_PTT_UNUSED_ENTRY(223),
905 I40E_PTT_UNUSED_ENTRY(224),
906 I40E_PTT_UNUSED_ENTRY(225),
907 I40E_PTT_UNUSED_ENTRY(226),
908 I40E_PTT_UNUSED_ENTRY(227),
909 I40E_PTT_UNUSED_ENTRY(228),
910 I40E_PTT_UNUSED_ENTRY(229),
912 I40E_PTT_UNUSED_ENTRY(230),
913 I40E_PTT_UNUSED_ENTRY(231),
914 I40E_PTT_UNUSED_ENTRY(232),
915 I40E_PTT_UNUSED_ENTRY(233),
916 I40E_PTT_UNUSED_ENTRY(234),
917 I40E_PTT_UNUSED_ENTRY(235),
918 I40E_PTT_UNUSED_ENTRY(236),
919 I40E_PTT_UNUSED_ENTRY(237),
920 I40E_PTT_UNUSED_ENTRY(238),
921 I40E_PTT_UNUSED_ENTRY(239),
923 I40E_PTT_UNUSED_ENTRY(240),
924 I40E_PTT_UNUSED_ENTRY(241),
925 I40E_PTT_UNUSED_ENTRY(242),
926 I40E_PTT_UNUSED_ENTRY(243),
927 I40E_PTT_UNUSED_ENTRY(244),
928 I40E_PTT_UNUSED_ENTRY(245),
929 I40E_PTT_UNUSED_ENTRY(246),
930 I40E_PTT_UNUSED_ENTRY(247),
931 I40E_PTT_UNUSED_ENTRY(248),
932 I40E_PTT_UNUSED_ENTRY(249),
934 I40E_PTT_UNUSED_ENTRY(250),
935 I40E_PTT_UNUSED_ENTRY(251),
936 I40E_PTT_UNUSED_ENTRY(252),
937 I40E_PTT_UNUSED_ENTRY(253),
938 I40E_PTT_UNUSED_ENTRY(254),
939 I40E_PTT_UNUSED_ENTRY(255)
944 * i40e_validate_mac_addr - Validate unicast MAC address
945 * @mac_addr: pointer to MAC address
947 * Tests a MAC address to ensure it is a valid Individual Address
949 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
951 enum i40e_status_code status = I40E_SUCCESS;
953 DEBUGFUNC("i40e_validate_mac_addr");
955 /* Broadcast addresses ARE multicast addresses
956 * Make sure it is not a multicast address
957 * Reject the zero address
959 if (I40E_IS_MULTICAST(mac_addr) ||
960 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
961 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
962 status = I40E_ERR_INVALID_MAC_ADDR;
969 * i40e_init_shared_code - Initialize the shared code
970 * @hw: pointer to hardware structure
972 * This assigns the MAC type and PHY code and inits the NVM.
973 * Does not touch the hardware. This function must be called prior to any
974 * other function in the shared code. The i40e_hw structure should be
975 * memset to 0 prior to calling this function. The following fields in
976 * hw structure should be filled in prior to calling this function:
977 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
978 * subsystem_vendor_id, and revision_id
980 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
982 enum i40e_status_code status = I40E_SUCCESS;
983 u32 port, ari, func_rid;
985 DEBUGFUNC("i40e_init_shared_code");
987 i40e_set_mac_type(hw);
989 switch (hw->mac.type) {
994 return I40E_ERR_DEVICE_NOT_SUPPORTED;
997 hw->phy.get_link_info = true;
999 /* Determine port number and PF number*/
1000 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1001 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1002 hw->port = (u8)port;
1003 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1004 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1005 func_rid = rd32(hw, I40E_PF_FUNC_RID);
1007 hw->pf_id = (u8)(func_rid & 0xff);
1009 hw->pf_id = (u8)(func_rid & 0x7);
1011 if (hw->mac.type == I40E_MAC_X722)
1012 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE |
1013 I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK;
1015 status = i40e_init_nvm(hw);
1020 * i40e_aq_mac_address_read - Retrieve the MAC addresses
1021 * @hw: pointer to the hw struct
1022 * @flags: a return indicator of what addresses were added to the addr store
1023 * @addrs: the requestor's mac addr store
1024 * @cmd_details: pointer to command details structure or NULL
1026 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1028 struct i40e_aqc_mac_address_read_data *addrs,
1029 struct i40e_asq_cmd_details *cmd_details)
1031 struct i40e_aq_desc desc;
1032 struct i40e_aqc_mac_address_read *cmd_data =
1033 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1034 enum i40e_status_code status;
1036 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1037 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1039 status = i40e_asq_send_command(hw, &desc, addrs,
1040 sizeof(*addrs), cmd_details);
1041 *flags = LE16_TO_CPU(cmd_data->command_flags);
1047 * i40e_aq_mac_address_write - Change the MAC addresses
1048 * @hw: pointer to the hw struct
1049 * @flags: indicates which MAC to be written
1050 * @mac_addr: address to write
1051 * @cmd_details: pointer to command details structure or NULL
1053 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1054 u16 flags, u8 *mac_addr,
1055 struct i40e_asq_cmd_details *cmd_details)
1057 struct i40e_aq_desc desc;
1058 struct i40e_aqc_mac_address_write *cmd_data =
1059 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1060 enum i40e_status_code status;
1062 i40e_fill_default_direct_cmd_desc(&desc,
1063 i40e_aqc_opc_mac_address_write);
1064 cmd_data->command_flags = CPU_TO_LE16(flags);
1065 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1066 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1067 ((u32)mac_addr[3] << 16) |
1068 ((u32)mac_addr[4] << 8) |
1071 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1077 * i40e_get_mac_addr - get MAC address
1078 * @hw: pointer to the HW structure
1079 * @mac_addr: pointer to MAC address
1081 * Reads the adapter's MAC address from register
1083 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1085 struct i40e_aqc_mac_address_read_data addrs;
1086 enum i40e_status_code status;
1089 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1091 if (flags & I40E_AQC_LAN_ADDR_VALID)
1092 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1093 I40E_NONDMA_TO_NONDMA);
1099 * i40e_get_port_mac_addr - get Port MAC address
1100 * @hw: pointer to the HW structure
1101 * @mac_addr: pointer to Port MAC address
1103 * Reads the adapter's Port MAC address
1105 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1107 struct i40e_aqc_mac_address_read_data addrs;
1108 enum i40e_status_code status;
1111 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1115 if (flags & I40E_AQC_PORT_ADDR_VALID)
1116 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1117 I40E_NONDMA_TO_NONDMA);
1119 status = I40E_ERR_INVALID_MAC_ADDR;
1125 * i40e_pre_tx_queue_cfg - pre tx queue configure
1126 * @hw: pointer to the HW structure
1127 * @queue: target pf queue index
1128 * @enable: state change request
1130 * Handles hw requirement to indicate intention to enable
1131 * or disable target queue.
1133 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1135 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1139 if (abs_queue_idx >= 128) {
1140 reg_block = abs_queue_idx / 128;
1141 abs_queue_idx %= 128;
1144 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1145 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1146 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1149 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1151 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1153 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1157 * i40e_get_san_mac_addr - get SAN MAC address
1158 * @hw: pointer to the HW structure
1159 * @mac_addr: pointer to SAN MAC address
1161 * Reads the adapter's SAN MAC address from NVM
1163 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1166 struct i40e_aqc_mac_address_read_data addrs;
1167 enum i40e_status_code status;
1170 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1174 if (flags & I40E_AQC_SAN_ADDR_VALID)
1175 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac),
1176 I40E_NONDMA_TO_NONDMA);
1178 status = I40E_ERR_INVALID_MAC_ADDR;
1184 * i40e_read_pba_string - Reads part number string from EEPROM
1185 * @hw: pointer to hardware structure
1186 * @pba_num: stores the part number string from the EEPROM
1187 * @pba_num_size: part number string buffer length
1189 * Reads the part number string from the EEPROM.
1191 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1194 enum i40e_status_code status = I40E_SUCCESS;
1200 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1201 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1202 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1206 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1207 if (status != I40E_SUCCESS) {
1208 DEBUGOUT("Failed to read PBA Block pointer.\n");
1212 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1213 if (status != I40E_SUCCESS) {
1214 DEBUGOUT("Failed to read PBA Block size.\n");
1218 /* Subtract one to get PBA word count (PBA Size word is included in
1222 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1223 DEBUGOUT("Buffer to small for PBA data.\n");
1224 return I40E_ERR_PARAM;
1227 for (i = 0; i < pba_size; i++) {
1228 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1229 if (status != I40E_SUCCESS) {
1230 DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1234 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1235 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1237 pba_num[(pba_size * 2)] = '\0';
1243 * i40e_get_media_type - Gets media type
1244 * @hw: pointer to the hardware structure
1246 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1248 enum i40e_media_type media;
1250 switch (hw->phy.link_info.phy_type) {
1251 case I40E_PHY_TYPE_10GBASE_SR:
1252 case I40E_PHY_TYPE_10GBASE_LR:
1253 case I40E_PHY_TYPE_1000BASE_SX:
1254 case I40E_PHY_TYPE_1000BASE_LX:
1255 case I40E_PHY_TYPE_40GBASE_SR4:
1256 case I40E_PHY_TYPE_40GBASE_LR4:
1257 case I40E_PHY_TYPE_25GBASE_LR:
1258 case I40E_PHY_TYPE_25GBASE_SR:
1259 media = I40E_MEDIA_TYPE_FIBER;
1261 case I40E_PHY_TYPE_100BASE_TX:
1262 case I40E_PHY_TYPE_1000BASE_T:
1263 case I40E_PHY_TYPE_10GBASE_T:
1264 media = I40E_MEDIA_TYPE_BASET;
1266 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1267 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1268 case I40E_PHY_TYPE_10GBASE_CR1:
1269 case I40E_PHY_TYPE_40GBASE_CR4:
1270 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1271 case I40E_PHY_TYPE_40GBASE_AOC:
1272 case I40E_PHY_TYPE_10GBASE_AOC:
1273 case I40E_PHY_TYPE_25GBASE_CR:
1274 case I40E_PHY_TYPE_25GBASE_AOC:
1275 case I40E_PHY_TYPE_25GBASE_ACC:
1276 media = I40E_MEDIA_TYPE_DA;
1278 case I40E_PHY_TYPE_1000BASE_KX:
1279 case I40E_PHY_TYPE_10GBASE_KX4:
1280 case I40E_PHY_TYPE_10GBASE_KR:
1281 case I40E_PHY_TYPE_40GBASE_KR4:
1282 case I40E_PHY_TYPE_20GBASE_KR2:
1283 case I40E_PHY_TYPE_25GBASE_KR:
1284 media = I40E_MEDIA_TYPE_BACKPLANE;
1286 case I40E_PHY_TYPE_SGMII:
1287 case I40E_PHY_TYPE_XAUI:
1288 case I40E_PHY_TYPE_XFI:
1289 case I40E_PHY_TYPE_XLAUI:
1290 case I40E_PHY_TYPE_XLPPI:
1292 media = I40E_MEDIA_TYPE_UNKNOWN;
1299 #define I40E_PF_RESET_WAIT_COUNT 200
1301 * i40e_pf_reset - Reset the PF
1302 * @hw: pointer to the hardware structure
1304 * Assuming someone else has triggered a global reset,
1305 * assure the global reset is complete and then reset the PF
1307 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1314 /* Poll for Global Reset steady state in case of recent GRST.
1315 * The grst delay value is in 100ms units, and we'll wait a
1316 * couple counts longer to be sure we don't just miss the end.
1318 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1319 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1320 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1322 grst_del = grst_del * 20;
1324 for (cnt = 0; cnt < grst_del; cnt++) {
1325 reg = rd32(hw, I40E_GLGEN_RSTAT);
1326 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1328 i40e_msec_delay(100);
1330 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1331 DEBUGOUT("Global reset polling failed to complete.\n");
1332 return I40E_ERR_RESET_FAILED;
1335 /* Now Wait for the FW to be ready */
1336 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1337 reg = rd32(hw, I40E_GLNVM_ULD);
1338 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1339 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1340 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1341 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1342 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1345 i40e_msec_delay(10);
1347 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1348 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1349 DEBUGOUT("wait for FW Reset complete timedout\n");
1350 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1351 return I40E_ERR_RESET_FAILED;
1354 /* If there was a Global Reset in progress when we got here,
1355 * we don't need to do the PF Reset
1360 reg = rd32(hw, I40E_PFGEN_CTRL);
1361 wr32(hw, I40E_PFGEN_CTRL,
1362 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1363 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1364 reg = rd32(hw, I40E_PFGEN_CTRL);
1365 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1367 reg2 = rd32(hw, I40E_GLGEN_RSTAT);
1368 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1369 DEBUGOUT("Core reset upcoming. Skipping PF reset request.\n");
1370 DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg2);
1371 return I40E_ERR_NOT_READY;
1375 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1376 DEBUGOUT("PF reset polling failed to complete.\n");
1377 return I40E_ERR_RESET_FAILED;
1381 i40e_clear_pxe_mode(hw);
1384 return I40E_SUCCESS;
1388 * i40e_clear_hw - clear out any left over hw state
1389 * @hw: pointer to the hw struct
1391 * Clear queues and interrupts, typically called at init time,
1392 * but after the capabilities have been found so we know how many
1393 * queues and msix vectors have been allocated.
1395 void i40e_clear_hw(struct i40e_hw *hw)
1397 u32 num_queues, base_queue;
1405 /* get number of interrupts, queues, and vfs */
1406 val = rd32(hw, I40E_GLPCI_CNF2);
1407 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1408 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1409 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1410 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1412 val = rd32(hw, I40E_PFLAN_QALLOC);
1413 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1414 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1415 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1416 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1417 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1418 num_queues = (j - base_queue) + 1;
1422 val = rd32(hw, I40E_PF_VT_PFALLOC);
1423 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1424 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1425 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1426 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1427 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1428 num_vfs = (j - i) + 1;
1432 /* stop all the interrupts */
1433 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1434 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1435 for (i = 0; i < num_pf_int - 2; i++)
1436 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1438 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1439 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1440 wr32(hw, I40E_PFINT_LNKLST0, val);
1441 for (i = 0; i < num_pf_int - 2; i++)
1442 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1443 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1444 for (i = 0; i < num_vfs; i++)
1445 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1446 for (i = 0; i < num_vf_int - 2; i++)
1447 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1449 /* warn the HW of the coming Tx disables */
1450 for (i = 0; i < num_queues; i++) {
1451 u32 abs_queue_idx = base_queue + i;
1454 if (abs_queue_idx >= 128) {
1455 reg_block = abs_queue_idx / 128;
1456 abs_queue_idx %= 128;
1459 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1460 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1461 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1462 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1464 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1466 i40e_usec_delay(400);
1468 /* stop all the queues */
1469 for (i = 0; i < num_queues; i++) {
1470 wr32(hw, I40E_QINT_TQCTL(i), 0);
1471 wr32(hw, I40E_QTX_ENA(i), 0);
1472 wr32(hw, I40E_QINT_RQCTL(i), 0);
1473 wr32(hw, I40E_QRX_ENA(i), 0);
1476 /* short wait for all queue disables to settle */
1477 i40e_usec_delay(50);
1481 * i40e_clear_pxe_mode - clear pxe operations mode
1482 * @hw: pointer to the hw struct
1484 * Make sure all PXE mode settings are cleared, including things
1485 * like descriptor fetch/write-back mode.
1487 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1489 if (i40e_check_asq_alive(hw))
1490 i40e_aq_clear_pxe_mode(hw, NULL);
1494 * i40e_led_is_mine - helper to find matching led
1495 * @hw: pointer to the hw struct
1496 * @idx: index into GPIO registers
1498 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1500 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1505 if (!hw->func_caps.led[idx])
1508 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1509 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1510 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1512 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1513 * if it is not our port then ignore
1515 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1522 #define I40E_COMBINED_ACTIVITY 0xA
1523 #define I40E_FILTER_ACTIVITY 0xE
1524 #define I40E_LINK_ACTIVITY 0xC
1525 #define I40E_MAC_ACTIVITY 0xD
1526 #define I40E_LED0 22
1529 * i40e_led_get - return current on/off mode
1530 * @hw: pointer to the hw struct
1532 * The value returned is the 'mode' field as defined in the
1533 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1534 * values are variations of possible behaviors relating to
1535 * blink, link, and wire.
1537 u32 i40e_led_get(struct i40e_hw *hw)
1539 u32 current_mode = 0;
1543 /* as per the documentation GPIO 22-29 are the LED
1544 * GPIO pins named LED0..LED7
1546 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1547 u32 gpio_val = i40e_led_is_mine(hw, i);
1552 /* ignore gpio LED src mode entries related to the activity
1555 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1556 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1557 switch (current_mode) {
1558 case I40E_COMBINED_ACTIVITY:
1559 case I40E_FILTER_ACTIVITY:
1560 case I40E_MAC_ACTIVITY:
1561 case I40E_LINK_ACTIVITY:
1567 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1568 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1576 * i40e_led_set - set new on/off mode
1577 * @hw: pointer to the hw struct
1578 * @mode: 0=off, 0xf=on (else see manual for mode details)
1579 * @blink: true if the LED should blink when on, false if steady
1581 * if this function is used to turn on the blink it should
1582 * be used to disable the blink when restoring the original state.
1584 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1586 u32 current_mode = 0;
1589 if (mode & 0xfffffff0)
1590 DEBUGOUT1("invalid mode passed in %X\n", mode);
1592 /* as per the documentation GPIO 22-29 are the LED
1593 * GPIO pins named LED0..LED7
1595 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1596 u32 gpio_val = i40e_led_is_mine(hw, i);
1601 /* ignore gpio LED src mode entries related to the activity
1604 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1605 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1606 switch (current_mode) {
1607 case I40E_COMBINED_ACTIVITY:
1608 case I40E_FILTER_ACTIVITY:
1609 case I40E_MAC_ACTIVITY:
1610 case I40E_LINK_ACTIVITY:
1616 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1617 /* this & is a bit of paranoia, but serves as a range check */
1618 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1619 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1622 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1624 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1626 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1631 /* Admin command wrappers */
1634 * i40e_aq_get_phy_capabilities
1635 * @hw: pointer to the hw struct
1636 * @abilities: structure for PHY capabilities to be filled
1637 * @qualified_modules: report Qualified Modules
1638 * @report_init: report init capabilities (active are default)
1639 * @cmd_details: pointer to command details structure or NULL
1641 * Returns the various PHY abilities supported on the Port.
1643 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1644 bool qualified_modules, bool report_init,
1645 struct i40e_aq_get_phy_abilities_resp *abilities,
1646 struct i40e_asq_cmd_details *cmd_details)
1648 struct i40e_aq_desc desc;
1649 enum i40e_status_code status;
1650 u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0;
1651 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1654 return I40E_ERR_PARAM;
1657 i40e_fill_default_direct_cmd_desc(&desc,
1658 i40e_aqc_opc_get_phy_abilities);
1660 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1661 if (abilities_size > I40E_AQ_LARGE_BUF)
1662 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1664 if (qualified_modules)
1665 desc.params.external.param0 |=
1666 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1669 desc.params.external.param0 |=
1670 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1672 status = i40e_asq_send_command(hw, &desc, abilities,
1673 abilities_size, cmd_details);
1675 if (status != I40E_SUCCESS)
1678 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) {
1679 status = I40E_ERR_UNKNOWN_PHY;
1681 } else if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) {
1684 status = I40E_ERR_TIMEOUT;
1686 } while ((hw->aq.asq_last_status != I40E_AQ_RC_OK) &&
1687 (total_delay < max_delay));
1689 if (status != I40E_SUCCESS)
1693 if (hw->mac.type == I40E_MAC_XL710 &&
1694 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1695 hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
1696 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1698 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1699 hw->phy.phy_types |=
1700 ((u64)abilities->phy_type_ext << 32);
1708 * i40e_aq_set_phy_config
1709 * @hw: pointer to the hw struct
1710 * @config: structure with PHY configuration to be set
1711 * @cmd_details: pointer to command details structure or NULL
1713 * Set the various PHY configuration parameters
1714 * supported on the Port.One or more of the Set PHY config parameters may be
1715 * ignored in an MFP mode as the PF may not have the privilege to set some
1716 * of the PHY Config parameters. This status will be indicated by the
1719 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1720 struct i40e_aq_set_phy_config *config,
1721 struct i40e_asq_cmd_details *cmd_details)
1723 struct i40e_aq_desc desc;
1724 struct i40e_aq_set_phy_config *cmd =
1725 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1726 enum i40e_status_code status;
1729 return I40E_ERR_PARAM;
1731 i40e_fill_default_direct_cmd_desc(&desc,
1732 i40e_aqc_opc_set_phy_config);
1736 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1743 * @hw: pointer to the hw struct
1744 * @aq_failures: buffer to return AdminQ failure information
1745 * @atomic_restart: whether to enable atomic link restart
1747 * Set the requested flow control mode using set_phy_config.
1749 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1750 bool atomic_restart)
1752 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1753 struct i40e_aq_get_phy_abilities_resp abilities;
1754 struct i40e_aq_set_phy_config config;
1755 enum i40e_status_code status;
1756 u8 pause_mask = 0x0;
1762 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1763 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1765 case I40E_FC_RX_PAUSE:
1766 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1768 case I40E_FC_TX_PAUSE:
1769 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1775 /* Get the current phy config */
1776 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1779 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1783 memset(&config, 0, sizeof(config));
1784 /* clear the old pause settings */
1785 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1786 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1787 /* set the new abilities */
1788 config.abilities |= pause_mask;
1789 /* If the abilities have changed, then set the new config */
1790 if (config.abilities != abilities.abilities) {
1791 /* Auto restart link so settings take effect */
1793 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1794 /* Copy over all the old settings */
1795 config.phy_type = abilities.phy_type;
1796 config.phy_type_ext = abilities.phy_type_ext;
1797 config.link_speed = abilities.link_speed;
1798 config.eee_capability = abilities.eee_capability;
1799 config.eeer = abilities.eeer_val;
1800 config.low_power_ctrl = abilities.d3_lpan;
1801 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1802 I40E_AQ_PHY_FEC_CONFIG_MASK;
1803 status = i40e_aq_set_phy_config(hw, &config, NULL);
1806 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1808 /* Update the link info */
1809 status = i40e_update_link_info(hw);
1811 /* Wait a little bit (on 40G cards it sometimes takes a really
1812 * long time for link to come back from the atomic reset)
1815 i40e_msec_delay(1000);
1816 status = i40e_update_link_info(hw);
1819 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1825 * i40e_aq_set_mac_config
1826 * @hw: pointer to the hw struct
1827 * @max_frame_size: Maximum Frame Size to be supported by the port
1828 * @crc_en: Tell HW to append a CRC to outgoing frames
1829 * @pacing: Pacing configurations
1830 * @cmd_details: pointer to command details structure or NULL
1832 * Configure MAC settings for frame size, jumbo frame support and the
1833 * addition of a CRC by the hardware.
1835 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1837 bool crc_en, u16 pacing,
1838 struct i40e_asq_cmd_details *cmd_details)
1840 struct i40e_aq_desc desc;
1841 struct i40e_aq_set_mac_config *cmd =
1842 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1843 enum i40e_status_code status;
1845 if (max_frame_size == 0)
1846 return I40E_ERR_PARAM;
1848 i40e_fill_default_direct_cmd_desc(&desc,
1849 i40e_aqc_opc_set_mac_config);
1851 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1852 cmd->params = ((u8)pacing & 0x0F) << 3;
1854 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1856 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1862 * i40e_aq_clear_pxe_mode
1863 * @hw: pointer to the hw struct
1864 * @cmd_details: pointer to command details structure or NULL
1866 * Tell the firmware that the driver is taking over from PXE
1868 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1869 struct i40e_asq_cmd_details *cmd_details)
1871 enum i40e_status_code status;
1872 struct i40e_aq_desc desc;
1873 struct i40e_aqc_clear_pxe *cmd =
1874 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1876 i40e_fill_default_direct_cmd_desc(&desc,
1877 i40e_aqc_opc_clear_pxe_mode);
1881 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1883 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1889 * i40e_aq_set_link_restart_an
1890 * @hw: pointer to the hw struct
1891 * @enable_link: if true: enable link, if false: disable link
1892 * @cmd_details: pointer to command details structure or NULL
1894 * Sets up the link and restarts the Auto-Negotiation over the link.
1896 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1897 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1899 struct i40e_aq_desc desc;
1900 struct i40e_aqc_set_link_restart_an *cmd =
1901 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1902 enum i40e_status_code status;
1904 i40e_fill_default_direct_cmd_desc(&desc,
1905 i40e_aqc_opc_set_link_restart_an);
1907 cmd->command = I40E_AQ_PHY_RESTART_AN;
1909 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1911 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1913 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1919 * i40e_aq_get_link_info
1920 * @hw: pointer to the hw struct
1921 * @enable_lse: enable/disable LinkStatusEvent reporting
1922 * @link: pointer to link status structure - optional
1923 * @cmd_details: pointer to command details structure or NULL
1925 * Returns the link status of the adapter.
1927 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1928 bool enable_lse, struct i40e_link_status *link,
1929 struct i40e_asq_cmd_details *cmd_details)
1931 struct i40e_aq_desc desc;
1932 struct i40e_aqc_get_link_status *resp =
1933 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1934 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1935 enum i40e_status_code status;
1936 bool tx_pause, rx_pause;
1939 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1942 command_flags = I40E_AQ_LSE_ENABLE;
1944 command_flags = I40E_AQ_LSE_DISABLE;
1945 resp->command_flags = CPU_TO_LE16(command_flags);
1947 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1949 if (status != I40E_SUCCESS)
1950 goto aq_get_link_info_exit;
1952 /* save off old link status information */
1953 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1954 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1956 /* update link status */
1957 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1958 hw->phy.media_type = i40e_get_media_type(hw);
1959 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1960 hw_link_info->link_info = resp->link_info;
1961 hw_link_info->an_info = resp->an_info;
1962 hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
1963 I40E_AQ_CONFIG_FEC_RS_ENA);
1964 hw_link_info->ext_info = resp->ext_info;
1965 hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
1966 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1967 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1969 /* update fc info */
1970 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1971 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1972 if (tx_pause & rx_pause)
1973 hw->fc.current_mode = I40E_FC_FULL;
1975 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1977 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1979 hw->fc.current_mode = I40E_FC_NONE;
1981 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1982 hw_link_info->crc_enable = true;
1984 hw_link_info->crc_enable = false;
1986 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
1987 hw_link_info->lse_enable = true;
1989 hw_link_info->lse_enable = false;
1991 if ((hw->mac.type == I40E_MAC_XL710) &&
1992 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1993 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1994 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1996 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1997 hw->aq.api_min_ver >= 7) {
2000 i40e_memcpy(&tmp, resp->link_type, sizeof(tmp),
2001 I40E_NONDMA_TO_NONDMA);
2002 hw->phy.phy_types = LE32_TO_CPU(tmp);
2003 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
2006 /* save link status information */
2008 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
2009 I40E_NONDMA_TO_NONDMA);
2011 /* flag cleared so helper functions don't call AQ again */
2012 hw->phy.get_link_info = false;
2014 aq_get_link_info_exit:
2019 * i40e_aq_set_phy_int_mask
2020 * @hw: pointer to the hw struct
2021 * @mask: interrupt mask to be set
2022 * @cmd_details: pointer to command details structure or NULL
2024 * Set link interrupt mask.
2026 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2028 struct i40e_asq_cmd_details *cmd_details)
2030 struct i40e_aq_desc desc;
2031 struct i40e_aqc_set_phy_int_mask *cmd =
2032 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2033 enum i40e_status_code status;
2035 i40e_fill_default_direct_cmd_desc(&desc,
2036 i40e_aqc_opc_set_phy_int_mask);
2038 cmd->event_mask = CPU_TO_LE16(mask);
2040 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2046 * i40e_aq_get_local_advt_reg
2047 * @hw: pointer to the hw struct
2048 * @advt_reg: local AN advertisement register value
2049 * @cmd_details: pointer to command details structure or NULL
2051 * Get the Local AN advertisement register value.
2053 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2055 struct i40e_asq_cmd_details *cmd_details)
2057 struct i40e_aq_desc desc;
2058 struct i40e_aqc_an_advt_reg *resp =
2059 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2060 enum i40e_status_code status;
2062 i40e_fill_default_direct_cmd_desc(&desc,
2063 i40e_aqc_opc_get_local_advt_reg);
2065 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2067 if (status != I40E_SUCCESS)
2068 goto aq_get_local_advt_reg_exit;
2070 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2071 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2073 aq_get_local_advt_reg_exit:
2078 * i40e_aq_set_local_advt_reg
2079 * @hw: pointer to the hw struct
2080 * @advt_reg: local AN advertisement register value
2081 * @cmd_details: pointer to command details structure or NULL
2083 * Get the Local AN advertisement register value.
2085 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2087 struct i40e_asq_cmd_details *cmd_details)
2089 struct i40e_aq_desc desc;
2090 struct i40e_aqc_an_advt_reg *cmd =
2091 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2092 enum i40e_status_code status;
2094 i40e_fill_default_direct_cmd_desc(&desc,
2095 i40e_aqc_opc_get_local_advt_reg);
2097 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2098 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2100 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2106 * i40e_aq_get_partner_advt
2107 * @hw: pointer to the hw struct
2108 * @advt_reg: AN partner advertisement register value
2109 * @cmd_details: pointer to command details structure or NULL
2111 * Get the link partner AN advertisement register value.
2113 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2115 struct i40e_asq_cmd_details *cmd_details)
2117 struct i40e_aq_desc desc;
2118 struct i40e_aqc_an_advt_reg *resp =
2119 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2120 enum i40e_status_code status;
2122 i40e_fill_default_direct_cmd_desc(&desc,
2123 i40e_aqc_opc_get_partner_advt);
2125 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2127 if (status != I40E_SUCCESS)
2128 goto aq_get_partner_advt_exit;
2130 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2131 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2133 aq_get_partner_advt_exit:
2138 * i40e_aq_set_lb_modes
2139 * @hw: pointer to the hw struct
2140 * @lb_modes: loopback mode to be set
2141 * @cmd_details: pointer to command details structure or NULL
2143 * Sets loopback modes.
2145 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2147 struct i40e_asq_cmd_details *cmd_details)
2149 struct i40e_aq_desc desc;
2150 struct i40e_aqc_set_lb_mode *cmd =
2151 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2152 enum i40e_status_code status;
2154 i40e_fill_default_direct_cmd_desc(&desc,
2155 i40e_aqc_opc_set_lb_modes);
2157 cmd->lb_mode = CPU_TO_LE16(lb_modes);
2159 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2165 * i40e_aq_set_phy_debug
2166 * @hw: pointer to the hw struct
2167 * @cmd_flags: debug command flags
2168 * @cmd_details: pointer to command details structure or NULL
2170 * Reset the external PHY.
2172 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2173 struct i40e_asq_cmd_details *cmd_details)
2175 struct i40e_aq_desc desc;
2176 struct i40e_aqc_set_phy_debug *cmd =
2177 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2178 enum i40e_status_code status;
2180 i40e_fill_default_direct_cmd_desc(&desc,
2181 i40e_aqc_opc_set_phy_debug);
2183 cmd->command_flags = cmd_flags;
2185 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2192 * @hw: pointer to the hw struct
2193 * @vsi_ctx: pointer to a vsi context struct
2194 * @cmd_details: pointer to command details structure or NULL
2196 * Add a VSI context to the hardware.
2198 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2199 struct i40e_vsi_context *vsi_ctx,
2200 struct i40e_asq_cmd_details *cmd_details)
2202 struct i40e_aq_desc desc;
2203 struct i40e_aqc_add_get_update_vsi *cmd =
2204 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2205 struct i40e_aqc_add_get_update_vsi_completion *resp =
2206 (struct i40e_aqc_add_get_update_vsi_completion *)
2208 enum i40e_status_code status;
2210 i40e_fill_default_direct_cmd_desc(&desc,
2211 i40e_aqc_opc_add_vsi);
2213 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2214 cmd->connection_type = vsi_ctx->connection_type;
2215 cmd->vf_id = vsi_ctx->vf_num;
2216 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2218 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2220 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2221 sizeof(vsi_ctx->info), cmd_details);
2223 if (status != I40E_SUCCESS)
2224 goto aq_add_vsi_exit;
2226 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2227 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2228 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2229 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2236 * i40e_aq_set_default_vsi
2237 * @hw: pointer to the hw struct
2239 * @cmd_details: pointer to command details structure or NULL
2241 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2243 struct i40e_asq_cmd_details *cmd_details)
2245 struct i40e_aq_desc desc;
2246 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2247 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2249 enum i40e_status_code status;
2251 i40e_fill_default_direct_cmd_desc(&desc,
2252 i40e_aqc_opc_set_vsi_promiscuous_modes);
2254 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2255 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2256 cmd->seid = CPU_TO_LE16(seid);
2258 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2264 * i40e_aq_clear_default_vsi
2265 * @hw: pointer to the hw struct
2267 * @cmd_details: pointer to command details structure or NULL
2269 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2271 struct i40e_asq_cmd_details *cmd_details)
2273 struct i40e_aq_desc desc;
2274 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2275 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2277 enum i40e_status_code status;
2279 i40e_fill_default_direct_cmd_desc(&desc,
2280 i40e_aqc_opc_set_vsi_promiscuous_modes);
2282 cmd->promiscuous_flags = CPU_TO_LE16(0);
2283 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2284 cmd->seid = CPU_TO_LE16(seid);
2286 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2292 * i40e_aq_set_vsi_unicast_promiscuous
2293 * @hw: pointer to the hw struct
2295 * @set: set unicast promiscuous enable/disable
2296 * @cmd_details: pointer to command details structure or NULL
2297 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2299 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2301 struct i40e_asq_cmd_details *cmd_details,
2302 bool rx_only_promisc)
2304 struct i40e_aq_desc desc;
2305 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2306 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2307 enum i40e_status_code status;
2310 i40e_fill_default_direct_cmd_desc(&desc,
2311 i40e_aqc_opc_set_vsi_promiscuous_modes);
2314 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2315 if (rx_only_promisc &&
2316 (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2317 (hw->aq.api_maj_ver > 1)))
2318 flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2321 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2323 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2324 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2325 (hw->aq.api_maj_ver > 1))
2326 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2328 cmd->seid = CPU_TO_LE16(seid);
2329 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2335 * i40e_aq_set_vsi_multicast_promiscuous
2336 * @hw: pointer to the hw struct
2338 * @set: set multicast promiscuous enable/disable
2339 * @cmd_details: pointer to command details structure or NULL
2341 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2342 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2344 struct i40e_aq_desc desc;
2345 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2346 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2347 enum i40e_status_code status;
2350 i40e_fill_default_direct_cmd_desc(&desc,
2351 i40e_aqc_opc_set_vsi_promiscuous_modes);
2354 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2356 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2358 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2360 cmd->seid = CPU_TO_LE16(seid);
2361 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2367 * i40e_aq_set_vsi_full_promiscuous
2368 * @hw: pointer to the hw struct
2370 * @set: set promiscuous enable/disable
2371 * @cmd_details: pointer to command details structure or NULL
2373 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw,
2375 struct i40e_asq_cmd_details *cmd_details)
2377 struct i40e_aq_desc desc;
2378 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2379 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2380 enum i40e_status_code status;
2383 i40e_fill_default_direct_cmd_desc(&desc,
2384 i40e_aqc_opc_set_vsi_promiscuous_modes);
2387 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST |
2388 I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2389 I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2391 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2393 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST |
2394 I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2395 I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2397 cmd->seid = CPU_TO_LE16(seid);
2398 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2404 * i40e_aq_set_vsi_mc_promisc_on_vlan
2405 * @hw: pointer to the hw struct
2407 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2408 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2409 * @cmd_details: pointer to command details structure or NULL
2411 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2412 u16 seid, bool enable, u16 vid,
2413 struct i40e_asq_cmd_details *cmd_details)
2415 struct i40e_aq_desc desc;
2416 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2417 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2418 enum i40e_status_code status;
2421 i40e_fill_default_direct_cmd_desc(&desc,
2422 i40e_aqc_opc_set_vsi_promiscuous_modes);
2425 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2427 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2428 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2429 cmd->seid = CPU_TO_LE16(seid);
2430 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2432 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2438 * i40e_aq_set_vsi_uc_promisc_on_vlan
2439 * @hw: pointer to the hw struct
2441 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2442 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2443 * @cmd_details: pointer to command details structure or NULL
2445 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2446 u16 seid, bool enable, u16 vid,
2447 struct i40e_asq_cmd_details *cmd_details)
2449 struct i40e_aq_desc desc;
2450 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2451 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2452 enum i40e_status_code status;
2455 i40e_fill_default_direct_cmd_desc(&desc,
2456 i40e_aqc_opc_set_vsi_promiscuous_modes);
2459 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2461 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2462 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2463 cmd->seid = CPU_TO_LE16(seid);
2464 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2466 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2472 * i40e_aq_set_vsi_bc_promisc_on_vlan
2473 * @hw: pointer to the hw struct
2475 * @enable: set broadcast promiscuous enable/disable for a given VLAN
2476 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2477 * @cmd_details: pointer to command details structure or NULL
2479 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2480 u16 seid, bool enable, u16 vid,
2481 struct i40e_asq_cmd_details *cmd_details)
2483 struct i40e_aq_desc desc;
2484 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2485 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2486 enum i40e_status_code status;
2489 i40e_fill_default_direct_cmd_desc(&desc,
2490 i40e_aqc_opc_set_vsi_promiscuous_modes);
2493 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2495 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2496 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2497 cmd->seid = CPU_TO_LE16(seid);
2498 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2500 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2506 * i40e_aq_set_vsi_broadcast
2507 * @hw: pointer to the hw struct
2509 * @set_filter: true to set filter, false to clear filter
2510 * @cmd_details: pointer to command details structure or NULL
2512 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2514 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2515 u16 seid, bool set_filter,
2516 struct i40e_asq_cmd_details *cmd_details)
2518 struct i40e_aq_desc desc;
2519 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2520 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2521 enum i40e_status_code status;
2523 i40e_fill_default_direct_cmd_desc(&desc,
2524 i40e_aqc_opc_set_vsi_promiscuous_modes);
2527 cmd->promiscuous_flags
2528 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2530 cmd->promiscuous_flags
2531 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2533 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2534 cmd->seid = CPU_TO_LE16(seid);
2535 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2541 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2542 * @hw: pointer to the hw struct
2544 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2545 * @cmd_details: pointer to command details structure or NULL
2547 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2548 u16 seid, bool enable,
2549 struct i40e_asq_cmd_details *cmd_details)
2551 struct i40e_aq_desc desc;
2552 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2553 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2554 enum i40e_status_code status;
2557 i40e_fill_default_direct_cmd_desc(&desc,
2558 i40e_aqc_opc_set_vsi_promiscuous_modes);
2560 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2562 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2563 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2564 cmd->seid = CPU_TO_LE16(seid);
2566 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2572 * i40e_get_vsi_params - get VSI configuration info
2573 * @hw: pointer to the hw struct
2574 * @vsi_ctx: pointer to a vsi context struct
2575 * @cmd_details: pointer to command details structure or NULL
2577 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2578 struct i40e_vsi_context *vsi_ctx,
2579 struct i40e_asq_cmd_details *cmd_details)
2581 struct i40e_aq_desc desc;
2582 struct i40e_aqc_add_get_update_vsi *cmd =
2583 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2584 struct i40e_aqc_add_get_update_vsi_completion *resp =
2585 (struct i40e_aqc_add_get_update_vsi_completion *)
2587 enum i40e_status_code status;
2589 UNREFERENCED_1PARAMETER(cmd_details);
2590 i40e_fill_default_direct_cmd_desc(&desc,
2591 i40e_aqc_opc_get_vsi_parameters);
2593 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2595 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2597 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2598 sizeof(vsi_ctx->info), NULL);
2600 if (status != I40E_SUCCESS)
2601 goto aq_get_vsi_params_exit;
2603 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2604 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2605 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2606 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2608 aq_get_vsi_params_exit:
2613 * i40e_aq_update_vsi_params
2614 * @hw: pointer to the hw struct
2615 * @vsi_ctx: pointer to a vsi context struct
2616 * @cmd_details: pointer to command details structure or NULL
2618 * Update a VSI context.
2620 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2621 struct i40e_vsi_context *vsi_ctx,
2622 struct i40e_asq_cmd_details *cmd_details)
2624 struct i40e_aq_desc desc;
2625 struct i40e_aqc_add_get_update_vsi *cmd =
2626 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2627 struct i40e_aqc_add_get_update_vsi_completion *resp =
2628 (struct i40e_aqc_add_get_update_vsi_completion *)
2630 enum i40e_status_code status;
2632 i40e_fill_default_direct_cmd_desc(&desc,
2633 i40e_aqc_opc_update_vsi_parameters);
2634 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2636 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2638 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2639 sizeof(vsi_ctx->info), cmd_details);
2641 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2642 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2648 * i40e_aq_get_switch_config
2649 * @hw: pointer to the hardware structure
2650 * @buf: pointer to the result buffer
2651 * @buf_size: length of input buffer
2652 * @start_seid: seid to start for the report, 0 == beginning
2653 * @cmd_details: pointer to command details structure or NULL
2655 * Fill the buf with switch configuration returned from AdminQ command
2657 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2658 struct i40e_aqc_get_switch_config_resp *buf,
2659 u16 buf_size, u16 *start_seid,
2660 struct i40e_asq_cmd_details *cmd_details)
2662 struct i40e_aq_desc desc;
2663 struct i40e_aqc_switch_seid *scfg =
2664 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2665 enum i40e_status_code status;
2667 i40e_fill_default_direct_cmd_desc(&desc,
2668 i40e_aqc_opc_get_switch_config);
2669 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2670 if (buf_size > I40E_AQ_LARGE_BUF)
2671 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2672 scfg->seid = CPU_TO_LE16(*start_seid);
2674 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2675 *start_seid = LE16_TO_CPU(scfg->seid);
2681 * i40e_aq_set_switch_config
2682 * @hw: pointer to the hardware structure
2683 * @flags: bit flag values to set
2684 * @valid_flags: which bit flags to set
2685 * @cmd_details: pointer to command details structure or NULL
2687 * Set switch configuration bits
2689 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2690 u16 flags, u16 valid_flags,
2691 struct i40e_asq_cmd_details *cmd_details)
2693 struct i40e_aq_desc desc;
2694 struct i40e_aqc_set_switch_config *scfg =
2695 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2696 enum i40e_status_code status;
2698 i40e_fill_default_direct_cmd_desc(&desc,
2699 i40e_aqc_opc_set_switch_config);
2700 scfg->flags = CPU_TO_LE16(flags);
2701 scfg->valid_flags = CPU_TO_LE16(valid_flags);
2702 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
2703 scfg->switch_tag = CPU_TO_LE16(hw->switch_tag);
2704 scfg->first_tag = CPU_TO_LE16(hw->first_tag);
2705 scfg->second_tag = CPU_TO_LE16(hw->second_tag);
2707 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2713 * i40e_aq_get_firmware_version
2714 * @hw: pointer to the hw struct
2715 * @fw_major_version: firmware major version
2716 * @fw_minor_version: firmware minor version
2717 * @fw_build: firmware build number
2718 * @api_major_version: major queue version
2719 * @api_minor_version: minor queue version
2720 * @cmd_details: pointer to command details structure or NULL
2722 * Get the firmware version from the admin queue commands
2724 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2725 u16 *fw_major_version, u16 *fw_minor_version,
2727 u16 *api_major_version, u16 *api_minor_version,
2728 struct i40e_asq_cmd_details *cmd_details)
2730 struct i40e_aq_desc desc;
2731 struct i40e_aqc_get_version *resp =
2732 (struct i40e_aqc_get_version *)&desc.params.raw;
2733 enum i40e_status_code status;
2735 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2737 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2739 if (status == I40E_SUCCESS) {
2740 if (fw_major_version != NULL)
2741 *fw_major_version = LE16_TO_CPU(resp->fw_major);
2742 if (fw_minor_version != NULL)
2743 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2744 if (fw_build != NULL)
2745 *fw_build = LE32_TO_CPU(resp->fw_build);
2746 if (api_major_version != NULL)
2747 *api_major_version = LE16_TO_CPU(resp->api_major);
2748 if (api_minor_version != NULL)
2749 *api_minor_version = LE16_TO_CPU(resp->api_minor);
2751 /* A workaround to fix the API version in SW */
2752 if (api_major_version && api_minor_version &&
2753 fw_major_version && fw_minor_version &&
2754 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2755 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2756 (*fw_major_version > 4)))
2757 *api_minor_version = 2;
2764 * i40e_aq_send_driver_version
2765 * @hw: pointer to the hw struct
2766 * @dv: driver's major, minor version
2767 * @cmd_details: pointer to command details structure or NULL
2769 * Send the driver version to the firmware
2771 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2772 struct i40e_driver_version *dv,
2773 struct i40e_asq_cmd_details *cmd_details)
2775 struct i40e_aq_desc desc;
2776 struct i40e_aqc_driver_version *cmd =
2777 (struct i40e_aqc_driver_version *)&desc.params.raw;
2778 enum i40e_status_code status;
2782 return I40E_ERR_PARAM;
2784 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2786 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2787 cmd->driver_major_ver = dv->major_version;
2788 cmd->driver_minor_ver = dv->minor_version;
2789 cmd->driver_build_ver = dv->build_version;
2790 cmd->driver_subbuild_ver = dv->subbuild_version;
2793 while (len < sizeof(dv->driver_string) &&
2794 (dv->driver_string[len] < 0x80) &&
2795 dv->driver_string[len])
2797 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2804 * i40e_get_link_status - get status of the HW network link
2805 * @hw: pointer to the hw struct
2806 * @link_up: pointer to bool (true/false = linkup/linkdown)
2808 * Variable link_up true if link is up, false if link is down.
2809 * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2811 * Side effect: LinkStatusEvent reporting becomes enabled
2813 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2815 enum i40e_status_code status = I40E_SUCCESS;
2817 if (hw->phy.get_link_info) {
2818 status = i40e_update_link_info(hw);
2820 if (status != I40E_SUCCESS)
2821 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2825 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2831 * i40e_updatelink_status - update status of the HW network link
2832 * @hw: pointer to the hw struct
2834 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2836 struct i40e_aq_get_phy_abilities_resp abilities;
2837 enum i40e_status_code status = I40E_SUCCESS;
2839 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2843 /* extra checking needed to ensure link info to user is timely */
2844 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2845 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2846 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2847 status = i40e_aq_get_phy_capabilities(hw, false, false,
2852 hw->phy.link_info.req_fec_info =
2853 abilities.fec_cfg_curr_mod_ext_info &
2854 (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS);
2856 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2857 sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2864 * i40e_get_link_speed
2865 * @hw: pointer to the hw struct
2867 * Returns the link speed of the adapter.
2869 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2871 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2872 enum i40e_status_code status = I40E_SUCCESS;
2874 if (hw->phy.get_link_info) {
2875 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2877 if (status != I40E_SUCCESS)
2878 goto i40e_link_speed_exit;
2881 speed = hw->phy.link_info.link_speed;
2883 i40e_link_speed_exit:
2888 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2889 * @hw: pointer to the hw struct
2890 * @uplink_seid: the MAC or other gizmo SEID
2891 * @downlink_seid: the VSI SEID
2892 * @enabled_tc: bitmap of TCs to be enabled
2893 * @default_port: true for default port VSI, false for control port
2894 * @veb_seid: pointer to where to put the resulting VEB SEID
2895 * @enable_stats: true to turn on VEB stats
2896 * @cmd_details: pointer to command details structure or NULL
2898 * This asks the FW to add a VEB between the uplink and downlink
2899 * elements. If the uplink SEID is 0, this will be a floating VEB.
2901 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2902 u16 downlink_seid, u8 enabled_tc,
2903 bool default_port, u16 *veb_seid,
2905 struct i40e_asq_cmd_details *cmd_details)
2907 struct i40e_aq_desc desc;
2908 struct i40e_aqc_add_veb *cmd =
2909 (struct i40e_aqc_add_veb *)&desc.params.raw;
2910 struct i40e_aqc_add_veb_completion *resp =
2911 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2912 enum i40e_status_code status;
2915 /* SEIDs need to either both be set or both be 0 for floating VEB */
2916 if (!!uplink_seid != !!downlink_seid)
2917 return I40E_ERR_PARAM;
2919 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2921 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2922 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2923 cmd->enable_tcs = enabled_tc;
2925 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2927 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2929 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2931 /* reverse logic here: set the bitflag to disable the stats */
2933 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2935 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2937 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2939 if (!status && veb_seid)
2940 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2946 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2947 * @hw: pointer to the hw struct
2948 * @veb_seid: the SEID of the VEB to query
2949 * @switch_id: the uplink switch id
2950 * @floating: set to true if the VEB is floating
2951 * @statistic_index: index of the stats counter block for this VEB
2952 * @vebs_used: number of VEB's used by function
2953 * @vebs_free: total VEB's not reserved by any function
2954 * @cmd_details: pointer to command details structure or NULL
2956 * This retrieves the parameters for a particular VEB, specified by
2957 * uplink_seid, and returns them to the caller.
2959 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2960 u16 veb_seid, u16 *switch_id,
2961 bool *floating, u16 *statistic_index,
2962 u16 *vebs_used, u16 *vebs_free,
2963 struct i40e_asq_cmd_details *cmd_details)
2965 struct i40e_aq_desc desc;
2966 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2967 (struct i40e_aqc_get_veb_parameters_completion *)
2969 enum i40e_status_code status;
2972 return I40E_ERR_PARAM;
2974 i40e_fill_default_direct_cmd_desc(&desc,
2975 i40e_aqc_opc_get_veb_parameters);
2976 cmd_resp->seid = CPU_TO_LE16(veb_seid);
2978 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2983 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2984 if (statistic_index)
2985 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2987 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2989 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2991 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2993 if (flags & I40E_AQC_ADD_VEB_FLOATING)
3004 * i40e_aq_add_macvlan
3005 * @hw: pointer to the hw struct
3006 * @seid: VSI for the mac address
3007 * @mv_list: list of macvlans to be added
3008 * @count: length of the list
3009 * @cmd_details: pointer to command details structure or NULL
3011 * Add MAC/VLAN addresses to the HW filtering
3013 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
3014 struct i40e_aqc_add_macvlan_element_data *mv_list,
3015 u16 count, struct i40e_asq_cmd_details *cmd_details)
3017 struct i40e_aq_desc desc;
3018 struct i40e_aqc_macvlan *cmd =
3019 (struct i40e_aqc_macvlan *)&desc.params.raw;
3020 enum i40e_status_code status;
3024 if (count == 0 || !mv_list || !hw)
3025 return I40E_ERR_PARAM;
3027 buf_size = count * sizeof(*mv_list);
3029 /* prep the rest of the request */
3030 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
3031 cmd->num_addresses = CPU_TO_LE16(count);
3032 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3036 for (i = 0; i < count; i++)
3037 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
3039 CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
3041 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3042 if (buf_size > I40E_AQ_LARGE_BUF)
3043 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3045 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3052 * i40e_aq_remove_macvlan
3053 * @hw: pointer to the hw struct
3054 * @seid: VSI for the mac address
3055 * @mv_list: list of macvlans to be removed
3056 * @count: length of the list
3057 * @cmd_details: pointer to command details structure or NULL
3059 * Remove MAC/VLAN addresses from the HW filtering
3061 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
3062 struct i40e_aqc_remove_macvlan_element_data *mv_list,
3063 u16 count, struct i40e_asq_cmd_details *cmd_details)
3065 struct i40e_aq_desc desc;
3066 struct i40e_aqc_macvlan *cmd =
3067 (struct i40e_aqc_macvlan *)&desc.params.raw;
3068 enum i40e_status_code status;
3071 if (count == 0 || !mv_list || !hw)
3072 return I40E_ERR_PARAM;
3074 buf_size = count * sizeof(*mv_list);
3076 /* prep the rest of the request */
3077 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
3078 cmd->num_addresses = CPU_TO_LE16(count);
3079 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3083 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3084 if (buf_size > I40E_AQ_LARGE_BUF)
3085 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3087 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3094 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3095 * @hw: pointer to the hw struct
3096 * @opcode: AQ opcode for add or delete mirror rule
3097 * @sw_seid: Switch SEID (to which rule refers)
3098 * @rule_type: Rule Type (ingress/egress/VLAN)
3099 * @id: Destination VSI SEID or Rule ID
3100 * @count: length of the list
3101 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3102 * @cmd_details: pointer to command details structure or NULL
3103 * @rule_id: Rule ID returned from FW
3104 * @rules_used: Number of rules used in internal switch
3105 * @rules_free: Number of rules free in internal switch
3107 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3108 * VEBs/VEPA elements only
3110 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3111 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3112 u16 count, __le16 *mr_list,
3113 struct i40e_asq_cmd_details *cmd_details,
3114 u16 *rule_id, u16 *rules_used, u16 *rules_free)
3116 struct i40e_aq_desc desc;
3117 struct i40e_aqc_add_delete_mirror_rule *cmd =
3118 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3119 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3120 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3121 enum i40e_status_code status;
3124 buf_size = count * sizeof(*mr_list);
3126 /* prep the rest of the request */
3127 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3128 cmd->seid = CPU_TO_LE16(sw_seid);
3129 cmd->rule_type = CPU_TO_LE16(rule_type &
3130 I40E_AQC_MIRROR_RULE_TYPE_MASK);
3131 cmd->num_entries = CPU_TO_LE16(count);
3132 /* Dest VSI for add, rule_id for delete */
3133 cmd->destination = CPU_TO_LE16(id);
3135 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3137 if (buf_size > I40E_AQ_LARGE_BUF)
3138 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3141 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3143 if (status == I40E_SUCCESS ||
3144 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3146 *rule_id = LE16_TO_CPU(resp->rule_id);
3148 *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3150 *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3156 * i40e_aq_add_mirrorrule - add a mirror rule
3157 * @hw: pointer to the hw struct
3158 * @sw_seid: Switch SEID (to which rule refers)
3159 * @rule_type: Rule Type (ingress/egress/VLAN)
3160 * @dest_vsi: SEID of VSI to which packets will be mirrored
3161 * @count: length of the list
3162 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3163 * @cmd_details: pointer to command details structure or NULL
3164 * @rule_id: Rule ID returned from FW
3165 * @rules_used: Number of rules used in internal switch
3166 * @rules_free: Number of rules free in internal switch
3168 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3170 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3171 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3172 struct i40e_asq_cmd_details *cmd_details,
3173 u16 *rule_id, u16 *rules_used, u16 *rules_free)
3175 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3176 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3177 if (count == 0 || !mr_list)
3178 return I40E_ERR_PARAM;
3181 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3182 rule_type, dest_vsi, count, mr_list,
3183 cmd_details, rule_id, rules_used, rules_free);
3187 * i40e_aq_delete_mirrorrule - delete a mirror rule
3188 * @hw: pointer to the hw struct
3189 * @sw_seid: Switch SEID (to which rule refers)
3190 * @rule_type: Rule Type (ingress/egress/VLAN)
3191 * @count: length of the list
3192 * @rule_id: Rule ID that is returned in the receive desc as part of
3194 * @mr_list: list of mirrored VLAN IDs to be removed
3195 * @cmd_details: pointer to command details structure or NULL
3196 * @rules_used: Number of rules used in internal switch
3197 * @rules_free: Number of rules free in internal switch
3199 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3201 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3202 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3203 struct i40e_asq_cmd_details *cmd_details,
3204 u16 *rules_used, u16 *rules_free)
3206 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3207 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3208 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3209 * mirroring. For other rule_type, count and rule_type should
3212 if (count == 0 || !mr_list)
3213 return I40E_ERR_PARAM;
3216 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3217 rule_type, rule_id, count, mr_list,
3218 cmd_details, NULL, rules_used, rules_free);
3222 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3223 * @hw: pointer to the hw struct
3224 * @seid: VSI for the vlan filters
3225 * @v_list: list of vlan filters to be added
3226 * @count: length of the list
3227 * @cmd_details: pointer to command details structure or NULL
3229 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3230 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3231 u8 count, struct i40e_asq_cmd_details *cmd_details)
3233 struct i40e_aq_desc desc;
3234 struct i40e_aqc_macvlan *cmd =
3235 (struct i40e_aqc_macvlan *)&desc.params.raw;
3236 enum i40e_status_code status;
3239 if (count == 0 || !v_list || !hw)
3240 return I40E_ERR_PARAM;
3242 buf_size = count * sizeof(*v_list);
3244 /* prep the rest of the request */
3245 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3246 cmd->num_addresses = CPU_TO_LE16(count);
3247 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3251 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3252 if (buf_size > I40E_AQ_LARGE_BUF)
3253 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3255 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3262 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3263 * @hw: pointer to the hw struct
3264 * @seid: VSI for the vlan filters
3265 * @v_list: list of macvlans to be removed
3266 * @count: length of the list
3267 * @cmd_details: pointer to command details structure or NULL
3269 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3270 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3271 u8 count, struct i40e_asq_cmd_details *cmd_details)
3273 struct i40e_aq_desc desc;
3274 struct i40e_aqc_macvlan *cmd =
3275 (struct i40e_aqc_macvlan *)&desc.params.raw;
3276 enum i40e_status_code status;
3279 if (count == 0 || !v_list || !hw)
3280 return I40E_ERR_PARAM;
3282 buf_size = count * sizeof(*v_list);
3284 /* prep the rest of the request */
3285 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3286 cmd->num_addresses = CPU_TO_LE16(count);
3287 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3291 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3292 if (buf_size > I40E_AQ_LARGE_BUF)
3293 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3295 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3302 * i40e_aq_send_msg_to_vf
3303 * @hw: pointer to the hardware structure
3304 * @vfid: vf id to send msg
3305 * @v_opcode: opcodes for VF-PF communication
3306 * @v_retval: return error code
3307 * @msg: pointer to the msg buffer
3308 * @msglen: msg length
3309 * @cmd_details: pointer to command details
3313 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3314 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3315 struct i40e_asq_cmd_details *cmd_details)
3317 struct i40e_aq_desc desc;
3318 struct i40e_aqc_pf_vf_message *cmd =
3319 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3320 enum i40e_status_code status;
3322 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3323 cmd->id = CPU_TO_LE32(vfid);
3324 desc.cookie_high = CPU_TO_LE32(v_opcode);
3325 desc.cookie_low = CPU_TO_LE32(v_retval);
3326 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3328 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3330 if (msglen > I40E_AQ_LARGE_BUF)
3331 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3332 desc.datalen = CPU_TO_LE16(msglen);
3334 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3340 * i40e_aq_debug_read_register
3341 * @hw: pointer to the hw struct
3342 * @reg_addr: register address
3343 * @reg_val: register value
3344 * @cmd_details: pointer to command details structure or NULL
3346 * Read the register using the admin queue commands
3348 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3349 u32 reg_addr, u64 *reg_val,
3350 struct i40e_asq_cmd_details *cmd_details)
3352 struct i40e_aq_desc desc;
3353 struct i40e_aqc_debug_reg_read_write *cmd_resp =
3354 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3355 enum i40e_status_code status;
3357 if (reg_val == NULL)
3358 return I40E_ERR_PARAM;
3360 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3362 cmd_resp->address = CPU_TO_LE32(reg_addr);
3364 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3366 if (status == I40E_SUCCESS) {
3367 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3368 (u64)LE32_TO_CPU(cmd_resp->value_low);
3375 * i40e_aq_debug_write_register
3376 * @hw: pointer to the hw struct
3377 * @reg_addr: register address
3378 * @reg_val: register value
3379 * @cmd_details: pointer to command details structure or NULL
3381 * Write to a register using the admin queue commands
3383 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3384 u32 reg_addr, u64 reg_val,
3385 struct i40e_asq_cmd_details *cmd_details)
3387 struct i40e_aq_desc desc;
3388 struct i40e_aqc_debug_reg_read_write *cmd =
3389 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3390 enum i40e_status_code status;
3392 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3394 cmd->address = CPU_TO_LE32(reg_addr);
3395 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3396 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3398 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3404 * i40e_aq_request_resource
3405 * @hw: pointer to the hw struct
3406 * @resource: resource id
3407 * @access: access type
3408 * @sdp_number: resource number
3409 * @timeout: the maximum time in ms that the driver may hold the resource
3410 * @cmd_details: pointer to command details structure or NULL
3412 * requests common resource using the admin queue commands
3414 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3415 enum i40e_aq_resources_ids resource,
3416 enum i40e_aq_resource_access_type access,
3417 u8 sdp_number, u64 *timeout,
3418 struct i40e_asq_cmd_details *cmd_details)
3420 struct i40e_aq_desc desc;
3421 struct i40e_aqc_request_resource *cmd_resp =
3422 (struct i40e_aqc_request_resource *)&desc.params.raw;
3423 enum i40e_status_code status;
3425 DEBUGFUNC("i40e_aq_request_resource");
3427 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3429 cmd_resp->resource_id = CPU_TO_LE16(resource);
3430 cmd_resp->access_type = CPU_TO_LE16(access);
3431 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3433 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3434 /* The completion specifies the maximum time in ms that the driver
3435 * may hold the resource in the Timeout field.
3436 * If the resource is held by someone else, the command completes with
3437 * busy return value and the timeout field indicates the maximum time
3438 * the current owner of the resource has to free it.
3440 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3441 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3447 * i40e_aq_release_resource
3448 * @hw: pointer to the hw struct
3449 * @resource: resource id
3450 * @sdp_number: resource number
3451 * @cmd_details: pointer to command details structure or NULL
3453 * release common resource using the admin queue commands
3455 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3456 enum i40e_aq_resources_ids resource,
3458 struct i40e_asq_cmd_details *cmd_details)
3460 struct i40e_aq_desc desc;
3461 struct i40e_aqc_request_resource *cmd =
3462 (struct i40e_aqc_request_resource *)&desc.params.raw;
3463 enum i40e_status_code status;
3465 DEBUGFUNC("i40e_aq_release_resource");
3467 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3469 cmd->resource_id = CPU_TO_LE16(resource);
3470 cmd->resource_number = CPU_TO_LE32(sdp_number);
3472 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3479 * @hw: pointer to the hw struct
3480 * @module_pointer: module pointer location in words from the NVM beginning
3481 * @offset: byte offset from the module beginning
3482 * @length: length of the section to be read (in bytes from the offset)
3483 * @data: command buffer (size [bytes] = length)
3484 * @last_command: tells if this is the last command in a series
3485 * @cmd_details: pointer to command details structure or NULL
3487 * Read the NVM using the admin queue commands
3489 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3490 u32 offset, u16 length, void *data,
3492 struct i40e_asq_cmd_details *cmd_details)
3494 struct i40e_aq_desc desc;
3495 struct i40e_aqc_nvm_update *cmd =
3496 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3497 enum i40e_status_code status;
3499 DEBUGFUNC("i40e_aq_read_nvm");
3501 /* In offset the highest byte must be zeroed. */
3502 if (offset & 0xFF000000) {
3503 status = I40E_ERR_PARAM;
3504 goto i40e_aq_read_nvm_exit;
3507 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3509 /* If this is the last command in a series, set the proper flag. */
3511 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3512 cmd->module_pointer = module_pointer;
3513 cmd->offset = CPU_TO_LE32(offset);
3514 cmd->length = CPU_TO_LE16(length);
3516 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3517 if (length > I40E_AQ_LARGE_BUF)
3518 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3520 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3522 i40e_aq_read_nvm_exit:
3527 * i40e_aq_read_nvm_config - read an nvm config block
3528 * @hw: pointer to the hw struct
3529 * @cmd_flags: NVM access admin command bits
3530 * @field_id: field or feature id
3531 * @data: buffer for result
3532 * @buf_size: buffer size
3533 * @element_count: pointer to count of elements read by FW
3534 * @cmd_details: pointer to command details structure or NULL
3536 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3537 u8 cmd_flags, u32 field_id, void *data,
3538 u16 buf_size, u16 *element_count,
3539 struct i40e_asq_cmd_details *cmd_details)
3541 struct i40e_aq_desc desc;
3542 struct i40e_aqc_nvm_config_read *cmd =
3543 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3544 enum i40e_status_code status;
3546 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3547 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3548 if (buf_size > I40E_AQ_LARGE_BUF)
3549 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3551 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3552 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3553 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3554 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3556 cmd->element_id_msw = 0;
3558 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3560 if (!status && element_count)
3561 *element_count = LE16_TO_CPU(cmd->element_count);
3567 * i40e_aq_write_nvm_config - write an nvm config block
3568 * @hw: pointer to the hw struct
3569 * @cmd_flags: NVM access admin command bits
3570 * @data: buffer for result
3571 * @buf_size: buffer size
3572 * @element_count: count of elements to be written
3573 * @cmd_details: pointer to command details structure or NULL
3575 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3576 u8 cmd_flags, void *data, u16 buf_size,
3578 struct i40e_asq_cmd_details *cmd_details)
3580 struct i40e_aq_desc desc;
3581 struct i40e_aqc_nvm_config_write *cmd =
3582 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3583 enum i40e_status_code status;
3585 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3586 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3587 if (buf_size > I40E_AQ_LARGE_BUF)
3588 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3590 cmd->element_count = CPU_TO_LE16(element_count);
3591 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3592 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3598 * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3599 * @hw: pointer to the hw struct
3600 * @buff: buffer for result
3601 * @buff_size: buffer size
3602 * @cmd_details: pointer to command details structure or NULL
3604 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3605 void *buff, u16 buff_size,
3606 struct i40e_asq_cmd_details *cmd_details)
3608 struct i40e_aq_desc desc;
3609 enum i40e_status_code status;
3611 UNREFERENCED_2PARAMETER(buff, buff_size);
3613 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3614 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3615 if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3616 status = I40E_ERR_NOT_IMPLEMENTED;
3623 * @hw: pointer to the hw struct
3624 * @module_pointer: module pointer location in words from the NVM beginning
3625 * @offset: offset in the module (expressed in 4 KB from module's beginning)
3626 * @length: length of the section to be erased (expressed in 4 KB)
3627 * @last_command: tells if this is the last command in a series
3628 * @cmd_details: pointer to command details structure or NULL
3630 * Erase the NVM sector using the admin queue commands
3632 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3633 u32 offset, u16 length, bool last_command,
3634 struct i40e_asq_cmd_details *cmd_details)
3636 struct i40e_aq_desc desc;
3637 struct i40e_aqc_nvm_update *cmd =
3638 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3639 enum i40e_status_code status;
3641 DEBUGFUNC("i40e_aq_erase_nvm");
3643 /* In offset the highest byte must be zeroed. */
3644 if (offset & 0xFF000000) {
3645 status = I40E_ERR_PARAM;
3646 goto i40e_aq_erase_nvm_exit;
3649 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3651 /* If this is the last command in a series, set the proper flag. */
3653 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3654 cmd->module_pointer = module_pointer;
3655 cmd->offset = CPU_TO_LE32(offset);
3656 cmd->length = CPU_TO_LE16(length);
3658 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3660 i40e_aq_erase_nvm_exit:
3665 * i40e_parse_discover_capabilities
3666 * @hw: pointer to the hw struct
3667 * @buff: pointer to a buffer containing device/function capability records
3668 * @cap_count: number of capability records in the list
3669 * @list_type_opc: type of capabilities list to parse
3671 * Parse the device/function capabilities list.
3673 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3675 enum i40e_admin_queue_opc list_type_opc)
3677 struct i40e_aqc_list_capabilities_element_resp *cap;
3678 u32 valid_functions, num_functions;
3679 u32 number, logical_id, phys_id;
3680 struct i40e_hw_capabilities *p;
3681 enum i40e_status_code status;
3682 u16 id, ocp_cfg_word0;
3686 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3688 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3689 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3690 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3691 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3695 for (i = 0; i < cap_count; i++, cap++) {
3696 id = LE16_TO_CPU(cap->id);
3697 number = LE32_TO_CPU(cap->number);
3698 logical_id = LE32_TO_CPU(cap->logical_id);
3699 phys_id = LE32_TO_CPU(cap->phys_id);
3700 major_rev = cap->major_rev;
3703 case I40E_AQ_CAP_ID_SWITCH_MODE:
3704 p->switch_mode = number;
3705 i40e_debug(hw, I40E_DEBUG_INIT,
3706 "HW Capability: Switch mode = %d\n",
3709 case I40E_AQ_CAP_ID_MNG_MODE:
3710 p->management_mode = number;
3711 if (major_rev > 1) {
3712 p->mng_protocols_over_mctp = logical_id;
3713 i40e_debug(hw, I40E_DEBUG_INIT,
3714 "HW Capability: Protocols over MCTP = %d\n",
3715 p->mng_protocols_over_mctp);
3717 p->mng_protocols_over_mctp = 0;
3719 i40e_debug(hw, I40E_DEBUG_INIT,
3720 "HW Capability: Management Mode = %d\n",
3721 p->management_mode);
3723 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3724 p->npar_enable = number;
3725 i40e_debug(hw, I40E_DEBUG_INIT,
3726 "HW Capability: NPAR enable = %d\n",
3729 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3731 i40e_debug(hw, I40E_DEBUG_INIT,
3732 "HW Capability: OS2BMC = %d\n", p->os2bmc);
3734 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3735 p->valid_functions = number;
3736 i40e_debug(hw, I40E_DEBUG_INIT,
3737 "HW Capability: Valid Functions = %d\n",
3738 p->valid_functions);
3740 case I40E_AQ_CAP_ID_SRIOV:
3742 p->sr_iov_1_1 = true;
3743 i40e_debug(hw, I40E_DEBUG_INIT,
3744 "HW Capability: SR-IOV = %d\n",
3747 case I40E_AQ_CAP_ID_VF:
3748 p->num_vfs = number;
3749 p->vf_base_id = logical_id;
3750 i40e_debug(hw, I40E_DEBUG_INIT,
3751 "HW Capability: VF count = %d\n",
3753 i40e_debug(hw, I40E_DEBUG_INIT,
3754 "HW Capability: VF base_id = %d\n",
3757 case I40E_AQ_CAP_ID_VMDQ:
3760 i40e_debug(hw, I40E_DEBUG_INIT,
3761 "HW Capability: VMDQ = %d\n", p->vmdq);
3763 case I40E_AQ_CAP_ID_8021QBG:
3765 p->evb_802_1_qbg = true;
3766 i40e_debug(hw, I40E_DEBUG_INIT,
3767 "HW Capability: 802.1Qbg = %d\n", number);
3769 case I40E_AQ_CAP_ID_8021QBR:
3771 p->evb_802_1_qbh = true;
3772 i40e_debug(hw, I40E_DEBUG_INIT,
3773 "HW Capability: 802.1Qbh = %d\n", number);
3775 case I40E_AQ_CAP_ID_VSI:
3776 p->num_vsis = number;
3777 i40e_debug(hw, I40E_DEBUG_INIT,
3778 "HW Capability: VSI count = %d\n",
3781 case I40E_AQ_CAP_ID_DCB:
3784 p->enabled_tcmap = logical_id;
3787 i40e_debug(hw, I40E_DEBUG_INIT,
3788 "HW Capability: DCB = %d\n", p->dcb);
3789 i40e_debug(hw, I40E_DEBUG_INIT,
3790 "HW Capability: TC Mapping = %d\n",
3792 i40e_debug(hw, I40E_DEBUG_INIT,
3793 "HW Capability: TC Max = %d\n", p->maxtc);
3795 case I40E_AQ_CAP_ID_FCOE:
3798 i40e_debug(hw, I40E_DEBUG_INIT,
3799 "HW Capability: FCOE = %d\n", p->fcoe);
3801 case I40E_AQ_CAP_ID_ISCSI:
3804 i40e_debug(hw, I40E_DEBUG_INIT,
3805 "HW Capability: iSCSI = %d\n", p->iscsi);
3807 case I40E_AQ_CAP_ID_RSS:
3809 p->rss_table_size = number;
3810 p->rss_table_entry_width = logical_id;
3811 i40e_debug(hw, I40E_DEBUG_INIT,
3812 "HW Capability: RSS = %d\n", p->rss);
3813 i40e_debug(hw, I40E_DEBUG_INIT,
3814 "HW Capability: RSS table size = %d\n",
3816 i40e_debug(hw, I40E_DEBUG_INIT,
3817 "HW Capability: RSS table width = %d\n",
3818 p->rss_table_entry_width);
3820 case I40E_AQ_CAP_ID_RXQ:
3821 p->num_rx_qp = number;
3822 p->base_queue = phys_id;
3823 i40e_debug(hw, I40E_DEBUG_INIT,
3824 "HW Capability: Rx QP = %d\n", number);
3825 i40e_debug(hw, I40E_DEBUG_INIT,
3826 "HW Capability: base_queue = %d\n",
3829 case I40E_AQ_CAP_ID_TXQ:
3830 p->num_tx_qp = number;
3831 p->base_queue = phys_id;
3832 i40e_debug(hw, I40E_DEBUG_INIT,
3833 "HW Capability: Tx QP = %d\n", number);
3834 i40e_debug(hw, I40E_DEBUG_INIT,
3835 "HW Capability: base_queue = %d\n",
3838 case I40E_AQ_CAP_ID_MSIX:
3839 p->num_msix_vectors = number;
3840 i40e_debug(hw, I40E_DEBUG_INIT,
3841 "HW Capability: MSIX vector count = %d\n",
3842 p->num_msix_vectors);
3844 case I40E_AQ_CAP_ID_VF_MSIX:
3845 p->num_msix_vectors_vf = number;
3846 i40e_debug(hw, I40E_DEBUG_INIT,
3847 "HW Capability: MSIX VF vector count = %d\n",
3848 p->num_msix_vectors_vf);
3850 case I40E_AQ_CAP_ID_FLEX10:
3851 if (major_rev == 1) {
3853 p->flex10_enable = true;
3854 p->flex10_capable = true;
3857 /* Capability revision >= 2 */
3859 p->flex10_enable = true;
3861 p->flex10_capable = true;
3863 p->flex10_mode = logical_id;
3864 p->flex10_status = phys_id;
3865 i40e_debug(hw, I40E_DEBUG_INIT,
3866 "HW Capability: Flex10 mode = %d\n",
3868 i40e_debug(hw, I40E_DEBUG_INIT,
3869 "HW Capability: Flex10 status = %d\n",
3872 case I40E_AQ_CAP_ID_CEM:
3875 i40e_debug(hw, I40E_DEBUG_INIT,
3876 "HW Capability: CEM = %d\n", p->mgmt_cem);
3878 case I40E_AQ_CAP_ID_IWARP:
3881 i40e_debug(hw, I40E_DEBUG_INIT,
3882 "HW Capability: iWARP = %d\n", p->iwarp);
3884 case I40E_AQ_CAP_ID_LED:
3885 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3886 p->led[phys_id] = true;
3887 i40e_debug(hw, I40E_DEBUG_INIT,
3888 "HW Capability: LED - PIN %d\n", phys_id);
3890 case I40E_AQ_CAP_ID_SDP:
3891 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3892 p->sdp[phys_id] = true;
3893 i40e_debug(hw, I40E_DEBUG_INIT,
3894 "HW Capability: SDP - PIN %d\n", phys_id);
3896 case I40E_AQ_CAP_ID_MDIO:
3898 p->mdio_port_num = phys_id;
3899 p->mdio_port_mode = logical_id;
3901 i40e_debug(hw, I40E_DEBUG_INIT,
3902 "HW Capability: MDIO port number = %d\n",
3904 i40e_debug(hw, I40E_DEBUG_INIT,
3905 "HW Capability: MDIO port mode = %d\n",
3908 case I40E_AQ_CAP_ID_1588:
3910 p->ieee_1588 = true;
3911 i40e_debug(hw, I40E_DEBUG_INIT,
3912 "HW Capability: IEEE 1588 = %d\n",
3915 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3917 p->fd_filters_guaranteed = number;
3918 p->fd_filters_best_effort = logical_id;
3919 i40e_debug(hw, I40E_DEBUG_INIT,
3920 "HW Capability: Flow Director = 1\n");
3921 i40e_debug(hw, I40E_DEBUG_INIT,
3922 "HW Capability: Guaranteed FD filters = %d\n",
3923 p->fd_filters_guaranteed);
3925 case I40E_AQ_CAP_ID_WSR_PROT:
3926 p->wr_csr_prot = (u64)number;
3927 p->wr_csr_prot |= (u64)logical_id << 32;
3928 i40e_debug(hw, I40E_DEBUG_INIT,
3929 "HW Capability: wr_csr_prot = 0x%llX\n\n",
3930 (p->wr_csr_prot & 0xffff));
3932 case I40E_AQ_CAP_ID_NVM_MGMT:
3933 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3934 p->sec_rev_disabled = true;
3935 if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3936 p->update_disabled = true;
3938 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3939 hw->num_wol_proxy_filters = (u16)number;
3940 hw->wol_proxy_vsi_seid = (u16)logical_id;
3941 p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3942 if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3943 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3945 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3946 p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3947 i40e_debug(hw, I40E_DEBUG_INIT,
3948 "HW Capability: WOL proxy filters = %d\n",
3949 hw->num_wol_proxy_filters);
3957 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3959 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3962 /* count the enabled ports (aka the "not disabled" ports) */
3964 for (i = 0; i < 4; i++) {
3965 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3968 /* use AQ read to get the physical register offset instead
3969 * of the port relative offset
3971 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3972 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3976 /* OCP cards case: if a mezz is removed the ethernet port is at
3977 * disabled state in PRTGEN_CNF register. Additional NVM read is
3978 * needed in order to check if we are dealing with OCP card.
3979 * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting
3980 * physical ports results in wrong partition id calculation and thus
3981 * not supporting WoL.
3983 if (hw->mac.type == I40E_MAC_X722) {
3984 if (i40e_acquire_nvm(hw, I40E_RESOURCE_READ) == I40E_SUCCESS) {
3985 status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR,
3986 2 * I40E_SR_OCP_CFG_WORD0,
3987 sizeof(ocp_cfg_word0),
3988 &ocp_cfg_word0, true, NULL);
3989 if (status == I40E_SUCCESS &&
3990 (ocp_cfg_word0 & I40E_SR_OCP_ENABLED))
3992 i40e_release_nvm(hw);
3996 valid_functions = p->valid_functions;
3998 while (valid_functions) {
3999 if (valid_functions & 1)
4001 valid_functions >>= 1;
4004 /* partition id is 1-based, and functions are evenly spread
4005 * across the ports as partitions
4007 if (hw->num_ports != 0) {
4008 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
4009 hw->num_partitions = num_functions / hw->num_ports;
4012 /* additional HW specific goodies that might
4013 * someday be HW version specific
4015 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
4019 * i40e_aq_discover_capabilities
4020 * @hw: pointer to the hw struct
4021 * @buff: a virtual buffer to hold the capabilities
4022 * @buff_size: Size of the virtual buffer
4023 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
4024 * @list_type_opc: capabilities type to discover - pass in the command opcode
4025 * @cmd_details: pointer to command details structure or NULL
4027 * Get the device capabilities descriptions from the firmware
4029 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
4030 void *buff, u16 buff_size, u16 *data_size,
4031 enum i40e_admin_queue_opc list_type_opc,
4032 struct i40e_asq_cmd_details *cmd_details)
4034 struct i40e_aqc_list_capabilites *cmd;
4035 struct i40e_aq_desc desc;
4036 enum i40e_status_code status = I40E_SUCCESS;
4038 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
4040 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
4041 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
4042 status = I40E_ERR_PARAM;
4046 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
4048 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4049 if (buff_size > I40E_AQ_LARGE_BUF)
4050 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4052 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4053 *data_size = LE16_TO_CPU(desc.datalen);
4058 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
4066 * i40e_aq_update_nvm
4067 * @hw: pointer to the hw struct
4068 * @module_pointer: module pointer location in words from the NVM beginning
4069 * @offset: byte offset from the module beginning
4070 * @length: length of the section to be written (in bytes from the offset)
4071 * @data: command buffer (size [bytes] = length)
4072 * @last_command: tells if this is the last command in a series
4073 * @preservation_flags: Preservation mode flags
4074 * @cmd_details: pointer to command details structure or NULL
4076 * Update the NVM using the admin queue commands
4078 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
4079 u32 offset, u16 length, void *data,
4080 bool last_command, u8 preservation_flags,
4081 struct i40e_asq_cmd_details *cmd_details)
4083 struct i40e_aq_desc desc;
4084 struct i40e_aqc_nvm_update *cmd =
4085 (struct i40e_aqc_nvm_update *)&desc.params.raw;
4086 enum i40e_status_code status;
4088 DEBUGFUNC("i40e_aq_update_nvm");
4090 /* In offset the highest byte must be zeroed. */
4091 if (offset & 0xFF000000) {
4092 status = I40E_ERR_PARAM;
4093 goto i40e_aq_update_nvm_exit;
4096 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4098 /* If this is the last command in a series, set the proper flag. */
4100 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
4101 if (hw->mac.type == I40E_MAC_X722) {
4102 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED)
4103 cmd->command_flags |=
4104 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED <<
4105 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4106 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL)
4107 cmd->command_flags |=
4108 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL <<
4109 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4111 cmd->module_pointer = module_pointer;
4112 cmd->offset = CPU_TO_LE32(offset);
4113 cmd->length = CPU_TO_LE16(length);
4115 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4116 if (length > I40E_AQ_LARGE_BUF)
4117 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4119 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
4121 i40e_aq_update_nvm_exit:
4126 * i40e_aq_nvm_progress
4127 * @hw: pointer to the hw struct
4128 * @progress: pointer to progress returned from AQ
4129 * @cmd_details: pointer to command details structure or NULL
4131 * Gets progress of flash rearrangement process
4133 enum i40e_status_code i40e_aq_nvm_progress(struct i40e_hw *hw, u8 *progress,
4134 struct i40e_asq_cmd_details *cmd_details)
4136 enum i40e_status_code status;
4137 struct i40e_aq_desc desc;
4139 DEBUGFUNC("i40e_aq_nvm_progress");
4141 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_progress);
4142 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4143 *progress = desc.params.raw[0];
4148 * i40e_aq_get_lldp_mib
4149 * @hw: pointer to the hw struct
4150 * @bridge_type: type of bridge requested
4151 * @mib_type: Local, Remote or both Local and Remote MIBs
4152 * @buff: pointer to a user supplied buffer to store the MIB block
4153 * @buff_size: size of the buffer (in bytes)
4154 * @local_len : length of the returned Local LLDP MIB
4155 * @remote_len: length of the returned Remote LLDP MIB
4156 * @cmd_details: pointer to command details structure or NULL
4158 * Requests the complete LLDP MIB (entire packet).
4160 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4161 u8 mib_type, void *buff, u16 buff_size,
4162 u16 *local_len, u16 *remote_len,
4163 struct i40e_asq_cmd_details *cmd_details)
4165 struct i40e_aq_desc desc;
4166 struct i40e_aqc_lldp_get_mib *cmd =
4167 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4168 struct i40e_aqc_lldp_get_mib *resp =
4169 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4170 enum i40e_status_code status;
4172 if (buff_size == 0 || !buff)
4173 return I40E_ERR_PARAM;
4175 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4176 /* Indirect Command */
4177 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4179 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4180 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4181 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4183 desc.datalen = CPU_TO_LE16(buff_size);
4185 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4186 if (buff_size > I40E_AQ_LARGE_BUF)
4187 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4189 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4191 if (local_len != NULL)
4192 *local_len = LE16_TO_CPU(resp->local_len);
4193 if (remote_len != NULL)
4194 *remote_len = LE16_TO_CPU(resp->remote_len);
4201 * i40e_aq_set_lldp_mib - Set the LLDP MIB
4202 * @hw: pointer to the hw struct
4203 * @mib_type: Local, Remote or both Local and Remote MIBs
4204 * @buff: pointer to a user supplied buffer to store the MIB block
4205 * @buff_size: size of the buffer (in bytes)
4206 * @cmd_details: pointer to command details structure or NULL
4210 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4211 u8 mib_type, void *buff, u16 buff_size,
4212 struct i40e_asq_cmd_details *cmd_details)
4214 struct i40e_aq_desc desc;
4215 struct i40e_aqc_lldp_set_local_mib *cmd =
4216 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4217 enum i40e_status_code status;
4219 if (buff_size == 0 || !buff)
4220 return I40E_ERR_PARAM;
4222 i40e_fill_default_direct_cmd_desc(&desc,
4223 i40e_aqc_opc_lldp_set_local_mib);
4224 /* Indirect Command */
4225 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4226 if (buff_size > I40E_AQ_LARGE_BUF)
4227 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4228 desc.datalen = CPU_TO_LE16(buff_size);
4230 cmd->type = mib_type;
4231 cmd->length = CPU_TO_LE16(buff_size);
4232 cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4233 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4235 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4240 * i40e_aq_cfg_lldp_mib_change_event
4241 * @hw: pointer to the hw struct
4242 * @enable_update: Enable or Disable event posting
4243 * @cmd_details: pointer to command details structure or NULL
4245 * Enable or Disable posting of an event on ARQ when LLDP MIB
4246 * associated with the interface changes
4248 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4250 struct i40e_asq_cmd_details *cmd_details)
4252 struct i40e_aq_desc desc;
4253 struct i40e_aqc_lldp_update_mib *cmd =
4254 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4255 enum i40e_status_code status;
4257 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4260 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4262 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4268 * i40e_aq_add_lldp_tlv
4269 * @hw: pointer to the hw struct
4270 * @bridge_type: type of bridge
4271 * @buff: buffer with TLV to add
4272 * @buff_size: length of the buffer
4273 * @tlv_len: length of the TLV to be added
4274 * @mib_len: length of the LLDP MIB returned in response
4275 * @cmd_details: pointer to command details structure or NULL
4277 * Add the specified TLV to LLDP Local MIB for the given bridge type,
4278 * it is responsibility of the caller to make sure that the TLV is not
4279 * already present in the LLDPDU.
4280 * In return firmware will write the complete LLDP MIB with the newly
4281 * added TLV in the response buffer.
4283 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4284 void *buff, u16 buff_size, u16 tlv_len,
4286 struct i40e_asq_cmd_details *cmd_details)
4288 struct i40e_aq_desc desc;
4289 struct i40e_aqc_lldp_add_tlv *cmd =
4290 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4291 enum i40e_status_code status;
4293 if (buff_size == 0 || !buff || tlv_len == 0)
4294 return I40E_ERR_PARAM;
4296 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4298 /* Indirect Command */
4299 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4300 if (buff_size > I40E_AQ_LARGE_BUF)
4301 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4302 desc.datalen = CPU_TO_LE16(buff_size);
4304 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4305 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4306 cmd->len = CPU_TO_LE16(tlv_len);
4308 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4310 if (mib_len != NULL)
4311 *mib_len = LE16_TO_CPU(desc.datalen);
4318 * i40e_aq_update_lldp_tlv
4319 * @hw: pointer to the hw struct
4320 * @bridge_type: type of bridge
4321 * @buff: buffer with TLV to update
4322 * @buff_size: size of the buffer holding original and updated TLVs
4323 * @old_len: Length of the Original TLV
4324 * @new_len: Length of the Updated TLV
4325 * @offset: offset of the updated TLV in the buff
4326 * @mib_len: length of the returned LLDP MIB
4327 * @cmd_details: pointer to command details structure or NULL
4329 * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4330 * Firmware will place the complete LLDP MIB in response buffer with the
4333 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4334 u8 bridge_type, void *buff, u16 buff_size,
4335 u16 old_len, u16 new_len, u16 offset,
4337 struct i40e_asq_cmd_details *cmd_details)
4339 struct i40e_aq_desc desc;
4340 struct i40e_aqc_lldp_update_tlv *cmd =
4341 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4342 enum i40e_status_code status;
4344 if (buff_size == 0 || !buff || offset == 0 ||
4345 old_len == 0 || new_len == 0)
4346 return I40E_ERR_PARAM;
4348 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4350 /* Indirect Command */
4351 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4352 if (buff_size > I40E_AQ_LARGE_BUF)
4353 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4354 desc.datalen = CPU_TO_LE16(buff_size);
4356 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4357 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4358 cmd->old_len = CPU_TO_LE16(old_len);
4359 cmd->new_offset = CPU_TO_LE16(offset);
4360 cmd->new_len = CPU_TO_LE16(new_len);
4362 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4364 if (mib_len != NULL)
4365 *mib_len = LE16_TO_CPU(desc.datalen);
4372 * i40e_aq_delete_lldp_tlv
4373 * @hw: pointer to the hw struct
4374 * @bridge_type: type of bridge
4375 * @buff: pointer to a user supplied buffer that has the TLV
4376 * @buff_size: length of the buffer
4377 * @tlv_len: length of the TLV to be deleted
4378 * @mib_len: length of the returned LLDP MIB
4379 * @cmd_details: pointer to command details structure or NULL
4381 * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4382 * The firmware places the entire LLDP MIB in the response buffer.
4384 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4385 u8 bridge_type, void *buff, u16 buff_size,
4386 u16 tlv_len, u16 *mib_len,
4387 struct i40e_asq_cmd_details *cmd_details)
4389 struct i40e_aq_desc desc;
4390 struct i40e_aqc_lldp_add_tlv *cmd =
4391 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4392 enum i40e_status_code status;
4394 if (buff_size == 0 || !buff)
4395 return I40E_ERR_PARAM;
4397 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4399 /* Indirect Command */
4400 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4401 if (buff_size > I40E_AQ_LARGE_BUF)
4402 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4403 desc.datalen = CPU_TO_LE16(buff_size);
4404 cmd->len = CPU_TO_LE16(tlv_len);
4405 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4406 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4408 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4410 if (mib_len != NULL)
4411 *mib_len = LE16_TO_CPU(desc.datalen);
4419 * @hw: pointer to the hw struct
4420 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4421 * @cmd_details: pointer to command details structure or NULL
4423 * Stop or Shutdown the embedded LLDP Agent
4425 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4426 struct i40e_asq_cmd_details *cmd_details)
4428 struct i40e_aq_desc desc;
4429 struct i40e_aqc_lldp_stop *cmd =
4430 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4431 enum i40e_status_code status;
4433 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4436 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4438 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4444 * i40e_aq_start_lldp
4445 * @hw: pointer to the hw struct
4446 * @cmd_details: pointer to command details structure or NULL
4448 * Start the embedded LLDP Agent on all ports.
4450 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4451 struct i40e_asq_cmd_details *cmd_details)
4453 struct i40e_aq_desc desc;
4454 struct i40e_aqc_lldp_start *cmd =
4455 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4456 enum i40e_status_code status;
4458 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4460 cmd->command = I40E_AQ_LLDP_AGENT_START;
4461 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4467 * i40e_aq_set_dcb_parameters
4468 * @hw: pointer to the hw struct
4469 * @cmd_details: pointer to command details structure or NULL
4470 * @dcb_enable: True if DCB configuration needs to be applied
4473 enum i40e_status_code
4474 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable,
4475 struct i40e_asq_cmd_details *cmd_details)
4477 struct i40e_aq_desc desc;
4478 struct i40e_aqc_set_dcb_parameters *cmd =
4479 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw;
4480 enum i40e_status_code status;
4482 i40e_fill_default_direct_cmd_desc(&desc,
4483 i40e_aqc_opc_set_dcb_parameters);
4486 cmd->valid_flags = I40E_DCB_VALID;
4487 cmd->command = I40E_AQ_DCB_SET_AGENT;
4489 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4495 * i40e_aq_get_cee_dcb_config
4496 * @hw: pointer to the hw struct
4497 * @buff: response buffer that stores CEE operational configuration
4498 * @buff_size: size of the buffer passed
4499 * @cmd_details: pointer to command details structure or NULL
4501 * Get CEE DCBX mode operational configuration from firmware
4503 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4504 void *buff, u16 buff_size,
4505 struct i40e_asq_cmd_details *cmd_details)
4507 struct i40e_aq_desc desc;
4508 enum i40e_status_code status;
4510 if (buff_size == 0 || !buff)
4511 return I40E_ERR_PARAM;
4513 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4515 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4516 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4523 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4524 * @hw: pointer to the hw struct
4525 * @start_agent: True if DCBx Agent needs to be Started
4526 * False if DCBx Agent needs to be Stopped
4527 * @cmd_details: pointer to command details structure or NULL
4529 * Start/Stop the embedded dcbx Agent
4531 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4533 struct i40e_asq_cmd_details *cmd_details)
4535 struct i40e_aq_desc desc;
4536 struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4537 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4539 enum i40e_status_code status;
4541 i40e_fill_default_direct_cmd_desc(&desc,
4542 i40e_aqc_opc_lldp_stop_start_spec_agent);
4545 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4547 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4553 * i40e_aq_add_udp_tunnel
4554 * @hw: pointer to the hw struct
4555 * @udp_port: the UDP port to add in Host byte order
4556 * @protocol_index: protocol index type
4557 * @filter_index: pointer to filter index
4558 * @cmd_details: pointer to command details structure or NULL
4560 * Note: Firmware expects the udp_port value to be in Little Endian format,
4561 * and this function will call CPU_TO_LE16 to convert from Host byte order to
4562 * Little Endian order.
4564 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4565 u16 udp_port, u8 protocol_index,
4567 struct i40e_asq_cmd_details *cmd_details)
4569 struct i40e_aq_desc desc;
4570 struct i40e_aqc_add_udp_tunnel *cmd =
4571 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4572 struct i40e_aqc_del_udp_tunnel_completion *resp =
4573 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4574 enum i40e_status_code status;
4576 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4578 cmd->udp_port = CPU_TO_LE16(udp_port);
4579 cmd->protocol_type = protocol_index;
4581 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4583 if (!status && filter_index)
4584 *filter_index = resp->index;
4590 * i40e_aq_del_udp_tunnel
4591 * @hw: pointer to the hw struct
4592 * @index: filter index
4593 * @cmd_details: pointer to command details structure or NULL
4595 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4596 struct i40e_asq_cmd_details *cmd_details)
4598 struct i40e_aq_desc desc;
4599 struct i40e_aqc_remove_udp_tunnel *cmd =
4600 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4601 enum i40e_status_code status;
4603 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4607 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4613 * i40e_aq_get_switch_resource_alloc (0x0204)
4614 * @hw: pointer to the hw struct
4615 * @num_entries: pointer to u8 to store the number of resource entries returned
4616 * @buf: pointer to a user supplied buffer. This buffer must be large enough
4617 * to store the resource information for all resource types. Each
4618 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
4619 * @count: size, in bytes, of the buffer provided
4620 * @cmd_details: pointer to command details structure or NULL
4622 * Query the resources allocated to a function.
4624 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4626 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4628 struct i40e_asq_cmd_details *cmd_details)
4630 struct i40e_aq_desc desc;
4631 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4632 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4633 enum i40e_status_code status;
4634 u16 length = count * sizeof(*buf);
4636 i40e_fill_default_direct_cmd_desc(&desc,
4637 i40e_aqc_opc_get_switch_resource_alloc);
4639 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4640 if (length > I40E_AQ_LARGE_BUF)
4641 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4643 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4645 if (!status && num_entries)
4646 *num_entries = cmd_resp->num_entries;
4652 * i40e_aq_delete_element - Delete switch element
4653 * @hw: pointer to the hw struct
4654 * @seid: the SEID to delete from the switch
4655 * @cmd_details: pointer to command details structure or NULL
4657 * This deletes a switch element from the switch.
4659 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4660 struct i40e_asq_cmd_details *cmd_details)
4662 struct i40e_aq_desc desc;
4663 struct i40e_aqc_switch_seid *cmd =
4664 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4665 enum i40e_status_code status;
4668 return I40E_ERR_PARAM;
4670 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4672 cmd->seid = CPU_TO_LE16(seid);
4674 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4680 * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4681 * @hw: pointer to the hw struct
4682 * @flags: component flags
4683 * @mac_seid: uplink seid (MAC SEID)
4684 * @vsi_seid: connected vsi seid
4685 * @ret_seid: seid of create pv component
4687 * This instantiates an i40e port virtualizer with specified flags.
4688 * Depending on specified flags the port virtualizer can act as a
4689 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4691 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4692 u16 mac_seid, u16 vsi_seid,
4695 struct i40e_aq_desc desc;
4696 struct i40e_aqc_add_update_pv *cmd =
4697 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4698 struct i40e_aqc_add_update_pv_completion *resp =
4699 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4700 enum i40e_status_code status;
4703 return I40E_ERR_PARAM;
4705 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4706 cmd->command_flags = CPU_TO_LE16(flags);
4707 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4708 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4710 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4711 if (!status && ret_seid)
4712 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4718 * i40e_aq_add_tag - Add an S/E-tag
4719 * @hw: pointer to the hw struct
4720 * @direct_to_queue: should s-tag direct flow to a specific queue
4721 * @vsi_seid: VSI SEID to use this tag
4722 * @tag: value of the tag
4723 * @queue_num: queue number, only valid is direct_to_queue is true
4724 * @tags_used: return value, number of tags in use by this PF
4725 * @tags_free: return value, number of unallocated tags
4726 * @cmd_details: pointer to command details structure or NULL
4728 * This associates an S- or E-tag to a VSI in the switch complex. It returns
4729 * the number of tags allocated by the PF, and the number of unallocated
4732 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4733 u16 vsi_seid, u16 tag, u16 queue_num,
4734 u16 *tags_used, u16 *tags_free,
4735 struct i40e_asq_cmd_details *cmd_details)
4737 struct i40e_aq_desc desc;
4738 struct i40e_aqc_add_tag *cmd =
4739 (struct i40e_aqc_add_tag *)&desc.params.raw;
4740 struct i40e_aqc_add_remove_tag_completion *resp =
4741 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4742 enum i40e_status_code status;
4745 return I40E_ERR_PARAM;
4747 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4749 cmd->seid = CPU_TO_LE16(vsi_seid);
4750 cmd->tag = CPU_TO_LE16(tag);
4751 if (direct_to_queue) {
4752 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4753 cmd->queue_number = CPU_TO_LE16(queue_num);
4756 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4759 if (tags_used != NULL)
4760 *tags_used = LE16_TO_CPU(resp->tags_used);
4761 if (tags_free != NULL)
4762 *tags_free = LE16_TO_CPU(resp->tags_free);
4769 * i40e_aq_remove_tag - Remove an S- or E-tag
4770 * @hw: pointer to the hw struct
4771 * @vsi_seid: VSI SEID this tag is associated with
4772 * @tag: value of the S-tag to delete
4773 * @tags_used: return value, number of tags in use by this PF
4774 * @tags_free: return value, number of unallocated tags
4775 * @cmd_details: pointer to command details structure or NULL
4777 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
4778 * the number of tags allocated by the PF, and the number of unallocated
4781 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4782 u16 tag, u16 *tags_used, u16 *tags_free,
4783 struct i40e_asq_cmd_details *cmd_details)
4785 struct i40e_aq_desc desc;
4786 struct i40e_aqc_remove_tag *cmd =
4787 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4788 struct i40e_aqc_add_remove_tag_completion *resp =
4789 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4790 enum i40e_status_code status;
4793 return I40E_ERR_PARAM;
4795 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4797 cmd->seid = CPU_TO_LE16(vsi_seid);
4798 cmd->tag = CPU_TO_LE16(tag);
4800 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4803 if (tags_used != NULL)
4804 *tags_used = LE16_TO_CPU(resp->tags_used);
4805 if (tags_free != NULL)
4806 *tags_free = LE16_TO_CPU(resp->tags_free);
4813 * i40e_aq_add_mcast_etag - Add a multicast E-tag
4814 * @hw: pointer to the hw struct
4815 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4816 * @etag: value of E-tag to add
4817 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4818 * @buf: address of indirect buffer
4819 * @tags_used: return value, number of E-tags in use by this port
4820 * @tags_free: return value, number of unallocated M-tags
4821 * @cmd_details: pointer to command details structure or NULL
4823 * This associates a multicast E-tag to a port virtualizer. It will return
4824 * the number of tags allocated by the PF, and the number of unallocated
4827 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4828 * num_tags_in_buf long.
4830 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4831 u16 etag, u8 num_tags_in_buf, void *buf,
4832 u16 *tags_used, u16 *tags_free,
4833 struct i40e_asq_cmd_details *cmd_details)
4835 struct i40e_aq_desc desc;
4836 struct i40e_aqc_add_remove_mcast_etag *cmd =
4837 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4838 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4839 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4840 enum i40e_status_code status;
4841 u16 length = sizeof(u16) * num_tags_in_buf;
4843 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4844 return I40E_ERR_PARAM;
4846 i40e_fill_default_direct_cmd_desc(&desc,
4847 i40e_aqc_opc_add_multicast_etag);
4849 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4850 cmd->etag = CPU_TO_LE16(etag);
4851 cmd->num_unicast_etags = num_tags_in_buf;
4853 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4854 if (length > I40E_AQ_LARGE_BUF)
4855 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4857 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4860 if (tags_used != NULL)
4861 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4862 if (tags_free != NULL)
4863 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4870 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4871 * @hw: pointer to the hw struct
4872 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4873 * @etag: value of the E-tag to remove
4874 * @tags_used: return value, number of tags in use by this port
4875 * @tags_free: return value, number of unallocated tags
4876 * @cmd_details: pointer to command details structure or NULL
4878 * This deletes an E-tag from the port virtualizer. It will return
4879 * the number of tags allocated by the port, and the number of unallocated
4882 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4883 u16 etag, u16 *tags_used, u16 *tags_free,
4884 struct i40e_asq_cmd_details *cmd_details)
4886 struct i40e_aq_desc desc;
4887 struct i40e_aqc_add_remove_mcast_etag *cmd =
4888 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4889 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4890 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4891 enum i40e_status_code status;
4895 return I40E_ERR_PARAM;
4897 i40e_fill_default_direct_cmd_desc(&desc,
4898 i40e_aqc_opc_remove_multicast_etag);
4900 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4901 cmd->etag = CPU_TO_LE16(etag);
4903 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4906 if (tags_used != NULL)
4907 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4908 if (tags_free != NULL)
4909 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4916 * i40e_aq_update_tag - Update an S/E-tag
4917 * @hw: pointer to the hw struct
4918 * @vsi_seid: VSI SEID using this S-tag
4919 * @old_tag: old tag value
4920 * @new_tag: new tag value
4921 * @tags_used: return value, number of tags in use by this PF
4922 * @tags_free: return value, number of unallocated tags
4923 * @cmd_details: pointer to command details structure or NULL
4925 * This updates the value of the tag currently attached to this VSI
4926 * in the switch complex. It will return the number of tags allocated
4927 * by the PF, and the number of unallocated tags available.
4929 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4930 u16 old_tag, u16 new_tag, u16 *tags_used,
4932 struct i40e_asq_cmd_details *cmd_details)
4934 struct i40e_aq_desc desc;
4935 struct i40e_aqc_update_tag *cmd =
4936 (struct i40e_aqc_update_tag *)&desc.params.raw;
4937 struct i40e_aqc_update_tag_completion *resp =
4938 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4939 enum i40e_status_code status;
4942 return I40E_ERR_PARAM;
4944 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4946 cmd->seid = CPU_TO_LE16(vsi_seid);
4947 cmd->old_tag = CPU_TO_LE16(old_tag);
4948 cmd->new_tag = CPU_TO_LE16(new_tag);
4950 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4953 if (tags_used != NULL)
4954 *tags_used = LE16_TO_CPU(resp->tags_used);
4955 if (tags_free != NULL)
4956 *tags_free = LE16_TO_CPU(resp->tags_free);
4963 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4964 * @hw: pointer to the hw struct
4965 * @tcmap: TC map for request/release any ignore PFC condition
4966 * @request: request or release ignore PFC condition
4967 * @tcmap_ret: return TCs for which PFC is currently ignored
4968 * @cmd_details: pointer to command details structure or NULL
4970 * This sends out request/release to ignore PFC condition for a TC.
4971 * It will return the TCs for which PFC is currently ignored.
4973 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4974 bool request, u8 *tcmap_ret,
4975 struct i40e_asq_cmd_details *cmd_details)
4977 struct i40e_aq_desc desc;
4978 struct i40e_aqc_pfc_ignore *cmd_resp =
4979 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4980 enum i40e_status_code status;
4982 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4985 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4987 cmd_resp->tc_bitmap = tcmap;
4989 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4992 if (tcmap_ret != NULL)
4993 *tcmap_ret = cmd_resp->tc_bitmap;
5000 * i40e_aq_dcb_updated - DCB Updated Command
5001 * @hw: pointer to the hw struct
5002 * @cmd_details: pointer to command details structure or NULL
5004 * When LLDP is handled in PF this command is used by the PF
5005 * to notify EMP that a DCB setting is modified.
5006 * When LLDP is handled in EMP this command is used by the PF
5007 * to notify EMP whenever one of the following parameters get
5009 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
5010 * - PCIRTT in PRTDCB_GENC.PCIRTT
5011 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
5012 * EMP will return when the shared RPB settings have been
5013 * recomputed and modified. The retval field in the descriptor
5014 * will be set to 0 when RPB is modified.
5016 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
5017 struct i40e_asq_cmd_details *cmd_details)
5019 struct i40e_aq_desc desc;
5020 enum i40e_status_code status;
5022 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
5024 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5030 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
5031 * @hw: pointer to the hw struct
5032 * @seid: defines the SEID of the switch for which the stats are requested
5033 * @vlan_id: the VLAN ID for which the statistics are requested
5034 * @stat_index: index of the statistics counters block assigned to this VLAN
5035 * @cmd_details: pointer to command details structure or NULL
5037 * XL710 supports 128 smonVlanStats counters.This command is used to
5038 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
5041 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
5042 u16 vlan_id, u16 *stat_index,
5043 struct i40e_asq_cmd_details *cmd_details)
5045 struct i40e_aq_desc desc;
5046 struct i40e_aqc_add_remove_statistics *cmd_resp =
5047 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5048 enum i40e_status_code status;
5050 if ((seid == 0) || (stat_index == NULL))
5051 return I40E_ERR_PARAM;
5053 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
5055 cmd_resp->seid = CPU_TO_LE16(seid);
5056 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
5058 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5060 if (!status && stat_index)
5061 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
5067 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
5068 * @hw: pointer to the hw struct
5069 * @seid: defines the SEID of the switch for which the stats are requested
5070 * @vlan_id: the VLAN ID for which the statistics are requested
5071 * @stat_index: index of the statistics counters block assigned to this VLAN
5072 * @cmd_details: pointer to command details structure or NULL
5074 * XL710 supports 128 smonVlanStats counters.This command is used to
5075 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
5078 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
5079 u16 vlan_id, u16 stat_index,
5080 struct i40e_asq_cmd_details *cmd_details)
5082 struct i40e_aq_desc desc;
5083 struct i40e_aqc_add_remove_statistics *cmd =
5084 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5085 enum i40e_status_code status;
5088 return I40E_ERR_PARAM;
5090 i40e_fill_default_direct_cmd_desc(&desc,
5091 i40e_aqc_opc_remove_statistics);
5093 cmd->seid = CPU_TO_LE16(seid);
5094 cmd->vlan = CPU_TO_LE16(vlan_id);
5095 cmd->stat_index = CPU_TO_LE16(stat_index);
5097 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5103 * i40e_aq_set_port_parameters - set physical port parameters.
5104 * @hw: pointer to the hw struct
5105 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
5106 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
5107 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
5108 * @double_vlan: if set double VLAN is enabled
5109 * @cmd_details: pointer to command details structure or NULL
5111 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
5112 u16 bad_frame_vsi, bool save_bad_pac,
5113 bool pad_short_pac, bool double_vlan,
5114 struct i40e_asq_cmd_details *cmd_details)
5116 struct i40e_aqc_set_port_parameters *cmd;
5117 enum i40e_status_code status;
5118 struct i40e_aq_desc desc;
5119 u16 command_flags = 0;
5121 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
5123 i40e_fill_default_direct_cmd_desc(&desc,
5124 i40e_aqc_opc_set_port_parameters);
5126 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
5128 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
5130 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
5132 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
5133 cmd->command_flags = CPU_TO_LE16(command_flags);
5135 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5141 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
5142 * @hw: pointer to the hw struct
5143 * @seid: seid for the physical port/switching component/vsi
5144 * @buff: Indirect buffer to hold data parameters and response
5145 * @buff_size: Indirect buffer size
5146 * @opcode: Tx scheduler AQ command opcode
5147 * @cmd_details: pointer to command details structure or NULL
5149 * Generic command handler for Tx scheduler AQ commands
5151 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
5152 void *buff, u16 buff_size,
5153 enum i40e_admin_queue_opc opcode,
5154 struct i40e_asq_cmd_details *cmd_details)
5156 struct i40e_aq_desc desc;
5157 struct i40e_aqc_tx_sched_ind *cmd =
5158 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
5159 enum i40e_status_code status;
5160 bool cmd_param_flag = false;
5163 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
5164 case i40e_aqc_opc_configure_vsi_tc_bw:
5165 case i40e_aqc_opc_enable_switching_comp_ets:
5166 case i40e_aqc_opc_modify_switching_comp_ets:
5167 case i40e_aqc_opc_disable_switching_comp_ets:
5168 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
5169 case i40e_aqc_opc_configure_switching_comp_bw_config:
5170 cmd_param_flag = true;
5172 case i40e_aqc_opc_query_vsi_bw_config:
5173 case i40e_aqc_opc_query_vsi_ets_sla_config:
5174 case i40e_aqc_opc_query_switching_comp_ets_config:
5175 case i40e_aqc_opc_query_port_ets_config:
5176 case i40e_aqc_opc_query_switching_comp_bw_config:
5177 cmd_param_flag = false;
5180 return I40E_ERR_PARAM;
5183 i40e_fill_default_direct_cmd_desc(&desc, opcode);
5185 /* Indirect command */
5186 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5188 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5189 if (buff_size > I40E_AQ_LARGE_BUF)
5190 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5192 desc.datalen = CPU_TO_LE16(buff_size);
5194 cmd->vsi_seid = CPU_TO_LE16(seid);
5196 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5202 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5203 * @hw: pointer to the hw struct
5205 * @credit: BW limit credits (0 = disabled)
5206 * @max_credit: Max BW limit credits
5207 * @cmd_details: pointer to command details structure or NULL
5209 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5210 u16 seid, u16 credit, u8 max_credit,
5211 struct i40e_asq_cmd_details *cmd_details)
5213 struct i40e_aq_desc desc;
5214 struct i40e_aqc_configure_vsi_bw_limit *cmd =
5215 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5216 enum i40e_status_code status;
5218 i40e_fill_default_direct_cmd_desc(&desc,
5219 i40e_aqc_opc_configure_vsi_bw_limit);
5221 cmd->vsi_seid = CPU_TO_LE16(seid);
5222 cmd->credit = CPU_TO_LE16(credit);
5223 cmd->max_credit = max_credit;
5225 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5231 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5232 * @hw: pointer to the hw struct
5233 * @seid: switching component seid
5234 * @credit: BW limit credits (0 = disabled)
5235 * @max_bw: Max BW limit credits
5236 * @cmd_details: pointer to command details structure or NULL
5238 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5239 u16 seid, u16 credit, u8 max_bw,
5240 struct i40e_asq_cmd_details *cmd_details)
5242 struct i40e_aq_desc desc;
5243 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5244 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5245 enum i40e_status_code status;
5247 i40e_fill_default_direct_cmd_desc(&desc,
5248 i40e_aqc_opc_configure_switching_comp_bw_limit);
5250 cmd->seid = CPU_TO_LE16(seid);
5251 cmd->credit = CPU_TO_LE16(credit);
5252 cmd->max_bw = max_bw;
5254 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5260 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5261 * @hw: pointer to the hw struct
5263 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5264 * @cmd_details: pointer to command details structure or NULL
5266 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5268 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5269 struct i40e_asq_cmd_details *cmd_details)
5271 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5272 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5277 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5278 * @hw: pointer to the hw struct
5280 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5281 * @cmd_details: pointer to command details structure or NULL
5283 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5285 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5286 struct i40e_asq_cmd_details *cmd_details)
5288 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5289 i40e_aqc_opc_configure_vsi_tc_bw,
5294 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5295 * @hw: pointer to the hw struct
5296 * @seid: seid of the switching component connected to Physical Port
5297 * @ets_data: Buffer holding ETS parameters
5298 * @opcode: Tx scheduler AQ command opcode
5299 * @cmd_details: pointer to command details structure or NULL
5301 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5303 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5304 enum i40e_admin_queue_opc opcode,
5305 struct i40e_asq_cmd_details *cmd_details)
5307 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5308 sizeof(*ets_data), opcode, cmd_details);
5312 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5313 * @hw: pointer to the hw struct
5314 * @seid: seid of the switching component
5315 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5316 * @cmd_details: pointer to command details structure or NULL
5318 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5320 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5321 struct i40e_asq_cmd_details *cmd_details)
5323 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5324 i40e_aqc_opc_configure_switching_comp_bw_config,
5329 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5330 * @hw: pointer to the hw struct
5331 * @seid: seid of the switching component
5332 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5333 * @cmd_details: pointer to command details structure or NULL
5335 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5336 struct i40e_hw *hw, u16 seid,
5337 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5338 struct i40e_asq_cmd_details *cmd_details)
5340 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5341 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5346 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5347 * @hw: pointer to the hw struct
5348 * @seid: seid of the VSI
5349 * @bw_data: Buffer to hold VSI BW configuration
5350 * @cmd_details: pointer to command details structure or NULL
5352 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5354 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5355 struct i40e_asq_cmd_details *cmd_details)
5357 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5358 i40e_aqc_opc_query_vsi_bw_config,
5363 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5364 * @hw: pointer to the hw struct
5365 * @seid: seid of the VSI
5366 * @bw_data: Buffer to hold VSI BW configuration per TC
5367 * @cmd_details: pointer to command details structure or NULL
5369 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5371 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5372 struct i40e_asq_cmd_details *cmd_details)
5374 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5375 i40e_aqc_opc_query_vsi_ets_sla_config,
5380 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5381 * @hw: pointer to the hw struct
5382 * @seid: seid of the switching component
5383 * @bw_data: Buffer to hold switching component's per TC BW config
5384 * @cmd_details: pointer to command details structure or NULL
5386 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5388 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5389 struct i40e_asq_cmd_details *cmd_details)
5391 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5392 i40e_aqc_opc_query_switching_comp_ets_config,
5397 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5398 * @hw: pointer to the hw struct
5399 * @seid: seid of the VSI or switching component connected to Physical Port
5400 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5401 * @cmd_details: pointer to command details structure or NULL
5403 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5405 struct i40e_aqc_query_port_ets_config_resp *bw_data,
5406 struct i40e_asq_cmd_details *cmd_details)
5408 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5409 i40e_aqc_opc_query_port_ets_config,
5414 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5415 * @hw: pointer to the hw struct
5416 * @seid: seid of the switching component
5417 * @bw_data: Buffer to hold switching component's BW configuration
5418 * @cmd_details: pointer to command details structure or NULL
5420 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5422 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5423 struct i40e_asq_cmd_details *cmd_details)
5425 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5426 i40e_aqc_opc_query_switching_comp_bw_config,
5431 * i40e_validate_filter_settings
5432 * @hw: pointer to the hardware structure
5433 * @settings: Filter control settings
5435 * Check and validate the filter control settings passed.
5436 * The function checks for the valid filter/context sizes being
5437 * passed for FCoE and PE.
5439 * Returns I40E_SUCCESS if the values passed are valid and within
5440 * range else returns an error.
5442 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5443 struct i40e_filter_control_settings *settings)
5445 u32 fcoe_cntx_size, fcoe_filt_size;
5446 u32 pe_cntx_size, pe_filt_size;
5451 /* Validate FCoE settings passed */
5452 switch (settings->fcoe_filt_num) {
5453 case I40E_HASH_FILTER_SIZE_1K:
5454 case I40E_HASH_FILTER_SIZE_2K:
5455 case I40E_HASH_FILTER_SIZE_4K:
5456 case I40E_HASH_FILTER_SIZE_8K:
5457 case I40E_HASH_FILTER_SIZE_16K:
5458 case I40E_HASH_FILTER_SIZE_32K:
5459 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5460 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5463 return I40E_ERR_PARAM;
5466 switch (settings->fcoe_cntx_num) {
5467 case I40E_DMA_CNTX_SIZE_512:
5468 case I40E_DMA_CNTX_SIZE_1K:
5469 case I40E_DMA_CNTX_SIZE_2K:
5470 case I40E_DMA_CNTX_SIZE_4K:
5471 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5472 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5475 return I40E_ERR_PARAM;
5478 /* Validate PE settings passed */
5479 switch (settings->pe_filt_num) {
5480 case I40E_HASH_FILTER_SIZE_1K:
5481 case I40E_HASH_FILTER_SIZE_2K:
5482 case I40E_HASH_FILTER_SIZE_4K:
5483 case I40E_HASH_FILTER_SIZE_8K:
5484 case I40E_HASH_FILTER_SIZE_16K:
5485 case I40E_HASH_FILTER_SIZE_32K:
5486 case I40E_HASH_FILTER_SIZE_64K:
5487 case I40E_HASH_FILTER_SIZE_128K:
5488 case I40E_HASH_FILTER_SIZE_256K:
5489 case I40E_HASH_FILTER_SIZE_512K:
5490 case I40E_HASH_FILTER_SIZE_1M:
5491 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5492 pe_filt_size <<= (u32)settings->pe_filt_num;
5495 return I40E_ERR_PARAM;
5498 switch (settings->pe_cntx_num) {
5499 case I40E_DMA_CNTX_SIZE_512:
5500 case I40E_DMA_CNTX_SIZE_1K:
5501 case I40E_DMA_CNTX_SIZE_2K:
5502 case I40E_DMA_CNTX_SIZE_4K:
5503 case I40E_DMA_CNTX_SIZE_8K:
5504 case I40E_DMA_CNTX_SIZE_16K:
5505 case I40E_DMA_CNTX_SIZE_32K:
5506 case I40E_DMA_CNTX_SIZE_64K:
5507 case I40E_DMA_CNTX_SIZE_128K:
5508 case I40E_DMA_CNTX_SIZE_256K:
5509 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5510 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5513 return I40E_ERR_PARAM;
5516 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5517 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5518 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5519 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5520 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
5521 return I40E_ERR_INVALID_SIZE;
5523 return I40E_SUCCESS;
5527 * i40e_set_filter_control
5528 * @hw: pointer to the hardware structure
5529 * @settings: Filter control settings
5531 * Set the Queue Filters for PE/FCoE and enable filters required
5532 * for a single PF. It is expected that these settings are programmed
5533 * at the driver initialization time.
5535 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5536 struct i40e_filter_control_settings *settings)
5538 enum i40e_status_code ret = I40E_SUCCESS;
5539 u32 hash_lut_size = 0;
5543 return I40E_ERR_PARAM;
5545 /* Validate the input settings */
5546 ret = i40e_validate_filter_settings(hw, settings);
5550 /* Read the PF Queue Filter control register */
5551 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5553 /* Program required PE hash buckets for the PF */
5554 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5555 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5556 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5557 /* Program required PE contexts for the PF */
5558 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5559 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5560 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5562 /* Program required FCoE hash buckets for the PF */
5563 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5564 val |= ((u32)settings->fcoe_filt_num <<
5565 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5566 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5567 /* Program required FCoE DDP contexts for the PF */
5568 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5569 val |= ((u32)settings->fcoe_cntx_num <<
5570 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5571 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5573 /* Program Hash LUT size for the PF */
5574 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5575 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5577 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5578 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5580 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5581 if (settings->enable_fdir)
5582 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5583 if (settings->enable_ethtype)
5584 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5585 if (settings->enable_macvlan)
5586 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5588 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5590 return I40E_SUCCESS;
5594 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5595 * @hw: pointer to the hw struct
5596 * @mac_addr: MAC address to use in the filter
5597 * @ethtype: Ethertype to use in the filter
5598 * @flags: Flags that needs to be applied to the filter
5599 * @vsi_seid: seid of the control VSI
5600 * @queue: VSI queue number to send the packet to
5601 * @is_add: Add control packet filter if True else remove
5602 * @stats: Structure to hold information on control filter counts
5603 * @cmd_details: pointer to command details structure or NULL
5605 * This command will Add or Remove control packet filter for a control VSI.
5606 * In return it will update the total number of perfect filter count in
5609 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5610 u8 *mac_addr, u16 ethtype, u16 flags,
5611 u16 vsi_seid, u16 queue, bool is_add,
5612 struct i40e_control_filter_stats *stats,
5613 struct i40e_asq_cmd_details *cmd_details)
5615 struct i40e_aq_desc desc;
5616 struct i40e_aqc_add_remove_control_packet_filter *cmd =
5617 (struct i40e_aqc_add_remove_control_packet_filter *)
5619 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5620 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5622 enum i40e_status_code status;
5625 return I40E_ERR_PARAM;
5628 i40e_fill_default_direct_cmd_desc(&desc,
5629 i40e_aqc_opc_add_control_packet_filter);
5630 cmd->queue = CPU_TO_LE16(queue);
5632 i40e_fill_default_direct_cmd_desc(&desc,
5633 i40e_aqc_opc_remove_control_packet_filter);
5637 i40e_memcpy(cmd->mac, mac_addr, ETH_ALEN,
5638 I40E_NONDMA_TO_NONDMA);
5640 cmd->etype = CPU_TO_LE16(ethtype);
5641 cmd->flags = CPU_TO_LE16(flags);
5642 cmd->seid = CPU_TO_LE16(vsi_seid);
5644 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5646 if (!status && stats) {
5647 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5648 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5649 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5650 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5657 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5658 * @hw: pointer to the hw struct
5659 * @seid: VSI seid to add ethertype filter from
5661 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5664 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5665 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5666 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5667 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5668 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5669 enum i40e_status_code status;
5671 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5672 seid, 0, true, NULL,
5675 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5679 * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5680 * @filters: list of cloud filters
5681 * @filter_count: length of list
5683 * There's an issue in the device where the Geneve VNI layout needs
5684 * to be shifted 1 byte over from the VxLAN VNI
5686 STATIC void i40e_fix_up_geneve_vni(
5687 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5690 struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters;
5693 for (i = 0; i < filter_count; i++) {
5697 tnl_type = (LE16_TO_CPU(f[i].flags) &
5698 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5699 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5700 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5701 ti = LE32_TO_CPU(f[i].tenant_id);
5702 f[i].tenant_id = CPU_TO_LE32(ti << 8);
5708 * i40e_aq_add_cloud_filters
5709 * @hw: pointer to the hardware structure
5710 * @seid: VSI seid to add cloud filters from
5711 * @filters: Buffer which contains the filters to be added
5712 * @filter_count: number of filters contained in the buffer
5714 * Set the cloud filters for a given VSI. The contents of the
5715 * i40e_aqc_add_remove_cloud_filters_element_data are filled
5716 * in by the caller of the function.
5719 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5721 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5724 struct i40e_aq_desc desc;
5725 struct i40e_aqc_add_remove_cloud_filters *cmd =
5726 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5727 enum i40e_status_code status;
5730 i40e_fill_default_direct_cmd_desc(&desc,
5731 i40e_aqc_opc_add_cloud_filters);
5733 buff_len = filter_count * sizeof(*filters);
5734 desc.datalen = CPU_TO_LE16(buff_len);
5735 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5736 cmd->num_filters = filter_count;
5737 cmd->seid = CPU_TO_LE16(seid);
5739 i40e_fix_up_geneve_vni(filters, filter_count);
5741 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5747 * i40e_aq_add_cloud_filters_big_buffer
5748 * @hw: pointer to the hardware structure
5749 * @seid: VSI seid to add cloud filters from
5750 * @filters: Buffer which contains the filters in big buffer to be added
5751 * @filter_count: number of filters contained in the buffer
5753 * Set the cloud filters for a given VSI. The contents of the
5754 * i40e_aqc_add_rm_cloud_filt_elem_ext are filled in by the caller of
5758 enum i40e_status_code i40e_aq_add_cloud_filters_big_buffer(struct i40e_hw *hw,
5760 struct i40e_aqc_add_rm_cloud_filt_elem_ext *filters,
5763 struct i40e_aq_desc desc;
5764 struct i40e_aqc_add_remove_cloud_filters *cmd =
5765 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5766 enum i40e_status_code status;
5770 i40e_fill_default_direct_cmd_desc(&desc,
5771 i40e_aqc_opc_add_cloud_filters);
5773 buff_len = filter_count * sizeof(*filters);
5774 desc.datalen = CPU_TO_LE16(buff_len);
5775 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5776 cmd->num_filters = filter_count;
5777 cmd->seid = CPU_TO_LE16(seid);
5778 cmd->big_buffer_flag = I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER;
5780 /* adjust Geneve VNI for HW issue */
5781 for (i = 0; i < filter_count; i++) {
5785 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5786 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5787 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5788 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5789 ti = LE32_TO_CPU(filters[i].element.tenant_id);
5790 filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5794 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5800 * i40e_aq_remove_cloud_filters
5801 * @hw: pointer to the hardware structure
5802 * @seid: VSI seid to remove cloud filters from
5803 * @filters: Buffer which contains the filters to be removed
5804 * @filter_count: number of filters contained in the buffer
5806 * Remove the cloud filters for a given VSI. The contents of the
5807 * i40e_aqc_add_remove_cloud_filters_element_data are filled
5808 * in by the caller of the function.
5811 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5813 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5816 struct i40e_aq_desc desc;
5817 struct i40e_aqc_add_remove_cloud_filters *cmd =
5818 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5819 enum i40e_status_code status;
5822 i40e_fill_default_direct_cmd_desc(&desc,
5823 i40e_aqc_opc_remove_cloud_filters);
5825 buff_len = filter_count * sizeof(*filters);
5826 desc.datalen = CPU_TO_LE16(buff_len);
5827 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5828 cmd->num_filters = filter_count;
5829 cmd->seid = CPU_TO_LE16(seid);
5831 i40e_fix_up_geneve_vni(filters, filter_count);
5833 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5839 * i40e_aq_remove_cloud_filters_big_buffer
5840 * @hw: pointer to the hardware structure
5841 * @seid: VSI seid to remove cloud filters from
5842 * @filters: Buffer which contains the filters in big buffer to be removed
5843 * @filter_count: number of filters contained in the buffer
5845 * Remove the cloud filters for a given VSI. The contents of the
5846 * i40e_aqc_add_rm_cloud_filt_elem_ext are filled in by the caller of
5850 enum i40e_status_code i40e_aq_remove_cloud_filters_big_buffer(
5853 struct i40e_aqc_add_rm_cloud_filt_elem_ext *filters,
5856 struct i40e_aq_desc desc;
5857 struct i40e_aqc_add_remove_cloud_filters *cmd =
5858 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5859 enum i40e_status_code status;
5863 i40e_fill_default_direct_cmd_desc(&desc,
5864 i40e_aqc_opc_remove_cloud_filters);
5866 buff_len = filter_count * sizeof(*filters);
5867 desc.datalen = CPU_TO_LE16(buff_len);
5868 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5869 cmd->num_filters = filter_count;
5870 cmd->seid = CPU_TO_LE16(seid);
5871 cmd->big_buffer_flag = I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER;
5873 /* adjust Geneve VNI for HW issue */
5874 for (i = 0; i < filter_count; i++) {
5878 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5879 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5880 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5881 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5882 ti = LE32_TO_CPU(filters[i].element.tenant_id);
5883 filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5887 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5893 * i40e_aq_replace_cloud_filters - Replace cloud filter command
5894 * @hw: pointer to the hw struct
5895 * @filters: pointer to the i40e_aqc_replace_cloud_filter_cmd struct
5896 * @cmd_buf: pointer to the i40e_aqc_replace_cloud_filter_cmd_buf struct
5900 i40e_status_code i40e_aq_replace_cloud_filters(struct i40e_hw *hw,
5901 struct i40e_aqc_replace_cloud_filters_cmd *filters,
5902 struct i40e_aqc_replace_cloud_filters_cmd_buf *cmd_buf)
5904 struct i40e_aq_desc desc;
5905 struct i40e_aqc_replace_cloud_filters_cmd *cmd =
5906 (struct i40e_aqc_replace_cloud_filters_cmd *)&desc.params.raw;
5907 enum i40e_status_code status = I40E_SUCCESS;
5910 i40e_fill_default_direct_cmd_desc(&desc,
5911 i40e_aqc_opc_replace_cloud_filters);
5913 desc.datalen = CPU_TO_LE16(32);
5914 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5915 cmd->old_filter_type = filters->old_filter_type;
5916 cmd->new_filter_type = filters->new_filter_type;
5917 cmd->valid_flags = filters->valid_flags;
5918 cmd->tr_bit = filters->tr_bit;
5920 status = i40e_asq_send_command(hw, &desc, cmd_buf,
5921 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf), NULL);
5923 /* for get cloud filters command */
5924 for (i = 0; i < 32; i += 4) {
5925 cmd_buf->filters[i / 4].filter_type = cmd_buf->data[i];
5926 cmd_buf->filters[i / 4].input[0] = cmd_buf->data[i + 1];
5927 cmd_buf->filters[i / 4].input[1] = cmd_buf->data[i + 2];
5928 cmd_buf->filters[i / 4].input[2] = cmd_buf->data[i + 3];
5936 * i40e_aq_alternate_write
5937 * @hw: pointer to the hardware structure
5938 * @reg_addr0: address of first dword to be read
5939 * @reg_val0: value to be written under 'reg_addr0'
5940 * @reg_addr1: address of second dword to be read
5941 * @reg_val1: value to be written under 'reg_addr1'
5943 * Write one or two dwords to alternate structure. Fields are indicated
5944 * by 'reg_addr0' and 'reg_addr1' register numbers.
5947 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5948 u32 reg_addr0, u32 reg_val0,
5949 u32 reg_addr1, u32 reg_val1)
5951 struct i40e_aq_desc desc;
5952 struct i40e_aqc_alternate_write *cmd_resp =
5953 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5954 enum i40e_status_code status;
5956 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5957 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5958 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5959 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5960 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5962 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5968 * i40e_aq_alternate_write_indirect
5969 * @hw: pointer to the hardware structure
5970 * @addr: address of a first register to be modified
5971 * @dw_count: number of alternate structure fields to write
5972 * @buffer: pointer to the command buffer
5974 * Write 'dw_count' dwords from 'buffer' to alternate structure
5975 * starting at 'addr'.
5978 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5979 u32 addr, u32 dw_count, void *buffer)
5981 struct i40e_aq_desc desc;
5982 struct i40e_aqc_alternate_ind_write *cmd_resp =
5983 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5984 enum i40e_status_code status;
5987 return I40E_ERR_PARAM;
5989 /* Indirect command */
5990 i40e_fill_default_direct_cmd_desc(&desc,
5991 i40e_aqc_opc_alternate_write_indirect);
5993 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5994 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5995 if (dw_count > (I40E_AQ_LARGE_BUF/4))
5996 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5998 cmd_resp->address = CPU_TO_LE32(addr);
5999 cmd_resp->length = CPU_TO_LE32(dw_count);
6001 status = i40e_asq_send_command(hw, &desc, buffer,
6002 I40E_LO_DWORD(4*dw_count), NULL);
6008 * i40e_aq_alternate_read
6009 * @hw: pointer to the hardware structure
6010 * @reg_addr0: address of first dword to be read
6011 * @reg_val0: pointer for data read from 'reg_addr0'
6012 * @reg_addr1: address of second dword to be read
6013 * @reg_val1: pointer for data read from 'reg_addr1'
6015 * Read one or two dwords from alternate structure. Fields are indicated
6016 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
6017 * is not passed then only register at 'reg_addr0' is read.
6020 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
6021 u32 reg_addr0, u32 *reg_val0,
6022 u32 reg_addr1, u32 *reg_val1)
6024 struct i40e_aq_desc desc;
6025 struct i40e_aqc_alternate_write *cmd_resp =
6026 (struct i40e_aqc_alternate_write *)&desc.params.raw;
6027 enum i40e_status_code status;
6029 if (reg_val0 == NULL)
6030 return I40E_ERR_PARAM;
6032 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
6033 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
6034 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
6036 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6038 if (status == I40E_SUCCESS) {
6039 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
6041 if (reg_val1 != NULL)
6042 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
6049 * i40e_aq_alternate_read_indirect
6050 * @hw: pointer to the hardware structure
6051 * @addr: address of the alternate structure field
6052 * @dw_count: number of alternate structure fields to read
6053 * @buffer: pointer to the command buffer
6055 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
6056 * place them in 'buffer'. The buffer should be allocated by caller.
6059 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
6060 u32 addr, u32 dw_count, void *buffer)
6062 struct i40e_aq_desc desc;
6063 struct i40e_aqc_alternate_ind_write *cmd_resp =
6064 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
6065 enum i40e_status_code status;
6068 return I40E_ERR_PARAM;
6070 /* Indirect command */
6071 i40e_fill_default_direct_cmd_desc(&desc,
6072 i40e_aqc_opc_alternate_read_indirect);
6074 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6075 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6076 if (dw_count > (I40E_AQ_LARGE_BUF/4))
6077 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6079 cmd_resp->address = CPU_TO_LE32(addr);
6080 cmd_resp->length = CPU_TO_LE32(dw_count);
6082 status = i40e_asq_send_command(hw, &desc, buffer,
6083 I40E_LO_DWORD(4*dw_count), NULL);
6089 * i40e_aq_alternate_clear
6090 * @hw: pointer to the HW structure.
6092 * Clear the alternate structures of the port from which the function
6096 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
6098 struct i40e_aq_desc desc;
6099 enum i40e_status_code status;
6101 i40e_fill_default_direct_cmd_desc(&desc,
6102 i40e_aqc_opc_alternate_clear_port);
6104 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6110 * i40e_aq_alternate_write_done
6111 * @hw: pointer to the HW structure.
6112 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
6113 * @reset_needed: indicates the SW should trigger GLOBAL reset
6115 * Indicates to the FW that alternate structures have been changed.
6118 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
6119 u8 bios_mode, bool *reset_needed)
6121 struct i40e_aq_desc desc;
6122 struct i40e_aqc_alternate_write_done *cmd =
6123 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6124 enum i40e_status_code status;
6126 if (reset_needed == NULL)
6127 return I40E_ERR_PARAM;
6129 i40e_fill_default_direct_cmd_desc(&desc,
6130 i40e_aqc_opc_alternate_write_done);
6132 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
6134 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6135 if (!status && reset_needed)
6136 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
6137 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
6143 * i40e_aq_set_oem_mode
6144 * @hw: pointer to the HW structure.
6145 * @oem_mode: the OEM mode to be used
6147 * Sets the device to a specific operating mode. Currently the only supported
6148 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
6151 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
6154 struct i40e_aq_desc desc;
6155 struct i40e_aqc_alternate_write_done *cmd =
6156 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6157 enum i40e_status_code status;
6159 i40e_fill_default_direct_cmd_desc(&desc,
6160 i40e_aqc_opc_alternate_set_mode);
6162 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
6164 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6170 * i40e_aq_resume_port_tx
6171 * @hw: pointer to the hardware structure
6172 * @cmd_details: pointer to command details structure or NULL
6174 * Resume port's Tx traffic
6176 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
6177 struct i40e_asq_cmd_details *cmd_details)
6179 struct i40e_aq_desc desc;
6180 enum i40e_status_code status;
6182 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
6184 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6190 * i40e_set_pci_config_data - store PCI bus info
6191 * @hw: pointer to hardware structure
6192 * @link_status: the link status word from PCI config space
6194 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
6196 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
6198 hw->bus.type = i40e_bus_type_pci_express;
6200 switch (link_status & I40E_PCI_LINK_WIDTH) {
6201 case I40E_PCI_LINK_WIDTH_1:
6202 hw->bus.width = i40e_bus_width_pcie_x1;
6204 case I40E_PCI_LINK_WIDTH_2:
6205 hw->bus.width = i40e_bus_width_pcie_x2;
6207 case I40E_PCI_LINK_WIDTH_4:
6208 hw->bus.width = i40e_bus_width_pcie_x4;
6210 case I40E_PCI_LINK_WIDTH_8:
6211 hw->bus.width = i40e_bus_width_pcie_x8;
6214 hw->bus.width = i40e_bus_width_unknown;
6218 switch (link_status & I40E_PCI_LINK_SPEED) {
6219 case I40E_PCI_LINK_SPEED_2500:
6220 hw->bus.speed = i40e_bus_speed_2500;
6222 case I40E_PCI_LINK_SPEED_5000:
6223 hw->bus.speed = i40e_bus_speed_5000;
6225 case I40E_PCI_LINK_SPEED_8000:
6226 hw->bus.speed = i40e_bus_speed_8000;
6229 hw->bus.speed = i40e_bus_speed_unknown;
6235 * i40e_aq_debug_dump
6236 * @hw: pointer to the hardware structure
6237 * @cluster_id: specific cluster to dump
6238 * @table_id: table id within cluster
6239 * @start_index: index of line in the block to read
6240 * @buff_size: dump buffer size
6241 * @buff: dump buffer
6242 * @ret_buff_size: actual buffer size returned
6243 * @ret_next_table: next block to read
6244 * @ret_next_index: next index to read
6245 * @cmd_details: pointer to command details structure or NULL
6247 * Dump internal FW/HW data for debug purposes.
6250 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
6251 u8 table_id, u32 start_index, u16 buff_size,
6252 void *buff, u16 *ret_buff_size,
6253 u8 *ret_next_table, u32 *ret_next_index,
6254 struct i40e_asq_cmd_details *cmd_details)
6256 struct i40e_aq_desc desc;
6257 struct i40e_aqc_debug_dump_internals *cmd =
6258 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6259 struct i40e_aqc_debug_dump_internals *resp =
6260 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6261 enum i40e_status_code status;
6263 if (buff_size == 0 || !buff)
6264 return I40E_ERR_PARAM;
6266 i40e_fill_default_direct_cmd_desc(&desc,
6267 i40e_aqc_opc_debug_dump_internals);
6268 /* Indirect Command */
6269 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6270 if (buff_size > I40E_AQ_LARGE_BUF)
6271 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6273 cmd->cluster_id = cluster_id;
6274 cmd->table_id = table_id;
6275 cmd->idx = CPU_TO_LE32(start_index);
6277 desc.datalen = CPU_TO_LE16(buff_size);
6279 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
6281 if (ret_buff_size != NULL)
6282 *ret_buff_size = LE16_TO_CPU(desc.datalen);
6283 if (ret_next_table != NULL)
6284 *ret_next_table = resp->table_id;
6285 if (ret_next_index != NULL)
6286 *ret_next_index = LE32_TO_CPU(resp->idx);
6293 * i40e_read_bw_from_alt_ram
6294 * @hw: pointer to the hardware structure
6295 * @max_bw: pointer for max_bw read
6296 * @min_bw: pointer for min_bw read
6297 * @min_valid: pointer for bool that is true if min_bw is a valid value
6298 * @max_valid: pointer for bool that is true if max_bw is a valid value
6300 * Read bw from the alternate ram for the given pf
6302 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
6303 u32 *max_bw, u32 *min_bw,
6304 bool *min_valid, bool *max_valid)
6306 enum i40e_status_code status;
6307 u32 max_bw_addr, min_bw_addr;
6309 /* Calculate the address of the min/max bw registers */
6310 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6311 I40E_ALT_STRUCT_MAX_BW_OFFSET +
6312 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6313 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6314 I40E_ALT_STRUCT_MIN_BW_OFFSET +
6315 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6317 /* Read the bandwidths from alt ram */
6318 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
6319 min_bw_addr, min_bw);
6321 if (*min_bw & I40E_ALT_BW_VALID_MASK)
6326 if (*max_bw & I40E_ALT_BW_VALID_MASK)
6335 * i40e_aq_configure_partition_bw
6336 * @hw: pointer to the hardware structure
6337 * @bw_data: Buffer holding valid pfs and bw limits
6338 * @cmd_details: pointer to command details
6340 * Configure partitions guaranteed/max bw
6342 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6343 struct i40e_aqc_configure_partition_bw_data *bw_data,
6344 struct i40e_asq_cmd_details *cmd_details)
6346 enum i40e_status_code status;
6347 struct i40e_aq_desc desc;
6348 u16 bwd_size = sizeof(*bw_data);
6350 i40e_fill_default_direct_cmd_desc(&desc,
6351 i40e_aqc_opc_configure_partition_bw);
6353 /* Indirect command */
6354 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6355 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6357 desc.datalen = CPU_TO_LE16(bwd_size);
6359 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6365 * i40e_read_phy_register_clause22
6366 * @hw: pointer to the HW structure
6367 * @reg: register address in the page
6368 * @phy_addr: PHY address on MDIO interface
6369 * @value: PHY register value
6371 * Reads specified PHY register value
6373 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
6374 u16 reg, u8 phy_addr, u16 *value)
6376 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6377 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6381 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6382 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6383 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
6384 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6385 (I40E_GLGEN_MSCA_MDICMD_MASK);
6386 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6388 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6389 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6390 status = I40E_SUCCESS;
6393 i40e_usec_delay(10);
6398 i40e_debug(hw, I40E_DEBUG_PHY,
6399 "PHY: Can't write command to external PHY.\n");
6401 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6402 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6403 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6410 * i40e_write_phy_register_clause22
6411 * @hw: pointer to the HW structure
6412 * @reg: register address in the page
6413 * @phy_addr: PHY address on MDIO interface
6414 * @value: PHY register value
6416 * Writes specified PHY register value
6418 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6419 u16 reg, u8 phy_addr, u16 value)
6421 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6422 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6426 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6427 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6429 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6430 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6431 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6432 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6433 (I40E_GLGEN_MSCA_MDICMD_MASK);
6435 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6437 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6438 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6439 status = I40E_SUCCESS;
6442 i40e_usec_delay(10);
6450 * i40e_read_phy_register_clause45
6451 * @hw: pointer to the HW structure
6452 * @page: registers page number
6453 * @reg: register address in the page
6454 * @phy_addr: PHY address on MDIO interface
6455 * @value: PHY register value
6457 * Reads specified PHY register value
6459 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6460 u8 page, u16 reg, u8 phy_addr, u16 *value)
6462 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6465 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6467 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6468 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6469 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6470 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6471 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6472 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6473 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6474 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6476 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6477 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6478 status = I40E_SUCCESS;
6481 i40e_usec_delay(10);
6486 i40e_debug(hw, I40E_DEBUG_PHY,
6487 "PHY: Can't write command to external PHY.\n");
6491 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6492 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6493 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6494 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6495 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6496 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6497 status = I40E_ERR_TIMEOUT;
6499 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6501 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6502 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6503 status = I40E_SUCCESS;
6506 i40e_usec_delay(10);
6511 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6512 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6513 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6515 i40e_debug(hw, I40E_DEBUG_PHY,
6516 "PHY: Can't read register value from external PHY.\n");
6524 * i40e_write_phy_register_clause45
6525 * @hw: pointer to the HW structure
6526 * @page: registers page number
6527 * @reg: register address in the page
6528 * @phy_addr: PHY address on MDIO interface
6529 * @value: PHY register value
6531 * Writes value to specified PHY register
6533 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6534 u8 page, u16 reg, u8 phy_addr, u16 value)
6536 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6539 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6541 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6542 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6543 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6544 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6545 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6546 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6547 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6548 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6550 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6551 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6552 status = I40E_SUCCESS;
6555 i40e_usec_delay(10);
6559 i40e_debug(hw, I40E_DEBUG_PHY,
6560 "PHY: Can't write command to external PHY.\n");
6564 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6565 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6567 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6568 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6569 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6570 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6571 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6572 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6573 status = I40E_ERR_TIMEOUT;
6575 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6577 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6578 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6579 status = I40E_SUCCESS;
6582 i40e_usec_delay(10);
6591 * i40e_write_phy_register
6592 * @hw: pointer to the HW structure
6593 * @page: registers page number
6594 * @reg: register address in the page
6595 * @phy_addr: PHY address on MDIO interface
6596 * @value: PHY register value
6598 * Writes value to specified PHY register
6600 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6601 u8 page, u16 reg, u8 phy_addr, u16 value)
6603 enum i40e_status_code status;
6605 switch (hw->device_id) {
6606 case I40E_DEV_ID_1G_BASE_T_X722:
6607 status = i40e_write_phy_register_clause22(hw,
6608 reg, phy_addr, value);
6610 case I40E_DEV_ID_10G_BASE_T:
6611 case I40E_DEV_ID_10G_BASE_T4:
6612 case I40E_DEV_ID_10G_BASE_T_X722:
6613 case I40E_DEV_ID_25G_B:
6614 case I40E_DEV_ID_25G_SFP28:
6615 status = i40e_write_phy_register_clause45(hw,
6616 page, reg, phy_addr, value);
6619 status = I40E_ERR_UNKNOWN_PHY;
6627 * i40e_read_phy_register
6628 * @hw: pointer to the HW structure
6629 * @page: registers page number
6630 * @reg: register address in the page
6631 * @phy_addr: PHY address on MDIO interface
6632 * @value: PHY register value
6634 * Reads specified PHY register value
6636 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6637 u8 page, u16 reg, u8 phy_addr, u16 *value)
6639 enum i40e_status_code status;
6641 switch (hw->device_id) {
6642 case I40E_DEV_ID_1G_BASE_T_X722:
6643 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6646 case I40E_DEV_ID_10G_BASE_T:
6647 case I40E_DEV_ID_10G_BASE_T4:
6648 case I40E_DEV_ID_10G_BASE_T_X722:
6649 case I40E_DEV_ID_25G_B:
6650 case I40E_DEV_ID_25G_SFP28:
6651 status = i40e_read_phy_register_clause45(hw, page, reg,
6655 status = I40E_ERR_UNKNOWN_PHY;
6663 * i40e_get_phy_address
6664 * @hw: pointer to the HW structure
6665 * @dev_num: PHY port num that address we want
6667 * Gets PHY address for current port
6669 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6671 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6672 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6674 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6678 * i40e_blink_phy_led
6679 * @hw: pointer to the HW structure
6680 * @time: time how long led will blinks in secs
6681 * @interval: gap between LED on and off in msecs
6683 * Blinks PHY link LED
6685 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6686 u32 time, u32 interval)
6688 enum i40e_status_code status = I40E_SUCCESS;
6693 u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6697 i = rd32(hw, I40E_PFGEN_PORTNUM);
6698 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6699 phy_addr = i40e_get_phy_address(hw, port_num);
6701 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6703 status = i40e_read_phy_register_clause45(hw,
6704 I40E_PHY_COM_REG_PAGE,
6708 goto phy_blinking_end;
6710 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6712 status = i40e_write_phy_register_clause45(hw,
6713 I40E_PHY_COM_REG_PAGE,
6717 goto phy_blinking_end;
6722 if (time > 0 && interval > 0) {
6723 for (i = 0; i < time * 1000; i += interval) {
6724 status = i40e_read_phy_register_clause45(hw,
6725 I40E_PHY_COM_REG_PAGE,
6726 led_addr, phy_addr, &led_reg);
6728 goto restore_config;
6729 if (led_reg & I40E_PHY_LED_MANUAL_ON)
6732 led_reg = I40E_PHY_LED_MANUAL_ON;
6733 status = i40e_write_phy_register_clause45(hw,
6734 I40E_PHY_COM_REG_PAGE,
6735 led_addr, phy_addr, led_reg);
6737 goto restore_config;
6738 i40e_msec_delay(interval);
6743 status = i40e_write_phy_register_clause45(hw,
6744 I40E_PHY_COM_REG_PAGE,
6745 led_addr, phy_addr, led_ctl);
6752 * i40e_led_get_reg - read LED register
6753 * @hw: pointer to the HW structure
6754 * @led_addr: LED register address
6755 * @reg_val: read register value
6757 static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr,
6760 enum i40e_status_code status;
6764 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6765 status = i40e_aq_get_phy_register(hw,
6766 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6767 I40E_PHY_COM_REG_PAGE,
6768 I40E_PHY_LED_PROV_REG_1,
6771 phy_addr = i40e_get_phy_address(hw, hw->port);
6772 status = i40e_read_phy_register_clause45(hw,
6773 I40E_PHY_COM_REG_PAGE,
6781 * i40e_led_set_reg - write LED register
6782 * @hw: pointer to the HW structure
6783 * @led_addr: LED register address
6784 * @reg_val: register value to write
6786 static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr,
6789 enum i40e_status_code status;
6792 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6793 status = i40e_aq_set_phy_register(hw,
6794 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6795 I40E_PHY_COM_REG_PAGE,
6796 I40E_PHY_LED_PROV_REG_1,
6799 phy_addr = i40e_get_phy_address(hw, hw->port);
6800 status = i40e_write_phy_register_clause45(hw,
6801 I40E_PHY_COM_REG_PAGE,
6810 * i40e_led_get_phy - return current on/off mode
6811 * @hw: pointer to the hw struct
6812 * @led_addr: address of led register to use
6813 * @val: original value of register to use
6816 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6819 enum i40e_status_code status = I40E_SUCCESS;
6826 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6827 status = i40e_aq_get_phy_register(hw,
6828 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6829 I40E_PHY_COM_REG_PAGE,
6830 I40E_PHY_LED_PROV_REG_1,
6832 if (status == I40E_SUCCESS)
6833 *val = (u16)reg_val_aq;
6836 temp_addr = I40E_PHY_LED_PROV_REG_1;
6837 phy_addr = i40e_get_phy_address(hw, hw->port);
6838 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6840 status = i40e_read_phy_register_clause45(hw,
6841 I40E_PHY_COM_REG_PAGE,
6842 temp_addr, phy_addr,
6847 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6848 *led_addr = temp_addr;
6857 * @hw: pointer to the HW structure
6858 * @on: true or false
6859 * @led_addr: address of led register to use
6860 * @mode: original val plus bit for set or ignore
6862 * Set led's on or off when controlled by the PHY
6865 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6866 u16 led_addr, u32 mode)
6868 enum i40e_status_code status = I40E_SUCCESS;
6872 status = i40e_led_get_reg(hw, led_addr, &led_reg);
6876 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6878 status = i40e_led_set_reg(hw, led_addr, led_reg);
6882 status = i40e_led_get_reg(hw, led_addr, &led_reg);
6884 goto restore_config;
6886 led_reg = I40E_PHY_LED_MANUAL_ON;
6889 status = i40e_led_set_reg(hw, led_addr, led_reg);
6891 goto restore_config;
6892 if (mode & I40E_PHY_LED_MODE_ORIG) {
6893 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6894 status = i40e_led_set_reg(hw, led_addr, led_ctl);
6899 status = i40e_led_set_reg(hw, led_addr, led_ctl);
6902 #endif /* PF_DRIVER */
6905 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6906 * @hw: pointer to the hw struct
6907 * @reg_addr: register address
6908 * @reg_val: ptr to register value
6909 * @cmd_details: pointer to command details structure or NULL
6911 * Use the firmware to read the Rx control register,
6912 * especially useful if the Rx unit is under heavy pressure
6914 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6915 u32 reg_addr, u32 *reg_val,
6916 struct i40e_asq_cmd_details *cmd_details)
6918 struct i40e_aq_desc desc;
6919 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
6920 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6921 enum i40e_status_code status;
6923 if (reg_val == NULL)
6924 return I40E_ERR_PARAM;
6926 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
6928 cmd_resp->address = CPU_TO_LE32(reg_addr);
6930 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6932 if (status == I40E_SUCCESS)
6933 *reg_val = LE32_TO_CPU(cmd_resp->value);
6939 * i40e_read_rx_ctl - read from an Rx control register
6940 * @hw: pointer to the hw struct
6941 * @reg_addr: register address
6943 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
6945 enum i40e_status_code status = I40E_SUCCESS;
6950 use_register = (((hw->aq.api_maj_ver == 1) &&
6951 (hw->aq.api_min_ver < 5)) ||
6952 (hw->mac.type == I40E_MAC_X722));
6953 if (!use_register) {
6955 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
6956 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6963 /* if the AQ access failed, try the old-fashioned way */
6964 if (status || use_register)
6965 val = rd32(hw, reg_addr);
6971 * i40e_aq_rx_ctl_write_register
6972 * @hw: pointer to the hw struct
6973 * @reg_addr: register address
6974 * @reg_val: register value
6975 * @cmd_details: pointer to command details structure or NULL
6977 * Use the firmware to write to an Rx control register,
6978 * especially useful if the Rx unit is under heavy pressure
6980 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
6981 u32 reg_addr, u32 reg_val,
6982 struct i40e_asq_cmd_details *cmd_details)
6984 struct i40e_aq_desc desc;
6985 struct i40e_aqc_rx_ctl_reg_read_write *cmd =
6986 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6987 enum i40e_status_code status;
6989 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
6991 cmd->address = CPU_TO_LE32(reg_addr);
6992 cmd->value = CPU_TO_LE32(reg_val);
6994 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7000 * i40e_write_rx_ctl - write to an Rx control register
7001 * @hw: pointer to the hw struct
7002 * @reg_addr: register address
7003 * @reg_val: register value
7005 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
7007 enum i40e_status_code status = I40E_SUCCESS;
7011 use_register = (((hw->aq.api_maj_ver == 1) &&
7012 (hw->aq.api_min_ver < 5)) ||
7013 (hw->mac.type == I40E_MAC_X722));
7014 if (!use_register) {
7016 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
7018 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
7025 /* if the AQ access failed, try the old-fashioned way */
7026 if (status || use_register)
7027 wr32(hw, reg_addr, reg_val);
7031 * i40e_aq_set_phy_register
7032 * @hw: pointer to the hw struct
7033 * @phy_select: select which phy should be accessed
7034 * @dev_addr: PHY device address
7035 * @reg_addr: PHY register address
7036 * @reg_val: new register value
7037 * @cmd_details: pointer to command details structure or NULL
7039 * Write the external PHY register.
7041 enum i40e_status_code i40e_aq_set_phy_register(struct i40e_hw *hw,
7042 u8 phy_select, u8 dev_addr,
7043 u32 reg_addr, u32 reg_val,
7044 struct i40e_asq_cmd_details *cmd_details)
7046 struct i40e_aq_desc desc;
7047 struct i40e_aqc_phy_register_access *cmd =
7048 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7049 enum i40e_status_code status;
7051 i40e_fill_default_direct_cmd_desc(&desc,
7052 i40e_aqc_opc_set_phy_register);
7054 cmd->phy_interface = phy_select;
7055 cmd->dev_addres = dev_addr;
7056 cmd->reg_address = CPU_TO_LE32(reg_addr);
7057 cmd->reg_value = CPU_TO_LE32(reg_val);
7059 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7065 * i40e_aq_get_phy_register
7066 * @hw: pointer to the hw struct
7067 * @phy_select: select which phy should be accessed
7068 * @dev_addr: PHY device address
7069 * @reg_addr: PHY register address
7070 * @reg_val: read register value
7071 * @cmd_details: pointer to command details structure or NULL
7073 * Read the external PHY register.
7075 enum i40e_status_code i40e_aq_get_phy_register(struct i40e_hw *hw,
7076 u8 phy_select, u8 dev_addr,
7077 u32 reg_addr, u32 *reg_val,
7078 struct i40e_asq_cmd_details *cmd_details)
7080 struct i40e_aq_desc desc;
7081 struct i40e_aqc_phy_register_access *cmd =
7082 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7083 enum i40e_status_code status;
7085 i40e_fill_default_direct_cmd_desc(&desc,
7086 i40e_aqc_opc_get_phy_register);
7088 cmd->phy_interface = phy_select;
7089 cmd->dev_addres = dev_addr;
7090 cmd->reg_address = CPU_TO_LE32(reg_addr);
7092 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7094 *reg_val = LE32_TO_CPU(cmd->reg_value);
7102 * i40e_aq_send_msg_to_pf
7103 * @hw: pointer to the hardware structure
7104 * @v_opcode: opcodes for VF-PF communication
7105 * @v_retval: return error code
7106 * @msg: pointer to the msg buffer
7107 * @msglen: msg length
7108 * @cmd_details: pointer to command details
7110 * Send message to PF driver using admin queue. By default, this message
7111 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
7112 * completion before returning.
7114 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
7115 enum virtchnl_ops v_opcode,
7116 enum i40e_status_code v_retval,
7117 u8 *msg, u16 msglen,
7118 struct i40e_asq_cmd_details *cmd_details)
7120 struct i40e_aq_desc desc;
7121 struct i40e_asq_cmd_details details;
7122 enum i40e_status_code status;
7124 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
7125 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
7126 desc.cookie_high = CPU_TO_LE32(v_opcode);
7127 desc.cookie_low = CPU_TO_LE32(v_retval);
7129 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
7130 | I40E_AQ_FLAG_RD));
7131 if (msglen > I40E_AQ_LARGE_BUF)
7132 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7133 desc.datalen = CPU_TO_LE16(msglen);
7136 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
7137 details.async = true;
7138 cmd_details = &details;
7140 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
7141 msglen, cmd_details);
7146 * i40e_vf_parse_hw_config
7147 * @hw: pointer to the hardware structure
7148 * @msg: pointer to the virtual channel VF resource structure
7150 * Given a VF resource message from the PF, populate the hw struct
7151 * with appropriate information.
7153 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
7154 struct virtchnl_vf_resource *msg)
7156 struct virtchnl_vsi_resource *vsi_res;
7159 vsi_res = &msg->vsi_res[0];
7161 hw->dev_caps.num_vsis = msg->num_vsis;
7162 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
7163 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
7164 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
7165 hw->dev_caps.dcb = msg->vf_cap_flags &
7166 VIRTCHNL_VF_OFFLOAD_L2;
7167 hw->dev_caps.iwarp = (msg->vf_cap_flags &
7168 VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
7169 for (i = 0; i < msg->num_vsis; i++) {
7170 if (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) {
7171 i40e_memcpy(hw->mac.perm_addr,
7172 vsi_res->default_mac_addr,
7174 I40E_NONDMA_TO_NONDMA);
7175 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
7177 I40E_NONDMA_TO_NONDMA);
7185 * @hw: pointer to the hardware structure
7187 * Send a VF_RESET message to the PF. Does not wait for response from PF
7188 * as none will be forthcoming. Immediately after calling this function,
7189 * the admin queue should be shut down and (optionally) reinitialized.
7191 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
7193 return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF,
7194 I40E_SUCCESS, NULL, 0, NULL);
7196 #endif /* VF_DRIVER */
7199 * i40e_aq_set_arp_proxy_config
7200 * @hw: pointer to the HW structure
7201 * @proxy_config: pointer to proxy config command table struct
7202 * @cmd_details: pointer to command details
7204 * Set ARP offload parameters from pre-populated
7205 * i40e_aqc_arp_proxy_data struct
7207 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
7208 struct i40e_aqc_arp_proxy_data *proxy_config,
7209 struct i40e_asq_cmd_details *cmd_details)
7211 struct i40e_aq_desc desc;
7212 enum i40e_status_code status;
7215 return I40E_ERR_PARAM;
7217 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
7219 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7220 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7221 desc.params.external.addr_high =
7222 CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
7223 desc.params.external.addr_low =
7224 CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
7225 desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_arp_proxy_data));
7227 status = i40e_asq_send_command(hw, &desc, proxy_config,
7228 sizeof(struct i40e_aqc_arp_proxy_data),
7235 * i40e_aq_opc_set_ns_proxy_table_entry
7236 * @hw: pointer to the HW structure
7237 * @ns_proxy_table_entry: pointer to NS table entry command struct
7238 * @cmd_details: pointer to command details
7240 * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
7241 * from pre-populated i40e_aqc_ns_proxy_data struct
7243 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
7244 struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
7245 struct i40e_asq_cmd_details *cmd_details)
7247 struct i40e_aq_desc desc;
7248 enum i40e_status_code status;
7250 if (!ns_proxy_table_entry)
7251 return I40E_ERR_PARAM;
7253 i40e_fill_default_direct_cmd_desc(&desc,
7254 i40e_aqc_opc_set_ns_proxy_table_entry);
7256 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7257 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7258 desc.params.external.addr_high =
7259 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
7260 desc.params.external.addr_low =
7261 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
7262 desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_ns_proxy_data));
7264 status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
7265 sizeof(struct i40e_aqc_ns_proxy_data),
7272 * i40e_aq_set_clear_wol_filter
7273 * @hw: pointer to the hw struct
7274 * @filter_index: index of filter to modify (0-7)
7275 * @filter: buffer containing filter to be set
7276 * @set_filter: true to set filter, false to clear filter
7277 * @no_wol_tco: if true, pass through packets cannot cause wake-up
7278 * if false, pass through packets may cause wake-up
7279 * @filter_valid: true if filter action is valid
7280 * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
7281 * @cmd_details: pointer to command details structure or NULL
7283 * Set or clear WoL filter for port attached to the PF
7285 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
7287 struct i40e_aqc_set_wol_filter_data *filter,
7288 bool set_filter, bool no_wol_tco,
7289 bool filter_valid, bool no_wol_tco_valid,
7290 struct i40e_asq_cmd_details *cmd_details)
7292 struct i40e_aq_desc desc;
7293 struct i40e_aqc_set_wol_filter *cmd =
7294 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
7295 enum i40e_status_code status;
7297 u16 valid_flags = 0;
7300 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
7302 if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
7303 return I40E_ERR_PARAM;
7304 cmd->filter_index = CPU_TO_LE16(filter_index);
7308 return I40E_ERR_PARAM;
7310 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
7311 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR;
7315 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
7316 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
7319 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
7320 if (no_wol_tco_valid)
7321 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
7322 cmd->valid_flags = CPU_TO_LE16(valid_flags);
7324 buff_len = sizeof(*filter);
7325 desc.datalen = CPU_TO_LE16(buff_len);
7327 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7328 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7330 cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
7331 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
7333 status = i40e_asq_send_command(hw, &desc, filter,
7334 buff_len, cmd_details);
7340 * i40e_aq_get_wake_event_reason
7341 * @hw: pointer to the hw struct
7342 * @wake_reason: return value, index of matching filter
7343 * @cmd_details: pointer to command details structure or NULL
7345 * Get information for the reason of a Wake Up event
7347 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
7349 struct i40e_asq_cmd_details *cmd_details)
7351 struct i40e_aq_desc desc;
7352 struct i40e_aqc_get_wake_reason_completion *resp =
7353 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
7354 enum i40e_status_code status;
7356 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
7358 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7360 if (status == I40E_SUCCESS)
7361 *wake_reason = LE16_TO_CPU(resp->wake_reason);
7367 * i40e_aq_clear_all_wol_filters
7368 * @hw: pointer to the hw struct
7369 * @cmd_details: pointer to command details structure or NULL
7371 * Get information for the reason of a Wake Up event
7373 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw,
7374 struct i40e_asq_cmd_details *cmd_details)
7376 struct i40e_aq_desc desc;
7377 enum i40e_status_code status;
7379 i40e_fill_default_direct_cmd_desc(&desc,
7380 i40e_aqc_opc_clear_all_wol_filters);
7382 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7388 * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
7389 * @hw: pointer to the hw struct
7390 * @buff: command buffer (size in bytes = buff_size)
7391 * @buff_size: buffer size in bytes
7392 * @track_id: package tracking id
7393 * @error_offset: returns error offset
7394 * @error_info: returns error information
7395 * @cmd_details: pointer to command details structure or NULL
7398 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
7399 u16 buff_size, u32 track_id,
7400 u32 *error_offset, u32 *error_info,
7401 struct i40e_asq_cmd_details *cmd_details)
7403 struct i40e_aq_desc desc;
7404 struct i40e_aqc_write_personalization_profile *cmd =
7405 (struct i40e_aqc_write_personalization_profile *)
7407 struct i40e_aqc_write_ddp_resp *resp;
7408 enum i40e_status_code status;
7410 i40e_fill_default_direct_cmd_desc(&desc,
7411 i40e_aqc_opc_write_personalization_profile);
7413 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
7414 if (buff_size > I40E_AQ_LARGE_BUF)
7415 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7417 desc.datalen = CPU_TO_LE16(buff_size);
7419 cmd->profile_track_id = CPU_TO_LE32(track_id);
7421 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7423 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
7425 *error_offset = LE32_TO_CPU(resp->error_offset);
7427 *error_info = LE32_TO_CPU(resp->error_info);
7434 * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
7435 * @hw: pointer to the hw struct
7436 * @buff: command buffer (size in bytes = buff_size)
7437 * @buff_size: buffer size in bytes
7438 * @flags: AdminQ command flags
7439 * @cmd_details: pointer to command details structure or NULL
7442 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
7443 u16 buff_size, u8 flags,
7444 struct i40e_asq_cmd_details *cmd_details)
7446 struct i40e_aq_desc desc;
7447 struct i40e_aqc_get_applied_profiles *cmd =
7448 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
7449 enum i40e_status_code status;
7451 i40e_fill_default_direct_cmd_desc(&desc,
7452 i40e_aqc_opc_get_personalization_profile_list);
7454 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7455 if (buff_size > I40E_AQ_LARGE_BUF)
7456 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7457 desc.datalen = CPU_TO_LE16(buff_size);
7461 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7467 * i40e_find_segment_in_package
7468 * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
7469 * @pkg_hdr: pointer to the package header to be searched
7471 * This function searches a package file for a particular segment type. On
7472 * success it returns a pointer to the segment header, otherwise it will
7475 struct i40e_generic_seg_header *
7476 i40e_find_segment_in_package(u32 segment_type,
7477 struct i40e_package_header *pkg_hdr)
7479 struct i40e_generic_seg_header *segment;
7482 /* Search all package segments for the requested segment type */
7483 for (i = 0; i < pkg_hdr->segment_count; i++) {
7485 (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
7486 pkg_hdr->segment_offset[i]);
7488 if (segment->type == segment_type)
7495 /* Get section table in profile */
7496 #define I40E_SECTION_TABLE(profile, sec_tbl) \
7498 struct i40e_profile_segment *p = (profile); \
7501 count = p->device_table_count; \
7502 nvm = (u32 *)&p->device_table[count]; \
7503 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \
7506 /* Get section header in profile */
7507 #define I40E_SECTION_HEADER(profile, offset) \
7508 (struct i40e_profile_section_header *)((u8 *)(profile) + (offset))
7511 * i40e_find_section_in_profile
7512 * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE)
7513 * @profile: pointer to the i40e segment header to be searched
7515 * This function searches i40e segment for a particular section type. On
7516 * success it returns a pointer to the section header, otherwise it will
7519 struct i40e_profile_section_header *
7520 i40e_find_section_in_profile(u32 section_type,
7521 struct i40e_profile_segment *profile)
7523 struct i40e_profile_section_header *sec;
7524 struct i40e_section_table *sec_tbl;
7528 if (profile->header.type != SEGMENT_TYPE_I40E)
7531 I40E_SECTION_TABLE(profile, sec_tbl);
7533 for (i = 0; i < sec_tbl->section_count; i++) {
7534 sec_off = sec_tbl->section_offset[i];
7535 sec = I40E_SECTION_HEADER(profile, sec_off);
7536 if (sec->section.type == section_type)
7544 * i40e_ddp_exec_aq_section - Execute generic AQ for DDP
7545 * @hw: pointer to the hw struct
7546 * @aq: command buffer containing all data to execute AQ
7549 i40e_status_code i40e_ddp_exec_aq_section(struct i40e_hw *hw,
7550 struct i40e_profile_aq_section *aq)
7552 enum i40e_status_code status;
7553 struct i40e_aq_desc desc;
7557 i40e_fill_default_direct_cmd_desc(&desc, aq->opcode);
7558 desc.flags |= CPU_TO_LE16(aq->flags);
7559 i40e_memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw),
7560 I40E_NONDMA_TO_NONDMA);
7562 msglen = aq->datalen;
7564 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
7566 if (msglen > I40E_AQ_LARGE_BUF)
7567 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7568 desc.datalen = CPU_TO_LE16(msglen);
7572 status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL);
7574 if (status != I40E_SUCCESS) {
7575 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7576 "unable to exec DDP AQ opcode %u, error %d\n",
7577 aq->opcode, status);
7581 /* copy returned desc to aq_buf */
7582 i40e_memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw),
7583 I40E_NONDMA_TO_NONDMA);
7585 return I40E_SUCCESS;
7589 * i40e_validate_profile
7590 * @hw: pointer to the hardware structure
7591 * @profile: pointer to the profile segment of the package to be validated
7592 * @track_id: package tracking id
7593 * @rollback: flag if the profile is for rollback.
7595 * Validates supported devices and profile's sections.
7597 STATIC enum i40e_status_code
7598 i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7599 u32 track_id, bool rollback)
7601 struct i40e_profile_section_header *sec = NULL;
7602 enum i40e_status_code status = I40E_SUCCESS;
7603 struct i40e_section_table *sec_tbl;
7609 if (track_id == I40E_DDP_TRACKID_INVALID) {
7610 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n");
7611 return I40E_NOT_SUPPORTED;
7614 dev_cnt = profile->device_table_count;
7615 for (i = 0; i < dev_cnt; i++) {
7616 vendor_dev_id = profile->device_table[i].vendor_dev_id;
7617 if ((vendor_dev_id >> 16) == I40E_INTEL_VENDOR_ID &&
7618 hw->device_id == (vendor_dev_id & 0xFFFF))
7621 if (dev_cnt && (i == dev_cnt)) {
7622 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7623 "Device doesn't support DDP\n");
7624 return I40E_ERR_DEVICE_NOT_SUPPORTED;
7627 I40E_SECTION_TABLE(profile, sec_tbl);
7629 /* Validate sections types */
7630 for (i = 0; i < sec_tbl->section_count; i++) {
7631 sec_off = sec_tbl->section_offset[i];
7632 sec = I40E_SECTION_HEADER(profile, sec_off);
7634 if (sec->section.type == SECTION_TYPE_MMIO ||
7635 sec->section.type == SECTION_TYPE_AQ ||
7636 sec->section.type == SECTION_TYPE_RB_AQ) {
7637 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7638 "Not a roll-back package\n");
7639 return I40E_NOT_SUPPORTED;
7642 if (sec->section.type == SECTION_TYPE_RB_AQ ||
7643 sec->section.type == SECTION_TYPE_RB_MMIO) {
7644 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7645 "Not an original package\n");
7646 return I40E_NOT_SUPPORTED;
7655 * i40e_write_profile
7656 * @hw: pointer to the hardware structure
7657 * @profile: pointer to the profile segment of the package to be downloaded
7658 * @track_id: package tracking id
7660 * Handles the download of a complete package.
7662 enum i40e_status_code
7663 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7666 enum i40e_status_code status = I40E_SUCCESS;
7667 struct i40e_section_table *sec_tbl;
7668 struct i40e_profile_section_header *sec = NULL;
7669 struct i40e_profile_aq_section *ddp_aq;
7670 u32 section_size = 0;
7671 u32 offset = 0, info = 0;
7675 status = i40e_validate_profile(hw, profile, track_id, false);
7679 I40E_SECTION_TABLE(profile, sec_tbl);
7681 for (i = 0; i < sec_tbl->section_count; i++) {
7682 sec_off = sec_tbl->section_offset[i];
7683 sec = I40E_SECTION_HEADER(profile, sec_off);
7684 /* Process generic admin command */
7685 if (sec->section.type == SECTION_TYPE_AQ) {
7686 ddp_aq = (struct i40e_profile_aq_section *)&sec[1];
7687 status = i40e_ddp_exec_aq_section(hw, ddp_aq);
7689 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7690 "Failed to execute aq: section %d, opcode %u\n",
7694 sec->section.type = SECTION_TYPE_RB_AQ;
7697 /* Skip any non-mmio sections */
7698 if (sec->section.type != SECTION_TYPE_MMIO)
7701 section_size = sec->section.size +
7702 sizeof(struct i40e_profile_section_header);
7704 /* Write MMIO section */
7705 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
7706 track_id, &offset, &info, NULL);
7708 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7709 "Failed to write profile: section %d, offset %d, info %d\n",
7718 * i40e_rollback_profile
7719 * @hw: pointer to the hardware structure
7720 * @profile: pointer to the profile segment of the package to be removed
7721 * @track_id: package tracking id
7723 * Rolls back previously loaded package.
7725 enum i40e_status_code
7726 i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7729 struct i40e_profile_section_header *sec = NULL;
7730 enum i40e_status_code status = I40E_SUCCESS;
7731 struct i40e_section_table *sec_tbl;
7732 u32 offset = 0, info = 0;
7733 u32 section_size = 0;
7737 status = i40e_validate_profile(hw, profile, track_id, true);
7741 I40E_SECTION_TABLE(profile, sec_tbl);
7743 /* For rollback write sections in reverse */
7744 for (i = sec_tbl->section_count - 1; i >= 0; i--) {
7745 sec_off = sec_tbl->section_offset[i];
7746 sec = I40E_SECTION_HEADER(profile, sec_off);
7748 /* Skip any non-rollback sections */
7749 if (sec->section.type != SECTION_TYPE_RB_MMIO)
7752 section_size = sec->section.size +
7753 sizeof(struct i40e_profile_section_header);
7755 /* Write roll-back MMIO section */
7756 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
7757 track_id, &offset, &info, NULL);
7759 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7760 "Failed to write profile: section %d, offset %d, info %d\n",
7769 * i40e_add_pinfo_to_list
7770 * @hw: pointer to the hardware structure
7771 * @profile: pointer to the profile segment of the package
7772 * @profile_info_sec: buffer for information section
7773 * @track_id: package tracking id
7775 * Register a profile to the list of loaded profiles.
7777 enum i40e_status_code
7778 i40e_add_pinfo_to_list(struct i40e_hw *hw,
7779 struct i40e_profile_segment *profile,
7780 u8 *profile_info_sec, u32 track_id)
7782 enum i40e_status_code status = I40E_SUCCESS;
7783 struct i40e_profile_section_header *sec = NULL;
7784 struct i40e_profile_info *pinfo;
7785 u32 offset = 0, info = 0;
7787 sec = (struct i40e_profile_section_header *)profile_info_sec;
7789 sec->data_end = sizeof(struct i40e_profile_section_header) +
7790 sizeof(struct i40e_profile_info);
7791 sec->section.type = SECTION_TYPE_INFO;
7792 sec->section.offset = sizeof(struct i40e_profile_section_header);
7793 sec->section.size = sizeof(struct i40e_profile_info);
7794 pinfo = (struct i40e_profile_info *)(profile_info_sec +
7795 sec->section.offset);
7796 pinfo->track_id = track_id;
7797 pinfo->version = profile->version;
7798 pinfo->op = I40E_DDP_ADD_TRACKID;
7799 i40e_memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE,
7800 I40E_NONDMA_TO_NONDMA);
7802 status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
7803 track_id, &offset, &info, NULL);