1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "i40e_type.h"
35 #include "i40e_adminq.h"
36 #include "i40e_prototype.h"
41 * i40e_set_mac_type - Sets MAC type
42 * @hw: pointer to the HW structure
44 * This function sets the mac type of the adapter based on the
45 * vendor ID and device ID stored in the hw structure.
47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
53 enum i40e_status_code status = I40E_SUCCESS;
55 DEBUGFUNC("i40e_set_mac_type\n");
57 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
58 switch (hw->device_id) {
59 case I40E_DEV_ID_SFP_XL710:
60 case I40E_DEV_ID_QEMU:
61 case I40E_DEV_ID_KX_B:
62 case I40E_DEV_ID_KX_C:
63 case I40E_DEV_ID_QSFP_A:
64 case I40E_DEV_ID_QSFP_B:
65 case I40E_DEV_ID_QSFP_C:
66 case I40E_DEV_ID_10G_BASE_T:
67 case I40E_DEV_ID_10G_BASE_T4:
68 case I40E_DEV_ID_20G_KR2:
69 case I40E_DEV_ID_20G_KR2_A:
70 case I40E_DEV_ID_25G_B:
71 case I40E_DEV_ID_25G_SFP28:
72 hw->mac.type = I40E_MAC_XL710;
74 #ifdef X722_A0_SUPPORT
75 case I40E_DEV_ID_X722_A0:
77 case I40E_DEV_ID_KX_X722:
78 case I40E_DEV_ID_QSFP_X722:
79 case I40E_DEV_ID_SFP_X722:
80 case I40E_DEV_ID_1G_BASE_T_X722:
81 case I40E_DEV_ID_10G_BASE_T_X722:
82 case I40E_DEV_ID_SFP_I_X722:
83 hw->mac.type = I40E_MAC_X722;
85 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
86 case I40E_DEV_ID_X722_VF:
87 #ifdef X722_A0_SUPPORT
88 case I40E_DEV_ID_X722_A0_VF:
90 hw->mac.type = I40E_MAC_X722_VF;
92 #endif /* INTEGRATED_VF || VF_DRIVER */
93 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
95 case I40E_DEV_ID_VF_HV:
96 case I40E_DEV_ID_ADAPTIVE_VF:
97 hw->mac.type = I40E_MAC_VF;
101 hw->mac.type = I40E_MAC_GENERIC;
105 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
108 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
109 hw->mac.type, status);
114 * i40e_aq_str - convert AQ err code to a string
115 * @hw: pointer to the HW structure
116 * @aq_err: the AQ error code to convert
118 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
123 case I40E_AQ_RC_EPERM:
124 return "I40E_AQ_RC_EPERM";
125 case I40E_AQ_RC_ENOENT:
126 return "I40E_AQ_RC_ENOENT";
127 case I40E_AQ_RC_ESRCH:
128 return "I40E_AQ_RC_ESRCH";
129 case I40E_AQ_RC_EINTR:
130 return "I40E_AQ_RC_EINTR";
132 return "I40E_AQ_RC_EIO";
133 case I40E_AQ_RC_ENXIO:
134 return "I40E_AQ_RC_ENXIO";
135 case I40E_AQ_RC_E2BIG:
136 return "I40E_AQ_RC_E2BIG";
137 case I40E_AQ_RC_EAGAIN:
138 return "I40E_AQ_RC_EAGAIN";
139 case I40E_AQ_RC_ENOMEM:
140 return "I40E_AQ_RC_ENOMEM";
141 case I40E_AQ_RC_EACCES:
142 return "I40E_AQ_RC_EACCES";
143 case I40E_AQ_RC_EFAULT:
144 return "I40E_AQ_RC_EFAULT";
145 case I40E_AQ_RC_EBUSY:
146 return "I40E_AQ_RC_EBUSY";
147 case I40E_AQ_RC_EEXIST:
148 return "I40E_AQ_RC_EEXIST";
149 case I40E_AQ_RC_EINVAL:
150 return "I40E_AQ_RC_EINVAL";
151 case I40E_AQ_RC_ENOTTY:
152 return "I40E_AQ_RC_ENOTTY";
153 case I40E_AQ_RC_ENOSPC:
154 return "I40E_AQ_RC_ENOSPC";
155 case I40E_AQ_RC_ENOSYS:
156 return "I40E_AQ_RC_ENOSYS";
157 case I40E_AQ_RC_ERANGE:
158 return "I40E_AQ_RC_ERANGE";
159 case I40E_AQ_RC_EFLUSHED:
160 return "I40E_AQ_RC_EFLUSHED";
161 case I40E_AQ_RC_BAD_ADDR:
162 return "I40E_AQ_RC_BAD_ADDR";
163 case I40E_AQ_RC_EMODE:
164 return "I40E_AQ_RC_EMODE";
165 case I40E_AQ_RC_EFBIG:
166 return "I40E_AQ_RC_EFBIG";
169 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
174 * i40e_stat_str - convert status err code to a string
175 * @hw: pointer to the HW structure
176 * @stat_err: the status error code to convert
178 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
184 return "I40E_ERR_NVM";
185 case I40E_ERR_NVM_CHECKSUM:
186 return "I40E_ERR_NVM_CHECKSUM";
188 return "I40E_ERR_PHY";
189 case I40E_ERR_CONFIG:
190 return "I40E_ERR_CONFIG";
192 return "I40E_ERR_PARAM";
193 case I40E_ERR_MAC_TYPE:
194 return "I40E_ERR_MAC_TYPE";
195 case I40E_ERR_UNKNOWN_PHY:
196 return "I40E_ERR_UNKNOWN_PHY";
197 case I40E_ERR_LINK_SETUP:
198 return "I40E_ERR_LINK_SETUP";
199 case I40E_ERR_ADAPTER_STOPPED:
200 return "I40E_ERR_ADAPTER_STOPPED";
201 case I40E_ERR_INVALID_MAC_ADDR:
202 return "I40E_ERR_INVALID_MAC_ADDR";
203 case I40E_ERR_DEVICE_NOT_SUPPORTED:
204 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
205 case I40E_ERR_MASTER_REQUESTS_PENDING:
206 return "I40E_ERR_MASTER_REQUESTS_PENDING";
207 case I40E_ERR_INVALID_LINK_SETTINGS:
208 return "I40E_ERR_INVALID_LINK_SETTINGS";
209 case I40E_ERR_AUTONEG_NOT_COMPLETE:
210 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
211 case I40E_ERR_RESET_FAILED:
212 return "I40E_ERR_RESET_FAILED";
213 case I40E_ERR_SWFW_SYNC:
214 return "I40E_ERR_SWFW_SYNC";
215 case I40E_ERR_NO_AVAILABLE_VSI:
216 return "I40E_ERR_NO_AVAILABLE_VSI";
217 case I40E_ERR_NO_MEMORY:
218 return "I40E_ERR_NO_MEMORY";
219 case I40E_ERR_BAD_PTR:
220 return "I40E_ERR_BAD_PTR";
221 case I40E_ERR_RING_FULL:
222 return "I40E_ERR_RING_FULL";
223 case I40E_ERR_INVALID_PD_ID:
224 return "I40E_ERR_INVALID_PD_ID";
225 case I40E_ERR_INVALID_QP_ID:
226 return "I40E_ERR_INVALID_QP_ID";
227 case I40E_ERR_INVALID_CQ_ID:
228 return "I40E_ERR_INVALID_CQ_ID";
229 case I40E_ERR_INVALID_CEQ_ID:
230 return "I40E_ERR_INVALID_CEQ_ID";
231 case I40E_ERR_INVALID_AEQ_ID:
232 return "I40E_ERR_INVALID_AEQ_ID";
233 case I40E_ERR_INVALID_SIZE:
234 return "I40E_ERR_INVALID_SIZE";
235 case I40E_ERR_INVALID_ARP_INDEX:
236 return "I40E_ERR_INVALID_ARP_INDEX";
237 case I40E_ERR_INVALID_FPM_FUNC_ID:
238 return "I40E_ERR_INVALID_FPM_FUNC_ID";
239 case I40E_ERR_QP_INVALID_MSG_SIZE:
240 return "I40E_ERR_QP_INVALID_MSG_SIZE";
241 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
242 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
243 case I40E_ERR_INVALID_FRAG_COUNT:
244 return "I40E_ERR_INVALID_FRAG_COUNT";
245 case I40E_ERR_QUEUE_EMPTY:
246 return "I40E_ERR_QUEUE_EMPTY";
247 case I40E_ERR_INVALID_ALIGNMENT:
248 return "I40E_ERR_INVALID_ALIGNMENT";
249 case I40E_ERR_FLUSHED_QUEUE:
250 return "I40E_ERR_FLUSHED_QUEUE";
251 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
252 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
253 case I40E_ERR_INVALID_IMM_DATA_SIZE:
254 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
255 case I40E_ERR_TIMEOUT:
256 return "I40E_ERR_TIMEOUT";
257 case I40E_ERR_OPCODE_MISMATCH:
258 return "I40E_ERR_OPCODE_MISMATCH";
259 case I40E_ERR_CQP_COMPL_ERROR:
260 return "I40E_ERR_CQP_COMPL_ERROR";
261 case I40E_ERR_INVALID_VF_ID:
262 return "I40E_ERR_INVALID_VF_ID";
263 case I40E_ERR_INVALID_HMCFN_ID:
264 return "I40E_ERR_INVALID_HMCFN_ID";
265 case I40E_ERR_BACKING_PAGE_ERROR:
266 return "I40E_ERR_BACKING_PAGE_ERROR";
267 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
268 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
269 case I40E_ERR_INVALID_PBLE_INDEX:
270 return "I40E_ERR_INVALID_PBLE_INDEX";
271 case I40E_ERR_INVALID_SD_INDEX:
272 return "I40E_ERR_INVALID_SD_INDEX";
273 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
274 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
275 case I40E_ERR_INVALID_SD_TYPE:
276 return "I40E_ERR_INVALID_SD_TYPE";
277 case I40E_ERR_MEMCPY_FAILED:
278 return "I40E_ERR_MEMCPY_FAILED";
279 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
280 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
281 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
282 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
283 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
284 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
285 case I40E_ERR_SRQ_ENABLED:
286 return "I40E_ERR_SRQ_ENABLED";
287 case I40E_ERR_ADMIN_QUEUE_ERROR:
288 return "I40E_ERR_ADMIN_QUEUE_ERROR";
289 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
290 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
291 case I40E_ERR_BUF_TOO_SHORT:
292 return "I40E_ERR_BUF_TOO_SHORT";
293 case I40E_ERR_ADMIN_QUEUE_FULL:
294 return "I40E_ERR_ADMIN_QUEUE_FULL";
295 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
296 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
297 case I40E_ERR_BAD_IWARP_CQE:
298 return "I40E_ERR_BAD_IWARP_CQE";
299 case I40E_ERR_NVM_BLANK_MODE:
300 return "I40E_ERR_NVM_BLANK_MODE";
301 case I40E_ERR_NOT_IMPLEMENTED:
302 return "I40E_ERR_NOT_IMPLEMENTED";
303 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
304 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
305 case I40E_ERR_DIAG_TEST_FAILED:
306 return "I40E_ERR_DIAG_TEST_FAILED";
307 case I40E_ERR_NOT_READY:
308 return "I40E_ERR_NOT_READY";
309 case I40E_NOT_SUPPORTED:
310 return "I40E_NOT_SUPPORTED";
311 case I40E_ERR_FIRMWARE_API_VERSION:
312 return "I40E_ERR_FIRMWARE_API_VERSION";
313 case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR:
314 return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR";
317 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
323 * @hw: debug mask related to admin queue
325 * @desc: pointer to admin queue descriptor
326 * @buffer: pointer to command buffer
327 * @buf_len: max length of buffer
329 * Dumps debug log about adminq command with descriptor contents.
331 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
332 void *buffer, u16 buf_len)
334 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
335 u8 *buf = (u8 *)buffer;
339 if ((!(mask & hw->debug_mask)) || (desc == NULL))
342 len = LE16_TO_CPU(aq_desc->datalen);
345 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
346 LE16_TO_CPU(aq_desc->opcode),
347 LE16_TO_CPU(aq_desc->flags),
348 LE16_TO_CPU(aq_desc->datalen),
349 LE16_TO_CPU(aq_desc->retval));
350 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
351 LE32_TO_CPU(aq_desc->cookie_high),
352 LE32_TO_CPU(aq_desc->cookie_low));
353 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
354 LE32_TO_CPU(aq_desc->params.internal.param0),
355 LE32_TO_CPU(aq_desc->params.internal.param1));
356 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
357 LE32_TO_CPU(aq_desc->params.external.addr_high),
358 LE32_TO_CPU(aq_desc->params.external.addr_low));
360 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
361 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
364 /* write the full 16-byte chunks */
365 for (i = 0; i < (len - 16); i += 16)
367 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
368 i, buf[i], buf[i+1], buf[i+2], buf[i+3],
369 buf[i+4], buf[i+5], buf[i+6], buf[i+7],
370 buf[i+8], buf[i+9], buf[i+10], buf[i+11],
371 buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
372 /* the most we could have left is 16 bytes, pad with zeros */
378 memset(d_buf, 0, sizeof(d_buf));
379 for (j = 0; i < len; j++, i++)
382 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
383 i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
384 d_buf[4], d_buf[5], d_buf[6], d_buf[7],
385 d_buf[8], d_buf[9], d_buf[10], d_buf[11],
386 d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
392 * i40e_check_asq_alive
393 * @hw: pointer to the hw struct
395 * Returns true if Queue is enabled else false.
397 bool i40e_check_asq_alive(struct i40e_hw *hw)
403 return !!(rd32(hw, hw->aq.asq.len) &
404 I40E_PF_ATQLEN_ATQENABLE_MASK);
406 return !!(rd32(hw, hw->aq.asq.len) &
407 I40E_PF_ATQLEN_ATQENABLE_MASK);
408 #endif /* INTEGRATED_VF */
409 #endif /* PF_DRIVER */
413 return !!(rd32(hw, hw->aq.asq.len) &
414 I40E_VF_ATQLEN1_ATQENABLE_MASK);
416 return !!(rd32(hw, hw->aq.asq.len) &
417 I40E_VF_ATQLEN1_ATQENABLE_MASK);
418 #endif /* INTEGRATED_VF */
419 #endif /* VF_DRIVER */
424 * i40e_aq_queue_shutdown
425 * @hw: pointer to the hw struct
426 * @unloading: is the driver unloading itself
428 * Tell the Firmware that we're shutting down the AdminQ and whether
429 * or not the driver is unloading as well.
431 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
434 struct i40e_aq_desc desc;
435 struct i40e_aqc_queue_shutdown *cmd =
436 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
437 enum i40e_status_code status;
439 i40e_fill_default_direct_cmd_desc(&desc,
440 i40e_aqc_opc_queue_shutdown);
443 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
444 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
450 * i40e_aq_get_set_rss_lut
451 * @hw: pointer to the hardware structure
452 * @vsi_id: vsi fw index
453 * @pf_lut: for PF table set true, for VSI table set false
454 * @lut: pointer to the lut buffer provided by the caller
455 * @lut_size: size of the lut buffer
456 * @set: set true to set the table, false to get the table
458 * Internal function to get or set RSS look up table
460 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
461 u16 vsi_id, bool pf_lut,
462 u8 *lut, u16 lut_size,
465 enum i40e_status_code status;
466 struct i40e_aq_desc desc;
467 struct i40e_aqc_get_set_rss_lut *cmd_resp =
468 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
471 i40e_fill_default_direct_cmd_desc(&desc,
472 i40e_aqc_opc_set_rss_lut);
474 i40e_fill_default_direct_cmd_desc(&desc,
475 i40e_aqc_opc_get_rss_lut);
477 /* Indirect command */
478 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
479 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
482 CPU_TO_LE16((u16)((vsi_id <<
483 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
484 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
485 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
488 cmd_resp->flags |= CPU_TO_LE16((u16)
489 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
490 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
491 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
493 cmd_resp->flags |= CPU_TO_LE16((u16)
494 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
495 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
496 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
498 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
504 * i40e_aq_get_rss_lut
505 * @hw: pointer to the hardware structure
506 * @vsi_id: vsi fw index
507 * @pf_lut: for PF table set true, for VSI table set false
508 * @lut: pointer to the lut buffer provided by the caller
509 * @lut_size: size of the lut buffer
511 * get the RSS lookup table, PF or VSI type
513 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
514 bool pf_lut, u8 *lut, u16 lut_size)
516 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
521 * i40e_aq_set_rss_lut
522 * @hw: pointer to the hardware structure
523 * @vsi_id: vsi fw index
524 * @pf_lut: for PF table set true, for VSI table set false
525 * @lut: pointer to the lut buffer provided by the caller
526 * @lut_size: size of the lut buffer
528 * set the RSS lookup table, PF or VSI type
530 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
531 bool pf_lut, u8 *lut, u16 lut_size)
533 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
537 * i40e_aq_get_set_rss_key
538 * @hw: pointer to the hw struct
539 * @vsi_id: vsi fw index
540 * @key: pointer to key info struct
541 * @set: set true to set the key, false to get the key
543 * get the RSS key per VSI
545 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
547 struct i40e_aqc_get_set_rss_key_data *key,
550 enum i40e_status_code status;
551 struct i40e_aq_desc desc;
552 struct i40e_aqc_get_set_rss_key *cmd_resp =
553 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
554 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
557 i40e_fill_default_direct_cmd_desc(&desc,
558 i40e_aqc_opc_set_rss_key);
560 i40e_fill_default_direct_cmd_desc(&desc,
561 i40e_aqc_opc_get_rss_key);
563 /* Indirect command */
564 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
565 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
568 CPU_TO_LE16((u16)((vsi_id <<
569 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
570 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
571 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
573 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
579 * i40e_aq_get_rss_key
580 * @hw: pointer to the hw struct
581 * @vsi_id: vsi fw index
582 * @key: pointer to key info struct
585 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
587 struct i40e_aqc_get_set_rss_key_data *key)
589 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
593 * i40e_aq_set_rss_key
594 * @hw: pointer to the hw struct
595 * @vsi_id: vsi fw index
596 * @key: pointer to key info struct
598 * set the RSS key per VSI
600 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
602 struct i40e_aqc_get_set_rss_key_data *key)
604 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
607 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
608 * hardware to a bit-field that can be used by SW to more easily determine the
611 * Macros are used to shorten the table lines and make this table human
614 * We store the PTYPE in the top byte of the bit field - this is just so that
615 * we can check that the table doesn't have a row missing, as the index into
616 * the table should be the PTYPE.
620 * IF NOT i40e_ptype_lookup[ptype].known
623 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
624 * Use the rest of the fields to look at the tunnels, inner protocols, etc
626 * Use the enum i40e_rx_l2_ptype to decode the packet type
630 /* macro to make the table lines short */
631 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
634 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
635 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
636 I40E_RX_PTYPE_##OUTER_FRAG, \
637 I40E_RX_PTYPE_TUNNEL_##T, \
638 I40E_RX_PTYPE_TUNNEL_END_##TE, \
639 I40E_RX_PTYPE_##TEF, \
640 I40E_RX_PTYPE_INNER_PROT_##I, \
641 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
643 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
644 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
646 /* shorter macros makes the table fit but are terse */
647 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
648 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
649 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
651 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
652 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
653 /* L2 Packet types */
654 I40E_PTT_UNUSED_ENTRY(0),
655 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
656 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
657 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
658 I40E_PTT_UNUSED_ENTRY(4),
659 I40E_PTT_UNUSED_ENTRY(5),
660 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
661 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
662 I40E_PTT_UNUSED_ENTRY(8),
663 I40E_PTT_UNUSED_ENTRY(9),
664 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
665 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
666 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
667 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
668 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
669 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
670 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
671 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
672 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
673 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
674 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
675 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
677 /* Non Tunneled IPv4 */
678 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
679 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
680 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
681 I40E_PTT_UNUSED_ENTRY(25),
682 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
683 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
684 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
687 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
688 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
689 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
690 I40E_PTT_UNUSED_ENTRY(32),
691 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
692 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
693 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
696 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
697 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
698 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
699 I40E_PTT_UNUSED_ENTRY(39),
700 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
701 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
702 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
704 /* IPv4 --> GRE/NAT */
705 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
707 /* IPv4 --> GRE/NAT --> IPv4 */
708 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
709 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
710 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
711 I40E_PTT_UNUSED_ENTRY(47),
712 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
713 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
714 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
716 /* IPv4 --> GRE/NAT --> IPv6 */
717 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
718 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
719 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
720 I40E_PTT_UNUSED_ENTRY(54),
721 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
722 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
723 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
725 /* IPv4 --> GRE/NAT --> MAC */
726 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
728 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
729 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
730 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
731 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
732 I40E_PTT_UNUSED_ENTRY(62),
733 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
734 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
735 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
737 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
738 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
739 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
740 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
741 I40E_PTT_UNUSED_ENTRY(69),
742 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
743 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
744 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
746 /* IPv4 --> GRE/NAT --> MAC/VLAN */
747 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
749 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
750 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
751 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
752 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
753 I40E_PTT_UNUSED_ENTRY(77),
754 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
755 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
756 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
758 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
759 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
760 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
761 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
762 I40E_PTT_UNUSED_ENTRY(84),
763 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
764 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
765 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
767 /* Non Tunneled IPv6 */
768 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
769 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
770 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4),
771 I40E_PTT_UNUSED_ENTRY(91),
772 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
773 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
774 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
777 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
778 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
779 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
780 I40E_PTT_UNUSED_ENTRY(98),
781 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
782 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
783 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
786 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
787 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
788 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
789 I40E_PTT_UNUSED_ENTRY(105),
790 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
791 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
792 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
794 /* IPv6 --> GRE/NAT */
795 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
797 /* IPv6 --> GRE/NAT -> IPv4 */
798 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
799 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
800 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
801 I40E_PTT_UNUSED_ENTRY(113),
802 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
803 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
804 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
806 /* IPv6 --> GRE/NAT -> IPv6 */
807 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
808 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
809 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
810 I40E_PTT_UNUSED_ENTRY(120),
811 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
812 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
813 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
815 /* IPv6 --> GRE/NAT -> MAC */
816 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
818 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
819 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
820 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
821 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
822 I40E_PTT_UNUSED_ENTRY(128),
823 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
824 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
825 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
827 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
828 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
829 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
830 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
831 I40E_PTT_UNUSED_ENTRY(135),
832 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
833 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
834 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
836 /* IPv6 --> GRE/NAT -> MAC/VLAN */
837 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
839 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
840 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
841 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
842 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
843 I40E_PTT_UNUSED_ENTRY(143),
844 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
845 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
846 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
848 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
849 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
850 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
851 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
852 I40E_PTT_UNUSED_ENTRY(150),
853 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
854 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
855 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
858 I40E_PTT_UNUSED_ENTRY(154),
859 I40E_PTT_UNUSED_ENTRY(155),
860 I40E_PTT_UNUSED_ENTRY(156),
861 I40E_PTT_UNUSED_ENTRY(157),
862 I40E_PTT_UNUSED_ENTRY(158),
863 I40E_PTT_UNUSED_ENTRY(159),
865 I40E_PTT_UNUSED_ENTRY(160),
866 I40E_PTT_UNUSED_ENTRY(161),
867 I40E_PTT_UNUSED_ENTRY(162),
868 I40E_PTT_UNUSED_ENTRY(163),
869 I40E_PTT_UNUSED_ENTRY(164),
870 I40E_PTT_UNUSED_ENTRY(165),
871 I40E_PTT_UNUSED_ENTRY(166),
872 I40E_PTT_UNUSED_ENTRY(167),
873 I40E_PTT_UNUSED_ENTRY(168),
874 I40E_PTT_UNUSED_ENTRY(169),
876 I40E_PTT_UNUSED_ENTRY(170),
877 I40E_PTT_UNUSED_ENTRY(171),
878 I40E_PTT_UNUSED_ENTRY(172),
879 I40E_PTT_UNUSED_ENTRY(173),
880 I40E_PTT_UNUSED_ENTRY(174),
881 I40E_PTT_UNUSED_ENTRY(175),
882 I40E_PTT_UNUSED_ENTRY(176),
883 I40E_PTT_UNUSED_ENTRY(177),
884 I40E_PTT_UNUSED_ENTRY(178),
885 I40E_PTT_UNUSED_ENTRY(179),
887 I40E_PTT_UNUSED_ENTRY(180),
888 I40E_PTT_UNUSED_ENTRY(181),
889 I40E_PTT_UNUSED_ENTRY(182),
890 I40E_PTT_UNUSED_ENTRY(183),
891 I40E_PTT_UNUSED_ENTRY(184),
892 I40E_PTT_UNUSED_ENTRY(185),
893 I40E_PTT_UNUSED_ENTRY(186),
894 I40E_PTT_UNUSED_ENTRY(187),
895 I40E_PTT_UNUSED_ENTRY(188),
896 I40E_PTT_UNUSED_ENTRY(189),
898 I40E_PTT_UNUSED_ENTRY(190),
899 I40E_PTT_UNUSED_ENTRY(191),
900 I40E_PTT_UNUSED_ENTRY(192),
901 I40E_PTT_UNUSED_ENTRY(193),
902 I40E_PTT_UNUSED_ENTRY(194),
903 I40E_PTT_UNUSED_ENTRY(195),
904 I40E_PTT_UNUSED_ENTRY(196),
905 I40E_PTT_UNUSED_ENTRY(197),
906 I40E_PTT_UNUSED_ENTRY(198),
907 I40E_PTT_UNUSED_ENTRY(199),
909 I40E_PTT_UNUSED_ENTRY(200),
910 I40E_PTT_UNUSED_ENTRY(201),
911 I40E_PTT_UNUSED_ENTRY(202),
912 I40E_PTT_UNUSED_ENTRY(203),
913 I40E_PTT_UNUSED_ENTRY(204),
914 I40E_PTT_UNUSED_ENTRY(205),
915 I40E_PTT_UNUSED_ENTRY(206),
916 I40E_PTT_UNUSED_ENTRY(207),
917 I40E_PTT_UNUSED_ENTRY(208),
918 I40E_PTT_UNUSED_ENTRY(209),
920 I40E_PTT_UNUSED_ENTRY(210),
921 I40E_PTT_UNUSED_ENTRY(211),
922 I40E_PTT_UNUSED_ENTRY(212),
923 I40E_PTT_UNUSED_ENTRY(213),
924 I40E_PTT_UNUSED_ENTRY(214),
925 I40E_PTT_UNUSED_ENTRY(215),
926 I40E_PTT_UNUSED_ENTRY(216),
927 I40E_PTT_UNUSED_ENTRY(217),
928 I40E_PTT_UNUSED_ENTRY(218),
929 I40E_PTT_UNUSED_ENTRY(219),
931 I40E_PTT_UNUSED_ENTRY(220),
932 I40E_PTT_UNUSED_ENTRY(221),
933 I40E_PTT_UNUSED_ENTRY(222),
934 I40E_PTT_UNUSED_ENTRY(223),
935 I40E_PTT_UNUSED_ENTRY(224),
936 I40E_PTT_UNUSED_ENTRY(225),
937 I40E_PTT_UNUSED_ENTRY(226),
938 I40E_PTT_UNUSED_ENTRY(227),
939 I40E_PTT_UNUSED_ENTRY(228),
940 I40E_PTT_UNUSED_ENTRY(229),
942 I40E_PTT_UNUSED_ENTRY(230),
943 I40E_PTT_UNUSED_ENTRY(231),
944 I40E_PTT_UNUSED_ENTRY(232),
945 I40E_PTT_UNUSED_ENTRY(233),
946 I40E_PTT_UNUSED_ENTRY(234),
947 I40E_PTT_UNUSED_ENTRY(235),
948 I40E_PTT_UNUSED_ENTRY(236),
949 I40E_PTT_UNUSED_ENTRY(237),
950 I40E_PTT_UNUSED_ENTRY(238),
951 I40E_PTT_UNUSED_ENTRY(239),
953 I40E_PTT_UNUSED_ENTRY(240),
954 I40E_PTT_UNUSED_ENTRY(241),
955 I40E_PTT_UNUSED_ENTRY(242),
956 I40E_PTT_UNUSED_ENTRY(243),
957 I40E_PTT_UNUSED_ENTRY(244),
958 I40E_PTT_UNUSED_ENTRY(245),
959 I40E_PTT_UNUSED_ENTRY(246),
960 I40E_PTT_UNUSED_ENTRY(247),
961 I40E_PTT_UNUSED_ENTRY(248),
962 I40E_PTT_UNUSED_ENTRY(249),
964 I40E_PTT_UNUSED_ENTRY(250),
965 I40E_PTT_UNUSED_ENTRY(251),
966 I40E_PTT_UNUSED_ENTRY(252),
967 I40E_PTT_UNUSED_ENTRY(253),
968 I40E_PTT_UNUSED_ENTRY(254),
969 I40E_PTT_UNUSED_ENTRY(255)
974 * i40e_validate_mac_addr - Validate unicast MAC address
975 * @mac_addr: pointer to MAC address
977 * Tests a MAC address to ensure it is a valid Individual Address
979 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
981 enum i40e_status_code status = I40E_SUCCESS;
983 DEBUGFUNC("i40e_validate_mac_addr");
985 /* Broadcast addresses ARE multicast addresses
986 * Make sure it is not a multicast address
987 * Reject the zero address
989 if (I40E_IS_MULTICAST(mac_addr) ||
990 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
991 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
992 status = I40E_ERR_INVALID_MAC_ADDR;
999 * i40e_init_shared_code - Initialize the shared code
1000 * @hw: pointer to hardware structure
1002 * This assigns the MAC type and PHY code and inits the NVM.
1003 * Does not touch the hardware. This function must be called prior to any
1004 * other function in the shared code. The i40e_hw structure should be
1005 * memset to 0 prior to calling this function. The following fields in
1006 * hw structure should be filled in prior to calling this function:
1007 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1008 * subsystem_vendor_id, and revision_id
1010 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
1012 enum i40e_status_code status = I40E_SUCCESS;
1013 u32 port, ari, func_rid;
1015 DEBUGFUNC("i40e_init_shared_code");
1017 i40e_set_mac_type(hw);
1019 switch (hw->mac.type) {
1020 case I40E_MAC_XL710:
1024 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1027 hw->phy.get_link_info = true;
1029 /* Determine port number and PF number*/
1030 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1031 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1032 hw->port = (u8)port;
1033 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1034 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1035 func_rid = rd32(hw, I40E_PF_FUNC_RID);
1037 hw->pf_id = (u8)(func_rid & 0xff);
1039 hw->pf_id = (u8)(func_rid & 0x7);
1041 if (hw->mac.type == I40E_MAC_X722)
1042 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE |
1043 I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK;
1045 status = i40e_init_nvm(hw);
1050 * i40e_aq_mac_address_read - Retrieve the MAC addresses
1051 * @hw: pointer to the hw struct
1052 * @flags: a return indicator of what addresses were added to the addr store
1053 * @addrs: the requestor's mac addr store
1054 * @cmd_details: pointer to command details structure or NULL
1056 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1058 struct i40e_aqc_mac_address_read_data *addrs,
1059 struct i40e_asq_cmd_details *cmd_details)
1061 struct i40e_aq_desc desc;
1062 struct i40e_aqc_mac_address_read *cmd_data =
1063 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1064 enum i40e_status_code status;
1066 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1067 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1069 status = i40e_asq_send_command(hw, &desc, addrs,
1070 sizeof(*addrs), cmd_details);
1071 *flags = LE16_TO_CPU(cmd_data->command_flags);
1077 * i40e_aq_mac_address_write - Change the MAC addresses
1078 * @hw: pointer to the hw struct
1079 * @flags: indicates which MAC to be written
1080 * @mac_addr: address to write
1081 * @cmd_details: pointer to command details structure or NULL
1083 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1084 u16 flags, u8 *mac_addr,
1085 struct i40e_asq_cmd_details *cmd_details)
1087 struct i40e_aq_desc desc;
1088 struct i40e_aqc_mac_address_write *cmd_data =
1089 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1090 enum i40e_status_code status;
1092 i40e_fill_default_direct_cmd_desc(&desc,
1093 i40e_aqc_opc_mac_address_write);
1094 cmd_data->command_flags = CPU_TO_LE16(flags);
1095 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1096 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1097 ((u32)mac_addr[3] << 16) |
1098 ((u32)mac_addr[4] << 8) |
1101 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1107 * i40e_get_mac_addr - get MAC address
1108 * @hw: pointer to the HW structure
1109 * @mac_addr: pointer to MAC address
1111 * Reads the adapter's MAC address from register
1113 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1115 struct i40e_aqc_mac_address_read_data addrs;
1116 enum i40e_status_code status;
1119 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1121 if (flags & I40E_AQC_LAN_ADDR_VALID)
1122 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1123 I40E_NONDMA_TO_NONDMA);
1129 * i40e_get_port_mac_addr - get Port MAC address
1130 * @hw: pointer to the HW structure
1131 * @mac_addr: pointer to Port MAC address
1133 * Reads the adapter's Port MAC address
1135 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1137 struct i40e_aqc_mac_address_read_data addrs;
1138 enum i40e_status_code status;
1141 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1145 if (flags & I40E_AQC_PORT_ADDR_VALID)
1146 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1147 I40E_NONDMA_TO_NONDMA);
1149 status = I40E_ERR_INVALID_MAC_ADDR;
1155 * i40e_pre_tx_queue_cfg - pre tx queue configure
1156 * @hw: pointer to the HW structure
1157 * @queue: target pf queue index
1158 * @enable: state change request
1160 * Handles hw requirement to indicate intention to enable
1161 * or disable target queue.
1163 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1165 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1169 if (abs_queue_idx >= 128) {
1170 reg_block = abs_queue_idx / 128;
1171 abs_queue_idx %= 128;
1174 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1175 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1176 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1179 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1181 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1183 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1187 * i40e_get_san_mac_addr - get SAN MAC address
1188 * @hw: pointer to the HW structure
1189 * @mac_addr: pointer to SAN MAC address
1191 * Reads the adapter's SAN MAC address from NVM
1193 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1196 struct i40e_aqc_mac_address_read_data addrs;
1197 enum i40e_status_code status;
1200 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1204 if (flags & I40E_AQC_SAN_ADDR_VALID)
1205 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac),
1206 I40E_NONDMA_TO_NONDMA);
1208 status = I40E_ERR_INVALID_MAC_ADDR;
1214 * i40e_read_pba_string - Reads part number string from EEPROM
1215 * @hw: pointer to hardware structure
1216 * @pba_num: stores the part number string from the EEPROM
1217 * @pba_num_size: part number string buffer length
1219 * Reads the part number string from the EEPROM.
1221 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1224 enum i40e_status_code status = I40E_SUCCESS;
1230 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1231 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1232 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1236 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1237 if (status != I40E_SUCCESS) {
1238 DEBUGOUT("Failed to read PBA Block pointer.\n");
1242 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1243 if (status != I40E_SUCCESS) {
1244 DEBUGOUT("Failed to read PBA Block size.\n");
1248 /* Subtract one to get PBA word count (PBA Size word is included in
1252 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1253 DEBUGOUT("Buffer to small for PBA data.\n");
1254 return I40E_ERR_PARAM;
1257 for (i = 0; i < pba_size; i++) {
1258 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1259 if (status != I40E_SUCCESS) {
1260 DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1264 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1265 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1267 pba_num[(pba_size * 2)] = '\0';
1273 * i40e_get_media_type - Gets media type
1274 * @hw: pointer to the hardware structure
1276 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1278 enum i40e_media_type media;
1280 switch (hw->phy.link_info.phy_type) {
1281 case I40E_PHY_TYPE_10GBASE_SR:
1282 case I40E_PHY_TYPE_10GBASE_LR:
1283 case I40E_PHY_TYPE_1000BASE_SX:
1284 case I40E_PHY_TYPE_1000BASE_LX:
1285 case I40E_PHY_TYPE_40GBASE_SR4:
1286 case I40E_PHY_TYPE_40GBASE_LR4:
1287 case I40E_PHY_TYPE_25GBASE_LR:
1288 case I40E_PHY_TYPE_25GBASE_SR:
1289 media = I40E_MEDIA_TYPE_FIBER;
1291 case I40E_PHY_TYPE_100BASE_TX:
1292 case I40E_PHY_TYPE_1000BASE_T:
1293 case I40E_PHY_TYPE_10GBASE_T:
1294 media = I40E_MEDIA_TYPE_BASET;
1296 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1297 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1298 case I40E_PHY_TYPE_10GBASE_CR1:
1299 case I40E_PHY_TYPE_40GBASE_CR4:
1300 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1301 case I40E_PHY_TYPE_40GBASE_AOC:
1302 case I40E_PHY_TYPE_10GBASE_AOC:
1303 case I40E_PHY_TYPE_25GBASE_CR:
1304 case I40E_PHY_TYPE_25GBASE_AOC:
1305 case I40E_PHY_TYPE_25GBASE_ACC:
1306 media = I40E_MEDIA_TYPE_DA;
1308 case I40E_PHY_TYPE_1000BASE_KX:
1309 case I40E_PHY_TYPE_10GBASE_KX4:
1310 case I40E_PHY_TYPE_10GBASE_KR:
1311 case I40E_PHY_TYPE_40GBASE_KR4:
1312 case I40E_PHY_TYPE_20GBASE_KR2:
1313 case I40E_PHY_TYPE_25GBASE_KR:
1314 media = I40E_MEDIA_TYPE_BACKPLANE;
1316 case I40E_PHY_TYPE_SGMII:
1317 case I40E_PHY_TYPE_XAUI:
1318 case I40E_PHY_TYPE_XFI:
1319 case I40E_PHY_TYPE_XLAUI:
1320 case I40E_PHY_TYPE_XLPPI:
1322 media = I40E_MEDIA_TYPE_UNKNOWN;
1329 #define I40E_PF_RESET_WAIT_COUNT 200
1331 * i40e_pf_reset - Reset the PF
1332 * @hw: pointer to the hardware structure
1334 * Assuming someone else has triggered a global reset,
1335 * assure the global reset is complete and then reset the PF
1337 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1344 /* Poll for Global Reset steady state in case of recent GRST.
1345 * The grst delay value is in 100ms units, and we'll wait a
1346 * couple counts longer to be sure we don't just miss the end.
1348 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1349 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1350 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1352 grst_del = grst_del * 20;
1354 for (cnt = 0; cnt < grst_del; cnt++) {
1355 reg = rd32(hw, I40E_GLGEN_RSTAT);
1356 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1358 i40e_msec_delay(100);
1360 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1361 DEBUGOUT("Global reset polling failed to complete.\n");
1362 return I40E_ERR_RESET_FAILED;
1365 /* Now Wait for the FW to be ready */
1366 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1367 reg = rd32(hw, I40E_GLNVM_ULD);
1368 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1369 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1370 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1371 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1372 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1375 i40e_msec_delay(10);
1377 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1378 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1379 DEBUGOUT("wait for FW Reset complete timedout\n");
1380 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1381 return I40E_ERR_RESET_FAILED;
1384 /* If there was a Global Reset in progress when we got here,
1385 * we don't need to do the PF Reset
1390 reg = rd32(hw, I40E_PFGEN_CTRL);
1391 wr32(hw, I40E_PFGEN_CTRL,
1392 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1393 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1394 reg = rd32(hw, I40E_PFGEN_CTRL);
1395 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1397 reg2 = rd32(hw, I40E_GLGEN_RSTAT);
1398 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1399 DEBUGOUT("Core reset upcoming. Skipping PF reset request.\n");
1400 DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg2);
1401 return I40E_ERR_NOT_READY;
1405 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1406 DEBUGOUT("PF reset polling failed to complete.\n");
1407 return I40E_ERR_RESET_FAILED;
1411 i40e_clear_pxe_mode(hw);
1414 return I40E_SUCCESS;
1418 * i40e_clear_hw - clear out any left over hw state
1419 * @hw: pointer to the hw struct
1421 * Clear queues and interrupts, typically called at init time,
1422 * but after the capabilities have been found so we know how many
1423 * queues and msix vectors have been allocated.
1425 void i40e_clear_hw(struct i40e_hw *hw)
1427 u32 num_queues, base_queue;
1435 /* get number of interrupts, queues, and vfs */
1436 val = rd32(hw, I40E_GLPCI_CNF2);
1437 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1438 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1439 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1440 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1442 val = rd32(hw, I40E_PFLAN_QALLOC);
1443 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1444 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1445 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1446 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1447 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1448 num_queues = (j - base_queue) + 1;
1452 val = rd32(hw, I40E_PF_VT_PFALLOC);
1453 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1454 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1455 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1456 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1457 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1458 num_vfs = (j - i) + 1;
1462 /* stop all the interrupts */
1463 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1464 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1465 for (i = 0; i < num_pf_int - 2; i++)
1466 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1468 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1469 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1470 wr32(hw, I40E_PFINT_LNKLST0, val);
1471 for (i = 0; i < num_pf_int - 2; i++)
1472 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1473 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1474 for (i = 0; i < num_vfs; i++)
1475 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1476 for (i = 0; i < num_vf_int - 2; i++)
1477 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1479 /* warn the HW of the coming Tx disables */
1480 for (i = 0; i < num_queues; i++) {
1481 u32 abs_queue_idx = base_queue + i;
1484 if (abs_queue_idx >= 128) {
1485 reg_block = abs_queue_idx / 128;
1486 abs_queue_idx %= 128;
1489 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1490 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1491 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1492 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1494 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1496 i40e_usec_delay(400);
1498 /* stop all the queues */
1499 for (i = 0; i < num_queues; i++) {
1500 wr32(hw, I40E_QINT_TQCTL(i), 0);
1501 wr32(hw, I40E_QTX_ENA(i), 0);
1502 wr32(hw, I40E_QINT_RQCTL(i), 0);
1503 wr32(hw, I40E_QRX_ENA(i), 0);
1506 /* short wait for all queue disables to settle */
1507 i40e_usec_delay(50);
1511 * i40e_clear_pxe_mode - clear pxe operations mode
1512 * @hw: pointer to the hw struct
1514 * Make sure all PXE mode settings are cleared, including things
1515 * like descriptor fetch/write-back mode.
1517 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1519 if (i40e_check_asq_alive(hw))
1520 i40e_aq_clear_pxe_mode(hw, NULL);
1524 * i40e_led_is_mine - helper to find matching led
1525 * @hw: pointer to the hw struct
1526 * @idx: index into GPIO registers
1528 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1530 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1535 if (!hw->func_caps.led[idx])
1538 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1539 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1540 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1542 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1543 * if it is not our port then ignore
1545 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1552 #define I40E_COMBINED_ACTIVITY 0xA
1553 #define I40E_FILTER_ACTIVITY 0xE
1554 #define I40E_LINK_ACTIVITY 0xC
1555 #define I40E_MAC_ACTIVITY 0xD
1556 #define I40E_LED0 22
1559 * i40e_led_get - return current on/off mode
1560 * @hw: pointer to the hw struct
1562 * The value returned is the 'mode' field as defined in the
1563 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1564 * values are variations of possible behaviors relating to
1565 * blink, link, and wire.
1567 u32 i40e_led_get(struct i40e_hw *hw)
1569 u32 current_mode = 0;
1573 /* as per the documentation GPIO 22-29 are the LED
1574 * GPIO pins named LED0..LED7
1576 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1577 u32 gpio_val = i40e_led_is_mine(hw, i);
1582 /* ignore gpio LED src mode entries related to the activity
1585 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1586 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1587 switch (current_mode) {
1588 case I40E_COMBINED_ACTIVITY:
1589 case I40E_FILTER_ACTIVITY:
1590 case I40E_MAC_ACTIVITY:
1591 case I40E_LINK_ACTIVITY:
1597 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1598 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1606 * i40e_led_set - set new on/off mode
1607 * @hw: pointer to the hw struct
1608 * @mode: 0=off, 0xf=on (else see manual for mode details)
1609 * @blink: true if the LED should blink when on, false if steady
1611 * if this function is used to turn on the blink it should
1612 * be used to disable the blink when restoring the original state.
1614 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1616 u32 current_mode = 0;
1619 if (mode & 0xfffffff0)
1620 DEBUGOUT1("invalid mode passed in %X\n", mode);
1622 /* as per the documentation GPIO 22-29 are the LED
1623 * GPIO pins named LED0..LED7
1625 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1626 u32 gpio_val = i40e_led_is_mine(hw, i);
1631 /* ignore gpio LED src mode entries related to the activity
1634 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1635 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1636 switch (current_mode) {
1637 case I40E_COMBINED_ACTIVITY:
1638 case I40E_FILTER_ACTIVITY:
1639 case I40E_MAC_ACTIVITY:
1640 case I40E_LINK_ACTIVITY:
1646 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1647 /* this & is a bit of paranoia, but serves as a range check */
1648 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1649 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1652 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1654 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1656 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1661 /* Admin command wrappers */
1664 * i40e_aq_get_phy_capabilities
1665 * @hw: pointer to the hw struct
1666 * @abilities: structure for PHY capabilities to be filled
1667 * @qualified_modules: report Qualified Modules
1668 * @report_init: report init capabilities (active are default)
1669 * @cmd_details: pointer to command details structure or NULL
1671 * Returns the various PHY abilities supported on the Port.
1673 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1674 bool qualified_modules, bool report_init,
1675 struct i40e_aq_get_phy_abilities_resp *abilities,
1676 struct i40e_asq_cmd_details *cmd_details)
1678 struct i40e_aq_desc desc;
1679 enum i40e_status_code status;
1680 u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0;
1681 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1684 return I40E_ERR_PARAM;
1687 i40e_fill_default_direct_cmd_desc(&desc,
1688 i40e_aqc_opc_get_phy_abilities);
1690 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1691 if (abilities_size > I40E_AQ_LARGE_BUF)
1692 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1694 if (qualified_modules)
1695 desc.params.external.param0 |=
1696 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1699 desc.params.external.param0 |=
1700 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1702 status = i40e_asq_send_command(hw, &desc, abilities,
1703 abilities_size, cmd_details);
1705 if (status != I40E_SUCCESS)
1708 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) {
1709 status = I40E_ERR_UNKNOWN_PHY;
1711 } else if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) {
1714 status = I40E_ERR_TIMEOUT;
1716 } while ((hw->aq.asq_last_status != I40E_AQ_RC_OK) &&
1717 (total_delay < max_delay));
1719 if (status != I40E_SUCCESS)
1723 if (hw->mac.type == I40E_MAC_XL710 &&
1724 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1725 hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
1726 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1728 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1729 hw->phy.phy_types |=
1730 ((u64)abilities->phy_type_ext << 32);
1738 * i40e_aq_set_phy_config
1739 * @hw: pointer to the hw struct
1740 * @config: structure with PHY configuration to be set
1741 * @cmd_details: pointer to command details structure or NULL
1743 * Set the various PHY configuration parameters
1744 * supported on the Port.One or more of the Set PHY config parameters may be
1745 * ignored in an MFP mode as the PF may not have the privilege to set some
1746 * of the PHY Config parameters. This status will be indicated by the
1749 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1750 struct i40e_aq_set_phy_config *config,
1751 struct i40e_asq_cmd_details *cmd_details)
1753 struct i40e_aq_desc desc;
1754 struct i40e_aq_set_phy_config *cmd =
1755 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1756 enum i40e_status_code status;
1759 return I40E_ERR_PARAM;
1761 i40e_fill_default_direct_cmd_desc(&desc,
1762 i40e_aqc_opc_set_phy_config);
1766 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1773 * @hw: pointer to the hw struct
1774 * @aq_failures: buffer to return AdminQ failure information
1775 * @atomic_restart: whether to enable atomic link restart
1777 * Set the requested flow control mode using set_phy_config.
1779 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1780 bool atomic_restart)
1782 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1783 struct i40e_aq_get_phy_abilities_resp abilities;
1784 struct i40e_aq_set_phy_config config;
1785 enum i40e_status_code status;
1786 u8 pause_mask = 0x0;
1792 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1793 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1795 case I40E_FC_RX_PAUSE:
1796 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1798 case I40E_FC_TX_PAUSE:
1799 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1805 /* Get the current phy config */
1806 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1809 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1813 memset(&config, 0, sizeof(config));
1814 /* clear the old pause settings */
1815 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1816 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1817 /* set the new abilities */
1818 config.abilities |= pause_mask;
1819 /* If the abilities have changed, then set the new config */
1820 if (config.abilities != abilities.abilities) {
1821 /* Auto restart link so settings take effect */
1823 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1824 /* Copy over all the old settings */
1825 config.phy_type = abilities.phy_type;
1826 config.phy_type_ext = abilities.phy_type_ext;
1827 config.link_speed = abilities.link_speed;
1828 config.eee_capability = abilities.eee_capability;
1829 config.eeer = abilities.eeer_val;
1830 config.low_power_ctrl = abilities.d3_lpan;
1831 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1832 I40E_AQ_PHY_FEC_CONFIG_MASK;
1833 status = i40e_aq_set_phy_config(hw, &config, NULL);
1836 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1838 /* Update the link info */
1839 status = i40e_update_link_info(hw);
1841 /* Wait a little bit (on 40G cards it sometimes takes a really
1842 * long time for link to come back from the atomic reset)
1845 i40e_msec_delay(1000);
1846 status = i40e_update_link_info(hw);
1849 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1855 * i40e_aq_set_mac_config
1856 * @hw: pointer to the hw struct
1857 * @max_frame_size: Maximum Frame Size to be supported by the port
1858 * @crc_en: Tell HW to append a CRC to outgoing frames
1859 * @pacing: Pacing configurations
1860 * @cmd_details: pointer to command details structure or NULL
1862 * Configure MAC settings for frame size, jumbo frame support and the
1863 * addition of a CRC by the hardware.
1865 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1867 bool crc_en, u16 pacing,
1868 struct i40e_asq_cmd_details *cmd_details)
1870 struct i40e_aq_desc desc;
1871 struct i40e_aq_set_mac_config *cmd =
1872 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1873 enum i40e_status_code status;
1875 if (max_frame_size == 0)
1876 return I40E_ERR_PARAM;
1878 i40e_fill_default_direct_cmd_desc(&desc,
1879 i40e_aqc_opc_set_mac_config);
1881 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1882 cmd->params = ((u8)pacing & 0x0F) << 3;
1884 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1886 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1892 * i40e_aq_clear_pxe_mode
1893 * @hw: pointer to the hw struct
1894 * @cmd_details: pointer to command details structure or NULL
1896 * Tell the firmware that the driver is taking over from PXE
1898 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1899 struct i40e_asq_cmd_details *cmd_details)
1901 enum i40e_status_code status;
1902 struct i40e_aq_desc desc;
1903 struct i40e_aqc_clear_pxe *cmd =
1904 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1906 i40e_fill_default_direct_cmd_desc(&desc,
1907 i40e_aqc_opc_clear_pxe_mode);
1911 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1913 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1919 * i40e_aq_set_link_restart_an
1920 * @hw: pointer to the hw struct
1921 * @enable_link: if true: enable link, if false: disable link
1922 * @cmd_details: pointer to command details structure or NULL
1924 * Sets up the link and restarts the Auto-Negotiation over the link.
1926 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1927 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1929 struct i40e_aq_desc desc;
1930 struct i40e_aqc_set_link_restart_an *cmd =
1931 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1932 enum i40e_status_code status;
1934 i40e_fill_default_direct_cmd_desc(&desc,
1935 i40e_aqc_opc_set_link_restart_an);
1937 cmd->command = I40E_AQ_PHY_RESTART_AN;
1939 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1941 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1943 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1949 * i40e_aq_get_link_info
1950 * @hw: pointer to the hw struct
1951 * @enable_lse: enable/disable LinkStatusEvent reporting
1952 * @link: pointer to link status structure - optional
1953 * @cmd_details: pointer to command details structure or NULL
1955 * Returns the link status of the adapter.
1957 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1958 bool enable_lse, struct i40e_link_status *link,
1959 struct i40e_asq_cmd_details *cmd_details)
1961 struct i40e_aq_desc desc;
1962 struct i40e_aqc_get_link_status *resp =
1963 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1964 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1965 enum i40e_status_code status;
1966 bool tx_pause, rx_pause;
1969 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1972 command_flags = I40E_AQ_LSE_ENABLE;
1974 command_flags = I40E_AQ_LSE_DISABLE;
1975 resp->command_flags = CPU_TO_LE16(command_flags);
1977 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1979 if (status != I40E_SUCCESS)
1980 goto aq_get_link_info_exit;
1982 /* save off old link status information */
1983 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1984 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1986 /* update link status */
1987 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1988 hw->phy.media_type = i40e_get_media_type(hw);
1989 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1990 hw_link_info->link_info = resp->link_info;
1991 hw_link_info->an_info = resp->an_info;
1992 hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
1993 I40E_AQ_CONFIG_FEC_RS_ENA);
1994 hw_link_info->ext_info = resp->ext_info;
1995 hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
1996 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1997 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1999 /* update fc info */
2000 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
2001 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
2002 if (tx_pause & rx_pause)
2003 hw->fc.current_mode = I40E_FC_FULL;
2005 hw->fc.current_mode = I40E_FC_TX_PAUSE;
2007 hw->fc.current_mode = I40E_FC_RX_PAUSE;
2009 hw->fc.current_mode = I40E_FC_NONE;
2011 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
2012 hw_link_info->crc_enable = true;
2014 hw_link_info->crc_enable = false;
2016 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
2017 hw_link_info->lse_enable = true;
2019 hw_link_info->lse_enable = false;
2021 if ((hw->mac.type == I40E_MAC_XL710) &&
2022 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
2023 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
2024 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
2026 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
2027 hw->aq.api_min_ver >= 7) {
2030 i40e_memcpy(&tmp, resp->link_type, sizeof(tmp),
2031 I40E_NONDMA_TO_NONDMA);
2032 hw->phy.phy_types = LE32_TO_CPU(tmp);
2033 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
2036 /* save link status information */
2038 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
2039 I40E_NONDMA_TO_NONDMA);
2041 /* flag cleared so helper functions don't call AQ again */
2042 hw->phy.get_link_info = false;
2044 aq_get_link_info_exit:
2049 * i40e_aq_set_phy_int_mask
2050 * @hw: pointer to the hw struct
2051 * @mask: interrupt mask to be set
2052 * @cmd_details: pointer to command details structure or NULL
2054 * Set link interrupt mask.
2056 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2058 struct i40e_asq_cmd_details *cmd_details)
2060 struct i40e_aq_desc desc;
2061 struct i40e_aqc_set_phy_int_mask *cmd =
2062 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2063 enum i40e_status_code status;
2065 i40e_fill_default_direct_cmd_desc(&desc,
2066 i40e_aqc_opc_set_phy_int_mask);
2068 cmd->event_mask = CPU_TO_LE16(mask);
2070 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2076 * i40e_aq_get_local_advt_reg
2077 * @hw: pointer to the hw struct
2078 * @advt_reg: local AN advertisement register value
2079 * @cmd_details: pointer to command details structure or NULL
2081 * Get the Local AN advertisement register value.
2083 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2085 struct i40e_asq_cmd_details *cmd_details)
2087 struct i40e_aq_desc desc;
2088 struct i40e_aqc_an_advt_reg *resp =
2089 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2090 enum i40e_status_code status;
2092 i40e_fill_default_direct_cmd_desc(&desc,
2093 i40e_aqc_opc_get_local_advt_reg);
2095 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2097 if (status != I40E_SUCCESS)
2098 goto aq_get_local_advt_reg_exit;
2100 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2101 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2103 aq_get_local_advt_reg_exit:
2108 * i40e_aq_set_local_advt_reg
2109 * @hw: pointer to the hw struct
2110 * @advt_reg: local AN advertisement register value
2111 * @cmd_details: pointer to command details structure or NULL
2113 * Get the Local AN advertisement register value.
2115 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2117 struct i40e_asq_cmd_details *cmd_details)
2119 struct i40e_aq_desc desc;
2120 struct i40e_aqc_an_advt_reg *cmd =
2121 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2122 enum i40e_status_code status;
2124 i40e_fill_default_direct_cmd_desc(&desc,
2125 i40e_aqc_opc_get_local_advt_reg);
2127 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2128 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2130 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2136 * i40e_aq_get_partner_advt
2137 * @hw: pointer to the hw struct
2138 * @advt_reg: AN partner advertisement register value
2139 * @cmd_details: pointer to command details structure or NULL
2141 * Get the link partner AN advertisement register value.
2143 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2145 struct i40e_asq_cmd_details *cmd_details)
2147 struct i40e_aq_desc desc;
2148 struct i40e_aqc_an_advt_reg *resp =
2149 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2150 enum i40e_status_code status;
2152 i40e_fill_default_direct_cmd_desc(&desc,
2153 i40e_aqc_opc_get_partner_advt);
2155 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2157 if (status != I40E_SUCCESS)
2158 goto aq_get_partner_advt_exit;
2160 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2161 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2163 aq_get_partner_advt_exit:
2168 * i40e_aq_set_lb_modes
2169 * @hw: pointer to the hw struct
2170 * @lb_modes: loopback mode to be set
2171 * @cmd_details: pointer to command details structure or NULL
2173 * Sets loopback modes.
2175 enum i40e_status_code
2176 i40e_aq_set_lb_modes(struct i40e_hw *hw, u8 lb_level, u8 lb_type, u8 speed,
2177 struct i40e_asq_cmd_details *cmd_details)
2179 struct i40e_aq_desc desc;
2180 struct i40e_aqc_set_lb_mode *cmd =
2181 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2182 enum i40e_status_code status;
2184 i40e_fill_default_direct_cmd_desc(&desc,
2185 i40e_aqc_opc_set_lb_modes);
2187 cmd->lb_level = lb_level;
2188 cmd->lb_type = lb_type;
2191 cmd->force_speed = 1;
2193 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2199 * i40e_aq_set_phy_debug
2200 * @hw: pointer to the hw struct
2201 * @cmd_flags: debug command flags
2202 * @cmd_details: pointer to command details structure or NULL
2204 * Reset the external PHY.
2206 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2207 struct i40e_asq_cmd_details *cmd_details)
2209 struct i40e_aq_desc desc;
2210 struct i40e_aqc_set_phy_debug *cmd =
2211 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2212 enum i40e_status_code status;
2214 i40e_fill_default_direct_cmd_desc(&desc,
2215 i40e_aqc_opc_set_phy_debug);
2217 cmd->command_flags = cmd_flags;
2219 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2226 * @hw: pointer to the hw struct
2227 * @vsi_ctx: pointer to a vsi context struct
2228 * @cmd_details: pointer to command details structure or NULL
2230 * Add a VSI context to the hardware.
2232 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2233 struct i40e_vsi_context *vsi_ctx,
2234 struct i40e_asq_cmd_details *cmd_details)
2236 struct i40e_aq_desc desc;
2237 struct i40e_aqc_add_get_update_vsi *cmd =
2238 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2239 struct i40e_aqc_add_get_update_vsi_completion *resp =
2240 (struct i40e_aqc_add_get_update_vsi_completion *)
2242 enum i40e_status_code status;
2244 i40e_fill_default_direct_cmd_desc(&desc,
2245 i40e_aqc_opc_add_vsi);
2247 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2248 cmd->connection_type = vsi_ctx->connection_type;
2249 cmd->vf_id = vsi_ctx->vf_num;
2250 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2252 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2254 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2255 sizeof(vsi_ctx->info), cmd_details);
2257 if (status != I40E_SUCCESS)
2258 goto aq_add_vsi_exit;
2260 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2261 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2262 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2263 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2270 * i40e_aq_set_default_vsi
2271 * @hw: pointer to the hw struct
2273 * @cmd_details: pointer to command details structure or NULL
2275 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2277 struct i40e_asq_cmd_details *cmd_details)
2279 struct i40e_aq_desc desc;
2280 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2281 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2283 enum i40e_status_code status;
2285 i40e_fill_default_direct_cmd_desc(&desc,
2286 i40e_aqc_opc_set_vsi_promiscuous_modes);
2288 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2289 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2290 cmd->seid = CPU_TO_LE16(seid);
2292 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2298 * i40e_aq_clear_default_vsi
2299 * @hw: pointer to the hw struct
2301 * @cmd_details: pointer to command details structure or NULL
2303 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2305 struct i40e_asq_cmd_details *cmd_details)
2307 struct i40e_aq_desc desc;
2308 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2309 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2311 enum i40e_status_code status;
2313 i40e_fill_default_direct_cmd_desc(&desc,
2314 i40e_aqc_opc_set_vsi_promiscuous_modes);
2316 cmd->promiscuous_flags = CPU_TO_LE16(0);
2317 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2318 cmd->seid = CPU_TO_LE16(seid);
2320 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2326 * i40e_aq_set_vsi_unicast_promiscuous
2327 * @hw: pointer to the hw struct
2329 * @set: set unicast promiscuous enable/disable
2330 * @cmd_details: pointer to command details structure or NULL
2331 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2333 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2335 struct i40e_asq_cmd_details *cmd_details,
2336 bool rx_only_promisc)
2338 struct i40e_aq_desc desc;
2339 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2340 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2341 enum i40e_status_code status;
2344 i40e_fill_default_direct_cmd_desc(&desc,
2345 i40e_aqc_opc_set_vsi_promiscuous_modes);
2348 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2349 if (rx_only_promisc &&
2350 (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2351 (hw->aq.api_maj_ver > 1)))
2352 flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2355 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2357 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2358 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2359 (hw->aq.api_maj_ver > 1))
2360 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2362 cmd->seid = CPU_TO_LE16(seid);
2363 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2369 * i40e_aq_set_vsi_multicast_promiscuous
2370 * @hw: pointer to the hw struct
2372 * @set: set multicast promiscuous enable/disable
2373 * @cmd_details: pointer to command details structure or NULL
2375 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2376 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2378 struct i40e_aq_desc desc;
2379 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2380 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2381 enum i40e_status_code status;
2384 i40e_fill_default_direct_cmd_desc(&desc,
2385 i40e_aqc_opc_set_vsi_promiscuous_modes);
2388 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2390 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2392 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2394 cmd->seid = CPU_TO_LE16(seid);
2395 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2401 * i40e_aq_set_vsi_full_promiscuous
2402 * @hw: pointer to the hw struct
2404 * @set: set promiscuous enable/disable
2405 * @cmd_details: pointer to command details structure or NULL
2407 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw,
2409 struct i40e_asq_cmd_details *cmd_details)
2411 struct i40e_aq_desc desc;
2412 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2413 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2414 enum i40e_status_code status;
2417 i40e_fill_default_direct_cmd_desc(&desc,
2418 i40e_aqc_opc_set_vsi_promiscuous_modes);
2421 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST |
2422 I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2423 I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2425 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2427 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST |
2428 I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2429 I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2431 cmd->seid = CPU_TO_LE16(seid);
2432 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2438 * i40e_aq_set_vsi_mc_promisc_on_vlan
2439 * @hw: pointer to the hw struct
2441 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2442 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2443 * @cmd_details: pointer to command details structure or NULL
2445 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2446 u16 seid, bool enable, u16 vid,
2447 struct i40e_asq_cmd_details *cmd_details)
2449 struct i40e_aq_desc desc;
2450 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2451 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2452 enum i40e_status_code status;
2455 i40e_fill_default_direct_cmd_desc(&desc,
2456 i40e_aqc_opc_set_vsi_promiscuous_modes);
2459 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2461 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2462 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2463 cmd->seid = CPU_TO_LE16(seid);
2464 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2466 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2472 * i40e_aq_set_vsi_uc_promisc_on_vlan
2473 * @hw: pointer to the hw struct
2475 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2476 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2477 * @cmd_details: pointer to command details structure or NULL
2479 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2480 u16 seid, bool enable, u16 vid,
2481 struct i40e_asq_cmd_details *cmd_details)
2483 struct i40e_aq_desc desc;
2484 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2485 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2486 enum i40e_status_code status;
2489 i40e_fill_default_direct_cmd_desc(&desc,
2490 i40e_aqc_opc_set_vsi_promiscuous_modes);
2493 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2495 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2496 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2497 cmd->seid = CPU_TO_LE16(seid);
2498 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2500 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2506 * i40e_aq_set_vsi_bc_promisc_on_vlan
2507 * @hw: pointer to the hw struct
2509 * @enable: set broadcast promiscuous enable/disable for a given VLAN
2510 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2511 * @cmd_details: pointer to command details structure or NULL
2513 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2514 u16 seid, bool enable, u16 vid,
2515 struct i40e_asq_cmd_details *cmd_details)
2517 struct i40e_aq_desc desc;
2518 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2519 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2520 enum i40e_status_code status;
2523 i40e_fill_default_direct_cmd_desc(&desc,
2524 i40e_aqc_opc_set_vsi_promiscuous_modes);
2527 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2529 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2530 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2531 cmd->seid = CPU_TO_LE16(seid);
2532 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2534 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2540 * i40e_aq_set_vsi_broadcast
2541 * @hw: pointer to the hw struct
2543 * @set_filter: true to set filter, false to clear filter
2544 * @cmd_details: pointer to command details structure or NULL
2546 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2548 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2549 u16 seid, bool set_filter,
2550 struct i40e_asq_cmd_details *cmd_details)
2552 struct i40e_aq_desc desc;
2553 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2554 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2555 enum i40e_status_code status;
2557 i40e_fill_default_direct_cmd_desc(&desc,
2558 i40e_aqc_opc_set_vsi_promiscuous_modes);
2561 cmd->promiscuous_flags
2562 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2564 cmd->promiscuous_flags
2565 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2567 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2568 cmd->seid = CPU_TO_LE16(seid);
2569 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2575 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2576 * @hw: pointer to the hw struct
2578 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2579 * @cmd_details: pointer to command details structure or NULL
2581 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2582 u16 seid, bool enable,
2583 struct i40e_asq_cmd_details *cmd_details)
2585 struct i40e_aq_desc desc;
2586 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2587 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2588 enum i40e_status_code status;
2591 i40e_fill_default_direct_cmd_desc(&desc,
2592 i40e_aqc_opc_set_vsi_promiscuous_modes);
2594 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2596 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2597 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2598 cmd->seid = CPU_TO_LE16(seid);
2600 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2606 * i40e_get_vsi_params - get VSI configuration info
2607 * @hw: pointer to the hw struct
2608 * @vsi_ctx: pointer to a vsi context struct
2609 * @cmd_details: pointer to command details structure or NULL
2611 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2612 struct i40e_vsi_context *vsi_ctx,
2613 struct i40e_asq_cmd_details *cmd_details)
2615 struct i40e_aq_desc desc;
2616 struct i40e_aqc_add_get_update_vsi *cmd =
2617 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2618 struct i40e_aqc_add_get_update_vsi_completion *resp =
2619 (struct i40e_aqc_add_get_update_vsi_completion *)
2621 enum i40e_status_code status;
2623 UNREFERENCED_1PARAMETER(cmd_details);
2624 i40e_fill_default_direct_cmd_desc(&desc,
2625 i40e_aqc_opc_get_vsi_parameters);
2627 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2629 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2631 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2632 sizeof(vsi_ctx->info), NULL);
2634 if (status != I40E_SUCCESS)
2635 goto aq_get_vsi_params_exit;
2637 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2638 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2639 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2640 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2642 aq_get_vsi_params_exit:
2647 * i40e_aq_update_vsi_params
2648 * @hw: pointer to the hw struct
2649 * @vsi_ctx: pointer to a vsi context struct
2650 * @cmd_details: pointer to command details structure or NULL
2652 * Update a VSI context.
2654 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2655 struct i40e_vsi_context *vsi_ctx,
2656 struct i40e_asq_cmd_details *cmd_details)
2658 struct i40e_aq_desc desc;
2659 struct i40e_aqc_add_get_update_vsi *cmd =
2660 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2661 struct i40e_aqc_add_get_update_vsi_completion *resp =
2662 (struct i40e_aqc_add_get_update_vsi_completion *)
2664 enum i40e_status_code status;
2666 i40e_fill_default_direct_cmd_desc(&desc,
2667 i40e_aqc_opc_update_vsi_parameters);
2668 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2670 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2672 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2673 sizeof(vsi_ctx->info), cmd_details);
2675 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2676 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2682 * i40e_aq_get_switch_config
2683 * @hw: pointer to the hardware structure
2684 * @buf: pointer to the result buffer
2685 * @buf_size: length of input buffer
2686 * @start_seid: seid to start for the report, 0 == beginning
2687 * @cmd_details: pointer to command details structure or NULL
2689 * Fill the buf with switch configuration returned from AdminQ command
2691 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2692 struct i40e_aqc_get_switch_config_resp *buf,
2693 u16 buf_size, u16 *start_seid,
2694 struct i40e_asq_cmd_details *cmd_details)
2696 struct i40e_aq_desc desc;
2697 struct i40e_aqc_switch_seid *scfg =
2698 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2699 enum i40e_status_code status;
2701 i40e_fill_default_direct_cmd_desc(&desc,
2702 i40e_aqc_opc_get_switch_config);
2703 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2704 if (buf_size > I40E_AQ_LARGE_BUF)
2705 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2706 scfg->seid = CPU_TO_LE16(*start_seid);
2708 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2709 *start_seid = LE16_TO_CPU(scfg->seid);
2715 * i40e_aq_set_switch_config
2716 * @hw: pointer to the hardware structure
2717 * @flags: bit flag values to set
2718 * @valid_flags: which bit flags to set
2719 * @cmd_details: pointer to command details structure or NULL
2721 * Set switch configuration bits
2723 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2724 u16 flags, u16 valid_flags,
2725 struct i40e_asq_cmd_details *cmd_details)
2727 struct i40e_aq_desc desc;
2728 struct i40e_aqc_set_switch_config *scfg =
2729 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2730 enum i40e_status_code status;
2732 i40e_fill_default_direct_cmd_desc(&desc,
2733 i40e_aqc_opc_set_switch_config);
2734 scfg->flags = CPU_TO_LE16(flags);
2735 scfg->valid_flags = CPU_TO_LE16(valid_flags);
2736 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
2737 scfg->switch_tag = CPU_TO_LE16(hw->switch_tag);
2738 scfg->first_tag = CPU_TO_LE16(hw->first_tag);
2739 scfg->second_tag = CPU_TO_LE16(hw->second_tag);
2741 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2747 * i40e_aq_get_firmware_version
2748 * @hw: pointer to the hw struct
2749 * @fw_major_version: firmware major version
2750 * @fw_minor_version: firmware minor version
2751 * @fw_build: firmware build number
2752 * @api_major_version: major queue version
2753 * @api_minor_version: minor queue version
2754 * @cmd_details: pointer to command details structure or NULL
2756 * Get the firmware version from the admin queue commands
2758 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2759 u16 *fw_major_version, u16 *fw_minor_version,
2761 u16 *api_major_version, u16 *api_minor_version,
2762 struct i40e_asq_cmd_details *cmd_details)
2764 struct i40e_aq_desc desc;
2765 struct i40e_aqc_get_version *resp =
2766 (struct i40e_aqc_get_version *)&desc.params.raw;
2767 enum i40e_status_code status;
2769 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2771 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2773 if (status == I40E_SUCCESS) {
2774 if (fw_major_version != NULL)
2775 *fw_major_version = LE16_TO_CPU(resp->fw_major);
2776 if (fw_minor_version != NULL)
2777 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2778 if (fw_build != NULL)
2779 *fw_build = LE32_TO_CPU(resp->fw_build);
2780 if (api_major_version != NULL)
2781 *api_major_version = LE16_TO_CPU(resp->api_major);
2782 if (api_minor_version != NULL)
2783 *api_minor_version = LE16_TO_CPU(resp->api_minor);
2785 /* A workaround to fix the API version in SW */
2786 if (api_major_version && api_minor_version &&
2787 fw_major_version && fw_minor_version &&
2788 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2789 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2790 (*fw_major_version > 4)))
2791 *api_minor_version = 2;
2798 * i40e_aq_send_driver_version
2799 * @hw: pointer to the hw struct
2800 * @dv: driver's major, minor version
2801 * @cmd_details: pointer to command details structure or NULL
2803 * Send the driver version to the firmware
2805 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2806 struct i40e_driver_version *dv,
2807 struct i40e_asq_cmd_details *cmd_details)
2809 struct i40e_aq_desc desc;
2810 struct i40e_aqc_driver_version *cmd =
2811 (struct i40e_aqc_driver_version *)&desc.params.raw;
2812 enum i40e_status_code status;
2816 return I40E_ERR_PARAM;
2818 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2820 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2821 cmd->driver_major_ver = dv->major_version;
2822 cmd->driver_minor_ver = dv->minor_version;
2823 cmd->driver_build_ver = dv->build_version;
2824 cmd->driver_subbuild_ver = dv->subbuild_version;
2827 while (len < sizeof(dv->driver_string) &&
2828 (dv->driver_string[len] < 0x80) &&
2829 dv->driver_string[len])
2831 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2838 * i40e_get_link_status - get status of the HW network link
2839 * @hw: pointer to the hw struct
2840 * @link_up: pointer to bool (true/false = linkup/linkdown)
2842 * Variable link_up true if link is up, false if link is down.
2843 * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2845 * Side effect: LinkStatusEvent reporting becomes enabled
2847 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2849 enum i40e_status_code status = I40E_SUCCESS;
2851 if (hw->phy.get_link_info) {
2852 status = i40e_update_link_info(hw);
2854 if (status != I40E_SUCCESS)
2855 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2859 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2865 * i40e_updatelink_status - update status of the HW network link
2866 * @hw: pointer to the hw struct
2868 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2870 struct i40e_aq_get_phy_abilities_resp abilities;
2871 enum i40e_status_code status = I40E_SUCCESS;
2873 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2877 /* extra checking needed to ensure link info to user is timely */
2878 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2879 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2880 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2881 status = i40e_aq_get_phy_capabilities(hw, false, false,
2886 hw->phy.link_info.req_fec_info =
2887 abilities.fec_cfg_curr_mod_ext_info &
2888 (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS);
2890 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2891 sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2898 * i40e_get_link_speed
2899 * @hw: pointer to the hw struct
2901 * Returns the link speed of the adapter.
2903 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2905 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2906 enum i40e_status_code status = I40E_SUCCESS;
2908 if (hw->phy.get_link_info) {
2909 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2911 if (status != I40E_SUCCESS)
2912 goto i40e_link_speed_exit;
2915 speed = hw->phy.link_info.link_speed;
2917 i40e_link_speed_exit:
2922 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2923 * @hw: pointer to the hw struct
2924 * @uplink_seid: the MAC or other gizmo SEID
2925 * @downlink_seid: the VSI SEID
2926 * @enabled_tc: bitmap of TCs to be enabled
2927 * @default_port: true for default port VSI, false for control port
2928 * @veb_seid: pointer to where to put the resulting VEB SEID
2929 * @enable_stats: true to turn on VEB stats
2930 * @cmd_details: pointer to command details structure or NULL
2932 * This asks the FW to add a VEB between the uplink and downlink
2933 * elements. If the uplink SEID is 0, this will be a floating VEB.
2935 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2936 u16 downlink_seid, u8 enabled_tc,
2937 bool default_port, u16 *veb_seid,
2939 struct i40e_asq_cmd_details *cmd_details)
2941 struct i40e_aq_desc desc;
2942 struct i40e_aqc_add_veb *cmd =
2943 (struct i40e_aqc_add_veb *)&desc.params.raw;
2944 struct i40e_aqc_add_veb_completion *resp =
2945 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2946 enum i40e_status_code status;
2949 /* SEIDs need to either both be set or both be 0 for floating VEB */
2950 if (!!uplink_seid != !!downlink_seid)
2951 return I40E_ERR_PARAM;
2953 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2955 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2956 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2957 cmd->enable_tcs = enabled_tc;
2959 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2961 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2963 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2965 /* reverse logic here: set the bitflag to disable the stats */
2967 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2969 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2971 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2973 if (!status && veb_seid)
2974 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2980 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2981 * @hw: pointer to the hw struct
2982 * @veb_seid: the SEID of the VEB to query
2983 * @switch_id: the uplink switch id
2984 * @floating: set to true if the VEB is floating
2985 * @statistic_index: index of the stats counter block for this VEB
2986 * @vebs_used: number of VEB's used by function
2987 * @vebs_free: total VEB's not reserved by any function
2988 * @cmd_details: pointer to command details structure or NULL
2990 * This retrieves the parameters for a particular VEB, specified by
2991 * uplink_seid, and returns them to the caller.
2993 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2994 u16 veb_seid, u16 *switch_id,
2995 bool *floating, u16 *statistic_index,
2996 u16 *vebs_used, u16 *vebs_free,
2997 struct i40e_asq_cmd_details *cmd_details)
2999 struct i40e_aq_desc desc;
3000 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
3001 (struct i40e_aqc_get_veb_parameters_completion *)
3003 enum i40e_status_code status;
3006 return I40E_ERR_PARAM;
3008 i40e_fill_default_direct_cmd_desc(&desc,
3009 i40e_aqc_opc_get_veb_parameters);
3010 cmd_resp->seid = CPU_TO_LE16(veb_seid);
3012 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3017 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
3018 if (statistic_index)
3019 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
3021 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
3023 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
3025 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
3027 if (flags & I40E_AQC_ADD_VEB_FLOATING)
3038 * i40e_aq_add_macvlan
3039 * @hw: pointer to the hw struct
3040 * @seid: VSI for the mac address
3041 * @mv_list: list of macvlans to be added
3042 * @count: length of the list
3043 * @cmd_details: pointer to command details structure or NULL
3045 * Add MAC/VLAN addresses to the HW filtering
3047 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
3048 struct i40e_aqc_add_macvlan_element_data *mv_list,
3049 u16 count, struct i40e_asq_cmd_details *cmd_details)
3051 struct i40e_aq_desc desc;
3052 struct i40e_aqc_macvlan *cmd =
3053 (struct i40e_aqc_macvlan *)&desc.params.raw;
3054 enum i40e_status_code status;
3058 if (count == 0 || !mv_list || !hw)
3059 return I40E_ERR_PARAM;
3061 buf_size = count * sizeof(*mv_list);
3063 /* prep the rest of the request */
3064 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
3065 cmd->num_addresses = CPU_TO_LE16(count);
3066 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3070 for (i = 0; i < count; i++)
3071 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
3073 CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
3075 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3076 if (buf_size > I40E_AQ_LARGE_BUF)
3077 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3079 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3086 * i40e_aq_remove_macvlan
3087 * @hw: pointer to the hw struct
3088 * @seid: VSI for the mac address
3089 * @mv_list: list of macvlans to be removed
3090 * @count: length of the list
3091 * @cmd_details: pointer to command details structure or NULL
3093 * Remove MAC/VLAN addresses from the HW filtering
3095 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
3096 struct i40e_aqc_remove_macvlan_element_data *mv_list,
3097 u16 count, struct i40e_asq_cmd_details *cmd_details)
3099 struct i40e_aq_desc desc;
3100 struct i40e_aqc_macvlan *cmd =
3101 (struct i40e_aqc_macvlan *)&desc.params.raw;
3102 enum i40e_status_code status;
3105 if (count == 0 || !mv_list || !hw)
3106 return I40E_ERR_PARAM;
3108 buf_size = count * sizeof(*mv_list);
3110 /* prep the rest of the request */
3111 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
3112 cmd->num_addresses = CPU_TO_LE16(count);
3113 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3117 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3118 if (buf_size > I40E_AQ_LARGE_BUF)
3119 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3121 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3128 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3129 * @hw: pointer to the hw struct
3130 * @opcode: AQ opcode for add or delete mirror rule
3131 * @sw_seid: Switch SEID (to which rule refers)
3132 * @rule_type: Rule Type (ingress/egress/VLAN)
3133 * @id: Destination VSI SEID or Rule ID
3134 * @count: length of the list
3135 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3136 * @cmd_details: pointer to command details structure or NULL
3137 * @rule_id: Rule ID returned from FW
3138 * @rules_used: Number of rules used in internal switch
3139 * @rules_free: Number of rules free in internal switch
3141 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3142 * VEBs/VEPA elements only
3144 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3145 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3146 u16 count, __le16 *mr_list,
3147 struct i40e_asq_cmd_details *cmd_details,
3148 u16 *rule_id, u16 *rules_used, u16 *rules_free)
3150 struct i40e_aq_desc desc;
3151 struct i40e_aqc_add_delete_mirror_rule *cmd =
3152 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3153 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3154 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3155 enum i40e_status_code status;
3158 buf_size = count * sizeof(*mr_list);
3160 /* prep the rest of the request */
3161 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3162 cmd->seid = CPU_TO_LE16(sw_seid);
3163 cmd->rule_type = CPU_TO_LE16(rule_type &
3164 I40E_AQC_MIRROR_RULE_TYPE_MASK);
3165 cmd->num_entries = CPU_TO_LE16(count);
3166 /* Dest VSI for add, rule_id for delete */
3167 cmd->destination = CPU_TO_LE16(id);
3169 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3171 if (buf_size > I40E_AQ_LARGE_BUF)
3172 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3175 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3177 if (status == I40E_SUCCESS ||
3178 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3180 *rule_id = LE16_TO_CPU(resp->rule_id);
3182 *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3184 *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3190 * i40e_aq_add_mirrorrule - add a mirror rule
3191 * @hw: pointer to the hw struct
3192 * @sw_seid: Switch SEID (to which rule refers)
3193 * @rule_type: Rule Type (ingress/egress/VLAN)
3194 * @dest_vsi: SEID of VSI to which packets will be mirrored
3195 * @count: length of the list
3196 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3197 * @cmd_details: pointer to command details structure or NULL
3198 * @rule_id: Rule ID returned from FW
3199 * @rules_used: Number of rules used in internal switch
3200 * @rules_free: Number of rules free in internal switch
3202 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3204 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3205 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3206 struct i40e_asq_cmd_details *cmd_details,
3207 u16 *rule_id, u16 *rules_used, u16 *rules_free)
3209 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3210 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3211 if (count == 0 || !mr_list)
3212 return I40E_ERR_PARAM;
3215 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3216 rule_type, dest_vsi, count, mr_list,
3217 cmd_details, rule_id, rules_used, rules_free);
3221 * i40e_aq_delete_mirrorrule - delete a mirror rule
3222 * @hw: pointer to the hw struct
3223 * @sw_seid: Switch SEID (to which rule refers)
3224 * @rule_type: Rule Type (ingress/egress/VLAN)
3225 * @count: length of the list
3226 * @rule_id: Rule ID that is returned in the receive desc as part of
3228 * @mr_list: list of mirrored VLAN IDs to be removed
3229 * @cmd_details: pointer to command details structure or NULL
3230 * @rules_used: Number of rules used in internal switch
3231 * @rules_free: Number of rules free in internal switch
3233 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3235 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3236 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3237 struct i40e_asq_cmd_details *cmd_details,
3238 u16 *rules_used, u16 *rules_free)
3240 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3241 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3242 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3243 * mirroring. For other rule_type, count and rule_type should
3246 if (count == 0 || !mr_list)
3247 return I40E_ERR_PARAM;
3250 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3251 rule_type, rule_id, count, mr_list,
3252 cmd_details, NULL, rules_used, rules_free);
3256 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3257 * @hw: pointer to the hw struct
3258 * @seid: VSI for the vlan filters
3259 * @v_list: list of vlan filters to be added
3260 * @count: length of the list
3261 * @cmd_details: pointer to command details structure or NULL
3263 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3264 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3265 u8 count, struct i40e_asq_cmd_details *cmd_details)
3267 struct i40e_aq_desc desc;
3268 struct i40e_aqc_macvlan *cmd =
3269 (struct i40e_aqc_macvlan *)&desc.params.raw;
3270 enum i40e_status_code status;
3273 if (count == 0 || !v_list || !hw)
3274 return I40E_ERR_PARAM;
3276 buf_size = count * sizeof(*v_list);
3278 /* prep the rest of the request */
3279 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3280 cmd->num_addresses = CPU_TO_LE16(count);
3281 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3285 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3286 if (buf_size > I40E_AQ_LARGE_BUF)
3287 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3289 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3296 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3297 * @hw: pointer to the hw struct
3298 * @seid: VSI for the vlan filters
3299 * @v_list: list of macvlans to be removed
3300 * @count: length of the list
3301 * @cmd_details: pointer to command details structure or NULL
3303 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3304 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3305 u8 count, struct i40e_asq_cmd_details *cmd_details)
3307 struct i40e_aq_desc desc;
3308 struct i40e_aqc_macvlan *cmd =
3309 (struct i40e_aqc_macvlan *)&desc.params.raw;
3310 enum i40e_status_code status;
3313 if (count == 0 || !v_list || !hw)
3314 return I40E_ERR_PARAM;
3316 buf_size = count * sizeof(*v_list);
3318 /* prep the rest of the request */
3319 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3320 cmd->num_addresses = CPU_TO_LE16(count);
3321 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3325 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3326 if (buf_size > I40E_AQ_LARGE_BUF)
3327 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3329 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3336 * i40e_aq_send_msg_to_vf
3337 * @hw: pointer to the hardware structure
3338 * @vfid: vf id to send msg
3339 * @v_opcode: opcodes for VF-PF communication
3340 * @v_retval: return error code
3341 * @msg: pointer to the msg buffer
3342 * @msglen: msg length
3343 * @cmd_details: pointer to command details
3347 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3348 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3349 struct i40e_asq_cmd_details *cmd_details)
3351 struct i40e_aq_desc desc;
3352 struct i40e_aqc_pf_vf_message *cmd =
3353 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3354 enum i40e_status_code status;
3356 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3357 cmd->id = CPU_TO_LE32(vfid);
3358 desc.cookie_high = CPU_TO_LE32(v_opcode);
3359 desc.cookie_low = CPU_TO_LE32(v_retval);
3360 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3362 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3364 if (msglen > I40E_AQ_LARGE_BUF)
3365 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3366 desc.datalen = CPU_TO_LE16(msglen);
3368 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3374 * i40e_aq_debug_read_register
3375 * @hw: pointer to the hw struct
3376 * @reg_addr: register address
3377 * @reg_val: register value
3378 * @cmd_details: pointer to command details structure or NULL
3380 * Read the register using the admin queue commands
3382 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3383 u32 reg_addr, u64 *reg_val,
3384 struct i40e_asq_cmd_details *cmd_details)
3386 struct i40e_aq_desc desc;
3387 struct i40e_aqc_debug_reg_read_write *cmd_resp =
3388 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3389 enum i40e_status_code status;
3391 if (reg_val == NULL)
3392 return I40E_ERR_PARAM;
3394 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3396 cmd_resp->address = CPU_TO_LE32(reg_addr);
3398 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3400 if (status == I40E_SUCCESS) {
3401 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3402 (u64)LE32_TO_CPU(cmd_resp->value_low);
3409 * i40e_aq_debug_write_register
3410 * @hw: pointer to the hw struct
3411 * @reg_addr: register address
3412 * @reg_val: register value
3413 * @cmd_details: pointer to command details structure or NULL
3415 * Write to a register using the admin queue commands
3417 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3418 u32 reg_addr, u64 reg_val,
3419 struct i40e_asq_cmd_details *cmd_details)
3421 struct i40e_aq_desc desc;
3422 struct i40e_aqc_debug_reg_read_write *cmd =
3423 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3424 enum i40e_status_code status;
3426 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3428 cmd->address = CPU_TO_LE32(reg_addr);
3429 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3430 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3432 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3438 * i40e_aq_request_resource
3439 * @hw: pointer to the hw struct
3440 * @resource: resource id
3441 * @access: access type
3442 * @sdp_number: resource number
3443 * @timeout: the maximum time in ms that the driver may hold the resource
3444 * @cmd_details: pointer to command details structure or NULL
3446 * requests common resource using the admin queue commands
3448 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3449 enum i40e_aq_resources_ids resource,
3450 enum i40e_aq_resource_access_type access,
3451 u8 sdp_number, u64 *timeout,
3452 struct i40e_asq_cmd_details *cmd_details)
3454 struct i40e_aq_desc desc;
3455 struct i40e_aqc_request_resource *cmd_resp =
3456 (struct i40e_aqc_request_resource *)&desc.params.raw;
3457 enum i40e_status_code status;
3459 DEBUGFUNC("i40e_aq_request_resource");
3461 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3463 cmd_resp->resource_id = CPU_TO_LE16(resource);
3464 cmd_resp->access_type = CPU_TO_LE16(access);
3465 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3467 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3468 /* The completion specifies the maximum time in ms that the driver
3469 * may hold the resource in the Timeout field.
3470 * If the resource is held by someone else, the command completes with
3471 * busy return value and the timeout field indicates the maximum time
3472 * the current owner of the resource has to free it.
3474 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3475 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3481 * i40e_aq_release_resource
3482 * @hw: pointer to the hw struct
3483 * @resource: resource id
3484 * @sdp_number: resource number
3485 * @cmd_details: pointer to command details structure or NULL
3487 * release common resource using the admin queue commands
3489 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3490 enum i40e_aq_resources_ids resource,
3492 struct i40e_asq_cmd_details *cmd_details)
3494 struct i40e_aq_desc desc;
3495 struct i40e_aqc_request_resource *cmd =
3496 (struct i40e_aqc_request_resource *)&desc.params.raw;
3497 enum i40e_status_code status;
3499 DEBUGFUNC("i40e_aq_release_resource");
3501 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3503 cmd->resource_id = CPU_TO_LE16(resource);
3504 cmd->resource_number = CPU_TO_LE32(sdp_number);
3506 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3513 * @hw: pointer to the hw struct
3514 * @module_pointer: module pointer location in words from the NVM beginning
3515 * @offset: byte offset from the module beginning
3516 * @length: length of the section to be read (in bytes from the offset)
3517 * @data: command buffer (size [bytes] = length)
3518 * @last_command: tells if this is the last command in a series
3519 * @cmd_details: pointer to command details structure or NULL
3521 * Read the NVM using the admin queue commands
3523 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3524 u32 offset, u16 length, void *data,
3526 struct i40e_asq_cmd_details *cmd_details)
3528 struct i40e_aq_desc desc;
3529 struct i40e_aqc_nvm_update *cmd =
3530 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3531 enum i40e_status_code status;
3533 DEBUGFUNC("i40e_aq_read_nvm");
3535 /* In offset the highest byte must be zeroed. */
3536 if (offset & 0xFF000000) {
3537 status = I40E_ERR_PARAM;
3538 goto i40e_aq_read_nvm_exit;
3541 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3543 /* If this is the last command in a series, set the proper flag. */
3545 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3546 cmd->module_pointer = module_pointer;
3547 cmd->offset = CPU_TO_LE32(offset);
3548 cmd->length = CPU_TO_LE16(length);
3550 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3551 if (length > I40E_AQ_LARGE_BUF)
3552 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3554 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3556 i40e_aq_read_nvm_exit:
3561 * i40e_aq_read_nvm_config - read an nvm config block
3562 * @hw: pointer to the hw struct
3563 * @cmd_flags: NVM access admin command bits
3564 * @field_id: field or feature id
3565 * @data: buffer for result
3566 * @buf_size: buffer size
3567 * @element_count: pointer to count of elements read by FW
3568 * @cmd_details: pointer to command details structure or NULL
3570 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3571 u8 cmd_flags, u32 field_id, void *data,
3572 u16 buf_size, u16 *element_count,
3573 struct i40e_asq_cmd_details *cmd_details)
3575 struct i40e_aq_desc desc;
3576 struct i40e_aqc_nvm_config_read *cmd =
3577 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3578 enum i40e_status_code status;
3580 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3581 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3582 if (buf_size > I40E_AQ_LARGE_BUF)
3583 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3585 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3586 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3587 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3588 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3590 cmd->element_id_msw = 0;
3592 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3594 if (!status && element_count)
3595 *element_count = LE16_TO_CPU(cmd->element_count);
3601 * i40e_aq_write_nvm_config - write an nvm config block
3602 * @hw: pointer to the hw struct
3603 * @cmd_flags: NVM access admin command bits
3604 * @data: buffer for result
3605 * @buf_size: buffer size
3606 * @element_count: count of elements to be written
3607 * @cmd_details: pointer to command details structure or NULL
3609 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3610 u8 cmd_flags, void *data, u16 buf_size,
3612 struct i40e_asq_cmd_details *cmd_details)
3614 struct i40e_aq_desc desc;
3615 struct i40e_aqc_nvm_config_write *cmd =
3616 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3617 enum i40e_status_code status;
3619 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3620 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3621 if (buf_size > I40E_AQ_LARGE_BUF)
3622 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3624 cmd->element_count = CPU_TO_LE16(element_count);
3625 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3626 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3632 * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3633 * @hw: pointer to the hw struct
3634 * @buff: buffer for result
3635 * @buff_size: buffer size
3636 * @cmd_details: pointer to command details structure or NULL
3638 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3639 void *buff, u16 buff_size,
3640 struct i40e_asq_cmd_details *cmd_details)
3642 struct i40e_aq_desc desc;
3643 enum i40e_status_code status;
3645 UNREFERENCED_2PARAMETER(buff, buff_size);
3647 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3648 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3649 if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3650 status = I40E_ERR_NOT_IMPLEMENTED;
3657 * @hw: pointer to the hw struct
3658 * @module_pointer: module pointer location in words from the NVM beginning
3659 * @offset: offset in the module (expressed in 4 KB from module's beginning)
3660 * @length: length of the section to be erased (expressed in 4 KB)
3661 * @last_command: tells if this is the last command in a series
3662 * @cmd_details: pointer to command details structure or NULL
3664 * Erase the NVM sector using the admin queue commands
3666 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3667 u32 offset, u16 length, bool last_command,
3668 struct i40e_asq_cmd_details *cmd_details)
3670 struct i40e_aq_desc desc;
3671 struct i40e_aqc_nvm_update *cmd =
3672 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3673 enum i40e_status_code status;
3675 DEBUGFUNC("i40e_aq_erase_nvm");
3677 /* In offset the highest byte must be zeroed. */
3678 if (offset & 0xFF000000) {
3679 status = I40E_ERR_PARAM;
3680 goto i40e_aq_erase_nvm_exit;
3683 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3685 /* If this is the last command in a series, set the proper flag. */
3687 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3688 cmd->module_pointer = module_pointer;
3689 cmd->offset = CPU_TO_LE32(offset);
3690 cmd->length = CPU_TO_LE16(length);
3692 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3694 i40e_aq_erase_nvm_exit:
3699 * i40e_parse_discover_capabilities
3700 * @hw: pointer to the hw struct
3701 * @buff: pointer to a buffer containing device/function capability records
3702 * @cap_count: number of capability records in the list
3703 * @list_type_opc: type of capabilities list to parse
3705 * Parse the device/function capabilities list.
3707 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3709 enum i40e_admin_queue_opc list_type_opc)
3711 struct i40e_aqc_list_capabilities_element_resp *cap;
3712 u32 valid_functions, num_functions;
3713 u32 number, logical_id, phys_id;
3714 struct i40e_hw_capabilities *p;
3719 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3721 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3722 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3723 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3724 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3728 for (i = 0; i < cap_count; i++, cap++) {
3729 id = LE16_TO_CPU(cap->id);
3730 number = LE32_TO_CPU(cap->number);
3731 logical_id = LE32_TO_CPU(cap->logical_id);
3732 phys_id = LE32_TO_CPU(cap->phys_id);
3733 major_rev = cap->major_rev;
3736 case I40E_AQ_CAP_ID_SWITCH_MODE:
3737 p->switch_mode = number;
3738 i40e_debug(hw, I40E_DEBUG_INIT,
3739 "HW Capability: Switch mode = %d\n",
3742 case I40E_AQ_CAP_ID_MNG_MODE:
3743 p->management_mode = number;
3744 if (major_rev > 1) {
3745 p->mng_protocols_over_mctp = logical_id;
3746 i40e_debug(hw, I40E_DEBUG_INIT,
3747 "HW Capability: Protocols over MCTP = %d\n",
3748 p->mng_protocols_over_mctp);
3750 p->mng_protocols_over_mctp = 0;
3752 i40e_debug(hw, I40E_DEBUG_INIT,
3753 "HW Capability: Management Mode = %d\n",
3754 p->management_mode);
3756 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3757 p->npar_enable = number;
3758 i40e_debug(hw, I40E_DEBUG_INIT,
3759 "HW Capability: NPAR enable = %d\n",
3762 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3764 i40e_debug(hw, I40E_DEBUG_INIT,
3765 "HW Capability: OS2BMC = %d\n", p->os2bmc);
3767 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3768 p->valid_functions = number;
3769 i40e_debug(hw, I40E_DEBUG_INIT,
3770 "HW Capability: Valid Functions = %d\n",
3771 p->valid_functions);
3773 case I40E_AQ_CAP_ID_SRIOV:
3775 p->sr_iov_1_1 = true;
3776 i40e_debug(hw, I40E_DEBUG_INIT,
3777 "HW Capability: SR-IOV = %d\n",
3780 case I40E_AQ_CAP_ID_VF:
3781 p->num_vfs = number;
3782 p->vf_base_id = logical_id;
3783 i40e_debug(hw, I40E_DEBUG_INIT,
3784 "HW Capability: VF count = %d\n",
3786 i40e_debug(hw, I40E_DEBUG_INIT,
3787 "HW Capability: VF base_id = %d\n",
3790 case I40E_AQ_CAP_ID_VMDQ:
3793 i40e_debug(hw, I40E_DEBUG_INIT,
3794 "HW Capability: VMDQ = %d\n", p->vmdq);
3796 case I40E_AQ_CAP_ID_8021QBG:
3798 p->evb_802_1_qbg = true;
3799 i40e_debug(hw, I40E_DEBUG_INIT,
3800 "HW Capability: 802.1Qbg = %d\n", number);
3802 case I40E_AQ_CAP_ID_8021QBR:
3804 p->evb_802_1_qbh = true;
3805 i40e_debug(hw, I40E_DEBUG_INIT,
3806 "HW Capability: 802.1Qbh = %d\n", number);
3808 case I40E_AQ_CAP_ID_VSI:
3809 p->num_vsis = number;
3810 i40e_debug(hw, I40E_DEBUG_INIT,
3811 "HW Capability: VSI count = %d\n",
3814 case I40E_AQ_CAP_ID_DCB:
3817 p->enabled_tcmap = logical_id;
3820 i40e_debug(hw, I40E_DEBUG_INIT,
3821 "HW Capability: DCB = %d\n", p->dcb);
3822 i40e_debug(hw, I40E_DEBUG_INIT,
3823 "HW Capability: TC Mapping = %d\n",
3825 i40e_debug(hw, I40E_DEBUG_INIT,
3826 "HW Capability: TC Max = %d\n", p->maxtc);
3828 case I40E_AQ_CAP_ID_FCOE:
3831 i40e_debug(hw, I40E_DEBUG_INIT,
3832 "HW Capability: FCOE = %d\n", p->fcoe);
3834 case I40E_AQ_CAP_ID_ISCSI:
3837 i40e_debug(hw, I40E_DEBUG_INIT,
3838 "HW Capability: iSCSI = %d\n", p->iscsi);
3840 case I40E_AQ_CAP_ID_RSS:
3842 p->rss_table_size = number;
3843 p->rss_table_entry_width = logical_id;
3844 i40e_debug(hw, I40E_DEBUG_INIT,
3845 "HW Capability: RSS = %d\n", p->rss);
3846 i40e_debug(hw, I40E_DEBUG_INIT,
3847 "HW Capability: RSS table size = %d\n",
3849 i40e_debug(hw, I40E_DEBUG_INIT,
3850 "HW Capability: RSS table width = %d\n",
3851 p->rss_table_entry_width);
3853 case I40E_AQ_CAP_ID_RXQ:
3854 p->num_rx_qp = number;
3855 p->base_queue = phys_id;
3856 i40e_debug(hw, I40E_DEBUG_INIT,
3857 "HW Capability: Rx QP = %d\n", number);
3858 i40e_debug(hw, I40E_DEBUG_INIT,
3859 "HW Capability: base_queue = %d\n",
3862 case I40E_AQ_CAP_ID_TXQ:
3863 p->num_tx_qp = number;
3864 p->base_queue = phys_id;
3865 i40e_debug(hw, I40E_DEBUG_INIT,
3866 "HW Capability: Tx QP = %d\n", number);
3867 i40e_debug(hw, I40E_DEBUG_INIT,
3868 "HW Capability: base_queue = %d\n",
3871 case I40E_AQ_CAP_ID_MSIX:
3872 p->num_msix_vectors = number;
3873 i40e_debug(hw, I40E_DEBUG_INIT,
3874 "HW Capability: MSIX vector count = %d\n",
3875 p->num_msix_vectors);
3877 case I40E_AQ_CAP_ID_VF_MSIX:
3878 p->num_msix_vectors_vf = number;
3879 i40e_debug(hw, I40E_DEBUG_INIT,
3880 "HW Capability: MSIX VF vector count = %d\n",
3881 p->num_msix_vectors_vf);
3883 case I40E_AQ_CAP_ID_FLEX10:
3884 if (major_rev == 1) {
3886 p->flex10_enable = true;
3887 p->flex10_capable = true;
3890 /* Capability revision >= 2 */
3892 p->flex10_enable = true;
3894 p->flex10_capable = true;
3896 p->flex10_mode = logical_id;
3897 p->flex10_status = phys_id;
3898 i40e_debug(hw, I40E_DEBUG_INIT,
3899 "HW Capability: Flex10 mode = %d\n",
3901 i40e_debug(hw, I40E_DEBUG_INIT,
3902 "HW Capability: Flex10 status = %d\n",
3905 case I40E_AQ_CAP_ID_CEM:
3908 i40e_debug(hw, I40E_DEBUG_INIT,
3909 "HW Capability: CEM = %d\n", p->mgmt_cem);
3911 case I40E_AQ_CAP_ID_IWARP:
3914 i40e_debug(hw, I40E_DEBUG_INIT,
3915 "HW Capability: iWARP = %d\n", p->iwarp);
3917 case I40E_AQ_CAP_ID_LED:
3918 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3919 p->led[phys_id] = true;
3920 i40e_debug(hw, I40E_DEBUG_INIT,
3921 "HW Capability: LED - PIN %d\n", phys_id);
3923 case I40E_AQ_CAP_ID_SDP:
3924 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3925 p->sdp[phys_id] = true;
3926 i40e_debug(hw, I40E_DEBUG_INIT,
3927 "HW Capability: SDP - PIN %d\n", phys_id);
3929 case I40E_AQ_CAP_ID_MDIO:
3931 p->mdio_port_num = phys_id;
3932 p->mdio_port_mode = logical_id;
3934 i40e_debug(hw, I40E_DEBUG_INIT,
3935 "HW Capability: MDIO port number = %d\n",
3937 i40e_debug(hw, I40E_DEBUG_INIT,
3938 "HW Capability: MDIO port mode = %d\n",
3941 case I40E_AQ_CAP_ID_1588:
3943 p->ieee_1588 = true;
3944 i40e_debug(hw, I40E_DEBUG_INIT,
3945 "HW Capability: IEEE 1588 = %d\n",
3948 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3950 p->fd_filters_guaranteed = number;
3951 p->fd_filters_best_effort = logical_id;
3952 i40e_debug(hw, I40E_DEBUG_INIT,
3953 "HW Capability: Flow Director = 1\n");
3954 i40e_debug(hw, I40E_DEBUG_INIT,
3955 "HW Capability: Guaranteed FD filters = %d\n",
3956 p->fd_filters_guaranteed);
3958 case I40E_AQ_CAP_ID_WSR_PROT:
3959 p->wr_csr_prot = (u64)number;
3960 p->wr_csr_prot |= (u64)logical_id << 32;
3961 i40e_debug(hw, I40E_DEBUG_INIT,
3962 "HW Capability: wr_csr_prot = 0x%llX\n\n",
3963 (p->wr_csr_prot & 0xffff));
3965 case I40E_AQ_CAP_ID_NVM_MGMT:
3966 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3967 p->sec_rev_disabled = true;
3968 if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3969 p->update_disabled = true;
3971 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3972 hw->num_wol_proxy_filters = (u16)number;
3973 hw->wol_proxy_vsi_seid = (u16)logical_id;
3974 p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3975 if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3976 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3978 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3979 p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3980 i40e_debug(hw, I40E_DEBUG_INIT,
3981 "HW Capability: WOL proxy filters = %d\n",
3982 hw->num_wol_proxy_filters);
3990 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3992 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3995 /* count the enabled ports (aka the "not disabled" ports) */
3997 for (i = 0; i < 4; i++) {
3998 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
4001 /* use AQ read to get the physical register offset instead
4002 * of the port relative offset
4004 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
4005 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
4009 valid_functions = p->valid_functions;
4011 while (valid_functions) {
4012 if (valid_functions & 1)
4014 valid_functions >>= 1;
4017 /* partition id is 1-based, and functions are evenly spread
4018 * across the ports as partitions
4020 if (hw->num_ports != 0) {
4021 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
4022 hw->num_partitions = num_functions / hw->num_ports;
4025 /* additional HW specific goodies that might
4026 * someday be HW version specific
4028 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
4032 * i40e_aq_discover_capabilities
4033 * @hw: pointer to the hw struct
4034 * @buff: a virtual buffer to hold the capabilities
4035 * @buff_size: Size of the virtual buffer
4036 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
4037 * @list_type_opc: capabilities type to discover - pass in the command opcode
4038 * @cmd_details: pointer to command details structure or NULL
4040 * Get the device capabilities descriptions from the firmware
4042 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
4043 void *buff, u16 buff_size, u16 *data_size,
4044 enum i40e_admin_queue_opc list_type_opc,
4045 struct i40e_asq_cmd_details *cmd_details)
4047 struct i40e_aqc_list_capabilites *cmd;
4048 struct i40e_aq_desc desc;
4049 enum i40e_status_code status = I40E_SUCCESS;
4051 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
4053 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
4054 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
4055 status = I40E_ERR_PARAM;
4059 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
4061 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4062 if (buff_size > I40E_AQ_LARGE_BUF)
4063 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4065 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4066 *data_size = LE16_TO_CPU(desc.datalen);
4071 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
4079 * i40e_aq_update_nvm
4080 * @hw: pointer to the hw struct
4081 * @module_pointer: module pointer location in words from the NVM beginning
4082 * @offset: byte offset from the module beginning
4083 * @length: length of the section to be written (in bytes from the offset)
4084 * @data: command buffer (size [bytes] = length)
4085 * @last_command: tells if this is the last command in a series
4086 * @preservation_flags: Preservation mode flags
4087 * @cmd_details: pointer to command details structure or NULL
4089 * Update the NVM using the admin queue commands
4091 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
4092 u32 offset, u16 length, void *data,
4093 bool last_command, u8 preservation_flags,
4094 struct i40e_asq_cmd_details *cmd_details)
4096 struct i40e_aq_desc desc;
4097 struct i40e_aqc_nvm_update *cmd =
4098 (struct i40e_aqc_nvm_update *)&desc.params.raw;
4099 enum i40e_status_code status;
4101 DEBUGFUNC("i40e_aq_update_nvm");
4103 /* In offset the highest byte must be zeroed. */
4104 if (offset & 0xFF000000) {
4105 status = I40E_ERR_PARAM;
4106 goto i40e_aq_update_nvm_exit;
4109 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4111 /* If this is the last command in a series, set the proper flag. */
4113 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
4114 if (hw->mac.type == I40E_MAC_X722) {
4115 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED)
4116 cmd->command_flags |=
4117 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED <<
4118 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4119 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL)
4120 cmd->command_flags |=
4121 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL <<
4122 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4124 cmd->module_pointer = module_pointer;
4125 cmd->offset = CPU_TO_LE32(offset);
4126 cmd->length = CPU_TO_LE16(length);
4128 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4129 if (length > I40E_AQ_LARGE_BUF)
4130 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4132 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
4134 i40e_aq_update_nvm_exit:
4139 * i40e_aq_nvm_progress
4140 * @hw: pointer to the hw struct
4141 * @progress: pointer to progress returned from AQ
4142 * @cmd_details: pointer to command details structure or NULL
4144 * Gets progress of flash rearrangement process
4146 enum i40e_status_code i40e_aq_nvm_progress(struct i40e_hw *hw, u8 *progress,
4147 struct i40e_asq_cmd_details *cmd_details)
4149 enum i40e_status_code status;
4150 struct i40e_aq_desc desc;
4152 DEBUGFUNC("i40e_aq_nvm_progress");
4154 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_progress);
4155 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4156 *progress = desc.params.raw[0];
4161 * i40e_aq_get_lldp_mib
4162 * @hw: pointer to the hw struct
4163 * @bridge_type: type of bridge requested
4164 * @mib_type: Local, Remote or both Local and Remote MIBs
4165 * @buff: pointer to a user supplied buffer to store the MIB block
4166 * @buff_size: size of the buffer (in bytes)
4167 * @local_len : length of the returned Local LLDP MIB
4168 * @remote_len: length of the returned Remote LLDP MIB
4169 * @cmd_details: pointer to command details structure or NULL
4171 * Requests the complete LLDP MIB (entire packet).
4173 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4174 u8 mib_type, void *buff, u16 buff_size,
4175 u16 *local_len, u16 *remote_len,
4176 struct i40e_asq_cmd_details *cmd_details)
4178 struct i40e_aq_desc desc;
4179 struct i40e_aqc_lldp_get_mib *cmd =
4180 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4181 struct i40e_aqc_lldp_get_mib *resp =
4182 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4183 enum i40e_status_code status;
4185 if (buff_size == 0 || !buff)
4186 return I40E_ERR_PARAM;
4188 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4189 /* Indirect Command */
4190 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4192 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4193 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4194 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4196 desc.datalen = CPU_TO_LE16(buff_size);
4198 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4199 if (buff_size > I40E_AQ_LARGE_BUF)
4200 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4202 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4204 if (local_len != NULL)
4205 *local_len = LE16_TO_CPU(resp->local_len);
4206 if (remote_len != NULL)
4207 *remote_len = LE16_TO_CPU(resp->remote_len);
4214 * i40e_aq_set_lldp_mib - Set the LLDP MIB
4215 * @hw: pointer to the hw struct
4216 * @mib_type: Local, Remote or both Local and Remote MIBs
4217 * @buff: pointer to a user supplied buffer to store the MIB block
4218 * @buff_size: size of the buffer (in bytes)
4219 * @cmd_details: pointer to command details structure or NULL
4223 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4224 u8 mib_type, void *buff, u16 buff_size,
4225 struct i40e_asq_cmd_details *cmd_details)
4227 struct i40e_aq_desc desc;
4228 struct i40e_aqc_lldp_set_local_mib *cmd =
4229 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4230 enum i40e_status_code status;
4232 if (buff_size == 0 || !buff)
4233 return I40E_ERR_PARAM;
4235 i40e_fill_default_direct_cmd_desc(&desc,
4236 i40e_aqc_opc_lldp_set_local_mib);
4237 /* Indirect Command */
4238 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4239 if (buff_size > I40E_AQ_LARGE_BUF)
4240 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4241 desc.datalen = CPU_TO_LE16(buff_size);
4243 cmd->type = mib_type;
4244 cmd->length = CPU_TO_LE16(buff_size);
4245 cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4246 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4248 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4253 * i40e_aq_cfg_lldp_mib_change_event
4254 * @hw: pointer to the hw struct
4255 * @enable_update: Enable or Disable event posting
4256 * @cmd_details: pointer to command details structure or NULL
4258 * Enable or Disable posting of an event on ARQ when LLDP MIB
4259 * associated with the interface changes
4261 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4263 struct i40e_asq_cmd_details *cmd_details)
4265 struct i40e_aq_desc desc;
4266 struct i40e_aqc_lldp_update_mib *cmd =
4267 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4268 enum i40e_status_code status;
4270 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4273 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4275 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4281 * i40e_aq_add_lldp_tlv
4282 * @hw: pointer to the hw struct
4283 * @bridge_type: type of bridge
4284 * @buff: buffer with TLV to add
4285 * @buff_size: length of the buffer
4286 * @tlv_len: length of the TLV to be added
4287 * @mib_len: length of the LLDP MIB returned in response
4288 * @cmd_details: pointer to command details structure or NULL
4290 * Add the specified TLV to LLDP Local MIB for the given bridge type,
4291 * it is responsibility of the caller to make sure that the TLV is not
4292 * already present in the LLDPDU.
4293 * In return firmware will write the complete LLDP MIB with the newly
4294 * added TLV in the response buffer.
4296 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4297 void *buff, u16 buff_size, u16 tlv_len,
4299 struct i40e_asq_cmd_details *cmd_details)
4301 struct i40e_aq_desc desc;
4302 struct i40e_aqc_lldp_add_tlv *cmd =
4303 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4304 enum i40e_status_code status;
4306 if (buff_size == 0 || !buff || tlv_len == 0)
4307 return I40E_ERR_PARAM;
4309 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4311 /* Indirect Command */
4312 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4313 if (buff_size > I40E_AQ_LARGE_BUF)
4314 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4315 desc.datalen = CPU_TO_LE16(buff_size);
4317 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4318 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4319 cmd->len = CPU_TO_LE16(tlv_len);
4321 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4323 if (mib_len != NULL)
4324 *mib_len = LE16_TO_CPU(desc.datalen);
4331 * i40e_aq_update_lldp_tlv
4332 * @hw: pointer to the hw struct
4333 * @bridge_type: type of bridge
4334 * @buff: buffer with TLV to update
4335 * @buff_size: size of the buffer holding original and updated TLVs
4336 * @old_len: Length of the Original TLV
4337 * @new_len: Length of the Updated TLV
4338 * @offset: offset of the updated TLV in the buff
4339 * @mib_len: length of the returned LLDP MIB
4340 * @cmd_details: pointer to command details structure or NULL
4342 * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4343 * Firmware will place the complete LLDP MIB in response buffer with the
4346 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4347 u8 bridge_type, void *buff, u16 buff_size,
4348 u16 old_len, u16 new_len, u16 offset,
4350 struct i40e_asq_cmd_details *cmd_details)
4352 struct i40e_aq_desc desc;
4353 struct i40e_aqc_lldp_update_tlv *cmd =
4354 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4355 enum i40e_status_code status;
4357 if (buff_size == 0 || !buff || offset == 0 ||
4358 old_len == 0 || new_len == 0)
4359 return I40E_ERR_PARAM;
4361 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4363 /* Indirect Command */
4364 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4365 if (buff_size > I40E_AQ_LARGE_BUF)
4366 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4367 desc.datalen = CPU_TO_LE16(buff_size);
4369 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4370 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4371 cmd->old_len = CPU_TO_LE16(old_len);
4372 cmd->new_offset = CPU_TO_LE16(offset);
4373 cmd->new_len = CPU_TO_LE16(new_len);
4375 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4377 if (mib_len != NULL)
4378 *mib_len = LE16_TO_CPU(desc.datalen);
4385 * i40e_aq_delete_lldp_tlv
4386 * @hw: pointer to the hw struct
4387 * @bridge_type: type of bridge
4388 * @buff: pointer to a user supplied buffer that has the TLV
4389 * @buff_size: length of the buffer
4390 * @tlv_len: length of the TLV to be deleted
4391 * @mib_len: length of the returned LLDP MIB
4392 * @cmd_details: pointer to command details structure or NULL
4394 * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4395 * The firmware places the entire LLDP MIB in the response buffer.
4397 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4398 u8 bridge_type, void *buff, u16 buff_size,
4399 u16 tlv_len, u16 *mib_len,
4400 struct i40e_asq_cmd_details *cmd_details)
4402 struct i40e_aq_desc desc;
4403 struct i40e_aqc_lldp_add_tlv *cmd =
4404 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4405 enum i40e_status_code status;
4407 if (buff_size == 0 || !buff)
4408 return I40E_ERR_PARAM;
4410 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4412 /* Indirect Command */
4413 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4414 if (buff_size > I40E_AQ_LARGE_BUF)
4415 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4416 desc.datalen = CPU_TO_LE16(buff_size);
4417 cmd->len = CPU_TO_LE16(tlv_len);
4418 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4419 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4421 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4423 if (mib_len != NULL)
4424 *mib_len = LE16_TO_CPU(desc.datalen);
4432 * @hw: pointer to the hw struct
4433 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4434 * @cmd_details: pointer to command details structure or NULL
4436 * Stop or Shutdown the embedded LLDP Agent
4438 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4439 struct i40e_asq_cmd_details *cmd_details)
4441 struct i40e_aq_desc desc;
4442 struct i40e_aqc_lldp_stop *cmd =
4443 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4444 enum i40e_status_code status;
4446 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4449 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4451 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4457 * i40e_aq_start_lldp
4458 * @hw: pointer to the hw struct
4459 * @cmd_details: pointer to command details structure or NULL
4461 * Start the embedded LLDP Agent on all ports.
4463 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4464 struct i40e_asq_cmd_details *cmd_details)
4466 struct i40e_aq_desc desc;
4467 struct i40e_aqc_lldp_start *cmd =
4468 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4469 enum i40e_status_code status;
4471 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4473 cmd->command = I40E_AQ_LLDP_AGENT_START;
4474 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4480 * i40e_aq_set_dcb_parameters
4481 * @hw: pointer to the hw struct
4482 * @cmd_details: pointer to command details structure or NULL
4483 * @dcb_enable: True if DCB configuration needs to be applied
4486 enum i40e_status_code
4487 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable,
4488 struct i40e_asq_cmd_details *cmd_details)
4490 struct i40e_aq_desc desc;
4491 struct i40e_aqc_set_dcb_parameters *cmd =
4492 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw;
4493 enum i40e_status_code status;
4495 i40e_fill_default_direct_cmd_desc(&desc,
4496 i40e_aqc_opc_set_dcb_parameters);
4499 cmd->valid_flags = I40E_DCB_VALID;
4500 cmd->command = I40E_AQ_DCB_SET_AGENT;
4502 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4508 * i40e_aq_get_cee_dcb_config
4509 * @hw: pointer to the hw struct
4510 * @buff: response buffer that stores CEE operational configuration
4511 * @buff_size: size of the buffer passed
4512 * @cmd_details: pointer to command details structure or NULL
4514 * Get CEE DCBX mode operational configuration from firmware
4516 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4517 void *buff, u16 buff_size,
4518 struct i40e_asq_cmd_details *cmd_details)
4520 struct i40e_aq_desc desc;
4521 enum i40e_status_code status;
4523 if (buff_size == 0 || !buff)
4524 return I40E_ERR_PARAM;
4526 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4528 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4529 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4536 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4537 * @hw: pointer to the hw struct
4538 * @start_agent: True if DCBx Agent needs to be Started
4539 * False if DCBx Agent needs to be Stopped
4540 * @cmd_details: pointer to command details structure or NULL
4542 * Start/Stop the embedded dcbx Agent
4544 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4546 struct i40e_asq_cmd_details *cmd_details)
4548 struct i40e_aq_desc desc;
4549 struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4550 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4552 enum i40e_status_code status;
4554 i40e_fill_default_direct_cmd_desc(&desc,
4555 i40e_aqc_opc_lldp_stop_start_spec_agent);
4558 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4560 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4566 * i40e_aq_add_udp_tunnel
4567 * @hw: pointer to the hw struct
4568 * @udp_port: the UDP port to add in Host byte order
4569 * @protocol_index: protocol index type
4570 * @filter_index: pointer to filter index
4571 * @cmd_details: pointer to command details structure or NULL
4573 * Note: Firmware expects the udp_port value to be in Little Endian format,
4574 * and this function will call CPU_TO_LE16 to convert from Host byte order to
4575 * Little Endian order.
4577 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4578 u16 udp_port, u8 protocol_index,
4580 struct i40e_asq_cmd_details *cmd_details)
4582 struct i40e_aq_desc desc;
4583 struct i40e_aqc_add_udp_tunnel *cmd =
4584 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4585 struct i40e_aqc_del_udp_tunnel_completion *resp =
4586 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4587 enum i40e_status_code status;
4589 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4591 cmd->udp_port = CPU_TO_LE16(udp_port);
4592 cmd->protocol_type = protocol_index;
4594 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4596 if (!status && filter_index)
4597 *filter_index = resp->index;
4603 * i40e_aq_del_udp_tunnel
4604 * @hw: pointer to the hw struct
4605 * @index: filter index
4606 * @cmd_details: pointer to command details structure or NULL
4608 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4609 struct i40e_asq_cmd_details *cmd_details)
4611 struct i40e_aq_desc desc;
4612 struct i40e_aqc_remove_udp_tunnel *cmd =
4613 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4614 enum i40e_status_code status;
4616 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4620 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4626 * i40e_aq_get_switch_resource_alloc (0x0204)
4627 * @hw: pointer to the hw struct
4628 * @num_entries: pointer to u8 to store the number of resource entries returned
4629 * @buf: pointer to a user supplied buffer. This buffer must be large enough
4630 * to store the resource information for all resource types. Each
4631 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
4632 * @count: size, in bytes, of the buffer provided
4633 * @cmd_details: pointer to command details structure or NULL
4635 * Query the resources allocated to a function.
4637 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4639 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4641 struct i40e_asq_cmd_details *cmd_details)
4643 struct i40e_aq_desc desc;
4644 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4645 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4646 enum i40e_status_code status;
4647 u16 length = count * sizeof(*buf);
4649 i40e_fill_default_direct_cmd_desc(&desc,
4650 i40e_aqc_opc_get_switch_resource_alloc);
4652 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4653 if (length > I40E_AQ_LARGE_BUF)
4654 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4656 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4658 if (!status && num_entries)
4659 *num_entries = cmd_resp->num_entries;
4665 * i40e_aq_delete_element - Delete switch element
4666 * @hw: pointer to the hw struct
4667 * @seid: the SEID to delete from the switch
4668 * @cmd_details: pointer to command details structure or NULL
4670 * This deletes a switch element from the switch.
4672 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4673 struct i40e_asq_cmd_details *cmd_details)
4675 struct i40e_aq_desc desc;
4676 struct i40e_aqc_switch_seid *cmd =
4677 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4678 enum i40e_status_code status;
4681 return I40E_ERR_PARAM;
4683 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4685 cmd->seid = CPU_TO_LE16(seid);
4687 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4693 * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4694 * @hw: pointer to the hw struct
4695 * @flags: component flags
4696 * @mac_seid: uplink seid (MAC SEID)
4697 * @vsi_seid: connected vsi seid
4698 * @ret_seid: seid of create pv component
4700 * This instantiates an i40e port virtualizer with specified flags.
4701 * Depending on specified flags the port virtualizer can act as a
4702 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4704 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4705 u16 mac_seid, u16 vsi_seid,
4708 struct i40e_aq_desc desc;
4709 struct i40e_aqc_add_update_pv *cmd =
4710 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4711 struct i40e_aqc_add_update_pv_completion *resp =
4712 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4713 enum i40e_status_code status;
4716 return I40E_ERR_PARAM;
4718 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4719 cmd->command_flags = CPU_TO_LE16(flags);
4720 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4721 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4723 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4724 if (!status && ret_seid)
4725 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4731 * i40e_aq_add_tag - Add an S/E-tag
4732 * @hw: pointer to the hw struct
4733 * @direct_to_queue: should s-tag direct flow to a specific queue
4734 * @vsi_seid: VSI SEID to use this tag
4735 * @tag: value of the tag
4736 * @queue_num: queue number, only valid is direct_to_queue is true
4737 * @tags_used: return value, number of tags in use by this PF
4738 * @tags_free: return value, number of unallocated tags
4739 * @cmd_details: pointer to command details structure or NULL
4741 * This associates an S- or E-tag to a VSI in the switch complex. It returns
4742 * the number of tags allocated by the PF, and the number of unallocated
4745 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4746 u16 vsi_seid, u16 tag, u16 queue_num,
4747 u16 *tags_used, u16 *tags_free,
4748 struct i40e_asq_cmd_details *cmd_details)
4750 struct i40e_aq_desc desc;
4751 struct i40e_aqc_add_tag *cmd =
4752 (struct i40e_aqc_add_tag *)&desc.params.raw;
4753 struct i40e_aqc_add_remove_tag_completion *resp =
4754 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4755 enum i40e_status_code status;
4758 return I40E_ERR_PARAM;
4760 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4762 cmd->seid = CPU_TO_LE16(vsi_seid);
4763 cmd->tag = CPU_TO_LE16(tag);
4764 if (direct_to_queue) {
4765 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4766 cmd->queue_number = CPU_TO_LE16(queue_num);
4769 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4772 if (tags_used != NULL)
4773 *tags_used = LE16_TO_CPU(resp->tags_used);
4774 if (tags_free != NULL)
4775 *tags_free = LE16_TO_CPU(resp->tags_free);
4782 * i40e_aq_remove_tag - Remove an S- or E-tag
4783 * @hw: pointer to the hw struct
4784 * @vsi_seid: VSI SEID this tag is associated with
4785 * @tag: value of the S-tag to delete
4786 * @tags_used: return value, number of tags in use by this PF
4787 * @tags_free: return value, number of unallocated tags
4788 * @cmd_details: pointer to command details structure or NULL
4790 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
4791 * the number of tags allocated by the PF, and the number of unallocated
4794 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4795 u16 tag, u16 *tags_used, u16 *tags_free,
4796 struct i40e_asq_cmd_details *cmd_details)
4798 struct i40e_aq_desc desc;
4799 struct i40e_aqc_remove_tag *cmd =
4800 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4801 struct i40e_aqc_add_remove_tag_completion *resp =
4802 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4803 enum i40e_status_code status;
4806 return I40E_ERR_PARAM;
4808 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4810 cmd->seid = CPU_TO_LE16(vsi_seid);
4811 cmd->tag = CPU_TO_LE16(tag);
4813 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4816 if (tags_used != NULL)
4817 *tags_used = LE16_TO_CPU(resp->tags_used);
4818 if (tags_free != NULL)
4819 *tags_free = LE16_TO_CPU(resp->tags_free);
4826 * i40e_aq_add_mcast_etag - Add a multicast E-tag
4827 * @hw: pointer to the hw struct
4828 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4829 * @etag: value of E-tag to add
4830 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4831 * @buf: address of indirect buffer
4832 * @tags_used: return value, number of E-tags in use by this port
4833 * @tags_free: return value, number of unallocated M-tags
4834 * @cmd_details: pointer to command details structure or NULL
4836 * This associates a multicast E-tag to a port virtualizer. It will return
4837 * the number of tags allocated by the PF, and the number of unallocated
4840 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4841 * num_tags_in_buf long.
4843 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4844 u16 etag, u8 num_tags_in_buf, void *buf,
4845 u16 *tags_used, u16 *tags_free,
4846 struct i40e_asq_cmd_details *cmd_details)
4848 struct i40e_aq_desc desc;
4849 struct i40e_aqc_add_remove_mcast_etag *cmd =
4850 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4851 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4852 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4853 enum i40e_status_code status;
4854 u16 length = sizeof(u16) * num_tags_in_buf;
4856 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4857 return I40E_ERR_PARAM;
4859 i40e_fill_default_direct_cmd_desc(&desc,
4860 i40e_aqc_opc_add_multicast_etag);
4862 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4863 cmd->etag = CPU_TO_LE16(etag);
4864 cmd->num_unicast_etags = num_tags_in_buf;
4866 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4867 if (length > I40E_AQ_LARGE_BUF)
4868 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4870 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4873 if (tags_used != NULL)
4874 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4875 if (tags_free != NULL)
4876 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4883 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4884 * @hw: pointer to the hw struct
4885 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4886 * @etag: value of the E-tag to remove
4887 * @tags_used: return value, number of tags in use by this port
4888 * @tags_free: return value, number of unallocated tags
4889 * @cmd_details: pointer to command details structure or NULL
4891 * This deletes an E-tag from the port virtualizer. It will return
4892 * the number of tags allocated by the port, and the number of unallocated
4895 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4896 u16 etag, u16 *tags_used, u16 *tags_free,
4897 struct i40e_asq_cmd_details *cmd_details)
4899 struct i40e_aq_desc desc;
4900 struct i40e_aqc_add_remove_mcast_etag *cmd =
4901 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4902 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4903 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4904 enum i40e_status_code status;
4908 return I40E_ERR_PARAM;
4910 i40e_fill_default_direct_cmd_desc(&desc,
4911 i40e_aqc_opc_remove_multicast_etag);
4913 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4914 cmd->etag = CPU_TO_LE16(etag);
4916 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4919 if (tags_used != NULL)
4920 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4921 if (tags_free != NULL)
4922 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4929 * i40e_aq_update_tag - Update an S/E-tag
4930 * @hw: pointer to the hw struct
4931 * @vsi_seid: VSI SEID using this S-tag
4932 * @old_tag: old tag value
4933 * @new_tag: new tag value
4934 * @tags_used: return value, number of tags in use by this PF
4935 * @tags_free: return value, number of unallocated tags
4936 * @cmd_details: pointer to command details structure or NULL
4938 * This updates the value of the tag currently attached to this VSI
4939 * in the switch complex. It will return the number of tags allocated
4940 * by the PF, and the number of unallocated tags available.
4942 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4943 u16 old_tag, u16 new_tag, u16 *tags_used,
4945 struct i40e_asq_cmd_details *cmd_details)
4947 struct i40e_aq_desc desc;
4948 struct i40e_aqc_update_tag *cmd =
4949 (struct i40e_aqc_update_tag *)&desc.params.raw;
4950 struct i40e_aqc_update_tag_completion *resp =
4951 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4952 enum i40e_status_code status;
4955 return I40E_ERR_PARAM;
4957 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4959 cmd->seid = CPU_TO_LE16(vsi_seid);
4960 cmd->old_tag = CPU_TO_LE16(old_tag);
4961 cmd->new_tag = CPU_TO_LE16(new_tag);
4963 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4966 if (tags_used != NULL)
4967 *tags_used = LE16_TO_CPU(resp->tags_used);
4968 if (tags_free != NULL)
4969 *tags_free = LE16_TO_CPU(resp->tags_free);
4976 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4977 * @hw: pointer to the hw struct
4978 * @tcmap: TC map for request/release any ignore PFC condition
4979 * @request: request or release ignore PFC condition
4980 * @tcmap_ret: return TCs for which PFC is currently ignored
4981 * @cmd_details: pointer to command details structure or NULL
4983 * This sends out request/release to ignore PFC condition for a TC.
4984 * It will return the TCs for which PFC is currently ignored.
4986 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4987 bool request, u8 *tcmap_ret,
4988 struct i40e_asq_cmd_details *cmd_details)
4990 struct i40e_aq_desc desc;
4991 struct i40e_aqc_pfc_ignore *cmd_resp =
4992 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4993 enum i40e_status_code status;
4995 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4998 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
5000 cmd_resp->tc_bitmap = tcmap;
5002 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5005 if (tcmap_ret != NULL)
5006 *tcmap_ret = cmd_resp->tc_bitmap;
5013 * i40e_aq_dcb_updated - DCB Updated Command
5014 * @hw: pointer to the hw struct
5015 * @cmd_details: pointer to command details structure or NULL
5017 * When LLDP is handled in PF this command is used by the PF
5018 * to notify EMP that a DCB setting is modified.
5019 * When LLDP is handled in EMP this command is used by the PF
5020 * to notify EMP whenever one of the following parameters get
5022 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
5023 * - PCIRTT in PRTDCB_GENC.PCIRTT
5024 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
5025 * EMP will return when the shared RPB settings have been
5026 * recomputed and modified. The retval field in the descriptor
5027 * will be set to 0 when RPB is modified.
5029 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
5030 struct i40e_asq_cmd_details *cmd_details)
5032 struct i40e_aq_desc desc;
5033 enum i40e_status_code status;
5035 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
5037 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5043 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
5044 * @hw: pointer to the hw struct
5045 * @seid: defines the SEID of the switch for which the stats are requested
5046 * @vlan_id: the VLAN ID for which the statistics are requested
5047 * @stat_index: index of the statistics counters block assigned to this VLAN
5048 * @cmd_details: pointer to command details structure or NULL
5050 * XL710 supports 128 smonVlanStats counters.This command is used to
5051 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
5054 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
5055 u16 vlan_id, u16 *stat_index,
5056 struct i40e_asq_cmd_details *cmd_details)
5058 struct i40e_aq_desc desc;
5059 struct i40e_aqc_add_remove_statistics *cmd_resp =
5060 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5061 enum i40e_status_code status;
5063 if ((seid == 0) || (stat_index == NULL))
5064 return I40E_ERR_PARAM;
5066 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
5068 cmd_resp->seid = CPU_TO_LE16(seid);
5069 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
5071 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5073 if (!status && stat_index)
5074 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
5080 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
5081 * @hw: pointer to the hw struct
5082 * @seid: defines the SEID of the switch for which the stats are requested
5083 * @vlan_id: the VLAN ID for which the statistics are requested
5084 * @stat_index: index of the statistics counters block assigned to this VLAN
5085 * @cmd_details: pointer to command details structure or NULL
5087 * XL710 supports 128 smonVlanStats counters.This command is used to
5088 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
5091 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
5092 u16 vlan_id, u16 stat_index,
5093 struct i40e_asq_cmd_details *cmd_details)
5095 struct i40e_aq_desc desc;
5096 struct i40e_aqc_add_remove_statistics *cmd =
5097 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5098 enum i40e_status_code status;
5101 return I40E_ERR_PARAM;
5103 i40e_fill_default_direct_cmd_desc(&desc,
5104 i40e_aqc_opc_remove_statistics);
5106 cmd->seid = CPU_TO_LE16(seid);
5107 cmd->vlan = CPU_TO_LE16(vlan_id);
5108 cmd->stat_index = CPU_TO_LE16(stat_index);
5110 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5116 * i40e_aq_set_port_parameters - set physical port parameters.
5117 * @hw: pointer to the hw struct
5118 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
5119 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
5120 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
5121 * @double_vlan: if set double VLAN is enabled
5122 * @cmd_details: pointer to command details structure or NULL
5124 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
5125 u16 bad_frame_vsi, bool save_bad_pac,
5126 bool pad_short_pac, bool double_vlan,
5127 struct i40e_asq_cmd_details *cmd_details)
5129 struct i40e_aqc_set_port_parameters *cmd;
5130 enum i40e_status_code status;
5131 struct i40e_aq_desc desc;
5132 u16 command_flags = 0;
5134 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
5136 i40e_fill_default_direct_cmd_desc(&desc,
5137 i40e_aqc_opc_set_port_parameters);
5139 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
5141 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
5143 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
5145 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
5146 cmd->command_flags = CPU_TO_LE16(command_flags);
5148 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5154 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
5155 * @hw: pointer to the hw struct
5156 * @seid: seid for the physical port/switching component/vsi
5157 * @buff: Indirect buffer to hold data parameters and response
5158 * @buff_size: Indirect buffer size
5159 * @opcode: Tx scheduler AQ command opcode
5160 * @cmd_details: pointer to command details structure or NULL
5162 * Generic command handler for Tx scheduler AQ commands
5164 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
5165 void *buff, u16 buff_size,
5166 enum i40e_admin_queue_opc opcode,
5167 struct i40e_asq_cmd_details *cmd_details)
5169 struct i40e_aq_desc desc;
5170 struct i40e_aqc_tx_sched_ind *cmd =
5171 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
5172 enum i40e_status_code status;
5173 bool cmd_param_flag = false;
5176 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
5177 case i40e_aqc_opc_configure_vsi_tc_bw:
5178 case i40e_aqc_opc_enable_switching_comp_ets:
5179 case i40e_aqc_opc_modify_switching_comp_ets:
5180 case i40e_aqc_opc_disable_switching_comp_ets:
5181 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
5182 case i40e_aqc_opc_configure_switching_comp_bw_config:
5183 cmd_param_flag = true;
5185 case i40e_aqc_opc_query_vsi_bw_config:
5186 case i40e_aqc_opc_query_vsi_ets_sla_config:
5187 case i40e_aqc_opc_query_switching_comp_ets_config:
5188 case i40e_aqc_opc_query_port_ets_config:
5189 case i40e_aqc_opc_query_switching_comp_bw_config:
5190 cmd_param_flag = false;
5193 return I40E_ERR_PARAM;
5196 i40e_fill_default_direct_cmd_desc(&desc, opcode);
5198 /* Indirect command */
5199 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5201 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5202 if (buff_size > I40E_AQ_LARGE_BUF)
5203 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5205 desc.datalen = CPU_TO_LE16(buff_size);
5207 cmd->vsi_seid = CPU_TO_LE16(seid);
5209 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5215 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5216 * @hw: pointer to the hw struct
5218 * @credit: BW limit credits (0 = disabled)
5219 * @max_credit: Max BW limit credits
5220 * @cmd_details: pointer to command details structure or NULL
5222 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5223 u16 seid, u16 credit, u8 max_credit,
5224 struct i40e_asq_cmd_details *cmd_details)
5226 struct i40e_aq_desc desc;
5227 struct i40e_aqc_configure_vsi_bw_limit *cmd =
5228 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5229 enum i40e_status_code status;
5231 i40e_fill_default_direct_cmd_desc(&desc,
5232 i40e_aqc_opc_configure_vsi_bw_limit);
5234 cmd->vsi_seid = CPU_TO_LE16(seid);
5235 cmd->credit = CPU_TO_LE16(credit);
5236 cmd->max_credit = max_credit;
5238 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5244 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5245 * @hw: pointer to the hw struct
5246 * @seid: switching component seid
5247 * @credit: BW limit credits (0 = disabled)
5248 * @max_bw: Max BW limit credits
5249 * @cmd_details: pointer to command details structure or NULL
5251 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5252 u16 seid, u16 credit, u8 max_bw,
5253 struct i40e_asq_cmd_details *cmd_details)
5255 struct i40e_aq_desc desc;
5256 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5257 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5258 enum i40e_status_code status;
5260 i40e_fill_default_direct_cmd_desc(&desc,
5261 i40e_aqc_opc_configure_switching_comp_bw_limit);
5263 cmd->seid = CPU_TO_LE16(seid);
5264 cmd->credit = CPU_TO_LE16(credit);
5265 cmd->max_bw = max_bw;
5267 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5273 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5274 * @hw: pointer to the hw struct
5276 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5277 * @cmd_details: pointer to command details structure or NULL
5279 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5281 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5282 struct i40e_asq_cmd_details *cmd_details)
5284 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5285 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5290 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5291 * @hw: pointer to the hw struct
5293 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5294 * @cmd_details: pointer to command details structure or NULL
5296 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5298 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5299 struct i40e_asq_cmd_details *cmd_details)
5301 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5302 i40e_aqc_opc_configure_vsi_tc_bw,
5307 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5308 * @hw: pointer to the hw struct
5309 * @seid: seid of the switching component connected to Physical Port
5310 * @ets_data: Buffer holding ETS parameters
5311 * @opcode: Tx scheduler AQ command opcode
5312 * @cmd_details: pointer to command details structure or NULL
5314 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5316 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5317 enum i40e_admin_queue_opc opcode,
5318 struct i40e_asq_cmd_details *cmd_details)
5320 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5321 sizeof(*ets_data), opcode, cmd_details);
5325 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5326 * @hw: pointer to the hw struct
5327 * @seid: seid of the switching component
5328 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5329 * @cmd_details: pointer to command details structure or NULL
5331 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5333 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5334 struct i40e_asq_cmd_details *cmd_details)
5336 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5337 i40e_aqc_opc_configure_switching_comp_bw_config,
5342 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5343 * @hw: pointer to the hw struct
5344 * @seid: seid of the switching component
5345 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5346 * @cmd_details: pointer to command details structure or NULL
5348 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5349 struct i40e_hw *hw, u16 seid,
5350 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5351 struct i40e_asq_cmd_details *cmd_details)
5353 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5354 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5359 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5360 * @hw: pointer to the hw struct
5361 * @seid: seid of the VSI
5362 * @bw_data: Buffer to hold VSI BW configuration
5363 * @cmd_details: pointer to command details structure or NULL
5365 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5367 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5368 struct i40e_asq_cmd_details *cmd_details)
5370 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5371 i40e_aqc_opc_query_vsi_bw_config,
5376 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5377 * @hw: pointer to the hw struct
5378 * @seid: seid of the VSI
5379 * @bw_data: Buffer to hold VSI BW configuration per TC
5380 * @cmd_details: pointer to command details structure or NULL
5382 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5384 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5385 struct i40e_asq_cmd_details *cmd_details)
5387 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5388 i40e_aqc_opc_query_vsi_ets_sla_config,
5393 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5394 * @hw: pointer to the hw struct
5395 * @seid: seid of the switching component
5396 * @bw_data: Buffer to hold switching component's per TC BW config
5397 * @cmd_details: pointer to command details structure or NULL
5399 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5401 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5402 struct i40e_asq_cmd_details *cmd_details)
5404 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5405 i40e_aqc_opc_query_switching_comp_ets_config,
5410 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5411 * @hw: pointer to the hw struct
5412 * @seid: seid of the VSI or switching component connected to Physical Port
5413 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5414 * @cmd_details: pointer to command details structure or NULL
5416 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5418 struct i40e_aqc_query_port_ets_config_resp *bw_data,
5419 struct i40e_asq_cmd_details *cmd_details)
5421 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5422 i40e_aqc_opc_query_port_ets_config,
5427 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5428 * @hw: pointer to the hw struct
5429 * @seid: seid of the switching component
5430 * @bw_data: Buffer to hold switching component's BW configuration
5431 * @cmd_details: pointer to command details structure or NULL
5433 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5435 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5436 struct i40e_asq_cmd_details *cmd_details)
5438 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5439 i40e_aqc_opc_query_switching_comp_bw_config,
5444 * i40e_validate_filter_settings
5445 * @hw: pointer to the hardware structure
5446 * @settings: Filter control settings
5448 * Check and validate the filter control settings passed.
5449 * The function checks for the valid filter/context sizes being
5450 * passed for FCoE and PE.
5452 * Returns I40E_SUCCESS if the values passed are valid and within
5453 * range else returns an error.
5455 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5456 struct i40e_filter_control_settings *settings)
5458 u32 fcoe_cntx_size, fcoe_filt_size;
5459 u32 pe_cntx_size, pe_filt_size;
5464 /* Validate FCoE settings passed */
5465 switch (settings->fcoe_filt_num) {
5466 case I40E_HASH_FILTER_SIZE_1K:
5467 case I40E_HASH_FILTER_SIZE_2K:
5468 case I40E_HASH_FILTER_SIZE_4K:
5469 case I40E_HASH_FILTER_SIZE_8K:
5470 case I40E_HASH_FILTER_SIZE_16K:
5471 case I40E_HASH_FILTER_SIZE_32K:
5472 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5473 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5476 return I40E_ERR_PARAM;
5479 switch (settings->fcoe_cntx_num) {
5480 case I40E_DMA_CNTX_SIZE_512:
5481 case I40E_DMA_CNTX_SIZE_1K:
5482 case I40E_DMA_CNTX_SIZE_2K:
5483 case I40E_DMA_CNTX_SIZE_4K:
5484 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5485 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5488 return I40E_ERR_PARAM;
5491 /* Validate PE settings passed */
5492 switch (settings->pe_filt_num) {
5493 case I40E_HASH_FILTER_SIZE_1K:
5494 case I40E_HASH_FILTER_SIZE_2K:
5495 case I40E_HASH_FILTER_SIZE_4K:
5496 case I40E_HASH_FILTER_SIZE_8K:
5497 case I40E_HASH_FILTER_SIZE_16K:
5498 case I40E_HASH_FILTER_SIZE_32K:
5499 case I40E_HASH_FILTER_SIZE_64K:
5500 case I40E_HASH_FILTER_SIZE_128K:
5501 case I40E_HASH_FILTER_SIZE_256K:
5502 case I40E_HASH_FILTER_SIZE_512K:
5503 case I40E_HASH_FILTER_SIZE_1M:
5504 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5505 pe_filt_size <<= (u32)settings->pe_filt_num;
5508 return I40E_ERR_PARAM;
5511 switch (settings->pe_cntx_num) {
5512 case I40E_DMA_CNTX_SIZE_512:
5513 case I40E_DMA_CNTX_SIZE_1K:
5514 case I40E_DMA_CNTX_SIZE_2K:
5515 case I40E_DMA_CNTX_SIZE_4K:
5516 case I40E_DMA_CNTX_SIZE_8K:
5517 case I40E_DMA_CNTX_SIZE_16K:
5518 case I40E_DMA_CNTX_SIZE_32K:
5519 case I40E_DMA_CNTX_SIZE_64K:
5520 case I40E_DMA_CNTX_SIZE_128K:
5521 case I40E_DMA_CNTX_SIZE_256K:
5522 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5523 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5526 return I40E_ERR_PARAM;
5529 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5530 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5531 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5532 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5533 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
5534 return I40E_ERR_INVALID_SIZE;
5536 return I40E_SUCCESS;
5540 * i40e_set_filter_control
5541 * @hw: pointer to the hardware structure
5542 * @settings: Filter control settings
5544 * Set the Queue Filters for PE/FCoE and enable filters required
5545 * for a single PF. It is expected that these settings are programmed
5546 * at the driver initialization time.
5548 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5549 struct i40e_filter_control_settings *settings)
5551 enum i40e_status_code ret = I40E_SUCCESS;
5552 u32 hash_lut_size = 0;
5556 return I40E_ERR_PARAM;
5558 /* Validate the input settings */
5559 ret = i40e_validate_filter_settings(hw, settings);
5563 /* Read the PF Queue Filter control register */
5564 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5566 /* Program required PE hash buckets for the PF */
5567 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5568 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5569 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5570 /* Program required PE contexts for the PF */
5571 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5572 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5573 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5575 /* Program required FCoE hash buckets for the PF */
5576 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5577 val |= ((u32)settings->fcoe_filt_num <<
5578 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5579 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5580 /* Program required FCoE DDP contexts for the PF */
5581 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5582 val |= ((u32)settings->fcoe_cntx_num <<
5583 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5584 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5586 /* Program Hash LUT size for the PF */
5587 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5588 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5590 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5591 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5593 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5594 if (settings->enable_fdir)
5595 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5596 if (settings->enable_ethtype)
5597 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5598 if (settings->enable_macvlan)
5599 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5601 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5603 return I40E_SUCCESS;
5607 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5608 * @hw: pointer to the hw struct
5609 * @mac_addr: MAC address to use in the filter
5610 * @ethtype: Ethertype to use in the filter
5611 * @flags: Flags that needs to be applied to the filter
5612 * @vsi_seid: seid of the control VSI
5613 * @queue: VSI queue number to send the packet to
5614 * @is_add: Add control packet filter if True else remove
5615 * @stats: Structure to hold information on control filter counts
5616 * @cmd_details: pointer to command details structure or NULL
5618 * This command will Add or Remove control packet filter for a control VSI.
5619 * In return it will update the total number of perfect filter count in
5622 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5623 u8 *mac_addr, u16 ethtype, u16 flags,
5624 u16 vsi_seid, u16 queue, bool is_add,
5625 struct i40e_control_filter_stats *stats,
5626 struct i40e_asq_cmd_details *cmd_details)
5628 struct i40e_aq_desc desc;
5629 struct i40e_aqc_add_remove_control_packet_filter *cmd =
5630 (struct i40e_aqc_add_remove_control_packet_filter *)
5632 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5633 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5635 enum i40e_status_code status;
5638 return I40E_ERR_PARAM;
5641 i40e_fill_default_direct_cmd_desc(&desc,
5642 i40e_aqc_opc_add_control_packet_filter);
5643 cmd->queue = CPU_TO_LE16(queue);
5645 i40e_fill_default_direct_cmd_desc(&desc,
5646 i40e_aqc_opc_remove_control_packet_filter);
5650 i40e_memcpy(cmd->mac, mac_addr, ETH_ALEN,
5651 I40E_NONDMA_TO_NONDMA);
5653 cmd->etype = CPU_TO_LE16(ethtype);
5654 cmd->flags = CPU_TO_LE16(flags);
5655 cmd->seid = CPU_TO_LE16(vsi_seid);
5657 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5659 if (!status && stats) {
5660 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5661 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5662 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5663 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5670 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5671 * @hw: pointer to the hw struct
5672 * @seid: VSI seid to add ethertype filter from
5674 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5677 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5678 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5679 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5680 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5681 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5682 enum i40e_status_code status;
5684 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5685 seid, 0, true, NULL,
5688 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5692 * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5693 * @filters: list of cloud filters
5694 * @filter_count: length of list
5696 * There's an issue in the device where the Geneve VNI layout needs
5697 * to be shifted 1 byte over from the VxLAN VNI
5699 STATIC void i40e_fix_up_geneve_vni(
5700 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5703 struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters;
5706 for (i = 0; i < filter_count; i++) {
5710 tnl_type = (LE16_TO_CPU(f[i].flags) &
5711 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5712 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5713 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5714 ti = LE32_TO_CPU(f[i].tenant_id);
5715 f[i].tenant_id = CPU_TO_LE32(ti << 8);
5721 * i40e_aq_add_cloud_filters
5722 * @hw: pointer to the hardware structure
5723 * @seid: VSI seid to add cloud filters from
5724 * @filters: Buffer which contains the filters to be added
5725 * @filter_count: number of filters contained in the buffer
5727 * Set the cloud filters for a given VSI. The contents of the
5728 * i40e_aqc_add_remove_cloud_filters_element_data are filled
5729 * in by the caller of the function.
5732 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5734 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5737 struct i40e_aq_desc desc;
5738 struct i40e_aqc_add_remove_cloud_filters *cmd =
5739 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5740 enum i40e_status_code status;
5743 i40e_fill_default_direct_cmd_desc(&desc,
5744 i40e_aqc_opc_add_cloud_filters);
5746 buff_len = filter_count * sizeof(*filters);
5747 desc.datalen = CPU_TO_LE16(buff_len);
5748 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5749 cmd->num_filters = filter_count;
5750 cmd->seid = CPU_TO_LE16(seid);
5752 i40e_fix_up_geneve_vni(filters, filter_count);
5754 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5760 * i40e_aq_add_cloud_filters_big_buffer
5761 * @hw: pointer to the hardware structure
5762 * @seid: VSI seid to add cloud filters from
5763 * @filters: Buffer which contains the filters in big buffer to be added
5764 * @filter_count: number of filters contained in the buffer
5766 * Set the cloud filters for a given VSI. The contents of the
5767 * i40e_aqc_add_rm_cloud_filt_elem_ext are filled in by the caller of
5771 enum i40e_status_code i40e_aq_add_cloud_filters_big_buffer(struct i40e_hw *hw,
5773 struct i40e_aqc_add_rm_cloud_filt_elem_ext *filters,
5776 struct i40e_aq_desc desc;
5777 struct i40e_aqc_add_remove_cloud_filters *cmd =
5778 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5779 enum i40e_status_code status;
5783 i40e_fill_default_direct_cmd_desc(&desc,
5784 i40e_aqc_opc_add_cloud_filters);
5786 buff_len = filter_count * sizeof(*filters);
5787 desc.datalen = CPU_TO_LE16(buff_len);
5788 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5789 cmd->num_filters = filter_count;
5790 cmd->seid = CPU_TO_LE16(seid);
5791 cmd->big_buffer_flag = I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER;
5793 /* adjust Geneve VNI for HW issue */
5794 for (i = 0; i < filter_count; i++) {
5798 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5799 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5800 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5801 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5802 ti = LE32_TO_CPU(filters[i].element.tenant_id);
5803 filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5807 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5813 * i40e_aq_remove_cloud_filters
5814 * @hw: pointer to the hardware structure
5815 * @seid: VSI seid to remove cloud filters from
5816 * @filters: Buffer which contains the filters to be removed
5817 * @filter_count: number of filters contained in the buffer
5819 * Remove the cloud filters for a given VSI. The contents of the
5820 * i40e_aqc_add_remove_cloud_filters_element_data are filled
5821 * in by the caller of the function.
5824 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5826 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5829 struct i40e_aq_desc desc;
5830 struct i40e_aqc_add_remove_cloud_filters *cmd =
5831 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5832 enum i40e_status_code status;
5835 i40e_fill_default_direct_cmd_desc(&desc,
5836 i40e_aqc_opc_remove_cloud_filters);
5838 buff_len = filter_count * sizeof(*filters);
5839 desc.datalen = CPU_TO_LE16(buff_len);
5840 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5841 cmd->num_filters = filter_count;
5842 cmd->seid = CPU_TO_LE16(seid);
5844 i40e_fix_up_geneve_vni(filters, filter_count);
5846 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5852 * i40e_aq_remove_cloud_filters_big_buffer
5853 * @hw: pointer to the hardware structure
5854 * @seid: VSI seid to remove cloud filters from
5855 * @filters: Buffer which contains the filters in big buffer to be removed
5856 * @filter_count: number of filters contained in the buffer
5858 * Remove the cloud filters for a given VSI. The contents of the
5859 * i40e_aqc_add_rm_cloud_filt_elem_ext are filled in by the caller of
5863 enum i40e_status_code i40e_aq_remove_cloud_filters_big_buffer(
5866 struct i40e_aqc_add_rm_cloud_filt_elem_ext *filters,
5869 struct i40e_aq_desc desc;
5870 struct i40e_aqc_add_remove_cloud_filters *cmd =
5871 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5872 enum i40e_status_code status;
5876 i40e_fill_default_direct_cmd_desc(&desc,
5877 i40e_aqc_opc_remove_cloud_filters);
5879 buff_len = filter_count * sizeof(*filters);
5880 desc.datalen = CPU_TO_LE16(buff_len);
5881 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5882 cmd->num_filters = filter_count;
5883 cmd->seid = CPU_TO_LE16(seid);
5884 cmd->big_buffer_flag = I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER;
5886 /* adjust Geneve VNI for HW issue */
5887 for (i = 0; i < filter_count; i++) {
5891 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5892 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5893 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5894 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5895 ti = LE32_TO_CPU(filters[i].element.tenant_id);
5896 filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5900 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5906 * i40e_aq_replace_cloud_filters - Replace cloud filter command
5907 * @hw: pointer to the hw struct
5908 * @filters: pointer to the i40e_aqc_replace_cloud_filter_cmd struct
5909 * @cmd_buf: pointer to the i40e_aqc_replace_cloud_filter_cmd_buf struct
5913 i40e_status_code i40e_aq_replace_cloud_filters(struct i40e_hw *hw,
5914 struct i40e_aqc_replace_cloud_filters_cmd *filters,
5915 struct i40e_aqc_replace_cloud_filters_cmd_buf *cmd_buf)
5917 struct i40e_aq_desc desc;
5918 struct i40e_aqc_replace_cloud_filters_cmd *cmd =
5919 (struct i40e_aqc_replace_cloud_filters_cmd *)&desc.params.raw;
5920 enum i40e_status_code status = I40E_SUCCESS;
5923 i40e_fill_default_direct_cmd_desc(&desc,
5924 i40e_aqc_opc_replace_cloud_filters);
5926 desc.datalen = CPU_TO_LE16(32);
5927 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5928 cmd->old_filter_type = filters->old_filter_type;
5929 cmd->new_filter_type = filters->new_filter_type;
5930 cmd->valid_flags = filters->valid_flags;
5931 cmd->tr_bit = filters->tr_bit;
5933 status = i40e_asq_send_command(hw, &desc, cmd_buf,
5934 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf), NULL);
5936 /* for get cloud filters command */
5937 for (i = 0; i < 32; i += 4) {
5938 cmd_buf->filters[i / 4].filter_type = cmd_buf->data[i];
5939 cmd_buf->filters[i / 4].input[0] = cmd_buf->data[i + 1];
5940 cmd_buf->filters[i / 4].input[1] = cmd_buf->data[i + 2];
5941 cmd_buf->filters[i / 4].input[2] = cmd_buf->data[i + 3];
5949 * i40e_aq_alternate_write
5950 * @hw: pointer to the hardware structure
5951 * @reg_addr0: address of first dword to be read
5952 * @reg_val0: value to be written under 'reg_addr0'
5953 * @reg_addr1: address of second dword to be read
5954 * @reg_val1: value to be written under 'reg_addr1'
5956 * Write one or two dwords to alternate structure. Fields are indicated
5957 * by 'reg_addr0' and 'reg_addr1' register numbers.
5960 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5961 u32 reg_addr0, u32 reg_val0,
5962 u32 reg_addr1, u32 reg_val1)
5964 struct i40e_aq_desc desc;
5965 struct i40e_aqc_alternate_write *cmd_resp =
5966 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5967 enum i40e_status_code status;
5969 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5970 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5971 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5972 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5973 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5975 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5981 * i40e_aq_alternate_write_indirect
5982 * @hw: pointer to the hardware structure
5983 * @addr: address of a first register to be modified
5984 * @dw_count: number of alternate structure fields to write
5985 * @buffer: pointer to the command buffer
5987 * Write 'dw_count' dwords from 'buffer' to alternate structure
5988 * starting at 'addr'.
5991 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5992 u32 addr, u32 dw_count, void *buffer)
5994 struct i40e_aq_desc desc;
5995 struct i40e_aqc_alternate_ind_write *cmd_resp =
5996 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5997 enum i40e_status_code status;
6000 return I40E_ERR_PARAM;
6002 /* Indirect command */
6003 i40e_fill_default_direct_cmd_desc(&desc,
6004 i40e_aqc_opc_alternate_write_indirect);
6006 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6007 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6008 if (dw_count > (I40E_AQ_LARGE_BUF/4))
6009 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6011 cmd_resp->address = CPU_TO_LE32(addr);
6012 cmd_resp->length = CPU_TO_LE32(dw_count);
6014 status = i40e_asq_send_command(hw, &desc, buffer,
6015 I40E_LO_DWORD(4*dw_count), NULL);
6021 * i40e_aq_alternate_read
6022 * @hw: pointer to the hardware structure
6023 * @reg_addr0: address of first dword to be read
6024 * @reg_val0: pointer for data read from 'reg_addr0'
6025 * @reg_addr1: address of second dword to be read
6026 * @reg_val1: pointer for data read from 'reg_addr1'
6028 * Read one or two dwords from alternate structure. Fields are indicated
6029 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
6030 * is not passed then only register at 'reg_addr0' is read.
6033 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
6034 u32 reg_addr0, u32 *reg_val0,
6035 u32 reg_addr1, u32 *reg_val1)
6037 struct i40e_aq_desc desc;
6038 struct i40e_aqc_alternate_write *cmd_resp =
6039 (struct i40e_aqc_alternate_write *)&desc.params.raw;
6040 enum i40e_status_code status;
6042 if (reg_val0 == NULL)
6043 return I40E_ERR_PARAM;
6045 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
6046 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
6047 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
6049 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6051 if (status == I40E_SUCCESS) {
6052 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
6054 if (reg_val1 != NULL)
6055 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
6062 * i40e_aq_alternate_read_indirect
6063 * @hw: pointer to the hardware structure
6064 * @addr: address of the alternate structure field
6065 * @dw_count: number of alternate structure fields to read
6066 * @buffer: pointer to the command buffer
6068 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
6069 * place them in 'buffer'. The buffer should be allocated by caller.
6072 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
6073 u32 addr, u32 dw_count, void *buffer)
6075 struct i40e_aq_desc desc;
6076 struct i40e_aqc_alternate_ind_write *cmd_resp =
6077 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
6078 enum i40e_status_code status;
6081 return I40E_ERR_PARAM;
6083 /* Indirect command */
6084 i40e_fill_default_direct_cmd_desc(&desc,
6085 i40e_aqc_opc_alternate_read_indirect);
6087 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6088 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6089 if (dw_count > (I40E_AQ_LARGE_BUF/4))
6090 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6092 cmd_resp->address = CPU_TO_LE32(addr);
6093 cmd_resp->length = CPU_TO_LE32(dw_count);
6095 status = i40e_asq_send_command(hw, &desc, buffer,
6096 I40E_LO_DWORD(4*dw_count), NULL);
6102 * i40e_aq_alternate_clear
6103 * @hw: pointer to the HW structure.
6105 * Clear the alternate structures of the port from which the function
6109 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
6111 struct i40e_aq_desc desc;
6112 enum i40e_status_code status;
6114 i40e_fill_default_direct_cmd_desc(&desc,
6115 i40e_aqc_opc_alternate_clear_port);
6117 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6123 * i40e_aq_alternate_write_done
6124 * @hw: pointer to the HW structure.
6125 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
6126 * @reset_needed: indicates the SW should trigger GLOBAL reset
6128 * Indicates to the FW that alternate structures have been changed.
6131 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
6132 u8 bios_mode, bool *reset_needed)
6134 struct i40e_aq_desc desc;
6135 struct i40e_aqc_alternate_write_done *cmd =
6136 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6137 enum i40e_status_code status;
6139 if (reset_needed == NULL)
6140 return I40E_ERR_PARAM;
6142 i40e_fill_default_direct_cmd_desc(&desc,
6143 i40e_aqc_opc_alternate_write_done);
6145 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
6147 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6148 if (!status && reset_needed)
6149 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
6150 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
6156 * i40e_aq_set_oem_mode
6157 * @hw: pointer to the HW structure.
6158 * @oem_mode: the OEM mode to be used
6160 * Sets the device to a specific operating mode. Currently the only supported
6161 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
6164 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
6167 struct i40e_aq_desc desc;
6168 struct i40e_aqc_alternate_write_done *cmd =
6169 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6170 enum i40e_status_code status;
6172 i40e_fill_default_direct_cmd_desc(&desc,
6173 i40e_aqc_opc_alternate_set_mode);
6175 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
6177 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6183 * i40e_aq_resume_port_tx
6184 * @hw: pointer to the hardware structure
6185 * @cmd_details: pointer to command details structure or NULL
6187 * Resume port's Tx traffic
6189 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
6190 struct i40e_asq_cmd_details *cmd_details)
6192 struct i40e_aq_desc desc;
6193 enum i40e_status_code status;
6195 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
6197 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6203 * i40e_set_pci_config_data - store PCI bus info
6204 * @hw: pointer to hardware structure
6205 * @link_status: the link status word from PCI config space
6207 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
6209 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
6211 hw->bus.type = i40e_bus_type_pci_express;
6213 switch (link_status & I40E_PCI_LINK_WIDTH) {
6214 case I40E_PCI_LINK_WIDTH_1:
6215 hw->bus.width = i40e_bus_width_pcie_x1;
6217 case I40E_PCI_LINK_WIDTH_2:
6218 hw->bus.width = i40e_bus_width_pcie_x2;
6220 case I40E_PCI_LINK_WIDTH_4:
6221 hw->bus.width = i40e_bus_width_pcie_x4;
6223 case I40E_PCI_LINK_WIDTH_8:
6224 hw->bus.width = i40e_bus_width_pcie_x8;
6227 hw->bus.width = i40e_bus_width_unknown;
6231 switch (link_status & I40E_PCI_LINK_SPEED) {
6232 case I40E_PCI_LINK_SPEED_2500:
6233 hw->bus.speed = i40e_bus_speed_2500;
6235 case I40E_PCI_LINK_SPEED_5000:
6236 hw->bus.speed = i40e_bus_speed_5000;
6238 case I40E_PCI_LINK_SPEED_8000:
6239 hw->bus.speed = i40e_bus_speed_8000;
6242 hw->bus.speed = i40e_bus_speed_unknown;
6248 * i40e_aq_debug_dump
6249 * @hw: pointer to the hardware structure
6250 * @cluster_id: specific cluster to dump
6251 * @table_id: table id within cluster
6252 * @start_index: index of line in the block to read
6253 * @buff_size: dump buffer size
6254 * @buff: dump buffer
6255 * @ret_buff_size: actual buffer size returned
6256 * @ret_next_table: next block to read
6257 * @ret_next_index: next index to read
6258 * @cmd_details: pointer to command details structure or NULL
6260 * Dump internal FW/HW data for debug purposes.
6263 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
6264 u8 table_id, u32 start_index, u16 buff_size,
6265 void *buff, u16 *ret_buff_size,
6266 u8 *ret_next_table, u32 *ret_next_index,
6267 struct i40e_asq_cmd_details *cmd_details)
6269 struct i40e_aq_desc desc;
6270 struct i40e_aqc_debug_dump_internals *cmd =
6271 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6272 struct i40e_aqc_debug_dump_internals *resp =
6273 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6274 enum i40e_status_code status;
6276 if (buff_size == 0 || !buff)
6277 return I40E_ERR_PARAM;
6279 i40e_fill_default_direct_cmd_desc(&desc,
6280 i40e_aqc_opc_debug_dump_internals);
6281 /* Indirect Command */
6282 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6283 if (buff_size > I40E_AQ_LARGE_BUF)
6284 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6286 cmd->cluster_id = cluster_id;
6287 cmd->table_id = table_id;
6288 cmd->idx = CPU_TO_LE32(start_index);
6290 desc.datalen = CPU_TO_LE16(buff_size);
6292 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
6294 if (ret_buff_size != NULL)
6295 *ret_buff_size = LE16_TO_CPU(desc.datalen);
6296 if (ret_next_table != NULL)
6297 *ret_next_table = resp->table_id;
6298 if (ret_next_index != NULL)
6299 *ret_next_index = LE32_TO_CPU(resp->idx);
6306 * i40e_read_bw_from_alt_ram
6307 * @hw: pointer to the hardware structure
6308 * @max_bw: pointer for max_bw read
6309 * @min_bw: pointer for min_bw read
6310 * @min_valid: pointer for bool that is true if min_bw is a valid value
6311 * @max_valid: pointer for bool that is true if max_bw is a valid value
6313 * Read bw from the alternate ram for the given pf
6315 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
6316 u32 *max_bw, u32 *min_bw,
6317 bool *min_valid, bool *max_valid)
6319 enum i40e_status_code status;
6320 u32 max_bw_addr, min_bw_addr;
6322 /* Calculate the address of the min/max bw registers */
6323 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6324 I40E_ALT_STRUCT_MAX_BW_OFFSET +
6325 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6326 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6327 I40E_ALT_STRUCT_MIN_BW_OFFSET +
6328 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6330 /* Read the bandwidths from alt ram */
6331 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
6332 min_bw_addr, min_bw);
6334 if (*min_bw & I40E_ALT_BW_VALID_MASK)
6339 if (*max_bw & I40E_ALT_BW_VALID_MASK)
6348 * i40e_aq_configure_partition_bw
6349 * @hw: pointer to the hardware structure
6350 * @bw_data: Buffer holding valid pfs and bw limits
6351 * @cmd_details: pointer to command details
6353 * Configure partitions guaranteed/max bw
6355 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6356 struct i40e_aqc_configure_partition_bw_data *bw_data,
6357 struct i40e_asq_cmd_details *cmd_details)
6359 enum i40e_status_code status;
6360 struct i40e_aq_desc desc;
6361 u16 bwd_size = sizeof(*bw_data);
6363 i40e_fill_default_direct_cmd_desc(&desc,
6364 i40e_aqc_opc_configure_partition_bw);
6366 /* Indirect command */
6367 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6368 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6370 desc.datalen = CPU_TO_LE16(bwd_size);
6372 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6378 * i40e_read_phy_register_clause22
6379 * @hw: pointer to the HW structure
6380 * @reg: register address in the page
6381 * @phy_addr: PHY address on MDIO interface
6382 * @value: PHY register value
6384 * Reads specified PHY register value
6386 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
6387 u16 reg, u8 phy_addr, u16 *value)
6389 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6390 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6394 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6395 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6396 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
6397 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6398 (I40E_GLGEN_MSCA_MDICMD_MASK);
6399 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6401 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6402 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6403 status = I40E_SUCCESS;
6406 i40e_usec_delay(10);
6411 i40e_debug(hw, I40E_DEBUG_PHY,
6412 "PHY: Can't write command to external PHY.\n");
6414 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6415 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6416 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6423 * i40e_write_phy_register_clause22
6424 * @hw: pointer to the HW structure
6425 * @reg: register address in the page
6426 * @phy_addr: PHY address on MDIO interface
6427 * @value: PHY register value
6429 * Writes specified PHY register value
6431 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6432 u16 reg, u8 phy_addr, u16 value)
6434 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6435 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6439 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6440 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6442 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6443 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6444 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6445 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6446 (I40E_GLGEN_MSCA_MDICMD_MASK);
6448 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6450 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6451 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6452 status = I40E_SUCCESS;
6455 i40e_usec_delay(10);
6463 * i40e_read_phy_register_clause45
6464 * @hw: pointer to the HW structure
6465 * @page: registers page number
6466 * @reg: register address in the page
6467 * @phy_addr: PHY address on MDIO interface
6468 * @value: PHY register value
6470 * Reads specified PHY register value
6472 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6473 u8 page, u16 reg, u8 phy_addr, u16 *value)
6475 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6478 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6480 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6481 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6482 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6483 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6484 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6485 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6486 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6487 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6489 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6490 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6491 status = I40E_SUCCESS;
6494 i40e_usec_delay(10);
6499 i40e_debug(hw, I40E_DEBUG_PHY,
6500 "PHY: Can't write command to external PHY.\n");
6504 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6505 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6506 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6507 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6508 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6509 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6510 status = I40E_ERR_TIMEOUT;
6512 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6514 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6515 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6516 status = I40E_SUCCESS;
6519 i40e_usec_delay(10);
6524 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6525 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6526 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6528 i40e_debug(hw, I40E_DEBUG_PHY,
6529 "PHY: Can't read register value from external PHY.\n");
6537 * i40e_write_phy_register_clause45
6538 * @hw: pointer to the HW structure
6539 * @page: registers page number
6540 * @reg: register address in the page
6541 * @phy_addr: PHY address on MDIO interface
6542 * @value: PHY register value
6544 * Writes value to specified PHY register
6546 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6547 u8 page, u16 reg, u8 phy_addr, u16 value)
6549 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6552 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6554 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6555 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6556 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6557 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6558 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6559 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6560 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6561 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6563 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6564 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6565 status = I40E_SUCCESS;
6568 i40e_usec_delay(10);
6572 i40e_debug(hw, I40E_DEBUG_PHY,
6573 "PHY: Can't write command to external PHY.\n");
6577 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6578 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6580 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6581 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6582 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6583 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6584 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6585 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6586 status = I40E_ERR_TIMEOUT;
6588 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6590 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6591 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6592 status = I40E_SUCCESS;
6595 i40e_usec_delay(10);
6604 * i40e_write_phy_register
6605 * @hw: pointer to the HW structure
6606 * @page: registers page number
6607 * @reg: register address in the page
6608 * @phy_addr: PHY address on MDIO interface
6609 * @value: PHY register value
6611 * Writes value to specified PHY register
6613 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6614 u8 page, u16 reg, u8 phy_addr, u16 value)
6616 enum i40e_status_code status;
6618 switch (hw->device_id) {
6619 case I40E_DEV_ID_1G_BASE_T_X722:
6620 status = i40e_write_phy_register_clause22(hw,
6621 reg, phy_addr, value);
6623 case I40E_DEV_ID_10G_BASE_T:
6624 case I40E_DEV_ID_10G_BASE_T4:
6625 case I40E_DEV_ID_10G_BASE_T_X722:
6626 case I40E_DEV_ID_25G_B:
6627 case I40E_DEV_ID_25G_SFP28:
6628 status = i40e_write_phy_register_clause45(hw,
6629 page, reg, phy_addr, value);
6632 status = I40E_ERR_UNKNOWN_PHY;
6640 * i40e_read_phy_register
6641 * @hw: pointer to the HW structure
6642 * @page: registers page number
6643 * @reg: register address in the page
6644 * @phy_addr: PHY address on MDIO interface
6645 * @value: PHY register value
6647 * Reads specified PHY register value
6649 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6650 u8 page, u16 reg, u8 phy_addr, u16 *value)
6652 enum i40e_status_code status;
6654 switch (hw->device_id) {
6655 case I40E_DEV_ID_1G_BASE_T_X722:
6656 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6659 case I40E_DEV_ID_10G_BASE_T:
6660 case I40E_DEV_ID_10G_BASE_T4:
6661 case I40E_DEV_ID_10G_BASE_T_X722:
6662 case I40E_DEV_ID_25G_B:
6663 case I40E_DEV_ID_25G_SFP28:
6664 status = i40e_read_phy_register_clause45(hw, page, reg,
6668 status = I40E_ERR_UNKNOWN_PHY;
6676 * i40e_get_phy_address
6677 * @hw: pointer to the HW structure
6678 * @dev_num: PHY port num that address we want
6680 * Gets PHY address for current port
6682 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6684 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6685 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6687 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6691 * i40e_blink_phy_led
6692 * @hw: pointer to the HW structure
6693 * @time: time how long led will blinks in secs
6694 * @interval: gap between LED on and off in msecs
6696 * Blinks PHY link LED
6698 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6699 u32 time, u32 interval)
6701 enum i40e_status_code status = I40E_SUCCESS;
6706 u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6710 i = rd32(hw, I40E_PFGEN_PORTNUM);
6711 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6712 phy_addr = i40e_get_phy_address(hw, port_num);
6714 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6716 status = i40e_read_phy_register_clause45(hw,
6717 I40E_PHY_COM_REG_PAGE,
6721 goto phy_blinking_end;
6723 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6725 status = i40e_write_phy_register_clause45(hw,
6726 I40E_PHY_COM_REG_PAGE,
6730 goto phy_blinking_end;
6735 if (time > 0 && interval > 0) {
6736 for (i = 0; i < time * 1000; i += interval) {
6737 status = i40e_read_phy_register_clause45(hw,
6738 I40E_PHY_COM_REG_PAGE,
6739 led_addr, phy_addr, &led_reg);
6741 goto restore_config;
6742 if (led_reg & I40E_PHY_LED_MANUAL_ON)
6745 led_reg = I40E_PHY_LED_MANUAL_ON;
6746 status = i40e_write_phy_register_clause45(hw,
6747 I40E_PHY_COM_REG_PAGE,
6748 led_addr, phy_addr, led_reg);
6750 goto restore_config;
6751 i40e_msec_delay(interval);
6756 status = i40e_write_phy_register_clause45(hw,
6757 I40E_PHY_COM_REG_PAGE,
6758 led_addr, phy_addr, led_ctl);
6765 * i40e_led_get_reg - read LED register
6766 * @hw: pointer to the HW structure
6767 * @led_addr: LED register address
6768 * @reg_val: read register value
6770 static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr,
6773 enum i40e_status_code status;
6777 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6778 status = i40e_aq_get_phy_register(hw,
6779 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6780 I40E_PHY_COM_REG_PAGE,
6781 I40E_PHY_LED_PROV_REG_1,
6784 phy_addr = i40e_get_phy_address(hw, hw->port);
6785 status = i40e_read_phy_register_clause45(hw,
6786 I40E_PHY_COM_REG_PAGE,
6794 * i40e_led_set_reg - write LED register
6795 * @hw: pointer to the HW structure
6796 * @led_addr: LED register address
6797 * @reg_val: register value to write
6799 static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr,
6802 enum i40e_status_code status;
6805 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6806 status = i40e_aq_set_phy_register(hw,
6807 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6808 I40E_PHY_COM_REG_PAGE,
6809 I40E_PHY_LED_PROV_REG_1,
6812 phy_addr = i40e_get_phy_address(hw, hw->port);
6813 status = i40e_write_phy_register_clause45(hw,
6814 I40E_PHY_COM_REG_PAGE,
6823 * i40e_led_get_phy - return current on/off mode
6824 * @hw: pointer to the hw struct
6825 * @led_addr: address of led register to use
6826 * @val: original value of register to use
6829 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6832 enum i40e_status_code status = I40E_SUCCESS;
6839 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6840 status = i40e_aq_get_phy_register(hw,
6841 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6842 I40E_PHY_COM_REG_PAGE,
6843 I40E_PHY_LED_PROV_REG_1,
6845 if (status == I40E_SUCCESS)
6846 *val = (u16)reg_val_aq;
6849 temp_addr = I40E_PHY_LED_PROV_REG_1;
6850 phy_addr = i40e_get_phy_address(hw, hw->port);
6851 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6853 status = i40e_read_phy_register_clause45(hw,
6854 I40E_PHY_COM_REG_PAGE,
6855 temp_addr, phy_addr,
6860 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6861 *led_addr = temp_addr;
6870 * @hw: pointer to the HW structure
6871 * @on: true or false
6872 * @led_addr: address of led register to use
6873 * @mode: original val plus bit for set or ignore
6875 * Set led's on or off when controlled by the PHY
6878 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6879 u16 led_addr, u32 mode)
6881 enum i40e_status_code status = I40E_SUCCESS;
6885 status = i40e_led_get_reg(hw, led_addr, &led_reg);
6889 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6891 status = i40e_led_set_reg(hw, led_addr, led_reg);
6895 status = i40e_led_get_reg(hw, led_addr, &led_reg);
6897 goto restore_config;
6899 led_reg = I40E_PHY_LED_MANUAL_ON;
6902 status = i40e_led_set_reg(hw, led_addr, led_reg);
6904 goto restore_config;
6905 if (mode & I40E_PHY_LED_MODE_ORIG) {
6906 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6907 status = i40e_led_set_reg(hw, led_addr, led_ctl);
6912 status = i40e_led_set_reg(hw, led_addr, led_ctl);
6915 #endif /* PF_DRIVER */
6918 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6919 * @hw: pointer to the hw struct
6920 * @reg_addr: register address
6921 * @reg_val: ptr to register value
6922 * @cmd_details: pointer to command details structure or NULL
6924 * Use the firmware to read the Rx control register,
6925 * especially useful if the Rx unit is under heavy pressure
6927 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6928 u32 reg_addr, u32 *reg_val,
6929 struct i40e_asq_cmd_details *cmd_details)
6931 struct i40e_aq_desc desc;
6932 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
6933 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6934 enum i40e_status_code status;
6936 if (reg_val == NULL)
6937 return I40E_ERR_PARAM;
6939 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
6941 cmd_resp->address = CPU_TO_LE32(reg_addr);
6943 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6945 if (status == I40E_SUCCESS)
6946 *reg_val = LE32_TO_CPU(cmd_resp->value);
6952 * i40e_read_rx_ctl - read from an Rx control register
6953 * @hw: pointer to the hw struct
6954 * @reg_addr: register address
6956 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
6958 enum i40e_status_code status = I40E_SUCCESS;
6963 use_register = (((hw->aq.api_maj_ver == 1) &&
6964 (hw->aq.api_min_ver < 5)) ||
6965 (hw->mac.type == I40E_MAC_X722));
6966 if (!use_register) {
6968 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
6969 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6976 /* if the AQ access failed, try the old-fashioned way */
6977 if (status || use_register)
6978 val = rd32(hw, reg_addr);
6984 * i40e_aq_rx_ctl_write_register
6985 * @hw: pointer to the hw struct
6986 * @reg_addr: register address
6987 * @reg_val: register value
6988 * @cmd_details: pointer to command details structure or NULL
6990 * Use the firmware to write to an Rx control register,
6991 * especially useful if the Rx unit is under heavy pressure
6993 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
6994 u32 reg_addr, u32 reg_val,
6995 struct i40e_asq_cmd_details *cmd_details)
6997 struct i40e_aq_desc desc;
6998 struct i40e_aqc_rx_ctl_reg_read_write *cmd =
6999 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
7000 enum i40e_status_code status;
7002 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
7004 cmd->address = CPU_TO_LE32(reg_addr);
7005 cmd->value = CPU_TO_LE32(reg_val);
7007 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7013 * i40e_write_rx_ctl - write to an Rx control register
7014 * @hw: pointer to the hw struct
7015 * @reg_addr: register address
7016 * @reg_val: register value
7018 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
7020 enum i40e_status_code status = I40E_SUCCESS;
7024 use_register = (((hw->aq.api_maj_ver == 1) &&
7025 (hw->aq.api_min_ver < 5)) ||
7026 (hw->mac.type == I40E_MAC_X722));
7027 if (!use_register) {
7029 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
7031 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
7038 /* if the AQ access failed, try the old-fashioned way */
7039 if (status || use_register)
7040 wr32(hw, reg_addr, reg_val);
7044 * i40e_aq_set_phy_register
7045 * @hw: pointer to the hw struct
7046 * @phy_select: select which phy should be accessed
7047 * @dev_addr: PHY device address
7048 * @reg_addr: PHY register address
7049 * @reg_val: new register value
7050 * @cmd_details: pointer to command details structure or NULL
7052 * Write the external PHY register.
7054 enum i40e_status_code i40e_aq_set_phy_register(struct i40e_hw *hw,
7055 u8 phy_select, u8 dev_addr,
7056 u32 reg_addr, u32 reg_val,
7057 struct i40e_asq_cmd_details *cmd_details)
7059 struct i40e_aq_desc desc;
7060 struct i40e_aqc_phy_register_access *cmd =
7061 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7062 enum i40e_status_code status;
7064 i40e_fill_default_direct_cmd_desc(&desc,
7065 i40e_aqc_opc_set_phy_register);
7067 cmd->phy_interface = phy_select;
7068 cmd->dev_addres = dev_addr;
7069 cmd->reg_address = CPU_TO_LE32(reg_addr);
7070 cmd->reg_value = CPU_TO_LE32(reg_val);
7072 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7078 * i40e_aq_get_phy_register
7079 * @hw: pointer to the hw struct
7080 * @phy_select: select which phy should be accessed
7081 * @dev_addr: PHY device address
7082 * @reg_addr: PHY register address
7083 * @reg_val: read register value
7084 * @cmd_details: pointer to command details structure or NULL
7086 * Read the external PHY register.
7088 enum i40e_status_code i40e_aq_get_phy_register(struct i40e_hw *hw,
7089 u8 phy_select, u8 dev_addr,
7090 u32 reg_addr, u32 *reg_val,
7091 struct i40e_asq_cmd_details *cmd_details)
7093 struct i40e_aq_desc desc;
7094 struct i40e_aqc_phy_register_access *cmd =
7095 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7096 enum i40e_status_code status;
7098 i40e_fill_default_direct_cmd_desc(&desc,
7099 i40e_aqc_opc_get_phy_register);
7101 cmd->phy_interface = phy_select;
7102 cmd->dev_addres = dev_addr;
7103 cmd->reg_address = CPU_TO_LE32(reg_addr);
7105 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7107 *reg_val = LE32_TO_CPU(cmd->reg_value);
7115 * i40e_aq_send_msg_to_pf
7116 * @hw: pointer to the hardware structure
7117 * @v_opcode: opcodes for VF-PF communication
7118 * @v_retval: return error code
7119 * @msg: pointer to the msg buffer
7120 * @msglen: msg length
7121 * @cmd_details: pointer to command details
7123 * Send message to PF driver using admin queue. By default, this message
7124 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
7125 * completion before returning.
7127 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
7128 enum virtchnl_ops v_opcode,
7129 enum i40e_status_code v_retval,
7130 u8 *msg, u16 msglen,
7131 struct i40e_asq_cmd_details *cmd_details)
7133 struct i40e_aq_desc desc;
7134 struct i40e_asq_cmd_details details;
7135 enum i40e_status_code status;
7137 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
7138 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
7139 desc.cookie_high = CPU_TO_LE32(v_opcode);
7140 desc.cookie_low = CPU_TO_LE32(v_retval);
7142 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
7143 | I40E_AQ_FLAG_RD));
7144 if (msglen > I40E_AQ_LARGE_BUF)
7145 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7146 desc.datalen = CPU_TO_LE16(msglen);
7149 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
7150 details.async = true;
7151 cmd_details = &details;
7153 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
7154 msglen, cmd_details);
7159 * i40e_vf_parse_hw_config
7160 * @hw: pointer to the hardware structure
7161 * @msg: pointer to the virtual channel VF resource structure
7163 * Given a VF resource message from the PF, populate the hw struct
7164 * with appropriate information.
7166 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
7167 struct virtchnl_vf_resource *msg)
7169 struct virtchnl_vsi_resource *vsi_res;
7172 vsi_res = &msg->vsi_res[0];
7174 hw->dev_caps.num_vsis = msg->num_vsis;
7175 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
7176 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
7177 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
7178 hw->dev_caps.dcb = msg->vf_offload_flags &
7179 VIRTCHNL_VF_OFFLOAD_L2;
7180 hw->dev_caps.iwarp = (msg->vf_offload_flags &
7181 VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
7182 for (i = 0; i < msg->num_vsis; i++) {
7183 if (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) {
7184 i40e_memcpy(hw->mac.perm_addr,
7185 vsi_res->default_mac_addr,
7187 I40E_NONDMA_TO_NONDMA);
7188 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
7190 I40E_NONDMA_TO_NONDMA);
7198 * @hw: pointer to the hardware structure
7200 * Send a VF_RESET message to the PF. Does not wait for response from PF
7201 * as none will be forthcoming. Immediately after calling this function,
7202 * the admin queue should be shut down and (optionally) reinitialized.
7204 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
7206 return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF,
7207 I40E_SUCCESS, NULL, 0, NULL);
7209 #endif /* VF_DRIVER */
7212 * i40e_aq_set_arp_proxy_config
7213 * @hw: pointer to the HW structure
7214 * @proxy_config: pointer to proxy config command table struct
7215 * @cmd_details: pointer to command details
7217 * Set ARP offload parameters from pre-populated
7218 * i40e_aqc_arp_proxy_data struct
7220 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
7221 struct i40e_aqc_arp_proxy_data *proxy_config,
7222 struct i40e_asq_cmd_details *cmd_details)
7224 struct i40e_aq_desc desc;
7225 enum i40e_status_code status;
7228 return I40E_ERR_PARAM;
7230 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
7232 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7233 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7234 desc.params.external.addr_high =
7235 CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
7236 desc.params.external.addr_low =
7237 CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
7238 desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_arp_proxy_data));
7240 status = i40e_asq_send_command(hw, &desc, proxy_config,
7241 sizeof(struct i40e_aqc_arp_proxy_data),
7248 * i40e_aq_opc_set_ns_proxy_table_entry
7249 * @hw: pointer to the HW structure
7250 * @ns_proxy_table_entry: pointer to NS table entry command struct
7251 * @cmd_details: pointer to command details
7253 * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
7254 * from pre-populated i40e_aqc_ns_proxy_data struct
7256 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
7257 struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
7258 struct i40e_asq_cmd_details *cmd_details)
7260 struct i40e_aq_desc desc;
7261 enum i40e_status_code status;
7263 if (!ns_proxy_table_entry)
7264 return I40E_ERR_PARAM;
7266 i40e_fill_default_direct_cmd_desc(&desc,
7267 i40e_aqc_opc_set_ns_proxy_table_entry);
7269 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7270 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7271 desc.params.external.addr_high =
7272 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
7273 desc.params.external.addr_low =
7274 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
7275 desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_ns_proxy_data));
7277 status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
7278 sizeof(struct i40e_aqc_ns_proxy_data),
7285 * i40e_aq_set_clear_wol_filter
7286 * @hw: pointer to the hw struct
7287 * @filter_index: index of filter to modify (0-7)
7288 * @filter: buffer containing filter to be set
7289 * @set_filter: true to set filter, false to clear filter
7290 * @no_wol_tco: if true, pass through packets cannot cause wake-up
7291 * if false, pass through packets may cause wake-up
7292 * @filter_valid: true if filter action is valid
7293 * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
7294 * @cmd_details: pointer to command details structure or NULL
7296 * Set or clear WoL filter for port attached to the PF
7298 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
7300 struct i40e_aqc_set_wol_filter_data *filter,
7301 bool set_filter, bool no_wol_tco,
7302 bool filter_valid, bool no_wol_tco_valid,
7303 struct i40e_asq_cmd_details *cmd_details)
7305 struct i40e_aq_desc desc;
7306 struct i40e_aqc_set_wol_filter *cmd =
7307 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
7308 enum i40e_status_code status;
7310 u16 valid_flags = 0;
7313 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
7315 if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
7316 return I40E_ERR_PARAM;
7317 cmd->filter_index = CPU_TO_LE16(filter_index);
7321 return I40E_ERR_PARAM;
7323 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
7324 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR;
7328 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
7329 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
7332 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
7333 if (no_wol_tco_valid)
7334 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
7335 cmd->valid_flags = CPU_TO_LE16(valid_flags);
7337 buff_len = sizeof(*filter);
7338 desc.datalen = CPU_TO_LE16(buff_len);
7340 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7341 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7343 cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
7344 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
7346 status = i40e_asq_send_command(hw, &desc, filter,
7347 buff_len, cmd_details);
7353 * i40e_aq_get_wake_event_reason
7354 * @hw: pointer to the hw struct
7355 * @wake_reason: return value, index of matching filter
7356 * @cmd_details: pointer to command details structure or NULL
7358 * Get information for the reason of a Wake Up event
7360 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
7362 struct i40e_asq_cmd_details *cmd_details)
7364 struct i40e_aq_desc desc;
7365 struct i40e_aqc_get_wake_reason_completion *resp =
7366 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
7367 enum i40e_status_code status;
7369 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
7371 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7373 if (status == I40E_SUCCESS)
7374 *wake_reason = LE16_TO_CPU(resp->wake_reason);
7380 * i40e_aq_clear_all_wol_filters
7381 * @hw: pointer to the hw struct
7382 * @cmd_details: pointer to command details structure or NULL
7384 * Get information for the reason of a Wake Up event
7386 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw,
7387 struct i40e_asq_cmd_details *cmd_details)
7389 struct i40e_aq_desc desc;
7390 enum i40e_status_code status;
7392 i40e_fill_default_direct_cmd_desc(&desc,
7393 i40e_aqc_opc_clear_all_wol_filters);
7395 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7401 * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
7402 * @hw: pointer to the hw struct
7403 * @buff: command buffer (size in bytes = buff_size)
7404 * @buff_size: buffer size in bytes
7405 * @track_id: package tracking id
7406 * @error_offset: returns error offset
7407 * @error_info: returns error information
7408 * @cmd_details: pointer to command details structure or NULL
7411 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
7412 u16 buff_size, u32 track_id,
7413 u32 *error_offset, u32 *error_info,
7414 struct i40e_asq_cmd_details *cmd_details)
7416 struct i40e_aq_desc desc;
7417 struct i40e_aqc_write_personalization_profile *cmd =
7418 (struct i40e_aqc_write_personalization_profile *)
7420 struct i40e_aqc_write_ddp_resp *resp;
7421 enum i40e_status_code status;
7423 i40e_fill_default_direct_cmd_desc(&desc,
7424 i40e_aqc_opc_write_personalization_profile);
7426 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
7427 if (buff_size > I40E_AQ_LARGE_BUF)
7428 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7430 desc.datalen = CPU_TO_LE16(buff_size);
7432 cmd->profile_track_id = CPU_TO_LE32(track_id);
7434 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7436 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
7438 *error_offset = LE32_TO_CPU(resp->error_offset);
7440 *error_info = LE32_TO_CPU(resp->error_info);
7447 * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
7448 * @hw: pointer to the hw struct
7449 * @buff: command buffer (size in bytes = buff_size)
7450 * @buff_size: buffer size in bytes
7451 * @flags: AdminQ command flags
7452 * @cmd_details: pointer to command details structure or NULL
7455 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
7456 u16 buff_size, u8 flags,
7457 struct i40e_asq_cmd_details *cmd_details)
7459 struct i40e_aq_desc desc;
7460 struct i40e_aqc_get_applied_profiles *cmd =
7461 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
7462 enum i40e_status_code status;
7464 i40e_fill_default_direct_cmd_desc(&desc,
7465 i40e_aqc_opc_get_personalization_profile_list);
7467 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7468 if (buff_size > I40E_AQ_LARGE_BUF)
7469 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7470 desc.datalen = CPU_TO_LE16(buff_size);
7474 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7480 * i40e_find_segment_in_package
7481 * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
7482 * @pkg_hdr: pointer to the package header to be searched
7484 * This function searches a package file for a particular segment type. On
7485 * success it returns a pointer to the segment header, otherwise it will
7488 struct i40e_generic_seg_header *
7489 i40e_find_segment_in_package(u32 segment_type,
7490 struct i40e_package_header *pkg_hdr)
7492 struct i40e_generic_seg_header *segment;
7495 /* Search all package segments for the requested segment type */
7496 for (i = 0; i < pkg_hdr->segment_count; i++) {
7498 (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
7499 pkg_hdr->segment_offset[i]);
7501 if (segment->type == segment_type)
7508 /* Get section table in profile */
7509 #define I40E_SECTION_TABLE(profile, sec_tbl) \
7511 struct i40e_profile_segment *p = (profile); \
7514 count = p->device_table_count; \
7515 nvm = (u32 *)&p->device_table[count]; \
7516 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \
7519 /* Get section header in profile */
7520 #define I40E_SECTION_HEADER(profile, offset) \
7521 (struct i40e_profile_section_header *)((u8 *)(profile) + (offset))
7524 * i40e_find_section_in_profile
7525 * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE)
7526 * @profile: pointer to the i40e segment header to be searched
7528 * This function searches i40e segment for a particular section type. On
7529 * success it returns a pointer to the section header, otherwise it will
7532 struct i40e_profile_section_header *
7533 i40e_find_section_in_profile(u32 section_type,
7534 struct i40e_profile_segment *profile)
7536 struct i40e_profile_section_header *sec;
7537 struct i40e_section_table *sec_tbl;
7541 if (profile->header.type != SEGMENT_TYPE_I40E)
7544 I40E_SECTION_TABLE(profile, sec_tbl);
7546 for (i = 0; i < sec_tbl->section_count; i++) {
7547 sec_off = sec_tbl->section_offset[i];
7548 sec = I40E_SECTION_HEADER(profile, sec_off);
7549 if (sec->section.type == section_type)
7557 * i40e_ddp_exec_aq_section - Execute generic AQ for DDP
7558 * @hw: pointer to the hw struct
7559 * @aq: command buffer containing all data to execute AQ
7562 i40e_status_code i40e_ddp_exec_aq_section(struct i40e_hw *hw,
7563 struct i40e_profile_aq_section *aq)
7565 enum i40e_status_code status;
7566 struct i40e_aq_desc desc;
7570 i40e_fill_default_direct_cmd_desc(&desc, aq->opcode);
7571 desc.flags |= CPU_TO_LE16(aq->flags);
7572 i40e_memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw),
7573 I40E_NONDMA_TO_NONDMA);
7575 msglen = aq->datalen;
7577 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
7579 if (msglen > I40E_AQ_LARGE_BUF)
7580 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7581 desc.datalen = CPU_TO_LE16(msglen);
7585 status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL);
7587 if (status != I40E_SUCCESS) {
7588 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7589 "unable to exec DDP AQ opcode %u, error %d\n",
7590 aq->opcode, status);
7594 /* copy returned desc to aq_buf */
7595 i40e_memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw),
7596 I40E_NONDMA_TO_NONDMA);
7598 return I40E_SUCCESS;
7602 * i40e_validate_profile
7603 * @hw: pointer to the hardware structure
7604 * @profile: pointer to the profile segment of the package to be validated
7605 * @track_id: package tracking id
7606 * @rollback: flag if the profile is for rollback.
7608 * Validates supported devices and profile's sections.
7610 STATIC enum i40e_status_code
7611 i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7612 u32 track_id, bool rollback)
7614 struct i40e_profile_section_header *sec = NULL;
7615 enum i40e_status_code status = I40E_SUCCESS;
7616 struct i40e_section_table *sec_tbl;
7622 if (track_id == I40E_DDP_TRACKID_INVALID) {
7623 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n");
7624 return I40E_NOT_SUPPORTED;
7627 dev_cnt = profile->device_table_count;
7628 for (i = 0; i < dev_cnt; i++) {
7629 vendor_dev_id = profile->device_table[i].vendor_dev_id;
7630 if ((vendor_dev_id >> 16) == I40E_INTEL_VENDOR_ID &&
7631 hw->device_id == (vendor_dev_id & 0xFFFF))
7634 if (dev_cnt && (i == dev_cnt)) {
7635 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7636 "Device doesn't support DDP\n");
7637 return I40E_ERR_DEVICE_NOT_SUPPORTED;
7640 I40E_SECTION_TABLE(profile, sec_tbl);
7642 /* Validate sections types */
7643 for (i = 0; i < sec_tbl->section_count; i++) {
7644 sec_off = sec_tbl->section_offset[i];
7645 sec = I40E_SECTION_HEADER(profile, sec_off);
7647 if (sec->section.type == SECTION_TYPE_MMIO ||
7648 sec->section.type == SECTION_TYPE_AQ ||
7649 sec->section.type == SECTION_TYPE_RB_AQ) {
7650 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7651 "Not a roll-back package\n");
7652 return I40E_NOT_SUPPORTED;
7655 if (sec->section.type == SECTION_TYPE_RB_AQ ||
7656 sec->section.type == SECTION_TYPE_RB_MMIO) {
7657 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7658 "Not an original package\n");
7659 return I40E_NOT_SUPPORTED;
7668 * i40e_write_profile
7669 * @hw: pointer to the hardware structure
7670 * @profile: pointer to the profile segment of the package to be downloaded
7671 * @track_id: package tracking id
7673 * Handles the download of a complete package.
7675 enum i40e_status_code
7676 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7679 enum i40e_status_code status = I40E_SUCCESS;
7680 struct i40e_section_table *sec_tbl;
7681 struct i40e_profile_section_header *sec = NULL;
7682 struct i40e_profile_aq_section *ddp_aq;
7683 u32 section_size = 0;
7684 u32 offset = 0, info = 0;
7688 status = i40e_validate_profile(hw, profile, track_id, false);
7692 I40E_SECTION_TABLE(profile, sec_tbl);
7694 for (i = 0; i < sec_tbl->section_count; i++) {
7695 sec_off = sec_tbl->section_offset[i];
7696 sec = I40E_SECTION_HEADER(profile, sec_off);
7697 /* Process generic admin command */
7698 if (sec->section.type == SECTION_TYPE_AQ) {
7699 ddp_aq = (struct i40e_profile_aq_section *)&sec[1];
7700 status = i40e_ddp_exec_aq_section(hw, ddp_aq);
7702 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7703 "Failed to execute aq: section %d, opcode %u\n",
7707 sec->section.type = SECTION_TYPE_RB_AQ;
7710 /* Skip any non-mmio sections */
7711 if (sec->section.type != SECTION_TYPE_MMIO)
7714 section_size = sec->section.size +
7715 sizeof(struct i40e_profile_section_header);
7717 /* Write MMIO section */
7718 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
7719 track_id, &offset, &info, NULL);
7721 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7722 "Failed to write profile: section %d, offset %d, info %d\n",
7731 * i40e_rollback_profile
7732 * @hw: pointer to the hardware structure
7733 * @profile: pointer to the profile segment of the package to be removed
7734 * @track_id: package tracking id
7736 * Rolls back previously loaded package.
7738 enum i40e_status_code
7739 i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7742 struct i40e_profile_section_header *sec = NULL;
7743 enum i40e_status_code status = I40E_SUCCESS;
7744 struct i40e_section_table *sec_tbl;
7745 u32 offset = 0, info = 0;
7746 u32 section_size = 0;
7750 status = i40e_validate_profile(hw, profile, track_id, true);
7754 I40E_SECTION_TABLE(profile, sec_tbl);
7756 /* For rollback write sections in reverse */
7757 for (i = sec_tbl->section_count - 1; i >= 0; i--) {
7758 sec_off = sec_tbl->section_offset[i];
7759 sec = I40E_SECTION_HEADER(profile, sec_off);
7761 /* Skip any non-rollback sections */
7762 if (sec->section.type != SECTION_TYPE_RB_MMIO)
7765 section_size = sec->section.size +
7766 sizeof(struct i40e_profile_section_header);
7768 /* Write roll-back MMIO section */
7769 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
7770 track_id, &offset, &info, NULL);
7772 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7773 "Failed to write profile: section %d, offset %d, info %d\n",
7782 * i40e_add_pinfo_to_list
7783 * @hw: pointer to the hardware structure
7784 * @profile: pointer to the profile segment of the package
7785 * @profile_info_sec: buffer for information section
7786 * @track_id: package tracking id
7788 * Register a profile to the list of loaded profiles.
7790 enum i40e_status_code
7791 i40e_add_pinfo_to_list(struct i40e_hw *hw,
7792 struct i40e_profile_segment *profile,
7793 u8 *profile_info_sec, u32 track_id)
7795 enum i40e_status_code status = I40E_SUCCESS;
7796 struct i40e_profile_section_header *sec = NULL;
7797 struct i40e_profile_info *pinfo;
7798 u32 offset = 0, info = 0;
7800 sec = (struct i40e_profile_section_header *)profile_info_sec;
7802 sec->data_end = sizeof(struct i40e_profile_section_header) +
7803 sizeof(struct i40e_profile_info);
7804 sec->section.type = SECTION_TYPE_INFO;
7805 sec->section.offset = sizeof(struct i40e_profile_section_header);
7806 sec->section.size = sizeof(struct i40e_profile_info);
7807 pinfo = (struct i40e_profile_info *)(profile_info_sec +
7808 sec->section.offset);
7809 pinfo->track_id = track_id;
7810 pinfo->version = profile->version;
7811 pinfo->op = I40E_DDP_ADD_TRACKID;
7812 i40e_memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE,
7813 I40E_NONDMA_TO_NONDMA);
7815 status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
7816 track_id, &offset, &info, NULL);