1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "i40e_type.h"
35 #include "i40e_adminq.h"
36 #include "i40e_prototype.h"
37 #include "i40e_virtchnl.h"
41 * i40e_set_mac_type - Sets MAC type
42 * @hw: pointer to the HW structure
44 * This function sets the mac type of the adapter based on the
45 * vendor ID and device ID stored in the hw structure.
47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
53 enum i40e_status_code status = I40E_SUCCESS;
55 DEBUGFUNC("i40e_set_mac_type\n");
57 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
58 switch (hw->device_id) {
59 case I40E_DEV_ID_SFP_XL710:
60 case I40E_DEV_ID_QEMU:
61 case I40E_DEV_ID_KX_B:
62 case I40E_DEV_ID_KX_C:
63 case I40E_DEV_ID_QSFP_A:
64 case I40E_DEV_ID_QSFP_B:
65 case I40E_DEV_ID_QSFP_C:
66 case I40E_DEV_ID_10G_BASE_T:
67 case I40E_DEV_ID_10G_BASE_T4:
68 case I40E_DEV_ID_20G_KR2:
69 case I40E_DEV_ID_20G_KR2_A:
70 case I40E_DEV_ID_25G_B:
71 case I40E_DEV_ID_25G_SFP28:
72 hw->mac.type = I40E_MAC_XL710;
75 #ifdef X722_A0_SUPPORT
76 case I40E_DEV_ID_X722_A0:
78 case I40E_DEV_ID_KX_X722:
79 case I40E_DEV_ID_QSFP_X722:
80 case I40E_DEV_ID_SFP_X722:
81 case I40E_DEV_ID_1G_BASE_T_X722:
82 case I40E_DEV_ID_10G_BASE_T_X722:
83 case I40E_DEV_ID_SFP_I_X722:
84 hw->mac.type = I40E_MAC_X722;
88 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
89 case I40E_DEV_ID_X722_VF:
90 case I40E_DEV_ID_X722_VF_HV:
91 #ifdef X722_A0_SUPPORT
92 case I40E_DEV_ID_X722_A0_VF:
94 hw->mac.type = I40E_MAC_X722_VF;
96 #endif /* INTEGRATED_VF || VF_DRIVER */
97 #endif /* X722_SUPPORT */
98 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
100 case I40E_DEV_ID_VF_HV:
101 hw->mac.type = I40E_MAC_VF;
105 hw->mac.type = I40E_MAC_GENERIC;
109 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
112 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
113 hw->mac.type, status);
117 #ifndef I40E_NDIS_SUPPORT
119 * i40e_aq_str - convert AQ err code to a string
120 * @hw: pointer to the HW structure
121 * @aq_err: the AQ error code to convert
123 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
128 case I40E_AQ_RC_EPERM:
129 return "I40E_AQ_RC_EPERM";
130 case I40E_AQ_RC_ENOENT:
131 return "I40E_AQ_RC_ENOENT";
132 case I40E_AQ_RC_ESRCH:
133 return "I40E_AQ_RC_ESRCH";
134 case I40E_AQ_RC_EINTR:
135 return "I40E_AQ_RC_EINTR";
137 return "I40E_AQ_RC_EIO";
138 case I40E_AQ_RC_ENXIO:
139 return "I40E_AQ_RC_ENXIO";
140 case I40E_AQ_RC_E2BIG:
141 return "I40E_AQ_RC_E2BIG";
142 case I40E_AQ_RC_EAGAIN:
143 return "I40E_AQ_RC_EAGAIN";
144 case I40E_AQ_RC_ENOMEM:
145 return "I40E_AQ_RC_ENOMEM";
146 case I40E_AQ_RC_EACCES:
147 return "I40E_AQ_RC_EACCES";
148 case I40E_AQ_RC_EFAULT:
149 return "I40E_AQ_RC_EFAULT";
150 case I40E_AQ_RC_EBUSY:
151 return "I40E_AQ_RC_EBUSY";
152 case I40E_AQ_RC_EEXIST:
153 return "I40E_AQ_RC_EEXIST";
154 case I40E_AQ_RC_EINVAL:
155 return "I40E_AQ_RC_EINVAL";
156 case I40E_AQ_RC_ENOTTY:
157 return "I40E_AQ_RC_ENOTTY";
158 case I40E_AQ_RC_ENOSPC:
159 return "I40E_AQ_RC_ENOSPC";
160 case I40E_AQ_RC_ENOSYS:
161 return "I40E_AQ_RC_ENOSYS";
162 case I40E_AQ_RC_ERANGE:
163 return "I40E_AQ_RC_ERANGE";
164 case I40E_AQ_RC_EFLUSHED:
165 return "I40E_AQ_RC_EFLUSHED";
166 case I40E_AQ_RC_BAD_ADDR:
167 return "I40E_AQ_RC_BAD_ADDR";
168 case I40E_AQ_RC_EMODE:
169 return "I40E_AQ_RC_EMODE";
170 case I40E_AQ_RC_EFBIG:
171 return "I40E_AQ_RC_EFBIG";
174 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
179 * i40e_stat_str - convert status err code to a string
180 * @hw: pointer to the HW structure
181 * @stat_err: the status error code to convert
183 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
189 return "I40E_ERR_NVM";
190 case I40E_ERR_NVM_CHECKSUM:
191 return "I40E_ERR_NVM_CHECKSUM";
193 return "I40E_ERR_PHY";
194 case I40E_ERR_CONFIG:
195 return "I40E_ERR_CONFIG";
197 return "I40E_ERR_PARAM";
198 case I40E_ERR_MAC_TYPE:
199 return "I40E_ERR_MAC_TYPE";
200 case I40E_ERR_UNKNOWN_PHY:
201 return "I40E_ERR_UNKNOWN_PHY";
202 case I40E_ERR_LINK_SETUP:
203 return "I40E_ERR_LINK_SETUP";
204 case I40E_ERR_ADAPTER_STOPPED:
205 return "I40E_ERR_ADAPTER_STOPPED";
206 case I40E_ERR_INVALID_MAC_ADDR:
207 return "I40E_ERR_INVALID_MAC_ADDR";
208 case I40E_ERR_DEVICE_NOT_SUPPORTED:
209 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
210 case I40E_ERR_MASTER_REQUESTS_PENDING:
211 return "I40E_ERR_MASTER_REQUESTS_PENDING";
212 case I40E_ERR_INVALID_LINK_SETTINGS:
213 return "I40E_ERR_INVALID_LINK_SETTINGS";
214 case I40E_ERR_AUTONEG_NOT_COMPLETE:
215 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
216 case I40E_ERR_RESET_FAILED:
217 return "I40E_ERR_RESET_FAILED";
218 case I40E_ERR_SWFW_SYNC:
219 return "I40E_ERR_SWFW_SYNC";
220 case I40E_ERR_NO_AVAILABLE_VSI:
221 return "I40E_ERR_NO_AVAILABLE_VSI";
222 case I40E_ERR_NO_MEMORY:
223 return "I40E_ERR_NO_MEMORY";
224 case I40E_ERR_BAD_PTR:
225 return "I40E_ERR_BAD_PTR";
226 case I40E_ERR_RING_FULL:
227 return "I40E_ERR_RING_FULL";
228 case I40E_ERR_INVALID_PD_ID:
229 return "I40E_ERR_INVALID_PD_ID";
230 case I40E_ERR_INVALID_QP_ID:
231 return "I40E_ERR_INVALID_QP_ID";
232 case I40E_ERR_INVALID_CQ_ID:
233 return "I40E_ERR_INVALID_CQ_ID";
234 case I40E_ERR_INVALID_CEQ_ID:
235 return "I40E_ERR_INVALID_CEQ_ID";
236 case I40E_ERR_INVALID_AEQ_ID:
237 return "I40E_ERR_INVALID_AEQ_ID";
238 case I40E_ERR_INVALID_SIZE:
239 return "I40E_ERR_INVALID_SIZE";
240 case I40E_ERR_INVALID_ARP_INDEX:
241 return "I40E_ERR_INVALID_ARP_INDEX";
242 case I40E_ERR_INVALID_FPM_FUNC_ID:
243 return "I40E_ERR_INVALID_FPM_FUNC_ID";
244 case I40E_ERR_QP_INVALID_MSG_SIZE:
245 return "I40E_ERR_QP_INVALID_MSG_SIZE";
246 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
247 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
248 case I40E_ERR_INVALID_FRAG_COUNT:
249 return "I40E_ERR_INVALID_FRAG_COUNT";
250 case I40E_ERR_QUEUE_EMPTY:
251 return "I40E_ERR_QUEUE_EMPTY";
252 case I40E_ERR_INVALID_ALIGNMENT:
253 return "I40E_ERR_INVALID_ALIGNMENT";
254 case I40E_ERR_FLUSHED_QUEUE:
255 return "I40E_ERR_FLUSHED_QUEUE";
256 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
257 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
258 case I40E_ERR_INVALID_IMM_DATA_SIZE:
259 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
260 case I40E_ERR_TIMEOUT:
261 return "I40E_ERR_TIMEOUT";
262 case I40E_ERR_OPCODE_MISMATCH:
263 return "I40E_ERR_OPCODE_MISMATCH";
264 case I40E_ERR_CQP_COMPL_ERROR:
265 return "I40E_ERR_CQP_COMPL_ERROR";
266 case I40E_ERR_INVALID_VF_ID:
267 return "I40E_ERR_INVALID_VF_ID";
268 case I40E_ERR_INVALID_HMCFN_ID:
269 return "I40E_ERR_INVALID_HMCFN_ID";
270 case I40E_ERR_BACKING_PAGE_ERROR:
271 return "I40E_ERR_BACKING_PAGE_ERROR";
272 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
273 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
274 case I40E_ERR_INVALID_PBLE_INDEX:
275 return "I40E_ERR_INVALID_PBLE_INDEX";
276 case I40E_ERR_INVALID_SD_INDEX:
277 return "I40E_ERR_INVALID_SD_INDEX";
278 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
279 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
280 case I40E_ERR_INVALID_SD_TYPE:
281 return "I40E_ERR_INVALID_SD_TYPE";
282 case I40E_ERR_MEMCPY_FAILED:
283 return "I40E_ERR_MEMCPY_FAILED";
284 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
285 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
286 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
287 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
288 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
289 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
290 case I40E_ERR_SRQ_ENABLED:
291 return "I40E_ERR_SRQ_ENABLED";
292 case I40E_ERR_ADMIN_QUEUE_ERROR:
293 return "I40E_ERR_ADMIN_QUEUE_ERROR";
294 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
295 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
296 case I40E_ERR_BUF_TOO_SHORT:
297 return "I40E_ERR_BUF_TOO_SHORT";
298 case I40E_ERR_ADMIN_QUEUE_FULL:
299 return "I40E_ERR_ADMIN_QUEUE_FULL";
300 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
301 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
302 case I40E_ERR_BAD_IWARP_CQE:
303 return "I40E_ERR_BAD_IWARP_CQE";
304 case I40E_ERR_NVM_BLANK_MODE:
305 return "I40E_ERR_NVM_BLANK_MODE";
306 case I40E_ERR_NOT_IMPLEMENTED:
307 return "I40E_ERR_NOT_IMPLEMENTED";
308 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
309 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
310 case I40E_ERR_DIAG_TEST_FAILED:
311 return "I40E_ERR_DIAG_TEST_FAILED";
312 case I40E_ERR_NOT_READY:
313 return "I40E_ERR_NOT_READY";
314 case I40E_NOT_SUPPORTED:
315 return "I40E_NOT_SUPPORTED";
316 case I40E_ERR_FIRMWARE_API_VERSION:
317 return "I40E_ERR_FIRMWARE_API_VERSION";
320 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
324 #endif /* I40E_NDIS_SUPPORT */
327 * @hw: debug mask related to admin queue
329 * @desc: pointer to admin queue descriptor
330 * @buffer: pointer to command buffer
331 * @buf_len: max length of buffer
333 * Dumps debug log about adminq command with descriptor contents.
335 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
336 void *buffer, u16 buf_len)
338 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
339 u16 len = LE16_TO_CPU(aq_desc->datalen);
340 u8 *buf = (u8 *)buffer;
343 if ((!(mask & hw->debug_mask)) || (desc == NULL))
347 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
348 LE16_TO_CPU(aq_desc->opcode),
349 LE16_TO_CPU(aq_desc->flags),
350 LE16_TO_CPU(aq_desc->datalen),
351 LE16_TO_CPU(aq_desc->retval));
352 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
353 LE32_TO_CPU(aq_desc->cookie_high),
354 LE32_TO_CPU(aq_desc->cookie_low));
355 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
356 LE32_TO_CPU(aq_desc->params.internal.param0),
357 LE32_TO_CPU(aq_desc->params.internal.param1));
358 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
359 LE32_TO_CPU(aq_desc->params.external.addr_high),
360 LE32_TO_CPU(aq_desc->params.external.addr_low));
362 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
363 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
366 /* write the full 16-byte chunks */
367 for (i = 0; i < (len - 16); i += 16)
369 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
370 i, buf[i], buf[i+1], buf[i+2], buf[i+3],
371 buf[i+4], buf[i+5], buf[i+6], buf[i+7],
372 buf[i+8], buf[i+9], buf[i+10], buf[i+11],
373 buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
374 /* the most we could have left is 16 bytes, pad with zeros */
380 memset(d_buf, 0, sizeof(d_buf));
381 for (j = 0; i < len; j++, i++)
384 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
385 i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
386 d_buf[4], d_buf[5], d_buf[6], d_buf[7],
387 d_buf[8], d_buf[9], d_buf[10], d_buf[11],
388 d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
394 * i40e_check_asq_alive
395 * @hw: pointer to the hw struct
397 * Returns true if Queue is enabled else false.
399 bool i40e_check_asq_alive(struct i40e_hw *hw)
405 return !!(rd32(hw, hw->aq.asq.len) &
406 I40E_PF_ATQLEN_ATQENABLE_MASK);
408 return !!(rd32(hw, hw->aq.asq.len) &
409 I40E_PF_ATQLEN_ATQENABLE_MASK);
410 #endif /* INTEGRATED_VF */
411 #endif /* PF_DRIVER */
415 return !!(rd32(hw, hw->aq.asq.len) &
416 I40E_VF_ATQLEN1_ATQENABLE_MASK);
418 return !!(rd32(hw, hw->aq.asq.len) &
419 I40E_VF_ATQLEN1_ATQENABLE_MASK);
420 #endif /* INTEGRATED_VF */
421 #endif /* VF_DRIVER */
426 * i40e_aq_queue_shutdown
427 * @hw: pointer to the hw struct
428 * @unloading: is the driver unloading itself
430 * Tell the Firmware that we're shutting down the AdminQ and whether
431 * or not the driver is unloading as well.
433 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
436 struct i40e_aq_desc desc;
437 struct i40e_aqc_queue_shutdown *cmd =
438 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
439 enum i40e_status_code status;
441 i40e_fill_default_direct_cmd_desc(&desc,
442 i40e_aqc_opc_queue_shutdown);
445 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
446 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
453 * i40e_aq_get_set_rss_lut
454 * @hw: pointer to the hardware structure
455 * @vsi_id: vsi fw index
456 * @pf_lut: for PF table set true, for VSI table set false
457 * @lut: pointer to the lut buffer provided by the caller
458 * @lut_size: size of the lut buffer
459 * @set: set true to set the table, false to get the table
461 * Internal function to get or set RSS look up table
463 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
464 u16 vsi_id, bool pf_lut,
465 u8 *lut, u16 lut_size,
468 enum i40e_status_code status;
469 struct i40e_aq_desc desc;
470 struct i40e_aqc_get_set_rss_lut *cmd_resp =
471 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
474 i40e_fill_default_direct_cmd_desc(&desc,
475 i40e_aqc_opc_set_rss_lut);
477 i40e_fill_default_direct_cmd_desc(&desc,
478 i40e_aqc_opc_get_rss_lut);
480 /* Indirect command */
481 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
482 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
485 CPU_TO_LE16((u16)((vsi_id <<
486 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
487 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
488 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
491 cmd_resp->flags |= CPU_TO_LE16((u16)
492 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
493 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
494 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
496 cmd_resp->flags |= CPU_TO_LE16((u16)
497 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
498 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
499 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
501 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
507 * i40e_aq_get_rss_lut
508 * @hw: pointer to the hardware structure
509 * @vsi_id: vsi fw index
510 * @pf_lut: for PF table set true, for VSI table set false
511 * @lut: pointer to the lut buffer provided by the caller
512 * @lut_size: size of the lut buffer
514 * get the RSS lookup table, PF or VSI type
516 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
517 bool pf_lut, u8 *lut, u16 lut_size)
519 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
524 * i40e_aq_set_rss_lut
525 * @hw: pointer to the hardware structure
526 * @vsi_id: vsi fw index
527 * @pf_lut: for PF table set true, for VSI table set false
528 * @lut: pointer to the lut buffer provided by the caller
529 * @lut_size: size of the lut buffer
531 * set the RSS lookup table, PF or VSI type
533 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
534 bool pf_lut, u8 *lut, u16 lut_size)
536 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
540 * i40e_aq_get_set_rss_key
541 * @hw: pointer to the hw struct
542 * @vsi_id: vsi fw index
543 * @key: pointer to key info struct
544 * @set: set true to set the key, false to get the key
546 * get the RSS key per VSI
548 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
550 struct i40e_aqc_get_set_rss_key_data *key,
553 enum i40e_status_code status;
554 struct i40e_aq_desc desc;
555 struct i40e_aqc_get_set_rss_key *cmd_resp =
556 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
557 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
560 i40e_fill_default_direct_cmd_desc(&desc,
561 i40e_aqc_opc_set_rss_key);
563 i40e_fill_default_direct_cmd_desc(&desc,
564 i40e_aqc_opc_get_rss_key);
566 /* Indirect command */
567 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
568 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
571 CPU_TO_LE16((u16)((vsi_id <<
572 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
573 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
574 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
576 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
582 * i40e_aq_get_rss_key
583 * @hw: pointer to the hw struct
584 * @vsi_id: vsi fw index
585 * @key: pointer to key info struct
588 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
590 struct i40e_aqc_get_set_rss_key_data *key)
592 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
596 * i40e_aq_set_rss_key
597 * @hw: pointer to the hw struct
598 * @vsi_id: vsi fw index
599 * @key: pointer to key info struct
601 * set the RSS key per VSI
603 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
605 struct i40e_aqc_get_set_rss_key_data *key)
607 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
609 #endif /* X722_SUPPORT */
611 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
612 * hardware to a bit-field that can be used by SW to more easily determine the
615 * Macros are used to shorten the table lines and make this table human
618 * We store the PTYPE in the top byte of the bit field - this is just so that
619 * we can check that the table doesn't have a row missing, as the index into
620 * the table should be the PTYPE.
624 * IF NOT i40e_ptype_lookup[ptype].known
627 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
628 * Use the rest of the fields to look at the tunnels, inner protocols, etc
630 * Use the enum i40e_rx_l2_ptype to decode the packet type
634 /* macro to make the table lines short */
635 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
638 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
639 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
640 I40E_RX_PTYPE_##OUTER_FRAG, \
641 I40E_RX_PTYPE_TUNNEL_##T, \
642 I40E_RX_PTYPE_TUNNEL_END_##TE, \
643 I40E_RX_PTYPE_##TEF, \
644 I40E_RX_PTYPE_INNER_PROT_##I, \
645 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
647 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
648 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
650 /* shorter macros makes the table fit but are terse */
651 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
652 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
653 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
655 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
656 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
657 /* L2 Packet types */
658 I40E_PTT_UNUSED_ENTRY(0),
659 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
660 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
661 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
662 I40E_PTT_UNUSED_ENTRY(4),
663 I40E_PTT_UNUSED_ENTRY(5),
664 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
665 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
666 I40E_PTT_UNUSED_ENTRY(8),
667 I40E_PTT_UNUSED_ENTRY(9),
668 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
669 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
670 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
671 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
672 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
673 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
674 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
675 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
676 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
677 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
678 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
679 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
681 /* Non Tunneled IPv4 */
682 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
683 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
684 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
685 I40E_PTT_UNUSED_ENTRY(25),
686 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
687 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
688 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
691 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
692 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
693 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
694 I40E_PTT_UNUSED_ENTRY(32),
695 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
696 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
697 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
700 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
701 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
702 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
703 I40E_PTT_UNUSED_ENTRY(39),
704 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
705 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
706 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
708 /* IPv4 --> GRE/NAT */
709 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
711 /* IPv4 --> GRE/NAT --> IPv4 */
712 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
713 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
714 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
715 I40E_PTT_UNUSED_ENTRY(47),
716 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
717 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
718 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
720 /* IPv4 --> GRE/NAT --> IPv6 */
721 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
722 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
723 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
724 I40E_PTT_UNUSED_ENTRY(54),
725 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
726 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
727 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
729 /* IPv4 --> GRE/NAT --> MAC */
730 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
732 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
733 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
734 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
735 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
736 I40E_PTT_UNUSED_ENTRY(62),
737 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
738 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
739 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
741 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
742 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
743 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
744 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
745 I40E_PTT_UNUSED_ENTRY(69),
746 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
747 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
748 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
750 /* IPv4 --> GRE/NAT --> MAC/VLAN */
751 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
753 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
754 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
755 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
756 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
757 I40E_PTT_UNUSED_ENTRY(77),
758 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
759 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
760 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
762 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
763 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
764 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
765 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
766 I40E_PTT_UNUSED_ENTRY(84),
767 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
768 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
769 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
771 /* Non Tunneled IPv6 */
772 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
773 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
774 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4),
775 I40E_PTT_UNUSED_ENTRY(91),
776 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
777 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
778 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
781 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
782 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
783 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
784 I40E_PTT_UNUSED_ENTRY(98),
785 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
786 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
787 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
790 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
791 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
792 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
793 I40E_PTT_UNUSED_ENTRY(105),
794 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
795 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
796 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
798 /* IPv6 --> GRE/NAT */
799 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
801 /* IPv6 --> GRE/NAT -> IPv4 */
802 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
803 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
804 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
805 I40E_PTT_UNUSED_ENTRY(113),
806 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
807 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
808 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
810 /* IPv6 --> GRE/NAT -> IPv6 */
811 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
812 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
813 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
814 I40E_PTT_UNUSED_ENTRY(120),
815 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
816 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
817 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
819 /* IPv6 --> GRE/NAT -> MAC */
820 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
822 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
823 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
824 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
825 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
826 I40E_PTT_UNUSED_ENTRY(128),
827 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
828 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
829 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
831 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
832 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
833 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
834 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
835 I40E_PTT_UNUSED_ENTRY(135),
836 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
837 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
838 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
840 /* IPv6 --> GRE/NAT -> MAC/VLAN */
841 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
843 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
844 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
845 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
846 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
847 I40E_PTT_UNUSED_ENTRY(143),
848 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
849 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
850 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
852 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
853 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
854 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
855 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
856 I40E_PTT_UNUSED_ENTRY(150),
857 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
858 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
859 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
862 I40E_PTT_UNUSED_ENTRY(154),
863 I40E_PTT_UNUSED_ENTRY(155),
864 I40E_PTT_UNUSED_ENTRY(156),
865 I40E_PTT_UNUSED_ENTRY(157),
866 I40E_PTT_UNUSED_ENTRY(158),
867 I40E_PTT_UNUSED_ENTRY(159),
869 I40E_PTT_UNUSED_ENTRY(160),
870 I40E_PTT_UNUSED_ENTRY(161),
871 I40E_PTT_UNUSED_ENTRY(162),
872 I40E_PTT_UNUSED_ENTRY(163),
873 I40E_PTT_UNUSED_ENTRY(164),
874 I40E_PTT_UNUSED_ENTRY(165),
875 I40E_PTT_UNUSED_ENTRY(166),
876 I40E_PTT_UNUSED_ENTRY(167),
877 I40E_PTT_UNUSED_ENTRY(168),
878 I40E_PTT_UNUSED_ENTRY(169),
880 I40E_PTT_UNUSED_ENTRY(170),
881 I40E_PTT_UNUSED_ENTRY(171),
882 I40E_PTT_UNUSED_ENTRY(172),
883 I40E_PTT_UNUSED_ENTRY(173),
884 I40E_PTT_UNUSED_ENTRY(174),
885 I40E_PTT_UNUSED_ENTRY(175),
886 I40E_PTT_UNUSED_ENTRY(176),
887 I40E_PTT_UNUSED_ENTRY(177),
888 I40E_PTT_UNUSED_ENTRY(178),
889 I40E_PTT_UNUSED_ENTRY(179),
891 I40E_PTT_UNUSED_ENTRY(180),
892 I40E_PTT_UNUSED_ENTRY(181),
893 I40E_PTT_UNUSED_ENTRY(182),
894 I40E_PTT_UNUSED_ENTRY(183),
895 I40E_PTT_UNUSED_ENTRY(184),
896 I40E_PTT_UNUSED_ENTRY(185),
897 I40E_PTT_UNUSED_ENTRY(186),
898 I40E_PTT_UNUSED_ENTRY(187),
899 I40E_PTT_UNUSED_ENTRY(188),
900 I40E_PTT_UNUSED_ENTRY(189),
902 I40E_PTT_UNUSED_ENTRY(190),
903 I40E_PTT_UNUSED_ENTRY(191),
904 I40E_PTT_UNUSED_ENTRY(192),
905 I40E_PTT_UNUSED_ENTRY(193),
906 I40E_PTT_UNUSED_ENTRY(194),
907 I40E_PTT_UNUSED_ENTRY(195),
908 I40E_PTT_UNUSED_ENTRY(196),
909 I40E_PTT_UNUSED_ENTRY(197),
910 I40E_PTT_UNUSED_ENTRY(198),
911 I40E_PTT_UNUSED_ENTRY(199),
913 I40E_PTT_UNUSED_ENTRY(200),
914 I40E_PTT_UNUSED_ENTRY(201),
915 I40E_PTT_UNUSED_ENTRY(202),
916 I40E_PTT_UNUSED_ENTRY(203),
917 I40E_PTT_UNUSED_ENTRY(204),
918 I40E_PTT_UNUSED_ENTRY(205),
919 I40E_PTT_UNUSED_ENTRY(206),
920 I40E_PTT_UNUSED_ENTRY(207),
921 I40E_PTT_UNUSED_ENTRY(208),
922 I40E_PTT_UNUSED_ENTRY(209),
924 I40E_PTT_UNUSED_ENTRY(210),
925 I40E_PTT_UNUSED_ENTRY(211),
926 I40E_PTT_UNUSED_ENTRY(212),
927 I40E_PTT_UNUSED_ENTRY(213),
928 I40E_PTT_UNUSED_ENTRY(214),
929 I40E_PTT_UNUSED_ENTRY(215),
930 I40E_PTT_UNUSED_ENTRY(216),
931 I40E_PTT_UNUSED_ENTRY(217),
932 I40E_PTT_UNUSED_ENTRY(218),
933 I40E_PTT_UNUSED_ENTRY(219),
935 I40E_PTT_UNUSED_ENTRY(220),
936 I40E_PTT_UNUSED_ENTRY(221),
937 I40E_PTT_UNUSED_ENTRY(222),
938 I40E_PTT_UNUSED_ENTRY(223),
939 I40E_PTT_UNUSED_ENTRY(224),
940 I40E_PTT_UNUSED_ENTRY(225),
941 I40E_PTT_UNUSED_ENTRY(226),
942 I40E_PTT_UNUSED_ENTRY(227),
943 I40E_PTT_UNUSED_ENTRY(228),
944 I40E_PTT_UNUSED_ENTRY(229),
946 I40E_PTT_UNUSED_ENTRY(230),
947 I40E_PTT_UNUSED_ENTRY(231),
948 I40E_PTT_UNUSED_ENTRY(232),
949 I40E_PTT_UNUSED_ENTRY(233),
950 I40E_PTT_UNUSED_ENTRY(234),
951 I40E_PTT_UNUSED_ENTRY(235),
952 I40E_PTT_UNUSED_ENTRY(236),
953 I40E_PTT_UNUSED_ENTRY(237),
954 I40E_PTT_UNUSED_ENTRY(238),
955 I40E_PTT_UNUSED_ENTRY(239),
957 I40E_PTT_UNUSED_ENTRY(240),
958 I40E_PTT_UNUSED_ENTRY(241),
959 I40E_PTT_UNUSED_ENTRY(242),
960 I40E_PTT_UNUSED_ENTRY(243),
961 I40E_PTT_UNUSED_ENTRY(244),
962 I40E_PTT_UNUSED_ENTRY(245),
963 I40E_PTT_UNUSED_ENTRY(246),
964 I40E_PTT_UNUSED_ENTRY(247),
965 I40E_PTT_UNUSED_ENTRY(248),
966 I40E_PTT_UNUSED_ENTRY(249),
968 I40E_PTT_UNUSED_ENTRY(250),
969 I40E_PTT_UNUSED_ENTRY(251),
970 I40E_PTT_UNUSED_ENTRY(252),
971 I40E_PTT_UNUSED_ENTRY(253),
972 I40E_PTT_UNUSED_ENTRY(254),
973 I40E_PTT_UNUSED_ENTRY(255)
978 * i40e_validate_mac_addr - Validate unicast MAC address
979 * @mac_addr: pointer to MAC address
981 * Tests a MAC address to ensure it is a valid Individual Address
983 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
985 enum i40e_status_code status = I40E_SUCCESS;
987 DEBUGFUNC("i40e_validate_mac_addr");
989 /* Broadcast addresses ARE multicast addresses
990 * Make sure it is not a multicast address
991 * Reject the zero address
993 if (I40E_IS_MULTICAST(mac_addr) ||
994 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
995 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
996 status = I40E_ERR_INVALID_MAC_ADDR;
1003 * i40e_init_shared_code - Initialize the shared code
1004 * @hw: pointer to hardware structure
1006 * This assigns the MAC type and PHY code and inits the NVM.
1007 * Does not touch the hardware. This function must be called prior to any
1008 * other function in the shared code. The i40e_hw structure should be
1009 * memset to 0 prior to calling this function. The following fields in
1010 * hw structure should be filled in prior to calling this function:
1011 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1012 * subsystem_vendor_id, and revision_id
1014 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
1016 enum i40e_status_code status = I40E_SUCCESS;
1017 u32 port, ari, func_rid;
1019 DEBUGFUNC("i40e_init_shared_code");
1021 i40e_set_mac_type(hw);
1023 switch (hw->mac.type) {
1024 case I40E_MAC_XL710:
1030 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1033 hw->phy.get_link_info = true;
1035 /* Determine port number and PF number*/
1036 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1037 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1038 hw->port = (u8)port;
1039 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1040 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1041 func_rid = rd32(hw, I40E_PF_FUNC_RID);
1043 hw->pf_id = (u8)(func_rid & 0xff);
1045 hw->pf_id = (u8)(func_rid & 0x7);
1048 if (hw->mac.type == I40E_MAC_X722)
1049 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
1052 status = i40e_init_nvm(hw);
1057 * i40e_aq_mac_address_read - Retrieve the MAC addresses
1058 * @hw: pointer to the hw struct
1059 * @flags: a return indicator of what addresses were added to the addr store
1060 * @addrs: the requestor's mac addr store
1061 * @cmd_details: pointer to command details structure or NULL
1063 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1065 struct i40e_aqc_mac_address_read_data *addrs,
1066 struct i40e_asq_cmd_details *cmd_details)
1068 struct i40e_aq_desc desc;
1069 struct i40e_aqc_mac_address_read *cmd_data =
1070 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1071 enum i40e_status_code status;
1073 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1074 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1076 status = i40e_asq_send_command(hw, &desc, addrs,
1077 sizeof(*addrs), cmd_details);
1078 *flags = LE16_TO_CPU(cmd_data->command_flags);
1084 * i40e_aq_mac_address_write - Change the MAC addresses
1085 * @hw: pointer to the hw struct
1086 * @flags: indicates which MAC to be written
1087 * @mac_addr: address to write
1088 * @cmd_details: pointer to command details structure or NULL
1090 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1091 u16 flags, u8 *mac_addr,
1092 struct i40e_asq_cmd_details *cmd_details)
1094 struct i40e_aq_desc desc;
1095 struct i40e_aqc_mac_address_write *cmd_data =
1096 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1097 enum i40e_status_code status;
1099 i40e_fill_default_direct_cmd_desc(&desc,
1100 i40e_aqc_opc_mac_address_write);
1101 cmd_data->command_flags = CPU_TO_LE16(flags);
1102 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1103 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1104 ((u32)mac_addr[3] << 16) |
1105 ((u32)mac_addr[4] << 8) |
1108 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1114 * i40e_get_mac_addr - get MAC address
1115 * @hw: pointer to the HW structure
1116 * @mac_addr: pointer to MAC address
1118 * Reads the adapter's MAC address from register
1120 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1122 struct i40e_aqc_mac_address_read_data addrs;
1123 enum i40e_status_code status;
1126 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1128 if (flags & I40E_AQC_LAN_ADDR_VALID)
1129 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
1135 * i40e_get_port_mac_addr - get Port MAC address
1136 * @hw: pointer to the HW structure
1137 * @mac_addr: pointer to Port MAC address
1139 * Reads the adapter's Port MAC address
1141 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1143 struct i40e_aqc_mac_address_read_data addrs;
1144 enum i40e_status_code status;
1147 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1151 if (flags & I40E_AQC_PORT_ADDR_VALID)
1152 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
1154 status = I40E_ERR_INVALID_MAC_ADDR;
1160 * i40e_pre_tx_queue_cfg - pre tx queue configure
1161 * @hw: pointer to the HW structure
1162 * @queue: target pf queue index
1163 * @enable: state change request
1165 * Handles hw requirement to indicate intention to enable
1166 * or disable target queue.
1168 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1170 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1174 if (abs_queue_idx >= 128) {
1175 reg_block = abs_queue_idx / 128;
1176 abs_queue_idx %= 128;
1179 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1180 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1181 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1184 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1186 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1188 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1192 * i40e_get_san_mac_addr - get SAN MAC address
1193 * @hw: pointer to the HW structure
1194 * @mac_addr: pointer to SAN MAC address
1196 * Reads the adapter's SAN MAC address from NVM
1198 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1201 struct i40e_aqc_mac_address_read_data addrs;
1202 enum i40e_status_code status;
1205 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1209 if (flags & I40E_AQC_SAN_ADDR_VALID)
1210 memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac));
1212 status = I40E_ERR_INVALID_MAC_ADDR;
1218 * i40e_read_pba_string - Reads part number string from EEPROM
1219 * @hw: pointer to hardware structure
1220 * @pba_num: stores the part number string from the EEPROM
1221 * @pba_num_size: part number string buffer length
1223 * Reads the part number string from the EEPROM.
1225 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1228 enum i40e_status_code status = I40E_SUCCESS;
1234 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1235 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1236 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1240 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1241 if (status != I40E_SUCCESS) {
1242 DEBUGOUT("Failed to read PBA Block pointer.\n");
1246 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1247 if (status != I40E_SUCCESS) {
1248 DEBUGOUT("Failed to read PBA Block size.\n");
1252 /* Subtract one to get PBA word count (PBA Size word is included in
1256 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1257 DEBUGOUT("Buffer to small for PBA data.\n");
1258 return I40E_ERR_PARAM;
1261 for (i = 0; i < pba_size; i++) {
1262 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1263 if (status != I40E_SUCCESS) {
1264 DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1268 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1269 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1271 pba_num[(pba_size * 2)] = '\0';
1277 * i40e_get_media_type - Gets media type
1278 * @hw: pointer to the hardware structure
1280 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1282 enum i40e_media_type media;
1284 switch (hw->phy.link_info.phy_type) {
1285 case I40E_PHY_TYPE_10GBASE_SR:
1286 case I40E_PHY_TYPE_10GBASE_LR:
1287 case I40E_PHY_TYPE_1000BASE_SX:
1288 case I40E_PHY_TYPE_1000BASE_LX:
1289 case I40E_PHY_TYPE_40GBASE_SR4:
1290 case I40E_PHY_TYPE_40GBASE_LR4:
1291 case I40E_PHY_TYPE_25GBASE_LR:
1292 case I40E_PHY_TYPE_25GBASE_SR:
1293 media = I40E_MEDIA_TYPE_FIBER;
1295 case I40E_PHY_TYPE_100BASE_TX:
1296 case I40E_PHY_TYPE_1000BASE_T:
1297 case I40E_PHY_TYPE_10GBASE_T:
1298 media = I40E_MEDIA_TYPE_BASET;
1300 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1301 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1302 case I40E_PHY_TYPE_10GBASE_CR1:
1303 case I40E_PHY_TYPE_40GBASE_CR4:
1304 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1305 case I40E_PHY_TYPE_40GBASE_AOC:
1306 case I40E_PHY_TYPE_10GBASE_AOC:
1307 case I40E_PHY_TYPE_25GBASE_CR:
1308 media = I40E_MEDIA_TYPE_DA;
1310 case I40E_PHY_TYPE_1000BASE_KX:
1311 case I40E_PHY_TYPE_10GBASE_KX4:
1312 case I40E_PHY_TYPE_10GBASE_KR:
1313 case I40E_PHY_TYPE_40GBASE_KR4:
1314 case I40E_PHY_TYPE_20GBASE_KR2:
1315 case I40E_PHY_TYPE_25GBASE_KR:
1316 media = I40E_MEDIA_TYPE_BACKPLANE;
1318 case I40E_PHY_TYPE_SGMII:
1319 case I40E_PHY_TYPE_XAUI:
1320 case I40E_PHY_TYPE_XFI:
1321 case I40E_PHY_TYPE_XLAUI:
1322 case I40E_PHY_TYPE_XLPPI:
1324 media = I40E_MEDIA_TYPE_UNKNOWN;
1331 #define I40E_PF_RESET_WAIT_COUNT 200
1333 * i40e_pf_reset - Reset the PF
1334 * @hw: pointer to the hardware structure
1336 * Assuming someone else has triggered a global reset,
1337 * assure the global reset is complete and then reset the PF
1339 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1346 /* Poll for Global Reset steady state in case of recent GRST.
1347 * The grst delay value is in 100ms units, and we'll wait a
1348 * couple counts longer to be sure we don't just miss the end.
1350 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1351 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1352 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1354 grst_del = grst_del * 20;
1356 for (cnt = 0; cnt < grst_del; cnt++) {
1357 reg = rd32(hw, I40E_GLGEN_RSTAT);
1358 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1360 i40e_msec_delay(100);
1362 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1363 DEBUGOUT("Global reset polling failed to complete.\n");
1364 return I40E_ERR_RESET_FAILED;
1367 /* Now Wait for the FW to be ready */
1368 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1369 reg = rd32(hw, I40E_GLNVM_ULD);
1370 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1371 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1372 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1373 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1374 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1377 i40e_msec_delay(10);
1379 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1380 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1381 DEBUGOUT("wait for FW Reset complete timedout\n");
1382 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1383 return I40E_ERR_RESET_FAILED;
1386 /* If there was a Global Reset in progress when we got here,
1387 * we don't need to do the PF Reset
1390 reg = rd32(hw, I40E_PFGEN_CTRL);
1391 wr32(hw, I40E_PFGEN_CTRL,
1392 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1393 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1394 reg = rd32(hw, I40E_PFGEN_CTRL);
1395 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1399 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1400 DEBUGOUT("PF reset polling failed to complete.\n");
1401 return I40E_ERR_RESET_FAILED;
1405 i40e_clear_pxe_mode(hw);
1408 return I40E_SUCCESS;
1412 * i40e_clear_hw - clear out any left over hw state
1413 * @hw: pointer to the hw struct
1415 * Clear queues and interrupts, typically called at init time,
1416 * but after the capabilities have been found so we know how many
1417 * queues and msix vectors have been allocated.
1419 void i40e_clear_hw(struct i40e_hw *hw)
1421 u32 num_queues, base_queue;
1429 /* get number of interrupts, queues, and vfs */
1430 val = rd32(hw, I40E_GLPCI_CNF2);
1431 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1432 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1433 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1434 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1436 val = rd32(hw, I40E_PFLAN_QALLOC);
1437 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1438 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1439 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1440 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1441 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1442 num_queues = (j - base_queue) + 1;
1446 val = rd32(hw, I40E_PF_VT_PFALLOC);
1447 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1448 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1449 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1450 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1451 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1452 num_vfs = (j - i) + 1;
1456 /* stop all the interrupts */
1457 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1458 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1459 for (i = 0; i < num_pf_int - 2; i++)
1460 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1462 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1463 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1464 wr32(hw, I40E_PFINT_LNKLST0, val);
1465 for (i = 0; i < num_pf_int - 2; i++)
1466 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1467 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1468 for (i = 0; i < num_vfs; i++)
1469 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1470 for (i = 0; i < num_vf_int - 2; i++)
1471 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1473 /* warn the HW of the coming Tx disables */
1474 for (i = 0; i < num_queues; i++) {
1475 u32 abs_queue_idx = base_queue + i;
1478 if (abs_queue_idx >= 128) {
1479 reg_block = abs_queue_idx / 128;
1480 abs_queue_idx %= 128;
1483 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1484 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1485 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1486 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1488 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1490 i40e_usec_delay(400);
1492 /* stop all the queues */
1493 for (i = 0; i < num_queues; i++) {
1494 wr32(hw, I40E_QINT_TQCTL(i), 0);
1495 wr32(hw, I40E_QTX_ENA(i), 0);
1496 wr32(hw, I40E_QINT_RQCTL(i), 0);
1497 wr32(hw, I40E_QRX_ENA(i), 0);
1500 /* short wait for all queue disables to settle */
1501 i40e_usec_delay(50);
1505 * i40e_clear_pxe_mode - clear pxe operations mode
1506 * @hw: pointer to the hw struct
1508 * Make sure all PXE mode settings are cleared, including things
1509 * like descriptor fetch/write-back mode.
1511 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1513 if (i40e_check_asq_alive(hw))
1514 i40e_aq_clear_pxe_mode(hw, NULL);
1518 * i40e_led_is_mine - helper to find matching led
1519 * @hw: pointer to the hw struct
1520 * @idx: index into GPIO registers
1522 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1524 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1529 if (!hw->func_caps.led[idx])
1532 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1533 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1534 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1536 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1537 * if it is not our port then ignore
1539 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1546 #define I40E_COMBINED_ACTIVITY 0xA
1547 #define I40E_FILTER_ACTIVITY 0xE
1548 #define I40E_LINK_ACTIVITY 0xC
1549 #define I40E_MAC_ACTIVITY 0xD
1550 #define I40E_LED0 22
1553 * i40e_led_get - return current on/off mode
1554 * @hw: pointer to the hw struct
1556 * The value returned is the 'mode' field as defined in the
1557 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1558 * values are variations of possible behaviors relating to
1559 * blink, link, and wire.
1561 u32 i40e_led_get(struct i40e_hw *hw)
1563 u32 current_mode = 0;
1567 /* as per the documentation GPIO 22-29 are the LED
1568 * GPIO pins named LED0..LED7
1570 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1571 u32 gpio_val = i40e_led_is_mine(hw, i);
1576 /* ignore gpio LED src mode entries related to the activity
1579 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1580 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1581 switch (current_mode) {
1582 case I40E_COMBINED_ACTIVITY:
1583 case I40E_FILTER_ACTIVITY:
1584 case I40E_MAC_ACTIVITY:
1590 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1591 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1599 * i40e_led_set - set new on/off mode
1600 * @hw: pointer to the hw struct
1601 * @mode: 0=off, 0xf=on (else see manual for mode details)
1602 * @blink: true if the LED should blink when on, false if steady
1604 * if this function is used to turn on the blink it should
1605 * be used to disable the blink when restoring the original state.
1607 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1609 u32 current_mode = 0;
1612 if (mode & 0xfffffff0)
1613 DEBUGOUT1("invalid mode passed in %X\n", mode);
1615 /* as per the documentation GPIO 22-29 are the LED
1616 * GPIO pins named LED0..LED7
1618 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1619 u32 gpio_val = i40e_led_is_mine(hw, i);
1624 /* ignore gpio LED src mode entries related to the activity
1627 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1628 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1629 switch (current_mode) {
1630 case I40E_COMBINED_ACTIVITY:
1631 case I40E_FILTER_ACTIVITY:
1632 case I40E_MAC_ACTIVITY:
1638 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1639 /* this & is a bit of paranoia, but serves as a range check */
1640 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1641 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1643 if (mode == I40E_LINK_ACTIVITY)
1647 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1649 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1651 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1656 /* Admin command wrappers */
1659 * i40e_aq_get_phy_capabilities
1660 * @hw: pointer to the hw struct
1661 * @abilities: structure for PHY capabilities to be filled
1662 * @qualified_modules: report Qualified Modules
1663 * @report_init: report init capabilities (active are default)
1664 * @cmd_details: pointer to command details structure or NULL
1666 * Returns the various PHY abilities supported on the Port.
1668 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1669 bool qualified_modules, bool report_init,
1670 struct i40e_aq_get_phy_abilities_resp *abilities,
1671 struct i40e_asq_cmd_details *cmd_details)
1673 struct i40e_aq_desc desc;
1674 enum i40e_status_code status;
1675 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1678 return I40E_ERR_PARAM;
1680 i40e_fill_default_direct_cmd_desc(&desc,
1681 i40e_aqc_opc_get_phy_abilities);
1683 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1684 if (abilities_size > I40E_AQ_LARGE_BUF)
1685 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1687 if (qualified_modules)
1688 desc.params.external.param0 |=
1689 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1692 desc.params.external.param0 |=
1693 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1695 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1698 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1699 status = I40E_ERR_UNKNOWN_PHY;
1702 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1703 hw->phy.phy_types |= ((u64)abilities->phy_type_ext << 32);
1710 * i40e_aq_set_phy_config
1711 * @hw: pointer to the hw struct
1712 * @config: structure with PHY configuration to be set
1713 * @cmd_details: pointer to command details structure or NULL
1715 * Set the various PHY configuration parameters
1716 * supported on the Port.One or more of the Set PHY config parameters may be
1717 * ignored in an MFP mode as the PF may not have the privilege to set some
1718 * of the PHY Config parameters. This status will be indicated by the
1721 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1722 struct i40e_aq_set_phy_config *config,
1723 struct i40e_asq_cmd_details *cmd_details)
1725 struct i40e_aq_desc desc;
1726 struct i40e_aq_set_phy_config *cmd =
1727 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1728 enum i40e_status_code status;
1731 return I40E_ERR_PARAM;
1733 i40e_fill_default_direct_cmd_desc(&desc,
1734 i40e_aqc_opc_set_phy_config);
1738 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1745 * @hw: pointer to the hw struct
1747 * Set the requested flow control mode using set_phy_config.
1749 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1750 bool atomic_restart)
1752 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1753 struct i40e_aq_get_phy_abilities_resp abilities;
1754 struct i40e_aq_set_phy_config config;
1755 enum i40e_status_code status;
1756 u8 pause_mask = 0x0;
1762 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1763 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1765 case I40E_FC_RX_PAUSE:
1766 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1768 case I40E_FC_TX_PAUSE:
1769 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1775 /* Get the current phy config */
1776 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1779 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1783 memset(&config, 0, sizeof(config));
1784 /* clear the old pause settings */
1785 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1786 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1787 /* set the new abilities */
1788 config.abilities |= pause_mask;
1789 /* If the abilities have changed, then set the new config */
1790 if (config.abilities != abilities.abilities) {
1791 /* Auto restart link so settings take effect */
1793 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1794 /* Copy over all the old settings */
1795 config.phy_type = abilities.phy_type;
1796 config.phy_type_ext = abilities.phy_type_ext;
1797 config.link_speed = abilities.link_speed;
1798 config.eee_capability = abilities.eee_capability;
1799 config.eeer = abilities.eeer_val;
1800 config.low_power_ctrl = abilities.d3_lpan;
1801 status = i40e_aq_set_phy_config(hw, &config, NULL);
1804 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1806 /* Update the link info */
1807 status = i40e_update_link_info(hw);
1809 /* Wait a little bit (on 40G cards it sometimes takes a really
1810 * long time for link to come back from the atomic reset)
1813 i40e_msec_delay(1000);
1814 status = i40e_update_link_info(hw);
1817 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1823 * i40e_aq_set_mac_config
1824 * @hw: pointer to the hw struct
1825 * @max_frame_size: Maximum Frame Size to be supported by the port
1826 * @crc_en: Tell HW to append a CRC to outgoing frames
1827 * @pacing: Pacing configurations
1828 * @cmd_details: pointer to command details structure or NULL
1830 * Configure MAC settings for frame size, jumbo frame support and the
1831 * addition of a CRC by the hardware.
1833 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1835 bool crc_en, u16 pacing,
1836 struct i40e_asq_cmd_details *cmd_details)
1838 struct i40e_aq_desc desc;
1839 struct i40e_aq_set_mac_config *cmd =
1840 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1841 enum i40e_status_code status;
1843 if (max_frame_size == 0)
1844 return I40E_ERR_PARAM;
1846 i40e_fill_default_direct_cmd_desc(&desc,
1847 i40e_aqc_opc_set_mac_config);
1849 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1850 cmd->params = ((u8)pacing & 0x0F) << 3;
1852 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1854 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1860 * i40e_aq_clear_pxe_mode
1861 * @hw: pointer to the hw struct
1862 * @cmd_details: pointer to command details structure or NULL
1864 * Tell the firmware that the driver is taking over from PXE
1866 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1867 struct i40e_asq_cmd_details *cmd_details)
1869 enum i40e_status_code status;
1870 struct i40e_aq_desc desc;
1871 struct i40e_aqc_clear_pxe *cmd =
1872 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1874 i40e_fill_default_direct_cmd_desc(&desc,
1875 i40e_aqc_opc_clear_pxe_mode);
1879 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1881 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1887 * i40e_aq_set_link_restart_an
1888 * @hw: pointer to the hw struct
1889 * @enable_link: if true: enable link, if false: disable link
1890 * @cmd_details: pointer to command details structure or NULL
1892 * Sets up the link and restarts the Auto-Negotiation over the link.
1894 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1895 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1897 struct i40e_aq_desc desc;
1898 struct i40e_aqc_set_link_restart_an *cmd =
1899 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1900 enum i40e_status_code status;
1902 i40e_fill_default_direct_cmd_desc(&desc,
1903 i40e_aqc_opc_set_link_restart_an);
1905 cmd->command = I40E_AQ_PHY_RESTART_AN;
1907 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1909 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1911 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1917 * i40e_aq_get_link_info
1918 * @hw: pointer to the hw struct
1919 * @enable_lse: enable/disable LinkStatusEvent reporting
1920 * @link: pointer to link status structure - optional
1921 * @cmd_details: pointer to command details structure or NULL
1923 * Returns the link status of the adapter.
1925 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1926 bool enable_lse, struct i40e_link_status *link,
1927 struct i40e_asq_cmd_details *cmd_details)
1929 struct i40e_aq_desc desc;
1930 struct i40e_aqc_get_link_status *resp =
1931 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1932 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1933 enum i40e_status_code status;
1934 bool tx_pause, rx_pause;
1937 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1940 command_flags = I40E_AQ_LSE_ENABLE;
1942 command_flags = I40E_AQ_LSE_DISABLE;
1943 resp->command_flags = CPU_TO_LE16(command_flags);
1945 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1947 if (status != I40E_SUCCESS)
1948 goto aq_get_link_info_exit;
1950 /* save off old link status information */
1951 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1952 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1954 /* update link status */
1955 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1956 hw->phy.media_type = i40e_get_media_type(hw);
1957 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1958 hw_link_info->link_info = resp->link_info;
1959 hw_link_info->an_info = resp->an_info;
1960 hw_link_info->ext_info = resp->ext_info;
1961 hw_link_info->loopback = resp->loopback;
1962 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1963 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1965 /* update fc info */
1966 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1967 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1968 if (tx_pause & rx_pause)
1969 hw->fc.current_mode = I40E_FC_FULL;
1971 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1973 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1975 hw->fc.current_mode = I40E_FC_NONE;
1977 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1978 hw_link_info->crc_enable = true;
1980 hw_link_info->crc_enable = false;
1982 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
1983 hw_link_info->lse_enable = true;
1985 hw_link_info->lse_enable = false;
1987 if ((hw->mac.type == I40E_MAC_XL710) &&
1988 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1989 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1990 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1992 /* save link status information */
1994 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1995 I40E_NONDMA_TO_NONDMA);
1997 /* flag cleared so helper functions don't call AQ again */
1998 hw->phy.get_link_info = false;
2000 aq_get_link_info_exit:
2005 * i40e_aq_set_phy_int_mask
2006 * @hw: pointer to the hw struct
2007 * @mask: interrupt mask to be set
2008 * @cmd_details: pointer to command details structure or NULL
2010 * Set link interrupt mask.
2012 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2014 struct i40e_asq_cmd_details *cmd_details)
2016 struct i40e_aq_desc desc;
2017 struct i40e_aqc_set_phy_int_mask *cmd =
2018 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2019 enum i40e_status_code status;
2021 i40e_fill_default_direct_cmd_desc(&desc,
2022 i40e_aqc_opc_set_phy_int_mask);
2024 cmd->event_mask = CPU_TO_LE16(mask);
2026 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2032 * i40e_aq_get_local_advt_reg
2033 * @hw: pointer to the hw struct
2034 * @advt_reg: local AN advertisement register value
2035 * @cmd_details: pointer to command details structure or NULL
2037 * Get the Local AN advertisement register value.
2039 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2041 struct i40e_asq_cmd_details *cmd_details)
2043 struct i40e_aq_desc desc;
2044 struct i40e_aqc_an_advt_reg *resp =
2045 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2046 enum i40e_status_code status;
2048 i40e_fill_default_direct_cmd_desc(&desc,
2049 i40e_aqc_opc_get_local_advt_reg);
2051 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2053 if (status != I40E_SUCCESS)
2054 goto aq_get_local_advt_reg_exit;
2056 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2057 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2059 aq_get_local_advt_reg_exit:
2064 * i40e_aq_set_local_advt_reg
2065 * @hw: pointer to the hw struct
2066 * @advt_reg: local AN advertisement register value
2067 * @cmd_details: pointer to command details structure or NULL
2069 * Get the Local AN advertisement register value.
2071 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2073 struct i40e_asq_cmd_details *cmd_details)
2075 struct i40e_aq_desc desc;
2076 struct i40e_aqc_an_advt_reg *cmd =
2077 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2078 enum i40e_status_code status;
2080 i40e_fill_default_direct_cmd_desc(&desc,
2081 i40e_aqc_opc_get_local_advt_reg);
2083 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2084 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2086 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2092 * i40e_aq_get_partner_advt
2093 * @hw: pointer to the hw struct
2094 * @advt_reg: AN partner advertisement register value
2095 * @cmd_details: pointer to command details structure or NULL
2097 * Get the link partner AN advertisement register value.
2099 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2101 struct i40e_asq_cmd_details *cmd_details)
2103 struct i40e_aq_desc desc;
2104 struct i40e_aqc_an_advt_reg *resp =
2105 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2106 enum i40e_status_code status;
2108 i40e_fill_default_direct_cmd_desc(&desc,
2109 i40e_aqc_opc_get_partner_advt);
2111 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2113 if (status != I40E_SUCCESS)
2114 goto aq_get_partner_advt_exit;
2116 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2117 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2119 aq_get_partner_advt_exit:
2124 * i40e_aq_set_lb_modes
2125 * @hw: pointer to the hw struct
2126 * @lb_modes: loopback mode to be set
2127 * @cmd_details: pointer to command details structure or NULL
2129 * Sets loopback modes.
2131 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2133 struct i40e_asq_cmd_details *cmd_details)
2135 struct i40e_aq_desc desc;
2136 struct i40e_aqc_set_lb_mode *cmd =
2137 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2138 enum i40e_status_code status;
2140 i40e_fill_default_direct_cmd_desc(&desc,
2141 i40e_aqc_opc_set_lb_modes);
2143 cmd->lb_mode = CPU_TO_LE16(lb_modes);
2145 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2151 * i40e_aq_set_phy_debug
2152 * @hw: pointer to the hw struct
2153 * @cmd_flags: debug command flags
2154 * @cmd_details: pointer to command details structure or NULL
2156 * Reset the external PHY.
2158 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2159 struct i40e_asq_cmd_details *cmd_details)
2161 struct i40e_aq_desc desc;
2162 struct i40e_aqc_set_phy_debug *cmd =
2163 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2164 enum i40e_status_code status;
2166 i40e_fill_default_direct_cmd_desc(&desc,
2167 i40e_aqc_opc_set_phy_debug);
2169 cmd->command_flags = cmd_flags;
2171 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2178 * @hw: pointer to the hw struct
2179 * @vsi_ctx: pointer to a vsi context struct
2180 * @cmd_details: pointer to command details structure or NULL
2182 * Add a VSI context to the hardware.
2184 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2185 struct i40e_vsi_context *vsi_ctx,
2186 struct i40e_asq_cmd_details *cmd_details)
2188 struct i40e_aq_desc desc;
2189 struct i40e_aqc_add_get_update_vsi *cmd =
2190 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2191 struct i40e_aqc_add_get_update_vsi_completion *resp =
2192 (struct i40e_aqc_add_get_update_vsi_completion *)
2194 enum i40e_status_code status;
2196 i40e_fill_default_direct_cmd_desc(&desc,
2197 i40e_aqc_opc_add_vsi);
2199 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2200 cmd->connection_type = vsi_ctx->connection_type;
2201 cmd->vf_id = vsi_ctx->vf_num;
2202 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2204 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2206 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2207 sizeof(vsi_ctx->info), cmd_details);
2209 if (status != I40E_SUCCESS)
2210 goto aq_add_vsi_exit;
2212 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2213 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2214 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2215 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2222 * i40e_aq_set_default_vsi
2223 * @hw: pointer to the hw struct
2225 * @cmd_details: pointer to command details structure or NULL
2227 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2229 struct i40e_asq_cmd_details *cmd_details)
2231 struct i40e_aq_desc desc;
2232 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2233 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2235 enum i40e_status_code status;
2237 i40e_fill_default_direct_cmd_desc(&desc,
2238 i40e_aqc_opc_set_vsi_promiscuous_modes);
2240 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2241 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2242 cmd->seid = CPU_TO_LE16(seid);
2244 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2250 * i40e_aq_clear_default_vsi
2251 * @hw: pointer to the hw struct
2253 * @cmd_details: pointer to command details structure or NULL
2255 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2257 struct i40e_asq_cmd_details *cmd_details)
2259 struct i40e_aq_desc desc;
2260 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2261 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2263 enum i40e_status_code status;
2265 i40e_fill_default_direct_cmd_desc(&desc,
2266 i40e_aqc_opc_set_vsi_promiscuous_modes);
2268 cmd->promiscuous_flags = CPU_TO_LE16(0);
2269 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2270 cmd->seid = CPU_TO_LE16(seid);
2272 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2278 * i40e_aq_set_vsi_unicast_promiscuous
2279 * @hw: pointer to the hw struct
2281 * @set: set unicast promiscuous enable/disable
2282 * @cmd_details: pointer to command details structure or NULL
2283 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2285 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2287 struct i40e_asq_cmd_details *cmd_details,
2288 bool rx_only_promisc)
2290 struct i40e_aq_desc desc;
2291 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2292 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2293 enum i40e_status_code status;
2296 i40e_fill_default_direct_cmd_desc(&desc,
2297 i40e_aqc_opc_set_vsi_promiscuous_modes);
2300 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2301 if (rx_only_promisc &&
2302 (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2303 (hw->aq.api_maj_ver > 1)))
2304 flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2307 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2309 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2310 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2311 (hw->aq.api_maj_ver > 1))
2312 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2314 cmd->seid = CPU_TO_LE16(seid);
2315 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2321 * i40e_aq_set_vsi_multicast_promiscuous
2322 * @hw: pointer to the hw struct
2324 * @set: set multicast promiscuous enable/disable
2325 * @cmd_details: pointer to command details structure or NULL
2327 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2328 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2330 struct i40e_aq_desc desc;
2331 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2332 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2333 enum i40e_status_code status;
2336 i40e_fill_default_direct_cmd_desc(&desc,
2337 i40e_aqc_opc_set_vsi_promiscuous_modes);
2340 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2342 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2344 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2346 cmd->seid = CPU_TO_LE16(seid);
2347 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2353 * i40e_aq_set_vsi_mc_promisc_on_vlan
2354 * @hw: pointer to the hw struct
2356 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2357 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2358 * @cmd_details: pointer to command details structure or NULL
2360 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2361 u16 seid, bool enable, u16 vid,
2362 struct i40e_asq_cmd_details *cmd_details)
2364 struct i40e_aq_desc desc;
2365 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2366 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2367 enum i40e_status_code status;
2370 i40e_fill_default_direct_cmd_desc(&desc,
2371 i40e_aqc_opc_set_vsi_promiscuous_modes);
2374 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2376 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2377 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2378 cmd->seid = CPU_TO_LE16(seid);
2379 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2381 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2387 * i40e_aq_set_vsi_uc_promisc_on_vlan
2388 * @hw: pointer to the hw struct
2390 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2391 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2392 * @cmd_details: pointer to command details structure or NULL
2394 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2395 u16 seid, bool enable, u16 vid,
2396 struct i40e_asq_cmd_details *cmd_details)
2398 struct i40e_aq_desc desc;
2399 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2400 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2401 enum i40e_status_code status;
2404 i40e_fill_default_direct_cmd_desc(&desc,
2405 i40e_aqc_opc_set_vsi_promiscuous_modes);
2408 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2410 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2411 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2412 cmd->seid = CPU_TO_LE16(seid);
2413 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2415 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2421 * i40e_aq_set_vsi_broadcast
2422 * @hw: pointer to the hw struct
2424 * @set_filter: true to set filter, false to clear filter
2425 * @cmd_details: pointer to command details structure or NULL
2427 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2429 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2430 u16 seid, bool set_filter,
2431 struct i40e_asq_cmd_details *cmd_details)
2433 struct i40e_aq_desc desc;
2434 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2435 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2436 enum i40e_status_code status;
2438 i40e_fill_default_direct_cmd_desc(&desc,
2439 i40e_aqc_opc_set_vsi_promiscuous_modes);
2442 cmd->promiscuous_flags
2443 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2445 cmd->promiscuous_flags
2446 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2448 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2449 cmd->seid = CPU_TO_LE16(seid);
2450 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2456 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2457 * @hw: pointer to the hw struct
2459 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2460 * @cmd_details: pointer to command details structure or NULL
2462 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2463 u16 seid, bool enable,
2464 struct i40e_asq_cmd_details *cmd_details)
2466 struct i40e_aq_desc desc;
2467 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2468 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2469 enum i40e_status_code status;
2472 i40e_fill_default_direct_cmd_desc(&desc,
2473 i40e_aqc_opc_set_vsi_promiscuous_modes);
2475 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2477 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2478 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2479 cmd->seid = CPU_TO_LE16(seid);
2481 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2487 * i40e_get_vsi_params - get VSI configuration info
2488 * @hw: pointer to the hw struct
2489 * @vsi_ctx: pointer to a vsi context struct
2490 * @cmd_details: pointer to command details structure or NULL
2492 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2493 struct i40e_vsi_context *vsi_ctx,
2494 struct i40e_asq_cmd_details *cmd_details)
2496 struct i40e_aq_desc desc;
2497 struct i40e_aqc_add_get_update_vsi *cmd =
2498 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2499 struct i40e_aqc_add_get_update_vsi_completion *resp =
2500 (struct i40e_aqc_add_get_update_vsi_completion *)
2502 enum i40e_status_code status;
2504 UNREFERENCED_1PARAMETER(cmd_details);
2505 i40e_fill_default_direct_cmd_desc(&desc,
2506 i40e_aqc_opc_get_vsi_parameters);
2508 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2510 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2512 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2513 sizeof(vsi_ctx->info), NULL);
2515 if (status != I40E_SUCCESS)
2516 goto aq_get_vsi_params_exit;
2518 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2519 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2520 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2521 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2523 aq_get_vsi_params_exit:
2528 * i40e_aq_update_vsi_params
2529 * @hw: pointer to the hw struct
2530 * @vsi_ctx: pointer to a vsi context struct
2531 * @cmd_details: pointer to command details structure or NULL
2533 * Update a VSI context.
2535 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2536 struct i40e_vsi_context *vsi_ctx,
2537 struct i40e_asq_cmd_details *cmd_details)
2539 struct i40e_aq_desc desc;
2540 struct i40e_aqc_add_get_update_vsi *cmd =
2541 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2542 struct i40e_aqc_add_get_update_vsi_completion *resp =
2543 (struct i40e_aqc_add_get_update_vsi_completion *)
2545 enum i40e_status_code status;
2547 i40e_fill_default_direct_cmd_desc(&desc,
2548 i40e_aqc_opc_update_vsi_parameters);
2549 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2551 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2553 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2554 sizeof(vsi_ctx->info), cmd_details);
2556 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2557 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2563 * i40e_aq_get_switch_config
2564 * @hw: pointer to the hardware structure
2565 * @buf: pointer to the result buffer
2566 * @buf_size: length of input buffer
2567 * @start_seid: seid to start for the report, 0 == beginning
2568 * @cmd_details: pointer to command details structure or NULL
2570 * Fill the buf with switch configuration returned from AdminQ command
2572 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2573 struct i40e_aqc_get_switch_config_resp *buf,
2574 u16 buf_size, u16 *start_seid,
2575 struct i40e_asq_cmd_details *cmd_details)
2577 struct i40e_aq_desc desc;
2578 struct i40e_aqc_switch_seid *scfg =
2579 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2580 enum i40e_status_code status;
2582 i40e_fill_default_direct_cmd_desc(&desc,
2583 i40e_aqc_opc_get_switch_config);
2584 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2585 if (buf_size > I40E_AQ_LARGE_BUF)
2586 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2587 scfg->seid = CPU_TO_LE16(*start_seid);
2589 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2590 *start_seid = LE16_TO_CPU(scfg->seid);
2596 * i40e_aq_set_switch_config
2597 * @hw: pointer to the hardware structure
2598 * @flags: bit flag values to set
2599 * @valid_flags: which bit flags to set
2600 * @cmd_details: pointer to command details structure or NULL
2602 * Set switch configuration bits
2604 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2605 u16 flags, u16 valid_flags,
2606 struct i40e_asq_cmd_details *cmd_details)
2608 struct i40e_aq_desc desc;
2609 struct i40e_aqc_set_switch_config *scfg =
2610 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2611 enum i40e_status_code status;
2613 i40e_fill_default_direct_cmd_desc(&desc,
2614 i40e_aqc_opc_set_switch_config);
2615 scfg->flags = CPU_TO_LE16(flags);
2616 scfg->valid_flags = CPU_TO_LE16(valid_flags);
2618 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2624 * i40e_aq_get_firmware_version
2625 * @hw: pointer to the hw struct
2626 * @fw_major_version: firmware major version
2627 * @fw_minor_version: firmware minor version
2628 * @fw_build: firmware build number
2629 * @api_major_version: major queue version
2630 * @api_minor_version: minor queue version
2631 * @cmd_details: pointer to command details structure or NULL
2633 * Get the firmware version from the admin queue commands
2635 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2636 u16 *fw_major_version, u16 *fw_minor_version,
2638 u16 *api_major_version, u16 *api_minor_version,
2639 struct i40e_asq_cmd_details *cmd_details)
2641 struct i40e_aq_desc desc;
2642 struct i40e_aqc_get_version *resp =
2643 (struct i40e_aqc_get_version *)&desc.params.raw;
2644 enum i40e_status_code status;
2646 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2648 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2650 if (status == I40E_SUCCESS) {
2651 if (fw_major_version != NULL)
2652 *fw_major_version = LE16_TO_CPU(resp->fw_major);
2653 if (fw_minor_version != NULL)
2654 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2655 if (fw_build != NULL)
2656 *fw_build = LE32_TO_CPU(resp->fw_build);
2657 if (api_major_version != NULL)
2658 *api_major_version = LE16_TO_CPU(resp->api_major);
2659 if (api_minor_version != NULL)
2660 *api_minor_version = LE16_TO_CPU(resp->api_minor);
2662 /* A workaround to fix the API version in SW */
2663 if (api_major_version && api_minor_version &&
2664 fw_major_version && fw_minor_version &&
2665 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2666 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2667 (*fw_major_version > 4)))
2668 *api_minor_version = 2;
2675 * i40e_aq_send_driver_version
2676 * @hw: pointer to the hw struct
2677 * @dv: driver's major, minor version
2678 * @cmd_details: pointer to command details structure or NULL
2680 * Send the driver version to the firmware
2682 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2683 struct i40e_driver_version *dv,
2684 struct i40e_asq_cmd_details *cmd_details)
2686 struct i40e_aq_desc desc;
2687 struct i40e_aqc_driver_version *cmd =
2688 (struct i40e_aqc_driver_version *)&desc.params.raw;
2689 enum i40e_status_code status;
2693 return I40E_ERR_PARAM;
2695 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2697 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2698 cmd->driver_major_ver = dv->major_version;
2699 cmd->driver_minor_ver = dv->minor_version;
2700 cmd->driver_build_ver = dv->build_version;
2701 cmd->driver_subbuild_ver = dv->subbuild_version;
2704 while (len < sizeof(dv->driver_string) &&
2705 (dv->driver_string[len] < 0x80) &&
2706 dv->driver_string[len])
2708 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2715 * i40e_get_link_status - get status of the HW network link
2716 * @hw: pointer to the hw struct
2717 * @link_up: pointer to bool (true/false = linkup/linkdown)
2719 * Variable link_up true if link is up, false if link is down.
2720 * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2722 * Side effect: LinkStatusEvent reporting becomes enabled
2724 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2726 enum i40e_status_code status = I40E_SUCCESS;
2728 if (hw->phy.get_link_info) {
2729 status = i40e_update_link_info(hw);
2731 if (status != I40E_SUCCESS)
2732 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2736 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2742 * i40e_updatelink_status - update status of the HW network link
2743 * @hw: pointer to the hw struct
2745 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2747 struct i40e_aq_get_phy_abilities_resp abilities;
2748 enum i40e_status_code status = I40E_SUCCESS;
2750 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2754 /* extra checking needed to ensure link info to user is timely */
2755 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2756 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2757 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2758 status = i40e_aq_get_phy_capabilities(hw, false, false,
2763 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2764 sizeof(hw->phy.link_info.module_type));
2771 * i40e_get_link_speed
2772 * @hw: pointer to the hw struct
2774 * Returns the link speed of the adapter.
2776 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2778 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2779 enum i40e_status_code status = I40E_SUCCESS;
2781 if (hw->phy.get_link_info) {
2782 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2784 if (status != I40E_SUCCESS)
2785 goto i40e_link_speed_exit;
2788 speed = hw->phy.link_info.link_speed;
2790 i40e_link_speed_exit:
2795 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2796 * @hw: pointer to the hw struct
2797 * @uplink_seid: the MAC or other gizmo SEID
2798 * @downlink_seid: the VSI SEID
2799 * @enabled_tc: bitmap of TCs to be enabled
2800 * @default_port: true for default port VSI, false for control port
2801 * @veb_seid: pointer to where to put the resulting VEB SEID
2802 * @enable_stats: true to turn on VEB stats
2803 * @cmd_details: pointer to command details structure or NULL
2805 * This asks the FW to add a VEB between the uplink and downlink
2806 * elements. If the uplink SEID is 0, this will be a floating VEB.
2808 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2809 u16 downlink_seid, u8 enabled_tc,
2810 bool default_port, u16 *veb_seid,
2812 struct i40e_asq_cmd_details *cmd_details)
2814 struct i40e_aq_desc desc;
2815 struct i40e_aqc_add_veb *cmd =
2816 (struct i40e_aqc_add_veb *)&desc.params.raw;
2817 struct i40e_aqc_add_veb_completion *resp =
2818 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2819 enum i40e_status_code status;
2822 /* SEIDs need to either both be set or both be 0 for floating VEB */
2823 if (!!uplink_seid != !!downlink_seid)
2824 return I40E_ERR_PARAM;
2826 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2828 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2829 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2830 cmd->enable_tcs = enabled_tc;
2832 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2834 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2836 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2838 /* reverse logic here: set the bitflag to disable the stats */
2840 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2842 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2844 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2846 if (!status && veb_seid)
2847 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2853 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2854 * @hw: pointer to the hw struct
2855 * @veb_seid: the SEID of the VEB to query
2856 * @switch_id: the uplink switch id
2857 * @floating: set to true if the VEB is floating
2858 * @statistic_index: index of the stats counter block for this VEB
2859 * @vebs_used: number of VEB's used by function
2860 * @vebs_free: total VEB's not reserved by any function
2861 * @cmd_details: pointer to command details structure or NULL
2863 * This retrieves the parameters for a particular VEB, specified by
2864 * uplink_seid, and returns them to the caller.
2866 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2867 u16 veb_seid, u16 *switch_id,
2868 bool *floating, u16 *statistic_index,
2869 u16 *vebs_used, u16 *vebs_free,
2870 struct i40e_asq_cmd_details *cmd_details)
2872 struct i40e_aq_desc desc;
2873 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2874 (struct i40e_aqc_get_veb_parameters_completion *)
2876 enum i40e_status_code status;
2879 return I40E_ERR_PARAM;
2881 i40e_fill_default_direct_cmd_desc(&desc,
2882 i40e_aqc_opc_get_veb_parameters);
2883 cmd_resp->seid = CPU_TO_LE16(veb_seid);
2885 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2890 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2891 if (statistic_index)
2892 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2894 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2896 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2898 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2900 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2911 * i40e_aq_add_macvlan
2912 * @hw: pointer to the hw struct
2913 * @seid: VSI for the mac address
2914 * @mv_list: list of macvlans to be added
2915 * @count: length of the list
2916 * @cmd_details: pointer to command details structure or NULL
2918 * Add MAC/VLAN addresses to the HW filtering
2920 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2921 struct i40e_aqc_add_macvlan_element_data *mv_list,
2922 u16 count, struct i40e_asq_cmd_details *cmd_details)
2924 struct i40e_aq_desc desc;
2925 struct i40e_aqc_macvlan *cmd =
2926 (struct i40e_aqc_macvlan *)&desc.params.raw;
2927 enum i40e_status_code status;
2931 if (count == 0 || !mv_list || !hw)
2932 return I40E_ERR_PARAM;
2934 buf_size = count * sizeof(*mv_list);
2936 /* prep the rest of the request */
2937 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2938 cmd->num_addresses = CPU_TO_LE16(count);
2939 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2943 for (i = 0; i < count; i++)
2944 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
2946 CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2948 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2949 if (buf_size > I40E_AQ_LARGE_BUF)
2950 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2952 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2959 * i40e_aq_remove_macvlan
2960 * @hw: pointer to the hw struct
2961 * @seid: VSI for the mac address
2962 * @mv_list: list of macvlans to be removed
2963 * @count: length of the list
2964 * @cmd_details: pointer to command details structure or NULL
2966 * Remove MAC/VLAN addresses from the HW filtering
2968 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2969 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2970 u16 count, struct i40e_asq_cmd_details *cmd_details)
2972 struct i40e_aq_desc desc;
2973 struct i40e_aqc_macvlan *cmd =
2974 (struct i40e_aqc_macvlan *)&desc.params.raw;
2975 enum i40e_status_code status;
2978 if (count == 0 || !mv_list || !hw)
2979 return I40E_ERR_PARAM;
2981 buf_size = count * sizeof(*mv_list);
2983 /* prep the rest of the request */
2984 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2985 cmd->num_addresses = CPU_TO_LE16(count);
2986 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2990 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2991 if (buf_size > I40E_AQ_LARGE_BUF)
2992 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2994 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3001 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3002 * @hw: pointer to the hw struct
3003 * @opcode: AQ opcode for add or delete mirror rule
3004 * @sw_seid: Switch SEID (to which rule refers)
3005 * @rule_type: Rule Type (ingress/egress/VLAN)
3006 * @id: Destination VSI SEID or Rule ID
3007 * @count: length of the list
3008 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3009 * @cmd_details: pointer to command details structure or NULL
3010 * @rule_id: Rule ID returned from FW
3011 * @rule_used: Number of rules used in internal switch
3012 * @rule_free: Number of rules free in internal switch
3014 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3015 * VEBs/VEPA elements only
3017 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3018 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3019 u16 count, __le16 *mr_list,
3020 struct i40e_asq_cmd_details *cmd_details,
3021 u16 *rule_id, u16 *rules_used, u16 *rules_free)
3023 struct i40e_aq_desc desc;
3024 struct i40e_aqc_add_delete_mirror_rule *cmd =
3025 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3026 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3027 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3028 enum i40e_status_code status;
3031 buf_size = count * sizeof(*mr_list);
3033 /* prep the rest of the request */
3034 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3035 cmd->seid = CPU_TO_LE16(sw_seid);
3036 cmd->rule_type = CPU_TO_LE16(rule_type &
3037 I40E_AQC_MIRROR_RULE_TYPE_MASK);
3038 cmd->num_entries = CPU_TO_LE16(count);
3039 /* Dest VSI for add, rule_id for delete */
3040 cmd->destination = CPU_TO_LE16(id);
3042 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3044 if (buf_size > I40E_AQ_LARGE_BUF)
3045 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3048 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3050 if (status == I40E_SUCCESS ||
3051 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3053 *rule_id = LE16_TO_CPU(resp->rule_id);
3055 *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3057 *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3063 * i40e_aq_add_mirrorrule - add a mirror rule
3064 * @hw: pointer to the hw struct
3065 * @sw_seid: Switch SEID (to which rule refers)
3066 * @rule_type: Rule Type (ingress/egress/VLAN)
3067 * @dest_vsi: SEID of VSI to which packets will be mirrored
3068 * @count: length of the list
3069 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3070 * @cmd_details: pointer to command details structure or NULL
3071 * @rule_id: Rule ID returned from FW
3072 * @rule_used: Number of rules used in internal switch
3073 * @rule_free: Number of rules free in internal switch
3075 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3077 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3078 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3079 struct i40e_asq_cmd_details *cmd_details,
3080 u16 *rule_id, u16 *rules_used, u16 *rules_free)
3082 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3083 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3084 if (count == 0 || !mr_list)
3085 return I40E_ERR_PARAM;
3088 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3089 rule_type, dest_vsi, count, mr_list,
3090 cmd_details, rule_id, rules_used, rules_free);
3094 * i40e_aq_delete_mirrorrule - delete a mirror rule
3095 * @hw: pointer to the hw struct
3096 * @sw_seid: Switch SEID (to which rule refers)
3097 * @rule_type: Rule Type (ingress/egress/VLAN)
3098 * @count: length of the list
3099 * @rule_id: Rule ID that is returned in the receive desc as part of
3101 * @mr_list: list of mirrored VLAN IDs to be removed
3102 * @cmd_details: pointer to command details structure or NULL
3103 * @rule_used: Number of rules used in internal switch
3104 * @rule_free: Number of rules free in internal switch
3106 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3108 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3109 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3110 struct i40e_asq_cmd_details *cmd_details,
3111 u16 *rules_used, u16 *rules_free)
3113 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3114 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3115 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3116 * mirroring. For other rule_type, count and rule_type should
3119 if (count == 0 || !mr_list)
3120 return I40E_ERR_PARAM;
3123 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3124 rule_type, rule_id, count, mr_list,
3125 cmd_details, NULL, rules_used, rules_free);
3129 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3130 * @hw: pointer to the hw struct
3131 * @seid: VSI for the vlan filters
3132 * @v_list: list of vlan filters to be added
3133 * @count: length of the list
3134 * @cmd_details: pointer to command details structure or NULL
3136 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3137 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3138 u8 count, struct i40e_asq_cmd_details *cmd_details)
3140 struct i40e_aq_desc desc;
3141 struct i40e_aqc_macvlan *cmd =
3142 (struct i40e_aqc_macvlan *)&desc.params.raw;
3143 enum i40e_status_code status;
3146 if (count == 0 || !v_list || !hw)
3147 return I40E_ERR_PARAM;
3149 buf_size = count * sizeof(*v_list);
3151 /* prep the rest of the request */
3152 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3153 cmd->num_addresses = CPU_TO_LE16(count);
3154 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3158 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3159 if (buf_size > I40E_AQ_LARGE_BUF)
3160 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3162 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3169 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3170 * @hw: pointer to the hw struct
3171 * @seid: VSI for the vlan filters
3172 * @v_list: list of macvlans to be removed
3173 * @count: length of the list
3174 * @cmd_details: pointer to command details structure or NULL
3176 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3177 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3178 u8 count, struct i40e_asq_cmd_details *cmd_details)
3180 struct i40e_aq_desc desc;
3181 struct i40e_aqc_macvlan *cmd =
3182 (struct i40e_aqc_macvlan *)&desc.params.raw;
3183 enum i40e_status_code status;
3186 if (count == 0 || !v_list || !hw)
3187 return I40E_ERR_PARAM;
3189 buf_size = count * sizeof(*v_list);
3191 /* prep the rest of the request */
3192 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3193 cmd->num_addresses = CPU_TO_LE16(count);
3194 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3198 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3199 if (buf_size > I40E_AQ_LARGE_BUF)
3200 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3202 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3209 * i40e_aq_send_msg_to_vf
3210 * @hw: pointer to the hardware structure
3211 * @vfid: vf id to send msg
3212 * @v_opcode: opcodes for VF-PF communication
3213 * @v_retval: return error code
3214 * @msg: pointer to the msg buffer
3215 * @msglen: msg length
3216 * @cmd_details: pointer to command details
3220 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3221 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3222 struct i40e_asq_cmd_details *cmd_details)
3224 struct i40e_aq_desc desc;
3225 struct i40e_aqc_pf_vf_message *cmd =
3226 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3227 enum i40e_status_code status;
3229 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3230 cmd->id = CPU_TO_LE32(vfid);
3231 desc.cookie_high = CPU_TO_LE32(v_opcode);
3232 desc.cookie_low = CPU_TO_LE32(v_retval);
3233 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3235 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3237 if (msglen > I40E_AQ_LARGE_BUF)
3238 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3239 desc.datalen = CPU_TO_LE16(msglen);
3241 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3247 * i40e_aq_debug_read_register
3248 * @hw: pointer to the hw struct
3249 * @reg_addr: register address
3250 * @reg_val: register value
3251 * @cmd_details: pointer to command details structure or NULL
3253 * Read the register using the admin queue commands
3255 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3256 u32 reg_addr, u64 *reg_val,
3257 struct i40e_asq_cmd_details *cmd_details)
3259 struct i40e_aq_desc desc;
3260 struct i40e_aqc_debug_reg_read_write *cmd_resp =
3261 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3262 enum i40e_status_code status;
3264 if (reg_val == NULL)
3265 return I40E_ERR_PARAM;
3267 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3269 cmd_resp->address = CPU_TO_LE32(reg_addr);
3271 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3273 if (status == I40E_SUCCESS) {
3274 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3275 (u64)LE32_TO_CPU(cmd_resp->value_low);
3282 * i40e_aq_debug_write_register
3283 * @hw: pointer to the hw struct
3284 * @reg_addr: register address
3285 * @reg_val: register value
3286 * @cmd_details: pointer to command details structure or NULL
3288 * Write to a register using the admin queue commands
3290 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3291 u32 reg_addr, u64 reg_val,
3292 struct i40e_asq_cmd_details *cmd_details)
3294 struct i40e_aq_desc desc;
3295 struct i40e_aqc_debug_reg_read_write *cmd =
3296 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3297 enum i40e_status_code status;
3299 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3301 cmd->address = CPU_TO_LE32(reg_addr);
3302 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3303 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3305 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3311 * i40e_aq_request_resource
3312 * @hw: pointer to the hw struct
3313 * @resource: resource id
3314 * @access: access type
3315 * @sdp_number: resource number
3316 * @timeout: the maximum time in ms that the driver may hold the resource
3317 * @cmd_details: pointer to command details structure or NULL
3319 * requests common resource using the admin queue commands
3321 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3322 enum i40e_aq_resources_ids resource,
3323 enum i40e_aq_resource_access_type access,
3324 u8 sdp_number, u64 *timeout,
3325 struct i40e_asq_cmd_details *cmd_details)
3327 struct i40e_aq_desc desc;
3328 struct i40e_aqc_request_resource *cmd_resp =
3329 (struct i40e_aqc_request_resource *)&desc.params.raw;
3330 enum i40e_status_code status;
3332 DEBUGFUNC("i40e_aq_request_resource");
3334 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3336 cmd_resp->resource_id = CPU_TO_LE16(resource);
3337 cmd_resp->access_type = CPU_TO_LE16(access);
3338 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3340 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3341 /* The completion specifies the maximum time in ms that the driver
3342 * may hold the resource in the Timeout field.
3343 * If the resource is held by someone else, the command completes with
3344 * busy return value and the timeout field indicates the maximum time
3345 * the current owner of the resource has to free it.
3347 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3348 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3354 * i40e_aq_release_resource
3355 * @hw: pointer to the hw struct
3356 * @resource: resource id
3357 * @sdp_number: resource number
3358 * @cmd_details: pointer to command details structure or NULL
3360 * release common resource using the admin queue commands
3362 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3363 enum i40e_aq_resources_ids resource,
3365 struct i40e_asq_cmd_details *cmd_details)
3367 struct i40e_aq_desc desc;
3368 struct i40e_aqc_request_resource *cmd =
3369 (struct i40e_aqc_request_resource *)&desc.params.raw;
3370 enum i40e_status_code status;
3372 DEBUGFUNC("i40e_aq_release_resource");
3374 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3376 cmd->resource_id = CPU_TO_LE16(resource);
3377 cmd->resource_number = CPU_TO_LE32(sdp_number);
3379 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3386 * @hw: pointer to the hw struct
3387 * @module_pointer: module pointer location in words from the NVM beginning
3388 * @offset: byte offset from the module beginning
3389 * @length: length of the section to be read (in bytes from the offset)
3390 * @data: command buffer (size [bytes] = length)
3391 * @last_command: tells if this is the last command in a series
3392 * @cmd_details: pointer to command details structure or NULL
3394 * Read the NVM using the admin queue commands
3396 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3397 u32 offset, u16 length, void *data,
3399 struct i40e_asq_cmd_details *cmd_details)
3401 struct i40e_aq_desc desc;
3402 struct i40e_aqc_nvm_update *cmd =
3403 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3404 enum i40e_status_code status;
3406 DEBUGFUNC("i40e_aq_read_nvm");
3408 /* In offset the highest byte must be zeroed. */
3409 if (offset & 0xFF000000) {
3410 status = I40E_ERR_PARAM;
3411 goto i40e_aq_read_nvm_exit;
3414 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3416 /* If this is the last command in a series, set the proper flag. */
3418 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3419 cmd->module_pointer = module_pointer;
3420 cmd->offset = CPU_TO_LE32(offset);
3421 cmd->length = CPU_TO_LE16(length);
3423 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3424 if (length > I40E_AQ_LARGE_BUF)
3425 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3427 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3429 i40e_aq_read_nvm_exit:
3434 * i40e_aq_read_nvm_config - read an nvm config block
3435 * @hw: pointer to the hw struct
3436 * @cmd_flags: NVM access admin command bits
3437 * @field_id: field or feature id
3438 * @data: buffer for result
3439 * @buf_size: buffer size
3440 * @element_count: pointer to count of elements read by FW
3441 * @cmd_details: pointer to command details structure or NULL
3443 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3444 u8 cmd_flags, u32 field_id, void *data,
3445 u16 buf_size, u16 *element_count,
3446 struct i40e_asq_cmd_details *cmd_details)
3448 struct i40e_aq_desc desc;
3449 struct i40e_aqc_nvm_config_read *cmd =
3450 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3451 enum i40e_status_code status;
3453 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3454 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3455 if (buf_size > I40E_AQ_LARGE_BUF)
3456 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3458 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3459 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3460 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3461 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3463 cmd->element_id_msw = 0;
3465 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3467 if (!status && element_count)
3468 *element_count = LE16_TO_CPU(cmd->element_count);
3474 * i40e_aq_write_nvm_config - write an nvm config block
3475 * @hw: pointer to the hw struct
3476 * @cmd_flags: NVM access admin command bits
3477 * @data: buffer for result
3478 * @buf_size: buffer size
3479 * @element_count: count of elements to be written
3480 * @cmd_details: pointer to command details structure or NULL
3482 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3483 u8 cmd_flags, void *data, u16 buf_size,
3485 struct i40e_asq_cmd_details *cmd_details)
3487 struct i40e_aq_desc desc;
3488 struct i40e_aqc_nvm_config_write *cmd =
3489 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3490 enum i40e_status_code status;
3492 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3493 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3494 if (buf_size > I40E_AQ_LARGE_BUF)
3495 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3497 cmd->element_count = CPU_TO_LE16(element_count);
3498 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3499 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3505 * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3506 * @hw: pointer to the hw struct
3507 * @cmd_details: pointer to command details structure or NULL
3509 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3510 void *buff, u16 buff_size,
3511 struct i40e_asq_cmd_details *cmd_details)
3513 struct i40e_aq_desc desc;
3514 enum i40e_status_code status;
3516 UNREFERENCED_2PARAMETER(buff, buff_size);
3518 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3519 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3520 if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3521 status = I40E_ERR_NOT_IMPLEMENTED;
3528 * @hw: pointer to the hw struct
3529 * @module_pointer: module pointer location in words from the NVM beginning
3530 * @offset: offset in the module (expressed in 4 KB from module's beginning)
3531 * @length: length of the section to be erased (expressed in 4 KB)
3532 * @last_command: tells if this is the last command in a series
3533 * @cmd_details: pointer to command details structure or NULL
3535 * Erase the NVM sector using the admin queue commands
3537 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3538 u32 offset, u16 length, bool last_command,
3539 struct i40e_asq_cmd_details *cmd_details)
3541 struct i40e_aq_desc desc;
3542 struct i40e_aqc_nvm_update *cmd =
3543 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3544 enum i40e_status_code status;
3546 DEBUGFUNC("i40e_aq_erase_nvm");
3548 /* In offset the highest byte must be zeroed. */
3549 if (offset & 0xFF000000) {
3550 status = I40E_ERR_PARAM;
3551 goto i40e_aq_erase_nvm_exit;
3554 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3556 /* If this is the last command in a series, set the proper flag. */
3558 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3559 cmd->module_pointer = module_pointer;
3560 cmd->offset = CPU_TO_LE32(offset);
3561 cmd->length = CPU_TO_LE16(length);
3563 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3565 i40e_aq_erase_nvm_exit:
3570 * i40e_parse_discover_capabilities
3571 * @hw: pointer to the hw struct
3572 * @buff: pointer to a buffer containing device/function capability records
3573 * @cap_count: number of capability records in the list
3574 * @list_type_opc: type of capabilities list to parse
3576 * Parse the device/function capabilities list.
3578 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3580 enum i40e_admin_queue_opc list_type_opc)
3582 struct i40e_aqc_list_capabilities_element_resp *cap;
3583 u32 valid_functions, num_functions;
3584 u32 number, logical_id, phys_id;
3585 struct i40e_hw_capabilities *p;
3590 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3592 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3593 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3594 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3595 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3599 for (i = 0; i < cap_count; i++, cap++) {
3600 id = LE16_TO_CPU(cap->id);
3601 number = LE32_TO_CPU(cap->number);
3602 logical_id = LE32_TO_CPU(cap->logical_id);
3603 phys_id = LE32_TO_CPU(cap->phys_id);
3604 major_rev = cap->major_rev;
3607 case I40E_AQ_CAP_ID_SWITCH_MODE:
3608 p->switch_mode = number;
3609 i40e_debug(hw, I40E_DEBUG_INIT,
3610 "HW Capability: Switch mode = %d\n",
3613 case I40E_AQ_CAP_ID_MNG_MODE:
3614 p->management_mode = number;
3615 if (major_rev > 1) {
3616 p->mng_protocols_over_mctp = logical_id;
3617 i40e_debug(hw, I40E_DEBUG_INIT,
3618 "HW Capability: Protocols over MCTP = %d\n",
3619 p->mng_protocols_over_mctp);
3621 p->mng_protocols_over_mctp = 0;
3623 i40e_debug(hw, I40E_DEBUG_INIT,
3624 "HW Capability: Management Mode = %d\n",
3625 p->management_mode);
3627 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3628 p->npar_enable = number;
3629 i40e_debug(hw, I40E_DEBUG_INIT,
3630 "HW Capability: NPAR enable = %d\n",
3633 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3635 i40e_debug(hw, I40E_DEBUG_INIT,
3636 "HW Capability: OS2BMC = %d\n", p->os2bmc);
3638 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3639 p->valid_functions = number;
3640 i40e_debug(hw, I40E_DEBUG_INIT,
3641 "HW Capability: Valid Functions = %d\n",
3642 p->valid_functions);
3644 case I40E_AQ_CAP_ID_SRIOV:
3646 p->sr_iov_1_1 = true;
3647 i40e_debug(hw, I40E_DEBUG_INIT,
3648 "HW Capability: SR-IOV = %d\n",
3651 case I40E_AQ_CAP_ID_VF:
3652 p->num_vfs = number;
3653 p->vf_base_id = logical_id;
3654 i40e_debug(hw, I40E_DEBUG_INIT,
3655 "HW Capability: VF count = %d\n",
3657 i40e_debug(hw, I40E_DEBUG_INIT,
3658 "HW Capability: VF base_id = %d\n",
3661 case I40E_AQ_CAP_ID_VMDQ:
3664 i40e_debug(hw, I40E_DEBUG_INIT,
3665 "HW Capability: VMDQ = %d\n", p->vmdq);
3667 case I40E_AQ_CAP_ID_8021QBG:
3669 p->evb_802_1_qbg = true;
3670 i40e_debug(hw, I40E_DEBUG_INIT,
3671 "HW Capability: 802.1Qbg = %d\n", number);
3673 case I40E_AQ_CAP_ID_8021QBR:
3675 p->evb_802_1_qbh = true;
3676 i40e_debug(hw, I40E_DEBUG_INIT,
3677 "HW Capability: 802.1Qbh = %d\n", number);
3679 case I40E_AQ_CAP_ID_VSI:
3680 p->num_vsis = number;
3681 i40e_debug(hw, I40E_DEBUG_INIT,
3682 "HW Capability: VSI count = %d\n",
3685 case I40E_AQ_CAP_ID_DCB:
3688 p->enabled_tcmap = logical_id;
3691 i40e_debug(hw, I40E_DEBUG_INIT,
3692 "HW Capability: DCB = %d\n", p->dcb);
3693 i40e_debug(hw, I40E_DEBUG_INIT,
3694 "HW Capability: TC Mapping = %d\n",
3696 i40e_debug(hw, I40E_DEBUG_INIT,
3697 "HW Capability: TC Max = %d\n", p->maxtc);
3699 case I40E_AQ_CAP_ID_FCOE:
3702 i40e_debug(hw, I40E_DEBUG_INIT,
3703 "HW Capability: FCOE = %d\n", p->fcoe);
3705 case I40E_AQ_CAP_ID_ISCSI:
3708 i40e_debug(hw, I40E_DEBUG_INIT,
3709 "HW Capability: iSCSI = %d\n", p->iscsi);
3711 case I40E_AQ_CAP_ID_RSS:
3713 p->rss_table_size = number;
3714 p->rss_table_entry_width = logical_id;
3715 i40e_debug(hw, I40E_DEBUG_INIT,
3716 "HW Capability: RSS = %d\n", p->rss);
3717 i40e_debug(hw, I40E_DEBUG_INIT,
3718 "HW Capability: RSS table size = %d\n",
3720 i40e_debug(hw, I40E_DEBUG_INIT,
3721 "HW Capability: RSS table width = %d\n",
3722 p->rss_table_entry_width);
3724 case I40E_AQ_CAP_ID_RXQ:
3725 p->num_rx_qp = number;
3726 p->base_queue = phys_id;
3727 i40e_debug(hw, I40E_DEBUG_INIT,
3728 "HW Capability: Rx QP = %d\n", number);
3729 i40e_debug(hw, I40E_DEBUG_INIT,
3730 "HW Capability: base_queue = %d\n",
3733 case I40E_AQ_CAP_ID_TXQ:
3734 p->num_tx_qp = number;
3735 p->base_queue = phys_id;
3736 i40e_debug(hw, I40E_DEBUG_INIT,
3737 "HW Capability: Tx QP = %d\n", number);
3738 i40e_debug(hw, I40E_DEBUG_INIT,
3739 "HW Capability: base_queue = %d\n",
3742 case I40E_AQ_CAP_ID_MSIX:
3743 p->num_msix_vectors = number;
3744 i40e_debug(hw, I40E_DEBUG_INIT,
3745 "HW Capability: MSIX vector count = %d\n",
3746 p->num_msix_vectors);
3748 case I40E_AQ_CAP_ID_VF_MSIX:
3749 p->num_msix_vectors_vf = number;
3750 i40e_debug(hw, I40E_DEBUG_INIT,
3751 "HW Capability: MSIX VF vector count = %d\n",
3752 p->num_msix_vectors_vf);
3754 case I40E_AQ_CAP_ID_FLEX10:
3755 if (major_rev == 1) {
3757 p->flex10_enable = true;
3758 p->flex10_capable = true;
3761 /* Capability revision >= 2 */
3763 p->flex10_enable = true;
3765 p->flex10_capable = true;
3767 p->flex10_mode = logical_id;
3768 p->flex10_status = phys_id;
3769 i40e_debug(hw, I40E_DEBUG_INIT,
3770 "HW Capability: Flex10 mode = %d\n",
3772 i40e_debug(hw, I40E_DEBUG_INIT,
3773 "HW Capability: Flex10 status = %d\n",
3776 case I40E_AQ_CAP_ID_CEM:
3779 i40e_debug(hw, I40E_DEBUG_INIT,
3780 "HW Capability: CEM = %d\n", p->mgmt_cem);
3782 case I40E_AQ_CAP_ID_IWARP:
3785 i40e_debug(hw, I40E_DEBUG_INIT,
3786 "HW Capability: iWARP = %d\n", p->iwarp);
3788 case I40E_AQ_CAP_ID_LED:
3789 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3790 p->led[phys_id] = true;
3791 i40e_debug(hw, I40E_DEBUG_INIT,
3792 "HW Capability: LED - PIN %d\n", phys_id);
3794 case I40E_AQ_CAP_ID_SDP:
3795 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3796 p->sdp[phys_id] = true;
3797 i40e_debug(hw, I40E_DEBUG_INIT,
3798 "HW Capability: SDP - PIN %d\n", phys_id);
3800 case I40E_AQ_CAP_ID_MDIO:
3802 p->mdio_port_num = phys_id;
3803 p->mdio_port_mode = logical_id;
3805 i40e_debug(hw, I40E_DEBUG_INIT,
3806 "HW Capability: MDIO port number = %d\n",
3808 i40e_debug(hw, I40E_DEBUG_INIT,
3809 "HW Capability: MDIO port mode = %d\n",
3812 case I40E_AQ_CAP_ID_1588:
3814 p->ieee_1588 = true;
3815 i40e_debug(hw, I40E_DEBUG_INIT,
3816 "HW Capability: IEEE 1588 = %d\n",
3819 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3821 p->fd_filters_guaranteed = number;
3822 p->fd_filters_best_effort = logical_id;
3823 i40e_debug(hw, I40E_DEBUG_INIT,
3824 "HW Capability: Flow Director = 1\n");
3825 i40e_debug(hw, I40E_DEBUG_INIT,
3826 "HW Capability: Guaranteed FD filters = %d\n",
3827 p->fd_filters_guaranteed);
3829 case I40E_AQ_CAP_ID_WSR_PROT:
3830 p->wr_csr_prot = (u64)number;
3831 p->wr_csr_prot |= (u64)logical_id << 32;
3832 i40e_debug(hw, I40E_DEBUG_INIT,
3833 "HW Capability: wr_csr_prot = 0x%llX\n\n",
3834 (p->wr_csr_prot & 0xffff));
3836 case I40E_AQ_CAP_ID_NVM_MGMT:
3837 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3838 p->sec_rev_disabled = true;
3839 if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3840 p->update_disabled = true;
3843 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3844 hw->num_wol_proxy_filters = (u16)number;
3845 hw->wol_proxy_vsi_seid = (u16)logical_id;
3846 p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3847 if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3848 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3850 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3851 p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3852 i40e_debug(hw, I40E_DEBUG_INIT,
3853 "HW Capability: WOL proxy filters = %d\n",
3854 hw->num_wol_proxy_filters);
3863 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3865 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3868 /* count the enabled ports (aka the "not disabled" ports) */
3870 for (i = 0; i < 4; i++) {
3871 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3874 /* use AQ read to get the physical register offset instead
3875 * of the port relative offset
3877 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3878 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3882 valid_functions = p->valid_functions;
3884 while (valid_functions) {
3885 if (valid_functions & 1)
3887 valid_functions >>= 1;
3890 /* partition id is 1-based, and functions are evenly spread
3891 * across the ports as partitions
3893 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3894 hw->num_partitions = num_functions / hw->num_ports;
3896 /* additional HW specific goodies that might
3897 * someday be HW version specific
3899 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3903 * i40e_aq_discover_capabilities
3904 * @hw: pointer to the hw struct
3905 * @buff: a virtual buffer to hold the capabilities
3906 * @buff_size: Size of the virtual buffer
3907 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3908 * @list_type_opc: capabilities type to discover - pass in the command opcode
3909 * @cmd_details: pointer to command details structure or NULL
3911 * Get the device capabilities descriptions from the firmware
3913 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3914 void *buff, u16 buff_size, u16 *data_size,
3915 enum i40e_admin_queue_opc list_type_opc,
3916 struct i40e_asq_cmd_details *cmd_details)
3918 struct i40e_aqc_list_capabilites *cmd;
3919 struct i40e_aq_desc desc;
3920 enum i40e_status_code status = I40E_SUCCESS;
3922 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3924 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3925 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3926 status = I40E_ERR_PARAM;
3930 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3932 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3933 if (buff_size > I40E_AQ_LARGE_BUF)
3934 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3936 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3937 *data_size = LE16_TO_CPU(desc.datalen);
3942 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3950 * i40e_aq_update_nvm
3951 * @hw: pointer to the hw struct
3952 * @module_pointer: module pointer location in words from the NVM beginning
3953 * @offset: byte offset from the module beginning
3954 * @length: length of the section to be written (in bytes from the offset)
3955 * @data: command buffer (size [bytes] = length)
3956 * @last_command: tells if this is the last command in a series
3957 * @cmd_details: pointer to command details structure or NULL
3959 * Update the NVM using the admin queue commands
3961 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3962 u32 offset, u16 length, void *data,
3964 struct i40e_asq_cmd_details *cmd_details)
3966 struct i40e_aq_desc desc;
3967 struct i40e_aqc_nvm_update *cmd =
3968 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3969 enum i40e_status_code status;
3971 DEBUGFUNC("i40e_aq_update_nvm");
3973 /* In offset the highest byte must be zeroed. */
3974 if (offset & 0xFF000000) {
3975 status = I40E_ERR_PARAM;
3976 goto i40e_aq_update_nvm_exit;
3979 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3981 /* If this is the last command in a series, set the proper flag. */
3983 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3984 cmd->module_pointer = module_pointer;
3985 cmd->offset = CPU_TO_LE32(offset);
3986 cmd->length = CPU_TO_LE16(length);
3988 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3989 if (length > I40E_AQ_LARGE_BUF)
3990 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3992 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3994 i40e_aq_update_nvm_exit:
3999 * i40e_aq_get_lldp_mib
4000 * @hw: pointer to the hw struct
4001 * @bridge_type: type of bridge requested
4002 * @mib_type: Local, Remote or both Local and Remote MIBs
4003 * @buff: pointer to a user supplied buffer to store the MIB block
4004 * @buff_size: size of the buffer (in bytes)
4005 * @local_len : length of the returned Local LLDP MIB
4006 * @remote_len: length of the returned Remote LLDP MIB
4007 * @cmd_details: pointer to command details structure or NULL
4009 * Requests the complete LLDP MIB (entire packet).
4011 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4012 u8 mib_type, void *buff, u16 buff_size,
4013 u16 *local_len, u16 *remote_len,
4014 struct i40e_asq_cmd_details *cmd_details)
4016 struct i40e_aq_desc desc;
4017 struct i40e_aqc_lldp_get_mib *cmd =
4018 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4019 struct i40e_aqc_lldp_get_mib *resp =
4020 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4021 enum i40e_status_code status;
4023 if (buff_size == 0 || !buff)
4024 return I40E_ERR_PARAM;
4026 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4027 /* Indirect Command */
4028 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4030 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4031 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4032 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4034 desc.datalen = CPU_TO_LE16(buff_size);
4036 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4037 if (buff_size > I40E_AQ_LARGE_BUF)
4038 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4040 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4042 if (local_len != NULL)
4043 *local_len = LE16_TO_CPU(resp->local_len);
4044 if (remote_len != NULL)
4045 *remote_len = LE16_TO_CPU(resp->remote_len);
4052 * i40e_aq_set_lldp_mib - Set the LLDP MIB
4053 * @hw: pointer to the hw struct
4054 * @mib_type: Local, Remote or both Local and Remote MIBs
4055 * @buff: pointer to a user supplied buffer to store the MIB block
4056 * @buff_size: size of the buffer (in bytes)
4057 * @cmd_details: pointer to command details structure or NULL
4061 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4062 u8 mib_type, void *buff, u16 buff_size,
4063 struct i40e_asq_cmd_details *cmd_details)
4065 struct i40e_aq_desc desc;
4066 struct i40e_aqc_lldp_set_local_mib *cmd =
4067 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4068 enum i40e_status_code status;
4070 if (buff_size == 0 || !buff)
4071 return I40E_ERR_PARAM;
4073 i40e_fill_default_direct_cmd_desc(&desc,
4074 i40e_aqc_opc_lldp_set_local_mib);
4075 /* Indirect Command */
4076 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4077 if (buff_size > I40E_AQ_LARGE_BUF)
4078 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4079 desc.datalen = CPU_TO_LE16(buff_size);
4081 cmd->type = mib_type;
4082 cmd->length = CPU_TO_LE16(buff_size);
4083 cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4084 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4086 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4091 * i40e_aq_cfg_lldp_mib_change_event
4092 * @hw: pointer to the hw struct
4093 * @enable_update: Enable or Disable event posting
4094 * @cmd_details: pointer to command details structure or NULL
4096 * Enable or Disable posting of an event on ARQ when LLDP MIB
4097 * associated with the interface changes
4099 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4101 struct i40e_asq_cmd_details *cmd_details)
4103 struct i40e_aq_desc desc;
4104 struct i40e_aqc_lldp_update_mib *cmd =
4105 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4106 enum i40e_status_code status;
4108 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4111 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4113 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4119 * i40e_aq_add_lldp_tlv
4120 * @hw: pointer to the hw struct
4121 * @bridge_type: type of bridge
4122 * @buff: buffer with TLV to add
4123 * @buff_size: length of the buffer
4124 * @tlv_len: length of the TLV to be added
4125 * @mib_len: length of the LLDP MIB returned in response
4126 * @cmd_details: pointer to command details structure or NULL
4128 * Add the specified TLV to LLDP Local MIB for the given bridge type,
4129 * it is responsibility of the caller to make sure that the TLV is not
4130 * already present in the LLDPDU.
4131 * In return firmware will write the complete LLDP MIB with the newly
4132 * added TLV in the response buffer.
4134 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4135 void *buff, u16 buff_size, u16 tlv_len,
4137 struct i40e_asq_cmd_details *cmd_details)
4139 struct i40e_aq_desc desc;
4140 struct i40e_aqc_lldp_add_tlv *cmd =
4141 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4142 enum i40e_status_code status;
4144 if (buff_size == 0 || !buff || tlv_len == 0)
4145 return I40E_ERR_PARAM;
4147 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4149 /* Indirect Command */
4150 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4151 if (buff_size > I40E_AQ_LARGE_BUF)
4152 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4153 desc.datalen = CPU_TO_LE16(buff_size);
4155 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4156 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4157 cmd->len = CPU_TO_LE16(tlv_len);
4159 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4161 if (mib_len != NULL)
4162 *mib_len = LE16_TO_CPU(desc.datalen);
4169 * i40e_aq_update_lldp_tlv
4170 * @hw: pointer to the hw struct
4171 * @bridge_type: type of bridge
4172 * @buff: buffer with TLV to update
4173 * @buff_size: size of the buffer holding original and updated TLVs
4174 * @old_len: Length of the Original TLV
4175 * @new_len: Length of the Updated TLV
4176 * @offset: offset of the updated TLV in the buff
4177 * @mib_len: length of the returned LLDP MIB
4178 * @cmd_details: pointer to command details structure or NULL
4180 * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4181 * Firmware will place the complete LLDP MIB in response buffer with the
4184 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4185 u8 bridge_type, void *buff, u16 buff_size,
4186 u16 old_len, u16 new_len, u16 offset,
4188 struct i40e_asq_cmd_details *cmd_details)
4190 struct i40e_aq_desc desc;
4191 struct i40e_aqc_lldp_update_tlv *cmd =
4192 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4193 enum i40e_status_code status;
4195 if (buff_size == 0 || !buff || offset == 0 ||
4196 old_len == 0 || new_len == 0)
4197 return I40E_ERR_PARAM;
4199 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4201 /* Indirect Command */
4202 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4203 if (buff_size > I40E_AQ_LARGE_BUF)
4204 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4205 desc.datalen = CPU_TO_LE16(buff_size);
4207 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4208 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4209 cmd->old_len = CPU_TO_LE16(old_len);
4210 cmd->new_offset = CPU_TO_LE16(offset);
4211 cmd->new_len = CPU_TO_LE16(new_len);
4213 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4215 if (mib_len != NULL)
4216 *mib_len = LE16_TO_CPU(desc.datalen);
4223 * i40e_aq_delete_lldp_tlv
4224 * @hw: pointer to the hw struct
4225 * @bridge_type: type of bridge
4226 * @buff: pointer to a user supplied buffer that has the TLV
4227 * @buff_size: length of the buffer
4228 * @tlv_len: length of the TLV to be deleted
4229 * @mib_len: length of the returned LLDP MIB
4230 * @cmd_details: pointer to command details structure or NULL
4232 * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4233 * The firmware places the entire LLDP MIB in the response buffer.
4235 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4236 u8 bridge_type, void *buff, u16 buff_size,
4237 u16 tlv_len, u16 *mib_len,
4238 struct i40e_asq_cmd_details *cmd_details)
4240 struct i40e_aq_desc desc;
4241 struct i40e_aqc_lldp_add_tlv *cmd =
4242 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4243 enum i40e_status_code status;
4245 if (buff_size == 0 || !buff)
4246 return I40E_ERR_PARAM;
4248 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4250 /* Indirect Command */
4251 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4252 if (buff_size > I40E_AQ_LARGE_BUF)
4253 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4254 desc.datalen = CPU_TO_LE16(buff_size);
4255 cmd->len = CPU_TO_LE16(tlv_len);
4256 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4257 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4259 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4261 if (mib_len != NULL)
4262 *mib_len = LE16_TO_CPU(desc.datalen);
4270 * @hw: pointer to the hw struct
4271 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4272 * @cmd_details: pointer to command details structure or NULL
4274 * Stop or Shutdown the embedded LLDP Agent
4276 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4277 struct i40e_asq_cmd_details *cmd_details)
4279 struct i40e_aq_desc desc;
4280 struct i40e_aqc_lldp_stop *cmd =
4281 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4282 enum i40e_status_code status;
4284 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4287 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4289 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4295 * i40e_aq_start_lldp
4296 * @hw: pointer to the hw struct
4297 * @cmd_details: pointer to command details structure or NULL
4299 * Start the embedded LLDP Agent on all ports.
4301 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4302 struct i40e_asq_cmd_details *cmd_details)
4304 struct i40e_aq_desc desc;
4305 struct i40e_aqc_lldp_start *cmd =
4306 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4307 enum i40e_status_code status;
4309 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4311 cmd->command = I40E_AQ_LLDP_AGENT_START;
4313 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4319 * i40e_aq_get_cee_dcb_config
4320 * @hw: pointer to the hw struct
4321 * @buff: response buffer that stores CEE operational configuration
4322 * @buff_size: size of the buffer passed
4323 * @cmd_details: pointer to command details structure or NULL
4325 * Get CEE DCBX mode operational configuration from firmware
4327 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4328 void *buff, u16 buff_size,
4329 struct i40e_asq_cmd_details *cmd_details)
4331 struct i40e_aq_desc desc;
4332 enum i40e_status_code status;
4334 if (buff_size == 0 || !buff)
4335 return I40E_ERR_PARAM;
4337 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4339 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4340 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4347 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4348 * @hw: pointer to the hw struct
4349 * @start_agent: True if DCBx Agent needs to be Started
4350 * False if DCBx Agent needs to be Stopped
4351 * @cmd_details: pointer to command details structure or NULL
4353 * Start/Stop the embedded dcbx Agent
4355 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4357 struct i40e_asq_cmd_details *cmd_details)
4359 struct i40e_aq_desc desc;
4360 struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4361 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4363 enum i40e_status_code status;
4365 i40e_fill_default_direct_cmd_desc(&desc,
4366 i40e_aqc_opc_lldp_stop_start_spec_agent);
4369 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4371 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4377 * i40e_aq_add_udp_tunnel
4378 * @hw: pointer to the hw struct
4379 * @udp_port: the UDP port to add
4380 * @header_len: length of the tunneling header length in DWords
4381 * @protocol_index: protocol index type
4382 * @filter_index: pointer to filter index
4383 * @cmd_details: pointer to command details structure or NULL
4385 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4386 u16 udp_port, u8 protocol_index,
4388 struct i40e_asq_cmd_details *cmd_details)
4390 struct i40e_aq_desc desc;
4391 struct i40e_aqc_add_udp_tunnel *cmd =
4392 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4393 struct i40e_aqc_del_udp_tunnel_completion *resp =
4394 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4395 enum i40e_status_code status;
4397 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4399 cmd->udp_port = CPU_TO_LE16(udp_port);
4400 cmd->protocol_type = protocol_index;
4402 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4404 if (!status && filter_index)
4405 *filter_index = resp->index;
4411 * i40e_aq_del_udp_tunnel
4412 * @hw: pointer to the hw struct
4413 * @index: filter index
4414 * @cmd_details: pointer to command details structure or NULL
4416 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4417 struct i40e_asq_cmd_details *cmd_details)
4419 struct i40e_aq_desc desc;
4420 struct i40e_aqc_remove_udp_tunnel *cmd =
4421 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4422 enum i40e_status_code status;
4424 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4428 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4434 * i40e_aq_get_switch_resource_alloc (0x0204)
4435 * @hw: pointer to the hw struct
4436 * @num_entries: pointer to u8 to store the number of resource entries returned
4437 * @buf: pointer to a user supplied buffer. This buffer must be large enough
4438 * to store the resource information for all resource types. Each
4439 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
4440 * @count: size, in bytes, of the buffer provided
4441 * @cmd_details: pointer to command details structure or NULL
4443 * Query the resources allocated to a function.
4445 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4447 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4449 struct i40e_asq_cmd_details *cmd_details)
4451 struct i40e_aq_desc desc;
4452 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4453 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4454 enum i40e_status_code status;
4455 u16 length = count * sizeof(*buf);
4457 i40e_fill_default_direct_cmd_desc(&desc,
4458 i40e_aqc_opc_get_switch_resource_alloc);
4460 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4461 if (length > I40E_AQ_LARGE_BUF)
4462 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4464 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4466 if (!status && num_entries)
4467 *num_entries = cmd_resp->num_entries;
4473 * i40e_aq_delete_element - Delete switch element
4474 * @hw: pointer to the hw struct
4475 * @seid: the SEID to delete from the switch
4476 * @cmd_details: pointer to command details structure or NULL
4478 * This deletes a switch element from the switch.
4480 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4481 struct i40e_asq_cmd_details *cmd_details)
4483 struct i40e_aq_desc desc;
4484 struct i40e_aqc_switch_seid *cmd =
4485 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4486 enum i40e_status_code status;
4489 return I40E_ERR_PARAM;
4491 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4493 cmd->seid = CPU_TO_LE16(seid);
4495 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4501 * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4502 * @hw: pointer to the hw struct
4503 * @flags: component flags
4504 * @mac_seid: uplink seid (MAC SEID)
4505 * @vsi_seid: connected vsi seid
4506 * @ret_seid: seid of create pv component
4508 * This instantiates an i40e port virtualizer with specified flags.
4509 * Depending on specified flags the port virtualizer can act as a
4510 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4512 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4513 u16 mac_seid, u16 vsi_seid,
4516 struct i40e_aq_desc desc;
4517 struct i40e_aqc_add_update_pv *cmd =
4518 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4519 struct i40e_aqc_add_update_pv_completion *resp =
4520 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4521 enum i40e_status_code status;
4524 return I40E_ERR_PARAM;
4526 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4527 cmd->command_flags = CPU_TO_LE16(flags);
4528 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4529 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4531 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4532 if (!status && ret_seid)
4533 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4539 * i40e_aq_add_tag - Add an S/E-tag
4540 * @hw: pointer to the hw struct
4541 * @direct_to_queue: should s-tag direct flow to a specific queue
4542 * @vsi_seid: VSI SEID to use this tag
4543 * @tag: value of the tag
4544 * @queue_num: queue number, only valid is direct_to_queue is true
4545 * @tags_used: return value, number of tags in use by this PF
4546 * @tags_free: return value, number of unallocated tags
4547 * @cmd_details: pointer to command details structure or NULL
4549 * This associates an S- or E-tag to a VSI in the switch complex. It returns
4550 * the number of tags allocated by the PF, and the number of unallocated
4553 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4554 u16 vsi_seid, u16 tag, u16 queue_num,
4555 u16 *tags_used, u16 *tags_free,
4556 struct i40e_asq_cmd_details *cmd_details)
4558 struct i40e_aq_desc desc;
4559 struct i40e_aqc_add_tag *cmd =
4560 (struct i40e_aqc_add_tag *)&desc.params.raw;
4561 struct i40e_aqc_add_remove_tag_completion *resp =
4562 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4563 enum i40e_status_code status;
4566 return I40E_ERR_PARAM;
4568 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4570 cmd->seid = CPU_TO_LE16(vsi_seid);
4571 cmd->tag = CPU_TO_LE16(tag);
4572 if (direct_to_queue) {
4573 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4574 cmd->queue_number = CPU_TO_LE16(queue_num);
4577 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4580 if (tags_used != NULL)
4581 *tags_used = LE16_TO_CPU(resp->tags_used);
4582 if (tags_free != NULL)
4583 *tags_free = LE16_TO_CPU(resp->tags_free);
4590 * i40e_aq_remove_tag - Remove an S- or E-tag
4591 * @hw: pointer to the hw struct
4592 * @vsi_seid: VSI SEID this tag is associated with
4593 * @tag: value of the S-tag to delete
4594 * @tags_used: return value, number of tags in use by this PF
4595 * @tags_free: return value, number of unallocated tags
4596 * @cmd_details: pointer to command details structure or NULL
4598 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
4599 * the number of tags allocated by the PF, and the number of unallocated
4602 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4603 u16 tag, u16 *tags_used, u16 *tags_free,
4604 struct i40e_asq_cmd_details *cmd_details)
4606 struct i40e_aq_desc desc;
4607 struct i40e_aqc_remove_tag *cmd =
4608 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4609 struct i40e_aqc_add_remove_tag_completion *resp =
4610 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4611 enum i40e_status_code status;
4614 return I40E_ERR_PARAM;
4616 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4618 cmd->seid = CPU_TO_LE16(vsi_seid);
4619 cmd->tag = CPU_TO_LE16(tag);
4621 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4624 if (tags_used != NULL)
4625 *tags_used = LE16_TO_CPU(resp->tags_used);
4626 if (tags_free != NULL)
4627 *tags_free = LE16_TO_CPU(resp->tags_free);
4634 * i40e_aq_add_mcast_etag - Add a multicast E-tag
4635 * @hw: pointer to the hw struct
4636 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4637 * @etag: value of E-tag to add
4638 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4639 * @buf: address of indirect buffer
4640 * @tags_used: return value, number of E-tags in use by this port
4641 * @tags_free: return value, number of unallocated M-tags
4642 * @cmd_details: pointer to command details structure or NULL
4644 * This associates a multicast E-tag to a port virtualizer. It will return
4645 * the number of tags allocated by the PF, and the number of unallocated
4648 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4649 * num_tags_in_buf long.
4651 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4652 u16 etag, u8 num_tags_in_buf, void *buf,
4653 u16 *tags_used, u16 *tags_free,
4654 struct i40e_asq_cmd_details *cmd_details)
4656 struct i40e_aq_desc desc;
4657 struct i40e_aqc_add_remove_mcast_etag *cmd =
4658 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4659 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4660 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4661 enum i40e_status_code status;
4662 u16 length = sizeof(u16) * num_tags_in_buf;
4664 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4665 return I40E_ERR_PARAM;
4667 i40e_fill_default_direct_cmd_desc(&desc,
4668 i40e_aqc_opc_add_multicast_etag);
4670 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4671 cmd->etag = CPU_TO_LE16(etag);
4672 cmd->num_unicast_etags = num_tags_in_buf;
4674 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4675 if (length > I40E_AQ_LARGE_BUF)
4676 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4678 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4681 if (tags_used != NULL)
4682 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4683 if (tags_free != NULL)
4684 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4691 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4692 * @hw: pointer to the hw struct
4693 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4694 * @etag: value of the E-tag to remove
4695 * @tags_used: return value, number of tags in use by this port
4696 * @tags_free: return value, number of unallocated tags
4697 * @cmd_details: pointer to command details structure or NULL
4699 * This deletes an E-tag from the port virtualizer. It will return
4700 * the number of tags allocated by the port, and the number of unallocated
4703 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4704 u16 etag, u16 *tags_used, u16 *tags_free,
4705 struct i40e_asq_cmd_details *cmd_details)
4707 struct i40e_aq_desc desc;
4708 struct i40e_aqc_add_remove_mcast_etag *cmd =
4709 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4710 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4711 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4712 enum i40e_status_code status;
4716 return I40E_ERR_PARAM;
4718 i40e_fill_default_direct_cmd_desc(&desc,
4719 i40e_aqc_opc_remove_multicast_etag);
4721 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4722 cmd->etag = CPU_TO_LE16(etag);
4724 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4727 if (tags_used != NULL)
4728 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4729 if (tags_free != NULL)
4730 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4737 * i40e_aq_update_tag - Update an S/E-tag
4738 * @hw: pointer to the hw struct
4739 * @vsi_seid: VSI SEID using this S-tag
4740 * @old_tag: old tag value
4741 * @new_tag: new tag value
4742 * @tags_used: return value, number of tags in use by this PF
4743 * @tags_free: return value, number of unallocated tags
4744 * @cmd_details: pointer to command details structure or NULL
4746 * This updates the value of the tag currently attached to this VSI
4747 * in the switch complex. It will return the number of tags allocated
4748 * by the PF, and the number of unallocated tags available.
4750 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4751 u16 old_tag, u16 new_tag, u16 *tags_used,
4753 struct i40e_asq_cmd_details *cmd_details)
4755 struct i40e_aq_desc desc;
4756 struct i40e_aqc_update_tag *cmd =
4757 (struct i40e_aqc_update_tag *)&desc.params.raw;
4758 struct i40e_aqc_update_tag_completion *resp =
4759 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4760 enum i40e_status_code status;
4763 return I40E_ERR_PARAM;
4765 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4767 cmd->seid = CPU_TO_LE16(vsi_seid);
4768 cmd->old_tag = CPU_TO_LE16(old_tag);
4769 cmd->new_tag = CPU_TO_LE16(new_tag);
4771 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4774 if (tags_used != NULL)
4775 *tags_used = LE16_TO_CPU(resp->tags_used);
4776 if (tags_free != NULL)
4777 *tags_free = LE16_TO_CPU(resp->tags_free);
4784 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4785 * @hw: pointer to the hw struct
4786 * @tcmap: TC map for request/release any ignore PFC condition
4787 * @request: request or release ignore PFC condition
4788 * @tcmap_ret: return TCs for which PFC is currently ignored
4789 * @cmd_details: pointer to command details structure or NULL
4791 * This sends out request/release to ignore PFC condition for a TC.
4792 * It will return the TCs for which PFC is currently ignored.
4794 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4795 bool request, u8 *tcmap_ret,
4796 struct i40e_asq_cmd_details *cmd_details)
4798 struct i40e_aq_desc desc;
4799 struct i40e_aqc_pfc_ignore *cmd_resp =
4800 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4801 enum i40e_status_code status;
4803 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4806 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4808 cmd_resp->tc_bitmap = tcmap;
4810 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4813 if (tcmap_ret != NULL)
4814 *tcmap_ret = cmd_resp->tc_bitmap;
4821 * i40e_aq_dcb_updated - DCB Updated Command
4822 * @hw: pointer to the hw struct
4823 * @cmd_details: pointer to command details structure or NULL
4825 * When LLDP is handled in PF this command is used by the PF
4826 * to notify EMP that a DCB setting is modified.
4827 * When LLDP is handled in EMP this command is used by the PF
4828 * to notify EMP whenever one of the following parameters get
4830 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4831 * - PCIRTT in PRTDCB_GENC.PCIRTT
4832 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4833 * EMP will return when the shared RPB settings have been
4834 * recomputed and modified. The retval field in the descriptor
4835 * will be set to 0 when RPB is modified.
4837 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4838 struct i40e_asq_cmd_details *cmd_details)
4840 struct i40e_aq_desc desc;
4841 enum i40e_status_code status;
4843 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4845 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4851 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4852 * @hw: pointer to the hw struct
4853 * @seid: defines the SEID of the switch for which the stats are requested
4854 * @vlan_id: the VLAN ID for which the statistics are requested
4855 * @stat_index: index of the statistics counters block assigned to this VLAN
4856 * @cmd_details: pointer to command details structure or NULL
4858 * XL710 supports 128 smonVlanStats counters.This command is used to
4859 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4862 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4863 u16 vlan_id, u16 *stat_index,
4864 struct i40e_asq_cmd_details *cmd_details)
4866 struct i40e_aq_desc desc;
4867 struct i40e_aqc_add_remove_statistics *cmd_resp =
4868 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4869 enum i40e_status_code status;
4871 if ((seid == 0) || (stat_index == NULL))
4872 return I40E_ERR_PARAM;
4874 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4876 cmd_resp->seid = CPU_TO_LE16(seid);
4877 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4879 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4881 if (!status && stat_index)
4882 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4888 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4889 * @hw: pointer to the hw struct
4890 * @seid: defines the SEID of the switch for which the stats are requested
4891 * @vlan_id: the VLAN ID for which the statistics are requested
4892 * @stat_index: index of the statistics counters block assigned to this VLAN
4893 * @cmd_details: pointer to command details structure or NULL
4895 * XL710 supports 128 smonVlanStats counters.This command is used to
4896 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4899 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4900 u16 vlan_id, u16 stat_index,
4901 struct i40e_asq_cmd_details *cmd_details)
4903 struct i40e_aq_desc desc;
4904 struct i40e_aqc_add_remove_statistics *cmd =
4905 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4906 enum i40e_status_code status;
4909 return I40E_ERR_PARAM;
4911 i40e_fill_default_direct_cmd_desc(&desc,
4912 i40e_aqc_opc_remove_statistics);
4914 cmd->seid = CPU_TO_LE16(seid);
4915 cmd->vlan = CPU_TO_LE16(vlan_id);
4916 cmd->stat_index = CPU_TO_LE16(stat_index);
4918 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4924 * i40e_aq_set_port_parameters - set physical port parameters.
4925 * @hw: pointer to the hw struct
4926 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4927 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4928 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4929 * @double_vlan: if set double VLAN is enabled
4930 * @cmd_details: pointer to command details structure or NULL
4932 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4933 u16 bad_frame_vsi, bool save_bad_pac,
4934 bool pad_short_pac, bool double_vlan,
4935 struct i40e_asq_cmd_details *cmd_details)
4937 struct i40e_aqc_set_port_parameters *cmd;
4938 enum i40e_status_code status;
4939 struct i40e_aq_desc desc;
4940 u16 command_flags = 0;
4942 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4944 i40e_fill_default_direct_cmd_desc(&desc,
4945 i40e_aqc_opc_set_port_parameters);
4947 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4949 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4951 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4953 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4954 cmd->command_flags = CPU_TO_LE16(command_flags);
4956 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4962 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
4963 * @hw: pointer to the hw struct
4964 * @seid: seid for the physical port/switching component/vsi
4965 * @buff: Indirect buffer to hold data parameters and response
4966 * @buff_size: Indirect buffer size
4967 * @opcode: Tx scheduler AQ command opcode
4968 * @cmd_details: pointer to command details structure or NULL
4970 * Generic command handler for Tx scheduler AQ commands
4972 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
4973 void *buff, u16 buff_size,
4974 enum i40e_admin_queue_opc opcode,
4975 struct i40e_asq_cmd_details *cmd_details)
4977 struct i40e_aq_desc desc;
4978 struct i40e_aqc_tx_sched_ind *cmd =
4979 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4980 enum i40e_status_code status;
4981 bool cmd_param_flag = false;
4984 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
4985 case i40e_aqc_opc_configure_vsi_tc_bw:
4986 case i40e_aqc_opc_enable_switching_comp_ets:
4987 case i40e_aqc_opc_modify_switching_comp_ets:
4988 case i40e_aqc_opc_disable_switching_comp_ets:
4989 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
4990 case i40e_aqc_opc_configure_switching_comp_bw_config:
4991 cmd_param_flag = true;
4993 case i40e_aqc_opc_query_vsi_bw_config:
4994 case i40e_aqc_opc_query_vsi_ets_sla_config:
4995 case i40e_aqc_opc_query_switching_comp_ets_config:
4996 case i40e_aqc_opc_query_port_ets_config:
4997 case i40e_aqc_opc_query_switching_comp_bw_config:
4998 cmd_param_flag = false;
5001 return I40E_ERR_PARAM;
5004 i40e_fill_default_direct_cmd_desc(&desc, opcode);
5006 /* Indirect command */
5007 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5009 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5010 if (buff_size > I40E_AQ_LARGE_BUF)
5011 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5013 desc.datalen = CPU_TO_LE16(buff_size);
5015 cmd->vsi_seid = CPU_TO_LE16(seid);
5017 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5023 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5024 * @hw: pointer to the hw struct
5026 * @credit: BW limit credits (0 = disabled)
5027 * @max_credit: Max BW limit credits
5028 * @cmd_details: pointer to command details structure or NULL
5030 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5031 u16 seid, u16 credit, u8 max_credit,
5032 struct i40e_asq_cmd_details *cmd_details)
5034 struct i40e_aq_desc desc;
5035 struct i40e_aqc_configure_vsi_bw_limit *cmd =
5036 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5037 enum i40e_status_code status;
5039 i40e_fill_default_direct_cmd_desc(&desc,
5040 i40e_aqc_opc_configure_vsi_bw_limit);
5042 cmd->vsi_seid = CPU_TO_LE16(seid);
5043 cmd->credit = CPU_TO_LE16(credit);
5044 cmd->max_credit = max_credit;
5046 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5052 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5053 * @hw: pointer to the hw struct
5054 * @seid: switching component seid
5055 * @credit: BW limit credits (0 = disabled)
5056 * @max_bw: Max BW limit credits
5057 * @cmd_details: pointer to command details structure or NULL
5059 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5060 u16 seid, u16 credit, u8 max_bw,
5061 struct i40e_asq_cmd_details *cmd_details)
5063 struct i40e_aq_desc desc;
5064 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5065 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5066 enum i40e_status_code status;
5068 i40e_fill_default_direct_cmd_desc(&desc,
5069 i40e_aqc_opc_configure_switching_comp_bw_limit);
5071 cmd->seid = CPU_TO_LE16(seid);
5072 cmd->credit = CPU_TO_LE16(credit);
5073 cmd->max_bw = max_bw;
5075 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5081 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5082 * @hw: pointer to the hw struct
5084 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5085 * @cmd_details: pointer to command details structure or NULL
5087 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5089 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5090 struct i40e_asq_cmd_details *cmd_details)
5092 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5093 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5098 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5099 * @hw: pointer to the hw struct
5101 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5102 * @cmd_details: pointer to command details structure or NULL
5104 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5106 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5107 struct i40e_asq_cmd_details *cmd_details)
5109 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5110 i40e_aqc_opc_configure_vsi_tc_bw,
5115 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5116 * @hw: pointer to the hw struct
5117 * @seid: seid of the switching component connected to Physical Port
5118 * @ets_data: Buffer holding ETS parameters
5119 * @cmd_details: pointer to command details structure or NULL
5121 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5123 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5124 enum i40e_admin_queue_opc opcode,
5125 struct i40e_asq_cmd_details *cmd_details)
5127 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5128 sizeof(*ets_data), opcode, cmd_details);
5132 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5133 * @hw: pointer to the hw struct
5134 * @seid: seid of the switching component
5135 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5136 * @cmd_details: pointer to command details structure or NULL
5138 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5140 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5141 struct i40e_asq_cmd_details *cmd_details)
5143 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5144 i40e_aqc_opc_configure_switching_comp_bw_config,
5149 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5150 * @hw: pointer to the hw struct
5151 * @seid: seid of the switching component
5152 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5153 * @cmd_details: pointer to command details structure or NULL
5155 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5156 struct i40e_hw *hw, u16 seid,
5157 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5158 struct i40e_asq_cmd_details *cmd_details)
5160 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5161 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5166 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5167 * @hw: pointer to the hw struct
5168 * @seid: seid of the VSI
5169 * @bw_data: Buffer to hold VSI BW configuration
5170 * @cmd_details: pointer to command details structure or NULL
5172 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5174 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5175 struct i40e_asq_cmd_details *cmd_details)
5177 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5178 i40e_aqc_opc_query_vsi_bw_config,
5183 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5184 * @hw: pointer to the hw struct
5185 * @seid: seid of the VSI
5186 * @bw_data: Buffer to hold VSI BW configuration per TC
5187 * @cmd_details: pointer to command details structure or NULL
5189 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5191 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5192 struct i40e_asq_cmd_details *cmd_details)
5194 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5195 i40e_aqc_opc_query_vsi_ets_sla_config,
5200 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5201 * @hw: pointer to the hw struct
5202 * @seid: seid of the switching component
5203 * @bw_data: Buffer to hold switching component's per TC BW config
5204 * @cmd_details: pointer to command details structure or NULL
5206 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5208 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5209 struct i40e_asq_cmd_details *cmd_details)
5211 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5212 i40e_aqc_opc_query_switching_comp_ets_config,
5217 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5218 * @hw: pointer to the hw struct
5219 * @seid: seid of the VSI or switching component connected to Physical Port
5220 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5221 * @cmd_details: pointer to command details structure or NULL
5223 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5225 struct i40e_aqc_query_port_ets_config_resp *bw_data,
5226 struct i40e_asq_cmd_details *cmd_details)
5228 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5229 i40e_aqc_opc_query_port_ets_config,
5234 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5235 * @hw: pointer to the hw struct
5236 * @seid: seid of the switching component
5237 * @bw_data: Buffer to hold switching component's BW configuration
5238 * @cmd_details: pointer to command details structure or NULL
5240 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5242 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5243 struct i40e_asq_cmd_details *cmd_details)
5245 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5246 i40e_aqc_opc_query_switching_comp_bw_config,
5251 * i40e_validate_filter_settings
5252 * @hw: pointer to the hardware structure
5253 * @settings: Filter control settings
5255 * Check and validate the filter control settings passed.
5256 * The function checks for the valid filter/context sizes being
5257 * passed for FCoE and PE.
5259 * Returns I40E_SUCCESS if the values passed are valid and within
5260 * range else returns an error.
5262 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5263 struct i40e_filter_control_settings *settings)
5265 u32 fcoe_cntx_size, fcoe_filt_size;
5266 u32 pe_cntx_size, pe_filt_size;
5271 /* Validate FCoE settings passed */
5272 switch (settings->fcoe_filt_num) {
5273 case I40E_HASH_FILTER_SIZE_1K:
5274 case I40E_HASH_FILTER_SIZE_2K:
5275 case I40E_HASH_FILTER_SIZE_4K:
5276 case I40E_HASH_FILTER_SIZE_8K:
5277 case I40E_HASH_FILTER_SIZE_16K:
5278 case I40E_HASH_FILTER_SIZE_32K:
5279 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5280 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5283 return I40E_ERR_PARAM;
5286 switch (settings->fcoe_cntx_num) {
5287 case I40E_DMA_CNTX_SIZE_512:
5288 case I40E_DMA_CNTX_SIZE_1K:
5289 case I40E_DMA_CNTX_SIZE_2K:
5290 case I40E_DMA_CNTX_SIZE_4K:
5291 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5292 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5295 return I40E_ERR_PARAM;
5298 /* Validate PE settings passed */
5299 switch (settings->pe_filt_num) {
5300 case I40E_HASH_FILTER_SIZE_1K:
5301 case I40E_HASH_FILTER_SIZE_2K:
5302 case I40E_HASH_FILTER_SIZE_4K:
5303 case I40E_HASH_FILTER_SIZE_8K:
5304 case I40E_HASH_FILTER_SIZE_16K:
5305 case I40E_HASH_FILTER_SIZE_32K:
5306 case I40E_HASH_FILTER_SIZE_64K:
5307 case I40E_HASH_FILTER_SIZE_128K:
5308 case I40E_HASH_FILTER_SIZE_256K:
5309 case I40E_HASH_FILTER_SIZE_512K:
5310 case I40E_HASH_FILTER_SIZE_1M:
5311 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5312 pe_filt_size <<= (u32)settings->pe_filt_num;
5315 return I40E_ERR_PARAM;
5318 switch (settings->pe_cntx_num) {
5319 case I40E_DMA_CNTX_SIZE_512:
5320 case I40E_DMA_CNTX_SIZE_1K:
5321 case I40E_DMA_CNTX_SIZE_2K:
5322 case I40E_DMA_CNTX_SIZE_4K:
5323 case I40E_DMA_CNTX_SIZE_8K:
5324 case I40E_DMA_CNTX_SIZE_16K:
5325 case I40E_DMA_CNTX_SIZE_32K:
5326 case I40E_DMA_CNTX_SIZE_64K:
5327 case I40E_DMA_CNTX_SIZE_128K:
5328 case I40E_DMA_CNTX_SIZE_256K:
5329 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5330 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5333 return I40E_ERR_PARAM;
5336 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5337 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5338 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5339 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5340 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
5341 return I40E_ERR_INVALID_SIZE;
5343 return I40E_SUCCESS;
5347 * i40e_set_filter_control
5348 * @hw: pointer to the hardware structure
5349 * @settings: Filter control settings
5351 * Set the Queue Filters for PE/FCoE and enable filters required
5352 * for a single PF. It is expected that these settings are programmed
5353 * at the driver initialization time.
5355 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5356 struct i40e_filter_control_settings *settings)
5358 enum i40e_status_code ret = I40E_SUCCESS;
5359 u32 hash_lut_size = 0;
5363 return I40E_ERR_PARAM;
5365 /* Validate the input settings */
5366 ret = i40e_validate_filter_settings(hw, settings);
5370 /* Read the PF Queue Filter control register */
5371 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5373 /* Program required PE hash buckets for the PF */
5374 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5375 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5376 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5377 /* Program required PE contexts for the PF */
5378 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5379 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5380 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5382 /* Program required FCoE hash buckets for the PF */
5383 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5384 val |= ((u32)settings->fcoe_filt_num <<
5385 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5386 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5387 /* Program required FCoE DDP contexts for the PF */
5388 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5389 val |= ((u32)settings->fcoe_cntx_num <<
5390 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5391 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5393 /* Program Hash LUT size for the PF */
5394 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5395 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5397 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5398 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5400 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5401 if (settings->enable_fdir)
5402 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5403 if (settings->enable_ethtype)
5404 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5405 if (settings->enable_macvlan)
5406 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5408 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5410 return I40E_SUCCESS;
5414 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5415 * @hw: pointer to the hw struct
5416 * @mac_addr: MAC address to use in the filter
5417 * @ethtype: Ethertype to use in the filter
5418 * @flags: Flags that needs to be applied to the filter
5419 * @vsi_seid: seid of the control VSI
5420 * @queue: VSI queue number to send the packet to
5421 * @is_add: Add control packet filter if True else remove
5422 * @stats: Structure to hold information on control filter counts
5423 * @cmd_details: pointer to command details structure or NULL
5425 * This command will Add or Remove control packet filter for a control VSI.
5426 * In return it will update the total number of perfect filter count in
5429 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5430 u8 *mac_addr, u16 ethtype, u16 flags,
5431 u16 vsi_seid, u16 queue, bool is_add,
5432 struct i40e_control_filter_stats *stats,
5433 struct i40e_asq_cmd_details *cmd_details)
5435 struct i40e_aq_desc desc;
5436 struct i40e_aqc_add_remove_control_packet_filter *cmd =
5437 (struct i40e_aqc_add_remove_control_packet_filter *)
5439 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5440 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5442 enum i40e_status_code status;
5445 return I40E_ERR_PARAM;
5448 i40e_fill_default_direct_cmd_desc(&desc,
5449 i40e_aqc_opc_add_control_packet_filter);
5450 cmd->queue = CPU_TO_LE16(queue);
5452 i40e_fill_default_direct_cmd_desc(&desc,
5453 i40e_aqc_opc_remove_control_packet_filter);
5457 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
5458 I40E_NONDMA_TO_NONDMA);
5460 cmd->etype = CPU_TO_LE16(ethtype);
5461 cmd->flags = CPU_TO_LE16(flags);
5462 cmd->seid = CPU_TO_LE16(vsi_seid);
5464 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5466 if (!status && stats) {
5467 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5468 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5469 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5470 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5477 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5478 * @hw: pointer to the hw struct
5479 * @seid: VSI seid to add ethertype filter from
5481 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5482 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5485 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5486 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5487 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5488 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5489 enum i40e_status_code status;
5491 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5492 seid, 0, true, NULL,
5495 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5499 * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5500 * @filters: list of cloud filters
5501 * @filter_count: length of list
5503 * There's an issue in the device where the Geneve VNI layout needs
5504 * to be shifted 1 byte over from the VxLAN VNI
5506 STATIC void i40e_fix_up_geneve_vni(
5507 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5510 struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters;
5513 for (i = 0; i < filter_count; i++) {
5517 tnl_type = (LE16_TO_CPU(f[i].flags) &
5518 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5519 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5520 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5521 ti = LE32_TO_CPU(f[i].tenant_id);
5522 f[i].tenant_id = CPU_TO_LE32(ti << 8);
5528 * i40e_aq_add_cloud_filters
5529 * @hw: pointer to the hardware structure
5530 * @seid: VSI seid to add cloud filters from
5531 * @filters: Buffer which contains the filters to be added
5532 * @filter_count: number of filters contained in the buffer
5534 * Set the cloud filters for a given VSI. The contents of the
5535 * i40e_aqc_add_remove_cloud_filters_element_data are filled
5536 * in by the caller of the function.
5539 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5541 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5544 struct i40e_aq_desc desc;
5545 struct i40e_aqc_add_remove_cloud_filters *cmd =
5546 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5547 enum i40e_status_code status;
5550 i40e_fill_default_direct_cmd_desc(&desc,
5551 i40e_aqc_opc_add_cloud_filters);
5553 buff_len = filter_count * sizeof(*filters);
5554 desc.datalen = CPU_TO_LE16(buff_len);
5555 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5556 cmd->num_filters = filter_count;
5557 cmd->seid = CPU_TO_LE16(seid);
5559 i40e_fix_up_geneve_vni(filters, filter_count);
5561 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5567 * i40e_aq_remove_cloud_filters
5568 * @hw: pointer to the hardware structure
5569 * @seid: VSI seid to remove cloud filters from
5570 * @filters: Buffer which contains the filters to be removed
5571 * @filter_count: number of filters contained in the buffer
5573 * Remove the cloud filters for a given VSI. The contents of the
5574 * i40e_aqc_add_remove_cloud_filters_element_data are filled
5575 * in by the caller of the function.
5578 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5580 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5583 struct i40e_aq_desc desc;
5584 struct i40e_aqc_add_remove_cloud_filters *cmd =
5585 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5586 enum i40e_status_code status;
5589 i40e_fill_default_direct_cmd_desc(&desc,
5590 i40e_aqc_opc_remove_cloud_filters);
5592 buff_len = filter_count * sizeof(*filters);
5593 desc.datalen = CPU_TO_LE16(buff_len);
5594 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5595 cmd->num_filters = filter_count;
5596 cmd->seid = CPU_TO_LE16(seid);
5598 i40e_fix_up_geneve_vni(filters, filter_count);
5600 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5606 * i40e_aq_alternate_write
5607 * @hw: pointer to the hardware structure
5608 * @reg_addr0: address of first dword to be read
5609 * @reg_val0: value to be written under 'reg_addr0'
5610 * @reg_addr1: address of second dword to be read
5611 * @reg_val1: value to be written under 'reg_addr1'
5613 * Write one or two dwords to alternate structure. Fields are indicated
5614 * by 'reg_addr0' and 'reg_addr1' register numbers.
5617 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5618 u32 reg_addr0, u32 reg_val0,
5619 u32 reg_addr1, u32 reg_val1)
5621 struct i40e_aq_desc desc;
5622 struct i40e_aqc_alternate_write *cmd_resp =
5623 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5624 enum i40e_status_code status;
5626 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5627 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5628 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5629 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5630 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5632 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5638 * i40e_aq_alternate_write_indirect
5639 * @hw: pointer to the hardware structure
5640 * @addr: address of a first register to be modified
5641 * @dw_count: number of alternate structure fields to write
5642 * @buffer: pointer to the command buffer
5644 * Write 'dw_count' dwords from 'buffer' to alternate structure
5645 * starting at 'addr'.
5648 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5649 u32 addr, u32 dw_count, void *buffer)
5651 struct i40e_aq_desc desc;
5652 struct i40e_aqc_alternate_ind_write *cmd_resp =
5653 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5654 enum i40e_status_code status;
5657 return I40E_ERR_PARAM;
5659 /* Indirect command */
5660 i40e_fill_default_direct_cmd_desc(&desc,
5661 i40e_aqc_opc_alternate_write_indirect);
5663 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5664 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5665 if (dw_count > (I40E_AQ_LARGE_BUF/4))
5666 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5668 cmd_resp->address = CPU_TO_LE32(addr);
5669 cmd_resp->length = CPU_TO_LE32(dw_count);
5671 status = i40e_asq_send_command(hw, &desc, buffer,
5672 I40E_LO_DWORD(4*dw_count), NULL);
5678 * i40e_aq_alternate_read
5679 * @hw: pointer to the hardware structure
5680 * @reg_addr0: address of first dword to be read
5681 * @reg_val0: pointer for data read from 'reg_addr0'
5682 * @reg_addr1: address of second dword to be read
5683 * @reg_val1: pointer for data read from 'reg_addr1'
5685 * Read one or two dwords from alternate structure. Fields are indicated
5686 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5687 * is not passed then only register at 'reg_addr0' is read.
5690 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5691 u32 reg_addr0, u32 *reg_val0,
5692 u32 reg_addr1, u32 *reg_val1)
5694 struct i40e_aq_desc desc;
5695 struct i40e_aqc_alternate_write *cmd_resp =
5696 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5697 enum i40e_status_code status;
5699 if (reg_val0 == NULL)
5700 return I40E_ERR_PARAM;
5702 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5703 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5704 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5706 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5708 if (status == I40E_SUCCESS) {
5709 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5711 if (reg_val1 != NULL)
5712 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5719 * i40e_aq_alternate_read_indirect
5720 * @hw: pointer to the hardware structure
5721 * @addr: address of the alternate structure field
5722 * @dw_count: number of alternate structure fields to read
5723 * @buffer: pointer to the command buffer
5725 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5726 * place them in 'buffer'. The buffer should be allocated by caller.
5729 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5730 u32 addr, u32 dw_count, void *buffer)
5732 struct i40e_aq_desc desc;
5733 struct i40e_aqc_alternate_ind_write *cmd_resp =
5734 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5735 enum i40e_status_code status;
5738 return I40E_ERR_PARAM;
5740 /* Indirect command */
5741 i40e_fill_default_direct_cmd_desc(&desc,
5742 i40e_aqc_opc_alternate_read_indirect);
5744 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5745 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5746 if (dw_count > (I40E_AQ_LARGE_BUF/4))
5747 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5749 cmd_resp->address = CPU_TO_LE32(addr);
5750 cmd_resp->length = CPU_TO_LE32(dw_count);
5752 status = i40e_asq_send_command(hw, &desc, buffer,
5753 I40E_LO_DWORD(4*dw_count), NULL);
5759 * i40e_aq_alternate_clear
5760 * @hw: pointer to the HW structure.
5762 * Clear the alternate structures of the port from which the function
5766 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5768 struct i40e_aq_desc desc;
5769 enum i40e_status_code status;
5771 i40e_fill_default_direct_cmd_desc(&desc,
5772 i40e_aqc_opc_alternate_clear_port);
5774 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5780 * i40e_aq_alternate_write_done
5781 * @hw: pointer to the HW structure.
5782 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
5783 * @reset_needed: indicates the SW should trigger GLOBAL reset
5785 * Indicates to the FW that alternate structures have been changed.
5788 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
5789 u8 bios_mode, bool *reset_needed)
5791 struct i40e_aq_desc desc;
5792 struct i40e_aqc_alternate_write_done *cmd =
5793 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5794 enum i40e_status_code status;
5796 if (reset_needed == NULL)
5797 return I40E_ERR_PARAM;
5799 i40e_fill_default_direct_cmd_desc(&desc,
5800 i40e_aqc_opc_alternate_write_done);
5802 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
5804 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5805 if (!status && reset_needed)
5806 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
5807 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
5813 * i40e_aq_set_oem_mode
5814 * @hw: pointer to the HW structure.
5815 * @oem_mode: the OEM mode to be used
5817 * Sets the device to a specific operating mode. Currently the only supported
5818 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
5821 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
5824 struct i40e_aq_desc desc;
5825 struct i40e_aqc_alternate_write_done *cmd =
5826 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5827 enum i40e_status_code status;
5829 i40e_fill_default_direct_cmd_desc(&desc,
5830 i40e_aqc_opc_alternate_set_mode);
5832 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
5834 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5840 * i40e_aq_resume_port_tx
5841 * @hw: pointer to the hardware structure
5842 * @cmd_details: pointer to command details structure or NULL
5844 * Resume port's Tx traffic
5846 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
5847 struct i40e_asq_cmd_details *cmd_details)
5849 struct i40e_aq_desc desc;
5850 enum i40e_status_code status;
5852 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
5854 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5860 * i40e_set_pci_config_data - store PCI bus info
5861 * @hw: pointer to hardware structure
5862 * @link_status: the link status word from PCI config space
5864 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
5866 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
5868 hw->bus.type = i40e_bus_type_pci_express;
5870 switch (link_status & I40E_PCI_LINK_WIDTH) {
5871 case I40E_PCI_LINK_WIDTH_1:
5872 hw->bus.width = i40e_bus_width_pcie_x1;
5874 case I40E_PCI_LINK_WIDTH_2:
5875 hw->bus.width = i40e_bus_width_pcie_x2;
5877 case I40E_PCI_LINK_WIDTH_4:
5878 hw->bus.width = i40e_bus_width_pcie_x4;
5880 case I40E_PCI_LINK_WIDTH_8:
5881 hw->bus.width = i40e_bus_width_pcie_x8;
5884 hw->bus.width = i40e_bus_width_unknown;
5888 switch (link_status & I40E_PCI_LINK_SPEED) {
5889 case I40E_PCI_LINK_SPEED_2500:
5890 hw->bus.speed = i40e_bus_speed_2500;
5892 case I40E_PCI_LINK_SPEED_5000:
5893 hw->bus.speed = i40e_bus_speed_5000;
5895 case I40E_PCI_LINK_SPEED_8000:
5896 hw->bus.speed = i40e_bus_speed_8000;
5899 hw->bus.speed = i40e_bus_speed_unknown;
5905 * i40e_aq_debug_dump
5906 * @hw: pointer to the hardware structure
5907 * @cluster_id: specific cluster to dump
5908 * @table_id: table id within cluster
5909 * @start_index: index of line in the block to read
5910 * @buff_size: dump buffer size
5911 * @buff: dump buffer
5912 * @ret_buff_size: actual buffer size returned
5913 * @ret_next_table: next block to read
5914 * @ret_next_index: next index to read
5916 * Dump internal FW/HW data for debug purposes.
5919 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
5920 u8 table_id, u32 start_index, u16 buff_size,
5921 void *buff, u16 *ret_buff_size,
5922 u8 *ret_next_table, u32 *ret_next_index,
5923 struct i40e_asq_cmd_details *cmd_details)
5925 struct i40e_aq_desc desc;
5926 struct i40e_aqc_debug_dump_internals *cmd =
5927 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5928 struct i40e_aqc_debug_dump_internals *resp =
5929 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5930 enum i40e_status_code status;
5932 if (buff_size == 0 || !buff)
5933 return I40E_ERR_PARAM;
5935 i40e_fill_default_direct_cmd_desc(&desc,
5936 i40e_aqc_opc_debug_dump_internals);
5937 /* Indirect Command */
5938 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5939 if (buff_size > I40E_AQ_LARGE_BUF)
5940 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5942 cmd->cluster_id = cluster_id;
5943 cmd->table_id = table_id;
5944 cmd->idx = CPU_TO_LE32(start_index);
5946 desc.datalen = CPU_TO_LE16(buff_size);
5948 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5950 if (ret_buff_size != NULL)
5951 *ret_buff_size = LE16_TO_CPU(desc.datalen);
5952 if (ret_next_table != NULL)
5953 *ret_next_table = resp->table_id;
5954 if (ret_next_index != NULL)
5955 *ret_next_index = LE32_TO_CPU(resp->idx);
5962 * i40e_read_bw_from_alt_ram
5963 * @hw: pointer to the hardware structure
5964 * @max_bw: pointer for max_bw read
5965 * @min_bw: pointer for min_bw read
5966 * @min_valid: pointer for bool that is true if min_bw is a valid value
5967 * @max_valid: pointer for bool that is true if max_bw is a valid value
5969 * Read bw from the alternate ram for the given pf
5971 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
5972 u32 *max_bw, u32 *min_bw,
5973 bool *min_valid, bool *max_valid)
5975 enum i40e_status_code status;
5976 u32 max_bw_addr, min_bw_addr;
5978 /* Calculate the address of the min/max bw registers */
5979 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5980 I40E_ALT_STRUCT_MAX_BW_OFFSET +
5981 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5982 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5983 I40E_ALT_STRUCT_MIN_BW_OFFSET +
5984 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5986 /* Read the bandwidths from alt ram */
5987 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
5988 min_bw_addr, min_bw);
5990 if (*min_bw & I40E_ALT_BW_VALID_MASK)
5995 if (*max_bw & I40E_ALT_BW_VALID_MASK)
6004 * i40e_aq_configure_partition_bw
6005 * @hw: pointer to the hardware structure
6006 * @bw_data: Buffer holding valid pfs and bw limits
6007 * @cmd_details: pointer to command details
6009 * Configure partitions guaranteed/max bw
6011 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6012 struct i40e_aqc_configure_partition_bw_data *bw_data,
6013 struct i40e_asq_cmd_details *cmd_details)
6015 enum i40e_status_code status;
6016 struct i40e_aq_desc desc;
6017 u16 bwd_size = sizeof(*bw_data);
6019 i40e_fill_default_direct_cmd_desc(&desc,
6020 i40e_aqc_opc_configure_partition_bw);
6022 /* Indirect command */
6023 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6024 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6026 desc.datalen = CPU_TO_LE16(bwd_size);
6028 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6034 * i40e_read_phy_register_clause22
6035 * @hw: pointer to the HW structure
6036 * @reg: register address in the page
6037 * @phy_adr: PHY address on MDIO interface
6038 * @value: PHY register value
6040 * Reads specified PHY register value
6042 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
6043 u16 reg, u8 phy_addr, u16 *value)
6045 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6046 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6050 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6051 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6052 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
6053 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6054 (I40E_GLGEN_MSCA_MDICMD_MASK);
6055 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6057 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6058 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6059 status = I40E_SUCCESS;
6062 i40e_usec_delay(10);
6067 i40e_debug(hw, I40E_DEBUG_PHY,
6068 "PHY: Can't write command to external PHY.\n");
6070 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6071 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6072 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6079 * i40e_write_phy_register_clause22
6080 * @hw: pointer to the HW structure
6081 * @reg: register address in the page
6082 * @phy_adr: PHY address on MDIO interface
6083 * @value: PHY register value
6085 * Writes specified PHY register value
6087 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6088 u16 reg, u8 phy_addr, u16 value)
6090 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6091 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6095 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6096 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6098 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6099 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6100 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6101 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6102 (I40E_GLGEN_MSCA_MDICMD_MASK);
6104 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6106 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6107 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6108 status = I40E_SUCCESS;
6111 i40e_usec_delay(10);
6119 * i40e_read_phy_register_clause45
6120 * @hw: pointer to the HW structure
6121 * @page: registers page number
6122 * @reg: register address in the page
6123 * @phy_adr: PHY address on MDIO interface
6124 * @value: PHY register value
6126 * Reads specified PHY register value
6128 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6129 u8 page, u16 reg, u8 phy_addr, u16 *value)
6131 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6134 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6136 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6137 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6138 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6139 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6140 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6141 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6142 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6143 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6145 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6146 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6147 status = I40E_SUCCESS;
6150 i40e_usec_delay(10);
6155 i40e_debug(hw, I40E_DEBUG_PHY,
6156 "PHY: Can't write command to external PHY.\n");
6160 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6161 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6162 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6163 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6164 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6165 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6166 status = I40E_ERR_TIMEOUT;
6168 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6170 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6171 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6172 status = I40E_SUCCESS;
6175 i40e_usec_delay(10);
6180 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6181 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6182 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6184 i40e_debug(hw, I40E_DEBUG_PHY,
6185 "PHY: Can't read register value from external PHY.\n");
6193 * i40e_write_phy_register_clause45
6194 * @hw: pointer to the HW structure
6195 * @page: registers page number
6196 * @reg: register address in the page
6197 * @phy_adr: PHY address on MDIO interface
6198 * @value: PHY register value
6200 * Writes value to specified PHY register
6202 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6203 u8 page, u16 reg, u8 phy_addr, u16 value)
6205 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6208 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6210 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6211 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6212 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6213 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6214 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6215 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6216 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6217 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6219 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6220 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6221 status = I40E_SUCCESS;
6224 i40e_usec_delay(10);
6228 i40e_debug(hw, I40E_DEBUG_PHY,
6229 "PHY: Can't write command to external PHY.\n");
6233 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6234 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6236 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6237 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6238 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6239 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6240 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6241 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6242 status = I40E_ERR_TIMEOUT;
6244 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6246 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6247 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6248 status = I40E_SUCCESS;
6251 i40e_usec_delay(10);
6260 * i40e_write_phy_register
6261 * @hw: pointer to the HW structure
6262 * @page: registers page number
6263 * @reg: register address in the page
6264 * @phy_adr: PHY address on MDIO interface
6265 * @value: PHY register value
6267 * Writes value to specified PHY register
6269 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6270 u8 page, u16 reg, u8 phy_addr, u16 value)
6272 enum i40e_status_code status;
6274 switch (hw->device_id) {
6275 case I40E_DEV_ID_1G_BASE_T_X722:
6276 status = i40e_write_phy_register_clause22(hw,
6277 reg, phy_addr, value);
6279 case I40E_DEV_ID_10G_BASE_T:
6280 case I40E_DEV_ID_10G_BASE_T4:
6281 case I40E_DEV_ID_10G_BASE_T_X722:
6282 case I40E_DEV_ID_25G_B:
6283 case I40E_DEV_ID_25G_SFP28:
6284 status = i40e_write_phy_register_clause45(hw,
6285 page, reg, phy_addr, value);
6288 status = I40E_ERR_UNKNOWN_PHY;
6296 * i40e_read_phy_register
6297 * @hw: pointer to the HW structure
6298 * @page: registers page number
6299 * @reg: register address in the page
6300 * @phy_adr: PHY address on MDIO interface
6301 * @value: PHY register value
6303 * Reads specified PHY register value
6305 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6306 u8 page, u16 reg, u8 phy_addr, u16 *value)
6308 enum i40e_status_code status;
6310 switch (hw->device_id) {
6311 case I40E_DEV_ID_1G_BASE_T_X722:
6312 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6315 case I40E_DEV_ID_10G_BASE_T:
6316 case I40E_DEV_ID_10G_BASE_T4:
6317 case I40E_DEV_ID_10G_BASE_T_X722:
6318 case I40E_DEV_ID_25G_B:
6319 case I40E_DEV_ID_25G_SFP28:
6320 status = i40e_read_phy_register_clause45(hw, page, reg,
6324 status = I40E_ERR_UNKNOWN_PHY;
6332 * i40e_get_phy_address
6333 * @hw: pointer to the HW structure
6334 * @dev_num: PHY port num that address we want
6335 * @phy_addr: Returned PHY address
6337 * Gets PHY address for current port
6339 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6341 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6342 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6344 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6348 * i40e_blink_phy_led
6349 * @hw: pointer to the HW structure
6350 * @time: time how long led will blinks in secs
6351 * @interval: gap between LED on and off in msecs
6353 * Blinks PHY link LED
6355 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6356 u32 time, u32 interval)
6358 enum i40e_status_code status = I40E_SUCCESS;
6363 u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6367 i = rd32(hw, I40E_PFGEN_PORTNUM);
6368 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6369 phy_addr = i40e_get_phy_address(hw, port_num);
6371 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6373 status = i40e_read_phy_register_clause45(hw,
6374 I40E_PHY_COM_REG_PAGE,
6378 goto phy_blinking_end;
6380 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6382 status = i40e_write_phy_register_clause45(hw,
6383 I40E_PHY_COM_REG_PAGE,
6387 goto phy_blinking_end;
6392 if (time > 0 && interval > 0) {
6393 for (i = 0; i < time * 1000; i += interval) {
6394 status = i40e_read_phy_register_clause45(hw,
6395 I40E_PHY_COM_REG_PAGE,
6396 led_addr, phy_addr, &led_reg);
6398 goto restore_config;
6399 if (led_reg & I40E_PHY_LED_MANUAL_ON)
6402 led_reg = I40E_PHY_LED_MANUAL_ON;
6403 status = i40e_write_phy_register_clause45(hw,
6404 I40E_PHY_COM_REG_PAGE,
6405 led_addr, phy_addr, led_reg);
6407 goto restore_config;
6408 i40e_msec_delay(interval);
6413 status = i40e_write_phy_register_clause45(hw,
6414 I40E_PHY_COM_REG_PAGE,
6415 led_addr, phy_addr, led_ctl);
6422 * i40e_led_get_phy - return current on/off mode
6423 * @hw: pointer to the hw struct
6424 * @led_addr: address of led register to use
6425 * @val: original value of register to use
6428 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6431 enum i40e_status_code status = I40E_SUCCESS;
6439 temp_addr = I40E_PHY_LED_PROV_REG_1;
6440 i = rd32(hw, I40E_PFGEN_PORTNUM);
6441 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6442 phy_addr = i40e_get_phy_address(hw, port_num);
6444 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6446 status = i40e_read_phy_register_clause45(hw,
6447 I40E_PHY_COM_REG_PAGE,
6448 temp_addr, phy_addr,
6453 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6454 *led_addr = temp_addr;
6463 * @hw: pointer to the HW structure
6464 * @on: true or false
6465 * @mode: original val plus bit for set or ignore
6466 * Set led's on or off when controlled by the PHY
6469 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6470 u16 led_addr, u32 mode)
6472 enum i40e_status_code status = I40E_SUCCESS;
6479 i = rd32(hw, I40E_PFGEN_PORTNUM);
6480 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6481 phy_addr = i40e_get_phy_address(hw, port_num);
6482 status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6483 led_addr, phy_addr, &led_reg);
6487 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6489 status = i40e_write_phy_register_clause45(hw,
6490 I40E_PHY_COM_REG_PAGE,
6496 status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6497 led_addr, phy_addr, &led_reg);
6499 goto restore_config;
6501 led_reg = I40E_PHY_LED_MANUAL_ON;
6504 status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6505 led_addr, phy_addr, led_reg);
6507 goto restore_config;
6508 if (mode & I40E_PHY_LED_MODE_ORIG) {
6509 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6510 status = i40e_write_phy_register_clause45(hw,
6511 I40E_PHY_COM_REG_PAGE,
6512 led_addr, phy_addr, led_ctl);
6516 status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6517 led_addr, phy_addr, led_ctl);
6520 #endif /* PF_DRIVER */
6523 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6524 * @hw: pointer to the hw struct
6525 * @reg_addr: register address
6526 * @reg_val: ptr to register value
6527 * @cmd_details: pointer to command details structure or NULL
6529 * Use the firmware to read the Rx control register,
6530 * especially useful if the Rx unit is under heavy pressure
6532 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6533 u32 reg_addr, u32 *reg_val,
6534 struct i40e_asq_cmd_details *cmd_details)
6536 struct i40e_aq_desc desc;
6537 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
6538 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6539 enum i40e_status_code status;
6541 if (reg_val == NULL)
6542 return I40E_ERR_PARAM;
6544 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
6546 cmd_resp->address = CPU_TO_LE32(reg_addr);
6548 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6550 if (status == I40E_SUCCESS)
6551 *reg_val = LE32_TO_CPU(cmd_resp->value);
6557 * i40e_read_rx_ctl - read from an Rx control register
6558 * @hw: pointer to the hw struct
6559 * @reg_addr: register address
6561 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
6563 enum i40e_status_code status = I40E_SUCCESS;
6568 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6569 if (!use_register) {
6571 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
6572 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6579 /* if the AQ access failed, try the old-fashioned way */
6580 if (status || use_register)
6581 val = rd32(hw, reg_addr);
6587 * i40e_aq_rx_ctl_write_register
6588 * @hw: pointer to the hw struct
6589 * @reg_addr: register address
6590 * @reg_val: register value
6591 * @cmd_details: pointer to command details structure or NULL
6593 * Use the firmware to write to an Rx control register,
6594 * especially useful if the Rx unit is under heavy pressure
6596 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
6597 u32 reg_addr, u32 reg_val,
6598 struct i40e_asq_cmd_details *cmd_details)
6600 struct i40e_aq_desc desc;
6601 struct i40e_aqc_rx_ctl_reg_read_write *cmd =
6602 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6603 enum i40e_status_code status;
6605 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
6607 cmd->address = CPU_TO_LE32(reg_addr);
6608 cmd->value = CPU_TO_LE32(reg_val);
6610 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6616 * i40e_write_rx_ctl - write to an Rx control register
6617 * @hw: pointer to the hw struct
6618 * @reg_addr: register address
6619 * @reg_val: register value
6621 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
6623 enum i40e_status_code status = I40E_SUCCESS;
6627 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6628 if (!use_register) {
6630 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
6632 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6639 /* if the AQ access failed, try the old-fashioned way */
6640 if (status || use_register)
6641 wr32(hw, reg_addr, reg_val);
6646 * i40e_aq_send_msg_to_pf
6647 * @hw: pointer to the hardware structure
6648 * @v_opcode: opcodes for VF-PF communication
6649 * @v_retval: return error code
6650 * @msg: pointer to the msg buffer
6651 * @msglen: msg length
6652 * @cmd_details: pointer to command details
6654 * Send message to PF driver using admin queue. By default, this message
6655 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
6656 * completion before returning.
6658 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
6659 enum i40e_virtchnl_ops v_opcode,
6660 enum i40e_status_code v_retval,
6661 u8 *msg, u16 msglen,
6662 struct i40e_asq_cmd_details *cmd_details)
6664 struct i40e_aq_desc desc;
6665 struct i40e_asq_cmd_details details;
6666 enum i40e_status_code status;
6668 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
6669 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
6670 desc.cookie_high = CPU_TO_LE32(v_opcode);
6671 desc.cookie_low = CPU_TO_LE32(v_retval);
6673 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
6674 | I40E_AQ_FLAG_RD));
6675 if (msglen > I40E_AQ_LARGE_BUF)
6676 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6677 desc.datalen = CPU_TO_LE16(msglen);
6680 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
6681 details.async = true;
6682 cmd_details = &details;
6684 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
6685 msglen, cmd_details);
6690 * i40e_vf_parse_hw_config
6691 * @hw: pointer to the hardware structure
6692 * @msg: pointer to the virtual channel VF resource structure
6694 * Given a VF resource message from the PF, populate the hw struct
6695 * with appropriate information.
6697 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
6698 struct i40e_virtchnl_vf_resource *msg)
6700 struct i40e_virtchnl_vsi_resource *vsi_res;
6703 vsi_res = &msg->vsi_res[0];
6705 hw->dev_caps.num_vsis = msg->num_vsis;
6706 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
6707 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
6708 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
6709 hw->dev_caps.dcb = msg->vf_offload_flags &
6710 I40E_VIRTCHNL_VF_OFFLOAD_L2;
6711 hw->dev_caps.fcoe = (msg->vf_offload_flags &
6712 I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
6713 hw->dev_caps.iwarp = (msg->vf_offload_flags &
6714 I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
6715 for (i = 0; i < msg->num_vsis; i++) {
6716 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
6717 i40e_memcpy(hw->mac.perm_addr,
6718 vsi_res->default_mac_addr,
6719 I40E_ETH_LENGTH_OF_ADDRESS,
6720 I40E_NONDMA_TO_NONDMA);
6721 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
6722 I40E_ETH_LENGTH_OF_ADDRESS,
6723 I40E_NONDMA_TO_NONDMA);
6731 * @hw: pointer to the hardware structure
6733 * Send a VF_RESET message to the PF. Does not wait for response from PF
6734 * as none will be forthcoming. Immediately after calling this function,
6735 * the admin queue should be shut down and (optionally) reinitialized.
6737 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
6739 return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
6740 I40E_SUCCESS, NULL, 0, NULL);
6742 #endif /* VF_DRIVER */
6746 * i40e_aq_set_arp_proxy_config
6747 * @hw: pointer to the HW structure
6748 * @proxy_config - pointer to proxy config command table struct
6749 * @cmd_details: pointer to command details
6751 * Set ARP offload parameters from pre-populated
6752 * i40e_aqc_arp_proxy_data struct
6754 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
6755 struct i40e_aqc_arp_proxy_data *proxy_config,
6756 struct i40e_asq_cmd_details *cmd_details)
6758 struct i40e_aq_desc desc;
6759 enum i40e_status_code status;
6762 return I40E_ERR_PARAM;
6764 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
6766 desc.params.external.addr_high =
6767 CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
6768 desc.params.external.addr_low =
6769 CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
6771 status = i40e_asq_send_command(hw, &desc, proxy_config,
6772 sizeof(struct i40e_aqc_arp_proxy_data),
6779 * i40e_aq_opc_set_ns_proxy_table_entry
6780 * @hw: pointer to the HW structure
6781 * @ns_proxy_table_entry: pointer to NS table entry command struct
6782 * @cmd_details: pointer to command details
6784 * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
6785 * from pre-populated i40e_aqc_ns_proxy_data struct
6787 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
6788 struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
6789 struct i40e_asq_cmd_details *cmd_details)
6791 struct i40e_aq_desc desc;
6792 enum i40e_status_code status;
6794 if (!ns_proxy_table_entry)
6795 return I40E_ERR_PARAM;
6797 i40e_fill_default_direct_cmd_desc(&desc,
6798 i40e_aqc_opc_set_ns_proxy_table_entry);
6800 desc.params.external.addr_high =
6801 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
6802 desc.params.external.addr_low =
6803 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
6805 status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
6806 sizeof(struct i40e_aqc_ns_proxy_data),
6813 * i40e_aq_set_clear_wol_filter
6814 * @hw: pointer to the hw struct
6815 * @filter_index: index of filter to modify (0-7)
6816 * @filter: buffer containing filter to be set
6817 * @set_filter: true to set filter, false to clear filter
6818 * @no_wol_tco: if true, pass through packets cannot cause wake-up
6819 * if false, pass through packets may cause wake-up
6820 * @filter_valid: true if filter action is valid
6821 * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
6822 * @cmd_details: pointer to command details structure or NULL
6824 * Set or clear WoL filter for port attached to the PF
6826 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
6828 struct i40e_aqc_set_wol_filter_data *filter,
6829 bool set_filter, bool no_wol_tco,
6830 bool filter_valid, bool no_wol_tco_valid,
6831 struct i40e_asq_cmd_details *cmd_details)
6833 struct i40e_aq_desc desc;
6834 struct i40e_aqc_set_wol_filter *cmd =
6835 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
6836 enum i40e_status_code status;
6838 u16 valid_flags = 0;
6841 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
6843 if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
6844 return I40E_ERR_PARAM;
6845 cmd->filter_index = CPU_TO_LE16(filter_index);
6849 return I40E_ERR_PARAM;
6850 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
6851 buff_len = sizeof(*filter);
6854 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
6855 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
6858 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
6859 if (no_wol_tco_valid)
6860 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
6861 cmd->valid_flags = CPU_TO_LE16(valid_flags);
6863 cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
6864 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
6866 status = i40e_asq_send_command(hw, &desc, filter,
6867 buff_len, cmd_details);
6873 * i40e_aq_get_wake_event_reason
6874 * @hw: pointer to the hw struct
6875 * @wake_reason: return value, index of matching filter
6876 * @cmd_details: pointer to command details structure or NULL
6878 * Get information for the reason of a Wake Up event
6880 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
6882 struct i40e_asq_cmd_details *cmd_details)
6884 struct i40e_aq_desc desc;
6885 struct i40e_aqc_get_wake_reason_completion *resp =
6886 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
6887 enum i40e_status_code status;
6889 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
6891 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6893 if (status == I40E_SUCCESS)
6894 *wake_reason = LE16_TO_CPU(resp->wake_reason);
6899 #endif /* X722_SUPPORT */