drivers/net/i40e/base/i40e_common.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "i40e_type.h"
  35 #include "i40e_adminq.h"
  36 #include "i40e_prototype.h"
  37 #include "i40e_virtchnl.h"
  38
  39
  40 /**
  41  * i40e_set_mac_type - Sets MAC type
  42  * @hw: pointer to the HW structure
  43  *
  44  * This function sets the mac type of the adapter based on the
  45  * vendor ID and device ID stored in the hw structure.
  46  **/
  47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  49 #else
  50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  51 #endif
  52 {
  53         enum i40e_status_code status = I40E_SUCCESS;
  54
  55         DEBUGFUNC("i40e_set_mac_type\n");
  56
  57         if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
  58                 switch (hw->device_id) {
  59                 case I40E_DEV_ID_SFP_XL710:
  60                 case I40E_DEV_ID_QEMU:
  61                 case I40E_DEV_ID_KX_B:
  62                 case I40E_DEV_ID_KX_C:
  63                 case I40E_DEV_ID_QSFP_A:
  64                 case I40E_DEV_ID_QSFP_B:
  65                 case I40E_DEV_ID_QSFP_C:
  66                 case I40E_DEV_ID_10G_BASE_T:
  67                 case I40E_DEV_ID_10G_BASE_T4:
  68                 case I40E_DEV_ID_20G_KR2:
  69                 case I40E_DEV_ID_20G_KR2_A:
  70                 case I40E_DEV_ID_25G_B:
  71                 case I40E_DEV_ID_25G_SFP28:
  72                         hw->mac.type = I40E_MAC_XL710;
  73                         break;
  74 #ifdef X722_SUPPORT
  75 #ifdef X722_A0_SUPPORT
  76                 case I40E_DEV_ID_X722_A0:
  77 #endif
  78                 case I40E_DEV_ID_KX_X722:
  79                 case I40E_DEV_ID_QSFP_X722:
  80                 case I40E_DEV_ID_SFP_X722:
  81                 case I40E_DEV_ID_1G_BASE_T_X722:
  82                 case I40E_DEV_ID_10G_BASE_T_X722:
  83                 case I40E_DEV_ID_SFP_I_X722:
  84                         hw->mac.type = I40E_MAC_X722;
  85                         break;
  86 #endif
  87 #ifdef X722_SUPPORT
  88 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  89                 case I40E_DEV_ID_X722_VF:
  90                 case I40E_DEV_ID_X722_VF_HV:
  91 #ifdef X722_A0_SUPPORT
  92                 case I40E_DEV_ID_X722_A0_VF:
  93 #endif
  94                         hw->mac.type = I40E_MAC_X722_VF;
  95                         break;
  96 #endif /* INTEGRATED_VF || VF_DRIVER */
  97 #endif /* X722_SUPPORT */
  98 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  99                 case I40E_DEV_ID_VF:
 100                 case I40E_DEV_ID_VF_HV:
 101                         hw->mac.type = I40E_MAC_VF;
 102                         break;
 103 #endif
 104                 default:
 105                         hw->mac.type = I40E_MAC_GENERIC;
 106                         break;
 107                 }
 108         } else {
 109                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
 110         }
 111
 112         DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
 113                   hw->mac.type, status);
 114         return status;
 115 }
 116
 117 #ifndef I40E_NDIS_SUPPORT
 118 /**
 119  * i40e_aq_str - convert AQ err code to a string
 120  * @hw: pointer to the HW structure
 121  * @aq_err: the AQ error code to convert
 122  **/
 123 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
 124 {
 125         switch (aq_err) {
 126         case I40E_AQ_RC_OK:
 127                 return "OK";
 128         case I40E_AQ_RC_EPERM:
 129                 return "I40E_AQ_RC_EPERM";
 130         case I40E_AQ_RC_ENOENT:
 131                 return "I40E_AQ_RC_ENOENT";
 132         case I40E_AQ_RC_ESRCH:
 133                 return "I40E_AQ_RC_ESRCH";
 134         case I40E_AQ_RC_EINTR:
 135                 return "I40E_AQ_RC_EINTR";
 136         case I40E_AQ_RC_EIO:
 137                 return "I40E_AQ_RC_EIO";
 138         case I40E_AQ_RC_ENXIO:
 139                 return "I40E_AQ_RC_ENXIO";
 140         case I40E_AQ_RC_E2BIG:
 141                 return "I40E_AQ_RC_E2BIG";
 142         case I40E_AQ_RC_EAGAIN:
 143                 return "I40E_AQ_RC_EAGAIN";
 144         case I40E_AQ_RC_ENOMEM:
 145                 return "I40E_AQ_RC_ENOMEM";
 146         case I40E_AQ_RC_EACCES:
 147                 return "I40E_AQ_RC_EACCES";
 148         case I40E_AQ_RC_EFAULT:
 149                 return "I40E_AQ_RC_EFAULT";
 150         case I40E_AQ_RC_EBUSY:
 151                 return "I40E_AQ_RC_EBUSY";
 152         case I40E_AQ_RC_EEXIST:
 153                 return "I40E_AQ_RC_EEXIST";
 154         case I40E_AQ_RC_EINVAL:
 155                 return "I40E_AQ_RC_EINVAL";
 156         case I40E_AQ_RC_ENOTTY:
 157                 return "I40E_AQ_RC_ENOTTY";
 158         case I40E_AQ_RC_ENOSPC:
 159                 return "I40E_AQ_RC_ENOSPC";
 160         case I40E_AQ_RC_ENOSYS:
 161                 return "I40E_AQ_RC_ENOSYS";
 162         case I40E_AQ_RC_ERANGE:
 163                 return "I40E_AQ_RC_ERANGE";
 164         case I40E_AQ_RC_EFLUSHED:
 165                 return "I40E_AQ_RC_EFLUSHED";
 166         case I40E_AQ_RC_BAD_ADDR:
 167                 return "I40E_AQ_RC_BAD_ADDR";
 168         case I40E_AQ_RC_EMODE:
 169                 return "I40E_AQ_RC_EMODE";
 170         case I40E_AQ_RC_EFBIG:
 171                 return "I40E_AQ_RC_EFBIG";
 172         }
 173
 174         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 175         return hw->err_str;
 176 }
 177
 178 /**
 179  * i40e_stat_str - convert status err code to a string
 180  * @hw: pointer to the HW structure
 181  * @stat_err: the status error code to convert
 182  **/
 183 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
 184 {
 185         switch (stat_err) {
 186         case I40E_SUCCESS:
 187                 return "OK";
 188         case I40E_ERR_NVM:
 189                 return "I40E_ERR_NVM";
 190         case I40E_ERR_NVM_CHECKSUM:
 191                 return "I40E_ERR_NVM_CHECKSUM";
 192         case I40E_ERR_PHY:
 193                 return "I40E_ERR_PHY";
 194         case I40E_ERR_CONFIG:
 195                 return "I40E_ERR_CONFIG";
 196         case I40E_ERR_PARAM:
 197                 return "I40E_ERR_PARAM";
 198         case I40E_ERR_MAC_TYPE:
 199                 return "I40E_ERR_MAC_TYPE";
 200         case I40E_ERR_UNKNOWN_PHY:
 201                 return "I40E_ERR_UNKNOWN_PHY";
 202         case I40E_ERR_LINK_SETUP:
 203                 return "I40E_ERR_LINK_SETUP";
 204         case I40E_ERR_ADAPTER_STOPPED:
 205                 return "I40E_ERR_ADAPTER_STOPPED";
 206         case I40E_ERR_INVALID_MAC_ADDR:
 207                 return "I40E_ERR_INVALID_MAC_ADDR";
 208         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 209                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 210         case I40E_ERR_MASTER_REQUESTS_PENDING:
 211                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 212         case I40E_ERR_INVALID_LINK_SETTINGS:
 213                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 214         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 215                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 216         case I40E_ERR_RESET_FAILED:
 217                 return "I40E_ERR_RESET_FAILED";
 218         case I40E_ERR_SWFW_SYNC:
 219                 return "I40E_ERR_SWFW_SYNC";
 220         case I40E_ERR_NO_AVAILABLE_VSI:
 221                 return "I40E_ERR_NO_AVAILABLE_VSI";
 222         case I40E_ERR_NO_MEMORY:
 223                 return "I40E_ERR_NO_MEMORY";
 224         case I40E_ERR_BAD_PTR:
 225                 return "I40E_ERR_BAD_PTR";
 226         case I40E_ERR_RING_FULL:
 227                 return "I40E_ERR_RING_FULL";
 228         case I40E_ERR_INVALID_PD_ID:
 229                 return "I40E_ERR_INVALID_PD_ID";
 230         case I40E_ERR_INVALID_QP_ID:
 231                 return "I40E_ERR_INVALID_QP_ID";
 232         case I40E_ERR_INVALID_CQ_ID:
 233                 return "I40E_ERR_INVALID_CQ_ID";
 234         case I40E_ERR_INVALID_CEQ_ID:
 235                 return "I40E_ERR_INVALID_CEQ_ID";
 236         case I40E_ERR_INVALID_AEQ_ID:
 237                 return "I40E_ERR_INVALID_AEQ_ID";
 238         case I40E_ERR_INVALID_SIZE:
 239                 return "I40E_ERR_INVALID_SIZE";
 240         case I40E_ERR_INVALID_ARP_INDEX:
 241                 return "I40E_ERR_INVALID_ARP_INDEX";
 242         case I40E_ERR_INVALID_FPM_FUNC_ID:
 243                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 244         case I40E_ERR_QP_INVALID_MSG_SIZE:
 245                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 246         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 247                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 248         case I40E_ERR_INVALID_FRAG_COUNT:
 249                 return "I40E_ERR_INVALID_FRAG_COUNT";
 250         case I40E_ERR_QUEUE_EMPTY:
 251                 return "I40E_ERR_QUEUE_EMPTY";
 252         case I40E_ERR_INVALID_ALIGNMENT:
 253                 return "I40E_ERR_INVALID_ALIGNMENT";
 254         case I40E_ERR_FLUSHED_QUEUE:
 255                 return "I40E_ERR_FLUSHED_QUEUE";
 256         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 257                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 258         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 259                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 260         case I40E_ERR_TIMEOUT:
 261                 return "I40E_ERR_TIMEOUT";
 262         case I40E_ERR_OPCODE_MISMATCH:
 263                 return "I40E_ERR_OPCODE_MISMATCH";
 264         case I40E_ERR_CQP_COMPL_ERROR:
 265                 return "I40E_ERR_CQP_COMPL_ERROR";
 266         case I40E_ERR_INVALID_VF_ID:
 267                 return "I40E_ERR_INVALID_VF_ID";
 268         case I40E_ERR_INVALID_HMCFN_ID:
 269                 return "I40E_ERR_INVALID_HMCFN_ID";
 270         case I40E_ERR_BACKING_PAGE_ERROR:
 271                 return "I40E_ERR_BACKING_PAGE_ERROR";
 272         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 273                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 274         case I40E_ERR_INVALID_PBLE_INDEX:
 275                 return "I40E_ERR_INVALID_PBLE_INDEX";
 276         case I40E_ERR_INVALID_SD_INDEX:
 277                 return "I40E_ERR_INVALID_SD_INDEX";
 278         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 279                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 280         case I40E_ERR_INVALID_SD_TYPE:
 281                 return "I40E_ERR_INVALID_SD_TYPE";
 282         case I40E_ERR_MEMCPY_FAILED:
 283                 return "I40E_ERR_MEMCPY_FAILED";
 284         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 285                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 286         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 287                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 288         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 289                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 290         case I40E_ERR_SRQ_ENABLED:
 291                 return "I40E_ERR_SRQ_ENABLED";
 292         case I40E_ERR_ADMIN_QUEUE_ERROR:
 293                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 294         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 295                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 296         case I40E_ERR_BUF_TOO_SHORT:
 297                 return "I40E_ERR_BUF_TOO_SHORT";
 298         case I40E_ERR_ADMIN_QUEUE_FULL:
 299                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 300         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 301                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 302         case I40E_ERR_BAD_IWARP_CQE:
 303                 return "I40E_ERR_BAD_IWARP_CQE";
 304         case I40E_ERR_NVM_BLANK_MODE:
 305                 return "I40E_ERR_NVM_BLANK_MODE";
 306         case I40E_ERR_NOT_IMPLEMENTED:
 307                 return "I40E_ERR_NOT_IMPLEMENTED";
 308         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 309                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 310         case I40E_ERR_DIAG_TEST_FAILED:
 311                 return "I40E_ERR_DIAG_TEST_FAILED";
 312         case I40E_ERR_NOT_READY:
 313                 return "I40E_ERR_NOT_READY";
 314         case I40E_NOT_SUPPORTED:
 315                 return "I40E_NOT_SUPPORTED";
 316         case I40E_ERR_FIRMWARE_API_VERSION:
 317                 return "I40E_ERR_FIRMWARE_API_VERSION";
 318         }
 319
 320         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 321         return hw->err_str;
 322 }
 323
 324 #endif /* I40E_NDIS_SUPPORT */
 325 /**
 326  * i40e_debug_aq
 327  * @hw: debug mask related to admin queue
 328  * @mask: debug mask
 329  * @desc: pointer to admin queue descriptor
 330  * @buffer: pointer to command buffer
 331  * @buf_len: max length of buffer
 332  *
 333  * Dumps debug log about adminq command with descriptor contents.
 334  **/
 335 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 336                    void *buffer, u16 buf_len)
 337 {
 338         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 339         u16 len = LE16_TO_CPU(aq_desc->datalen);
 340         u8 *buf = (u8 *)buffer;
 341         u16 i = 0;
 342
 343         if ((!(mask & hw->debug_mask)) || (desc == NULL))
 344                 return;
 345
 346         i40e_debug(hw, mask,
 347                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 348                    LE16_TO_CPU(aq_desc->opcode),
 349                    LE16_TO_CPU(aq_desc->flags),
 350                    LE16_TO_CPU(aq_desc->datalen),
 351                    LE16_TO_CPU(aq_desc->retval));
 352         i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
 353                    LE32_TO_CPU(aq_desc->cookie_high),
 354                    LE32_TO_CPU(aq_desc->cookie_low));
 355         i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
 356                    LE32_TO_CPU(aq_desc->params.internal.param0),
 357                    LE32_TO_CPU(aq_desc->params.internal.param1));
 358         i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
 359                    LE32_TO_CPU(aq_desc->params.external.addr_high),
 360                    LE32_TO_CPU(aq_desc->params.external.addr_low));
 361
 362         if ((buffer != NULL) && (aq_desc->datalen != 0)) {
 363                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 364                 if (buf_len < len)
 365                         len = buf_len;
 366                 /* write the full 16-byte chunks */
 367                 for (i = 0; i < (len - 16); i += 16)
 368                         i40e_debug(hw, mask,
 369                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 370                                    i, buf[i], buf[i+1], buf[i+2], buf[i+3],
 371                                    buf[i+4], buf[i+5], buf[i+6], buf[i+7],
 372                                    buf[i+8], buf[i+9], buf[i+10], buf[i+11],
 373                                    buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
 374                 /* the most we could have left is 16 bytes, pad with zeros */
 375                 if (i < len) {
 376                         char d_buf[16];
 377                         int j, i_sav;
 378
 379                         i_sav = i;
 380                         memset(d_buf, 0, sizeof(d_buf));
 381                         for (j = 0; i < len; j++, i++)
 382                                 d_buf[j] = buf[i];
 383                         i40e_debug(hw, mask,
 384                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 385                                    i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
 386                                    d_buf[4], d_buf[5], d_buf[6], d_buf[7],
 387                                    d_buf[8], d_buf[9], d_buf[10], d_buf[11],
 388                                    d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
 389                 }
 390         }
 391 }
 392
 393 /**
 394  * i40e_check_asq_alive
 395  * @hw: pointer to the hw struct
 396  *
 397  * Returns true if Queue is enabled else false.
 398  **/
 399 bool i40e_check_asq_alive(struct i40e_hw *hw)
 400 {
 401         if (hw->aq.asq.len)
 402 #ifdef PF_DRIVER
 403 #ifdef INTEGRATED_VF
 404                 if (!i40e_is_vf(hw))
 405                         return !!(rd32(hw, hw->aq.asq.len) &
 406                                 I40E_PF_ATQLEN_ATQENABLE_MASK);
 407 #else
 408                 return !!(rd32(hw, hw->aq.asq.len) &
 409                         I40E_PF_ATQLEN_ATQENABLE_MASK);
 410 #endif /* INTEGRATED_VF */
 411 #endif /* PF_DRIVER */
 412 #ifdef VF_DRIVER
 413 #ifdef INTEGRATED_VF
 414                 if (i40e_is_vf(hw))
 415                         return !!(rd32(hw, hw->aq.asq.len) &
 416                                 I40E_VF_ATQLEN1_ATQENABLE_MASK);
 417 #else
 418                 return !!(rd32(hw, hw->aq.asq.len) &
 419                         I40E_VF_ATQLEN1_ATQENABLE_MASK);
 420 #endif /* INTEGRATED_VF */
 421 #endif /* VF_DRIVER */
 422         return false;
 423 }
 424
 425 /**
 426  * i40e_aq_queue_shutdown
 427  * @hw: pointer to the hw struct
 428  * @unloading: is the driver unloading itself
 429  *
 430  * Tell the Firmware that we're shutting down the AdminQ and whether
 431  * or not the driver is unloading as well.
 432  **/
 433 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
 434                                              bool unloading)
 435 {
 436         struct i40e_aq_desc desc;
 437         struct i40e_aqc_queue_shutdown *cmd =
 438                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 439         enum i40e_status_code status;
 440
 441         i40e_fill_default_direct_cmd_desc(&desc,
 442                                           i40e_aqc_opc_queue_shutdown);
 443
 444         if (unloading)
 445                 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
 446         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 447
 448         return status;
 449 }
 450 #ifdef X722_SUPPORT
 451
 452 /**
 453  * i40e_aq_get_set_rss_lut
 454  * @hw: pointer to the hardware structure
 455  * @vsi_id: vsi fw index
 456  * @pf_lut: for PF table set true, for VSI table set false
 457  * @lut: pointer to the lut buffer provided by the caller
 458  * @lut_size: size of the lut buffer
 459  * @set: set true to set the table, false to get the table
 460  *
 461  * Internal function to get or set RSS look up table
 462  **/
 463 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 464                                                      u16 vsi_id, bool pf_lut,
 465                                                      u8 *lut, u16 lut_size,
 466                                                      bool set)
 467 {
 468         enum i40e_status_code status;
 469         struct i40e_aq_desc desc;
 470         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 471                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 472
 473         if (set)
 474                 i40e_fill_default_direct_cmd_desc(&desc,
 475                                                   i40e_aqc_opc_set_rss_lut);
 476         else
 477                 i40e_fill_default_direct_cmd_desc(&desc,
 478                                                   i40e_aqc_opc_get_rss_lut);
 479
 480         /* Indirect command */
 481         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 482         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 483
 484         cmd_resp->vsi_id =
 485                         CPU_TO_LE16((u16)((vsi_id <<
 486                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 487                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 488         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 489
 490         if (pf_lut)
 491                 cmd_resp->flags |= CPU_TO_LE16((u16)
 492                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 493                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 494                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 495         else
 496                 cmd_resp->flags |= CPU_TO_LE16((u16)
 497                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 498                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 499                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 500
 501         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 502
 503         return status;
 504 }
 505
 506 /**
 507  * i40e_aq_get_rss_lut
 508  * @hw: pointer to the hardware structure
 509  * @vsi_id: vsi fw index
 510  * @pf_lut: for PF table set true, for VSI table set false
 511  * @lut: pointer to the lut buffer provided by the caller
 512  * @lut_size: size of the lut buffer
 513  *
 514  * get the RSS lookup table, PF or VSI type
 515  **/
 516 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 517                                           bool pf_lut, u8 *lut, u16 lut_size)
 518 {
 519         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 520                                        false);
 521 }
 522
 523 /**
 524  * i40e_aq_set_rss_lut
 525  * @hw: pointer to the hardware structure
 526  * @vsi_id: vsi fw index
 527  * @pf_lut: for PF table set true, for VSI table set false
 528  * @lut: pointer to the lut buffer provided by the caller
 529  * @lut_size: size of the lut buffer
 530  *
 531  * set the RSS lookup table, PF or VSI type
 532  **/
 533 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 534                                           bool pf_lut, u8 *lut, u16 lut_size)
 535 {
 536         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
 537 }
 538
 539 /**
 540  * i40e_aq_get_set_rss_key
 541  * @hw: pointer to the hw struct
 542  * @vsi_id: vsi fw index
 543  * @key: pointer to key info struct
 544  * @set: set true to set the key, false to get the key
 545  *
 546  * get the RSS key per VSI
 547  **/
 548 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 549                                       u16 vsi_id,
 550                                       struct i40e_aqc_get_set_rss_key_data *key,
 551                                       bool set)
 552 {
 553         enum i40e_status_code status;
 554         struct i40e_aq_desc desc;
 555         struct i40e_aqc_get_set_rss_key *cmd_resp =
 556                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 557         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 558
 559         if (set)
 560                 i40e_fill_default_direct_cmd_desc(&desc,
 561                                                   i40e_aqc_opc_set_rss_key);
 562         else
 563                 i40e_fill_default_direct_cmd_desc(&desc,
 564                                                   i40e_aqc_opc_get_rss_key);
 565
 566         /* Indirect command */
 567         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 568         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 569
 570         cmd_resp->vsi_id =
 571                         CPU_TO_LE16((u16)((vsi_id <<
 572                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 573                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 574         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 575
 576         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 577
 578         return status;
 579 }
 580
 581 /**
 582  * i40e_aq_get_rss_key
 583  * @hw: pointer to the hw struct
 584  * @vsi_id: vsi fw index
 585  * @key: pointer to key info struct
 586  *
 587  **/
 588 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
 589                                       u16 vsi_id,
 590                                       struct i40e_aqc_get_set_rss_key_data *key)
 591 {
 592         return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
 593 }
 594
 595 /**
 596  * i40e_aq_set_rss_key
 597  * @hw: pointer to the hw struct
 598  * @vsi_id: vsi fw index
 599  * @key: pointer to key info struct
 600  *
 601  * set the RSS key per VSI
 602  **/
 603 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
 604                                       u16 vsi_id,
 605                                       struct i40e_aqc_get_set_rss_key_data *key)
 606 {
 607         return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
 608 }
 609 #endif /* X722_SUPPORT */
 610
 611 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 612  * hardware to a bit-field that can be used by SW to more easily determine the
 613  * packet type.
 614  *
 615  * Macros are used to shorten the table lines and make this table human
 616  * readable.
 617  *
 618  * We store the PTYPE in the top byte of the bit field - this is just so that
 619  * we can check that the table doesn't have a row missing, as the index into
 620  * the table should be the PTYPE.
 621  *
 622  * Typical work flow:
 623  *
 624  * IF NOT i40e_ptype_lookup[ptype].known
 625  * THEN
 626  *      Packet is unknown
 627  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 628  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 629  * ELSE
 630  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 631  * ENDIF
 632  */
 633
 634 /* macro to make the table lines short */
 635 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 636         {       PTYPE, \
 637                 1, \
 638                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 639                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 640                 I40E_RX_PTYPE_##OUTER_FRAG, \
 641                 I40E_RX_PTYPE_TUNNEL_##T, \
 642                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 643                 I40E_RX_PTYPE_##TEF, \
 644                 I40E_RX_PTYPE_INNER_PROT_##I, \
 645                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 646
 647 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 648                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 649
 650 /* shorter macros makes the table fit but are terse */
 651 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 652 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 653 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 654
 655 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 656 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 657         /* L2 Packet types */
 658         I40E_PTT_UNUSED_ENTRY(0),
 659         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 660         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 661         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 662         I40E_PTT_UNUSED_ENTRY(4),
 663         I40E_PTT_UNUSED_ENTRY(5),
 664         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 665         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 666         I40E_PTT_UNUSED_ENTRY(8),
 667         I40E_PTT_UNUSED_ENTRY(9),
 668         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 669         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 670         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 671         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 672         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 673         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 674         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 675         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 676         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 677         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 678         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 679         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 680
 681         /* Non Tunneled IPv4 */
 682         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 683         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 684         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 685         I40E_PTT_UNUSED_ENTRY(25),
 686         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 687         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 688         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 689
 690         /* IPv4 --> IPv4 */
 691         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 692         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 693         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 694         I40E_PTT_UNUSED_ENTRY(32),
 695         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 696         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 697         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 698
 699         /* IPv4 --> IPv6 */
 700         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 701         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 702         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 703         I40E_PTT_UNUSED_ENTRY(39),
 704         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 705         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 706         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 707
 708         /* IPv4 --> GRE/NAT */
 709         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 710
 711         /* IPv4 --> GRE/NAT --> IPv4 */
 712         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 713         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 714         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 715         I40E_PTT_UNUSED_ENTRY(47),
 716         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 717         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 718         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 719
 720         /* IPv4 --> GRE/NAT --> IPv6 */
 721         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 722         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 723         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 724         I40E_PTT_UNUSED_ENTRY(54),
 725         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 726         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 727         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 728
 729         /* IPv4 --> GRE/NAT --> MAC */
 730         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 731
 732         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 733         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 734         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 735         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 736         I40E_PTT_UNUSED_ENTRY(62),
 737         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 738         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 739         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 740
 741         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 742         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 743         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 744         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 745         I40E_PTT_UNUSED_ENTRY(69),
 746         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 747         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 748         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 749
 750         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 751         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 752
 753         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 754         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 755         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 756         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 757         I40E_PTT_UNUSED_ENTRY(77),
 758         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 759         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 760         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 761
 762         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 763         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 764         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 765         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 766         I40E_PTT_UNUSED_ENTRY(84),
 767         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 768         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 769         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 770
 771         /* Non Tunneled IPv6 */
 772         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 773         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 774         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
 775         I40E_PTT_UNUSED_ENTRY(91),
 776         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 777         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 778         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 779
 780         /* IPv6 --> IPv4 */
 781         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 782         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 783         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 784         I40E_PTT_UNUSED_ENTRY(98),
 785         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 786         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 787         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 788
 789         /* IPv6 --> IPv6 */
 790         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 791         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 792         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 793         I40E_PTT_UNUSED_ENTRY(105),
 794         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 795         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 796         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 797
 798         /* IPv6 --> GRE/NAT */
 799         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 800
 801         /* IPv6 --> GRE/NAT -> IPv4 */
 802         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 803         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 804         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 805         I40E_PTT_UNUSED_ENTRY(113),
 806         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 807         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 808         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 809
 810         /* IPv6 --> GRE/NAT -> IPv6 */
 811         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 812         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 813         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 814         I40E_PTT_UNUSED_ENTRY(120),
 815         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 816         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 817         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 818
 819         /* IPv6 --> GRE/NAT -> MAC */
 820         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 821
 822         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 823         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 824         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 825         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 826         I40E_PTT_UNUSED_ENTRY(128),
 827         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 828         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 829         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 830
 831         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 832         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 833         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 834         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 835         I40E_PTT_UNUSED_ENTRY(135),
 836         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 837         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 838         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 839
 840         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 841         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 842
 843         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 844         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 845         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 846         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 847         I40E_PTT_UNUSED_ENTRY(143),
 848         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 849         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 850         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 851
 852         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 853         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 854         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 855         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 856         I40E_PTT_UNUSED_ENTRY(150),
 857         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 858         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 859         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 860
 861         /* unused entries */
 862         I40E_PTT_UNUSED_ENTRY(154),
 863         I40E_PTT_UNUSED_ENTRY(155),
 864         I40E_PTT_UNUSED_ENTRY(156),
 865         I40E_PTT_UNUSED_ENTRY(157),
 866         I40E_PTT_UNUSED_ENTRY(158),
 867         I40E_PTT_UNUSED_ENTRY(159),
 868
 869         I40E_PTT_UNUSED_ENTRY(160),
 870         I40E_PTT_UNUSED_ENTRY(161),
 871         I40E_PTT_UNUSED_ENTRY(162),
 872         I40E_PTT_UNUSED_ENTRY(163),
 873         I40E_PTT_UNUSED_ENTRY(164),
 874         I40E_PTT_UNUSED_ENTRY(165),
 875         I40E_PTT_UNUSED_ENTRY(166),
 876         I40E_PTT_UNUSED_ENTRY(167),
 877         I40E_PTT_UNUSED_ENTRY(168),
 878         I40E_PTT_UNUSED_ENTRY(169),
 879
 880         I40E_PTT_UNUSED_ENTRY(170),
 881         I40E_PTT_UNUSED_ENTRY(171),
 882         I40E_PTT_UNUSED_ENTRY(172),
 883         I40E_PTT_UNUSED_ENTRY(173),
 884         I40E_PTT_UNUSED_ENTRY(174),
 885         I40E_PTT_UNUSED_ENTRY(175),
 886         I40E_PTT_UNUSED_ENTRY(176),
 887         I40E_PTT_UNUSED_ENTRY(177),
 888         I40E_PTT_UNUSED_ENTRY(178),
 889         I40E_PTT_UNUSED_ENTRY(179),
 890
 891         I40E_PTT_UNUSED_ENTRY(180),
 892         I40E_PTT_UNUSED_ENTRY(181),
 893         I40E_PTT_UNUSED_ENTRY(182),
 894         I40E_PTT_UNUSED_ENTRY(183),
 895         I40E_PTT_UNUSED_ENTRY(184),
 896         I40E_PTT_UNUSED_ENTRY(185),
 897         I40E_PTT_UNUSED_ENTRY(186),
 898         I40E_PTT_UNUSED_ENTRY(187),
 899         I40E_PTT_UNUSED_ENTRY(188),
 900         I40E_PTT_UNUSED_ENTRY(189),
 901
 902         I40E_PTT_UNUSED_ENTRY(190),
 903         I40E_PTT_UNUSED_ENTRY(191),
 904         I40E_PTT_UNUSED_ENTRY(192),
 905         I40E_PTT_UNUSED_ENTRY(193),
 906         I40E_PTT_UNUSED_ENTRY(194),
 907         I40E_PTT_UNUSED_ENTRY(195),
 908         I40E_PTT_UNUSED_ENTRY(196),
 909         I40E_PTT_UNUSED_ENTRY(197),
 910         I40E_PTT_UNUSED_ENTRY(198),
 911         I40E_PTT_UNUSED_ENTRY(199),
 912
 913         I40E_PTT_UNUSED_ENTRY(200),
 914         I40E_PTT_UNUSED_ENTRY(201),
 915         I40E_PTT_UNUSED_ENTRY(202),
 916         I40E_PTT_UNUSED_ENTRY(203),
 917         I40E_PTT_UNUSED_ENTRY(204),
 918         I40E_PTT_UNUSED_ENTRY(205),
 919         I40E_PTT_UNUSED_ENTRY(206),
 920         I40E_PTT_UNUSED_ENTRY(207),
 921         I40E_PTT_UNUSED_ENTRY(208),
 922         I40E_PTT_UNUSED_ENTRY(209),
 923
 924         I40E_PTT_UNUSED_ENTRY(210),
 925         I40E_PTT_UNUSED_ENTRY(211),
 926         I40E_PTT_UNUSED_ENTRY(212),
 927         I40E_PTT_UNUSED_ENTRY(213),
 928         I40E_PTT_UNUSED_ENTRY(214),
 929         I40E_PTT_UNUSED_ENTRY(215),
 930         I40E_PTT_UNUSED_ENTRY(216),
 931         I40E_PTT_UNUSED_ENTRY(217),
 932         I40E_PTT_UNUSED_ENTRY(218),
 933         I40E_PTT_UNUSED_ENTRY(219),
 934
 935         I40E_PTT_UNUSED_ENTRY(220),
 936         I40E_PTT_UNUSED_ENTRY(221),
 937         I40E_PTT_UNUSED_ENTRY(222),
 938         I40E_PTT_UNUSED_ENTRY(223),
 939         I40E_PTT_UNUSED_ENTRY(224),
 940         I40E_PTT_UNUSED_ENTRY(225),
 941         I40E_PTT_UNUSED_ENTRY(226),
 942         I40E_PTT_UNUSED_ENTRY(227),
 943         I40E_PTT_UNUSED_ENTRY(228),
 944         I40E_PTT_UNUSED_ENTRY(229),
 945
 946         I40E_PTT_UNUSED_ENTRY(230),
 947         I40E_PTT_UNUSED_ENTRY(231),
 948         I40E_PTT_UNUSED_ENTRY(232),
 949         I40E_PTT_UNUSED_ENTRY(233),
 950         I40E_PTT_UNUSED_ENTRY(234),
 951         I40E_PTT_UNUSED_ENTRY(235),
 952         I40E_PTT_UNUSED_ENTRY(236),
 953         I40E_PTT_UNUSED_ENTRY(237),
 954         I40E_PTT_UNUSED_ENTRY(238),
 955         I40E_PTT_UNUSED_ENTRY(239),
 956
 957         I40E_PTT_UNUSED_ENTRY(240),
 958         I40E_PTT_UNUSED_ENTRY(241),
 959         I40E_PTT_UNUSED_ENTRY(242),
 960         I40E_PTT_UNUSED_ENTRY(243),
 961         I40E_PTT_UNUSED_ENTRY(244),
 962         I40E_PTT_UNUSED_ENTRY(245),
 963         I40E_PTT_UNUSED_ENTRY(246),
 964         I40E_PTT_UNUSED_ENTRY(247),
 965         I40E_PTT_UNUSED_ENTRY(248),
 966         I40E_PTT_UNUSED_ENTRY(249),
 967
 968         I40E_PTT_UNUSED_ENTRY(250),
 969         I40E_PTT_UNUSED_ENTRY(251),
 970         I40E_PTT_UNUSED_ENTRY(252),
 971         I40E_PTT_UNUSED_ENTRY(253),
 972         I40E_PTT_UNUSED_ENTRY(254),
 973         I40E_PTT_UNUSED_ENTRY(255)
 974 };
 975
 976
 977 /**
 978  * i40e_validate_mac_addr - Validate unicast MAC address
 979  * @mac_addr: pointer to MAC address
 980  *
 981  * Tests a MAC address to ensure it is a valid Individual Address
 982  **/
 983 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
 984 {
 985         enum i40e_status_code status = I40E_SUCCESS;
 986
 987         DEBUGFUNC("i40e_validate_mac_addr");
 988
 989         /* Broadcast addresses ARE multicast addresses
 990          * Make sure it is not a multicast address
 991          * Reject the zero address
 992          */
 993         if (I40E_IS_MULTICAST(mac_addr) ||
 994             (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
 995               mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
 996                 status = I40E_ERR_INVALID_MAC_ADDR;
 997
 998         return status;
 999 }
1000 #ifdef PF_DRIVER
1001
1002 /**
1003  * i40e_init_shared_code - Initialize the shared code
1004  * @hw: pointer to hardware structure
1005  *
1006  * This assigns the MAC type and PHY code and inits the NVM.
1007  * Does not touch the hardware. This function must be called prior to any
1008  * other function in the shared code. The i40e_hw structure should be
1009  * memset to 0 prior to calling this function.  The following fields in
1010  * hw structure should be filled in prior to calling this function:
1011  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1012  * subsystem_vendor_id, and revision_id
1013  **/
1014 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
1015 {
1016         enum i40e_status_code status = I40E_SUCCESS;
1017         u32 port, ari, func_rid;
1018
1019         DEBUGFUNC("i40e_init_shared_code");
1020
1021         i40e_set_mac_type(hw);
1022
1023         switch (hw->mac.type) {
1024         case I40E_MAC_XL710:
1025 #ifdef X722_SUPPORT
1026         case I40E_MAC_X722:
1027 #endif
1028                 break;
1029         default:
1030                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1031         }
1032
1033         hw->phy.get_link_info = true;
1034
1035         /* Determine port number and PF number*/
1036         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1037                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1038         hw->port = (u8)port;
1039         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1040                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1041         func_rid = rd32(hw, I40E_PF_FUNC_RID);
1042         if (ari)
1043                 hw->pf_id = (u8)(func_rid & 0xff);
1044         else
1045                 hw->pf_id = (u8)(func_rid & 0x7);
1046
1047 #ifdef X722_SUPPORT
1048         if (hw->mac.type == I40E_MAC_X722)
1049                 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
1050
1051 #endif
1052         status = i40e_init_nvm(hw);
1053         return status;
1054 }
1055
1056 /**
1057  * i40e_aq_mac_address_read - Retrieve the MAC addresses
1058  * @hw: pointer to the hw struct
1059  * @flags: a return indicator of what addresses were added to the addr store
1060  * @addrs: the requestor's mac addr store
1061  * @cmd_details: pointer to command details structure or NULL
1062  **/
1063 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1064                                    u16 *flags,
1065                                    struct i40e_aqc_mac_address_read_data *addrs,
1066                                    struct i40e_asq_cmd_details *cmd_details)
1067 {
1068         struct i40e_aq_desc desc;
1069         struct i40e_aqc_mac_address_read *cmd_data =
1070                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1071         enum i40e_status_code status;
1072
1073         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1074         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1075
1076         status = i40e_asq_send_command(hw, &desc, addrs,
1077                                        sizeof(*addrs), cmd_details);
1078         *flags = LE16_TO_CPU(cmd_data->command_flags);
1079
1080         return status;
1081 }
1082
1083 /**
1084  * i40e_aq_mac_address_write - Change the MAC addresses
1085  * @hw: pointer to the hw struct
1086  * @flags: indicates which MAC to be written
1087  * @mac_addr: address to write
1088  * @cmd_details: pointer to command details structure or NULL
1089  **/
1090 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1091                                     u16 flags, u8 *mac_addr,
1092                                     struct i40e_asq_cmd_details *cmd_details)
1093 {
1094         struct i40e_aq_desc desc;
1095         struct i40e_aqc_mac_address_write *cmd_data =
1096                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1097         enum i40e_status_code status;
1098
1099         i40e_fill_default_direct_cmd_desc(&desc,
1100                                           i40e_aqc_opc_mac_address_write);
1101         cmd_data->command_flags = CPU_TO_LE16(flags);
1102         cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1103         cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1104                                         ((u32)mac_addr[3] << 16) |
1105                                         ((u32)mac_addr[4] << 8) |
1106                                         mac_addr[5]);
1107
1108         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1109
1110         return status;
1111 }
1112
1113 /**
1114  * i40e_get_mac_addr - get MAC address
1115  * @hw: pointer to the HW structure
1116  * @mac_addr: pointer to MAC address
1117  *
1118  * Reads the adapter's MAC address from register
1119  **/
1120 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1121 {
1122         struct i40e_aqc_mac_address_read_data addrs;
1123         enum i40e_status_code status;
1124         u16 flags = 0;
1125
1126         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1127
1128         if (flags & I40E_AQC_LAN_ADDR_VALID)
1129                 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
1130
1131         return status;
1132 }
1133
1134 /**
1135  * i40e_get_port_mac_addr - get Port MAC address
1136  * @hw: pointer to the HW structure
1137  * @mac_addr: pointer to Port MAC address
1138  *
1139  * Reads the adapter's Port MAC address
1140  **/
1141 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1142 {
1143         struct i40e_aqc_mac_address_read_data addrs;
1144         enum i40e_status_code status;
1145         u16 flags = 0;
1146
1147         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1148         if (status)
1149                 return status;
1150
1151         if (flags & I40E_AQC_PORT_ADDR_VALID)
1152                 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
1153         else
1154                 status = I40E_ERR_INVALID_MAC_ADDR;
1155
1156         return status;
1157 }
1158
1159 /**
1160  * i40e_pre_tx_queue_cfg - pre tx queue configure
1161  * @hw: pointer to the HW structure
1162  * @queue: target pf queue index
1163  * @enable: state change request
1164  *
1165  * Handles hw requirement to indicate intention to enable
1166  * or disable target queue.
1167  **/
1168 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1169 {
1170         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1171         u32 reg_block = 0;
1172         u32 reg_val;
1173
1174         if (abs_queue_idx >= 128) {
1175                 reg_block = abs_queue_idx / 128;
1176                 abs_queue_idx %= 128;
1177         }
1178
1179         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1180         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1181         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1182
1183         if (enable)
1184                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1185         else
1186                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1187
1188         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1189 }
1190
1191 /**
1192  * i40e_get_san_mac_addr - get SAN MAC address
1193  * @hw: pointer to the HW structure
1194  * @mac_addr: pointer to SAN MAC address
1195  *
1196  * Reads the adapter's SAN MAC address from NVM
1197  **/
1198 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1199                                             u8 *mac_addr)
1200 {
1201         struct i40e_aqc_mac_address_read_data addrs;
1202         enum i40e_status_code status;
1203         u16 flags = 0;
1204
1205         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1206         if (status)
1207                 return status;
1208
1209         if (flags & I40E_AQC_SAN_ADDR_VALID)
1210                 memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac));
1211         else
1212                 status = I40E_ERR_INVALID_MAC_ADDR;
1213
1214         return status;
1215 }
1216
1217 /**
1218  *  i40e_read_pba_string - Reads part number string from EEPROM
1219  *  @hw: pointer to hardware structure
1220  *  @pba_num: stores the part number string from the EEPROM
1221  *  @pba_num_size: part number string buffer length
1222  *
1223  *  Reads the part number string from the EEPROM.
1224  **/
1225 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1226                                             u32 pba_num_size)
1227 {
1228         enum i40e_status_code status = I40E_SUCCESS;
1229         u16 pba_word = 0;
1230         u16 pba_size = 0;
1231         u16 pba_ptr = 0;
1232         u16 i = 0;
1233
1234         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1235         if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1236                 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1237                 return status;
1238         }
1239
1240         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1241         if (status != I40E_SUCCESS) {
1242                 DEBUGOUT("Failed to read PBA Block pointer.\n");
1243                 return status;
1244         }
1245
1246         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1247         if (status != I40E_SUCCESS) {
1248                 DEBUGOUT("Failed to read PBA Block size.\n");
1249                 return status;
1250         }
1251
1252         /* Subtract one to get PBA word count (PBA Size word is included in
1253          * total size)
1254          */
1255         pba_size--;
1256         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1257                 DEBUGOUT("Buffer to small for PBA data.\n");
1258                 return I40E_ERR_PARAM;
1259         }
1260
1261         for (i = 0; i < pba_size; i++) {
1262                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1263                 if (status != I40E_SUCCESS) {
1264                         DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1265                         return status;
1266                 }
1267
1268                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1269                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1270         }
1271         pba_num[(pba_size * 2)] = '\0';
1272
1273         return status;
1274 }
1275
1276 /**
1277  * i40e_get_media_type - Gets media type
1278  * @hw: pointer to the hardware structure
1279  **/
1280 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1281 {
1282         enum i40e_media_type media;
1283
1284         switch (hw->phy.link_info.phy_type) {
1285         case I40E_PHY_TYPE_10GBASE_SR:
1286         case I40E_PHY_TYPE_10GBASE_LR:
1287         case I40E_PHY_TYPE_1000BASE_SX:
1288         case I40E_PHY_TYPE_1000BASE_LX:
1289         case I40E_PHY_TYPE_40GBASE_SR4:
1290         case I40E_PHY_TYPE_40GBASE_LR4:
1291         case I40E_PHY_TYPE_25GBASE_LR:
1292         case I40E_PHY_TYPE_25GBASE_SR:
1293                 media = I40E_MEDIA_TYPE_FIBER;
1294                 break;
1295         case I40E_PHY_TYPE_100BASE_TX:
1296         case I40E_PHY_TYPE_1000BASE_T:
1297         case I40E_PHY_TYPE_10GBASE_T:
1298                 media = I40E_MEDIA_TYPE_BASET;
1299                 break;
1300         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1301         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1302         case I40E_PHY_TYPE_10GBASE_CR1:
1303         case I40E_PHY_TYPE_40GBASE_CR4:
1304         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1305         case I40E_PHY_TYPE_40GBASE_AOC:
1306         case I40E_PHY_TYPE_10GBASE_AOC:
1307         case I40E_PHY_TYPE_25GBASE_CR:
1308                 media = I40E_MEDIA_TYPE_DA;
1309                 break;
1310         case I40E_PHY_TYPE_1000BASE_KX:
1311         case I40E_PHY_TYPE_10GBASE_KX4:
1312         case I40E_PHY_TYPE_10GBASE_KR:
1313         case I40E_PHY_TYPE_40GBASE_KR4:
1314         case I40E_PHY_TYPE_20GBASE_KR2:
1315         case I40E_PHY_TYPE_25GBASE_KR:
1316                 media = I40E_MEDIA_TYPE_BACKPLANE;
1317                 break;
1318         case I40E_PHY_TYPE_SGMII:
1319         case I40E_PHY_TYPE_XAUI:
1320         case I40E_PHY_TYPE_XFI:
1321         case I40E_PHY_TYPE_XLAUI:
1322         case I40E_PHY_TYPE_XLPPI:
1323         default:
1324                 media = I40E_MEDIA_TYPE_UNKNOWN;
1325                 break;
1326         }
1327
1328         return media;
1329 }
1330
1331 #define I40E_PF_RESET_WAIT_COUNT        200
1332 /**
1333  * i40e_pf_reset - Reset the PF
1334  * @hw: pointer to the hardware structure
1335  *
1336  * Assuming someone else has triggered a global reset,
1337  * assure the global reset is complete and then reset the PF
1338  **/
1339 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1340 {
1341         u32 cnt = 0;
1342         u32 cnt1 = 0;
1343         u32 reg = 0;
1344         u32 grst_del;
1345
1346         /* Poll for Global Reset steady state in case of recent GRST.
1347          * The grst delay value is in 100ms units, and we'll wait a
1348          * couple counts longer to be sure we don't just miss the end.
1349          */
1350         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1351                         I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1352                         I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1353
1354         grst_del = grst_del * 20;
1355
1356         for (cnt = 0; cnt < grst_del; cnt++) {
1357                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1358                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1359                         break;
1360                 i40e_msec_delay(100);
1361         }
1362         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1363                 DEBUGOUT("Global reset polling failed to complete.\n");
1364                 return I40E_ERR_RESET_FAILED;
1365         }
1366
1367         /* Now Wait for the FW to be ready */
1368         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1369                 reg = rd32(hw, I40E_GLNVM_ULD);
1370                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1371                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1372                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1373                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1374                         DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1375                         break;
1376                 }
1377                 i40e_msec_delay(10);
1378         }
1379         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1380                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1381                 DEBUGOUT("wait for FW Reset complete timedout\n");
1382                 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1383                 return I40E_ERR_RESET_FAILED;
1384         }
1385
1386         /* If there was a Global Reset in progress when we got here,
1387          * we don't need to do the PF Reset
1388          */
1389         if (!cnt) {
1390                 reg = rd32(hw, I40E_PFGEN_CTRL);
1391                 wr32(hw, I40E_PFGEN_CTRL,
1392                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1393                 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1394                         reg = rd32(hw, I40E_PFGEN_CTRL);
1395                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1396                                 break;
1397                         i40e_msec_delay(1);
1398                 }
1399                 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1400                         DEBUGOUT("PF reset polling failed to complete.\n");
1401                         return I40E_ERR_RESET_FAILED;
1402                 }
1403         }
1404
1405         i40e_clear_pxe_mode(hw);
1406
1407
1408         return I40E_SUCCESS;
1409 }
1410
1411 /**
1412  * i40e_clear_hw - clear out any left over hw state
1413  * @hw: pointer to the hw struct
1414  *
1415  * Clear queues and interrupts, typically called at init time,
1416  * but after the capabilities have been found so we know how many
1417  * queues and msix vectors have been allocated.
1418  **/
1419 void i40e_clear_hw(struct i40e_hw *hw)
1420 {
1421         u32 num_queues, base_queue;
1422         u32 num_pf_int;
1423         u32 num_vf_int;
1424         u32 num_vfs;
1425         u32 i, j;
1426         u32 val;
1427         u32 eol = 0x7ff;
1428
1429         /* get number of interrupts, queues, and vfs */
1430         val = rd32(hw, I40E_GLPCI_CNF2);
1431         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1432                         I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1433         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1434                         I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1435
1436         val = rd32(hw, I40E_PFLAN_QALLOC);
1437         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1438                         I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1439         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1440                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1441         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1442                 num_queues = (j - base_queue) + 1;
1443         else
1444                 num_queues = 0;
1445
1446         val = rd32(hw, I40E_PF_VT_PFALLOC);
1447         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1448                         I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1449         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1450                         I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1451         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1452                 num_vfs = (j - i) + 1;
1453         else
1454                 num_vfs = 0;
1455
1456         /* stop all the interrupts */
1457         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1458         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1459         for (i = 0; i < num_pf_int - 2; i++)
1460                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1461
1462         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1463         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1464         wr32(hw, I40E_PFINT_LNKLST0, val);
1465         for (i = 0; i < num_pf_int - 2; i++)
1466                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1467         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1468         for (i = 0; i < num_vfs; i++)
1469                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1470         for (i = 0; i < num_vf_int - 2; i++)
1471                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1472
1473         /* warn the HW of the coming Tx disables */
1474         for (i = 0; i < num_queues; i++) {
1475                 u32 abs_queue_idx = base_queue + i;
1476                 u32 reg_block = 0;
1477
1478                 if (abs_queue_idx >= 128) {
1479                         reg_block = abs_queue_idx / 128;
1480                         abs_queue_idx %= 128;
1481                 }
1482
1483                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1484                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1485                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1486                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1487
1488                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1489         }
1490         i40e_usec_delay(400);
1491
1492         /* stop all the queues */
1493         for (i = 0; i < num_queues; i++) {
1494                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1495                 wr32(hw, I40E_QTX_ENA(i), 0);
1496                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1497                 wr32(hw, I40E_QRX_ENA(i), 0);
1498         }
1499
1500         /* short wait for all queue disables to settle */
1501         i40e_usec_delay(50);
1502 }
1503
1504 /**
1505  * i40e_clear_pxe_mode - clear pxe operations mode
1506  * @hw: pointer to the hw struct
1507  *
1508  * Make sure all PXE mode settings are cleared, including things
1509  * like descriptor fetch/write-back mode.
1510  **/
1511 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1512 {
1513         if (i40e_check_asq_alive(hw))
1514                 i40e_aq_clear_pxe_mode(hw, NULL);
1515 }
1516
1517 /**
1518  * i40e_led_is_mine - helper to find matching led
1519  * @hw: pointer to the hw struct
1520  * @idx: index into GPIO registers
1521  *
1522  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1523  */
1524 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1525 {
1526         u32 gpio_val = 0;
1527         u32 port;
1528
1529         if (!hw->func_caps.led[idx])
1530                 return 0;
1531
1532         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1533         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1534                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1535
1536         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1537          * if it is not our port then ignore
1538          */
1539         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1540             (port != hw->port))
1541                 return 0;
1542
1543         return gpio_val;
1544 }
1545
1546 #define I40E_COMBINED_ACTIVITY 0xA
1547 #define I40E_FILTER_ACTIVITY 0xE
1548 #define I40E_LINK_ACTIVITY 0xC
1549 #define I40E_MAC_ACTIVITY 0xD
1550 #define I40E_LED0 22
1551
1552 /**
1553  * i40e_led_get - return current on/off mode
1554  * @hw: pointer to the hw struct
1555  *
1556  * The value returned is the 'mode' field as defined in the
1557  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1558  * values are variations of possible behaviors relating to
1559  * blink, link, and wire.
1560  **/
1561 u32 i40e_led_get(struct i40e_hw *hw)
1562 {
1563         u32 current_mode = 0;
1564         u32 mode = 0;
1565         int i;
1566
1567         /* as per the documentation GPIO 22-29 are the LED
1568          * GPIO pins named LED0..LED7
1569          */
1570         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1571                 u32 gpio_val = i40e_led_is_mine(hw, i);
1572
1573                 if (!gpio_val)
1574                         continue;
1575
1576                 /* ignore gpio LED src mode entries related to the activity
1577                  *  LEDs
1578                  */
1579                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1580                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1581                 switch (current_mode) {
1582                 case I40E_COMBINED_ACTIVITY:
1583                 case I40E_FILTER_ACTIVITY:
1584                 case I40E_MAC_ACTIVITY:
1585                         continue;
1586                 default:
1587                         break;
1588                 }
1589
1590                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1591                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1592                 break;
1593         }
1594
1595         return mode;
1596 }
1597
1598 /**
1599  * i40e_led_set - set new on/off mode
1600  * @hw: pointer to the hw struct
1601  * @mode: 0=off, 0xf=on (else see manual for mode details)
1602  * @blink: true if the LED should blink when on, false if steady
1603  *
1604  * if this function is used to turn on the blink it should
1605  * be used to disable the blink when restoring the original state.
1606  **/
1607 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1608 {
1609         u32 current_mode = 0;
1610         int i;
1611
1612         if (mode & 0xfffffff0)
1613                 DEBUGOUT1("invalid mode passed in %X\n", mode);
1614
1615         /* as per the documentation GPIO 22-29 are the LED
1616          * GPIO pins named LED0..LED7
1617          */
1618         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1619                 u32 gpio_val = i40e_led_is_mine(hw, i);
1620
1621                 if (!gpio_val)
1622                         continue;
1623
1624                 /* ignore gpio LED src mode entries related to the activity
1625                  * LEDs
1626                  */
1627                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1628                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1629                 switch (current_mode) {
1630                 case I40E_COMBINED_ACTIVITY:
1631                 case I40E_FILTER_ACTIVITY:
1632                 case I40E_MAC_ACTIVITY:
1633                         continue;
1634                 default:
1635                         break;
1636                 }
1637
1638                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1639                 /* this & is a bit of paranoia, but serves as a range check */
1640                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1641                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1642
1643                 if (mode == I40E_LINK_ACTIVITY)
1644                         blink = false;
1645
1646                 if (blink)
1647                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1648                 else
1649                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1650
1651                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1652                 break;
1653         }
1654 }
1655
1656 /* Admin command wrappers */
1657
1658 /**
1659  * i40e_aq_get_phy_capabilities
1660  * @hw: pointer to the hw struct
1661  * @abilities: structure for PHY capabilities to be filled
1662  * @qualified_modules: report Qualified Modules
1663  * @report_init: report init capabilities (active are default)
1664  * @cmd_details: pointer to command details structure or NULL
1665  *
1666  * Returns the various PHY abilities supported on the Port.
1667  **/
1668 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1669                         bool qualified_modules, bool report_init,
1670                         struct i40e_aq_get_phy_abilities_resp *abilities,
1671                         struct i40e_asq_cmd_details *cmd_details)
1672 {
1673         struct i40e_aq_desc desc;
1674         enum i40e_status_code status;
1675         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1676
1677         if (!abilities)
1678                 return I40E_ERR_PARAM;
1679
1680         i40e_fill_default_direct_cmd_desc(&desc,
1681                                           i40e_aqc_opc_get_phy_abilities);
1682
1683         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1684         if (abilities_size > I40E_AQ_LARGE_BUF)
1685                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1686
1687         if (qualified_modules)
1688                 desc.params.external.param0 |=
1689                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1690
1691         if (report_init)
1692                 desc.params.external.param0 |=
1693                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1694
1695         status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1696                                     cmd_details);
1697
1698         if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1699                 status = I40E_ERR_UNKNOWN_PHY;
1700
1701         if (report_init) {
1702                 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1703                 hw->phy.phy_types |= ((u64)abilities->phy_type_ext << 32);
1704         }
1705
1706         return status;
1707 }
1708
1709 /**
1710  * i40e_aq_set_phy_config
1711  * @hw: pointer to the hw struct
1712  * @config: structure with PHY configuration to be set
1713  * @cmd_details: pointer to command details structure or NULL
1714  *
1715  * Set the various PHY configuration parameters
1716  * supported on the Port.One or more of the Set PHY config parameters may be
1717  * ignored in an MFP mode as the PF may not have the privilege to set some
1718  * of the PHY Config parameters. This status will be indicated by the
1719  * command response.
1720  **/
1721 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1722                                 struct i40e_aq_set_phy_config *config,
1723                                 struct i40e_asq_cmd_details *cmd_details)
1724 {
1725         struct i40e_aq_desc desc;
1726         struct i40e_aq_set_phy_config *cmd =
1727                 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1728         enum i40e_status_code status;
1729
1730         if (!config)
1731                 return I40E_ERR_PARAM;
1732
1733         i40e_fill_default_direct_cmd_desc(&desc,
1734                                           i40e_aqc_opc_set_phy_config);
1735
1736         *cmd = *config;
1737
1738         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1739
1740         return status;
1741 }
1742
1743 /**
1744  * i40e_set_fc
1745  * @hw: pointer to the hw struct
1746  *
1747  * Set the requested flow control mode using set_phy_config.
1748  **/
1749 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1750                                   bool atomic_restart)
1751 {
1752         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1753         struct i40e_aq_get_phy_abilities_resp abilities;
1754         struct i40e_aq_set_phy_config config;
1755         enum i40e_status_code status;
1756         u8 pause_mask = 0x0;
1757
1758         *aq_failures = 0x0;
1759
1760         switch (fc_mode) {
1761         case I40E_FC_FULL:
1762                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1763                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1764                 break;
1765         case I40E_FC_RX_PAUSE:
1766                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1767                 break;
1768         case I40E_FC_TX_PAUSE:
1769                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1770                 break;
1771         default:
1772                 break;
1773         }
1774
1775         /* Get the current phy config */
1776         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1777                                               NULL);
1778         if (status) {
1779                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1780                 return status;
1781         }
1782
1783         memset(&config, 0, sizeof(config));
1784         /* clear the old pause settings */
1785         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1786                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1787         /* set the new abilities */
1788         config.abilities |= pause_mask;
1789         /* If the abilities have changed, then set the new config */
1790         if (config.abilities != abilities.abilities) {
1791                 /* Auto restart link so settings take effect */
1792                 if (atomic_restart)
1793                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1794                 /* Copy over all the old settings */
1795                 config.phy_type = abilities.phy_type;
1796                 config.phy_type_ext = abilities.phy_type_ext;
1797                 config.link_speed = abilities.link_speed;
1798                 config.eee_capability = abilities.eee_capability;
1799                 config.eeer = abilities.eeer_val;
1800                 config.low_power_ctrl = abilities.d3_lpan;
1801                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1802
1803                 if (status)
1804                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1805         }
1806         /* Update the link info */
1807         status = i40e_update_link_info(hw);
1808         if (status) {
1809                 /* Wait a little bit (on 40G cards it sometimes takes a really
1810                  * long time for link to come back from the atomic reset)
1811                  * and try once more
1812                  */
1813                 i40e_msec_delay(1000);
1814                 status = i40e_update_link_info(hw);
1815         }
1816         if (status)
1817                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1818
1819         return status;
1820 }
1821
1822 /**
1823  * i40e_aq_set_mac_config
1824  * @hw: pointer to the hw struct
1825  * @max_frame_size: Maximum Frame Size to be supported by the port
1826  * @crc_en: Tell HW to append a CRC to outgoing frames
1827  * @pacing: Pacing configurations
1828  * @cmd_details: pointer to command details structure or NULL
1829  *
1830  * Configure MAC settings for frame size, jumbo frame support and the
1831  * addition of a CRC by the hardware.
1832  **/
1833 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1834                                 u16 max_frame_size,
1835                                 bool crc_en, u16 pacing,
1836                                 struct i40e_asq_cmd_details *cmd_details)
1837 {
1838         struct i40e_aq_desc desc;
1839         struct i40e_aq_set_mac_config *cmd =
1840                 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1841         enum i40e_status_code status;
1842
1843         if (max_frame_size == 0)
1844                 return I40E_ERR_PARAM;
1845
1846         i40e_fill_default_direct_cmd_desc(&desc,
1847                                           i40e_aqc_opc_set_mac_config);
1848
1849         cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1850         cmd->params = ((u8)pacing & 0x0F) << 3;
1851         if (crc_en)
1852                 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1853
1854         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1855
1856         return status;
1857 }
1858
1859 /**
1860  * i40e_aq_clear_pxe_mode
1861  * @hw: pointer to the hw struct
1862  * @cmd_details: pointer to command details structure or NULL
1863  *
1864  * Tell the firmware that the driver is taking over from PXE
1865  **/
1866 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1867                         struct i40e_asq_cmd_details *cmd_details)
1868 {
1869         enum i40e_status_code status;
1870         struct i40e_aq_desc desc;
1871         struct i40e_aqc_clear_pxe *cmd =
1872                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1873
1874         i40e_fill_default_direct_cmd_desc(&desc,
1875                                           i40e_aqc_opc_clear_pxe_mode);
1876
1877         cmd->rx_cnt = 0x2;
1878
1879         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1880
1881         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1882
1883         return status;
1884 }
1885
1886 /**
1887  * i40e_aq_set_link_restart_an
1888  * @hw: pointer to the hw struct
1889  * @enable_link: if true: enable link, if false: disable link
1890  * @cmd_details: pointer to command details structure or NULL
1891  *
1892  * Sets up the link and restarts the Auto-Negotiation over the link.
1893  **/
1894 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1895                 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1896 {
1897         struct i40e_aq_desc desc;
1898         struct i40e_aqc_set_link_restart_an *cmd =
1899                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1900         enum i40e_status_code status;
1901
1902         i40e_fill_default_direct_cmd_desc(&desc,
1903                                           i40e_aqc_opc_set_link_restart_an);
1904
1905         cmd->command = I40E_AQ_PHY_RESTART_AN;
1906         if (enable_link)
1907                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1908         else
1909                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1910
1911         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1912
1913         return status;
1914 }
1915
1916 /**
1917  * i40e_aq_get_link_info
1918  * @hw: pointer to the hw struct
1919  * @enable_lse: enable/disable LinkStatusEvent reporting
1920  * @link: pointer to link status structure - optional
1921  * @cmd_details: pointer to command details structure or NULL
1922  *
1923  * Returns the link status of the adapter.
1924  **/
1925 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1926                                 bool enable_lse, struct i40e_link_status *link,
1927                                 struct i40e_asq_cmd_details *cmd_details)
1928 {
1929         struct i40e_aq_desc desc;
1930         struct i40e_aqc_get_link_status *resp =
1931                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1932         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1933         enum i40e_status_code status;
1934         bool tx_pause, rx_pause;
1935         u16 command_flags;
1936
1937         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1938
1939         if (enable_lse)
1940                 command_flags = I40E_AQ_LSE_ENABLE;
1941         else
1942                 command_flags = I40E_AQ_LSE_DISABLE;
1943         resp->command_flags = CPU_TO_LE16(command_flags);
1944
1945         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1946
1947         if (status != I40E_SUCCESS)
1948                 goto aq_get_link_info_exit;
1949
1950         /* save off old link status information */
1951         i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1952                     sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1953
1954         /* update link status */
1955         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1956         hw->phy.media_type = i40e_get_media_type(hw);
1957         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1958         hw_link_info->link_info = resp->link_info;
1959         hw_link_info->an_info = resp->an_info;
1960         hw_link_info->ext_info = resp->ext_info;
1961         hw_link_info->loopback = resp->loopback;
1962         hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1963         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1964
1965         /* update fc info */
1966         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1967         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1968         if (tx_pause & rx_pause)
1969                 hw->fc.current_mode = I40E_FC_FULL;
1970         else if (tx_pause)
1971                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1972         else if (rx_pause)
1973                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1974         else
1975                 hw->fc.current_mode = I40E_FC_NONE;
1976
1977         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1978                 hw_link_info->crc_enable = true;
1979         else
1980                 hw_link_info->crc_enable = false;
1981
1982         if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
1983                 hw_link_info->lse_enable = true;
1984         else
1985                 hw_link_info->lse_enable = false;
1986
1987         if ((hw->mac.type == I40E_MAC_XL710) &&
1988             (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1989              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1990                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1991
1992         /* save link status information */
1993         if (link)
1994                 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1995                             I40E_NONDMA_TO_NONDMA);
1996
1997         /* flag cleared so helper functions don't call AQ again */
1998         hw->phy.get_link_info = false;
1999
2000 aq_get_link_info_exit:
2001         return status;
2002 }
2003
2004 /**
2005  * i40e_aq_set_phy_int_mask
2006  * @hw: pointer to the hw struct
2007  * @mask: interrupt mask to be set
2008  * @cmd_details: pointer to command details structure or NULL
2009  *
2010  * Set link interrupt mask.
2011  **/
2012 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2013                                 u16 mask,
2014                                 struct i40e_asq_cmd_details *cmd_details)
2015 {
2016         struct i40e_aq_desc desc;
2017         struct i40e_aqc_set_phy_int_mask *cmd =
2018                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2019         enum i40e_status_code status;
2020
2021         i40e_fill_default_direct_cmd_desc(&desc,
2022                                           i40e_aqc_opc_set_phy_int_mask);
2023
2024         cmd->event_mask = CPU_TO_LE16(mask);
2025
2026         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2027
2028         return status;
2029 }
2030
2031 /**
2032  * i40e_aq_get_local_advt_reg
2033  * @hw: pointer to the hw struct
2034  * @advt_reg: local AN advertisement register value
2035  * @cmd_details: pointer to command details structure or NULL
2036  *
2037  * Get the Local AN advertisement register value.
2038  **/
2039 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2040                                 u64 *advt_reg,
2041                                 struct i40e_asq_cmd_details *cmd_details)
2042 {
2043         struct i40e_aq_desc desc;
2044         struct i40e_aqc_an_advt_reg *resp =
2045                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2046         enum i40e_status_code status;
2047
2048         i40e_fill_default_direct_cmd_desc(&desc,
2049                                           i40e_aqc_opc_get_local_advt_reg);
2050
2051         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2052
2053         if (status != I40E_SUCCESS)
2054                 goto aq_get_local_advt_reg_exit;
2055
2056         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2057         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2058
2059 aq_get_local_advt_reg_exit:
2060         return status;
2061 }
2062
2063 /**
2064  * i40e_aq_set_local_advt_reg
2065  * @hw: pointer to the hw struct
2066  * @advt_reg: local AN advertisement register value
2067  * @cmd_details: pointer to command details structure or NULL
2068  *
2069  * Get the Local AN advertisement register value.
2070  **/
2071 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2072                                 u64 advt_reg,
2073                                 struct i40e_asq_cmd_details *cmd_details)
2074 {
2075         struct i40e_aq_desc desc;
2076         struct i40e_aqc_an_advt_reg *cmd =
2077                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2078         enum i40e_status_code status;
2079
2080         i40e_fill_default_direct_cmd_desc(&desc,
2081                                           i40e_aqc_opc_get_local_advt_reg);
2082
2083         cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2084         cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2085
2086         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2087
2088         return status;
2089 }
2090
2091 /**
2092  * i40e_aq_get_partner_advt
2093  * @hw: pointer to the hw struct
2094  * @advt_reg: AN partner advertisement register value
2095  * @cmd_details: pointer to command details structure or NULL
2096  *
2097  * Get the link partner AN advertisement register value.
2098  **/
2099 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2100                                 u64 *advt_reg,
2101                                 struct i40e_asq_cmd_details *cmd_details)
2102 {
2103         struct i40e_aq_desc desc;
2104         struct i40e_aqc_an_advt_reg *resp =
2105                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2106         enum i40e_status_code status;
2107
2108         i40e_fill_default_direct_cmd_desc(&desc,
2109                                           i40e_aqc_opc_get_partner_advt);
2110
2111         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2112
2113         if (status != I40E_SUCCESS)
2114                 goto aq_get_partner_advt_exit;
2115
2116         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2117         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2118
2119 aq_get_partner_advt_exit:
2120         return status;
2121 }
2122
2123 /**
2124  * i40e_aq_set_lb_modes
2125  * @hw: pointer to the hw struct
2126  * @lb_modes: loopback mode to be set
2127  * @cmd_details: pointer to command details structure or NULL
2128  *
2129  * Sets loopback modes.
2130  **/
2131 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2132                                 u16 lb_modes,
2133                                 struct i40e_asq_cmd_details *cmd_details)
2134 {
2135         struct i40e_aq_desc desc;
2136         struct i40e_aqc_set_lb_mode *cmd =
2137                 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2138         enum i40e_status_code status;
2139
2140         i40e_fill_default_direct_cmd_desc(&desc,
2141                                           i40e_aqc_opc_set_lb_modes);
2142
2143         cmd->lb_mode = CPU_TO_LE16(lb_modes);
2144
2145         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2146
2147         return status;
2148 }
2149
2150 /**
2151  * i40e_aq_set_phy_debug
2152  * @hw: pointer to the hw struct
2153  * @cmd_flags: debug command flags
2154  * @cmd_details: pointer to command details structure or NULL
2155  *
2156  * Reset the external PHY.
2157  **/
2158 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2159                                 struct i40e_asq_cmd_details *cmd_details)
2160 {
2161         struct i40e_aq_desc desc;
2162         struct i40e_aqc_set_phy_debug *cmd =
2163                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2164         enum i40e_status_code status;
2165
2166         i40e_fill_default_direct_cmd_desc(&desc,
2167                                           i40e_aqc_opc_set_phy_debug);
2168
2169         cmd->command_flags = cmd_flags;
2170
2171         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2172
2173         return status;
2174 }
2175
2176 /**
2177  * i40e_aq_add_vsi
2178  * @hw: pointer to the hw struct
2179  * @vsi_ctx: pointer to a vsi context struct
2180  * @cmd_details: pointer to command details structure or NULL
2181  *
2182  * Add a VSI context to the hardware.
2183 **/
2184 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2185                                 struct i40e_vsi_context *vsi_ctx,
2186                                 struct i40e_asq_cmd_details *cmd_details)
2187 {
2188         struct i40e_aq_desc desc;
2189         struct i40e_aqc_add_get_update_vsi *cmd =
2190                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2191         struct i40e_aqc_add_get_update_vsi_completion *resp =
2192                 (struct i40e_aqc_add_get_update_vsi_completion *)
2193                 &desc.params.raw;
2194         enum i40e_status_code status;
2195
2196         i40e_fill_default_direct_cmd_desc(&desc,
2197                                           i40e_aqc_opc_add_vsi);
2198
2199         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2200         cmd->connection_type = vsi_ctx->connection_type;
2201         cmd->vf_id = vsi_ctx->vf_num;
2202         cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2203
2204         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2205
2206         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2207                                     sizeof(vsi_ctx->info), cmd_details);
2208
2209         if (status != I40E_SUCCESS)
2210                 goto aq_add_vsi_exit;
2211
2212         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2213         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2214         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2215         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2216
2217 aq_add_vsi_exit:
2218         return status;
2219 }
2220
2221 /**
2222  * i40e_aq_set_default_vsi
2223  * @hw: pointer to the hw struct
2224  * @seid: vsi number
2225  * @cmd_details: pointer to command details structure or NULL
2226  **/
2227 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2228                                 u16 seid,
2229                                 struct i40e_asq_cmd_details *cmd_details)
2230 {
2231         struct i40e_aq_desc desc;
2232         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2233                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2234                 &desc.params.raw;
2235         enum i40e_status_code status;
2236
2237         i40e_fill_default_direct_cmd_desc(&desc,
2238                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2239
2240         cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2241         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2242         cmd->seid = CPU_TO_LE16(seid);
2243
2244         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2245
2246         return status;
2247 }
2248
2249 /**
2250  * i40e_aq_clear_default_vsi
2251  * @hw: pointer to the hw struct
2252  * @seid: vsi number
2253  * @cmd_details: pointer to command details structure or NULL
2254  **/
2255 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2256                                 u16 seid,
2257                                 struct i40e_asq_cmd_details *cmd_details)
2258 {
2259         struct i40e_aq_desc desc;
2260         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2261                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2262                 &desc.params.raw;
2263         enum i40e_status_code status;
2264
2265         i40e_fill_default_direct_cmd_desc(&desc,
2266                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2267
2268         cmd->promiscuous_flags = CPU_TO_LE16(0);
2269         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2270         cmd->seid = CPU_TO_LE16(seid);
2271
2272         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2273
2274         return status;
2275 }
2276
2277 /**
2278  * i40e_aq_set_vsi_unicast_promiscuous
2279  * @hw: pointer to the hw struct
2280  * @seid: vsi number
2281  * @set: set unicast promiscuous enable/disable
2282  * @cmd_details: pointer to command details structure or NULL
2283  * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2284  **/
2285 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2286                                 u16 seid, bool set,
2287                                 struct i40e_asq_cmd_details *cmd_details,
2288                                 bool rx_only_promisc)
2289 {
2290         struct i40e_aq_desc desc;
2291         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2292                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2293         enum i40e_status_code status;
2294         u16 flags = 0;
2295
2296         i40e_fill_default_direct_cmd_desc(&desc,
2297                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2298
2299         if (set) {
2300                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2301                 if (rx_only_promisc &&
2302                     (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2303                      (hw->aq.api_maj_ver > 1)))
2304                         flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2305         }
2306
2307         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2308
2309         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2310         if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2311              (hw->aq.api_maj_ver > 1))
2312                 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2313
2314         cmd->seid = CPU_TO_LE16(seid);
2315         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2316
2317         return status;
2318 }
2319
2320 /**
2321  * i40e_aq_set_vsi_multicast_promiscuous
2322  * @hw: pointer to the hw struct
2323  * @seid: vsi number
2324  * @set: set multicast promiscuous enable/disable
2325  * @cmd_details: pointer to command details structure or NULL
2326  **/
2327 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2328                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2329 {
2330         struct i40e_aq_desc desc;
2331         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2332                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2333         enum i40e_status_code status;
2334         u16 flags = 0;
2335
2336         i40e_fill_default_direct_cmd_desc(&desc,
2337                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2338
2339         if (set)
2340                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2341
2342         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2343
2344         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2345
2346         cmd->seid = CPU_TO_LE16(seid);
2347         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2348
2349         return status;
2350 }
2351
2352 /**
2353  * i40e_aq_set_vsi_mc_promisc_on_vlan
2354  * @hw: pointer to the hw struct
2355  * @seid: vsi number
2356  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2357  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2358  * @cmd_details: pointer to command details structure or NULL
2359  **/
2360 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2361                                 u16 seid, bool enable, u16 vid,
2362                                 struct i40e_asq_cmd_details *cmd_details)
2363 {
2364         struct i40e_aq_desc desc;
2365         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2366                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2367         enum i40e_status_code status;
2368         u16 flags = 0;
2369
2370         i40e_fill_default_direct_cmd_desc(&desc,
2371                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2372
2373         if (enable)
2374                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2375
2376         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2377         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2378         cmd->seid = CPU_TO_LE16(seid);
2379         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2380
2381         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2382
2383         return status;
2384 }
2385
2386 /**
2387  * i40e_aq_set_vsi_uc_promisc_on_vlan
2388  * @hw: pointer to the hw struct
2389  * @seid: vsi number
2390  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2391  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2392  * @cmd_details: pointer to command details structure or NULL
2393  **/
2394 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2395                                 u16 seid, bool enable, u16 vid,
2396                                 struct i40e_asq_cmd_details *cmd_details)
2397 {
2398         struct i40e_aq_desc desc;
2399         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2400                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2401         enum i40e_status_code status;
2402         u16 flags = 0;
2403
2404         i40e_fill_default_direct_cmd_desc(&desc,
2405                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2406
2407         if (enable)
2408                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2409
2410         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2411         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2412         cmd->seid = CPU_TO_LE16(seid);
2413         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2414
2415         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2416
2417         return status;
2418 }
2419
2420 /**
2421  * i40e_aq_set_vsi_broadcast
2422  * @hw: pointer to the hw struct
2423  * @seid: vsi number
2424  * @set_filter: true to set filter, false to clear filter
2425  * @cmd_details: pointer to command details structure or NULL
2426  *
2427  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2428  **/
2429 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2430                                 u16 seid, bool set_filter,
2431                                 struct i40e_asq_cmd_details *cmd_details)
2432 {
2433         struct i40e_aq_desc desc;
2434         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2435                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2436         enum i40e_status_code status;
2437
2438         i40e_fill_default_direct_cmd_desc(&desc,
2439                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2440
2441         if (set_filter)
2442                 cmd->promiscuous_flags
2443                             |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2444         else
2445                 cmd->promiscuous_flags
2446                             &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2447
2448         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2449         cmd->seid = CPU_TO_LE16(seid);
2450         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2451
2452         return status;
2453 }
2454
2455 /**
2456  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2457  * @hw: pointer to the hw struct
2458  * @seid: vsi number
2459  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2460  * @cmd_details: pointer to command details structure or NULL
2461  **/
2462 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2463                                 u16 seid, bool enable,
2464                                 struct i40e_asq_cmd_details *cmd_details)
2465 {
2466         struct i40e_aq_desc desc;
2467         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2468                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2469         enum i40e_status_code status;
2470         u16 flags = 0;
2471
2472         i40e_fill_default_direct_cmd_desc(&desc,
2473                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2474         if (enable)
2475                 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2476
2477         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2478         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2479         cmd->seid = CPU_TO_LE16(seid);
2480
2481         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2482
2483         return status;
2484 }
2485
2486 /**
2487  * i40e_get_vsi_params - get VSI configuration info
2488  * @hw: pointer to the hw struct
2489  * @vsi_ctx: pointer to a vsi context struct
2490  * @cmd_details: pointer to command details structure or NULL
2491  **/
2492 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2493                                 struct i40e_vsi_context *vsi_ctx,
2494                                 struct i40e_asq_cmd_details *cmd_details)
2495 {
2496         struct i40e_aq_desc desc;
2497         struct i40e_aqc_add_get_update_vsi *cmd =
2498                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2499         struct i40e_aqc_add_get_update_vsi_completion *resp =
2500                 (struct i40e_aqc_add_get_update_vsi_completion *)
2501                 &desc.params.raw;
2502         enum i40e_status_code status;
2503
2504         UNREFERENCED_1PARAMETER(cmd_details);
2505         i40e_fill_default_direct_cmd_desc(&desc,
2506                                           i40e_aqc_opc_get_vsi_parameters);
2507
2508         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2509
2510         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2511
2512         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2513                                     sizeof(vsi_ctx->info), NULL);
2514
2515         if (status != I40E_SUCCESS)
2516                 goto aq_get_vsi_params_exit;
2517
2518         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2519         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2520         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2521         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2522
2523 aq_get_vsi_params_exit:
2524         return status;
2525 }
2526
2527 /**
2528  * i40e_aq_update_vsi_params
2529  * @hw: pointer to the hw struct
2530  * @vsi_ctx: pointer to a vsi context struct
2531  * @cmd_details: pointer to command details structure or NULL
2532  *
2533  * Update a VSI context.
2534  **/
2535 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2536                                 struct i40e_vsi_context *vsi_ctx,
2537                                 struct i40e_asq_cmd_details *cmd_details)
2538 {
2539         struct i40e_aq_desc desc;
2540         struct i40e_aqc_add_get_update_vsi *cmd =
2541                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2542         struct i40e_aqc_add_get_update_vsi_completion *resp =
2543                 (struct i40e_aqc_add_get_update_vsi_completion *)
2544                 &desc.params.raw;
2545         enum i40e_status_code status;
2546
2547         i40e_fill_default_direct_cmd_desc(&desc,
2548                                           i40e_aqc_opc_update_vsi_parameters);
2549         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2550
2551         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2552
2553         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2554                                     sizeof(vsi_ctx->info), cmd_details);
2555
2556         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2557         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2558
2559         return status;
2560 }
2561
2562 /**
2563  * i40e_aq_get_switch_config
2564  * @hw: pointer to the hardware structure
2565  * @buf: pointer to the result buffer
2566  * @buf_size: length of input buffer
2567  * @start_seid: seid to start for the report, 0 == beginning
2568  * @cmd_details: pointer to command details structure or NULL
2569  *
2570  * Fill the buf with switch configuration returned from AdminQ command
2571  **/
2572 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2573                                 struct i40e_aqc_get_switch_config_resp *buf,
2574                                 u16 buf_size, u16 *start_seid,
2575                                 struct i40e_asq_cmd_details *cmd_details)
2576 {
2577         struct i40e_aq_desc desc;
2578         struct i40e_aqc_switch_seid *scfg =
2579                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2580         enum i40e_status_code status;
2581
2582         i40e_fill_default_direct_cmd_desc(&desc,
2583                                           i40e_aqc_opc_get_switch_config);
2584         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2585         if (buf_size > I40E_AQ_LARGE_BUF)
2586                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2587         scfg->seid = CPU_TO_LE16(*start_seid);
2588
2589         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2590         *start_seid = LE16_TO_CPU(scfg->seid);
2591
2592         return status;
2593 }
2594
2595 /**
2596  * i40e_aq_set_switch_config
2597  * @hw: pointer to the hardware structure
2598  * @flags: bit flag values to set
2599  * @valid_flags: which bit flags to set
2600  * @cmd_details: pointer to command details structure or NULL
2601  *
2602  * Set switch configuration bits
2603  **/
2604 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2605                                 u16 flags, u16 valid_flags,
2606                                 struct i40e_asq_cmd_details *cmd_details)
2607 {
2608         struct i40e_aq_desc desc;
2609         struct i40e_aqc_set_switch_config *scfg =
2610                 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2611         enum i40e_status_code status;
2612
2613         i40e_fill_default_direct_cmd_desc(&desc,
2614                                           i40e_aqc_opc_set_switch_config);
2615         scfg->flags = CPU_TO_LE16(flags);
2616         scfg->valid_flags = CPU_TO_LE16(valid_flags);
2617
2618         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2619
2620         return status;
2621 }
2622
2623 /**
2624  * i40e_aq_get_firmware_version
2625  * @hw: pointer to the hw struct
2626  * @fw_major_version: firmware major version
2627  * @fw_minor_version: firmware minor version
2628  * @fw_build: firmware build number
2629  * @api_major_version: major queue version
2630  * @api_minor_version: minor queue version
2631  * @cmd_details: pointer to command details structure or NULL
2632  *
2633  * Get the firmware version from the admin queue commands
2634  **/
2635 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2636                                 u16 *fw_major_version, u16 *fw_minor_version,
2637                                 u32 *fw_build,
2638                                 u16 *api_major_version, u16 *api_minor_version,
2639                                 struct i40e_asq_cmd_details *cmd_details)
2640 {
2641         struct i40e_aq_desc desc;
2642         struct i40e_aqc_get_version *resp =
2643                 (struct i40e_aqc_get_version *)&desc.params.raw;
2644         enum i40e_status_code status;
2645
2646         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2647
2648         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2649
2650         if (status == I40E_SUCCESS) {
2651                 if (fw_major_version != NULL)
2652                         *fw_major_version = LE16_TO_CPU(resp->fw_major);
2653                 if (fw_minor_version != NULL)
2654                         *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2655                 if (fw_build != NULL)
2656                         *fw_build = LE32_TO_CPU(resp->fw_build);
2657                 if (api_major_version != NULL)
2658                         *api_major_version = LE16_TO_CPU(resp->api_major);
2659                 if (api_minor_version != NULL)
2660                         *api_minor_version = LE16_TO_CPU(resp->api_minor);
2661
2662                 /* A workaround to fix the API version in SW */
2663                 if (api_major_version && api_minor_version &&
2664                     fw_major_version && fw_minor_version &&
2665                     ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2666                     (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2667                      (*fw_major_version > 4)))
2668                         *api_minor_version = 2;
2669         }
2670
2671         return status;
2672 }
2673
2674 /**
2675  * i40e_aq_send_driver_version
2676  * @hw: pointer to the hw struct
2677  * @dv: driver's major, minor version
2678  * @cmd_details: pointer to command details structure or NULL
2679  *
2680  * Send the driver version to the firmware
2681  **/
2682 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2683                                 struct i40e_driver_version *dv,
2684                                 struct i40e_asq_cmd_details *cmd_details)
2685 {
2686         struct i40e_aq_desc desc;
2687         struct i40e_aqc_driver_version *cmd =
2688                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2689         enum i40e_status_code status;
2690         u16 len;
2691
2692         if (dv == NULL)
2693                 return I40E_ERR_PARAM;
2694
2695         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2696
2697         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2698         cmd->driver_major_ver = dv->major_version;
2699         cmd->driver_minor_ver = dv->minor_version;
2700         cmd->driver_build_ver = dv->build_version;
2701         cmd->driver_subbuild_ver = dv->subbuild_version;
2702
2703         len = 0;
2704         while (len < sizeof(dv->driver_string) &&
2705                (dv->driver_string[len] < 0x80) &&
2706                dv->driver_string[len])
2707                 len++;
2708         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2709                                        len, cmd_details);
2710
2711         return status;
2712 }
2713
2714 /**
2715  * i40e_get_link_status - get status of the HW network link
2716  * @hw: pointer to the hw struct
2717  * @link_up: pointer to bool (true/false = linkup/linkdown)
2718  *
2719  * Variable link_up true if link is up, false if link is down.
2720  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2721  *
2722  * Side effect: LinkStatusEvent reporting becomes enabled
2723  **/
2724 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2725 {
2726         enum i40e_status_code status = I40E_SUCCESS;
2727
2728         if (hw->phy.get_link_info) {
2729                 status = i40e_update_link_info(hw);
2730
2731                 if (status != I40E_SUCCESS)
2732                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2733                                    status);
2734         }
2735
2736         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2737
2738         return status;
2739 }
2740
2741 /**
2742  * i40e_updatelink_status - update status of the HW network link
2743  * @hw: pointer to the hw struct
2744  **/
2745 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2746 {
2747         struct i40e_aq_get_phy_abilities_resp abilities;
2748         enum i40e_status_code status = I40E_SUCCESS;
2749
2750         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2751         if (status)
2752                 return status;
2753
2754         /* extra checking needed to ensure link info to user is timely */
2755         if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2756             ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2757              !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2758                 status = i40e_aq_get_phy_capabilities(hw, false, false,
2759                                                       &abilities, NULL);
2760                 if (status)
2761                         return status;
2762
2763                 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2764                         sizeof(hw->phy.link_info.module_type));
2765         }
2766         return status;
2767 }
2768
2769
2770 /**
2771  * i40e_get_link_speed
2772  * @hw: pointer to the hw struct
2773  *
2774  * Returns the link speed of the adapter.
2775  **/
2776 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2777 {
2778         enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2779         enum i40e_status_code status = I40E_SUCCESS;
2780
2781         if (hw->phy.get_link_info) {
2782                 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2783
2784                 if (status != I40E_SUCCESS)
2785                         goto i40e_link_speed_exit;
2786         }
2787
2788         speed = hw->phy.link_info.link_speed;
2789
2790 i40e_link_speed_exit:
2791         return speed;
2792 }
2793
2794 /**
2795  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2796  * @hw: pointer to the hw struct
2797  * @uplink_seid: the MAC or other gizmo SEID
2798  * @downlink_seid: the VSI SEID
2799  * @enabled_tc: bitmap of TCs to be enabled
2800  * @default_port: true for default port VSI, false for control port
2801  * @veb_seid: pointer to where to put the resulting VEB SEID
2802  * @enable_stats: true to turn on VEB stats
2803  * @cmd_details: pointer to command details structure or NULL
2804  *
2805  * This asks the FW to add a VEB between the uplink and downlink
2806  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2807  **/
2808 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2809                                 u16 downlink_seid, u8 enabled_tc,
2810                                 bool default_port, u16 *veb_seid,
2811                                 bool enable_stats,
2812                                 struct i40e_asq_cmd_details *cmd_details)
2813 {
2814         struct i40e_aq_desc desc;
2815         struct i40e_aqc_add_veb *cmd =
2816                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2817         struct i40e_aqc_add_veb_completion *resp =
2818                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2819         enum i40e_status_code status;
2820         u16 veb_flags = 0;
2821
2822         /* SEIDs need to either both be set or both be 0 for floating VEB */
2823         if (!!uplink_seid != !!downlink_seid)
2824                 return I40E_ERR_PARAM;
2825
2826         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2827
2828         cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2829         cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2830         cmd->enable_tcs = enabled_tc;
2831         if (!uplink_seid)
2832                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2833         if (default_port)
2834                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2835         else
2836                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2837
2838         /* reverse logic here: set the bitflag to disable the stats */
2839         if (!enable_stats)
2840                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2841
2842         cmd->veb_flags = CPU_TO_LE16(veb_flags);
2843
2844         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2845
2846         if (!status && veb_seid)
2847                 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2848
2849         return status;
2850 }
2851
2852 /**
2853  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2854  * @hw: pointer to the hw struct
2855  * @veb_seid: the SEID of the VEB to query
2856  * @switch_id: the uplink switch id
2857  * @floating: set to true if the VEB is floating
2858  * @statistic_index: index of the stats counter block for this VEB
2859  * @vebs_used: number of VEB's used by function
2860  * @vebs_free: total VEB's not reserved by any function
2861  * @cmd_details: pointer to command details structure or NULL
2862  *
2863  * This retrieves the parameters for a particular VEB, specified by
2864  * uplink_seid, and returns them to the caller.
2865  **/
2866 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2867                                 u16 veb_seid, u16 *switch_id,
2868                                 bool *floating, u16 *statistic_index,
2869                                 u16 *vebs_used, u16 *vebs_free,
2870                                 struct i40e_asq_cmd_details *cmd_details)
2871 {
2872         struct i40e_aq_desc desc;
2873         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2874                 (struct i40e_aqc_get_veb_parameters_completion *)
2875                 &desc.params.raw;
2876         enum i40e_status_code status;
2877
2878         if (veb_seid == 0)
2879                 return I40E_ERR_PARAM;
2880
2881         i40e_fill_default_direct_cmd_desc(&desc,
2882                                           i40e_aqc_opc_get_veb_parameters);
2883         cmd_resp->seid = CPU_TO_LE16(veb_seid);
2884
2885         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2886         if (status)
2887                 goto get_veb_exit;
2888
2889         if (switch_id)
2890                 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2891         if (statistic_index)
2892                 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2893         if (vebs_used)
2894                 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2895         if (vebs_free)
2896                 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2897         if (floating) {
2898                 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2899
2900                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2901                         *floating = true;
2902                 else
2903                         *floating = false;
2904         }
2905
2906 get_veb_exit:
2907         return status;
2908 }
2909
2910 /**
2911  * i40e_aq_add_macvlan
2912  * @hw: pointer to the hw struct
2913  * @seid: VSI for the mac address
2914  * @mv_list: list of macvlans to be added
2915  * @count: length of the list
2916  * @cmd_details: pointer to command details structure or NULL
2917  *
2918  * Add MAC/VLAN addresses to the HW filtering
2919  **/
2920 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2921                         struct i40e_aqc_add_macvlan_element_data *mv_list,
2922                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2923 {
2924         struct i40e_aq_desc desc;
2925         struct i40e_aqc_macvlan *cmd =
2926                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2927         enum i40e_status_code status;
2928         u16 buf_size;
2929         int i;
2930
2931         if (count == 0 || !mv_list || !hw)
2932                 return I40E_ERR_PARAM;
2933
2934         buf_size = count * sizeof(*mv_list);
2935
2936         /* prep the rest of the request */
2937         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2938         cmd->num_addresses = CPU_TO_LE16(count);
2939         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2940         cmd->seid[1] = 0;
2941         cmd->seid[2] = 0;
2942
2943         for (i = 0; i < count; i++)
2944                 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
2945                         mv_list[i].flags |=
2946                             CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2947
2948         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2949         if (buf_size > I40E_AQ_LARGE_BUF)
2950                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2951
2952         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2953                                        cmd_details);
2954
2955         return status;
2956 }
2957
2958 /**
2959  * i40e_aq_remove_macvlan
2960  * @hw: pointer to the hw struct
2961  * @seid: VSI for the mac address
2962  * @mv_list: list of macvlans to be removed
2963  * @count: length of the list
2964  * @cmd_details: pointer to command details structure or NULL
2965  *
2966  * Remove MAC/VLAN addresses from the HW filtering
2967  **/
2968 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2969                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
2970                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2971 {
2972         struct i40e_aq_desc desc;
2973         struct i40e_aqc_macvlan *cmd =
2974                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2975         enum i40e_status_code status;
2976         u16 buf_size;
2977
2978         if (count == 0 || !mv_list || !hw)
2979                 return I40E_ERR_PARAM;
2980
2981         buf_size = count * sizeof(*mv_list);
2982
2983         /* prep the rest of the request */
2984         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2985         cmd->num_addresses = CPU_TO_LE16(count);
2986         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2987         cmd->seid[1] = 0;
2988         cmd->seid[2] = 0;
2989
2990         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2991         if (buf_size > I40E_AQ_LARGE_BUF)
2992                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2993
2994         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2995                                        cmd_details);
2996
2997         return status;
2998 }
2999
3000 /**
3001  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3002  * @hw: pointer to the hw struct
3003  * @opcode: AQ opcode for add or delete mirror rule
3004  * @sw_seid: Switch SEID (to which rule refers)
3005  * @rule_type: Rule Type (ingress/egress/VLAN)
3006  * @id: Destination VSI SEID or Rule ID
3007  * @count: length of the list
3008  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3009  * @cmd_details: pointer to command details structure or NULL
3010  * @rule_id: Rule ID returned from FW
3011  * @rule_used: Number of rules used in internal switch
3012  * @rule_free: Number of rules free in internal switch
3013  *
3014  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3015  * VEBs/VEPA elements only
3016  **/
3017 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3018                         u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3019                         u16 count, __le16 *mr_list,
3020                         struct i40e_asq_cmd_details *cmd_details,
3021                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3022 {
3023         struct i40e_aq_desc desc;
3024         struct i40e_aqc_add_delete_mirror_rule *cmd =
3025                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3026         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3027         (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3028         enum i40e_status_code status;
3029         u16 buf_size;
3030
3031         buf_size = count * sizeof(*mr_list);
3032
3033         /* prep the rest of the request */
3034         i40e_fill_default_direct_cmd_desc(&desc, opcode);
3035         cmd->seid = CPU_TO_LE16(sw_seid);
3036         cmd->rule_type = CPU_TO_LE16(rule_type &
3037                                      I40E_AQC_MIRROR_RULE_TYPE_MASK);
3038         cmd->num_entries = CPU_TO_LE16(count);
3039         /* Dest VSI for add, rule_id for delete */
3040         cmd->destination = CPU_TO_LE16(id);
3041         if (mr_list) {
3042                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3043                                                 I40E_AQ_FLAG_RD));
3044                 if (buf_size > I40E_AQ_LARGE_BUF)
3045                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3046         }
3047
3048         status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3049                                        cmd_details);
3050         if (status == I40E_SUCCESS ||
3051             hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3052                 if (rule_id)
3053                         *rule_id = LE16_TO_CPU(resp->rule_id);
3054                 if (rules_used)
3055                         *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3056                 if (rules_free)
3057                         *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3058         }
3059         return status;
3060 }
3061
3062 /**
3063  * i40e_aq_add_mirrorrule - add a mirror rule
3064  * @hw: pointer to the hw struct
3065  * @sw_seid: Switch SEID (to which rule refers)
3066  * @rule_type: Rule Type (ingress/egress/VLAN)
3067  * @dest_vsi: SEID of VSI to which packets will be mirrored
3068  * @count: length of the list
3069  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3070  * @cmd_details: pointer to command details structure or NULL
3071  * @rule_id: Rule ID returned from FW
3072  * @rule_used: Number of rules used in internal switch
3073  * @rule_free: Number of rules free in internal switch
3074  *
3075  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3076  **/
3077 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3078                         u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3079                         struct i40e_asq_cmd_details *cmd_details,
3080                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3081 {
3082         if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3083             rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3084                 if (count == 0 || !mr_list)
3085                         return I40E_ERR_PARAM;
3086         }
3087
3088         return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3089                                   rule_type, dest_vsi, count, mr_list,
3090                                   cmd_details, rule_id, rules_used, rules_free);
3091 }
3092
3093 /**
3094  * i40e_aq_delete_mirrorrule - delete a mirror rule
3095  * @hw: pointer to the hw struct
3096  * @sw_seid: Switch SEID (to which rule refers)
3097  * @rule_type: Rule Type (ingress/egress/VLAN)
3098  * @count: length of the list
3099  * @rule_id: Rule ID that is returned in the receive desc as part of
3100  *              add_mirrorrule.
3101  * @mr_list: list of mirrored VLAN IDs to be removed
3102  * @cmd_details: pointer to command details structure or NULL
3103  * @rule_used: Number of rules used in internal switch
3104  * @rule_free: Number of rules free in internal switch
3105  *
3106  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3107  **/
3108 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3109                         u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3110                         struct i40e_asq_cmd_details *cmd_details,
3111                         u16 *rules_used, u16 *rules_free)
3112 {
3113         /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3114         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3115                 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3116                  * mirroring. For other rule_type, count and rule_type should
3117                  * not matter.
3118                  */
3119                 if (count == 0 || !mr_list)
3120                         return I40E_ERR_PARAM;
3121         }
3122
3123         return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3124                                   rule_type, rule_id, count, mr_list,
3125                                   cmd_details, NULL, rules_used, rules_free);
3126 }
3127
3128 /**
3129  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3130  * @hw: pointer to the hw struct
3131  * @seid: VSI for the vlan filters
3132  * @v_list: list of vlan filters to be added
3133  * @count: length of the list
3134  * @cmd_details: pointer to command details structure or NULL
3135  **/
3136 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3137                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3138                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3139 {
3140         struct i40e_aq_desc desc;
3141         struct i40e_aqc_macvlan *cmd =
3142                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3143         enum i40e_status_code status;
3144         u16 buf_size;
3145
3146         if (count == 0 || !v_list || !hw)
3147                 return I40E_ERR_PARAM;
3148
3149         buf_size = count * sizeof(*v_list);
3150
3151         /* prep the rest of the request */
3152         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3153         cmd->num_addresses = CPU_TO_LE16(count);
3154         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3155         cmd->seid[1] = 0;
3156         cmd->seid[2] = 0;
3157
3158         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3159         if (buf_size > I40E_AQ_LARGE_BUF)
3160                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3161
3162         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3163                                        cmd_details);
3164
3165         return status;
3166 }
3167
3168 /**
3169  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3170  * @hw: pointer to the hw struct
3171  * @seid: VSI for the vlan filters
3172  * @v_list: list of macvlans to be removed
3173  * @count: length of the list
3174  * @cmd_details: pointer to command details structure or NULL
3175  **/
3176 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3177                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3178                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3179 {
3180         struct i40e_aq_desc desc;
3181         struct i40e_aqc_macvlan *cmd =
3182                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3183         enum i40e_status_code status;
3184         u16 buf_size;
3185
3186         if (count == 0 || !v_list || !hw)
3187                 return I40E_ERR_PARAM;
3188
3189         buf_size = count * sizeof(*v_list);
3190
3191         /* prep the rest of the request */
3192         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3193         cmd->num_addresses = CPU_TO_LE16(count);
3194         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3195         cmd->seid[1] = 0;
3196         cmd->seid[2] = 0;
3197
3198         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3199         if (buf_size > I40E_AQ_LARGE_BUF)
3200                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3201
3202         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3203                                        cmd_details);
3204
3205         return status;
3206 }
3207
3208 /**
3209  * i40e_aq_send_msg_to_vf
3210  * @hw: pointer to the hardware structure
3211  * @vfid: vf id to send msg
3212  * @v_opcode: opcodes for VF-PF communication
3213  * @v_retval: return error code
3214  * @msg: pointer to the msg buffer
3215  * @msglen: msg length
3216  * @cmd_details: pointer to command details
3217  *
3218  * send msg to vf
3219  **/
3220 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3221                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3222                                 struct i40e_asq_cmd_details *cmd_details)
3223 {
3224         struct i40e_aq_desc desc;
3225         struct i40e_aqc_pf_vf_message *cmd =
3226                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3227         enum i40e_status_code status;
3228
3229         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3230         cmd->id = CPU_TO_LE32(vfid);
3231         desc.cookie_high = CPU_TO_LE32(v_opcode);
3232         desc.cookie_low = CPU_TO_LE32(v_retval);
3233         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3234         if (msglen) {
3235                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3236                                                 I40E_AQ_FLAG_RD));
3237                 if (msglen > I40E_AQ_LARGE_BUF)
3238                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3239                 desc.datalen = CPU_TO_LE16(msglen);
3240         }
3241         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3242
3243         return status;
3244 }
3245
3246 /**
3247  * i40e_aq_debug_read_register
3248  * @hw: pointer to the hw struct
3249  * @reg_addr: register address
3250  * @reg_val: register value
3251  * @cmd_details: pointer to command details structure or NULL
3252  *
3253  * Read the register using the admin queue commands
3254  **/
3255 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3256                                 u32 reg_addr, u64 *reg_val,
3257                                 struct i40e_asq_cmd_details *cmd_details)
3258 {
3259         struct i40e_aq_desc desc;
3260         struct i40e_aqc_debug_reg_read_write *cmd_resp =
3261                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3262         enum i40e_status_code status;
3263
3264         if (reg_val == NULL)
3265                 return I40E_ERR_PARAM;
3266
3267         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3268
3269         cmd_resp->address = CPU_TO_LE32(reg_addr);
3270
3271         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3272
3273         if (status == I40E_SUCCESS) {
3274                 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3275                            (u64)LE32_TO_CPU(cmd_resp->value_low);
3276         }
3277
3278         return status;
3279 }
3280
3281 /**
3282  * i40e_aq_debug_write_register
3283  * @hw: pointer to the hw struct
3284  * @reg_addr: register address
3285  * @reg_val: register value
3286  * @cmd_details: pointer to command details structure or NULL
3287  *
3288  * Write to a register using the admin queue commands
3289  **/
3290 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3291                                 u32 reg_addr, u64 reg_val,
3292                                 struct i40e_asq_cmd_details *cmd_details)
3293 {
3294         struct i40e_aq_desc desc;
3295         struct i40e_aqc_debug_reg_read_write *cmd =
3296                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3297         enum i40e_status_code status;
3298
3299         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3300
3301         cmd->address = CPU_TO_LE32(reg_addr);
3302         cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3303         cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3304
3305         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3306
3307         return status;
3308 }
3309
3310 /**
3311  * i40e_aq_request_resource
3312  * @hw: pointer to the hw struct
3313  * @resource: resource id
3314  * @access: access type
3315  * @sdp_number: resource number
3316  * @timeout: the maximum time in ms that the driver may hold the resource
3317  * @cmd_details: pointer to command details structure or NULL
3318  *
3319  * requests common resource using the admin queue commands
3320  **/
3321 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3322                                 enum i40e_aq_resources_ids resource,
3323                                 enum i40e_aq_resource_access_type access,
3324                                 u8 sdp_number, u64 *timeout,
3325                                 struct i40e_asq_cmd_details *cmd_details)
3326 {
3327         struct i40e_aq_desc desc;
3328         struct i40e_aqc_request_resource *cmd_resp =
3329                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3330         enum i40e_status_code status;
3331
3332         DEBUGFUNC("i40e_aq_request_resource");
3333
3334         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3335
3336         cmd_resp->resource_id = CPU_TO_LE16(resource);
3337         cmd_resp->access_type = CPU_TO_LE16(access);
3338         cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3339
3340         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3341         /* The completion specifies the maximum time in ms that the driver
3342          * may hold the resource in the Timeout field.
3343          * If the resource is held by someone else, the command completes with
3344          * busy return value and the timeout field indicates the maximum time
3345          * the current owner of the resource has to free it.
3346          */
3347         if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3348                 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3349
3350         return status;
3351 }
3352
3353 /**
3354  * i40e_aq_release_resource
3355  * @hw: pointer to the hw struct
3356  * @resource: resource id
3357  * @sdp_number: resource number
3358  * @cmd_details: pointer to command details structure or NULL
3359  *
3360  * release common resource using the admin queue commands
3361  **/
3362 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3363                                 enum i40e_aq_resources_ids resource,
3364                                 u8 sdp_number,
3365                                 struct i40e_asq_cmd_details *cmd_details)
3366 {
3367         struct i40e_aq_desc desc;
3368         struct i40e_aqc_request_resource *cmd =
3369                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3370         enum i40e_status_code status;
3371
3372         DEBUGFUNC("i40e_aq_release_resource");
3373
3374         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3375
3376         cmd->resource_id = CPU_TO_LE16(resource);
3377         cmd->resource_number = CPU_TO_LE32(sdp_number);
3378
3379         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3380
3381         return status;
3382 }
3383
3384 /**
3385  * i40e_aq_read_nvm
3386  * @hw: pointer to the hw struct
3387  * @module_pointer: module pointer location in words from the NVM beginning
3388  * @offset: byte offset from the module beginning
3389  * @length: length of the section to be read (in bytes from the offset)
3390  * @data: command buffer (size [bytes] = length)
3391  * @last_command: tells if this is the last command in a series
3392  * @cmd_details: pointer to command details structure or NULL
3393  *
3394  * Read the NVM using the admin queue commands
3395  **/
3396 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3397                                 u32 offset, u16 length, void *data,
3398                                 bool last_command,
3399                                 struct i40e_asq_cmd_details *cmd_details)
3400 {
3401         struct i40e_aq_desc desc;
3402         struct i40e_aqc_nvm_update *cmd =
3403                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3404         enum i40e_status_code status;
3405
3406         DEBUGFUNC("i40e_aq_read_nvm");
3407
3408         /* In offset the highest byte must be zeroed. */
3409         if (offset & 0xFF000000) {
3410                 status = I40E_ERR_PARAM;
3411                 goto i40e_aq_read_nvm_exit;
3412         }
3413
3414         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3415
3416         /* If this is the last command in a series, set the proper flag. */
3417         if (last_command)
3418                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3419         cmd->module_pointer = module_pointer;
3420         cmd->offset = CPU_TO_LE32(offset);
3421         cmd->length = CPU_TO_LE16(length);
3422
3423         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3424         if (length > I40E_AQ_LARGE_BUF)
3425                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3426
3427         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3428
3429 i40e_aq_read_nvm_exit:
3430         return status;
3431 }
3432
3433 /**
3434  * i40e_aq_read_nvm_config - read an nvm config block
3435  * @hw: pointer to the hw struct
3436  * @cmd_flags: NVM access admin command bits
3437  * @field_id: field or feature id
3438  * @data: buffer for result
3439  * @buf_size: buffer size
3440  * @element_count: pointer to count of elements read by FW
3441  * @cmd_details: pointer to command details structure or NULL
3442  **/
3443 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3444                                 u8 cmd_flags, u32 field_id, void *data,
3445                                 u16 buf_size, u16 *element_count,
3446                                 struct i40e_asq_cmd_details *cmd_details)
3447 {
3448         struct i40e_aq_desc desc;
3449         struct i40e_aqc_nvm_config_read *cmd =
3450                 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3451         enum i40e_status_code status;
3452
3453         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3454         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3455         if (buf_size > I40E_AQ_LARGE_BUF)
3456                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3457
3458         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3459         cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3460         if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3461                 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3462         else
3463                 cmd->element_id_msw = 0;
3464
3465         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3466
3467         if (!status && element_count)
3468                 *element_count = LE16_TO_CPU(cmd->element_count);
3469
3470         return status;
3471 }
3472
3473 /**
3474  * i40e_aq_write_nvm_config - write an nvm config block
3475  * @hw: pointer to the hw struct
3476  * @cmd_flags: NVM access admin command bits
3477  * @data: buffer for result
3478  * @buf_size: buffer size
3479  * @element_count: count of elements to be written
3480  * @cmd_details: pointer to command details structure or NULL
3481  **/
3482 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3483                                 u8 cmd_flags, void *data, u16 buf_size,
3484                                 u16 element_count,
3485                                 struct i40e_asq_cmd_details *cmd_details)
3486 {
3487         struct i40e_aq_desc desc;
3488         struct i40e_aqc_nvm_config_write *cmd =
3489                 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3490         enum i40e_status_code status;
3491
3492         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3493         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3494         if (buf_size > I40E_AQ_LARGE_BUF)
3495                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3496
3497         cmd->element_count = CPU_TO_LE16(element_count);
3498         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3499         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3500
3501         return status;
3502 }
3503
3504 /**
3505  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3506  * @hw: pointer to the hw struct
3507  * @cmd_details: pointer to command details structure or NULL
3508  **/
3509 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3510                                 void *buff, u16 buff_size,
3511                                 struct i40e_asq_cmd_details *cmd_details)
3512 {
3513         struct i40e_aq_desc desc;
3514         enum i40e_status_code status;
3515
3516         UNREFERENCED_2PARAMETER(buff, buff_size);
3517
3518         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3519         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3520         if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3521                 status = I40E_ERR_NOT_IMPLEMENTED;
3522
3523         return status;
3524 }
3525
3526 /**
3527  * i40e_aq_erase_nvm
3528  * @hw: pointer to the hw struct
3529  * @module_pointer: module pointer location in words from the NVM beginning
3530  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3531  * @length: length of the section to be erased (expressed in 4 KB)
3532  * @last_command: tells if this is the last command in a series
3533  * @cmd_details: pointer to command details structure or NULL
3534  *
3535  * Erase the NVM sector using the admin queue commands
3536  **/
3537 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3538                                 u32 offset, u16 length, bool last_command,
3539                                 struct i40e_asq_cmd_details *cmd_details)
3540 {
3541         struct i40e_aq_desc desc;
3542         struct i40e_aqc_nvm_update *cmd =
3543                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3544         enum i40e_status_code status;
3545
3546         DEBUGFUNC("i40e_aq_erase_nvm");
3547
3548         /* In offset the highest byte must be zeroed. */
3549         if (offset & 0xFF000000) {
3550                 status = I40E_ERR_PARAM;
3551                 goto i40e_aq_erase_nvm_exit;
3552         }
3553
3554         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3555
3556         /* If this is the last command in a series, set the proper flag. */
3557         if (last_command)
3558                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3559         cmd->module_pointer = module_pointer;
3560         cmd->offset = CPU_TO_LE32(offset);
3561         cmd->length = CPU_TO_LE16(length);
3562
3563         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3564
3565 i40e_aq_erase_nvm_exit:
3566         return status;
3567 }
3568
3569 /**
3570  * i40e_parse_discover_capabilities
3571  * @hw: pointer to the hw struct
3572  * @buff: pointer to a buffer containing device/function capability records
3573  * @cap_count: number of capability records in the list
3574  * @list_type_opc: type of capabilities list to parse
3575  *
3576  * Parse the device/function capabilities list.
3577  **/
3578 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3579                                      u32 cap_count,
3580                                      enum i40e_admin_queue_opc list_type_opc)
3581 {
3582         struct i40e_aqc_list_capabilities_element_resp *cap;
3583         u32 valid_functions, num_functions;
3584         u32 number, logical_id, phys_id;
3585         struct i40e_hw_capabilities *p;
3586         u8 major_rev;
3587         u32 i = 0;
3588         u16 id;
3589
3590         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3591
3592         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3593                 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3594         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3595                 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3596         else
3597                 return;
3598
3599         for (i = 0; i < cap_count; i++, cap++) {
3600                 id = LE16_TO_CPU(cap->id);
3601                 number = LE32_TO_CPU(cap->number);
3602                 logical_id = LE32_TO_CPU(cap->logical_id);
3603                 phys_id = LE32_TO_CPU(cap->phys_id);
3604                 major_rev = cap->major_rev;
3605
3606                 switch (id) {
3607                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3608                         p->switch_mode = number;
3609                         i40e_debug(hw, I40E_DEBUG_INIT,
3610                                    "HW Capability: Switch mode = %d\n",
3611                                    p->switch_mode);
3612                         break;
3613                 case I40E_AQ_CAP_ID_MNG_MODE:
3614                         p->management_mode = number;
3615                         if (major_rev > 1) {
3616                                 p->mng_protocols_over_mctp = logical_id;
3617                                 i40e_debug(hw, I40E_DEBUG_INIT,
3618                                            "HW Capability: Protocols over MCTP = %d\n",
3619                                            p->mng_protocols_over_mctp);
3620                         } else {
3621                                 p->mng_protocols_over_mctp = 0;
3622                         }
3623                         i40e_debug(hw, I40E_DEBUG_INIT,
3624                                    "HW Capability: Management Mode = %d\n",
3625                                    p->management_mode);
3626                         break;
3627                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3628                         p->npar_enable = number;
3629                         i40e_debug(hw, I40E_DEBUG_INIT,
3630                                    "HW Capability: NPAR enable = %d\n",
3631                                    p->npar_enable);
3632                         break;
3633                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3634                         p->os2bmc = number;
3635                         i40e_debug(hw, I40E_DEBUG_INIT,
3636                                    "HW Capability: OS2BMC = %d\n", p->os2bmc);
3637                         break;
3638                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3639                         p->valid_functions = number;
3640                         i40e_debug(hw, I40E_DEBUG_INIT,
3641                                    "HW Capability: Valid Functions = %d\n",
3642                                    p->valid_functions);
3643                         break;
3644                 case I40E_AQ_CAP_ID_SRIOV:
3645                         if (number == 1)
3646                                 p->sr_iov_1_1 = true;
3647                         i40e_debug(hw, I40E_DEBUG_INIT,
3648                                    "HW Capability: SR-IOV = %d\n",
3649                                    p->sr_iov_1_1);
3650                         break;
3651                 case I40E_AQ_CAP_ID_VF:
3652                         p->num_vfs = number;
3653                         p->vf_base_id = logical_id;
3654                         i40e_debug(hw, I40E_DEBUG_INIT,
3655                                    "HW Capability: VF count = %d\n",
3656                                    p->num_vfs);
3657                         i40e_debug(hw, I40E_DEBUG_INIT,
3658                                    "HW Capability: VF base_id = %d\n",
3659                                    p->vf_base_id);
3660                         break;
3661                 case I40E_AQ_CAP_ID_VMDQ:
3662                         if (number == 1)
3663                                 p->vmdq = true;
3664                         i40e_debug(hw, I40E_DEBUG_INIT,
3665                                    "HW Capability: VMDQ = %d\n", p->vmdq);
3666                         break;
3667                 case I40E_AQ_CAP_ID_8021QBG:
3668                         if (number == 1)
3669                                 p->evb_802_1_qbg = true;
3670                         i40e_debug(hw, I40E_DEBUG_INIT,
3671                                    "HW Capability: 802.1Qbg = %d\n", number);
3672                         break;
3673                 case I40E_AQ_CAP_ID_8021QBR:
3674                         if (number == 1)
3675                                 p->evb_802_1_qbh = true;
3676                         i40e_debug(hw, I40E_DEBUG_INIT,
3677                                    "HW Capability: 802.1Qbh = %d\n", number);
3678                         break;
3679                 case I40E_AQ_CAP_ID_VSI:
3680                         p->num_vsis = number;
3681                         i40e_debug(hw, I40E_DEBUG_INIT,
3682                                    "HW Capability: VSI count = %d\n",
3683                                    p->num_vsis);
3684                         break;
3685                 case I40E_AQ_CAP_ID_DCB:
3686                         if (number == 1) {
3687                                 p->dcb = true;
3688                                 p->enabled_tcmap = logical_id;
3689                                 p->maxtc = phys_id;
3690                         }
3691                         i40e_debug(hw, I40E_DEBUG_INIT,
3692                                    "HW Capability: DCB = %d\n", p->dcb);
3693                         i40e_debug(hw, I40E_DEBUG_INIT,
3694                                    "HW Capability: TC Mapping = %d\n",
3695                                    logical_id);
3696                         i40e_debug(hw, I40E_DEBUG_INIT,
3697                                    "HW Capability: TC Max = %d\n", p->maxtc);
3698                         break;
3699                 case I40E_AQ_CAP_ID_FCOE:
3700                         if (number == 1)
3701                                 p->fcoe = true;
3702                         i40e_debug(hw, I40E_DEBUG_INIT,
3703                                    "HW Capability: FCOE = %d\n", p->fcoe);
3704                         break;
3705                 case I40E_AQ_CAP_ID_ISCSI:
3706                         if (number == 1)
3707                                 p->iscsi = true;
3708                         i40e_debug(hw, I40E_DEBUG_INIT,
3709                                    "HW Capability: iSCSI = %d\n", p->iscsi);
3710                         break;
3711                 case I40E_AQ_CAP_ID_RSS:
3712                         p->rss = true;
3713                         p->rss_table_size = number;
3714                         p->rss_table_entry_width = logical_id;
3715                         i40e_debug(hw, I40E_DEBUG_INIT,
3716                                    "HW Capability: RSS = %d\n", p->rss);
3717                         i40e_debug(hw, I40E_DEBUG_INIT,
3718                                    "HW Capability: RSS table size = %d\n",
3719                                    p->rss_table_size);
3720                         i40e_debug(hw, I40E_DEBUG_INIT,
3721                                    "HW Capability: RSS table width = %d\n",
3722                                    p->rss_table_entry_width);
3723                         break;
3724                 case I40E_AQ_CAP_ID_RXQ:
3725                         p->num_rx_qp = number;
3726                         p->base_queue = phys_id;
3727                         i40e_debug(hw, I40E_DEBUG_INIT,
3728                                    "HW Capability: Rx QP = %d\n", number);
3729                         i40e_debug(hw, I40E_DEBUG_INIT,
3730                                    "HW Capability: base_queue = %d\n",
3731                                    p->base_queue);
3732                         break;
3733                 case I40E_AQ_CAP_ID_TXQ:
3734                         p->num_tx_qp = number;
3735                         p->base_queue = phys_id;
3736                         i40e_debug(hw, I40E_DEBUG_INIT,
3737                                    "HW Capability: Tx QP = %d\n", number);
3738                         i40e_debug(hw, I40E_DEBUG_INIT,
3739                                    "HW Capability: base_queue = %d\n",
3740                                    p->base_queue);
3741                         break;
3742                 case I40E_AQ_CAP_ID_MSIX:
3743                         p->num_msix_vectors = number;
3744                         i40e_debug(hw, I40E_DEBUG_INIT,
3745                                    "HW Capability: MSIX vector count = %d\n",
3746                                    p->num_msix_vectors);
3747                         break;
3748                 case I40E_AQ_CAP_ID_VF_MSIX:
3749                         p->num_msix_vectors_vf = number;
3750                         i40e_debug(hw, I40E_DEBUG_INIT,
3751                                    "HW Capability: MSIX VF vector count = %d\n",
3752                                    p->num_msix_vectors_vf);
3753                         break;
3754                 case I40E_AQ_CAP_ID_FLEX10:
3755                         if (major_rev == 1) {
3756                                 if (number == 1) {
3757                                         p->flex10_enable = true;
3758                                         p->flex10_capable = true;
3759                                 }
3760                         } else {
3761                                 /* Capability revision >= 2 */
3762                                 if (number & 1)
3763                                         p->flex10_enable = true;
3764                                 if (number & 2)
3765                                         p->flex10_capable = true;
3766                         }
3767                         p->flex10_mode = logical_id;
3768                         p->flex10_status = phys_id;
3769                         i40e_debug(hw, I40E_DEBUG_INIT,
3770                                    "HW Capability: Flex10 mode = %d\n",
3771                                    p->flex10_mode);
3772                         i40e_debug(hw, I40E_DEBUG_INIT,
3773                                    "HW Capability: Flex10 status = %d\n",
3774                                    p->flex10_status);
3775                         break;
3776                 case I40E_AQ_CAP_ID_CEM:
3777                         if (number == 1)
3778                                 p->mgmt_cem = true;
3779                         i40e_debug(hw, I40E_DEBUG_INIT,
3780                                    "HW Capability: CEM = %d\n", p->mgmt_cem);
3781                         break;
3782                 case I40E_AQ_CAP_ID_IWARP:
3783                         if (number == 1)
3784                                 p->iwarp = true;
3785                         i40e_debug(hw, I40E_DEBUG_INIT,
3786                                    "HW Capability: iWARP = %d\n", p->iwarp);
3787                         break;
3788                 case I40E_AQ_CAP_ID_LED:
3789                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3790                                 p->led[phys_id] = true;
3791                         i40e_debug(hw, I40E_DEBUG_INIT,
3792                                    "HW Capability: LED - PIN %d\n", phys_id);
3793                         break;
3794                 case I40E_AQ_CAP_ID_SDP:
3795                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3796                                 p->sdp[phys_id] = true;
3797                         i40e_debug(hw, I40E_DEBUG_INIT,
3798                                    "HW Capability: SDP - PIN %d\n", phys_id);
3799                         break;
3800                 case I40E_AQ_CAP_ID_MDIO:
3801                         if (number == 1) {
3802                                 p->mdio_port_num = phys_id;
3803                                 p->mdio_port_mode = logical_id;
3804                         }
3805                         i40e_debug(hw, I40E_DEBUG_INIT,
3806                                    "HW Capability: MDIO port number = %d\n",
3807                                    p->mdio_port_num);
3808                         i40e_debug(hw, I40E_DEBUG_INIT,
3809                                    "HW Capability: MDIO port mode = %d\n",
3810                                    p->mdio_port_mode);
3811                         break;
3812                 case I40E_AQ_CAP_ID_1588:
3813                         if (number == 1)
3814                                 p->ieee_1588 = true;
3815                         i40e_debug(hw, I40E_DEBUG_INIT,
3816                                    "HW Capability: IEEE 1588 = %d\n",
3817                                    p->ieee_1588);
3818                         break;
3819                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3820                         p->fd = true;
3821                         p->fd_filters_guaranteed = number;
3822                         p->fd_filters_best_effort = logical_id;
3823                         i40e_debug(hw, I40E_DEBUG_INIT,
3824                                    "HW Capability: Flow Director = 1\n");
3825                         i40e_debug(hw, I40E_DEBUG_INIT,
3826                                    "HW Capability: Guaranteed FD filters = %d\n",
3827                                    p->fd_filters_guaranteed);
3828                         break;
3829                 case I40E_AQ_CAP_ID_WSR_PROT:
3830                         p->wr_csr_prot = (u64)number;
3831                         p->wr_csr_prot |= (u64)logical_id << 32;
3832                         i40e_debug(hw, I40E_DEBUG_INIT,
3833                                    "HW Capability: wr_csr_prot = 0x%llX\n\n",
3834                                    (p->wr_csr_prot & 0xffff));
3835                         break;
3836                 case I40E_AQ_CAP_ID_NVM_MGMT:
3837                         if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3838                                 p->sec_rev_disabled = true;
3839                         if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3840                                 p->update_disabled = true;
3841                         break;
3842 #ifdef X722_SUPPORT
3843                 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3844                         hw->num_wol_proxy_filters = (u16)number;
3845                         hw->wol_proxy_vsi_seid = (u16)logical_id;
3846                         p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3847                         if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3848                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3849                         else
3850                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3851                         p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3852                         i40e_debug(hw, I40E_DEBUG_INIT,
3853                                    "HW Capability: WOL proxy filters = %d\n",
3854                                    hw->num_wol_proxy_filters);
3855                         break;
3856 #endif
3857                 default:
3858                         break;
3859                 }
3860         }
3861
3862         if (p->fcoe)
3863                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3864
3865         /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3866         p->fcoe = false;
3867
3868         /* count the enabled ports (aka the "not disabled" ports) */
3869         hw->num_ports = 0;
3870         for (i = 0; i < 4; i++) {
3871                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3872                 u64 port_cfg = 0;
3873
3874                 /* use AQ read to get the physical register offset instead
3875                  * of the port relative offset
3876                  */
3877                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3878                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3879                         hw->num_ports++;
3880         }
3881
3882         valid_functions = p->valid_functions;
3883         num_functions = 0;
3884         while (valid_functions) {
3885                 if (valid_functions & 1)
3886                         num_functions++;
3887                 valid_functions >>= 1;
3888         }
3889
3890         /* partition id is 1-based, and functions are evenly spread
3891          * across the ports as partitions
3892          */
3893         hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3894         hw->num_partitions = num_functions / hw->num_ports;
3895
3896         /* additional HW specific goodies that might
3897          * someday be HW version specific
3898          */
3899         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3900 }
3901
3902 /**
3903  * i40e_aq_discover_capabilities
3904  * @hw: pointer to the hw struct
3905  * @buff: a virtual buffer to hold the capabilities
3906  * @buff_size: Size of the virtual buffer
3907  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3908  * @list_type_opc: capabilities type to discover - pass in the command opcode
3909  * @cmd_details: pointer to command details structure or NULL
3910  *
3911  * Get the device capabilities descriptions from the firmware
3912  **/
3913 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3914                                 void *buff, u16 buff_size, u16 *data_size,
3915                                 enum i40e_admin_queue_opc list_type_opc,
3916                                 struct i40e_asq_cmd_details *cmd_details)
3917 {
3918         struct i40e_aqc_list_capabilites *cmd;
3919         struct i40e_aq_desc desc;
3920         enum i40e_status_code status = I40E_SUCCESS;
3921
3922         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3923
3924         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3925                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3926                 status = I40E_ERR_PARAM;
3927                 goto exit;
3928         }
3929
3930         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3931
3932         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3933         if (buff_size > I40E_AQ_LARGE_BUF)
3934                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3935
3936         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3937         *data_size = LE16_TO_CPU(desc.datalen);
3938
3939         if (status)
3940                 goto exit;
3941
3942         i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3943                                          list_type_opc);
3944
3945 exit:
3946         return status;
3947 }
3948
3949 /**
3950  * i40e_aq_update_nvm
3951  * @hw: pointer to the hw struct
3952  * @module_pointer: module pointer location in words from the NVM beginning
3953  * @offset: byte offset from the module beginning
3954  * @length: length of the section to be written (in bytes from the offset)
3955  * @data: command buffer (size [bytes] = length)
3956  * @last_command: tells if this is the last command in a series
3957  * @cmd_details: pointer to command details structure or NULL
3958  *
3959  * Update the NVM using the admin queue commands
3960  **/
3961 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3962                                 u32 offset, u16 length, void *data,
3963                                 bool last_command,
3964                                 struct i40e_asq_cmd_details *cmd_details)
3965 {
3966         struct i40e_aq_desc desc;
3967         struct i40e_aqc_nvm_update *cmd =
3968                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3969         enum i40e_status_code status;
3970
3971         DEBUGFUNC("i40e_aq_update_nvm");
3972
3973         /* In offset the highest byte must be zeroed. */
3974         if (offset & 0xFF000000) {
3975                 status = I40E_ERR_PARAM;
3976                 goto i40e_aq_update_nvm_exit;
3977         }
3978
3979         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3980
3981         /* If this is the last command in a series, set the proper flag. */
3982         if (last_command)
3983                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3984         cmd->module_pointer = module_pointer;
3985         cmd->offset = CPU_TO_LE32(offset);
3986         cmd->length = CPU_TO_LE16(length);
3987
3988         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3989         if (length > I40E_AQ_LARGE_BUF)
3990                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3991
3992         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3993
3994 i40e_aq_update_nvm_exit:
3995         return status;
3996 }
3997
3998 /**
3999  * i40e_aq_get_lldp_mib
4000  * @hw: pointer to the hw struct
4001  * @bridge_type: type of bridge requested
4002  * @mib_type: Local, Remote or both Local and Remote MIBs
4003  * @buff: pointer to a user supplied buffer to store the MIB block
4004  * @buff_size: size of the buffer (in bytes)
4005  * @local_len : length of the returned Local LLDP MIB
4006  * @remote_len: length of the returned Remote LLDP MIB
4007  * @cmd_details: pointer to command details structure or NULL
4008  *
4009  * Requests the complete LLDP MIB (entire packet).
4010  **/
4011 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4012                                 u8 mib_type, void *buff, u16 buff_size,
4013                                 u16 *local_len, u16 *remote_len,
4014                                 struct i40e_asq_cmd_details *cmd_details)
4015 {
4016         struct i40e_aq_desc desc;
4017         struct i40e_aqc_lldp_get_mib *cmd =
4018                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4019         struct i40e_aqc_lldp_get_mib *resp =
4020                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4021         enum i40e_status_code status;
4022
4023         if (buff_size == 0 || !buff)
4024                 return I40E_ERR_PARAM;
4025
4026         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4027         /* Indirect Command */
4028         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4029
4030         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4031         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4032                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4033
4034         desc.datalen = CPU_TO_LE16(buff_size);
4035
4036         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4037         if (buff_size > I40E_AQ_LARGE_BUF)
4038                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4039
4040         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4041         if (!status) {
4042                 if (local_len != NULL)
4043                         *local_len = LE16_TO_CPU(resp->local_len);
4044                 if (remote_len != NULL)
4045                         *remote_len = LE16_TO_CPU(resp->remote_len);
4046         }
4047
4048         return status;
4049 }
4050
4051  /**
4052  * i40e_aq_set_lldp_mib - Set the LLDP MIB
4053  * @hw: pointer to the hw struct
4054  * @mib_type: Local, Remote or both Local and Remote MIBs
4055  * @buff: pointer to a user supplied buffer to store the MIB block
4056  * @buff_size: size of the buffer (in bytes)
4057  * @cmd_details: pointer to command details structure or NULL
4058  *
4059  * Set the LLDP MIB.
4060  **/
4061 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4062                                 u8 mib_type, void *buff, u16 buff_size,
4063                                 struct i40e_asq_cmd_details *cmd_details)
4064 {
4065         struct i40e_aq_desc desc;
4066         struct i40e_aqc_lldp_set_local_mib *cmd =
4067                 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4068         enum i40e_status_code status;
4069
4070         if (buff_size == 0 || !buff)
4071                 return I40E_ERR_PARAM;
4072
4073         i40e_fill_default_direct_cmd_desc(&desc,
4074                                 i40e_aqc_opc_lldp_set_local_mib);
4075         /* Indirect Command */
4076         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4077         if (buff_size > I40E_AQ_LARGE_BUF)
4078                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4079         desc.datalen = CPU_TO_LE16(buff_size);
4080
4081         cmd->type = mib_type;
4082         cmd->length = CPU_TO_LE16(buff_size);
4083         cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4084         cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4085
4086         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4087         return status;
4088 }
4089
4090 /**
4091  * i40e_aq_cfg_lldp_mib_change_event
4092  * @hw: pointer to the hw struct
4093  * @enable_update: Enable or Disable event posting
4094  * @cmd_details: pointer to command details structure or NULL
4095  *
4096  * Enable or Disable posting of an event on ARQ when LLDP MIB
4097  * associated with the interface changes
4098  **/
4099 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4100                                 bool enable_update,
4101                                 struct i40e_asq_cmd_details *cmd_details)
4102 {
4103         struct i40e_aq_desc desc;
4104         struct i40e_aqc_lldp_update_mib *cmd =
4105                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4106         enum i40e_status_code status;
4107
4108         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4109
4110         if (!enable_update)
4111                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4112
4113         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4114
4115         return status;
4116 }
4117
4118 /**
4119  * i40e_aq_add_lldp_tlv
4120  * @hw: pointer to the hw struct
4121  * @bridge_type: type of bridge
4122  * @buff: buffer with TLV to add
4123  * @buff_size: length of the buffer
4124  * @tlv_len: length of the TLV to be added
4125  * @mib_len: length of the LLDP MIB returned in response
4126  * @cmd_details: pointer to command details structure or NULL
4127  *
4128  * Add the specified TLV to LLDP Local MIB for the given bridge type,
4129  * it is responsibility of the caller to make sure that the TLV is not
4130  * already present in the LLDPDU.
4131  * In return firmware will write the complete LLDP MIB with the newly
4132  * added TLV in the response buffer.
4133  **/
4134 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4135                                 void *buff, u16 buff_size, u16 tlv_len,
4136                                 u16 *mib_len,
4137                                 struct i40e_asq_cmd_details *cmd_details)
4138 {
4139         struct i40e_aq_desc desc;
4140         struct i40e_aqc_lldp_add_tlv *cmd =
4141                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4142         enum i40e_status_code status;
4143
4144         if (buff_size == 0 || !buff || tlv_len == 0)
4145                 return I40E_ERR_PARAM;
4146
4147         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4148
4149         /* Indirect Command */
4150         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4151         if (buff_size > I40E_AQ_LARGE_BUF)
4152                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4153         desc.datalen = CPU_TO_LE16(buff_size);
4154
4155         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4156                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4157         cmd->len = CPU_TO_LE16(tlv_len);
4158
4159         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4160         if (!status) {
4161                 if (mib_len != NULL)
4162                         *mib_len = LE16_TO_CPU(desc.datalen);
4163         }
4164
4165         return status;
4166 }
4167
4168 /**
4169  * i40e_aq_update_lldp_tlv
4170  * @hw: pointer to the hw struct
4171  * @bridge_type: type of bridge
4172  * @buff: buffer with TLV to update
4173  * @buff_size: size of the buffer holding original and updated TLVs
4174  * @old_len: Length of the Original TLV
4175  * @new_len: Length of the Updated TLV
4176  * @offset: offset of the updated TLV in the buff
4177  * @mib_len: length of the returned LLDP MIB
4178  * @cmd_details: pointer to command details structure or NULL
4179  *
4180  * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4181  * Firmware will place the complete LLDP MIB in response buffer with the
4182  * updated TLV.
4183  **/
4184 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4185                                 u8 bridge_type, void *buff, u16 buff_size,
4186                                 u16 old_len, u16 new_len, u16 offset,
4187                                 u16 *mib_len,
4188                                 struct i40e_asq_cmd_details *cmd_details)
4189 {
4190         struct i40e_aq_desc desc;
4191         struct i40e_aqc_lldp_update_tlv *cmd =
4192                 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4193         enum i40e_status_code status;
4194
4195         if (buff_size == 0 || !buff || offset == 0 ||
4196             old_len == 0 || new_len == 0)
4197                 return I40E_ERR_PARAM;
4198
4199         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4200
4201         /* Indirect Command */
4202         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4203         if (buff_size > I40E_AQ_LARGE_BUF)
4204                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4205         desc.datalen = CPU_TO_LE16(buff_size);
4206
4207         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4208                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4209         cmd->old_len = CPU_TO_LE16(old_len);
4210         cmd->new_offset = CPU_TO_LE16(offset);
4211         cmd->new_len = CPU_TO_LE16(new_len);
4212
4213         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4214         if (!status) {
4215                 if (mib_len != NULL)
4216                         *mib_len = LE16_TO_CPU(desc.datalen);
4217         }
4218
4219         return status;
4220 }
4221
4222 /**
4223  * i40e_aq_delete_lldp_tlv
4224  * @hw: pointer to the hw struct
4225  * @bridge_type: type of bridge
4226  * @buff: pointer to a user supplied buffer that has the TLV
4227  * @buff_size: length of the buffer
4228  * @tlv_len: length of the TLV to be deleted
4229  * @mib_len: length of the returned LLDP MIB
4230  * @cmd_details: pointer to command details structure or NULL
4231  *
4232  * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4233  * The firmware places the entire LLDP MIB in the response buffer.
4234  **/
4235 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4236                                 u8 bridge_type, void *buff, u16 buff_size,
4237                                 u16 tlv_len, u16 *mib_len,
4238                                 struct i40e_asq_cmd_details *cmd_details)
4239 {
4240         struct i40e_aq_desc desc;
4241         struct i40e_aqc_lldp_add_tlv *cmd =
4242                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4243         enum i40e_status_code status;
4244
4245         if (buff_size == 0 || !buff)
4246                 return I40E_ERR_PARAM;
4247
4248         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4249
4250         /* Indirect Command */
4251         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4252         if (buff_size > I40E_AQ_LARGE_BUF)
4253                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4254         desc.datalen = CPU_TO_LE16(buff_size);
4255         cmd->len = CPU_TO_LE16(tlv_len);
4256         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4257                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4258
4259         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4260         if (!status) {
4261                 if (mib_len != NULL)
4262                         *mib_len = LE16_TO_CPU(desc.datalen);
4263         }
4264
4265         return status;
4266 }
4267
4268 /**
4269  * i40e_aq_stop_lldp
4270  * @hw: pointer to the hw struct
4271  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4272  * @cmd_details: pointer to command details structure or NULL
4273  *
4274  * Stop or Shutdown the embedded LLDP Agent
4275  **/
4276 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4277                                 struct i40e_asq_cmd_details *cmd_details)
4278 {
4279         struct i40e_aq_desc desc;
4280         struct i40e_aqc_lldp_stop *cmd =
4281                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4282         enum i40e_status_code status;
4283
4284         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4285
4286         if (shutdown_agent)
4287                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4288
4289         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4290
4291         return status;
4292 }
4293
4294 /**
4295  * i40e_aq_start_lldp
4296  * @hw: pointer to the hw struct
4297  * @cmd_details: pointer to command details structure or NULL
4298  *
4299  * Start the embedded LLDP Agent on all ports.
4300  **/
4301 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4302                                 struct i40e_asq_cmd_details *cmd_details)
4303 {
4304         struct i40e_aq_desc desc;
4305         struct i40e_aqc_lldp_start *cmd =
4306                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4307         enum i40e_status_code status;
4308
4309         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4310
4311         cmd->command = I40E_AQ_LLDP_AGENT_START;
4312
4313         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4314
4315         return status;
4316 }
4317
4318 /**
4319  * i40e_aq_get_cee_dcb_config
4320  * @hw: pointer to the hw struct
4321  * @buff: response buffer that stores CEE operational configuration
4322  * @buff_size: size of the buffer passed
4323  * @cmd_details: pointer to command details structure or NULL
4324  *
4325  * Get CEE DCBX mode operational configuration from firmware
4326  **/
4327 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4328                                 void *buff, u16 buff_size,
4329                                 struct i40e_asq_cmd_details *cmd_details)
4330 {
4331         struct i40e_aq_desc desc;
4332         enum i40e_status_code status;
4333
4334         if (buff_size == 0 || !buff)
4335                 return I40E_ERR_PARAM;
4336
4337         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4338
4339         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4340         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4341                                        cmd_details);
4342
4343         return status;
4344 }
4345
4346 /**
4347  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4348  * @hw: pointer to the hw struct
4349  * @start_agent: True if DCBx Agent needs to be Started
4350  *                              False if DCBx Agent needs to be Stopped
4351  * @cmd_details: pointer to command details structure or NULL
4352  *
4353  * Start/Stop the embedded dcbx Agent
4354  **/
4355 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4356                                 bool start_agent,
4357                                 struct i40e_asq_cmd_details *cmd_details)
4358 {
4359         struct i40e_aq_desc desc;
4360         struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4361                 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4362                                 &desc.params.raw;
4363         enum i40e_status_code status;
4364
4365         i40e_fill_default_direct_cmd_desc(&desc,
4366                                 i40e_aqc_opc_lldp_stop_start_spec_agent);
4367
4368         if (start_agent)
4369                 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4370
4371         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4372
4373         return status;
4374 }
4375
4376 /**
4377  * i40e_aq_add_udp_tunnel
4378  * @hw: pointer to the hw struct
4379  * @udp_port: the UDP port to add
4380  * @header_len: length of the tunneling header length in DWords
4381  * @protocol_index: protocol index type
4382  * @filter_index: pointer to filter index
4383  * @cmd_details: pointer to command details structure or NULL
4384  **/
4385 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4386                                 u16 udp_port, u8 protocol_index,
4387                                 u8 *filter_index,
4388                                 struct i40e_asq_cmd_details *cmd_details)
4389 {
4390         struct i40e_aq_desc desc;
4391         struct i40e_aqc_add_udp_tunnel *cmd =
4392                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4393         struct i40e_aqc_del_udp_tunnel_completion *resp =
4394                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4395         enum i40e_status_code status;
4396
4397         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4398
4399         cmd->udp_port = CPU_TO_LE16(udp_port);
4400         cmd->protocol_type = protocol_index;
4401
4402         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4403
4404         if (!status && filter_index)
4405                 *filter_index = resp->index;
4406
4407         return status;
4408 }
4409
4410 /**
4411  * i40e_aq_del_udp_tunnel
4412  * @hw: pointer to the hw struct
4413  * @index: filter index
4414  * @cmd_details: pointer to command details structure or NULL
4415  **/
4416 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4417                                 struct i40e_asq_cmd_details *cmd_details)
4418 {
4419         struct i40e_aq_desc desc;
4420         struct i40e_aqc_remove_udp_tunnel *cmd =
4421                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4422         enum i40e_status_code status;
4423
4424         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4425
4426         cmd->index = index;
4427
4428         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4429
4430         return status;
4431 }
4432
4433 /**
4434  * i40e_aq_get_switch_resource_alloc (0x0204)
4435  * @hw: pointer to the hw struct
4436  * @num_entries: pointer to u8 to store the number of resource entries returned
4437  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
4438  *        to store the resource information for all resource types.  Each
4439  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
4440  * @count: size, in bytes, of the buffer provided
4441  * @cmd_details: pointer to command details structure or NULL
4442  *
4443  * Query the resources allocated to a function.
4444  **/
4445 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4446                         u8 *num_entries,
4447                         struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4448                         u16 count,
4449                         struct i40e_asq_cmd_details *cmd_details)
4450 {
4451         struct i40e_aq_desc desc;
4452         struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4453                 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4454         enum i40e_status_code status;
4455         u16 length = count * sizeof(*buf);
4456
4457         i40e_fill_default_direct_cmd_desc(&desc,
4458                                         i40e_aqc_opc_get_switch_resource_alloc);
4459
4460         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4461         if (length > I40E_AQ_LARGE_BUF)
4462                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4463
4464         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4465
4466         if (!status && num_entries)
4467                 *num_entries = cmd_resp->num_entries;
4468
4469         return status;
4470 }
4471
4472 /**
4473  * i40e_aq_delete_element - Delete switch element
4474  * @hw: pointer to the hw struct
4475  * @seid: the SEID to delete from the switch
4476  * @cmd_details: pointer to command details structure or NULL
4477  *
4478  * This deletes a switch element from the switch.
4479  **/
4480 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4481                                 struct i40e_asq_cmd_details *cmd_details)
4482 {
4483         struct i40e_aq_desc desc;
4484         struct i40e_aqc_switch_seid *cmd =
4485                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4486         enum i40e_status_code status;
4487
4488         if (seid == 0)
4489                 return I40E_ERR_PARAM;
4490
4491         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4492
4493         cmd->seid = CPU_TO_LE16(seid);
4494
4495         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4496
4497         return status;
4498 }
4499
4500 /**
4501  * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4502  * @hw: pointer to the hw struct
4503  * @flags: component flags
4504  * @mac_seid: uplink seid (MAC SEID)
4505  * @vsi_seid: connected vsi seid
4506  * @ret_seid: seid of create pv component
4507  *
4508  * This instantiates an i40e port virtualizer with specified flags.
4509  * Depending on specified flags the port virtualizer can act as a
4510  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4511  */
4512 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4513                                        u16 mac_seid, u16 vsi_seid,
4514                                        u16 *ret_seid)
4515 {
4516         struct i40e_aq_desc desc;
4517         struct i40e_aqc_add_update_pv *cmd =
4518                 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4519         struct i40e_aqc_add_update_pv_completion *resp =
4520                 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4521         enum i40e_status_code status;
4522
4523         if (vsi_seid == 0)
4524                 return I40E_ERR_PARAM;
4525
4526         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4527         cmd->command_flags = CPU_TO_LE16(flags);
4528         cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4529         cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4530
4531         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4532         if (!status && ret_seid)
4533                 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4534
4535         return status;
4536 }
4537
4538 /**
4539  * i40e_aq_add_tag - Add an S/E-tag
4540  * @hw: pointer to the hw struct
4541  * @direct_to_queue: should s-tag direct flow to a specific queue
4542  * @vsi_seid: VSI SEID to use this tag
4543  * @tag: value of the tag
4544  * @queue_num: queue number, only valid is direct_to_queue is true
4545  * @tags_used: return value, number of tags in use by this PF
4546  * @tags_free: return value, number of unallocated tags
4547  * @cmd_details: pointer to command details structure or NULL
4548  *
4549  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4550  * the number of tags allocated by the PF, and the number of unallocated
4551  * tags available.
4552  **/
4553 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4554                                 u16 vsi_seid, u16 tag, u16 queue_num,
4555                                 u16 *tags_used, u16 *tags_free,
4556                                 struct i40e_asq_cmd_details *cmd_details)
4557 {
4558         struct i40e_aq_desc desc;
4559         struct i40e_aqc_add_tag *cmd =
4560                 (struct i40e_aqc_add_tag *)&desc.params.raw;
4561         struct i40e_aqc_add_remove_tag_completion *resp =
4562                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4563         enum i40e_status_code status;
4564
4565         if (vsi_seid == 0)
4566                 return I40E_ERR_PARAM;
4567
4568         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4569
4570         cmd->seid = CPU_TO_LE16(vsi_seid);
4571         cmd->tag = CPU_TO_LE16(tag);
4572         if (direct_to_queue) {
4573                 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4574                 cmd->queue_number = CPU_TO_LE16(queue_num);
4575         }
4576
4577         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4578
4579         if (!status) {
4580                 if (tags_used != NULL)
4581                         *tags_used = LE16_TO_CPU(resp->tags_used);
4582                 if (tags_free != NULL)
4583                         *tags_free = LE16_TO_CPU(resp->tags_free);
4584         }
4585
4586         return status;
4587 }
4588
4589 /**
4590  * i40e_aq_remove_tag - Remove an S- or E-tag
4591  * @hw: pointer to the hw struct
4592  * @vsi_seid: VSI SEID this tag is associated with
4593  * @tag: value of the S-tag to delete
4594  * @tags_used: return value, number of tags in use by this PF
4595  * @tags_free: return value, number of unallocated tags
4596  * @cmd_details: pointer to command details structure or NULL
4597  *
4598  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4599  * the number of tags allocated by the PF, and the number of unallocated
4600  * tags available.
4601  **/
4602 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4603                                 u16 tag, u16 *tags_used, u16 *tags_free,
4604                                 struct i40e_asq_cmd_details *cmd_details)
4605 {
4606         struct i40e_aq_desc desc;
4607         struct i40e_aqc_remove_tag *cmd =
4608                 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4609         struct i40e_aqc_add_remove_tag_completion *resp =
4610                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4611         enum i40e_status_code status;
4612
4613         if (vsi_seid == 0)
4614                 return I40E_ERR_PARAM;
4615
4616         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4617
4618         cmd->seid = CPU_TO_LE16(vsi_seid);
4619         cmd->tag = CPU_TO_LE16(tag);
4620
4621         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4622
4623         if (!status) {
4624                 if (tags_used != NULL)
4625                         *tags_used = LE16_TO_CPU(resp->tags_used);
4626                 if (tags_free != NULL)
4627                         *tags_free = LE16_TO_CPU(resp->tags_free);
4628         }
4629
4630         return status;
4631 }
4632
4633 /**
4634  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4635  * @hw: pointer to the hw struct
4636  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4637  * @etag: value of E-tag to add
4638  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4639  * @buf: address of indirect buffer
4640  * @tags_used: return value, number of E-tags in use by this port
4641  * @tags_free: return value, number of unallocated M-tags
4642  * @cmd_details: pointer to command details structure or NULL
4643  *
4644  * This associates a multicast E-tag to a port virtualizer.  It will return
4645  * the number of tags allocated by the PF, and the number of unallocated
4646  * tags available.
4647  *
4648  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4649  * num_tags_in_buf long.
4650  **/
4651 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4652                                 u16 etag, u8 num_tags_in_buf, void *buf,
4653                                 u16 *tags_used, u16 *tags_free,
4654                                 struct i40e_asq_cmd_details *cmd_details)
4655 {
4656         struct i40e_aq_desc desc;
4657         struct i40e_aqc_add_remove_mcast_etag *cmd =
4658                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4659         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4660            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4661         enum i40e_status_code status;
4662         u16 length = sizeof(u16) * num_tags_in_buf;
4663
4664         if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4665                 return I40E_ERR_PARAM;
4666
4667         i40e_fill_default_direct_cmd_desc(&desc,
4668                                           i40e_aqc_opc_add_multicast_etag);
4669
4670         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4671         cmd->etag = CPU_TO_LE16(etag);
4672         cmd->num_unicast_etags = num_tags_in_buf;
4673
4674         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4675         if (length > I40E_AQ_LARGE_BUF)
4676                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4677
4678         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4679
4680         if (!status) {
4681                 if (tags_used != NULL)
4682                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4683                 if (tags_free != NULL)
4684                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4685         }
4686
4687         return status;
4688 }
4689
4690 /**
4691  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4692  * @hw: pointer to the hw struct
4693  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4694  * @etag: value of the E-tag to remove
4695  * @tags_used: return value, number of tags in use by this port
4696  * @tags_free: return value, number of unallocated tags
4697  * @cmd_details: pointer to command details structure or NULL
4698  *
4699  * This deletes an E-tag from the port virtualizer.  It will return
4700  * the number of tags allocated by the port, and the number of unallocated
4701  * tags available.
4702  **/
4703 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4704                                 u16 etag, u16 *tags_used, u16 *tags_free,
4705                                 struct i40e_asq_cmd_details *cmd_details)
4706 {
4707         struct i40e_aq_desc desc;
4708         struct i40e_aqc_add_remove_mcast_etag *cmd =
4709                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4710         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4711            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4712         enum i40e_status_code status;
4713
4714
4715         if (pv_seid == 0)
4716                 return I40E_ERR_PARAM;
4717
4718         i40e_fill_default_direct_cmd_desc(&desc,
4719                                           i40e_aqc_opc_remove_multicast_etag);
4720
4721         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4722         cmd->etag = CPU_TO_LE16(etag);
4723
4724         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4725
4726         if (!status) {
4727                 if (tags_used != NULL)
4728                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4729                 if (tags_free != NULL)
4730                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4731         }
4732
4733         return status;
4734 }
4735
4736 /**
4737  * i40e_aq_update_tag - Update an S/E-tag
4738  * @hw: pointer to the hw struct
4739  * @vsi_seid: VSI SEID using this S-tag
4740  * @old_tag: old tag value
4741  * @new_tag: new tag value
4742  * @tags_used: return value, number of tags in use by this PF
4743  * @tags_free: return value, number of unallocated tags
4744  * @cmd_details: pointer to command details structure or NULL
4745  *
4746  * This updates the value of the tag currently attached to this VSI
4747  * in the switch complex.  It will return the number of tags allocated
4748  * by the PF, and the number of unallocated tags available.
4749  **/
4750 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4751                                 u16 old_tag, u16 new_tag, u16 *tags_used,
4752                                 u16 *tags_free,
4753                                 struct i40e_asq_cmd_details *cmd_details)
4754 {
4755         struct i40e_aq_desc desc;
4756         struct i40e_aqc_update_tag *cmd =
4757                 (struct i40e_aqc_update_tag *)&desc.params.raw;
4758         struct i40e_aqc_update_tag_completion *resp =
4759                 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4760         enum i40e_status_code status;
4761
4762         if (vsi_seid == 0)
4763                 return I40E_ERR_PARAM;
4764
4765         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4766
4767         cmd->seid = CPU_TO_LE16(vsi_seid);
4768         cmd->old_tag = CPU_TO_LE16(old_tag);
4769         cmd->new_tag = CPU_TO_LE16(new_tag);
4770
4771         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4772
4773         if (!status) {
4774                 if (tags_used != NULL)
4775                         *tags_used = LE16_TO_CPU(resp->tags_used);
4776                 if (tags_free != NULL)
4777                         *tags_free = LE16_TO_CPU(resp->tags_free);
4778         }
4779
4780         return status;
4781 }
4782
4783 /**
4784  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4785  * @hw: pointer to the hw struct
4786  * @tcmap: TC map for request/release any ignore PFC condition
4787  * @request: request or release ignore PFC condition
4788  * @tcmap_ret: return TCs for which PFC is currently ignored
4789  * @cmd_details: pointer to command details structure or NULL
4790  *
4791  * This sends out request/release to ignore PFC condition for a TC.
4792  * It will return the TCs for which PFC is currently ignored.
4793  **/
4794 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4795                                 bool request, u8 *tcmap_ret,
4796                                 struct i40e_asq_cmd_details *cmd_details)
4797 {
4798         struct i40e_aq_desc desc;
4799         struct i40e_aqc_pfc_ignore *cmd_resp =
4800                 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4801         enum i40e_status_code status;
4802
4803         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4804
4805         if (request)
4806                 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4807
4808         cmd_resp->tc_bitmap = tcmap;
4809
4810         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4811
4812         if (!status) {
4813                 if (tcmap_ret != NULL)
4814                         *tcmap_ret = cmd_resp->tc_bitmap;
4815         }
4816
4817         return status;
4818 }
4819
4820 /**
4821  * i40e_aq_dcb_updated - DCB Updated Command
4822  * @hw: pointer to the hw struct
4823  * @cmd_details: pointer to command details structure or NULL
4824  *
4825  * When LLDP is handled in PF this command is used by the PF
4826  * to notify EMP that a DCB setting is modified.
4827  * When LLDP is handled in EMP this command is used by the PF
4828  * to notify EMP whenever one of the following parameters get
4829  * modified:
4830  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4831  *   - PCIRTT in PRTDCB_GENC.PCIRTT
4832  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4833  * EMP will return when the shared RPB settings have been
4834  * recomputed and modified. The retval field in the descriptor
4835  * will be set to 0 when RPB is modified.
4836  **/
4837 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4838                                 struct i40e_asq_cmd_details *cmd_details)
4839 {
4840         struct i40e_aq_desc desc;
4841         enum i40e_status_code status;
4842
4843         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4844
4845         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4846
4847         return status;
4848 }
4849
4850 /**
4851  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4852  * @hw: pointer to the hw struct
4853  * @seid: defines the SEID of the switch for which the stats are requested
4854  * @vlan_id: the VLAN ID for which the statistics are requested
4855  * @stat_index: index of the statistics counters block assigned to this VLAN
4856  * @cmd_details: pointer to command details structure or NULL
4857  *
4858  * XL710 supports 128 smonVlanStats counters.This command is used to
4859  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4860  * switch.
4861  **/
4862 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4863                                 u16 vlan_id, u16 *stat_index,
4864                                 struct i40e_asq_cmd_details *cmd_details)
4865 {
4866         struct i40e_aq_desc desc;
4867         struct i40e_aqc_add_remove_statistics *cmd_resp =
4868                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4869         enum i40e_status_code status;
4870
4871         if ((seid == 0) || (stat_index == NULL))
4872                 return I40E_ERR_PARAM;
4873
4874         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4875
4876         cmd_resp->seid = CPU_TO_LE16(seid);
4877         cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4878
4879         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4880
4881         if (!status && stat_index)
4882                 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4883
4884         return status;
4885 }
4886
4887 /**
4888  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4889  * @hw: pointer to the hw struct
4890  * @seid: defines the SEID of the switch for which the stats are requested
4891  * @vlan_id: the VLAN ID for which the statistics are requested
4892  * @stat_index: index of the statistics counters block assigned to this VLAN
4893  * @cmd_details: pointer to command details structure or NULL
4894  *
4895  * XL710 supports 128 smonVlanStats counters.This command is used to
4896  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4897  * switch.
4898  **/
4899 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4900                                 u16 vlan_id, u16 stat_index,
4901                                 struct i40e_asq_cmd_details *cmd_details)
4902 {
4903         struct i40e_aq_desc desc;
4904         struct i40e_aqc_add_remove_statistics *cmd =
4905                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4906         enum i40e_status_code status;
4907
4908         if (seid == 0)
4909                 return I40E_ERR_PARAM;
4910
4911         i40e_fill_default_direct_cmd_desc(&desc,
4912                                           i40e_aqc_opc_remove_statistics);
4913
4914         cmd->seid = CPU_TO_LE16(seid);
4915         cmd->vlan  = CPU_TO_LE16(vlan_id);
4916         cmd->stat_index = CPU_TO_LE16(stat_index);
4917
4918         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4919
4920         return status;
4921 }
4922
4923 /**
4924  * i40e_aq_set_port_parameters - set physical port parameters.
4925  * @hw: pointer to the hw struct
4926  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4927  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4928  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4929  * @double_vlan: if set double VLAN is enabled
4930  * @cmd_details: pointer to command details structure or NULL
4931  **/
4932 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4933                                 u16 bad_frame_vsi, bool save_bad_pac,
4934                                 bool pad_short_pac, bool double_vlan,
4935                                 struct i40e_asq_cmd_details *cmd_details)
4936 {
4937         struct i40e_aqc_set_port_parameters *cmd;
4938         enum i40e_status_code status;
4939         struct i40e_aq_desc desc;
4940         u16 command_flags = 0;
4941
4942         cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4943
4944         i40e_fill_default_direct_cmd_desc(&desc,
4945                                           i40e_aqc_opc_set_port_parameters);
4946
4947         cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4948         if (save_bad_pac)
4949                 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4950         if (pad_short_pac)
4951                 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4952         if (double_vlan)
4953                 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4954         cmd->command_flags = CPU_TO_LE16(command_flags);
4955
4956         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4957
4958         return status;
4959 }
4960
4961 /**
4962  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
4963  * @hw: pointer to the hw struct
4964  * @seid: seid for the physical port/switching component/vsi
4965  * @buff: Indirect buffer to hold data parameters and response
4966  * @buff_size: Indirect buffer size
4967  * @opcode: Tx scheduler AQ command opcode
4968  * @cmd_details: pointer to command details structure or NULL
4969  *
4970  * Generic command handler for Tx scheduler AQ commands
4971  **/
4972 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
4973                                 void *buff, u16 buff_size,
4974                                  enum i40e_admin_queue_opc opcode,
4975                                 struct i40e_asq_cmd_details *cmd_details)
4976 {
4977         struct i40e_aq_desc desc;
4978         struct i40e_aqc_tx_sched_ind *cmd =
4979                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4980         enum i40e_status_code status;
4981         bool cmd_param_flag = false;
4982
4983         switch (opcode) {
4984         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
4985         case i40e_aqc_opc_configure_vsi_tc_bw:
4986         case i40e_aqc_opc_enable_switching_comp_ets:
4987         case i40e_aqc_opc_modify_switching_comp_ets:
4988         case i40e_aqc_opc_disable_switching_comp_ets:
4989         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
4990         case i40e_aqc_opc_configure_switching_comp_bw_config:
4991                 cmd_param_flag = true;
4992                 break;
4993         case i40e_aqc_opc_query_vsi_bw_config:
4994         case i40e_aqc_opc_query_vsi_ets_sla_config:
4995         case i40e_aqc_opc_query_switching_comp_ets_config:
4996         case i40e_aqc_opc_query_port_ets_config:
4997         case i40e_aqc_opc_query_switching_comp_bw_config:
4998                 cmd_param_flag = false;
4999                 break;
5000         default:
5001                 return I40E_ERR_PARAM;
5002         }
5003
5004         i40e_fill_default_direct_cmd_desc(&desc, opcode);
5005
5006         /* Indirect command */
5007         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5008         if (cmd_param_flag)
5009                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5010         if (buff_size > I40E_AQ_LARGE_BUF)
5011                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5012
5013         desc.datalen = CPU_TO_LE16(buff_size);
5014
5015         cmd->vsi_seid = CPU_TO_LE16(seid);
5016
5017         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5018
5019         return status;
5020 }
5021
5022 /**
5023  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5024  * @hw: pointer to the hw struct
5025  * @seid: VSI seid
5026  * @credit: BW limit credits (0 = disabled)
5027  * @max_credit: Max BW limit credits
5028  * @cmd_details: pointer to command details structure or NULL
5029  **/
5030 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5031                                 u16 seid, u16 credit, u8 max_credit,
5032                                 struct i40e_asq_cmd_details *cmd_details)
5033 {
5034         struct i40e_aq_desc desc;
5035         struct i40e_aqc_configure_vsi_bw_limit *cmd =
5036                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5037         enum i40e_status_code status;
5038
5039         i40e_fill_default_direct_cmd_desc(&desc,
5040                                           i40e_aqc_opc_configure_vsi_bw_limit);
5041
5042         cmd->vsi_seid = CPU_TO_LE16(seid);
5043         cmd->credit = CPU_TO_LE16(credit);
5044         cmd->max_credit = max_credit;
5045
5046         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5047
5048         return status;
5049 }
5050
5051 /**
5052  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5053  * @hw: pointer to the hw struct
5054  * @seid: switching component seid
5055  * @credit: BW limit credits (0 = disabled)
5056  * @max_bw: Max BW limit credits
5057  * @cmd_details: pointer to command details structure or NULL
5058  **/
5059 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5060                                 u16 seid, u16 credit, u8 max_bw,
5061                                 struct i40e_asq_cmd_details *cmd_details)
5062 {
5063         struct i40e_aq_desc desc;
5064         struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5065           (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5066         enum i40e_status_code status;
5067
5068         i40e_fill_default_direct_cmd_desc(&desc,
5069                                 i40e_aqc_opc_configure_switching_comp_bw_limit);
5070
5071         cmd->seid = CPU_TO_LE16(seid);
5072         cmd->credit = CPU_TO_LE16(credit);
5073         cmd->max_bw = max_bw;
5074
5075         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5076
5077         return status;
5078 }
5079
5080 /**
5081  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5082  * @hw: pointer to the hw struct
5083  * @seid: VSI seid
5084  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5085  * @cmd_details: pointer to command details structure or NULL
5086  **/
5087 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5088                         u16 seid,
5089                         struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5090                         struct i40e_asq_cmd_details *cmd_details)
5091 {
5092         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5093                                     i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5094                                     cmd_details);
5095 }
5096
5097 /**
5098  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5099  * @hw: pointer to the hw struct
5100  * @seid: VSI seid
5101  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5102  * @cmd_details: pointer to command details structure or NULL
5103  **/
5104 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5105                         u16 seid,
5106                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5107                         struct i40e_asq_cmd_details *cmd_details)
5108 {
5109         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5110                                     i40e_aqc_opc_configure_vsi_tc_bw,
5111                                     cmd_details);
5112 }
5113
5114 /**
5115  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5116  * @hw: pointer to the hw struct
5117  * @seid: seid of the switching component connected to Physical Port
5118  * @ets_data: Buffer holding ETS parameters
5119  * @cmd_details: pointer to command details structure or NULL
5120  **/
5121 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5122                 u16 seid,
5123                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5124                 enum i40e_admin_queue_opc opcode,
5125                 struct i40e_asq_cmd_details *cmd_details)
5126 {
5127         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5128                                     sizeof(*ets_data), opcode, cmd_details);
5129 }
5130
5131 /**
5132  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5133  * @hw: pointer to the hw struct
5134  * @seid: seid of the switching component
5135  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5136  * @cmd_details: pointer to command details structure or NULL
5137  **/
5138 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5139         u16 seid,
5140         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5141         struct i40e_asq_cmd_details *cmd_details)
5142 {
5143         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5144                             i40e_aqc_opc_configure_switching_comp_bw_config,
5145                             cmd_details);
5146 }
5147
5148 /**
5149  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5150  * @hw: pointer to the hw struct
5151  * @seid: seid of the switching component
5152  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5153  * @cmd_details: pointer to command details structure or NULL
5154  **/
5155 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5156         struct i40e_hw *hw, u16 seid,
5157         struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5158         struct i40e_asq_cmd_details *cmd_details)
5159 {
5160         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5161                             i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5162                             cmd_details);
5163 }
5164
5165 /**
5166  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5167  * @hw: pointer to the hw struct
5168  * @seid: seid of the VSI
5169  * @bw_data: Buffer to hold VSI BW configuration
5170  * @cmd_details: pointer to command details structure or NULL
5171  **/
5172 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5173                         u16 seid,
5174                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5175                         struct i40e_asq_cmd_details *cmd_details)
5176 {
5177         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5178                                     i40e_aqc_opc_query_vsi_bw_config,
5179                                     cmd_details);
5180 }
5181
5182 /**
5183  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5184  * @hw: pointer to the hw struct
5185  * @seid: seid of the VSI
5186  * @bw_data: Buffer to hold VSI BW configuration per TC
5187  * @cmd_details: pointer to command details structure or NULL
5188  **/
5189 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5190                         u16 seid,
5191                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5192                         struct i40e_asq_cmd_details *cmd_details)
5193 {
5194         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5195                                     i40e_aqc_opc_query_vsi_ets_sla_config,
5196                                     cmd_details);
5197 }
5198
5199 /**
5200  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5201  * @hw: pointer to the hw struct
5202  * @seid: seid of the switching component
5203  * @bw_data: Buffer to hold switching component's per TC BW config
5204  * @cmd_details: pointer to command details structure or NULL
5205  **/
5206 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5207                 u16 seid,
5208                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5209                 struct i40e_asq_cmd_details *cmd_details)
5210 {
5211         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5212                                    i40e_aqc_opc_query_switching_comp_ets_config,
5213                                    cmd_details);
5214 }
5215
5216 /**
5217  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5218  * @hw: pointer to the hw struct
5219  * @seid: seid of the VSI or switching component connected to Physical Port
5220  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5221  * @cmd_details: pointer to command details structure or NULL
5222  **/
5223 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5224                         u16 seid,
5225                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
5226                         struct i40e_asq_cmd_details *cmd_details)
5227 {
5228         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5229                                     i40e_aqc_opc_query_port_ets_config,
5230                                     cmd_details);
5231 }
5232
5233 /**
5234  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5235  * @hw: pointer to the hw struct
5236  * @seid: seid of the switching component
5237  * @bw_data: Buffer to hold switching component's BW configuration
5238  * @cmd_details: pointer to command details structure or NULL
5239  **/
5240 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5241                 u16 seid,
5242                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5243                 struct i40e_asq_cmd_details *cmd_details)
5244 {
5245         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5246                                     i40e_aqc_opc_query_switching_comp_bw_config,
5247                                     cmd_details);
5248 }
5249
5250 /**
5251  * i40e_validate_filter_settings
5252  * @hw: pointer to the hardware structure
5253  * @settings: Filter control settings
5254  *
5255  * Check and validate the filter control settings passed.
5256  * The function checks for the valid filter/context sizes being
5257  * passed for FCoE and PE.
5258  *
5259  * Returns I40E_SUCCESS if the values passed are valid and within
5260  * range else returns an error.
5261  **/
5262 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5263                                 struct i40e_filter_control_settings *settings)
5264 {
5265         u32 fcoe_cntx_size, fcoe_filt_size;
5266         u32 pe_cntx_size, pe_filt_size;
5267         u32 fcoe_fmax;
5268
5269         u32 val;
5270
5271         /* Validate FCoE settings passed */
5272         switch (settings->fcoe_filt_num) {
5273         case I40E_HASH_FILTER_SIZE_1K:
5274         case I40E_HASH_FILTER_SIZE_2K:
5275         case I40E_HASH_FILTER_SIZE_4K:
5276         case I40E_HASH_FILTER_SIZE_8K:
5277         case I40E_HASH_FILTER_SIZE_16K:
5278         case I40E_HASH_FILTER_SIZE_32K:
5279                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5280                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5281                 break;
5282         default:
5283                 return I40E_ERR_PARAM;
5284         }
5285
5286         switch (settings->fcoe_cntx_num) {
5287         case I40E_DMA_CNTX_SIZE_512:
5288         case I40E_DMA_CNTX_SIZE_1K:
5289         case I40E_DMA_CNTX_SIZE_2K:
5290         case I40E_DMA_CNTX_SIZE_4K:
5291                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5292                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5293                 break;
5294         default:
5295                 return I40E_ERR_PARAM;
5296         }
5297
5298         /* Validate PE settings passed */
5299         switch (settings->pe_filt_num) {
5300         case I40E_HASH_FILTER_SIZE_1K:
5301         case I40E_HASH_FILTER_SIZE_2K:
5302         case I40E_HASH_FILTER_SIZE_4K:
5303         case I40E_HASH_FILTER_SIZE_8K:
5304         case I40E_HASH_FILTER_SIZE_16K:
5305         case I40E_HASH_FILTER_SIZE_32K:
5306         case I40E_HASH_FILTER_SIZE_64K:
5307         case I40E_HASH_FILTER_SIZE_128K:
5308         case I40E_HASH_FILTER_SIZE_256K:
5309         case I40E_HASH_FILTER_SIZE_512K:
5310         case I40E_HASH_FILTER_SIZE_1M:
5311                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5312                 pe_filt_size <<= (u32)settings->pe_filt_num;
5313                 break;
5314         default:
5315                 return I40E_ERR_PARAM;
5316         }
5317
5318         switch (settings->pe_cntx_num) {
5319         case I40E_DMA_CNTX_SIZE_512:
5320         case I40E_DMA_CNTX_SIZE_1K:
5321         case I40E_DMA_CNTX_SIZE_2K:
5322         case I40E_DMA_CNTX_SIZE_4K:
5323         case I40E_DMA_CNTX_SIZE_8K:
5324         case I40E_DMA_CNTX_SIZE_16K:
5325         case I40E_DMA_CNTX_SIZE_32K:
5326         case I40E_DMA_CNTX_SIZE_64K:
5327         case I40E_DMA_CNTX_SIZE_128K:
5328         case I40E_DMA_CNTX_SIZE_256K:
5329                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5330                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5331                 break;
5332         default:
5333                 return I40E_ERR_PARAM;
5334         }
5335
5336         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5337         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5338         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5339                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5340         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
5341                 return I40E_ERR_INVALID_SIZE;
5342
5343         return I40E_SUCCESS;
5344 }
5345
5346 /**
5347  * i40e_set_filter_control
5348  * @hw: pointer to the hardware structure
5349  * @settings: Filter control settings
5350  *
5351  * Set the Queue Filters for PE/FCoE and enable filters required
5352  * for a single PF. It is expected that these settings are programmed
5353  * at the driver initialization time.
5354  **/
5355 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5356                                 struct i40e_filter_control_settings *settings)
5357 {
5358         enum i40e_status_code ret = I40E_SUCCESS;
5359         u32 hash_lut_size = 0;
5360         u32 val;
5361
5362         if (!settings)
5363                 return I40E_ERR_PARAM;
5364
5365         /* Validate the input settings */
5366         ret = i40e_validate_filter_settings(hw, settings);
5367         if (ret)
5368                 return ret;
5369
5370         /* Read the PF Queue Filter control register */
5371         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5372
5373         /* Program required PE hash buckets for the PF */
5374         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5375         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5376                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5377         /* Program required PE contexts for the PF */
5378         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5379         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5380                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5381
5382         /* Program required FCoE hash buckets for the PF */
5383         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5384         val |= ((u32)settings->fcoe_filt_num <<
5385                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5386                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5387         /* Program required FCoE DDP contexts for the PF */
5388         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5389         val |= ((u32)settings->fcoe_cntx_num <<
5390                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5391                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5392
5393         /* Program Hash LUT size for the PF */
5394         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5395         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5396                 hash_lut_size = 1;
5397         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5398                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5399
5400         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5401         if (settings->enable_fdir)
5402                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5403         if (settings->enable_ethtype)
5404                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5405         if (settings->enable_macvlan)
5406                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5407
5408         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5409
5410         return I40E_SUCCESS;
5411 }
5412
5413 /**
5414  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5415  * @hw: pointer to the hw struct
5416  * @mac_addr: MAC address to use in the filter
5417  * @ethtype: Ethertype to use in the filter
5418  * @flags: Flags that needs to be applied to the filter
5419  * @vsi_seid: seid of the control VSI
5420  * @queue: VSI queue number to send the packet to
5421  * @is_add: Add control packet filter if True else remove
5422  * @stats: Structure to hold information on control filter counts
5423  * @cmd_details: pointer to command details structure or NULL
5424  *
5425  * This command will Add or Remove control packet filter for a control VSI.
5426  * In return it will update the total number of perfect filter count in
5427  * the stats member.
5428  **/
5429 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5430                                 u8 *mac_addr, u16 ethtype, u16 flags,
5431                                 u16 vsi_seid, u16 queue, bool is_add,
5432                                 struct i40e_control_filter_stats *stats,
5433                                 struct i40e_asq_cmd_details *cmd_details)
5434 {
5435         struct i40e_aq_desc desc;
5436         struct i40e_aqc_add_remove_control_packet_filter *cmd =
5437                 (struct i40e_aqc_add_remove_control_packet_filter *)
5438                 &desc.params.raw;
5439         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5440                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5441                 &desc.params.raw;
5442         enum i40e_status_code status;
5443
5444         if (vsi_seid == 0)
5445                 return I40E_ERR_PARAM;
5446
5447         if (is_add) {
5448                 i40e_fill_default_direct_cmd_desc(&desc,
5449                                 i40e_aqc_opc_add_control_packet_filter);
5450                 cmd->queue = CPU_TO_LE16(queue);
5451         } else {
5452                 i40e_fill_default_direct_cmd_desc(&desc,
5453                                 i40e_aqc_opc_remove_control_packet_filter);
5454         }
5455
5456         if (mac_addr)
5457                 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
5458                             I40E_NONDMA_TO_NONDMA);
5459
5460         cmd->etype = CPU_TO_LE16(ethtype);
5461         cmd->flags = CPU_TO_LE16(flags);
5462         cmd->seid = CPU_TO_LE16(vsi_seid);
5463
5464         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5465
5466         if (!status && stats) {
5467                 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5468                 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5469                 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5470                 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5471         }
5472
5473         return status;
5474 }
5475
5476 /**
5477  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5478  * @hw: pointer to the hw struct
5479  * @seid: VSI seid to add ethertype filter from
5480  **/
5481 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5482 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5483                                                     u16 seid)
5484 {
5485         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5486                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5487                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5488         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5489         enum i40e_status_code status;
5490
5491         status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5492                                                        seid, 0, true, NULL,
5493                                                        NULL);
5494         if (status)
5495                 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5496 }
5497
5498 /**
5499  * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5500  * @filters: list of cloud filters
5501  * @filter_count: length of list
5502  *
5503  * There's an issue in the device where the Geneve VNI layout needs
5504  * to be shifted 1 byte over from the VxLAN VNI
5505  **/
5506 STATIC void i40e_fix_up_geneve_vni(
5507         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5508         u8 filter_count)
5509 {
5510         struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters;
5511         int i;
5512
5513         for (i = 0; i < filter_count; i++) {
5514                 u16 tnl_type;
5515                 u32 ti;
5516
5517                 tnl_type = (LE16_TO_CPU(f[i].flags) &
5518                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5519                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5520                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5521                         ti = LE32_TO_CPU(f[i].tenant_id);
5522                         f[i].tenant_id = CPU_TO_LE32(ti << 8);
5523                 }
5524         }
5525 }
5526
5527 /**
5528  * i40e_aq_add_cloud_filters
5529  * @hw: pointer to the hardware structure
5530  * @seid: VSI seid to add cloud filters from
5531  * @filters: Buffer which contains the filters to be added
5532  * @filter_count: number of filters contained in the buffer
5533  *
5534  * Set the cloud filters for a given VSI.  The contents of the
5535  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5536  * in by the caller of the function.
5537  *
5538  **/
5539 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5540         u16 seid,
5541         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5542         u8 filter_count)
5543 {
5544         struct i40e_aq_desc desc;
5545         struct i40e_aqc_add_remove_cloud_filters *cmd =
5546         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5547         enum i40e_status_code status;
5548         u16 buff_len;
5549
5550         i40e_fill_default_direct_cmd_desc(&desc,
5551                                           i40e_aqc_opc_add_cloud_filters);
5552
5553         buff_len = filter_count * sizeof(*filters);
5554         desc.datalen = CPU_TO_LE16(buff_len);
5555         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5556         cmd->num_filters = filter_count;
5557         cmd->seid = CPU_TO_LE16(seid);
5558
5559         i40e_fix_up_geneve_vni(filters, filter_count);
5560
5561         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5562
5563         return status;
5564 }
5565
5566 /**
5567  * i40e_aq_remove_cloud_filters
5568  * @hw: pointer to the hardware structure
5569  * @seid: VSI seid to remove cloud filters from
5570  * @filters: Buffer which contains the filters to be removed
5571  * @filter_count: number of filters contained in the buffer
5572  *
5573  * Remove the cloud filters for a given VSI.  The contents of the
5574  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5575  * in by the caller of the function.
5576  *
5577  **/
5578 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5579                 u16 seid,
5580                 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5581                 u8 filter_count)
5582 {
5583         struct i40e_aq_desc desc;
5584         struct i40e_aqc_add_remove_cloud_filters *cmd =
5585         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5586         enum i40e_status_code status;
5587         u16 buff_len;
5588
5589         i40e_fill_default_direct_cmd_desc(&desc,
5590                                           i40e_aqc_opc_remove_cloud_filters);
5591
5592         buff_len = filter_count * sizeof(*filters);
5593         desc.datalen = CPU_TO_LE16(buff_len);
5594         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5595         cmd->num_filters = filter_count;
5596         cmd->seid = CPU_TO_LE16(seid);
5597
5598         i40e_fix_up_geneve_vni(filters, filter_count);
5599
5600         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5601
5602         return status;
5603 }
5604
5605 /**
5606  * i40e_aq_alternate_write
5607  * @hw: pointer to the hardware structure
5608  * @reg_addr0: address of first dword to be read
5609  * @reg_val0: value to be written under 'reg_addr0'
5610  * @reg_addr1: address of second dword to be read
5611  * @reg_val1: value to be written under 'reg_addr1'
5612  *
5613  * Write one or two dwords to alternate structure. Fields are indicated
5614  * by 'reg_addr0' and 'reg_addr1' register numbers.
5615  *
5616  **/
5617 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5618                                 u32 reg_addr0, u32 reg_val0,
5619                                 u32 reg_addr1, u32 reg_val1)
5620 {
5621         struct i40e_aq_desc desc;
5622         struct i40e_aqc_alternate_write *cmd_resp =
5623                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5624         enum i40e_status_code status;
5625
5626         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5627         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5628         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5629         cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5630         cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5631
5632         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5633
5634         return status;
5635 }
5636
5637 /**
5638  * i40e_aq_alternate_write_indirect
5639  * @hw: pointer to the hardware structure
5640  * @addr: address of a first register to be modified
5641  * @dw_count: number of alternate structure fields to write
5642  * @buffer: pointer to the command buffer
5643  *
5644  * Write 'dw_count' dwords from 'buffer' to alternate structure
5645  * starting at 'addr'.
5646  *
5647  **/
5648 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5649                                 u32 addr, u32 dw_count, void *buffer)
5650 {
5651         struct i40e_aq_desc desc;
5652         struct i40e_aqc_alternate_ind_write *cmd_resp =
5653                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5654         enum i40e_status_code status;
5655
5656         if (buffer == NULL)
5657                 return I40E_ERR_PARAM;
5658
5659         /* Indirect command */
5660         i40e_fill_default_direct_cmd_desc(&desc,
5661                                          i40e_aqc_opc_alternate_write_indirect);
5662
5663         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5664         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5665         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5666                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5667
5668         cmd_resp->address = CPU_TO_LE32(addr);
5669         cmd_resp->length = CPU_TO_LE32(dw_count);
5670
5671         status = i40e_asq_send_command(hw, &desc, buffer,
5672                                        I40E_LO_DWORD(4*dw_count), NULL);
5673
5674         return status;
5675 }
5676
5677 /**
5678  * i40e_aq_alternate_read
5679  * @hw: pointer to the hardware structure
5680  * @reg_addr0: address of first dword to be read
5681  * @reg_val0: pointer for data read from 'reg_addr0'
5682  * @reg_addr1: address of second dword to be read
5683  * @reg_val1: pointer for data read from 'reg_addr1'
5684  *
5685  * Read one or two dwords from alternate structure. Fields are indicated
5686  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5687  * is not passed then only register at 'reg_addr0' is read.
5688  *
5689  **/
5690 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5691                                 u32 reg_addr0, u32 *reg_val0,
5692                                 u32 reg_addr1, u32 *reg_val1)
5693 {
5694         struct i40e_aq_desc desc;
5695         struct i40e_aqc_alternate_write *cmd_resp =
5696                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5697         enum i40e_status_code status;
5698
5699         if (reg_val0 == NULL)
5700                 return I40E_ERR_PARAM;
5701
5702         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5703         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5704         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5705
5706         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5707
5708         if (status == I40E_SUCCESS) {
5709                 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5710
5711                 if (reg_val1 != NULL)
5712                         *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5713         }
5714
5715         return status;
5716 }
5717
5718 /**
5719  * i40e_aq_alternate_read_indirect
5720  * @hw: pointer to the hardware structure
5721  * @addr: address of the alternate structure field
5722  * @dw_count: number of alternate structure fields to read
5723  * @buffer: pointer to the command buffer
5724  *
5725  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5726  * place them in 'buffer'. The buffer should be allocated by caller.
5727  *
5728  **/
5729 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5730                                 u32 addr, u32 dw_count, void *buffer)
5731 {
5732         struct i40e_aq_desc desc;
5733         struct i40e_aqc_alternate_ind_write *cmd_resp =
5734                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5735         enum i40e_status_code status;
5736
5737         if (buffer == NULL)
5738                 return I40E_ERR_PARAM;
5739
5740         /* Indirect command */
5741         i40e_fill_default_direct_cmd_desc(&desc,
5742                 i40e_aqc_opc_alternate_read_indirect);
5743
5744         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5745         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5746         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5747                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5748
5749         cmd_resp->address = CPU_TO_LE32(addr);
5750         cmd_resp->length = CPU_TO_LE32(dw_count);
5751
5752         status = i40e_asq_send_command(hw, &desc, buffer,
5753                                        I40E_LO_DWORD(4*dw_count), NULL);
5754
5755         return status;
5756 }
5757
5758 /**
5759  *  i40e_aq_alternate_clear
5760  *  @hw: pointer to the HW structure.
5761  *
5762  *  Clear the alternate structures of the port from which the function
5763  *  is called.
5764  *
5765  **/
5766 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5767 {
5768         struct i40e_aq_desc desc;
5769         enum i40e_status_code status;
5770
5771         i40e_fill_default_direct_cmd_desc(&desc,
5772                                           i40e_aqc_opc_alternate_clear_port);
5773
5774         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5775
5776         return status;
5777 }
5778
5779 /**
5780  *  i40e_aq_alternate_write_done
5781  *  @hw: pointer to the HW structure.
5782  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
5783  *  @reset_needed: indicates the SW should trigger GLOBAL reset
5784  *
5785  *  Indicates to the FW that alternate structures have been changed.
5786  *
5787  **/
5788 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
5789                 u8 bios_mode, bool *reset_needed)
5790 {
5791         struct i40e_aq_desc desc;
5792         struct i40e_aqc_alternate_write_done *cmd =
5793                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5794         enum i40e_status_code status;
5795
5796         if (reset_needed == NULL)
5797                 return I40E_ERR_PARAM;
5798
5799         i40e_fill_default_direct_cmd_desc(&desc,
5800                                           i40e_aqc_opc_alternate_write_done);
5801
5802         cmd->cmd_flags = CPU_TO_LE16(bios_mode);
5803
5804         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5805         if (!status && reset_needed)
5806                 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
5807                                  I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
5808
5809         return status;
5810 }
5811
5812 /**
5813  *  i40e_aq_set_oem_mode
5814  *  @hw: pointer to the HW structure.
5815  *  @oem_mode: the OEM mode to be used
5816  *
5817  *  Sets the device to a specific operating mode. Currently the only supported
5818  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
5819  *
5820  **/
5821 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
5822                 u8 oem_mode)
5823 {
5824         struct i40e_aq_desc desc;
5825         struct i40e_aqc_alternate_write_done *cmd =
5826                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5827         enum i40e_status_code status;
5828
5829         i40e_fill_default_direct_cmd_desc(&desc,
5830                                           i40e_aqc_opc_alternate_set_mode);
5831
5832         cmd->cmd_flags = CPU_TO_LE16(oem_mode);
5833
5834         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5835
5836         return status;
5837 }
5838
5839 /**
5840  * i40e_aq_resume_port_tx
5841  * @hw: pointer to the hardware structure
5842  * @cmd_details: pointer to command details structure or NULL
5843  *
5844  * Resume port's Tx traffic
5845  **/
5846 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
5847                                 struct i40e_asq_cmd_details *cmd_details)
5848 {
5849         struct i40e_aq_desc desc;
5850         enum i40e_status_code status;
5851
5852         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
5853
5854         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5855
5856         return status;
5857 }
5858
5859 /**
5860  * i40e_set_pci_config_data - store PCI bus info
5861  * @hw: pointer to hardware structure
5862  * @link_status: the link status word from PCI config space
5863  *
5864  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
5865  **/
5866 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
5867 {
5868         hw->bus.type = i40e_bus_type_pci_express;
5869
5870         switch (link_status & I40E_PCI_LINK_WIDTH) {
5871         case I40E_PCI_LINK_WIDTH_1:
5872                 hw->bus.width = i40e_bus_width_pcie_x1;
5873                 break;
5874         case I40E_PCI_LINK_WIDTH_2:
5875                 hw->bus.width = i40e_bus_width_pcie_x2;
5876                 break;
5877         case I40E_PCI_LINK_WIDTH_4:
5878                 hw->bus.width = i40e_bus_width_pcie_x4;
5879                 break;
5880         case I40E_PCI_LINK_WIDTH_8:
5881                 hw->bus.width = i40e_bus_width_pcie_x8;
5882                 break;
5883         default:
5884                 hw->bus.width = i40e_bus_width_unknown;
5885                 break;
5886         }
5887
5888         switch (link_status & I40E_PCI_LINK_SPEED) {
5889         case I40E_PCI_LINK_SPEED_2500:
5890                 hw->bus.speed = i40e_bus_speed_2500;
5891                 break;
5892         case I40E_PCI_LINK_SPEED_5000:
5893                 hw->bus.speed = i40e_bus_speed_5000;
5894                 break;
5895         case I40E_PCI_LINK_SPEED_8000:
5896                 hw->bus.speed = i40e_bus_speed_8000;
5897                 break;
5898         default:
5899                 hw->bus.speed = i40e_bus_speed_unknown;
5900                 break;
5901         }
5902 }
5903
5904 /**
5905  * i40e_aq_debug_dump
5906  * @hw: pointer to the hardware structure
5907  * @cluster_id: specific cluster to dump
5908  * @table_id: table id within cluster
5909  * @start_index: index of line in the block to read
5910  * @buff_size: dump buffer size
5911  * @buff: dump buffer
5912  * @ret_buff_size: actual buffer size returned
5913  * @ret_next_table: next block to read
5914  * @ret_next_index: next index to read
5915  *
5916  * Dump internal FW/HW data for debug purposes.
5917  *
5918  **/
5919 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
5920                                 u8 table_id, u32 start_index, u16 buff_size,
5921                                 void *buff, u16 *ret_buff_size,
5922                                 u8 *ret_next_table, u32 *ret_next_index,
5923                                 struct i40e_asq_cmd_details *cmd_details)
5924 {
5925         struct i40e_aq_desc desc;
5926         struct i40e_aqc_debug_dump_internals *cmd =
5927                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5928         struct i40e_aqc_debug_dump_internals *resp =
5929                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5930         enum i40e_status_code status;
5931
5932         if (buff_size == 0 || !buff)
5933                 return I40E_ERR_PARAM;
5934
5935         i40e_fill_default_direct_cmd_desc(&desc,
5936                                           i40e_aqc_opc_debug_dump_internals);
5937         /* Indirect Command */
5938         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5939         if (buff_size > I40E_AQ_LARGE_BUF)
5940                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5941
5942         cmd->cluster_id = cluster_id;
5943         cmd->table_id = table_id;
5944         cmd->idx = CPU_TO_LE32(start_index);
5945
5946         desc.datalen = CPU_TO_LE16(buff_size);
5947
5948         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5949         if (!status) {
5950                 if (ret_buff_size != NULL)
5951                         *ret_buff_size = LE16_TO_CPU(desc.datalen);
5952                 if (ret_next_table != NULL)
5953                         *ret_next_table = resp->table_id;
5954                 if (ret_next_index != NULL)
5955                         *ret_next_index = LE32_TO_CPU(resp->idx);
5956         }
5957
5958         return status;
5959 }
5960
5961 /**
5962  * i40e_read_bw_from_alt_ram
5963  * @hw: pointer to the hardware structure
5964  * @max_bw: pointer for max_bw read
5965  * @min_bw: pointer for min_bw read
5966  * @min_valid: pointer for bool that is true if min_bw is a valid value
5967  * @max_valid: pointer for bool that is true if max_bw is a valid value
5968  *
5969  * Read bw from the alternate ram for the given pf
5970  **/
5971 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
5972                                         u32 *max_bw, u32 *min_bw,
5973                                         bool *min_valid, bool *max_valid)
5974 {
5975         enum i40e_status_code status;
5976         u32 max_bw_addr, min_bw_addr;
5977
5978         /* Calculate the address of the min/max bw registers */
5979         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5980                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
5981                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5982         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5983                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
5984                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5985
5986         /* Read the bandwidths from alt ram */
5987         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
5988                                         min_bw_addr, min_bw);
5989
5990         if (*min_bw & I40E_ALT_BW_VALID_MASK)
5991                 *min_valid = true;
5992         else
5993                 *min_valid = false;
5994
5995         if (*max_bw & I40E_ALT_BW_VALID_MASK)
5996                 *max_valid = true;
5997         else
5998                 *max_valid = false;
5999
6000         return status;
6001 }
6002
6003 /**
6004  * i40e_aq_configure_partition_bw
6005  * @hw: pointer to the hardware structure
6006  * @bw_data: Buffer holding valid pfs and bw limits
6007  * @cmd_details: pointer to command details
6008  *
6009  * Configure partitions guaranteed/max bw
6010  **/
6011 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6012                         struct i40e_aqc_configure_partition_bw_data *bw_data,
6013                         struct i40e_asq_cmd_details *cmd_details)
6014 {
6015         enum i40e_status_code status;
6016         struct i40e_aq_desc desc;
6017         u16 bwd_size = sizeof(*bw_data);
6018
6019         i40e_fill_default_direct_cmd_desc(&desc,
6020                                 i40e_aqc_opc_configure_partition_bw);
6021
6022         /* Indirect command */
6023         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6024         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6025
6026         desc.datalen = CPU_TO_LE16(bwd_size);
6027
6028         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6029
6030         return status;
6031 }
6032
6033 /**
6034  * i40e_read_phy_register_clause22
6035  * @hw: pointer to the HW structure
6036  * @reg: register address in the page
6037  * @phy_adr: PHY address on MDIO interface
6038  * @value: PHY register value
6039  *
6040  * Reads specified PHY register value
6041  **/
6042 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
6043                                         u16 reg, u8 phy_addr, u16 *value)
6044 {
6045         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6046         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6047         u32 command = 0;
6048         u16 retry = 1000;
6049
6050         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6051                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6052                   (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
6053                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6054                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6055         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6056         do {
6057                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6058                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6059                         status = I40E_SUCCESS;
6060                         break;
6061                 }
6062                 i40e_usec_delay(10);
6063                 retry--;
6064         } while (retry);
6065
6066         if (status) {
6067                 i40e_debug(hw, I40E_DEBUG_PHY,
6068                            "PHY: Can't write command to external PHY.\n");
6069         } else {
6070                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6071                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6072                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6073         }
6074
6075         return status;
6076 }
6077
6078 /**
6079  * i40e_write_phy_register_clause22
6080  * @hw: pointer to the HW structure
6081  * @reg: register address in the page
6082  * @phy_adr: PHY address on MDIO interface
6083  * @value: PHY register value
6084  *
6085  * Writes specified PHY register value
6086  **/
6087 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6088                                         u16 reg, u8 phy_addr, u16 value)
6089 {
6090         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6091         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6092         u32 command  = 0;
6093         u16 retry = 1000;
6094
6095         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6096         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6097
6098         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6099                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6100                   (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6101                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6102                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6103
6104         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6105         do {
6106                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6107                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6108                         status = I40E_SUCCESS;
6109                         break;
6110                 }
6111                 i40e_usec_delay(10);
6112                 retry--;
6113         } while (retry);
6114
6115         return status;
6116 }
6117
6118 /**
6119  * i40e_read_phy_register_clause45
6120  * @hw: pointer to the HW structure
6121  * @page: registers page number
6122  * @reg: register address in the page
6123  * @phy_adr: PHY address on MDIO interface
6124  * @value: PHY register value
6125  *
6126  * Reads specified PHY register value
6127  **/
6128 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6129                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6130 {
6131         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6132         u32 command  = 0;
6133         u16 retry = 1000;
6134         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6135
6136         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6137                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6138                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6139                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6140                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6141                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6142                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6143         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6144         do {
6145                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6146                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6147                         status = I40E_SUCCESS;
6148                         break;
6149                 }
6150                 i40e_usec_delay(10);
6151                 retry--;
6152         } while (retry);
6153
6154         if (status) {
6155                 i40e_debug(hw, I40E_DEBUG_PHY,
6156                            "PHY: Can't write command to external PHY.\n");
6157                 goto phy_read_end;
6158         }
6159
6160         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6161                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6162                   (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6163                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6164                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6165                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6166         status = I40E_ERR_TIMEOUT;
6167         retry = 1000;
6168         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6169         do {
6170                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6171                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6172                         status = I40E_SUCCESS;
6173                         break;
6174                 }
6175                 i40e_usec_delay(10);
6176                 retry--;
6177         } while (retry);
6178
6179         if (!status) {
6180                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6181                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6182                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6183         } else {
6184                 i40e_debug(hw, I40E_DEBUG_PHY,
6185                            "PHY: Can't read register value from external PHY.\n");
6186         }
6187
6188 phy_read_end:
6189         return status;
6190 }
6191
6192 /**
6193  * i40e_write_phy_register_clause45
6194  * @hw: pointer to the HW structure
6195  * @page: registers page number
6196  * @reg: register address in the page
6197  * @phy_adr: PHY address on MDIO interface
6198  * @value: PHY register value
6199  *
6200  * Writes value to specified PHY register
6201  **/
6202 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6203                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6204 {
6205         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6206         u32 command  = 0;
6207         u16 retry = 1000;
6208         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6209
6210         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6211                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6212                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6213                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6214                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6215                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6216                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6217         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6218         do {
6219                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6220                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6221                         status = I40E_SUCCESS;
6222                         break;
6223                 }
6224                 i40e_usec_delay(10);
6225                 retry--;
6226         } while (retry);
6227         if (status) {
6228                 i40e_debug(hw, I40E_DEBUG_PHY,
6229                            "PHY: Can't write command to external PHY.\n");
6230                 goto phy_write_end;
6231         }
6232
6233         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6234         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6235
6236         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6237                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6238                   (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6239                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6240                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6241                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6242         status = I40E_ERR_TIMEOUT;
6243         retry = 1000;
6244         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6245         do {
6246                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6247                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6248                         status = I40E_SUCCESS;
6249                         break;
6250                 }
6251                 i40e_usec_delay(10);
6252                 retry--;
6253         } while (retry);
6254
6255 phy_write_end:
6256         return status;
6257 }
6258
6259 /**
6260  * i40e_write_phy_register
6261  * @hw: pointer to the HW structure
6262  * @page: registers page number
6263  * @reg: register address in the page
6264  * @phy_adr: PHY address on MDIO interface
6265  * @value: PHY register value
6266  *
6267  * Writes value to specified PHY register
6268  **/
6269 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6270                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6271 {
6272         enum i40e_status_code status;
6273
6274         switch (hw->device_id) {
6275         case I40E_DEV_ID_1G_BASE_T_X722:
6276                 status = i40e_write_phy_register_clause22(hw,
6277                         reg, phy_addr, value);
6278                 break;
6279         case I40E_DEV_ID_10G_BASE_T:
6280         case I40E_DEV_ID_10G_BASE_T4:
6281         case I40E_DEV_ID_10G_BASE_T_X722:
6282         case I40E_DEV_ID_25G_B:
6283         case I40E_DEV_ID_25G_SFP28:
6284                 status = i40e_write_phy_register_clause45(hw,
6285                         page, reg, phy_addr, value);
6286                 break;
6287         default:
6288                 status = I40E_ERR_UNKNOWN_PHY;
6289                 break;
6290         }
6291
6292         return status;
6293 }
6294
6295 /**
6296  * i40e_read_phy_register
6297  * @hw: pointer to the HW structure
6298  * @page: registers page number
6299  * @reg: register address in the page
6300  * @phy_adr: PHY address on MDIO interface
6301  * @value: PHY register value
6302  *
6303  * Reads specified PHY register value
6304  **/
6305 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6306                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6307 {
6308         enum i40e_status_code status;
6309
6310         switch (hw->device_id) {
6311         case I40E_DEV_ID_1G_BASE_T_X722:
6312                 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6313                                                          value);
6314                 break;
6315         case I40E_DEV_ID_10G_BASE_T:
6316         case I40E_DEV_ID_10G_BASE_T4:
6317         case I40E_DEV_ID_10G_BASE_T_X722:
6318         case I40E_DEV_ID_25G_B:
6319         case I40E_DEV_ID_25G_SFP28:
6320                 status = i40e_read_phy_register_clause45(hw, page, reg,
6321                                                          phy_addr, value);
6322                 break;
6323         default:
6324                 status = I40E_ERR_UNKNOWN_PHY;
6325                 break;
6326         }
6327
6328         return status;
6329 }
6330
6331 /**
6332  * i40e_get_phy_address
6333  * @hw: pointer to the HW structure
6334  * @dev_num: PHY port num that address we want
6335  * @phy_addr: Returned PHY address
6336  *
6337  * Gets PHY address for current port
6338  **/
6339 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6340 {
6341         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6342         u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6343
6344         return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6345 }
6346
6347 /**
6348  * i40e_blink_phy_led
6349  * @hw: pointer to the HW structure
6350  * @time: time how long led will blinks in secs
6351  * @interval: gap between LED on and off in msecs
6352  *
6353  * Blinks PHY link LED
6354  **/
6355 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6356                                               u32 time, u32 interval)
6357 {
6358         enum i40e_status_code status = I40E_SUCCESS;
6359         u32 i;
6360         u16 led_ctl = 0;
6361         u16 gpio_led_port;
6362         u16 led_reg;
6363         u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6364         u8 phy_addr = 0;
6365         u8 port_num;
6366
6367         i = rd32(hw, I40E_PFGEN_PORTNUM);
6368         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6369         phy_addr = i40e_get_phy_address(hw, port_num);
6370
6371         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6372              led_addr++) {
6373                 status = i40e_read_phy_register_clause45(hw,
6374                                                          I40E_PHY_COM_REG_PAGE,
6375                                                          led_addr, phy_addr,
6376                                                          &led_reg);
6377                 if (status)
6378                         goto phy_blinking_end;
6379                 led_ctl = led_reg;
6380                 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6381                         led_reg = 0;
6382                         status = i40e_write_phy_register_clause45(hw,
6383                                                          I40E_PHY_COM_REG_PAGE,
6384                                                          led_addr, phy_addr,
6385                                                          led_reg);
6386                         if (status)
6387                                 goto phy_blinking_end;
6388                         break;
6389                 }
6390         }
6391
6392         if (time > 0 && interval > 0) {
6393                 for (i = 0; i < time * 1000; i += interval) {
6394                         status = i40e_read_phy_register_clause45(hw,
6395                                                 I40E_PHY_COM_REG_PAGE,
6396                                                 led_addr, phy_addr, &led_reg);
6397                         if (status)
6398                                 goto restore_config;
6399                         if (led_reg & I40E_PHY_LED_MANUAL_ON)
6400                                 led_reg = 0;
6401                         else
6402                                 led_reg = I40E_PHY_LED_MANUAL_ON;
6403                         status = i40e_write_phy_register_clause45(hw,
6404                                                 I40E_PHY_COM_REG_PAGE,
6405                                                 led_addr, phy_addr, led_reg);
6406                         if (status)
6407                                 goto restore_config;
6408                         i40e_msec_delay(interval);
6409                 }
6410         }
6411
6412 restore_config:
6413         status = i40e_write_phy_register_clause45(hw,
6414                                                   I40E_PHY_COM_REG_PAGE,
6415                                                   led_addr, phy_addr, led_ctl);
6416
6417 phy_blinking_end:
6418         return status;
6419 }
6420
6421 /**
6422  * i40e_led_get_phy - return current on/off mode
6423  * @hw: pointer to the hw struct
6424  * @led_addr: address of led register to use
6425  * @val: original value of register to use
6426  *
6427  **/
6428 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6429                                        u16 *val)
6430 {
6431         enum i40e_status_code status = I40E_SUCCESS;
6432         u16 gpio_led_port;
6433         u8 phy_addr = 0;
6434         u16 reg_val;
6435         u16 temp_addr;
6436         u8 port_num;
6437         u32 i;
6438
6439         temp_addr = I40E_PHY_LED_PROV_REG_1;
6440         i = rd32(hw, I40E_PFGEN_PORTNUM);
6441         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6442         phy_addr = i40e_get_phy_address(hw, port_num);
6443
6444         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6445              temp_addr++) {
6446                 status = i40e_read_phy_register_clause45(hw,
6447                                                          I40E_PHY_COM_REG_PAGE,
6448                                                          temp_addr, phy_addr,
6449                                                          &reg_val);
6450                 if (status)
6451                         return status;
6452                 *val = reg_val;
6453                 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6454                         *led_addr = temp_addr;
6455                         break;
6456                 }
6457         }
6458         return status;
6459 }
6460
6461 /**
6462  * i40e_led_set_phy
6463  * @hw: pointer to the HW structure
6464  * @on: true or false
6465  * @mode: original val plus bit for set or ignore
6466  * Set led's on or off when controlled by the PHY
6467  *
6468  **/
6469 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6470                                        u16 led_addr, u32 mode)
6471 {
6472         enum i40e_status_code status = I40E_SUCCESS;
6473         u16 led_ctl = 0;
6474         u16 led_reg = 0;
6475         u8 phy_addr = 0;
6476         u8 port_num;
6477         u32 i;
6478
6479         i = rd32(hw, I40E_PFGEN_PORTNUM);
6480         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6481         phy_addr = i40e_get_phy_address(hw, port_num);
6482         status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6483                                                  led_addr, phy_addr, &led_reg);
6484         if (status)
6485                 return status;
6486         led_ctl = led_reg;
6487         if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6488                 led_reg = 0;
6489                 status = i40e_write_phy_register_clause45(hw,
6490                                                           I40E_PHY_COM_REG_PAGE,
6491                                                           led_addr, phy_addr,
6492                                                           led_reg);
6493                 if (status)
6494                         return status;
6495         }
6496         status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6497                                                  led_addr, phy_addr, &led_reg);
6498         if (status)
6499                 goto restore_config;
6500         if (on)
6501                 led_reg = I40E_PHY_LED_MANUAL_ON;
6502         else
6503                 led_reg = 0;
6504         status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6505                                                   led_addr, phy_addr, led_reg);
6506         if (status)
6507                 goto restore_config;
6508         if (mode & I40E_PHY_LED_MODE_ORIG) {
6509                 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6510                 status = i40e_write_phy_register_clause45(hw,
6511                                                  I40E_PHY_COM_REG_PAGE,
6512                                                  led_addr, phy_addr, led_ctl);
6513         }
6514         return status;
6515 restore_config:
6516         status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6517                                                   led_addr, phy_addr, led_ctl);
6518         return status;
6519 }
6520 #endif /* PF_DRIVER */
6521
6522 /**
6523  * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6524  * @hw: pointer to the hw struct
6525  * @reg_addr: register address
6526  * @reg_val: ptr to register value
6527  * @cmd_details: pointer to command details structure or NULL
6528  *
6529  * Use the firmware to read the Rx control register,
6530  * especially useful if the Rx unit is under heavy pressure
6531  **/
6532 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6533                                 u32 reg_addr, u32 *reg_val,
6534                                 struct i40e_asq_cmd_details *cmd_details)
6535 {
6536         struct i40e_aq_desc desc;
6537         struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
6538                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6539         enum i40e_status_code status;
6540
6541         if (reg_val == NULL)
6542                 return I40E_ERR_PARAM;
6543
6544         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
6545
6546         cmd_resp->address = CPU_TO_LE32(reg_addr);
6547
6548         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6549
6550         if (status == I40E_SUCCESS)
6551                 *reg_val = LE32_TO_CPU(cmd_resp->value);
6552
6553         return status;
6554 }
6555
6556 /**
6557  * i40e_read_rx_ctl - read from an Rx control register
6558  * @hw: pointer to the hw struct
6559  * @reg_addr: register address
6560  **/
6561 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
6562 {
6563         enum i40e_status_code status = I40E_SUCCESS;
6564         bool use_register;
6565         int retry = 5;
6566         u32 val = 0;
6567
6568         use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6569         if (!use_register) {
6570 do_retry:
6571                 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
6572                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6573                         i40e_msec_delay(1);
6574                         retry--;
6575                         goto do_retry;
6576                 }
6577         }
6578
6579         /* if the AQ access failed, try the old-fashioned way */
6580         if (status || use_register)
6581                 val = rd32(hw, reg_addr);
6582
6583         return val;
6584 }
6585
6586 /**
6587  * i40e_aq_rx_ctl_write_register
6588  * @hw: pointer to the hw struct
6589  * @reg_addr: register address
6590  * @reg_val: register value
6591  * @cmd_details: pointer to command details structure or NULL
6592  *
6593  * Use the firmware to write to an Rx control register,
6594  * especially useful if the Rx unit is under heavy pressure
6595  **/
6596 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
6597                                 u32 reg_addr, u32 reg_val,
6598                                 struct i40e_asq_cmd_details *cmd_details)
6599 {
6600         struct i40e_aq_desc desc;
6601         struct i40e_aqc_rx_ctl_reg_read_write *cmd =
6602                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6603         enum i40e_status_code status;
6604
6605         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
6606
6607         cmd->address = CPU_TO_LE32(reg_addr);
6608         cmd->value = CPU_TO_LE32(reg_val);
6609
6610         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6611
6612         return status;
6613 }
6614
6615 /**
6616  * i40e_write_rx_ctl - write to an Rx control register
6617  * @hw: pointer to the hw struct
6618  * @reg_addr: register address
6619  * @reg_val: register value
6620  **/
6621 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
6622 {
6623         enum i40e_status_code status = I40E_SUCCESS;
6624         bool use_register;
6625         int retry = 5;
6626
6627         use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6628         if (!use_register) {
6629 do_retry:
6630                 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
6631                                                        reg_val, NULL);
6632                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6633                         i40e_msec_delay(1);
6634                         retry--;
6635                         goto do_retry;
6636                 }
6637         }
6638
6639         /* if the AQ access failed, try the old-fashioned way */
6640         if (status || use_register)
6641                 wr32(hw, reg_addr, reg_val);
6642 }
6643 #ifdef VF_DRIVER
6644
6645 /**
6646  * i40e_aq_send_msg_to_pf
6647  * @hw: pointer to the hardware structure
6648  * @v_opcode: opcodes for VF-PF communication
6649  * @v_retval: return error code
6650  * @msg: pointer to the msg buffer
6651  * @msglen: msg length
6652  * @cmd_details: pointer to command details
6653  *
6654  * Send message to PF driver using admin queue. By default, this message
6655  * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
6656  * completion before returning.
6657  **/
6658 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
6659                                 enum i40e_virtchnl_ops v_opcode,
6660                                 enum i40e_status_code v_retval,
6661                                 u8 *msg, u16 msglen,
6662                                 struct i40e_asq_cmd_details *cmd_details)
6663 {
6664         struct i40e_aq_desc desc;
6665         struct i40e_asq_cmd_details details;
6666         enum i40e_status_code status;
6667
6668         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
6669         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
6670         desc.cookie_high = CPU_TO_LE32(v_opcode);
6671         desc.cookie_low = CPU_TO_LE32(v_retval);
6672         if (msglen) {
6673                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
6674                                                 | I40E_AQ_FLAG_RD));
6675                 if (msglen > I40E_AQ_LARGE_BUF)
6676                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6677                 desc.datalen = CPU_TO_LE16(msglen);
6678         }
6679         if (!cmd_details) {
6680                 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
6681                 details.async = true;
6682                 cmd_details = &details;
6683         }
6684         status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
6685                                        msglen, cmd_details);
6686         return status;
6687 }
6688
6689 /**
6690  * i40e_vf_parse_hw_config
6691  * @hw: pointer to the hardware structure
6692  * @msg: pointer to the virtual channel VF resource structure
6693  *
6694  * Given a VF resource message from the PF, populate the hw struct
6695  * with appropriate information.
6696  **/
6697 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
6698                              struct i40e_virtchnl_vf_resource *msg)
6699 {
6700         struct i40e_virtchnl_vsi_resource *vsi_res;
6701         int i;
6702
6703         vsi_res = &msg->vsi_res[0];
6704
6705         hw->dev_caps.num_vsis = msg->num_vsis;
6706         hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
6707         hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
6708         hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
6709         hw->dev_caps.dcb = msg->vf_offload_flags &
6710                            I40E_VIRTCHNL_VF_OFFLOAD_L2;
6711         hw->dev_caps.fcoe = (msg->vf_offload_flags &
6712                              I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
6713         hw->dev_caps.iwarp = (msg->vf_offload_flags &
6714                               I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
6715         for (i = 0; i < msg->num_vsis; i++) {
6716                 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
6717                         i40e_memcpy(hw->mac.perm_addr,
6718                                     vsi_res->default_mac_addr,
6719                                     I40E_ETH_LENGTH_OF_ADDRESS,
6720                                     I40E_NONDMA_TO_NONDMA);
6721                         i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
6722                                     I40E_ETH_LENGTH_OF_ADDRESS,
6723                                     I40E_NONDMA_TO_NONDMA);
6724                 }
6725                 vsi_res++;
6726         }
6727 }
6728
6729 /**
6730  * i40e_vf_reset
6731  * @hw: pointer to the hardware structure
6732  *
6733  * Send a VF_RESET message to the PF. Does not wait for response from PF
6734  * as none will be forthcoming. Immediately after calling this function,
6735  * the admin queue should be shut down and (optionally) reinitialized.
6736  **/
6737 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
6738 {
6739         return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
6740                                       I40E_SUCCESS, NULL, 0, NULL);
6741 }
6742 #endif /* VF_DRIVER */
6743 #ifdef X722_SUPPORT
6744
6745 /**
6746  * i40e_aq_set_arp_proxy_config
6747  * @hw: pointer to the HW structure
6748  * @proxy_config - pointer to proxy config command table struct
6749  * @cmd_details: pointer to command details
6750  *
6751  * Set ARP offload parameters from pre-populated
6752  * i40e_aqc_arp_proxy_data struct
6753  **/
6754 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
6755                                 struct i40e_aqc_arp_proxy_data *proxy_config,
6756                                 struct i40e_asq_cmd_details *cmd_details)
6757 {
6758         struct i40e_aq_desc desc;
6759         enum i40e_status_code status;
6760
6761         if (!proxy_config)
6762                 return I40E_ERR_PARAM;
6763
6764         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
6765
6766         desc.params.external.addr_high =
6767                                   CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
6768         desc.params.external.addr_low =
6769                                   CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
6770
6771         status = i40e_asq_send_command(hw, &desc, proxy_config,
6772                                        sizeof(struct i40e_aqc_arp_proxy_data),
6773                                        cmd_details);
6774
6775         return status;
6776 }
6777
6778 /**
6779  * i40e_aq_opc_set_ns_proxy_table_entry
6780  * @hw: pointer to the HW structure
6781  * @ns_proxy_table_entry: pointer to NS table entry command struct
6782  * @cmd_details: pointer to command details
6783  *
6784  * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
6785  * from pre-populated i40e_aqc_ns_proxy_data struct
6786  **/
6787 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
6788                         struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
6789                         struct i40e_asq_cmd_details *cmd_details)
6790 {
6791         struct i40e_aq_desc desc;
6792         enum i40e_status_code status;
6793
6794         if (!ns_proxy_table_entry)
6795                 return I40E_ERR_PARAM;
6796
6797         i40e_fill_default_direct_cmd_desc(&desc,
6798                                 i40e_aqc_opc_set_ns_proxy_table_entry);
6799
6800         desc.params.external.addr_high =
6801                 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
6802         desc.params.external.addr_low =
6803                 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
6804
6805         status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
6806                                        sizeof(struct i40e_aqc_ns_proxy_data),
6807                                        cmd_details);
6808
6809         return status;
6810 }
6811
6812 /**
6813  * i40e_aq_set_clear_wol_filter
6814  * @hw: pointer to the hw struct
6815  * @filter_index: index of filter to modify (0-7)
6816  * @filter: buffer containing filter to be set
6817  * @set_filter: true to set filter, false to clear filter
6818  * @no_wol_tco: if true, pass through packets cannot cause wake-up
6819  *              if false, pass through packets may cause wake-up
6820  * @filter_valid: true if filter action is valid
6821  * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
6822  * @cmd_details: pointer to command details structure or NULL
6823  *
6824  * Set or clear WoL filter for port attached to the PF
6825  **/
6826 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
6827                                 u8 filter_index,
6828                                 struct i40e_aqc_set_wol_filter_data *filter,
6829                                 bool set_filter, bool no_wol_tco,
6830                                 bool filter_valid, bool no_wol_tco_valid,
6831                                 struct i40e_asq_cmd_details *cmd_details)
6832 {
6833         struct i40e_aq_desc desc;
6834         struct i40e_aqc_set_wol_filter *cmd =
6835                 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
6836         enum i40e_status_code status;
6837         u16 cmd_flags = 0;
6838         u16 valid_flags = 0;
6839         u16 buff_len = 0;
6840
6841         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
6842
6843         if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
6844                 return  I40E_ERR_PARAM;
6845         cmd->filter_index = CPU_TO_LE16(filter_index);
6846
6847         if (set_filter) {
6848                 if (!filter)
6849                         return  I40E_ERR_PARAM;
6850                 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
6851                 buff_len = sizeof(*filter);
6852         }
6853         if (no_wol_tco)
6854                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
6855         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
6856
6857         if (filter_valid)
6858                 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
6859         if (no_wol_tco_valid)
6860                 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
6861         cmd->valid_flags = CPU_TO_LE16(valid_flags);
6862
6863         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
6864         cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
6865
6866         status = i40e_asq_send_command(hw, &desc, filter,
6867                                        buff_len, cmd_details);
6868
6869         return status;
6870 }
6871
6872 /**
6873  * i40e_aq_get_wake_event_reason
6874  * @hw: pointer to the hw struct
6875  * @wake_reason: return value, index of matching filter
6876  * @cmd_details: pointer to command details structure or NULL
6877  *
6878  * Get information for the reason of a Wake Up event
6879  **/
6880 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
6881                                 u16 *wake_reason,
6882                                 struct i40e_asq_cmd_details *cmd_details)
6883 {
6884         struct i40e_aq_desc desc;
6885         struct i40e_aqc_get_wake_reason_completion *resp =
6886                 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
6887         enum i40e_status_code status;
6888
6889         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
6890
6891         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6892
6893         if (status == I40E_SUCCESS)
6894                 *wake_reason = LE16_TO_CPU(resp->wake_reason);
6895
6896         return status;
6897 }
6898
6899 #endif /* X722_SUPPORT */