drivers/net/i40e/base/i40e_common.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "i40e_type.h"
  35 #include "i40e_adminq.h"
  36 #include "i40e_prototype.h"
  37 #include "i40e_virtchnl.h"
  38
  39
  40 /**
  41  * i40e_set_mac_type - Sets MAC type
  42  * @hw: pointer to the HW structure
  43  *
  44  * This function sets the mac type of the adapter based on the
  45  * vendor ID and device ID stored in the hw structure.
  46  **/
  47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  49 #else
  50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  51 #endif
  52 {
  53         enum i40e_status_code status = I40E_SUCCESS;
  54
  55         DEBUGFUNC("i40e_set_mac_type\n");
  56
  57         if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
  58                 switch (hw->device_id) {
  59                 case I40E_DEV_ID_SFP_XL710:
  60                 case I40E_DEV_ID_QEMU:
  61                 case I40E_DEV_ID_KX_B:
  62                 case I40E_DEV_ID_KX_C:
  63                 case I40E_DEV_ID_QSFP_A:
  64                 case I40E_DEV_ID_QSFP_B:
  65                 case I40E_DEV_ID_QSFP_C:
  66                 case I40E_DEV_ID_10G_BASE_T:
  67                 case I40E_DEV_ID_10G_BASE_T4:
  68                 case I40E_DEV_ID_20G_KR2:
  69                 case I40E_DEV_ID_20G_KR2_A:
  70                         hw->mac.type = I40E_MAC_XL710;
  71                         break;
  72 #ifdef X722_SUPPORT
  73 #ifdef X722_A0_SUPPORT
  74                 case I40E_DEV_ID_X722_A0:
  75 #endif
  76                 case I40E_DEV_ID_KX_X722:
  77                 case I40E_DEV_ID_QSFP_X722:
  78                 case I40E_DEV_ID_SFP_X722:
  79                 case I40E_DEV_ID_1G_BASE_T_X722:
  80                 case I40E_DEV_ID_10G_BASE_T_X722:
  81                         hw->mac.type = I40E_MAC_X722;
  82                         break;
  83 #endif
  84 #ifdef X722_SUPPORT
  85 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  86                 case I40E_DEV_ID_X722_VF:
  87                 case I40E_DEV_ID_X722_VF_HV:
  88 #ifdef X722_A0_SUPPORT
  89                 case I40E_DEV_ID_X722_A0_VF:
  90 #endif
  91                         hw->mac.type = I40E_MAC_X722_VF;
  92                         break;
  93 #endif /* INTEGRATED_VF || VF_DRIVER */
  94 #endif /* X722_SUPPORT */
  95 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  96                 case I40E_DEV_ID_VF:
  97                 case I40E_DEV_ID_VF_HV:
  98                         hw->mac.type = I40E_MAC_VF;
  99                         break;
 100 #endif
 101                 default:
 102                         hw->mac.type = I40E_MAC_GENERIC;
 103                         break;
 104                 }
 105         } else {
 106                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
 107         }
 108
 109         DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
 110                   hw->mac.type, status);
 111         return status;
 112 }
 113
 114 #ifndef I40E_NDIS_SUPPORT
 115 /**
 116  * i40e_aq_str - convert AQ err code to a string
 117  * @hw: pointer to the HW structure
 118  * @aq_err: the AQ error code to convert
 119  **/
 120 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
 121 {
 122         switch (aq_err) {
 123         case I40E_AQ_RC_OK:
 124                 return "OK";
 125         case I40E_AQ_RC_EPERM:
 126                 return "I40E_AQ_RC_EPERM";
 127         case I40E_AQ_RC_ENOENT:
 128                 return "I40E_AQ_RC_ENOENT";
 129         case I40E_AQ_RC_ESRCH:
 130                 return "I40E_AQ_RC_ESRCH";
 131         case I40E_AQ_RC_EINTR:
 132                 return "I40E_AQ_RC_EINTR";
 133         case I40E_AQ_RC_EIO:
 134                 return "I40E_AQ_RC_EIO";
 135         case I40E_AQ_RC_ENXIO:
 136                 return "I40E_AQ_RC_ENXIO";
 137         case I40E_AQ_RC_E2BIG:
 138                 return "I40E_AQ_RC_E2BIG";
 139         case I40E_AQ_RC_EAGAIN:
 140                 return "I40E_AQ_RC_EAGAIN";
 141         case I40E_AQ_RC_ENOMEM:
 142                 return "I40E_AQ_RC_ENOMEM";
 143         case I40E_AQ_RC_EACCES:
 144                 return "I40E_AQ_RC_EACCES";
 145         case I40E_AQ_RC_EFAULT:
 146                 return "I40E_AQ_RC_EFAULT";
 147         case I40E_AQ_RC_EBUSY:
 148                 return "I40E_AQ_RC_EBUSY";
 149         case I40E_AQ_RC_EEXIST:
 150                 return "I40E_AQ_RC_EEXIST";
 151         case I40E_AQ_RC_EINVAL:
 152                 return "I40E_AQ_RC_EINVAL";
 153         case I40E_AQ_RC_ENOTTY:
 154                 return "I40E_AQ_RC_ENOTTY";
 155         case I40E_AQ_RC_ENOSPC:
 156                 return "I40E_AQ_RC_ENOSPC";
 157         case I40E_AQ_RC_ENOSYS:
 158                 return "I40E_AQ_RC_ENOSYS";
 159         case I40E_AQ_RC_ERANGE:
 160                 return "I40E_AQ_RC_ERANGE";
 161         case I40E_AQ_RC_EFLUSHED:
 162                 return "I40E_AQ_RC_EFLUSHED";
 163         case I40E_AQ_RC_BAD_ADDR:
 164                 return "I40E_AQ_RC_BAD_ADDR";
 165         case I40E_AQ_RC_EMODE:
 166                 return "I40E_AQ_RC_EMODE";
 167         case I40E_AQ_RC_EFBIG:
 168                 return "I40E_AQ_RC_EFBIG";
 169         }
 170
 171         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 172         return hw->err_str;
 173 }
 174
 175 /**
 176  * i40e_stat_str - convert status err code to a string
 177  * @hw: pointer to the HW structure
 178  * @stat_err: the status error code to convert
 179  **/
 180 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
 181 {
 182         switch (stat_err) {
 183         case I40E_SUCCESS:
 184                 return "OK";
 185         case I40E_ERR_NVM:
 186                 return "I40E_ERR_NVM";
 187         case I40E_ERR_NVM_CHECKSUM:
 188                 return "I40E_ERR_NVM_CHECKSUM";
 189         case I40E_ERR_PHY:
 190                 return "I40E_ERR_PHY";
 191         case I40E_ERR_CONFIG:
 192                 return "I40E_ERR_CONFIG";
 193         case I40E_ERR_PARAM:
 194                 return "I40E_ERR_PARAM";
 195         case I40E_ERR_MAC_TYPE:
 196                 return "I40E_ERR_MAC_TYPE";
 197         case I40E_ERR_UNKNOWN_PHY:
 198                 return "I40E_ERR_UNKNOWN_PHY";
 199         case I40E_ERR_LINK_SETUP:
 200                 return "I40E_ERR_LINK_SETUP";
 201         case I40E_ERR_ADAPTER_STOPPED:
 202                 return "I40E_ERR_ADAPTER_STOPPED";
 203         case I40E_ERR_INVALID_MAC_ADDR:
 204                 return "I40E_ERR_INVALID_MAC_ADDR";
 205         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 206                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 207         case I40E_ERR_MASTER_REQUESTS_PENDING:
 208                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 209         case I40E_ERR_INVALID_LINK_SETTINGS:
 210                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 211         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 212                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 213         case I40E_ERR_RESET_FAILED:
 214                 return "I40E_ERR_RESET_FAILED";
 215         case I40E_ERR_SWFW_SYNC:
 216                 return "I40E_ERR_SWFW_SYNC";
 217         case I40E_ERR_NO_AVAILABLE_VSI:
 218                 return "I40E_ERR_NO_AVAILABLE_VSI";
 219         case I40E_ERR_NO_MEMORY:
 220                 return "I40E_ERR_NO_MEMORY";
 221         case I40E_ERR_BAD_PTR:
 222                 return "I40E_ERR_BAD_PTR";
 223         case I40E_ERR_RING_FULL:
 224                 return "I40E_ERR_RING_FULL";
 225         case I40E_ERR_INVALID_PD_ID:
 226                 return "I40E_ERR_INVALID_PD_ID";
 227         case I40E_ERR_INVALID_QP_ID:
 228                 return "I40E_ERR_INVALID_QP_ID";
 229         case I40E_ERR_INVALID_CQ_ID:
 230                 return "I40E_ERR_INVALID_CQ_ID";
 231         case I40E_ERR_INVALID_CEQ_ID:
 232                 return "I40E_ERR_INVALID_CEQ_ID";
 233         case I40E_ERR_INVALID_AEQ_ID:
 234                 return "I40E_ERR_INVALID_AEQ_ID";
 235         case I40E_ERR_INVALID_SIZE:
 236                 return "I40E_ERR_INVALID_SIZE";
 237         case I40E_ERR_INVALID_ARP_INDEX:
 238                 return "I40E_ERR_INVALID_ARP_INDEX";
 239         case I40E_ERR_INVALID_FPM_FUNC_ID:
 240                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 241         case I40E_ERR_QP_INVALID_MSG_SIZE:
 242                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 243         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 244                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 245         case I40E_ERR_INVALID_FRAG_COUNT:
 246                 return "I40E_ERR_INVALID_FRAG_COUNT";
 247         case I40E_ERR_QUEUE_EMPTY:
 248                 return "I40E_ERR_QUEUE_EMPTY";
 249         case I40E_ERR_INVALID_ALIGNMENT:
 250                 return "I40E_ERR_INVALID_ALIGNMENT";
 251         case I40E_ERR_FLUSHED_QUEUE:
 252                 return "I40E_ERR_FLUSHED_QUEUE";
 253         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 254                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 255         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 256                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 257         case I40E_ERR_TIMEOUT:
 258                 return "I40E_ERR_TIMEOUT";
 259         case I40E_ERR_OPCODE_MISMATCH:
 260                 return "I40E_ERR_OPCODE_MISMATCH";
 261         case I40E_ERR_CQP_COMPL_ERROR:
 262                 return "I40E_ERR_CQP_COMPL_ERROR";
 263         case I40E_ERR_INVALID_VF_ID:
 264                 return "I40E_ERR_INVALID_VF_ID";
 265         case I40E_ERR_INVALID_HMCFN_ID:
 266                 return "I40E_ERR_INVALID_HMCFN_ID";
 267         case I40E_ERR_BACKING_PAGE_ERROR:
 268                 return "I40E_ERR_BACKING_PAGE_ERROR";
 269         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 270                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 271         case I40E_ERR_INVALID_PBLE_INDEX:
 272                 return "I40E_ERR_INVALID_PBLE_INDEX";
 273         case I40E_ERR_INVALID_SD_INDEX:
 274                 return "I40E_ERR_INVALID_SD_INDEX";
 275         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 276                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 277         case I40E_ERR_INVALID_SD_TYPE:
 278                 return "I40E_ERR_INVALID_SD_TYPE";
 279         case I40E_ERR_MEMCPY_FAILED:
 280                 return "I40E_ERR_MEMCPY_FAILED";
 281         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 282                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 283         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 284                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 285         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 286                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 287         case I40E_ERR_SRQ_ENABLED:
 288                 return "I40E_ERR_SRQ_ENABLED";
 289         case I40E_ERR_ADMIN_QUEUE_ERROR:
 290                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 291         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 292                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 293         case I40E_ERR_BUF_TOO_SHORT:
 294                 return "I40E_ERR_BUF_TOO_SHORT";
 295         case I40E_ERR_ADMIN_QUEUE_FULL:
 296                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 297         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 298                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 299         case I40E_ERR_BAD_IWARP_CQE:
 300                 return "I40E_ERR_BAD_IWARP_CQE";
 301         case I40E_ERR_NVM_BLANK_MODE:
 302                 return "I40E_ERR_NVM_BLANK_MODE";
 303         case I40E_ERR_NOT_IMPLEMENTED:
 304                 return "I40E_ERR_NOT_IMPLEMENTED";
 305         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 306                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 307         case I40E_ERR_DIAG_TEST_FAILED:
 308                 return "I40E_ERR_DIAG_TEST_FAILED";
 309         case I40E_ERR_NOT_READY:
 310                 return "I40E_ERR_NOT_READY";
 311         case I40E_NOT_SUPPORTED:
 312                 return "I40E_NOT_SUPPORTED";
 313         case I40E_ERR_FIRMWARE_API_VERSION:
 314                 return "I40E_ERR_FIRMWARE_API_VERSION";
 315         }
 316
 317         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 318         return hw->err_str;
 319 }
 320
 321 #endif /* I40E_NDIS_SUPPORT */
 322 /**
 323  * i40e_debug_aq
 324  * @hw: debug mask related to admin queue
 325  * @mask: debug mask
 326  * @desc: pointer to admin queue descriptor
 327  * @buffer: pointer to command buffer
 328  * @buf_len: max length of buffer
 329  *
 330  * Dumps debug log about adminq command with descriptor contents.
 331  **/
 332 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 333                    void *buffer, u16 buf_len)
 334 {
 335         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 336         u16 len = LE16_TO_CPU(aq_desc->datalen);
 337         u8 *buf = (u8 *)buffer;
 338         u16 i = 0;
 339
 340         if ((!(mask & hw->debug_mask)) || (desc == NULL))
 341                 return;
 342
 343         i40e_debug(hw, mask,
 344                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 345                    LE16_TO_CPU(aq_desc->opcode),
 346                    LE16_TO_CPU(aq_desc->flags),
 347                    LE16_TO_CPU(aq_desc->datalen),
 348                    LE16_TO_CPU(aq_desc->retval));
 349         i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
 350                    LE32_TO_CPU(aq_desc->cookie_high),
 351                    LE32_TO_CPU(aq_desc->cookie_low));
 352         i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
 353                    LE32_TO_CPU(aq_desc->params.internal.param0),
 354                    LE32_TO_CPU(aq_desc->params.internal.param1));
 355         i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
 356                    LE32_TO_CPU(aq_desc->params.external.addr_high),
 357                    LE32_TO_CPU(aq_desc->params.external.addr_low));
 358
 359         if ((buffer != NULL) && (aq_desc->datalen != 0)) {
 360                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 361                 if (buf_len < len)
 362                         len = buf_len;
 363                 /* write the full 16-byte chunks */
 364                 for (i = 0; i < (len - 16); i += 16)
 365                         i40e_debug(hw, mask,
 366                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 367                                    i, buf[i], buf[i+1], buf[i+2], buf[i+3],
 368                                    buf[i+4], buf[i+5], buf[i+6], buf[i+7],
 369                                    buf[i+8], buf[i+9], buf[i+10], buf[i+11],
 370                                    buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
 371                 /* the most we could have left is 16 bytes, pad with zeros */
 372                 if (i < len) {
 373                         char d_buf[16];
 374                         int j;
 375
 376                         memset(d_buf, 0, sizeof(d_buf));
 377                         for (j = 0; i < len; j++, i++)
 378                                 d_buf[j] = buf[i];
 379                         i40e_debug(hw, mask,
 380                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 381                                    i, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
 382                                    d_buf[4], d_buf[5], d_buf[6], d_buf[7],
 383                                    d_buf[8], d_buf[9], d_buf[10], d_buf[11],
 384                                    d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
 385                 }
 386         }
 387 }
 388
 389 /**
 390  * i40e_check_asq_alive
 391  * @hw: pointer to the hw struct
 392  *
 393  * Returns true if Queue is enabled else false.
 394  **/
 395 bool i40e_check_asq_alive(struct i40e_hw *hw)
 396 {
 397         if (hw->aq.asq.len)
 398 #ifdef PF_DRIVER
 399 #ifdef INTEGRATED_VF
 400                 if (!i40e_is_vf(hw))
 401                         return !!(rd32(hw, hw->aq.asq.len) &
 402                                 I40E_PF_ATQLEN_ATQENABLE_MASK);
 403 #else
 404                 return !!(rd32(hw, hw->aq.asq.len) &
 405                         I40E_PF_ATQLEN_ATQENABLE_MASK);
 406 #endif /* INTEGRATED_VF */
 407 #endif /* PF_DRIVER */
 408 #ifdef VF_DRIVER
 409 #ifdef INTEGRATED_VF
 410                 if (i40e_is_vf(hw))
 411                         return !!(rd32(hw, hw->aq.asq.len) &
 412                                 I40E_VF_ATQLEN1_ATQENABLE_MASK);
 413 #else
 414                 return !!(rd32(hw, hw->aq.asq.len) &
 415                         I40E_VF_ATQLEN1_ATQENABLE_MASK);
 416 #endif /* INTEGRATED_VF */
 417 #endif /* VF_DRIVER */
 418         return false;
 419 }
 420
 421 /**
 422  * i40e_aq_queue_shutdown
 423  * @hw: pointer to the hw struct
 424  * @unloading: is the driver unloading itself
 425  *
 426  * Tell the Firmware that we're shutting down the AdminQ and whether
 427  * or not the driver is unloading as well.
 428  **/
 429 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
 430                                              bool unloading)
 431 {
 432         struct i40e_aq_desc desc;
 433         struct i40e_aqc_queue_shutdown *cmd =
 434                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 435         enum i40e_status_code status;
 436
 437         i40e_fill_default_direct_cmd_desc(&desc,
 438                                           i40e_aqc_opc_queue_shutdown);
 439
 440         if (unloading)
 441                 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
 442         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 443
 444         return status;
 445 }
 446 #ifdef X722_SUPPORT
 447
 448 /**
 449  * i40e_aq_get_set_rss_lut
 450  * @hw: pointer to the hardware structure
 451  * @vsi_id: vsi fw index
 452  * @pf_lut: for PF table set true, for VSI table set false
 453  * @lut: pointer to the lut buffer provided by the caller
 454  * @lut_size: size of the lut buffer
 455  * @set: set true to set the table, false to get the table
 456  *
 457  * Internal function to get or set RSS look up table
 458  **/
 459 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 460                                                      u16 vsi_id, bool pf_lut,
 461                                                      u8 *lut, u16 lut_size,
 462                                                      bool set)
 463 {
 464         enum i40e_status_code status;
 465         struct i40e_aq_desc desc;
 466         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 467                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 468
 469         if (set)
 470                 i40e_fill_default_direct_cmd_desc(&desc,
 471                                                   i40e_aqc_opc_set_rss_lut);
 472         else
 473                 i40e_fill_default_direct_cmd_desc(&desc,
 474                                                   i40e_aqc_opc_get_rss_lut);
 475
 476         /* Indirect command */
 477         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 478         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 479
 480         cmd_resp->vsi_id =
 481                         CPU_TO_LE16((u16)((vsi_id <<
 482                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 483                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 484         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 485
 486         if (pf_lut)
 487                 cmd_resp->flags |= CPU_TO_LE16((u16)
 488                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 489                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 490                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 491         else
 492                 cmd_resp->flags |= CPU_TO_LE16((u16)
 493                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 494                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 495                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 496
 497         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 498
 499         return status;
 500 }
 501
 502 /**
 503  * i40e_aq_get_rss_lut
 504  * @hw: pointer to the hardware structure
 505  * @vsi_id: vsi fw index
 506  * @pf_lut: for PF table set true, for VSI table set false
 507  * @lut: pointer to the lut buffer provided by the caller
 508  * @lut_size: size of the lut buffer
 509  *
 510  * get the RSS lookup table, PF or VSI type
 511  **/
 512 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 513                                           bool pf_lut, u8 *lut, u16 lut_size)
 514 {
 515         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 516                                        false);
 517 }
 518
 519 /**
 520  * i40e_aq_set_rss_lut
 521  * @hw: pointer to the hardware structure
 522  * @vsi_id: vsi fw index
 523  * @pf_lut: for PF table set true, for VSI table set false
 524  * @lut: pointer to the lut buffer provided by the caller
 525  * @lut_size: size of the lut buffer
 526  *
 527  * set the RSS lookup table, PF or VSI type
 528  **/
 529 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 530                                           bool pf_lut, u8 *lut, u16 lut_size)
 531 {
 532         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
 533 }
 534
 535 /**
 536  * i40e_aq_get_set_rss_key
 537  * @hw: pointer to the hw struct
 538  * @vsi_id: vsi fw index
 539  * @key: pointer to key info struct
 540  * @set: set true to set the key, false to get the key
 541  *
 542  * get the RSS key per VSI
 543  **/
 544 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 545                                       u16 vsi_id,
 546                                       struct i40e_aqc_get_set_rss_key_data *key,
 547                                       bool set)
 548 {
 549         enum i40e_status_code status;
 550         struct i40e_aq_desc desc;
 551         struct i40e_aqc_get_set_rss_key *cmd_resp =
 552                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 553         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 554
 555         if (set)
 556                 i40e_fill_default_direct_cmd_desc(&desc,
 557                                                   i40e_aqc_opc_set_rss_key);
 558         else
 559                 i40e_fill_default_direct_cmd_desc(&desc,
 560                                                   i40e_aqc_opc_get_rss_key);
 561
 562         /* Indirect command */
 563         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 564         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 565
 566         cmd_resp->vsi_id =
 567                         CPU_TO_LE16((u16)((vsi_id <<
 568                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 569                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 570         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 571
 572         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 573
 574         return status;
 575 }
 576
 577 /**
 578  * i40e_aq_get_rss_key
 579  * @hw: pointer to the hw struct
 580  * @vsi_id: vsi fw index
 581  * @key: pointer to key info struct
 582  *
 583  **/
 584 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
 585                                       u16 vsi_id,
 586                                       struct i40e_aqc_get_set_rss_key_data *key)
 587 {
 588         return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
 589 }
 590
 591 /**
 592  * i40e_aq_set_rss_key
 593  * @hw: pointer to the hw struct
 594  * @vsi_id: vsi fw index
 595  * @key: pointer to key info struct
 596  *
 597  * set the RSS key per VSI
 598  **/
 599 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
 600                                       u16 vsi_id,
 601                                       struct i40e_aqc_get_set_rss_key_data *key)
 602 {
 603         return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
 604 }
 605 #endif /* X722_SUPPORT */
 606
 607 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 608  * hardware to a bit-field that can be used by SW to more easily determine the
 609  * packet type.
 610  *
 611  * Macros are used to shorten the table lines and make this table human
 612  * readable.
 613  *
 614  * We store the PTYPE in the top byte of the bit field - this is just so that
 615  * we can check that the table doesn't have a row missing, as the index into
 616  * the table should be the PTYPE.
 617  *
 618  * Typical work flow:
 619  *
 620  * IF NOT i40e_ptype_lookup[ptype].known
 621  * THEN
 622  *      Packet is unknown
 623  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 624  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 625  * ELSE
 626  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 627  * ENDIF
 628  */
 629
 630 /* macro to make the table lines short */
 631 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 632         {       PTYPE, \
 633                 1, \
 634                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 635                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 636                 I40E_RX_PTYPE_##OUTER_FRAG, \
 637                 I40E_RX_PTYPE_TUNNEL_##T, \
 638                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 639                 I40E_RX_PTYPE_##TEF, \
 640                 I40E_RX_PTYPE_INNER_PROT_##I, \
 641                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 642
 643 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 644                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 645
 646 /* shorter macros makes the table fit but are terse */
 647 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 648 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 649 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 650
 651 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 652 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 653         /* L2 Packet types */
 654         I40E_PTT_UNUSED_ENTRY(0),
 655         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 656         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 657         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 658         I40E_PTT_UNUSED_ENTRY(4),
 659         I40E_PTT_UNUSED_ENTRY(5),
 660         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 661         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 662         I40E_PTT_UNUSED_ENTRY(8),
 663         I40E_PTT_UNUSED_ENTRY(9),
 664         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 665         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 666         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 667         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 668         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 669         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 670         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 671         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 672         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 673         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 674         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 675         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 676
 677         /* Non Tunneled IPv4 */
 678         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 679         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 680         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 681         I40E_PTT_UNUSED_ENTRY(25),
 682         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 683         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 684         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 685
 686         /* IPv4 --> IPv4 */
 687         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 688         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 689         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 690         I40E_PTT_UNUSED_ENTRY(32),
 691         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 692         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 693         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 694
 695         /* IPv4 --> IPv6 */
 696         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 697         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 698         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 699         I40E_PTT_UNUSED_ENTRY(39),
 700         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 701         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 702         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 703
 704         /* IPv4 --> GRE/NAT */
 705         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 706
 707         /* IPv4 --> GRE/NAT --> IPv4 */
 708         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 709         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 710         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 711         I40E_PTT_UNUSED_ENTRY(47),
 712         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 713         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 714         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 715
 716         /* IPv4 --> GRE/NAT --> IPv6 */
 717         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 718         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 719         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 720         I40E_PTT_UNUSED_ENTRY(54),
 721         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 722         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 723         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 724
 725         /* IPv4 --> GRE/NAT --> MAC */
 726         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 727
 728         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 729         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 730         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 731         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 732         I40E_PTT_UNUSED_ENTRY(62),
 733         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 734         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 735         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 736
 737         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 738         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 739         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 740         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 741         I40E_PTT_UNUSED_ENTRY(69),
 742         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 743         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 744         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 745
 746         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 747         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 748
 749         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 750         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 751         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 752         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 753         I40E_PTT_UNUSED_ENTRY(77),
 754         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 755         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 756         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 757
 758         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 759         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 760         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 761         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 762         I40E_PTT_UNUSED_ENTRY(84),
 763         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 764         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 765         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 766
 767         /* Non Tunneled IPv6 */
 768         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 769         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 770         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY3),
 771         I40E_PTT_UNUSED_ENTRY(91),
 772         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 773         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 774         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 775
 776         /* IPv6 --> IPv4 */
 777         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 778         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 779         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 780         I40E_PTT_UNUSED_ENTRY(98),
 781         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 782         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 783         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 784
 785         /* IPv6 --> IPv6 */
 786         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 787         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 788         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 789         I40E_PTT_UNUSED_ENTRY(105),
 790         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 791         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 792         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 793
 794         /* IPv6 --> GRE/NAT */
 795         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 796
 797         /* IPv6 --> GRE/NAT -> IPv4 */
 798         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 799         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 800         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 801         I40E_PTT_UNUSED_ENTRY(113),
 802         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 803         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 804         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 805
 806         /* IPv6 --> GRE/NAT -> IPv6 */
 807         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 808         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 809         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 810         I40E_PTT_UNUSED_ENTRY(120),
 811         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 812         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 813         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 814
 815         /* IPv6 --> GRE/NAT -> MAC */
 816         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 817
 818         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 819         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 820         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 821         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 822         I40E_PTT_UNUSED_ENTRY(128),
 823         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 824         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 825         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 826
 827         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 828         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 829         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 830         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 831         I40E_PTT_UNUSED_ENTRY(135),
 832         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 833         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 834         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 835
 836         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 837         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 838
 839         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 840         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 841         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 842         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 843         I40E_PTT_UNUSED_ENTRY(143),
 844         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 845         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 846         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 847
 848         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 849         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 850         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 851         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 852         I40E_PTT_UNUSED_ENTRY(150),
 853         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 854         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 855         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 856
 857         /* unused entries */
 858         I40E_PTT_UNUSED_ENTRY(154),
 859         I40E_PTT_UNUSED_ENTRY(155),
 860         I40E_PTT_UNUSED_ENTRY(156),
 861         I40E_PTT_UNUSED_ENTRY(157),
 862         I40E_PTT_UNUSED_ENTRY(158),
 863         I40E_PTT_UNUSED_ENTRY(159),
 864
 865         I40E_PTT_UNUSED_ENTRY(160),
 866         I40E_PTT_UNUSED_ENTRY(161),
 867         I40E_PTT_UNUSED_ENTRY(162),
 868         I40E_PTT_UNUSED_ENTRY(163),
 869         I40E_PTT_UNUSED_ENTRY(164),
 870         I40E_PTT_UNUSED_ENTRY(165),
 871         I40E_PTT_UNUSED_ENTRY(166),
 872         I40E_PTT_UNUSED_ENTRY(167),
 873         I40E_PTT_UNUSED_ENTRY(168),
 874         I40E_PTT_UNUSED_ENTRY(169),
 875
 876         I40E_PTT_UNUSED_ENTRY(170),
 877         I40E_PTT_UNUSED_ENTRY(171),
 878         I40E_PTT_UNUSED_ENTRY(172),
 879         I40E_PTT_UNUSED_ENTRY(173),
 880         I40E_PTT_UNUSED_ENTRY(174),
 881         I40E_PTT_UNUSED_ENTRY(175),
 882         I40E_PTT_UNUSED_ENTRY(176),
 883         I40E_PTT_UNUSED_ENTRY(177),
 884         I40E_PTT_UNUSED_ENTRY(178),
 885         I40E_PTT_UNUSED_ENTRY(179),
 886
 887         I40E_PTT_UNUSED_ENTRY(180),
 888         I40E_PTT_UNUSED_ENTRY(181),
 889         I40E_PTT_UNUSED_ENTRY(182),
 890         I40E_PTT_UNUSED_ENTRY(183),
 891         I40E_PTT_UNUSED_ENTRY(184),
 892         I40E_PTT_UNUSED_ENTRY(185),
 893         I40E_PTT_UNUSED_ENTRY(186),
 894         I40E_PTT_UNUSED_ENTRY(187),
 895         I40E_PTT_UNUSED_ENTRY(188),
 896         I40E_PTT_UNUSED_ENTRY(189),
 897
 898         I40E_PTT_UNUSED_ENTRY(190),
 899         I40E_PTT_UNUSED_ENTRY(191),
 900         I40E_PTT_UNUSED_ENTRY(192),
 901         I40E_PTT_UNUSED_ENTRY(193),
 902         I40E_PTT_UNUSED_ENTRY(194),
 903         I40E_PTT_UNUSED_ENTRY(195),
 904         I40E_PTT_UNUSED_ENTRY(196),
 905         I40E_PTT_UNUSED_ENTRY(197),
 906         I40E_PTT_UNUSED_ENTRY(198),
 907         I40E_PTT_UNUSED_ENTRY(199),
 908
 909         I40E_PTT_UNUSED_ENTRY(200),
 910         I40E_PTT_UNUSED_ENTRY(201),
 911         I40E_PTT_UNUSED_ENTRY(202),
 912         I40E_PTT_UNUSED_ENTRY(203),
 913         I40E_PTT_UNUSED_ENTRY(204),
 914         I40E_PTT_UNUSED_ENTRY(205),
 915         I40E_PTT_UNUSED_ENTRY(206),
 916         I40E_PTT_UNUSED_ENTRY(207),
 917         I40E_PTT_UNUSED_ENTRY(208),
 918         I40E_PTT_UNUSED_ENTRY(209),
 919
 920         I40E_PTT_UNUSED_ENTRY(210),
 921         I40E_PTT_UNUSED_ENTRY(211),
 922         I40E_PTT_UNUSED_ENTRY(212),
 923         I40E_PTT_UNUSED_ENTRY(213),
 924         I40E_PTT_UNUSED_ENTRY(214),
 925         I40E_PTT_UNUSED_ENTRY(215),
 926         I40E_PTT_UNUSED_ENTRY(216),
 927         I40E_PTT_UNUSED_ENTRY(217),
 928         I40E_PTT_UNUSED_ENTRY(218),
 929         I40E_PTT_UNUSED_ENTRY(219),
 930
 931         I40E_PTT_UNUSED_ENTRY(220),
 932         I40E_PTT_UNUSED_ENTRY(221),
 933         I40E_PTT_UNUSED_ENTRY(222),
 934         I40E_PTT_UNUSED_ENTRY(223),
 935         I40E_PTT_UNUSED_ENTRY(224),
 936         I40E_PTT_UNUSED_ENTRY(225),
 937         I40E_PTT_UNUSED_ENTRY(226),
 938         I40E_PTT_UNUSED_ENTRY(227),
 939         I40E_PTT_UNUSED_ENTRY(228),
 940         I40E_PTT_UNUSED_ENTRY(229),
 941
 942         I40E_PTT_UNUSED_ENTRY(230),
 943         I40E_PTT_UNUSED_ENTRY(231),
 944         I40E_PTT_UNUSED_ENTRY(232),
 945         I40E_PTT_UNUSED_ENTRY(233),
 946         I40E_PTT_UNUSED_ENTRY(234),
 947         I40E_PTT_UNUSED_ENTRY(235),
 948         I40E_PTT_UNUSED_ENTRY(236),
 949         I40E_PTT_UNUSED_ENTRY(237),
 950         I40E_PTT_UNUSED_ENTRY(238),
 951         I40E_PTT_UNUSED_ENTRY(239),
 952
 953         I40E_PTT_UNUSED_ENTRY(240),
 954         I40E_PTT_UNUSED_ENTRY(241),
 955         I40E_PTT_UNUSED_ENTRY(242),
 956         I40E_PTT_UNUSED_ENTRY(243),
 957         I40E_PTT_UNUSED_ENTRY(244),
 958         I40E_PTT_UNUSED_ENTRY(245),
 959         I40E_PTT_UNUSED_ENTRY(246),
 960         I40E_PTT_UNUSED_ENTRY(247),
 961         I40E_PTT_UNUSED_ENTRY(248),
 962         I40E_PTT_UNUSED_ENTRY(249),
 963
 964         I40E_PTT_UNUSED_ENTRY(250),
 965         I40E_PTT_UNUSED_ENTRY(251),
 966         I40E_PTT_UNUSED_ENTRY(252),
 967         I40E_PTT_UNUSED_ENTRY(253),
 968         I40E_PTT_UNUSED_ENTRY(254),
 969         I40E_PTT_UNUSED_ENTRY(255)
 970 };
 971
 972
 973 /**
 974  * i40e_validate_mac_addr - Validate unicast MAC address
 975  * @mac_addr: pointer to MAC address
 976  *
 977  * Tests a MAC address to ensure it is a valid Individual Address
 978  **/
 979 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
 980 {
 981         enum i40e_status_code status = I40E_SUCCESS;
 982
 983         DEBUGFUNC("i40e_validate_mac_addr");
 984
 985         /* Broadcast addresses ARE multicast addresses
 986          * Make sure it is not a multicast address
 987          * Reject the zero address
 988          */
 989         if (I40E_IS_MULTICAST(mac_addr) ||
 990             (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
 991               mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
 992                 status = I40E_ERR_INVALID_MAC_ADDR;
 993
 994         return status;
 995 }
 996 #ifdef PF_DRIVER
 997
 998 /**
 999  * i40e_init_shared_code - Initialize the shared code
1000  * @hw: pointer to hardware structure
1001  *
1002  * This assigns the MAC type and PHY code and inits the NVM.
1003  * Does not touch the hardware. This function must be called prior to any
1004  * other function in the shared code. The i40e_hw structure should be
1005  * memset to 0 prior to calling this function.  The following fields in
1006  * hw structure should be filled in prior to calling this function:
1007  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1008  * subsystem_vendor_id, and revision_id
1009  **/
1010 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
1011 {
1012         enum i40e_status_code status = I40E_SUCCESS;
1013         u32 port, ari, func_rid;
1014
1015         DEBUGFUNC("i40e_init_shared_code");
1016
1017         i40e_set_mac_type(hw);
1018
1019         switch (hw->mac.type) {
1020         case I40E_MAC_XL710:
1021 #ifdef X722_SUPPORT
1022         case I40E_MAC_X722:
1023 #endif
1024                 break;
1025         default:
1026                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1027         }
1028
1029         hw->phy.get_link_info = true;
1030
1031         /* Determine port number and PF number*/
1032         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1033                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1034         hw->port = (u8)port;
1035         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1036                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1037         func_rid = rd32(hw, I40E_PF_FUNC_RID);
1038         if (ari)
1039                 hw->pf_id = (u8)(func_rid & 0xff);
1040         else
1041                 hw->pf_id = (u8)(func_rid & 0x7);
1042
1043 #ifdef X722_SUPPORT
1044         if (hw->mac.type == I40E_MAC_X722)
1045                 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
1046
1047 #endif
1048         status = i40e_init_nvm(hw);
1049         return status;
1050 }
1051
1052 /**
1053  * i40e_aq_mac_address_read - Retrieve the MAC addresses
1054  * @hw: pointer to the hw struct
1055  * @flags: a return indicator of what addresses were added to the addr store
1056  * @addrs: the requestor's mac addr store
1057  * @cmd_details: pointer to command details structure or NULL
1058  **/
1059 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1060                                    u16 *flags,
1061                                    struct i40e_aqc_mac_address_read_data *addrs,
1062                                    struct i40e_asq_cmd_details *cmd_details)
1063 {
1064         struct i40e_aq_desc desc;
1065         struct i40e_aqc_mac_address_read *cmd_data =
1066                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1067         enum i40e_status_code status;
1068
1069         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1070         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1071
1072         status = i40e_asq_send_command(hw, &desc, addrs,
1073                                        sizeof(*addrs), cmd_details);
1074         *flags = LE16_TO_CPU(cmd_data->command_flags);
1075
1076         return status;
1077 }
1078
1079 /**
1080  * i40e_aq_mac_address_write - Change the MAC addresses
1081  * @hw: pointer to the hw struct
1082  * @flags: indicates which MAC to be written
1083  * @mac_addr: address to write
1084  * @cmd_details: pointer to command details structure or NULL
1085  **/
1086 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1087                                     u16 flags, u8 *mac_addr,
1088                                     struct i40e_asq_cmd_details *cmd_details)
1089 {
1090         struct i40e_aq_desc desc;
1091         struct i40e_aqc_mac_address_write *cmd_data =
1092                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1093         enum i40e_status_code status;
1094
1095         i40e_fill_default_direct_cmd_desc(&desc,
1096                                           i40e_aqc_opc_mac_address_write);
1097         cmd_data->command_flags = CPU_TO_LE16(flags);
1098         cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1099         cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1100                                         ((u32)mac_addr[3] << 16) |
1101                                         ((u32)mac_addr[4] << 8) |
1102                                         mac_addr[5]);
1103
1104         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1105
1106         return status;
1107 }
1108
1109 /**
1110  * i40e_get_mac_addr - get MAC address
1111  * @hw: pointer to the HW structure
1112  * @mac_addr: pointer to MAC address
1113  *
1114  * Reads the adapter's MAC address from register
1115  **/
1116 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1117 {
1118         struct i40e_aqc_mac_address_read_data addrs;
1119         enum i40e_status_code status;
1120         u16 flags = 0;
1121
1122         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1123
1124         if (flags & I40E_AQC_LAN_ADDR_VALID)
1125                 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
1126
1127         return status;
1128 }
1129
1130 /**
1131  * i40e_get_port_mac_addr - get Port MAC address
1132  * @hw: pointer to the HW structure
1133  * @mac_addr: pointer to Port MAC address
1134  *
1135  * Reads the adapter's Port MAC address
1136  **/
1137 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1138 {
1139         struct i40e_aqc_mac_address_read_data addrs;
1140         enum i40e_status_code status;
1141         u16 flags = 0;
1142
1143         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1144         if (status)
1145                 return status;
1146
1147         if (flags & I40E_AQC_PORT_ADDR_VALID)
1148                 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
1149         else
1150                 status = I40E_ERR_INVALID_MAC_ADDR;
1151
1152         return status;
1153 }
1154
1155 /**
1156  * i40e_pre_tx_queue_cfg - pre tx queue configure
1157  * @hw: pointer to the HW structure
1158  * @queue: target pf queue index
1159  * @enable: state change request
1160  *
1161  * Handles hw requirement to indicate intention to enable
1162  * or disable target queue.
1163  **/
1164 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1165 {
1166         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1167         u32 reg_block = 0;
1168         u32 reg_val;
1169
1170         if (abs_queue_idx >= 128) {
1171                 reg_block = abs_queue_idx / 128;
1172                 abs_queue_idx %= 128;
1173         }
1174
1175         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1176         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1177         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1178
1179         if (enable)
1180                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1181         else
1182                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1183
1184         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1185 }
1186
1187 /**
1188  *  i40e_read_pba_string - Reads part number string from EEPROM
1189  *  @hw: pointer to hardware structure
1190  *  @pba_num: stores the part number string from the EEPROM
1191  *  @pba_num_size: part number string buffer length
1192  *
1193  *  Reads the part number string from the EEPROM.
1194  **/
1195 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1196                                             u32 pba_num_size)
1197 {
1198         enum i40e_status_code status = I40E_SUCCESS;
1199         u16 pba_word = 0;
1200         u16 pba_size = 0;
1201         u16 pba_ptr = 0;
1202         u16 i = 0;
1203
1204         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1205         if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1206                 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1207                 return status;
1208         }
1209
1210         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1211         if (status != I40E_SUCCESS) {
1212                 DEBUGOUT("Failed to read PBA Block pointer.\n");
1213                 return status;
1214         }
1215
1216         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1217         if (status != I40E_SUCCESS) {
1218                 DEBUGOUT("Failed to read PBA Block size.\n");
1219                 return status;
1220         }
1221
1222         /* Subtract one to get PBA word count (PBA Size word is included in
1223          * total size)
1224          */
1225         pba_size--;
1226         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1227                 DEBUGOUT("Buffer to small for PBA data.\n");
1228                 return I40E_ERR_PARAM;
1229         }
1230
1231         for (i = 0; i < pba_size; i++) {
1232                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1233                 if (status != I40E_SUCCESS) {
1234                         DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1235                         return status;
1236                 }
1237
1238                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1239                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1240         }
1241         pba_num[(pba_size * 2)] = '\0';
1242
1243         return status;
1244 }
1245
1246 /**
1247  * i40e_get_media_type - Gets media type
1248  * @hw: pointer to the hardware structure
1249  **/
1250 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1251 {
1252         enum i40e_media_type media;
1253
1254         switch (hw->phy.link_info.phy_type) {
1255         case I40E_PHY_TYPE_10GBASE_SR:
1256         case I40E_PHY_TYPE_10GBASE_LR:
1257         case I40E_PHY_TYPE_1000BASE_SX:
1258         case I40E_PHY_TYPE_1000BASE_LX:
1259         case I40E_PHY_TYPE_40GBASE_SR4:
1260         case I40E_PHY_TYPE_40GBASE_LR4:
1261                 media = I40E_MEDIA_TYPE_FIBER;
1262                 break;
1263         case I40E_PHY_TYPE_100BASE_TX:
1264         case I40E_PHY_TYPE_1000BASE_T:
1265         case I40E_PHY_TYPE_10GBASE_T:
1266                 media = I40E_MEDIA_TYPE_BASET;
1267                 break;
1268         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1269         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1270         case I40E_PHY_TYPE_10GBASE_CR1:
1271         case I40E_PHY_TYPE_40GBASE_CR4:
1272         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1273         case I40E_PHY_TYPE_40GBASE_AOC:
1274         case I40E_PHY_TYPE_10GBASE_AOC:
1275                 media = I40E_MEDIA_TYPE_DA;
1276                 break;
1277         case I40E_PHY_TYPE_1000BASE_KX:
1278         case I40E_PHY_TYPE_10GBASE_KX4:
1279         case I40E_PHY_TYPE_10GBASE_KR:
1280         case I40E_PHY_TYPE_40GBASE_KR4:
1281         case I40E_PHY_TYPE_20GBASE_KR2:
1282                 media = I40E_MEDIA_TYPE_BACKPLANE;
1283                 break;
1284         case I40E_PHY_TYPE_SGMII:
1285         case I40E_PHY_TYPE_XAUI:
1286         case I40E_PHY_TYPE_XFI:
1287         case I40E_PHY_TYPE_XLAUI:
1288         case I40E_PHY_TYPE_XLPPI:
1289         default:
1290                 media = I40E_MEDIA_TYPE_UNKNOWN;
1291                 break;
1292         }
1293
1294         return media;
1295 }
1296
1297 #define I40E_PF_RESET_WAIT_COUNT        200
1298 /**
1299  * i40e_pf_reset - Reset the PF
1300  * @hw: pointer to the hardware structure
1301  *
1302  * Assuming someone else has triggered a global reset,
1303  * assure the global reset is complete and then reset the PF
1304  **/
1305 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1306 {
1307         u32 cnt = 0;
1308         u32 cnt1 = 0;
1309         u32 reg = 0;
1310         u32 grst_del;
1311
1312         /* Poll for Global Reset steady state in case of recent GRST.
1313          * The grst delay value is in 100ms units, and we'll wait a
1314          * couple counts longer to be sure we don't just miss the end.
1315          */
1316         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1317                         I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1318                         I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1319 #ifdef I40E_ESS_SUPPORT
1320         /* It can take upto 15 secs for GRST steady state */
1321         grst_del = grst_del * 20; /* bump it to 16 secs max to be safe */
1322 #endif
1323         for (cnt = 0; cnt < grst_del + 10; cnt++) {
1324                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1325                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1326                         break;
1327                 i40e_msec_delay(100);
1328         }
1329         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1330                 DEBUGOUT("Global reset polling failed to complete.\n");
1331                 return I40E_ERR_RESET_FAILED;
1332         }
1333
1334         /* Now Wait for the FW to be ready */
1335         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1336                 reg = rd32(hw, I40E_GLNVM_ULD);
1337                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1338                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1339                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1340                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1341                         DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1342                         break;
1343                 }
1344                 i40e_msec_delay(10);
1345         }
1346         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1347                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1348                 DEBUGOUT("wait for FW Reset complete timedout\n");
1349                 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1350                 return I40E_ERR_RESET_FAILED;
1351         }
1352
1353         /* If there was a Global Reset in progress when we got here,
1354          * we don't need to do the PF Reset
1355          */
1356         if (!cnt) {
1357                 reg = rd32(hw, I40E_PFGEN_CTRL);
1358                 wr32(hw, I40E_PFGEN_CTRL,
1359                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1360                 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1361                         reg = rd32(hw, I40E_PFGEN_CTRL);
1362                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1363                                 break;
1364                         i40e_msec_delay(1);
1365                 }
1366                 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1367                         DEBUGOUT("PF reset polling failed to complete.\n");
1368                         return I40E_ERR_RESET_FAILED;
1369                 }
1370         }
1371
1372         i40e_clear_pxe_mode(hw);
1373
1374
1375         return I40E_SUCCESS;
1376 }
1377
1378 /**
1379  * i40e_clear_hw - clear out any left over hw state
1380  * @hw: pointer to the hw struct
1381  *
1382  * Clear queues and interrupts, typically called at init time,
1383  * but after the capabilities have been found so we know how many
1384  * queues and msix vectors have been allocated.
1385  **/
1386 void i40e_clear_hw(struct i40e_hw *hw)
1387 {
1388         u32 num_queues, base_queue;
1389         u32 num_pf_int;
1390         u32 num_vf_int;
1391         u32 num_vfs;
1392         u32 i, j;
1393         u32 val;
1394         u32 eol = 0x7ff;
1395
1396         /* get number of interrupts, queues, and vfs */
1397         val = rd32(hw, I40E_GLPCI_CNF2);
1398         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1399                         I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1400         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1401                         I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1402
1403         val = rd32(hw, I40E_PFLAN_QALLOC);
1404         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1405                         I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1406         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1407                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1408         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1409                 num_queues = (j - base_queue) + 1;
1410         else
1411                 num_queues = 0;
1412
1413         val = rd32(hw, I40E_PF_VT_PFALLOC);
1414         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1415                         I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1416         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1417                         I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1418         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1419                 num_vfs = (j - i) + 1;
1420         else
1421                 num_vfs = 0;
1422
1423         /* stop all the interrupts */
1424         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1425         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1426         for (i = 0; i < num_pf_int - 2; i++)
1427                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1428
1429         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1430         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1431         wr32(hw, I40E_PFINT_LNKLST0, val);
1432         for (i = 0; i < num_pf_int - 2; i++)
1433                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1434         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1435         for (i = 0; i < num_vfs; i++)
1436                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1437         for (i = 0; i < num_vf_int - 2; i++)
1438                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1439
1440         /* warn the HW of the coming Tx disables */
1441         for (i = 0; i < num_queues; i++) {
1442                 u32 abs_queue_idx = base_queue + i;
1443                 u32 reg_block = 0;
1444
1445                 if (abs_queue_idx >= 128) {
1446                         reg_block = abs_queue_idx / 128;
1447                         abs_queue_idx %= 128;
1448                 }
1449
1450                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1451                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1452                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1453                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1454
1455                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1456         }
1457         i40e_usec_delay(400);
1458
1459         /* stop all the queues */
1460         for (i = 0; i < num_queues; i++) {
1461                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1462                 wr32(hw, I40E_QTX_ENA(i), 0);
1463                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1464                 wr32(hw, I40E_QRX_ENA(i), 0);
1465         }
1466
1467         /* short wait for all queue disables to settle */
1468         i40e_usec_delay(50);
1469 }
1470
1471 /**
1472  * i40e_clear_pxe_mode - clear pxe operations mode
1473  * @hw: pointer to the hw struct
1474  *
1475  * Make sure all PXE mode settings are cleared, including things
1476  * like descriptor fetch/write-back mode.
1477  **/
1478 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1479 {
1480         if (i40e_check_asq_alive(hw))
1481                 i40e_aq_clear_pxe_mode(hw, NULL);
1482 }
1483
1484 /**
1485  * i40e_led_is_mine - helper to find matching led
1486  * @hw: pointer to the hw struct
1487  * @idx: index into GPIO registers
1488  *
1489  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1490  */
1491 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1492 {
1493         u32 gpio_val = 0;
1494         u32 port;
1495
1496         if (!hw->func_caps.led[idx])
1497                 return 0;
1498
1499         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1500         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1501                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1502
1503         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1504          * if it is not our port then ignore
1505          */
1506         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1507             (port != hw->port))
1508                 return 0;
1509
1510         return gpio_val;
1511 }
1512
1513 #define I40E_COMBINED_ACTIVITY 0xA
1514 #define I40E_FILTER_ACTIVITY 0xE
1515 #define I40E_LINK_ACTIVITY 0xC
1516 #define I40E_MAC_ACTIVITY 0xD
1517 #define I40E_LED0 22
1518
1519 /**
1520  * i40e_led_get - return current on/off mode
1521  * @hw: pointer to the hw struct
1522  *
1523  * The value returned is the 'mode' field as defined in the
1524  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1525  * values are variations of possible behaviors relating to
1526  * blink, link, and wire.
1527  **/
1528 u32 i40e_led_get(struct i40e_hw *hw)
1529 {
1530         u32 current_mode = 0;
1531         u32 mode = 0;
1532         int i;
1533
1534         /* as per the documentation GPIO 22-29 are the LED
1535          * GPIO pins named LED0..LED7
1536          */
1537         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1538                 u32 gpio_val = i40e_led_is_mine(hw, i);
1539
1540                 if (!gpio_val)
1541                         continue;
1542
1543                 /* ignore gpio LED src mode entries related to the activity LEDs */
1544                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1545                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1546                 switch (current_mode) {
1547                 case I40E_COMBINED_ACTIVITY:
1548                 case I40E_FILTER_ACTIVITY:
1549                 case I40E_MAC_ACTIVITY:
1550                         continue;
1551                 default:
1552                         break;
1553                 }
1554
1555                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1556                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1557                 break;
1558         }
1559
1560         return mode;
1561 }
1562
1563 /**
1564  * i40e_led_set - set new on/off mode
1565  * @hw: pointer to the hw struct
1566  * @mode: 0=off, 0xf=on (else see manual for mode details)
1567  * @blink: true if the LED should blink when on, false if steady
1568  *
1569  * if this function is used to turn on the blink it should
1570  * be used to disable the blink when restoring the original state.
1571  **/
1572 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1573 {
1574         u32 current_mode = 0;
1575         int i;
1576
1577         if (mode & 0xfffffff0)
1578                 DEBUGOUT1("invalid mode passed in %X\n", mode);
1579
1580         /* as per the documentation GPIO 22-29 are the LED
1581          * GPIO pins named LED0..LED7
1582          */
1583         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1584                 u32 gpio_val = i40e_led_is_mine(hw, i);
1585
1586                 if (!gpio_val)
1587                         continue;
1588
1589                 /* ignore gpio LED src mode entries related to the activity LEDs */
1590                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1591                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1592                 switch (current_mode) {
1593                 case I40E_COMBINED_ACTIVITY:
1594                 case I40E_FILTER_ACTIVITY:
1595                 case I40E_MAC_ACTIVITY:
1596                         continue;
1597                 default:
1598                         break;
1599                 }
1600
1601                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1602                 /* this & is a bit of paranoia, but serves as a range check */
1603                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1604                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1605
1606                 if (mode == I40E_LINK_ACTIVITY)
1607                         blink = false;
1608
1609                 if (blink)
1610                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1611                 else
1612                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1613
1614                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1615                 break;
1616         }
1617 }
1618
1619 /* Admin command wrappers */
1620
1621 /**
1622  * i40e_aq_get_phy_capabilities
1623  * @hw: pointer to the hw struct
1624  * @abilities: structure for PHY capabilities to be filled
1625  * @qualified_modules: report Qualified Modules
1626  * @report_init: report init capabilities (active are default)
1627  * @cmd_details: pointer to command details structure or NULL
1628  *
1629  * Returns the various PHY abilities supported on the Port.
1630  **/
1631 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1632                         bool qualified_modules, bool report_init,
1633                         struct i40e_aq_get_phy_abilities_resp *abilities,
1634                         struct i40e_asq_cmd_details *cmd_details)
1635 {
1636         struct i40e_aq_desc desc;
1637         enum i40e_status_code status;
1638         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1639
1640         if (!abilities)
1641                 return I40E_ERR_PARAM;
1642
1643         i40e_fill_default_direct_cmd_desc(&desc,
1644                                           i40e_aqc_opc_get_phy_abilities);
1645
1646         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1647         if (abilities_size > I40E_AQ_LARGE_BUF)
1648                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1649
1650         if (qualified_modules)
1651                 desc.params.external.param0 |=
1652                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1653
1654         if (report_init)
1655                 desc.params.external.param0 |=
1656                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1657
1658         status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1659                                     cmd_details);
1660
1661         if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1662                 status = I40E_ERR_UNKNOWN_PHY;
1663
1664         if (report_init)
1665                 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1666
1667         return status;
1668 }
1669
1670 /**
1671  * i40e_aq_set_phy_config
1672  * @hw: pointer to the hw struct
1673  * @config: structure with PHY configuration to be set
1674  * @cmd_details: pointer to command details structure or NULL
1675  *
1676  * Set the various PHY configuration parameters
1677  * supported on the Port.One or more of the Set PHY config parameters may be
1678  * ignored in an MFP mode as the PF may not have the privilege to set some
1679  * of the PHY Config parameters. This status will be indicated by the
1680  * command response.
1681  **/
1682 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1683                                 struct i40e_aq_set_phy_config *config,
1684                                 struct i40e_asq_cmd_details *cmd_details)
1685 {
1686         struct i40e_aq_desc desc;
1687         struct i40e_aq_set_phy_config *cmd =
1688                 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1689         enum i40e_status_code status;
1690
1691         if (!config)
1692                 return I40E_ERR_PARAM;
1693
1694         i40e_fill_default_direct_cmd_desc(&desc,
1695                                           i40e_aqc_opc_set_phy_config);
1696
1697         *cmd = *config;
1698
1699         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1700
1701         return status;
1702 }
1703
1704 /**
1705  * i40e_set_fc
1706  * @hw: pointer to the hw struct
1707  *
1708  * Set the requested flow control mode using set_phy_config.
1709  **/
1710 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1711                                   bool atomic_restart)
1712 {
1713         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1714         struct i40e_aq_get_phy_abilities_resp abilities;
1715         struct i40e_aq_set_phy_config config;
1716         enum i40e_status_code status;
1717         u8 pause_mask = 0x0;
1718
1719         *aq_failures = 0x0;
1720
1721         switch (fc_mode) {
1722         case I40E_FC_FULL:
1723                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1724                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1725                 break;
1726         case I40E_FC_RX_PAUSE:
1727                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1728                 break;
1729         case I40E_FC_TX_PAUSE:
1730                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1731                 break;
1732         default:
1733                 break;
1734         }
1735
1736         /* Get the current phy config */
1737         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1738                                               NULL);
1739         if (status) {
1740                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1741                 return status;
1742         }
1743
1744         memset(&config, 0, sizeof(config));
1745         /* clear the old pause settings */
1746         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1747                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1748         /* set the new abilities */
1749         config.abilities |= pause_mask;
1750         /* If the abilities have changed, then set the new config */
1751         if (config.abilities != abilities.abilities) {
1752                 /* Auto restart link so settings take effect */
1753                 if (atomic_restart)
1754                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1755                 /* Copy over all the old settings */
1756                 config.phy_type = abilities.phy_type;
1757                 config.link_speed = abilities.link_speed;
1758                 config.eee_capability = abilities.eee_capability;
1759                 config.eeer = abilities.eeer_val;
1760                 config.low_power_ctrl = abilities.d3_lpan;
1761                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1762
1763                 if (status)
1764                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1765         }
1766         /* Update the link info */
1767         status = i40e_update_link_info(hw);
1768         if (status) {
1769                 /* Wait a little bit (on 40G cards it sometimes takes a really
1770                  * long time for link to come back from the atomic reset)
1771                  * and try once more
1772                  */
1773                 i40e_msec_delay(1000);
1774                 status = i40e_update_link_info(hw);
1775         }
1776         if (status)
1777                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1778
1779         return status;
1780 }
1781
1782 /**
1783  * i40e_aq_set_mac_config
1784  * @hw: pointer to the hw struct
1785  * @max_frame_size: Maximum Frame Size to be supported by the port
1786  * @crc_en: Tell HW to append a CRC to outgoing frames
1787  * @pacing: Pacing configurations
1788  * @cmd_details: pointer to command details structure or NULL
1789  *
1790  * Configure MAC settings for frame size, jumbo frame support and the
1791  * addition of a CRC by the hardware.
1792  **/
1793 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1794                                 u16 max_frame_size,
1795                                 bool crc_en, u16 pacing,
1796                                 struct i40e_asq_cmd_details *cmd_details)
1797 {
1798         struct i40e_aq_desc desc;
1799         struct i40e_aq_set_mac_config *cmd =
1800                 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1801         enum i40e_status_code status;
1802
1803         if (max_frame_size == 0)
1804                 return I40E_ERR_PARAM;
1805
1806         i40e_fill_default_direct_cmd_desc(&desc,
1807                                           i40e_aqc_opc_set_mac_config);
1808
1809         cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1810         cmd->params = ((u8)pacing & 0x0F) << 3;
1811         if (crc_en)
1812                 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1813
1814         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1815
1816         return status;
1817 }
1818
1819 /**
1820  * i40e_aq_clear_pxe_mode
1821  * @hw: pointer to the hw struct
1822  * @cmd_details: pointer to command details structure or NULL
1823  *
1824  * Tell the firmware that the driver is taking over from PXE
1825  **/
1826 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1827                         struct i40e_asq_cmd_details *cmd_details)
1828 {
1829         enum i40e_status_code status;
1830         struct i40e_aq_desc desc;
1831         struct i40e_aqc_clear_pxe *cmd =
1832                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1833
1834         i40e_fill_default_direct_cmd_desc(&desc,
1835                                           i40e_aqc_opc_clear_pxe_mode);
1836
1837         cmd->rx_cnt = 0x2;
1838
1839         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1840
1841         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1842
1843         return status;
1844 }
1845
1846 /**
1847  * i40e_aq_set_link_restart_an
1848  * @hw: pointer to the hw struct
1849  * @enable_link: if true: enable link, if false: disable link
1850  * @cmd_details: pointer to command details structure or NULL
1851  *
1852  * Sets up the link and restarts the Auto-Negotiation over the link.
1853  **/
1854 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1855                 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1856 {
1857         struct i40e_aq_desc desc;
1858         struct i40e_aqc_set_link_restart_an *cmd =
1859                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1860         enum i40e_status_code status;
1861
1862         i40e_fill_default_direct_cmd_desc(&desc,
1863                                           i40e_aqc_opc_set_link_restart_an);
1864
1865         cmd->command = I40E_AQ_PHY_RESTART_AN;
1866         if (enable_link)
1867                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1868         else
1869                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1870
1871         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1872
1873         return status;
1874 }
1875
1876 /**
1877  * i40e_aq_get_link_info
1878  * @hw: pointer to the hw struct
1879  * @enable_lse: enable/disable LinkStatusEvent reporting
1880  * @link: pointer to link status structure - optional
1881  * @cmd_details: pointer to command details structure or NULL
1882  *
1883  * Returns the link status of the adapter.
1884  **/
1885 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1886                                 bool enable_lse, struct i40e_link_status *link,
1887                                 struct i40e_asq_cmd_details *cmd_details)
1888 {
1889         struct i40e_aq_desc desc;
1890         struct i40e_aqc_get_link_status *resp =
1891                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1892         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1893         enum i40e_status_code status;
1894         bool tx_pause, rx_pause;
1895         u16 command_flags;
1896
1897         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1898
1899         if (enable_lse)
1900                 command_flags = I40E_AQ_LSE_ENABLE;
1901         else
1902                 command_flags = I40E_AQ_LSE_DISABLE;
1903         resp->command_flags = CPU_TO_LE16(command_flags);
1904
1905         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1906
1907         if (status != I40E_SUCCESS)
1908                 goto aq_get_link_info_exit;
1909
1910         /* save off old link status information */
1911         i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1912                     sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1913
1914         /* update link status */
1915         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1916         hw->phy.media_type = i40e_get_media_type(hw);
1917         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1918         hw_link_info->link_info = resp->link_info;
1919         hw_link_info->an_info = resp->an_info;
1920         hw_link_info->ext_info = resp->ext_info;
1921         hw_link_info->loopback = resp->loopback;
1922         hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1923         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1924
1925         /* update fc info */
1926         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1927         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1928         if (tx_pause & rx_pause)
1929                 hw->fc.current_mode = I40E_FC_FULL;
1930         else if (tx_pause)
1931                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1932         else if (rx_pause)
1933                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1934         else
1935                 hw->fc.current_mode = I40E_FC_NONE;
1936
1937         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1938                 hw_link_info->crc_enable = true;
1939         else
1940                 hw_link_info->crc_enable = false;
1941
1942         if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1943                 hw_link_info->lse_enable = true;
1944         else
1945                 hw_link_info->lse_enable = false;
1946
1947         if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1948              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1949                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1950
1951         /* save link status information */
1952         if (link)
1953                 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1954                             I40E_NONDMA_TO_NONDMA);
1955
1956         /* flag cleared so helper functions don't call AQ again */
1957         hw->phy.get_link_info = false;
1958
1959 aq_get_link_info_exit:
1960         return status;
1961 }
1962
1963 /**
1964  * i40e_aq_set_phy_int_mask
1965  * @hw: pointer to the hw struct
1966  * @mask: interrupt mask to be set
1967  * @cmd_details: pointer to command details structure or NULL
1968  *
1969  * Set link interrupt mask.
1970  **/
1971 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1972                                 u16 mask,
1973                                 struct i40e_asq_cmd_details *cmd_details)
1974 {
1975         struct i40e_aq_desc desc;
1976         struct i40e_aqc_set_phy_int_mask *cmd =
1977                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1978         enum i40e_status_code status;
1979
1980         i40e_fill_default_direct_cmd_desc(&desc,
1981                                           i40e_aqc_opc_set_phy_int_mask);
1982
1983         cmd->event_mask = CPU_TO_LE16(mask);
1984
1985         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1986
1987         return status;
1988 }
1989
1990 /**
1991  * i40e_aq_get_local_advt_reg
1992  * @hw: pointer to the hw struct
1993  * @advt_reg: local AN advertisement register value
1994  * @cmd_details: pointer to command details structure or NULL
1995  *
1996  * Get the Local AN advertisement register value.
1997  **/
1998 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
1999                                 u64 *advt_reg,
2000                                 struct i40e_asq_cmd_details *cmd_details)
2001 {
2002         struct i40e_aq_desc desc;
2003         struct i40e_aqc_an_advt_reg *resp =
2004                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2005         enum i40e_status_code status;
2006
2007         i40e_fill_default_direct_cmd_desc(&desc,
2008                                           i40e_aqc_opc_get_local_advt_reg);
2009
2010         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2011
2012         if (status != I40E_SUCCESS)
2013                 goto aq_get_local_advt_reg_exit;
2014
2015         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2016         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2017
2018 aq_get_local_advt_reg_exit:
2019         return status;
2020 }
2021
2022 /**
2023  * i40e_aq_set_local_advt_reg
2024  * @hw: pointer to the hw struct
2025  * @advt_reg: local AN advertisement register value
2026  * @cmd_details: pointer to command details structure or NULL
2027  *
2028  * Get the Local AN advertisement register value.
2029  **/
2030 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2031                                 u64 advt_reg,
2032                                 struct i40e_asq_cmd_details *cmd_details)
2033 {
2034         struct i40e_aq_desc desc;
2035         struct i40e_aqc_an_advt_reg *cmd =
2036                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2037         enum i40e_status_code status;
2038
2039         i40e_fill_default_direct_cmd_desc(&desc,
2040                                           i40e_aqc_opc_get_local_advt_reg);
2041
2042         cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2043         cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2044
2045         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2046
2047         return status;
2048 }
2049
2050 /**
2051  * i40e_aq_get_partner_advt
2052  * @hw: pointer to the hw struct
2053  * @advt_reg: AN partner advertisement register value
2054  * @cmd_details: pointer to command details structure or NULL
2055  *
2056  * Get the link partner AN advertisement register value.
2057  **/
2058 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2059                                 u64 *advt_reg,
2060                                 struct i40e_asq_cmd_details *cmd_details)
2061 {
2062         struct i40e_aq_desc desc;
2063         struct i40e_aqc_an_advt_reg *resp =
2064                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2065         enum i40e_status_code status;
2066
2067         i40e_fill_default_direct_cmd_desc(&desc,
2068                                           i40e_aqc_opc_get_partner_advt);
2069
2070         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2071
2072         if (status != I40E_SUCCESS)
2073                 goto aq_get_partner_advt_exit;
2074
2075         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2076         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2077
2078 aq_get_partner_advt_exit:
2079         return status;
2080 }
2081
2082 /**
2083  * i40e_aq_set_lb_modes
2084  * @hw: pointer to the hw struct
2085  * @lb_modes: loopback mode to be set
2086  * @cmd_details: pointer to command details structure or NULL
2087  *
2088  * Sets loopback modes.
2089  **/
2090 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2091                                 u16 lb_modes,
2092                                 struct i40e_asq_cmd_details *cmd_details)
2093 {
2094         struct i40e_aq_desc desc;
2095         struct i40e_aqc_set_lb_mode *cmd =
2096                 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2097         enum i40e_status_code status;
2098
2099         i40e_fill_default_direct_cmd_desc(&desc,
2100                                           i40e_aqc_opc_set_lb_modes);
2101
2102         cmd->lb_mode = CPU_TO_LE16(lb_modes);
2103
2104         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2105
2106         return status;
2107 }
2108
2109 /**
2110  * i40e_aq_set_phy_debug
2111  * @hw: pointer to the hw struct
2112  * @cmd_flags: debug command flags
2113  * @cmd_details: pointer to command details structure or NULL
2114  *
2115  * Reset the external PHY.
2116  **/
2117 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2118                                 struct i40e_asq_cmd_details *cmd_details)
2119 {
2120         struct i40e_aq_desc desc;
2121         struct i40e_aqc_set_phy_debug *cmd =
2122                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2123         enum i40e_status_code status;
2124
2125         i40e_fill_default_direct_cmd_desc(&desc,
2126                                           i40e_aqc_opc_set_phy_debug);
2127
2128         cmd->command_flags = cmd_flags;
2129
2130         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2131
2132         return status;
2133 }
2134
2135 /**
2136  * i40e_aq_add_vsi
2137  * @hw: pointer to the hw struct
2138  * @vsi_ctx: pointer to a vsi context struct
2139  * @cmd_details: pointer to command details structure or NULL
2140  *
2141  * Add a VSI context to the hardware.
2142 **/
2143 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2144                                 struct i40e_vsi_context *vsi_ctx,
2145                                 struct i40e_asq_cmd_details *cmd_details)
2146 {
2147         struct i40e_aq_desc desc;
2148         struct i40e_aqc_add_get_update_vsi *cmd =
2149                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2150         struct i40e_aqc_add_get_update_vsi_completion *resp =
2151                 (struct i40e_aqc_add_get_update_vsi_completion *)
2152                 &desc.params.raw;
2153         enum i40e_status_code status;
2154
2155         i40e_fill_default_direct_cmd_desc(&desc,
2156                                           i40e_aqc_opc_add_vsi);
2157
2158         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2159         cmd->connection_type = vsi_ctx->connection_type;
2160         cmd->vf_id = vsi_ctx->vf_num;
2161         cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2162
2163         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2164
2165         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2166                                     sizeof(vsi_ctx->info), cmd_details);
2167
2168         if (status != I40E_SUCCESS)
2169                 goto aq_add_vsi_exit;
2170
2171         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2172         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2173         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2174         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2175
2176 aq_add_vsi_exit:
2177         return status;
2178 }
2179
2180 /**
2181  * i40e_aq_set_default_vsi
2182  * @hw: pointer to the hw struct
2183  * @seid: vsi number
2184  * @cmd_details: pointer to command details structure or NULL
2185  **/
2186 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2187                                 u16 seid,
2188                                 struct i40e_asq_cmd_details *cmd_details)
2189 {
2190         struct i40e_aq_desc desc;
2191         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2192                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2193                 &desc.params.raw;
2194         enum i40e_status_code status;
2195
2196         i40e_fill_default_direct_cmd_desc(&desc,
2197                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2198
2199         cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2200         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2201         cmd->seid = CPU_TO_LE16(seid);
2202
2203         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2204
2205         return status;
2206 }
2207
2208 /**
2209  * i40e_aq_set_vsi_unicast_promiscuous
2210  * @hw: pointer to the hw struct
2211  * @seid: vsi number
2212  * @set: set unicast promiscuous enable/disable
2213  * @cmd_details: pointer to command details structure or NULL
2214  **/
2215 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2216                                 u16 seid, bool set,
2217                                 struct i40e_asq_cmd_details *cmd_details)
2218 {
2219         struct i40e_aq_desc desc;
2220         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2221                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2222         enum i40e_status_code status;
2223         u16 flags = 0;
2224
2225         i40e_fill_default_direct_cmd_desc(&desc,
2226                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2227
2228         if (set)
2229                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2230
2231         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2232
2233         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2234
2235         cmd->seid = CPU_TO_LE16(seid);
2236         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2237
2238         return status;
2239 }
2240
2241 /**
2242  * i40e_aq_set_vsi_multicast_promiscuous
2243  * @hw: pointer to the hw struct
2244  * @seid: vsi number
2245  * @set: set multicast promiscuous enable/disable
2246  * @cmd_details: pointer to command details structure or NULL
2247  **/
2248 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2249                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2250 {
2251         struct i40e_aq_desc desc;
2252         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2253                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2254         enum i40e_status_code status;
2255         u16 flags = 0;
2256
2257         i40e_fill_default_direct_cmd_desc(&desc,
2258                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2259
2260         if (set)
2261                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2262
2263         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2264
2265         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2266
2267         cmd->seid = CPU_TO_LE16(seid);
2268         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2269
2270         return status;
2271 }
2272
2273 /**
2274  * i40e_aq_set_vsi_mc_promisc_on_vlan
2275  * @hw: pointer to the hw struct
2276  * @seid: vsi number
2277  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2278  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2279  * @cmd_details: pointer to command details structure or NULL
2280  **/
2281 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2282                                 u16 seid, bool enable, u16 vid,
2283                                 struct i40e_asq_cmd_details *cmd_details)
2284 {
2285         struct i40e_aq_desc desc;
2286         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2287                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2288         enum i40e_status_code status;
2289         u16 flags = 0;
2290
2291         i40e_fill_default_direct_cmd_desc(&desc,
2292                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2293
2294         if (enable)
2295                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2296
2297         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2298         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2299         cmd->seid = CPU_TO_LE16(seid);
2300         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2301
2302         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2303
2304         return status;
2305 }
2306
2307 /**
2308  * i40e_aq_set_vsi_uc_promisc_on_vlan
2309  * @hw: pointer to the hw struct
2310  * @seid: vsi number
2311  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2312  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2313  * @cmd_details: pointer to command details structure or NULL
2314  **/
2315 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2316                                 u16 seid, bool enable, u16 vid,
2317                                 struct i40e_asq_cmd_details *cmd_details)
2318 {
2319         struct i40e_aq_desc desc;
2320         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2321                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2322         enum i40e_status_code status;
2323         u16 flags = 0;
2324
2325         i40e_fill_default_direct_cmd_desc(&desc,
2326                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2327
2328         if (enable)
2329                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2330
2331         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2332         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2333         cmd->seid = CPU_TO_LE16(seid);
2334         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2335
2336         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2337
2338         return status;
2339 }
2340
2341 /**
2342  * i40e_aq_set_vsi_broadcast
2343  * @hw: pointer to the hw struct
2344  * @seid: vsi number
2345  * @set_filter: true to set filter, false to clear filter
2346  * @cmd_details: pointer to command details structure or NULL
2347  *
2348  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2349  **/
2350 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2351                                 u16 seid, bool set_filter,
2352                                 struct i40e_asq_cmd_details *cmd_details)
2353 {
2354         struct i40e_aq_desc desc;
2355         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2356                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2357         enum i40e_status_code status;
2358
2359         i40e_fill_default_direct_cmd_desc(&desc,
2360                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2361
2362         if (set_filter)
2363                 cmd->promiscuous_flags
2364                             |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2365         else
2366                 cmd->promiscuous_flags
2367                             &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2368
2369         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2370         cmd->seid = CPU_TO_LE16(seid);
2371         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2372
2373         return status;
2374 }
2375
2376 /**
2377  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2378  * @hw: pointer to the hw struct
2379  * @seid: vsi number
2380  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2381  * @cmd_details: pointer to command details structure or NULL
2382  **/
2383 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2384                                 u16 seid, bool enable,
2385                                 struct i40e_asq_cmd_details *cmd_details)
2386 {
2387         struct i40e_aq_desc desc;
2388         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2389                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2390         enum i40e_status_code status;
2391         u16 flags = 0;
2392
2393         i40e_fill_default_direct_cmd_desc(&desc,
2394                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2395         if (enable)
2396                 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2397
2398         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2399         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2400         cmd->seid = CPU_TO_LE16(seid);
2401
2402         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2403
2404         return status;
2405 }
2406
2407 /**
2408  * i40e_get_vsi_params - get VSI configuration info
2409  * @hw: pointer to the hw struct
2410  * @vsi_ctx: pointer to a vsi context struct
2411  * @cmd_details: pointer to command details structure or NULL
2412  **/
2413 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2414                                 struct i40e_vsi_context *vsi_ctx,
2415                                 struct i40e_asq_cmd_details *cmd_details)
2416 {
2417         struct i40e_aq_desc desc;
2418         struct i40e_aqc_add_get_update_vsi *cmd =
2419                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2420         struct i40e_aqc_add_get_update_vsi_completion *resp =
2421                 (struct i40e_aqc_add_get_update_vsi_completion *)
2422                 &desc.params.raw;
2423         enum i40e_status_code status;
2424
2425         UNREFERENCED_1PARAMETER(cmd_details);
2426         i40e_fill_default_direct_cmd_desc(&desc,
2427                                           i40e_aqc_opc_get_vsi_parameters);
2428
2429         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2430
2431         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2432
2433         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2434                                     sizeof(vsi_ctx->info), NULL);
2435
2436         if (status != I40E_SUCCESS)
2437                 goto aq_get_vsi_params_exit;
2438
2439         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2440         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2441         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2442         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2443
2444 aq_get_vsi_params_exit:
2445         return status;
2446 }
2447
2448 /**
2449  * i40e_aq_update_vsi_params
2450  * @hw: pointer to the hw struct
2451  * @vsi_ctx: pointer to a vsi context struct
2452  * @cmd_details: pointer to command details structure or NULL
2453  *
2454  * Update a VSI context.
2455  **/
2456 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2457                                 struct i40e_vsi_context *vsi_ctx,
2458                                 struct i40e_asq_cmd_details *cmd_details)
2459 {
2460         struct i40e_aq_desc desc;
2461         struct i40e_aqc_add_get_update_vsi *cmd =
2462                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2463         enum i40e_status_code status;
2464
2465         i40e_fill_default_direct_cmd_desc(&desc,
2466                                           i40e_aqc_opc_update_vsi_parameters);
2467         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2468
2469         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2470
2471         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2472                                     sizeof(vsi_ctx->info), cmd_details);
2473
2474         return status;
2475 }
2476
2477 /**
2478  * i40e_aq_get_switch_config
2479  * @hw: pointer to the hardware structure
2480  * @buf: pointer to the result buffer
2481  * @buf_size: length of input buffer
2482  * @start_seid: seid to start for the report, 0 == beginning
2483  * @cmd_details: pointer to command details structure or NULL
2484  *
2485  * Fill the buf with switch configuration returned from AdminQ command
2486  **/
2487 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2488                                 struct i40e_aqc_get_switch_config_resp *buf,
2489                                 u16 buf_size, u16 *start_seid,
2490                                 struct i40e_asq_cmd_details *cmd_details)
2491 {
2492         struct i40e_aq_desc desc;
2493         struct i40e_aqc_switch_seid *scfg =
2494                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2495         enum i40e_status_code status;
2496
2497         i40e_fill_default_direct_cmd_desc(&desc,
2498                                           i40e_aqc_opc_get_switch_config);
2499         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2500         if (buf_size > I40E_AQ_LARGE_BUF)
2501                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2502         scfg->seid = CPU_TO_LE16(*start_seid);
2503
2504         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2505         *start_seid = LE16_TO_CPU(scfg->seid);
2506
2507         return status;
2508 }
2509
2510 /**
2511  * i40e_aq_get_firmware_version
2512  * @hw: pointer to the hw struct
2513  * @fw_major_version: firmware major version
2514  * @fw_minor_version: firmware minor version
2515  * @fw_build: firmware build number
2516  * @api_major_version: major queue version
2517  * @api_minor_version: minor queue version
2518  * @cmd_details: pointer to command details structure or NULL
2519  *
2520  * Get the firmware version from the admin queue commands
2521  **/
2522 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2523                                 u16 *fw_major_version, u16 *fw_minor_version,
2524                                 u32 *fw_build,
2525                                 u16 *api_major_version, u16 *api_minor_version,
2526                                 struct i40e_asq_cmd_details *cmd_details)
2527 {
2528         struct i40e_aq_desc desc;
2529         struct i40e_aqc_get_version *resp =
2530                 (struct i40e_aqc_get_version *)&desc.params.raw;
2531         enum i40e_status_code status;
2532
2533         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2534
2535         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2536
2537         if (status == I40E_SUCCESS) {
2538                 if (fw_major_version != NULL)
2539                         *fw_major_version = LE16_TO_CPU(resp->fw_major);
2540                 if (fw_minor_version != NULL)
2541                         *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2542                 if (fw_build != NULL)
2543                         *fw_build = LE32_TO_CPU(resp->fw_build);
2544                 if (api_major_version != NULL)
2545                         *api_major_version = LE16_TO_CPU(resp->api_major);
2546                 if (api_minor_version != NULL)
2547                         *api_minor_version = LE16_TO_CPU(resp->api_minor);
2548
2549                 /* A workaround to fix the API version in SW */
2550                 if (api_major_version && api_minor_version &&
2551                     fw_major_version && fw_minor_version &&
2552                     ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2553                     (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2554                      (*fw_major_version > 4)))
2555                         *api_minor_version = 2;
2556         }
2557
2558         return status;
2559 }
2560
2561 /**
2562  * i40e_aq_send_driver_version
2563  * @hw: pointer to the hw struct
2564  * @dv: driver's major, minor version
2565  * @cmd_details: pointer to command details structure or NULL
2566  *
2567  * Send the driver version to the firmware
2568  **/
2569 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2570                                 struct i40e_driver_version *dv,
2571                                 struct i40e_asq_cmd_details *cmd_details)
2572 {
2573         struct i40e_aq_desc desc;
2574         struct i40e_aqc_driver_version *cmd =
2575                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2576         enum i40e_status_code status;
2577         u16 len;
2578
2579         if (dv == NULL)
2580                 return I40E_ERR_PARAM;
2581
2582         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2583
2584         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2585         cmd->driver_major_ver = dv->major_version;
2586         cmd->driver_minor_ver = dv->minor_version;
2587         cmd->driver_build_ver = dv->build_version;
2588         cmd->driver_subbuild_ver = dv->subbuild_version;
2589
2590         len = 0;
2591         while (len < sizeof(dv->driver_string) &&
2592                (dv->driver_string[len] < 0x80) &&
2593                dv->driver_string[len])
2594                 len++;
2595         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2596                                        len, cmd_details);
2597
2598         return status;
2599 }
2600
2601 /**
2602  * i40e_get_link_status - get status of the HW network link
2603  * @hw: pointer to the hw struct
2604  * @link_up: pointer to bool (true/false = linkup/linkdown)
2605  *
2606  * Variable link_up true if link is up, false if link is down.
2607  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2608  *
2609  * Side effect: LinkStatusEvent reporting becomes enabled
2610  **/
2611 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2612 {
2613         enum i40e_status_code status = I40E_SUCCESS;
2614
2615         if (hw->phy.get_link_info) {
2616                 status = i40e_update_link_info(hw);
2617
2618                 if (status != I40E_SUCCESS)
2619                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2620                                    status);
2621         }
2622
2623         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2624
2625         return status;
2626 }
2627
2628 /**
2629  * i40e_updatelink_status - update status of the HW network link
2630  * @hw: pointer to the hw struct
2631  **/
2632 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2633 {
2634         struct i40e_aq_get_phy_abilities_resp abilities;
2635         enum i40e_status_code status = I40E_SUCCESS;
2636
2637         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2638         if (status)
2639                 return status;
2640
2641         if (hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) {
2642                 status = i40e_aq_get_phy_capabilities(hw, false, false,
2643                                                       &abilities, NULL);
2644                 if (status)
2645                         return status;
2646
2647                 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2648                         sizeof(hw->phy.link_info.module_type));
2649         }
2650         return status;
2651 }
2652
2653
2654 /**
2655  * i40e_get_link_speed
2656  * @hw: pointer to the hw struct
2657  *
2658  * Returns the link speed of the adapter.
2659  **/
2660 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2661 {
2662         enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2663         enum i40e_status_code status = I40E_SUCCESS;
2664
2665         if (hw->phy.get_link_info) {
2666                 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2667
2668                 if (status != I40E_SUCCESS)
2669                         goto i40e_link_speed_exit;
2670         }
2671
2672         speed = hw->phy.link_info.link_speed;
2673
2674 i40e_link_speed_exit:
2675         return speed;
2676 }
2677
2678 /**
2679  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2680  * @hw: pointer to the hw struct
2681  * @uplink_seid: the MAC or other gizmo SEID
2682  * @downlink_seid: the VSI SEID
2683  * @enabled_tc: bitmap of TCs to be enabled
2684  * @default_port: true for default port VSI, false for control port
2685  * @veb_seid: pointer to where to put the resulting VEB SEID
2686  * @enable_stats: true to turn on VEB stats
2687  * @cmd_details: pointer to command details structure or NULL
2688  *
2689  * This asks the FW to add a VEB between the uplink and downlink
2690  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2691  **/
2692 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2693                                 u16 downlink_seid, u8 enabled_tc,
2694                                 bool default_port, u16 *veb_seid,
2695                                 bool enable_stats,
2696                                 struct i40e_asq_cmd_details *cmd_details)
2697 {
2698         struct i40e_aq_desc desc;
2699         struct i40e_aqc_add_veb *cmd =
2700                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2701         struct i40e_aqc_add_veb_completion *resp =
2702                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2703         enum i40e_status_code status;
2704         u16 veb_flags = 0;
2705
2706         /* SEIDs need to either both be set or both be 0 for floating VEB */
2707         if (!!uplink_seid != !!downlink_seid)
2708                 return I40E_ERR_PARAM;
2709
2710         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2711
2712         cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2713         cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2714         cmd->enable_tcs = enabled_tc;
2715         if (!uplink_seid)
2716                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2717         if (default_port)
2718                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2719         else
2720                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2721
2722         /* reverse logic here: set the bitflag to disable the stats */
2723         if (!enable_stats)
2724                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2725
2726         cmd->veb_flags = CPU_TO_LE16(veb_flags);
2727
2728         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2729
2730         if (!status && veb_seid)
2731                 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2732
2733         return status;
2734 }
2735
2736 /**
2737  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2738  * @hw: pointer to the hw struct
2739  * @veb_seid: the SEID of the VEB to query
2740  * @switch_id: the uplink switch id
2741  * @floating: set to true if the VEB is floating
2742  * @statistic_index: index of the stats counter block for this VEB
2743  * @vebs_used: number of VEB's used by function
2744  * @vebs_free: total VEB's not reserved by any function
2745  * @cmd_details: pointer to command details structure or NULL
2746  *
2747  * This retrieves the parameters for a particular VEB, specified by
2748  * uplink_seid, and returns them to the caller.
2749  **/
2750 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2751                                 u16 veb_seid, u16 *switch_id,
2752                                 bool *floating, u16 *statistic_index,
2753                                 u16 *vebs_used, u16 *vebs_free,
2754                                 struct i40e_asq_cmd_details *cmd_details)
2755 {
2756         struct i40e_aq_desc desc;
2757         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2758                 (struct i40e_aqc_get_veb_parameters_completion *)
2759                 &desc.params.raw;
2760         enum i40e_status_code status;
2761
2762         if (veb_seid == 0)
2763                 return I40E_ERR_PARAM;
2764
2765         i40e_fill_default_direct_cmd_desc(&desc,
2766                                           i40e_aqc_opc_get_veb_parameters);
2767         cmd_resp->seid = CPU_TO_LE16(veb_seid);
2768
2769         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2770         if (status)
2771                 goto get_veb_exit;
2772
2773         if (switch_id)
2774                 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2775         if (statistic_index)
2776                 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2777         if (vebs_used)
2778                 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2779         if (vebs_free)
2780                 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2781         if (floating) {
2782                 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2783                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2784                         *floating = true;
2785                 else
2786                         *floating = false;
2787         }
2788
2789 get_veb_exit:
2790         return status;
2791 }
2792
2793 /**
2794  * i40e_aq_add_macvlan
2795  * @hw: pointer to the hw struct
2796  * @seid: VSI for the mac address
2797  * @mv_list: list of macvlans to be added
2798  * @count: length of the list
2799  * @cmd_details: pointer to command details structure or NULL
2800  *
2801  * Add MAC/VLAN addresses to the HW filtering
2802  **/
2803 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2804                         struct i40e_aqc_add_macvlan_element_data *mv_list,
2805                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2806 {
2807         struct i40e_aq_desc desc;
2808         struct i40e_aqc_macvlan *cmd =
2809                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2810         enum i40e_status_code status;
2811         u16 buf_size;
2812         int i;
2813
2814         if (count == 0 || !mv_list || !hw)
2815                 return I40E_ERR_PARAM;
2816
2817         buf_size = count * sizeof(*mv_list);
2818
2819         /* prep the rest of the request */
2820         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2821         cmd->num_addresses = CPU_TO_LE16(count);
2822         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2823         cmd->seid[1] = 0;
2824         cmd->seid[2] = 0;
2825
2826         for (i = 0; i < count; i++)
2827                 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
2828                         mv_list[i].flags |=
2829                             CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2830
2831         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2832         if (buf_size > I40E_AQ_LARGE_BUF)
2833                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2834
2835         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2836                                        cmd_details);
2837
2838         return status;
2839 }
2840
2841 /**
2842  * i40e_aq_remove_macvlan
2843  * @hw: pointer to the hw struct
2844  * @seid: VSI for the mac address
2845  * @mv_list: list of macvlans to be removed
2846  * @count: length of the list
2847  * @cmd_details: pointer to command details structure or NULL
2848  *
2849  * Remove MAC/VLAN addresses from the HW filtering
2850  **/
2851 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2852                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
2853                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2854 {
2855         struct i40e_aq_desc desc;
2856         struct i40e_aqc_macvlan *cmd =
2857                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2858         enum i40e_status_code status;
2859         u16 buf_size;
2860
2861         if (count == 0 || !mv_list || !hw)
2862                 return I40E_ERR_PARAM;
2863
2864         buf_size = count * sizeof(*mv_list);
2865
2866         /* prep the rest of the request */
2867         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2868         cmd->num_addresses = CPU_TO_LE16(count);
2869         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2870         cmd->seid[1] = 0;
2871         cmd->seid[2] = 0;
2872
2873         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2874         if (buf_size > I40E_AQ_LARGE_BUF)
2875                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2876
2877         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2878                                        cmd_details);
2879
2880         return status;
2881 }
2882
2883 /**
2884  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
2885  * @hw: pointer to the hw struct
2886  * @opcode: AQ opcode for add or delete mirror rule
2887  * @sw_seid: Switch SEID (to which rule refers)
2888  * @rule_type: Rule Type (ingress/egress/VLAN)
2889  * @id: Destination VSI SEID or Rule ID
2890  * @count: length of the list
2891  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2892  * @cmd_details: pointer to command details structure or NULL
2893  * @rule_id: Rule ID returned from FW
2894  * @rule_used: Number of rules used in internal switch
2895  * @rule_free: Number of rules free in internal switch
2896  *
2897  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
2898  * VEBs/VEPA elements only
2899  **/
2900 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
2901                         u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
2902                         u16 count, __le16 *mr_list,
2903                         struct i40e_asq_cmd_details *cmd_details,
2904                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
2905 {
2906         struct i40e_aq_desc desc;
2907         struct i40e_aqc_add_delete_mirror_rule *cmd =
2908                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
2909         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
2910         (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
2911         enum i40e_status_code status;
2912         u16 buf_size;
2913
2914         buf_size = count * sizeof(*mr_list);
2915
2916         /* prep the rest of the request */
2917         i40e_fill_default_direct_cmd_desc(&desc, opcode);
2918         cmd->seid = CPU_TO_LE16(sw_seid);
2919         cmd->rule_type = CPU_TO_LE16(rule_type &
2920                                      I40E_AQC_MIRROR_RULE_TYPE_MASK);
2921         cmd->num_entries = CPU_TO_LE16(count);
2922         /* Dest VSI for add, rule_id for delete */
2923         cmd->destination = CPU_TO_LE16(id);
2924         if (mr_list) {
2925                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
2926                                                 I40E_AQ_FLAG_RD));
2927                 if (buf_size > I40E_AQ_LARGE_BUF)
2928                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2929         }
2930
2931         status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
2932                                        cmd_details);
2933         if (status == I40E_SUCCESS ||
2934             hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
2935                 if (rule_id)
2936                         *rule_id = LE16_TO_CPU(resp->rule_id);
2937                 if (rules_used)
2938                         *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
2939                 if (rules_free)
2940                         *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
2941         }
2942         return status;
2943 }
2944
2945 /**
2946  * i40e_aq_add_mirrorrule - add a mirror rule
2947  * @hw: pointer to the hw struct
2948  * @sw_seid: Switch SEID (to which rule refers)
2949  * @rule_type: Rule Type (ingress/egress/VLAN)
2950  * @dest_vsi: SEID of VSI to which packets will be mirrored
2951  * @count: length of the list
2952  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2953  * @cmd_details: pointer to command details structure or NULL
2954  * @rule_id: Rule ID returned from FW
2955  * @rule_used: Number of rules used in internal switch
2956  * @rule_free: Number of rules free in internal switch
2957  *
2958  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
2959  **/
2960 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2961                         u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
2962                         struct i40e_asq_cmd_details *cmd_details,
2963                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
2964 {
2965         if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
2966             rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
2967                 if (count == 0 || !mr_list)
2968                         return I40E_ERR_PARAM;
2969         }
2970
2971         return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
2972                                   rule_type, dest_vsi, count, mr_list,
2973                                   cmd_details, rule_id, rules_used, rules_free);
2974 }
2975
2976 /**
2977  * i40e_aq_delete_mirrorrule - delete a mirror rule
2978  * @hw: pointer to the hw struct
2979  * @sw_seid: Switch SEID (to which rule refers)
2980  * @rule_type: Rule Type (ingress/egress/VLAN)
2981  * @count: length of the list
2982  * @rule_id: Rule ID that is returned in the receive desc as part of
2983  *              add_mirrorrule.
2984  * @mr_list: list of mirrored VLAN IDs to be removed
2985  * @cmd_details: pointer to command details structure or NULL
2986  * @rule_used: Number of rules used in internal switch
2987  * @rule_free: Number of rules free in internal switch
2988  *
2989  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
2990  **/
2991 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2992                         u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
2993                         struct i40e_asq_cmd_details *cmd_details,
2994                         u16 *rules_used, u16 *rules_free)
2995 {
2996         /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
2997         if (rule_type != I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
2998                 if (!rule_id)
2999                         return I40E_ERR_PARAM;
3000         } else {
3001                 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3002                  * mirroring. For other rule_type, count and rule_type should
3003                  * not matter.
3004                  */
3005                 if (count == 0 || !mr_list)
3006                         return I40E_ERR_PARAM;
3007         }
3008
3009         return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3010                                   rule_type, rule_id, count, mr_list,
3011                                   cmd_details, NULL, rules_used, rules_free);
3012 }
3013
3014 /**
3015  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3016  * @hw: pointer to the hw struct
3017  * @seid: VSI for the vlan filters
3018  * @v_list: list of vlan filters to be added
3019  * @count: length of the list
3020  * @cmd_details: pointer to command details structure or NULL
3021  **/
3022 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3023                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3024                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3025 {
3026         struct i40e_aq_desc desc;
3027         struct i40e_aqc_macvlan *cmd =
3028                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3029         enum i40e_status_code status;
3030         u16 buf_size;
3031
3032         if (count == 0 || !v_list || !hw)
3033                 return I40E_ERR_PARAM;
3034
3035         buf_size = count * sizeof(*v_list);
3036
3037         /* prep the rest of the request */
3038         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3039         cmd->num_addresses = CPU_TO_LE16(count);
3040         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3041         cmd->seid[1] = 0;
3042         cmd->seid[2] = 0;
3043
3044         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3045         if (buf_size > I40E_AQ_LARGE_BUF)
3046                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3047
3048         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3049                                        cmd_details);
3050
3051         return status;
3052 }
3053
3054 /**
3055  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3056  * @hw: pointer to the hw struct
3057  * @seid: VSI for the vlan filters
3058  * @v_list: list of macvlans to be removed
3059  * @count: length of the list
3060  * @cmd_details: pointer to command details structure or NULL
3061  **/
3062 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3063                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3064                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3065 {
3066         struct i40e_aq_desc desc;
3067         struct i40e_aqc_macvlan *cmd =
3068                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3069         enum i40e_status_code status;
3070         u16 buf_size;
3071
3072         if (count == 0 || !v_list || !hw)
3073                 return I40E_ERR_PARAM;
3074
3075         buf_size = count * sizeof(*v_list);
3076
3077         /* prep the rest of the request */
3078         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3079         cmd->num_addresses = CPU_TO_LE16(count);
3080         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3081         cmd->seid[1] = 0;
3082         cmd->seid[2] = 0;
3083
3084         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3085         if (buf_size > I40E_AQ_LARGE_BUF)
3086                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3087
3088         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3089                                        cmd_details);
3090
3091         return status;
3092 }
3093
3094 /**
3095  * i40e_aq_send_msg_to_vf
3096  * @hw: pointer to the hardware structure
3097  * @vfid: vf id to send msg
3098  * @v_opcode: opcodes for VF-PF communication
3099  * @v_retval: return error code
3100  * @msg: pointer to the msg buffer
3101  * @msglen: msg length
3102  * @cmd_details: pointer to command details
3103  *
3104  * send msg to vf
3105  **/
3106 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3107                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3108                                 struct i40e_asq_cmd_details *cmd_details)
3109 {
3110         struct i40e_aq_desc desc;
3111         struct i40e_aqc_pf_vf_message *cmd =
3112                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3113         enum i40e_status_code status;
3114
3115         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3116         cmd->id = CPU_TO_LE32(vfid);
3117         desc.cookie_high = CPU_TO_LE32(v_opcode);
3118         desc.cookie_low = CPU_TO_LE32(v_retval);
3119         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3120         if (msglen) {
3121                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3122                                                 I40E_AQ_FLAG_RD));
3123                 if (msglen > I40E_AQ_LARGE_BUF)
3124                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3125                 desc.datalen = CPU_TO_LE16(msglen);
3126         }
3127         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3128
3129         return status;
3130 }
3131
3132 /**
3133  * i40e_aq_debug_read_register
3134  * @hw: pointer to the hw struct
3135  * @reg_addr: register address
3136  * @reg_val: register value
3137  * @cmd_details: pointer to command details structure or NULL
3138  *
3139  * Read the register using the admin queue commands
3140  **/
3141 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3142                                 u32 reg_addr, u64 *reg_val,
3143                                 struct i40e_asq_cmd_details *cmd_details)
3144 {
3145         struct i40e_aq_desc desc;
3146         struct i40e_aqc_debug_reg_read_write *cmd_resp =
3147                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3148         enum i40e_status_code status;
3149
3150         if (reg_val == NULL)
3151                 return I40E_ERR_PARAM;
3152
3153         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3154
3155         cmd_resp->address = CPU_TO_LE32(reg_addr);
3156
3157         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3158
3159         if (status == I40E_SUCCESS) {
3160                 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3161                            (u64)LE32_TO_CPU(cmd_resp->value_low);
3162         }
3163
3164         return status;
3165 }
3166
3167 /**
3168  * i40e_aq_debug_write_register
3169  * @hw: pointer to the hw struct
3170  * @reg_addr: register address
3171  * @reg_val: register value
3172  * @cmd_details: pointer to command details structure or NULL
3173  *
3174  * Write to a register using the admin queue commands
3175  **/
3176 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3177                                 u32 reg_addr, u64 reg_val,
3178                                 struct i40e_asq_cmd_details *cmd_details)
3179 {
3180         struct i40e_aq_desc desc;
3181         struct i40e_aqc_debug_reg_read_write *cmd =
3182                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3183         enum i40e_status_code status;
3184
3185         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3186
3187         cmd->address = CPU_TO_LE32(reg_addr);
3188         cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3189         cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3190
3191         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3192
3193         return status;
3194 }
3195
3196 /**
3197  * i40e_aq_get_hmc_resource_profile
3198  * @hw: pointer to the hw struct
3199  * @profile: type of profile the HMC is to be set as
3200  * @pe_vf_enabled_count: the number of PE enabled VFs the system has
3201  * @cmd_details: pointer to command details structure or NULL
3202  *
3203  * query the HMC profile of the device.
3204  **/
3205 enum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw,
3206                                 enum i40e_aq_hmc_profile *profile,
3207                                 u8 *pe_vf_enabled_count,
3208                                 struct i40e_asq_cmd_details *cmd_details)
3209 {
3210         struct i40e_aq_desc desc;
3211         struct i40e_aq_get_set_hmc_resource_profile *resp =
3212                 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
3213         enum i40e_status_code status;
3214
3215         i40e_fill_default_direct_cmd_desc(&desc,
3216                                 i40e_aqc_opc_query_hmc_resource_profile);
3217         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3218
3219         *profile = (enum i40e_aq_hmc_profile)(resp->pm_profile &
3220                    I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK);
3221         *pe_vf_enabled_count = resp->pe_vf_enabled &
3222                                I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK;
3223
3224         return status;
3225 }
3226
3227 /**
3228  * i40e_aq_set_hmc_resource_profile
3229  * @hw: pointer to the hw struct
3230  * @profile: type of profile the HMC is to be set as
3231  * @pe_vf_enabled_count: the number of PE enabled VFs the system has
3232  * @cmd_details: pointer to command details structure or NULL
3233  *
3234  * set the HMC profile of the device.
3235  **/
3236 enum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
3237                                 enum i40e_aq_hmc_profile profile,
3238                                 u8 pe_vf_enabled_count,
3239                                 struct i40e_asq_cmd_details *cmd_details)
3240 {
3241         struct i40e_aq_desc desc;
3242         struct i40e_aq_get_set_hmc_resource_profile *cmd =
3243                 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
3244         enum i40e_status_code status;
3245
3246         i40e_fill_default_direct_cmd_desc(&desc,
3247                                         i40e_aqc_opc_set_hmc_resource_profile);
3248
3249         cmd->pm_profile = (u8)profile;
3250         cmd->pe_vf_enabled = pe_vf_enabled_count;
3251
3252         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3253
3254         return status;
3255 }
3256
3257 /**
3258  * i40e_aq_request_resource
3259  * @hw: pointer to the hw struct
3260  * @resource: resource id
3261  * @access: access type
3262  * @sdp_number: resource number
3263  * @timeout: the maximum time in ms that the driver may hold the resource
3264  * @cmd_details: pointer to command details structure or NULL
3265  *
3266  * requests common resource using the admin queue commands
3267  **/
3268 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3269                                 enum i40e_aq_resources_ids resource,
3270                                 enum i40e_aq_resource_access_type access,
3271                                 u8 sdp_number, u64 *timeout,
3272                                 struct i40e_asq_cmd_details *cmd_details)
3273 {
3274         struct i40e_aq_desc desc;
3275         struct i40e_aqc_request_resource *cmd_resp =
3276                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3277         enum i40e_status_code status;
3278
3279         DEBUGFUNC("i40e_aq_request_resource");
3280
3281         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3282
3283         cmd_resp->resource_id = CPU_TO_LE16(resource);
3284         cmd_resp->access_type = CPU_TO_LE16(access);
3285         cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3286
3287         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3288         /* The completion specifies the maximum time in ms that the driver
3289          * may hold the resource in the Timeout field.
3290          * If the resource is held by someone else, the command completes with
3291          * busy return value and the timeout field indicates the maximum time
3292          * the current owner of the resource has to free it.
3293          */
3294         if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3295                 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3296
3297         return status;
3298 }
3299
3300 /**
3301  * i40e_aq_release_resource
3302  * @hw: pointer to the hw struct
3303  * @resource: resource id
3304  * @sdp_number: resource number
3305  * @cmd_details: pointer to command details structure or NULL
3306  *
3307  * release common resource using the admin queue commands
3308  **/
3309 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3310                                 enum i40e_aq_resources_ids resource,
3311                                 u8 sdp_number,
3312                                 struct i40e_asq_cmd_details *cmd_details)
3313 {
3314         struct i40e_aq_desc desc;
3315         struct i40e_aqc_request_resource *cmd =
3316                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3317         enum i40e_status_code status;
3318
3319         DEBUGFUNC("i40e_aq_release_resource");
3320
3321         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3322
3323         cmd->resource_id = CPU_TO_LE16(resource);
3324         cmd->resource_number = CPU_TO_LE32(sdp_number);
3325
3326         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3327
3328         return status;
3329 }
3330
3331 /**
3332  * i40e_aq_read_nvm
3333  * @hw: pointer to the hw struct
3334  * @module_pointer: module pointer location in words from the NVM beginning
3335  * @offset: byte offset from the module beginning
3336  * @length: length of the section to be read (in bytes from the offset)
3337  * @data: command buffer (size [bytes] = length)
3338  * @last_command: tells if this is the last command in a series
3339  * @cmd_details: pointer to command details structure or NULL
3340  *
3341  * Read the NVM using the admin queue commands
3342  **/
3343 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3344                                 u32 offset, u16 length, void *data,
3345                                 bool last_command,
3346                                 struct i40e_asq_cmd_details *cmd_details)
3347 {
3348         struct i40e_aq_desc desc;
3349         struct i40e_aqc_nvm_update *cmd =
3350                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3351         enum i40e_status_code status;
3352
3353         DEBUGFUNC("i40e_aq_read_nvm");
3354
3355         /* In offset the highest byte must be zeroed. */
3356         if (offset & 0xFF000000) {
3357                 status = I40E_ERR_PARAM;
3358                 goto i40e_aq_read_nvm_exit;
3359         }
3360
3361         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3362
3363         /* If this is the last command in a series, set the proper flag. */
3364         if (last_command)
3365                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3366         cmd->module_pointer = module_pointer;
3367         cmd->offset = CPU_TO_LE32(offset);
3368         cmd->length = CPU_TO_LE16(length);
3369
3370         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3371         if (length > I40E_AQ_LARGE_BUF)
3372                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3373
3374         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3375
3376 i40e_aq_read_nvm_exit:
3377         return status;
3378 }
3379
3380 /**
3381  * i40e_aq_read_nvm_config - read an nvm config block
3382  * @hw: pointer to the hw struct
3383  * @cmd_flags: NVM access admin command bits
3384  * @field_id: field or feature id
3385  * @data: buffer for result
3386  * @buf_size: buffer size
3387  * @element_count: pointer to count of elements read by FW
3388  * @cmd_details: pointer to command details structure or NULL
3389  **/
3390 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3391                                 u8 cmd_flags, u32 field_id, void *data,
3392                                 u16 buf_size, u16 *element_count,
3393                                 struct i40e_asq_cmd_details *cmd_details)
3394 {
3395         struct i40e_aq_desc desc;
3396         struct i40e_aqc_nvm_config_read *cmd =
3397                 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3398         enum i40e_status_code status;
3399
3400         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3401         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3402         if (buf_size > I40E_AQ_LARGE_BUF)
3403                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3404
3405         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3406         cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3407         if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3408                 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3409         else
3410                 cmd->element_id_msw = 0;
3411
3412         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3413
3414         if (!status && element_count)
3415                 *element_count = LE16_TO_CPU(cmd->element_count);
3416
3417         return status;
3418 }
3419
3420 /**
3421  * i40e_aq_write_nvm_config - write an nvm config block
3422  * @hw: pointer to the hw struct
3423  * @cmd_flags: NVM access admin command bits
3424  * @data: buffer for result
3425  * @buf_size: buffer size
3426  * @element_count: count of elements to be written
3427  * @cmd_details: pointer to command details structure or NULL
3428  **/
3429 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3430                                 u8 cmd_flags, void *data, u16 buf_size,
3431                                 u16 element_count,
3432                                 struct i40e_asq_cmd_details *cmd_details)
3433 {
3434         struct i40e_aq_desc desc;
3435         struct i40e_aqc_nvm_config_write *cmd =
3436                 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3437         enum i40e_status_code status;
3438
3439         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3440         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3441         if (buf_size > I40E_AQ_LARGE_BUF)
3442                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3443
3444         cmd->element_count = CPU_TO_LE16(element_count);
3445         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3446         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3447
3448         return status;
3449 }
3450
3451 /**
3452  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3453  * @hw: pointer to the hw struct
3454  * @cmd_details: pointer to command details structure or NULL
3455  **/
3456 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3457                                 void *buff, u16 buff_size,
3458                                 struct i40e_asq_cmd_details *cmd_details)
3459 {
3460         struct i40e_aq_desc desc;
3461         enum i40e_status_code status;
3462
3463         UNREFERENCED_2PARAMETER(buff, buff_size);
3464
3465         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3466         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3467         if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3468                 status = I40E_ERR_NOT_IMPLEMENTED;
3469
3470         return status;
3471 }
3472
3473 /**
3474  * i40e_aq_erase_nvm
3475  * @hw: pointer to the hw struct
3476  * @module_pointer: module pointer location in words from the NVM beginning
3477  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3478  * @length: length of the section to be erased (expressed in 4 KB)
3479  * @last_command: tells if this is the last command in a series
3480  * @cmd_details: pointer to command details structure or NULL
3481  *
3482  * Erase the NVM sector using the admin queue commands
3483  **/
3484 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3485                                 u32 offset, u16 length, bool last_command,
3486                                 struct i40e_asq_cmd_details *cmd_details)
3487 {
3488         struct i40e_aq_desc desc;
3489         struct i40e_aqc_nvm_update *cmd =
3490                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3491         enum i40e_status_code status;
3492
3493         DEBUGFUNC("i40e_aq_erase_nvm");
3494
3495         /* In offset the highest byte must be zeroed. */
3496         if (offset & 0xFF000000) {
3497                 status = I40E_ERR_PARAM;
3498                 goto i40e_aq_erase_nvm_exit;
3499         }
3500
3501         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3502
3503         /* If this is the last command in a series, set the proper flag. */
3504         if (last_command)
3505                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3506         cmd->module_pointer = module_pointer;
3507         cmd->offset = CPU_TO_LE32(offset);
3508         cmd->length = CPU_TO_LE16(length);
3509
3510         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3511
3512 i40e_aq_erase_nvm_exit:
3513         return status;
3514 }
3515
3516 /**
3517  * i40e_parse_discover_capabilities
3518  * @hw: pointer to the hw struct
3519  * @buff: pointer to a buffer containing device/function capability records
3520  * @cap_count: number of capability records in the list
3521  * @list_type_opc: type of capabilities list to parse
3522  *
3523  * Parse the device/function capabilities list.
3524  **/
3525 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3526                                      u32 cap_count,
3527                                      enum i40e_admin_queue_opc list_type_opc)
3528 {
3529         struct i40e_aqc_list_capabilities_element_resp *cap;
3530         u32 valid_functions, num_functions;
3531         u32 number, logical_id, phys_id;
3532         struct i40e_hw_capabilities *p;
3533         u8 major_rev;
3534         u32 i = 0;
3535         u16 id;
3536
3537         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3538
3539         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3540                 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3541         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3542                 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3543         else
3544                 return;
3545
3546         for (i = 0; i < cap_count; i++, cap++) {
3547                 id = LE16_TO_CPU(cap->id);
3548                 number = LE32_TO_CPU(cap->number);
3549                 logical_id = LE32_TO_CPU(cap->logical_id);
3550                 phys_id = LE32_TO_CPU(cap->phys_id);
3551                 major_rev = cap->major_rev;
3552
3553                 switch (id) {
3554                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3555                         p->switch_mode = number;
3556                         i40e_debug(hw, I40E_DEBUG_INIT,
3557                                    "HW Capability: Switch mode = %d\n",
3558                                    p->switch_mode);
3559                         break;
3560                 case I40E_AQ_CAP_ID_MNG_MODE:
3561                         p->management_mode = number;
3562                         i40e_debug(hw, I40E_DEBUG_INIT,
3563                                    "HW Capability: Management Mode = %d\n",
3564                                    p->management_mode);
3565                         break;
3566                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3567                         p->npar_enable = number;
3568                         i40e_debug(hw, I40E_DEBUG_INIT,
3569                                    "HW Capability: NPAR enable = %d\n",
3570                                    p->npar_enable);
3571                         break;
3572                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3573                         p->os2bmc = number;
3574                         i40e_debug(hw, I40E_DEBUG_INIT,
3575                                    "HW Capability: OS2BMC = %d\n", p->os2bmc);
3576                         break;
3577                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3578                         p->valid_functions = number;
3579                         i40e_debug(hw, I40E_DEBUG_INIT,
3580                                    "HW Capability: Valid Functions = %d\n",
3581                                    p->valid_functions);
3582                         break;
3583                 case I40E_AQ_CAP_ID_SRIOV:
3584                         if (number == 1)
3585                                 p->sr_iov_1_1 = true;
3586                         i40e_debug(hw, I40E_DEBUG_INIT,
3587                                    "HW Capability: SR-IOV = %d\n",
3588                                    p->sr_iov_1_1);
3589                         break;
3590                 case I40E_AQ_CAP_ID_VF:
3591                         p->num_vfs = number;
3592                         p->vf_base_id = logical_id;
3593                         i40e_debug(hw, I40E_DEBUG_INIT,
3594                                    "HW Capability: VF count = %d\n",
3595                                    p->num_vfs);
3596                         i40e_debug(hw, I40E_DEBUG_INIT,
3597                                    "HW Capability: VF base_id = %d\n",
3598                                    p->vf_base_id);
3599                         break;
3600                 case I40E_AQ_CAP_ID_VMDQ:
3601                         if (number == 1)
3602                                 p->vmdq = true;
3603                         i40e_debug(hw, I40E_DEBUG_INIT,
3604                                    "HW Capability: VMDQ = %d\n", p->vmdq);
3605                         break;
3606                 case I40E_AQ_CAP_ID_8021QBG:
3607                         if (number == 1)
3608                                 p->evb_802_1_qbg = true;
3609                         i40e_debug(hw, I40E_DEBUG_INIT,
3610                                    "HW Capability: 802.1Qbg = %d\n", number);
3611                         break;
3612                 case I40E_AQ_CAP_ID_8021QBR:
3613                         if (number == 1)
3614                                 p->evb_802_1_qbh = true;
3615                         i40e_debug(hw, I40E_DEBUG_INIT,
3616                                    "HW Capability: 802.1Qbh = %d\n", number);
3617                         break;
3618                 case I40E_AQ_CAP_ID_VSI:
3619                         p->num_vsis = number;
3620                         i40e_debug(hw, I40E_DEBUG_INIT,
3621                                    "HW Capability: VSI count = %d\n",
3622                                    p->num_vsis);
3623                         break;
3624                 case I40E_AQ_CAP_ID_DCB:
3625                         if (number == 1) {
3626                                 p->dcb = true;
3627                                 p->enabled_tcmap = logical_id;
3628                                 p->maxtc = phys_id;
3629                         }
3630                         i40e_debug(hw, I40E_DEBUG_INIT,
3631                                    "HW Capability: DCB = %d\n", p->dcb);
3632                         i40e_debug(hw, I40E_DEBUG_INIT,
3633                                    "HW Capability: TC Mapping = %d\n",
3634                                    logical_id);
3635                         i40e_debug(hw, I40E_DEBUG_INIT,
3636                                    "HW Capability: TC Max = %d\n", p->maxtc);
3637                         break;
3638                 case I40E_AQ_CAP_ID_FCOE:
3639                         if (number == 1)
3640                                 p->fcoe = true;
3641                         i40e_debug(hw, I40E_DEBUG_INIT,
3642                                    "HW Capability: FCOE = %d\n", p->fcoe);
3643                         break;
3644                 case I40E_AQ_CAP_ID_ISCSI:
3645                         if (number == 1)
3646                                 p->iscsi = true;
3647                         i40e_debug(hw, I40E_DEBUG_INIT,
3648                                    "HW Capability: iSCSI = %d\n", p->iscsi);
3649                         break;
3650                 case I40E_AQ_CAP_ID_RSS:
3651                         p->rss = true;
3652                         p->rss_table_size = number;
3653                         p->rss_table_entry_width = logical_id;
3654                         i40e_debug(hw, I40E_DEBUG_INIT,
3655                                    "HW Capability: RSS = %d\n", p->rss);
3656                         i40e_debug(hw, I40E_DEBUG_INIT,
3657                                    "HW Capability: RSS table size = %d\n",
3658                                    p->rss_table_size);
3659                         i40e_debug(hw, I40E_DEBUG_INIT,
3660                                    "HW Capability: RSS table width = %d\n",
3661                                    p->rss_table_entry_width);
3662                         break;
3663                 case I40E_AQ_CAP_ID_RXQ:
3664                         p->num_rx_qp = number;
3665                         p->base_queue = phys_id;
3666                         i40e_debug(hw, I40E_DEBUG_INIT,
3667                                    "HW Capability: Rx QP = %d\n", number);
3668                         i40e_debug(hw, I40E_DEBUG_INIT,
3669                                    "HW Capability: base_queue = %d\n",
3670                                    p->base_queue);
3671                         break;
3672                 case I40E_AQ_CAP_ID_TXQ:
3673                         p->num_tx_qp = number;
3674                         p->base_queue = phys_id;
3675                         i40e_debug(hw, I40E_DEBUG_INIT,
3676                                    "HW Capability: Tx QP = %d\n", number);
3677                         i40e_debug(hw, I40E_DEBUG_INIT,
3678                                    "HW Capability: base_queue = %d\n",
3679                                    p->base_queue);
3680                         break;
3681                 case I40E_AQ_CAP_ID_MSIX:
3682                         p->num_msix_vectors = number;
3683                         i40e_debug(hw, I40E_DEBUG_INIT,
3684                                    "HW Capability: MSIX vector count = %d\n",
3685                                    p->num_msix_vectors_vf);
3686                         break;
3687                 case I40E_AQ_CAP_ID_VF_MSIX:
3688                         p->num_msix_vectors_vf = number;
3689                         i40e_debug(hw, I40E_DEBUG_INIT,
3690                                    "HW Capability: MSIX VF vector count = %d\n",
3691                                    p->num_msix_vectors_vf);
3692                         break;
3693                 case I40E_AQ_CAP_ID_FLEX10:
3694                         if (major_rev == 1) {
3695                                 if (number == 1) {
3696                                         p->flex10_enable = true;
3697                                         p->flex10_capable = true;
3698                                 }
3699                         } else {
3700                                 /* Capability revision >= 2 */
3701                                 if (number & 1)
3702                                         p->flex10_enable = true;
3703                                 if (number & 2)
3704                                         p->flex10_capable = true;
3705                         }
3706                         p->flex10_mode = logical_id;
3707                         p->flex10_status = phys_id;
3708                         i40e_debug(hw, I40E_DEBUG_INIT,
3709                                    "HW Capability: Flex10 mode = %d\n",
3710                                    p->flex10_mode);
3711                         i40e_debug(hw, I40E_DEBUG_INIT,
3712                                    "HW Capability: Flex10 status = %d\n",
3713                                    p->flex10_status);
3714                         break;
3715                 case I40E_AQ_CAP_ID_CEM:
3716                         if (number == 1)
3717                                 p->mgmt_cem = true;
3718                         i40e_debug(hw, I40E_DEBUG_INIT,
3719                                    "HW Capability: CEM = %d\n", p->mgmt_cem);
3720                         break;
3721                 case I40E_AQ_CAP_ID_IWARP:
3722                         if (number == 1)
3723                                 p->iwarp = true;
3724                         i40e_debug(hw, I40E_DEBUG_INIT,
3725                                    "HW Capability: iWARP = %d\n", p->iwarp);
3726                         break;
3727                 case I40E_AQ_CAP_ID_LED:
3728                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3729                                 p->led[phys_id] = true;
3730                         i40e_debug(hw, I40E_DEBUG_INIT,
3731                                    "HW Capability: LED - PIN %d\n", phys_id);
3732                         break;
3733                 case I40E_AQ_CAP_ID_SDP:
3734                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3735                                 p->sdp[phys_id] = true;
3736                         i40e_debug(hw, I40E_DEBUG_INIT,
3737                                    "HW Capability: SDP - PIN %d\n", phys_id);
3738                         break;
3739                 case I40E_AQ_CAP_ID_MDIO:
3740                         if (number == 1) {
3741                                 p->mdio_port_num = phys_id;
3742                                 p->mdio_port_mode = logical_id;
3743                         }
3744                         i40e_debug(hw, I40E_DEBUG_INIT,
3745                                    "HW Capability: MDIO port number = %d\n",
3746                                    p->mdio_port_num);
3747                         i40e_debug(hw, I40E_DEBUG_INIT,
3748                                    "HW Capability: MDIO port mode = %d\n",
3749                                    p->mdio_port_mode);
3750                         break;
3751                 case I40E_AQ_CAP_ID_1588:
3752                         if (number == 1)
3753                                 p->ieee_1588 = true;
3754                         i40e_debug(hw, I40E_DEBUG_INIT,
3755                                    "HW Capability: IEEE 1588 = %d\n",
3756                                    p->ieee_1588);
3757                         break;
3758                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3759                         p->fd = true;
3760                         p->fd_filters_guaranteed = number;
3761                         p->fd_filters_best_effort = logical_id;
3762                         i40e_debug(hw, I40E_DEBUG_INIT,
3763                                    "HW Capability: Flow Director = 1\n");
3764                         i40e_debug(hw, I40E_DEBUG_INIT,
3765                                    "HW Capability: Guaranteed FD filters = %d\n",
3766                                    p->fd_filters_guaranteed);
3767                         break;
3768                 case I40E_AQ_CAP_ID_WSR_PROT:
3769                         p->wr_csr_prot = (u64)number;
3770                         p->wr_csr_prot |= (u64)logical_id << 32;
3771                         i40e_debug(hw, I40E_DEBUG_INIT,
3772                                    "HW Capability: wr_csr_prot = 0x%llX\n\n",
3773                                    (p->wr_csr_prot & 0xffff));
3774                         break;
3775 #ifdef X722_SUPPORT
3776                 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3777                         hw->num_wol_proxy_filters = (u16)number;
3778                         hw->wol_proxy_vsi_seid = (u16)logical_id;
3779                         p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3780                         if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3781                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3782                         else
3783                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3784                         p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3785                         p->proxy_support = p->proxy_support;
3786                         i40e_debug(hw, I40E_DEBUG_INIT,
3787                                    "HW Capability: WOL proxy filters = %d\n",
3788                                    hw->num_wol_proxy_filters);
3789                         break;
3790 #endif
3791                 default:
3792                         break;
3793                 }
3794         }
3795
3796         if (p->fcoe)
3797                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3798
3799 #ifdef I40E_FCOE_ENA
3800         /* Software override ensuring FCoE is disabled if npar or mfp
3801          * mode because it is not supported in these modes.
3802          */
3803         if (p->npar_enable || p->flex10_enable)
3804                 p->fcoe = false;
3805 #else
3806         /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3807         p->fcoe = false;
3808 #endif
3809
3810         /* count the enabled ports (aka the "not disabled" ports) */
3811         hw->num_ports = 0;
3812         for (i = 0; i < 4; i++) {
3813                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3814                 u64 port_cfg = 0;
3815
3816                 /* use AQ read to get the physical register offset instead
3817                  * of the port relative offset
3818                  */
3819                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3820                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3821                         hw->num_ports++;
3822         }
3823
3824         valid_functions = p->valid_functions;
3825         num_functions = 0;
3826         while (valid_functions) {
3827                 if (valid_functions & 1)
3828                         num_functions++;
3829                 valid_functions >>= 1;
3830         }
3831
3832         /* partition id is 1-based, and functions are evenly spread
3833          * across the ports as partitions
3834          */
3835         hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3836         hw->num_partitions = num_functions / hw->num_ports;
3837
3838         /* additional HW specific goodies that might
3839          * someday be HW version specific
3840          */
3841         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3842 }
3843
3844 /**
3845  * i40e_aq_discover_capabilities
3846  * @hw: pointer to the hw struct
3847  * @buff: a virtual buffer to hold the capabilities
3848  * @buff_size: Size of the virtual buffer
3849  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3850  * @list_type_opc: capabilities type to discover - pass in the command opcode
3851  * @cmd_details: pointer to command details structure or NULL
3852  *
3853  * Get the device capabilities descriptions from the firmware
3854  **/
3855 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3856                                 void *buff, u16 buff_size, u16 *data_size,
3857                                 enum i40e_admin_queue_opc list_type_opc,
3858                                 struct i40e_asq_cmd_details *cmd_details)
3859 {
3860         struct i40e_aqc_list_capabilites *cmd;
3861         struct i40e_aq_desc desc;
3862         enum i40e_status_code status = I40E_SUCCESS;
3863
3864         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3865
3866         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3867                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3868                 status = I40E_ERR_PARAM;
3869                 goto exit;
3870         }
3871
3872         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3873
3874         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3875         if (buff_size > I40E_AQ_LARGE_BUF)
3876                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3877
3878         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3879         *data_size = LE16_TO_CPU(desc.datalen);
3880
3881         if (status)
3882                 goto exit;
3883
3884         i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3885                                          list_type_opc);
3886
3887 exit:
3888         return status;
3889 }
3890
3891 /**
3892  * i40e_aq_update_nvm
3893  * @hw: pointer to the hw struct
3894  * @module_pointer: module pointer location in words from the NVM beginning
3895  * @offset: byte offset from the module beginning
3896  * @length: length of the section to be written (in bytes from the offset)
3897  * @data: command buffer (size [bytes] = length)
3898  * @last_command: tells if this is the last command in a series
3899  * @cmd_details: pointer to command details structure or NULL
3900  *
3901  * Update the NVM using the admin queue commands
3902  **/
3903 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3904                                 u32 offset, u16 length, void *data,
3905                                 bool last_command,
3906                                 struct i40e_asq_cmd_details *cmd_details)
3907 {
3908         struct i40e_aq_desc desc;
3909         struct i40e_aqc_nvm_update *cmd =
3910                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3911         enum i40e_status_code status;
3912
3913         DEBUGFUNC("i40e_aq_update_nvm");
3914
3915         /* In offset the highest byte must be zeroed. */
3916         if (offset & 0xFF000000) {
3917                 status = I40E_ERR_PARAM;
3918                 goto i40e_aq_update_nvm_exit;
3919         }
3920
3921         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3922
3923         /* If this is the last command in a series, set the proper flag. */
3924         if (last_command)
3925                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3926         cmd->module_pointer = module_pointer;
3927         cmd->offset = CPU_TO_LE32(offset);
3928         cmd->length = CPU_TO_LE16(length);
3929
3930         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3931         if (length > I40E_AQ_LARGE_BUF)
3932                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3933
3934         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3935
3936 i40e_aq_update_nvm_exit:
3937         return status;
3938 }
3939
3940 /**
3941  * i40e_aq_get_lldp_mib
3942  * @hw: pointer to the hw struct
3943  * @bridge_type: type of bridge requested
3944  * @mib_type: Local, Remote or both Local and Remote MIBs
3945  * @buff: pointer to a user supplied buffer to store the MIB block
3946  * @buff_size: size of the buffer (in bytes)
3947  * @local_len : length of the returned Local LLDP MIB
3948  * @remote_len: length of the returned Remote LLDP MIB
3949  * @cmd_details: pointer to command details structure or NULL
3950  *
3951  * Requests the complete LLDP MIB (entire packet).
3952  **/
3953 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3954                                 u8 mib_type, void *buff, u16 buff_size,
3955                                 u16 *local_len, u16 *remote_len,
3956                                 struct i40e_asq_cmd_details *cmd_details)
3957 {
3958         struct i40e_aq_desc desc;
3959         struct i40e_aqc_lldp_get_mib *cmd =
3960                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3961         struct i40e_aqc_lldp_get_mib *resp =
3962                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3963         enum i40e_status_code status;
3964
3965         if (buff_size == 0 || !buff)
3966                 return I40E_ERR_PARAM;
3967
3968         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3969         /* Indirect Command */
3970         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3971
3972         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3973         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3974                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3975
3976         desc.datalen = CPU_TO_LE16(buff_size);
3977
3978         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3979         if (buff_size > I40E_AQ_LARGE_BUF)
3980                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3981
3982         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3983         if (!status) {
3984                 if (local_len != NULL)
3985                         *local_len = LE16_TO_CPU(resp->local_len);
3986                 if (remote_len != NULL)
3987                         *remote_len = LE16_TO_CPU(resp->remote_len);
3988         }
3989
3990         return status;
3991 }
3992
3993  /**
3994  * i40e_aq_set_lldp_mib - Set the LLDP MIB
3995  * @hw: pointer to the hw struct
3996  * @mib_type: Local, Remote or both Local and Remote MIBs
3997  * @buff: pointer to a user supplied buffer to store the MIB block
3998  * @buff_size: size of the buffer (in bytes)
3999  * @cmd_details: pointer to command details structure or NULL
4000  *
4001  * Set the LLDP MIB.
4002  **/
4003 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4004                                 u8 mib_type, void *buff, u16 buff_size,
4005                                 struct i40e_asq_cmd_details *cmd_details)
4006 {
4007         struct i40e_aq_desc desc;
4008         struct i40e_aqc_lldp_set_local_mib *cmd =
4009                 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4010         enum i40e_status_code status;
4011
4012         if (buff_size == 0 || !buff)
4013                 return I40E_ERR_PARAM;
4014
4015         i40e_fill_default_direct_cmd_desc(&desc,
4016                                 i40e_aqc_opc_lldp_set_local_mib);
4017         /* Indirect Command */
4018         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4019         if (buff_size > I40E_AQ_LARGE_BUF)
4020                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4021         desc.datalen = CPU_TO_LE16(buff_size);
4022
4023         cmd->type = mib_type;
4024         cmd->length = CPU_TO_LE16(buff_size);
4025         cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4026         cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4027
4028         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4029         return status;
4030 }
4031
4032 /**
4033  * i40e_aq_cfg_lldp_mib_change_event
4034  * @hw: pointer to the hw struct
4035  * @enable_update: Enable or Disable event posting
4036  * @cmd_details: pointer to command details structure or NULL
4037  *
4038  * Enable or Disable posting of an event on ARQ when LLDP MIB
4039  * associated with the interface changes
4040  **/
4041 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4042                                 bool enable_update,
4043                                 struct i40e_asq_cmd_details *cmd_details)
4044 {
4045         struct i40e_aq_desc desc;
4046         struct i40e_aqc_lldp_update_mib *cmd =
4047                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4048         enum i40e_status_code status;
4049
4050         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4051
4052         if (!enable_update)
4053                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4054
4055         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4056
4057         return status;
4058 }
4059
4060 /**
4061  * i40e_aq_add_lldp_tlv
4062  * @hw: pointer to the hw struct
4063  * @bridge_type: type of bridge
4064  * @buff: buffer with TLV to add
4065  * @buff_size: length of the buffer
4066  * @tlv_len: length of the TLV to be added
4067  * @mib_len: length of the LLDP MIB returned in response
4068  * @cmd_details: pointer to command details structure or NULL
4069  *
4070  * Add the specified TLV to LLDP Local MIB for the given bridge type,
4071  * it is responsibility of the caller to make sure that the TLV is not
4072  * already present in the LLDPDU.
4073  * In return firmware will write the complete LLDP MIB with the newly
4074  * added TLV in the response buffer.
4075  **/
4076 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4077                                 void *buff, u16 buff_size, u16 tlv_len,
4078                                 u16 *mib_len,
4079                                 struct i40e_asq_cmd_details *cmd_details)
4080 {
4081         struct i40e_aq_desc desc;
4082         struct i40e_aqc_lldp_add_tlv *cmd =
4083                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4084         enum i40e_status_code status;
4085
4086         if (buff_size == 0 || !buff || tlv_len == 0)
4087                 return I40E_ERR_PARAM;
4088
4089         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4090
4091         /* Indirect Command */
4092         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4093         if (buff_size > I40E_AQ_LARGE_BUF)
4094                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4095         desc.datalen = CPU_TO_LE16(buff_size);
4096
4097         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4098                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4099         cmd->len = CPU_TO_LE16(tlv_len);
4100
4101         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4102         if (!status) {
4103                 if (mib_len != NULL)
4104                         *mib_len = LE16_TO_CPU(desc.datalen);
4105         }
4106
4107         return status;
4108 }
4109
4110 /**
4111  * i40e_aq_update_lldp_tlv
4112  * @hw: pointer to the hw struct
4113  * @bridge_type: type of bridge
4114  * @buff: buffer with TLV to update
4115  * @buff_size: size of the buffer holding original and updated TLVs
4116  * @old_len: Length of the Original TLV
4117  * @new_len: Length of the Updated TLV
4118  * @offset: offset of the updated TLV in the buff
4119  * @mib_len: length of the returned LLDP MIB
4120  * @cmd_details: pointer to command details structure or NULL
4121  *
4122  * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4123  * Firmware will place the complete LLDP MIB in response buffer with the
4124  * updated TLV.
4125  **/
4126 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4127                                 u8 bridge_type, void *buff, u16 buff_size,
4128                                 u16 old_len, u16 new_len, u16 offset,
4129                                 u16 *mib_len,
4130                                 struct i40e_asq_cmd_details *cmd_details)
4131 {
4132         struct i40e_aq_desc desc;
4133         struct i40e_aqc_lldp_update_tlv *cmd =
4134                 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4135         enum i40e_status_code status;
4136
4137         if (buff_size == 0 || !buff || offset == 0 ||
4138             old_len == 0 || new_len == 0)
4139                 return I40E_ERR_PARAM;
4140
4141         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4142
4143         /* Indirect Command */
4144         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4145         if (buff_size > I40E_AQ_LARGE_BUF)
4146                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4147         desc.datalen = CPU_TO_LE16(buff_size);
4148
4149         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4150                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4151         cmd->old_len = CPU_TO_LE16(old_len);
4152         cmd->new_offset = CPU_TO_LE16(offset);
4153         cmd->new_len = CPU_TO_LE16(new_len);
4154
4155         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4156         if (!status) {
4157                 if (mib_len != NULL)
4158                         *mib_len = LE16_TO_CPU(desc.datalen);
4159         }
4160
4161         return status;
4162 }
4163
4164 /**
4165  * i40e_aq_delete_lldp_tlv
4166  * @hw: pointer to the hw struct
4167  * @bridge_type: type of bridge
4168  * @buff: pointer to a user supplied buffer that has the TLV
4169  * @buff_size: length of the buffer
4170  * @tlv_len: length of the TLV to be deleted
4171  * @mib_len: length of the returned LLDP MIB
4172  * @cmd_details: pointer to command details structure or NULL
4173  *
4174  * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4175  * The firmware places the entire LLDP MIB in the response buffer.
4176  **/
4177 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4178                                 u8 bridge_type, void *buff, u16 buff_size,
4179                                 u16 tlv_len, u16 *mib_len,
4180                                 struct i40e_asq_cmd_details *cmd_details)
4181 {
4182         struct i40e_aq_desc desc;
4183         struct i40e_aqc_lldp_add_tlv *cmd =
4184                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4185         enum i40e_status_code status;
4186
4187         if (buff_size == 0 || !buff)
4188                 return I40E_ERR_PARAM;
4189
4190         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4191
4192         /* Indirect Command */
4193         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4194         if (buff_size > I40E_AQ_LARGE_BUF)
4195                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4196         desc.datalen = CPU_TO_LE16(buff_size);
4197         cmd->len = CPU_TO_LE16(tlv_len);
4198         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4199                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4200
4201         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4202         if (!status) {
4203                 if (mib_len != NULL)
4204                         *mib_len = LE16_TO_CPU(desc.datalen);
4205         }
4206
4207         return status;
4208 }
4209
4210 /**
4211  * i40e_aq_stop_lldp
4212  * @hw: pointer to the hw struct
4213  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4214  * @cmd_details: pointer to command details structure or NULL
4215  *
4216  * Stop or Shutdown the embedded LLDP Agent
4217  **/
4218 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4219                                 struct i40e_asq_cmd_details *cmd_details)
4220 {
4221         struct i40e_aq_desc desc;
4222         struct i40e_aqc_lldp_stop *cmd =
4223                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4224         enum i40e_status_code status;
4225
4226         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4227
4228         if (shutdown_agent)
4229                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4230
4231         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4232
4233         return status;
4234 }
4235
4236 /**
4237  * i40e_aq_start_lldp
4238  * @hw: pointer to the hw struct
4239  * @cmd_details: pointer to command details structure or NULL
4240  *
4241  * Start the embedded LLDP Agent on all ports.
4242  **/
4243 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4244                                 struct i40e_asq_cmd_details *cmd_details)
4245 {
4246         struct i40e_aq_desc desc;
4247         struct i40e_aqc_lldp_start *cmd =
4248                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4249         enum i40e_status_code status;
4250
4251         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4252
4253         cmd->command = I40E_AQ_LLDP_AGENT_START;
4254
4255         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4256
4257         return status;
4258 }
4259
4260 /**
4261  * i40e_aq_get_cee_dcb_config
4262  * @hw: pointer to the hw struct
4263  * @buff: response buffer that stores CEE operational configuration
4264  * @buff_size: size of the buffer passed
4265  * @cmd_details: pointer to command details structure or NULL
4266  *
4267  * Get CEE DCBX mode operational configuration from firmware
4268  **/
4269 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4270                                 void *buff, u16 buff_size,
4271                                 struct i40e_asq_cmd_details *cmd_details)
4272 {
4273         struct i40e_aq_desc desc;
4274         enum i40e_status_code status;
4275
4276         if (buff_size == 0 || !buff)
4277                 return I40E_ERR_PARAM;
4278
4279         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4280
4281         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4282         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4283                                        cmd_details);
4284
4285         return status;
4286 }
4287
4288 /**
4289  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4290  * @hw: pointer to the hw struct
4291  * @start_agent: True if DCBx Agent needs to be Started
4292  *                              False if DCBx Agent needs to be Stopped
4293  * @cmd_details: pointer to command details structure or NULL
4294  *
4295  * Start/Stop the embedded dcbx Agent
4296  **/
4297 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4298                                 bool start_agent,
4299                                 struct i40e_asq_cmd_details *cmd_details)
4300 {
4301         struct i40e_aq_desc desc;
4302         struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4303                 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4304                                 &desc.params.raw;
4305         enum i40e_status_code status;
4306
4307         i40e_fill_default_direct_cmd_desc(&desc,
4308                                 i40e_aqc_opc_lldp_stop_start_spec_agent);
4309
4310         if (start_agent)
4311                 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4312
4313         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4314
4315         return status;
4316 }
4317
4318 /**
4319  * i40e_aq_add_udp_tunnel
4320  * @hw: pointer to the hw struct
4321  * @udp_port: the UDP port to add
4322  * @header_len: length of the tunneling header length in DWords
4323  * @protocol_index: protocol index type
4324  * @filter_index: pointer to filter index
4325  * @cmd_details: pointer to command details structure or NULL
4326  **/
4327 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4328                                 u16 udp_port, u8 protocol_index,
4329                                 u8 *filter_index,
4330                                 struct i40e_asq_cmd_details *cmd_details)
4331 {
4332         struct i40e_aq_desc desc;
4333         struct i40e_aqc_add_udp_tunnel *cmd =
4334                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4335         struct i40e_aqc_del_udp_tunnel_completion *resp =
4336                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4337         enum i40e_status_code status;
4338
4339         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4340
4341         cmd->udp_port = CPU_TO_LE16(udp_port);
4342         cmd->protocol_type = protocol_index;
4343
4344         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4345
4346         if (!status && filter_index)
4347                 *filter_index = resp->index;
4348
4349         return status;
4350 }
4351
4352 /**
4353  * i40e_aq_del_udp_tunnel
4354  * @hw: pointer to the hw struct
4355  * @index: filter index
4356  * @cmd_details: pointer to command details structure or NULL
4357  **/
4358 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4359                                 struct i40e_asq_cmd_details *cmd_details)
4360 {
4361         struct i40e_aq_desc desc;
4362         struct i40e_aqc_remove_udp_tunnel *cmd =
4363                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4364         enum i40e_status_code status;
4365
4366         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4367
4368         cmd->index = index;
4369
4370         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4371
4372         return status;
4373 }
4374
4375 /**
4376  * i40e_aq_get_switch_resource_alloc (0x0204)
4377  * @hw: pointer to the hw struct
4378  * @num_entries: pointer to u8 to store the number of resource entries returned
4379  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
4380  *        to store the resource information for all resource types.  Each
4381  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
4382  * @count: size, in bytes, of the buffer provided
4383  * @cmd_details: pointer to command details structure or NULL
4384  *
4385  * Query the resources allocated to a function.
4386  **/
4387 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4388                         u8 *num_entries,
4389                         struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4390                         u16 count,
4391                         struct i40e_asq_cmd_details *cmd_details)
4392 {
4393         struct i40e_aq_desc desc;
4394         struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4395                 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4396         enum i40e_status_code status;
4397         u16 length = count * sizeof(*buf);
4398
4399         i40e_fill_default_direct_cmd_desc(&desc,
4400                                         i40e_aqc_opc_get_switch_resource_alloc);
4401
4402         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4403         if (length > I40E_AQ_LARGE_BUF)
4404                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4405
4406         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4407
4408         if (!status && num_entries)
4409                 *num_entries = cmd_resp->num_entries;
4410
4411         return status;
4412 }
4413
4414 /**
4415  * i40e_aq_delete_element - Delete switch element
4416  * @hw: pointer to the hw struct
4417  * @seid: the SEID to delete from the switch
4418  * @cmd_details: pointer to command details structure or NULL
4419  *
4420  * This deletes a switch element from the switch.
4421  **/
4422 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4423                                 struct i40e_asq_cmd_details *cmd_details)
4424 {
4425         struct i40e_aq_desc desc;
4426         struct i40e_aqc_switch_seid *cmd =
4427                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4428         enum i40e_status_code status;
4429
4430         if (seid == 0)
4431                 return I40E_ERR_PARAM;
4432
4433         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4434
4435         cmd->seid = CPU_TO_LE16(seid);
4436
4437         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4438
4439         return status;
4440 }
4441
4442 /**
4443  * i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4444  * @hw: pointer to the hw struct
4445  * @flags: component flags
4446  * @mac_seid: uplink seid (MAC SEID)
4447  * @vsi_seid: connected vsi seid
4448  * @ret_seid: seid of create pv component
4449  *
4450  * This instantiates an i40e port virtualizer with specified flags.
4451  * Depending on specified flags the port virtualizer can act as a
4452  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4453  */
4454 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4455                                        u16 mac_seid, u16 vsi_seid,
4456                                        u16 *ret_seid)
4457 {
4458         struct i40e_aq_desc desc;
4459         struct i40e_aqc_add_update_pv *cmd =
4460                 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4461         struct i40e_aqc_add_update_pv_completion *resp =
4462                 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4463         enum i40e_status_code status;
4464
4465         if (vsi_seid == 0)
4466                 return I40E_ERR_PARAM;
4467
4468         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4469         cmd->command_flags = CPU_TO_LE16(flags);
4470         cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4471         cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4472
4473         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4474         if (!status && ret_seid)
4475                 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4476
4477         return status;
4478 }
4479
4480 /**
4481  * i40e_aq_add_tag - Add an S/E-tag
4482  * @hw: pointer to the hw struct
4483  * @direct_to_queue: should s-tag direct flow to a specific queue
4484  * @vsi_seid: VSI SEID to use this tag
4485  * @tag: value of the tag
4486  * @queue_num: queue number, only valid is direct_to_queue is true
4487  * @tags_used: return value, number of tags in use by this PF
4488  * @tags_free: return value, number of unallocated tags
4489  * @cmd_details: pointer to command details structure or NULL
4490  *
4491  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4492  * the number of tags allocated by the PF, and the number of unallocated
4493  * tags available.
4494  **/
4495 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4496                                 u16 vsi_seid, u16 tag, u16 queue_num,
4497                                 u16 *tags_used, u16 *tags_free,
4498                                 struct i40e_asq_cmd_details *cmd_details)
4499 {
4500         struct i40e_aq_desc desc;
4501         struct i40e_aqc_add_tag *cmd =
4502                 (struct i40e_aqc_add_tag *)&desc.params.raw;
4503         struct i40e_aqc_add_remove_tag_completion *resp =
4504                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4505         enum i40e_status_code status;
4506
4507         if (vsi_seid == 0)
4508                 return I40E_ERR_PARAM;
4509
4510         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4511
4512         cmd->seid = CPU_TO_LE16(vsi_seid);
4513         cmd->tag = CPU_TO_LE16(tag);
4514         if (direct_to_queue) {
4515                 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4516                 cmd->queue_number = CPU_TO_LE16(queue_num);
4517         }
4518
4519         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4520
4521         if (!status) {
4522                 if (tags_used != NULL)
4523                         *tags_used = LE16_TO_CPU(resp->tags_used);
4524                 if (tags_free != NULL)
4525                         *tags_free = LE16_TO_CPU(resp->tags_free);
4526         }
4527
4528         return status;
4529 }
4530
4531 /**
4532  * i40e_aq_remove_tag - Remove an S- or E-tag
4533  * @hw: pointer to the hw struct
4534  * @vsi_seid: VSI SEID this tag is associated with
4535  * @tag: value of the S-tag to delete
4536  * @tags_used: return value, number of tags in use by this PF
4537  * @tags_free: return value, number of unallocated tags
4538  * @cmd_details: pointer to command details structure or NULL
4539  *
4540  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4541  * the number of tags allocated by the PF, and the number of unallocated
4542  * tags available.
4543  **/
4544 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4545                                 u16 tag, u16 *tags_used, u16 *tags_free,
4546                                 struct i40e_asq_cmd_details *cmd_details)
4547 {
4548         struct i40e_aq_desc desc;
4549         struct i40e_aqc_remove_tag *cmd =
4550                 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4551         struct i40e_aqc_add_remove_tag_completion *resp =
4552                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4553         enum i40e_status_code status;
4554
4555         if (vsi_seid == 0)
4556                 return I40E_ERR_PARAM;
4557
4558         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4559
4560         cmd->seid = CPU_TO_LE16(vsi_seid);
4561         cmd->tag = CPU_TO_LE16(tag);
4562
4563         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4564
4565         if (!status) {
4566                 if (tags_used != NULL)
4567                         *tags_used = LE16_TO_CPU(resp->tags_used);
4568                 if (tags_free != NULL)
4569                         *tags_free = LE16_TO_CPU(resp->tags_free);
4570         }
4571
4572         return status;
4573 }
4574
4575 /**
4576  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4577  * @hw: pointer to the hw struct
4578  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4579  * @etag: value of E-tag to add
4580  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4581  * @buf: address of indirect buffer
4582  * @tags_used: return value, number of E-tags in use by this port
4583  * @tags_free: return value, number of unallocated M-tags
4584  * @cmd_details: pointer to command details structure or NULL
4585  *
4586  * This associates a multicast E-tag to a port virtualizer.  It will return
4587  * the number of tags allocated by the PF, and the number of unallocated
4588  * tags available.
4589  *
4590  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4591  * num_tags_in_buf long.
4592  **/
4593 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4594                                 u16 etag, u8 num_tags_in_buf, void *buf,
4595                                 u16 *tags_used, u16 *tags_free,
4596                                 struct i40e_asq_cmd_details *cmd_details)
4597 {
4598         struct i40e_aq_desc desc;
4599         struct i40e_aqc_add_remove_mcast_etag *cmd =
4600                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4601         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4602            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4603         enum i40e_status_code status;
4604         u16 length = sizeof(u16) * num_tags_in_buf;
4605
4606         if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4607                 return I40E_ERR_PARAM;
4608
4609         i40e_fill_default_direct_cmd_desc(&desc,
4610                                           i40e_aqc_opc_add_multicast_etag);
4611
4612         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4613         cmd->etag = CPU_TO_LE16(etag);
4614         cmd->num_unicast_etags = num_tags_in_buf;
4615
4616         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4617         if (length > I40E_AQ_LARGE_BUF)
4618                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4619
4620         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4621
4622         if (!status) {
4623                 if (tags_used != NULL)
4624                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4625                 if (tags_free != NULL)
4626                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4627         }
4628
4629         return status;
4630 }
4631
4632 /**
4633  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4634  * @hw: pointer to the hw struct
4635  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4636  * @etag: value of the E-tag to remove
4637  * @tags_used: return value, number of tags in use by this port
4638  * @tags_free: return value, number of unallocated tags
4639  * @cmd_details: pointer to command details structure or NULL
4640  *
4641  * This deletes an E-tag from the port virtualizer.  It will return
4642  * the number of tags allocated by the port, and the number of unallocated
4643  * tags available.
4644  **/
4645 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4646                                 u16 etag, u16 *tags_used, u16 *tags_free,
4647                                 struct i40e_asq_cmd_details *cmd_details)
4648 {
4649         struct i40e_aq_desc desc;
4650         struct i40e_aqc_add_remove_mcast_etag *cmd =
4651                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4652         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4653            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4654         enum i40e_status_code status;
4655
4656
4657         if (pv_seid == 0)
4658                 return I40E_ERR_PARAM;
4659
4660         i40e_fill_default_direct_cmd_desc(&desc,
4661                                           i40e_aqc_opc_remove_multicast_etag);
4662
4663         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4664         cmd->etag = CPU_TO_LE16(etag);
4665
4666         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4667
4668         if (!status) {
4669                 if (tags_used != NULL)
4670                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4671                 if (tags_free != NULL)
4672                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4673         }
4674
4675         return status;
4676 }
4677
4678 /**
4679  * i40e_aq_update_tag - Update an S/E-tag
4680  * @hw: pointer to the hw struct
4681  * @vsi_seid: VSI SEID using this S-tag
4682  * @old_tag: old tag value
4683  * @new_tag: new tag value
4684  * @tags_used: return value, number of tags in use by this PF
4685  * @tags_free: return value, number of unallocated tags
4686  * @cmd_details: pointer to command details structure or NULL
4687  *
4688  * This updates the value of the tag currently attached to this VSI
4689  * in the switch complex.  It will return the number of tags allocated
4690  * by the PF, and the number of unallocated tags available.
4691  **/
4692 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4693                                 u16 old_tag, u16 new_tag, u16 *tags_used,
4694                                 u16 *tags_free,
4695                                 struct i40e_asq_cmd_details *cmd_details)
4696 {
4697         struct i40e_aq_desc desc;
4698         struct i40e_aqc_update_tag *cmd =
4699                 (struct i40e_aqc_update_tag *)&desc.params.raw;
4700         struct i40e_aqc_update_tag_completion *resp =
4701                 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4702         enum i40e_status_code status;
4703
4704         if (vsi_seid == 0)
4705                 return I40E_ERR_PARAM;
4706
4707         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4708
4709         cmd->seid = CPU_TO_LE16(vsi_seid);
4710         cmd->old_tag = CPU_TO_LE16(old_tag);
4711         cmd->new_tag = CPU_TO_LE16(new_tag);
4712
4713         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4714
4715         if (!status) {
4716                 if (tags_used != NULL)
4717                         *tags_used = LE16_TO_CPU(resp->tags_used);
4718                 if (tags_free != NULL)
4719                         *tags_free = LE16_TO_CPU(resp->tags_free);
4720         }
4721
4722         return status;
4723 }
4724
4725 /**
4726  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4727  * @hw: pointer to the hw struct
4728  * @tcmap: TC map for request/release any ignore PFC condition
4729  * @request: request or release ignore PFC condition
4730  * @tcmap_ret: return TCs for which PFC is currently ignored
4731  * @cmd_details: pointer to command details structure or NULL
4732  *
4733  * This sends out request/release to ignore PFC condition for a TC.
4734  * It will return the TCs for which PFC is currently ignored.
4735  **/
4736 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4737                                 bool request, u8 *tcmap_ret,
4738                                 struct i40e_asq_cmd_details *cmd_details)
4739 {
4740         struct i40e_aq_desc desc;
4741         struct i40e_aqc_pfc_ignore *cmd_resp =
4742                 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4743         enum i40e_status_code status;
4744
4745         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4746
4747         if (request)
4748                 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4749
4750         cmd_resp->tc_bitmap = tcmap;
4751
4752         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4753
4754         if (!status) {
4755                 if (tcmap_ret != NULL)
4756                         *tcmap_ret = cmd_resp->tc_bitmap;
4757         }
4758
4759         return status;
4760 }
4761
4762 /**
4763  * i40e_aq_dcb_updated - DCB Updated Command
4764  * @hw: pointer to the hw struct
4765  * @cmd_details: pointer to command details structure or NULL
4766  *
4767  * When LLDP is handled in PF this command is used by the PF
4768  * to notify EMP that a DCB setting is modified.
4769  * When LLDP is handled in EMP this command is used by the PF
4770  * to notify EMP whenever one of the following parameters get
4771  * modified:
4772  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4773  *   - PCIRTT in PRTDCB_GENC.PCIRTT
4774  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4775  * EMP will return when the shared RPB settings have been
4776  * recomputed and modified. The retval field in the descriptor
4777  * will be set to 0 when RPB is modified.
4778  **/
4779 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4780                                 struct i40e_asq_cmd_details *cmd_details)
4781 {
4782         struct i40e_aq_desc desc;
4783         enum i40e_status_code status;
4784
4785         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4786
4787         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4788
4789         return status;
4790 }
4791
4792 /**
4793  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4794  * @hw: pointer to the hw struct
4795  * @seid: defines the SEID of the switch for which the stats are requested
4796  * @vlan_id: the VLAN ID for which the statistics are requested
4797  * @stat_index: index of the statistics counters block assigned to this VLAN
4798  * @cmd_details: pointer to command details structure or NULL
4799  *
4800  * XL710 supports 128 smonVlanStats counters.This command is used to
4801  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4802  * switch.
4803  **/
4804 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4805                                 u16 vlan_id, u16 *stat_index,
4806                                 struct i40e_asq_cmd_details *cmd_details)
4807 {
4808         struct i40e_aq_desc desc;
4809         struct i40e_aqc_add_remove_statistics *cmd_resp =
4810                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4811         enum i40e_status_code status;
4812
4813         if ((seid == 0) || (stat_index == NULL))
4814                 return I40E_ERR_PARAM;
4815
4816         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4817
4818         cmd_resp->seid = CPU_TO_LE16(seid);
4819         cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4820
4821         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4822
4823         if (!status && stat_index)
4824                 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4825
4826         return status;
4827 }
4828
4829 /**
4830  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4831  * @hw: pointer to the hw struct
4832  * @seid: defines the SEID of the switch for which the stats are requested
4833  * @vlan_id: the VLAN ID for which the statistics are requested
4834  * @stat_index: index of the statistics counters block assigned to this VLAN
4835  * @cmd_details: pointer to command details structure or NULL
4836  *
4837  * XL710 supports 128 smonVlanStats counters.This command is used to
4838  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4839  * switch.
4840  **/
4841 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4842                                 u16 vlan_id, u16 stat_index,
4843                                 struct i40e_asq_cmd_details *cmd_details)
4844 {
4845         struct i40e_aq_desc desc;
4846         struct i40e_aqc_add_remove_statistics *cmd =
4847                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4848         enum i40e_status_code status;
4849
4850         if (seid == 0)
4851                 return I40E_ERR_PARAM;
4852
4853         i40e_fill_default_direct_cmd_desc(&desc,
4854                                           i40e_aqc_opc_remove_statistics);
4855
4856         cmd->seid = CPU_TO_LE16(seid);
4857         cmd->vlan  = CPU_TO_LE16(vlan_id);
4858         cmd->stat_index = CPU_TO_LE16(stat_index);
4859
4860         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4861
4862         return status;
4863 }
4864
4865 /**
4866  * i40e_aq_set_port_parameters - set physical port parameters.
4867  * @hw: pointer to the hw struct
4868  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4869  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4870  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4871  * @double_vlan: if set double VLAN is enabled
4872  * @cmd_details: pointer to command details structure or NULL
4873  **/
4874 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4875                                 u16 bad_frame_vsi, bool save_bad_pac,
4876                                 bool pad_short_pac, bool double_vlan,
4877                                 struct i40e_asq_cmd_details *cmd_details)
4878 {
4879         struct i40e_aqc_set_port_parameters *cmd;
4880         enum i40e_status_code status;
4881         struct i40e_aq_desc desc;
4882         u16 command_flags = 0;
4883
4884         cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4885
4886         i40e_fill_default_direct_cmd_desc(&desc,
4887                                           i40e_aqc_opc_set_port_parameters);
4888
4889         cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4890         if (save_bad_pac)
4891                 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4892         if (pad_short_pac)
4893                 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4894         if (double_vlan)
4895                 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4896         cmd->command_flags = CPU_TO_LE16(command_flags);
4897
4898         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4899
4900         return status;
4901 }
4902
4903 /**
4904  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
4905  * @hw: pointer to the hw struct
4906  * @seid: seid for the physical port/switching component/vsi
4907  * @buff: Indirect buffer to hold data parameters and response
4908  * @buff_size: Indirect buffer size
4909  * @opcode: Tx scheduler AQ command opcode
4910  * @cmd_details: pointer to command details structure or NULL
4911  *
4912  * Generic command handler for Tx scheduler AQ commands
4913  **/
4914 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
4915                                 void *buff, u16 buff_size,
4916                                  enum i40e_admin_queue_opc opcode,
4917                                 struct i40e_asq_cmd_details *cmd_details)
4918 {
4919         struct i40e_aq_desc desc;
4920         struct i40e_aqc_tx_sched_ind *cmd =
4921                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4922         enum i40e_status_code status;
4923         bool cmd_param_flag = false;
4924
4925         switch (opcode) {
4926         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
4927         case i40e_aqc_opc_configure_vsi_tc_bw:
4928         case i40e_aqc_opc_enable_switching_comp_ets:
4929         case i40e_aqc_opc_modify_switching_comp_ets:
4930         case i40e_aqc_opc_disable_switching_comp_ets:
4931         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
4932         case i40e_aqc_opc_configure_switching_comp_bw_config:
4933                 cmd_param_flag = true;
4934                 break;
4935         case i40e_aqc_opc_query_vsi_bw_config:
4936         case i40e_aqc_opc_query_vsi_ets_sla_config:
4937         case i40e_aqc_opc_query_switching_comp_ets_config:
4938         case i40e_aqc_opc_query_port_ets_config:
4939         case i40e_aqc_opc_query_switching_comp_bw_config:
4940                 cmd_param_flag = false;
4941                 break;
4942         default:
4943                 return I40E_ERR_PARAM;
4944         }
4945
4946         i40e_fill_default_direct_cmd_desc(&desc, opcode);
4947
4948         /* Indirect command */
4949         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4950         if (cmd_param_flag)
4951                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4952         if (buff_size > I40E_AQ_LARGE_BUF)
4953                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4954
4955         desc.datalen = CPU_TO_LE16(buff_size);
4956
4957         cmd->vsi_seid = CPU_TO_LE16(seid);
4958
4959         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4960
4961         return status;
4962 }
4963
4964 /**
4965  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
4966  * @hw: pointer to the hw struct
4967  * @seid: VSI seid
4968  * @credit: BW limit credits (0 = disabled)
4969  * @max_credit: Max BW limit credits
4970  * @cmd_details: pointer to command details structure or NULL
4971  **/
4972 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
4973                                 u16 seid, u16 credit, u8 max_credit,
4974                                 struct i40e_asq_cmd_details *cmd_details)
4975 {
4976         struct i40e_aq_desc desc;
4977         struct i40e_aqc_configure_vsi_bw_limit *cmd =
4978                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
4979         enum i40e_status_code status;
4980
4981         i40e_fill_default_direct_cmd_desc(&desc,
4982                                           i40e_aqc_opc_configure_vsi_bw_limit);
4983
4984         cmd->vsi_seid = CPU_TO_LE16(seid);
4985         cmd->credit = CPU_TO_LE16(credit);
4986         cmd->max_credit = max_credit;
4987
4988         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4989
4990         return status;
4991 }
4992
4993 /**
4994  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
4995  * @hw: pointer to the hw struct
4996  * @seid: switching component seid
4997  * @credit: BW limit credits (0 = disabled)
4998  * @max_bw: Max BW limit credits
4999  * @cmd_details: pointer to command details structure or NULL
5000  **/
5001 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5002                                 u16 seid, u16 credit, u8 max_bw,
5003                                 struct i40e_asq_cmd_details *cmd_details)
5004 {
5005         struct i40e_aq_desc desc;
5006         struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5007           (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5008         enum i40e_status_code status;
5009
5010         i40e_fill_default_direct_cmd_desc(&desc,
5011                                 i40e_aqc_opc_configure_switching_comp_bw_limit);
5012
5013         cmd->seid = CPU_TO_LE16(seid);
5014         cmd->credit = CPU_TO_LE16(credit);
5015         cmd->max_bw = max_bw;
5016
5017         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5018
5019         return status;
5020 }
5021
5022 /**
5023  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5024  * @hw: pointer to the hw struct
5025  * @seid: VSI seid
5026  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5027  * @cmd_details: pointer to command details structure or NULL
5028  **/
5029 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5030                         u16 seid,
5031                         struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5032                         struct i40e_asq_cmd_details *cmd_details)
5033 {
5034         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5035                                     i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5036                                     cmd_details);
5037 }
5038
5039 /**
5040  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5041  * @hw: pointer to the hw struct
5042  * @seid: VSI seid
5043  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5044  * @cmd_details: pointer to command details structure or NULL
5045  **/
5046 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5047                         u16 seid,
5048                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5049                         struct i40e_asq_cmd_details *cmd_details)
5050 {
5051         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5052                                     i40e_aqc_opc_configure_vsi_tc_bw,
5053                                     cmd_details);
5054 }
5055
5056 /**
5057  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5058  * @hw: pointer to the hw struct
5059  * @seid: seid of the switching component connected to Physical Port
5060  * @ets_data: Buffer holding ETS parameters
5061  * @cmd_details: pointer to command details structure or NULL
5062  **/
5063 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5064                 u16 seid,
5065                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5066                 enum i40e_admin_queue_opc opcode,
5067                 struct i40e_asq_cmd_details *cmd_details)
5068 {
5069         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5070                                     sizeof(*ets_data), opcode, cmd_details);
5071 }
5072
5073 /**
5074  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5075  * @hw: pointer to the hw struct
5076  * @seid: seid of the switching component
5077  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5078  * @cmd_details: pointer to command details structure or NULL
5079  **/
5080 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5081         u16 seid,
5082         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5083         struct i40e_asq_cmd_details *cmd_details)
5084 {
5085         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5086                             i40e_aqc_opc_configure_switching_comp_bw_config,
5087                             cmd_details);
5088 }
5089
5090 /**
5091  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5092  * @hw: pointer to the hw struct
5093  * @seid: seid of the switching component
5094  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5095  * @cmd_details: pointer to command details structure or NULL
5096  **/
5097 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5098         struct i40e_hw *hw, u16 seid,
5099         struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5100         struct i40e_asq_cmd_details *cmd_details)
5101 {
5102         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5103                             i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5104                             cmd_details);
5105 }
5106
5107 /**
5108  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5109  * @hw: pointer to the hw struct
5110  * @seid: seid of the VSI
5111  * @bw_data: Buffer to hold VSI BW configuration
5112  * @cmd_details: pointer to command details structure or NULL
5113  **/
5114 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5115                         u16 seid,
5116                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5117                         struct i40e_asq_cmd_details *cmd_details)
5118 {
5119         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5120                                     i40e_aqc_opc_query_vsi_bw_config,
5121                                     cmd_details);
5122 }
5123
5124 /**
5125  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5126  * @hw: pointer to the hw struct
5127  * @seid: seid of the VSI
5128  * @bw_data: Buffer to hold VSI BW configuration per TC
5129  * @cmd_details: pointer to command details structure or NULL
5130  **/
5131 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5132                         u16 seid,
5133                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5134                         struct i40e_asq_cmd_details *cmd_details)
5135 {
5136         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5137                                     i40e_aqc_opc_query_vsi_ets_sla_config,
5138                                     cmd_details);
5139 }
5140
5141 /**
5142  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5143  * @hw: pointer to the hw struct
5144  * @seid: seid of the switching component
5145  * @bw_data: Buffer to hold switching component's per TC BW config
5146  * @cmd_details: pointer to command details structure or NULL
5147  **/
5148 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5149                 u16 seid,
5150                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5151                 struct i40e_asq_cmd_details *cmd_details)
5152 {
5153         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5154                                    i40e_aqc_opc_query_switching_comp_ets_config,
5155                                    cmd_details);
5156 }
5157
5158 /**
5159  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5160  * @hw: pointer to the hw struct
5161  * @seid: seid of the VSI or switching component connected to Physical Port
5162  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5163  * @cmd_details: pointer to command details structure or NULL
5164  **/
5165 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5166                         u16 seid,
5167                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
5168                         struct i40e_asq_cmd_details *cmd_details)
5169 {
5170         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5171                                     i40e_aqc_opc_query_port_ets_config,
5172                                     cmd_details);
5173 }
5174
5175 /**
5176  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5177  * @hw: pointer to the hw struct
5178  * @seid: seid of the switching component
5179  * @bw_data: Buffer to hold switching component's BW configuration
5180  * @cmd_details: pointer to command details structure or NULL
5181  **/
5182 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5183                 u16 seid,
5184                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5185                 struct i40e_asq_cmd_details *cmd_details)
5186 {
5187         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5188                                     i40e_aqc_opc_query_switching_comp_bw_config,
5189                                     cmd_details);
5190 }
5191
5192 /**
5193  * i40e_validate_filter_settings
5194  * @hw: pointer to the hardware structure
5195  * @settings: Filter control settings
5196  *
5197  * Check and validate the filter control settings passed.
5198  * The function checks for the valid filter/context sizes being
5199  * passed for FCoE and PE.
5200  *
5201  * Returns I40E_SUCCESS if the values passed are valid and within
5202  * range else returns an error.
5203  **/
5204 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5205                                 struct i40e_filter_control_settings *settings)
5206 {
5207         u32 fcoe_cntx_size, fcoe_filt_size;
5208         u32 pe_cntx_size, pe_filt_size;
5209         u32 fcoe_fmax;
5210
5211         u32 val;
5212
5213         /* Validate FCoE settings passed */
5214         switch (settings->fcoe_filt_num) {
5215         case I40E_HASH_FILTER_SIZE_1K:
5216         case I40E_HASH_FILTER_SIZE_2K:
5217         case I40E_HASH_FILTER_SIZE_4K:
5218         case I40E_HASH_FILTER_SIZE_8K:
5219         case I40E_HASH_FILTER_SIZE_16K:
5220         case I40E_HASH_FILTER_SIZE_32K:
5221                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5222                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5223                 break;
5224         default:
5225                 return I40E_ERR_PARAM;
5226         }
5227
5228         switch (settings->fcoe_cntx_num) {
5229         case I40E_DMA_CNTX_SIZE_512:
5230         case I40E_DMA_CNTX_SIZE_1K:
5231         case I40E_DMA_CNTX_SIZE_2K:
5232         case I40E_DMA_CNTX_SIZE_4K:
5233                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5234                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5235                 break;
5236         default:
5237                 return I40E_ERR_PARAM;
5238         }
5239
5240         /* Validate PE settings passed */
5241         switch (settings->pe_filt_num) {
5242         case I40E_HASH_FILTER_SIZE_1K:
5243         case I40E_HASH_FILTER_SIZE_2K:
5244         case I40E_HASH_FILTER_SIZE_4K:
5245         case I40E_HASH_FILTER_SIZE_8K:
5246         case I40E_HASH_FILTER_SIZE_16K:
5247         case I40E_HASH_FILTER_SIZE_32K:
5248         case I40E_HASH_FILTER_SIZE_64K:
5249         case I40E_HASH_FILTER_SIZE_128K:
5250         case I40E_HASH_FILTER_SIZE_256K:
5251         case I40E_HASH_FILTER_SIZE_512K:
5252         case I40E_HASH_FILTER_SIZE_1M:
5253                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5254                 pe_filt_size <<= (u32)settings->pe_filt_num;
5255                 break;
5256         default:
5257                 return I40E_ERR_PARAM;
5258         }
5259
5260         switch (settings->pe_cntx_num) {
5261         case I40E_DMA_CNTX_SIZE_512:
5262         case I40E_DMA_CNTX_SIZE_1K:
5263         case I40E_DMA_CNTX_SIZE_2K:
5264         case I40E_DMA_CNTX_SIZE_4K:
5265         case I40E_DMA_CNTX_SIZE_8K:
5266         case I40E_DMA_CNTX_SIZE_16K:
5267         case I40E_DMA_CNTX_SIZE_32K:
5268         case I40E_DMA_CNTX_SIZE_64K:
5269         case I40E_DMA_CNTX_SIZE_128K:
5270         case I40E_DMA_CNTX_SIZE_256K:
5271                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5272                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5273                 break;
5274         default:
5275                 return I40E_ERR_PARAM;
5276         }
5277
5278         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5279         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5280         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5281                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5282         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
5283                 return I40E_ERR_INVALID_SIZE;
5284
5285         return I40E_SUCCESS;
5286 }
5287
5288 /**
5289  * i40e_set_filter_control
5290  * @hw: pointer to the hardware structure
5291  * @settings: Filter control settings
5292  *
5293  * Set the Queue Filters for PE/FCoE and enable filters required
5294  * for a single PF. It is expected that these settings are programmed
5295  * at the driver initialization time.
5296  **/
5297 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5298                                 struct i40e_filter_control_settings *settings)
5299 {
5300         enum i40e_status_code ret = I40E_SUCCESS;
5301         u32 hash_lut_size = 0;
5302         u32 val;
5303
5304         if (!settings)
5305                 return I40E_ERR_PARAM;
5306
5307         /* Validate the input settings */
5308         ret = i40e_validate_filter_settings(hw, settings);
5309         if (ret)
5310                 return ret;
5311
5312         /* Read the PF Queue Filter control register */
5313         val = rd32(hw, I40E_PFQF_CTL_0);
5314
5315         /* Program required PE hash buckets for the PF */
5316         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5317         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5318                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5319         /* Program required PE contexts for the PF */
5320         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5321         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5322                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5323
5324         /* Program required FCoE hash buckets for the PF */
5325         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5326         val |= ((u32)settings->fcoe_filt_num <<
5327                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5328                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5329         /* Program required FCoE DDP contexts for the PF */
5330         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5331         val |= ((u32)settings->fcoe_cntx_num <<
5332                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5333                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5334
5335         /* Program Hash LUT size for the PF */
5336         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5337         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5338                 hash_lut_size = 1;
5339         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5340                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5341
5342         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5343         if (settings->enable_fdir)
5344                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5345         if (settings->enable_ethtype)
5346                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5347         if (settings->enable_macvlan)
5348                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5349
5350         wr32(hw, I40E_PFQF_CTL_0, val);
5351
5352         return I40E_SUCCESS;
5353 }
5354
5355 /**
5356  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5357  * @hw: pointer to the hw struct
5358  * @mac_addr: MAC address to use in the filter
5359  * @ethtype: Ethertype to use in the filter
5360  * @flags: Flags that needs to be applied to the filter
5361  * @vsi_seid: seid of the control VSI
5362  * @queue: VSI queue number to send the packet to
5363  * @is_add: Add control packet filter if True else remove
5364  * @stats: Structure to hold information on control filter counts
5365  * @cmd_details: pointer to command details structure or NULL
5366  *
5367  * This command will Add or Remove control packet filter for a control VSI.
5368  * In return it will update the total number of perfect filter count in
5369  * the stats member.
5370  **/
5371 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5372                                 u8 *mac_addr, u16 ethtype, u16 flags,
5373                                 u16 vsi_seid, u16 queue, bool is_add,
5374                                 struct i40e_control_filter_stats *stats,
5375                                 struct i40e_asq_cmd_details *cmd_details)
5376 {
5377         struct i40e_aq_desc desc;
5378         struct i40e_aqc_add_remove_control_packet_filter *cmd =
5379                 (struct i40e_aqc_add_remove_control_packet_filter *)
5380                 &desc.params.raw;
5381         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5382                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5383                 &desc.params.raw;
5384         enum i40e_status_code status;
5385
5386         if (vsi_seid == 0)
5387                 return I40E_ERR_PARAM;
5388
5389         if (is_add) {
5390                 i40e_fill_default_direct_cmd_desc(&desc,
5391                                 i40e_aqc_opc_add_control_packet_filter);
5392                 cmd->queue = CPU_TO_LE16(queue);
5393         } else {
5394                 i40e_fill_default_direct_cmd_desc(&desc,
5395                                 i40e_aqc_opc_remove_control_packet_filter);
5396         }
5397
5398         if (mac_addr)
5399                 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
5400                             I40E_NONDMA_TO_NONDMA);
5401
5402         cmd->etype = CPU_TO_LE16(ethtype);
5403         cmd->flags = CPU_TO_LE16(flags);
5404         cmd->seid = CPU_TO_LE16(vsi_seid);
5405
5406         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5407
5408         if (!status && stats) {
5409                 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5410                 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5411                 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5412                 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5413         }
5414
5415         return status;
5416 }
5417
5418 /**
5419  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5420  * @hw: pointer to the hw struct
5421  * @seid: VSI seid to add ethertype filter from
5422  **/
5423 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5424 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5425                                                     u16 seid)
5426 {
5427         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5428                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5429                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5430         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5431         enum i40e_status_code status;
5432
5433         status = i40e_aq_add_rem_control_packet_filter(hw, 0, ethtype, flag,
5434                                                        seid, 0, true, NULL,
5435                                                        NULL);
5436         if (status)
5437                 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5438 }
5439
5440 /**
5441  * i40e_aq_add_cloud_filters
5442  * @hw: pointer to the hardware structure
5443  * @seid: VSI seid to add cloud filters from
5444  * @filters: Buffer which contains the filters to be added
5445  * @filter_count: number of filters contained in the buffer
5446  *
5447  * Set the cloud filters for a given VSI.  The contents of the
5448  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5449  * in by the caller of the function.
5450  *
5451  **/
5452 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5453         u16 seid,
5454         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5455         u8 filter_count)
5456 {
5457         struct i40e_aq_desc desc;
5458         struct i40e_aqc_add_remove_cloud_filters *cmd =
5459         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5460         u16 buff_len;
5461         enum i40e_status_code status;
5462
5463         i40e_fill_default_direct_cmd_desc(&desc,
5464                                           i40e_aqc_opc_add_cloud_filters);
5465
5466         buff_len = filter_count * sizeof(*filters);
5467         desc.datalen = CPU_TO_LE16(buff_len);
5468         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5469         cmd->num_filters = filter_count;
5470         cmd->seid = CPU_TO_LE16(seid);
5471
5472         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5473
5474         return status;
5475 }
5476
5477 /**
5478  * i40e_aq_remove_cloud_filters
5479  * @hw: pointer to the hardware structure
5480  * @seid: VSI seid to remove cloud filters from
5481  * @filters: Buffer which contains the filters to be removed
5482  * @filter_count: number of filters contained in the buffer
5483  *
5484  * Remove the cloud filters for a given VSI.  The contents of the
5485  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5486  * in by the caller of the function.
5487  *
5488  **/
5489 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5490                 u16 seid,
5491                 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5492                 u8 filter_count)
5493 {
5494         struct i40e_aq_desc desc;
5495         struct i40e_aqc_add_remove_cloud_filters *cmd =
5496         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5497         enum i40e_status_code status;
5498         u16 buff_len;
5499
5500         i40e_fill_default_direct_cmd_desc(&desc,
5501                                           i40e_aqc_opc_remove_cloud_filters);
5502
5503         buff_len = filter_count * sizeof(*filters);
5504         desc.datalen = CPU_TO_LE16(buff_len);
5505         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5506         cmd->num_filters = filter_count;
5507         cmd->seid = CPU_TO_LE16(seid);
5508
5509         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5510
5511         return status;
5512 }
5513
5514 /**
5515  * i40e_aq_alternate_write
5516  * @hw: pointer to the hardware structure
5517  * @reg_addr0: address of first dword to be read
5518  * @reg_val0: value to be written under 'reg_addr0'
5519  * @reg_addr1: address of second dword to be read
5520  * @reg_val1: value to be written under 'reg_addr1'
5521  *
5522  * Write one or two dwords to alternate structure. Fields are indicated
5523  * by 'reg_addr0' and 'reg_addr1' register numbers.
5524  *
5525  **/
5526 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5527                                 u32 reg_addr0, u32 reg_val0,
5528                                 u32 reg_addr1, u32 reg_val1)
5529 {
5530         struct i40e_aq_desc desc;
5531         struct i40e_aqc_alternate_write *cmd_resp =
5532                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5533         enum i40e_status_code status;
5534
5535         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5536         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5537         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5538         cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5539         cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5540
5541         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5542
5543         return status;
5544 }
5545
5546 /**
5547  * i40e_aq_alternate_write_indirect
5548  * @hw: pointer to the hardware structure
5549  * @addr: address of a first register to be modified
5550  * @dw_count: number of alternate structure fields to write
5551  * @buffer: pointer to the command buffer
5552  *
5553  * Write 'dw_count' dwords from 'buffer' to alternate structure
5554  * starting at 'addr'.
5555  *
5556  **/
5557 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5558                                 u32 addr, u32 dw_count, void *buffer)
5559 {
5560         struct i40e_aq_desc desc;
5561         struct i40e_aqc_alternate_ind_write *cmd_resp =
5562                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5563         enum i40e_status_code status;
5564
5565         if (buffer == NULL)
5566                 return I40E_ERR_PARAM;
5567
5568         /* Indirect command */
5569         i40e_fill_default_direct_cmd_desc(&desc,
5570                                          i40e_aqc_opc_alternate_write_indirect);
5571
5572         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5573         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5574         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5575                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5576
5577         cmd_resp->address = CPU_TO_LE32(addr);
5578         cmd_resp->length = CPU_TO_LE32(dw_count);
5579
5580         status = i40e_asq_send_command(hw, &desc, buffer,
5581                                        I40E_LO_DWORD(4*dw_count), NULL);
5582
5583         return status;
5584 }
5585
5586 /**
5587  * i40e_aq_alternate_read
5588  * @hw: pointer to the hardware structure
5589  * @reg_addr0: address of first dword to be read
5590  * @reg_val0: pointer for data read from 'reg_addr0'
5591  * @reg_addr1: address of second dword to be read
5592  * @reg_val1: pointer for data read from 'reg_addr1'
5593  *
5594  * Read one or two dwords from alternate structure. Fields are indicated
5595  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5596  * is not passed then only register at 'reg_addr0' is read.
5597  *
5598  **/
5599 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5600                                 u32 reg_addr0, u32 *reg_val0,
5601                                 u32 reg_addr1, u32 *reg_val1)
5602 {
5603         struct i40e_aq_desc desc;
5604         struct i40e_aqc_alternate_write *cmd_resp =
5605                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5606         enum i40e_status_code status;
5607
5608         if (reg_val0 == NULL)
5609                 return I40E_ERR_PARAM;
5610
5611         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5612         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5613         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5614
5615         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5616
5617         if (status == I40E_SUCCESS) {
5618                 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5619
5620                 if (reg_val1 != NULL)
5621                         *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5622         }
5623
5624         return status;
5625 }
5626
5627 /**
5628  * i40e_aq_alternate_read_indirect
5629  * @hw: pointer to the hardware structure
5630  * @addr: address of the alternate structure field
5631  * @dw_count: number of alternate structure fields to read
5632  * @buffer: pointer to the command buffer
5633  *
5634  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5635  * place them in 'buffer'. The buffer should be allocated by caller.
5636  *
5637  **/
5638 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5639                                 u32 addr, u32 dw_count, void *buffer)
5640 {
5641         struct i40e_aq_desc desc;
5642         struct i40e_aqc_alternate_ind_write *cmd_resp =
5643                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5644         enum i40e_status_code status;
5645
5646         if (buffer == NULL)
5647                 return I40E_ERR_PARAM;
5648
5649         /* Indirect command */
5650         i40e_fill_default_direct_cmd_desc(&desc,
5651                 i40e_aqc_opc_alternate_read_indirect);
5652
5653         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5654         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5655         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5656                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5657
5658         cmd_resp->address = CPU_TO_LE32(addr);
5659         cmd_resp->length = CPU_TO_LE32(dw_count);
5660
5661         status = i40e_asq_send_command(hw, &desc, buffer,
5662                                        I40E_LO_DWORD(4*dw_count), NULL);
5663
5664         return status;
5665 }
5666
5667 /**
5668  *  i40e_aq_alternate_clear
5669  *  @hw: pointer to the HW structure.
5670  *
5671  *  Clear the alternate structures of the port from which the function
5672  *  is called.
5673  *
5674  **/
5675 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5676 {
5677         struct i40e_aq_desc desc;
5678         enum i40e_status_code status;
5679
5680         i40e_fill_default_direct_cmd_desc(&desc,
5681                                           i40e_aqc_opc_alternate_clear_port);
5682
5683         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5684
5685         return status;
5686 }
5687
5688 /**
5689  *  i40e_aq_alternate_write_done
5690  *  @hw: pointer to the HW structure.
5691  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
5692  *  @reset_needed: indicates the SW should trigger GLOBAL reset
5693  *
5694  *  Indicates to the FW that alternate structures have been changed.
5695  *
5696  **/
5697 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
5698                 u8 bios_mode, bool *reset_needed)
5699 {
5700         struct i40e_aq_desc desc;
5701         struct i40e_aqc_alternate_write_done *cmd =
5702                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5703         enum i40e_status_code status;
5704
5705         if (reset_needed == NULL)
5706                 return I40E_ERR_PARAM;
5707
5708         i40e_fill_default_direct_cmd_desc(&desc,
5709                                           i40e_aqc_opc_alternate_write_done);
5710
5711         cmd->cmd_flags = CPU_TO_LE16(bios_mode);
5712
5713         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5714         if (!status && reset_needed)
5715                 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
5716                                  I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
5717
5718         return status;
5719 }
5720
5721 /**
5722  *  i40e_aq_set_oem_mode
5723  *  @hw: pointer to the HW structure.
5724  *  @oem_mode: the OEM mode to be used
5725  *
5726  *  Sets the device to a specific operating mode. Currently the only supported
5727  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
5728  *
5729  **/
5730 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
5731                 u8 oem_mode)
5732 {
5733         struct i40e_aq_desc desc;
5734         struct i40e_aqc_alternate_write_done *cmd =
5735                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5736         enum i40e_status_code status;
5737
5738         i40e_fill_default_direct_cmd_desc(&desc,
5739                                           i40e_aqc_opc_alternate_set_mode);
5740
5741         cmd->cmd_flags = CPU_TO_LE16(oem_mode);
5742
5743         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5744
5745         return status;
5746 }
5747
5748 /**
5749  * i40e_aq_resume_port_tx
5750  * @hw: pointer to the hardware structure
5751  * @cmd_details: pointer to command details structure or NULL
5752  *
5753  * Resume port's Tx traffic
5754  **/
5755 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
5756                                 struct i40e_asq_cmd_details *cmd_details)
5757 {
5758         struct i40e_aq_desc desc;
5759         enum i40e_status_code status;
5760
5761         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
5762
5763         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5764
5765         return status;
5766 }
5767
5768 /**
5769  * i40e_set_pci_config_data - store PCI bus info
5770  * @hw: pointer to hardware structure
5771  * @link_status: the link status word from PCI config space
5772  *
5773  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
5774  **/
5775 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
5776 {
5777         hw->bus.type = i40e_bus_type_pci_express;
5778
5779         switch (link_status & I40E_PCI_LINK_WIDTH) {
5780         case I40E_PCI_LINK_WIDTH_1:
5781                 hw->bus.width = i40e_bus_width_pcie_x1;
5782                 break;
5783         case I40E_PCI_LINK_WIDTH_2:
5784                 hw->bus.width = i40e_bus_width_pcie_x2;
5785                 break;
5786         case I40E_PCI_LINK_WIDTH_4:
5787                 hw->bus.width = i40e_bus_width_pcie_x4;
5788                 break;
5789         case I40E_PCI_LINK_WIDTH_8:
5790                 hw->bus.width = i40e_bus_width_pcie_x8;
5791                 break;
5792         default:
5793                 hw->bus.width = i40e_bus_width_unknown;
5794                 break;
5795         }
5796
5797         switch (link_status & I40E_PCI_LINK_SPEED) {
5798         case I40E_PCI_LINK_SPEED_2500:
5799                 hw->bus.speed = i40e_bus_speed_2500;
5800                 break;
5801         case I40E_PCI_LINK_SPEED_5000:
5802                 hw->bus.speed = i40e_bus_speed_5000;
5803                 break;
5804         case I40E_PCI_LINK_SPEED_8000:
5805                 hw->bus.speed = i40e_bus_speed_8000;
5806                 break;
5807         default:
5808                 hw->bus.speed = i40e_bus_speed_unknown;
5809                 break;
5810         }
5811 }
5812
5813 /**
5814  * i40e_aq_debug_dump
5815  * @hw: pointer to the hardware structure
5816  * @cluster_id: specific cluster to dump
5817  * @table_id: table id within cluster
5818  * @start_index: index of line in the block to read
5819  * @buff_size: dump buffer size
5820  * @buff: dump buffer
5821  * @ret_buff_size: actual buffer size returned
5822  * @ret_next_table: next block to read
5823  * @ret_next_index: next index to read
5824  *
5825  * Dump internal FW/HW data for debug purposes.
5826  *
5827  **/
5828 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
5829                                 u8 table_id, u32 start_index, u16 buff_size,
5830                                 void *buff, u16 *ret_buff_size,
5831                                 u8 *ret_next_table, u32 *ret_next_index,
5832                                 struct i40e_asq_cmd_details *cmd_details)
5833 {
5834         struct i40e_aq_desc desc;
5835         struct i40e_aqc_debug_dump_internals *cmd =
5836                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5837         struct i40e_aqc_debug_dump_internals *resp =
5838                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5839         enum i40e_status_code status;
5840
5841         if (buff_size == 0 || !buff)
5842                 return I40E_ERR_PARAM;
5843
5844         i40e_fill_default_direct_cmd_desc(&desc,
5845                                           i40e_aqc_opc_debug_dump_internals);
5846         /* Indirect Command */
5847         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5848         if (buff_size > I40E_AQ_LARGE_BUF)
5849                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5850
5851         cmd->cluster_id = cluster_id;
5852         cmd->table_id = table_id;
5853         cmd->idx = CPU_TO_LE32(start_index);
5854
5855         desc.datalen = CPU_TO_LE16(buff_size);
5856
5857         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5858         if (!status) {
5859                 if (ret_buff_size != NULL)
5860                         *ret_buff_size = LE16_TO_CPU(desc.datalen);
5861                 if (ret_next_table != NULL)
5862                         *ret_next_table = resp->table_id;
5863                 if (ret_next_index != NULL)
5864                         *ret_next_index = LE32_TO_CPU(resp->idx);
5865         }
5866
5867         return status;
5868 }
5869
5870 /**
5871  * i40e_read_bw_from_alt_ram
5872  * @hw: pointer to the hardware structure
5873  * @max_bw: pointer for max_bw read
5874  * @min_bw: pointer for min_bw read
5875  * @min_valid: pointer for bool that is true if min_bw is a valid value
5876  * @max_valid: pointer for bool that is true if max_bw is a valid value
5877  *
5878  * Read bw from the alternate ram for the given pf
5879  **/
5880 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
5881                                         u32 *max_bw, u32 *min_bw,
5882                                         bool *min_valid, bool *max_valid)
5883 {
5884         enum i40e_status_code status;
5885         u32 max_bw_addr, min_bw_addr;
5886
5887         /* Calculate the address of the min/max bw registers */
5888         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5889                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
5890                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5891         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5892                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
5893                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5894
5895         /* Read the bandwidths from alt ram */
5896         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
5897                                         min_bw_addr, min_bw);
5898
5899         if (*min_bw & I40E_ALT_BW_VALID_MASK)
5900                 *min_valid = true;
5901         else
5902                 *min_valid = false;
5903
5904         if (*max_bw & I40E_ALT_BW_VALID_MASK)
5905                 *max_valid = true;
5906         else
5907                 *max_valid = false;
5908
5909         return status;
5910 }
5911
5912 /**
5913  * i40e_aq_configure_partition_bw
5914  * @hw: pointer to the hardware structure
5915  * @bw_data: Buffer holding valid pfs and bw limits
5916  * @cmd_details: pointer to command details
5917  *
5918  * Configure partitions guaranteed/max bw
5919  **/
5920 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
5921                         struct i40e_aqc_configure_partition_bw_data *bw_data,
5922                         struct i40e_asq_cmd_details *cmd_details)
5923 {
5924         enum i40e_status_code status;
5925         struct i40e_aq_desc desc;
5926         u16 bwd_size = sizeof(*bw_data);
5927
5928         i40e_fill_default_direct_cmd_desc(&desc,
5929                                 i40e_aqc_opc_configure_partition_bw);
5930
5931         /* Indirect command */
5932         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5933         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5934
5935         if (bwd_size > I40E_AQ_LARGE_BUF)
5936                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5937
5938         desc.datalen = CPU_TO_LE16(bwd_size);
5939
5940         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
5941
5942         return status;
5943 }
5944 #endif /* PF_DRIVER */
5945 #ifdef VF_DRIVER
5946
5947 /**
5948  * i40e_aq_send_msg_to_pf
5949  * @hw: pointer to the hardware structure
5950  * @v_opcode: opcodes for VF-PF communication
5951  * @v_retval: return error code
5952  * @msg: pointer to the msg buffer
5953  * @msglen: msg length
5954  * @cmd_details: pointer to command details
5955  *
5956  * Send message to PF driver using admin queue. By default, this message
5957  * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
5958  * completion before returning.
5959  **/
5960 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
5961                                 enum i40e_virtchnl_ops v_opcode,
5962                                 enum i40e_status_code v_retval,
5963                                 u8 *msg, u16 msglen,
5964                                 struct i40e_asq_cmd_details *cmd_details)
5965 {
5966         struct i40e_aq_desc desc;
5967         struct i40e_asq_cmd_details details;
5968         enum i40e_status_code status;
5969
5970         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
5971         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
5972         desc.cookie_high = CPU_TO_LE32(v_opcode);
5973         desc.cookie_low = CPU_TO_LE32(v_retval);
5974         if (msglen) {
5975                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
5976                                                 | I40E_AQ_FLAG_RD));
5977                 if (msglen > I40E_AQ_LARGE_BUF)
5978                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5979                 desc.datalen = CPU_TO_LE16(msglen);
5980         }
5981         if (!cmd_details) {
5982                 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
5983                 details.async = true;
5984                 cmd_details = &details;
5985         }
5986         status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
5987                                        msglen, cmd_details);
5988         return status;
5989 }
5990
5991 /**
5992  * i40e_vf_parse_hw_config
5993  * @hw: pointer to the hardware structure
5994  * @msg: pointer to the virtual channel VF resource structure
5995  *
5996  * Given a VF resource message from the PF, populate the hw struct
5997  * with appropriate information.
5998  **/
5999 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
6000                              struct i40e_virtchnl_vf_resource *msg)
6001 {
6002         struct i40e_virtchnl_vsi_resource *vsi_res;
6003         int i;
6004
6005         vsi_res = &msg->vsi_res[0];
6006
6007         hw->dev_caps.num_vsis = msg->num_vsis;
6008         hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
6009         hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
6010         hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
6011         hw->dev_caps.dcb = msg->vf_offload_flags &
6012                            I40E_VIRTCHNL_VF_OFFLOAD_L2;
6013         hw->dev_caps.fcoe = (msg->vf_offload_flags &
6014                              I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
6015         hw->dev_caps.iwarp = (msg->vf_offload_flags &
6016                               I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
6017         for (i = 0; i < msg->num_vsis; i++) {
6018                 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
6019                         i40e_memcpy(hw->mac.perm_addr,
6020                                     vsi_res->default_mac_addr,
6021                                     I40E_ETH_LENGTH_OF_ADDRESS,
6022                                     I40E_NONDMA_TO_NONDMA);
6023                         i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
6024                                     I40E_ETH_LENGTH_OF_ADDRESS,
6025                                     I40E_NONDMA_TO_NONDMA);
6026                 }
6027                 vsi_res++;
6028         }
6029 }
6030
6031 /**
6032  * i40e_vf_reset
6033  * @hw: pointer to the hardware structure
6034  *
6035  * Send a VF_RESET message to the PF. Does not wait for response from PF
6036  * as none will be forthcoming. Immediately after calling this function,
6037  * the admin queue should be shut down and (optionally) reinitialized.
6038  **/
6039 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
6040 {
6041         return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
6042                                       I40E_SUCCESS, NULL, 0, NULL);
6043 }
6044 #endif /* VF_DRIVER */
6045 #ifdef X722_SUPPORT
6046
6047 /**
6048  * i40e_aq_set_arp_proxy_config
6049  * @hw: pointer to the HW structure
6050  * @proxy_config - pointer to proxy config command table struct
6051  * @cmd_details: pointer to command details
6052  *
6053  * Set ARP offload parameters from pre-populated
6054  * i40e_aqc_arp_proxy_data struct
6055  **/
6056 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
6057                                 struct i40e_aqc_arp_proxy_data *proxy_config,
6058                                 struct i40e_asq_cmd_details *cmd_details)
6059 {
6060         struct i40e_aq_desc desc;
6061         enum i40e_status_code status;
6062
6063         if (!proxy_config)
6064                 return I40E_ERR_PARAM;
6065
6066         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
6067
6068         desc.params.external.addr_high =
6069                                   CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
6070         desc.params.external.addr_low =
6071                                   CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
6072
6073         status = i40e_asq_send_command(hw, &desc, proxy_config,
6074                                        sizeof(struct i40e_aqc_arp_proxy_data),
6075                                        cmd_details);
6076
6077         return status;
6078 }
6079
6080 /**
6081  * i40e_aq_opc_set_ns_proxy_table_entry
6082  * @hw: pointer to the HW structure
6083  * @ns_proxy_table_entry: pointer to NS table entry command struct
6084  * @cmd_details: pointer to command details
6085  *
6086  * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
6087  * from pre-populated i40e_aqc_ns_proxy_data struct
6088  **/
6089 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
6090                         struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
6091                         struct i40e_asq_cmd_details *cmd_details)
6092 {
6093         struct i40e_aq_desc desc;
6094         enum i40e_status_code status;
6095
6096         if (!ns_proxy_table_entry)
6097                 return I40E_ERR_PARAM;
6098
6099         i40e_fill_default_direct_cmd_desc(&desc,
6100                                 i40e_aqc_opc_set_ns_proxy_table_entry);
6101
6102         desc.params.external.addr_high =
6103                 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
6104         desc.params.external.addr_low =
6105                 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
6106
6107         status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
6108                                        sizeof(struct i40e_aqc_ns_proxy_data),
6109                                        cmd_details);
6110
6111         return status;
6112 }
6113
6114 /**
6115  * i40e_aq_set_clear_wol_filter
6116  * @hw: pointer to the hw struct
6117  * @filter_index: index of filter to modify (0-7)
6118  * @filter: buffer containing filter to be set
6119  * @set_filter: true to set filter, false to clear filter
6120  * @no_wol_tco: if true, pass through packets cannot cause wake-up
6121  *              if false, pass through packets may cause wake-up
6122  * @filter_valid: true if filter action is valid
6123  * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
6124  * @cmd_details: pointer to command details structure or NULL
6125  *
6126  * Set or clear WoL filter for port attached to the PF
6127  **/
6128 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
6129                                 u8 filter_index,
6130                                 struct i40e_aqc_set_wol_filter_data *filter,
6131                                 bool set_filter, bool no_wol_tco,
6132                                 bool filter_valid, bool no_wol_tco_valid,
6133                                 struct i40e_asq_cmd_details *cmd_details)
6134 {
6135         struct i40e_aq_desc desc;
6136         struct i40e_aqc_set_wol_filter *cmd =
6137                 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
6138         enum i40e_status_code status;
6139         u16 cmd_flags = 0;
6140         u16 valid_flags = 0;
6141         u16 buff_len = 0;
6142
6143         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
6144
6145         if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
6146                 return  I40E_ERR_PARAM;
6147         cmd->filter_index = CPU_TO_LE16(filter_index);
6148
6149         if (set_filter) {
6150                 if (!filter)
6151                         return  I40E_ERR_PARAM;
6152                 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
6153                 buff_len = sizeof(*filter);
6154         }
6155         if (no_wol_tco)
6156                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
6157         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
6158
6159         if (filter_valid)
6160                 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
6161         if (no_wol_tco_valid)
6162                 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
6163         cmd->valid_flags = CPU_TO_LE16(valid_flags);
6164
6165         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
6166         cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
6167
6168         status = i40e_asq_send_command(hw, &desc, filter,
6169                                        buff_len, cmd_details);
6170
6171         return status;
6172 }
6173
6174 /**
6175  * i40e_aq_get_wake_event_reason
6176  * @hw: pointer to the hw struct
6177  * @wake_reason: return value, index of matching filter
6178  * @cmd_details: pointer to command details structure or NULL
6179  *
6180  * Get information for the reason of a Wake Up event
6181  **/
6182 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
6183                                 u16 *wake_reason,
6184                                 struct i40e_asq_cmd_details *cmd_details)
6185 {
6186         struct i40e_aq_desc desc;
6187         struct i40e_aqc_get_wake_reason_completion *resp =
6188                 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
6189         enum i40e_status_code status;
6190
6191         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
6192
6193         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6194
6195         if (status == I40E_SUCCESS)
6196                 *wake_reason = LE16_TO_CPU(resp->wake_reason);
6197
6198         return status;
6199 }
6200
6201 #endif /* X722_SUPPORT */