1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "i40e_type.h"
35 #include "i40e_adminq.h"
36 #include "i40e_prototype.h"
37 #include "i40e_virtchnl.h"
41 * i40e_set_mac_type - Sets MAC type
42 * @hw: pointer to the HW structure
44 * This function sets the mac type of the adapter based on the
45 * vendor ID and device ID stored in the hw structure.
47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
53 enum i40e_status_code status = I40E_SUCCESS;
55 DEBUGFUNC("i40e_set_mac_type\n");
57 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
58 switch (hw->device_id) {
59 case I40E_DEV_ID_SFP_XL710:
60 case I40E_DEV_ID_QEMU:
61 case I40E_DEV_ID_KX_B:
62 case I40E_DEV_ID_KX_C:
63 case I40E_DEV_ID_QSFP_A:
64 case I40E_DEV_ID_QSFP_B:
65 case I40E_DEV_ID_QSFP_C:
66 case I40E_DEV_ID_10G_BASE_T:
67 case I40E_DEV_ID_10G_BASE_T4:
68 case I40E_DEV_ID_20G_KR2:
69 case I40E_DEV_ID_20G_KR2_A:
70 case I40E_DEV_ID_25G_B:
71 case I40E_DEV_ID_25G_SFP28:
72 hw->mac.type = I40E_MAC_XL710;
75 #ifdef X722_A0_SUPPORT
76 case I40E_DEV_ID_X722_A0:
78 case I40E_DEV_ID_KX_X722:
79 case I40E_DEV_ID_QSFP_X722:
80 case I40E_DEV_ID_SFP_X722:
81 case I40E_DEV_ID_1G_BASE_T_X722:
82 case I40E_DEV_ID_10G_BASE_T_X722:
83 case I40E_DEV_ID_SFP_I_X722:
84 case I40E_DEV_ID_QSFP_I_X722:
85 hw->mac.type = I40E_MAC_X722;
89 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
90 case I40E_DEV_ID_X722_VF:
91 case I40E_DEV_ID_X722_VF_HV:
92 #ifdef X722_A0_SUPPORT
93 case I40E_DEV_ID_X722_A0_VF:
95 hw->mac.type = I40E_MAC_X722_VF;
97 #endif /* INTEGRATED_VF || VF_DRIVER */
98 #endif /* X722_SUPPORT */
99 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
101 case I40E_DEV_ID_VF_HV:
102 hw->mac.type = I40E_MAC_VF;
106 hw->mac.type = I40E_MAC_GENERIC;
110 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
113 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
114 hw->mac.type, status);
118 #ifndef I40E_NDIS_SUPPORT
120 * i40e_aq_str - convert AQ err code to a string
121 * @hw: pointer to the HW structure
122 * @aq_err: the AQ error code to convert
124 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
129 case I40E_AQ_RC_EPERM:
130 return "I40E_AQ_RC_EPERM";
131 case I40E_AQ_RC_ENOENT:
132 return "I40E_AQ_RC_ENOENT";
133 case I40E_AQ_RC_ESRCH:
134 return "I40E_AQ_RC_ESRCH";
135 case I40E_AQ_RC_EINTR:
136 return "I40E_AQ_RC_EINTR";
138 return "I40E_AQ_RC_EIO";
139 case I40E_AQ_RC_ENXIO:
140 return "I40E_AQ_RC_ENXIO";
141 case I40E_AQ_RC_E2BIG:
142 return "I40E_AQ_RC_E2BIG";
143 case I40E_AQ_RC_EAGAIN:
144 return "I40E_AQ_RC_EAGAIN";
145 case I40E_AQ_RC_ENOMEM:
146 return "I40E_AQ_RC_ENOMEM";
147 case I40E_AQ_RC_EACCES:
148 return "I40E_AQ_RC_EACCES";
149 case I40E_AQ_RC_EFAULT:
150 return "I40E_AQ_RC_EFAULT";
151 case I40E_AQ_RC_EBUSY:
152 return "I40E_AQ_RC_EBUSY";
153 case I40E_AQ_RC_EEXIST:
154 return "I40E_AQ_RC_EEXIST";
155 case I40E_AQ_RC_EINVAL:
156 return "I40E_AQ_RC_EINVAL";
157 case I40E_AQ_RC_ENOTTY:
158 return "I40E_AQ_RC_ENOTTY";
159 case I40E_AQ_RC_ENOSPC:
160 return "I40E_AQ_RC_ENOSPC";
161 case I40E_AQ_RC_ENOSYS:
162 return "I40E_AQ_RC_ENOSYS";
163 case I40E_AQ_RC_ERANGE:
164 return "I40E_AQ_RC_ERANGE";
165 case I40E_AQ_RC_EFLUSHED:
166 return "I40E_AQ_RC_EFLUSHED";
167 case I40E_AQ_RC_BAD_ADDR:
168 return "I40E_AQ_RC_BAD_ADDR";
169 case I40E_AQ_RC_EMODE:
170 return "I40E_AQ_RC_EMODE";
171 case I40E_AQ_RC_EFBIG:
172 return "I40E_AQ_RC_EFBIG";
175 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
180 * i40e_stat_str - convert status err code to a string
181 * @hw: pointer to the HW structure
182 * @stat_err: the status error code to convert
184 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
190 return "I40E_ERR_NVM";
191 case I40E_ERR_NVM_CHECKSUM:
192 return "I40E_ERR_NVM_CHECKSUM";
194 return "I40E_ERR_PHY";
195 case I40E_ERR_CONFIG:
196 return "I40E_ERR_CONFIG";
198 return "I40E_ERR_PARAM";
199 case I40E_ERR_MAC_TYPE:
200 return "I40E_ERR_MAC_TYPE";
201 case I40E_ERR_UNKNOWN_PHY:
202 return "I40E_ERR_UNKNOWN_PHY";
203 case I40E_ERR_LINK_SETUP:
204 return "I40E_ERR_LINK_SETUP";
205 case I40E_ERR_ADAPTER_STOPPED:
206 return "I40E_ERR_ADAPTER_STOPPED";
207 case I40E_ERR_INVALID_MAC_ADDR:
208 return "I40E_ERR_INVALID_MAC_ADDR";
209 case I40E_ERR_DEVICE_NOT_SUPPORTED:
210 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
211 case I40E_ERR_MASTER_REQUESTS_PENDING:
212 return "I40E_ERR_MASTER_REQUESTS_PENDING";
213 case I40E_ERR_INVALID_LINK_SETTINGS:
214 return "I40E_ERR_INVALID_LINK_SETTINGS";
215 case I40E_ERR_AUTONEG_NOT_COMPLETE:
216 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
217 case I40E_ERR_RESET_FAILED:
218 return "I40E_ERR_RESET_FAILED";
219 case I40E_ERR_SWFW_SYNC:
220 return "I40E_ERR_SWFW_SYNC";
221 case I40E_ERR_NO_AVAILABLE_VSI:
222 return "I40E_ERR_NO_AVAILABLE_VSI";
223 case I40E_ERR_NO_MEMORY:
224 return "I40E_ERR_NO_MEMORY";
225 case I40E_ERR_BAD_PTR:
226 return "I40E_ERR_BAD_PTR";
227 case I40E_ERR_RING_FULL:
228 return "I40E_ERR_RING_FULL";
229 case I40E_ERR_INVALID_PD_ID:
230 return "I40E_ERR_INVALID_PD_ID";
231 case I40E_ERR_INVALID_QP_ID:
232 return "I40E_ERR_INVALID_QP_ID";
233 case I40E_ERR_INVALID_CQ_ID:
234 return "I40E_ERR_INVALID_CQ_ID";
235 case I40E_ERR_INVALID_CEQ_ID:
236 return "I40E_ERR_INVALID_CEQ_ID";
237 case I40E_ERR_INVALID_AEQ_ID:
238 return "I40E_ERR_INVALID_AEQ_ID";
239 case I40E_ERR_INVALID_SIZE:
240 return "I40E_ERR_INVALID_SIZE";
241 case I40E_ERR_INVALID_ARP_INDEX:
242 return "I40E_ERR_INVALID_ARP_INDEX";
243 case I40E_ERR_INVALID_FPM_FUNC_ID:
244 return "I40E_ERR_INVALID_FPM_FUNC_ID";
245 case I40E_ERR_QP_INVALID_MSG_SIZE:
246 return "I40E_ERR_QP_INVALID_MSG_SIZE";
247 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
248 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
249 case I40E_ERR_INVALID_FRAG_COUNT:
250 return "I40E_ERR_INVALID_FRAG_COUNT";
251 case I40E_ERR_QUEUE_EMPTY:
252 return "I40E_ERR_QUEUE_EMPTY";
253 case I40E_ERR_INVALID_ALIGNMENT:
254 return "I40E_ERR_INVALID_ALIGNMENT";
255 case I40E_ERR_FLUSHED_QUEUE:
256 return "I40E_ERR_FLUSHED_QUEUE";
257 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
258 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
259 case I40E_ERR_INVALID_IMM_DATA_SIZE:
260 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
261 case I40E_ERR_TIMEOUT:
262 return "I40E_ERR_TIMEOUT";
263 case I40E_ERR_OPCODE_MISMATCH:
264 return "I40E_ERR_OPCODE_MISMATCH";
265 case I40E_ERR_CQP_COMPL_ERROR:
266 return "I40E_ERR_CQP_COMPL_ERROR";
267 case I40E_ERR_INVALID_VF_ID:
268 return "I40E_ERR_INVALID_VF_ID";
269 case I40E_ERR_INVALID_HMCFN_ID:
270 return "I40E_ERR_INVALID_HMCFN_ID";
271 case I40E_ERR_BACKING_PAGE_ERROR:
272 return "I40E_ERR_BACKING_PAGE_ERROR";
273 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
274 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
275 case I40E_ERR_INVALID_PBLE_INDEX:
276 return "I40E_ERR_INVALID_PBLE_INDEX";
277 case I40E_ERR_INVALID_SD_INDEX:
278 return "I40E_ERR_INVALID_SD_INDEX";
279 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
280 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
281 case I40E_ERR_INVALID_SD_TYPE:
282 return "I40E_ERR_INVALID_SD_TYPE";
283 case I40E_ERR_MEMCPY_FAILED:
284 return "I40E_ERR_MEMCPY_FAILED";
285 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
286 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
287 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
288 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
289 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
290 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
291 case I40E_ERR_SRQ_ENABLED:
292 return "I40E_ERR_SRQ_ENABLED";
293 case I40E_ERR_ADMIN_QUEUE_ERROR:
294 return "I40E_ERR_ADMIN_QUEUE_ERROR";
295 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
296 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
297 case I40E_ERR_BUF_TOO_SHORT:
298 return "I40E_ERR_BUF_TOO_SHORT";
299 case I40E_ERR_ADMIN_QUEUE_FULL:
300 return "I40E_ERR_ADMIN_QUEUE_FULL";
301 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
302 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
303 case I40E_ERR_BAD_IWARP_CQE:
304 return "I40E_ERR_BAD_IWARP_CQE";
305 case I40E_ERR_NVM_BLANK_MODE:
306 return "I40E_ERR_NVM_BLANK_MODE";
307 case I40E_ERR_NOT_IMPLEMENTED:
308 return "I40E_ERR_NOT_IMPLEMENTED";
309 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
310 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
311 case I40E_ERR_DIAG_TEST_FAILED:
312 return "I40E_ERR_DIAG_TEST_FAILED";
313 case I40E_ERR_NOT_READY:
314 return "I40E_ERR_NOT_READY";
315 case I40E_NOT_SUPPORTED:
316 return "I40E_NOT_SUPPORTED";
317 case I40E_ERR_FIRMWARE_API_VERSION:
318 return "I40E_ERR_FIRMWARE_API_VERSION";
321 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
325 #endif /* I40E_NDIS_SUPPORT */
328 * @hw: debug mask related to admin queue
330 * @desc: pointer to admin queue descriptor
331 * @buffer: pointer to command buffer
332 * @buf_len: max length of buffer
334 * Dumps debug log about adminq command with descriptor contents.
336 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
337 void *buffer, u16 buf_len)
339 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
340 u16 len = LE16_TO_CPU(aq_desc->datalen);
341 u8 *buf = (u8 *)buffer;
344 if ((!(mask & hw->debug_mask)) || (desc == NULL))
348 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
349 LE16_TO_CPU(aq_desc->opcode),
350 LE16_TO_CPU(aq_desc->flags),
351 LE16_TO_CPU(aq_desc->datalen),
352 LE16_TO_CPU(aq_desc->retval));
353 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
354 LE32_TO_CPU(aq_desc->cookie_high),
355 LE32_TO_CPU(aq_desc->cookie_low));
356 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
357 LE32_TO_CPU(aq_desc->params.internal.param0),
358 LE32_TO_CPU(aq_desc->params.internal.param1));
359 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
360 LE32_TO_CPU(aq_desc->params.external.addr_high),
361 LE32_TO_CPU(aq_desc->params.external.addr_low));
363 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
364 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
367 /* write the full 16-byte chunks */
368 for (i = 0; i < (len - 16); i += 16)
370 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
371 i, buf[i], buf[i+1], buf[i+2], buf[i+3],
372 buf[i+4], buf[i+5], buf[i+6], buf[i+7],
373 buf[i+8], buf[i+9], buf[i+10], buf[i+11],
374 buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
375 /* the most we could have left is 16 bytes, pad with zeros */
381 memset(d_buf, 0, sizeof(d_buf));
382 for (j = 0; i < len; j++, i++)
385 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
386 i_sav, d_buf[0], d_buf[1],
388 d_buf[4], d_buf[5], d_buf[6], d_buf[7],
389 d_buf[8], d_buf[9], d_buf[10], d_buf[11],
390 d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
396 * i40e_check_asq_alive
397 * @hw: pointer to the hw struct
399 * Returns true if Queue is enabled else false.
401 bool i40e_check_asq_alive(struct i40e_hw *hw)
407 return !!(rd32(hw, hw->aq.asq.len) &
408 I40E_PF_ATQLEN_ATQENABLE_MASK);
410 return !!(rd32(hw, hw->aq.asq.len) &
411 I40E_PF_ATQLEN_ATQENABLE_MASK);
412 #endif /* INTEGRATED_VF */
413 #endif /* PF_DRIVER */
417 return !!(rd32(hw, hw->aq.asq.len) &
418 I40E_VF_ATQLEN1_ATQENABLE_MASK);
420 return !!(rd32(hw, hw->aq.asq.len) &
421 I40E_VF_ATQLEN1_ATQENABLE_MASK);
422 #endif /* INTEGRATED_VF */
423 #endif /* VF_DRIVER */
428 * i40e_aq_queue_shutdown
429 * @hw: pointer to the hw struct
430 * @unloading: is the driver unloading itself
432 * Tell the Firmware that we're shutting down the AdminQ and whether
433 * or not the driver is unloading as well.
435 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
438 struct i40e_aq_desc desc;
439 struct i40e_aqc_queue_shutdown *cmd =
440 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
441 enum i40e_status_code status;
443 i40e_fill_default_direct_cmd_desc(&desc,
444 i40e_aqc_opc_queue_shutdown);
447 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
448 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
455 * i40e_aq_get_set_rss_lut
456 * @hw: pointer to the hardware structure
457 * @vsi_id: vsi fw index
458 * @pf_lut: for PF table set true, for VSI table set false
459 * @lut: pointer to the lut buffer provided by the caller
460 * @lut_size: size of the lut buffer
461 * @set: set true to set the table, false to get the table
463 * Internal function to get or set RSS look up table
465 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
466 u16 vsi_id, bool pf_lut,
467 u8 *lut, u16 lut_size,
470 enum i40e_status_code status;
471 struct i40e_aq_desc desc;
472 struct i40e_aqc_get_set_rss_lut *cmd_resp =
473 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
476 i40e_fill_default_direct_cmd_desc(&desc,
477 i40e_aqc_opc_set_rss_lut);
479 i40e_fill_default_direct_cmd_desc(&desc,
480 i40e_aqc_opc_get_rss_lut);
482 /* Indirect command */
483 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
484 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
487 CPU_TO_LE16((u16)((vsi_id <<
488 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
489 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
490 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
493 cmd_resp->flags |= CPU_TO_LE16((u16)
494 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
495 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
496 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
498 cmd_resp->flags |= CPU_TO_LE16((u16)
499 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
500 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
501 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
503 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
509 * i40e_aq_get_rss_lut
510 * @hw: pointer to the hardware structure
511 * @vsi_id: vsi fw index
512 * @pf_lut: for PF table set true, for VSI table set false
513 * @lut: pointer to the lut buffer provided by the caller
514 * @lut_size: size of the lut buffer
516 * get the RSS lookup table, PF or VSI type
518 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
519 bool pf_lut, u8 *lut, u16 lut_size)
521 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
526 * i40e_aq_set_rss_lut
527 * @hw: pointer to the hardware structure
528 * @vsi_id: vsi fw index
529 * @pf_lut: for PF table set true, for VSI table set false
530 * @lut: pointer to the lut buffer provided by the caller
531 * @lut_size: size of the lut buffer
533 * set the RSS lookup table, PF or VSI type
535 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
536 bool pf_lut, u8 *lut, u16 lut_size)
538 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
542 * i40e_aq_get_set_rss_key
543 * @hw: pointer to the hw struct
544 * @vsi_id: vsi fw index
545 * @key: pointer to key info struct
546 * @set: set true to set the key, false to get the key
548 * get the RSS key per VSI
550 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
552 struct i40e_aqc_get_set_rss_key_data *key,
555 enum i40e_status_code status;
556 struct i40e_aq_desc desc;
557 struct i40e_aqc_get_set_rss_key *cmd_resp =
558 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
559 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
562 i40e_fill_default_direct_cmd_desc(&desc,
563 i40e_aqc_opc_set_rss_key);
565 i40e_fill_default_direct_cmd_desc(&desc,
566 i40e_aqc_opc_get_rss_key);
568 /* Indirect command */
569 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
570 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
573 CPU_TO_LE16((u16)((vsi_id <<
574 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
575 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
576 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
578 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
584 * i40e_aq_get_rss_key
585 * @hw: pointer to the hw struct
586 * @vsi_id: vsi fw index
587 * @key: pointer to key info struct
590 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
592 struct i40e_aqc_get_set_rss_key_data *key)
594 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
598 * i40e_aq_set_rss_key
599 * @hw: pointer to the hw struct
600 * @vsi_id: vsi fw index
601 * @key: pointer to key info struct
603 * set the RSS key per VSI
605 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
607 struct i40e_aqc_get_set_rss_key_data *key)
609 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
611 #endif /* X722_SUPPORT */
613 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
614 * hardware to a bit-field that can be used by SW to more easily determine the
617 * Macros are used to shorten the table lines and make this table human
620 * We store the PTYPE in the top byte of the bit field - this is just so that
621 * we can check that the table doesn't have a row missing, as the index into
622 * the table should be the PTYPE.
626 * IF NOT i40e_ptype_lookup[ptype].known
629 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
630 * Use the rest of the fields to look at the tunnels, inner protocols, etc
632 * Use the enum i40e_rx_l2_ptype to decode the packet type
636 /* macro to make the table lines short */
637 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
640 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
641 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
642 I40E_RX_PTYPE_##OUTER_FRAG, \
643 I40E_RX_PTYPE_TUNNEL_##T, \
644 I40E_RX_PTYPE_TUNNEL_END_##TE, \
645 I40E_RX_PTYPE_##TEF, \
646 I40E_RX_PTYPE_INNER_PROT_##I, \
647 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
649 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
650 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
652 /* shorter macros makes the table fit but are terse */
653 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
654 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
655 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
657 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
658 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
659 /* L2 Packet types */
660 I40E_PTT_UNUSED_ENTRY(0),
661 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
662 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
663 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
664 I40E_PTT_UNUSED_ENTRY(4),
665 I40E_PTT_UNUSED_ENTRY(5),
666 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
667 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
668 I40E_PTT_UNUSED_ENTRY(8),
669 I40E_PTT_UNUSED_ENTRY(9),
670 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
671 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
672 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
673 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
674 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
675 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
676 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
677 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
678 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
679 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
680 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
681 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
683 /* Non Tunneled IPv4 */
684 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
685 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
686 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
687 I40E_PTT_UNUSED_ENTRY(25),
688 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
689 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
690 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
693 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
694 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
695 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
696 I40E_PTT_UNUSED_ENTRY(32),
697 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
698 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
699 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
702 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
703 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
704 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
705 I40E_PTT_UNUSED_ENTRY(39),
706 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
707 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
708 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
710 /* IPv4 --> GRE/NAT */
711 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
713 /* IPv4 --> GRE/NAT --> IPv4 */
714 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
715 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
716 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
717 I40E_PTT_UNUSED_ENTRY(47),
718 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
719 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
720 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
722 /* IPv4 --> GRE/NAT --> IPv6 */
723 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
724 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
725 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
726 I40E_PTT_UNUSED_ENTRY(54),
727 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
728 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
729 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
731 /* IPv4 --> GRE/NAT --> MAC */
732 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
734 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
735 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
736 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
737 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
738 I40E_PTT_UNUSED_ENTRY(62),
739 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
740 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
741 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
743 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
744 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
745 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
746 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
747 I40E_PTT_UNUSED_ENTRY(69),
748 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
749 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
750 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
752 /* IPv4 --> GRE/NAT --> MAC/VLAN */
753 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
755 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
756 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
757 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
758 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
759 I40E_PTT_UNUSED_ENTRY(77),
760 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
761 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
762 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
764 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
765 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
766 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
767 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
768 I40E_PTT_UNUSED_ENTRY(84),
769 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
770 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
771 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
773 /* Non Tunneled IPv6 */
774 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
775 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
776 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4),
777 I40E_PTT_UNUSED_ENTRY(91),
778 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
779 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
780 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
783 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
784 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
785 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
786 I40E_PTT_UNUSED_ENTRY(98),
787 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
788 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
789 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
792 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
793 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
794 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
795 I40E_PTT_UNUSED_ENTRY(105),
796 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
797 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
798 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
800 /* IPv6 --> GRE/NAT */
801 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
803 /* IPv6 --> GRE/NAT -> IPv4 */
804 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
805 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
806 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
807 I40E_PTT_UNUSED_ENTRY(113),
808 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
809 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
810 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
812 /* IPv6 --> GRE/NAT -> IPv6 */
813 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
814 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
815 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
816 I40E_PTT_UNUSED_ENTRY(120),
817 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
818 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
819 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
821 /* IPv6 --> GRE/NAT -> MAC */
822 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
824 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
825 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
826 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
827 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
828 I40E_PTT_UNUSED_ENTRY(128),
829 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
830 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
831 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
833 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
834 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
835 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
836 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
837 I40E_PTT_UNUSED_ENTRY(135),
838 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
839 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
840 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
842 /* IPv6 --> GRE/NAT -> MAC/VLAN */
843 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
845 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
846 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
847 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
848 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
849 I40E_PTT_UNUSED_ENTRY(143),
850 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
851 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
852 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
854 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
855 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
856 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
857 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
858 I40E_PTT_UNUSED_ENTRY(150),
859 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
860 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
861 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
864 I40E_PTT_UNUSED_ENTRY(154),
865 I40E_PTT_UNUSED_ENTRY(155),
866 I40E_PTT_UNUSED_ENTRY(156),
867 I40E_PTT_UNUSED_ENTRY(157),
868 I40E_PTT_UNUSED_ENTRY(158),
869 I40E_PTT_UNUSED_ENTRY(159),
871 I40E_PTT_UNUSED_ENTRY(160),
872 I40E_PTT_UNUSED_ENTRY(161),
873 I40E_PTT_UNUSED_ENTRY(162),
874 I40E_PTT_UNUSED_ENTRY(163),
875 I40E_PTT_UNUSED_ENTRY(164),
876 I40E_PTT_UNUSED_ENTRY(165),
877 I40E_PTT_UNUSED_ENTRY(166),
878 I40E_PTT_UNUSED_ENTRY(167),
879 I40E_PTT_UNUSED_ENTRY(168),
880 I40E_PTT_UNUSED_ENTRY(169),
882 I40E_PTT_UNUSED_ENTRY(170),
883 I40E_PTT_UNUSED_ENTRY(171),
884 I40E_PTT_UNUSED_ENTRY(172),
885 I40E_PTT_UNUSED_ENTRY(173),
886 I40E_PTT_UNUSED_ENTRY(174),
887 I40E_PTT_UNUSED_ENTRY(175),
888 I40E_PTT_UNUSED_ENTRY(176),
889 I40E_PTT_UNUSED_ENTRY(177),
890 I40E_PTT_UNUSED_ENTRY(178),
891 I40E_PTT_UNUSED_ENTRY(179),
893 I40E_PTT_UNUSED_ENTRY(180),
894 I40E_PTT_UNUSED_ENTRY(181),
895 I40E_PTT_UNUSED_ENTRY(182),
896 I40E_PTT_UNUSED_ENTRY(183),
897 I40E_PTT_UNUSED_ENTRY(184),
898 I40E_PTT_UNUSED_ENTRY(185),
899 I40E_PTT_UNUSED_ENTRY(186),
900 I40E_PTT_UNUSED_ENTRY(187),
901 I40E_PTT_UNUSED_ENTRY(188),
902 I40E_PTT_UNUSED_ENTRY(189),
904 I40E_PTT_UNUSED_ENTRY(190),
905 I40E_PTT_UNUSED_ENTRY(191),
906 I40E_PTT_UNUSED_ENTRY(192),
907 I40E_PTT_UNUSED_ENTRY(193),
908 I40E_PTT_UNUSED_ENTRY(194),
909 I40E_PTT_UNUSED_ENTRY(195),
910 I40E_PTT_UNUSED_ENTRY(196),
911 I40E_PTT_UNUSED_ENTRY(197),
912 I40E_PTT_UNUSED_ENTRY(198),
913 I40E_PTT_UNUSED_ENTRY(199),
915 I40E_PTT_UNUSED_ENTRY(200),
916 I40E_PTT_UNUSED_ENTRY(201),
917 I40E_PTT_UNUSED_ENTRY(202),
918 I40E_PTT_UNUSED_ENTRY(203),
919 I40E_PTT_UNUSED_ENTRY(204),
920 I40E_PTT_UNUSED_ENTRY(205),
921 I40E_PTT_UNUSED_ENTRY(206),
922 I40E_PTT_UNUSED_ENTRY(207),
923 I40E_PTT_UNUSED_ENTRY(208),
924 I40E_PTT_UNUSED_ENTRY(209),
926 I40E_PTT_UNUSED_ENTRY(210),
927 I40E_PTT_UNUSED_ENTRY(211),
928 I40E_PTT_UNUSED_ENTRY(212),
929 I40E_PTT_UNUSED_ENTRY(213),
930 I40E_PTT_UNUSED_ENTRY(214),
931 I40E_PTT_UNUSED_ENTRY(215),
932 I40E_PTT_UNUSED_ENTRY(216),
933 I40E_PTT_UNUSED_ENTRY(217),
934 I40E_PTT_UNUSED_ENTRY(218),
935 I40E_PTT_UNUSED_ENTRY(219),
937 I40E_PTT_UNUSED_ENTRY(220),
938 I40E_PTT_UNUSED_ENTRY(221),
939 I40E_PTT_UNUSED_ENTRY(222),
940 I40E_PTT_UNUSED_ENTRY(223),
941 I40E_PTT_UNUSED_ENTRY(224),
942 I40E_PTT_UNUSED_ENTRY(225),
943 I40E_PTT_UNUSED_ENTRY(226),
944 I40E_PTT_UNUSED_ENTRY(227),
945 I40E_PTT_UNUSED_ENTRY(228),
946 I40E_PTT_UNUSED_ENTRY(229),
948 I40E_PTT_UNUSED_ENTRY(230),
949 I40E_PTT_UNUSED_ENTRY(231),
950 I40E_PTT_UNUSED_ENTRY(232),
951 I40E_PTT_UNUSED_ENTRY(233),
952 I40E_PTT_UNUSED_ENTRY(234),
953 I40E_PTT_UNUSED_ENTRY(235),
954 I40E_PTT_UNUSED_ENTRY(236),
955 I40E_PTT_UNUSED_ENTRY(237),
956 I40E_PTT_UNUSED_ENTRY(238),
957 I40E_PTT_UNUSED_ENTRY(239),
959 I40E_PTT_UNUSED_ENTRY(240),
960 I40E_PTT_UNUSED_ENTRY(241),
961 I40E_PTT_UNUSED_ENTRY(242),
962 I40E_PTT_UNUSED_ENTRY(243),
963 I40E_PTT_UNUSED_ENTRY(244),
964 I40E_PTT_UNUSED_ENTRY(245),
965 I40E_PTT_UNUSED_ENTRY(246),
966 I40E_PTT_UNUSED_ENTRY(247),
967 I40E_PTT_UNUSED_ENTRY(248),
968 I40E_PTT_UNUSED_ENTRY(249),
970 I40E_PTT_UNUSED_ENTRY(250),
971 I40E_PTT_UNUSED_ENTRY(251),
972 I40E_PTT_UNUSED_ENTRY(252),
973 I40E_PTT_UNUSED_ENTRY(253),
974 I40E_PTT_UNUSED_ENTRY(254),
975 I40E_PTT_UNUSED_ENTRY(255)
980 * i40e_validate_mac_addr - Validate unicast MAC address
981 * @mac_addr: pointer to MAC address
983 * Tests a MAC address to ensure it is a valid Individual Address
985 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
987 enum i40e_status_code status = I40E_SUCCESS;
989 DEBUGFUNC("i40e_validate_mac_addr");
991 /* Broadcast addresses ARE multicast addresses
992 * Make sure it is not a multicast address
993 * Reject the zero address
995 if (I40E_IS_MULTICAST(mac_addr) ||
996 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
997 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
998 status = I40E_ERR_INVALID_MAC_ADDR;
1005 * i40e_init_shared_code - Initialize the shared code
1006 * @hw: pointer to hardware structure
1008 * This assigns the MAC type and PHY code and inits the NVM.
1009 * Does not touch the hardware. This function must be called prior to any
1010 * other function in the shared code. The i40e_hw structure should be
1011 * memset to 0 prior to calling this function. The following fields in
1012 * hw structure should be filled in prior to calling this function:
1013 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1014 * subsystem_vendor_id, and revision_id
1016 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
1018 enum i40e_status_code status = I40E_SUCCESS;
1019 u32 port, ari, func_rid;
1021 DEBUGFUNC("i40e_init_shared_code");
1023 i40e_set_mac_type(hw);
1025 switch (hw->mac.type) {
1026 case I40E_MAC_XL710:
1032 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1035 hw->phy.get_link_info = true;
1037 /* Determine port number and PF number*/
1038 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1039 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1040 hw->port = (u8)port;
1041 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1042 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1043 func_rid = rd32(hw, I40E_PF_FUNC_RID);
1045 hw->pf_id = (u8)(func_rid & 0xff);
1047 hw->pf_id = (u8)(func_rid & 0x7);
1050 if (hw->mac.type == I40E_MAC_X722)
1051 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
1054 status = i40e_init_nvm(hw);
1059 * i40e_aq_mac_address_read - Retrieve the MAC addresses
1060 * @hw: pointer to the hw struct
1061 * @flags: a return indicator of what addresses were added to the addr store
1062 * @addrs: the requestor's mac addr store
1063 * @cmd_details: pointer to command details structure or NULL
1065 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1067 struct i40e_aqc_mac_address_read_data *addrs,
1068 struct i40e_asq_cmd_details *cmd_details)
1070 struct i40e_aq_desc desc;
1071 struct i40e_aqc_mac_address_read *cmd_data =
1072 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1073 enum i40e_status_code status;
1075 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1076 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1078 status = i40e_asq_send_command(hw, &desc, addrs,
1079 sizeof(*addrs), cmd_details);
1080 *flags = LE16_TO_CPU(cmd_data->command_flags);
1086 * i40e_aq_mac_address_write - Change the MAC addresses
1087 * @hw: pointer to the hw struct
1088 * @flags: indicates which MAC to be written
1089 * @mac_addr: address to write
1090 * @cmd_details: pointer to command details structure or NULL
1092 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1093 u16 flags, u8 *mac_addr,
1094 struct i40e_asq_cmd_details *cmd_details)
1096 struct i40e_aq_desc desc;
1097 struct i40e_aqc_mac_address_write *cmd_data =
1098 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1099 enum i40e_status_code status;
1101 i40e_fill_default_direct_cmd_desc(&desc,
1102 i40e_aqc_opc_mac_address_write);
1103 cmd_data->command_flags = CPU_TO_LE16(flags);
1104 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1105 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1106 ((u32)mac_addr[3] << 16) |
1107 ((u32)mac_addr[4] << 8) |
1110 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1116 * i40e_get_mac_addr - get MAC address
1117 * @hw: pointer to the HW structure
1118 * @mac_addr: pointer to MAC address
1120 * Reads the adapter's MAC address from register
1122 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1124 struct i40e_aqc_mac_address_read_data addrs;
1125 enum i40e_status_code status;
1128 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1130 if (flags & I40E_AQC_LAN_ADDR_VALID)
1131 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
1137 * i40e_get_port_mac_addr - get Port MAC address
1138 * @hw: pointer to the HW structure
1139 * @mac_addr: pointer to Port MAC address
1141 * Reads the adapter's Port MAC address
1143 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1145 struct i40e_aqc_mac_address_read_data addrs;
1146 enum i40e_status_code status;
1149 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1153 if (flags & I40E_AQC_PORT_ADDR_VALID)
1154 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
1156 status = I40E_ERR_INVALID_MAC_ADDR;
1162 * i40e_pre_tx_queue_cfg - pre tx queue configure
1163 * @hw: pointer to the HW structure
1164 * @queue: target pf queue index
1165 * @enable: state change request
1167 * Handles hw requirement to indicate intention to enable
1168 * or disable target queue.
1170 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1172 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1176 if (abs_queue_idx >= 128) {
1177 reg_block = abs_queue_idx / 128;
1178 abs_queue_idx %= 128;
1181 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1182 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1183 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1186 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1188 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1190 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1194 * i40e_read_pba_string - Reads part number string from EEPROM
1195 * @hw: pointer to hardware structure
1196 * @pba_num: stores the part number string from the EEPROM
1197 * @pba_num_size: part number string buffer length
1199 * Reads the part number string from the EEPROM.
1201 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1204 enum i40e_status_code status = I40E_SUCCESS;
1210 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1211 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1212 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1216 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1217 if (status != I40E_SUCCESS) {
1218 DEBUGOUT("Failed to read PBA Block pointer.\n");
1222 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1223 if (status != I40E_SUCCESS) {
1224 DEBUGOUT("Failed to read PBA Block size.\n");
1228 /* Subtract one to get PBA word count (PBA Size word is included in
1232 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1233 DEBUGOUT("Buffer to small for PBA data.\n");
1234 return I40E_ERR_PARAM;
1237 for (i = 0; i < pba_size; i++) {
1238 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1239 if (status != I40E_SUCCESS) {
1240 DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1244 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1245 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1247 pba_num[(pba_size * 2)] = '\0';
1253 * i40e_get_media_type - Gets media type
1254 * @hw: pointer to the hardware structure
1256 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1258 enum i40e_media_type media;
1260 switch (hw->phy.link_info.phy_type) {
1261 case I40E_PHY_TYPE_10GBASE_SR:
1262 case I40E_PHY_TYPE_10GBASE_LR:
1263 case I40E_PHY_TYPE_1000BASE_SX:
1264 case I40E_PHY_TYPE_1000BASE_LX:
1265 case I40E_PHY_TYPE_40GBASE_SR4:
1266 case I40E_PHY_TYPE_40GBASE_LR4:
1267 media = I40E_MEDIA_TYPE_FIBER;
1269 case I40E_PHY_TYPE_100BASE_TX:
1270 case I40E_PHY_TYPE_1000BASE_T:
1271 case I40E_PHY_TYPE_10GBASE_T:
1272 media = I40E_MEDIA_TYPE_BASET;
1274 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1275 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1276 case I40E_PHY_TYPE_10GBASE_CR1:
1277 case I40E_PHY_TYPE_40GBASE_CR4:
1278 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1279 case I40E_PHY_TYPE_40GBASE_AOC:
1280 case I40E_PHY_TYPE_10GBASE_AOC:
1281 media = I40E_MEDIA_TYPE_DA;
1283 case I40E_PHY_TYPE_1000BASE_KX:
1284 case I40E_PHY_TYPE_10GBASE_KX4:
1285 case I40E_PHY_TYPE_10GBASE_KR:
1286 case I40E_PHY_TYPE_40GBASE_KR4:
1287 case I40E_PHY_TYPE_20GBASE_KR2:
1288 media = I40E_MEDIA_TYPE_BACKPLANE;
1290 case I40E_PHY_TYPE_SGMII:
1291 case I40E_PHY_TYPE_XAUI:
1292 case I40E_PHY_TYPE_XFI:
1293 case I40E_PHY_TYPE_XLAUI:
1294 case I40E_PHY_TYPE_XLPPI:
1296 media = I40E_MEDIA_TYPE_UNKNOWN;
1303 #define I40E_PF_RESET_WAIT_COUNT 200
1305 * i40e_pf_reset - Reset the PF
1306 * @hw: pointer to the hardware structure
1308 * Assuming someone else has triggered a global reset,
1309 * assure the global reset is complete and then reset the PF
1311 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1318 /* Poll for Global Reset steady state in case of recent GRST.
1319 * The grst delay value is in 100ms units, and we'll wait a
1320 * couple counts longer to be sure we don't just miss the end.
1322 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1323 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1324 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1326 grst_del = grst_del * 20;
1328 for (cnt = 0; cnt < grst_del; cnt++) {
1329 reg = rd32(hw, I40E_GLGEN_RSTAT);
1330 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1332 i40e_msec_delay(100);
1334 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1335 DEBUGOUT("Global reset polling failed to complete.\n");
1336 return I40E_ERR_RESET_FAILED;
1339 /* Now Wait for the FW to be ready */
1340 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1341 reg = rd32(hw, I40E_GLNVM_ULD);
1342 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1343 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1344 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1345 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1346 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1349 i40e_msec_delay(10);
1351 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1352 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1353 DEBUGOUT("wait for FW Reset complete timedout\n");
1354 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1355 return I40E_ERR_RESET_FAILED;
1358 /* If there was a Global Reset in progress when we got here,
1359 * we don't need to do the PF Reset
1362 reg = rd32(hw, I40E_PFGEN_CTRL);
1363 wr32(hw, I40E_PFGEN_CTRL,
1364 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1365 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1366 reg = rd32(hw, I40E_PFGEN_CTRL);
1367 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1371 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1372 DEBUGOUT("PF reset polling failed to complete.\n");
1373 return I40E_ERR_RESET_FAILED;
1377 i40e_clear_pxe_mode(hw);
1380 return I40E_SUCCESS;
1384 * i40e_clear_hw - clear out any left over hw state
1385 * @hw: pointer to the hw struct
1387 * Clear queues and interrupts, typically called at init time,
1388 * but after the capabilities have been found so we know how many
1389 * queues and msix vectors have been allocated.
1391 void i40e_clear_hw(struct i40e_hw *hw)
1393 u32 num_queues, base_queue;
1401 /* get number of interrupts, queues, and vfs */
1402 val = rd32(hw, I40E_GLPCI_CNF2);
1403 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1404 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1405 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1406 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1408 val = rd32(hw, I40E_PFLAN_QALLOC);
1409 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1410 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1411 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1412 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1413 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1414 num_queues = (j - base_queue) + 1;
1418 val = rd32(hw, I40E_PF_VT_PFALLOC);
1419 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1420 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1421 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1422 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1423 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1424 num_vfs = (j - i) + 1;
1428 /* stop all the interrupts */
1429 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1430 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1431 for (i = 0; i < num_pf_int - 2; i++)
1432 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1434 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1435 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1436 wr32(hw, I40E_PFINT_LNKLST0, val);
1437 for (i = 0; i < num_pf_int - 2; i++)
1438 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1439 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1440 for (i = 0; i < num_vfs; i++)
1441 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1442 for (i = 0; i < num_vf_int - 2; i++)
1443 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1445 /* warn the HW of the coming Tx disables */
1446 for (i = 0; i < num_queues; i++) {
1447 u32 abs_queue_idx = base_queue + i;
1450 if (abs_queue_idx >= 128) {
1451 reg_block = abs_queue_idx / 128;
1452 abs_queue_idx %= 128;
1455 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1456 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1457 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1458 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1460 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1462 i40e_usec_delay(400);
1464 /* stop all the queues */
1465 for (i = 0; i < num_queues; i++) {
1466 wr32(hw, I40E_QINT_TQCTL(i), 0);
1467 wr32(hw, I40E_QTX_ENA(i), 0);
1468 wr32(hw, I40E_QINT_RQCTL(i), 0);
1469 wr32(hw, I40E_QRX_ENA(i), 0);
1472 /* short wait for all queue disables to settle */
1473 i40e_usec_delay(50);
1477 * i40e_clear_pxe_mode - clear pxe operations mode
1478 * @hw: pointer to the hw struct
1480 * Make sure all PXE mode settings are cleared, including things
1481 * like descriptor fetch/write-back mode.
1483 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1485 if (i40e_check_asq_alive(hw))
1486 i40e_aq_clear_pxe_mode(hw, NULL);
1490 * i40e_led_is_mine - helper to find matching led
1491 * @hw: pointer to the hw struct
1492 * @idx: index into GPIO registers
1494 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1496 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1501 if (!hw->func_caps.led[idx])
1504 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1505 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1506 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1508 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1509 * if it is not our port then ignore
1511 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1518 #define I40E_COMBINED_ACTIVITY 0xA
1519 #define I40E_FILTER_ACTIVITY 0xE
1520 #define I40E_LINK_ACTIVITY 0xC
1521 #define I40E_MAC_ACTIVITY 0xD
1522 #define I40E_LED0 22
1525 * i40e_led_get - return current on/off mode
1526 * @hw: pointer to the hw struct
1528 * The value returned is the 'mode' field as defined in the
1529 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1530 * values are variations of possible behaviors relating to
1531 * blink, link, and wire.
1533 u32 i40e_led_get(struct i40e_hw *hw)
1535 u32 current_mode = 0;
1539 /* as per the documentation GPIO 22-29 are the LED
1540 * GPIO pins named LED0..LED7
1542 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1543 u32 gpio_val = i40e_led_is_mine(hw, i);
1548 /* ignore gpio LED src mode entries related to the activity
1551 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1552 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1553 switch (current_mode) {
1554 case I40E_COMBINED_ACTIVITY:
1555 case I40E_FILTER_ACTIVITY:
1556 case I40E_MAC_ACTIVITY:
1562 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1563 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1571 * i40e_led_set - set new on/off mode
1572 * @hw: pointer to the hw struct
1573 * @mode: 0=off, 0xf=on (else see manual for mode details)
1574 * @blink: true if the LED should blink when on, false if steady
1576 * if this function is used to turn on the blink it should
1577 * be used to disable the blink when restoring the original state.
1579 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1581 u32 current_mode = 0;
1584 if (mode & 0xfffffff0)
1585 DEBUGOUT1("invalid mode passed in %X\n", mode);
1587 /* as per the documentation GPIO 22-29 are the LED
1588 * GPIO pins named LED0..LED7
1590 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1591 u32 gpio_val = i40e_led_is_mine(hw, i);
1596 /* ignore gpio LED src mode entries related to the activity
1599 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1600 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1601 switch (current_mode) {
1602 case I40E_COMBINED_ACTIVITY:
1603 case I40E_FILTER_ACTIVITY:
1604 case I40E_MAC_ACTIVITY:
1610 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1611 /* this & is a bit of paranoia, but serves as a range check */
1612 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1613 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1615 if (mode == I40E_LINK_ACTIVITY)
1619 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1621 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1623 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1628 /* Admin command wrappers */
1631 * i40e_aq_get_phy_capabilities
1632 * @hw: pointer to the hw struct
1633 * @abilities: structure for PHY capabilities to be filled
1634 * @qualified_modules: report Qualified Modules
1635 * @report_init: report init capabilities (active are default)
1636 * @cmd_details: pointer to command details structure or NULL
1638 * Returns the various PHY abilities supported on the Port.
1640 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1641 bool qualified_modules, bool report_init,
1642 struct i40e_aq_get_phy_abilities_resp *abilities,
1643 struct i40e_asq_cmd_details *cmd_details)
1645 struct i40e_aq_desc desc;
1646 enum i40e_status_code status;
1647 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1650 return I40E_ERR_PARAM;
1652 i40e_fill_default_direct_cmd_desc(&desc,
1653 i40e_aqc_opc_get_phy_abilities);
1655 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1656 if (abilities_size > I40E_AQ_LARGE_BUF)
1657 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1659 if (qualified_modules)
1660 desc.params.external.param0 |=
1661 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1664 desc.params.external.param0 |=
1665 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1667 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1670 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1671 status = I40E_ERR_UNKNOWN_PHY;
1674 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1675 hw->phy.phy_types |= ((u64)abilities->phy_type_ext << 32);
1682 * i40e_aq_set_phy_config
1683 * @hw: pointer to the hw struct
1684 * @config: structure with PHY configuration to be set
1685 * @cmd_details: pointer to command details structure or NULL
1687 * Set the various PHY configuration parameters
1688 * supported on the Port.One or more of the Set PHY config parameters may be
1689 * ignored in an MFP mode as the PF may not have the privilege to set some
1690 * of the PHY Config parameters. This status will be indicated by the
1693 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1694 struct i40e_aq_set_phy_config *config,
1695 struct i40e_asq_cmd_details *cmd_details)
1697 struct i40e_aq_desc desc;
1698 struct i40e_aq_set_phy_config *cmd =
1699 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1700 enum i40e_status_code status;
1703 return I40E_ERR_PARAM;
1705 i40e_fill_default_direct_cmd_desc(&desc,
1706 i40e_aqc_opc_set_phy_config);
1710 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1717 * @hw: pointer to the hw struct
1719 * Set the requested flow control mode using set_phy_config.
1721 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1722 bool atomic_restart)
1724 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1725 struct i40e_aq_get_phy_abilities_resp abilities;
1726 struct i40e_aq_set_phy_config config;
1727 enum i40e_status_code status;
1728 u8 pause_mask = 0x0;
1734 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1735 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1737 case I40E_FC_RX_PAUSE:
1738 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1740 case I40E_FC_TX_PAUSE:
1741 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1747 /* Get the current phy config */
1748 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1751 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1755 memset(&config, 0, sizeof(config));
1756 /* clear the old pause settings */
1757 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1758 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1759 /* set the new abilities */
1760 config.abilities |= pause_mask;
1761 /* If the abilities have changed, then set the new config */
1762 if (config.abilities != abilities.abilities) {
1763 /* Auto restart link so settings take effect */
1765 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1766 /* Copy over all the old settings */
1767 config.phy_type = abilities.phy_type;
1768 config.link_speed = abilities.link_speed;
1769 config.eee_capability = abilities.eee_capability;
1770 config.eeer = abilities.eeer_val;
1771 config.low_power_ctrl = abilities.d3_lpan;
1772 status = i40e_aq_set_phy_config(hw, &config, NULL);
1775 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1777 /* Update the link info */
1778 status = i40e_update_link_info(hw);
1780 /* Wait a little bit (on 40G cards it sometimes takes a really
1781 * long time for link to come back from the atomic reset)
1784 i40e_msec_delay(1000);
1785 status = i40e_update_link_info(hw);
1788 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1794 * i40e_aq_set_mac_config
1795 * @hw: pointer to the hw struct
1796 * @max_frame_size: Maximum Frame Size to be supported by the port
1797 * @crc_en: Tell HW to append a CRC to outgoing frames
1798 * @pacing: Pacing configurations
1799 * @cmd_details: pointer to command details structure or NULL
1801 * Configure MAC settings for frame size, jumbo frame support and the
1802 * addition of a CRC by the hardware.
1804 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1806 bool crc_en, u16 pacing,
1807 struct i40e_asq_cmd_details *cmd_details)
1809 struct i40e_aq_desc desc;
1810 struct i40e_aq_set_mac_config *cmd =
1811 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1812 enum i40e_status_code status;
1814 if (max_frame_size == 0)
1815 return I40E_ERR_PARAM;
1817 i40e_fill_default_direct_cmd_desc(&desc,
1818 i40e_aqc_opc_set_mac_config);
1820 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1821 cmd->params = ((u8)pacing & 0x0F) << 3;
1823 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1825 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1831 * i40e_aq_clear_pxe_mode
1832 * @hw: pointer to the hw struct
1833 * @cmd_details: pointer to command details structure or NULL
1835 * Tell the firmware that the driver is taking over from PXE
1837 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1838 struct i40e_asq_cmd_details *cmd_details)
1840 enum i40e_status_code status;
1841 struct i40e_aq_desc desc;
1842 struct i40e_aqc_clear_pxe *cmd =
1843 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1845 i40e_fill_default_direct_cmd_desc(&desc,
1846 i40e_aqc_opc_clear_pxe_mode);
1850 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1852 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1858 * i40e_aq_set_link_restart_an
1859 * @hw: pointer to the hw struct
1860 * @enable_link: if true: enable link, if false: disable link
1861 * @cmd_details: pointer to command details structure or NULL
1863 * Sets up the link and restarts the Auto-Negotiation over the link.
1865 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1866 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1868 struct i40e_aq_desc desc;
1869 struct i40e_aqc_set_link_restart_an *cmd =
1870 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1871 enum i40e_status_code status;
1873 i40e_fill_default_direct_cmd_desc(&desc,
1874 i40e_aqc_opc_set_link_restart_an);
1876 cmd->command = I40E_AQ_PHY_RESTART_AN;
1878 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1880 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1882 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1888 * i40e_aq_get_link_info
1889 * @hw: pointer to the hw struct
1890 * @enable_lse: enable/disable LinkStatusEvent reporting
1891 * @link: pointer to link status structure - optional
1892 * @cmd_details: pointer to command details structure or NULL
1894 * Returns the link status of the adapter.
1896 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1897 bool enable_lse, struct i40e_link_status *link,
1898 struct i40e_asq_cmd_details *cmd_details)
1900 struct i40e_aq_desc desc;
1901 struct i40e_aqc_get_link_status *resp =
1902 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1903 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1904 enum i40e_status_code status;
1905 bool tx_pause, rx_pause;
1908 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1911 command_flags = I40E_AQ_LSE_ENABLE;
1913 command_flags = I40E_AQ_LSE_DISABLE;
1914 resp->command_flags = CPU_TO_LE16(command_flags);
1916 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1918 if (status != I40E_SUCCESS)
1919 goto aq_get_link_info_exit;
1921 /* save off old link status information */
1922 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1923 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1925 /* update link status */
1926 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1927 hw->phy.media_type = i40e_get_media_type(hw);
1928 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1929 hw_link_info->link_info = resp->link_info;
1930 hw_link_info->an_info = resp->an_info;
1931 hw_link_info->ext_info = resp->ext_info;
1932 hw_link_info->loopback = resp->loopback;
1933 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1934 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1936 /* update fc info */
1937 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1938 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1939 if (tx_pause & rx_pause)
1940 hw->fc.current_mode = I40E_FC_FULL;
1942 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1944 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1946 hw->fc.current_mode = I40E_FC_NONE;
1948 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1949 hw_link_info->crc_enable = true;
1951 hw_link_info->crc_enable = false;
1953 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1954 hw_link_info->lse_enable = true;
1956 hw_link_info->lse_enable = false;
1958 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1959 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1960 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1962 /* save link status information */
1964 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1965 I40E_NONDMA_TO_NONDMA);
1967 /* flag cleared so helper functions don't call AQ again */
1968 hw->phy.get_link_info = false;
1970 aq_get_link_info_exit:
1975 * i40e_aq_set_phy_int_mask
1976 * @hw: pointer to the hw struct
1977 * @mask: interrupt mask to be set
1978 * @cmd_details: pointer to command details structure or NULL
1980 * Set link interrupt mask.
1982 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1984 struct i40e_asq_cmd_details *cmd_details)
1986 struct i40e_aq_desc desc;
1987 struct i40e_aqc_set_phy_int_mask *cmd =
1988 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1989 enum i40e_status_code status;
1991 i40e_fill_default_direct_cmd_desc(&desc,
1992 i40e_aqc_opc_set_phy_int_mask);
1994 cmd->event_mask = CPU_TO_LE16(mask);
1996 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2002 * i40e_aq_get_local_advt_reg
2003 * @hw: pointer to the hw struct
2004 * @advt_reg: local AN advertisement register value
2005 * @cmd_details: pointer to command details structure or NULL
2007 * Get the Local AN advertisement register value.
2009 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2011 struct i40e_asq_cmd_details *cmd_details)
2013 struct i40e_aq_desc desc;
2014 struct i40e_aqc_an_advt_reg *resp =
2015 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2016 enum i40e_status_code status;
2018 i40e_fill_default_direct_cmd_desc(&desc,
2019 i40e_aqc_opc_get_local_advt_reg);
2021 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2023 if (status != I40E_SUCCESS)
2024 goto aq_get_local_advt_reg_exit;
2026 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2027 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2029 aq_get_local_advt_reg_exit:
2034 * i40e_aq_set_local_advt_reg
2035 * @hw: pointer to the hw struct
2036 * @advt_reg: local AN advertisement register value
2037 * @cmd_details: pointer to command details structure or NULL
2039 * Get the Local AN advertisement register value.
2041 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2043 struct i40e_asq_cmd_details *cmd_details)
2045 struct i40e_aq_desc desc;
2046 struct i40e_aqc_an_advt_reg *cmd =
2047 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2048 enum i40e_status_code status;
2050 i40e_fill_default_direct_cmd_desc(&desc,
2051 i40e_aqc_opc_get_local_advt_reg);
2053 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2054 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2056 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2062 * i40e_aq_get_partner_advt
2063 * @hw: pointer to the hw struct
2064 * @advt_reg: AN partner advertisement register value
2065 * @cmd_details: pointer to command details structure or NULL
2067 * Get the link partner AN advertisement register value.
2069 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2071 struct i40e_asq_cmd_details *cmd_details)
2073 struct i40e_aq_desc desc;
2074 struct i40e_aqc_an_advt_reg *resp =
2075 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2076 enum i40e_status_code status;
2078 i40e_fill_default_direct_cmd_desc(&desc,
2079 i40e_aqc_opc_get_partner_advt);
2081 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2083 if (status != I40E_SUCCESS)
2084 goto aq_get_partner_advt_exit;
2086 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2087 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2089 aq_get_partner_advt_exit:
2094 * i40e_aq_set_lb_modes
2095 * @hw: pointer to the hw struct
2096 * @lb_modes: loopback mode to be set
2097 * @cmd_details: pointer to command details structure or NULL
2099 * Sets loopback modes.
2101 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2103 struct i40e_asq_cmd_details *cmd_details)
2105 struct i40e_aq_desc desc;
2106 struct i40e_aqc_set_lb_mode *cmd =
2107 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2108 enum i40e_status_code status;
2110 i40e_fill_default_direct_cmd_desc(&desc,
2111 i40e_aqc_opc_set_lb_modes);
2113 cmd->lb_mode = CPU_TO_LE16(lb_modes);
2115 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2121 * i40e_aq_set_phy_debug
2122 * @hw: pointer to the hw struct
2123 * @cmd_flags: debug command flags
2124 * @cmd_details: pointer to command details structure or NULL
2126 * Reset the external PHY.
2128 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2129 struct i40e_asq_cmd_details *cmd_details)
2131 struct i40e_aq_desc desc;
2132 struct i40e_aqc_set_phy_debug *cmd =
2133 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2134 enum i40e_status_code status;
2136 i40e_fill_default_direct_cmd_desc(&desc,
2137 i40e_aqc_opc_set_phy_debug);
2139 cmd->command_flags = cmd_flags;
2141 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2148 * @hw: pointer to the hw struct
2149 * @vsi_ctx: pointer to a vsi context struct
2150 * @cmd_details: pointer to command details structure or NULL
2152 * Add a VSI context to the hardware.
2154 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2155 struct i40e_vsi_context *vsi_ctx,
2156 struct i40e_asq_cmd_details *cmd_details)
2158 struct i40e_aq_desc desc;
2159 struct i40e_aqc_add_get_update_vsi *cmd =
2160 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2161 struct i40e_aqc_add_get_update_vsi_completion *resp =
2162 (struct i40e_aqc_add_get_update_vsi_completion *)
2164 enum i40e_status_code status;
2166 i40e_fill_default_direct_cmd_desc(&desc,
2167 i40e_aqc_opc_add_vsi);
2169 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2170 cmd->connection_type = vsi_ctx->connection_type;
2171 cmd->vf_id = vsi_ctx->vf_num;
2172 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2174 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2176 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2177 sizeof(vsi_ctx->info), cmd_details);
2179 if (status != I40E_SUCCESS)
2180 goto aq_add_vsi_exit;
2182 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2183 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2184 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2185 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2192 * i40e_aq_set_default_vsi
2193 * @hw: pointer to the hw struct
2195 * @cmd_details: pointer to command details structure or NULL
2197 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2199 struct i40e_asq_cmd_details *cmd_details)
2201 struct i40e_aq_desc desc;
2202 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2203 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2205 enum i40e_status_code status;
2207 i40e_fill_default_direct_cmd_desc(&desc,
2208 i40e_aqc_opc_set_vsi_promiscuous_modes);
2210 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2211 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2212 cmd->seid = CPU_TO_LE16(seid);
2214 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2220 * i40e_aq_clear_default_vsi
2221 * @hw: pointer to the hw struct
2223 * @cmd_details: pointer to command details structure or NULL
2225 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2227 struct i40e_asq_cmd_details *cmd_details)
2229 struct i40e_aq_desc desc;
2230 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2231 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2233 enum i40e_status_code status;
2235 i40e_fill_default_direct_cmd_desc(&desc,
2236 i40e_aqc_opc_set_vsi_promiscuous_modes);
2238 cmd->promiscuous_flags = CPU_TO_LE16(0);
2239 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2240 cmd->seid = CPU_TO_LE16(seid);
2242 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2248 * i40e_aq_set_vsi_unicast_promiscuous
2249 * @hw: pointer to the hw struct
2251 * @set: set unicast promiscuous enable/disable
2252 * @cmd_details: pointer to command details structure or NULL
2253 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2255 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2257 struct i40e_asq_cmd_details *cmd_details,
2258 bool rx_only_promisc)
2260 struct i40e_aq_desc desc;
2261 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2262 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2263 enum i40e_status_code status;
2266 i40e_fill_default_direct_cmd_desc(&desc,
2267 i40e_aqc_opc_set_vsi_promiscuous_modes);
2270 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2271 if (rx_only_promisc &&
2272 (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2273 (hw->aq.api_maj_ver > 1)))
2274 flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2277 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2279 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2280 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2281 (hw->aq.api_maj_ver > 1))
2282 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2284 cmd->seid = CPU_TO_LE16(seid);
2285 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2291 * i40e_aq_set_vsi_multicast_promiscuous
2292 * @hw: pointer to the hw struct
2294 * @set: set multicast promiscuous enable/disable
2295 * @cmd_details: pointer to command details structure or NULL
2297 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2298 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2300 struct i40e_aq_desc desc;
2301 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2302 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2303 enum i40e_status_code status;
2306 i40e_fill_default_direct_cmd_desc(&desc,
2307 i40e_aqc_opc_set_vsi_promiscuous_modes);
2310 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2312 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2314 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2316 cmd->seid = CPU_TO_LE16(seid);
2317 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2323 * i40e_aq_set_vsi_mc_promisc_on_vlan
2324 * @hw: pointer to the hw struct
2326 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2327 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2328 * @cmd_details: pointer to command details structure or NULL
2330 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2331 u16 seid, bool enable, u16 vid,
2332 struct i40e_asq_cmd_details *cmd_details)
2334 struct i40e_aq_desc desc;
2335 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2336 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2337 enum i40e_status_code status;
2340 i40e_fill_default_direct_cmd_desc(&desc,
2341 i40e_aqc_opc_set_vsi_promiscuous_modes);
2344 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2346 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2347 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2348 cmd->seid = CPU_TO_LE16(seid);
2349 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2351 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2357 * i40e_aq_set_vsi_uc_promisc_on_vlan
2358 * @hw: pointer to the hw struct
2360 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2361 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2362 * @cmd_details: pointer to command details structure or NULL
2364 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2365 u16 seid, bool enable, u16 vid,
2366 struct i40e_asq_cmd_details *cmd_details)
2368 struct i40e_aq_desc desc;
2369 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2370 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2371 enum i40e_status_code status;
2374 i40e_fill_default_direct_cmd_desc(&desc,
2375 i40e_aqc_opc_set_vsi_promiscuous_modes);
2378 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2380 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2381 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2382 cmd->seid = CPU_TO_LE16(seid);
2383 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2385 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2391 * i40e_aq_set_vsi_broadcast
2392 * @hw: pointer to the hw struct
2394 * @set_filter: true to set filter, false to clear filter
2395 * @cmd_details: pointer to command details structure or NULL
2397 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2399 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2400 u16 seid, bool set_filter,
2401 struct i40e_asq_cmd_details *cmd_details)
2403 struct i40e_aq_desc desc;
2404 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2405 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2406 enum i40e_status_code status;
2408 i40e_fill_default_direct_cmd_desc(&desc,
2409 i40e_aqc_opc_set_vsi_promiscuous_modes);
2412 cmd->promiscuous_flags
2413 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2415 cmd->promiscuous_flags
2416 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2418 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2419 cmd->seid = CPU_TO_LE16(seid);
2420 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2426 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2427 * @hw: pointer to the hw struct
2429 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2430 * @cmd_details: pointer to command details structure or NULL
2432 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2433 u16 seid, bool enable,
2434 struct i40e_asq_cmd_details *cmd_details)
2436 struct i40e_aq_desc desc;
2437 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2438 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2439 enum i40e_status_code status;
2442 i40e_fill_default_direct_cmd_desc(&desc,
2443 i40e_aqc_opc_set_vsi_promiscuous_modes);
2445 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2447 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2448 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2449 cmd->seid = CPU_TO_LE16(seid);
2451 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2457 * i40e_get_vsi_params - get VSI configuration info
2458 * @hw: pointer to the hw struct
2459 * @vsi_ctx: pointer to a vsi context struct
2460 * @cmd_details: pointer to command details structure or NULL
2462 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2463 struct i40e_vsi_context *vsi_ctx,
2464 struct i40e_asq_cmd_details *cmd_details)
2466 struct i40e_aq_desc desc;
2467 struct i40e_aqc_add_get_update_vsi *cmd =
2468 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2469 struct i40e_aqc_add_get_update_vsi_completion *resp =
2470 (struct i40e_aqc_add_get_update_vsi_completion *)
2472 enum i40e_status_code status;
2474 UNREFERENCED_1PARAMETER(cmd_details);
2475 i40e_fill_default_direct_cmd_desc(&desc,
2476 i40e_aqc_opc_get_vsi_parameters);
2478 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2480 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2482 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2483 sizeof(vsi_ctx->info), NULL);
2485 if (status != I40E_SUCCESS)
2486 goto aq_get_vsi_params_exit;
2488 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2489 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2490 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2491 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2493 aq_get_vsi_params_exit:
2498 * i40e_aq_update_vsi_params
2499 * @hw: pointer to the hw struct
2500 * @vsi_ctx: pointer to a vsi context struct
2501 * @cmd_details: pointer to command details structure or NULL
2503 * Update a VSI context.
2505 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2506 struct i40e_vsi_context *vsi_ctx,
2507 struct i40e_asq_cmd_details *cmd_details)
2509 struct i40e_aq_desc desc;
2510 struct i40e_aqc_add_get_update_vsi *cmd =
2511 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2512 struct i40e_aqc_add_get_update_vsi_completion *resp =
2513 (struct i40e_aqc_add_get_update_vsi_completion *)
2515 enum i40e_status_code status;
2517 i40e_fill_default_direct_cmd_desc(&desc,
2518 i40e_aqc_opc_update_vsi_parameters);
2519 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2521 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2523 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2524 sizeof(vsi_ctx->info), cmd_details);
2526 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2527 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2533 * i40e_aq_get_switch_config
2534 * @hw: pointer to the hardware structure
2535 * @buf: pointer to the result buffer
2536 * @buf_size: length of input buffer
2537 * @start_seid: seid to start for the report, 0 == beginning
2538 * @cmd_details: pointer to command details structure or NULL
2540 * Fill the buf with switch configuration returned from AdminQ command
2542 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2543 struct i40e_aqc_get_switch_config_resp *buf,
2544 u16 buf_size, u16 *start_seid,
2545 struct i40e_asq_cmd_details *cmd_details)
2547 struct i40e_aq_desc desc;
2548 struct i40e_aqc_switch_seid *scfg =
2549 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2550 enum i40e_status_code status;
2552 i40e_fill_default_direct_cmd_desc(&desc,
2553 i40e_aqc_opc_get_switch_config);
2554 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2555 if (buf_size > I40E_AQ_LARGE_BUF)
2556 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2557 scfg->seid = CPU_TO_LE16(*start_seid);
2559 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2560 *start_seid = LE16_TO_CPU(scfg->seid);
2566 * i40e_aq_set_switch_config
2567 * @hw: pointer to the hardware structure
2568 * @flags: bit flag values to set
2569 * @valid_flags: which bit flags to set
2570 * @cmd_details: pointer to command details structure or NULL
2572 * Set switch configuration bits
2574 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2575 u16 flags, u16 valid_flags,
2576 struct i40e_asq_cmd_details *cmd_details)
2578 struct i40e_aq_desc desc;
2579 struct i40e_aqc_set_switch_config *scfg =
2580 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2581 enum i40e_status_code status;
2583 i40e_fill_default_direct_cmd_desc(&desc,
2584 i40e_aqc_opc_set_switch_config);
2585 scfg->flags = CPU_TO_LE16(flags);
2586 scfg->valid_flags = CPU_TO_LE16(valid_flags);
2588 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2594 * i40e_aq_get_firmware_version
2595 * @hw: pointer to the hw struct
2596 * @fw_major_version: firmware major version
2597 * @fw_minor_version: firmware minor version
2598 * @fw_build: firmware build number
2599 * @api_major_version: major queue version
2600 * @api_minor_version: minor queue version
2601 * @cmd_details: pointer to command details structure or NULL
2603 * Get the firmware version from the admin queue commands
2605 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2606 u16 *fw_major_version, u16 *fw_minor_version,
2608 u16 *api_major_version, u16 *api_minor_version,
2609 struct i40e_asq_cmd_details *cmd_details)
2611 struct i40e_aq_desc desc;
2612 struct i40e_aqc_get_version *resp =
2613 (struct i40e_aqc_get_version *)&desc.params.raw;
2614 enum i40e_status_code status;
2616 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2618 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2620 if (status == I40E_SUCCESS) {
2621 if (fw_major_version != NULL)
2622 *fw_major_version = LE16_TO_CPU(resp->fw_major);
2623 if (fw_minor_version != NULL)
2624 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2625 if (fw_build != NULL)
2626 *fw_build = LE32_TO_CPU(resp->fw_build);
2627 if (api_major_version != NULL)
2628 *api_major_version = LE16_TO_CPU(resp->api_major);
2629 if (api_minor_version != NULL)
2630 *api_minor_version = LE16_TO_CPU(resp->api_minor);
2632 /* A workaround to fix the API version in SW */
2633 if (api_major_version && api_minor_version &&
2634 fw_major_version && fw_minor_version &&
2635 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2636 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2637 (*fw_major_version > 4)))
2638 *api_minor_version = 2;
2645 * i40e_aq_send_driver_version
2646 * @hw: pointer to the hw struct
2647 * @dv: driver's major, minor version
2648 * @cmd_details: pointer to command details structure or NULL
2650 * Send the driver version to the firmware
2652 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2653 struct i40e_driver_version *dv,
2654 struct i40e_asq_cmd_details *cmd_details)
2656 struct i40e_aq_desc desc;
2657 struct i40e_aqc_driver_version *cmd =
2658 (struct i40e_aqc_driver_version *)&desc.params.raw;
2659 enum i40e_status_code status;
2663 return I40E_ERR_PARAM;
2665 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2667 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2668 cmd->driver_major_ver = dv->major_version;
2669 cmd->driver_minor_ver = dv->minor_version;
2670 cmd->driver_build_ver = dv->build_version;
2671 cmd->driver_subbuild_ver = dv->subbuild_version;
2674 while (len < sizeof(dv->driver_string) &&
2675 (dv->driver_string[len] < 0x80) &&
2676 dv->driver_string[len])
2678 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2685 * i40e_get_link_status - get status of the HW network link
2686 * @hw: pointer to the hw struct
2687 * @link_up: pointer to bool (true/false = linkup/linkdown)
2689 * Variable link_up true if link is up, false if link is down.
2690 * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2692 * Side effect: LinkStatusEvent reporting becomes enabled
2694 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2696 enum i40e_status_code status = I40E_SUCCESS;
2698 if (hw->phy.get_link_info) {
2699 status = i40e_update_link_info(hw);
2701 if (status != I40E_SUCCESS)
2702 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2706 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2712 * i40e_updatelink_status - update status of the HW network link
2713 * @hw: pointer to the hw struct
2715 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2717 struct i40e_aq_get_phy_abilities_resp abilities;
2718 enum i40e_status_code status = I40E_SUCCESS;
2720 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2724 if (hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) {
2725 status = i40e_aq_get_phy_capabilities(hw, false, false,
2730 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2731 sizeof(hw->phy.link_info.module_type));
2738 * i40e_get_link_speed
2739 * @hw: pointer to the hw struct
2741 * Returns the link speed of the adapter.
2743 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2745 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2746 enum i40e_status_code status = I40E_SUCCESS;
2748 if (hw->phy.get_link_info) {
2749 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2751 if (status != I40E_SUCCESS)
2752 goto i40e_link_speed_exit;
2755 speed = hw->phy.link_info.link_speed;
2757 i40e_link_speed_exit:
2762 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2763 * @hw: pointer to the hw struct
2764 * @uplink_seid: the MAC or other gizmo SEID
2765 * @downlink_seid: the VSI SEID
2766 * @enabled_tc: bitmap of TCs to be enabled
2767 * @default_port: true for default port VSI, false for control port
2768 * @veb_seid: pointer to where to put the resulting VEB SEID
2769 * @enable_stats: true to turn on VEB stats
2770 * @cmd_details: pointer to command details structure or NULL
2772 * This asks the FW to add a VEB between the uplink and downlink
2773 * elements. If the uplink SEID is 0, this will be a floating VEB.
2775 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2776 u16 downlink_seid, u8 enabled_tc,
2777 bool default_port, u16 *veb_seid,
2779 struct i40e_asq_cmd_details *cmd_details)
2781 struct i40e_aq_desc desc;
2782 struct i40e_aqc_add_veb *cmd =
2783 (struct i40e_aqc_add_veb *)&desc.params.raw;
2784 struct i40e_aqc_add_veb_completion *resp =
2785 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2786 enum i40e_status_code status;
2789 /* SEIDs need to either both be set or both be 0 for floating VEB */
2790 if (!!uplink_seid != !!downlink_seid)
2791 return I40E_ERR_PARAM;
2793 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2795 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2796 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2797 cmd->enable_tcs = enabled_tc;
2799 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2801 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2803 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2805 /* reverse logic here: set the bitflag to disable the stats */
2807 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2809 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2811 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2813 if (!status && veb_seid)
2814 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2820 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2821 * @hw: pointer to the hw struct
2822 * @veb_seid: the SEID of the VEB to query
2823 * @switch_id: the uplink switch id
2824 * @floating: set to true if the VEB is floating
2825 * @statistic_index: index of the stats counter block for this VEB
2826 * @vebs_used: number of VEB's used by function
2827 * @vebs_free: total VEB's not reserved by any function
2828 * @cmd_details: pointer to command details structure or NULL
2830 * This retrieves the parameters for a particular VEB, specified by
2831 * uplink_seid, and returns them to the caller.
2833 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2834 u16 veb_seid, u16 *switch_id,
2835 bool *floating, u16 *statistic_index,
2836 u16 *vebs_used, u16 *vebs_free,
2837 struct i40e_asq_cmd_details *cmd_details)
2839 struct i40e_aq_desc desc;
2840 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2841 (struct i40e_aqc_get_veb_parameters_completion *)
2843 enum i40e_status_code status;
2846 return I40E_ERR_PARAM;
2848 i40e_fill_default_direct_cmd_desc(&desc,
2849 i40e_aqc_opc_get_veb_parameters);
2850 cmd_resp->seid = CPU_TO_LE16(veb_seid);
2852 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2857 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2858 if (statistic_index)
2859 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2861 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2863 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2865 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2867 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2878 * i40e_aq_add_macvlan
2879 * @hw: pointer to the hw struct
2880 * @seid: VSI for the mac address
2881 * @mv_list: list of macvlans to be added
2882 * @count: length of the list
2883 * @cmd_details: pointer to command details structure or NULL
2885 * Add MAC/VLAN addresses to the HW filtering
2887 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2888 struct i40e_aqc_add_macvlan_element_data *mv_list,
2889 u16 count, struct i40e_asq_cmd_details *cmd_details)
2891 struct i40e_aq_desc desc;
2892 struct i40e_aqc_macvlan *cmd =
2893 (struct i40e_aqc_macvlan *)&desc.params.raw;
2894 enum i40e_status_code status;
2898 if (count == 0 || !mv_list || !hw)
2899 return I40E_ERR_PARAM;
2901 buf_size = count * sizeof(*mv_list);
2903 /* prep the rest of the request */
2904 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2905 cmd->num_addresses = CPU_TO_LE16(count);
2906 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2910 for (i = 0; i < count; i++)
2911 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
2913 CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2915 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2916 if (buf_size > I40E_AQ_LARGE_BUF)
2917 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2919 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2926 * i40e_aq_remove_macvlan
2927 * @hw: pointer to the hw struct
2928 * @seid: VSI for the mac address
2929 * @mv_list: list of macvlans to be removed
2930 * @count: length of the list
2931 * @cmd_details: pointer to command details structure or NULL
2933 * Remove MAC/VLAN addresses from the HW filtering
2935 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2936 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2937 u16 count, struct i40e_asq_cmd_details *cmd_details)
2939 struct i40e_aq_desc desc;
2940 struct i40e_aqc_macvlan *cmd =
2941 (struct i40e_aqc_macvlan *)&desc.params.raw;
2942 enum i40e_status_code status;
2945 if (count == 0 || !mv_list || !hw)
2946 return I40E_ERR_PARAM;
2948 buf_size = count * sizeof(*mv_list);
2950 /* prep the rest of the request */
2951 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2952 cmd->num_addresses = CPU_TO_LE16(count);
2953 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2957 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2958 if (buf_size > I40E_AQ_LARGE_BUF)
2959 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2961 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2968 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
2969 * @hw: pointer to the hw struct
2970 * @opcode: AQ opcode for add or delete mirror rule
2971 * @sw_seid: Switch SEID (to which rule refers)
2972 * @rule_type: Rule Type (ingress/egress/VLAN)
2973 * @id: Destination VSI SEID or Rule ID
2974 * @count: length of the list
2975 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2976 * @cmd_details: pointer to command details structure or NULL
2977 * @rule_id: Rule ID returned from FW
2978 * @rule_used: Number of rules used in internal switch
2979 * @rule_free: Number of rules free in internal switch
2981 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
2982 * VEBs/VEPA elements only
2984 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
2985 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
2986 u16 count, __le16 *mr_list,
2987 struct i40e_asq_cmd_details *cmd_details,
2988 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2990 struct i40e_aq_desc desc;
2991 struct i40e_aqc_add_delete_mirror_rule *cmd =
2992 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
2993 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
2994 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
2995 enum i40e_status_code status;
2998 buf_size = count * sizeof(*mr_list);
3000 /* prep the rest of the request */
3001 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3002 cmd->seid = CPU_TO_LE16(sw_seid);
3003 cmd->rule_type = CPU_TO_LE16(rule_type &
3004 I40E_AQC_MIRROR_RULE_TYPE_MASK);
3005 cmd->num_entries = CPU_TO_LE16(count);
3006 /* Dest VSI for add, rule_id for delete */
3007 cmd->destination = CPU_TO_LE16(id);
3009 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3011 if (buf_size > I40E_AQ_LARGE_BUF)
3012 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3015 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3017 if (status == I40E_SUCCESS ||
3018 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3020 *rule_id = LE16_TO_CPU(resp->rule_id);
3022 *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3024 *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3030 * i40e_aq_add_mirrorrule - add a mirror rule
3031 * @hw: pointer to the hw struct
3032 * @sw_seid: Switch SEID (to which rule refers)
3033 * @rule_type: Rule Type (ingress/egress/VLAN)
3034 * @dest_vsi: SEID of VSI to which packets will be mirrored
3035 * @count: length of the list
3036 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3037 * @cmd_details: pointer to command details structure or NULL
3038 * @rule_id: Rule ID returned from FW
3039 * @rule_used: Number of rules used in internal switch
3040 * @rule_free: Number of rules free in internal switch
3042 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3044 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3045 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3046 struct i40e_asq_cmd_details *cmd_details,
3047 u16 *rule_id, u16 *rules_used, u16 *rules_free)
3049 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3050 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3051 if (count == 0 || !mr_list)
3052 return I40E_ERR_PARAM;
3055 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3056 rule_type, dest_vsi, count, mr_list,
3057 cmd_details, rule_id, rules_used, rules_free);
3061 * i40e_aq_delete_mirrorrule - delete a mirror rule
3062 * @hw: pointer to the hw struct
3063 * @sw_seid: Switch SEID (to which rule refers)
3064 * @rule_type: Rule Type (ingress/egress/VLAN)
3065 * @count: length of the list
3066 * @rule_id: Rule ID that is returned in the receive desc as part of
3068 * @mr_list: list of mirrored VLAN IDs to be removed
3069 * @cmd_details: pointer to command details structure or NULL
3070 * @rule_used: Number of rules used in internal switch
3071 * @rule_free: Number of rules free in internal switch
3073 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3075 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3076 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3077 struct i40e_asq_cmd_details *cmd_details,
3078 u16 *rules_used, u16 *rules_free)
3080 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3081 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3082 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3083 * mirroring. For other rule_type, count and rule_type should
3086 if (count == 0 || !mr_list)
3087 return I40E_ERR_PARAM;
3090 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3091 rule_type, rule_id, count, mr_list,
3092 cmd_details, NULL, rules_used, rules_free);
3096 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3097 * @hw: pointer to the hw struct
3098 * @seid: VSI for the vlan filters
3099 * @v_list: list of vlan filters to be added
3100 * @count: length of the list
3101 * @cmd_details: pointer to command details structure or NULL
3103 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3104 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3105 u8 count, struct i40e_asq_cmd_details *cmd_details)
3107 struct i40e_aq_desc desc;
3108 struct i40e_aqc_macvlan *cmd =
3109 (struct i40e_aqc_macvlan *)&desc.params.raw;
3110 enum i40e_status_code status;
3113 if (count == 0 || !v_list || !hw)
3114 return I40E_ERR_PARAM;
3116 buf_size = count * sizeof(*v_list);
3118 /* prep the rest of the request */
3119 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3120 cmd->num_addresses = CPU_TO_LE16(count);
3121 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3125 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3126 if (buf_size > I40E_AQ_LARGE_BUF)
3127 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3129 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3136 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3137 * @hw: pointer to the hw struct
3138 * @seid: VSI for the vlan filters
3139 * @v_list: list of macvlans to be removed
3140 * @count: length of the list
3141 * @cmd_details: pointer to command details structure or NULL
3143 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3144 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3145 u8 count, struct i40e_asq_cmd_details *cmd_details)
3147 struct i40e_aq_desc desc;
3148 struct i40e_aqc_macvlan *cmd =
3149 (struct i40e_aqc_macvlan *)&desc.params.raw;
3150 enum i40e_status_code status;
3153 if (count == 0 || !v_list || !hw)
3154 return I40E_ERR_PARAM;
3156 buf_size = count * sizeof(*v_list);
3158 /* prep the rest of the request */
3159 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3160 cmd->num_addresses = CPU_TO_LE16(count);
3161 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3165 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3166 if (buf_size > I40E_AQ_LARGE_BUF)
3167 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3169 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3176 * i40e_aq_send_msg_to_vf
3177 * @hw: pointer to the hardware structure
3178 * @vfid: vf id to send msg
3179 * @v_opcode: opcodes for VF-PF communication
3180 * @v_retval: return error code
3181 * @msg: pointer to the msg buffer
3182 * @msglen: msg length
3183 * @cmd_details: pointer to command details
3187 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3188 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3189 struct i40e_asq_cmd_details *cmd_details)
3191 struct i40e_aq_desc desc;
3192 struct i40e_aqc_pf_vf_message *cmd =
3193 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3194 enum i40e_status_code status;
3196 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3197 cmd->id = CPU_TO_LE32(vfid);
3198 desc.cookie_high = CPU_TO_LE32(v_opcode);
3199 desc.cookie_low = CPU_TO_LE32(v_retval);
3200 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3202 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3204 if (msglen > I40E_AQ_LARGE_BUF)
3205 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3206 desc.datalen = CPU_TO_LE16(msglen);
3208 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3214 * i40e_aq_debug_read_register
3215 * @hw: pointer to the hw struct
3216 * @reg_addr: register address
3217 * @reg_val: register value
3218 * @cmd_details: pointer to command details structure or NULL
3220 * Read the register using the admin queue commands
3222 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3223 u32 reg_addr, u64 *reg_val,
3224 struct i40e_asq_cmd_details *cmd_details)
3226 struct i40e_aq_desc desc;
3227 struct i40e_aqc_debug_reg_read_write *cmd_resp =
3228 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3229 enum i40e_status_code status;
3231 if (reg_val == NULL)
3232 return I40E_ERR_PARAM;
3234 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3236 cmd_resp->address = CPU_TO_LE32(reg_addr);
3238 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3240 if (status == I40E_SUCCESS) {
3241 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3242 (u64)LE32_TO_CPU(cmd_resp->value_low);
3249 * i40e_aq_debug_write_register
3250 * @hw: pointer to the hw struct
3251 * @reg_addr: register address
3252 * @reg_val: register value
3253 * @cmd_details: pointer to command details structure or NULL
3255 * Write to a register using the admin queue commands
3257 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3258 u32 reg_addr, u64 reg_val,
3259 struct i40e_asq_cmd_details *cmd_details)
3261 struct i40e_aq_desc desc;
3262 struct i40e_aqc_debug_reg_read_write *cmd =
3263 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3264 enum i40e_status_code status;
3266 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3268 cmd->address = CPU_TO_LE32(reg_addr);
3269 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3270 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3272 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3278 * i40e_aq_request_resource
3279 * @hw: pointer to the hw struct
3280 * @resource: resource id
3281 * @access: access type
3282 * @sdp_number: resource number
3283 * @timeout: the maximum time in ms that the driver may hold the resource
3284 * @cmd_details: pointer to command details structure or NULL
3286 * requests common resource using the admin queue commands
3288 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3289 enum i40e_aq_resources_ids resource,
3290 enum i40e_aq_resource_access_type access,
3291 u8 sdp_number, u64 *timeout,
3292 struct i40e_asq_cmd_details *cmd_details)
3294 struct i40e_aq_desc desc;
3295 struct i40e_aqc_request_resource *cmd_resp =
3296 (struct i40e_aqc_request_resource *)&desc.params.raw;
3297 enum i40e_status_code status;
3299 DEBUGFUNC("i40e_aq_request_resource");
3301 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3303 cmd_resp->resource_id = CPU_TO_LE16(resource);
3304 cmd_resp->access_type = CPU_TO_LE16(access);
3305 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3307 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3308 /* The completion specifies the maximum time in ms that the driver
3309 * may hold the resource in the Timeout field.
3310 * If the resource is held by someone else, the command completes with
3311 * busy return value and the timeout field indicates the maximum time
3312 * the current owner of the resource has to free it.
3314 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3315 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3321 * i40e_aq_release_resource
3322 * @hw: pointer to the hw struct
3323 * @resource: resource id
3324 * @sdp_number: resource number
3325 * @cmd_details: pointer to command details structure or NULL
3327 * release common resource using the admin queue commands
3329 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3330 enum i40e_aq_resources_ids resource,
3332 struct i40e_asq_cmd_details *cmd_details)
3334 struct i40e_aq_desc desc;
3335 struct i40e_aqc_request_resource *cmd =
3336 (struct i40e_aqc_request_resource *)&desc.params.raw;
3337 enum i40e_status_code status;
3339 DEBUGFUNC("i40e_aq_release_resource");
3341 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3343 cmd->resource_id = CPU_TO_LE16(resource);
3344 cmd->resource_number = CPU_TO_LE32(sdp_number);
3346 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3353 * @hw: pointer to the hw struct
3354 * @module_pointer: module pointer location in words from the NVM beginning
3355 * @offset: byte offset from the module beginning
3356 * @length: length of the section to be read (in bytes from the offset)
3357 * @data: command buffer (size [bytes] = length)
3358 * @last_command: tells if this is the last command in a series
3359 * @cmd_details: pointer to command details structure or NULL
3361 * Read the NVM using the admin queue commands
3363 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3364 u32 offset, u16 length, void *data,
3366 struct i40e_asq_cmd_details *cmd_details)
3368 struct i40e_aq_desc desc;
3369 struct i40e_aqc_nvm_update *cmd =
3370 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3371 enum i40e_status_code status;
3373 DEBUGFUNC("i40e_aq_read_nvm");
3375 /* In offset the highest byte must be zeroed. */
3376 if (offset & 0xFF000000) {
3377 status = I40E_ERR_PARAM;
3378 goto i40e_aq_read_nvm_exit;
3381 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3383 /* If this is the last command in a series, set the proper flag. */
3385 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3386 cmd->module_pointer = module_pointer;
3387 cmd->offset = CPU_TO_LE32(offset);
3388 cmd->length = CPU_TO_LE16(length);
3390 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3391 if (length > I40E_AQ_LARGE_BUF)
3392 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3394 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3396 i40e_aq_read_nvm_exit:
3401 * i40e_aq_read_nvm_config - read an nvm config block
3402 * @hw: pointer to the hw struct
3403 * @cmd_flags: NVM access admin command bits
3404 * @field_id: field or feature id
3405 * @data: buffer for result
3406 * @buf_size: buffer size
3407 * @element_count: pointer to count of elements read by FW
3408 * @cmd_details: pointer to command details structure or NULL
3410 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3411 u8 cmd_flags, u32 field_id, void *data,
3412 u16 buf_size, u16 *element_count,
3413 struct i40e_asq_cmd_details *cmd_details)
3415 struct i40e_aq_desc desc;
3416 struct i40e_aqc_nvm_config_read *cmd =
3417 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3418 enum i40e_status_code status;
3420 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3421 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3422 if (buf_size > I40E_AQ_LARGE_BUF)
3423 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3425 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3426 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3427 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3428 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3430 cmd->element_id_msw = 0;
3432 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3434 if (!status && element_count)
3435 *element_count = LE16_TO_CPU(cmd->element_count);
3441 * i40e_aq_write_nvm_config - write an nvm config block
3442 * @hw: pointer to the hw struct
3443 * @cmd_flags: NVM access admin command bits
3444 * @data: buffer for result
3445 * @buf_size: buffer size
3446 * @element_count: count of elements to be written
3447 * @cmd_details: pointer to command details structure or NULL
3449 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3450 u8 cmd_flags, void *data, u16 buf_size,
3452 struct i40e_asq_cmd_details *cmd_details)
3454 struct i40e_aq_desc desc;
3455 struct i40e_aqc_nvm_config_write *cmd =
3456 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3457 enum i40e_status_code status;
3459 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3460 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3461 if (buf_size > I40E_AQ_LARGE_BUF)
3462 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3464 cmd->element_count = CPU_TO_LE16(element_count);
3465 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3466 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3472 * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3473 * @hw: pointer to the hw struct
3474 * @cmd_details: pointer to command details structure or NULL
3476 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3477 void *buff, u16 buff_size,
3478 struct i40e_asq_cmd_details *cmd_details)
3480 struct i40e_aq_desc desc;
3481 enum i40e_status_code status;
3483 UNREFERENCED_2PARAMETER(buff, buff_size);
3485 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3486 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3487 if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3488 status = I40E_ERR_NOT_IMPLEMENTED;
3495 * @hw: pointer to the hw struct
3496 * @module_pointer: module pointer location in words from the NVM beginning
3497 * @offset: offset in the module (expressed in 4 KB from module's beginning)
3498 * @length: length of the section to be erased (expressed in 4 KB)
3499 * @last_command: tells if this is the last command in a series
3500 * @cmd_details: pointer to command details structure or NULL
3502 * Erase the NVM sector using the admin queue commands
3504 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3505 u32 offset, u16 length, bool last_command,
3506 struct i40e_asq_cmd_details *cmd_details)
3508 struct i40e_aq_desc desc;
3509 struct i40e_aqc_nvm_update *cmd =
3510 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3511 enum i40e_status_code status;
3513 DEBUGFUNC("i40e_aq_erase_nvm");
3515 /* In offset the highest byte must be zeroed. */
3516 if (offset & 0xFF000000) {
3517 status = I40E_ERR_PARAM;
3518 goto i40e_aq_erase_nvm_exit;
3521 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3523 /* If this is the last command in a series, set the proper flag. */
3525 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3526 cmd->module_pointer = module_pointer;
3527 cmd->offset = CPU_TO_LE32(offset);
3528 cmd->length = CPU_TO_LE16(length);
3530 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3532 i40e_aq_erase_nvm_exit:
3537 * i40e_parse_discover_capabilities
3538 * @hw: pointer to the hw struct
3539 * @buff: pointer to a buffer containing device/function capability records
3540 * @cap_count: number of capability records in the list
3541 * @list_type_opc: type of capabilities list to parse
3543 * Parse the device/function capabilities list.
3545 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3547 enum i40e_admin_queue_opc list_type_opc)
3549 struct i40e_aqc_list_capabilities_element_resp *cap;
3550 u32 valid_functions, num_functions;
3551 u32 number, logical_id, phys_id;
3552 struct i40e_hw_capabilities *p;
3557 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3559 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3560 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3561 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3562 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3566 for (i = 0; i < cap_count; i++, cap++) {
3567 id = LE16_TO_CPU(cap->id);
3568 number = LE32_TO_CPU(cap->number);
3569 logical_id = LE32_TO_CPU(cap->logical_id);
3570 phys_id = LE32_TO_CPU(cap->phys_id);
3571 major_rev = cap->major_rev;
3574 case I40E_AQ_CAP_ID_SWITCH_MODE:
3575 p->switch_mode = number;
3576 i40e_debug(hw, I40E_DEBUG_INIT,
3577 "HW Capability: Switch mode = %d\n",
3580 case I40E_AQ_CAP_ID_MNG_MODE:
3581 p->management_mode = number;
3582 i40e_debug(hw, I40E_DEBUG_INIT,
3583 "HW Capability: Management Mode = %d\n",
3584 p->management_mode);
3586 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3587 p->npar_enable = number;
3588 i40e_debug(hw, I40E_DEBUG_INIT,
3589 "HW Capability: NPAR enable = %d\n",
3592 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3594 i40e_debug(hw, I40E_DEBUG_INIT,
3595 "HW Capability: OS2BMC = %d\n", p->os2bmc);
3597 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3598 p->valid_functions = number;
3599 i40e_debug(hw, I40E_DEBUG_INIT,
3600 "HW Capability: Valid Functions = %d\n",
3601 p->valid_functions);
3603 case I40E_AQ_CAP_ID_SRIOV:
3605 p->sr_iov_1_1 = true;
3606 i40e_debug(hw, I40E_DEBUG_INIT,
3607 "HW Capability: SR-IOV = %d\n",
3610 case I40E_AQ_CAP_ID_VF:
3611 p->num_vfs = number;
3612 p->vf_base_id = logical_id;
3613 i40e_debug(hw, I40E_DEBUG_INIT,
3614 "HW Capability: VF count = %d\n",
3616 i40e_debug(hw, I40E_DEBUG_INIT,
3617 "HW Capability: VF base_id = %d\n",
3620 case I40E_AQ_CAP_ID_VMDQ:
3623 i40e_debug(hw, I40E_DEBUG_INIT,
3624 "HW Capability: VMDQ = %d\n", p->vmdq);
3626 case I40E_AQ_CAP_ID_8021QBG:
3628 p->evb_802_1_qbg = true;
3629 i40e_debug(hw, I40E_DEBUG_INIT,
3630 "HW Capability: 802.1Qbg = %d\n", number);
3632 case I40E_AQ_CAP_ID_8021QBR:
3634 p->evb_802_1_qbh = true;
3635 i40e_debug(hw, I40E_DEBUG_INIT,
3636 "HW Capability: 802.1Qbh = %d\n", number);
3638 case I40E_AQ_CAP_ID_VSI:
3639 p->num_vsis = number;
3640 i40e_debug(hw, I40E_DEBUG_INIT,
3641 "HW Capability: VSI count = %d\n",
3644 case I40E_AQ_CAP_ID_DCB:
3647 p->enabled_tcmap = logical_id;
3650 i40e_debug(hw, I40E_DEBUG_INIT,
3651 "HW Capability: DCB = %d\n", p->dcb);
3652 i40e_debug(hw, I40E_DEBUG_INIT,
3653 "HW Capability: TC Mapping = %d\n",
3655 i40e_debug(hw, I40E_DEBUG_INIT,
3656 "HW Capability: TC Max = %d\n", p->maxtc);
3658 case I40E_AQ_CAP_ID_FCOE:
3661 i40e_debug(hw, I40E_DEBUG_INIT,
3662 "HW Capability: FCOE = %d\n", p->fcoe);
3664 case I40E_AQ_CAP_ID_ISCSI:
3667 i40e_debug(hw, I40E_DEBUG_INIT,
3668 "HW Capability: iSCSI = %d\n", p->iscsi);
3670 case I40E_AQ_CAP_ID_RSS:
3672 p->rss_table_size = number;
3673 p->rss_table_entry_width = logical_id;
3674 i40e_debug(hw, I40E_DEBUG_INIT,
3675 "HW Capability: RSS = %d\n", p->rss);
3676 i40e_debug(hw, I40E_DEBUG_INIT,
3677 "HW Capability: RSS table size = %d\n",
3679 i40e_debug(hw, I40E_DEBUG_INIT,
3680 "HW Capability: RSS table width = %d\n",
3681 p->rss_table_entry_width);
3683 case I40E_AQ_CAP_ID_RXQ:
3684 p->num_rx_qp = number;
3685 p->base_queue = phys_id;
3686 i40e_debug(hw, I40E_DEBUG_INIT,
3687 "HW Capability: Rx QP = %d\n", number);
3688 i40e_debug(hw, I40E_DEBUG_INIT,
3689 "HW Capability: base_queue = %d\n",
3692 case I40E_AQ_CAP_ID_TXQ:
3693 p->num_tx_qp = number;
3694 p->base_queue = phys_id;
3695 i40e_debug(hw, I40E_DEBUG_INIT,
3696 "HW Capability: Tx QP = %d\n", number);
3697 i40e_debug(hw, I40E_DEBUG_INIT,
3698 "HW Capability: base_queue = %d\n",
3701 case I40E_AQ_CAP_ID_MSIX:
3702 p->num_msix_vectors = number;
3703 i40e_debug(hw, I40E_DEBUG_INIT,
3704 "HW Capability: MSIX vector count = %d\n",
3705 p->num_msix_vectors);
3707 case I40E_AQ_CAP_ID_VF_MSIX:
3708 p->num_msix_vectors_vf = number;
3709 i40e_debug(hw, I40E_DEBUG_INIT,
3710 "HW Capability: MSIX VF vector count = %d\n",
3711 p->num_msix_vectors_vf);
3713 case I40E_AQ_CAP_ID_FLEX10:
3714 if (major_rev == 1) {
3716 p->flex10_enable = true;
3717 p->flex10_capable = true;
3720 /* Capability revision >= 2 */
3722 p->flex10_enable = true;
3724 p->flex10_capable = true;
3726 p->flex10_mode = logical_id;
3727 p->flex10_status = phys_id;
3728 i40e_debug(hw, I40E_DEBUG_INIT,
3729 "HW Capability: Flex10 mode = %d\n",
3731 i40e_debug(hw, I40E_DEBUG_INIT,
3732 "HW Capability: Flex10 status = %d\n",
3735 case I40E_AQ_CAP_ID_CEM:
3738 i40e_debug(hw, I40E_DEBUG_INIT,
3739 "HW Capability: CEM = %d\n", p->mgmt_cem);
3741 case I40E_AQ_CAP_ID_IWARP:
3744 i40e_debug(hw, I40E_DEBUG_INIT,
3745 "HW Capability: iWARP = %d\n", p->iwarp);
3747 case I40E_AQ_CAP_ID_LED:
3748 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3749 p->led[phys_id] = true;
3750 i40e_debug(hw, I40E_DEBUG_INIT,
3751 "HW Capability: LED - PIN %d\n", phys_id);
3753 case I40E_AQ_CAP_ID_SDP:
3754 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3755 p->sdp[phys_id] = true;
3756 i40e_debug(hw, I40E_DEBUG_INIT,
3757 "HW Capability: SDP - PIN %d\n", phys_id);
3759 case I40E_AQ_CAP_ID_MDIO:
3761 p->mdio_port_num = phys_id;
3762 p->mdio_port_mode = logical_id;
3764 i40e_debug(hw, I40E_DEBUG_INIT,
3765 "HW Capability: MDIO port number = %d\n",
3767 i40e_debug(hw, I40E_DEBUG_INIT,
3768 "HW Capability: MDIO port mode = %d\n",
3771 case I40E_AQ_CAP_ID_1588:
3773 p->ieee_1588 = true;
3774 i40e_debug(hw, I40E_DEBUG_INIT,
3775 "HW Capability: IEEE 1588 = %d\n",
3778 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3780 p->fd_filters_guaranteed = number;
3781 p->fd_filters_best_effort = logical_id;
3782 i40e_debug(hw, I40E_DEBUG_INIT,
3783 "HW Capability: Flow Director = 1\n");
3784 i40e_debug(hw, I40E_DEBUG_INIT,
3785 "HW Capability: Guaranteed FD filters = %d\n",
3786 p->fd_filters_guaranteed);
3788 case I40E_AQ_CAP_ID_WSR_PROT:
3789 p->wr_csr_prot = (u64)number;
3790 p->wr_csr_prot |= (u64)logical_id << 32;
3791 i40e_debug(hw, I40E_DEBUG_INIT,
3792 "HW Capability: wr_csr_prot = 0x%llX\n\n",
3793 (p->wr_csr_prot & 0xffff));
3795 case I40E_AQ_CAP_ID_NVM_MGMT:
3796 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3797 p->sec_rev_disabled = true;
3798 if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3799 p->update_disabled = true;
3802 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3803 hw->num_wol_proxy_filters = (u16)number;
3804 hw->wol_proxy_vsi_seid = (u16)logical_id;
3805 p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3806 if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3807 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3809 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3810 p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3811 p->proxy_support = p->proxy_support;
3812 i40e_debug(hw, I40E_DEBUG_INIT,
3813 "HW Capability: WOL proxy filters = %d\n",
3814 hw->num_wol_proxy_filters);
3823 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3825 #ifdef I40E_FCOE_ENA
3826 /* Software override ensuring FCoE is disabled if npar or mfp
3827 * mode because it is not supported in these modes.
3829 if (p->npar_enable || p->flex10_enable)
3832 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3836 /* count the enabled ports (aka the "not disabled" ports) */
3838 for (i = 0; i < 4; i++) {
3839 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3842 /* use AQ read to get the physical register offset instead
3843 * of the port relative offset
3845 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3846 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3850 valid_functions = p->valid_functions;
3852 while (valid_functions) {
3853 if (valid_functions & 1)
3855 valid_functions >>= 1;
3858 /* partition id is 1-based, and functions are evenly spread
3859 * across the ports as partitions
3861 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3862 hw->num_partitions = num_functions / hw->num_ports;
3864 /* additional HW specific goodies that might
3865 * someday be HW version specific
3867 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3871 * i40e_aq_discover_capabilities
3872 * @hw: pointer to the hw struct
3873 * @buff: a virtual buffer to hold the capabilities
3874 * @buff_size: Size of the virtual buffer
3875 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3876 * @list_type_opc: capabilities type to discover - pass in the command opcode
3877 * @cmd_details: pointer to command details structure or NULL
3879 * Get the device capabilities descriptions from the firmware
3881 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3882 void *buff, u16 buff_size, u16 *data_size,
3883 enum i40e_admin_queue_opc list_type_opc,
3884 struct i40e_asq_cmd_details *cmd_details)
3886 struct i40e_aqc_list_capabilites *cmd;
3887 struct i40e_aq_desc desc;
3888 enum i40e_status_code status = I40E_SUCCESS;
3890 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3892 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3893 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3894 status = I40E_ERR_PARAM;
3898 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3900 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3901 if (buff_size > I40E_AQ_LARGE_BUF)
3902 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3904 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3905 *data_size = LE16_TO_CPU(desc.datalen);
3910 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3918 * i40e_aq_update_nvm
3919 * @hw: pointer to the hw struct
3920 * @module_pointer: module pointer location in words from the NVM beginning
3921 * @offset: byte offset from the module beginning
3922 * @length: length of the section to be written (in bytes from the offset)
3923 * @data: command buffer (size [bytes] = length)
3924 * @last_command: tells if this is the last command in a series
3925 * @cmd_details: pointer to command details structure or NULL
3927 * Update the NVM using the admin queue commands
3929 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3930 u32 offset, u16 length, void *data,
3932 struct i40e_asq_cmd_details *cmd_details)
3934 struct i40e_aq_desc desc;
3935 struct i40e_aqc_nvm_update *cmd =
3936 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3937 enum i40e_status_code status;
3939 DEBUGFUNC("i40e_aq_update_nvm");
3941 /* In offset the highest byte must be zeroed. */
3942 if (offset & 0xFF000000) {
3943 status = I40E_ERR_PARAM;
3944 goto i40e_aq_update_nvm_exit;
3947 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3949 /* If this is the last command in a series, set the proper flag. */
3951 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3952 cmd->module_pointer = module_pointer;
3953 cmd->offset = CPU_TO_LE32(offset);
3954 cmd->length = CPU_TO_LE16(length);
3956 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3957 if (length > I40E_AQ_LARGE_BUF)
3958 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3960 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3962 i40e_aq_update_nvm_exit:
3967 * i40e_aq_get_lldp_mib
3968 * @hw: pointer to the hw struct
3969 * @bridge_type: type of bridge requested
3970 * @mib_type: Local, Remote or both Local and Remote MIBs
3971 * @buff: pointer to a user supplied buffer to store the MIB block
3972 * @buff_size: size of the buffer (in bytes)
3973 * @local_len : length of the returned Local LLDP MIB
3974 * @remote_len: length of the returned Remote LLDP MIB
3975 * @cmd_details: pointer to command details structure or NULL
3977 * Requests the complete LLDP MIB (entire packet).
3979 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3980 u8 mib_type, void *buff, u16 buff_size,
3981 u16 *local_len, u16 *remote_len,
3982 struct i40e_asq_cmd_details *cmd_details)
3984 struct i40e_aq_desc desc;
3985 struct i40e_aqc_lldp_get_mib *cmd =
3986 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3987 struct i40e_aqc_lldp_get_mib *resp =
3988 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3989 enum i40e_status_code status;
3991 if (buff_size == 0 || !buff)
3992 return I40E_ERR_PARAM;
3994 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3995 /* Indirect Command */
3996 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3998 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3999 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4000 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4002 desc.datalen = CPU_TO_LE16(buff_size);
4004 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4005 if (buff_size > I40E_AQ_LARGE_BUF)
4006 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4008 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4010 if (local_len != NULL)
4011 *local_len = LE16_TO_CPU(resp->local_len);
4012 if (remote_len != NULL)
4013 *remote_len = LE16_TO_CPU(resp->remote_len);
4020 * i40e_aq_set_lldp_mib - Set the LLDP MIB
4021 * @hw: pointer to the hw struct
4022 * @mib_type: Local, Remote or both Local and Remote MIBs
4023 * @buff: pointer to a user supplied buffer to store the MIB block
4024 * @buff_size: size of the buffer (in bytes)
4025 * @cmd_details: pointer to command details structure or NULL
4029 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4030 u8 mib_type, void *buff, u16 buff_size,
4031 struct i40e_asq_cmd_details *cmd_details)
4033 struct i40e_aq_desc desc;
4034 struct i40e_aqc_lldp_set_local_mib *cmd =
4035 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4036 enum i40e_status_code status;
4038 if (buff_size == 0 || !buff)
4039 return I40E_ERR_PARAM;
4041 i40e_fill_default_direct_cmd_desc(&desc,
4042 i40e_aqc_opc_lldp_set_local_mib);
4043 /* Indirect Command */
4044 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4045 if (buff_size > I40E_AQ_LARGE_BUF)
4046 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4047 desc.datalen = CPU_TO_LE16(buff_size);
4049 cmd->type = mib_type;
4050 cmd->length = CPU_TO_LE16(buff_size);
4051 cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4052 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4054 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4059 * i40e_aq_cfg_lldp_mib_change_event
4060 * @hw: pointer to the hw struct
4061 * @enable_update: Enable or Disable event posting
4062 * @cmd_details: pointer to command details structure or NULL
4064 * Enable or Disable posting of an event on ARQ when LLDP MIB
4065 * associated with the interface changes
4067 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4069 struct i40e_asq_cmd_details *cmd_details)
4071 struct i40e_aq_desc desc;
4072 struct i40e_aqc_lldp_update_mib *cmd =
4073 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4074 enum i40e_status_code status;
4076 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4079 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4081 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4087 * i40e_aq_add_lldp_tlv
4088 * @hw: pointer to the hw struct
4089 * @bridge_type: type of bridge
4090 * @buff: buffer with TLV to add
4091 * @buff_size: length of the buffer
4092 * @tlv_len: length of the TLV to be added
4093 * @mib_len: length of the LLDP MIB returned in response
4094 * @cmd_details: pointer to command details structure or NULL
4096 * Add the specified TLV to LLDP Local MIB for the given bridge type,
4097 * it is responsibility of the caller to make sure that the TLV is not
4098 * already present in the LLDPDU.
4099 * In return firmware will write the complete LLDP MIB with the newly
4100 * added TLV in the response buffer.
4102 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4103 void *buff, u16 buff_size, u16 tlv_len,
4105 struct i40e_asq_cmd_details *cmd_details)
4107 struct i40e_aq_desc desc;
4108 struct i40e_aqc_lldp_add_tlv *cmd =
4109 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4110 enum i40e_status_code status;
4112 if (buff_size == 0 || !buff || tlv_len == 0)
4113 return I40E_ERR_PARAM;
4115 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4117 /* Indirect Command */
4118 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4119 if (buff_size > I40E_AQ_LARGE_BUF)
4120 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4121 desc.datalen = CPU_TO_LE16(buff_size);
4123 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4124 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4125 cmd->len = CPU_TO_LE16(tlv_len);
4127 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4129 if (mib_len != NULL)
4130 *mib_len = LE16_TO_CPU(desc.datalen);
4137 * i40e_aq_update_lldp_tlv
4138 * @hw: pointer to the hw struct
4139 * @bridge_type: type of bridge
4140 * @buff: buffer with TLV to update
4141 * @buff_size: size of the buffer holding original and updated TLVs
4142 * @old_len: Length of the Original TLV
4143 * @new_len: Length of the Updated TLV
4144 * @offset: offset of the updated TLV in the buff
4145 * @mib_len: length of the returned LLDP MIB
4146 * @cmd_details: pointer to command details structure or NULL
4148 * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4149 * Firmware will place the complete LLDP MIB in response buffer with the
4152 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4153 u8 bridge_type, void *buff, u16 buff_size,
4154 u16 old_len, u16 new_len, u16 offset,
4156 struct i40e_asq_cmd_details *cmd_details)
4158 struct i40e_aq_desc desc;
4159 struct i40e_aqc_lldp_update_tlv *cmd =
4160 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4161 enum i40e_status_code status;
4163 if (buff_size == 0 || !buff || offset == 0 ||
4164 old_len == 0 || new_len == 0)
4165 return I40E_ERR_PARAM;
4167 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4169 /* Indirect Command */
4170 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4171 if (buff_size > I40E_AQ_LARGE_BUF)
4172 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4173 desc.datalen = CPU_TO_LE16(buff_size);
4175 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4176 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4177 cmd->old_len = CPU_TO_LE16(old_len);
4178 cmd->new_offset = CPU_TO_LE16(offset);
4179 cmd->new_len = CPU_TO_LE16(new_len);
4181 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4183 if (mib_len != NULL)
4184 *mib_len = LE16_TO_CPU(desc.datalen);
4191 * i40e_aq_delete_lldp_tlv
4192 * @hw: pointer to the hw struct
4193 * @bridge_type: type of bridge
4194 * @buff: pointer to a user supplied buffer that has the TLV
4195 * @buff_size: length of the buffer
4196 * @tlv_len: length of the TLV to be deleted
4197 * @mib_len: length of the returned LLDP MIB
4198 * @cmd_details: pointer to command details structure or NULL
4200 * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4201 * The firmware places the entire LLDP MIB in the response buffer.
4203 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4204 u8 bridge_type, void *buff, u16 buff_size,
4205 u16 tlv_len, u16 *mib_len,
4206 struct i40e_asq_cmd_details *cmd_details)
4208 struct i40e_aq_desc desc;
4209 struct i40e_aqc_lldp_add_tlv *cmd =
4210 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4211 enum i40e_status_code status;
4213 if (buff_size == 0 || !buff)
4214 return I40E_ERR_PARAM;
4216 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4218 /* Indirect Command */
4219 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4220 if (buff_size > I40E_AQ_LARGE_BUF)
4221 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4222 desc.datalen = CPU_TO_LE16(buff_size);
4223 cmd->len = CPU_TO_LE16(tlv_len);
4224 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4225 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4227 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4229 if (mib_len != NULL)
4230 *mib_len = LE16_TO_CPU(desc.datalen);
4238 * @hw: pointer to the hw struct
4239 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4240 * @cmd_details: pointer to command details structure or NULL
4242 * Stop or Shutdown the embedded LLDP Agent
4244 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4245 struct i40e_asq_cmd_details *cmd_details)
4247 struct i40e_aq_desc desc;
4248 struct i40e_aqc_lldp_stop *cmd =
4249 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4250 enum i40e_status_code status;
4252 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4255 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4257 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4263 * i40e_aq_start_lldp
4264 * @hw: pointer to the hw struct
4265 * @cmd_details: pointer to command details structure or NULL
4267 * Start the embedded LLDP Agent on all ports.
4269 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4270 struct i40e_asq_cmd_details *cmd_details)
4272 struct i40e_aq_desc desc;
4273 struct i40e_aqc_lldp_start *cmd =
4274 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4275 enum i40e_status_code status;
4277 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4279 cmd->command = I40E_AQ_LLDP_AGENT_START;
4281 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4287 * i40e_aq_get_cee_dcb_config
4288 * @hw: pointer to the hw struct
4289 * @buff: response buffer that stores CEE operational configuration
4290 * @buff_size: size of the buffer passed
4291 * @cmd_details: pointer to command details structure or NULL
4293 * Get CEE DCBX mode operational configuration from firmware
4295 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4296 void *buff, u16 buff_size,
4297 struct i40e_asq_cmd_details *cmd_details)
4299 struct i40e_aq_desc desc;
4300 enum i40e_status_code status;
4302 if (buff_size == 0 || !buff)
4303 return I40E_ERR_PARAM;
4305 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4307 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4308 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4315 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4316 * @hw: pointer to the hw struct
4317 * @start_agent: True if DCBx Agent needs to be Started
4318 * False if DCBx Agent needs to be Stopped
4319 * @cmd_details: pointer to command details structure or NULL
4321 * Start/Stop the embedded dcbx Agent
4323 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4325 struct i40e_asq_cmd_details *cmd_details)
4327 struct i40e_aq_desc desc;
4328 struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4329 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4331 enum i40e_status_code status;
4333 i40e_fill_default_direct_cmd_desc(&desc,
4334 i40e_aqc_opc_lldp_stop_start_spec_agent);
4337 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4339 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4345 * i40e_aq_add_udp_tunnel
4346 * @hw: pointer to the hw struct
4347 * @udp_port: the UDP port to add
4348 * @header_len: length of the tunneling header length in DWords
4349 * @protocol_index: protocol index type
4350 * @filter_index: pointer to filter index
4351 * @cmd_details: pointer to command details structure or NULL
4353 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4354 u16 udp_port, u8 protocol_index,
4356 struct i40e_asq_cmd_details *cmd_details)
4358 struct i40e_aq_desc desc;
4359 struct i40e_aqc_add_udp_tunnel *cmd =
4360 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4361 struct i40e_aqc_del_udp_tunnel_completion *resp =
4362 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4363 enum i40e_status_code status;
4365 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4367 cmd->udp_port = CPU_TO_LE16(udp_port);
4368 cmd->protocol_type = protocol_index;
4370 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4372 if (!status && filter_index)
4373 *filter_index = resp->index;
4379 * i40e_aq_del_udp_tunnel
4380 * @hw: pointer to the hw struct
4381 * @index: filter index
4382 * @cmd_details: pointer to command details structure or NULL
4384 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4385 struct i40e_asq_cmd_details *cmd_details)
4387 struct i40e_aq_desc desc;
4388 struct i40e_aqc_remove_udp_tunnel *cmd =
4389 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4390 enum i40e_status_code status;
4392 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4396 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4402 * i40e_aq_get_switch_resource_alloc (0x0204)
4403 * @hw: pointer to the hw struct
4404 * @num_entries: pointer to u8 to store the number of resource entries returned
4405 * @buf: pointer to a user supplied buffer. This buffer must be large enough
4406 * to store the resource information for all resource types. Each
4407 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
4408 * @count: size, in bytes, of the buffer provided
4409 * @cmd_details: pointer to command details structure or NULL
4411 * Query the resources allocated to a function.
4413 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4415 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4417 struct i40e_asq_cmd_details *cmd_details)
4419 struct i40e_aq_desc desc;
4420 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4421 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4422 enum i40e_status_code status;
4423 u16 length = count * sizeof(*buf);
4425 i40e_fill_default_direct_cmd_desc(&desc,
4426 i40e_aqc_opc_get_switch_resource_alloc);
4428 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4429 if (length > I40E_AQ_LARGE_BUF)
4430 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4432 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4434 if (!status && num_entries)
4435 *num_entries = cmd_resp->num_entries;
4441 * i40e_aq_delete_element - Delete switch element
4442 * @hw: pointer to the hw struct
4443 * @seid: the SEID to delete from the switch
4444 * @cmd_details: pointer to command details structure or NULL
4446 * This deletes a switch element from the switch.
4448 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4449 struct i40e_asq_cmd_details *cmd_details)
4451 struct i40e_aq_desc desc;
4452 struct i40e_aqc_switch_seid *cmd =
4453 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4454 enum i40e_status_code status;
4457 return I40E_ERR_PARAM;
4459 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4461 cmd->seid = CPU_TO_LE16(seid);
4463 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4469 * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4470 * @hw: pointer to the hw struct
4471 * @flags: component flags
4472 * @mac_seid: uplink seid (MAC SEID)
4473 * @vsi_seid: connected vsi seid
4474 * @ret_seid: seid of create pv component
4476 * This instantiates an i40e port virtualizer with specified flags.
4477 * Depending on specified flags the port virtualizer can act as a
4478 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4480 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4481 u16 mac_seid, u16 vsi_seid,
4484 struct i40e_aq_desc desc;
4485 struct i40e_aqc_add_update_pv *cmd =
4486 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4487 struct i40e_aqc_add_update_pv_completion *resp =
4488 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4489 enum i40e_status_code status;
4492 return I40E_ERR_PARAM;
4494 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4495 cmd->command_flags = CPU_TO_LE16(flags);
4496 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4497 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4499 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4500 if (!status && ret_seid)
4501 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4507 * i40e_aq_add_tag - Add an S/E-tag
4508 * @hw: pointer to the hw struct
4509 * @direct_to_queue: should s-tag direct flow to a specific queue
4510 * @vsi_seid: VSI SEID to use this tag
4511 * @tag: value of the tag
4512 * @queue_num: queue number, only valid is direct_to_queue is true
4513 * @tags_used: return value, number of tags in use by this PF
4514 * @tags_free: return value, number of unallocated tags
4515 * @cmd_details: pointer to command details structure or NULL
4517 * This associates an S- or E-tag to a VSI in the switch complex. It returns
4518 * the number of tags allocated by the PF, and the number of unallocated
4521 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4522 u16 vsi_seid, u16 tag, u16 queue_num,
4523 u16 *tags_used, u16 *tags_free,
4524 struct i40e_asq_cmd_details *cmd_details)
4526 struct i40e_aq_desc desc;
4527 struct i40e_aqc_add_tag *cmd =
4528 (struct i40e_aqc_add_tag *)&desc.params.raw;
4529 struct i40e_aqc_add_remove_tag_completion *resp =
4530 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4531 enum i40e_status_code status;
4534 return I40E_ERR_PARAM;
4536 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4538 cmd->seid = CPU_TO_LE16(vsi_seid);
4539 cmd->tag = CPU_TO_LE16(tag);
4540 if (direct_to_queue) {
4541 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4542 cmd->queue_number = CPU_TO_LE16(queue_num);
4545 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4548 if (tags_used != NULL)
4549 *tags_used = LE16_TO_CPU(resp->tags_used);
4550 if (tags_free != NULL)
4551 *tags_free = LE16_TO_CPU(resp->tags_free);
4558 * i40e_aq_remove_tag - Remove an S- or E-tag
4559 * @hw: pointer to the hw struct
4560 * @vsi_seid: VSI SEID this tag is associated with
4561 * @tag: value of the S-tag to delete
4562 * @tags_used: return value, number of tags in use by this PF
4563 * @tags_free: return value, number of unallocated tags
4564 * @cmd_details: pointer to command details structure or NULL
4566 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
4567 * the number of tags allocated by the PF, and the number of unallocated
4570 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4571 u16 tag, u16 *tags_used, u16 *tags_free,
4572 struct i40e_asq_cmd_details *cmd_details)
4574 struct i40e_aq_desc desc;
4575 struct i40e_aqc_remove_tag *cmd =
4576 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4577 struct i40e_aqc_add_remove_tag_completion *resp =
4578 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4579 enum i40e_status_code status;
4582 return I40E_ERR_PARAM;
4584 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4586 cmd->seid = CPU_TO_LE16(vsi_seid);
4587 cmd->tag = CPU_TO_LE16(tag);
4589 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4592 if (tags_used != NULL)
4593 *tags_used = LE16_TO_CPU(resp->tags_used);
4594 if (tags_free != NULL)
4595 *tags_free = LE16_TO_CPU(resp->tags_free);
4602 * i40e_aq_add_mcast_etag - Add a multicast E-tag
4603 * @hw: pointer to the hw struct
4604 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4605 * @etag: value of E-tag to add
4606 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4607 * @buf: address of indirect buffer
4608 * @tags_used: return value, number of E-tags in use by this port
4609 * @tags_free: return value, number of unallocated M-tags
4610 * @cmd_details: pointer to command details structure or NULL
4612 * This associates a multicast E-tag to a port virtualizer. It will return
4613 * the number of tags allocated by the PF, and the number of unallocated
4616 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4617 * num_tags_in_buf long.
4619 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4620 u16 etag, u8 num_tags_in_buf, void *buf,
4621 u16 *tags_used, u16 *tags_free,
4622 struct i40e_asq_cmd_details *cmd_details)
4624 struct i40e_aq_desc desc;
4625 struct i40e_aqc_add_remove_mcast_etag *cmd =
4626 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4627 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4628 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4629 enum i40e_status_code status;
4630 u16 length = sizeof(u16) * num_tags_in_buf;
4632 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4633 return I40E_ERR_PARAM;
4635 i40e_fill_default_direct_cmd_desc(&desc,
4636 i40e_aqc_opc_add_multicast_etag);
4638 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4639 cmd->etag = CPU_TO_LE16(etag);
4640 cmd->num_unicast_etags = num_tags_in_buf;
4642 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4643 if (length > I40E_AQ_LARGE_BUF)
4644 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4646 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4649 if (tags_used != NULL)
4650 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4651 if (tags_free != NULL)
4652 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4659 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4660 * @hw: pointer to the hw struct
4661 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4662 * @etag: value of the E-tag to remove
4663 * @tags_used: return value, number of tags in use by this port
4664 * @tags_free: return value, number of unallocated tags
4665 * @cmd_details: pointer to command details structure or NULL
4667 * This deletes an E-tag from the port virtualizer. It will return
4668 * the number of tags allocated by the port, and the number of unallocated
4671 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4672 u16 etag, u16 *tags_used, u16 *tags_free,
4673 struct i40e_asq_cmd_details *cmd_details)
4675 struct i40e_aq_desc desc;
4676 struct i40e_aqc_add_remove_mcast_etag *cmd =
4677 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4678 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4679 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4680 enum i40e_status_code status;
4684 return I40E_ERR_PARAM;
4686 i40e_fill_default_direct_cmd_desc(&desc,
4687 i40e_aqc_opc_remove_multicast_etag);
4689 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4690 cmd->etag = CPU_TO_LE16(etag);
4692 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4695 if (tags_used != NULL)
4696 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4697 if (tags_free != NULL)
4698 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4705 * i40e_aq_update_tag - Update an S/E-tag
4706 * @hw: pointer to the hw struct
4707 * @vsi_seid: VSI SEID using this S-tag
4708 * @old_tag: old tag value
4709 * @new_tag: new tag value
4710 * @tags_used: return value, number of tags in use by this PF
4711 * @tags_free: return value, number of unallocated tags
4712 * @cmd_details: pointer to command details structure or NULL
4714 * This updates the value of the tag currently attached to this VSI
4715 * in the switch complex. It will return the number of tags allocated
4716 * by the PF, and the number of unallocated tags available.
4718 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4719 u16 old_tag, u16 new_tag, u16 *tags_used,
4721 struct i40e_asq_cmd_details *cmd_details)
4723 struct i40e_aq_desc desc;
4724 struct i40e_aqc_update_tag *cmd =
4725 (struct i40e_aqc_update_tag *)&desc.params.raw;
4726 struct i40e_aqc_update_tag_completion *resp =
4727 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4728 enum i40e_status_code status;
4731 return I40E_ERR_PARAM;
4733 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4735 cmd->seid = CPU_TO_LE16(vsi_seid);
4736 cmd->old_tag = CPU_TO_LE16(old_tag);
4737 cmd->new_tag = CPU_TO_LE16(new_tag);
4739 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4742 if (tags_used != NULL)
4743 *tags_used = LE16_TO_CPU(resp->tags_used);
4744 if (tags_free != NULL)
4745 *tags_free = LE16_TO_CPU(resp->tags_free);
4752 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4753 * @hw: pointer to the hw struct
4754 * @tcmap: TC map for request/release any ignore PFC condition
4755 * @request: request or release ignore PFC condition
4756 * @tcmap_ret: return TCs for which PFC is currently ignored
4757 * @cmd_details: pointer to command details structure or NULL
4759 * This sends out request/release to ignore PFC condition for a TC.
4760 * It will return the TCs for which PFC is currently ignored.
4762 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4763 bool request, u8 *tcmap_ret,
4764 struct i40e_asq_cmd_details *cmd_details)
4766 struct i40e_aq_desc desc;
4767 struct i40e_aqc_pfc_ignore *cmd_resp =
4768 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4769 enum i40e_status_code status;
4771 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4774 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4776 cmd_resp->tc_bitmap = tcmap;
4778 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4781 if (tcmap_ret != NULL)
4782 *tcmap_ret = cmd_resp->tc_bitmap;
4789 * i40e_aq_dcb_updated - DCB Updated Command
4790 * @hw: pointer to the hw struct
4791 * @cmd_details: pointer to command details structure or NULL
4793 * When LLDP is handled in PF this command is used by the PF
4794 * to notify EMP that a DCB setting is modified.
4795 * When LLDP is handled in EMP this command is used by the PF
4796 * to notify EMP whenever one of the following parameters get
4798 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4799 * - PCIRTT in PRTDCB_GENC.PCIRTT
4800 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4801 * EMP will return when the shared RPB settings have been
4802 * recomputed and modified. The retval field in the descriptor
4803 * will be set to 0 when RPB is modified.
4805 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4806 struct i40e_asq_cmd_details *cmd_details)
4808 struct i40e_aq_desc desc;
4809 enum i40e_status_code status;
4811 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4813 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4819 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4820 * @hw: pointer to the hw struct
4821 * @seid: defines the SEID of the switch for which the stats are requested
4822 * @vlan_id: the VLAN ID for which the statistics are requested
4823 * @stat_index: index of the statistics counters block assigned to this VLAN
4824 * @cmd_details: pointer to command details structure or NULL
4826 * XL710 supports 128 smonVlanStats counters.This command is used to
4827 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4830 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4831 u16 vlan_id, u16 *stat_index,
4832 struct i40e_asq_cmd_details *cmd_details)
4834 struct i40e_aq_desc desc;
4835 struct i40e_aqc_add_remove_statistics *cmd_resp =
4836 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4837 enum i40e_status_code status;
4839 if ((seid == 0) || (stat_index == NULL))
4840 return I40E_ERR_PARAM;
4842 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4844 cmd_resp->seid = CPU_TO_LE16(seid);
4845 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4847 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4849 if (!status && stat_index)
4850 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4856 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4857 * @hw: pointer to the hw struct
4858 * @seid: defines the SEID of the switch for which the stats are requested
4859 * @vlan_id: the VLAN ID for which the statistics are requested
4860 * @stat_index: index of the statistics counters block assigned to this VLAN
4861 * @cmd_details: pointer to command details structure or NULL
4863 * XL710 supports 128 smonVlanStats counters.This command is used to
4864 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4867 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4868 u16 vlan_id, u16 stat_index,
4869 struct i40e_asq_cmd_details *cmd_details)
4871 struct i40e_aq_desc desc;
4872 struct i40e_aqc_add_remove_statistics *cmd =
4873 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4874 enum i40e_status_code status;
4877 return I40E_ERR_PARAM;
4879 i40e_fill_default_direct_cmd_desc(&desc,
4880 i40e_aqc_opc_remove_statistics);
4882 cmd->seid = CPU_TO_LE16(seid);
4883 cmd->vlan = CPU_TO_LE16(vlan_id);
4884 cmd->stat_index = CPU_TO_LE16(stat_index);
4886 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4892 * i40e_aq_set_port_parameters - set physical port parameters.
4893 * @hw: pointer to the hw struct
4894 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4895 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4896 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4897 * @double_vlan: if set double VLAN is enabled
4898 * @cmd_details: pointer to command details structure or NULL
4900 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4901 u16 bad_frame_vsi, bool save_bad_pac,
4902 bool pad_short_pac, bool double_vlan,
4903 struct i40e_asq_cmd_details *cmd_details)
4905 struct i40e_aqc_set_port_parameters *cmd;
4906 enum i40e_status_code status;
4907 struct i40e_aq_desc desc;
4908 u16 command_flags = 0;
4910 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4912 i40e_fill_default_direct_cmd_desc(&desc,
4913 i40e_aqc_opc_set_port_parameters);
4915 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4917 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4919 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4921 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4922 cmd->command_flags = CPU_TO_LE16(command_flags);
4924 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4930 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
4931 * @hw: pointer to the hw struct
4932 * @seid: seid for the physical port/switching component/vsi
4933 * @buff: Indirect buffer to hold data parameters and response
4934 * @buff_size: Indirect buffer size
4935 * @opcode: Tx scheduler AQ command opcode
4936 * @cmd_details: pointer to command details structure or NULL
4938 * Generic command handler for Tx scheduler AQ commands
4940 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
4941 void *buff, u16 buff_size,
4942 enum i40e_admin_queue_opc opcode,
4943 struct i40e_asq_cmd_details *cmd_details)
4945 struct i40e_aq_desc desc;
4946 struct i40e_aqc_tx_sched_ind *cmd =
4947 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4948 enum i40e_status_code status;
4949 bool cmd_param_flag = false;
4952 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
4953 case i40e_aqc_opc_configure_vsi_tc_bw:
4954 case i40e_aqc_opc_enable_switching_comp_ets:
4955 case i40e_aqc_opc_modify_switching_comp_ets:
4956 case i40e_aqc_opc_disable_switching_comp_ets:
4957 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
4958 case i40e_aqc_opc_configure_switching_comp_bw_config:
4959 cmd_param_flag = true;
4961 case i40e_aqc_opc_query_vsi_bw_config:
4962 case i40e_aqc_opc_query_vsi_ets_sla_config:
4963 case i40e_aqc_opc_query_switching_comp_ets_config:
4964 case i40e_aqc_opc_query_port_ets_config:
4965 case i40e_aqc_opc_query_switching_comp_bw_config:
4966 cmd_param_flag = false;
4969 return I40E_ERR_PARAM;
4972 i40e_fill_default_direct_cmd_desc(&desc, opcode);
4974 /* Indirect command */
4975 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4977 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4978 if (buff_size > I40E_AQ_LARGE_BUF)
4979 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4981 desc.datalen = CPU_TO_LE16(buff_size);
4983 cmd->vsi_seid = CPU_TO_LE16(seid);
4985 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4991 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
4992 * @hw: pointer to the hw struct
4994 * @credit: BW limit credits (0 = disabled)
4995 * @max_credit: Max BW limit credits
4996 * @cmd_details: pointer to command details structure or NULL
4998 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
4999 u16 seid, u16 credit, u8 max_credit,
5000 struct i40e_asq_cmd_details *cmd_details)
5002 struct i40e_aq_desc desc;
5003 struct i40e_aqc_configure_vsi_bw_limit *cmd =
5004 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5005 enum i40e_status_code status;
5007 i40e_fill_default_direct_cmd_desc(&desc,
5008 i40e_aqc_opc_configure_vsi_bw_limit);
5010 cmd->vsi_seid = CPU_TO_LE16(seid);
5011 cmd->credit = CPU_TO_LE16(credit);
5012 cmd->max_credit = max_credit;
5014 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5020 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5021 * @hw: pointer to the hw struct
5022 * @seid: switching component seid
5023 * @credit: BW limit credits (0 = disabled)
5024 * @max_bw: Max BW limit credits
5025 * @cmd_details: pointer to command details structure or NULL
5027 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5028 u16 seid, u16 credit, u8 max_bw,
5029 struct i40e_asq_cmd_details *cmd_details)
5031 struct i40e_aq_desc desc;
5032 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5033 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5034 enum i40e_status_code status;
5036 i40e_fill_default_direct_cmd_desc(&desc,
5037 i40e_aqc_opc_configure_switching_comp_bw_limit);
5039 cmd->seid = CPU_TO_LE16(seid);
5040 cmd->credit = CPU_TO_LE16(credit);
5041 cmd->max_bw = max_bw;
5043 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5049 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5050 * @hw: pointer to the hw struct
5052 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5053 * @cmd_details: pointer to command details structure or NULL
5055 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5057 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5058 struct i40e_asq_cmd_details *cmd_details)
5060 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5061 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5066 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5067 * @hw: pointer to the hw struct
5069 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5070 * @cmd_details: pointer to command details structure or NULL
5072 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5074 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5075 struct i40e_asq_cmd_details *cmd_details)
5077 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5078 i40e_aqc_opc_configure_vsi_tc_bw,
5083 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5084 * @hw: pointer to the hw struct
5085 * @seid: seid of the switching component connected to Physical Port
5086 * @ets_data: Buffer holding ETS parameters
5087 * @cmd_details: pointer to command details structure or NULL
5089 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5091 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5092 enum i40e_admin_queue_opc opcode,
5093 struct i40e_asq_cmd_details *cmd_details)
5095 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5096 sizeof(*ets_data), opcode, cmd_details);
5100 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5101 * @hw: pointer to the hw struct
5102 * @seid: seid of the switching component
5103 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5104 * @cmd_details: pointer to command details structure or NULL
5106 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5108 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5109 struct i40e_asq_cmd_details *cmd_details)
5111 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5112 i40e_aqc_opc_configure_switching_comp_bw_config,
5117 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5118 * @hw: pointer to the hw struct
5119 * @seid: seid of the switching component
5120 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5121 * @cmd_details: pointer to command details structure or NULL
5123 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5124 struct i40e_hw *hw, u16 seid,
5125 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5126 struct i40e_asq_cmd_details *cmd_details)
5128 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5129 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5134 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5135 * @hw: pointer to the hw struct
5136 * @seid: seid of the VSI
5137 * @bw_data: Buffer to hold VSI BW configuration
5138 * @cmd_details: pointer to command details structure or NULL
5140 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5142 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5143 struct i40e_asq_cmd_details *cmd_details)
5145 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5146 i40e_aqc_opc_query_vsi_bw_config,
5151 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5152 * @hw: pointer to the hw struct
5153 * @seid: seid of the VSI
5154 * @bw_data: Buffer to hold VSI BW configuration per TC
5155 * @cmd_details: pointer to command details structure or NULL
5157 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5159 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5160 struct i40e_asq_cmd_details *cmd_details)
5162 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5163 i40e_aqc_opc_query_vsi_ets_sla_config,
5168 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5169 * @hw: pointer to the hw struct
5170 * @seid: seid of the switching component
5171 * @bw_data: Buffer to hold switching component's per TC BW config
5172 * @cmd_details: pointer to command details structure or NULL
5174 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5176 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5177 struct i40e_asq_cmd_details *cmd_details)
5179 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5180 i40e_aqc_opc_query_switching_comp_ets_config,
5185 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5186 * @hw: pointer to the hw struct
5187 * @seid: seid of the VSI or switching component connected to Physical Port
5188 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5189 * @cmd_details: pointer to command details structure or NULL
5191 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5193 struct i40e_aqc_query_port_ets_config_resp *bw_data,
5194 struct i40e_asq_cmd_details *cmd_details)
5196 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5197 i40e_aqc_opc_query_port_ets_config,
5202 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5203 * @hw: pointer to the hw struct
5204 * @seid: seid of the switching component
5205 * @bw_data: Buffer to hold switching component's BW configuration
5206 * @cmd_details: pointer to command details structure or NULL
5208 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5210 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5211 struct i40e_asq_cmd_details *cmd_details)
5213 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5214 i40e_aqc_opc_query_switching_comp_bw_config,
5219 * i40e_validate_filter_settings
5220 * @hw: pointer to the hardware structure
5221 * @settings: Filter control settings
5223 * Check and validate the filter control settings passed.
5224 * The function checks for the valid filter/context sizes being
5225 * passed for FCoE and PE.
5227 * Returns I40E_SUCCESS if the values passed are valid and within
5228 * range else returns an error.
5230 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5231 struct i40e_filter_control_settings *settings)
5233 u32 fcoe_cntx_size, fcoe_filt_size;
5234 u32 pe_cntx_size, pe_filt_size;
5239 /* Validate FCoE settings passed */
5240 switch (settings->fcoe_filt_num) {
5241 case I40E_HASH_FILTER_SIZE_1K:
5242 case I40E_HASH_FILTER_SIZE_2K:
5243 case I40E_HASH_FILTER_SIZE_4K:
5244 case I40E_HASH_FILTER_SIZE_8K:
5245 case I40E_HASH_FILTER_SIZE_16K:
5246 case I40E_HASH_FILTER_SIZE_32K:
5247 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5248 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5251 return I40E_ERR_PARAM;
5254 switch (settings->fcoe_cntx_num) {
5255 case I40E_DMA_CNTX_SIZE_512:
5256 case I40E_DMA_CNTX_SIZE_1K:
5257 case I40E_DMA_CNTX_SIZE_2K:
5258 case I40E_DMA_CNTX_SIZE_4K:
5259 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5260 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5263 return I40E_ERR_PARAM;
5266 /* Validate PE settings passed */
5267 switch (settings->pe_filt_num) {
5268 case I40E_HASH_FILTER_SIZE_1K:
5269 case I40E_HASH_FILTER_SIZE_2K:
5270 case I40E_HASH_FILTER_SIZE_4K:
5271 case I40E_HASH_FILTER_SIZE_8K:
5272 case I40E_HASH_FILTER_SIZE_16K:
5273 case I40E_HASH_FILTER_SIZE_32K:
5274 case I40E_HASH_FILTER_SIZE_64K:
5275 case I40E_HASH_FILTER_SIZE_128K:
5276 case I40E_HASH_FILTER_SIZE_256K:
5277 case I40E_HASH_FILTER_SIZE_512K:
5278 case I40E_HASH_FILTER_SIZE_1M:
5279 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5280 pe_filt_size <<= (u32)settings->pe_filt_num;
5283 return I40E_ERR_PARAM;
5286 switch (settings->pe_cntx_num) {
5287 case I40E_DMA_CNTX_SIZE_512:
5288 case I40E_DMA_CNTX_SIZE_1K:
5289 case I40E_DMA_CNTX_SIZE_2K:
5290 case I40E_DMA_CNTX_SIZE_4K:
5291 case I40E_DMA_CNTX_SIZE_8K:
5292 case I40E_DMA_CNTX_SIZE_16K:
5293 case I40E_DMA_CNTX_SIZE_32K:
5294 case I40E_DMA_CNTX_SIZE_64K:
5295 case I40E_DMA_CNTX_SIZE_128K:
5296 case I40E_DMA_CNTX_SIZE_256K:
5297 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5298 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5301 return I40E_ERR_PARAM;
5304 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5305 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5306 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5307 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5308 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
5309 return I40E_ERR_INVALID_SIZE;
5311 return I40E_SUCCESS;
5315 * i40e_set_filter_control
5316 * @hw: pointer to the hardware structure
5317 * @settings: Filter control settings
5319 * Set the Queue Filters for PE/FCoE and enable filters required
5320 * for a single PF. It is expected that these settings are programmed
5321 * at the driver initialization time.
5323 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5324 struct i40e_filter_control_settings *settings)
5326 enum i40e_status_code ret = I40E_SUCCESS;
5327 u32 hash_lut_size = 0;
5331 return I40E_ERR_PARAM;
5333 /* Validate the input settings */
5334 ret = i40e_validate_filter_settings(hw, settings);
5338 /* Read the PF Queue Filter control register */
5339 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5341 /* Program required PE hash buckets for the PF */
5342 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5343 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5344 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5345 /* Program required PE contexts for the PF */
5346 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5347 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5348 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5350 /* Program required FCoE hash buckets for the PF */
5351 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5352 val |= ((u32)settings->fcoe_filt_num <<
5353 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5354 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5355 /* Program required FCoE DDP contexts for the PF */
5356 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5357 val |= ((u32)settings->fcoe_cntx_num <<
5358 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5359 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5361 /* Program Hash LUT size for the PF */
5362 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5363 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5365 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5366 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5368 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5369 if (settings->enable_fdir)
5370 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5371 if (settings->enable_ethtype)
5372 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5373 if (settings->enable_macvlan)
5374 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5376 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5378 return I40E_SUCCESS;
5382 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5383 * @hw: pointer to the hw struct
5384 * @mac_addr: MAC address to use in the filter
5385 * @ethtype: Ethertype to use in the filter
5386 * @flags: Flags that needs to be applied to the filter
5387 * @vsi_seid: seid of the control VSI
5388 * @queue: VSI queue number to send the packet to
5389 * @is_add: Add control packet filter if True else remove
5390 * @stats: Structure to hold information on control filter counts
5391 * @cmd_details: pointer to command details structure or NULL
5393 * This command will Add or Remove control packet filter for a control VSI.
5394 * In return it will update the total number of perfect filter count in
5397 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5398 u8 *mac_addr, u16 ethtype, u16 flags,
5399 u16 vsi_seid, u16 queue, bool is_add,
5400 struct i40e_control_filter_stats *stats,
5401 struct i40e_asq_cmd_details *cmd_details)
5403 struct i40e_aq_desc desc;
5404 struct i40e_aqc_add_remove_control_packet_filter *cmd =
5405 (struct i40e_aqc_add_remove_control_packet_filter *)
5407 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5408 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5410 enum i40e_status_code status;
5413 return I40E_ERR_PARAM;
5416 i40e_fill_default_direct_cmd_desc(&desc,
5417 i40e_aqc_opc_add_control_packet_filter);
5418 cmd->queue = CPU_TO_LE16(queue);
5420 i40e_fill_default_direct_cmd_desc(&desc,
5421 i40e_aqc_opc_remove_control_packet_filter);
5425 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
5426 I40E_NONDMA_TO_NONDMA);
5428 cmd->etype = CPU_TO_LE16(ethtype);
5429 cmd->flags = CPU_TO_LE16(flags);
5430 cmd->seid = CPU_TO_LE16(vsi_seid);
5432 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5434 if (!status && stats) {
5435 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5436 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5437 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5438 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5445 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5446 * @hw: pointer to the hw struct
5447 * @seid: VSI seid to add ethertype filter from
5449 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5450 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5453 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5454 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5455 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5456 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5457 enum i40e_status_code status;
5459 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5460 seid, 0, true, NULL,
5463 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5467 * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5468 * @filters: list of cloud filters
5469 * @filter_count: length of list
5471 * There's an issue in the device where the Geneve VNI layout needs
5472 * to be shifted 1 byte over from the VxLAN VNI
5474 STATIC void i40e_fix_up_geneve_vni(
5475 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5478 struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters;
5481 for (i = 0; i < filter_count; i++) {
5485 tnl_type = (le16_to_cpu(f[i].flags) &
5486 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5487 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5488 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5489 ti = le32_to_cpu(f[i].tenant_id);
5490 f[i].tenant_id = cpu_to_le32(ti << 8);
5496 * i40e_aq_add_cloud_filters
5497 * @hw: pointer to the hardware structure
5498 * @seid: VSI seid to add cloud filters from
5499 * @filters: Buffer which contains the filters to be added
5500 * @filter_count: number of filters contained in the buffer
5502 * Set the cloud filters for a given VSI. The contents of the
5503 * i40e_aqc_add_remove_cloud_filters_element_data are filled
5504 * in by the caller of the function.
5507 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5509 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5512 struct i40e_aq_desc desc;
5513 struct i40e_aqc_add_remove_cloud_filters *cmd =
5514 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5515 enum i40e_status_code status;
5518 i40e_fill_default_direct_cmd_desc(&desc,
5519 i40e_aqc_opc_add_cloud_filters);
5521 buff_len = filter_count * sizeof(*filters);
5522 desc.datalen = CPU_TO_LE16(buff_len);
5523 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5524 cmd->num_filters = filter_count;
5525 cmd->seid = CPU_TO_LE16(seid);
5527 i40e_fix_up_geneve_vni(filters, filter_count);
5529 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5535 * i40e_aq_remove_cloud_filters
5536 * @hw: pointer to the hardware structure
5537 * @seid: VSI seid to remove cloud filters from
5538 * @filters: Buffer which contains the filters to be removed
5539 * @filter_count: number of filters contained in the buffer
5541 * Remove the cloud filters for a given VSI. The contents of the
5542 * i40e_aqc_add_remove_cloud_filters_element_data are filled
5543 * in by the caller of the function.
5546 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5548 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5551 struct i40e_aq_desc desc;
5552 struct i40e_aqc_add_remove_cloud_filters *cmd =
5553 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5554 enum i40e_status_code status;
5557 i40e_fill_default_direct_cmd_desc(&desc,
5558 i40e_aqc_opc_remove_cloud_filters);
5560 buff_len = filter_count * sizeof(*filters);
5561 desc.datalen = CPU_TO_LE16(buff_len);
5562 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5563 cmd->num_filters = filter_count;
5564 cmd->seid = CPU_TO_LE16(seid);
5566 i40e_fix_up_geneve_vni(filters, filter_count);
5568 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5574 * i40e_aq_alternate_write
5575 * @hw: pointer to the hardware structure
5576 * @reg_addr0: address of first dword to be read
5577 * @reg_val0: value to be written under 'reg_addr0'
5578 * @reg_addr1: address of second dword to be read
5579 * @reg_val1: value to be written under 'reg_addr1'
5581 * Write one or two dwords to alternate structure. Fields are indicated
5582 * by 'reg_addr0' and 'reg_addr1' register numbers.
5585 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5586 u32 reg_addr0, u32 reg_val0,
5587 u32 reg_addr1, u32 reg_val1)
5589 struct i40e_aq_desc desc;
5590 struct i40e_aqc_alternate_write *cmd_resp =
5591 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5592 enum i40e_status_code status;
5594 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5595 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5596 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5597 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5598 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5600 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5606 * i40e_aq_alternate_write_indirect
5607 * @hw: pointer to the hardware structure
5608 * @addr: address of a first register to be modified
5609 * @dw_count: number of alternate structure fields to write
5610 * @buffer: pointer to the command buffer
5612 * Write 'dw_count' dwords from 'buffer' to alternate structure
5613 * starting at 'addr'.
5616 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5617 u32 addr, u32 dw_count, void *buffer)
5619 struct i40e_aq_desc desc;
5620 struct i40e_aqc_alternate_ind_write *cmd_resp =
5621 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5622 enum i40e_status_code status;
5625 return I40E_ERR_PARAM;
5627 /* Indirect command */
5628 i40e_fill_default_direct_cmd_desc(&desc,
5629 i40e_aqc_opc_alternate_write_indirect);
5631 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5632 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5633 if (dw_count > (I40E_AQ_LARGE_BUF/4))
5634 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5636 cmd_resp->address = CPU_TO_LE32(addr);
5637 cmd_resp->length = CPU_TO_LE32(dw_count);
5639 status = i40e_asq_send_command(hw, &desc, buffer,
5640 I40E_LO_DWORD(4*dw_count), NULL);
5646 * i40e_aq_alternate_read
5647 * @hw: pointer to the hardware structure
5648 * @reg_addr0: address of first dword to be read
5649 * @reg_val0: pointer for data read from 'reg_addr0'
5650 * @reg_addr1: address of second dword to be read
5651 * @reg_val1: pointer for data read from 'reg_addr1'
5653 * Read one or two dwords from alternate structure. Fields are indicated
5654 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5655 * is not passed then only register at 'reg_addr0' is read.
5658 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5659 u32 reg_addr0, u32 *reg_val0,
5660 u32 reg_addr1, u32 *reg_val1)
5662 struct i40e_aq_desc desc;
5663 struct i40e_aqc_alternate_write *cmd_resp =
5664 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5665 enum i40e_status_code status;
5667 if (reg_val0 == NULL)
5668 return I40E_ERR_PARAM;
5670 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5671 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5672 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5674 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5676 if (status == I40E_SUCCESS) {
5677 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5679 if (reg_val1 != NULL)
5680 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5687 * i40e_aq_alternate_read_indirect
5688 * @hw: pointer to the hardware structure
5689 * @addr: address of the alternate structure field
5690 * @dw_count: number of alternate structure fields to read
5691 * @buffer: pointer to the command buffer
5693 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5694 * place them in 'buffer'. The buffer should be allocated by caller.
5697 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5698 u32 addr, u32 dw_count, void *buffer)
5700 struct i40e_aq_desc desc;
5701 struct i40e_aqc_alternate_ind_write *cmd_resp =
5702 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5703 enum i40e_status_code status;
5706 return I40E_ERR_PARAM;
5708 /* Indirect command */
5709 i40e_fill_default_direct_cmd_desc(&desc,
5710 i40e_aqc_opc_alternate_read_indirect);
5712 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5713 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5714 if (dw_count > (I40E_AQ_LARGE_BUF/4))
5715 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5717 cmd_resp->address = CPU_TO_LE32(addr);
5718 cmd_resp->length = CPU_TO_LE32(dw_count);
5720 status = i40e_asq_send_command(hw, &desc, buffer,
5721 I40E_LO_DWORD(4*dw_count), NULL);
5727 * i40e_aq_alternate_clear
5728 * @hw: pointer to the HW structure.
5730 * Clear the alternate structures of the port from which the function
5734 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5736 struct i40e_aq_desc desc;
5737 enum i40e_status_code status;
5739 i40e_fill_default_direct_cmd_desc(&desc,
5740 i40e_aqc_opc_alternate_clear_port);
5742 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5748 * i40e_aq_alternate_write_done
5749 * @hw: pointer to the HW structure.
5750 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
5751 * @reset_needed: indicates the SW should trigger GLOBAL reset
5753 * Indicates to the FW that alternate structures have been changed.
5756 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
5757 u8 bios_mode, bool *reset_needed)
5759 struct i40e_aq_desc desc;
5760 struct i40e_aqc_alternate_write_done *cmd =
5761 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5762 enum i40e_status_code status;
5764 if (reset_needed == NULL)
5765 return I40E_ERR_PARAM;
5767 i40e_fill_default_direct_cmd_desc(&desc,
5768 i40e_aqc_opc_alternate_write_done);
5770 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
5772 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5773 if (!status && reset_needed)
5774 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
5775 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
5781 * i40e_aq_set_oem_mode
5782 * @hw: pointer to the HW structure.
5783 * @oem_mode: the OEM mode to be used
5785 * Sets the device to a specific operating mode. Currently the only supported
5786 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
5789 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
5792 struct i40e_aq_desc desc;
5793 struct i40e_aqc_alternate_write_done *cmd =
5794 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5795 enum i40e_status_code status;
5797 i40e_fill_default_direct_cmd_desc(&desc,
5798 i40e_aqc_opc_alternate_set_mode);
5800 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
5802 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5808 * i40e_aq_resume_port_tx
5809 * @hw: pointer to the hardware structure
5810 * @cmd_details: pointer to command details structure or NULL
5812 * Resume port's Tx traffic
5814 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
5815 struct i40e_asq_cmd_details *cmd_details)
5817 struct i40e_aq_desc desc;
5818 enum i40e_status_code status;
5820 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
5822 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5828 * i40e_set_pci_config_data - store PCI bus info
5829 * @hw: pointer to hardware structure
5830 * @link_status: the link status word from PCI config space
5832 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
5834 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
5836 hw->bus.type = i40e_bus_type_pci_express;
5838 switch (link_status & I40E_PCI_LINK_WIDTH) {
5839 case I40E_PCI_LINK_WIDTH_1:
5840 hw->bus.width = i40e_bus_width_pcie_x1;
5842 case I40E_PCI_LINK_WIDTH_2:
5843 hw->bus.width = i40e_bus_width_pcie_x2;
5845 case I40E_PCI_LINK_WIDTH_4:
5846 hw->bus.width = i40e_bus_width_pcie_x4;
5848 case I40E_PCI_LINK_WIDTH_8:
5849 hw->bus.width = i40e_bus_width_pcie_x8;
5852 hw->bus.width = i40e_bus_width_unknown;
5856 switch (link_status & I40E_PCI_LINK_SPEED) {
5857 case I40E_PCI_LINK_SPEED_2500:
5858 hw->bus.speed = i40e_bus_speed_2500;
5860 case I40E_PCI_LINK_SPEED_5000:
5861 hw->bus.speed = i40e_bus_speed_5000;
5863 case I40E_PCI_LINK_SPEED_8000:
5864 hw->bus.speed = i40e_bus_speed_8000;
5867 hw->bus.speed = i40e_bus_speed_unknown;
5873 * i40e_aq_debug_dump
5874 * @hw: pointer to the hardware structure
5875 * @cluster_id: specific cluster to dump
5876 * @table_id: table id within cluster
5877 * @start_index: index of line in the block to read
5878 * @buff_size: dump buffer size
5879 * @buff: dump buffer
5880 * @ret_buff_size: actual buffer size returned
5881 * @ret_next_table: next block to read
5882 * @ret_next_index: next index to read
5884 * Dump internal FW/HW data for debug purposes.
5887 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
5888 u8 table_id, u32 start_index, u16 buff_size,
5889 void *buff, u16 *ret_buff_size,
5890 u8 *ret_next_table, u32 *ret_next_index,
5891 struct i40e_asq_cmd_details *cmd_details)
5893 struct i40e_aq_desc desc;
5894 struct i40e_aqc_debug_dump_internals *cmd =
5895 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5896 struct i40e_aqc_debug_dump_internals *resp =
5897 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5898 enum i40e_status_code status;
5900 if (buff_size == 0 || !buff)
5901 return I40E_ERR_PARAM;
5903 i40e_fill_default_direct_cmd_desc(&desc,
5904 i40e_aqc_opc_debug_dump_internals);
5905 /* Indirect Command */
5906 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5907 if (buff_size > I40E_AQ_LARGE_BUF)
5908 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5910 cmd->cluster_id = cluster_id;
5911 cmd->table_id = table_id;
5912 cmd->idx = CPU_TO_LE32(start_index);
5914 desc.datalen = CPU_TO_LE16(buff_size);
5916 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5918 if (ret_buff_size != NULL)
5919 *ret_buff_size = LE16_TO_CPU(desc.datalen);
5920 if (ret_next_table != NULL)
5921 *ret_next_table = resp->table_id;
5922 if (ret_next_index != NULL)
5923 *ret_next_index = LE32_TO_CPU(resp->idx);
5930 * i40e_read_bw_from_alt_ram
5931 * @hw: pointer to the hardware structure
5932 * @max_bw: pointer for max_bw read
5933 * @min_bw: pointer for min_bw read
5934 * @min_valid: pointer for bool that is true if min_bw is a valid value
5935 * @max_valid: pointer for bool that is true if max_bw is a valid value
5937 * Read bw from the alternate ram for the given pf
5939 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
5940 u32 *max_bw, u32 *min_bw,
5941 bool *min_valid, bool *max_valid)
5943 enum i40e_status_code status;
5944 u32 max_bw_addr, min_bw_addr;
5946 /* Calculate the address of the min/max bw registers */
5947 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5948 I40E_ALT_STRUCT_MAX_BW_OFFSET +
5949 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5950 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5951 I40E_ALT_STRUCT_MIN_BW_OFFSET +
5952 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5954 /* Read the bandwidths from alt ram */
5955 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
5956 min_bw_addr, min_bw);
5958 if (*min_bw & I40E_ALT_BW_VALID_MASK)
5963 if (*max_bw & I40E_ALT_BW_VALID_MASK)
5972 * i40e_aq_configure_partition_bw
5973 * @hw: pointer to the hardware structure
5974 * @bw_data: Buffer holding valid pfs and bw limits
5975 * @cmd_details: pointer to command details
5977 * Configure partitions guaranteed/max bw
5979 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
5980 struct i40e_aqc_configure_partition_bw_data *bw_data,
5981 struct i40e_asq_cmd_details *cmd_details)
5983 enum i40e_status_code status;
5984 struct i40e_aq_desc desc;
5985 u16 bwd_size = sizeof(*bw_data);
5987 i40e_fill_default_direct_cmd_desc(&desc,
5988 i40e_aqc_opc_configure_partition_bw);
5990 /* Indirect command */
5991 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5992 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5994 if (bwd_size > I40E_AQ_LARGE_BUF)
5995 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5997 desc.datalen = CPU_TO_LE16(bwd_size);
5999 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6005 * i40e_read_phy_register
6006 * @hw: pointer to the HW structure
6007 * @page: registers page number
6008 * @reg: register address in the page
6009 * @phy_adr: PHY address on MDIO interface
6010 * @value: PHY register value
6012 * Reads specified PHY register value
6014 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6015 u8 page, u16 reg, u8 phy_addr,
6018 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6021 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6023 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6024 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6025 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6026 (I40E_MDIO_OPCODE_ADDRESS) |
6027 (I40E_MDIO_STCODE) |
6028 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6029 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6030 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6032 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6033 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6034 status = I40E_SUCCESS;
6037 i40e_usec_delay(10);
6042 i40e_debug(hw, I40E_DEBUG_PHY,
6043 "PHY: Can't write command to external PHY.\n");
6047 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6048 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6049 (I40E_MDIO_OPCODE_READ) |
6050 (I40E_MDIO_STCODE) |
6051 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6052 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6053 status = I40E_ERR_TIMEOUT;
6055 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6057 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6058 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6059 status = I40E_SUCCESS;
6062 i40e_usec_delay(10);
6067 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6068 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6069 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6071 i40e_debug(hw, I40E_DEBUG_PHY,
6072 "PHY: Can't read register value from external PHY.\n");
6080 * i40e_write_phy_register
6081 * @hw: pointer to the HW structure
6082 * @page: registers page number
6083 * @reg: register address in the page
6084 * @phy_adr: PHY address on MDIO interface
6085 * @value: PHY register value
6087 * Writes value to specified PHY register
6089 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6090 u8 page, u16 reg, u8 phy_addr,
6093 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6096 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6098 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6099 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6100 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6101 (I40E_MDIO_OPCODE_ADDRESS) |
6102 (I40E_MDIO_STCODE) |
6103 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6104 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6105 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6107 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6108 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6109 status = I40E_SUCCESS;
6112 i40e_usec_delay(10);
6116 i40e_debug(hw, I40E_DEBUG_PHY,
6117 "PHY: Can't write command to external PHY.\n");
6121 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6122 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6124 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6125 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6126 (I40E_MDIO_OPCODE_WRITE) |
6127 (I40E_MDIO_STCODE) |
6128 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6129 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6130 status = I40E_ERR_TIMEOUT;
6132 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6134 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6135 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6136 status = I40E_SUCCESS;
6139 i40e_usec_delay(10);
6148 * i40e_get_phy_address
6149 * @hw: pointer to the HW structure
6150 * @dev_num: PHY port num that address we want
6151 * @phy_addr: Returned PHY address
6153 * Gets PHY address for current port
6155 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6157 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6158 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6160 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6164 * i40e_blink_phy_led
6165 * @hw: pointer to the HW structure
6166 * @time: time how long led will blinks in secs
6167 * @interval: gap between LED on and off in msecs
6169 * Blinks PHY link LED
6171 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6172 u32 time, u32 interval)
6174 enum i40e_status_code status = I40E_SUCCESS;
6179 u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6183 i = rd32(hw, I40E_PFGEN_PORTNUM);
6184 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6185 phy_addr = i40e_get_phy_address(hw, port_num);
6187 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6189 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6190 led_addr, phy_addr, &led_reg);
6192 goto phy_blinking_end;
6194 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6196 status = i40e_write_phy_register(hw,
6197 I40E_PHY_COM_REG_PAGE,
6201 goto phy_blinking_end;
6206 if (time > 0 && interval > 0) {
6207 for (i = 0; i < time * 1000; i += interval) {
6208 status = i40e_read_phy_register(hw,
6209 I40E_PHY_COM_REG_PAGE,
6213 goto restore_config;
6214 if (led_reg & I40E_PHY_LED_MANUAL_ON)
6217 led_reg = I40E_PHY_LED_MANUAL_ON;
6218 status = i40e_write_phy_register(hw,
6219 I40E_PHY_COM_REG_PAGE,
6223 goto restore_config;
6224 i40e_msec_delay(interval);
6229 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6237 * i40e_led_get_phy - return current on/off mode
6238 * @hw: pointer to the hw struct
6239 * @led_addr: address of led register to use
6240 * @val: original value of register to use
6243 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6246 enum i40e_status_code status = I40E_SUCCESS;
6254 temp_addr = I40E_PHY_LED_PROV_REG_1;
6255 i = rd32(hw, I40E_PFGEN_PORTNUM);
6256 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6257 phy_addr = i40e_get_phy_address(hw, port_num);
6259 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6261 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6262 temp_addr, phy_addr, ®_val);
6266 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6267 *led_addr = temp_addr;
6276 * @hw: pointer to the HW structure
6277 * @on: true or false
6278 * @mode: original val plus bit for set or ignore
6279 * Set led's on or off when controlled by the PHY
6282 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6283 u16 led_addr, u32 mode)
6285 enum i40e_status_code status = I40E_SUCCESS;
6292 i = rd32(hw, I40E_PFGEN_PORTNUM);
6293 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6294 phy_addr = i40e_get_phy_address(hw, port_num);
6296 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6297 phy_addr, &led_reg);
6301 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6303 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6304 led_addr, phy_addr, led_reg);
6308 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6309 led_addr, phy_addr, &led_reg);
6311 goto restore_config;
6313 led_reg = I40E_PHY_LED_MANUAL_ON;
6316 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6317 led_addr, phy_addr, led_reg);
6319 goto restore_config;
6320 if (mode & I40E_PHY_LED_MODE_ORIG) {
6321 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6322 status = i40e_write_phy_register(hw,
6323 I40E_PHY_COM_REG_PAGE,
6324 led_addr, phy_addr, led_ctl);
6328 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6332 #endif /* PF_DRIVER */
6335 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6336 * @hw: pointer to the hw struct
6337 * @reg_addr: register address
6338 * @reg_val: ptr to register value
6339 * @cmd_details: pointer to command details structure or NULL
6341 * Use the firmware to read the Rx control register,
6342 * especially useful if the Rx unit is under heavy pressure
6344 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6345 u32 reg_addr, u32 *reg_val,
6346 struct i40e_asq_cmd_details *cmd_details)
6348 struct i40e_aq_desc desc;
6349 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
6350 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6351 enum i40e_status_code status;
6353 if (reg_val == NULL)
6354 return I40E_ERR_PARAM;
6356 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
6358 cmd_resp->address = CPU_TO_LE32(reg_addr);
6360 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6362 if (status == I40E_SUCCESS)
6363 *reg_val = LE32_TO_CPU(cmd_resp->value);
6369 * i40e_read_rx_ctl - read from an Rx control register
6370 * @hw: pointer to the hw struct
6371 * @reg_addr: register address
6373 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
6375 enum i40e_status_code status = I40E_SUCCESS;
6380 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6381 if (!use_register) {
6383 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
6384 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6391 /* if the AQ access failed, try the old-fashioned way */
6392 if (status || use_register)
6393 val = rd32(hw, reg_addr);
6399 * i40e_aq_rx_ctl_write_register
6400 * @hw: pointer to the hw struct
6401 * @reg_addr: register address
6402 * @reg_val: register value
6403 * @cmd_details: pointer to command details structure or NULL
6405 * Use the firmware to write to an Rx control register,
6406 * especially useful if the Rx unit is under heavy pressure
6408 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
6409 u32 reg_addr, u32 reg_val,
6410 struct i40e_asq_cmd_details *cmd_details)
6412 struct i40e_aq_desc desc;
6413 struct i40e_aqc_rx_ctl_reg_read_write *cmd =
6414 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6415 enum i40e_status_code status;
6417 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
6419 cmd->address = CPU_TO_LE32(reg_addr);
6420 cmd->value = CPU_TO_LE32(reg_val);
6422 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6428 * i40e_write_rx_ctl - write to an Rx control register
6429 * @hw: pointer to the hw struct
6430 * @reg_addr: register address
6431 * @reg_val: register value
6433 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
6435 enum i40e_status_code status = I40E_SUCCESS;
6439 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6440 if (!use_register) {
6442 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
6444 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6451 /* if the AQ access failed, try the old-fashioned way */
6452 if (status || use_register)
6453 wr32(hw, reg_addr, reg_val);
6458 * i40e_aq_send_msg_to_pf
6459 * @hw: pointer to the hardware structure
6460 * @v_opcode: opcodes for VF-PF communication
6461 * @v_retval: return error code
6462 * @msg: pointer to the msg buffer
6463 * @msglen: msg length
6464 * @cmd_details: pointer to command details
6466 * Send message to PF driver using admin queue. By default, this message
6467 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
6468 * completion before returning.
6470 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
6471 enum i40e_virtchnl_ops v_opcode,
6472 enum i40e_status_code v_retval,
6473 u8 *msg, u16 msglen,
6474 struct i40e_asq_cmd_details *cmd_details)
6476 struct i40e_aq_desc desc;
6477 struct i40e_asq_cmd_details details;
6478 enum i40e_status_code status;
6480 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
6481 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
6482 desc.cookie_high = CPU_TO_LE32(v_opcode);
6483 desc.cookie_low = CPU_TO_LE32(v_retval);
6485 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
6486 | I40E_AQ_FLAG_RD));
6487 if (msglen > I40E_AQ_LARGE_BUF)
6488 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6489 desc.datalen = CPU_TO_LE16(msglen);
6492 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
6493 details.async = true;
6494 cmd_details = &details;
6496 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
6497 msglen, cmd_details);
6502 * i40e_vf_parse_hw_config
6503 * @hw: pointer to the hardware structure
6504 * @msg: pointer to the virtual channel VF resource structure
6506 * Given a VF resource message from the PF, populate the hw struct
6507 * with appropriate information.
6509 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
6510 struct i40e_virtchnl_vf_resource *msg)
6512 struct i40e_virtchnl_vsi_resource *vsi_res;
6515 vsi_res = &msg->vsi_res[0];
6517 hw->dev_caps.num_vsis = msg->num_vsis;
6518 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
6519 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
6520 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
6521 hw->dev_caps.dcb = msg->vf_offload_flags &
6522 I40E_VIRTCHNL_VF_OFFLOAD_L2;
6523 hw->dev_caps.fcoe = (msg->vf_offload_flags &
6524 I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
6525 hw->dev_caps.iwarp = (msg->vf_offload_flags &
6526 I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
6527 for (i = 0; i < msg->num_vsis; i++) {
6528 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
6529 i40e_memcpy(hw->mac.perm_addr,
6530 vsi_res->default_mac_addr,
6531 I40E_ETH_LENGTH_OF_ADDRESS,
6532 I40E_NONDMA_TO_NONDMA);
6533 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
6534 I40E_ETH_LENGTH_OF_ADDRESS,
6535 I40E_NONDMA_TO_NONDMA);
6543 * @hw: pointer to the hardware structure
6545 * Send a VF_RESET message to the PF. Does not wait for response from PF
6546 * as none will be forthcoming. Immediately after calling this function,
6547 * the admin queue should be shut down and (optionally) reinitialized.
6549 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
6551 return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
6552 I40E_SUCCESS, NULL, 0, NULL);
6554 #endif /* VF_DRIVER */
6558 * i40e_aq_set_arp_proxy_config
6559 * @hw: pointer to the HW structure
6560 * @proxy_config - pointer to proxy config command table struct
6561 * @cmd_details: pointer to command details
6563 * Set ARP offload parameters from pre-populated
6564 * i40e_aqc_arp_proxy_data struct
6566 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
6567 struct i40e_aqc_arp_proxy_data *proxy_config,
6568 struct i40e_asq_cmd_details *cmd_details)
6570 struct i40e_aq_desc desc;
6571 enum i40e_status_code status;
6574 return I40E_ERR_PARAM;
6576 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
6578 desc.params.external.addr_high =
6579 CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
6580 desc.params.external.addr_low =
6581 CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
6583 status = i40e_asq_send_command(hw, &desc, proxy_config,
6584 sizeof(struct i40e_aqc_arp_proxy_data),
6591 * i40e_aq_opc_set_ns_proxy_table_entry
6592 * @hw: pointer to the HW structure
6593 * @ns_proxy_table_entry: pointer to NS table entry command struct
6594 * @cmd_details: pointer to command details
6596 * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
6597 * from pre-populated i40e_aqc_ns_proxy_data struct
6599 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
6600 struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
6601 struct i40e_asq_cmd_details *cmd_details)
6603 struct i40e_aq_desc desc;
6604 enum i40e_status_code status;
6606 if (!ns_proxy_table_entry)
6607 return I40E_ERR_PARAM;
6609 i40e_fill_default_direct_cmd_desc(&desc,
6610 i40e_aqc_opc_set_ns_proxy_table_entry);
6612 desc.params.external.addr_high =
6613 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
6614 desc.params.external.addr_low =
6615 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
6617 status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
6618 sizeof(struct i40e_aqc_ns_proxy_data),
6625 * i40e_aq_set_clear_wol_filter
6626 * @hw: pointer to the hw struct
6627 * @filter_index: index of filter to modify (0-7)
6628 * @filter: buffer containing filter to be set
6629 * @set_filter: true to set filter, false to clear filter
6630 * @no_wol_tco: if true, pass through packets cannot cause wake-up
6631 * if false, pass through packets may cause wake-up
6632 * @filter_valid: true if filter action is valid
6633 * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
6634 * @cmd_details: pointer to command details structure or NULL
6636 * Set or clear WoL filter for port attached to the PF
6638 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
6640 struct i40e_aqc_set_wol_filter_data *filter,
6641 bool set_filter, bool no_wol_tco,
6642 bool filter_valid, bool no_wol_tco_valid,
6643 struct i40e_asq_cmd_details *cmd_details)
6645 struct i40e_aq_desc desc;
6646 struct i40e_aqc_set_wol_filter *cmd =
6647 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
6648 enum i40e_status_code status;
6650 u16 valid_flags = 0;
6653 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
6655 if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
6656 return I40E_ERR_PARAM;
6657 cmd->filter_index = CPU_TO_LE16(filter_index);
6661 return I40E_ERR_PARAM;
6662 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
6663 buff_len = sizeof(*filter);
6666 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
6667 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
6670 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
6671 if (no_wol_tco_valid)
6672 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
6673 cmd->valid_flags = CPU_TO_LE16(valid_flags);
6675 cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
6676 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
6678 status = i40e_asq_send_command(hw, &desc, filter,
6679 buff_len, cmd_details);
6685 * i40e_aq_get_wake_event_reason
6686 * @hw: pointer to the hw struct
6687 * @wake_reason: return value, index of matching filter
6688 * @cmd_details: pointer to command details structure or NULL
6690 * Get information for the reason of a Wake Up event
6692 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
6694 struct i40e_asq_cmd_details *cmd_details)
6696 struct i40e_aq_desc desc;
6697 struct i40e_aqc_get_wake_reason_completion *resp =
6698 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
6699 enum i40e_status_code status;
6701 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
6703 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6705 if (status == I40E_SUCCESS)
6706 *wake_reason = LE16_TO_CPU(resp->wake_reason);
6711 #endif /* X722_SUPPORT */