drivers/net/i40e/base/i40e_common.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001-2018
   3  */
   4
   5 #include "i40e_type.h"
   6 #include "i40e_adminq.h"
   7 #include "i40e_prototype.h"
   8 #include "virtchnl.h"
   9
  10 /**
  11  * i40e_set_mac_type - Sets MAC type
  12  * @hw: pointer to the HW structure
  13  *
  14  * This function sets the mac type of the adapter based on the
  15  * vendor ID and device ID stored in the hw structure.
  16  **/
  17 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  18 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  19 #else
  20 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  21 #endif
  22 {
  23         enum i40e_status_code status = I40E_SUCCESS;
  24
  25         DEBUGFUNC("i40e_set_mac_type\n");
  26
  27         if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
  28                 switch (hw->device_id) {
  29                 case I40E_DEV_ID_SFP_XL710:
  30                 case I40E_DEV_ID_QEMU:
  31                 case I40E_DEV_ID_KX_B:
  32                 case I40E_DEV_ID_KX_C:
  33                 case I40E_DEV_ID_QSFP_A:
  34                 case I40E_DEV_ID_QSFP_B:
  35                 case I40E_DEV_ID_QSFP_C:
  36                 case I40E_DEV_ID_10G_BASE_T:
  37                 case I40E_DEV_ID_10G_BASE_T4:
  38                 case I40E_DEV_ID_20G_KR2:
  39                 case I40E_DEV_ID_20G_KR2_A:
  40                 case I40E_DEV_ID_25G_B:
  41                 case I40E_DEV_ID_25G_SFP28:
  42                         hw->mac.type = I40E_MAC_XL710;
  43                         break;
  44 #ifdef X722_A0_SUPPORT
  45                 case I40E_DEV_ID_X722_A0:
  46 #endif
  47                 case I40E_DEV_ID_KX_X722:
  48                 case I40E_DEV_ID_QSFP_X722:
  49                 case I40E_DEV_ID_SFP_X722:
  50                 case I40E_DEV_ID_1G_BASE_T_X722:
  51                 case I40E_DEV_ID_10G_BASE_T_X722:
  52                 case I40E_DEV_ID_SFP_I_X722:
  53                         hw->mac.type = I40E_MAC_X722;
  54                         break;
  55 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  56                 case I40E_DEV_ID_X722_VF:
  57 #ifdef X722_A0_SUPPORT
  58                 case I40E_DEV_ID_X722_A0_VF:
  59 #endif
  60                         hw->mac.type = I40E_MAC_X722_VF;
  61                         break;
  62 #endif /* INTEGRATED_VF || VF_DRIVER */
  63 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  64                 case I40E_DEV_ID_VF:
  65                 case I40E_DEV_ID_VF_HV:
  66                 case I40E_DEV_ID_ADAPTIVE_VF:
  67                         hw->mac.type = I40E_MAC_VF;
  68                         break;
  69 #endif
  70                 default:
  71                         hw->mac.type = I40E_MAC_GENERIC;
  72                         break;
  73                 }
  74         } else {
  75                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
  76         }
  77
  78         DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
  79                   hw->mac.type, status);
  80         return status;
  81 }
  82
  83 /**
  84  * i40e_aq_str - convert AQ err code to a string
  85  * @hw: pointer to the HW structure
  86  * @aq_err: the AQ error code to convert
  87  **/
  88 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
  89 {
  90         switch (aq_err) {
  91         case I40E_AQ_RC_OK:
  92                 return "OK";
  93         case I40E_AQ_RC_EPERM:
  94                 return "I40E_AQ_RC_EPERM";
  95         case I40E_AQ_RC_ENOENT:
  96                 return "I40E_AQ_RC_ENOENT";
  97         case I40E_AQ_RC_ESRCH:
  98                 return "I40E_AQ_RC_ESRCH";
  99         case I40E_AQ_RC_EINTR:
 100                 return "I40E_AQ_RC_EINTR";
 101         case I40E_AQ_RC_EIO:
 102                 return "I40E_AQ_RC_EIO";
 103         case I40E_AQ_RC_ENXIO:
 104                 return "I40E_AQ_RC_ENXIO";
 105         case I40E_AQ_RC_E2BIG:
 106                 return "I40E_AQ_RC_E2BIG";
 107         case I40E_AQ_RC_EAGAIN:
 108                 return "I40E_AQ_RC_EAGAIN";
 109         case I40E_AQ_RC_ENOMEM:
 110                 return "I40E_AQ_RC_ENOMEM";
 111         case I40E_AQ_RC_EACCES:
 112                 return "I40E_AQ_RC_EACCES";
 113         case I40E_AQ_RC_EFAULT:
 114                 return "I40E_AQ_RC_EFAULT";
 115         case I40E_AQ_RC_EBUSY:
 116                 return "I40E_AQ_RC_EBUSY";
 117         case I40E_AQ_RC_EEXIST:
 118                 return "I40E_AQ_RC_EEXIST";
 119         case I40E_AQ_RC_EINVAL:
 120                 return "I40E_AQ_RC_EINVAL";
 121         case I40E_AQ_RC_ENOTTY:
 122                 return "I40E_AQ_RC_ENOTTY";
 123         case I40E_AQ_RC_ENOSPC:
 124                 return "I40E_AQ_RC_ENOSPC";
 125         case I40E_AQ_RC_ENOSYS:
 126                 return "I40E_AQ_RC_ENOSYS";
 127         case I40E_AQ_RC_ERANGE:
 128                 return "I40E_AQ_RC_ERANGE";
 129         case I40E_AQ_RC_EFLUSHED:
 130                 return "I40E_AQ_RC_EFLUSHED";
 131         case I40E_AQ_RC_BAD_ADDR:
 132                 return "I40E_AQ_RC_BAD_ADDR";
 133         case I40E_AQ_RC_EMODE:
 134                 return "I40E_AQ_RC_EMODE";
 135         case I40E_AQ_RC_EFBIG:
 136                 return "I40E_AQ_RC_EFBIG";
 137         }
 138
 139         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 140         return hw->err_str;
 141 }
 142
 143 /**
 144  * i40e_stat_str - convert status err code to a string
 145  * @hw: pointer to the HW structure
 146  * @stat_err: the status error code to convert
 147  **/
 148 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
 149 {
 150         switch (stat_err) {
 151         case I40E_SUCCESS:
 152                 return "OK";
 153         case I40E_ERR_NVM:
 154                 return "I40E_ERR_NVM";
 155         case I40E_ERR_NVM_CHECKSUM:
 156                 return "I40E_ERR_NVM_CHECKSUM";
 157         case I40E_ERR_PHY:
 158                 return "I40E_ERR_PHY";
 159         case I40E_ERR_CONFIG:
 160                 return "I40E_ERR_CONFIG";
 161         case I40E_ERR_PARAM:
 162                 return "I40E_ERR_PARAM";
 163         case I40E_ERR_MAC_TYPE:
 164                 return "I40E_ERR_MAC_TYPE";
 165         case I40E_ERR_UNKNOWN_PHY:
 166                 return "I40E_ERR_UNKNOWN_PHY";
 167         case I40E_ERR_LINK_SETUP:
 168                 return "I40E_ERR_LINK_SETUP";
 169         case I40E_ERR_ADAPTER_STOPPED:
 170                 return "I40E_ERR_ADAPTER_STOPPED";
 171         case I40E_ERR_INVALID_MAC_ADDR:
 172                 return "I40E_ERR_INVALID_MAC_ADDR";
 173         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 174                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 175         case I40E_ERR_MASTER_REQUESTS_PENDING:
 176                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 177         case I40E_ERR_INVALID_LINK_SETTINGS:
 178                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 179         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 180                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 181         case I40E_ERR_RESET_FAILED:
 182                 return "I40E_ERR_RESET_FAILED";
 183         case I40E_ERR_SWFW_SYNC:
 184                 return "I40E_ERR_SWFW_SYNC";
 185         case I40E_ERR_NO_AVAILABLE_VSI:
 186                 return "I40E_ERR_NO_AVAILABLE_VSI";
 187         case I40E_ERR_NO_MEMORY:
 188                 return "I40E_ERR_NO_MEMORY";
 189         case I40E_ERR_BAD_PTR:
 190                 return "I40E_ERR_BAD_PTR";
 191         case I40E_ERR_RING_FULL:
 192                 return "I40E_ERR_RING_FULL";
 193         case I40E_ERR_INVALID_PD_ID:
 194                 return "I40E_ERR_INVALID_PD_ID";
 195         case I40E_ERR_INVALID_QP_ID:
 196                 return "I40E_ERR_INVALID_QP_ID";
 197         case I40E_ERR_INVALID_CQ_ID:
 198                 return "I40E_ERR_INVALID_CQ_ID";
 199         case I40E_ERR_INVALID_CEQ_ID:
 200                 return "I40E_ERR_INVALID_CEQ_ID";
 201         case I40E_ERR_INVALID_AEQ_ID:
 202                 return "I40E_ERR_INVALID_AEQ_ID";
 203         case I40E_ERR_INVALID_SIZE:
 204                 return "I40E_ERR_INVALID_SIZE";
 205         case I40E_ERR_INVALID_ARP_INDEX:
 206                 return "I40E_ERR_INVALID_ARP_INDEX";
 207         case I40E_ERR_INVALID_FPM_FUNC_ID:
 208                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 209         case I40E_ERR_QP_INVALID_MSG_SIZE:
 210                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 211         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 212                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 213         case I40E_ERR_INVALID_FRAG_COUNT:
 214                 return "I40E_ERR_INVALID_FRAG_COUNT";
 215         case I40E_ERR_QUEUE_EMPTY:
 216                 return "I40E_ERR_QUEUE_EMPTY";
 217         case I40E_ERR_INVALID_ALIGNMENT:
 218                 return "I40E_ERR_INVALID_ALIGNMENT";
 219         case I40E_ERR_FLUSHED_QUEUE:
 220                 return "I40E_ERR_FLUSHED_QUEUE";
 221         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 222                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 223         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 224                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 225         case I40E_ERR_TIMEOUT:
 226                 return "I40E_ERR_TIMEOUT";
 227         case I40E_ERR_OPCODE_MISMATCH:
 228                 return "I40E_ERR_OPCODE_MISMATCH";
 229         case I40E_ERR_CQP_COMPL_ERROR:
 230                 return "I40E_ERR_CQP_COMPL_ERROR";
 231         case I40E_ERR_INVALID_VF_ID:
 232                 return "I40E_ERR_INVALID_VF_ID";
 233         case I40E_ERR_INVALID_HMCFN_ID:
 234                 return "I40E_ERR_INVALID_HMCFN_ID";
 235         case I40E_ERR_BACKING_PAGE_ERROR:
 236                 return "I40E_ERR_BACKING_PAGE_ERROR";
 237         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 238                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 239         case I40E_ERR_INVALID_PBLE_INDEX:
 240                 return "I40E_ERR_INVALID_PBLE_INDEX";
 241         case I40E_ERR_INVALID_SD_INDEX:
 242                 return "I40E_ERR_INVALID_SD_INDEX";
 243         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 244                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 245         case I40E_ERR_INVALID_SD_TYPE:
 246                 return "I40E_ERR_INVALID_SD_TYPE";
 247         case I40E_ERR_MEMCPY_FAILED:
 248                 return "I40E_ERR_MEMCPY_FAILED";
 249         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 250                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 251         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 252                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 253         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 254                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 255         case I40E_ERR_SRQ_ENABLED:
 256                 return "I40E_ERR_SRQ_ENABLED";
 257         case I40E_ERR_ADMIN_QUEUE_ERROR:
 258                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 259         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 260                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 261         case I40E_ERR_BUF_TOO_SHORT:
 262                 return "I40E_ERR_BUF_TOO_SHORT";
 263         case I40E_ERR_ADMIN_QUEUE_FULL:
 264                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 265         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 266                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 267         case I40E_ERR_BAD_IWARP_CQE:
 268                 return "I40E_ERR_BAD_IWARP_CQE";
 269         case I40E_ERR_NVM_BLANK_MODE:
 270                 return "I40E_ERR_NVM_BLANK_MODE";
 271         case I40E_ERR_NOT_IMPLEMENTED:
 272                 return "I40E_ERR_NOT_IMPLEMENTED";
 273         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 274                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 275         case I40E_ERR_DIAG_TEST_FAILED:
 276                 return "I40E_ERR_DIAG_TEST_FAILED";
 277         case I40E_ERR_NOT_READY:
 278                 return "I40E_ERR_NOT_READY";
 279         case I40E_NOT_SUPPORTED:
 280                 return "I40E_NOT_SUPPORTED";
 281         case I40E_ERR_FIRMWARE_API_VERSION:
 282                 return "I40E_ERR_FIRMWARE_API_VERSION";
 283         case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR:
 284                 return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR";
 285         }
 286
 287         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 288         return hw->err_str;
 289 }
 290
 291 /**
 292  * i40e_debug_aq
 293  * @hw: debug mask related to admin queue
 294  * @mask: debug mask
 295  * @desc: pointer to admin queue descriptor
 296  * @buffer: pointer to command buffer
 297  * @buf_len: max length of buffer
 298  *
 299  * Dumps debug log about adminq command with descriptor contents.
 300  **/
 301 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 302                    void *buffer, u16 buf_len)
 303 {
 304         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 305         u8 *buf = (u8 *)buffer;
 306         u16 len;
 307         u16 i = 0;
 308
 309         if ((!(mask & hw->debug_mask)) || (desc == NULL))
 310                 return;
 311
 312         len = LE16_TO_CPU(aq_desc->datalen);
 313
 314         i40e_debug(hw, mask,
 315                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 316                    LE16_TO_CPU(aq_desc->opcode),
 317                    LE16_TO_CPU(aq_desc->flags),
 318                    LE16_TO_CPU(aq_desc->datalen),
 319                    LE16_TO_CPU(aq_desc->retval));
 320         i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
 321                    LE32_TO_CPU(aq_desc->cookie_high),
 322                    LE32_TO_CPU(aq_desc->cookie_low));
 323         i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
 324                    LE32_TO_CPU(aq_desc->params.internal.param0),
 325                    LE32_TO_CPU(aq_desc->params.internal.param1));
 326         i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
 327                    LE32_TO_CPU(aq_desc->params.external.addr_high),
 328                    LE32_TO_CPU(aq_desc->params.external.addr_low));
 329
 330         if ((buffer != NULL) && (aq_desc->datalen != 0)) {
 331                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 332                 if (buf_len < len)
 333                         len = buf_len;
 334                 /* write the full 16-byte chunks */
 335                 for (i = 0; i < (len - 16); i += 16)
 336                         i40e_debug(hw, mask,
 337                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 338                                    i, buf[i], buf[i+1], buf[i+2], buf[i+3],
 339                                    buf[i+4], buf[i+5], buf[i+6], buf[i+7],
 340                                    buf[i+8], buf[i+9], buf[i+10], buf[i+11],
 341                                    buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
 342                 /* the most we could have left is 16 bytes, pad with zeros */
 343                 if (i < len) {
 344                         char d_buf[16];
 345                         int j, i_sav;
 346
 347                         i_sav = i;
 348                         memset(d_buf, 0, sizeof(d_buf));
 349                         for (j = 0; i < len; j++, i++)
 350                                 d_buf[j] = buf[i];
 351                         i40e_debug(hw, mask,
 352                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 353                                    i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
 354                                    d_buf[4], d_buf[5], d_buf[6], d_buf[7],
 355                                    d_buf[8], d_buf[9], d_buf[10], d_buf[11],
 356                                    d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
 357                 }
 358         }
 359 }
 360
 361 /**
 362  * i40e_check_asq_alive
 363  * @hw: pointer to the hw struct
 364  *
 365  * Returns true if Queue is enabled else false.
 366  **/
 367 bool i40e_check_asq_alive(struct i40e_hw *hw)
 368 {
 369         if (hw->aq.asq.len)
 370 #ifdef PF_DRIVER
 371 #ifdef INTEGRATED_VF
 372                 if (!i40e_is_vf(hw))
 373                         return !!(rd32(hw, hw->aq.asq.len) &
 374                                 I40E_PF_ATQLEN_ATQENABLE_MASK);
 375 #else
 376                 return !!(rd32(hw, hw->aq.asq.len) &
 377                         I40E_PF_ATQLEN_ATQENABLE_MASK);
 378 #endif /* INTEGRATED_VF */
 379 #endif /* PF_DRIVER */
 380 #ifdef VF_DRIVER
 381 #ifdef INTEGRATED_VF
 382                 if (i40e_is_vf(hw))
 383                         return !!(rd32(hw, hw->aq.asq.len) &
 384                                 I40E_VF_ATQLEN1_ATQENABLE_MASK);
 385 #else
 386                 return !!(rd32(hw, hw->aq.asq.len) &
 387                         I40E_VF_ATQLEN1_ATQENABLE_MASK);
 388 #endif /* INTEGRATED_VF */
 389 #endif /* VF_DRIVER */
 390         return false;
 391 }
 392
 393 /**
 394  * i40e_aq_queue_shutdown
 395  * @hw: pointer to the hw struct
 396  * @unloading: is the driver unloading itself
 397  *
 398  * Tell the Firmware that we're shutting down the AdminQ and whether
 399  * or not the driver is unloading as well.
 400  **/
 401 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
 402                                              bool unloading)
 403 {
 404         struct i40e_aq_desc desc;
 405         struct i40e_aqc_queue_shutdown *cmd =
 406                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 407         enum i40e_status_code status;
 408
 409         i40e_fill_default_direct_cmd_desc(&desc,
 410                                           i40e_aqc_opc_queue_shutdown);
 411
 412         if (unloading)
 413                 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
 414         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 415
 416         return status;
 417 }
 418
 419 /**
 420  * i40e_aq_get_set_rss_lut
 421  * @hw: pointer to the hardware structure
 422  * @vsi_id: vsi fw index
 423  * @pf_lut: for PF table set true, for VSI table set false
 424  * @lut: pointer to the lut buffer provided by the caller
 425  * @lut_size: size of the lut buffer
 426  * @set: set true to set the table, false to get the table
 427  *
 428  * Internal function to get or set RSS look up table
 429  **/
 430 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 431                                                      u16 vsi_id, bool pf_lut,
 432                                                      u8 *lut, u16 lut_size,
 433                                                      bool set)
 434 {
 435         enum i40e_status_code status;
 436         struct i40e_aq_desc desc;
 437         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 438                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 439
 440         if (set)
 441                 i40e_fill_default_direct_cmd_desc(&desc,
 442                                                   i40e_aqc_opc_set_rss_lut);
 443         else
 444                 i40e_fill_default_direct_cmd_desc(&desc,
 445                                                   i40e_aqc_opc_get_rss_lut);
 446
 447         /* Indirect command */
 448         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 449         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 450
 451         cmd_resp->vsi_id =
 452                         CPU_TO_LE16((u16)((vsi_id <<
 453                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 454                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 455         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 456
 457         if (pf_lut)
 458                 cmd_resp->flags |= CPU_TO_LE16((u16)
 459                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 460                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 461                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 462         else
 463                 cmd_resp->flags |= CPU_TO_LE16((u16)
 464                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 465                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 466                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 467
 468         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 469
 470         return status;
 471 }
 472
 473 /**
 474  * i40e_aq_get_rss_lut
 475  * @hw: pointer to the hardware structure
 476  * @vsi_id: vsi fw index
 477  * @pf_lut: for PF table set true, for VSI table set false
 478  * @lut: pointer to the lut buffer provided by the caller
 479  * @lut_size: size of the lut buffer
 480  *
 481  * get the RSS lookup table, PF or VSI type
 482  **/
 483 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 484                                           bool pf_lut, u8 *lut, u16 lut_size)
 485 {
 486         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 487                                        false);
 488 }
 489
 490 /**
 491  * i40e_aq_set_rss_lut
 492  * @hw: pointer to the hardware structure
 493  * @vsi_id: vsi fw index
 494  * @pf_lut: for PF table set true, for VSI table set false
 495  * @lut: pointer to the lut buffer provided by the caller
 496  * @lut_size: size of the lut buffer
 497  *
 498  * set the RSS lookup table, PF or VSI type
 499  **/
 500 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 501                                           bool pf_lut, u8 *lut, u16 lut_size)
 502 {
 503         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
 504 }
 505
 506 /**
 507  * i40e_aq_get_set_rss_key
 508  * @hw: pointer to the hw struct
 509  * @vsi_id: vsi fw index
 510  * @key: pointer to key info struct
 511  * @set: set true to set the key, false to get the key
 512  *
 513  * get the RSS key per VSI
 514  **/
 515 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 516                                       u16 vsi_id,
 517                                       struct i40e_aqc_get_set_rss_key_data *key,
 518                                       bool set)
 519 {
 520         enum i40e_status_code status;
 521         struct i40e_aq_desc desc;
 522         struct i40e_aqc_get_set_rss_key *cmd_resp =
 523                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 524         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 525
 526         if (set)
 527                 i40e_fill_default_direct_cmd_desc(&desc,
 528                                                   i40e_aqc_opc_set_rss_key);
 529         else
 530                 i40e_fill_default_direct_cmd_desc(&desc,
 531                                                   i40e_aqc_opc_get_rss_key);
 532
 533         /* Indirect command */
 534         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 535         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 536
 537         cmd_resp->vsi_id =
 538                         CPU_TO_LE16((u16)((vsi_id <<
 539                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 540                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 541         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 542
 543         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 544
 545         return status;
 546 }
 547
 548 /**
 549  * i40e_aq_get_rss_key
 550  * @hw: pointer to the hw struct
 551  * @vsi_id: vsi fw index
 552  * @key: pointer to key info struct
 553  *
 554  **/
 555 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
 556                                       u16 vsi_id,
 557                                       struct i40e_aqc_get_set_rss_key_data *key)
 558 {
 559         return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
 560 }
 561
 562 /**
 563  * i40e_aq_set_rss_key
 564  * @hw: pointer to the hw struct
 565  * @vsi_id: vsi fw index
 566  * @key: pointer to key info struct
 567  *
 568  * set the RSS key per VSI
 569  **/
 570 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
 571                                       u16 vsi_id,
 572                                       struct i40e_aqc_get_set_rss_key_data *key)
 573 {
 574         return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
 575 }
 576
 577 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 578  * hardware to a bit-field that can be used by SW to more easily determine the
 579  * packet type.
 580  *
 581  * Macros are used to shorten the table lines and make this table human
 582  * readable.
 583  *
 584  * We store the PTYPE in the top byte of the bit field - this is just so that
 585  * we can check that the table doesn't have a row missing, as the index into
 586  * the table should be the PTYPE.
 587  *
 588  * Typical work flow:
 589  *
 590  * IF NOT i40e_ptype_lookup[ptype].known
 591  * THEN
 592  *      Packet is unknown
 593  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 594  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 595  * ELSE
 596  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 597  * ENDIF
 598  */
 599
 600 /* macro to make the table lines short */
 601 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 602         {       PTYPE, \
 603                 1, \
 604                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 605                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 606                 I40E_RX_PTYPE_##OUTER_FRAG, \
 607                 I40E_RX_PTYPE_TUNNEL_##T, \
 608                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 609                 I40E_RX_PTYPE_##TEF, \
 610                 I40E_RX_PTYPE_INNER_PROT_##I, \
 611                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 612
 613 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 614                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 615
 616 /* shorter macros makes the table fit but are terse */
 617 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 618 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 619 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 620
 621 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 622 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 623         /* L2 Packet types */
 624         I40E_PTT_UNUSED_ENTRY(0),
 625         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 626         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 627         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 628         I40E_PTT_UNUSED_ENTRY(4),
 629         I40E_PTT_UNUSED_ENTRY(5),
 630         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 631         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 632         I40E_PTT_UNUSED_ENTRY(8),
 633         I40E_PTT_UNUSED_ENTRY(9),
 634         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 635         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 636         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 637         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 638         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 639         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 640         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 641         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 642         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 643         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 644         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 645         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 646
 647         /* Non Tunneled IPv4 */
 648         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 649         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 650         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 651         I40E_PTT_UNUSED_ENTRY(25),
 652         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 653         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 654         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 655
 656         /* IPv4 --> IPv4 */
 657         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 658         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 659         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 660         I40E_PTT_UNUSED_ENTRY(32),
 661         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 662         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 663         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 664
 665         /* IPv4 --> IPv6 */
 666         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 667         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 668         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 669         I40E_PTT_UNUSED_ENTRY(39),
 670         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 671         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 672         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 673
 674         /* IPv4 --> GRE/NAT */
 675         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 676
 677         /* IPv4 --> GRE/NAT --> IPv4 */
 678         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 679         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 680         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 681         I40E_PTT_UNUSED_ENTRY(47),
 682         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 683         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 684         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 685
 686         /* IPv4 --> GRE/NAT --> IPv6 */
 687         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 688         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 689         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 690         I40E_PTT_UNUSED_ENTRY(54),
 691         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 692         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 693         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 694
 695         /* IPv4 --> GRE/NAT --> MAC */
 696         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 697
 698         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 699         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 700         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 701         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 702         I40E_PTT_UNUSED_ENTRY(62),
 703         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 704         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 705         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 706
 707         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 708         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 709         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 710         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 711         I40E_PTT_UNUSED_ENTRY(69),
 712         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 713         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 714         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 715
 716         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 717         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 718
 719         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 720         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 721         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 722         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 723         I40E_PTT_UNUSED_ENTRY(77),
 724         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 725         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 726         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 727
 728         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 729         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 730         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 731         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 732         I40E_PTT_UNUSED_ENTRY(84),
 733         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 734         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 735         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 736
 737         /* Non Tunneled IPv6 */
 738         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 739         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 740         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
 741         I40E_PTT_UNUSED_ENTRY(91),
 742         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 743         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 744         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 745
 746         /* IPv6 --> IPv4 */
 747         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 748         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 749         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 750         I40E_PTT_UNUSED_ENTRY(98),
 751         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 752         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 753         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 754
 755         /* IPv6 --> IPv6 */
 756         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 757         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 758         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 759         I40E_PTT_UNUSED_ENTRY(105),
 760         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 761         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 762         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 763
 764         /* IPv6 --> GRE/NAT */
 765         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 766
 767         /* IPv6 --> GRE/NAT -> IPv4 */
 768         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 769         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 770         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 771         I40E_PTT_UNUSED_ENTRY(113),
 772         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 773         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 774         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 775
 776         /* IPv6 --> GRE/NAT -> IPv6 */
 777         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 778         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 779         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 780         I40E_PTT_UNUSED_ENTRY(120),
 781         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 782         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 783         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 784
 785         /* IPv6 --> GRE/NAT -> MAC */
 786         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 787
 788         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 789         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 790         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 791         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 792         I40E_PTT_UNUSED_ENTRY(128),
 793         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 794         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 795         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 796
 797         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 798         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 799         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 800         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 801         I40E_PTT_UNUSED_ENTRY(135),
 802         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 803         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 804         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 805
 806         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 807         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 808
 809         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 810         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 811         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 812         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 813         I40E_PTT_UNUSED_ENTRY(143),
 814         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 815         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 816         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 817
 818         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 819         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 820         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 821         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 822         I40E_PTT_UNUSED_ENTRY(150),
 823         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 824         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 825         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 826
 827         /* unused entries */
 828         I40E_PTT_UNUSED_ENTRY(154),
 829         I40E_PTT_UNUSED_ENTRY(155),
 830         I40E_PTT_UNUSED_ENTRY(156),
 831         I40E_PTT_UNUSED_ENTRY(157),
 832         I40E_PTT_UNUSED_ENTRY(158),
 833         I40E_PTT_UNUSED_ENTRY(159),
 834
 835         I40E_PTT_UNUSED_ENTRY(160),
 836         I40E_PTT_UNUSED_ENTRY(161),
 837         I40E_PTT_UNUSED_ENTRY(162),
 838         I40E_PTT_UNUSED_ENTRY(163),
 839         I40E_PTT_UNUSED_ENTRY(164),
 840         I40E_PTT_UNUSED_ENTRY(165),
 841         I40E_PTT_UNUSED_ENTRY(166),
 842         I40E_PTT_UNUSED_ENTRY(167),
 843         I40E_PTT_UNUSED_ENTRY(168),
 844         I40E_PTT_UNUSED_ENTRY(169),
 845
 846         I40E_PTT_UNUSED_ENTRY(170),
 847         I40E_PTT_UNUSED_ENTRY(171),
 848         I40E_PTT_UNUSED_ENTRY(172),
 849         I40E_PTT_UNUSED_ENTRY(173),
 850         I40E_PTT_UNUSED_ENTRY(174),
 851         I40E_PTT_UNUSED_ENTRY(175),
 852         I40E_PTT_UNUSED_ENTRY(176),
 853         I40E_PTT_UNUSED_ENTRY(177),
 854         I40E_PTT_UNUSED_ENTRY(178),
 855         I40E_PTT_UNUSED_ENTRY(179),
 856
 857         I40E_PTT_UNUSED_ENTRY(180),
 858         I40E_PTT_UNUSED_ENTRY(181),
 859         I40E_PTT_UNUSED_ENTRY(182),
 860         I40E_PTT_UNUSED_ENTRY(183),
 861         I40E_PTT_UNUSED_ENTRY(184),
 862         I40E_PTT_UNUSED_ENTRY(185),
 863         I40E_PTT_UNUSED_ENTRY(186),
 864         I40E_PTT_UNUSED_ENTRY(187),
 865         I40E_PTT_UNUSED_ENTRY(188),
 866         I40E_PTT_UNUSED_ENTRY(189),
 867
 868         I40E_PTT_UNUSED_ENTRY(190),
 869         I40E_PTT_UNUSED_ENTRY(191),
 870         I40E_PTT_UNUSED_ENTRY(192),
 871         I40E_PTT_UNUSED_ENTRY(193),
 872         I40E_PTT_UNUSED_ENTRY(194),
 873         I40E_PTT_UNUSED_ENTRY(195),
 874         I40E_PTT_UNUSED_ENTRY(196),
 875         I40E_PTT_UNUSED_ENTRY(197),
 876         I40E_PTT_UNUSED_ENTRY(198),
 877         I40E_PTT_UNUSED_ENTRY(199),
 878
 879         I40E_PTT_UNUSED_ENTRY(200),
 880         I40E_PTT_UNUSED_ENTRY(201),
 881         I40E_PTT_UNUSED_ENTRY(202),
 882         I40E_PTT_UNUSED_ENTRY(203),
 883         I40E_PTT_UNUSED_ENTRY(204),
 884         I40E_PTT_UNUSED_ENTRY(205),
 885         I40E_PTT_UNUSED_ENTRY(206),
 886         I40E_PTT_UNUSED_ENTRY(207),
 887         I40E_PTT_UNUSED_ENTRY(208),
 888         I40E_PTT_UNUSED_ENTRY(209),
 889
 890         I40E_PTT_UNUSED_ENTRY(210),
 891         I40E_PTT_UNUSED_ENTRY(211),
 892         I40E_PTT_UNUSED_ENTRY(212),
 893         I40E_PTT_UNUSED_ENTRY(213),
 894         I40E_PTT_UNUSED_ENTRY(214),
 895         I40E_PTT_UNUSED_ENTRY(215),
 896         I40E_PTT_UNUSED_ENTRY(216),
 897         I40E_PTT_UNUSED_ENTRY(217),
 898         I40E_PTT_UNUSED_ENTRY(218),
 899         I40E_PTT_UNUSED_ENTRY(219),
 900
 901         I40E_PTT_UNUSED_ENTRY(220),
 902         I40E_PTT_UNUSED_ENTRY(221),
 903         I40E_PTT_UNUSED_ENTRY(222),
 904         I40E_PTT_UNUSED_ENTRY(223),
 905         I40E_PTT_UNUSED_ENTRY(224),
 906         I40E_PTT_UNUSED_ENTRY(225),
 907         I40E_PTT_UNUSED_ENTRY(226),
 908         I40E_PTT_UNUSED_ENTRY(227),
 909         I40E_PTT_UNUSED_ENTRY(228),
 910         I40E_PTT_UNUSED_ENTRY(229),
 911
 912         I40E_PTT_UNUSED_ENTRY(230),
 913         I40E_PTT_UNUSED_ENTRY(231),
 914         I40E_PTT_UNUSED_ENTRY(232),
 915         I40E_PTT_UNUSED_ENTRY(233),
 916         I40E_PTT_UNUSED_ENTRY(234),
 917         I40E_PTT_UNUSED_ENTRY(235),
 918         I40E_PTT_UNUSED_ENTRY(236),
 919         I40E_PTT_UNUSED_ENTRY(237),
 920         I40E_PTT_UNUSED_ENTRY(238),
 921         I40E_PTT_UNUSED_ENTRY(239),
 922
 923         I40E_PTT_UNUSED_ENTRY(240),
 924         I40E_PTT_UNUSED_ENTRY(241),
 925         I40E_PTT_UNUSED_ENTRY(242),
 926         I40E_PTT_UNUSED_ENTRY(243),
 927         I40E_PTT_UNUSED_ENTRY(244),
 928         I40E_PTT_UNUSED_ENTRY(245),
 929         I40E_PTT_UNUSED_ENTRY(246),
 930         I40E_PTT_UNUSED_ENTRY(247),
 931         I40E_PTT_UNUSED_ENTRY(248),
 932         I40E_PTT_UNUSED_ENTRY(249),
 933
 934         I40E_PTT_UNUSED_ENTRY(250),
 935         I40E_PTT_UNUSED_ENTRY(251),
 936         I40E_PTT_UNUSED_ENTRY(252),
 937         I40E_PTT_UNUSED_ENTRY(253),
 938         I40E_PTT_UNUSED_ENTRY(254),
 939         I40E_PTT_UNUSED_ENTRY(255)
 940 };
 941
 942
 943 /**
 944  * i40e_validate_mac_addr - Validate unicast MAC address
 945  * @mac_addr: pointer to MAC address
 946  *
 947  * Tests a MAC address to ensure it is a valid Individual Address
 948  **/
 949 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
 950 {
 951         enum i40e_status_code status = I40E_SUCCESS;
 952
 953         DEBUGFUNC("i40e_validate_mac_addr");
 954
 955         /* Broadcast addresses ARE multicast addresses
 956          * Make sure it is not a multicast address
 957          * Reject the zero address
 958          */
 959         if (I40E_IS_MULTICAST(mac_addr) ||
 960             (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
 961               mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
 962                 status = I40E_ERR_INVALID_MAC_ADDR;
 963
 964         return status;
 965 }
 966 #ifdef PF_DRIVER
 967
 968 /**
 969  * i40e_init_shared_code - Initialize the shared code
 970  * @hw: pointer to hardware structure
 971  *
 972  * This assigns the MAC type and PHY code and inits the NVM.
 973  * Does not touch the hardware. This function must be called prior to any
 974  * other function in the shared code. The i40e_hw structure should be
 975  * memset to 0 prior to calling this function.  The following fields in
 976  * hw structure should be filled in prior to calling this function:
 977  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
 978  * subsystem_vendor_id, and revision_id
 979  **/
 980 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
 981 {
 982         enum i40e_status_code status = I40E_SUCCESS;
 983         u32 port, ari, func_rid;
 984
 985         DEBUGFUNC("i40e_init_shared_code");
 986
 987         i40e_set_mac_type(hw);
 988
 989         switch (hw->mac.type) {
 990         case I40E_MAC_XL710:
 991         case I40E_MAC_X722:
 992                 break;
 993         default:
 994                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
 995         }
 996
 997         hw->phy.get_link_info = true;
 998
 999         /* Determine port number and PF number*/
1000         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1001                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1002         hw->port = (u8)port;
1003         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1004                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1005         func_rid = rd32(hw, I40E_PF_FUNC_RID);
1006         if (ari)
1007                 hw->pf_id = (u8)(func_rid & 0xff);
1008         else
1009                 hw->pf_id = (u8)(func_rid & 0x7);
1010
1011         if (hw->mac.type == I40E_MAC_X722)
1012                 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE |
1013                              I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK;
1014
1015         status = i40e_init_nvm(hw);
1016         return status;
1017 }
1018
1019 /**
1020  * i40e_aq_mac_address_read - Retrieve the MAC addresses
1021  * @hw: pointer to the hw struct
1022  * @flags: a return indicator of what addresses were added to the addr store
1023  * @addrs: the requestor's mac addr store
1024  * @cmd_details: pointer to command details structure or NULL
1025  **/
1026 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1027                                    u16 *flags,
1028                                    struct i40e_aqc_mac_address_read_data *addrs,
1029                                    struct i40e_asq_cmd_details *cmd_details)
1030 {
1031         struct i40e_aq_desc desc;
1032         struct i40e_aqc_mac_address_read *cmd_data =
1033                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1034         enum i40e_status_code status;
1035
1036         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1037         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1038
1039         status = i40e_asq_send_command(hw, &desc, addrs,
1040                                        sizeof(*addrs), cmd_details);
1041         *flags = LE16_TO_CPU(cmd_data->command_flags);
1042
1043         return status;
1044 }
1045
1046 /**
1047  * i40e_aq_mac_address_write - Change the MAC addresses
1048  * @hw: pointer to the hw struct
1049  * @flags: indicates which MAC to be written
1050  * @mac_addr: address to write
1051  * @cmd_details: pointer to command details structure or NULL
1052  **/
1053 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1054                                     u16 flags, u8 *mac_addr,
1055                                     struct i40e_asq_cmd_details *cmd_details)
1056 {
1057         struct i40e_aq_desc desc;
1058         struct i40e_aqc_mac_address_write *cmd_data =
1059                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1060         enum i40e_status_code status;
1061
1062         i40e_fill_default_direct_cmd_desc(&desc,
1063                                           i40e_aqc_opc_mac_address_write);
1064         cmd_data->command_flags = CPU_TO_LE16(flags);
1065         cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1066         cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1067                                         ((u32)mac_addr[3] << 16) |
1068                                         ((u32)mac_addr[4] << 8) |
1069                                         mac_addr[5]);
1070
1071         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1072
1073         return status;
1074 }
1075
1076 /**
1077  * i40e_get_mac_addr - get MAC address
1078  * @hw: pointer to the HW structure
1079  * @mac_addr: pointer to MAC address
1080  *
1081  * Reads the adapter's MAC address from register
1082  **/
1083 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1084 {
1085         struct i40e_aqc_mac_address_read_data addrs;
1086         enum i40e_status_code status;
1087         u16 flags = 0;
1088
1089         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1090
1091         if (flags & I40E_AQC_LAN_ADDR_VALID)
1092                 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1093                         I40E_NONDMA_TO_NONDMA);
1094
1095         return status;
1096 }
1097
1098 /**
1099  * i40e_get_port_mac_addr - get Port MAC address
1100  * @hw: pointer to the HW structure
1101  * @mac_addr: pointer to Port MAC address
1102  *
1103  * Reads the adapter's Port MAC address
1104  **/
1105 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1106 {
1107         struct i40e_aqc_mac_address_read_data addrs;
1108         enum i40e_status_code status;
1109         u16 flags = 0;
1110
1111         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1112         if (status)
1113                 return status;
1114
1115         if (flags & I40E_AQC_PORT_ADDR_VALID)
1116                 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1117                         I40E_NONDMA_TO_NONDMA);
1118         else
1119                 status = I40E_ERR_INVALID_MAC_ADDR;
1120
1121         return status;
1122 }
1123
1124 /**
1125  * i40e_pre_tx_queue_cfg - pre tx queue configure
1126  * @hw: pointer to the HW structure
1127  * @queue: target pf queue index
1128  * @enable: state change request
1129  *
1130  * Handles hw requirement to indicate intention to enable
1131  * or disable target queue.
1132  **/
1133 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1134 {
1135         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1136         u32 reg_block = 0;
1137         u32 reg_val;
1138
1139         if (abs_queue_idx >= 128) {
1140                 reg_block = abs_queue_idx / 128;
1141                 abs_queue_idx %= 128;
1142         }
1143
1144         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1145         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1146         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1147
1148         if (enable)
1149                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1150         else
1151                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1152
1153         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1154 }
1155
1156 /**
1157  * i40e_get_san_mac_addr - get SAN MAC address
1158  * @hw: pointer to the HW structure
1159  * @mac_addr: pointer to SAN MAC address
1160  *
1161  * Reads the adapter's SAN MAC address from NVM
1162  **/
1163 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1164                                             u8 *mac_addr)
1165 {
1166         struct i40e_aqc_mac_address_read_data addrs;
1167         enum i40e_status_code status;
1168         u16 flags = 0;
1169
1170         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1171         if (status)
1172                 return status;
1173
1174         if (flags & I40E_AQC_SAN_ADDR_VALID)
1175                 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac),
1176                         I40E_NONDMA_TO_NONDMA);
1177         else
1178                 status = I40E_ERR_INVALID_MAC_ADDR;
1179
1180         return status;
1181 }
1182
1183 /**
1184  *  i40e_read_pba_string - Reads part number string from EEPROM
1185  *  @hw: pointer to hardware structure
1186  *  @pba_num: stores the part number string from the EEPROM
1187  *  @pba_num_size: part number string buffer length
1188  *
1189  *  Reads the part number string from the EEPROM.
1190  **/
1191 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1192                                             u32 pba_num_size)
1193 {
1194         enum i40e_status_code status = I40E_SUCCESS;
1195         u16 pba_word = 0;
1196         u16 pba_size = 0;
1197         u16 pba_ptr = 0;
1198         u16 i = 0;
1199
1200         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1201         if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1202                 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1203                 return status;
1204         }
1205
1206         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1207         if (status != I40E_SUCCESS) {
1208                 DEBUGOUT("Failed to read PBA Block pointer.\n");
1209                 return status;
1210         }
1211
1212         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1213         if (status != I40E_SUCCESS) {
1214                 DEBUGOUT("Failed to read PBA Block size.\n");
1215                 return status;
1216         }
1217
1218         /* Subtract one to get PBA word count (PBA Size word is included in
1219          * total size)
1220          */
1221         pba_size--;
1222         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1223                 DEBUGOUT("Buffer to small for PBA data.\n");
1224                 return I40E_ERR_PARAM;
1225         }
1226
1227         for (i = 0; i < pba_size; i++) {
1228                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1229                 if (status != I40E_SUCCESS) {
1230                         DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1231                         return status;
1232                 }
1233
1234                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1235                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1236         }
1237         pba_num[(pba_size * 2)] = '\0';
1238
1239         return status;
1240 }
1241
1242 /**
1243  * i40e_get_media_type - Gets media type
1244  * @hw: pointer to the hardware structure
1245  **/
1246 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1247 {
1248         enum i40e_media_type media;
1249
1250         switch (hw->phy.link_info.phy_type) {
1251         case I40E_PHY_TYPE_10GBASE_SR:
1252         case I40E_PHY_TYPE_10GBASE_LR:
1253         case I40E_PHY_TYPE_1000BASE_SX:
1254         case I40E_PHY_TYPE_1000BASE_LX:
1255         case I40E_PHY_TYPE_40GBASE_SR4:
1256         case I40E_PHY_TYPE_40GBASE_LR4:
1257         case I40E_PHY_TYPE_25GBASE_LR:
1258         case I40E_PHY_TYPE_25GBASE_SR:
1259                 media = I40E_MEDIA_TYPE_FIBER;
1260                 break;
1261         case I40E_PHY_TYPE_100BASE_TX:
1262         case I40E_PHY_TYPE_1000BASE_T:
1263         case I40E_PHY_TYPE_10GBASE_T:
1264                 media = I40E_MEDIA_TYPE_BASET;
1265                 break;
1266         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1267         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1268         case I40E_PHY_TYPE_10GBASE_CR1:
1269         case I40E_PHY_TYPE_40GBASE_CR4:
1270         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1271         case I40E_PHY_TYPE_40GBASE_AOC:
1272         case I40E_PHY_TYPE_10GBASE_AOC:
1273         case I40E_PHY_TYPE_25GBASE_CR:
1274         case I40E_PHY_TYPE_25GBASE_AOC:
1275         case I40E_PHY_TYPE_25GBASE_ACC:
1276                 media = I40E_MEDIA_TYPE_DA;
1277                 break;
1278         case I40E_PHY_TYPE_1000BASE_KX:
1279         case I40E_PHY_TYPE_10GBASE_KX4:
1280         case I40E_PHY_TYPE_10GBASE_KR:
1281         case I40E_PHY_TYPE_40GBASE_KR4:
1282         case I40E_PHY_TYPE_20GBASE_KR2:
1283         case I40E_PHY_TYPE_25GBASE_KR:
1284                 media = I40E_MEDIA_TYPE_BACKPLANE;
1285                 break;
1286         case I40E_PHY_TYPE_SGMII:
1287         case I40E_PHY_TYPE_XAUI:
1288         case I40E_PHY_TYPE_XFI:
1289         case I40E_PHY_TYPE_XLAUI:
1290         case I40E_PHY_TYPE_XLPPI:
1291         default:
1292                 media = I40E_MEDIA_TYPE_UNKNOWN;
1293                 break;
1294         }
1295
1296         return media;
1297 }
1298
1299 /**
1300  * i40e_poll_globr - Poll for Global Reset completion
1301  * @hw: pointer to the hardware structure
1302  * @retry_limit: how many times to retry before failure
1303  **/
1304 STATIC enum i40e_status_code i40e_poll_globr(struct i40e_hw *hw,
1305                                              u32 retry_limit)
1306 {
1307         u32 cnt, reg = 0;
1308
1309         for (cnt = 0; cnt < retry_limit; cnt++) {
1310                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1311                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1312                         return I40E_SUCCESS;
1313                 i40e_msec_delay(100);
1314         }
1315
1316         DEBUGOUT("Global reset failed.\n");
1317         DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg);
1318
1319         return I40E_ERR_RESET_FAILED;
1320 }
1321
1322 #define I40E_PF_RESET_WAIT_COUNT        200
1323 /**
1324  * i40e_pf_reset - Reset the PF
1325  * @hw: pointer to the hardware structure
1326  *
1327  * Assuming someone else has triggered a global reset,
1328  * assure the global reset is complete and then reset the PF
1329  **/
1330 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1331 {
1332         u32 cnt = 0;
1333         u32 cnt1 = 0;
1334         u32 reg = 0;
1335         u32 grst_del;
1336
1337         /* Poll for Global Reset steady state in case of recent GRST.
1338          * The grst delay value is in 100ms units, and we'll wait a
1339          * couple counts longer to be sure we don't just miss the end.
1340          */
1341         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1342                         I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1343                         I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1344
1345         grst_del = min(grst_del * 20, 160U);
1346
1347         for (cnt = 0; cnt < grst_del; cnt++) {
1348                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1349                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1350                         break;
1351                 i40e_msec_delay(100);
1352         }
1353         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1354                 DEBUGOUT("Global reset polling failed to complete.\n");
1355                 return I40E_ERR_RESET_FAILED;
1356         }
1357
1358         /* Now Wait for the FW to be ready */
1359         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1360                 reg = rd32(hw, I40E_GLNVM_ULD);
1361                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1362                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1363                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1364                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1365                         DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1366                         break;
1367                 }
1368                 i40e_msec_delay(10);
1369         }
1370         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1371                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1372                 DEBUGOUT("wait for FW Reset complete timedout\n");
1373                 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1374                 return I40E_ERR_RESET_FAILED;
1375         }
1376
1377         /* If there was a Global Reset in progress when we got here,
1378          * we don't need to do the PF Reset
1379          */
1380         if (!cnt) {
1381                 u32 reg2 = 0;
1382
1383                 reg = rd32(hw, I40E_PFGEN_CTRL);
1384                 wr32(hw, I40E_PFGEN_CTRL,
1385                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1386                 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1387                         reg = rd32(hw, I40E_PFGEN_CTRL);
1388                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1389                                 break;
1390                         reg2 = rd32(hw, I40E_GLGEN_RSTAT);
1391                         if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK)
1392                                 break;
1393                         i40e_msec_delay(1);
1394                 }
1395                 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1396                         if (i40e_poll_globr(hw, grst_del) != I40E_SUCCESS)
1397                                 return I40E_ERR_RESET_FAILED;
1398                 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1399                         DEBUGOUT("PF reset polling failed to complete.\n");
1400                         return I40E_ERR_RESET_FAILED;
1401                 }
1402         }
1403
1404         i40e_clear_pxe_mode(hw);
1405
1406
1407         return I40E_SUCCESS;
1408 }
1409
1410 /**
1411  * i40e_clear_hw - clear out any left over hw state
1412  * @hw: pointer to the hw struct
1413  *
1414  * Clear queues and interrupts, typically called at init time,
1415  * but after the capabilities have been found so we know how many
1416  * queues and msix vectors have been allocated.
1417  **/
1418 void i40e_clear_hw(struct i40e_hw *hw)
1419 {
1420         u32 num_queues, base_queue;
1421         u32 num_pf_int;
1422         u32 num_vf_int;
1423         u32 num_vfs;
1424         u32 i, j;
1425         u32 val;
1426         u32 eol = 0x7ff;
1427
1428         /* get number of interrupts, queues, and vfs */
1429         val = rd32(hw, I40E_GLPCI_CNF2);
1430         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1431                         I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1432         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1433                         I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1434
1435         val = rd32(hw, I40E_PFLAN_QALLOC);
1436         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1437                         I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1438         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1439                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1440         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1441                 num_queues = (j - base_queue) + 1;
1442         else
1443                 num_queues = 0;
1444
1445         val = rd32(hw, I40E_PF_VT_PFALLOC);
1446         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1447                         I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1448         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1449                         I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1450         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1451                 num_vfs = (j - i) + 1;
1452         else
1453                 num_vfs = 0;
1454
1455         /* stop all the interrupts */
1456         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1457         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1458         for (i = 0; i < num_pf_int - 2; i++)
1459                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1460
1461         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1462         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1463         wr32(hw, I40E_PFINT_LNKLST0, val);
1464         for (i = 0; i < num_pf_int - 2; i++)
1465                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1466         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1467         for (i = 0; i < num_vfs; i++)
1468                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1469         for (i = 0; i < num_vf_int - 2; i++)
1470                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1471
1472         /* warn the HW of the coming Tx disables */
1473         for (i = 0; i < num_queues; i++) {
1474                 u32 abs_queue_idx = base_queue + i;
1475                 u32 reg_block = 0;
1476
1477                 if (abs_queue_idx >= 128) {
1478                         reg_block = abs_queue_idx / 128;
1479                         abs_queue_idx %= 128;
1480                 }
1481
1482                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1483                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1484                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1485                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1486
1487                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1488         }
1489         i40e_usec_delay(400);
1490
1491         /* stop all the queues */
1492         for (i = 0; i < num_queues; i++) {
1493                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1494                 wr32(hw, I40E_QTX_ENA(i), 0);
1495                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1496                 wr32(hw, I40E_QRX_ENA(i), 0);
1497         }
1498
1499         /* short wait for all queue disables to settle */
1500         i40e_usec_delay(50);
1501 }
1502
1503 /**
1504  * i40e_clear_pxe_mode - clear pxe operations mode
1505  * @hw: pointer to the hw struct
1506  *
1507  * Make sure all PXE mode settings are cleared, including things
1508  * like descriptor fetch/write-back mode.
1509  **/
1510 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1511 {
1512         if (i40e_check_asq_alive(hw))
1513                 i40e_aq_clear_pxe_mode(hw, NULL);
1514 }
1515
1516 /**
1517  * i40e_led_is_mine - helper to find matching led
1518  * @hw: pointer to the hw struct
1519  * @idx: index into GPIO registers
1520  *
1521  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1522  */
1523 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1524 {
1525         u32 gpio_val = 0;
1526         u32 port;
1527
1528         if (!hw->func_caps.led[idx])
1529                 return 0;
1530
1531         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1532         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1533                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1534
1535         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1536          * if it is not our port then ignore
1537          */
1538         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1539             (port != hw->port))
1540                 return 0;
1541
1542         return gpio_val;
1543 }
1544
1545 #define I40E_COMBINED_ACTIVITY 0xA
1546 #define I40E_FILTER_ACTIVITY 0xE
1547 #define I40E_LINK_ACTIVITY 0xC
1548 #define I40E_MAC_ACTIVITY 0xD
1549 #define I40E_LED0 22
1550
1551 /**
1552  * i40e_led_get - return current on/off mode
1553  * @hw: pointer to the hw struct
1554  *
1555  * The value returned is the 'mode' field as defined in the
1556  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1557  * values are variations of possible behaviors relating to
1558  * blink, link, and wire.
1559  **/
1560 u32 i40e_led_get(struct i40e_hw *hw)
1561 {
1562         u32 current_mode = 0;
1563         u32 mode = 0;
1564         int i;
1565
1566         /* as per the documentation GPIO 22-29 are the LED
1567          * GPIO pins named LED0..LED7
1568          */
1569         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1570                 u32 gpio_val = i40e_led_is_mine(hw, i);
1571
1572                 if (!gpio_val)
1573                         continue;
1574
1575                 /* ignore gpio LED src mode entries related to the activity
1576                  *  LEDs
1577                  */
1578                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1579                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1580                 switch (current_mode) {
1581                 case I40E_COMBINED_ACTIVITY:
1582                 case I40E_FILTER_ACTIVITY:
1583                 case I40E_MAC_ACTIVITY:
1584                 case I40E_LINK_ACTIVITY:
1585                         continue;
1586                 default:
1587                         break;
1588                 }
1589
1590                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1591                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1592                 break;
1593         }
1594
1595         return mode;
1596 }
1597
1598 /**
1599  * i40e_led_set - set new on/off mode
1600  * @hw: pointer to the hw struct
1601  * @mode: 0=off, 0xf=on (else see manual for mode details)
1602  * @blink: true if the LED should blink when on, false if steady
1603  *
1604  * if this function is used to turn on the blink it should
1605  * be used to disable the blink when restoring the original state.
1606  **/
1607 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1608 {
1609         u32 current_mode = 0;
1610         int i;
1611
1612         if (mode & 0xfffffff0)
1613                 DEBUGOUT1("invalid mode passed in %X\n", mode);
1614
1615         /* as per the documentation GPIO 22-29 are the LED
1616          * GPIO pins named LED0..LED7
1617          */
1618         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1619                 u32 gpio_val = i40e_led_is_mine(hw, i);
1620
1621                 if (!gpio_val)
1622                         continue;
1623
1624                 /* ignore gpio LED src mode entries related to the activity
1625                  * LEDs
1626                  */
1627                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1628                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1629                 switch (current_mode) {
1630                 case I40E_COMBINED_ACTIVITY:
1631                 case I40E_FILTER_ACTIVITY:
1632                 case I40E_MAC_ACTIVITY:
1633                 case I40E_LINK_ACTIVITY:
1634                         continue;
1635                 default:
1636                         break;
1637                 }
1638
1639                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1640                 /* this & is a bit of paranoia, but serves as a range check */
1641                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1642                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1643
1644                 if (blink)
1645                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1646                 else
1647                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1648
1649                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1650                 break;
1651         }
1652 }
1653
1654 /* Admin command wrappers */
1655
1656 /**
1657  * i40e_aq_get_phy_capabilities
1658  * @hw: pointer to the hw struct
1659  * @abilities: structure for PHY capabilities to be filled
1660  * @qualified_modules: report Qualified Modules
1661  * @report_init: report init capabilities (active are default)
1662  * @cmd_details: pointer to command details structure or NULL
1663  *
1664  * Returns the various PHY abilities supported on the Port.
1665  **/
1666 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1667                         bool qualified_modules, bool report_init,
1668                         struct i40e_aq_get_phy_abilities_resp *abilities,
1669                         struct i40e_asq_cmd_details *cmd_details)
1670 {
1671         struct i40e_aq_desc desc;
1672         enum i40e_status_code status;
1673         u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0;
1674         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1675
1676         if (!abilities)
1677                 return I40E_ERR_PARAM;
1678
1679         do {
1680                 i40e_fill_default_direct_cmd_desc(&desc,
1681                                                i40e_aqc_opc_get_phy_abilities);
1682
1683                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1684                 if (abilities_size > I40E_AQ_LARGE_BUF)
1685                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1686
1687                 if (qualified_modules)
1688                         desc.params.external.param0 |=
1689                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1690
1691                 if (report_init)
1692                         desc.params.external.param0 |=
1693                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1694
1695                 status = i40e_asq_send_command(hw, &desc, abilities,
1696                                                abilities_size, cmd_details);
1697
1698                 if (status != I40E_SUCCESS)
1699                         break;
1700
1701                 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) {
1702                         status = I40E_ERR_UNKNOWN_PHY;
1703                         break;
1704                 } else if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) {
1705                         i40e_msec_delay(1);
1706                         total_delay++;
1707                         status = I40E_ERR_TIMEOUT;
1708                 }
1709         } while ((hw->aq.asq_last_status != I40E_AQ_RC_OK) &&
1710                  (total_delay < max_delay));
1711
1712         if (status != I40E_SUCCESS)
1713                 return status;
1714
1715         if (report_init) {
1716                 if (hw->mac.type ==  I40E_MAC_XL710 &&
1717                     hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1718                     hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
1719                         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1720                 } else {
1721                         hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1722                         hw->phy.phy_types |=
1723                                         ((u64)abilities->phy_type_ext << 32);
1724                 }
1725         }
1726
1727         return status;
1728 }
1729
1730 /**
1731  * i40e_aq_set_phy_config
1732  * @hw: pointer to the hw struct
1733  * @config: structure with PHY configuration to be set
1734  * @cmd_details: pointer to command details structure or NULL
1735  *
1736  * Set the various PHY configuration parameters
1737  * supported on the Port.One or more of the Set PHY config parameters may be
1738  * ignored in an MFP mode as the PF may not have the privilege to set some
1739  * of the PHY Config parameters. This status will be indicated by the
1740  * command response.
1741  **/
1742 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1743                                 struct i40e_aq_set_phy_config *config,
1744                                 struct i40e_asq_cmd_details *cmd_details)
1745 {
1746         struct i40e_aq_desc desc;
1747         struct i40e_aq_set_phy_config *cmd =
1748                 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1749         enum i40e_status_code status;
1750
1751         if (!config)
1752                 return I40E_ERR_PARAM;
1753
1754         i40e_fill_default_direct_cmd_desc(&desc,
1755                                           i40e_aqc_opc_set_phy_config);
1756
1757         *cmd = *config;
1758
1759         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1760
1761         return status;
1762 }
1763
1764 /**
1765  * i40e_set_fc
1766  * @hw: pointer to the hw struct
1767  * @aq_failures: buffer to return AdminQ failure information
1768  * @atomic_restart: whether to enable atomic link restart
1769  *
1770  * Set the requested flow control mode using set_phy_config.
1771  **/
1772 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1773                                   bool atomic_restart)
1774 {
1775         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1776         struct i40e_aq_get_phy_abilities_resp abilities;
1777         struct i40e_aq_set_phy_config config;
1778         enum i40e_status_code status;
1779         u8 pause_mask = 0x0;
1780
1781         *aq_failures = 0x0;
1782
1783         switch (fc_mode) {
1784         case I40E_FC_FULL:
1785                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1786                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1787                 break;
1788         case I40E_FC_RX_PAUSE:
1789                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1790                 break;
1791         case I40E_FC_TX_PAUSE:
1792                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1793                 break;
1794         default:
1795                 break;
1796         }
1797
1798         /* Get the current phy config */
1799         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1800                                               NULL);
1801         if (status) {
1802                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1803                 return status;
1804         }
1805
1806         memset(&config, 0, sizeof(config));
1807         /* clear the old pause settings */
1808         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1809                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1810         /* set the new abilities */
1811         config.abilities |= pause_mask;
1812         /* If the abilities have changed, then set the new config */
1813         if (config.abilities != abilities.abilities) {
1814                 /* Auto restart link so settings take effect */
1815                 if (atomic_restart)
1816                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1817                 /* Copy over all the old settings */
1818                 config.phy_type = abilities.phy_type;
1819                 config.phy_type_ext = abilities.phy_type_ext;
1820                 config.link_speed = abilities.link_speed;
1821                 config.eee_capability = abilities.eee_capability;
1822                 config.eeer = abilities.eeer_val;
1823                 config.low_power_ctrl = abilities.d3_lpan;
1824                 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1825                                     I40E_AQ_PHY_FEC_CONFIG_MASK;
1826                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1827
1828                 if (status)
1829                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1830         }
1831         /* Update the link info */
1832         status = i40e_update_link_info(hw);
1833         if (status) {
1834                 /* Wait a little bit (on 40G cards it sometimes takes a really
1835                  * long time for link to come back from the atomic reset)
1836                  * and try once more
1837                  */
1838                 i40e_msec_delay(1000);
1839                 status = i40e_update_link_info(hw);
1840         }
1841         if (status)
1842                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1843
1844         return status;
1845 }
1846
1847 /**
1848  * i40e_aq_set_mac_config
1849  * @hw: pointer to the hw struct
1850  * @max_frame_size: Maximum Frame Size to be supported by the port
1851  * @crc_en: Tell HW to append a CRC to outgoing frames
1852  * @pacing: Pacing configurations
1853  * @cmd_details: pointer to command details structure or NULL
1854  *
1855  * Configure MAC settings for frame size, jumbo frame support and the
1856  * addition of a CRC by the hardware.
1857  **/
1858 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1859                                 u16 max_frame_size,
1860                                 bool crc_en, u16 pacing,
1861                                 struct i40e_asq_cmd_details *cmd_details)
1862 {
1863         struct i40e_aq_desc desc;
1864         struct i40e_aq_set_mac_config *cmd =
1865                 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1866         enum i40e_status_code status;
1867
1868         if (max_frame_size == 0)
1869                 return I40E_ERR_PARAM;
1870
1871         i40e_fill_default_direct_cmd_desc(&desc,
1872                                           i40e_aqc_opc_set_mac_config);
1873
1874         cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1875         cmd->params = ((u8)pacing & 0x0F) << 3;
1876         if (crc_en)
1877                 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1878
1879         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1880
1881         return status;
1882 }
1883
1884 /**
1885  * i40e_aq_clear_pxe_mode
1886  * @hw: pointer to the hw struct
1887  * @cmd_details: pointer to command details structure or NULL
1888  *
1889  * Tell the firmware that the driver is taking over from PXE
1890  **/
1891 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1892                         struct i40e_asq_cmd_details *cmd_details)
1893 {
1894         enum i40e_status_code status;
1895         struct i40e_aq_desc desc;
1896         struct i40e_aqc_clear_pxe *cmd =
1897                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1898
1899         i40e_fill_default_direct_cmd_desc(&desc,
1900                                           i40e_aqc_opc_clear_pxe_mode);
1901
1902         cmd->rx_cnt = 0x2;
1903
1904         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1905
1906         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1907
1908         return status;
1909 }
1910
1911 /**
1912  * i40e_aq_set_link_restart_an
1913  * @hw: pointer to the hw struct
1914  * @enable_link: if true: enable link, if false: disable link
1915  * @cmd_details: pointer to command details structure or NULL
1916  *
1917  * Sets up the link and restarts the Auto-Negotiation over the link.
1918  **/
1919 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1920                 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1921 {
1922         struct i40e_aq_desc desc;
1923         struct i40e_aqc_set_link_restart_an *cmd =
1924                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1925         enum i40e_status_code status;
1926
1927         i40e_fill_default_direct_cmd_desc(&desc,
1928                                           i40e_aqc_opc_set_link_restart_an);
1929
1930         cmd->command = I40E_AQ_PHY_RESTART_AN;
1931         if (enable_link)
1932                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1933         else
1934                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1935
1936         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1937
1938         return status;
1939 }
1940
1941 /**
1942  * i40e_aq_get_link_info
1943  * @hw: pointer to the hw struct
1944  * @enable_lse: enable/disable LinkStatusEvent reporting
1945  * @link: pointer to link status structure - optional
1946  * @cmd_details: pointer to command details structure or NULL
1947  *
1948  * Returns the link status of the adapter.
1949  **/
1950 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1951                                 bool enable_lse, struct i40e_link_status *link,
1952                                 struct i40e_asq_cmd_details *cmd_details)
1953 {
1954         struct i40e_aq_desc desc;
1955         struct i40e_aqc_get_link_status *resp =
1956                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1957         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1958         enum i40e_status_code status;
1959         bool tx_pause, rx_pause;
1960         u16 command_flags;
1961
1962         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1963
1964         if (enable_lse)
1965                 command_flags = I40E_AQ_LSE_ENABLE;
1966         else
1967                 command_flags = I40E_AQ_LSE_DISABLE;
1968         resp->command_flags = CPU_TO_LE16(command_flags);
1969
1970         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1971
1972         if (status != I40E_SUCCESS)
1973                 goto aq_get_link_info_exit;
1974
1975         /* save off old link status information */
1976         i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1977                     sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1978
1979         /* update link status */
1980         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1981         hw->phy.media_type = i40e_get_media_type(hw);
1982         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1983         hw_link_info->link_info = resp->link_info;
1984         hw_link_info->an_info = resp->an_info;
1985         hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
1986                                                  I40E_AQ_CONFIG_FEC_RS_ENA);
1987         hw_link_info->ext_info = resp->ext_info;
1988         hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
1989         hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1990         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1991
1992         /* update fc info */
1993         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1994         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1995         if (tx_pause & rx_pause)
1996                 hw->fc.current_mode = I40E_FC_FULL;
1997         else if (tx_pause)
1998                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1999         else if (rx_pause)
2000                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
2001         else
2002                 hw->fc.current_mode = I40E_FC_NONE;
2003
2004         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
2005                 hw_link_info->crc_enable = true;
2006         else
2007                 hw_link_info->crc_enable = false;
2008
2009         if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
2010                 hw_link_info->lse_enable = true;
2011         else
2012                 hw_link_info->lse_enable = false;
2013
2014         if ((hw->mac.type == I40E_MAC_XL710) &&
2015             (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
2016              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
2017                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
2018
2019         if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
2020             hw->aq.api_min_ver >= 7) {
2021                 __le32 tmp;
2022
2023                 i40e_memcpy(&tmp, resp->link_type, sizeof(tmp),
2024                             I40E_NONDMA_TO_NONDMA);
2025                 hw->phy.phy_types = LE32_TO_CPU(tmp);
2026                 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
2027         }
2028
2029         /* save link status information */
2030         if (link)
2031                 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
2032                             I40E_NONDMA_TO_NONDMA);
2033
2034         /* flag cleared so helper functions don't call AQ again */
2035         hw->phy.get_link_info = false;
2036
2037 aq_get_link_info_exit:
2038         return status;
2039 }
2040
2041 /**
2042  * i40e_aq_set_phy_int_mask
2043  * @hw: pointer to the hw struct
2044  * @mask: interrupt mask to be set
2045  * @cmd_details: pointer to command details structure or NULL
2046  *
2047  * Set link interrupt mask.
2048  **/
2049 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2050                                 u16 mask,
2051                                 struct i40e_asq_cmd_details *cmd_details)
2052 {
2053         struct i40e_aq_desc desc;
2054         struct i40e_aqc_set_phy_int_mask *cmd =
2055                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2056         enum i40e_status_code status;
2057
2058         i40e_fill_default_direct_cmd_desc(&desc,
2059                                           i40e_aqc_opc_set_phy_int_mask);
2060
2061         cmd->event_mask = CPU_TO_LE16(mask);
2062
2063         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2064
2065         return status;
2066 }
2067
2068 /**
2069  * i40e_aq_get_local_advt_reg
2070  * @hw: pointer to the hw struct
2071  * @advt_reg: local AN advertisement register value
2072  * @cmd_details: pointer to command details structure or NULL
2073  *
2074  * Get the Local AN advertisement register value.
2075  **/
2076 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2077                                 u64 *advt_reg,
2078                                 struct i40e_asq_cmd_details *cmd_details)
2079 {
2080         struct i40e_aq_desc desc;
2081         struct i40e_aqc_an_advt_reg *resp =
2082                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2083         enum i40e_status_code status;
2084
2085         i40e_fill_default_direct_cmd_desc(&desc,
2086                                           i40e_aqc_opc_get_local_advt_reg);
2087
2088         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2089
2090         if (status != I40E_SUCCESS)
2091                 goto aq_get_local_advt_reg_exit;
2092
2093         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2094         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2095
2096 aq_get_local_advt_reg_exit:
2097         return status;
2098 }
2099
2100 /**
2101  * i40e_aq_set_local_advt_reg
2102  * @hw: pointer to the hw struct
2103  * @advt_reg: local AN advertisement register value
2104  * @cmd_details: pointer to command details structure or NULL
2105  *
2106  * Get the Local AN advertisement register value.
2107  **/
2108 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2109                                 u64 advt_reg,
2110                                 struct i40e_asq_cmd_details *cmd_details)
2111 {
2112         struct i40e_aq_desc desc;
2113         struct i40e_aqc_an_advt_reg *cmd =
2114                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2115         enum i40e_status_code status;
2116
2117         i40e_fill_default_direct_cmd_desc(&desc,
2118                                           i40e_aqc_opc_get_local_advt_reg);
2119
2120         cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2121         cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2122
2123         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2124
2125         return status;
2126 }
2127
2128 /**
2129  * i40e_aq_get_partner_advt
2130  * @hw: pointer to the hw struct
2131  * @advt_reg: AN partner advertisement register value
2132  * @cmd_details: pointer to command details structure or NULL
2133  *
2134  * Get the link partner AN advertisement register value.
2135  **/
2136 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2137                                 u64 *advt_reg,
2138                                 struct i40e_asq_cmd_details *cmd_details)
2139 {
2140         struct i40e_aq_desc desc;
2141         struct i40e_aqc_an_advt_reg *resp =
2142                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2143         enum i40e_status_code status;
2144
2145         i40e_fill_default_direct_cmd_desc(&desc,
2146                                           i40e_aqc_opc_get_partner_advt);
2147
2148         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2149
2150         if (status != I40E_SUCCESS)
2151                 goto aq_get_partner_advt_exit;
2152
2153         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2154         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2155
2156 aq_get_partner_advt_exit:
2157         return status;
2158 }
2159
2160 /**
2161  * i40e_aq_set_lb_modes
2162  * @hw: pointer to the hw struct
2163  * @lb_modes: loopback mode to be set
2164  * @cmd_details: pointer to command details structure or NULL
2165  *
2166  * Sets loopback modes.
2167  **/
2168 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2169                                 u16 lb_modes,
2170                                 struct i40e_asq_cmd_details *cmd_details)
2171 {
2172         struct i40e_aq_desc desc;
2173         struct i40e_aqc_set_lb_mode *cmd =
2174                 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2175         enum i40e_status_code status;
2176
2177         i40e_fill_default_direct_cmd_desc(&desc,
2178                                           i40e_aqc_opc_set_lb_modes);
2179
2180         cmd->lb_mode = CPU_TO_LE16(lb_modes);
2181
2182         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2183
2184         return status;
2185 }
2186
2187 /**
2188  * i40e_aq_set_phy_debug
2189  * @hw: pointer to the hw struct
2190  * @cmd_flags: debug command flags
2191  * @cmd_details: pointer to command details structure or NULL
2192  *
2193  * Reset the external PHY.
2194  **/
2195 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2196                                 struct i40e_asq_cmd_details *cmd_details)
2197 {
2198         struct i40e_aq_desc desc;
2199         struct i40e_aqc_set_phy_debug *cmd =
2200                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2201         enum i40e_status_code status;
2202
2203         i40e_fill_default_direct_cmd_desc(&desc,
2204                                           i40e_aqc_opc_set_phy_debug);
2205
2206         cmd->command_flags = cmd_flags;
2207
2208         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2209
2210         return status;
2211 }
2212
2213 /**
2214  * i40e_aq_add_vsi
2215  * @hw: pointer to the hw struct
2216  * @vsi_ctx: pointer to a vsi context struct
2217  * @cmd_details: pointer to command details structure or NULL
2218  *
2219  * Add a VSI context to the hardware.
2220 **/
2221 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2222                                 struct i40e_vsi_context *vsi_ctx,
2223                                 struct i40e_asq_cmd_details *cmd_details)
2224 {
2225         struct i40e_aq_desc desc;
2226         struct i40e_aqc_add_get_update_vsi *cmd =
2227                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2228         struct i40e_aqc_add_get_update_vsi_completion *resp =
2229                 (struct i40e_aqc_add_get_update_vsi_completion *)
2230                 &desc.params.raw;
2231         enum i40e_status_code status;
2232
2233         i40e_fill_default_direct_cmd_desc(&desc,
2234                                           i40e_aqc_opc_add_vsi);
2235
2236         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2237         cmd->connection_type = vsi_ctx->connection_type;
2238         cmd->vf_id = vsi_ctx->vf_num;
2239         cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2240
2241         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2242
2243         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2244                                     sizeof(vsi_ctx->info), cmd_details);
2245
2246         if (status != I40E_SUCCESS)
2247                 goto aq_add_vsi_exit;
2248
2249         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2250         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2251         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2252         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2253
2254 aq_add_vsi_exit:
2255         return status;
2256 }
2257
2258 /**
2259  * i40e_aq_set_default_vsi
2260  * @hw: pointer to the hw struct
2261  * @seid: vsi number
2262  * @cmd_details: pointer to command details structure or NULL
2263  **/
2264 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2265                                 u16 seid,
2266                                 struct i40e_asq_cmd_details *cmd_details)
2267 {
2268         struct i40e_aq_desc desc;
2269         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2270                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2271                 &desc.params.raw;
2272         enum i40e_status_code status;
2273
2274         i40e_fill_default_direct_cmd_desc(&desc,
2275                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2276
2277         cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2278         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2279         cmd->seid = CPU_TO_LE16(seid);
2280
2281         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2282
2283         return status;
2284 }
2285
2286 /**
2287  * i40e_aq_clear_default_vsi
2288  * @hw: pointer to the hw struct
2289  * @seid: vsi number
2290  * @cmd_details: pointer to command details structure or NULL
2291  **/
2292 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2293                                 u16 seid,
2294                                 struct i40e_asq_cmd_details *cmd_details)
2295 {
2296         struct i40e_aq_desc desc;
2297         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2298                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2299                 &desc.params.raw;
2300         enum i40e_status_code status;
2301
2302         i40e_fill_default_direct_cmd_desc(&desc,
2303                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2304
2305         cmd->promiscuous_flags = CPU_TO_LE16(0);
2306         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2307         cmd->seid = CPU_TO_LE16(seid);
2308
2309         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2310
2311         return status;
2312 }
2313
2314 /**
2315  * i40e_aq_set_vsi_unicast_promiscuous
2316  * @hw: pointer to the hw struct
2317  * @seid: vsi number
2318  * @set: set unicast promiscuous enable/disable
2319  * @cmd_details: pointer to command details structure or NULL
2320  * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2321  **/
2322 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2323                                 u16 seid, bool set,
2324                                 struct i40e_asq_cmd_details *cmd_details,
2325                                 bool rx_only_promisc)
2326 {
2327         struct i40e_aq_desc desc;
2328         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2329                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2330         enum i40e_status_code status;
2331         u16 flags = 0;
2332
2333         i40e_fill_default_direct_cmd_desc(&desc,
2334                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2335
2336         if (set) {
2337                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2338                 if (rx_only_promisc &&
2339                     (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2340                      (hw->aq.api_maj_ver > 1)))
2341                         flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2342         }
2343
2344         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2345
2346         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2347         if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2348              (hw->aq.api_maj_ver > 1))
2349                 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2350
2351         cmd->seid = CPU_TO_LE16(seid);
2352         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2353
2354         return status;
2355 }
2356
2357 /**
2358  * i40e_aq_set_vsi_multicast_promiscuous
2359  * @hw: pointer to the hw struct
2360  * @seid: vsi number
2361  * @set: set multicast promiscuous enable/disable
2362  * @cmd_details: pointer to command details structure or NULL
2363  **/
2364 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2365                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2366 {
2367         struct i40e_aq_desc desc;
2368         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2369                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2370         enum i40e_status_code status;
2371         u16 flags = 0;
2372
2373         i40e_fill_default_direct_cmd_desc(&desc,
2374                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2375
2376         if (set)
2377                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2378
2379         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2380
2381         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2382
2383         cmd->seid = CPU_TO_LE16(seid);
2384         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2385
2386         return status;
2387 }
2388
2389 /**
2390 * i40e_aq_set_vsi_full_promiscuous
2391 * @hw: pointer to the hw struct
2392 * @seid: VSI number
2393 * @set: set promiscuous enable/disable
2394 * @cmd_details: pointer to command details structure or NULL
2395 **/
2396 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw,
2397                                 u16 seid, bool set,
2398                                 struct i40e_asq_cmd_details *cmd_details)
2399 {
2400         struct i40e_aq_desc desc;
2401         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2402                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2403         enum i40e_status_code status;
2404         u16 flags = 0;
2405
2406         i40e_fill_default_direct_cmd_desc(&desc,
2407                 i40e_aqc_opc_set_vsi_promiscuous_modes);
2408
2409         if (set)
2410                 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2411                         I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2412                         I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2413
2414         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2415
2416         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2417                                        I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2418                                        I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2419
2420         cmd->seid = CPU_TO_LE16(seid);
2421         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2422
2423         return status;
2424 }
2425
2426 /**
2427  * i40e_aq_set_vsi_mc_promisc_on_vlan
2428  * @hw: pointer to the hw struct
2429  * @seid: vsi number
2430  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2431  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2432  * @cmd_details: pointer to command details structure or NULL
2433  **/
2434 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2435                                 u16 seid, bool enable, u16 vid,
2436                                 struct i40e_asq_cmd_details *cmd_details)
2437 {
2438         struct i40e_aq_desc desc;
2439         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2440                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2441         enum i40e_status_code status;
2442         u16 flags = 0;
2443
2444         i40e_fill_default_direct_cmd_desc(&desc,
2445                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2446
2447         if (enable)
2448                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2449
2450         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2451         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2452         cmd->seid = CPU_TO_LE16(seid);
2453         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2454
2455         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2456
2457         return status;
2458 }
2459
2460 /**
2461  * i40e_aq_set_vsi_uc_promisc_on_vlan
2462  * @hw: pointer to the hw struct
2463  * @seid: vsi number
2464  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2465  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2466  * @cmd_details: pointer to command details structure or NULL
2467  **/
2468 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2469                                 u16 seid, bool enable, u16 vid,
2470                                 struct i40e_asq_cmd_details *cmd_details)
2471 {
2472         struct i40e_aq_desc desc;
2473         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2474                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2475         enum i40e_status_code status;
2476         u16 flags = 0;
2477
2478         i40e_fill_default_direct_cmd_desc(&desc,
2479                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2480
2481         if (enable)
2482                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2483
2484         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2485         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2486         cmd->seid = CPU_TO_LE16(seid);
2487         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2488
2489         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2490
2491         return status;
2492 }
2493
2494 /**
2495  * i40e_aq_set_vsi_bc_promisc_on_vlan
2496  * @hw: pointer to the hw struct
2497  * @seid: vsi number
2498  * @enable: set broadcast promiscuous enable/disable for a given VLAN
2499  * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2500  * @cmd_details: pointer to command details structure or NULL
2501  **/
2502 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2503                                 u16 seid, bool enable, u16 vid,
2504                                 struct i40e_asq_cmd_details *cmd_details)
2505 {
2506         struct i40e_aq_desc desc;
2507         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2508                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2509         enum i40e_status_code status;
2510         u16 flags = 0;
2511
2512         i40e_fill_default_direct_cmd_desc(&desc,
2513                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2514
2515         if (enable)
2516                 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2517
2518         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2519         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2520         cmd->seid = CPU_TO_LE16(seid);
2521         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2522
2523         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2524
2525         return status;
2526 }
2527
2528 /**
2529  * i40e_aq_set_vsi_broadcast
2530  * @hw: pointer to the hw struct
2531  * @seid: vsi number
2532  * @set_filter: true to set filter, false to clear filter
2533  * @cmd_details: pointer to command details structure or NULL
2534  *
2535  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2536  **/
2537 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2538                                 u16 seid, bool set_filter,
2539                                 struct i40e_asq_cmd_details *cmd_details)
2540 {
2541         struct i40e_aq_desc desc;
2542         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2543                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2544         enum i40e_status_code status;
2545
2546         i40e_fill_default_direct_cmd_desc(&desc,
2547                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2548
2549         if (set_filter)
2550                 cmd->promiscuous_flags
2551                             |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2552         else
2553                 cmd->promiscuous_flags
2554                             &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2555
2556         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2557         cmd->seid = CPU_TO_LE16(seid);
2558         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2559
2560         return status;
2561 }
2562
2563 /**
2564  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2565  * @hw: pointer to the hw struct
2566  * @seid: vsi number
2567  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2568  * @cmd_details: pointer to command details structure or NULL
2569  **/
2570 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2571                                 u16 seid, bool enable,
2572                                 struct i40e_asq_cmd_details *cmd_details)
2573 {
2574         struct i40e_aq_desc desc;
2575         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2576                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2577         enum i40e_status_code status;
2578         u16 flags = 0;
2579
2580         i40e_fill_default_direct_cmd_desc(&desc,
2581                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2582         if (enable)
2583                 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2584
2585         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2586         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2587         cmd->seid = CPU_TO_LE16(seid);
2588
2589         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2590
2591         return status;
2592 }
2593
2594 /**
2595  * i40e_get_vsi_params - get VSI configuration info
2596  * @hw: pointer to the hw struct
2597  * @vsi_ctx: pointer to a vsi context struct
2598  * @cmd_details: pointer to command details structure or NULL
2599  **/
2600 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2601                                 struct i40e_vsi_context *vsi_ctx,
2602                                 struct i40e_asq_cmd_details *cmd_details)
2603 {
2604         struct i40e_aq_desc desc;
2605         struct i40e_aqc_add_get_update_vsi *cmd =
2606                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2607         struct i40e_aqc_add_get_update_vsi_completion *resp =
2608                 (struct i40e_aqc_add_get_update_vsi_completion *)
2609                 &desc.params.raw;
2610         enum i40e_status_code status;
2611
2612         UNREFERENCED_1PARAMETER(cmd_details);
2613         i40e_fill_default_direct_cmd_desc(&desc,
2614                                           i40e_aqc_opc_get_vsi_parameters);
2615
2616         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2617
2618         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2619
2620         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2621                                     sizeof(vsi_ctx->info), NULL);
2622
2623         if (status != I40E_SUCCESS)
2624                 goto aq_get_vsi_params_exit;
2625
2626         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2627         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2628         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2629         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2630
2631 aq_get_vsi_params_exit:
2632         return status;
2633 }
2634
2635 /**
2636  * i40e_aq_update_vsi_params
2637  * @hw: pointer to the hw struct
2638  * @vsi_ctx: pointer to a vsi context struct
2639  * @cmd_details: pointer to command details structure or NULL
2640  *
2641  * Update a VSI context.
2642  **/
2643 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2644                                 struct i40e_vsi_context *vsi_ctx,
2645                                 struct i40e_asq_cmd_details *cmd_details)
2646 {
2647         struct i40e_aq_desc desc;
2648         struct i40e_aqc_add_get_update_vsi *cmd =
2649                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2650         struct i40e_aqc_add_get_update_vsi_completion *resp =
2651                 (struct i40e_aqc_add_get_update_vsi_completion *)
2652                 &desc.params.raw;
2653         enum i40e_status_code status;
2654
2655         i40e_fill_default_direct_cmd_desc(&desc,
2656                                           i40e_aqc_opc_update_vsi_parameters);
2657         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2658
2659         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2660
2661         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2662                                     sizeof(vsi_ctx->info), cmd_details);
2663
2664         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2665         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2666
2667         return status;
2668 }
2669
2670 /**
2671  * i40e_aq_get_switch_config
2672  * @hw: pointer to the hardware structure
2673  * @buf: pointer to the result buffer
2674  * @buf_size: length of input buffer
2675  * @start_seid: seid to start for the report, 0 == beginning
2676  * @cmd_details: pointer to command details structure or NULL
2677  *
2678  * Fill the buf with switch configuration returned from AdminQ command
2679  **/
2680 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2681                                 struct i40e_aqc_get_switch_config_resp *buf,
2682                                 u16 buf_size, u16 *start_seid,
2683                                 struct i40e_asq_cmd_details *cmd_details)
2684 {
2685         struct i40e_aq_desc desc;
2686         struct i40e_aqc_switch_seid *scfg =
2687                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2688         enum i40e_status_code status;
2689
2690         i40e_fill_default_direct_cmd_desc(&desc,
2691                                           i40e_aqc_opc_get_switch_config);
2692         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2693         if (buf_size > I40E_AQ_LARGE_BUF)
2694                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2695         scfg->seid = CPU_TO_LE16(*start_seid);
2696
2697         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2698         *start_seid = LE16_TO_CPU(scfg->seid);
2699
2700         return status;
2701 }
2702
2703 /**
2704  * i40e_aq_set_switch_config
2705  * @hw: pointer to the hardware structure
2706  * @flags: bit flag values to set
2707  * @mode: cloud filter mode
2708  * @valid_flags: which bit flags to set
2709  * @cmd_details: pointer to command details structure or NULL
2710  *
2711  * Set switch configuration bits
2712  **/
2713 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2714                                 u16 flags, u16 valid_flags, u8 mode,
2715                                 struct i40e_asq_cmd_details *cmd_details)
2716 {
2717         struct i40e_aq_desc desc;
2718         struct i40e_aqc_set_switch_config *scfg =
2719                 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2720         enum i40e_status_code status;
2721
2722         i40e_fill_default_direct_cmd_desc(&desc,
2723                                           i40e_aqc_opc_set_switch_config);
2724         scfg->flags = CPU_TO_LE16(flags);
2725         scfg->valid_flags = CPU_TO_LE16(valid_flags);
2726         scfg->mode = mode;
2727         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
2728                 scfg->switch_tag = CPU_TO_LE16(hw->switch_tag);
2729                 scfg->first_tag = CPU_TO_LE16(hw->first_tag);
2730                 scfg->second_tag = CPU_TO_LE16(hw->second_tag);
2731         }
2732         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2733
2734         return status;
2735 }
2736
2737 /**
2738  * i40e_aq_get_firmware_version
2739  * @hw: pointer to the hw struct
2740  * @fw_major_version: firmware major version
2741  * @fw_minor_version: firmware minor version
2742  * @fw_build: firmware build number
2743  * @api_major_version: major queue version
2744  * @api_minor_version: minor queue version
2745  * @cmd_details: pointer to command details structure or NULL
2746  *
2747  * Get the firmware version from the admin queue commands
2748  **/
2749 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2750                                 u16 *fw_major_version, u16 *fw_minor_version,
2751                                 u32 *fw_build,
2752                                 u16 *api_major_version, u16 *api_minor_version,
2753                                 struct i40e_asq_cmd_details *cmd_details)
2754 {
2755         struct i40e_aq_desc desc;
2756         struct i40e_aqc_get_version *resp =
2757                 (struct i40e_aqc_get_version *)&desc.params.raw;
2758         enum i40e_status_code status;
2759
2760         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2761
2762         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2763
2764         if (status == I40E_SUCCESS) {
2765                 if (fw_major_version != NULL)
2766                         *fw_major_version = LE16_TO_CPU(resp->fw_major);
2767                 if (fw_minor_version != NULL)
2768                         *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2769                 if (fw_build != NULL)
2770                         *fw_build = LE32_TO_CPU(resp->fw_build);
2771                 if (api_major_version != NULL)
2772                         *api_major_version = LE16_TO_CPU(resp->api_major);
2773                 if (api_minor_version != NULL)
2774                         *api_minor_version = LE16_TO_CPU(resp->api_minor);
2775
2776                 /* A workaround to fix the API version in SW */
2777                 if (api_major_version && api_minor_version &&
2778                     fw_major_version && fw_minor_version &&
2779                     ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2780                     (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2781                      (*fw_major_version > 4)))
2782                         *api_minor_version = 2;
2783         }
2784
2785         return status;
2786 }
2787
2788 /**
2789  * i40e_aq_send_driver_version
2790  * @hw: pointer to the hw struct
2791  * @dv: driver's major, minor version
2792  * @cmd_details: pointer to command details structure or NULL
2793  *
2794  * Send the driver version to the firmware
2795  **/
2796 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2797                                 struct i40e_driver_version *dv,
2798                                 struct i40e_asq_cmd_details *cmd_details)
2799 {
2800         struct i40e_aq_desc desc;
2801         struct i40e_aqc_driver_version *cmd =
2802                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2803         enum i40e_status_code status;
2804         u16 len;
2805
2806         if (dv == NULL)
2807                 return I40E_ERR_PARAM;
2808
2809         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2810
2811         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2812         cmd->driver_major_ver = dv->major_version;
2813         cmd->driver_minor_ver = dv->minor_version;
2814         cmd->driver_build_ver = dv->build_version;
2815         cmd->driver_subbuild_ver = dv->subbuild_version;
2816
2817         len = 0;
2818         while (len < sizeof(dv->driver_string) &&
2819                (dv->driver_string[len] < 0x80) &&
2820                dv->driver_string[len])
2821                 len++;
2822         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2823                                        len, cmd_details);
2824
2825         return status;
2826 }
2827
2828 /**
2829  * i40e_get_link_status - get status of the HW network link
2830  * @hw: pointer to the hw struct
2831  * @link_up: pointer to bool (true/false = linkup/linkdown)
2832  *
2833  * Variable link_up true if link is up, false if link is down.
2834  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2835  *
2836  * Side effect: LinkStatusEvent reporting becomes enabled
2837  **/
2838 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2839 {
2840         enum i40e_status_code status = I40E_SUCCESS;
2841
2842         if (hw->phy.get_link_info) {
2843                 status = i40e_update_link_info(hw);
2844
2845                 if (status != I40E_SUCCESS)
2846                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2847                                    status);
2848         }
2849
2850         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2851
2852         return status;
2853 }
2854
2855 /**
2856  * i40e_updatelink_status - update status of the HW network link
2857  * @hw: pointer to the hw struct
2858  **/
2859 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2860 {
2861         struct i40e_aq_get_phy_abilities_resp abilities;
2862         enum i40e_status_code status = I40E_SUCCESS;
2863
2864         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2865         if (status)
2866                 return status;
2867
2868         /* extra checking needed to ensure link info to user is timely */
2869         if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2870             ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2871              !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2872                 status = i40e_aq_get_phy_capabilities(hw, false, false,
2873                                                       &abilities, NULL);
2874                 if (status)
2875                         return status;
2876
2877                 hw->phy.link_info.req_fec_info =
2878                         abilities.fec_cfg_curr_mod_ext_info &
2879                         (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS);
2880
2881                 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2882                         sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2883         }
2884         return status;
2885 }
2886
2887
2888 /**
2889  * i40e_get_link_speed
2890  * @hw: pointer to the hw struct
2891  *
2892  * Returns the link speed of the adapter.
2893  **/
2894 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2895 {
2896         enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2897         enum i40e_status_code status = I40E_SUCCESS;
2898
2899         if (hw->phy.get_link_info) {
2900                 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2901
2902                 if (status != I40E_SUCCESS)
2903                         goto i40e_link_speed_exit;
2904         }
2905
2906         speed = hw->phy.link_info.link_speed;
2907
2908 i40e_link_speed_exit:
2909         return speed;
2910 }
2911
2912 /**
2913  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2914  * @hw: pointer to the hw struct
2915  * @uplink_seid: the MAC or other gizmo SEID
2916  * @downlink_seid: the VSI SEID
2917  * @enabled_tc: bitmap of TCs to be enabled
2918  * @default_port: true for default port VSI, false for control port
2919  * @veb_seid: pointer to where to put the resulting VEB SEID
2920  * @enable_stats: true to turn on VEB stats
2921  * @cmd_details: pointer to command details structure or NULL
2922  *
2923  * This asks the FW to add a VEB between the uplink and downlink
2924  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2925  **/
2926 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2927                                 u16 downlink_seid, u8 enabled_tc,
2928                                 bool default_port, u16 *veb_seid,
2929                                 bool enable_stats,
2930                                 struct i40e_asq_cmd_details *cmd_details)
2931 {
2932         struct i40e_aq_desc desc;
2933         struct i40e_aqc_add_veb *cmd =
2934                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2935         struct i40e_aqc_add_veb_completion *resp =
2936                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2937         enum i40e_status_code status;
2938         u16 veb_flags = 0;
2939
2940         /* SEIDs need to either both be set or both be 0 for floating VEB */
2941         if (!!uplink_seid != !!downlink_seid)
2942                 return I40E_ERR_PARAM;
2943
2944         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2945
2946         cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2947         cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2948         cmd->enable_tcs = enabled_tc;
2949         if (!uplink_seid)
2950                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2951         if (default_port)
2952                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2953         else
2954                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2955
2956         /* reverse logic here: set the bitflag to disable the stats */
2957         if (!enable_stats)
2958                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2959
2960         cmd->veb_flags = CPU_TO_LE16(veb_flags);
2961
2962         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2963
2964         if (!status && veb_seid)
2965                 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2966
2967         return status;
2968 }
2969
2970 /**
2971  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2972  * @hw: pointer to the hw struct
2973  * @veb_seid: the SEID of the VEB to query
2974  * @switch_id: the uplink switch id
2975  * @floating: set to true if the VEB is floating
2976  * @statistic_index: index of the stats counter block for this VEB
2977  * @vebs_used: number of VEB's used by function
2978  * @vebs_free: total VEB's not reserved by any function
2979  * @cmd_details: pointer to command details structure or NULL
2980  *
2981  * This retrieves the parameters for a particular VEB, specified by
2982  * uplink_seid, and returns them to the caller.
2983  **/
2984 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2985                                 u16 veb_seid, u16 *switch_id,
2986                                 bool *floating, u16 *statistic_index,
2987                                 u16 *vebs_used, u16 *vebs_free,
2988                                 struct i40e_asq_cmd_details *cmd_details)
2989 {
2990         struct i40e_aq_desc desc;
2991         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2992                 (struct i40e_aqc_get_veb_parameters_completion *)
2993                 &desc.params.raw;
2994         enum i40e_status_code status;
2995
2996         if (veb_seid == 0)
2997                 return I40E_ERR_PARAM;
2998
2999         i40e_fill_default_direct_cmd_desc(&desc,
3000                                           i40e_aqc_opc_get_veb_parameters);
3001         cmd_resp->seid = CPU_TO_LE16(veb_seid);
3002
3003         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3004         if (status)
3005                 goto get_veb_exit;
3006
3007         if (switch_id)
3008                 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
3009         if (statistic_index)
3010                 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
3011         if (vebs_used)
3012                 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
3013         if (vebs_free)
3014                 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
3015         if (floating) {
3016                 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
3017
3018                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
3019                         *floating = true;
3020                 else
3021                         *floating = false;
3022         }
3023
3024 get_veb_exit:
3025         return status;
3026 }
3027
3028 /**
3029  * i40e_aq_add_macvlan
3030  * @hw: pointer to the hw struct
3031  * @seid: VSI for the mac address
3032  * @mv_list: list of macvlans to be added
3033  * @count: length of the list
3034  * @cmd_details: pointer to command details structure or NULL
3035  *
3036  * Add MAC/VLAN addresses to the HW filtering
3037  **/
3038 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
3039                         struct i40e_aqc_add_macvlan_element_data *mv_list,
3040                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3041 {
3042         struct i40e_aq_desc desc;
3043         struct i40e_aqc_macvlan *cmd =
3044                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3045         enum i40e_status_code status;
3046         u16 buf_size;
3047         int i;
3048
3049         if (count == 0 || !mv_list || !hw)
3050                 return I40E_ERR_PARAM;
3051
3052         buf_size = count * sizeof(*mv_list);
3053
3054         /* prep the rest of the request */
3055         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
3056         cmd->num_addresses = CPU_TO_LE16(count);
3057         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3058         cmd->seid[1] = 0;
3059         cmd->seid[2] = 0;
3060
3061         for (i = 0; i < count; i++)
3062                 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
3063                         mv_list[i].flags |=
3064                             CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
3065
3066         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3067         if (buf_size > I40E_AQ_LARGE_BUF)
3068                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3069
3070         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3071                                        cmd_details);
3072
3073         return status;
3074 }
3075
3076 /**
3077  * i40e_aq_remove_macvlan
3078  * @hw: pointer to the hw struct
3079  * @seid: VSI for the mac address
3080  * @mv_list: list of macvlans to be removed
3081  * @count: length of the list
3082  * @cmd_details: pointer to command details structure or NULL
3083  *
3084  * Remove MAC/VLAN addresses from the HW filtering
3085  **/
3086 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
3087                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
3088                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3089 {
3090         struct i40e_aq_desc desc;
3091         struct i40e_aqc_macvlan *cmd =
3092                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3093         enum i40e_status_code status;
3094         u16 buf_size;
3095
3096         if (count == 0 || !mv_list || !hw)
3097                 return I40E_ERR_PARAM;
3098
3099         buf_size = count * sizeof(*mv_list);
3100
3101         /* prep the rest of the request */
3102         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
3103         cmd->num_addresses = CPU_TO_LE16(count);
3104         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3105         cmd->seid[1] = 0;
3106         cmd->seid[2] = 0;
3107
3108         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3109         if (buf_size > I40E_AQ_LARGE_BUF)
3110                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3111
3112         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3113                                        cmd_details);
3114
3115         return status;
3116 }
3117
3118 /**
3119  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3120  * @hw: pointer to the hw struct
3121  * @opcode: AQ opcode for add or delete mirror rule
3122  * @sw_seid: Switch SEID (to which rule refers)
3123  * @rule_type: Rule Type (ingress/egress/VLAN)
3124  * @id: Destination VSI SEID or Rule ID
3125  * @count: length of the list
3126  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3127  * @cmd_details: pointer to command details structure or NULL
3128  * @rule_id: Rule ID returned from FW
3129  * @rules_used: Number of rules used in internal switch
3130  * @rules_free: Number of rules free in internal switch
3131  *
3132  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3133  * VEBs/VEPA elements only
3134  **/
3135 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3136                         u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3137                         u16 count, __le16 *mr_list,
3138                         struct i40e_asq_cmd_details *cmd_details,
3139                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3140 {
3141         struct i40e_aq_desc desc;
3142         struct i40e_aqc_add_delete_mirror_rule *cmd =
3143                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3144         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3145         (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3146         enum i40e_status_code status;
3147         u16 buf_size;
3148
3149         buf_size = count * sizeof(*mr_list);
3150
3151         /* prep the rest of the request */
3152         i40e_fill_default_direct_cmd_desc(&desc, opcode);
3153         cmd->seid = CPU_TO_LE16(sw_seid);
3154         cmd->rule_type = CPU_TO_LE16(rule_type &
3155                                      I40E_AQC_MIRROR_RULE_TYPE_MASK);
3156         cmd->num_entries = CPU_TO_LE16(count);
3157         /* Dest VSI for add, rule_id for delete */
3158         cmd->destination = CPU_TO_LE16(id);
3159         if (mr_list) {
3160                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3161                                                 I40E_AQ_FLAG_RD));
3162                 if (buf_size > I40E_AQ_LARGE_BUF)
3163                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3164         }
3165
3166         status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3167                                        cmd_details);
3168         if (status == I40E_SUCCESS ||
3169             hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3170                 if (rule_id)
3171                         *rule_id = LE16_TO_CPU(resp->rule_id);
3172                 if (rules_used)
3173                         *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3174                 if (rules_free)
3175                         *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3176         }
3177         return status;
3178 }
3179
3180 /**
3181  * i40e_aq_add_mirrorrule - add a mirror rule
3182  * @hw: pointer to the hw struct
3183  * @sw_seid: Switch SEID (to which rule refers)
3184  * @rule_type: Rule Type (ingress/egress/VLAN)
3185  * @dest_vsi: SEID of VSI to which packets will be mirrored
3186  * @count: length of the list
3187  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3188  * @cmd_details: pointer to command details structure or NULL
3189  * @rule_id: Rule ID returned from FW
3190  * @rules_used: Number of rules used in internal switch
3191  * @rules_free: Number of rules free in internal switch
3192  *
3193  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3194  **/
3195 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3196                         u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3197                         struct i40e_asq_cmd_details *cmd_details,
3198                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3199 {
3200         if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3201             rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3202                 if (count == 0 || !mr_list)
3203                         return I40E_ERR_PARAM;
3204         }
3205
3206         return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3207                                   rule_type, dest_vsi, count, mr_list,
3208                                   cmd_details, rule_id, rules_used, rules_free);
3209 }
3210
3211 /**
3212  * i40e_aq_delete_mirrorrule - delete a mirror rule
3213  * @hw: pointer to the hw struct
3214  * @sw_seid: Switch SEID (to which rule refers)
3215  * @rule_type: Rule Type (ingress/egress/VLAN)
3216  * @count: length of the list
3217  * @rule_id: Rule ID that is returned in the receive desc as part of
3218  *              add_mirrorrule.
3219  * @mr_list: list of mirrored VLAN IDs to be removed
3220  * @cmd_details: pointer to command details structure or NULL
3221  * @rules_used: Number of rules used in internal switch
3222  * @rules_free: Number of rules free in internal switch
3223  *
3224  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3225  **/
3226 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3227                         u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3228                         struct i40e_asq_cmd_details *cmd_details,
3229                         u16 *rules_used, u16 *rules_free)
3230 {
3231         /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3232         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3233                 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3234                  * mirroring. For other rule_type, count and rule_type should
3235                  * not matter.
3236                  */
3237                 if (count == 0 || !mr_list)
3238                         return I40E_ERR_PARAM;
3239         }
3240
3241         return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3242                                   rule_type, rule_id, count, mr_list,
3243                                   cmd_details, NULL, rules_used, rules_free);
3244 }
3245
3246 /**
3247  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3248  * @hw: pointer to the hw struct
3249  * @seid: VSI for the vlan filters
3250  * @v_list: list of vlan filters to be added
3251  * @count: length of the list
3252  * @cmd_details: pointer to command details structure or NULL
3253  **/
3254 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3255                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3256                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3257 {
3258         struct i40e_aq_desc desc;
3259         struct i40e_aqc_macvlan *cmd =
3260                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3261         enum i40e_status_code status;
3262         u16 buf_size;
3263
3264         if (count == 0 || !v_list || !hw)
3265                 return I40E_ERR_PARAM;
3266
3267         buf_size = count * sizeof(*v_list);
3268
3269         /* prep the rest of the request */
3270         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3271         cmd->num_addresses = CPU_TO_LE16(count);
3272         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3273         cmd->seid[1] = 0;
3274         cmd->seid[2] = 0;
3275
3276         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3277         if (buf_size > I40E_AQ_LARGE_BUF)
3278                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3279
3280         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3281                                        cmd_details);
3282
3283         return status;
3284 }
3285
3286 /**
3287  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3288  * @hw: pointer to the hw struct
3289  * @seid: VSI for the vlan filters
3290  * @v_list: list of macvlans to be removed
3291  * @count: length of the list
3292  * @cmd_details: pointer to command details structure or NULL
3293  **/
3294 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3295                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3296                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3297 {
3298         struct i40e_aq_desc desc;
3299         struct i40e_aqc_macvlan *cmd =
3300                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3301         enum i40e_status_code status;
3302         u16 buf_size;
3303
3304         if (count == 0 || !v_list || !hw)
3305                 return I40E_ERR_PARAM;
3306
3307         buf_size = count * sizeof(*v_list);
3308
3309         /* prep the rest of the request */
3310         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3311         cmd->num_addresses = CPU_TO_LE16(count);
3312         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3313         cmd->seid[1] = 0;
3314         cmd->seid[2] = 0;
3315
3316         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3317         if (buf_size > I40E_AQ_LARGE_BUF)
3318                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3319
3320         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3321                                        cmd_details);
3322
3323         return status;
3324 }
3325
3326 /**
3327  * i40e_aq_send_msg_to_vf
3328  * @hw: pointer to the hardware structure
3329  * @vfid: vf id to send msg
3330  * @v_opcode: opcodes for VF-PF communication
3331  * @v_retval: return error code
3332  * @msg: pointer to the msg buffer
3333  * @msglen: msg length
3334  * @cmd_details: pointer to command details
3335  *
3336  * send msg to vf
3337  **/
3338 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3339                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3340                                 struct i40e_asq_cmd_details *cmd_details)
3341 {
3342         struct i40e_aq_desc desc;
3343         struct i40e_aqc_pf_vf_message *cmd =
3344                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3345         enum i40e_status_code status;
3346
3347         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3348         cmd->id = CPU_TO_LE32(vfid);
3349         desc.cookie_high = CPU_TO_LE32(v_opcode);
3350         desc.cookie_low = CPU_TO_LE32(v_retval);
3351         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3352         if (msglen) {
3353                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3354                                                 I40E_AQ_FLAG_RD));
3355                 if (msglen > I40E_AQ_LARGE_BUF)
3356                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3357                 desc.datalen = CPU_TO_LE16(msglen);
3358         }
3359         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3360
3361         return status;
3362 }
3363
3364 /**
3365  * i40e_aq_debug_read_register
3366  * @hw: pointer to the hw struct
3367  * @reg_addr: register address
3368  * @reg_val: register value
3369  * @cmd_details: pointer to command details structure or NULL
3370  *
3371  * Read the register using the admin queue commands
3372  **/
3373 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3374                                 u32 reg_addr, u64 *reg_val,
3375                                 struct i40e_asq_cmd_details *cmd_details)
3376 {
3377         struct i40e_aq_desc desc;
3378         struct i40e_aqc_debug_reg_read_write *cmd_resp =
3379                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3380         enum i40e_status_code status;
3381
3382         if (reg_val == NULL)
3383                 return I40E_ERR_PARAM;
3384
3385         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3386
3387         cmd_resp->address = CPU_TO_LE32(reg_addr);
3388
3389         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3390
3391         if (status == I40E_SUCCESS) {
3392                 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3393                            (u64)LE32_TO_CPU(cmd_resp->value_low);
3394         }
3395
3396         return status;
3397 }
3398
3399 /**
3400  * i40e_aq_debug_write_register
3401  * @hw: pointer to the hw struct
3402  * @reg_addr: register address
3403  * @reg_val: register value
3404  * @cmd_details: pointer to command details structure or NULL
3405  *
3406  * Write to a register using the admin queue commands
3407  **/
3408 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3409                                 u32 reg_addr, u64 reg_val,
3410                                 struct i40e_asq_cmd_details *cmd_details)
3411 {
3412         struct i40e_aq_desc desc;
3413         struct i40e_aqc_debug_reg_read_write *cmd =
3414                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3415         enum i40e_status_code status;
3416
3417         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3418
3419         cmd->address = CPU_TO_LE32(reg_addr);
3420         cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3421         cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3422
3423         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3424
3425         return status;
3426 }
3427
3428 /**
3429  * i40e_aq_request_resource
3430  * @hw: pointer to the hw struct
3431  * @resource: resource id
3432  * @access: access type
3433  * @sdp_number: resource number
3434  * @timeout: the maximum time in ms that the driver may hold the resource
3435  * @cmd_details: pointer to command details structure or NULL
3436  *
3437  * requests common resource using the admin queue commands
3438  **/
3439 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3440                                 enum i40e_aq_resources_ids resource,
3441                                 enum i40e_aq_resource_access_type access,
3442                                 u8 sdp_number, u64 *timeout,
3443                                 struct i40e_asq_cmd_details *cmd_details)
3444 {
3445         struct i40e_aq_desc desc;
3446         struct i40e_aqc_request_resource *cmd_resp =
3447                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3448         enum i40e_status_code status;
3449
3450         DEBUGFUNC("i40e_aq_request_resource");
3451
3452         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3453
3454         cmd_resp->resource_id = CPU_TO_LE16(resource);
3455         cmd_resp->access_type = CPU_TO_LE16(access);
3456         cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3457
3458         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3459         /* The completion specifies the maximum time in ms that the driver
3460          * may hold the resource in the Timeout field.
3461          * If the resource is held by someone else, the command completes with
3462          * busy return value and the timeout field indicates the maximum time
3463          * the current owner of the resource has to free it.
3464          */
3465         if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3466                 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3467
3468         return status;
3469 }
3470
3471 /**
3472  * i40e_aq_release_resource
3473  * @hw: pointer to the hw struct
3474  * @resource: resource id
3475  * @sdp_number: resource number
3476  * @cmd_details: pointer to command details structure or NULL
3477  *
3478  * release common resource using the admin queue commands
3479  **/
3480 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3481                                 enum i40e_aq_resources_ids resource,
3482                                 u8 sdp_number,
3483                                 struct i40e_asq_cmd_details *cmd_details)
3484 {
3485         struct i40e_aq_desc desc;
3486         struct i40e_aqc_request_resource *cmd =
3487                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3488         enum i40e_status_code status;
3489
3490         DEBUGFUNC("i40e_aq_release_resource");
3491
3492         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3493
3494         cmd->resource_id = CPU_TO_LE16(resource);
3495         cmd->resource_number = CPU_TO_LE32(sdp_number);
3496
3497         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3498
3499         return status;
3500 }
3501
3502 /**
3503  * i40e_aq_read_nvm
3504  * @hw: pointer to the hw struct
3505  * @module_pointer: module pointer location in words from the NVM beginning
3506  * @offset: byte offset from the module beginning
3507  * @length: length of the section to be read (in bytes from the offset)
3508  * @data: command buffer (size [bytes] = length)
3509  * @last_command: tells if this is the last command in a series
3510  * @cmd_details: pointer to command details structure or NULL
3511  *
3512  * Read the NVM using the admin queue commands
3513  **/
3514 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3515                                 u32 offset, u16 length, void *data,
3516                                 bool last_command,
3517                                 struct i40e_asq_cmd_details *cmd_details)
3518 {
3519         struct i40e_aq_desc desc;
3520         struct i40e_aqc_nvm_update *cmd =
3521                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3522         enum i40e_status_code status;
3523
3524         DEBUGFUNC("i40e_aq_read_nvm");
3525
3526         /* In offset the highest byte must be zeroed. */
3527         if (offset & 0xFF000000) {
3528                 status = I40E_ERR_PARAM;
3529                 goto i40e_aq_read_nvm_exit;
3530         }
3531
3532         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3533
3534         /* If this is the last command in a series, set the proper flag. */
3535         if (last_command)
3536                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3537         cmd->module_pointer = module_pointer;
3538         cmd->offset = CPU_TO_LE32(offset);
3539         cmd->length = CPU_TO_LE16(length);
3540
3541         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3542         if (length > I40E_AQ_LARGE_BUF)
3543                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3544
3545         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3546
3547 i40e_aq_read_nvm_exit:
3548         return status;
3549 }
3550
3551 /**
3552  * i40e_aq_read_nvm_config - read an nvm config block
3553  * @hw: pointer to the hw struct
3554  * @cmd_flags: NVM access admin command bits
3555  * @field_id: field or feature id
3556  * @data: buffer for result
3557  * @buf_size: buffer size
3558  * @element_count: pointer to count of elements read by FW
3559  * @cmd_details: pointer to command details structure or NULL
3560  **/
3561 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3562                                 u8 cmd_flags, u32 field_id, void *data,
3563                                 u16 buf_size, u16 *element_count,
3564                                 struct i40e_asq_cmd_details *cmd_details)
3565 {
3566         struct i40e_aq_desc desc;
3567         struct i40e_aqc_nvm_config_read *cmd =
3568                 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3569         enum i40e_status_code status;
3570
3571         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3572         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3573         if (buf_size > I40E_AQ_LARGE_BUF)
3574                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3575
3576         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3577         cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3578         if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3579                 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3580         else
3581                 cmd->element_id_msw = 0;
3582
3583         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3584
3585         if (!status && element_count)
3586                 *element_count = LE16_TO_CPU(cmd->element_count);
3587
3588         return status;
3589 }
3590
3591 /**
3592  * i40e_aq_write_nvm_config - write an nvm config block
3593  * @hw: pointer to the hw struct
3594  * @cmd_flags: NVM access admin command bits
3595  * @data: buffer for result
3596  * @buf_size: buffer size
3597  * @element_count: count of elements to be written
3598  * @cmd_details: pointer to command details structure or NULL
3599  **/
3600 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3601                                 u8 cmd_flags, void *data, u16 buf_size,
3602                                 u16 element_count,
3603                                 struct i40e_asq_cmd_details *cmd_details)
3604 {
3605         struct i40e_aq_desc desc;
3606         struct i40e_aqc_nvm_config_write *cmd =
3607                 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3608         enum i40e_status_code status;
3609
3610         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3611         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3612         if (buf_size > I40E_AQ_LARGE_BUF)
3613                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3614
3615         cmd->element_count = CPU_TO_LE16(element_count);
3616         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3617         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3618
3619         return status;
3620 }
3621
3622 /**
3623  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3624  * @hw: pointer to the hw struct
3625  * @buff: buffer for result
3626  * @buff_size: buffer size
3627  * @cmd_details: pointer to command details structure or NULL
3628  **/
3629 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3630                                 void *buff, u16 buff_size,
3631                                 struct i40e_asq_cmd_details *cmd_details)
3632 {
3633         struct i40e_aq_desc desc;
3634         enum i40e_status_code status;
3635
3636         UNREFERENCED_2PARAMETER(buff, buff_size);
3637
3638         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3639         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3640         if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3641                 status = I40E_ERR_NOT_IMPLEMENTED;
3642
3643         return status;
3644 }
3645
3646 /**
3647  * i40e_aq_erase_nvm
3648  * @hw: pointer to the hw struct
3649  * @module_pointer: module pointer location in words from the NVM beginning
3650  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3651  * @length: length of the section to be erased (expressed in 4 KB)
3652  * @last_command: tells if this is the last command in a series
3653  * @cmd_details: pointer to command details structure or NULL
3654  *
3655  * Erase the NVM sector using the admin queue commands
3656  **/
3657 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3658                                 u32 offset, u16 length, bool last_command,
3659                                 struct i40e_asq_cmd_details *cmd_details)
3660 {
3661         struct i40e_aq_desc desc;
3662         struct i40e_aqc_nvm_update *cmd =
3663                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3664         enum i40e_status_code status;
3665
3666         DEBUGFUNC("i40e_aq_erase_nvm");
3667
3668         /* In offset the highest byte must be zeroed. */
3669         if (offset & 0xFF000000) {
3670                 status = I40E_ERR_PARAM;
3671                 goto i40e_aq_erase_nvm_exit;
3672         }
3673
3674         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3675
3676         /* If this is the last command in a series, set the proper flag. */
3677         if (last_command)
3678                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3679         cmd->module_pointer = module_pointer;
3680         cmd->offset = CPU_TO_LE32(offset);
3681         cmd->length = CPU_TO_LE16(length);
3682
3683         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3684
3685 i40e_aq_erase_nvm_exit:
3686         return status;
3687 }
3688
3689 /**
3690  * i40e_parse_discover_capabilities
3691  * @hw: pointer to the hw struct
3692  * @buff: pointer to a buffer containing device/function capability records
3693  * @cap_count: number of capability records in the list
3694  * @list_type_opc: type of capabilities list to parse
3695  *
3696  * Parse the device/function capabilities list.
3697  **/
3698 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3699                                      u32 cap_count,
3700                                      enum i40e_admin_queue_opc list_type_opc)
3701 {
3702         struct i40e_aqc_list_capabilities_element_resp *cap;
3703         u32 valid_functions, num_functions;
3704         u32 number, logical_id, phys_id;
3705         struct i40e_hw_capabilities *p;
3706         enum i40e_status_code status;
3707         u16 id, ocp_cfg_word0;
3708         u8 major_rev;
3709         u32 i = 0;
3710
3711         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3712
3713         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3714                 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3715         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3716                 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3717         else
3718                 return;
3719
3720         for (i = 0; i < cap_count; i++, cap++) {
3721                 id = LE16_TO_CPU(cap->id);
3722                 number = LE32_TO_CPU(cap->number);
3723                 logical_id = LE32_TO_CPU(cap->logical_id);
3724                 phys_id = LE32_TO_CPU(cap->phys_id);
3725                 major_rev = cap->major_rev;
3726
3727                 switch (id) {
3728                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3729                         p->switch_mode = number;
3730                         i40e_debug(hw, I40E_DEBUG_INIT,
3731                                    "HW Capability: Switch mode = %d\n",
3732                                    p->switch_mode);
3733                         break;
3734                 case I40E_AQ_CAP_ID_MNG_MODE:
3735                         p->management_mode = number;
3736                         if (major_rev > 1) {
3737                                 p->mng_protocols_over_mctp = logical_id;
3738                                 i40e_debug(hw, I40E_DEBUG_INIT,
3739                                            "HW Capability: Protocols over MCTP = %d\n",
3740                                            p->mng_protocols_over_mctp);
3741                         } else {
3742                                 p->mng_protocols_over_mctp = 0;
3743                         }
3744                         i40e_debug(hw, I40E_DEBUG_INIT,
3745                                    "HW Capability: Management Mode = %d\n",
3746                                    p->management_mode);
3747                         break;
3748                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3749                         p->npar_enable = number;
3750                         i40e_debug(hw, I40E_DEBUG_INIT,
3751                                    "HW Capability: NPAR enable = %d\n",
3752                                    p->npar_enable);
3753                         break;
3754                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3755                         p->os2bmc = number;
3756                         i40e_debug(hw, I40E_DEBUG_INIT,
3757                                    "HW Capability: OS2BMC = %d\n", p->os2bmc);
3758                         break;
3759                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3760                         p->valid_functions = number;
3761                         i40e_debug(hw, I40E_DEBUG_INIT,
3762                                    "HW Capability: Valid Functions = %d\n",
3763                                    p->valid_functions);
3764                         break;
3765                 case I40E_AQ_CAP_ID_SRIOV:
3766                         if (number == 1)
3767                                 p->sr_iov_1_1 = true;
3768                         i40e_debug(hw, I40E_DEBUG_INIT,
3769                                    "HW Capability: SR-IOV = %d\n",
3770                                    p->sr_iov_1_1);
3771                         break;
3772                 case I40E_AQ_CAP_ID_VF:
3773                         p->num_vfs = number;
3774                         p->vf_base_id = logical_id;
3775                         i40e_debug(hw, I40E_DEBUG_INIT,
3776                                    "HW Capability: VF count = %d\n",
3777                                    p->num_vfs);
3778                         i40e_debug(hw, I40E_DEBUG_INIT,
3779                                    "HW Capability: VF base_id = %d\n",
3780                                    p->vf_base_id);
3781                         break;
3782                 case I40E_AQ_CAP_ID_VMDQ:
3783                         if (number == 1)
3784                                 p->vmdq = true;
3785                         i40e_debug(hw, I40E_DEBUG_INIT,
3786                                    "HW Capability: VMDQ = %d\n", p->vmdq);
3787                         break;
3788                 case I40E_AQ_CAP_ID_8021QBG:
3789                         if (number == 1)
3790                                 p->evb_802_1_qbg = true;
3791                         i40e_debug(hw, I40E_DEBUG_INIT,
3792                                    "HW Capability: 802.1Qbg = %d\n", number);
3793                         break;
3794                 case I40E_AQ_CAP_ID_8021QBR:
3795                         if (number == 1)
3796                                 p->evb_802_1_qbh = true;
3797                         i40e_debug(hw, I40E_DEBUG_INIT,
3798                                    "HW Capability: 802.1Qbh = %d\n", number);
3799                         break;
3800                 case I40E_AQ_CAP_ID_VSI:
3801                         p->num_vsis = number;
3802                         i40e_debug(hw, I40E_DEBUG_INIT,
3803                                    "HW Capability: VSI count = %d\n",
3804                                    p->num_vsis);
3805                         break;
3806                 case I40E_AQ_CAP_ID_DCB:
3807                         if (number == 1) {
3808                                 p->dcb = true;
3809                                 p->enabled_tcmap = logical_id;
3810                                 p->maxtc = phys_id;
3811                         }
3812                         i40e_debug(hw, I40E_DEBUG_INIT,
3813                                    "HW Capability: DCB = %d\n", p->dcb);
3814                         i40e_debug(hw, I40E_DEBUG_INIT,
3815                                    "HW Capability: TC Mapping = %d\n",
3816                                    logical_id);
3817                         i40e_debug(hw, I40E_DEBUG_INIT,
3818                                    "HW Capability: TC Max = %d\n", p->maxtc);
3819                         break;
3820                 case I40E_AQ_CAP_ID_FCOE:
3821                         if (number == 1)
3822                                 p->fcoe = true;
3823                         i40e_debug(hw, I40E_DEBUG_INIT,
3824                                    "HW Capability: FCOE = %d\n", p->fcoe);
3825                         break;
3826                 case I40E_AQ_CAP_ID_ISCSI:
3827                         if (number == 1)
3828                                 p->iscsi = true;
3829                         i40e_debug(hw, I40E_DEBUG_INIT,
3830                                    "HW Capability: iSCSI = %d\n", p->iscsi);
3831                         break;
3832                 case I40E_AQ_CAP_ID_RSS:
3833                         p->rss = true;
3834                         p->rss_table_size = number;
3835                         p->rss_table_entry_width = logical_id;
3836                         i40e_debug(hw, I40E_DEBUG_INIT,
3837                                    "HW Capability: RSS = %d\n", p->rss);
3838                         i40e_debug(hw, I40E_DEBUG_INIT,
3839                                    "HW Capability: RSS table size = %d\n",
3840                                    p->rss_table_size);
3841                         i40e_debug(hw, I40E_DEBUG_INIT,
3842                                    "HW Capability: RSS table width = %d\n",
3843                                    p->rss_table_entry_width);
3844                         break;
3845                 case I40E_AQ_CAP_ID_RXQ:
3846                         p->num_rx_qp = number;
3847                         p->base_queue = phys_id;
3848                         i40e_debug(hw, I40E_DEBUG_INIT,
3849                                    "HW Capability: Rx QP = %d\n", number);
3850                         i40e_debug(hw, I40E_DEBUG_INIT,
3851                                    "HW Capability: base_queue = %d\n",
3852                                    p->base_queue);
3853                         break;
3854                 case I40E_AQ_CAP_ID_TXQ:
3855                         p->num_tx_qp = number;
3856                         p->base_queue = phys_id;
3857                         i40e_debug(hw, I40E_DEBUG_INIT,
3858                                    "HW Capability: Tx QP = %d\n", number);
3859                         i40e_debug(hw, I40E_DEBUG_INIT,
3860                                    "HW Capability: base_queue = %d\n",
3861                                    p->base_queue);
3862                         break;
3863                 case I40E_AQ_CAP_ID_MSIX:
3864                         p->num_msix_vectors = number;
3865                         i40e_debug(hw, I40E_DEBUG_INIT,
3866                                    "HW Capability: MSIX vector count = %d\n",
3867                                    p->num_msix_vectors);
3868                         break;
3869                 case I40E_AQ_CAP_ID_VF_MSIX:
3870                         p->num_msix_vectors_vf = number;
3871                         i40e_debug(hw, I40E_DEBUG_INIT,
3872                                    "HW Capability: MSIX VF vector count = %d\n",
3873                                    p->num_msix_vectors_vf);
3874                         break;
3875                 case I40E_AQ_CAP_ID_FLEX10:
3876                         if (major_rev == 1) {
3877                                 if (number == 1) {
3878                                         p->flex10_enable = true;
3879                                         p->flex10_capable = true;
3880                                 }
3881                         } else {
3882                                 /* Capability revision >= 2 */
3883                                 if (number & 1)
3884                                         p->flex10_enable = true;
3885                                 if (number & 2)
3886                                         p->flex10_capable = true;
3887                         }
3888                         p->flex10_mode = logical_id;
3889                         p->flex10_status = phys_id;
3890                         i40e_debug(hw, I40E_DEBUG_INIT,
3891                                    "HW Capability: Flex10 mode = %d\n",
3892                                    p->flex10_mode);
3893                         i40e_debug(hw, I40E_DEBUG_INIT,
3894                                    "HW Capability: Flex10 status = %d\n",
3895                                    p->flex10_status);
3896                         break;
3897                 case I40E_AQ_CAP_ID_CEM:
3898                         if (number == 1)
3899                                 p->mgmt_cem = true;
3900                         i40e_debug(hw, I40E_DEBUG_INIT,
3901                                    "HW Capability: CEM = %d\n", p->mgmt_cem);
3902                         break;
3903                 case I40E_AQ_CAP_ID_IWARP:
3904                         if (number == 1)
3905                                 p->iwarp = true;
3906                         i40e_debug(hw, I40E_DEBUG_INIT,
3907                                    "HW Capability: iWARP = %d\n", p->iwarp);
3908                         break;
3909                 case I40E_AQ_CAP_ID_LED:
3910                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3911                                 p->led[phys_id] = true;
3912                         i40e_debug(hw, I40E_DEBUG_INIT,
3913                                    "HW Capability: LED - PIN %d\n", phys_id);
3914                         break;
3915                 case I40E_AQ_CAP_ID_SDP:
3916                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3917                                 p->sdp[phys_id] = true;
3918                         i40e_debug(hw, I40E_DEBUG_INIT,
3919                                    "HW Capability: SDP - PIN %d\n", phys_id);
3920                         break;
3921                 case I40E_AQ_CAP_ID_MDIO:
3922                         if (number == 1) {
3923                                 p->mdio_port_num = phys_id;
3924                                 p->mdio_port_mode = logical_id;
3925                         }
3926                         i40e_debug(hw, I40E_DEBUG_INIT,
3927                                    "HW Capability: MDIO port number = %d\n",
3928                                    p->mdio_port_num);
3929                         i40e_debug(hw, I40E_DEBUG_INIT,
3930                                    "HW Capability: MDIO port mode = %d\n",
3931                                    p->mdio_port_mode);
3932                         break;
3933                 case I40E_AQ_CAP_ID_1588:
3934                         if (number == 1)
3935                                 p->ieee_1588 = true;
3936                         i40e_debug(hw, I40E_DEBUG_INIT,
3937                                    "HW Capability: IEEE 1588 = %d\n",
3938                                    p->ieee_1588);
3939                         break;
3940                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3941                         p->fd = true;
3942                         p->fd_filters_guaranteed = number;
3943                         p->fd_filters_best_effort = logical_id;
3944                         i40e_debug(hw, I40E_DEBUG_INIT,
3945                                    "HW Capability: Flow Director = 1\n");
3946                         i40e_debug(hw, I40E_DEBUG_INIT,
3947                                    "HW Capability: Guaranteed FD filters = %d\n",
3948                                    p->fd_filters_guaranteed);
3949                         break;
3950                 case I40E_AQ_CAP_ID_WSR_PROT:
3951                         p->wr_csr_prot = (u64)number;
3952                         p->wr_csr_prot |= (u64)logical_id << 32;
3953                         i40e_debug(hw, I40E_DEBUG_INIT,
3954                                    "HW Capability: wr_csr_prot = 0x%llX\n\n",
3955                                    (p->wr_csr_prot & 0xffff));
3956                         break;
3957                 case I40E_AQ_CAP_ID_NVM_MGMT:
3958                         if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3959                                 p->sec_rev_disabled = true;
3960                         if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3961                                 p->update_disabled = true;
3962                         break;
3963                 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3964                         hw->num_wol_proxy_filters = (u16)number;
3965                         hw->wol_proxy_vsi_seid = (u16)logical_id;
3966                         p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3967                         if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3968                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3969                         else
3970                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3971                         p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3972                         i40e_debug(hw, I40E_DEBUG_INIT,
3973                                    "HW Capability: WOL proxy filters = %d\n",
3974                                    hw->num_wol_proxy_filters);
3975                         break;
3976                 default:
3977                         break;
3978                 }
3979         }
3980
3981         if (p->fcoe)
3982                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3983
3984         /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3985         p->fcoe = false;
3986
3987         /* count the enabled ports (aka the "not disabled" ports) */
3988         hw->num_ports = 0;
3989         for (i = 0; i < 4; i++) {
3990                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3991                 u64 port_cfg = 0;
3992
3993                 /* use AQ read to get the physical register offset instead
3994                  * of the port relative offset
3995                  */
3996                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3997                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3998                         hw->num_ports++;
3999         }
4000
4001         /* OCP cards case: if a mezz is removed the ethernet port is at
4002          * disabled state in PRTGEN_CNF register. Additional NVM read is
4003          * needed in order to check if we are dealing with OCP card.
4004          * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting
4005          * physical ports results in wrong partition id calculation and thus
4006          * not supporting WoL.
4007          */
4008         if (hw->mac.type == I40E_MAC_X722) {
4009                 if (i40e_acquire_nvm(hw, I40E_RESOURCE_READ) == I40E_SUCCESS) {
4010                         status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR,
4011                                                   2 * I40E_SR_OCP_CFG_WORD0,
4012                                                   sizeof(ocp_cfg_word0),
4013                                                   &ocp_cfg_word0, true, NULL);
4014                         if (status == I40E_SUCCESS &&
4015                             (ocp_cfg_word0 & I40E_SR_OCP_ENABLED))
4016                                 hw->num_ports = 4;
4017                         i40e_release_nvm(hw);
4018                 }
4019         }
4020
4021         valid_functions = p->valid_functions;
4022         num_functions = 0;
4023         while (valid_functions) {
4024                 if (valid_functions & 1)
4025                         num_functions++;
4026                 valid_functions >>= 1;
4027         }
4028
4029         /* partition id is 1-based, and functions are evenly spread
4030          * across the ports as partitions
4031          */
4032         if (hw->num_ports != 0) {
4033                 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
4034                 hw->num_partitions = num_functions / hw->num_ports;
4035         }
4036
4037         /* additional HW specific goodies that might
4038          * someday be HW version specific
4039          */
4040         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
4041 }
4042
4043 /**
4044  * i40e_aq_discover_capabilities
4045  * @hw: pointer to the hw struct
4046  * @buff: a virtual buffer to hold the capabilities
4047  * @buff_size: Size of the virtual buffer
4048  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
4049  * @list_type_opc: capabilities type to discover - pass in the command opcode
4050  * @cmd_details: pointer to command details structure or NULL
4051  *
4052  * Get the device capabilities descriptions from the firmware
4053  **/
4054 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
4055                                 void *buff, u16 buff_size, u16 *data_size,
4056                                 enum i40e_admin_queue_opc list_type_opc,
4057                                 struct i40e_asq_cmd_details *cmd_details)
4058 {
4059         struct i40e_aqc_list_capabilites *cmd;
4060         struct i40e_aq_desc desc;
4061         enum i40e_status_code status = I40E_SUCCESS;
4062
4063         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
4064
4065         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
4066                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
4067                 status = I40E_ERR_PARAM;
4068                 goto exit;
4069         }
4070
4071         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
4072
4073         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4074         if (buff_size > I40E_AQ_LARGE_BUF)
4075                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4076
4077         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4078         *data_size = LE16_TO_CPU(desc.datalen);
4079
4080         if (status)
4081                 goto exit;
4082
4083         i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
4084                                          list_type_opc);
4085
4086 exit:
4087         return status;
4088 }
4089
4090 /**
4091  * i40e_aq_update_nvm
4092  * @hw: pointer to the hw struct
4093  * @module_pointer: module pointer location in words from the NVM beginning
4094  * @offset: byte offset from the module beginning
4095  * @length: length of the section to be written (in bytes from the offset)
4096  * @data: command buffer (size [bytes] = length)
4097  * @last_command: tells if this is the last command in a series
4098  * @preservation_flags: Preservation mode flags
4099  * @cmd_details: pointer to command details structure or NULL
4100  *
4101  * Update the NVM using the admin queue commands
4102  **/
4103 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
4104                                 u32 offset, u16 length, void *data,
4105                                 bool last_command, u8 preservation_flags,
4106                                 struct i40e_asq_cmd_details *cmd_details)
4107 {
4108         struct i40e_aq_desc desc;
4109         struct i40e_aqc_nvm_update *cmd =
4110                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
4111         enum i40e_status_code status;
4112
4113         DEBUGFUNC("i40e_aq_update_nvm");
4114
4115         /* In offset the highest byte must be zeroed. */
4116         if (offset & 0xFF000000) {
4117                 status = I40E_ERR_PARAM;
4118                 goto i40e_aq_update_nvm_exit;
4119         }
4120
4121         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4122
4123         /* If this is the last command in a series, set the proper flag. */
4124         if (last_command)
4125                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
4126         if (hw->mac.type == I40E_MAC_X722) {
4127                 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED)
4128                         cmd->command_flags |=
4129                                 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED <<
4130                                  I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4131                 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL)
4132                         cmd->command_flags |=
4133                                 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL <<
4134                                  I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4135         }
4136         cmd->module_pointer = module_pointer;
4137         cmd->offset = CPU_TO_LE32(offset);
4138         cmd->length = CPU_TO_LE16(length);
4139
4140         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4141         if (length > I40E_AQ_LARGE_BUF)
4142                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4143
4144         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
4145
4146 i40e_aq_update_nvm_exit:
4147         return status;
4148 }
4149
4150 /**
4151  * i40e_aq_rearrange_nvm
4152  * @hw: pointer to the hw struct
4153  * @rearrange_nvm: defines direction of rearrangement
4154  * @cmd_details: pointer to command details structure or NULL
4155  *
4156  * Rearrange NVM structure, available only for transition FW
4157  **/
4158 enum i40e_status_code i40e_aq_rearrange_nvm(struct i40e_hw *hw,
4159                                 u8 rearrange_nvm,
4160                                 struct i40e_asq_cmd_details *cmd_details)
4161 {
4162         struct i40e_aqc_nvm_update *cmd;
4163         enum i40e_status_code status;
4164         struct i40e_aq_desc desc;
4165
4166         DEBUGFUNC("i40e_aq_rearrange_nvm");
4167
4168         cmd = (struct i40e_aqc_nvm_update *)&desc.params.raw;
4169
4170         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4171
4172         rearrange_nvm &= (I40E_AQ_NVM_REARRANGE_TO_FLAT |
4173                          I40E_AQ_NVM_REARRANGE_TO_STRUCT);
4174
4175         if (!rearrange_nvm) {
4176                 status = I40E_ERR_PARAM;
4177                 goto i40e_aq_rearrange_nvm_exit;
4178         }
4179
4180         cmd->command_flags |= rearrange_nvm;
4181         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4182
4183 i40e_aq_rearrange_nvm_exit:
4184         return status;
4185 }
4186
4187 /**
4188  * i40e_aq_nvm_progress
4189  * @hw: pointer to the hw struct
4190  * @progress: pointer to progress returned from AQ
4191  * @cmd_details: pointer to command details structure or NULL
4192  *
4193  * Gets progress of flash rearrangement process
4194  **/
4195 enum i40e_status_code i40e_aq_nvm_progress(struct i40e_hw *hw, u8 *progress,
4196                                 struct i40e_asq_cmd_details *cmd_details)
4197 {
4198         enum i40e_status_code status;
4199         struct i40e_aq_desc desc;
4200
4201         DEBUGFUNC("i40e_aq_nvm_progress");
4202
4203         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_progress);
4204         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4205         *progress = desc.params.raw[0];
4206         return status;
4207 }
4208
4209 /**
4210  * i40e_aq_get_lldp_mib
4211  * @hw: pointer to the hw struct
4212  * @bridge_type: type of bridge requested
4213  * @mib_type: Local, Remote or both Local and Remote MIBs
4214  * @buff: pointer to a user supplied buffer to store the MIB block
4215  * @buff_size: size of the buffer (in bytes)
4216  * @local_len : length of the returned Local LLDP MIB
4217  * @remote_len: length of the returned Remote LLDP MIB
4218  * @cmd_details: pointer to command details structure or NULL
4219  *
4220  * Requests the complete LLDP MIB (entire packet).
4221  **/
4222 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4223                                 u8 mib_type, void *buff, u16 buff_size,
4224                                 u16 *local_len, u16 *remote_len,
4225                                 struct i40e_asq_cmd_details *cmd_details)
4226 {
4227         struct i40e_aq_desc desc;
4228         struct i40e_aqc_lldp_get_mib *cmd =
4229                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4230         struct i40e_aqc_lldp_get_mib *resp =
4231                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4232         enum i40e_status_code status;
4233
4234         if (buff_size == 0 || !buff)
4235                 return I40E_ERR_PARAM;
4236
4237         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4238         /* Indirect Command */
4239         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4240
4241         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4242         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4243                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4244
4245         desc.datalen = CPU_TO_LE16(buff_size);
4246
4247         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4248         if (buff_size > I40E_AQ_LARGE_BUF)
4249                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4250
4251         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4252         if (!status) {
4253                 if (local_len != NULL)
4254                         *local_len = LE16_TO_CPU(resp->local_len);
4255                 if (remote_len != NULL)
4256                         *remote_len = LE16_TO_CPU(resp->remote_len);
4257         }
4258
4259         return status;
4260 }
4261
4262  /**
4263  * i40e_aq_set_lldp_mib - Set the LLDP MIB
4264  * @hw: pointer to the hw struct
4265  * @mib_type: Local, Remote or both Local and Remote MIBs
4266  * @buff: pointer to a user supplied buffer to store the MIB block
4267  * @buff_size: size of the buffer (in bytes)
4268  * @cmd_details: pointer to command details structure or NULL
4269  *
4270  * Set the LLDP MIB.
4271  **/
4272 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4273                                 u8 mib_type, void *buff, u16 buff_size,
4274                                 struct i40e_asq_cmd_details *cmd_details)
4275 {
4276         struct i40e_aq_desc desc;
4277         struct i40e_aqc_lldp_set_local_mib *cmd =
4278                 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4279         enum i40e_status_code status;
4280
4281         if (buff_size == 0 || !buff)
4282                 return I40E_ERR_PARAM;
4283
4284         i40e_fill_default_direct_cmd_desc(&desc,
4285                                 i40e_aqc_opc_lldp_set_local_mib);
4286         /* Indirect Command */
4287         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4288         if (buff_size > I40E_AQ_LARGE_BUF)
4289                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4290         desc.datalen = CPU_TO_LE16(buff_size);
4291
4292         cmd->type = mib_type;
4293         cmd->length = CPU_TO_LE16(buff_size);
4294         cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4295         cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4296
4297         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4298         return status;
4299 }
4300
4301 /**
4302  * i40e_aq_cfg_lldp_mib_change_event
4303  * @hw: pointer to the hw struct
4304  * @enable_update: Enable or Disable event posting
4305  * @cmd_details: pointer to command details structure or NULL
4306  *
4307  * Enable or Disable posting of an event on ARQ when LLDP MIB
4308  * associated with the interface changes
4309  **/
4310 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4311                                 bool enable_update,
4312                                 struct i40e_asq_cmd_details *cmd_details)
4313 {
4314         struct i40e_aq_desc desc;
4315         struct i40e_aqc_lldp_update_mib *cmd =
4316                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4317         enum i40e_status_code status;
4318
4319         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4320
4321         if (!enable_update)
4322                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4323
4324         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4325
4326         return status;
4327 }
4328
4329 /**
4330  * i40e_aq_add_lldp_tlv
4331  * @hw: pointer to the hw struct
4332  * @bridge_type: type of bridge
4333  * @buff: buffer with TLV to add
4334  * @buff_size: length of the buffer
4335  * @tlv_len: length of the TLV to be added
4336  * @mib_len: length of the LLDP MIB returned in response
4337  * @cmd_details: pointer to command details structure or NULL
4338  *
4339  * Add the specified TLV to LLDP Local MIB for the given bridge type,
4340  * it is responsibility of the caller to make sure that the TLV is not
4341  * already present in the LLDPDU.
4342  * In return firmware will write the complete LLDP MIB with the newly
4343  * added TLV in the response buffer.
4344  **/
4345 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4346                                 void *buff, u16 buff_size, u16 tlv_len,
4347                                 u16 *mib_len,
4348                                 struct i40e_asq_cmd_details *cmd_details)
4349 {
4350         struct i40e_aq_desc desc;
4351         struct i40e_aqc_lldp_add_tlv *cmd =
4352                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4353         enum i40e_status_code status;
4354
4355         if (buff_size == 0 || !buff || tlv_len == 0)
4356                 return I40E_ERR_PARAM;
4357
4358         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4359
4360         /* Indirect Command */
4361         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4362         if (buff_size > I40E_AQ_LARGE_BUF)
4363                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4364         desc.datalen = CPU_TO_LE16(buff_size);
4365
4366         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4367                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4368         cmd->len = CPU_TO_LE16(tlv_len);
4369
4370         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4371         if (!status) {
4372                 if (mib_len != NULL)
4373                         *mib_len = LE16_TO_CPU(desc.datalen);
4374         }
4375
4376         return status;
4377 }
4378
4379 /**
4380  * i40e_aq_update_lldp_tlv
4381  * @hw: pointer to the hw struct
4382  * @bridge_type: type of bridge
4383  * @buff: buffer with TLV to update
4384  * @buff_size: size of the buffer holding original and updated TLVs
4385  * @old_len: Length of the Original TLV
4386  * @new_len: Length of the Updated TLV
4387  * @offset: offset of the updated TLV in the buff
4388  * @mib_len: length of the returned LLDP MIB
4389  * @cmd_details: pointer to command details structure or NULL
4390  *
4391  * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4392  * Firmware will place the complete LLDP MIB in response buffer with the
4393  * updated TLV.
4394  **/
4395 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4396                                 u8 bridge_type, void *buff, u16 buff_size,
4397                                 u16 old_len, u16 new_len, u16 offset,
4398                                 u16 *mib_len,
4399                                 struct i40e_asq_cmd_details *cmd_details)
4400 {
4401         struct i40e_aq_desc desc;
4402         struct i40e_aqc_lldp_update_tlv *cmd =
4403                 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4404         enum i40e_status_code status;
4405
4406         if (buff_size == 0 || !buff || offset == 0 ||
4407             old_len == 0 || new_len == 0)
4408                 return I40E_ERR_PARAM;
4409
4410         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4411
4412         /* Indirect Command */
4413         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4414         if (buff_size > I40E_AQ_LARGE_BUF)
4415                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4416         desc.datalen = CPU_TO_LE16(buff_size);
4417
4418         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4419                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4420         cmd->old_len = CPU_TO_LE16(old_len);
4421         cmd->new_offset = CPU_TO_LE16(offset);
4422         cmd->new_len = CPU_TO_LE16(new_len);
4423
4424         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4425         if (!status) {
4426                 if (mib_len != NULL)
4427                         *mib_len = LE16_TO_CPU(desc.datalen);
4428         }
4429
4430         return status;
4431 }
4432
4433 /**
4434  * i40e_aq_delete_lldp_tlv
4435  * @hw: pointer to the hw struct
4436  * @bridge_type: type of bridge
4437  * @buff: pointer to a user supplied buffer that has the TLV
4438  * @buff_size: length of the buffer
4439  * @tlv_len: length of the TLV to be deleted
4440  * @mib_len: length of the returned LLDP MIB
4441  * @cmd_details: pointer to command details structure or NULL
4442  *
4443  * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4444  * The firmware places the entire LLDP MIB in the response buffer.
4445  **/
4446 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4447                                 u8 bridge_type, void *buff, u16 buff_size,
4448                                 u16 tlv_len, u16 *mib_len,
4449                                 struct i40e_asq_cmd_details *cmd_details)
4450 {
4451         struct i40e_aq_desc desc;
4452         struct i40e_aqc_lldp_add_tlv *cmd =
4453                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4454         enum i40e_status_code status;
4455
4456         if (buff_size == 0 || !buff)
4457                 return I40E_ERR_PARAM;
4458
4459         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4460
4461         /* Indirect Command */
4462         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4463         if (buff_size > I40E_AQ_LARGE_BUF)
4464                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4465         desc.datalen = CPU_TO_LE16(buff_size);
4466         cmd->len = CPU_TO_LE16(tlv_len);
4467         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4468                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4469
4470         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4471         if (!status) {
4472                 if (mib_len != NULL)
4473                         *mib_len = LE16_TO_CPU(desc.datalen);
4474         }
4475
4476         return status;
4477 }
4478
4479 /**
4480  * i40e_aq_stop_lldp
4481  * @hw: pointer to the hw struct
4482  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4483  * @cmd_details: pointer to command details structure or NULL
4484  *
4485  * Stop or Shutdown the embedded LLDP Agent
4486  **/
4487 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4488                                 struct i40e_asq_cmd_details *cmd_details)
4489 {
4490         struct i40e_aq_desc desc;
4491         struct i40e_aqc_lldp_stop *cmd =
4492                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4493         enum i40e_status_code status;
4494
4495         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4496
4497         if (shutdown_agent)
4498                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4499
4500         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4501
4502         return status;
4503 }
4504
4505 /**
4506  * i40e_aq_start_lldp
4507  * @hw: pointer to the hw struct
4508  * @cmd_details: pointer to command details structure or NULL
4509  *
4510  * Start the embedded LLDP Agent on all ports.
4511  **/
4512 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4513                                 struct i40e_asq_cmd_details *cmd_details)
4514 {
4515         struct i40e_aq_desc desc;
4516         struct i40e_aqc_lldp_start *cmd =
4517                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4518         enum i40e_status_code status;
4519
4520         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4521
4522         cmd->command = I40E_AQ_LLDP_AGENT_START;
4523         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4524
4525         return status;
4526 }
4527
4528 /**
4529  * i40e_aq_set_dcb_parameters
4530  * @hw: pointer to the hw struct
4531  * @cmd_details: pointer to command details structure or NULL
4532  * @dcb_enable: True if DCB configuration needs to be applied
4533  *
4534  **/
4535 enum i40e_status_code
4536 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable,
4537                            struct i40e_asq_cmd_details *cmd_details)
4538 {
4539         struct i40e_aq_desc desc;
4540         struct i40e_aqc_set_dcb_parameters *cmd =
4541                 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw;
4542         enum i40e_status_code status;
4543
4544         i40e_fill_default_direct_cmd_desc(&desc,
4545                                           i40e_aqc_opc_set_dcb_parameters);
4546
4547         if (dcb_enable) {
4548                 cmd->valid_flags = I40E_DCB_VALID;
4549                 cmd->command = I40E_AQ_DCB_SET_AGENT;
4550         }
4551         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4552
4553         return status;
4554 }
4555
4556 /**
4557  * i40e_aq_get_cee_dcb_config
4558  * @hw: pointer to the hw struct
4559  * @buff: response buffer that stores CEE operational configuration
4560  * @buff_size: size of the buffer passed
4561  * @cmd_details: pointer to command details structure or NULL
4562  *
4563  * Get CEE DCBX mode operational configuration from firmware
4564  **/
4565 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4566                                 void *buff, u16 buff_size,
4567                                 struct i40e_asq_cmd_details *cmd_details)
4568 {
4569         struct i40e_aq_desc desc;
4570         enum i40e_status_code status;
4571
4572         if (buff_size == 0 || !buff)
4573                 return I40E_ERR_PARAM;
4574
4575         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4576
4577         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4578         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4579                                        cmd_details);
4580
4581         return status;
4582 }
4583
4584 /**
4585  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4586  * @hw: pointer to the hw struct
4587  * @start_agent: True if DCBx Agent needs to be Started
4588  *                              False if DCBx Agent needs to be Stopped
4589  * @cmd_details: pointer to command details structure or NULL
4590  *
4591  * Start/Stop the embedded dcbx Agent
4592  **/
4593 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4594                                 bool start_agent,
4595                                 struct i40e_asq_cmd_details *cmd_details)
4596 {
4597         struct i40e_aq_desc desc;
4598         struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4599                 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4600                                 &desc.params.raw;
4601         enum i40e_status_code status;
4602
4603         i40e_fill_default_direct_cmd_desc(&desc,
4604                                 i40e_aqc_opc_lldp_stop_start_spec_agent);
4605
4606         if (start_agent)
4607                 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4608
4609         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4610
4611         return status;
4612 }
4613
4614 /**
4615  * i40e_aq_add_udp_tunnel
4616  * @hw: pointer to the hw struct
4617  * @udp_port: the UDP port to add in Host byte order
4618  * @protocol_index: protocol index type
4619  * @filter_index: pointer to filter index
4620  * @cmd_details: pointer to command details structure or NULL
4621  *
4622  * Note: Firmware expects the udp_port value to be in Little Endian format,
4623  * and this function will call CPU_TO_LE16 to convert from Host byte order to
4624  * Little Endian order.
4625  **/
4626 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4627                                 u16 udp_port, u8 protocol_index,
4628                                 u8 *filter_index,
4629                                 struct i40e_asq_cmd_details *cmd_details)
4630 {
4631         struct i40e_aq_desc desc;
4632         struct i40e_aqc_add_udp_tunnel *cmd =
4633                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4634         struct i40e_aqc_del_udp_tunnel_completion *resp =
4635                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4636         enum i40e_status_code status;
4637
4638         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4639
4640         cmd->udp_port = CPU_TO_LE16(udp_port);
4641         cmd->protocol_type = protocol_index;
4642
4643         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4644
4645         if (!status && filter_index)
4646                 *filter_index = resp->index;
4647
4648         return status;
4649 }
4650
4651 /**
4652  * i40e_aq_del_udp_tunnel
4653  * @hw: pointer to the hw struct
4654  * @index: filter index
4655  * @cmd_details: pointer to command details structure or NULL
4656  **/
4657 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4658                                 struct i40e_asq_cmd_details *cmd_details)
4659 {
4660         struct i40e_aq_desc desc;
4661         struct i40e_aqc_remove_udp_tunnel *cmd =
4662                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4663         enum i40e_status_code status;
4664
4665         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4666
4667         cmd->index = index;
4668
4669         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4670
4671         return status;
4672 }
4673
4674 /**
4675  * i40e_aq_get_switch_resource_alloc (0x0204)
4676  * @hw: pointer to the hw struct
4677  * @num_entries: pointer to u8 to store the number of resource entries returned
4678  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
4679  *        to store the resource information for all resource types.  Each
4680  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
4681  * @count: size, in bytes, of the buffer provided
4682  * @cmd_details: pointer to command details structure or NULL
4683  *
4684  * Query the resources allocated to a function.
4685  **/
4686 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4687                         u8 *num_entries,
4688                         struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4689                         u16 count,
4690                         struct i40e_asq_cmd_details *cmd_details)
4691 {
4692         struct i40e_aq_desc desc;
4693         struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4694                 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4695         enum i40e_status_code status;
4696         u16 length = count * sizeof(*buf);
4697
4698         i40e_fill_default_direct_cmd_desc(&desc,
4699                                         i40e_aqc_opc_get_switch_resource_alloc);
4700
4701         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4702         if (length > I40E_AQ_LARGE_BUF)
4703                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4704
4705         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4706
4707         if (!status && num_entries)
4708                 *num_entries = cmd_resp->num_entries;
4709
4710         return status;
4711 }
4712
4713 /**
4714  * i40e_aq_delete_element - Delete switch element
4715  * @hw: pointer to the hw struct
4716  * @seid: the SEID to delete from the switch
4717  * @cmd_details: pointer to command details structure or NULL
4718  *
4719  * This deletes a switch element from the switch.
4720  **/
4721 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4722                                 struct i40e_asq_cmd_details *cmd_details)
4723 {
4724         struct i40e_aq_desc desc;
4725         struct i40e_aqc_switch_seid *cmd =
4726                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4727         enum i40e_status_code status;
4728
4729         if (seid == 0)
4730                 return I40E_ERR_PARAM;
4731
4732         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4733
4734         cmd->seid = CPU_TO_LE16(seid);
4735
4736         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4737
4738         return status;
4739 }
4740
4741 /**
4742  * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4743  * @hw: pointer to the hw struct
4744  * @flags: component flags
4745  * @mac_seid: uplink seid (MAC SEID)
4746  * @vsi_seid: connected vsi seid
4747  * @ret_seid: seid of create pv component
4748  *
4749  * This instantiates an i40e port virtualizer with specified flags.
4750  * Depending on specified flags the port virtualizer can act as a
4751  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4752  */
4753 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4754                                        u16 mac_seid, u16 vsi_seid,
4755                                        u16 *ret_seid)
4756 {
4757         struct i40e_aq_desc desc;
4758         struct i40e_aqc_add_update_pv *cmd =
4759                 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4760         struct i40e_aqc_add_update_pv_completion *resp =
4761                 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4762         enum i40e_status_code status;
4763
4764         if (vsi_seid == 0)
4765                 return I40E_ERR_PARAM;
4766
4767         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4768         cmd->command_flags = CPU_TO_LE16(flags);
4769         cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4770         cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4771
4772         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4773         if (!status && ret_seid)
4774                 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4775
4776         return status;
4777 }
4778
4779 /**
4780  * i40e_aq_add_tag - Add an S/E-tag
4781  * @hw: pointer to the hw struct
4782  * @direct_to_queue: should s-tag direct flow to a specific queue
4783  * @vsi_seid: VSI SEID to use this tag
4784  * @tag: value of the tag
4785  * @queue_num: queue number, only valid is direct_to_queue is true
4786  * @tags_used: return value, number of tags in use by this PF
4787  * @tags_free: return value, number of unallocated tags
4788  * @cmd_details: pointer to command details structure or NULL
4789  *
4790  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4791  * the number of tags allocated by the PF, and the number of unallocated
4792  * tags available.
4793  **/
4794 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4795                                 u16 vsi_seid, u16 tag, u16 queue_num,
4796                                 u16 *tags_used, u16 *tags_free,
4797                                 struct i40e_asq_cmd_details *cmd_details)
4798 {
4799         struct i40e_aq_desc desc;
4800         struct i40e_aqc_add_tag *cmd =
4801                 (struct i40e_aqc_add_tag *)&desc.params.raw;
4802         struct i40e_aqc_add_remove_tag_completion *resp =
4803                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4804         enum i40e_status_code status;
4805
4806         if (vsi_seid == 0)
4807                 return I40E_ERR_PARAM;
4808
4809         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4810
4811         cmd->seid = CPU_TO_LE16(vsi_seid);
4812         cmd->tag = CPU_TO_LE16(tag);
4813         if (direct_to_queue) {
4814                 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4815                 cmd->queue_number = CPU_TO_LE16(queue_num);
4816         }
4817
4818         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4819
4820         if (!status) {
4821                 if (tags_used != NULL)
4822                         *tags_used = LE16_TO_CPU(resp->tags_used);
4823                 if (tags_free != NULL)
4824                         *tags_free = LE16_TO_CPU(resp->tags_free);
4825         }
4826
4827         return status;
4828 }
4829
4830 /**
4831  * i40e_aq_remove_tag - Remove an S- or E-tag
4832  * @hw: pointer to the hw struct
4833  * @vsi_seid: VSI SEID this tag is associated with
4834  * @tag: value of the S-tag to delete
4835  * @tags_used: return value, number of tags in use by this PF
4836  * @tags_free: return value, number of unallocated tags
4837  * @cmd_details: pointer to command details structure or NULL
4838  *
4839  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4840  * the number of tags allocated by the PF, and the number of unallocated
4841  * tags available.
4842  **/
4843 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4844                                 u16 tag, u16 *tags_used, u16 *tags_free,
4845                                 struct i40e_asq_cmd_details *cmd_details)
4846 {
4847         struct i40e_aq_desc desc;
4848         struct i40e_aqc_remove_tag *cmd =
4849                 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4850         struct i40e_aqc_add_remove_tag_completion *resp =
4851                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4852         enum i40e_status_code status;
4853
4854         if (vsi_seid == 0)
4855                 return I40E_ERR_PARAM;
4856
4857         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4858
4859         cmd->seid = CPU_TO_LE16(vsi_seid);
4860         cmd->tag = CPU_TO_LE16(tag);
4861
4862         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4863
4864         if (!status) {
4865                 if (tags_used != NULL)
4866                         *tags_used = LE16_TO_CPU(resp->tags_used);
4867                 if (tags_free != NULL)
4868                         *tags_free = LE16_TO_CPU(resp->tags_free);
4869         }
4870
4871         return status;
4872 }
4873
4874 /**
4875  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4876  * @hw: pointer to the hw struct
4877  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4878  * @etag: value of E-tag to add
4879  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4880  * @buf: address of indirect buffer
4881  * @tags_used: return value, number of E-tags in use by this port
4882  * @tags_free: return value, number of unallocated M-tags
4883  * @cmd_details: pointer to command details structure or NULL
4884  *
4885  * This associates a multicast E-tag to a port virtualizer.  It will return
4886  * the number of tags allocated by the PF, and the number of unallocated
4887  * tags available.
4888  *
4889  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4890  * num_tags_in_buf long.
4891  **/
4892 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4893                                 u16 etag, u8 num_tags_in_buf, void *buf,
4894                                 u16 *tags_used, u16 *tags_free,
4895                                 struct i40e_asq_cmd_details *cmd_details)
4896 {
4897         struct i40e_aq_desc desc;
4898         struct i40e_aqc_add_remove_mcast_etag *cmd =
4899                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4900         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4901            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4902         enum i40e_status_code status;
4903         u16 length = sizeof(u16) * num_tags_in_buf;
4904
4905         if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4906                 return I40E_ERR_PARAM;
4907
4908         i40e_fill_default_direct_cmd_desc(&desc,
4909                                           i40e_aqc_opc_add_multicast_etag);
4910
4911         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4912         cmd->etag = CPU_TO_LE16(etag);
4913         cmd->num_unicast_etags = num_tags_in_buf;
4914
4915         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4916         if (length > I40E_AQ_LARGE_BUF)
4917                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4918
4919         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4920
4921         if (!status) {
4922                 if (tags_used != NULL)
4923                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4924                 if (tags_free != NULL)
4925                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4926         }
4927
4928         return status;
4929 }
4930
4931 /**
4932  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4933  * @hw: pointer to the hw struct
4934  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4935  * @etag: value of the E-tag to remove
4936  * @tags_used: return value, number of tags in use by this port
4937  * @tags_free: return value, number of unallocated tags
4938  * @cmd_details: pointer to command details structure or NULL
4939  *
4940  * This deletes an E-tag from the port virtualizer.  It will return
4941  * the number of tags allocated by the port, and the number of unallocated
4942  * tags available.
4943  **/
4944 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4945                                 u16 etag, u16 *tags_used, u16 *tags_free,
4946                                 struct i40e_asq_cmd_details *cmd_details)
4947 {
4948         struct i40e_aq_desc desc;
4949         struct i40e_aqc_add_remove_mcast_etag *cmd =
4950                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4951         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4952            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4953         enum i40e_status_code status;
4954
4955
4956         if (pv_seid == 0)
4957                 return I40E_ERR_PARAM;
4958
4959         i40e_fill_default_direct_cmd_desc(&desc,
4960                                           i40e_aqc_opc_remove_multicast_etag);
4961
4962         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4963         cmd->etag = CPU_TO_LE16(etag);
4964
4965         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4966
4967         if (!status) {
4968                 if (tags_used != NULL)
4969                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4970                 if (tags_free != NULL)
4971                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4972         }
4973
4974         return status;
4975 }
4976
4977 /**
4978  * i40e_aq_update_tag - Update an S/E-tag
4979  * @hw: pointer to the hw struct
4980  * @vsi_seid: VSI SEID using this S-tag
4981  * @old_tag: old tag value
4982  * @new_tag: new tag value
4983  * @tags_used: return value, number of tags in use by this PF
4984  * @tags_free: return value, number of unallocated tags
4985  * @cmd_details: pointer to command details structure or NULL
4986  *
4987  * This updates the value of the tag currently attached to this VSI
4988  * in the switch complex.  It will return the number of tags allocated
4989  * by the PF, and the number of unallocated tags available.
4990  **/
4991 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4992                                 u16 old_tag, u16 new_tag, u16 *tags_used,
4993                                 u16 *tags_free,
4994                                 struct i40e_asq_cmd_details *cmd_details)
4995 {
4996         struct i40e_aq_desc desc;
4997         struct i40e_aqc_update_tag *cmd =
4998                 (struct i40e_aqc_update_tag *)&desc.params.raw;
4999         struct i40e_aqc_update_tag_completion *resp =
5000                 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
5001         enum i40e_status_code status;
5002
5003         if (vsi_seid == 0)
5004                 return I40E_ERR_PARAM;
5005
5006         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
5007
5008         cmd->seid = CPU_TO_LE16(vsi_seid);
5009         cmd->old_tag = CPU_TO_LE16(old_tag);
5010         cmd->new_tag = CPU_TO_LE16(new_tag);
5011
5012         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5013
5014         if (!status) {
5015                 if (tags_used != NULL)
5016                         *tags_used = LE16_TO_CPU(resp->tags_used);
5017                 if (tags_free != NULL)
5018                         *tags_free = LE16_TO_CPU(resp->tags_free);
5019         }
5020
5021         return status;
5022 }
5023
5024 /**
5025  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
5026  * @hw: pointer to the hw struct
5027  * @tcmap: TC map for request/release any ignore PFC condition
5028  * @request: request or release ignore PFC condition
5029  * @tcmap_ret: return TCs for which PFC is currently ignored
5030  * @cmd_details: pointer to command details structure or NULL
5031  *
5032  * This sends out request/release to ignore PFC condition for a TC.
5033  * It will return the TCs for which PFC is currently ignored.
5034  **/
5035 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
5036                                 bool request, u8 *tcmap_ret,
5037                                 struct i40e_asq_cmd_details *cmd_details)
5038 {
5039         struct i40e_aq_desc desc;
5040         struct i40e_aqc_pfc_ignore *cmd_resp =
5041                 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
5042         enum i40e_status_code status;
5043
5044         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
5045
5046         if (request)
5047                 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
5048
5049         cmd_resp->tc_bitmap = tcmap;
5050
5051         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5052
5053         if (!status) {
5054                 if (tcmap_ret != NULL)
5055                         *tcmap_ret = cmd_resp->tc_bitmap;
5056         }
5057
5058         return status;
5059 }
5060
5061 /**
5062  * i40e_aq_dcb_updated - DCB Updated Command
5063  * @hw: pointer to the hw struct
5064  * @cmd_details: pointer to command details structure or NULL
5065  *
5066  * When LLDP is handled in PF this command is used by the PF
5067  * to notify EMP that a DCB setting is modified.
5068  * When LLDP is handled in EMP this command is used by the PF
5069  * to notify EMP whenever one of the following parameters get
5070  * modified:
5071  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
5072  *   - PCIRTT in PRTDCB_GENC.PCIRTT
5073  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
5074  * EMP will return when the shared RPB settings have been
5075  * recomputed and modified. The retval field in the descriptor
5076  * will be set to 0 when RPB is modified.
5077  **/
5078 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
5079                                 struct i40e_asq_cmd_details *cmd_details)
5080 {
5081         struct i40e_aq_desc desc;
5082         enum i40e_status_code status;
5083
5084         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
5085
5086         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5087
5088         return status;
5089 }
5090
5091 /**
5092  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
5093  * @hw: pointer to the hw struct
5094  * @seid: defines the SEID of the switch for which the stats are requested
5095  * @vlan_id: the VLAN ID for which the statistics are requested
5096  * @stat_index: index of the statistics counters block assigned to this VLAN
5097  * @cmd_details: pointer to command details structure or NULL
5098  *
5099  * XL710 supports 128 smonVlanStats counters.This command is used to
5100  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
5101  * switch.
5102  **/
5103 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
5104                                 u16 vlan_id, u16 *stat_index,
5105                                 struct i40e_asq_cmd_details *cmd_details)
5106 {
5107         struct i40e_aq_desc desc;
5108         struct i40e_aqc_add_remove_statistics *cmd_resp =
5109                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5110         enum i40e_status_code status;
5111
5112         if ((seid == 0) || (stat_index == NULL))
5113                 return I40E_ERR_PARAM;
5114
5115         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
5116
5117         cmd_resp->seid = CPU_TO_LE16(seid);
5118         cmd_resp->vlan = CPU_TO_LE16(vlan_id);
5119
5120         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5121
5122         if (!status && stat_index)
5123                 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
5124
5125         return status;
5126 }
5127
5128 /**
5129  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
5130  * @hw: pointer to the hw struct
5131  * @seid: defines the SEID of the switch for which the stats are requested
5132  * @vlan_id: the VLAN ID for which the statistics are requested
5133  * @stat_index: index of the statistics counters block assigned to this VLAN
5134  * @cmd_details: pointer to command details structure or NULL
5135  *
5136  * XL710 supports 128 smonVlanStats counters.This command is used to
5137  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
5138  * switch.
5139  **/
5140 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
5141                                 u16 vlan_id, u16 stat_index,
5142                                 struct i40e_asq_cmd_details *cmd_details)
5143 {
5144         struct i40e_aq_desc desc;
5145         struct i40e_aqc_add_remove_statistics *cmd =
5146                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5147         enum i40e_status_code status;
5148
5149         if (seid == 0)
5150                 return I40E_ERR_PARAM;
5151
5152         i40e_fill_default_direct_cmd_desc(&desc,
5153                                           i40e_aqc_opc_remove_statistics);
5154
5155         cmd->seid = CPU_TO_LE16(seid);
5156         cmd->vlan  = CPU_TO_LE16(vlan_id);
5157         cmd->stat_index = CPU_TO_LE16(stat_index);
5158
5159         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5160
5161         return status;
5162 }
5163
5164 /**
5165  * i40e_aq_set_port_parameters - set physical port parameters.
5166  * @hw: pointer to the hw struct
5167  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
5168  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
5169  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
5170  * @double_vlan: if set double VLAN is enabled
5171  * @cmd_details: pointer to command details structure or NULL
5172  **/
5173 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
5174                                 u16 bad_frame_vsi, bool save_bad_pac,
5175                                 bool pad_short_pac, bool double_vlan,
5176                                 struct i40e_asq_cmd_details *cmd_details)
5177 {
5178         struct i40e_aqc_set_port_parameters *cmd;
5179         enum i40e_status_code status;
5180         struct i40e_aq_desc desc;
5181         u16 command_flags = 0;
5182
5183         cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
5184
5185         i40e_fill_default_direct_cmd_desc(&desc,
5186                                           i40e_aqc_opc_set_port_parameters);
5187
5188         cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
5189         if (save_bad_pac)
5190                 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
5191         if (pad_short_pac)
5192                 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
5193         if (double_vlan)
5194                 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
5195         cmd->command_flags = CPU_TO_LE16(command_flags);
5196
5197         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5198
5199         return status;
5200 }
5201
5202 /**
5203  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
5204  * @hw: pointer to the hw struct
5205  * @seid: seid for the physical port/switching component/vsi
5206  * @buff: Indirect buffer to hold data parameters and response
5207  * @buff_size: Indirect buffer size
5208  * @opcode: Tx scheduler AQ command opcode
5209  * @cmd_details: pointer to command details structure or NULL
5210  *
5211  * Generic command handler for Tx scheduler AQ commands
5212  **/
5213 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
5214                                 void *buff, u16 buff_size,
5215                                  enum i40e_admin_queue_opc opcode,
5216                                 struct i40e_asq_cmd_details *cmd_details)
5217 {
5218         struct i40e_aq_desc desc;
5219         struct i40e_aqc_tx_sched_ind *cmd =
5220                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
5221         enum i40e_status_code status;
5222         bool cmd_param_flag = false;
5223
5224         switch (opcode) {
5225         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
5226         case i40e_aqc_opc_configure_vsi_tc_bw:
5227         case i40e_aqc_opc_enable_switching_comp_ets:
5228         case i40e_aqc_opc_modify_switching_comp_ets:
5229         case i40e_aqc_opc_disable_switching_comp_ets:
5230         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
5231         case i40e_aqc_opc_configure_switching_comp_bw_config:
5232                 cmd_param_flag = true;
5233                 break;
5234         case i40e_aqc_opc_query_vsi_bw_config:
5235         case i40e_aqc_opc_query_vsi_ets_sla_config:
5236         case i40e_aqc_opc_query_switching_comp_ets_config:
5237         case i40e_aqc_opc_query_port_ets_config:
5238         case i40e_aqc_opc_query_switching_comp_bw_config:
5239                 cmd_param_flag = false;
5240                 break;
5241         default:
5242                 return I40E_ERR_PARAM;
5243         }
5244
5245         i40e_fill_default_direct_cmd_desc(&desc, opcode);
5246
5247         /* Indirect command */
5248         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5249         if (cmd_param_flag)
5250                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5251         if (buff_size > I40E_AQ_LARGE_BUF)
5252                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5253
5254         desc.datalen = CPU_TO_LE16(buff_size);
5255
5256         cmd->vsi_seid = CPU_TO_LE16(seid);
5257
5258         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5259
5260         return status;
5261 }
5262
5263 /**
5264  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5265  * @hw: pointer to the hw struct
5266  * @seid: VSI seid
5267  * @credit: BW limit credits (0 = disabled)
5268  * @max_credit: Max BW limit credits
5269  * @cmd_details: pointer to command details structure or NULL
5270  **/
5271 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5272                                 u16 seid, u16 credit, u8 max_credit,
5273                                 struct i40e_asq_cmd_details *cmd_details)
5274 {
5275         struct i40e_aq_desc desc;
5276         struct i40e_aqc_configure_vsi_bw_limit *cmd =
5277                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5278         enum i40e_status_code status;
5279
5280         i40e_fill_default_direct_cmd_desc(&desc,
5281                                           i40e_aqc_opc_configure_vsi_bw_limit);
5282
5283         cmd->vsi_seid = CPU_TO_LE16(seid);
5284         cmd->credit = CPU_TO_LE16(credit);
5285         cmd->max_credit = max_credit;
5286
5287         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5288
5289         return status;
5290 }
5291
5292 /**
5293  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5294  * @hw: pointer to the hw struct
5295  * @seid: switching component seid
5296  * @credit: BW limit credits (0 = disabled)
5297  * @max_bw: Max BW limit credits
5298  * @cmd_details: pointer to command details structure or NULL
5299  **/
5300 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5301                                 u16 seid, u16 credit, u8 max_bw,
5302                                 struct i40e_asq_cmd_details *cmd_details)
5303 {
5304         struct i40e_aq_desc desc;
5305         struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5306           (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5307         enum i40e_status_code status;
5308
5309         i40e_fill_default_direct_cmd_desc(&desc,
5310                                 i40e_aqc_opc_configure_switching_comp_bw_limit);
5311
5312         cmd->seid = CPU_TO_LE16(seid);
5313         cmd->credit = CPU_TO_LE16(credit);
5314         cmd->max_bw = max_bw;
5315
5316         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5317
5318         return status;
5319 }
5320
5321 /**
5322  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5323  * @hw: pointer to the hw struct
5324  * @seid: VSI seid
5325  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5326  * @cmd_details: pointer to command details structure or NULL
5327  **/
5328 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5329                         u16 seid,
5330                         struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5331                         struct i40e_asq_cmd_details *cmd_details)
5332 {
5333         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5334                                     i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5335                                     cmd_details);
5336 }
5337
5338 /**
5339  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5340  * @hw: pointer to the hw struct
5341  * @seid: VSI seid
5342  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5343  * @cmd_details: pointer to command details structure or NULL
5344  **/
5345 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5346                         u16 seid,
5347                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5348                         struct i40e_asq_cmd_details *cmd_details)
5349 {
5350         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5351                                     i40e_aqc_opc_configure_vsi_tc_bw,
5352                                     cmd_details);
5353 }
5354
5355 /**
5356  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5357  * @hw: pointer to the hw struct
5358  * @seid: seid of the switching component connected to Physical Port
5359  * @ets_data: Buffer holding ETS parameters
5360  * @opcode: Tx scheduler AQ command opcode
5361  * @cmd_details: pointer to command details structure or NULL
5362  **/
5363 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5364                 u16 seid,
5365                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5366                 enum i40e_admin_queue_opc opcode,
5367                 struct i40e_asq_cmd_details *cmd_details)
5368 {
5369         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5370                                     sizeof(*ets_data), opcode, cmd_details);
5371 }
5372
5373 /**
5374  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5375  * @hw: pointer to the hw struct
5376  * @seid: seid of the switching component
5377  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5378  * @cmd_details: pointer to command details structure or NULL
5379  **/
5380 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5381         u16 seid,
5382         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5383         struct i40e_asq_cmd_details *cmd_details)
5384 {
5385         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5386                             i40e_aqc_opc_configure_switching_comp_bw_config,
5387                             cmd_details);
5388 }
5389
5390 /**
5391  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5392  * @hw: pointer to the hw struct
5393  * @seid: seid of the switching component
5394  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5395  * @cmd_details: pointer to command details structure or NULL
5396  **/
5397 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5398         struct i40e_hw *hw, u16 seid,
5399         struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5400         struct i40e_asq_cmd_details *cmd_details)
5401 {
5402         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5403                             i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5404                             cmd_details);
5405 }
5406
5407 /**
5408  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5409  * @hw: pointer to the hw struct
5410  * @seid: seid of the VSI
5411  * @bw_data: Buffer to hold VSI BW configuration
5412  * @cmd_details: pointer to command details structure or NULL
5413  **/
5414 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5415                         u16 seid,
5416                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5417                         struct i40e_asq_cmd_details *cmd_details)
5418 {
5419         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5420                                     i40e_aqc_opc_query_vsi_bw_config,
5421                                     cmd_details);
5422 }
5423
5424 /**
5425  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5426  * @hw: pointer to the hw struct
5427  * @seid: seid of the VSI
5428  * @bw_data: Buffer to hold VSI BW configuration per TC
5429  * @cmd_details: pointer to command details structure or NULL
5430  **/
5431 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5432                         u16 seid,
5433                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5434                         struct i40e_asq_cmd_details *cmd_details)
5435 {
5436         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5437                                     i40e_aqc_opc_query_vsi_ets_sla_config,
5438                                     cmd_details);
5439 }
5440
5441 /**
5442  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5443  * @hw: pointer to the hw struct
5444  * @seid: seid of the switching component
5445  * @bw_data: Buffer to hold switching component's per TC BW config
5446  * @cmd_details: pointer to command details structure or NULL
5447  **/
5448 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5449                 u16 seid,
5450                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5451                 struct i40e_asq_cmd_details *cmd_details)
5452 {
5453         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5454                                    i40e_aqc_opc_query_switching_comp_ets_config,
5455                                    cmd_details);
5456 }
5457
5458 /**
5459  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5460  * @hw: pointer to the hw struct
5461  * @seid: seid of the VSI or switching component connected to Physical Port
5462  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5463  * @cmd_details: pointer to command details structure or NULL
5464  **/
5465 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5466                         u16 seid,
5467                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
5468                         struct i40e_asq_cmd_details *cmd_details)
5469 {
5470         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5471                                     i40e_aqc_opc_query_port_ets_config,
5472                                     cmd_details);
5473 }
5474
5475 /**
5476  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5477  * @hw: pointer to the hw struct
5478  * @seid: seid of the switching component
5479  * @bw_data: Buffer to hold switching component's BW configuration
5480  * @cmd_details: pointer to command details structure or NULL
5481  **/
5482 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5483                 u16 seid,
5484                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5485                 struct i40e_asq_cmd_details *cmd_details)
5486 {
5487         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5488                                     i40e_aqc_opc_query_switching_comp_bw_config,
5489                                     cmd_details);
5490 }
5491
5492 /**
5493  * i40e_validate_filter_settings
5494  * @hw: pointer to the hardware structure
5495  * @settings: Filter control settings
5496  *
5497  * Check and validate the filter control settings passed.
5498  * The function checks for the valid filter/context sizes being
5499  * passed for FCoE and PE.
5500  *
5501  * Returns I40E_SUCCESS if the values passed are valid and within
5502  * range else returns an error.
5503  **/
5504 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5505                                 struct i40e_filter_control_settings *settings)
5506 {
5507         u32 fcoe_cntx_size, fcoe_filt_size;
5508         u32 pe_cntx_size, pe_filt_size;
5509         u32 fcoe_fmax;
5510
5511         u32 val;
5512
5513         /* Validate FCoE settings passed */
5514         switch (settings->fcoe_filt_num) {
5515         case I40E_HASH_FILTER_SIZE_1K:
5516         case I40E_HASH_FILTER_SIZE_2K:
5517         case I40E_HASH_FILTER_SIZE_4K:
5518         case I40E_HASH_FILTER_SIZE_8K:
5519         case I40E_HASH_FILTER_SIZE_16K:
5520         case I40E_HASH_FILTER_SIZE_32K:
5521                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5522                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5523                 break;
5524         default:
5525                 return I40E_ERR_PARAM;
5526         }
5527
5528         switch (settings->fcoe_cntx_num) {
5529         case I40E_DMA_CNTX_SIZE_512:
5530         case I40E_DMA_CNTX_SIZE_1K:
5531         case I40E_DMA_CNTX_SIZE_2K:
5532         case I40E_DMA_CNTX_SIZE_4K:
5533                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5534                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5535                 break;
5536         default:
5537                 return I40E_ERR_PARAM;
5538         }
5539
5540         /* Validate PE settings passed */
5541         switch (settings->pe_filt_num) {
5542         case I40E_HASH_FILTER_SIZE_1K:
5543         case I40E_HASH_FILTER_SIZE_2K:
5544         case I40E_HASH_FILTER_SIZE_4K:
5545         case I40E_HASH_FILTER_SIZE_8K:
5546         case I40E_HASH_FILTER_SIZE_16K:
5547         case I40E_HASH_FILTER_SIZE_32K:
5548         case I40E_HASH_FILTER_SIZE_64K:
5549         case I40E_HASH_FILTER_SIZE_128K:
5550         case I40E_HASH_FILTER_SIZE_256K:
5551         case I40E_HASH_FILTER_SIZE_512K:
5552         case I40E_HASH_FILTER_SIZE_1M:
5553                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5554                 pe_filt_size <<= (u32)settings->pe_filt_num;
5555                 break;
5556         default:
5557                 return I40E_ERR_PARAM;
5558         }
5559
5560         switch (settings->pe_cntx_num) {
5561         case I40E_DMA_CNTX_SIZE_512:
5562         case I40E_DMA_CNTX_SIZE_1K:
5563         case I40E_DMA_CNTX_SIZE_2K:
5564         case I40E_DMA_CNTX_SIZE_4K:
5565         case I40E_DMA_CNTX_SIZE_8K:
5566         case I40E_DMA_CNTX_SIZE_16K:
5567         case I40E_DMA_CNTX_SIZE_32K:
5568         case I40E_DMA_CNTX_SIZE_64K:
5569         case I40E_DMA_CNTX_SIZE_128K:
5570         case I40E_DMA_CNTX_SIZE_256K:
5571                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5572                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5573                 break;
5574         default:
5575                 return I40E_ERR_PARAM;
5576         }
5577
5578         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5579         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5580         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5581                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5582         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
5583                 return I40E_ERR_INVALID_SIZE;
5584
5585         return I40E_SUCCESS;
5586 }
5587
5588 /**
5589  * i40e_set_filter_control
5590  * @hw: pointer to the hardware structure
5591  * @settings: Filter control settings
5592  *
5593  * Set the Queue Filters for PE/FCoE and enable filters required
5594  * for a single PF. It is expected that these settings are programmed
5595  * at the driver initialization time.
5596  **/
5597 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5598                                 struct i40e_filter_control_settings *settings)
5599 {
5600         enum i40e_status_code ret = I40E_SUCCESS;
5601         u32 hash_lut_size = 0;
5602         u32 val;
5603
5604         if (!settings)
5605                 return I40E_ERR_PARAM;
5606
5607         /* Validate the input settings */
5608         ret = i40e_validate_filter_settings(hw, settings);
5609         if (ret)
5610                 return ret;
5611
5612         /* Read the PF Queue Filter control register */
5613         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5614
5615         /* Program required PE hash buckets for the PF */
5616         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5617         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5618                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5619         /* Program required PE contexts for the PF */
5620         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5621         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5622                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5623
5624         /* Program required FCoE hash buckets for the PF */
5625         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5626         val |= ((u32)settings->fcoe_filt_num <<
5627                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5628                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5629         /* Program required FCoE DDP contexts for the PF */
5630         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5631         val |= ((u32)settings->fcoe_cntx_num <<
5632                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5633                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5634
5635         /* Program Hash LUT size for the PF */
5636         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5637         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5638                 hash_lut_size = 1;
5639         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5640                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5641
5642         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5643         if (settings->enable_fdir)
5644                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5645         if (settings->enable_ethtype)
5646                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5647         if (settings->enable_macvlan)
5648                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5649
5650         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5651
5652         return I40E_SUCCESS;
5653 }
5654
5655 /**
5656  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5657  * @hw: pointer to the hw struct
5658  * @mac_addr: MAC address to use in the filter
5659  * @ethtype: Ethertype to use in the filter
5660  * @flags: Flags that needs to be applied to the filter
5661  * @vsi_seid: seid of the control VSI
5662  * @queue: VSI queue number to send the packet to
5663  * @is_add: Add control packet filter if True else remove
5664  * @stats: Structure to hold information on control filter counts
5665  * @cmd_details: pointer to command details structure or NULL
5666  *
5667  * This command will Add or Remove control packet filter for a control VSI.
5668  * In return it will update the total number of perfect filter count in
5669  * the stats member.
5670  **/
5671 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5672                                 u8 *mac_addr, u16 ethtype, u16 flags,
5673                                 u16 vsi_seid, u16 queue, bool is_add,
5674                                 struct i40e_control_filter_stats *stats,
5675                                 struct i40e_asq_cmd_details *cmd_details)
5676 {
5677         struct i40e_aq_desc desc;
5678         struct i40e_aqc_add_remove_control_packet_filter *cmd =
5679                 (struct i40e_aqc_add_remove_control_packet_filter *)
5680                 &desc.params.raw;
5681         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5682                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5683                 &desc.params.raw;
5684         enum i40e_status_code status;
5685
5686         if (vsi_seid == 0)
5687                 return I40E_ERR_PARAM;
5688
5689         if (is_add) {
5690                 i40e_fill_default_direct_cmd_desc(&desc,
5691                                 i40e_aqc_opc_add_control_packet_filter);
5692                 cmd->queue = CPU_TO_LE16(queue);
5693         } else {
5694                 i40e_fill_default_direct_cmd_desc(&desc,
5695                                 i40e_aqc_opc_remove_control_packet_filter);
5696         }
5697
5698         if (mac_addr)
5699                 i40e_memcpy(cmd->mac, mac_addr, ETH_ALEN,
5700                             I40E_NONDMA_TO_NONDMA);
5701
5702         cmd->etype = CPU_TO_LE16(ethtype);
5703         cmd->flags = CPU_TO_LE16(flags);
5704         cmd->seid = CPU_TO_LE16(vsi_seid);
5705
5706         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5707
5708         if (!status && stats) {
5709                 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5710                 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5711                 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5712                 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5713         }
5714
5715         return status;
5716 }
5717
5718 /**
5719  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5720  * @hw: pointer to the hw struct
5721  * @seid: VSI seid to add ethertype filter from
5722  **/
5723 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5724                                                     u16 seid)
5725 {
5726 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5727         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5728                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5729                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5730         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5731         enum i40e_status_code status;
5732
5733         status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5734                                                        seid, 0, true, NULL,
5735                                                        NULL);
5736         if (status)
5737                 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5738 }
5739
5740 /**
5741  * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5742  * @filters: list of cloud filters
5743  * @filter_count: length of list
5744  *
5745  * There's an issue in the device where the Geneve VNI layout needs
5746  * to be shifted 1 byte over from the VxLAN VNI
5747  **/
5748 STATIC void i40e_fix_up_geneve_vni(
5749         struct i40e_aqc_cloud_filters_element_data *filters,
5750         u8 filter_count)
5751 {
5752         struct i40e_aqc_cloud_filters_element_data *f = filters;
5753         int i;
5754
5755         for (i = 0; i < filter_count; i++) {
5756                 u16 tnl_type;
5757                 u32 ti;
5758
5759                 tnl_type = (LE16_TO_CPU(f[i].flags) &
5760                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5761                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5762                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5763                         ti = LE32_TO_CPU(f[i].tenant_id);
5764                         f[i].tenant_id = CPU_TO_LE32(ti << 8);
5765                 }
5766         }
5767 }
5768
5769 /**
5770  * i40e_aq_add_cloud_filters
5771  * @hw: pointer to the hardware structure
5772  * @seid: VSI seid to add cloud filters from
5773  * @filters: Buffer which contains the filters to be added
5774  * @filter_count: number of filters contained in the buffer
5775  *
5776  * Set the cloud filters for a given VSI.  The contents of the
5777  * i40e_aqc_cloud_filters_element_data are filled
5778  * in by the caller of the function.
5779  *
5780  **/
5781 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5782         u16 seid,
5783         struct i40e_aqc_cloud_filters_element_data *filters,
5784         u8 filter_count)
5785 {
5786         struct i40e_aq_desc desc;
5787         struct i40e_aqc_add_remove_cloud_filters *cmd =
5788         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5789         enum i40e_status_code status;
5790         u16 buff_len;
5791
5792         i40e_fill_default_direct_cmd_desc(&desc,
5793                                           i40e_aqc_opc_add_cloud_filters);
5794
5795         buff_len = filter_count * sizeof(*filters);
5796         desc.datalen = CPU_TO_LE16(buff_len);
5797         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5798         cmd->num_filters = filter_count;
5799         cmd->seid = CPU_TO_LE16(seid);
5800
5801         i40e_fix_up_geneve_vni(filters, filter_count);
5802
5803         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5804
5805         return status;
5806 }
5807
5808 /**
5809  * i40e_aq_add_cloud_filters_bb
5810  * @hw: pointer to the hardware structure
5811  * @seid: VSI seid to add cloud filters from
5812  * @filters: Buffer which contains the filters in big buffer to be added
5813  * @filter_count: number of filters contained in the buffer
5814  *
5815  * Set the cloud filters for a given VSI.  The contents of the
5816  * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5817  * the function.
5818  *
5819  **/
5820 enum i40e_status_code
5821 i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5822                              struct i40e_aqc_cloud_filters_element_bb *filters,
5823                              u8 filter_count)
5824 {
5825         struct i40e_aq_desc desc;
5826         struct i40e_aqc_add_remove_cloud_filters *cmd =
5827         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5828         enum i40e_status_code status;
5829         u16 buff_len;
5830         int i;
5831
5832         i40e_fill_default_direct_cmd_desc(&desc,
5833                                           i40e_aqc_opc_add_cloud_filters);
5834
5835         buff_len = filter_count * sizeof(*filters);
5836         desc.datalen = CPU_TO_LE16(buff_len);
5837         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5838         cmd->num_filters = filter_count;
5839         cmd->seid = CPU_TO_LE16(seid);
5840         cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5841
5842         for (i = 0; i < filter_count; i++) {
5843                 u16 tnl_type;
5844                 u32 ti;
5845
5846                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5847                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5848                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5849
5850                 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5851                  * one more byte further than normally used for Tenant ID in
5852                  * other tunnel types.
5853                  */
5854                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5855                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5856                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5857                 }
5858         }
5859
5860         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5861
5862         return status;
5863 }
5864
5865 /**
5866  * i40e_aq_rem_cloud_filters
5867  * @hw: pointer to the hardware structure
5868  * @seid: VSI seid to remove cloud filters from
5869  * @filters: Buffer which contains the filters to be removed
5870  * @filter_count: number of filters contained in the buffer
5871  *
5872  * Remove the cloud filters for a given VSI.  The contents of the
5873  * i40e_aqc_cloud_filters_element_data are filled in by the caller
5874  * of the function.
5875  *
5876  **/
5877 enum i40e_status_code
5878 i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid,
5879                           struct i40e_aqc_cloud_filters_element_data *filters,
5880                           u8 filter_count)
5881 {
5882         struct i40e_aq_desc desc;
5883         struct i40e_aqc_add_remove_cloud_filters *cmd =
5884         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5885         enum i40e_status_code status;
5886         u16 buff_len;
5887
5888         i40e_fill_default_direct_cmd_desc(&desc,
5889                                           i40e_aqc_opc_remove_cloud_filters);
5890
5891         buff_len = filter_count * sizeof(*filters);
5892         desc.datalen = CPU_TO_LE16(buff_len);
5893         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5894         cmd->num_filters = filter_count;
5895         cmd->seid = CPU_TO_LE16(seid);
5896
5897         i40e_fix_up_geneve_vni(filters, filter_count);
5898
5899         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5900
5901         return status;
5902 }
5903
5904 /**
5905  * i40e_aq_rem_cloud_filters_bb
5906  * @hw: pointer to the hardware structure
5907  * @seid: VSI seid to remove cloud filters from
5908  * @filters: Buffer which contains the filters in big buffer to be removed
5909  * @filter_count: number of filters contained in the buffer
5910  *
5911  * Remove the big buffer cloud filters for a given VSI.  The contents of the
5912  * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5913  * function.
5914  *
5915  **/
5916 enum i40e_status_code
5917 i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5918                              struct i40e_aqc_cloud_filters_element_bb *filters,
5919                              u8 filter_count)
5920 {
5921         struct i40e_aq_desc desc;
5922         struct i40e_aqc_add_remove_cloud_filters *cmd =
5923         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5924         enum i40e_status_code status;
5925         u16 buff_len;
5926         int i;
5927
5928         i40e_fill_default_direct_cmd_desc(&desc,
5929                                           i40e_aqc_opc_remove_cloud_filters);
5930
5931         buff_len = filter_count * sizeof(*filters);
5932         desc.datalen = CPU_TO_LE16(buff_len);
5933         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5934         cmd->num_filters = filter_count;
5935         cmd->seid = CPU_TO_LE16(seid);
5936         cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5937
5938         for (i = 0; i < filter_count; i++) {
5939                 u16 tnl_type;
5940                 u32 ti;
5941
5942                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5943                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5944                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5945
5946                 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5947                  * one more byte further than normally used for Tenant ID in
5948                  * other tunnel types.
5949                  */
5950                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5951                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5952                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5953                 }
5954         }
5955
5956         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5957
5958         return status;
5959 }
5960
5961 /**
5962  * i40e_aq_replace_cloud_filters - Replace cloud filter command
5963  * @hw: pointer to the hw struct
5964  * @filters: pointer to the i40e_aqc_replace_cloud_filter_cmd struct
5965  * @cmd_buf: pointer to the i40e_aqc_replace_cloud_filter_cmd_buf struct
5966  *
5967  **/
5968 enum
5969 i40e_status_code i40e_aq_replace_cloud_filters(struct i40e_hw *hw,
5970         struct i40e_aqc_replace_cloud_filters_cmd *filters,
5971         struct i40e_aqc_replace_cloud_filters_cmd_buf *cmd_buf)
5972 {
5973         struct i40e_aq_desc desc;
5974         struct i40e_aqc_replace_cloud_filters_cmd *cmd =
5975                 (struct i40e_aqc_replace_cloud_filters_cmd *)&desc.params.raw;
5976         enum i40e_status_code status = I40E_SUCCESS;
5977         int i = 0;
5978
5979         i40e_fill_default_direct_cmd_desc(&desc,
5980                                           i40e_aqc_opc_replace_cloud_filters);
5981
5982         desc.datalen = CPU_TO_LE16(32);
5983         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5984         cmd->old_filter_type = filters->old_filter_type;
5985         cmd->new_filter_type = filters->new_filter_type;
5986         cmd->valid_flags = filters->valid_flags;
5987         cmd->tr_bit = filters->tr_bit;
5988
5989         status = i40e_asq_send_command(hw, &desc, cmd_buf,
5990                 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf),  NULL);
5991
5992         /* for get cloud filters command */
5993         for (i = 0; i < 32; i += 4) {
5994                 cmd_buf->filters[i / 4].filter_type = cmd_buf->data[i];
5995                 cmd_buf->filters[i / 4].input[0] = cmd_buf->data[i + 1];
5996                 cmd_buf->filters[i / 4].input[1] = cmd_buf->data[i + 2];
5997                 cmd_buf->filters[i / 4].input[2] = cmd_buf->data[i + 3];
5998         }
5999
6000         return status;
6001 }
6002
6003
6004 /**
6005  * i40e_aq_alternate_write
6006  * @hw: pointer to the hardware structure
6007  * @reg_addr0: address of first dword to be read
6008  * @reg_val0: value to be written under 'reg_addr0'
6009  * @reg_addr1: address of second dword to be read
6010  * @reg_val1: value to be written under 'reg_addr1'
6011  *
6012  * Write one or two dwords to alternate structure. Fields are indicated
6013  * by 'reg_addr0' and 'reg_addr1' register numbers.
6014  *
6015  **/
6016 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
6017                                 u32 reg_addr0, u32 reg_val0,
6018                                 u32 reg_addr1, u32 reg_val1)
6019 {
6020         struct i40e_aq_desc desc;
6021         struct i40e_aqc_alternate_write *cmd_resp =
6022                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
6023         enum i40e_status_code status;
6024
6025         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
6026         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
6027         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
6028         cmd_resp->data0 = CPU_TO_LE32(reg_val0);
6029         cmd_resp->data1 = CPU_TO_LE32(reg_val1);
6030
6031         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6032
6033         return status;
6034 }
6035
6036 /**
6037  * i40e_aq_alternate_write_indirect
6038  * @hw: pointer to the hardware structure
6039  * @addr: address of a first register to be modified
6040  * @dw_count: number of alternate structure fields to write
6041  * @buffer: pointer to the command buffer
6042  *
6043  * Write 'dw_count' dwords from 'buffer' to alternate structure
6044  * starting at 'addr'.
6045  *
6046  **/
6047 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
6048                                 u32 addr, u32 dw_count, void *buffer)
6049 {
6050         struct i40e_aq_desc desc;
6051         struct i40e_aqc_alternate_ind_write *cmd_resp =
6052                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
6053         enum i40e_status_code status;
6054
6055         if (buffer == NULL)
6056                 return I40E_ERR_PARAM;
6057
6058         /* Indirect command */
6059         i40e_fill_default_direct_cmd_desc(&desc,
6060                                          i40e_aqc_opc_alternate_write_indirect);
6061
6062         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6063         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6064         if (dw_count > (I40E_AQ_LARGE_BUF/4))
6065                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6066
6067         cmd_resp->address = CPU_TO_LE32(addr);
6068         cmd_resp->length = CPU_TO_LE32(dw_count);
6069
6070         status = i40e_asq_send_command(hw, &desc, buffer,
6071                                        I40E_LO_DWORD(4*dw_count), NULL);
6072
6073         return status;
6074 }
6075
6076 /**
6077  * i40e_aq_alternate_read
6078  * @hw: pointer to the hardware structure
6079  * @reg_addr0: address of first dword to be read
6080  * @reg_val0: pointer for data read from 'reg_addr0'
6081  * @reg_addr1: address of second dword to be read
6082  * @reg_val1: pointer for data read from 'reg_addr1'
6083  *
6084  * Read one or two dwords from alternate structure. Fields are indicated
6085  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
6086  * is not passed then only register at 'reg_addr0' is read.
6087  *
6088  **/
6089 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
6090                                 u32 reg_addr0, u32 *reg_val0,
6091                                 u32 reg_addr1, u32 *reg_val1)
6092 {
6093         struct i40e_aq_desc desc;
6094         struct i40e_aqc_alternate_write *cmd_resp =
6095                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
6096         enum i40e_status_code status;
6097
6098         if (reg_val0 == NULL)
6099                 return I40E_ERR_PARAM;
6100
6101         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
6102         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
6103         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
6104
6105         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6106
6107         if (status == I40E_SUCCESS) {
6108                 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
6109
6110                 if (reg_val1 != NULL)
6111                         *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
6112         }
6113
6114         return status;
6115 }
6116
6117 /**
6118  * i40e_aq_alternate_read_indirect
6119  * @hw: pointer to the hardware structure
6120  * @addr: address of the alternate structure field
6121  * @dw_count: number of alternate structure fields to read
6122  * @buffer: pointer to the command buffer
6123  *
6124  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
6125  * place them in 'buffer'. The buffer should be allocated by caller.
6126  *
6127  **/
6128 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
6129                                 u32 addr, u32 dw_count, void *buffer)
6130 {
6131         struct i40e_aq_desc desc;
6132         struct i40e_aqc_alternate_ind_write *cmd_resp =
6133                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
6134         enum i40e_status_code status;
6135
6136         if (buffer == NULL)
6137                 return I40E_ERR_PARAM;
6138
6139         /* Indirect command */
6140         i40e_fill_default_direct_cmd_desc(&desc,
6141                 i40e_aqc_opc_alternate_read_indirect);
6142
6143         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6144         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6145         if (dw_count > (I40E_AQ_LARGE_BUF/4))
6146                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6147
6148         cmd_resp->address = CPU_TO_LE32(addr);
6149         cmd_resp->length = CPU_TO_LE32(dw_count);
6150
6151         status = i40e_asq_send_command(hw, &desc, buffer,
6152                                        I40E_LO_DWORD(4*dw_count), NULL);
6153
6154         return status;
6155 }
6156
6157 /**
6158  *  i40e_aq_alternate_clear
6159  *  @hw: pointer to the HW structure.
6160  *
6161  *  Clear the alternate structures of the port from which the function
6162  *  is called.
6163  *
6164  **/
6165 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
6166 {
6167         struct i40e_aq_desc desc;
6168         enum i40e_status_code status;
6169
6170         i40e_fill_default_direct_cmd_desc(&desc,
6171                                           i40e_aqc_opc_alternate_clear_port);
6172
6173         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6174
6175         return status;
6176 }
6177
6178 /**
6179  *  i40e_aq_alternate_write_done
6180  *  @hw: pointer to the HW structure.
6181  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
6182  *  @reset_needed: indicates the SW should trigger GLOBAL reset
6183  *
6184  *  Indicates to the FW that alternate structures have been changed.
6185  *
6186  **/
6187 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
6188                 u8 bios_mode, bool *reset_needed)
6189 {
6190         struct i40e_aq_desc desc;
6191         struct i40e_aqc_alternate_write_done *cmd =
6192                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6193         enum i40e_status_code status;
6194
6195         if (reset_needed == NULL)
6196                 return I40E_ERR_PARAM;
6197
6198         i40e_fill_default_direct_cmd_desc(&desc,
6199                                           i40e_aqc_opc_alternate_write_done);
6200
6201         cmd->cmd_flags = CPU_TO_LE16(bios_mode);
6202
6203         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6204         if (!status && reset_needed)
6205                 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
6206                                  I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
6207
6208         return status;
6209 }
6210
6211 /**
6212  *  i40e_aq_set_oem_mode
6213  *  @hw: pointer to the HW structure.
6214  *  @oem_mode: the OEM mode to be used
6215  *
6216  *  Sets the device to a specific operating mode. Currently the only supported
6217  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
6218  *
6219  **/
6220 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
6221                 u8 oem_mode)
6222 {
6223         struct i40e_aq_desc desc;
6224         struct i40e_aqc_alternate_write_done *cmd =
6225                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6226         enum i40e_status_code status;
6227
6228         i40e_fill_default_direct_cmd_desc(&desc,
6229                                           i40e_aqc_opc_alternate_set_mode);
6230
6231         cmd->cmd_flags = CPU_TO_LE16(oem_mode);
6232
6233         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6234
6235         return status;
6236 }
6237
6238 /**
6239  * i40e_aq_resume_port_tx
6240  * @hw: pointer to the hardware structure
6241  * @cmd_details: pointer to command details structure or NULL
6242  *
6243  * Resume port's Tx traffic
6244  **/
6245 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
6246                                 struct i40e_asq_cmd_details *cmd_details)
6247 {
6248         struct i40e_aq_desc desc;
6249         enum i40e_status_code status;
6250
6251         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
6252
6253         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6254
6255         return status;
6256 }
6257
6258 /**
6259  * i40e_set_pci_config_data - store PCI bus info
6260  * @hw: pointer to hardware structure
6261  * @link_status: the link status word from PCI config space
6262  *
6263  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
6264  **/
6265 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
6266 {
6267         hw->bus.type = i40e_bus_type_pci_express;
6268
6269         switch (link_status & I40E_PCI_LINK_WIDTH) {
6270         case I40E_PCI_LINK_WIDTH_1:
6271                 hw->bus.width = i40e_bus_width_pcie_x1;
6272                 break;
6273         case I40E_PCI_LINK_WIDTH_2:
6274                 hw->bus.width = i40e_bus_width_pcie_x2;
6275                 break;
6276         case I40E_PCI_LINK_WIDTH_4:
6277                 hw->bus.width = i40e_bus_width_pcie_x4;
6278                 break;
6279         case I40E_PCI_LINK_WIDTH_8:
6280                 hw->bus.width = i40e_bus_width_pcie_x8;
6281                 break;
6282         default:
6283                 hw->bus.width = i40e_bus_width_unknown;
6284                 break;
6285         }
6286
6287         switch (link_status & I40E_PCI_LINK_SPEED) {
6288         case I40E_PCI_LINK_SPEED_2500:
6289                 hw->bus.speed = i40e_bus_speed_2500;
6290                 break;
6291         case I40E_PCI_LINK_SPEED_5000:
6292                 hw->bus.speed = i40e_bus_speed_5000;
6293                 break;
6294         case I40E_PCI_LINK_SPEED_8000:
6295                 hw->bus.speed = i40e_bus_speed_8000;
6296                 break;
6297         default:
6298                 hw->bus.speed = i40e_bus_speed_unknown;
6299                 break;
6300         }
6301 }
6302
6303 /**
6304  * i40e_aq_debug_dump
6305  * @hw: pointer to the hardware structure
6306  * @cluster_id: specific cluster to dump
6307  * @table_id: table id within cluster
6308  * @start_index: index of line in the block to read
6309  * @buff_size: dump buffer size
6310  * @buff: dump buffer
6311  * @ret_buff_size: actual buffer size returned
6312  * @ret_next_table: next block to read
6313  * @ret_next_index: next index to read
6314  * @cmd_details: pointer to command details structure or NULL
6315  *
6316  * Dump internal FW/HW data for debug purposes.
6317  *
6318  **/
6319 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
6320                                 u8 table_id, u32 start_index, u16 buff_size,
6321                                 void *buff, u16 *ret_buff_size,
6322                                 u8 *ret_next_table, u32 *ret_next_index,
6323                                 struct i40e_asq_cmd_details *cmd_details)
6324 {
6325         struct i40e_aq_desc desc;
6326         struct i40e_aqc_debug_dump_internals *cmd =
6327                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6328         struct i40e_aqc_debug_dump_internals *resp =
6329                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6330         enum i40e_status_code status;
6331
6332         if (buff_size == 0 || !buff)
6333                 return I40E_ERR_PARAM;
6334
6335         i40e_fill_default_direct_cmd_desc(&desc,
6336                                           i40e_aqc_opc_debug_dump_internals);
6337         /* Indirect Command */
6338         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6339         if (buff_size > I40E_AQ_LARGE_BUF)
6340                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6341
6342         cmd->cluster_id = cluster_id;
6343         cmd->table_id = table_id;
6344         cmd->idx = CPU_TO_LE32(start_index);
6345
6346         desc.datalen = CPU_TO_LE16(buff_size);
6347
6348         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
6349         if (!status) {
6350                 if (ret_buff_size != NULL)
6351                         *ret_buff_size = LE16_TO_CPU(desc.datalen);
6352                 if (ret_next_table != NULL)
6353                         *ret_next_table = resp->table_id;
6354                 if (ret_next_index != NULL)
6355                         *ret_next_index = LE32_TO_CPU(resp->idx);
6356         }
6357
6358         return status;
6359 }
6360
6361 /**
6362  * i40e_read_bw_from_alt_ram
6363  * @hw: pointer to the hardware structure
6364  * @max_bw: pointer for max_bw read
6365  * @min_bw: pointer for min_bw read
6366  * @min_valid: pointer for bool that is true if min_bw is a valid value
6367  * @max_valid: pointer for bool that is true if max_bw is a valid value
6368  *
6369  * Read bw from the alternate ram for the given pf
6370  **/
6371 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
6372                                         u32 *max_bw, u32 *min_bw,
6373                                         bool *min_valid, bool *max_valid)
6374 {
6375         enum i40e_status_code status;
6376         u32 max_bw_addr, min_bw_addr;
6377
6378         /* Calculate the address of the min/max bw registers */
6379         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6380                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
6381                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6382         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6383                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
6384                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6385
6386         /* Read the bandwidths from alt ram */
6387         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
6388                                         min_bw_addr, min_bw);
6389
6390         if (*min_bw & I40E_ALT_BW_VALID_MASK)
6391                 *min_valid = true;
6392         else
6393                 *min_valid = false;
6394
6395         if (*max_bw & I40E_ALT_BW_VALID_MASK)
6396                 *max_valid = true;
6397         else
6398                 *max_valid = false;
6399
6400         return status;
6401 }
6402
6403 /**
6404  * i40e_aq_configure_partition_bw
6405  * @hw: pointer to the hardware structure
6406  * @bw_data: Buffer holding valid pfs and bw limits
6407  * @cmd_details: pointer to command details
6408  *
6409  * Configure partitions guaranteed/max bw
6410  **/
6411 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6412                         struct i40e_aqc_configure_partition_bw_data *bw_data,
6413                         struct i40e_asq_cmd_details *cmd_details)
6414 {
6415         enum i40e_status_code status;
6416         struct i40e_aq_desc desc;
6417         u16 bwd_size = sizeof(*bw_data);
6418
6419         i40e_fill_default_direct_cmd_desc(&desc,
6420                                 i40e_aqc_opc_configure_partition_bw);
6421
6422         /* Indirect command */
6423         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6424         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6425
6426         desc.datalen = CPU_TO_LE16(bwd_size);
6427
6428         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6429
6430         return status;
6431 }
6432
6433 /**
6434  * i40e_read_phy_register_clause22
6435  * @hw: pointer to the HW structure
6436  * @reg: register address in the page
6437  * @phy_addr: PHY address on MDIO interface
6438  * @value: PHY register value
6439  *
6440  * Reads specified PHY register value
6441  **/
6442 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
6443                                         u16 reg, u8 phy_addr, u16 *value)
6444 {
6445         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6446         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6447         u32 command = 0;
6448         u16 retry = 1000;
6449
6450         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6451                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6452                   (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
6453                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6454                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6455         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6456         do {
6457                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6458                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6459                         status = I40E_SUCCESS;
6460                         break;
6461                 }
6462                 i40e_usec_delay(10);
6463                 retry--;
6464         } while (retry);
6465
6466         if (status) {
6467                 i40e_debug(hw, I40E_DEBUG_PHY,
6468                            "PHY: Can't write command to external PHY.\n");
6469         } else {
6470                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6471                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6472                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6473         }
6474
6475         return status;
6476 }
6477
6478 /**
6479  * i40e_write_phy_register_clause22
6480  * @hw: pointer to the HW structure
6481  * @reg: register address in the page
6482  * @phy_addr: PHY address on MDIO interface
6483  * @value: PHY register value
6484  *
6485  * Writes specified PHY register value
6486  **/
6487 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6488                                         u16 reg, u8 phy_addr, u16 value)
6489 {
6490         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6491         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6492         u32 command  = 0;
6493         u16 retry = 1000;
6494
6495         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6496         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6497
6498         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6499                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6500                   (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6501                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6502                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6503
6504         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6505         do {
6506                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6507                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6508                         status = I40E_SUCCESS;
6509                         break;
6510                 }
6511                 i40e_usec_delay(10);
6512                 retry--;
6513         } while (retry);
6514
6515         return status;
6516 }
6517
6518 /**
6519  * i40e_read_phy_register_clause45
6520  * @hw: pointer to the HW structure
6521  * @page: registers page number
6522  * @reg: register address in the page
6523  * @phy_addr: PHY address on MDIO interface
6524  * @value: PHY register value
6525  *
6526  * Reads specified PHY register value
6527  **/
6528 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6529                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6530 {
6531         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6532         u32 command  = 0;
6533         u16 retry = 1000;
6534         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6535
6536         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6537                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6538                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6539                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6540                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6541                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6542                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6543         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6544         do {
6545                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6546                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6547                         status = I40E_SUCCESS;
6548                         break;
6549                 }
6550                 i40e_usec_delay(10);
6551                 retry--;
6552         } while (retry);
6553
6554         if (status) {
6555                 i40e_debug(hw, I40E_DEBUG_PHY,
6556                            "PHY: Can't write command to external PHY.\n");
6557                 goto phy_read_end;
6558         }
6559
6560         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6561                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6562                   (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6563                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6564                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6565                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6566         status = I40E_ERR_TIMEOUT;
6567         retry = 1000;
6568         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6569         do {
6570                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6571                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6572                         status = I40E_SUCCESS;
6573                         break;
6574                 }
6575                 i40e_usec_delay(10);
6576                 retry--;
6577         } while (retry);
6578
6579         if (!status) {
6580                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6581                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6582                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6583         } else {
6584                 i40e_debug(hw, I40E_DEBUG_PHY,
6585                            "PHY: Can't read register value from external PHY.\n");
6586         }
6587
6588 phy_read_end:
6589         return status;
6590 }
6591
6592 /**
6593  * i40e_write_phy_register_clause45
6594  * @hw: pointer to the HW structure
6595  * @page: registers page number
6596  * @reg: register address in the page
6597  * @phy_addr: PHY address on MDIO interface
6598  * @value: PHY register value
6599  *
6600  * Writes value to specified PHY register
6601  **/
6602 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6603                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6604 {
6605         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6606         u32 command  = 0;
6607         u16 retry = 1000;
6608         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6609
6610         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6611                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6612                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6613                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6614                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6615                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6616                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6617         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6618         do {
6619                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6620                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6621                         status = I40E_SUCCESS;
6622                         break;
6623                 }
6624                 i40e_usec_delay(10);
6625                 retry--;
6626         } while (retry);
6627         if (status) {
6628                 i40e_debug(hw, I40E_DEBUG_PHY,
6629                            "PHY: Can't write command to external PHY.\n");
6630                 goto phy_write_end;
6631         }
6632
6633         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6634         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6635
6636         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6637                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6638                   (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6639                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6640                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6641                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6642         status = I40E_ERR_TIMEOUT;
6643         retry = 1000;
6644         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6645         do {
6646                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6647                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6648                         status = I40E_SUCCESS;
6649                         break;
6650                 }
6651                 i40e_usec_delay(10);
6652                 retry--;
6653         } while (retry);
6654
6655 phy_write_end:
6656         return status;
6657 }
6658
6659 /**
6660  * i40e_write_phy_register
6661  * @hw: pointer to the HW structure
6662  * @page: registers page number
6663  * @reg: register address in the page
6664  * @phy_addr: PHY address on MDIO interface
6665  * @value: PHY register value
6666  *
6667  * Writes value to specified PHY register
6668  **/
6669 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6670                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6671 {
6672         enum i40e_status_code status;
6673
6674         switch (hw->device_id) {
6675         case I40E_DEV_ID_1G_BASE_T_X722:
6676                 status = i40e_write_phy_register_clause22(hw,
6677                         reg, phy_addr, value);
6678                 break;
6679         case I40E_DEV_ID_10G_BASE_T:
6680         case I40E_DEV_ID_10G_BASE_T4:
6681         case I40E_DEV_ID_10G_BASE_T_X722:
6682         case I40E_DEV_ID_25G_B:
6683         case I40E_DEV_ID_25G_SFP28:
6684                 status = i40e_write_phy_register_clause45(hw,
6685                         page, reg, phy_addr, value);
6686                 break;
6687         default:
6688                 status = I40E_ERR_UNKNOWN_PHY;
6689                 break;
6690         }
6691
6692         return status;
6693 }
6694
6695 /**
6696  * i40e_read_phy_register
6697  * @hw: pointer to the HW structure
6698  * @page: registers page number
6699  * @reg: register address in the page
6700  * @phy_addr: PHY address on MDIO interface
6701  * @value: PHY register value
6702  *
6703  * Reads specified PHY register value
6704  **/
6705 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6706                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6707 {
6708         enum i40e_status_code status;
6709
6710         switch (hw->device_id) {
6711         case I40E_DEV_ID_1G_BASE_T_X722:
6712                 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6713                                                          value);
6714                 break;
6715         case I40E_DEV_ID_10G_BASE_T:
6716         case I40E_DEV_ID_10G_BASE_T4:
6717         case I40E_DEV_ID_10G_BASE_T_X722:
6718         case I40E_DEV_ID_25G_B:
6719         case I40E_DEV_ID_25G_SFP28:
6720                 status = i40e_read_phy_register_clause45(hw, page, reg,
6721                                                          phy_addr, value);
6722                 break;
6723         default:
6724                 status = I40E_ERR_UNKNOWN_PHY;
6725                 break;
6726         }
6727
6728         return status;
6729 }
6730
6731 /**
6732  * i40e_get_phy_address
6733  * @hw: pointer to the HW structure
6734  * @dev_num: PHY port num that address we want
6735  *
6736  * Gets PHY address for current port
6737  **/
6738 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6739 {
6740         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6741         u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6742
6743         return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6744 }
6745
6746 /**
6747  * i40e_blink_phy_led
6748  * @hw: pointer to the HW structure
6749  * @time: time how long led will blinks in secs
6750  * @interval: gap between LED on and off in msecs
6751  *
6752  * Blinks PHY link LED
6753  **/
6754 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6755                                               u32 time, u32 interval)
6756 {
6757         enum i40e_status_code status = I40E_SUCCESS;
6758         u32 i;
6759         u16 led_ctl = 0;
6760         u16 gpio_led_port;
6761         u16 led_reg;
6762         u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6763         u8 phy_addr = 0;
6764         u8 port_num;
6765
6766         i = rd32(hw, I40E_PFGEN_PORTNUM);
6767         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6768         phy_addr = i40e_get_phy_address(hw, port_num);
6769
6770         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6771              led_addr++) {
6772                 status = i40e_read_phy_register_clause45(hw,
6773                                                          I40E_PHY_COM_REG_PAGE,
6774                                                          led_addr, phy_addr,
6775                                                          &led_reg);
6776                 if (status)
6777                         goto phy_blinking_end;
6778                 led_ctl = led_reg;
6779                 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6780                         led_reg = 0;
6781                         status = i40e_write_phy_register_clause45(hw,
6782                                                          I40E_PHY_COM_REG_PAGE,
6783                                                          led_addr, phy_addr,
6784                                                          led_reg);
6785                         if (status)
6786                                 goto phy_blinking_end;
6787                         break;
6788                 }
6789         }
6790
6791         if (time > 0 && interval > 0) {
6792                 for (i = 0; i < time * 1000; i += interval) {
6793                         status = i40e_read_phy_register_clause45(hw,
6794                                                 I40E_PHY_COM_REG_PAGE,
6795                                                 led_addr, phy_addr, &led_reg);
6796                         if (status)
6797                                 goto restore_config;
6798                         if (led_reg & I40E_PHY_LED_MANUAL_ON)
6799                                 led_reg = 0;
6800                         else
6801                                 led_reg = I40E_PHY_LED_MANUAL_ON;
6802                         status = i40e_write_phy_register_clause45(hw,
6803                                                 I40E_PHY_COM_REG_PAGE,
6804                                                 led_addr, phy_addr, led_reg);
6805                         if (status)
6806                                 goto restore_config;
6807                         i40e_msec_delay(interval);
6808                 }
6809         }
6810
6811 restore_config:
6812         status = i40e_write_phy_register_clause45(hw,
6813                                                   I40E_PHY_COM_REG_PAGE,
6814                                                   led_addr, phy_addr, led_ctl);
6815
6816 phy_blinking_end:
6817         return status;
6818 }
6819
6820 /**
6821  * i40e_led_get_reg - read LED register
6822  * @hw: pointer to the HW structure
6823  * @led_addr: LED register address
6824  * @reg_val: read register value
6825  **/
6826 static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr,
6827                                               u32 *reg_val)
6828 {
6829         enum i40e_status_code status;
6830         u8 phy_addr = 0;
6831
6832         *reg_val = 0;
6833         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6834                 status = i40e_aq_get_phy_register(hw,
6835                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6836                                                 I40E_PHY_COM_REG_PAGE, true,
6837                                                 I40E_PHY_LED_PROV_REG_1,
6838                                                 reg_val, NULL);
6839         } else {
6840                 phy_addr = i40e_get_phy_address(hw, hw->port);
6841                 status = i40e_read_phy_register_clause45(hw,
6842                                                          I40E_PHY_COM_REG_PAGE,
6843                                                          led_addr, phy_addr,
6844                                                          (u16 *)reg_val);
6845         }
6846         return status;
6847 }
6848
6849 /**
6850  * i40e_led_set_reg - write LED register
6851  * @hw: pointer to the HW structure
6852  * @led_addr: LED register address
6853  * @reg_val: register value to write
6854  **/
6855 static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr,
6856                                               u32 reg_val)
6857 {
6858         enum i40e_status_code status;
6859         u8 phy_addr = 0;
6860
6861         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6862                 status = i40e_aq_set_phy_register(hw,
6863                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6864                                                 I40E_PHY_COM_REG_PAGE, true,
6865                                                 I40E_PHY_LED_PROV_REG_1,
6866                                                 reg_val, NULL);
6867         } else {
6868                 phy_addr = i40e_get_phy_address(hw, hw->port);
6869                 status = i40e_write_phy_register_clause45(hw,
6870                                                           I40E_PHY_COM_REG_PAGE,
6871                                                           led_addr, phy_addr,
6872                                                           (u16)reg_val);
6873         }
6874
6875         return status;
6876 }
6877
6878 /**
6879  * i40e_led_get_phy - return current on/off mode
6880  * @hw: pointer to the hw struct
6881  * @led_addr: address of led register to use
6882  * @val: original value of register to use
6883  *
6884  **/
6885 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6886                                        u16 *val)
6887 {
6888         enum i40e_status_code status = I40E_SUCCESS;
6889         u16 gpio_led_port;
6890         u32 reg_val_aq;
6891         u16 temp_addr;
6892         u8 phy_addr = 0;
6893         u16 reg_val;
6894
6895         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6896                 status = i40e_aq_get_phy_register(hw,
6897                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6898                                                 I40E_PHY_COM_REG_PAGE, true,
6899                                                 I40E_PHY_LED_PROV_REG_1,
6900                                                 &reg_val_aq, NULL);
6901                 if (status == I40E_SUCCESS)
6902                         *val = (u16)reg_val_aq;
6903                 return status;
6904         }
6905         temp_addr = I40E_PHY_LED_PROV_REG_1;
6906         phy_addr = i40e_get_phy_address(hw, hw->port);
6907         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6908              temp_addr++) {
6909                 status = i40e_read_phy_register_clause45(hw,
6910                                                          I40E_PHY_COM_REG_PAGE,
6911                                                          temp_addr, phy_addr,
6912                                                          &reg_val);
6913                 if (status)
6914                         return status;
6915                 *val = reg_val;
6916                 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6917                         *led_addr = temp_addr;
6918                         break;
6919                 }
6920         }
6921         return status;
6922 }
6923
6924 /**
6925  * i40e_led_set_phy
6926  * @hw: pointer to the HW structure
6927  * @on: true or false
6928  * @led_addr: address of led register to use
6929  * @mode: original val plus bit for set or ignore
6930  *
6931  * Set led's on or off when controlled by the PHY
6932  *
6933  **/
6934 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6935                                        u16 led_addr, u32 mode)
6936 {
6937         enum i40e_status_code status = I40E_SUCCESS;
6938         u32 led_ctl = 0;
6939         u32 led_reg = 0;
6940
6941         status = i40e_led_get_reg(hw, led_addr, &led_reg);
6942         if (status)
6943                 return status;
6944         led_ctl = led_reg;
6945         if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6946                 led_reg = 0;
6947                 status = i40e_led_set_reg(hw, led_addr, led_reg);
6948                 if (status)
6949                         return status;
6950         }
6951         status = i40e_led_get_reg(hw, led_addr, &led_reg);
6952         if (status)
6953                 goto restore_config;
6954         if (on)
6955                 led_reg = I40E_PHY_LED_MANUAL_ON;
6956         else
6957                 led_reg = 0;
6958         status = i40e_led_set_reg(hw, led_addr, led_reg);
6959         if (status)
6960                 goto restore_config;
6961         if (mode & I40E_PHY_LED_MODE_ORIG) {
6962                 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6963                 status = i40e_led_set_reg(hw, led_addr, led_ctl);
6964         }
6965         return status;
6966
6967 restore_config:
6968         status = i40e_led_set_reg(hw, led_addr, led_ctl);
6969         return status;
6970 }
6971 #endif /* PF_DRIVER */
6972
6973 /**
6974  * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6975  * @hw: pointer to the hw struct
6976  * @reg_addr: register address
6977  * @reg_val: ptr to register value
6978  * @cmd_details: pointer to command details structure or NULL
6979  *
6980  * Use the firmware to read the Rx control register,
6981  * especially useful if the Rx unit is under heavy pressure
6982  **/
6983 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6984                                 u32 reg_addr, u32 *reg_val,
6985                                 struct i40e_asq_cmd_details *cmd_details)
6986 {
6987         struct i40e_aq_desc desc;
6988         struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
6989                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6990         enum i40e_status_code status;
6991
6992         if (reg_val == NULL)
6993                 return I40E_ERR_PARAM;
6994
6995         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
6996
6997         cmd_resp->address = CPU_TO_LE32(reg_addr);
6998
6999         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7000
7001         if (status == I40E_SUCCESS)
7002                 *reg_val = LE32_TO_CPU(cmd_resp->value);
7003
7004         return status;
7005 }
7006
7007 /**
7008  * i40e_read_rx_ctl - read from an Rx control register
7009  * @hw: pointer to the hw struct
7010  * @reg_addr: register address
7011  **/
7012 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
7013 {
7014         enum i40e_status_code status = I40E_SUCCESS;
7015         bool use_register;
7016         int retry = 5;
7017         u32 val = 0;
7018
7019         use_register = (((hw->aq.api_maj_ver == 1) &&
7020                         (hw->aq.api_min_ver < 5)) ||
7021                         (hw->mac.type == I40E_MAC_X722));
7022         if (!use_register) {
7023 do_retry:
7024                 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
7025                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
7026                         i40e_msec_delay(1);
7027                         retry--;
7028                         goto do_retry;
7029                 }
7030         }
7031
7032         /* if the AQ access failed, try the old-fashioned way */
7033         if (status || use_register)
7034                 val = rd32(hw, reg_addr);
7035
7036         return val;
7037 }
7038
7039 /**
7040  * i40e_aq_rx_ctl_write_register
7041  * @hw: pointer to the hw struct
7042  * @reg_addr: register address
7043  * @reg_val: register value
7044  * @cmd_details: pointer to command details structure or NULL
7045  *
7046  * Use the firmware to write to an Rx control register,
7047  * especially useful if the Rx unit is under heavy pressure
7048  **/
7049 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
7050                                 u32 reg_addr, u32 reg_val,
7051                                 struct i40e_asq_cmd_details *cmd_details)
7052 {
7053         struct i40e_aq_desc desc;
7054         struct i40e_aqc_rx_ctl_reg_read_write *cmd =
7055                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
7056         enum i40e_status_code status;
7057
7058         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
7059
7060         cmd->address = CPU_TO_LE32(reg_addr);
7061         cmd->value = CPU_TO_LE32(reg_val);
7062
7063         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7064
7065         return status;
7066 }
7067
7068 /**
7069  * i40e_write_rx_ctl - write to an Rx control register
7070  * @hw: pointer to the hw struct
7071  * @reg_addr: register address
7072  * @reg_val: register value
7073  **/
7074 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
7075 {
7076         enum i40e_status_code status = I40E_SUCCESS;
7077         bool use_register;
7078         int retry = 5;
7079
7080         use_register = (((hw->aq.api_maj_ver == 1) &&
7081                         (hw->aq.api_min_ver < 5)) ||
7082                         (hw->mac.type == I40E_MAC_X722));
7083         if (!use_register) {
7084 do_retry:
7085                 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
7086                                                        reg_val, NULL);
7087                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
7088                         i40e_msec_delay(1);
7089                         retry--;
7090                         goto do_retry;
7091                 }
7092         }
7093
7094         /* if the AQ access failed, try the old-fashioned way */
7095         if (status || use_register)
7096                 wr32(hw, reg_addr, reg_val);
7097 }
7098
7099 /**
7100  * i40e_aq_set_phy_register
7101  * @hw: pointer to the hw struct
7102  * @phy_select: select which phy should be accessed
7103  * @dev_addr: PHY device address
7104  * @page_change: enable auto page change
7105  * @reg_addr: PHY register address
7106  * @reg_val: new register value
7107  * @cmd_details: pointer to command details structure or NULL
7108  *
7109  * Write the external PHY register.
7110  **/
7111 enum i40e_status_code i40e_aq_set_phy_register(struct i40e_hw *hw,
7112                                 u8 phy_select, u8 dev_addr, bool page_change,
7113                                 u32 reg_addr, u32 reg_val,
7114                                 struct i40e_asq_cmd_details *cmd_details)
7115 {
7116         struct i40e_aq_desc desc;
7117         struct i40e_aqc_phy_register_access *cmd =
7118                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7119         enum i40e_status_code status;
7120
7121         i40e_fill_default_direct_cmd_desc(&desc,
7122                                           i40e_aqc_opc_set_phy_register);
7123
7124         cmd->phy_interface = phy_select;
7125         cmd->dev_addres = dev_addr;
7126         cmd->reg_address = CPU_TO_LE32(reg_addr);
7127         cmd->reg_value = CPU_TO_LE32(reg_val);
7128
7129         if (!page_change)
7130                 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
7131
7132         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7133
7134         return status;
7135 }
7136
7137 /**
7138  * i40e_aq_get_phy_register
7139  * @hw: pointer to the hw struct
7140  * @phy_select: select which phy should be accessed
7141  * @dev_addr: PHY device address
7142  * @page_change: enable auto page change
7143  * @reg_addr: PHY register address
7144  * @reg_val: read register value
7145  * @cmd_details: pointer to command details structure or NULL
7146  *
7147  * Read the external PHY register.
7148  **/
7149 enum i40e_status_code i40e_aq_get_phy_register(struct i40e_hw *hw,
7150                                 u8 phy_select, u8 dev_addr, bool page_change,
7151                                 u32 reg_addr, u32 *reg_val,
7152                                 struct i40e_asq_cmd_details *cmd_details)
7153 {
7154         struct i40e_aq_desc desc;
7155         struct i40e_aqc_phy_register_access *cmd =
7156                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7157         enum i40e_status_code status;
7158
7159         i40e_fill_default_direct_cmd_desc(&desc,
7160                                           i40e_aqc_opc_get_phy_register);
7161
7162         cmd->phy_interface = phy_select;
7163         cmd->dev_addres = dev_addr;
7164         cmd->reg_address = CPU_TO_LE32(reg_addr);
7165
7166         if (!page_change)
7167                 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
7168
7169         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7170         if (!status)
7171                 *reg_val = LE32_TO_CPU(cmd->reg_value);
7172
7173         return status;
7174 }
7175
7176 #ifdef VF_DRIVER
7177
7178 /**
7179  * i40e_aq_send_msg_to_pf
7180  * @hw: pointer to the hardware structure
7181  * @v_opcode: opcodes for VF-PF communication
7182  * @v_retval: return error code
7183  * @msg: pointer to the msg buffer
7184  * @msglen: msg length
7185  * @cmd_details: pointer to command details
7186  *
7187  * Send message to PF driver using admin queue. By default, this message
7188  * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
7189  * completion before returning.
7190  **/
7191 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
7192                                 enum virtchnl_ops v_opcode,
7193                                 enum i40e_status_code v_retval,
7194                                 u8 *msg, u16 msglen,
7195                                 struct i40e_asq_cmd_details *cmd_details)
7196 {
7197         struct i40e_aq_desc desc;
7198         struct i40e_asq_cmd_details details;
7199         enum i40e_status_code status;
7200
7201         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
7202         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
7203         desc.cookie_high = CPU_TO_LE32(v_opcode);
7204         desc.cookie_low = CPU_TO_LE32(v_retval);
7205         if (msglen) {
7206                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
7207                                                 | I40E_AQ_FLAG_RD));
7208                 if (msglen > I40E_AQ_LARGE_BUF)
7209                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7210                 desc.datalen = CPU_TO_LE16(msglen);
7211         }
7212         if (!cmd_details) {
7213                 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
7214                 details.async = true;
7215                 cmd_details = &details;
7216         }
7217         status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
7218                                        msglen, cmd_details);
7219         return status;
7220 }
7221
7222 /**
7223  * i40e_vf_parse_hw_config
7224  * @hw: pointer to the hardware structure
7225  * @msg: pointer to the virtual channel VF resource structure
7226  *
7227  * Given a VF resource message from the PF, populate the hw struct
7228  * with appropriate information.
7229  **/
7230 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
7231                              struct virtchnl_vf_resource *msg)
7232 {
7233         struct virtchnl_vsi_resource *vsi_res;
7234         int i;
7235
7236         vsi_res = &msg->vsi_res[0];
7237
7238         hw->dev_caps.num_vsis = msg->num_vsis;
7239         hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
7240         hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
7241         hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
7242         hw->dev_caps.dcb = msg->vf_cap_flags &
7243                            VIRTCHNL_VF_OFFLOAD_L2;
7244         hw->dev_caps.iwarp = (msg->vf_cap_flags &
7245                               VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
7246         for (i = 0; i < msg->num_vsis; i++) {
7247                 if (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) {
7248                         i40e_memcpy(hw->mac.perm_addr,
7249                                     vsi_res->default_mac_addr,
7250                                     ETH_ALEN,
7251                                     I40E_NONDMA_TO_NONDMA);
7252                         i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
7253                                     ETH_ALEN,
7254                                     I40E_NONDMA_TO_NONDMA);
7255                 }
7256                 vsi_res++;
7257         }
7258 }
7259
7260 /**
7261  * i40e_vf_reset
7262  * @hw: pointer to the hardware structure
7263  *
7264  * Send a VF_RESET message to the PF. Does not wait for response from PF
7265  * as none will be forthcoming. Immediately after calling this function,
7266  * the admin queue should be shut down and (optionally) reinitialized.
7267  **/
7268 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
7269 {
7270         return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF,
7271                                       I40E_SUCCESS, NULL, 0, NULL);
7272 }
7273 #endif /* VF_DRIVER */
7274
7275 /**
7276  * i40e_aq_set_arp_proxy_config
7277  * @hw: pointer to the HW structure
7278  * @proxy_config: pointer to proxy config command table struct
7279  * @cmd_details: pointer to command details
7280  *
7281  * Set ARP offload parameters from pre-populated
7282  * i40e_aqc_arp_proxy_data struct
7283  **/
7284 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
7285                                 struct i40e_aqc_arp_proxy_data *proxy_config,
7286                                 struct i40e_asq_cmd_details *cmd_details)
7287 {
7288         struct i40e_aq_desc desc;
7289         enum i40e_status_code status;
7290
7291         if (!proxy_config)
7292                 return I40E_ERR_PARAM;
7293
7294         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
7295
7296         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7297         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7298         desc.params.external.addr_high =
7299                                   CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
7300         desc.params.external.addr_low =
7301                                   CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
7302         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_arp_proxy_data));
7303
7304         status = i40e_asq_send_command(hw, &desc, proxy_config,
7305                                        sizeof(struct i40e_aqc_arp_proxy_data),
7306                                        cmd_details);
7307
7308         return status;
7309 }
7310
7311 /**
7312  * i40e_aq_opc_set_ns_proxy_table_entry
7313  * @hw: pointer to the HW structure
7314  * @ns_proxy_table_entry: pointer to NS table entry command struct
7315  * @cmd_details: pointer to command details
7316  *
7317  * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
7318  * from pre-populated i40e_aqc_ns_proxy_data struct
7319  **/
7320 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
7321                         struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
7322                         struct i40e_asq_cmd_details *cmd_details)
7323 {
7324         struct i40e_aq_desc desc;
7325         enum i40e_status_code status;
7326
7327         if (!ns_proxy_table_entry)
7328                 return I40E_ERR_PARAM;
7329
7330         i40e_fill_default_direct_cmd_desc(&desc,
7331                                 i40e_aqc_opc_set_ns_proxy_table_entry);
7332
7333         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7334         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7335         desc.params.external.addr_high =
7336                 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
7337         desc.params.external.addr_low =
7338                 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
7339         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_ns_proxy_data));
7340
7341         status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
7342                                        sizeof(struct i40e_aqc_ns_proxy_data),
7343                                        cmd_details);
7344
7345         return status;
7346 }
7347
7348 /**
7349  * i40e_aq_set_clear_wol_filter
7350  * @hw: pointer to the hw struct
7351  * @filter_index: index of filter to modify (0-7)
7352  * @filter: buffer containing filter to be set
7353  * @set_filter: true to set filter, false to clear filter
7354  * @no_wol_tco: if true, pass through packets cannot cause wake-up
7355  *              if false, pass through packets may cause wake-up
7356  * @filter_valid: true if filter action is valid
7357  * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
7358  * @cmd_details: pointer to command details structure or NULL
7359  *
7360  * Set or clear WoL filter for port attached to the PF
7361  **/
7362 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
7363                                 u8 filter_index,
7364                                 struct i40e_aqc_set_wol_filter_data *filter,
7365                                 bool set_filter, bool no_wol_tco,
7366                                 bool filter_valid, bool no_wol_tco_valid,
7367                                 struct i40e_asq_cmd_details *cmd_details)
7368 {
7369         struct i40e_aq_desc desc;
7370         struct i40e_aqc_set_wol_filter *cmd =
7371                 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
7372         enum i40e_status_code status;
7373         u16 cmd_flags = 0;
7374         u16 valid_flags = 0;
7375         u16 buff_len = 0;
7376
7377         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
7378
7379         if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
7380                 return  I40E_ERR_PARAM;
7381         cmd->filter_index = CPU_TO_LE16(filter_index);
7382
7383         if (set_filter) {
7384                 if (!filter)
7385                         return  I40E_ERR_PARAM;
7386
7387                 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
7388                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR;
7389         }
7390
7391         if (no_wol_tco)
7392                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
7393         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
7394
7395         if (filter_valid)
7396                 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
7397         if (no_wol_tco_valid)
7398                 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
7399         cmd->valid_flags = CPU_TO_LE16(valid_flags);
7400
7401         buff_len = sizeof(*filter);
7402         desc.datalen = CPU_TO_LE16(buff_len);
7403
7404         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7405         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7406
7407         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
7408         cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
7409
7410         status = i40e_asq_send_command(hw, &desc, filter,
7411                                        buff_len, cmd_details);
7412
7413         return status;
7414 }
7415
7416 /**
7417  * i40e_aq_get_wake_event_reason
7418  * @hw: pointer to the hw struct
7419  * @wake_reason: return value, index of matching filter
7420  * @cmd_details: pointer to command details structure or NULL
7421  *
7422  * Get information for the reason of a Wake Up event
7423  **/
7424 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
7425                                 u16 *wake_reason,
7426                                 struct i40e_asq_cmd_details *cmd_details)
7427 {
7428         struct i40e_aq_desc desc;
7429         struct i40e_aqc_get_wake_reason_completion *resp =
7430                 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
7431         enum i40e_status_code status;
7432
7433         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
7434
7435         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7436
7437         if (status == I40E_SUCCESS)
7438                 *wake_reason = LE16_TO_CPU(resp->wake_reason);
7439
7440         return status;
7441 }
7442
7443 /**
7444 * i40e_aq_clear_all_wol_filters
7445 * @hw: pointer to the hw struct
7446 * @cmd_details: pointer to command details structure or NULL
7447 *
7448 * Get information for the reason of a Wake Up event
7449 **/
7450 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw,
7451         struct i40e_asq_cmd_details *cmd_details)
7452 {
7453         struct i40e_aq_desc desc;
7454         enum i40e_status_code status;
7455
7456         i40e_fill_default_direct_cmd_desc(&desc,
7457                                           i40e_aqc_opc_clear_all_wol_filters);
7458
7459         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7460
7461         return status;
7462 }
7463
7464 /**
7465  * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
7466  * @hw: pointer to the hw struct
7467  * @buff: command buffer (size in bytes = buff_size)
7468  * @buff_size: buffer size in bytes
7469  * @track_id: package tracking id
7470  * @error_offset: returns error offset
7471  * @error_info: returns error information
7472  * @cmd_details: pointer to command details structure or NULL
7473  **/
7474 enum
7475 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
7476                                    u16 buff_size, u32 track_id,
7477                                    u32 *error_offset, u32 *error_info,
7478                                    struct i40e_asq_cmd_details *cmd_details)
7479 {
7480         struct i40e_aq_desc desc;
7481         struct i40e_aqc_write_personalization_profile *cmd =
7482                 (struct i40e_aqc_write_personalization_profile *)
7483                 &desc.params.raw;
7484         struct i40e_aqc_write_ddp_resp *resp;
7485         enum i40e_status_code status;
7486
7487         i40e_fill_default_direct_cmd_desc(&desc,
7488                                   i40e_aqc_opc_write_personalization_profile);
7489
7490         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
7491         if (buff_size > I40E_AQ_LARGE_BUF)
7492                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7493
7494         desc.datalen = CPU_TO_LE16(buff_size);
7495
7496         cmd->profile_track_id = CPU_TO_LE32(track_id);
7497
7498         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7499         if (!status) {
7500                 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
7501                 if (error_offset)
7502                         *error_offset = LE32_TO_CPU(resp->error_offset);
7503                 if (error_info)
7504                         *error_info = LE32_TO_CPU(resp->error_info);
7505         }
7506
7507         return status;
7508 }
7509
7510 /**
7511  * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
7512  * @hw: pointer to the hw struct
7513  * @buff: command buffer (size in bytes = buff_size)
7514  * @buff_size: buffer size in bytes
7515  * @flags: AdminQ command flags
7516  * @cmd_details: pointer to command details structure or NULL
7517  **/
7518 enum
7519 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
7520                                       u16 buff_size, u8 flags,
7521                                       struct i40e_asq_cmd_details *cmd_details)
7522 {
7523         struct i40e_aq_desc desc;
7524         struct i40e_aqc_get_applied_profiles *cmd =
7525                 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
7526         enum i40e_status_code status;
7527
7528         i40e_fill_default_direct_cmd_desc(&desc,
7529                           i40e_aqc_opc_get_personalization_profile_list);
7530
7531         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7532         if (buff_size > I40E_AQ_LARGE_BUF)
7533                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7534         desc.datalen = CPU_TO_LE16(buff_size);
7535
7536         cmd->flags = flags;
7537
7538         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7539
7540         return status;
7541 }
7542
7543 /**
7544  * i40e_find_segment_in_package
7545  * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
7546  * @pkg_hdr: pointer to the package header to be searched
7547  *
7548  * This function searches a package file for a particular segment type. On
7549  * success it returns a pointer to the segment header, otherwise it will
7550  * return NULL.
7551  **/
7552 struct i40e_generic_seg_header *
7553 i40e_find_segment_in_package(u32 segment_type,
7554                              struct i40e_package_header *pkg_hdr)
7555 {
7556         struct i40e_generic_seg_header *segment;
7557         u32 i;
7558
7559         /* Search all package segments for the requested segment type */
7560         for (i = 0; i < pkg_hdr->segment_count; i++) {
7561                 segment =
7562                         (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
7563                          pkg_hdr->segment_offset[i]);
7564
7565                 if (segment->type == segment_type)
7566                         return segment;
7567         }
7568
7569         return NULL;
7570 }
7571
7572 /* Get section table in profile */
7573 #define I40E_SECTION_TABLE(profile, sec_tbl)                            \
7574         do {                                                            \
7575                 struct i40e_profile_segment *p = (profile);             \
7576                 u32 count;                                              \
7577                 u32 *nvm;                                               \
7578                 count = p->device_table_count;                          \
7579                 nvm = (u32 *)&p->device_table[count];                   \
7580                 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \
7581         } while (0)
7582
7583 /* Get section header in profile */
7584 #define I40E_SECTION_HEADER(profile, offset)                            \
7585         (struct i40e_profile_section_header *)((u8 *)(profile) + (offset))
7586
7587 /**
7588  * i40e_find_section_in_profile
7589  * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE)
7590  * @profile: pointer to the i40e segment header to be searched
7591  *
7592  * This function searches i40e segment for a particular section type. On
7593  * success it returns a pointer to the section header, otherwise it will
7594  * return NULL.
7595  **/
7596 struct i40e_profile_section_header *
7597 i40e_find_section_in_profile(u32 section_type,
7598                              struct i40e_profile_segment *profile)
7599 {
7600         struct i40e_profile_section_header *sec;
7601         struct i40e_section_table *sec_tbl;
7602         u32 sec_off;
7603         u32 i;
7604
7605         if (profile->header.type != SEGMENT_TYPE_I40E)
7606                 return NULL;
7607
7608         I40E_SECTION_TABLE(profile, sec_tbl);
7609
7610         for (i = 0; i < sec_tbl->section_count; i++) {
7611                 sec_off = sec_tbl->section_offset[i];
7612                 sec = I40E_SECTION_HEADER(profile, sec_off);
7613                 if (sec->section.type == section_type)
7614                         return sec;
7615         }
7616
7617         return NULL;
7618 }
7619
7620 /**
7621  * i40e_ddp_exec_aq_section - Execute generic AQ for DDP
7622  * @hw: pointer to the hw struct
7623  * @aq: command buffer containing all data to execute AQ
7624  **/
7625 STATIC enum
7626 i40e_status_code i40e_ddp_exec_aq_section(struct i40e_hw *hw,
7627                                           struct i40e_profile_aq_section *aq)
7628 {
7629         enum i40e_status_code status;
7630         struct i40e_aq_desc desc;
7631         u8 *msg = NULL;
7632         u16 msglen;
7633
7634         i40e_fill_default_direct_cmd_desc(&desc, aq->opcode);
7635         desc.flags |= CPU_TO_LE16(aq->flags);
7636         i40e_memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw),
7637                     I40E_NONDMA_TO_NONDMA);
7638
7639         msglen = aq->datalen;
7640         if (msglen) {
7641                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
7642                                                 I40E_AQ_FLAG_RD));
7643                 if (msglen > I40E_AQ_LARGE_BUF)
7644                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7645                 desc.datalen = CPU_TO_LE16(msglen);
7646                 msg = &aq->data[0];
7647         }
7648
7649         status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL);
7650
7651         if (status != I40E_SUCCESS) {
7652                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7653                            "unable to exec DDP AQ opcode %u, error %d\n",
7654                            aq->opcode, status);
7655                 return status;
7656         }
7657
7658         /* copy returned desc to aq_buf */
7659         i40e_memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw),
7660                     I40E_NONDMA_TO_NONDMA);
7661
7662         return I40E_SUCCESS;
7663 }
7664
7665 /**
7666  * i40e_validate_profile
7667  * @hw: pointer to the hardware structure
7668  * @profile: pointer to the profile segment of the package to be validated
7669  * @track_id: package tracking id
7670  * @rollback: flag if the profile is for rollback.
7671  *
7672  * Validates supported devices and profile's sections.
7673  */
7674 STATIC enum i40e_status_code
7675 i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7676                       u32 track_id, bool rollback)
7677 {
7678         struct i40e_profile_section_header *sec = NULL;
7679         enum i40e_status_code status = I40E_SUCCESS;
7680         struct i40e_section_table *sec_tbl;
7681         u32 vendor_dev_id;
7682         u32 dev_cnt;
7683         u32 sec_off;
7684         u32 i;
7685
7686         if (track_id == I40E_DDP_TRACKID_INVALID) {
7687                 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n");
7688                 return I40E_NOT_SUPPORTED;
7689         }
7690
7691         dev_cnt = profile->device_table_count;
7692         for (i = 0; i < dev_cnt; i++) {
7693                 vendor_dev_id = profile->device_table[i].vendor_dev_id;
7694                 if ((vendor_dev_id >> 16) == I40E_INTEL_VENDOR_ID &&
7695                     hw->device_id == (vendor_dev_id & 0xFFFF))
7696                         break;
7697         }
7698         if (dev_cnt && (i == dev_cnt)) {
7699                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7700                            "Device doesn't support DDP\n");
7701                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
7702         }
7703
7704         I40E_SECTION_TABLE(profile, sec_tbl);
7705
7706         /* Validate sections types */
7707         for (i = 0; i < sec_tbl->section_count; i++) {
7708                 sec_off = sec_tbl->section_offset[i];
7709                 sec = I40E_SECTION_HEADER(profile, sec_off);
7710                 if (rollback) {
7711                         if (sec->section.type == SECTION_TYPE_MMIO ||
7712                             sec->section.type == SECTION_TYPE_AQ ||
7713                             sec->section.type == SECTION_TYPE_RB_AQ) {
7714                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7715                                            "Not a roll-back package\n");
7716                                 return I40E_NOT_SUPPORTED;
7717                         }
7718                 } else {
7719                         if (sec->section.type == SECTION_TYPE_RB_AQ ||
7720                             sec->section.type == SECTION_TYPE_RB_MMIO) {
7721                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7722                                            "Not an original package\n");
7723                                 return I40E_NOT_SUPPORTED;
7724                         }
7725                 }
7726         }
7727
7728         return status;
7729 }
7730
7731 /**
7732  * i40e_write_profile
7733  * @hw: pointer to the hardware structure
7734  * @profile: pointer to the profile segment of the package to be downloaded
7735  * @track_id: package tracking id
7736  *
7737  * Handles the download of a complete package.
7738  */
7739 enum i40e_status_code
7740 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7741                    u32 track_id)
7742 {
7743         enum i40e_status_code status = I40E_SUCCESS;
7744         struct i40e_section_table *sec_tbl;
7745         struct i40e_profile_section_header *sec = NULL;
7746         struct i40e_profile_aq_section *ddp_aq;
7747         u32 section_size = 0;
7748         u32 offset = 0, info = 0;
7749         u32 sec_off;
7750         u32 i;
7751
7752         status = i40e_validate_profile(hw, profile, track_id, false);
7753         if (status)
7754                 return status;
7755
7756         I40E_SECTION_TABLE(profile, sec_tbl);
7757
7758         for (i = 0; i < sec_tbl->section_count; i++) {
7759                 sec_off = sec_tbl->section_offset[i];
7760                 sec = I40E_SECTION_HEADER(profile, sec_off);
7761                 /* Process generic admin command */
7762                 if (sec->section.type == SECTION_TYPE_AQ) {
7763                         ddp_aq = (struct i40e_profile_aq_section *)&sec[1];
7764                         status = i40e_ddp_exec_aq_section(hw, ddp_aq);
7765                         if (status) {
7766                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7767                                            "Failed to execute aq: section %d, opcode %u\n",
7768                                            i, ddp_aq->opcode);
7769                                 break;
7770                         }
7771                         sec->section.type = SECTION_TYPE_RB_AQ;
7772                 }
7773
7774                 /* Skip any non-mmio sections */
7775                 if (sec->section.type != SECTION_TYPE_MMIO)
7776                         continue;
7777
7778                 section_size = sec->section.size +
7779                         sizeof(struct i40e_profile_section_header);
7780
7781                 /* Write MMIO section */
7782                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
7783                                            track_id, &offset, &info, NULL);
7784                 if (status) {
7785                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
7786                                    "Failed to write profile: section %d, offset %d, info %d\n",
7787                                    i, offset, info);
7788                         break;
7789                 }
7790         }
7791         return status;
7792 }
7793
7794 /**
7795  * i40e_rollback_profile
7796  * @hw: pointer to the hardware structure
7797  * @profile: pointer to the profile segment of the package to be removed
7798  * @track_id: package tracking id
7799  *
7800  * Rolls back previously loaded package.
7801  */
7802 enum i40e_status_code
7803 i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7804                       u32 track_id)
7805 {
7806         struct i40e_profile_section_header *sec = NULL;
7807         enum i40e_status_code status = I40E_SUCCESS;
7808         struct i40e_section_table *sec_tbl;
7809         u32 offset = 0, info = 0;
7810         u32 section_size = 0;
7811         u32 sec_off;
7812         int i;
7813
7814         status = i40e_validate_profile(hw, profile, track_id, true);
7815         if (status)
7816                 return status;
7817
7818         I40E_SECTION_TABLE(profile, sec_tbl);
7819
7820         /* For rollback write sections in reverse */
7821         for (i = sec_tbl->section_count - 1; i >= 0; i--) {
7822                 sec_off = sec_tbl->section_offset[i];
7823                 sec = I40E_SECTION_HEADER(profile, sec_off);
7824
7825                 /* Skip any non-rollback sections */
7826                 if (sec->section.type != SECTION_TYPE_RB_MMIO)
7827                         continue;
7828
7829                 section_size = sec->section.size +
7830                         sizeof(struct i40e_profile_section_header);
7831
7832                 /* Write roll-back MMIO section */
7833                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
7834                                            track_id, &offset, &info, NULL);
7835                 if (status) {
7836                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
7837                                    "Failed to write profile: section %d, offset %d, info %d\n",
7838                                    i, offset, info);
7839                         break;
7840                 }
7841         }
7842         return status;
7843 }
7844
7845 /**
7846  * i40e_add_pinfo_to_list
7847  * @hw: pointer to the hardware structure
7848  * @profile: pointer to the profile segment of the package
7849  * @profile_info_sec: buffer for information section
7850  * @track_id: package tracking id
7851  *
7852  * Register a profile to the list of loaded profiles.
7853  */
7854 enum i40e_status_code
7855 i40e_add_pinfo_to_list(struct i40e_hw *hw,
7856                        struct i40e_profile_segment *profile,
7857                        u8 *profile_info_sec, u32 track_id)
7858 {
7859         enum i40e_status_code status = I40E_SUCCESS;
7860         struct i40e_profile_section_header *sec = NULL;
7861         struct i40e_profile_info *pinfo;
7862         u32 offset = 0, info = 0;
7863
7864         sec = (struct i40e_profile_section_header *)profile_info_sec;
7865         sec->tbl_size = 1;
7866         sec->data_end = sizeof(struct i40e_profile_section_header) +
7867                         sizeof(struct i40e_profile_info);
7868         sec->section.type = SECTION_TYPE_INFO;
7869         sec->section.offset = sizeof(struct i40e_profile_section_header);
7870         sec->section.size = sizeof(struct i40e_profile_info);
7871         pinfo = (struct i40e_profile_info *)(profile_info_sec +
7872                                              sec->section.offset);
7873         pinfo->track_id = track_id;
7874         pinfo->version = profile->version;
7875         pinfo->op = I40E_DDP_ADD_TRACKID;
7876         i40e_memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE,
7877                     I40E_NONDMA_TO_NONDMA);
7878
7879         status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
7880                                    track_id, &offset, &info, NULL);
7881         return status;
7882 }