drivers/net/i40e/base/i40e_common.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "i40e_type.h"
  35 #include "i40e_adminq.h"
  36 #include "i40e_prototype.h"
  37 #include "i40e_virtchnl.h"
  38
  39
  40 /**
  41  * i40e_set_mac_type - Sets MAC type
  42  * @hw: pointer to the HW structure
  43  *
  44  * This function sets the mac type of the adapter based on the
  45  * vendor ID and device ID stored in the hw structure.
  46  **/
  47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  49 #else
  50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  51 #endif
  52 {
  53         enum i40e_status_code status = I40E_SUCCESS;
  54
  55         DEBUGFUNC("i40e_set_mac_type\n");
  56
  57         if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
  58                 switch (hw->device_id) {
  59                 case I40E_DEV_ID_SFP_XL710:
  60                 case I40E_DEV_ID_QEMU:
  61                 case I40E_DEV_ID_KX_B:
  62                 case I40E_DEV_ID_KX_C:
  63                 case I40E_DEV_ID_QSFP_A:
  64                 case I40E_DEV_ID_QSFP_B:
  65                 case I40E_DEV_ID_QSFP_C:
  66                 case I40E_DEV_ID_10G_BASE_T:
  67                 case I40E_DEV_ID_10G_BASE_T4:
  68                 case I40E_DEV_ID_20G_KR2:
  69                 case I40E_DEV_ID_20G_KR2_A:
  70                 case I40E_DEV_ID_25G_B:
  71                 case I40E_DEV_ID_25G_SFP28:
  72                         hw->mac.type = I40E_MAC_XL710;
  73                         break;
  74 #ifdef X722_SUPPORT
  75 #ifdef X722_A0_SUPPORT
  76                 case I40E_DEV_ID_X722_A0:
  77 #endif
  78                 case I40E_DEV_ID_KX_X722:
  79                 case I40E_DEV_ID_QSFP_X722:
  80                 case I40E_DEV_ID_SFP_X722:
  81                 case I40E_DEV_ID_1G_BASE_T_X722:
  82                 case I40E_DEV_ID_10G_BASE_T_X722:
  83                 case I40E_DEV_ID_SFP_I_X722:
  84                         hw->mac.type = I40E_MAC_X722;
  85                         break;
  86 #endif
  87 #ifdef X722_SUPPORT
  88 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  89                 case I40E_DEV_ID_X722_VF:
  90 #ifdef X722_A0_SUPPORT
  91                 case I40E_DEV_ID_X722_A0_VF:
  92 #endif
  93                         hw->mac.type = I40E_MAC_X722_VF;
  94                         break;
  95 #endif /* INTEGRATED_VF || VF_DRIVER */
  96 #endif /* X722_SUPPORT */
  97 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  98                 case I40E_DEV_ID_VF:
  99                 case I40E_DEV_ID_VF_HV:
 100                         hw->mac.type = I40E_MAC_VF;
 101                         break;
 102 #endif
 103                 default:
 104                         hw->mac.type = I40E_MAC_GENERIC;
 105                         break;
 106                 }
 107         } else {
 108                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
 109         }
 110
 111         DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
 112                   hw->mac.type, status);
 113         return status;
 114 }
 115
 116 #ifndef I40E_NDIS_SUPPORT
 117 /**
 118  * i40e_aq_str - convert AQ err code to a string
 119  * @hw: pointer to the HW structure
 120  * @aq_err: the AQ error code to convert
 121  **/
 122 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
 123 {
 124         switch (aq_err) {
 125         case I40E_AQ_RC_OK:
 126                 return "OK";
 127         case I40E_AQ_RC_EPERM:
 128                 return "I40E_AQ_RC_EPERM";
 129         case I40E_AQ_RC_ENOENT:
 130                 return "I40E_AQ_RC_ENOENT";
 131         case I40E_AQ_RC_ESRCH:
 132                 return "I40E_AQ_RC_ESRCH";
 133         case I40E_AQ_RC_EINTR:
 134                 return "I40E_AQ_RC_EINTR";
 135         case I40E_AQ_RC_EIO:
 136                 return "I40E_AQ_RC_EIO";
 137         case I40E_AQ_RC_ENXIO:
 138                 return "I40E_AQ_RC_ENXIO";
 139         case I40E_AQ_RC_E2BIG:
 140                 return "I40E_AQ_RC_E2BIG";
 141         case I40E_AQ_RC_EAGAIN:
 142                 return "I40E_AQ_RC_EAGAIN";
 143         case I40E_AQ_RC_ENOMEM:
 144                 return "I40E_AQ_RC_ENOMEM";
 145         case I40E_AQ_RC_EACCES:
 146                 return "I40E_AQ_RC_EACCES";
 147         case I40E_AQ_RC_EFAULT:
 148                 return "I40E_AQ_RC_EFAULT";
 149         case I40E_AQ_RC_EBUSY:
 150                 return "I40E_AQ_RC_EBUSY";
 151         case I40E_AQ_RC_EEXIST:
 152                 return "I40E_AQ_RC_EEXIST";
 153         case I40E_AQ_RC_EINVAL:
 154                 return "I40E_AQ_RC_EINVAL";
 155         case I40E_AQ_RC_ENOTTY:
 156                 return "I40E_AQ_RC_ENOTTY";
 157         case I40E_AQ_RC_ENOSPC:
 158                 return "I40E_AQ_RC_ENOSPC";
 159         case I40E_AQ_RC_ENOSYS:
 160                 return "I40E_AQ_RC_ENOSYS";
 161         case I40E_AQ_RC_ERANGE:
 162                 return "I40E_AQ_RC_ERANGE";
 163         case I40E_AQ_RC_EFLUSHED:
 164                 return "I40E_AQ_RC_EFLUSHED";
 165         case I40E_AQ_RC_BAD_ADDR:
 166                 return "I40E_AQ_RC_BAD_ADDR";
 167         case I40E_AQ_RC_EMODE:
 168                 return "I40E_AQ_RC_EMODE";
 169         case I40E_AQ_RC_EFBIG:
 170                 return "I40E_AQ_RC_EFBIG";
 171         }
 172
 173         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 174         return hw->err_str;
 175 }
 176
 177 /**
 178  * i40e_stat_str - convert status err code to a string
 179  * @hw: pointer to the HW structure
 180  * @stat_err: the status error code to convert
 181  **/
 182 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
 183 {
 184         switch (stat_err) {
 185         case I40E_SUCCESS:
 186                 return "OK";
 187         case I40E_ERR_NVM:
 188                 return "I40E_ERR_NVM";
 189         case I40E_ERR_NVM_CHECKSUM:
 190                 return "I40E_ERR_NVM_CHECKSUM";
 191         case I40E_ERR_PHY:
 192                 return "I40E_ERR_PHY";
 193         case I40E_ERR_CONFIG:
 194                 return "I40E_ERR_CONFIG";
 195         case I40E_ERR_PARAM:
 196                 return "I40E_ERR_PARAM";
 197         case I40E_ERR_MAC_TYPE:
 198                 return "I40E_ERR_MAC_TYPE";
 199         case I40E_ERR_UNKNOWN_PHY:
 200                 return "I40E_ERR_UNKNOWN_PHY";
 201         case I40E_ERR_LINK_SETUP:
 202                 return "I40E_ERR_LINK_SETUP";
 203         case I40E_ERR_ADAPTER_STOPPED:
 204                 return "I40E_ERR_ADAPTER_STOPPED";
 205         case I40E_ERR_INVALID_MAC_ADDR:
 206                 return "I40E_ERR_INVALID_MAC_ADDR";
 207         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 208                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 209         case I40E_ERR_MASTER_REQUESTS_PENDING:
 210                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 211         case I40E_ERR_INVALID_LINK_SETTINGS:
 212                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 213         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 214                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 215         case I40E_ERR_RESET_FAILED:
 216                 return "I40E_ERR_RESET_FAILED";
 217         case I40E_ERR_SWFW_SYNC:
 218                 return "I40E_ERR_SWFW_SYNC";
 219         case I40E_ERR_NO_AVAILABLE_VSI:
 220                 return "I40E_ERR_NO_AVAILABLE_VSI";
 221         case I40E_ERR_NO_MEMORY:
 222                 return "I40E_ERR_NO_MEMORY";
 223         case I40E_ERR_BAD_PTR:
 224                 return "I40E_ERR_BAD_PTR";
 225         case I40E_ERR_RING_FULL:
 226                 return "I40E_ERR_RING_FULL";
 227         case I40E_ERR_INVALID_PD_ID:
 228                 return "I40E_ERR_INVALID_PD_ID";
 229         case I40E_ERR_INVALID_QP_ID:
 230                 return "I40E_ERR_INVALID_QP_ID";
 231         case I40E_ERR_INVALID_CQ_ID:
 232                 return "I40E_ERR_INVALID_CQ_ID";
 233         case I40E_ERR_INVALID_CEQ_ID:
 234                 return "I40E_ERR_INVALID_CEQ_ID";
 235         case I40E_ERR_INVALID_AEQ_ID:
 236                 return "I40E_ERR_INVALID_AEQ_ID";
 237         case I40E_ERR_INVALID_SIZE:
 238                 return "I40E_ERR_INVALID_SIZE";
 239         case I40E_ERR_INVALID_ARP_INDEX:
 240                 return "I40E_ERR_INVALID_ARP_INDEX";
 241         case I40E_ERR_INVALID_FPM_FUNC_ID:
 242                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 243         case I40E_ERR_QP_INVALID_MSG_SIZE:
 244                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 245         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 246                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 247         case I40E_ERR_INVALID_FRAG_COUNT:
 248                 return "I40E_ERR_INVALID_FRAG_COUNT";
 249         case I40E_ERR_QUEUE_EMPTY:
 250                 return "I40E_ERR_QUEUE_EMPTY";
 251         case I40E_ERR_INVALID_ALIGNMENT:
 252                 return "I40E_ERR_INVALID_ALIGNMENT";
 253         case I40E_ERR_FLUSHED_QUEUE:
 254                 return "I40E_ERR_FLUSHED_QUEUE";
 255         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 256                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 257         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 258                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 259         case I40E_ERR_TIMEOUT:
 260                 return "I40E_ERR_TIMEOUT";
 261         case I40E_ERR_OPCODE_MISMATCH:
 262                 return "I40E_ERR_OPCODE_MISMATCH";
 263         case I40E_ERR_CQP_COMPL_ERROR:
 264                 return "I40E_ERR_CQP_COMPL_ERROR";
 265         case I40E_ERR_INVALID_VF_ID:
 266                 return "I40E_ERR_INVALID_VF_ID";
 267         case I40E_ERR_INVALID_HMCFN_ID:
 268                 return "I40E_ERR_INVALID_HMCFN_ID";
 269         case I40E_ERR_BACKING_PAGE_ERROR:
 270                 return "I40E_ERR_BACKING_PAGE_ERROR";
 271         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 272                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 273         case I40E_ERR_INVALID_PBLE_INDEX:
 274                 return "I40E_ERR_INVALID_PBLE_INDEX";
 275         case I40E_ERR_INVALID_SD_INDEX:
 276                 return "I40E_ERR_INVALID_SD_INDEX";
 277         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 278                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 279         case I40E_ERR_INVALID_SD_TYPE:
 280                 return "I40E_ERR_INVALID_SD_TYPE";
 281         case I40E_ERR_MEMCPY_FAILED:
 282                 return "I40E_ERR_MEMCPY_FAILED";
 283         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 284                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 285         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 286                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 287         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 288                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 289         case I40E_ERR_SRQ_ENABLED:
 290                 return "I40E_ERR_SRQ_ENABLED";
 291         case I40E_ERR_ADMIN_QUEUE_ERROR:
 292                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 293         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 294                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 295         case I40E_ERR_BUF_TOO_SHORT:
 296                 return "I40E_ERR_BUF_TOO_SHORT";
 297         case I40E_ERR_ADMIN_QUEUE_FULL:
 298                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 299         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 300                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 301         case I40E_ERR_BAD_IWARP_CQE:
 302                 return "I40E_ERR_BAD_IWARP_CQE";
 303         case I40E_ERR_NVM_BLANK_MODE:
 304                 return "I40E_ERR_NVM_BLANK_MODE";
 305         case I40E_ERR_NOT_IMPLEMENTED:
 306                 return "I40E_ERR_NOT_IMPLEMENTED";
 307         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 308                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 309         case I40E_ERR_DIAG_TEST_FAILED:
 310                 return "I40E_ERR_DIAG_TEST_FAILED";
 311         case I40E_ERR_NOT_READY:
 312                 return "I40E_ERR_NOT_READY";
 313         case I40E_NOT_SUPPORTED:
 314                 return "I40E_NOT_SUPPORTED";
 315         case I40E_ERR_FIRMWARE_API_VERSION:
 316                 return "I40E_ERR_FIRMWARE_API_VERSION";
 317         }
 318
 319         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 320         return hw->err_str;
 321 }
 322
 323 #endif /* I40E_NDIS_SUPPORT */
 324 /**
 325  * i40e_debug_aq
 326  * @hw: debug mask related to admin queue
 327  * @mask: debug mask
 328  * @desc: pointer to admin queue descriptor
 329  * @buffer: pointer to command buffer
 330  * @buf_len: max length of buffer
 331  *
 332  * Dumps debug log about adminq command with descriptor contents.
 333  **/
 334 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 335                    void *buffer, u16 buf_len)
 336 {
 337         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 338         u16 len = LE16_TO_CPU(aq_desc->datalen);
 339         u8 *buf = (u8 *)buffer;
 340         u16 i = 0;
 341
 342         if ((!(mask & hw->debug_mask)) || (desc == NULL))
 343                 return;
 344
 345         i40e_debug(hw, mask,
 346                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 347                    LE16_TO_CPU(aq_desc->opcode),
 348                    LE16_TO_CPU(aq_desc->flags),
 349                    LE16_TO_CPU(aq_desc->datalen),
 350                    LE16_TO_CPU(aq_desc->retval));
 351         i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
 352                    LE32_TO_CPU(aq_desc->cookie_high),
 353                    LE32_TO_CPU(aq_desc->cookie_low));
 354         i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
 355                    LE32_TO_CPU(aq_desc->params.internal.param0),
 356                    LE32_TO_CPU(aq_desc->params.internal.param1));
 357         i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
 358                    LE32_TO_CPU(aq_desc->params.external.addr_high),
 359                    LE32_TO_CPU(aq_desc->params.external.addr_low));
 360
 361         if ((buffer != NULL) && (aq_desc->datalen != 0)) {
 362                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 363                 if (buf_len < len)
 364                         len = buf_len;
 365                 /* write the full 16-byte chunks */
 366                 for (i = 0; i < (len - 16); i += 16)
 367                         i40e_debug(hw, mask,
 368                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 369                                    i, buf[i], buf[i+1], buf[i+2], buf[i+3],
 370                                    buf[i+4], buf[i+5], buf[i+6], buf[i+7],
 371                                    buf[i+8], buf[i+9], buf[i+10], buf[i+11],
 372                                    buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
 373                 /* the most we could have left is 16 bytes, pad with zeros */
 374                 if (i < len) {
 375                         char d_buf[16];
 376                         int j, i_sav;
 377
 378                         i_sav = i;
 379                         memset(d_buf, 0, sizeof(d_buf));
 380                         for (j = 0; i < len; j++, i++)
 381                                 d_buf[j] = buf[i];
 382                         i40e_debug(hw, mask,
 383                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 384                                    i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
 385                                    d_buf[4], d_buf[5], d_buf[6], d_buf[7],
 386                                    d_buf[8], d_buf[9], d_buf[10], d_buf[11],
 387                                    d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
 388                 }
 389         }
 390 }
 391
 392 /**
 393  * i40e_check_asq_alive
 394  * @hw: pointer to the hw struct
 395  *
 396  * Returns true if Queue is enabled else false.
 397  **/
 398 bool i40e_check_asq_alive(struct i40e_hw *hw)
 399 {
 400         if (hw->aq.asq.len)
 401 #ifdef PF_DRIVER
 402 #ifdef INTEGRATED_VF
 403                 if (!i40e_is_vf(hw))
 404                         return !!(rd32(hw, hw->aq.asq.len) &
 405                                 I40E_PF_ATQLEN_ATQENABLE_MASK);
 406 #else
 407                 return !!(rd32(hw, hw->aq.asq.len) &
 408                         I40E_PF_ATQLEN_ATQENABLE_MASK);
 409 #endif /* INTEGRATED_VF */
 410 #endif /* PF_DRIVER */
 411 #ifdef VF_DRIVER
 412 #ifdef INTEGRATED_VF
 413                 if (i40e_is_vf(hw))
 414                         return !!(rd32(hw, hw->aq.asq.len) &
 415                                 I40E_VF_ATQLEN1_ATQENABLE_MASK);
 416 #else
 417                 return !!(rd32(hw, hw->aq.asq.len) &
 418                         I40E_VF_ATQLEN1_ATQENABLE_MASK);
 419 #endif /* INTEGRATED_VF */
 420 #endif /* VF_DRIVER */
 421         return false;
 422 }
 423
 424 /**
 425  * i40e_aq_queue_shutdown
 426  * @hw: pointer to the hw struct
 427  * @unloading: is the driver unloading itself
 428  *
 429  * Tell the Firmware that we're shutting down the AdminQ and whether
 430  * or not the driver is unloading as well.
 431  **/
 432 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
 433                                              bool unloading)
 434 {
 435         struct i40e_aq_desc desc;
 436         struct i40e_aqc_queue_shutdown *cmd =
 437                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 438         enum i40e_status_code status;
 439
 440         i40e_fill_default_direct_cmd_desc(&desc,
 441                                           i40e_aqc_opc_queue_shutdown);
 442
 443         if (unloading)
 444                 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
 445         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 446
 447         return status;
 448 }
 449 #ifdef X722_SUPPORT
 450
 451 /**
 452  * i40e_aq_get_set_rss_lut
 453  * @hw: pointer to the hardware structure
 454  * @vsi_id: vsi fw index
 455  * @pf_lut: for PF table set true, for VSI table set false
 456  * @lut: pointer to the lut buffer provided by the caller
 457  * @lut_size: size of the lut buffer
 458  * @set: set true to set the table, false to get the table
 459  *
 460  * Internal function to get or set RSS look up table
 461  **/
 462 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 463                                                      u16 vsi_id, bool pf_lut,
 464                                                      u8 *lut, u16 lut_size,
 465                                                      bool set)
 466 {
 467         enum i40e_status_code status;
 468         struct i40e_aq_desc desc;
 469         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 470                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 471
 472         if (set)
 473                 i40e_fill_default_direct_cmd_desc(&desc,
 474                                                   i40e_aqc_opc_set_rss_lut);
 475         else
 476                 i40e_fill_default_direct_cmd_desc(&desc,
 477                                                   i40e_aqc_opc_get_rss_lut);
 478
 479         /* Indirect command */
 480         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 481         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 482
 483         cmd_resp->vsi_id =
 484                         CPU_TO_LE16((u16)((vsi_id <<
 485                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 486                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 487         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 488
 489         if (pf_lut)
 490                 cmd_resp->flags |= CPU_TO_LE16((u16)
 491                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 492                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 493                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 494         else
 495                 cmd_resp->flags |= CPU_TO_LE16((u16)
 496                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 497                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 498                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 499
 500         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 501
 502         return status;
 503 }
 504
 505 /**
 506  * i40e_aq_get_rss_lut
 507  * @hw: pointer to the hardware structure
 508  * @vsi_id: vsi fw index
 509  * @pf_lut: for PF table set true, for VSI table set false
 510  * @lut: pointer to the lut buffer provided by the caller
 511  * @lut_size: size of the lut buffer
 512  *
 513  * get the RSS lookup table, PF or VSI type
 514  **/
 515 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 516                                           bool pf_lut, u8 *lut, u16 lut_size)
 517 {
 518         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 519                                        false);
 520 }
 521
 522 /**
 523  * i40e_aq_set_rss_lut
 524  * @hw: pointer to the hardware structure
 525  * @vsi_id: vsi fw index
 526  * @pf_lut: for PF table set true, for VSI table set false
 527  * @lut: pointer to the lut buffer provided by the caller
 528  * @lut_size: size of the lut buffer
 529  *
 530  * set the RSS lookup table, PF or VSI type
 531  **/
 532 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 533                                           bool pf_lut, u8 *lut, u16 lut_size)
 534 {
 535         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
 536 }
 537
 538 /**
 539  * i40e_aq_get_set_rss_key
 540  * @hw: pointer to the hw struct
 541  * @vsi_id: vsi fw index
 542  * @key: pointer to key info struct
 543  * @set: set true to set the key, false to get the key
 544  *
 545  * get the RSS key per VSI
 546  **/
 547 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 548                                       u16 vsi_id,
 549                                       struct i40e_aqc_get_set_rss_key_data *key,
 550                                       bool set)
 551 {
 552         enum i40e_status_code status;
 553         struct i40e_aq_desc desc;
 554         struct i40e_aqc_get_set_rss_key *cmd_resp =
 555                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 556         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 557
 558         if (set)
 559                 i40e_fill_default_direct_cmd_desc(&desc,
 560                                                   i40e_aqc_opc_set_rss_key);
 561         else
 562                 i40e_fill_default_direct_cmd_desc(&desc,
 563                                                   i40e_aqc_opc_get_rss_key);
 564
 565         /* Indirect command */
 566         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 567         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 568
 569         cmd_resp->vsi_id =
 570                         CPU_TO_LE16((u16)((vsi_id <<
 571                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 572                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 573         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 574
 575         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 576
 577         return status;
 578 }
 579
 580 /**
 581  * i40e_aq_get_rss_key
 582  * @hw: pointer to the hw struct
 583  * @vsi_id: vsi fw index
 584  * @key: pointer to key info struct
 585  *
 586  **/
 587 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
 588                                       u16 vsi_id,
 589                                       struct i40e_aqc_get_set_rss_key_data *key)
 590 {
 591         return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
 592 }
 593
 594 /**
 595  * i40e_aq_set_rss_key
 596  * @hw: pointer to the hw struct
 597  * @vsi_id: vsi fw index
 598  * @key: pointer to key info struct
 599  *
 600  * set the RSS key per VSI
 601  **/
 602 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
 603                                       u16 vsi_id,
 604                                       struct i40e_aqc_get_set_rss_key_data *key)
 605 {
 606         return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
 607 }
 608 #endif /* X722_SUPPORT */
 609
 610 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 611  * hardware to a bit-field that can be used by SW to more easily determine the
 612  * packet type.
 613  *
 614  * Macros are used to shorten the table lines and make this table human
 615  * readable.
 616  *
 617  * We store the PTYPE in the top byte of the bit field - this is just so that
 618  * we can check that the table doesn't have a row missing, as the index into
 619  * the table should be the PTYPE.
 620  *
 621  * Typical work flow:
 622  *
 623  * IF NOT i40e_ptype_lookup[ptype].known
 624  * THEN
 625  *      Packet is unknown
 626  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 627  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 628  * ELSE
 629  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 630  * ENDIF
 631  */
 632
 633 /* macro to make the table lines short */
 634 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 635         {       PTYPE, \
 636                 1, \
 637                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 638                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 639                 I40E_RX_PTYPE_##OUTER_FRAG, \
 640                 I40E_RX_PTYPE_TUNNEL_##T, \
 641                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 642                 I40E_RX_PTYPE_##TEF, \
 643                 I40E_RX_PTYPE_INNER_PROT_##I, \
 644                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 645
 646 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 647                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 648
 649 /* shorter macros makes the table fit but are terse */
 650 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 651 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 652 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 653
 654 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 655 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 656         /* L2 Packet types */
 657         I40E_PTT_UNUSED_ENTRY(0),
 658         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 659         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 660         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 661         I40E_PTT_UNUSED_ENTRY(4),
 662         I40E_PTT_UNUSED_ENTRY(5),
 663         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 664         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 665         I40E_PTT_UNUSED_ENTRY(8),
 666         I40E_PTT_UNUSED_ENTRY(9),
 667         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 668         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 669         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 670         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 671         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 672         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 673         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 674         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 675         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 676         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 677         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 678         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 679
 680         /* Non Tunneled IPv4 */
 681         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 682         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 683         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 684         I40E_PTT_UNUSED_ENTRY(25),
 685         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 686         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 687         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 688
 689         /* IPv4 --> IPv4 */
 690         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 691         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 692         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 693         I40E_PTT_UNUSED_ENTRY(32),
 694         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 695         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 696         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 697
 698         /* IPv4 --> IPv6 */
 699         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 700         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 701         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 702         I40E_PTT_UNUSED_ENTRY(39),
 703         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 704         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 705         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 706
 707         /* IPv4 --> GRE/NAT */
 708         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 709
 710         /* IPv4 --> GRE/NAT --> IPv4 */
 711         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 712         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 713         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 714         I40E_PTT_UNUSED_ENTRY(47),
 715         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 716         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 717         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 718
 719         /* IPv4 --> GRE/NAT --> IPv6 */
 720         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 721         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 722         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 723         I40E_PTT_UNUSED_ENTRY(54),
 724         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 725         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 726         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 727
 728         /* IPv4 --> GRE/NAT --> MAC */
 729         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 730
 731         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 732         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 733         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 734         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 735         I40E_PTT_UNUSED_ENTRY(62),
 736         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 737         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 738         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 739
 740         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 741         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 742         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 743         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 744         I40E_PTT_UNUSED_ENTRY(69),
 745         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 746         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 747         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 748
 749         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 750         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 751
 752         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 753         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 754         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 755         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 756         I40E_PTT_UNUSED_ENTRY(77),
 757         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 758         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 759         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 760
 761         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 762         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 763         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 764         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 765         I40E_PTT_UNUSED_ENTRY(84),
 766         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 767         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 768         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 769
 770         /* Non Tunneled IPv6 */
 771         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 772         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 773         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
 774         I40E_PTT_UNUSED_ENTRY(91),
 775         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 776         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 777         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 778
 779         /* IPv6 --> IPv4 */
 780         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 781         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 782         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 783         I40E_PTT_UNUSED_ENTRY(98),
 784         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 785         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 786         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 787
 788         /* IPv6 --> IPv6 */
 789         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 790         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 791         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 792         I40E_PTT_UNUSED_ENTRY(105),
 793         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 794         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 795         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 796
 797         /* IPv6 --> GRE/NAT */
 798         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 799
 800         /* IPv6 --> GRE/NAT -> IPv4 */
 801         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 802         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 803         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 804         I40E_PTT_UNUSED_ENTRY(113),
 805         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 806         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 807         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 808
 809         /* IPv6 --> GRE/NAT -> IPv6 */
 810         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 811         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 812         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 813         I40E_PTT_UNUSED_ENTRY(120),
 814         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 815         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 816         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 817
 818         /* IPv6 --> GRE/NAT -> MAC */
 819         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 820
 821         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 822         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 823         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 824         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 825         I40E_PTT_UNUSED_ENTRY(128),
 826         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 827         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 828         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 829
 830         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 831         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 832         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 833         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 834         I40E_PTT_UNUSED_ENTRY(135),
 835         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 836         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 837         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 838
 839         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 840         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 841
 842         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 843         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 844         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 845         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 846         I40E_PTT_UNUSED_ENTRY(143),
 847         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 848         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 849         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 850
 851         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 852         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 853         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 854         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 855         I40E_PTT_UNUSED_ENTRY(150),
 856         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 857         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 858         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 859
 860         /* unused entries */
 861         I40E_PTT_UNUSED_ENTRY(154),
 862         I40E_PTT_UNUSED_ENTRY(155),
 863         I40E_PTT_UNUSED_ENTRY(156),
 864         I40E_PTT_UNUSED_ENTRY(157),
 865         I40E_PTT_UNUSED_ENTRY(158),
 866         I40E_PTT_UNUSED_ENTRY(159),
 867
 868         I40E_PTT_UNUSED_ENTRY(160),
 869         I40E_PTT_UNUSED_ENTRY(161),
 870         I40E_PTT_UNUSED_ENTRY(162),
 871         I40E_PTT_UNUSED_ENTRY(163),
 872         I40E_PTT_UNUSED_ENTRY(164),
 873         I40E_PTT_UNUSED_ENTRY(165),
 874         I40E_PTT_UNUSED_ENTRY(166),
 875         I40E_PTT_UNUSED_ENTRY(167),
 876         I40E_PTT_UNUSED_ENTRY(168),
 877         I40E_PTT_UNUSED_ENTRY(169),
 878
 879         I40E_PTT_UNUSED_ENTRY(170),
 880         I40E_PTT_UNUSED_ENTRY(171),
 881         I40E_PTT_UNUSED_ENTRY(172),
 882         I40E_PTT_UNUSED_ENTRY(173),
 883         I40E_PTT_UNUSED_ENTRY(174),
 884         I40E_PTT_UNUSED_ENTRY(175),
 885         I40E_PTT_UNUSED_ENTRY(176),
 886         I40E_PTT_UNUSED_ENTRY(177),
 887         I40E_PTT_UNUSED_ENTRY(178),
 888         I40E_PTT_UNUSED_ENTRY(179),
 889
 890         I40E_PTT_UNUSED_ENTRY(180),
 891         I40E_PTT_UNUSED_ENTRY(181),
 892         I40E_PTT_UNUSED_ENTRY(182),
 893         I40E_PTT_UNUSED_ENTRY(183),
 894         I40E_PTT_UNUSED_ENTRY(184),
 895         I40E_PTT_UNUSED_ENTRY(185),
 896         I40E_PTT_UNUSED_ENTRY(186),
 897         I40E_PTT_UNUSED_ENTRY(187),
 898         I40E_PTT_UNUSED_ENTRY(188),
 899         I40E_PTT_UNUSED_ENTRY(189),
 900
 901         I40E_PTT_UNUSED_ENTRY(190),
 902         I40E_PTT_UNUSED_ENTRY(191),
 903         I40E_PTT_UNUSED_ENTRY(192),
 904         I40E_PTT_UNUSED_ENTRY(193),
 905         I40E_PTT_UNUSED_ENTRY(194),
 906         I40E_PTT_UNUSED_ENTRY(195),
 907         I40E_PTT_UNUSED_ENTRY(196),
 908         I40E_PTT_UNUSED_ENTRY(197),
 909         I40E_PTT_UNUSED_ENTRY(198),
 910         I40E_PTT_UNUSED_ENTRY(199),
 911
 912         I40E_PTT_UNUSED_ENTRY(200),
 913         I40E_PTT_UNUSED_ENTRY(201),
 914         I40E_PTT_UNUSED_ENTRY(202),
 915         I40E_PTT_UNUSED_ENTRY(203),
 916         I40E_PTT_UNUSED_ENTRY(204),
 917         I40E_PTT_UNUSED_ENTRY(205),
 918         I40E_PTT_UNUSED_ENTRY(206),
 919         I40E_PTT_UNUSED_ENTRY(207),
 920         I40E_PTT_UNUSED_ENTRY(208),
 921         I40E_PTT_UNUSED_ENTRY(209),
 922
 923         I40E_PTT_UNUSED_ENTRY(210),
 924         I40E_PTT_UNUSED_ENTRY(211),
 925         I40E_PTT_UNUSED_ENTRY(212),
 926         I40E_PTT_UNUSED_ENTRY(213),
 927         I40E_PTT_UNUSED_ENTRY(214),
 928         I40E_PTT_UNUSED_ENTRY(215),
 929         I40E_PTT_UNUSED_ENTRY(216),
 930         I40E_PTT_UNUSED_ENTRY(217),
 931         I40E_PTT_UNUSED_ENTRY(218),
 932         I40E_PTT_UNUSED_ENTRY(219),
 933
 934         I40E_PTT_UNUSED_ENTRY(220),
 935         I40E_PTT_UNUSED_ENTRY(221),
 936         I40E_PTT_UNUSED_ENTRY(222),
 937         I40E_PTT_UNUSED_ENTRY(223),
 938         I40E_PTT_UNUSED_ENTRY(224),
 939         I40E_PTT_UNUSED_ENTRY(225),
 940         I40E_PTT_UNUSED_ENTRY(226),
 941         I40E_PTT_UNUSED_ENTRY(227),
 942         I40E_PTT_UNUSED_ENTRY(228),
 943         I40E_PTT_UNUSED_ENTRY(229),
 944
 945         I40E_PTT_UNUSED_ENTRY(230),
 946         I40E_PTT_UNUSED_ENTRY(231),
 947         I40E_PTT_UNUSED_ENTRY(232),
 948         I40E_PTT_UNUSED_ENTRY(233),
 949         I40E_PTT_UNUSED_ENTRY(234),
 950         I40E_PTT_UNUSED_ENTRY(235),
 951         I40E_PTT_UNUSED_ENTRY(236),
 952         I40E_PTT_UNUSED_ENTRY(237),
 953         I40E_PTT_UNUSED_ENTRY(238),
 954         I40E_PTT_UNUSED_ENTRY(239),
 955
 956         I40E_PTT_UNUSED_ENTRY(240),
 957         I40E_PTT_UNUSED_ENTRY(241),
 958         I40E_PTT_UNUSED_ENTRY(242),
 959         I40E_PTT_UNUSED_ENTRY(243),
 960         I40E_PTT_UNUSED_ENTRY(244),
 961         I40E_PTT_UNUSED_ENTRY(245),
 962         I40E_PTT_UNUSED_ENTRY(246),
 963         I40E_PTT_UNUSED_ENTRY(247),
 964         I40E_PTT_UNUSED_ENTRY(248),
 965         I40E_PTT_UNUSED_ENTRY(249),
 966
 967         I40E_PTT_UNUSED_ENTRY(250),
 968         I40E_PTT_UNUSED_ENTRY(251),
 969         I40E_PTT_UNUSED_ENTRY(252),
 970         I40E_PTT_UNUSED_ENTRY(253),
 971         I40E_PTT_UNUSED_ENTRY(254),
 972         I40E_PTT_UNUSED_ENTRY(255)
 973 };
 974
 975
 976 /**
 977  * i40e_validate_mac_addr - Validate unicast MAC address
 978  * @mac_addr: pointer to MAC address
 979  *
 980  * Tests a MAC address to ensure it is a valid Individual Address
 981  **/
 982 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
 983 {
 984         enum i40e_status_code status = I40E_SUCCESS;
 985
 986         DEBUGFUNC("i40e_validate_mac_addr");
 987
 988         /* Broadcast addresses ARE multicast addresses
 989          * Make sure it is not a multicast address
 990          * Reject the zero address
 991          */
 992         if (I40E_IS_MULTICAST(mac_addr) ||
 993             (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
 994               mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
 995                 status = I40E_ERR_INVALID_MAC_ADDR;
 996
 997         return status;
 998 }
 999 #ifdef PF_DRIVER
1000
1001 /**
1002  * i40e_init_shared_code - Initialize the shared code
1003  * @hw: pointer to hardware structure
1004  *
1005  * This assigns the MAC type and PHY code and inits the NVM.
1006  * Does not touch the hardware. This function must be called prior to any
1007  * other function in the shared code. The i40e_hw structure should be
1008  * memset to 0 prior to calling this function.  The following fields in
1009  * hw structure should be filled in prior to calling this function:
1010  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1011  * subsystem_vendor_id, and revision_id
1012  **/
1013 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
1014 {
1015         enum i40e_status_code status = I40E_SUCCESS;
1016         u32 port, ari, func_rid;
1017
1018         DEBUGFUNC("i40e_init_shared_code");
1019
1020         i40e_set_mac_type(hw);
1021
1022         switch (hw->mac.type) {
1023         case I40E_MAC_XL710:
1024 #ifdef X722_SUPPORT
1025         case I40E_MAC_X722:
1026 #endif
1027                 break;
1028         default:
1029                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1030         }
1031
1032         hw->phy.get_link_info = true;
1033
1034         /* Determine port number and PF number*/
1035         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1036                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1037         hw->port = (u8)port;
1038         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1039                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1040         func_rid = rd32(hw, I40E_PF_FUNC_RID);
1041         if (ari)
1042                 hw->pf_id = (u8)(func_rid & 0xff);
1043         else
1044                 hw->pf_id = (u8)(func_rid & 0x7);
1045
1046 #ifdef X722_SUPPORT
1047         if (hw->mac.type == I40E_MAC_X722)
1048                 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
1049
1050 #endif
1051         status = i40e_init_nvm(hw);
1052         return status;
1053 }
1054
1055 /**
1056  * i40e_aq_mac_address_read - Retrieve the MAC addresses
1057  * @hw: pointer to the hw struct
1058  * @flags: a return indicator of what addresses were added to the addr store
1059  * @addrs: the requestor's mac addr store
1060  * @cmd_details: pointer to command details structure or NULL
1061  **/
1062 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1063                                    u16 *flags,
1064                                    struct i40e_aqc_mac_address_read_data *addrs,
1065                                    struct i40e_asq_cmd_details *cmd_details)
1066 {
1067         struct i40e_aq_desc desc;
1068         struct i40e_aqc_mac_address_read *cmd_data =
1069                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1070         enum i40e_status_code status;
1071
1072         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1073         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1074
1075         status = i40e_asq_send_command(hw, &desc, addrs,
1076                                        sizeof(*addrs), cmd_details);
1077         *flags = LE16_TO_CPU(cmd_data->command_flags);
1078
1079         return status;
1080 }
1081
1082 /**
1083  * i40e_aq_mac_address_write - Change the MAC addresses
1084  * @hw: pointer to the hw struct
1085  * @flags: indicates which MAC to be written
1086  * @mac_addr: address to write
1087  * @cmd_details: pointer to command details structure or NULL
1088  **/
1089 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1090                                     u16 flags, u8 *mac_addr,
1091                                     struct i40e_asq_cmd_details *cmd_details)
1092 {
1093         struct i40e_aq_desc desc;
1094         struct i40e_aqc_mac_address_write *cmd_data =
1095                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1096         enum i40e_status_code status;
1097
1098         i40e_fill_default_direct_cmd_desc(&desc,
1099                                           i40e_aqc_opc_mac_address_write);
1100         cmd_data->command_flags = CPU_TO_LE16(flags);
1101         cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1102         cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1103                                         ((u32)mac_addr[3] << 16) |
1104                                         ((u32)mac_addr[4] << 8) |
1105                                         mac_addr[5]);
1106
1107         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1108
1109         return status;
1110 }
1111
1112 /**
1113  * i40e_get_mac_addr - get MAC address
1114  * @hw: pointer to the HW structure
1115  * @mac_addr: pointer to MAC address
1116  *
1117  * Reads the adapter's MAC address from register
1118  **/
1119 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1120 {
1121         struct i40e_aqc_mac_address_read_data addrs;
1122         enum i40e_status_code status;
1123         u16 flags = 0;
1124
1125         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1126
1127         if (flags & I40E_AQC_LAN_ADDR_VALID)
1128                 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1129                         I40E_NONDMA_TO_NONDMA);
1130
1131         return status;
1132 }
1133
1134 /**
1135  * i40e_get_port_mac_addr - get Port MAC address
1136  * @hw: pointer to the HW structure
1137  * @mac_addr: pointer to Port MAC address
1138  *
1139  * Reads the adapter's Port MAC address
1140  **/
1141 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1142 {
1143         struct i40e_aqc_mac_address_read_data addrs;
1144         enum i40e_status_code status;
1145         u16 flags = 0;
1146
1147         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1148         if (status)
1149                 return status;
1150
1151         if (flags & I40E_AQC_PORT_ADDR_VALID)
1152                 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1153                         I40E_NONDMA_TO_NONDMA);
1154         else
1155                 status = I40E_ERR_INVALID_MAC_ADDR;
1156
1157         return status;
1158 }
1159
1160 /**
1161  * i40e_pre_tx_queue_cfg - pre tx queue configure
1162  * @hw: pointer to the HW structure
1163  * @queue: target pf queue index
1164  * @enable: state change request
1165  *
1166  * Handles hw requirement to indicate intention to enable
1167  * or disable target queue.
1168  **/
1169 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1170 {
1171         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1172         u32 reg_block = 0;
1173         u32 reg_val;
1174
1175         if (abs_queue_idx >= 128) {
1176                 reg_block = abs_queue_idx / 128;
1177                 abs_queue_idx %= 128;
1178         }
1179
1180         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1181         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1182         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1183
1184         if (enable)
1185                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1186         else
1187                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1188
1189         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1190 }
1191
1192 /**
1193  * i40e_get_san_mac_addr - get SAN MAC address
1194  * @hw: pointer to the HW structure
1195  * @mac_addr: pointer to SAN MAC address
1196  *
1197  * Reads the adapter's SAN MAC address from NVM
1198  **/
1199 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1200                                             u8 *mac_addr)
1201 {
1202         struct i40e_aqc_mac_address_read_data addrs;
1203         enum i40e_status_code status;
1204         u16 flags = 0;
1205
1206         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1207         if (status)
1208                 return status;
1209
1210         if (flags & I40E_AQC_SAN_ADDR_VALID)
1211                 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac),
1212                         I40E_NONDMA_TO_NONDMA);
1213         else
1214                 status = I40E_ERR_INVALID_MAC_ADDR;
1215
1216         return status;
1217 }
1218
1219 /**
1220  *  i40e_read_pba_string - Reads part number string from EEPROM
1221  *  @hw: pointer to hardware structure
1222  *  @pba_num: stores the part number string from the EEPROM
1223  *  @pba_num_size: part number string buffer length
1224  *
1225  *  Reads the part number string from the EEPROM.
1226  **/
1227 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1228                                             u32 pba_num_size)
1229 {
1230         enum i40e_status_code status = I40E_SUCCESS;
1231         u16 pba_word = 0;
1232         u16 pba_size = 0;
1233         u16 pba_ptr = 0;
1234         u16 i = 0;
1235
1236         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1237         if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1238                 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1239                 return status;
1240         }
1241
1242         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1243         if (status != I40E_SUCCESS) {
1244                 DEBUGOUT("Failed to read PBA Block pointer.\n");
1245                 return status;
1246         }
1247
1248         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1249         if (status != I40E_SUCCESS) {
1250                 DEBUGOUT("Failed to read PBA Block size.\n");
1251                 return status;
1252         }
1253
1254         /* Subtract one to get PBA word count (PBA Size word is included in
1255          * total size)
1256          */
1257         pba_size--;
1258         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1259                 DEBUGOUT("Buffer to small for PBA data.\n");
1260                 return I40E_ERR_PARAM;
1261         }
1262
1263         for (i = 0; i < pba_size; i++) {
1264                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1265                 if (status != I40E_SUCCESS) {
1266                         DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1267                         return status;
1268                 }
1269
1270                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1271                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1272         }
1273         pba_num[(pba_size * 2)] = '\0';
1274
1275         return status;
1276 }
1277
1278 /**
1279  * i40e_get_media_type - Gets media type
1280  * @hw: pointer to the hardware structure
1281  **/
1282 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1283 {
1284         enum i40e_media_type media;
1285
1286         switch (hw->phy.link_info.phy_type) {
1287         case I40E_PHY_TYPE_10GBASE_SR:
1288         case I40E_PHY_TYPE_10GBASE_LR:
1289         case I40E_PHY_TYPE_1000BASE_SX:
1290         case I40E_PHY_TYPE_1000BASE_LX:
1291         case I40E_PHY_TYPE_40GBASE_SR4:
1292         case I40E_PHY_TYPE_40GBASE_LR4:
1293         case I40E_PHY_TYPE_25GBASE_LR:
1294         case I40E_PHY_TYPE_25GBASE_SR:
1295                 media = I40E_MEDIA_TYPE_FIBER;
1296                 break;
1297         case I40E_PHY_TYPE_100BASE_TX:
1298         case I40E_PHY_TYPE_1000BASE_T:
1299         case I40E_PHY_TYPE_10GBASE_T:
1300                 media = I40E_MEDIA_TYPE_BASET;
1301                 break;
1302         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1303         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1304         case I40E_PHY_TYPE_10GBASE_CR1:
1305         case I40E_PHY_TYPE_40GBASE_CR4:
1306         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1307         case I40E_PHY_TYPE_40GBASE_AOC:
1308         case I40E_PHY_TYPE_10GBASE_AOC:
1309         case I40E_PHY_TYPE_25GBASE_CR:
1310                 media = I40E_MEDIA_TYPE_DA;
1311                 break;
1312         case I40E_PHY_TYPE_1000BASE_KX:
1313         case I40E_PHY_TYPE_10GBASE_KX4:
1314         case I40E_PHY_TYPE_10GBASE_KR:
1315         case I40E_PHY_TYPE_40GBASE_KR4:
1316         case I40E_PHY_TYPE_20GBASE_KR2:
1317         case I40E_PHY_TYPE_25GBASE_KR:
1318                 media = I40E_MEDIA_TYPE_BACKPLANE;
1319                 break;
1320         case I40E_PHY_TYPE_SGMII:
1321         case I40E_PHY_TYPE_XAUI:
1322         case I40E_PHY_TYPE_XFI:
1323         case I40E_PHY_TYPE_XLAUI:
1324         case I40E_PHY_TYPE_XLPPI:
1325         default:
1326                 media = I40E_MEDIA_TYPE_UNKNOWN;
1327                 break;
1328         }
1329
1330         return media;
1331 }
1332
1333 #define I40E_PF_RESET_WAIT_COUNT        200
1334 /**
1335  * i40e_pf_reset - Reset the PF
1336  * @hw: pointer to the hardware structure
1337  *
1338  * Assuming someone else has triggered a global reset,
1339  * assure the global reset is complete and then reset the PF
1340  **/
1341 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1342 {
1343         u32 cnt = 0;
1344         u32 cnt1 = 0;
1345         u32 reg = 0;
1346         u32 grst_del;
1347
1348         /* Poll for Global Reset steady state in case of recent GRST.
1349          * The grst delay value is in 100ms units, and we'll wait a
1350          * couple counts longer to be sure we don't just miss the end.
1351          */
1352         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1353                         I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1354                         I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1355
1356         grst_del = grst_del * 20;
1357
1358         for (cnt = 0; cnt < grst_del; cnt++) {
1359                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1360                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1361                         break;
1362                 i40e_msec_delay(100);
1363         }
1364         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1365                 DEBUGOUT("Global reset polling failed to complete.\n");
1366                 return I40E_ERR_RESET_FAILED;
1367         }
1368
1369         /* Now Wait for the FW to be ready */
1370         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1371                 reg = rd32(hw, I40E_GLNVM_ULD);
1372                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1373                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1374                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1375                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1376                         DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1377                         break;
1378                 }
1379                 i40e_msec_delay(10);
1380         }
1381         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1382                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1383                 DEBUGOUT("wait for FW Reset complete timedout\n");
1384                 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1385                 return I40E_ERR_RESET_FAILED;
1386         }
1387
1388         /* If there was a Global Reset in progress when we got here,
1389          * we don't need to do the PF Reset
1390          */
1391         if (!cnt) {
1392                 reg = rd32(hw, I40E_PFGEN_CTRL);
1393                 wr32(hw, I40E_PFGEN_CTRL,
1394                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1395                 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1396                         reg = rd32(hw, I40E_PFGEN_CTRL);
1397                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1398                                 break;
1399                         i40e_msec_delay(1);
1400                 }
1401                 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1402                         DEBUGOUT("PF reset polling failed to complete.\n");
1403                         return I40E_ERR_RESET_FAILED;
1404                 }
1405         }
1406
1407         i40e_clear_pxe_mode(hw);
1408
1409
1410         return I40E_SUCCESS;
1411 }
1412
1413 /**
1414  * i40e_clear_hw - clear out any left over hw state
1415  * @hw: pointer to the hw struct
1416  *
1417  * Clear queues and interrupts, typically called at init time,
1418  * but after the capabilities have been found so we know how many
1419  * queues and msix vectors have been allocated.
1420  **/
1421 void i40e_clear_hw(struct i40e_hw *hw)
1422 {
1423         u32 num_queues, base_queue;
1424         u32 num_pf_int;
1425         u32 num_vf_int;
1426         u32 num_vfs;
1427         u32 i, j;
1428         u32 val;
1429         u32 eol = 0x7ff;
1430
1431         /* get number of interrupts, queues, and vfs */
1432         val = rd32(hw, I40E_GLPCI_CNF2);
1433         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1434                         I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1435         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1436                         I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1437
1438         val = rd32(hw, I40E_PFLAN_QALLOC);
1439         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1440                         I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1441         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1442                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1443         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1444                 num_queues = (j - base_queue) + 1;
1445         else
1446                 num_queues = 0;
1447
1448         val = rd32(hw, I40E_PF_VT_PFALLOC);
1449         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1450                         I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1451         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1452                         I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1453         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1454                 num_vfs = (j - i) + 1;
1455         else
1456                 num_vfs = 0;
1457
1458         /* stop all the interrupts */
1459         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1460         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1461         for (i = 0; i < num_pf_int - 2; i++)
1462                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1463
1464         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1465         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1466         wr32(hw, I40E_PFINT_LNKLST0, val);
1467         for (i = 0; i < num_pf_int - 2; i++)
1468                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1469         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1470         for (i = 0; i < num_vfs; i++)
1471                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1472         for (i = 0; i < num_vf_int - 2; i++)
1473                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1474
1475         /* warn the HW of the coming Tx disables */
1476         for (i = 0; i < num_queues; i++) {
1477                 u32 abs_queue_idx = base_queue + i;
1478                 u32 reg_block = 0;
1479
1480                 if (abs_queue_idx >= 128) {
1481                         reg_block = abs_queue_idx / 128;
1482                         abs_queue_idx %= 128;
1483                 }
1484
1485                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1486                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1487                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1488                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1489
1490                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1491         }
1492         i40e_usec_delay(400);
1493
1494         /* stop all the queues */
1495         for (i = 0; i < num_queues; i++) {
1496                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1497                 wr32(hw, I40E_QTX_ENA(i), 0);
1498                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1499                 wr32(hw, I40E_QRX_ENA(i), 0);
1500         }
1501
1502         /* short wait for all queue disables to settle */
1503         i40e_usec_delay(50);
1504 }
1505
1506 /**
1507  * i40e_clear_pxe_mode - clear pxe operations mode
1508  * @hw: pointer to the hw struct
1509  *
1510  * Make sure all PXE mode settings are cleared, including things
1511  * like descriptor fetch/write-back mode.
1512  **/
1513 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1514 {
1515         if (i40e_check_asq_alive(hw))
1516                 i40e_aq_clear_pxe_mode(hw, NULL);
1517 }
1518
1519 /**
1520  * i40e_led_is_mine - helper to find matching led
1521  * @hw: pointer to the hw struct
1522  * @idx: index into GPIO registers
1523  *
1524  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1525  */
1526 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1527 {
1528         u32 gpio_val = 0;
1529         u32 port;
1530
1531         if (!hw->func_caps.led[idx])
1532                 return 0;
1533
1534         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1535         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1536                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1537
1538         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1539          * if it is not our port then ignore
1540          */
1541         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1542             (port != hw->port))
1543                 return 0;
1544
1545         return gpio_val;
1546 }
1547
1548 #define I40E_COMBINED_ACTIVITY 0xA
1549 #define I40E_FILTER_ACTIVITY 0xE
1550 #define I40E_LINK_ACTIVITY 0xC
1551 #define I40E_MAC_ACTIVITY 0xD
1552 #define I40E_LED0 22
1553
1554 /**
1555  * i40e_led_get - return current on/off mode
1556  * @hw: pointer to the hw struct
1557  *
1558  * The value returned is the 'mode' field as defined in the
1559  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1560  * values are variations of possible behaviors relating to
1561  * blink, link, and wire.
1562  **/
1563 u32 i40e_led_get(struct i40e_hw *hw)
1564 {
1565         u32 current_mode = 0;
1566         u32 mode = 0;
1567         int i;
1568
1569         /* as per the documentation GPIO 22-29 are the LED
1570          * GPIO pins named LED0..LED7
1571          */
1572         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1573                 u32 gpio_val = i40e_led_is_mine(hw, i);
1574
1575                 if (!gpio_val)
1576                         continue;
1577
1578                 /* ignore gpio LED src mode entries related to the activity
1579                  *  LEDs
1580                  */
1581                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1582                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1583                 switch (current_mode) {
1584                 case I40E_COMBINED_ACTIVITY:
1585                 case I40E_FILTER_ACTIVITY:
1586                 case I40E_MAC_ACTIVITY:
1587                         continue;
1588                 default:
1589                         break;
1590                 }
1591
1592                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1593                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1594                 break;
1595         }
1596
1597         return mode;
1598 }
1599
1600 /**
1601  * i40e_led_set - set new on/off mode
1602  * @hw: pointer to the hw struct
1603  * @mode: 0=off, 0xf=on (else see manual for mode details)
1604  * @blink: true if the LED should blink when on, false if steady
1605  *
1606  * if this function is used to turn on the blink it should
1607  * be used to disable the blink when restoring the original state.
1608  **/
1609 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1610 {
1611         u32 current_mode = 0;
1612         int i;
1613
1614         if (mode & 0xfffffff0)
1615                 DEBUGOUT1("invalid mode passed in %X\n", mode);
1616
1617         /* as per the documentation GPIO 22-29 are the LED
1618          * GPIO pins named LED0..LED7
1619          */
1620         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1621                 u32 gpio_val = i40e_led_is_mine(hw, i);
1622
1623                 if (!gpio_val)
1624                         continue;
1625
1626                 /* ignore gpio LED src mode entries related to the activity
1627                  * LEDs
1628                  */
1629                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1630                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1631                 switch (current_mode) {
1632                 case I40E_COMBINED_ACTIVITY:
1633                 case I40E_FILTER_ACTIVITY:
1634                 case I40E_MAC_ACTIVITY:
1635                         continue;
1636                 default:
1637                         break;
1638                 }
1639
1640                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1641                 /* this & is a bit of paranoia, but serves as a range check */
1642                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1643                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1644
1645                 if (mode == I40E_LINK_ACTIVITY)
1646                         blink = false;
1647
1648                 if (blink)
1649                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1650                 else
1651                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1652
1653                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1654                 break;
1655         }
1656 }
1657
1658 /* Admin command wrappers */
1659
1660 /**
1661  * i40e_aq_get_phy_capabilities
1662  * @hw: pointer to the hw struct
1663  * @abilities: structure for PHY capabilities to be filled
1664  * @qualified_modules: report Qualified Modules
1665  * @report_init: report init capabilities (active are default)
1666  * @cmd_details: pointer to command details structure or NULL
1667  *
1668  * Returns the various PHY abilities supported on the Port.
1669  **/
1670 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1671                         bool qualified_modules, bool report_init,
1672                         struct i40e_aq_get_phy_abilities_resp *abilities,
1673                         struct i40e_asq_cmd_details *cmd_details)
1674 {
1675         struct i40e_aq_desc desc;
1676         enum i40e_status_code status;
1677         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1678
1679         if (!abilities)
1680                 return I40E_ERR_PARAM;
1681
1682         i40e_fill_default_direct_cmd_desc(&desc,
1683                                           i40e_aqc_opc_get_phy_abilities);
1684
1685         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1686         if (abilities_size > I40E_AQ_LARGE_BUF)
1687                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1688
1689         if (qualified_modules)
1690                 desc.params.external.param0 |=
1691                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1692
1693         if (report_init)
1694                 desc.params.external.param0 |=
1695                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1696
1697         status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1698                                     cmd_details);
1699
1700         if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1701                 status = I40E_ERR_UNKNOWN_PHY;
1702
1703         if (report_init) {
1704                 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1705                 hw->phy.phy_types |= ((u64)abilities->phy_type_ext << 32);
1706         }
1707
1708         return status;
1709 }
1710
1711 /**
1712  * i40e_aq_set_phy_config
1713  * @hw: pointer to the hw struct
1714  * @config: structure with PHY configuration to be set
1715  * @cmd_details: pointer to command details structure or NULL
1716  *
1717  * Set the various PHY configuration parameters
1718  * supported on the Port.One or more of the Set PHY config parameters may be
1719  * ignored in an MFP mode as the PF may not have the privilege to set some
1720  * of the PHY Config parameters. This status will be indicated by the
1721  * command response.
1722  **/
1723 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1724                                 struct i40e_aq_set_phy_config *config,
1725                                 struct i40e_asq_cmd_details *cmd_details)
1726 {
1727         struct i40e_aq_desc desc;
1728         struct i40e_aq_set_phy_config *cmd =
1729                 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1730         enum i40e_status_code status;
1731
1732         if (!config)
1733                 return I40E_ERR_PARAM;
1734
1735         i40e_fill_default_direct_cmd_desc(&desc,
1736                                           i40e_aqc_opc_set_phy_config);
1737
1738         *cmd = *config;
1739
1740         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1741
1742         return status;
1743 }
1744
1745 /**
1746  * i40e_set_fc
1747  * @hw: pointer to the hw struct
1748  *
1749  * Set the requested flow control mode using set_phy_config.
1750  **/
1751 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1752                                   bool atomic_restart)
1753 {
1754         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1755         struct i40e_aq_get_phy_abilities_resp abilities;
1756         struct i40e_aq_set_phy_config config;
1757         enum i40e_status_code status;
1758         u8 pause_mask = 0x0;
1759
1760         *aq_failures = 0x0;
1761
1762         switch (fc_mode) {
1763         case I40E_FC_FULL:
1764                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1765                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1766                 break;
1767         case I40E_FC_RX_PAUSE:
1768                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1769                 break;
1770         case I40E_FC_TX_PAUSE:
1771                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1772                 break;
1773         default:
1774                 break;
1775         }
1776
1777         /* Get the current phy config */
1778         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1779                                               NULL);
1780         if (status) {
1781                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1782                 return status;
1783         }
1784
1785         memset(&config, 0, sizeof(config));
1786         /* clear the old pause settings */
1787         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1788                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1789         /* set the new abilities */
1790         config.abilities |= pause_mask;
1791         /* If the abilities have changed, then set the new config */
1792         if (config.abilities != abilities.abilities) {
1793                 /* Auto restart link so settings take effect */
1794                 if (atomic_restart)
1795                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1796                 /* Copy over all the old settings */
1797                 config.phy_type = abilities.phy_type;
1798                 config.phy_type_ext = abilities.phy_type_ext;
1799                 config.link_speed = abilities.link_speed;
1800                 config.eee_capability = abilities.eee_capability;
1801                 config.eeer = abilities.eeer_val;
1802                 config.low_power_ctrl = abilities.d3_lpan;
1803                 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1804                                     I40E_AQ_PHY_FEC_CONFIG_MASK;
1805                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1806
1807                 if (status)
1808                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1809         }
1810         /* Update the link info */
1811         status = i40e_update_link_info(hw);
1812         if (status) {
1813                 /* Wait a little bit (on 40G cards it sometimes takes a really
1814                  * long time for link to come back from the atomic reset)
1815                  * and try once more
1816                  */
1817                 i40e_msec_delay(1000);
1818                 status = i40e_update_link_info(hw);
1819         }
1820         if (status)
1821                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1822
1823         return status;
1824 }
1825
1826 /**
1827  * i40e_aq_set_mac_config
1828  * @hw: pointer to the hw struct
1829  * @max_frame_size: Maximum Frame Size to be supported by the port
1830  * @crc_en: Tell HW to append a CRC to outgoing frames
1831  * @pacing: Pacing configurations
1832  * @cmd_details: pointer to command details structure or NULL
1833  *
1834  * Configure MAC settings for frame size, jumbo frame support and the
1835  * addition of a CRC by the hardware.
1836  **/
1837 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1838                                 u16 max_frame_size,
1839                                 bool crc_en, u16 pacing,
1840                                 struct i40e_asq_cmd_details *cmd_details)
1841 {
1842         struct i40e_aq_desc desc;
1843         struct i40e_aq_set_mac_config *cmd =
1844                 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1845         enum i40e_status_code status;
1846
1847         if (max_frame_size == 0)
1848                 return I40E_ERR_PARAM;
1849
1850         i40e_fill_default_direct_cmd_desc(&desc,
1851                                           i40e_aqc_opc_set_mac_config);
1852
1853         cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1854         cmd->params = ((u8)pacing & 0x0F) << 3;
1855         if (crc_en)
1856                 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1857
1858         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1859
1860         return status;
1861 }
1862
1863 /**
1864  * i40e_aq_clear_pxe_mode
1865  * @hw: pointer to the hw struct
1866  * @cmd_details: pointer to command details structure or NULL
1867  *
1868  * Tell the firmware that the driver is taking over from PXE
1869  **/
1870 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1871                         struct i40e_asq_cmd_details *cmd_details)
1872 {
1873         enum i40e_status_code status;
1874         struct i40e_aq_desc desc;
1875         struct i40e_aqc_clear_pxe *cmd =
1876                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1877
1878         i40e_fill_default_direct_cmd_desc(&desc,
1879                                           i40e_aqc_opc_clear_pxe_mode);
1880
1881         cmd->rx_cnt = 0x2;
1882
1883         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1884
1885         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1886
1887         return status;
1888 }
1889
1890 /**
1891  * i40e_aq_set_link_restart_an
1892  * @hw: pointer to the hw struct
1893  * @enable_link: if true: enable link, if false: disable link
1894  * @cmd_details: pointer to command details structure or NULL
1895  *
1896  * Sets up the link and restarts the Auto-Negotiation over the link.
1897  **/
1898 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1899                 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1900 {
1901         struct i40e_aq_desc desc;
1902         struct i40e_aqc_set_link_restart_an *cmd =
1903                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1904         enum i40e_status_code status;
1905
1906         i40e_fill_default_direct_cmd_desc(&desc,
1907                                           i40e_aqc_opc_set_link_restart_an);
1908
1909         cmd->command = I40E_AQ_PHY_RESTART_AN;
1910         if (enable_link)
1911                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1912         else
1913                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1914
1915         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1916
1917         return status;
1918 }
1919
1920 /**
1921  * i40e_aq_get_link_info
1922  * @hw: pointer to the hw struct
1923  * @enable_lse: enable/disable LinkStatusEvent reporting
1924  * @link: pointer to link status structure - optional
1925  * @cmd_details: pointer to command details structure or NULL
1926  *
1927  * Returns the link status of the adapter.
1928  **/
1929 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1930                                 bool enable_lse, struct i40e_link_status *link,
1931                                 struct i40e_asq_cmd_details *cmd_details)
1932 {
1933         struct i40e_aq_desc desc;
1934         struct i40e_aqc_get_link_status *resp =
1935                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1936         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1937         enum i40e_status_code status;
1938         bool tx_pause, rx_pause;
1939         u16 command_flags;
1940
1941         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1942
1943         if (enable_lse)
1944                 command_flags = I40E_AQ_LSE_ENABLE;
1945         else
1946                 command_flags = I40E_AQ_LSE_DISABLE;
1947         resp->command_flags = CPU_TO_LE16(command_flags);
1948
1949         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1950
1951         if (status != I40E_SUCCESS)
1952                 goto aq_get_link_info_exit;
1953
1954         /* save off old link status information */
1955         i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1956                     sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1957
1958         /* update link status */
1959         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1960         hw->phy.media_type = i40e_get_media_type(hw);
1961         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1962         hw_link_info->link_info = resp->link_info;
1963         hw_link_info->an_info = resp->an_info;
1964         hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
1965                                                  I40E_AQ_CONFIG_FEC_RS_ENA);
1966         hw_link_info->ext_info = resp->ext_info;
1967         hw_link_info->loopback = resp->loopback;
1968         hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1969         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1970
1971         /* update fc info */
1972         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1973         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1974         if (tx_pause & rx_pause)
1975                 hw->fc.current_mode = I40E_FC_FULL;
1976         else if (tx_pause)
1977                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1978         else if (rx_pause)
1979                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1980         else
1981                 hw->fc.current_mode = I40E_FC_NONE;
1982
1983         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1984                 hw_link_info->crc_enable = true;
1985         else
1986                 hw_link_info->crc_enable = false;
1987
1988         if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
1989                 hw_link_info->lse_enable = true;
1990         else
1991                 hw_link_info->lse_enable = false;
1992
1993         if ((hw->mac.type == I40E_MAC_XL710) &&
1994             (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1995              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1996                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1997
1998         /* save link status information */
1999         if (link)
2000                 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
2001                             I40E_NONDMA_TO_NONDMA);
2002
2003         /* flag cleared so helper functions don't call AQ again */
2004         hw->phy.get_link_info = false;
2005
2006 aq_get_link_info_exit:
2007         return status;
2008 }
2009
2010 /**
2011  * i40e_aq_set_phy_int_mask
2012  * @hw: pointer to the hw struct
2013  * @mask: interrupt mask to be set
2014  * @cmd_details: pointer to command details structure or NULL
2015  *
2016  * Set link interrupt mask.
2017  **/
2018 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2019                                 u16 mask,
2020                                 struct i40e_asq_cmd_details *cmd_details)
2021 {
2022         struct i40e_aq_desc desc;
2023         struct i40e_aqc_set_phy_int_mask *cmd =
2024                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2025         enum i40e_status_code status;
2026
2027         i40e_fill_default_direct_cmd_desc(&desc,
2028                                           i40e_aqc_opc_set_phy_int_mask);
2029
2030         cmd->event_mask = CPU_TO_LE16(mask);
2031
2032         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2033
2034         return status;
2035 }
2036
2037 /**
2038  * i40e_aq_get_local_advt_reg
2039  * @hw: pointer to the hw struct
2040  * @advt_reg: local AN advertisement register value
2041  * @cmd_details: pointer to command details structure or NULL
2042  *
2043  * Get the Local AN advertisement register value.
2044  **/
2045 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2046                                 u64 *advt_reg,
2047                                 struct i40e_asq_cmd_details *cmd_details)
2048 {
2049         struct i40e_aq_desc desc;
2050         struct i40e_aqc_an_advt_reg *resp =
2051                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2052         enum i40e_status_code status;
2053
2054         i40e_fill_default_direct_cmd_desc(&desc,
2055                                           i40e_aqc_opc_get_local_advt_reg);
2056
2057         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2058
2059         if (status != I40E_SUCCESS)
2060                 goto aq_get_local_advt_reg_exit;
2061
2062         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2063         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2064
2065 aq_get_local_advt_reg_exit:
2066         return status;
2067 }
2068
2069 /**
2070  * i40e_aq_set_local_advt_reg
2071  * @hw: pointer to the hw struct
2072  * @advt_reg: local AN advertisement register value
2073  * @cmd_details: pointer to command details structure or NULL
2074  *
2075  * Get the Local AN advertisement register value.
2076  **/
2077 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2078                                 u64 advt_reg,
2079                                 struct i40e_asq_cmd_details *cmd_details)
2080 {
2081         struct i40e_aq_desc desc;
2082         struct i40e_aqc_an_advt_reg *cmd =
2083                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2084         enum i40e_status_code status;
2085
2086         i40e_fill_default_direct_cmd_desc(&desc,
2087                                           i40e_aqc_opc_get_local_advt_reg);
2088
2089         cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2090         cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2091
2092         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2093
2094         return status;
2095 }
2096
2097 /**
2098  * i40e_aq_get_partner_advt
2099  * @hw: pointer to the hw struct
2100  * @advt_reg: AN partner advertisement register value
2101  * @cmd_details: pointer to command details structure or NULL
2102  *
2103  * Get the link partner AN advertisement register value.
2104  **/
2105 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2106                                 u64 *advt_reg,
2107                                 struct i40e_asq_cmd_details *cmd_details)
2108 {
2109         struct i40e_aq_desc desc;
2110         struct i40e_aqc_an_advt_reg *resp =
2111                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2112         enum i40e_status_code status;
2113
2114         i40e_fill_default_direct_cmd_desc(&desc,
2115                                           i40e_aqc_opc_get_partner_advt);
2116
2117         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2118
2119         if (status != I40E_SUCCESS)
2120                 goto aq_get_partner_advt_exit;
2121
2122         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2123         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2124
2125 aq_get_partner_advt_exit:
2126         return status;
2127 }
2128
2129 /**
2130  * i40e_aq_set_lb_modes
2131  * @hw: pointer to the hw struct
2132  * @lb_modes: loopback mode to be set
2133  * @cmd_details: pointer to command details structure or NULL
2134  *
2135  * Sets loopback modes.
2136  **/
2137 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2138                                 u16 lb_modes,
2139                                 struct i40e_asq_cmd_details *cmd_details)
2140 {
2141         struct i40e_aq_desc desc;
2142         struct i40e_aqc_set_lb_mode *cmd =
2143                 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2144         enum i40e_status_code status;
2145
2146         i40e_fill_default_direct_cmd_desc(&desc,
2147                                           i40e_aqc_opc_set_lb_modes);
2148
2149         cmd->lb_mode = CPU_TO_LE16(lb_modes);
2150
2151         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2152
2153         return status;
2154 }
2155
2156 /**
2157  * i40e_aq_set_phy_debug
2158  * @hw: pointer to the hw struct
2159  * @cmd_flags: debug command flags
2160  * @cmd_details: pointer to command details structure or NULL
2161  *
2162  * Reset the external PHY.
2163  **/
2164 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2165                                 struct i40e_asq_cmd_details *cmd_details)
2166 {
2167         struct i40e_aq_desc desc;
2168         struct i40e_aqc_set_phy_debug *cmd =
2169                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2170         enum i40e_status_code status;
2171
2172         i40e_fill_default_direct_cmd_desc(&desc,
2173                                           i40e_aqc_opc_set_phy_debug);
2174
2175         cmd->command_flags = cmd_flags;
2176
2177         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2178
2179         return status;
2180 }
2181
2182 /**
2183  * i40e_aq_add_vsi
2184  * @hw: pointer to the hw struct
2185  * @vsi_ctx: pointer to a vsi context struct
2186  * @cmd_details: pointer to command details structure or NULL
2187  *
2188  * Add a VSI context to the hardware.
2189 **/
2190 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2191                                 struct i40e_vsi_context *vsi_ctx,
2192                                 struct i40e_asq_cmd_details *cmd_details)
2193 {
2194         struct i40e_aq_desc desc;
2195         struct i40e_aqc_add_get_update_vsi *cmd =
2196                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2197         struct i40e_aqc_add_get_update_vsi_completion *resp =
2198                 (struct i40e_aqc_add_get_update_vsi_completion *)
2199                 &desc.params.raw;
2200         enum i40e_status_code status;
2201
2202         i40e_fill_default_direct_cmd_desc(&desc,
2203                                           i40e_aqc_opc_add_vsi);
2204
2205         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2206         cmd->connection_type = vsi_ctx->connection_type;
2207         cmd->vf_id = vsi_ctx->vf_num;
2208         cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2209
2210         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2211
2212         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2213                                     sizeof(vsi_ctx->info), cmd_details);
2214
2215         if (status != I40E_SUCCESS)
2216                 goto aq_add_vsi_exit;
2217
2218         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2219         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2220         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2221         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2222
2223 aq_add_vsi_exit:
2224         return status;
2225 }
2226
2227 /**
2228  * i40e_aq_set_default_vsi
2229  * @hw: pointer to the hw struct
2230  * @seid: vsi number
2231  * @cmd_details: pointer to command details structure or NULL
2232  **/
2233 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2234                                 u16 seid,
2235                                 struct i40e_asq_cmd_details *cmd_details)
2236 {
2237         struct i40e_aq_desc desc;
2238         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2239                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2240                 &desc.params.raw;
2241         enum i40e_status_code status;
2242
2243         i40e_fill_default_direct_cmd_desc(&desc,
2244                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2245
2246         cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2247         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2248         cmd->seid = CPU_TO_LE16(seid);
2249
2250         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2251
2252         return status;
2253 }
2254
2255 /**
2256  * i40e_aq_clear_default_vsi
2257  * @hw: pointer to the hw struct
2258  * @seid: vsi number
2259  * @cmd_details: pointer to command details structure or NULL
2260  **/
2261 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2262                                 u16 seid,
2263                                 struct i40e_asq_cmd_details *cmd_details)
2264 {
2265         struct i40e_aq_desc desc;
2266         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2267                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2268                 &desc.params.raw;
2269         enum i40e_status_code status;
2270
2271         i40e_fill_default_direct_cmd_desc(&desc,
2272                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2273
2274         cmd->promiscuous_flags = CPU_TO_LE16(0);
2275         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2276         cmd->seid = CPU_TO_LE16(seid);
2277
2278         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2279
2280         return status;
2281 }
2282
2283 /**
2284  * i40e_aq_set_vsi_unicast_promiscuous
2285  * @hw: pointer to the hw struct
2286  * @seid: vsi number
2287  * @set: set unicast promiscuous enable/disable
2288  * @cmd_details: pointer to command details structure or NULL
2289  * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2290  **/
2291 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2292                                 u16 seid, bool set,
2293                                 struct i40e_asq_cmd_details *cmd_details,
2294                                 bool rx_only_promisc)
2295 {
2296         struct i40e_aq_desc desc;
2297         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2298                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2299         enum i40e_status_code status;
2300         u16 flags = 0;
2301
2302         i40e_fill_default_direct_cmd_desc(&desc,
2303                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2304
2305         if (set) {
2306                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2307                 if (rx_only_promisc &&
2308                     (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2309                      (hw->aq.api_maj_ver > 1)))
2310                         flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2311         }
2312
2313         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2314
2315         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2316         if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2317              (hw->aq.api_maj_ver > 1))
2318                 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2319
2320         cmd->seid = CPU_TO_LE16(seid);
2321         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2322
2323         return status;
2324 }
2325
2326 /**
2327  * i40e_aq_set_vsi_multicast_promiscuous
2328  * @hw: pointer to the hw struct
2329  * @seid: vsi number
2330  * @set: set multicast promiscuous enable/disable
2331  * @cmd_details: pointer to command details structure or NULL
2332  **/
2333 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2334                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2335 {
2336         struct i40e_aq_desc desc;
2337         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2338                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2339         enum i40e_status_code status;
2340         u16 flags = 0;
2341
2342         i40e_fill_default_direct_cmd_desc(&desc,
2343                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2344
2345         if (set)
2346                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2347
2348         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2349
2350         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2351
2352         cmd->seid = CPU_TO_LE16(seid);
2353         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2354
2355         return status;
2356 }
2357
2358 /**
2359 * i40e_aq_set_vsi_full_promiscuous
2360 * @hw: pointer to the hw struct
2361 * @seid: VSI number
2362 * @set: set promiscuous enable/disable
2363 * @cmd_details: pointer to command details structure or NULL
2364 **/
2365 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw,
2366                                 u16 seid, bool set,
2367                                 struct i40e_asq_cmd_details *cmd_details)
2368 {
2369         struct i40e_aq_desc desc;
2370         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2371                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2372         enum i40e_status_code status;
2373         u16 flags = 0;
2374
2375         i40e_fill_default_direct_cmd_desc(&desc,
2376                 i40e_aqc_opc_set_vsi_promiscuous_modes);
2377
2378         if (set)
2379                 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2380                         I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2381                         I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2382
2383         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2384
2385         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2386                                        I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2387                                        I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2388
2389         cmd->seid = CPU_TO_LE16(seid);
2390         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2391
2392         return status;
2393 }
2394
2395 /**
2396  * i40e_aq_set_vsi_mc_promisc_on_vlan
2397  * @hw: pointer to the hw struct
2398  * @seid: vsi number
2399  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2400  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2401  * @cmd_details: pointer to command details structure or NULL
2402  **/
2403 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2404                                 u16 seid, bool enable, u16 vid,
2405                                 struct i40e_asq_cmd_details *cmd_details)
2406 {
2407         struct i40e_aq_desc desc;
2408         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2409                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2410         enum i40e_status_code status;
2411         u16 flags = 0;
2412
2413         i40e_fill_default_direct_cmd_desc(&desc,
2414                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2415
2416         if (enable)
2417                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2418
2419         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2420         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2421         cmd->seid = CPU_TO_LE16(seid);
2422         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2423
2424         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2425
2426         return status;
2427 }
2428
2429 /**
2430  * i40e_aq_set_vsi_uc_promisc_on_vlan
2431  * @hw: pointer to the hw struct
2432  * @seid: vsi number
2433  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2434  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2435  * @cmd_details: pointer to command details structure or NULL
2436  **/
2437 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2438                                 u16 seid, bool enable, u16 vid,
2439                                 struct i40e_asq_cmd_details *cmd_details)
2440 {
2441         struct i40e_aq_desc desc;
2442         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2443                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2444         enum i40e_status_code status;
2445         u16 flags = 0;
2446
2447         i40e_fill_default_direct_cmd_desc(&desc,
2448                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2449
2450         if (enable)
2451                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2452
2453         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2454         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2455         cmd->seid = CPU_TO_LE16(seid);
2456         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2457
2458         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2459
2460         return status;
2461 }
2462
2463 /**
2464  * i40e_aq_set_vsi_broadcast
2465  * @hw: pointer to the hw struct
2466  * @seid: vsi number
2467  * @set_filter: true to set filter, false to clear filter
2468  * @cmd_details: pointer to command details structure or NULL
2469  *
2470  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2471  **/
2472 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2473                                 u16 seid, bool set_filter,
2474                                 struct i40e_asq_cmd_details *cmd_details)
2475 {
2476         struct i40e_aq_desc desc;
2477         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2478                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2479         enum i40e_status_code status;
2480
2481         i40e_fill_default_direct_cmd_desc(&desc,
2482                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2483
2484         if (set_filter)
2485                 cmd->promiscuous_flags
2486                             |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2487         else
2488                 cmd->promiscuous_flags
2489                             &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2490
2491         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2492         cmd->seid = CPU_TO_LE16(seid);
2493         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2494
2495         return status;
2496 }
2497
2498 /**
2499  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2500  * @hw: pointer to the hw struct
2501  * @seid: vsi number
2502  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2503  * @cmd_details: pointer to command details structure or NULL
2504  **/
2505 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2506                                 u16 seid, bool enable,
2507                                 struct i40e_asq_cmd_details *cmd_details)
2508 {
2509         struct i40e_aq_desc desc;
2510         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2511                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2512         enum i40e_status_code status;
2513         u16 flags = 0;
2514
2515         i40e_fill_default_direct_cmd_desc(&desc,
2516                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2517         if (enable)
2518                 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2519
2520         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2521         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2522         cmd->seid = CPU_TO_LE16(seid);
2523
2524         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2525
2526         return status;
2527 }
2528
2529 /**
2530  * i40e_get_vsi_params - get VSI configuration info
2531  * @hw: pointer to the hw struct
2532  * @vsi_ctx: pointer to a vsi context struct
2533  * @cmd_details: pointer to command details structure or NULL
2534  **/
2535 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2536                                 struct i40e_vsi_context *vsi_ctx,
2537                                 struct i40e_asq_cmd_details *cmd_details)
2538 {
2539         struct i40e_aq_desc desc;
2540         struct i40e_aqc_add_get_update_vsi *cmd =
2541                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2542         struct i40e_aqc_add_get_update_vsi_completion *resp =
2543                 (struct i40e_aqc_add_get_update_vsi_completion *)
2544                 &desc.params.raw;
2545         enum i40e_status_code status;
2546
2547         UNREFERENCED_1PARAMETER(cmd_details);
2548         i40e_fill_default_direct_cmd_desc(&desc,
2549                                           i40e_aqc_opc_get_vsi_parameters);
2550
2551         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2552
2553         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2554
2555         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2556                                     sizeof(vsi_ctx->info), NULL);
2557
2558         if (status != I40E_SUCCESS)
2559                 goto aq_get_vsi_params_exit;
2560
2561         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2562         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2563         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2564         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2565
2566 aq_get_vsi_params_exit:
2567         return status;
2568 }
2569
2570 /**
2571  * i40e_aq_update_vsi_params
2572  * @hw: pointer to the hw struct
2573  * @vsi_ctx: pointer to a vsi context struct
2574  * @cmd_details: pointer to command details structure or NULL
2575  *
2576  * Update a VSI context.
2577  **/
2578 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2579                                 struct i40e_vsi_context *vsi_ctx,
2580                                 struct i40e_asq_cmd_details *cmd_details)
2581 {
2582         struct i40e_aq_desc desc;
2583         struct i40e_aqc_add_get_update_vsi *cmd =
2584                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2585         struct i40e_aqc_add_get_update_vsi_completion *resp =
2586                 (struct i40e_aqc_add_get_update_vsi_completion *)
2587                 &desc.params.raw;
2588         enum i40e_status_code status;
2589
2590         i40e_fill_default_direct_cmd_desc(&desc,
2591                                           i40e_aqc_opc_update_vsi_parameters);
2592         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2593
2594         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2595
2596         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2597                                     sizeof(vsi_ctx->info), cmd_details);
2598
2599         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2600         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2601
2602         return status;
2603 }
2604
2605 /**
2606  * i40e_aq_get_switch_config
2607  * @hw: pointer to the hardware structure
2608  * @buf: pointer to the result buffer
2609  * @buf_size: length of input buffer
2610  * @start_seid: seid to start for the report, 0 == beginning
2611  * @cmd_details: pointer to command details structure or NULL
2612  *
2613  * Fill the buf with switch configuration returned from AdminQ command
2614  **/
2615 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2616                                 struct i40e_aqc_get_switch_config_resp *buf,
2617                                 u16 buf_size, u16 *start_seid,
2618                                 struct i40e_asq_cmd_details *cmd_details)
2619 {
2620         struct i40e_aq_desc desc;
2621         struct i40e_aqc_switch_seid *scfg =
2622                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2623         enum i40e_status_code status;
2624
2625         i40e_fill_default_direct_cmd_desc(&desc,
2626                                           i40e_aqc_opc_get_switch_config);
2627         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2628         if (buf_size > I40E_AQ_LARGE_BUF)
2629                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2630         scfg->seid = CPU_TO_LE16(*start_seid);
2631
2632         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2633         *start_seid = LE16_TO_CPU(scfg->seid);
2634
2635         return status;
2636 }
2637
2638 /**
2639  * i40e_aq_set_switch_config
2640  * @hw: pointer to the hardware structure
2641  * @flags: bit flag values to set
2642  * @valid_flags: which bit flags to set
2643  * @cmd_details: pointer to command details structure or NULL
2644  *
2645  * Set switch configuration bits
2646  **/
2647 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2648                                 u16 flags, u16 valid_flags,
2649                                 struct i40e_asq_cmd_details *cmd_details)
2650 {
2651         struct i40e_aq_desc desc;
2652         struct i40e_aqc_set_switch_config *scfg =
2653                 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2654         enum i40e_status_code status;
2655
2656         i40e_fill_default_direct_cmd_desc(&desc,
2657                                           i40e_aqc_opc_set_switch_config);
2658         scfg->flags = CPU_TO_LE16(flags);
2659         scfg->valid_flags = CPU_TO_LE16(valid_flags);
2660
2661         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2662
2663         return status;
2664 }
2665
2666 /**
2667  * i40e_aq_get_firmware_version
2668  * @hw: pointer to the hw struct
2669  * @fw_major_version: firmware major version
2670  * @fw_minor_version: firmware minor version
2671  * @fw_build: firmware build number
2672  * @api_major_version: major queue version
2673  * @api_minor_version: minor queue version
2674  * @cmd_details: pointer to command details structure or NULL
2675  *
2676  * Get the firmware version from the admin queue commands
2677  **/
2678 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2679                                 u16 *fw_major_version, u16 *fw_minor_version,
2680                                 u32 *fw_build,
2681                                 u16 *api_major_version, u16 *api_minor_version,
2682                                 struct i40e_asq_cmd_details *cmd_details)
2683 {
2684         struct i40e_aq_desc desc;
2685         struct i40e_aqc_get_version *resp =
2686                 (struct i40e_aqc_get_version *)&desc.params.raw;
2687         enum i40e_status_code status;
2688
2689         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2690
2691         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2692
2693         if (status == I40E_SUCCESS) {
2694                 if (fw_major_version != NULL)
2695                         *fw_major_version = LE16_TO_CPU(resp->fw_major);
2696                 if (fw_minor_version != NULL)
2697                         *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2698                 if (fw_build != NULL)
2699                         *fw_build = LE32_TO_CPU(resp->fw_build);
2700                 if (api_major_version != NULL)
2701                         *api_major_version = LE16_TO_CPU(resp->api_major);
2702                 if (api_minor_version != NULL)
2703                         *api_minor_version = LE16_TO_CPU(resp->api_minor);
2704
2705                 /* A workaround to fix the API version in SW */
2706                 if (api_major_version && api_minor_version &&
2707                     fw_major_version && fw_minor_version &&
2708                     ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2709                     (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2710                      (*fw_major_version > 4)))
2711                         *api_minor_version = 2;
2712         }
2713
2714         return status;
2715 }
2716
2717 /**
2718  * i40e_aq_send_driver_version
2719  * @hw: pointer to the hw struct
2720  * @dv: driver's major, minor version
2721  * @cmd_details: pointer to command details structure or NULL
2722  *
2723  * Send the driver version to the firmware
2724  **/
2725 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2726                                 struct i40e_driver_version *dv,
2727                                 struct i40e_asq_cmd_details *cmd_details)
2728 {
2729         struct i40e_aq_desc desc;
2730         struct i40e_aqc_driver_version *cmd =
2731                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2732         enum i40e_status_code status;
2733         u16 len;
2734
2735         if (dv == NULL)
2736                 return I40E_ERR_PARAM;
2737
2738         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2739
2740         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2741         cmd->driver_major_ver = dv->major_version;
2742         cmd->driver_minor_ver = dv->minor_version;
2743         cmd->driver_build_ver = dv->build_version;
2744         cmd->driver_subbuild_ver = dv->subbuild_version;
2745
2746         len = 0;
2747         while (len < sizeof(dv->driver_string) &&
2748                (dv->driver_string[len] < 0x80) &&
2749                dv->driver_string[len])
2750                 len++;
2751         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2752                                        len, cmd_details);
2753
2754         return status;
2755 }
2756
2757 /**
2758  * i40e_get_link_status - get status of the HW network link
2759  * @hw: pointer to the hw struct
2760  * @link_up: pointer to bool (true/false = linkup/linkdown)
2761  *
2762  * Variable link_up true if link is up, false if link is down.
2763  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2764  *
2765  * Side effect: LinkStatusEvent reporting becomes enabled
2766  **/
2767 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2768 {
2769         enum i40e_status_code status = I40E_SUCCESS;
2770
2771         if (hw->phy.get_link_info) {
2772                 status = i40e_update_link_info(hw);
2773
2774                 if (status != I40E_SUCCESS)
2775                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2776                                    status);
2777         }
2778
2779         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2780
2781         return status;
2782 }
2783
2784 /**
2785  * i40e_updatelink_status - update status of the HW network link
2786  * @hw: pointer to the hw struct
2787  **/
2788 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2789 {
2790         struct i40e_aq_get_phy_abilities_resp abilities;
2791         enum i40e_status_code status = I40E_SUCCESS;
2792
2793         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2794         if (status)
2795                 return status;
2796
2797         /* extra checking needed to ensure link info to user is timely */
2798         if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2799             ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2800              !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2801                 status = i40e_aq_get_phy_capabilities(hw, false, false,
2802                                                       &abilities, NULL);
2803                 if (status)
2804                         return status;
2805
2806                 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2807                         sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2808         }
2809         return status;
2810 }
2811
2812
2813 /**
2814  * i40e_get_link_speed
2815  * @hw: pointer to the hw struct
2816  *
2817  * Returns the link speed of the adapter.
2818  **/
2819 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2820 {
2821         enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2822         enum i40e_status_code status = I40E_SUCCESS;
2823
2824         if (hw->phy.get_link_info) {
2825                 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2826
2827                 if (status != I40E_SUCCESS)
2828                         goto i40e_link_speed_exit;
2829         }
2830
2831         speed = hw->phy.link_info.link_speed;
2832
2833 i40e_link_speed_exit:
2834         return speed;
2835 }
2836
2837 /**
2838  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2839  * @hw: pointer to the hw struct
2840  * @uplink_seid: the MAC or other gizmo SEID
2841  * @downlink_seid: the VSI SEID
2842  * @enabled_tc: bitmap of TCs to be enabled
2843  * @default_port: true for default port VSI, false for control port
2844  * @veb_seid: pointer to where to put the resulting VEB SEID
2845  * @enable_stats: true to turn on VEB stats
2846  * @cmd_details: pointer to command details structure or NULL
2847  *
2848  * This asks the FW to add a VEB between the uplink and downlink
2849  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2850  **/
2851 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2852                                 u16 downlink_seid, u8 enabled_tc,
2853                                 bool default_port, u16 *veb_seid,
2854                                 bool enable_stats,
2855                                 struct i40e_asq_cmd_details *cmd_details)
2856 {
2857         struct i40e_aq_desc desc;
2858         struct i40e_aqc_add_veb *cmd =
2859                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2860         struct i40e_aqc_add_veb_completion *resp =
2861                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2862         enum i40e_status_code status;
2863         u16 veb_flags = 0;
2864
2865         /* SEIDs need to either both be set or both be 0 for floating VEB */
2866         if (!!uplink_seid != !!downlink_seid)
2867                 return I40E_ERR_PARAM;
2868
2869         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2870
2871         cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2872         cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2873         cmd->enable_tcs = enabled_tc;
2874         if (!uplink_seid)
2875                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2876         if (default_port)
2877                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2878         else
2879                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2880
2881         /* reverse logic here: set the bitflag to disable the stats */
2882         if (!enable_stats)
2883                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2884
2885         cmd->veb_flags = CPU_TO_LE16(veb_flags);
2886
2887         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2888
2889         if (!status && veb_seid)
2890                 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2891
2892         return status;
2893 }
2894
2895 /**
2896  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2897  * @hw: pointer to the hw struct
2898  * @veb_seid: the SEID of the VEB to query
2899  * @switch_id: the uplink switch id
2900  * @floating: set to true if the VEB is floating
2901  * @statistic_index: index of the stats counter block for this VEB
2902  * @vebs_used: number of VEB's used by function
2903  * @vebs_free: total VEB's not reserved by any function
2904  * @cmd_details: pointer to command details structure or NULL
2905  *
2906  * This retrieves the parameters for a particular VEB, specified by
2907  * uplink_seid, and returns them to the caller.
2908  **/
2909 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2910                                 u16 veb_seid, u16 *switch_id,
2911                                 bool *floating, u16 *statistic_index,
2912                                 u16 *vebs_used, u16 *vebs_free,
2913                                 struct i40e_asq_cmd_details *cmd_details)
2914 {
2915         struct i40e_aq_desc desc;
2916         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2917                 (struct i40e_aqc_get_veb_parameters_completion *)
2918                 &desc.params.raw;
2919         enum i40e_status_code status;
2920
2921         if (veb_seid == 0)
2922                 return I40E_ERR_PARAM;
2923
2924         i40e_fill_default_direct_cmd_desc(&desc,
2925                                           i40e_aqc_opc_get_veb_parameters);
2926         cmd_resp->seid = CPU_TO_LE16(veb_seid);
2927
2928         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2929         if (status)
2930                 goto get_veb_exit;
2931
2932         if (switch_id)
2933                 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2934         if (statistic_index)
2935                 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2936         if (vebs_used)
2937                 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2938         if (vebs_free)
2939                 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2940         if (floating) {
2941                 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2942
2943                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2944                         *floating = true;
2945                 else
2946                         *floating = false;
2947         }
2948
2949 get_veb_exit:
2950         return status;
2951 }
2952
2953 /**
2954  * i40e_aq_add_macvlan
2955  * @hw: pointer to the hw struct
2956  * @seid: VSI for the mac address
2957  * @mv_list: list of macvlans to be added
2958  * @count: length of the list
2959  * @cmd_details: pointer to command details structure or NULL
2960  *
2961  * Add MAC/VLAN addresses to the HW filtering
2962  **/
2963 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2964                         struct i40e_aqc_add_macvlan_element_data *mv_list,
2965                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2966 {
2967         struct i40e_aq_desc desc;
2968         struct i40e_aqc_macvlan *cmd =
2969                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2970         enum i40e_status_code status;
2971         u16 buf_size;
2972         int i;
2973
2974         if (count == 0 || !mv_list || !hw)
2975                 return I40E_ERR_PARAM;
2976
2977         buf_size = count * sizeof(*mv_list);
2978
2979         /* prep the rest of the request */
2980         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2981         cmd->num_addresses = CPU_TO_LE16(count);
2982         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2983         cmd->seid[1] = 0;
2984         cmd->seid[2] = 0;
2985
2986         for (i = 0; i < count; i++)
2987                 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
2988                         mv_list[i].flags |=
2989                             CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2990
2991         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2992         if (buf_size > I40E_AQ_LARGE_BUF)
2993                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2994
2995         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2996                                        cmd_details);
2997
2998         return status;
2999 }
3000
3001 /**
3002  * i40e_aq_remove_macvlan
3003  * @hw: pointer to the hw struct
3004  * @seid: VSI for the mac address
3005  * @mv_list: list of macvlans to be removed
3006  * @count: length of the list
3007  * @cmd_details: pointer to command details structure or NULL
3008  *
3009  * Remove MAC/VLAN addresses from the HW filtering
3010  **/
3011 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
3012                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
3013                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3014 {
3015         struct i40e_aq_desc desc;
3016         struct i40e_aqc_macvlan *cmd =
3017                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3018         enum i40e_status_code status;
3019         u16 buf_size;
3020
3021         if (count == 0 || !mv_list || !hw)
3022                 return I40E_ERR_PARAM;
3023
3024         buf_size = count * sizeof(*mv_list);
3025
3026         /* prep the rest of the request */
3027         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
3028         cmd->num_addresses = CPU_TO_LE16(count);
3029         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3030         cmd->seid[1] = 0;
3031         cmd->seid[2] = 0;
3032
3033         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3034         if (buf_size > I40E_AQ_LARGE_BUF)
3035                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3036
3037         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3038                                        cmd_details);
3039
3040         return status;
3041 }
3042
3043 /**
3044  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3045  * @hw: pointer to the hw struct
3046  * @opcode: AQ opcode for add or delete mirror rule
3047  * @sw_seid: Switch SEID (to which rule refers)
3048  * @rule_type: Rule Type (ingress/egress/VLAN)
3049  * @id: Destination VSI SEID or Rule ID
3050  * @count: length of the list
3051  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3052  * @cmd_details: pointer to command details structure or NULL
3053  * @rule_id: Rule ID returned from FW
3054  * @rule_used: Number of rules used in internal switch
3055  * @rule_free: Number of rules free in internal switch
3056  *
3057  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3058  * VEBs/VEPA elements only
3059  **/
3060 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3061                         u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3062                         u16 count, __le16 *mr_list,
3063                         struct i40e_asq_cmd_details *cmd_details,
3064                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3065 {
3066         struct i40e_aq_desc desc;
3067         struct i40e_aqc_add_delete_mirror_rule *cmd =
3068                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3069         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3070         (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3071         enum i40e_status_code status;
3072         u16 buf_size;
3073
3074         buf_size = count * sizeof(*mr_list);
3075
3076         /* prep the rest of the request */
3077         i40e_fill_default_direct_cmd_desc(&desc, opcode);
3078         cmd->seid = CPU_TO_LE16(sw_seid);
3079         cmd->rule_type = CPU_TO_LE16(rule_type &
3080                                      I40E_AQC_MIRROR_RULE_TYPE_MASK);
3081         cmd->num_entries = CPU_TO_LE16(count);
3082         /* Dest VSI for add, rule_id for delete */
3083         cmd->destination = CPU_TO_LE16(id);
3084         if (mr_list) {
3085                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3086                                                 I40E_AQ_FLAG_RD));
3087                 if (buf_size > I40E_AQ_LARGE_BUF)
3088                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3089         }
3090
3091         status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3092                                        cmd_details);
3093         if (status == I40E_SUCCESS ||
3094             hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3095                 if (rule_id)
3096                         *rule_id = LE16_TO_CPU(resp->rule_id);
3097                 if (rules_used)
3098                         *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3099                 if (rules_free)
3100                         *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3101         }
3102         return status;
3103 }
3104
3105 /**
3106  * i40e_aq_add_mirrorrule - add a mirror rule
3107  * @hw: pointer to the hw struct
3108  * @sw_seid: Switch SEID (to which rule refers)
3109  * @rule_type: Rule Type (ingress/egress/VLAN)
3110  * @dest_vsi: SEID of VSI to which packets will be mirrored
3111  * @count: length of the list
3112  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3113  * @cmd_details: pointer to command details structure or NULL
3114  * @rule_id: Rule ID returned from FW
3115  * @rule_used: Number of rules used in internal switch
3116  * @rule_free: Number of rules free in internal switch
3117  *
3118  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3119  **/
3120 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3121                         u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3122                         struct i40e_asq_cmd_details *cmd_details,
3123                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3124 {
3125         if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3126             rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3127                 if (count == 0 || !mr_list)
3128                         return I40E_ERR_PARAM;
3129         }
3130
3131         return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3132                                   rule_type, dest_vsi, count, mr_list,
3133                                   cmd_details, rule_id, rules_used, rules_free);
3134 }
3135
3136 /**
3137  * i40e_aq_delete_mirrorrule - delete a mirror rule
3138  * @hw: pointer to the hw struct
3139  * @sw_seid: Switch SEID (to which rule refers)
3140  * @rule_type: Rule Type (ingress/egress/VLAN)
3141  * @count: length of the list
3142  * @rule_id: Rule ID that is returned in the receive desc as part of
3143  *              add_mirrorrule.
3144  * @mr_list: list of mirrored VLAN IDs to be removed
3145  * @cmd_details: pointer to command details structure or NULL
3146  * @rule_used: Number of rules used in internal switch
3147  * @rule_free: Number of rules free in internal switch
3148  *
3149  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3150  **/
3151 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3152                         u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3153                         struct i40e_asq_cmd_details *cmd_details,
3154                         u16 *rules_used, u16 *rules_free)
3155 {
3156         /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3157         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3158                 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3159                  * mirroring. For other rule_type, count and rule_type should
3160                  * not matter.
3161                  */
3162                 if (count == 0 || !mr_list)
3163                         return I40E_ERR_PARAM;
3164         }
3165
3166         return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3167                                   rule_type, rule_id, count, mr_list,
3168                                   cmd_details, NULL, rules_used, rules_free);
3169 }
3170
3171 /**
3172  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3173  * @hw: pointer to the hw struct
3174  * @seid: VSI for the vlan filters
3175  * @v_list: list of vlan filters to be added
3176  * @count: length of the list
3177  * @cmd_details: pointer to command details structure or NULL
3178  **/
3179 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3180                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3181                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3182 {
3183         struct i40e_aq_desc desc;
3184         struct i40e_aqc_macvlan *cmd =
3185                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3186         enum i40e_status_code status;
3187         u16 buf_size;
3188
3189         if (count == 0 || !v_list || !hw)
3190                 return I40E_ERR_PARAM;
3191
3192         buf_size = count * sizeof(*v_list);
3193
3194         /* prep the rest of the request */
3195         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3196         cmd->num_addresses = CPU_TO_LE16(count);
3197         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3198         cmd->seid[1] = 0;
3199         cmd->seid[2] = 0;
3200
3201         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3202         if (buf_size > I40E_AQ_LARGE_BUF)
3203                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3204
3205         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3206                                        cmd_details);
3207
3208         return status;
3209 }
3210
3211 /**
3212  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3213  * @hw: pointer to the hw struct
3214  * @seid: VSI for the vlan filters
3215  * @v_list: list of macvlans to be removed
3216  * @count: length of the list
3217  * @cmd_details: pointer to command details structure or NULL
3218  **/
3219 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3220                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3221                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3222 {
3223         struct i40e_aq_desc desc;
3224         struct i40e_aqc_macvlan *cmd =
3225                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3226         enum i40e_status_code status;
3227         u16 buf_size;
3228
3229         if (count == 0 || !v_list || !hw)
3230                 return I40E_ERR_PARAM;
3231
3232         buf_size = count * sizeof(*v_list);
3233
3234         /* prep the rest of the request */
3235         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3236         cmd->num_addresses = CPU_TO_LE16(count);
3237         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3238         cmd->seid[1] = 0;
3239         cmd->seid[2] = 0;
3240
3241         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3242         if (buf_size > I40E_AQ_LARGE_BUF)
3243                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3244
3245         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3246                                        cmd_details);
3247
3248         return status;
3249 }
3250
3251 /**
3252  * i40e_aq_send_msg_to_vf
3253  * @hw: pointer to the hardware structure
3254  * @vfid: vf id to send msg
3255  * @v_opcode: opcodes for VF-PF communication
3256  * @v_retval: return error code
3257  * @msg: pointer to the msg buffer
3258  * @msglen: msg length
3259  * @cmd_details: pointer to command details
3260  *
3261  * send msg to vf
3262  **/
3263 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3264                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3265                                 struct i40e_asq_cmd_details *cmd_details)
3266 {
3267         struct i40e_aq_desc desc;
3268         struct i40e_aqc_pf_vf_message *cmd =
3269                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3270         enum i40e_status_code status;
3271
3272         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3273         cmd->id = CPU_TO_LE32(vfid);
3274         desc.cookie_high = CPU_TO_LE32(v_opcode);
3275         desc.cookie_low = CPU_TO_LE32(v_retval);
3276         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3277         if (msglen) {
3278                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3279                                                 I40E_AQ_FLAG_RD));
3280                 if (msglen > I40E_AQ_LARGE_BUF)
3281                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3282                 desc.datalen = CPU_TO_LE16(msglen);
3283         }
3284         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3285
3286         return status;
3287 }
3288
3289 /**
3290  * i40e_aq_debug_read_register
3291  * @hw: pointer to the hw struct
3292  * @reg_addr: register address
3293  * @reg_val: register value
3294  * @cmd_details: pointer to command details structure or NULL
3295  *
3296  * Read the register using the admin queue commands
3297  **/
3298 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3299                                 u32 reg_addr, u64 *reg_val,
3300                                 struct i40e_asq_cmd_details *cmd_details)
3301 {
3302         struct i40e_aq_desc desc;
3303         struct i40e_aqc_debug_reg_read_write *cmd_resp =
3304                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3305         enum i40e_status_code status;
3306
3307         if (reg_val == NULL)
3308                 return I40E_ERR_PARAM;
3309
3310         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3311
3312         cmd_resp->address = CPU_TO_LE32(reg_addr);
3313
3314         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3315
3316         if (status == I40E_SUCCESS) {
3317                 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3318                            (u64)LE32_TO_CPU(cmd_resp->value_low);
3319         }
3320
3321         return status;
3322 }
3323
3324 /**
3325  * i40e_aq_debug_write_register
3326  * @hw: pointer to the hw struct
3327  * @reg_addr: register address
3328  * @reg_val: register value
3329  * @cmd_details: pointer to command details structure or NULL
3330  *
3331  * Write to a register using the admin queue commands
3332  **/
3333 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3334                                 u32 reg_addr, u64 reg_val,
3335                                 struct i40e_asq_cmd_details *cmd_details)
3336 {
3337         struct i40e_aq_desc desc;
3338         struct i40e_aqc_debug_reg_read_write *cmd =
3339                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3340         enum i40e_status_code status;
3341
3342         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3343
3344         cmd->address = CPU_TO_LE32(reg_addr);
3345         cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3346         cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3347
3348         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3349
3350         return status;
3351 }
3352
3353 /**
3354  * i40e_aq_request_resource
3355  * @hw: pointer to the hw struct
3356  * @resource: resource id
3357  * @access: access type
3358  * @sdp_number: resource number
3359  * @timeout: the maximum time in ms that the driver may hold the resource
3360  * @cmd_details: pointer to command details structure or NULL
3361  *
3362  * requests common resource using the admin queue commands
3363  **/
3364 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3365                                 enum i40e_aq_resources_ids resource,
3366                                 enum i40e_aq_resource_access_type access,
3367                                 u8 sdp_number, u64 *timeout,
3368                                 struct i40e_asq_cmd_details *cmd_details)
3369 {
3370         struct i40e_aq_desc desc;
3371         struct i40e_aqc_request_resource *cmd_resp =
3372                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3373         enum i40e_status_code status;
3374
3375         DEBUGFUNC("i40e_aq_request_resource");
3376
3377         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3378
3379         cmd_resp->resource_id = CPU_TO_LE16(resource);
3380         cmd_resp->access_type = CPU_TO_LE16(access);
3381         cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3382
3383         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3384         /* The completion specifies the maximum time in ms that the driver
3385          * may hold the resource in the Timeout field.
3386          * If the resource is held by someone else, the command completes with
3387          * busy return value and the timeout field indicates the maximum time
3388          * the current owner of the resource has to free it.
3389          */
3390         if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3391                 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3392
3393         return status;
3394 }
3395
3396 /**
3397  * i40e_aq_release_resource
3398  * @hw: pointer to the hw struct
3399  * @resource: resource id
3400  * @sdp_number: resource number
3401  * @cmd_details: pointer to command details structure or NULL
3402  *
3403  * release common resource using the admin queue commands
3404  **/
3405 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3406                                 enum i40e_aq_resources_ids resource,
3407                                 u8 sdp_number,
3408                                 struct i40e_asq_cmd_details *cmd_details)
3409 {
3410         struct i40e_aq_desc desc;
3411         struct i40e_aqc_request_resource *cmd =
3412                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3413         enum i40e_status_code status;
3414
3415         DEBUGFUNC("i40e_aq_release_resource");
3416
3417         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3418
3419         cmd->resource_id = CPU_TO_LE16(resource);
3420         cmd->resource_number = CPU_TO_LE32(sdp_number);
3421
3422         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3423
3424         return status;
3425 }
3426
3427 /**
3428  * i40e_aq_read_nvm
3429  * @hw: pointer to the hw struct
3430  * @module_pointer: module pointer location in words from the NVM beginning
3431  * @offset: byte offset from the module beginning
3432  * @length: length of the section to be read (in bytes from the offset)
3433  * @data: command buffer (size [bytes] = length)
3434  * @last_command: tells if this is the last command in a series
3435  * @cmd_details: pointer to command details structure or NULL
3436  *
3437  * Read the NVM using the admin queue commands
3438  **/
3439 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3440                                 u32 offset, u16 length, void *data,
3441                                 bool last_command,
3442                                 struct i40e_asq_cmd_details *cmd_details)
3443 {
3444         struct i40e_aq_desc desc;
3445         struct i40e_aqc_nvm_update *cmd =
3446                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3447         enum i40e_status_code status;
3448
3449         DEBUGFUNC("i40e_aq_read_nvm");
3450
3451         /* In offset the highest byte must be zeroed. */
3452         if (offset & 0xFF000000) {
3453                 status = I40E_ERR_PARAM;
3454                 goto i40e_aq_read_nvm_exit;
3455         }
3456
3457         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3458
3459         /* If this is the last command in a series, set the proper flag. */
3460         if (last_command)
3461                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3462         cmd->module_pointer = module_pointer;
3463         cmd->offset = CPU_TO_LE32(offset);
3464         cmd->length = CPU_TO_LE16(length);
3465
3466         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3467         if (length > I40E_AQ_LARGE_BUF)
3468                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3469
3470         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3471
3472 i40e_aq_read_nvm_exit:
3473         return status;
3474 }
3475
3476 /**
3477  * i40e_aq_read_nvm_config - read an nvm config block
3478  * @hw: pointer to the hw struct
3479  * @cmd_flags: NVM access admin command bits
3480  * @field_id: field or feature id
3481  * @data: buffer for result
3482  * @buf_size: buffer size
3483  * @element_count: pointer to count of elements read by FW
3484  * @cmd_details: pointer to command details structure or NULL
3485  **/
3486 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3487                                 u8 cmd_flags, u32 field_id, void *data,
3488                                 u16 buf_size, u16 *element_count,
3489                                 struct i40e_asq_cmd_details *cmd_details)
3490 {
3491         struct i40e_aq_desc desc;
3492         struct i40e_aqc_nvm_config_read *cmd =
3493                 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3494         enum i40e_status_code status;
3495
3496         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3497         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3498         if (buf_size > I40E_AQ_LARGE_BUF)
3499                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3500
3501         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3502         cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3503         if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3504                 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3505         else
3506                 cmd->element_id_msw = 0;
3507
3508         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3509
3510         if (!status && element_count)
3511                 *element_count = LE16_TO_CPU(cmd->element_count);
3512
3513         return status;
3514 }
3515
3516 /**
3517  * i40e_aq_write_nvm_config - write an nvm config block
3518  * @hw: pointer to the hw struct
3519  * @cmd_flags: NVM access admin command bits
3520  * @data: buffer for result
3521  * @buf_size: buffer size
3522  * @element_count: count of elements to be written
3523  * @cmd_details: pointer to command details structure or NULL
3524  **/
3525 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3526                                 u8 cmd_flags, void *data, u16 buf_size,
3527                                 u16 element_count,
3528                                 struct i40e_asq_cmd_details *cmd_details)
3529 {
3530         struct i40e_aq_desc desc;
3531         struct i40e_aqc_nvm_config_write *cmd =
3532                 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3533         enum i40e_status_code status;
3534
3535         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3536         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3537         if (buf_size > I40E_AQ_LARGE_BUF)
3538                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3539
3540         cmd->element_count = CPU_TO_LE16(element_count);
3541         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3542         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3543
3544         return status;
3545 }
3546
3547 /**
3548  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3549  * @hw: pointer to the hw struct
3550  * @cmd_details: pointer to command details structure or NULL
3551  **/
3552 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3553                                 void *buff, u16 buff_size,
3554                                 struct i40e_asq_cmd_details *cmd_details)
3555 {
3556         struct i40e_aq_desc desc;
3557         enum i40e_status_code status;
3558
3559         UNREFERENCED_2PARAMETER(buff, buff_size);
3560
3561         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3562         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3563         if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3564                 status = I40E_ERR_NOT_IMPLEMENTED;
3565
3566         return status;
3567 }
3568
3569 /**
3570  * i40e_aq_erase_nvm
3571  * @hw: pointer to the hw struct
3572  * @module_pointer: module pointer location in words from the NVM beginning
3573  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3574  * @length: length of the section to be erased (expressed in 4 KB)
3575  * @last_command: tells if this is the last command in a series
3576  * @cmd_details: pointer to command details structure or NULL
3577  *
3578  * Erase the NVM sector using the admin queue commands
3579  **/
3580 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3581                                 u32 offset, u16 length, bool last_command,
3582                                 struct i40e_asq_cmd_details *cmd_details)
3583 {
3584         struct i40e_aq_desc desc;
3585         struct i40e_aqc_nvm_update *cmd =
3586                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3587         enum i40e_status_code status;
3588
3589         DEBUGFUNC("i40e_aq_erase_nvm");
3590
3591         /* In offset the highest byte must be zeroed. */
3592         if (offset & 0xFF000000) {
3593                 status = I40E_ERR_PARAM;
3594                 goto i40e_aq_erase_nvm_exit;
3595         }
3596
3597         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3598
3599         /* If this is the last command in a series, set the proper flag. */
3600         if (last_command)
3601                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3602         cmd->module_pointer = module_pointer;
3603         cmd->offset = CPU_TO_LE32(offset);
3604         cmd->length = CPU_TO_LE16(length);
3605
3606         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3607
3608 i40e_aq_erase_nvm_exit:
3609         return status;
3610 }
3611
3612 /**
3613  * i40e_parse_discover_capabilities
3614  * @hw: pointer to the hw struct
3615  * @buff: pointer to a buffer containing device/function capability records
3616  * @cap_count: number of capability records in the list
3617  * @list_type_opc: type of capabilities list to parse
3618  *
3619  * Parse the device/function capabilities list.
3620  **/
3621 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3622                                      u32 cap_count,
3623                                      enum i40e_admin_queue_opc list_type_opc)
3624 {
3625         struct i40e_aqc_list_capabilities_element_resp *cap;
3626         u32 valid_functions, num_functions;
3627         u32 number, logical_id, phys_id;
3628         struct i40e_hw_capabilities *p;
3629         u8 major_rev;
3630         u32 i = 0;
3631         u16 id;
3632
3633         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3634
3635         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3636                 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3637         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3638                 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3639         else
3640                 return;
3641
3642         for (i = 0; i < cap_count; i++, cap++) {
3643                 id = LE16_TO_CPU(cap->id);
3644                 number = LE32_TO_CPU(cap->number);
3645                 logical_id = LE32_TO_CPU(cap->logical_id);
3646                 phys_id = LE32_TO_CPU(cap->phys_id);
3647                 major_rev = cap->major_rev;
3648
3649                 switch (id) {
3650                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3651                         p->switch_mode = number;
3652                         i40e_debug(hw, I40E_DEBUG_INIT,
3653                                    "HW Capability: Switch mode = %d\n",
3654                                    p->switch_mode);
3655                         break;
3656                 case I40E_AQ_CAP_ID_MNG_MODE:
3657                         p->management_mode = number;
3658                         if (major_rev > 1) {
3659                                 p->mng_protocols_over_mctp = logical_id;
3660                                 i40e_debug(hw, I40E_DEBUG_INIT,
3661                                            "HW Capability: Protocols over MCTP = %d\n",
3662                                            p->mng_protocols_over_mctp);
3663                         } else {
3664                                 p->mng_protocols_over_mctp = 0;
3665                         }
3666                         i40e_debug(hw, I40E_DEBUG_INIT,
3667                                    "HW Capability: Management Mode = %d\n",
3668                                    p->management_mode);
3669                         break;
3670                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3671                         p->npar_enable = number;
3672                         i40e_debug(hw, I40E_DEBUG_INIT,
3673                                    "HW Capability: NPAR enable = %d\n",
3674                                    p->npar_enable);
3675                         break;
3676                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3677                         p->os2bmc = number;
3678                         i40e_debug(hw, I40E_DEBUG_INIT,
3679                                    "HW Capability: OS2BMC = %d\n", p->os2bmc);
3680                         break;
3681                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3682                         p->valid_functions = number;
3683                         i40e_debug(hw, I40E_DEBUG_INIT,
3684                                    "HW Capability: Valid Functions = %d\n",
3685                                    p->valid_functions);
3686                         break;
3687                 case I40E_AQ_CAP_ID_SRIOV:
3688                         if (number == 1)
3689                                 p->sr_iov_1_1 = true;
3690                         i40e_debug(hw, I40E_DEBUG_INIT,
3691                                    "HW Capability: SR-IOV = %d\n",
3692                                    p->sr_iov_1_1);
3693                         break;
3694                 case I40E_AQ_CAP_ID_VF:
3695                         p->num_vfs = number;
3696                         p->vf_base_id = logical_id;
3697                         i40e_debug(hw, I40E_DEBUG_INIT,
3698                                    "HW Capability: VF count = %d\n",
3699                                    p->num_vfs);
3700                         i40e_debug(hw, I40E_DEBUG_INIT,
3701                                    "HW Capability: VF base_id = %d\n",
3702                                    p->vf_base_id);
3703                         break;
3704                 case I40E_AQ_CAP_ID_VMDQ:
3705                         if (number == 1)
3706                                 p->vmdq = true;
3707                         i40e_debug(hw, I40E_DEBUG_INIT,
3708                                    "HW Capability: VMDQ = %d\n", p->vmdq);
3709                         break;
3710                 case I40E_AQ_CAP_ID_8021QBG:
3711                         if (number == 1)
3712                                 p->evb_802_1_qbg = true;
3713                         i40e_debug(hw, I40E_DEBUG_INIT,
3714                                    "HW Capability: 802.1Qbg = %d\n", number);
3715                         break;
3716                 case I40E_AQ_CAP_ID_8021QBR:
3717                         if (number == 1)
3718                                 p->evb_802_1_qbh = true;
3719                         i40e_debug(hw, I40E_DEBUG_INIT,
3720                                    "HW Capability: 802.1Qbh = %d\n", number);
3721                         break;
3722                 case I40E_AQ_CAP_ID_VSI:
3723                         p->num_vsis = number;
3724                         i40e_debug(hw, I40E_DEBUG_INIT,
3725                                    "HW Capability: VSI count = %d\n",
3726                                    p->num_vsis);
3727                         break;
3728                 case I40E_AQ_CAP_ID_DCB:
3729                         if (number == 1) {
3730                                 p->dcb = true;
3731                                 p->enabled_tcmap = logical_id;
3732                                 p->maxtc = phys_id;
3733                         }
3734                         i40e_debug(hw, I40E_DEBUG_INIT,
3735                                    "HW Capability: DCB = %d\n", p->dcb);
3736                         i40e_debug(hw, I40E_DEBUG_INIT,
3737                                    "HW Capability: TC Mapping = %d\n",
3738                                    logical_id);
3739                         i40e_debug(hw, I40E_DEBUG_INIT,
3740                                    "HW Capability: TC Max = %d\n", p->maxtc);
3741                         break;
3742                 case I40E_AQ_CAP_ID_FCOE:
3743                         if (number == 1)
3744                                 p->fcoe = true;
3745                         i40e_debug(hw, I40E_DEBUG_INIT,
3746                                    "HW Capability: FCOE = %d\n", p->fcoe);
3747                         break;
3748                 case I40E_AQ_CAP_ID_ISCSI:
3749                         if (number == 1)
3750                                 p->iscsi = true;
3751                         i40e_debug(hw, I40E_DEBUG_INIT,
3752                                    "HW Capability: iSCSI = %d\n", p->iscsi);
3753                         break;
3754                 case I40E_AQ_CAP_ID_RSS:
3755                         p->rss = true;
3756                         p->rss_table_size = number;
3757                         p->rss_table_entry_width = logical_id;
3758                         i40e_debug(hw, I40E_DEBUG_INIT,
3759                                    "HW Capability: RSS = %d\n", p->rss);
3760                         i40e_debug(hw, I40E_DEBUG_INIT,
3761                                    "HW Capability: RSS table size = %d\n",
3762                                    p->rss_table_size);
3763                         i40e_debug(hw, I40E_DEBUG_INIT,
3764                                    "HW Capability: RSS table width = %d\n",
3765                                    p->rss_table_entry_width);
3766                         break;
3767                 case I40E_AQ_CAP_ID_RXQ:
3768                         p->num_rx_qp = number;
3769                         p->base_queue = phys_id;
3770                         i40e_debug(hw, I40E_DEBUG_INIT,
3771                                    "HW Capability: Rx QP = %d\n", number);
3772                         i40e_debug(hw, I40E_DEBUG_INIT,
3773                                    "HW Capability: base_queue = %d\n",
3774                                    p->base_queue);
3775                         break;
3776                 case I40E_AQ_CAP_ID_TXQ:
3777                         p->num_tx_qp = number;
3778                         p->base_queue = phys_id;
3779                         i40e_debug(hw, I40E_DEBUG_INIT,
3780                                    "HW Capability: Tx QP = %d\n", number);
3781                         i40e_debug(hw, I40E_DEBUG_INIT,
3782                                    "HW Capability: base_queue = %d\n",
3783                                    p->base_queue);
3784                         break;
3785                 case I40E_AQ_CAP_ID_MSIX:
3786                         p->num_msix_vectors = number;
3787                         i40e_debug(hw, I40E_DEBUG_INIT,
3788                                    "HW Capability: MSIX vector count = %d\n",
3789                                    p->num_msix_vectors);
3790                         break;
3791                 case I40E_AQ_CAP_ID_VF_MSIX:
3792                         p->num_msix_vectors_vf = number;
3793                         i40e_debug(hw, I40E_DEBUG_INIT,
3794                                    "HW Capability: MSIX VF vector count = %d\n",
3795                                    p->num_msix_vectors_vf);
3796                         break;
3797                 case I40E_AQ_CAP_ID_FLEX10:
3798                         if (major_rev == 1) {
3799                                 if (number == 1) {
3800                                         p->flex10_enable = true;
3801                                         p->flex10_capable = true;
3802                                 }
3803                         } else {
3804                                 /* Capability revision >= 2 */
3805                                 if (number & 1)
3806                                         p->flex10_enable = true;
3807                                 if (number & 2)
3808                                         p->flex10_capable = true;
3809                         }
3810                         p->flex10_mode = logical_id;
3811                         p->flex10_status = phys_id;
3812                         i40e_debug(hw, I40E_DEBUG_INIT,
3813                                    "HW Capability: Flex10 mode = %d\n",
3814                                    p->flex10_mode);
3815                         i40e_debug(hw, I40E_DEBUG_INIT,
3816                                    "HW Capability: Flex10 status = %d\n",
3817                                    p->flex10_status);
3818                         break;
3819                 case I40E_AQ_CAP_ID_CEM:
3820                         if (number == 1)
3821                                 p->mgmt_cem = true;
3822                         i40e_debug(hw, I40E_DEBUG_INIT,
3823                                    "HW Capability: CEM = %d\n", p->mgmt_cem);
3824                         break;
3825                 case I40E_AQ_CAP_ID_IWARP:
3826                         if (number == 1)
3827                                 p->iwarp = true;
3828                         i40e_debug(hw, I40E_DEBUG_INIT,
3829                                    "HW Capability: iWARP = %d\n", p->iwarp);
3830                         break;
3831                 case I40E_AQ_CAP_ID_LED:
3832                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3833                                 p->led[phys_id] = true;
3834                         i40e_debug(hw, I40E_DEBUG_INIT,
3835                                    "HW Capability: LED - PIN %d\n", phys_id);
3836                         break;
3837                 case I40E_AQ_CAP_ID_SDP:
3838                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3839                                 p->sdp[phys_id] = true;
3840                         i40e_debug(hw, I40E_DEBUG_INIT,
3841                                    "HW Capability: SDP - PIN %d\n", phys_id);
3842                         break;
3843                 case I40E_AQ_CAP_ID_MDIO:
3844                         if (number == 1) {
3845                                 p->mdio_port_num = phys_id;
3846                                 p->mdio_port_mode = logical_id;
3847                         }
3848                         i40e_debug(hw, I40E_DEBUG_INIT,
3849                                    "HW Capability: MDIO port number = %d\n",
3850                                    p->mdio_port_num);
3851                         i40e_debug(hw, I40E_DEBUG_INIT,
3852                                    "HW Capability: MDIO port mode = %d\n",
3853                                    p->mdio_port_mode);
3854                         break;
3855                 case I40E_AQ_CAP_ID_1588:
3856                         if (number == 1)
3857                                 p->ieee_1588 = true;
3858                         i40e_debug(hw, I40E_DEBUG_INIT,
3859                                    "HW Capability: IEEE 1588 = %d\n",
3860                                    p->ieee_1588);
3861                         break;
3862                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3863                         p->fd = true;
3864                         p->fd_filters_guaranteed = number;
3865                         p->fd_filters_best_effort = logical_id;
3866                         i40e_debug(hw, I40E_DEBUG_INIT,
3867                                    "HW Capability: Flow Director = 1\n");
3868                         i40e_debug(hw, I40E_DEBUG_INIT,
3869                                    "HW Capability: Guaranteed FD filters = %d\n",
3870                                    p->fd_filters_guaranteed);
3871                         break;
3872                 case I40E_AQ_CAP_ID_WSR_PROT:
3873                         p->wr_csr_prot = (u64)number;
3874                         p->wr_csr_prot |= (u64)logical_id << 32;
3875                         i40e_debug(hw, I40E_DEBUG_INIT,
3876                                    "HW Capability: wr_csr_prot = 0x%llX\n\n",
3877                                    (p->wr_csr_prot & 0xffff));
3878                         break;
3879                 case I40E_AQ_CAP_ID_NVM_MGMT:
3880                         if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3881                                 p->sec_rev_disabled = true;
3882                         if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3883                                 p->update_disabled = true;
3884                         break;
3885 #ifdef X722_SUPPORT
3886                 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3887                         hw->num_wol_proxy_filters = (u16)number;
3888                         hw->wol_proxy_vsi_seid = (u16)logical_id;
3889                         p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3890                         if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3891                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3892                         else
3893                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3894                         p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3895                         i40e_debug(hw, I40E_DEBUG_INIT,
3896                                    "HW Capability: WOL proxy filters = %d\n",
3897                                    hw->num_wol_proxy_filters);
3898                         break;
3899 #endif
3900                 default:
3901                         break;
3902                 }
3903         }
3904
3905         if (p->fcoe)
3906                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3907
3908         /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3909         p->fcoe = false;
3910
3911         /* count the enabled ports (aka the "not disabled" ports) */
3912         hw->num_ports = 0;
3913         for (i = 0; i < 4; i++) {
3914                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3915                 u64 port_cfg = 0;
3916
3917                 /* use AQ read to get the physical register offset instead
3918                  * of the port relative offset
3919                  */
3920                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3921                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3922                         hw->num_ports++;
3923         }
3924
3925         valid_functions = p->valid_functions;
3926         num_functions = 0;
3927         while (valid_functions) {
3928                 if (valid_functions & 1)
3929                         num_functions++;
3930                 valid_functions >>= 1;
3931         }
3932
3933         /* partition id is 1-based, and functions are evenly spread
3934          * across the ports as partitions
3935          */
3936         hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3937         hw->num_partitions = num_functions / hw->num_ports;
3938
3939         /* additional HW specific goodies that might
3940          * someday be HW version specific
3941          */
3942         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3943 }
3944
3945 /**
3946  * i40e_aq_discover_capabilities
3947  * @hw: pointer to the hw struct
3948  * @buff: a virtual buffer to hold the capabilities
3949  * @buff_size: Size of the virtual buffer
3950  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3951  * @list_type_opc: capabilities type to discover - pass in the command opcode
3952  * @cmd_details: pointer to command details structure or NULL
3953  *
3954  * Get the device capabilities descriptions from the firmware
3955  **/
3956 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3957                                 void *buff, u16 buff_size, u16 *data_size,
3958                                 enum i40e_admin_queue_opc list_type_opc,
3959                                 struct i40e_asq_cmd_details *cmd_details)
3960 {
3961         struct i40e_aqc_list_capabilites *cmd;
3962         struct i40e_aq_desc desc;
3963         enum i40e_status_code status = I40E_SUCCESS;
3964
3965         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3966
3967         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3968                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3969                 status = I40E_ERR_PARAM;
3970                 goto exit;
3971         }
3972
3973         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3974
3975         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3976         if (buff_size > I40E_AQ_LARGE_BUF)
3977                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3978
3979         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3980         *data_size = LE16_TO_CPU(desc.datalen);
3981
3982         if (status)
3983                 goto exit;
3984
3985         i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3986                                          list_type_opc);
3987
3988 exit:
3989         return status;
3990 }
3991
3992 /**
3993  * i40e_aq_update_nvm
3994  * @hw: pointer to the hw struct
3995  * @module_pointer: module pointer location in words from the NVM beginning
3996  * @offset: byte offset from the module beginning
3997  * @length: length of the section to be written (in bytes from the offset)
3998  * @data: command buffer (size [bytes] = length)
3999  * @last_command: tells if this is the last command in a series
4000  * @cmd_details: pointer to command details structure or NULL
4001  *
4002  * Update the NVM using the admin queue commands
4003  **/
4004 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
4005                                 u32 offset, u16 length, void *data,
4006                                 bool last_command,
4007                                 struct i40e_asq_cmd_details *cmd_details)
4008 {
4009         struct i40e_aq_desc desc;
4010         struct i40e_aqc_nvm_update *cmd =
4011                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
4012         enum i40e_status_code status;
4013
4014         DEBUGFUNC("i40e_aq_update_nvm");
4015
4016         /* In offset the highest byte must be zeroed. */
4017         if (offset & 0xFF000000) {
4018                 status = I40E_ERR_PARAM;
4019                 goto i40e_aq_update_nvm_exit;
4020         }
4021
4022         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4023
4024         /* If this is the last command in a series, set the proper flag. */
4025         if (last_command)
4026                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
4027         cmd->module_pointer = module_pointer;
4028         cmd->offset = CPU_TO_LE32(offset);
4029         cmd->length = CPU_TO_LE16(length);
4030
4031         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4032         if (length > I40E_AQ_LARGE_BUF)
4033                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4034
4035         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
4036
4037 i40e_aq_update_nvm_exit:
4038         return status;
4039 }
4040
4041 /**
4042  * i40e_aq_get_lldp_mib
4043  * @hw: pointer to the hw struct
4044  * @bridge_type: type of bridge requested
4045  * @mib_type: Local, Remote or both Local and Remote MIBs
4046  * @buff: pointer to a user supplied buffer to store the MIB block
4047  * @buff_size: size of the buffer (in bytes)
4048  * @local_len : length of the returned Local LLDP MIB
4049  * @remote_len: length of the returned Remote LLDP MIB
4050  * @cmd_details: pointer to command details structure or NULL
4051  *
4052  * Requests the complete LLDP MIB (entire packet).
4053  **/
4054 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4055                                 u8 mib_type, void *buff, u16 buff_size,
4056                                 u16 *local_len, u16 *remote_len,
4057                                 struct i40e_asq_cmd_details *cmd_details)
4058 {
4059         struct i40e_aq_desc desc;
4060         struct i40e_aqc_lldp_get_mib *cmd =
4061                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4062         struct i40e_aqc_lldp_get_mib *resp =
4063                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4064         enum i40e_status_code status;
4065
4066         if (buff_size == 0 || !buff)
4067                 return I40E_ERR_PARAM;
4068
4069         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4070         /* Indirect Command */
4071         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4072
4073         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4074         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4075                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4076
4077         desc.datalen = CPU_TO_LE16(buff_size);
4078
4079         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4080         if (buff_size > I40E_AQ_LARGE_BUF)
4081                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4082
4083         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4084         if (!status) {
4085                 if (local_len != NULL)
4086                         *local_len = LE16_TO_CPU(resp->local_len);
4087                 if (remote_len != NULL)
4088                         *remote_len = LE16_TO_CPU(resp->remote_len);
4089         }
4090
4091         return status;
4092 }
4093
4094  /**
4095  * i40e_aq_set_lldp_mib - Set the LLDP MIB
4096  * @hw: pointer to the hw struct
4097  * @mib_type: Local, Remote or both Local and Remote MIBs
4098  * @buff: pointer to a user supplied buffer to store the MIB block
4099  * @buff_size: size of the buffer (in bytes)
4100  * @cmd_details: pointer to command details structure or NULL
4101  *
4102  * Set the LLDP MIB.
4103  **/
4104 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4105                                 u8 mib_type, void *buff, u16 buff_size,
4106                                 struct i40e_asq_cmd_details *cmd_details)
4107 {
4108         struct i40e_aq_desc desc;
4109         struct i40e_aqc_lldp_set_local_mib *cmd =
4110                 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4111         enum i40e_status_code status;
4112
4113         if (buff_size == 0 || !buff)
4114                 return I40E_ERR_PARAM;
4115
4116         i40e_fill_default_direct_cmd_desc(&desc,
4117                                 i40e_aqc_opc_lldp_set_local_mib);
4118         /* Indirect Command */
4119         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4120         if (buff_size > I40E_AQ_LARGE_BUF)
4121                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4122         desc.datalen = CPU_TO_LE16(buff_size);
4123
4124         cmd->type = mib_type;
4125         cmd->length = CPU_TO_LE16(buff_size);
4126         cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4127         cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4128
4129         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4130         return status;
4131 }
4132
4133 /**
4134  * i40e_aq_cfg_lldp_mib_change_event
4135  * @hw: pointer to the hw struct
4136  * @enable_update: Enable or Disable event posting
4137  * @cmd_details: pointer to command details structure or NULL
4138  *
4139  * Enable or Disable posting of an event on ARQ when LLDP MIB
4140  * associated with the interface changes
4141  **/
4142 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4143                                 bool enable_update,
4144                                 struct i40e_asq_cmd_details *cmd_details)
4145 {
4146         struct i40e_aq_desc desc;
4147         struct i40e_aqc_lldp_update_mib *cmd =
4148                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4149         enum i40e_status_code status;
4150
4151         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4152
4153         if (!enable_update)
4154                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4155
4156         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4157
4158         return status;
4159 }
4160
4161 /**
4162  * i40e_aq_add_lldp_tlv
4163  * @hw: pointer to the hw struct
4164  * @bridge_type: type of bridge
4165  * @buff: buffer with TLV to add
4166  * @buff_size: length of the buffer
4167  * @tlv_len: length of the TLV to be added
4168  * @mib_len: length of the LLDP MIB returned in response
4169  * @cmd_details: pointer to command details structure or NULL
4170  *
4171  * Add the specified TLV to LLDP Local MIB for the given bridge type,
4172  * it is responsibility of the caller to make sure that the TLV is not
4173  * already present in the LLDPDU.
4174  * In return firmware will write the complete LLDP MIB with the newly
4175  * added TLV in the response buffer.
4176  **/
4177 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4178                                 void *buff, u16 buff_size, u16 tlv_len,
4179                                 u16 *mib_len,
4180                                 struct i40e_asq_cmd_details *cmd_details)
4181 {
4182         struct i40e_aq_desc desc;
4183         struct i40e_aqc_lldp_add_tlv *cmd =
4184                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4185         enum i40e_status_code status;
4186
4187         if (buff_size == 0 || !buff || tlv_len == 0)
4188                 return I40E_ERR_PARAM;
4189
4190         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4191
4192         /* Indirect Command */
4193         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4194         if (buff_size > I40E_AQ_LARGE_BUF)
4195                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4196         desc.datalen = CPU_TO_LE16(buff_size);
4197
4198         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4199                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4200         cmd->len = CPU_TO_LE16(tlv_len);
4201
4202         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4203         if (!status) {
4204                 if (mib_len != NULL)
4205                         *mib_len = LE16_TO_CPU(desc.datalen);
4206         }
4207
4208         return status;
4209 }
4210
4211 /**
4212  * i40e_aq_update_lldp_tlv
4213  * @hw: pointer to the hw struct
4214  * @bridge_type: type of bridge
4215  * @buff: buffer with TLV to update
4216  * @buff_size: size of the buffer holding original and updated TLVs
4217  * @old_len: Length of the Original TLV
4218  * @new_len: Length of the Updated TLV
4219  * @offset: offset of the updated TLV in the buff
4220  * @mib_len: length of the returned LLDP MIB
4221  * @cmd_details: pointer to command details structure or NULL
4222  *
4223  * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4224  * Firmware will place the complete LLDP MIB in response buffer with the
4225  * updated TLV.
4226  **/
4227 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4228                                 u8 bridge_type, void *buff, u16 buff_size,
4229                                 u16 old_len, u16 new_len, u16 offset,
4230                                 u16 *mib_len,
4231                                 struct i40e_asq_cmd_details *cmd_details)
4232 {
4233         struct i40e_aq_desc desc;
4234         struct i40e_aqc_lldp_update_tlv *cmd =
4235                 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4236         enum i40e_status_code status;
4237
4238         if (buff_size == 0 || !buff || offset == 0 ||
4239             old_len == 0 || new_len == 0)
4240                 return I40E_ERR_PARAM;
4241
4242         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4243
4244         /* Indirect Command */
4245         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4246         if (buff_size > I40E_AQ_LARGE_BUF)
4247                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4248         desc.datalen = CPU_TO_LE16(buff_size);
4249
4250         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4251                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4252         cmd->old_len = CPU_TO_LE16(old_len);
4253         cmd->new_offset = CPU_TO_LE16(offset);
4254         cmd->new_len = CPU_TO_LE16(new_len);
4255
4256         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4257         if (!status) {
4258                 if (mib_len != NULL)
4259                         *mib_len = LE16_TO_CPU(desc.datalen);
4260         }
4261
4262         return status;
4263 }
4264
4265 /**
4266  * i40e_aq_delete_lldp_tlv
4267  * @hw: pointer to the hw struct
4268  * @bridge_type: type of bridge
4269  * @buff: pointer to a user supplied buffer that has the TLV
4270  * @buff_size: length of the buffer
4271  * @tlv_len: length of the TLV to be deleted
4272  * @mib_len: length of the returned LLDP MIB
4273  * @cmd_details: pointer to command details structure or NULL
4274  *
4275  * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4276  * The firmware places the entire LLDP MIB in the response buffer.
4277  **/
4278 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4279                                 u8 bridge_type, void *buff, u16 buff_size,
4280                                 u16 tlv_len, u16 *mib_len,
4281                                 struct i40e_asq_cmd_details *cmd_details)
4282 {
4283         struct i40e_aq_desc desc;
4284         struct i40e_aqc_lldp_add_tlv *cmd =
4285                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4286         enum i40e_status_code status;
4287
4288         if (buff_size == 0 || !buff)
4289                 return I40E_ERR_PARAM;
4290
4291         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4292
4293         /* Indirect Command */
4294         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4295         if (buff_size > I40E_AQ_LARGE_BUF)
4296                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4297         desc.datalen = CPU_TO_LE16(buff_size);
4298         cmd->len = CPU_TO_LE16(tlv_len);
4299         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4300                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4301
4302         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4303         if (!status) {
4304                 if (mib_len != NULL)
4305                         *mib_len = LE16_TO_CPU(desc.datalen);
4306         }
4307
4308         return status;
4309 }
4310
4311 /**
4312  * i40e_aq_stop_lldp
4313  * @hw: pointer to the hw struct
4314  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4315  * @cmd_details: pointer to command details structure or NULL
4316  *
4317  * Stop or Shutdown the embedded LLDP Agent
4318  **/
4319 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4320                                 struct i40e_asq_cmd_details *cmd_details)
4321 {
4322         struct i40e_aq_desc desc;
4323         struct i40e_aqc_lldp_stop *cmd =
4324                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4325         enum i40e_status_code status;
4326
4327         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4328
4329         if (shutdown_agent)
4330                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4331
4332         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4333
4334         return status;
4335 }
4336
4337 /**
4338  * i40e_aq_start_lldp
4339  * @hw: pointer to the hw struct
4340  * @cmd_details: pointer to command details structure or NULL
4341  *
4342  * Start the embedded LLDP Agent on all ports.
4343  **/
4344 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4345                                 struct i40e_asq_cmd_details *cmd_details)
4346 {
4347         struct i40e_aq_desc desc;
4348         struct i40e_aqc_lldp_start *cmd =
4349                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4350         enum i40e_status_code status;
4351
4352         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4353
4354         cmd->command = I40E_AQ_LLDP_AGENT_START;
4355
4356         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4357
4358         return status;
4359 }
4360
4361 /**
4362  * i40e_aq_get_cee_dcb_config
4363  * @hw: pointer to the hw struct
4364  * @buff: response buffer that stores CEE operational configuration
4365  * @buff_size: size of the buffer passed
4366  * @cmd_details: pointer to command details structure or NULL
4367  *
4368  * Get CEE DCBX mode operational configuration from firmware
4369  **/
4370 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4371                                 void *buff, u16 buff_size,
4372                                 struct i40e_asq_cmd_details *cmd_details)
4373 {
4374         struct i40e_aq_desc desc;
4375         enum i40e_status_code status;
4376
4377         if (buff_size == 0 || !buff)
4378                 return I40E_ERR_PARAM;
4379
4380         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4381
4382         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4383         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4384                                        cmd_details);
4385
4386         return status;
4387 }
4388
4389 /**
4390  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4391  * @hw: pointer to the hw struct
4392  * @start_agent: True if DCBx Agent needs to be Started
4393  *                              False if DCBx Agent needs to be Stopped
4394  * @cmd_details: pointer to command details structure or NULL
4395  *
4396  * Start/Stop the embedded dcbx Agent
4397  **/
4398 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4399                                 bool start_agent,
4400                                 struct i40e_asq_cmd_details *cmd_details)
4401 {
4402         struct i40e_aq_desc desc;
4403         struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4404                 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4405                                 &desc.params.raw;
4406         enum i40e_status_code status;
4407
4408         i40e_fill_default_direct_cmd_desc(&desc,
4409                                 i40e_aqc_opc_lldp_stop_start_spec_agent);
4410
4411         if (start_agent)
4412                 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4413
4414         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4415
4416         return status;
4417 }
4418
4419 /**
4420  * i40e_aq_add_udp_tunnel
4421  * @hw: pointer to the hw struct
4422  * @udp_port: the UDP port to add
4423  * @header_len: length of the tunneling header length in DWords
4424  * @protocol_index: protocol index type
4425  * @filter_index: pointer to filter index
4426  * @cmd_details: pointer to command details structure or NULL
4427  **/
4428 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4429                                 u16 udp_port, u8 protocol_index,
4430                                 u8 *filter_index,
4431                                 struct i40e_asq_cmd_details *cmd_details)
4432 {
4433         struct i40e_aq_desc desc;
4434         struct i40e_aqc_add_udp_tunnel *cmd =
4435                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4436         struct i40e_aqc_del_udp_tunnel_completion *resp =
4437                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4438         enum i40e_status_code status;
4439
4440         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4441
4442         cmd->udp_port = CPU_TO_LE16(udp_port);
4443         cmd->protocol_type = protocol_index;
4444
4445         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4446
4447         if (!status && filter_index)
4448                 *filter_index = resp->index;
4449
4450         return status;
4451 }
4452
4453 /**
4454  * i40e_aq_del_udp_tunnel
4455  * @hw: pointer to the hw struct
4456  * @index: filter index
4457  * @cmd_details: pointer to command details structure or NULL
4458  **/
4459 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4460                                 struct i40e_asq_cmd_details *cmd_details)
4461 {
4462         struct i40e_aq_desc desc;
4463         struct i40e_aqc_remove_udp_tunnel *cmd =
4464                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4465         enum i40e_status_code status;
4466
4467         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4468
4469         cmd->index = index;
4470
4471         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4472
4473         return status;
4474 }
4475
4476 /**
4477  * i40e_aq_get_switch_resource_alloc (0x0204)
4478  * @hw: pointer to the hw struct
4479  * @num_entries: pointer to u8 to store the number of resource entries returned
4480  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
4481  *        to store the resource information for all resource types.  Each
4482  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
4483  * @count: size, in bytes, of the buffer provided
4484  * @cmd_details: pointer to command details structure or NULL
4485  *
4486  * Query the resources allocated to a function.
4487  **/
4488 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4489                         u8 *num_entries,
4490                         struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4491                         u16 count,
4492                         struct i40e_asq_cmd_details *cmd_details)
4493 {
4494         struct i40e_aq_desc desc;
4495         struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4496                 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4497         enum i40e_status_code status;
4498         u16 length = count * sizeof(*buf);
4499
4500         i40e_fill_default_direct_cmd_desc(&desc,
4501                                         i40e_aqc_opc_get_switch_resource_alloc);
4502
4503         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4504         if (length > I40E_AQ_LARGE_BUF)
4505                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4506
4507         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4508
4509         if (!status && num_entries)
4510                 *num_entries = cmd_resp->num_entries;
4511
4512         return status;
4513 }
4514
4515 /**
4516  * i40e_aq_delete_element - Delete switch element
4517  * @hw: pointer to the hw struct
4518  * @seid: the SEID to delete from the switch
4519  * @cmd_details: pointer to command details structure or NULL
4520  *
4521  * This deletes a switch element from the switch.
4522  **/
4523 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4524                                 struct i40e_asq_cmd_details *cmd_details)
4525 {
4526         struct i40e_aq_desc desc;
4527         struct i40e_aqc_switch_seid *cmd =
4528                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4529         enum i40e_status_code status;
4530
4531         if (seid == 0)
4532                 return I40E_ERR_PARAM;
4533
4534         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4535
4536         cmd->seid = CPU_TO_LE16(seid);
4537
4538         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4539
4540         return status;
4541 }
4542
4543 /**
4544  * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4545  * @hw: pointer to the hw struct
4546  * @flags: component flags
4547  * @mac_seid: uplink seid (MAC SEID)
4548  * @vsi_seid: connected vsi seid
4549  * @ret_seid: seid of create pv component
4550  *
4551  * This instantiates an i40e port virtualizer with specified flags.
4552  * Depending on specified flags the port virtualizer can act as a
4553  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4554  */
4555 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4556                                        u16 mac_seid, u16 vsi_seid,
4557                                        u16 *ret_seid)
4558 {
4559         struct i40e_aq_desc desc;
4560         struct i40e_aqc_add_update_pv *cmd =
4561                 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4562         struct i40e_aqc_add_update_pv_completion *resp =
4563                 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4564         enum i40e_status_code status;
4565
4566         if (vsi_seid == 0)
4567                 return I40E_ERR_PARAM;
4568
4569         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4570         cmd->command_flags = CPU_TO_LE16(flags);
4571         cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4572         cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4573
4574         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4575         if (!status && ret_seid)
4576                 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4577
4578         return status;
4579 }
4580
4581 /**
4582  * i40e_aq_add_tag - Add an S/E-tag
4583  * @hw: pointer to the hw struct
4584  * @direct_to_queue: should s-tag direct flow to a specific queue
4585  * @vsi_seid: VSI SEID to use this tag
4586  * @tag: value of the tag
4587  * @queue_num: queue number, only valid is direct_to_queue is true
4588  * @tags_used: return value, number of tags in use by this PF
4589  * @tags_free: return value, number of unallocated tags
4590  * @cmd_details: pointer to command details structure or NULL
4591  *
4592  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4593  * the number of tags allocated by the PF, and the number of unallocated
4594  * tags available.
4595  **/
4596 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4597                                 u16 vsi_seid, u16 tag, u16 queue_num,
4598                                 u16 *tags_used, u16 *tags_free,
4599                                 struct i40e_asq_cmd_details *cmd_details)
4600 {
4601         struct i40e_aq_desc desc;
4602         struct i40e_aqc_add_tag *cmd =
4603                 (struct i40e_aqc_add_tag *)&desc.params.raw;
4604         struct i40e_aqc_add_remove_tag_completion *resp =
4605                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4606         enum i40e_status_code status;
4607
4608         if (vsi_seid == 0)
4609                 return I40E_ERR_PARAM;
4610
4611         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4612
4613         cmd->seid = CPU_TO_LE16(vsi_seid);
4614         cmd->tag = CPU_TO_LE16(tag);
4615         if (direct_to_queue) {
4616                 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4617                 cmd->queue_number = CPU_TO_LE16(queue_num);
4618         }
4619
4620         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4621
4622         if (!status) {
4623                 if (tags_used != NULL)
4624                         *tags_used = LE16_TO_CPU(resp->tags_used);
4625                 if (tags_free != NULL)
4626                         *tags_free = LE16_TO_CPU(resp->tags_free);
4627         }
4628
4629         return status;
4630 }
4631
4632 /**
4633  * i40e_aq_remove_tag - Remove an S- or E-tag
4634  * @hw: pointer to the hw struct
4635  * @vsi_seid: VSI SEID this tag is associated with
4636  * @tag: value of the S-tag to delete
4637  * @tags_used: return value, number of tags in use by this PF
4638  * @tags_free: return value, number of unallocated tags
4639  * @cmd_details: pointer to command details structure or NULL
4640  *
4641  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4642  * the number of tags allocated by the PF, and the number of unallocated
4643  * tags available.
4644  **/
4645 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4646                                 u16 tag, u16 *tags_used, u16 *tags_free,
4647                                 struct i40e_asq_cmd_details *cmd_details)
4648 {
4649         struct i40e_aq_desc desc;
4650         struct i40e_aqc_remove_tag *cmd =
4651                 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4652         struct i40e_aqc_add_remove_tag_completion *resp =
4653                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4654         enum i40e_status_code status;
4655
4656         if (vsi_seid == 0)
4657                 return I40E_ERR_PARAM;
4658
4659         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4660
4661         cmd->seid = CPU_TO_LE16(vsi_seid);
4662         cmd->tag = CPU_TO_LE16(tag);
4663
4664         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4665
4666         if (!status) {
4667                 if (tags_used != NULL)
4668                         *tags_used = LE16_TO_CPU(resp->tags_used);
4669                 if (tags_free != NULL)
4670                         *tags_free = LE16_TO_CPU(resp->tags_free);
4671         }
4672
4673         return status;
4674 }
4675
4676 /**
4677  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4678  * @hw: pointer to the hw struct
4679  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4680  * @etag: value of E-tag to add
4681  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4682  * @buf: address of indirect buffer
4683  * @tags_used: return value, number of E-tags in use by this port
4684  * @tags_free: return value, number of unallocated M-tags
4685  * @cmd_details: pointer to command details structure or NULL
4686  *
4687  * This associates a multicast E-tag to a port virtualizer.  It will return
4688  * the number of tags allocated by the PF, and the number of unallocated
4689  * tags available.
4690  *
4691  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4692  * num_tags_in_buf long.
4693  **/
4694 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4695                                 u16 etag, u8 num_tags_in_buf, void *buf,
4696                                 u16 *tags_used, u16 *tags_free,
4697                                 struct i40e_asq_cmd_details *cmd_details)
4698 {
4699         struct i40e_aq_desc desc;
4700         struct i40e_aqc_add_remove_mcast_etag *cmd =
4701                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4702         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4703            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4704         enum i40e_status_code status;
4705         u16 length = sizeof(u16) * num_tags_in_buf;
4706
4707         if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4708                 return I40E_ERR_PARAM;
4709
4710         i40e_fill_default_direct_cmd_desc(&desc,
4711                                           i40e_aqc_opc_add_multicast_etag);
4712
4713         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4714         cmd->etag = CPU_TO_LE16(etag);
4715         cmd->num_unicast_etags = num_tags_in_buf;
4716
4717         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4718         if (length > I40E_AQ_LARGE_BUF)
4719                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4720
4721         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4722
4723         if (!status) {
4724                 if (tags_used != NULL)
4725                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4726                 if (tags_free != NULL)
4727                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4728         }
4729
4730         return status;
4731 }
4732
4733 /**
4734  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4735  * @hw: pointer to the hw struct
4736  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4737  * @etag: value of the E-tag to remove
4738  * @tags_used: return value, number of tags in use by this port
4739  * @tags_free: return value, number of unallocated tags
4740  * @cmd_details: pointer to command details structure or NULL
4741  *
4742  * This deletes an E-tag from the port virtualizer.  It will return
4743  * the number of tags allocated by the port, and the number of unallocated
4744  * tags available.
4745  **/
4746 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4747                                 u16 etag, u16 *tags_used, u16 *tags_free,
4748                                 struct i40e_asq_cmd_details *cmd_details)
4749 {
4750         struct i40e_aq_desc desc;
4751         struct i40e_aqc_add_remove_mcast_etag *cmd =
4752                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4753         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4754            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4755         enum i40e_status_code status;
4756
4757
4758         if (pv_seid == 0)
4759                 return I40E_ERR_PARAM;
4760
4761         i40e_fill_default_direct_cmd_desc(&desc,
4762                                           i40e_aqc_opc_remove_multicast_etag);
4763
4764         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4765         cmd->etag = CPU_TO_LE16(etag);
4766
4767         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4768
4769         if (!status) {
4770                 if (tags_used != NULL)
4771                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4772                 if (tags_free != NULL)
4773                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4774         }
4775
4776         return status;
4777 }
4778
4779 /**
4780  * i40e_aq_update_tag - Update an S/E-tag
4781  * @hw: pointer to the hw struct
4782  * @vsi_seid: VSI SEID using this S-tag
4783  * @old_tag: old tag value
4784  * @new_tag: new tag value
4785  * @tags_used: return value, number of tags in use by this PF
4786  * @tags_free: return value, number of unallocated tags
4787  * @cmd_details: pointer to command details structure or NULL
4788  *
4789  * This updates the value of the tag currently attached to this VSI
4790  * in the switch complex.  It will return the number of tags allocated
4791  * by the PF, and the number of unallocated tags available.
4792  **/
4793 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4794                                 u16 old_tag, u16 new_tag, u16 *tags_used,
4795                                 u16 *tags_free,
4796                                 struct i40e_asq_cmd_details *cmd_details)
4797 {
4798         struct i40e_aq_desc desc;
4799         struct i40e_aqc_update_tag *cmd =
4800                 (struct i40e_aqc_update_tag *)&desc.params.raw;
4801         struct i40e_aqc_update_tag_completion *resp =
4802                 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4803         enum i40e_status_code status;
4804
4805         if (vsi_seid == 0)
4806                 return I40E_ERR_PARAM;
4807
4808         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4809
4810         cmd->seid = CPU_TO_LE16(vsi_seid);
4811         cmd->old_tag = CPU_TO_LE16(old_tag);
4812         cmd->new_tag = CPU_TO_LE16(new_tag);
4813
4814         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4815
4816         if (!status) {
4817                 if (tags_used != NULL)
4818                         *tags_used = LE16_TO_CPU(resp->tags_used);
4819                 if (tags_free != NULL)
4820                         *tags_free = LE16_TO_CPU(resp->tags_free);
4821         }
4822
4823         return status;
4824 }
4825
4826 /**
4827  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4828  * @hw: pointer to the hw struct
4829  * @tcmap: TC map for request/release any ignore PFC condition
4830  * @request: request or release ignore PFC condition
4831  * @tcmap_ret: return TCs for which PFC is currently ignored
4832  * @cmd_details: pointer to command details structure or NULL
4833  *
4834  * This sends out request/release to ignore PFC condition for a TC.
4835  * It will return the TCs for which PFC is currently ignored.
4836  **/
4837 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4838                                 bool request, u8 *tcmap_ret,
4839                                 struct i40e_asq_cmd_details *cmd_details)
4840 {
4841         struct i40e_aq_desc desc;
4842         struct i40e_aqc_pfc_ignore *cmd_resp =
4843                 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4844         enum i40e_status_code status;
4845
4846         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4847
4848         if (request)
4849                 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4850
4851         cmd_resp->tc_bitmap = tcmap;
4852
4853         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4854
4855         if (!status) {
4856                 if (tcmap_ret != NULL)
4857                         *tcmap_ret = cmd_resp->tc_bitmap;
4858         }
4859
4860         return status;
4861 }
4862
4863 /**
4864  * i40e_aq_dcb_updated - DCB Updated Command
4865  * @hw: pointer to the hw struct
4866  * @cmd_details: pointer to command details structure or NULL
4867  *
4868  * When LLDP is handled in PF this command is used by the PF
4869  * to notify EMP that a DCB setting is modified.
4870  * When LLDP is handled in EMP this command is used by the PF
4871  * to notify EMP whenever one of the following parameters get
4872  * modified:
4873  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4874  *   - PCIRTT in PRTDCB_GENC.PCIRTT
4875  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4876  * EMP will return when the shared RPB settings have been
4877  * recomputed and modified. The retval field in the descriptor
4878  * will be set to 0 when RPB is modified.
4879  **/
4880 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4881                                 struct i40e_asq_cmd_details *cmd_details)
4882 {
4883         struct i40e_aq_desc desc;
4884         enum i40e_status_code status;
4885
4886         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4887
4888         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4889
4890         return status;
4891 }
4892
4893 /**
4894  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4895  * @hw: pointer to the hw struct
4896  * @seid: defines the SEID of the switch for which the stats are requested
4897  * @vlan_id: the VLAN ID for which the statistics are requested
4898  * @stat_index: index of the statistics counters block assigned to this VLAN
4899  * @cmd_details: pointer to command details structure or NULL
4900  *
4901  * XL710 supports 128 smonVlanStats counters.This command is used to
4902  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4903  * switch.
4904  **/
4905 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4906                                 u16 vlan_id, u16 *stat_index,
4907                                 struct i40e_asq_cmd_details *cmd_details)
4908 {
4909         struct i40e_aq_desc desc;
4910         struct i40e_aqc_add_remove_statistics *cmd_resp =
4911                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4912         enum i40e_status_code status;
4913
4914         if ((seid == 0) || (stat_index == NULL))
4915                 return I40E_ERR_PARAM;
4916
4917         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4918
4919         cmd_resp->seid = CPU_TO_LE16(seid);
4920         cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4921
4922         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4923
4924         if (!status && stat_index)
4925                 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4926
4927         return status;
4928 }
4929
4930 /**
4931  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4932  * @hw: pointer to the hw struct
4933  * @seid: defines the SEID of the switch for which the stats are requested
4934  * @vlan_id: the VLAN ID for which the statistics are requested
4935  * @stat_index: index of the statistics counters block assigned to this VLAN
4936  * @cmd_details: pointer to command details structure or NULL
4937  *
4938  * XL710 supports 128 smonVlanStats counters.This command is used to
4939  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4940  * switch.
4941  **/
4942 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4943                                 u16 vlan_id, u16 stat_index,
4944                                 struct i40e_asq_cmd_details *cmd_details)
4945 {
4946         struct i40e_aq_desc desc;
4947         struct i40e_aqc_add_remove_statistics *cmd =
4948                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4949         enum i40e_status_code status;
4950
4951         if (seid == 0)
4952                 return I40E_ERR_PARAM;
4953
4954         i40e_fill_default_direct_cmd_desc(&desc,
4955                                           i40e_aqc_opc_remove_statistics);
4956
4957         cmd->seid = CPU_TO_LE16(seid);
4958         cmd->vlan  = CPU_TO_LE16(vlan_id);
4959         cmd->stat_index = CPU_TO_LE16(stat_index);
4960
4961         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4962
4963         return status;
4964 }
4965
4966 /**
4967  * i40e_aq_set_port_parameters - set physical port parameters.
4968  * @hw: pointer to the hw struct
4969  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4970  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4971  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4972  * @double_vlan: if set double VLAN is enabled
4973  * @cmd_details: pointer to command details structure or NULL
4974  **/
4975 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4976                                 u16 bad_frame_vsi, bool save_bad_pac,
4977                                 bool pad_short_pac, bool double_vlan,
4978                                 struct i40e_asq_cmd_details *cmd_details)
4979 {
4980         struct i40e_aqc_set_port_parameters *cmd;
4981         enum i40e_status_code status;
4982         struct i40e_aq_desc desc;
4983         u16 command_flags = 0;
4984
4985         cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4986
4987         i40e_fill_default_direct_cmd_desc(&desc,
4988                                           i40e_aqc_opc_set_port_parameters);
4989
4990         cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4991         if (save_bad_pac)
4992                 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4993         if (pad_short_pac)
4994                 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4995         if (double_vlan)
4996                 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4997         cmd->command_flags = CPU_TO_LE16(command_flags);
4998
4999         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5000
5001         return status;
5002 }
5003
5004 /**
5005  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
5006  * @hw: pointer to the hw struct
5007  * @seid: seid for the physical port/switching component/vsi
5008  * @buff: Indirect buffer to hold data parameters and response
5009  * @buff_size: Indirect buffer size
5010  * @opcode: Tx scheduler AQ command opcode
5011  * @cmd_details: pointer to command details structure or NULL
5012  *
5013  * Generic command handler for Tx scheduler AQ commands
5014  **/
5015 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
5016                                 void *buff, u16 buff_size,
5017                                  enum i40e_admin_queue_opc opcode,
5018                                 struct i40e_asq_cmd_details *cmd_details)
5019 {
5020         struct i40e_aq_desc desc;
5021         struct i40e_aqc_tx_sched_ind *cmd =
5022                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
5023         enum i40e_status_code status;
5024         bool cmd_param_flag = false;
5025
5026         switch (opcode) {
5027         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
5028         case i40e_aqc_opc_configure_vsi_tc_bw:
5029         case i40e_aqc_opc_enable_switching_comp_ets:
5030         case i40e_aqc_opc_modify_switching_comp_ets:
5031         case i40e_aqc_opc_disable_switching_comp_ets:
5032         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
5033         case i40e_aqc_opc_configure_switching_comp_bw_config:
5034                 cmd_param_flag = true;
5035                 break;
5036         case i40e_aqc_opc_query_vsi_bw_config:
5037         case i40e_aqc_opc_query_vsi_ets_sla_config:
5038         case i40e_aqc_opc_query_switching_comp_ets_config:
5039         case i40e_aqc_opc_query_port_ets_config:
5040         case i40e_aqc_opc_query_switching_comp_bw_config:
5041                 cmd_param_flag = false;
5042                 break;
5043         default:
5044                 return I40E_ERR_PARAM;
5045         }
5046
5047         i40e_fill_default_direct_cmd_desc(&desc, opcode);
5048
5049         /* Indirect command */
5050         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5051         if (cmd_param_flag)
5052                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5053         if (buff_size > I40E_AQ_LARGE_BUF)
5054                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5055
5056         desc.datalen = CPU_TO_LE16(buff_size);
5057
5058         cmd->vsi_seid = CPU_TO_LE16(seid);
5059
5060         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5061
5062         return status;
5063 }
5064
5065 /**
5066  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5067  * @hw: pointer to the hw struct
5068  * @seid: VSI seid
5069  * @credit: BW limit credits (0 = disabled)
5070  * @max_credit: Max BW limit credits
5071  * @cmd_details: pointer to command details structure or NULL
5072  **/
5073 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5074                                 u16 seid, u16 credit, u8 max_credit,
5075                                 struct i40e_asq_cmd_details *cmd_details)
5076 {
5077         struct i40e_aq_desc desc;
5078         struct i40e_aqc_configure_vsi_bw_limit *cmd =
5079                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5080         enum i40e_status_code status;
5081
5082         i40e_fill_default_direct_cmd_desc(&desc,
5083                                           i40e_aqc_opc_configure_vsi_bw_limit);
5084
5085         cmd->vsi_seid = CPU_TO_LE16(seid);
5086         cmd->credit = CPU_TO_LE16(credit);
5087         cmd->max_credit = max_credit;
5088
5089         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5090
5091         return status;
5092 }
5093
5094 /**
5095  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5096  * @hw: pointer to the hw struct
5097  * @seid: switching component seid
5098  * @credit: BW limit credits (0 = disabled)
5099  * @max_bw: Max BW limit credits
5100  * @cmd_details: pointer to command details structure or NULL
5101  **/
5102 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5103                                 u16 seid, u16 credit, u8 max_bw,
5104                                 struct i40e_asq_cmd_details *cmd_details)
5105 {
5106         struct i40e_aq_desc desc;
5107         struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5108           (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5109         enum i40e_status_code status;
5110
5111         i40e_fill_default_direct_cmd_desc(&desc,
5112                                 i40e_aqc_opc_configure_switching_comp_bw_limit);
5113
5114         cmd->seid = CPU_TO_LE16(seid);
5115         cmd->credit = CPU_TO_LE16(credit);
5116         cmd->max_bw = max_bw;
5117
5118         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5119
5120         return status;
5121 }
5122
5123 /**
5124  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5125  * @hw: pointer to the hw struct
5126  * @seid: VSI seid
5127  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5128  * @cmd_details: pointer to command details structure or NULL
5129  **/
5130 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5131                         u16 seid,
5132                         struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5133                         struct i40e_asq_cmd_details *cmd_details)
5134 {
5135         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5136                                     i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5137                                     cmd_details);
5138 }
5139
5140 /**
5141  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5142  * @hw: pointer to the hw struct
5143  * @seid: VSI seid
5144  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5145  * @cmd_details: pointer to command details structure or NULL
5146  **/
5147 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5148                         u16 seid,
5149                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5150                         struct i40e_asq_cmd_details *cmd_details)
5151 {
5152         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5153                                     i40e_aqc_opc_configure_vsi_tc_bw,
5154                                     cmd_details);
5155 }
5156
5157 /**
5158  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5159  * @hw: pointer to the hw struct
5160  * @seid: seid of the switching component connected to Physical Port
5161  * @ets_data: Buffer holding ETS parameters
5162  * @cmd_details: pointer to command details structure or NULL
5163  **/
5164 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5165                 u16 seid,
5166                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5167                 enum i40e_admin_queue_opc opcode,
5168                 struct i40e_asq_cmd_details *cmd_details)
5169 {
5170         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5171                                     sizeof(*ets_data), opcode, cmd_details);
5172 }
5173
5174 /**
5175  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5176  * @hw: pointer to the hw struct
5177  * @seid: seid of the switching component
5178  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5179  * @cmd_details: pointer to command details structure or NULL
5180  **/
5181 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5182         u16 seid,
5183         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5184         struct i40e_asq_cmd_details *cmd_details)
5185 {
5186         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5187                             i40e_aqc_opc_configure_switching_comp_bw_config,
5188                             cmd_details);
5189 }
5190
5191 /**
5192  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5193  * @hw: pointer to the hw struct
5194  * @seid: seid of the switching component
5195  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5196  * @cmd_details: pointer to command details structure or NULL
5197  **/
5198 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5199         struct i40e_hw *hw, u16 seid,
5200         struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5201         struct i40e_asq_cmd_details *cmd_details)
5202 {
5203         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5204                             i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5205                             cmd_details);
5206 }
5207
5208 /**
5209  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5210  * @hw: pointer to the hw struct
5211  * @seid: seid of the VSI
5212  * @bw_data: Buffer to hold VSI BW configuration
5213  * @cmd_details: pointer to command details structure or NULL
5214  **/
5215 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5216                         u16 seid,
5217                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5218                         struct i40e_asq_cmd_details *cmd_details)
5219 {
5220         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5221                                     i40e_aqc_opc_query_vsi_bw_config,
5222                                     cmd_details);
5223 }
5224
5225 /**
5226  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5227  * @hw: pointer to the hw struct
5228  * @seid: seid of the VSI
5229  * @bw_data: Buffer to hold VSI BW configuration per TC
5230  * @cmd_details: pointer to command details structure or NULL
5231  **/
5232 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5233                         u16 seid,
5234                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5235                         struct i40e_asq_cmd_details *cmd_details)
5236 {
5237         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5238                                     i40e_aqc_opc_query_vsi_ets_sla_config,
5239                                     cmd_details);
5240 }
5241
5242 /**
5243  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5244  * @hw: pointer to the hw struct
5245  * @seid: seid of the switching component
5246  * @bw_data: Buffer to hold switching component's per TC BW config
5247  * @cmd_details: pointer to command details structure or NULL
5248  **/
5249 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5250                 u16 seid,
5251                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5252                 struct i40e_asq_cmd_details *cmd_details)
5253 {
5254         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5255                                    i40e_aqc_opc_query_switching_comp_ets_config,
5256                                    cmd_details);
5257 }
5258
5259 /**
5260  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5261  * @hw: pointer to the hw struct
5262  * @seid: seid of the VSI or switching component connected to Physical Port
5263  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5264  * @cmd_details: pointer to command details structure or NULL
5265  **/
5266 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5267                         u16 seid,
5268                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
5269                         struct i40e_asq_cmd_details *cmd_details)
5270 {
5271         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5272                                     i40e_aqc_opc_query_port_ets_config,
5273                                     cmd_details);
5274 }
5275
5276 /**
5277  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5278  * @hw: pointer to the hw struct
5279  * @seid: seid of the switching component
5280  * @bw_data: Buffer to hold switching component's BW configuration
5281  * @cmd_details: pointer to command details structure or NULL
5282  **/
5283 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5284                 u16 seid,
5285                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5286                 struct i40e_asq_cmd_details *cmd_details)
5287 {
5288         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5289                                     i40e_aqc_opc_query_switching_comp_bw_config,
5290                                     cmd_details);
5291 }
5292
5293 /**
5294  * i40e_validate_filter_settings
5295  * @hw: pointer to the hardware structure
5296  * @settings: Filter control settings
5297  *
5298  * Check and validate the filter control settings passed.
5299  * The function checks for the valid filter/context sizes being
5300  * passed for FCoE and PE.
5301  *
5302  * Returns I40E_SUCCESS if the values passed are valid and within
5303  * range else returns an error.
5304  **/
5305 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5306                                 struct i40e_filter_control_settings *settings)
5307 {
5308         u32 fcoe_cntx_size, fcoe_filt_size;
5309         u32 pe_cntx_size, pe_filt_size;
5310         u32 fcoe_fmax;
5311
5312         u32 val;
5313
5314         /* Validate FCoE settings passed */
5315         switch (settings->fcoe_filt_num) {
5316         case I40E_HASH_FILTER_SIZE_1K:
5317         case I40E_HASH_FILTER_SIZE_2K:
5318         case I40E_HASH_FILTER_SIZE_4K:
5319         case I40E_HASH_FILTER_SIZE_8K:
5320         case I40E_HASH_FILTER_SIZE_16K:
5321         case I40E_HASH_FILTER_SIZE_32K:
5322                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5323                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5324                 break;
5325         default:
5326                 return I40E_ERR_PARAM;
5327         }
5328
5329         switch (settings->fcoe_cntx_num) {
5330         case I40E_DMA_CNTX_SIZE_512:
5331         case I40E_DMA_CNTX_SIZE_1K:
5332         case I40E_DMA_CNTX_SIZE_2K:
5333         case I40E_DMA_CNTX_SIZE_4K:
5334                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5335                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5336                 break;
5337         default:
5338                 return I40E_ERR_PARAM;
5339         }
5340
5341         /* Validate PE settings passed */
5342         switch (settings->pe_filt_num) {
5343         case I40E_HASH_FILTER_SIZE_1K:
5344         case I40E_HASH_FILTER_SIZE_2K:
5345         case I40E_HASH_FILTER_SIZE_4K:
5346         case I40E_HASH_FILTER_SIZE_8K:
5347         case I40E_HASH_FILTER_SIZE_16K:
5348         case I40E_HASH_FILTER_SIZE_32K:
5349         case I40E_HASH_FILTER_SIZE_64K:
5350         case I40E_HASH_FILTER_SIZE_128K:
5351         case I40E_HASH_FILTER_SIZE_256K:
5352         case I40E_HASH_FILTER_SIZE_512K:
5353         case I40E_HASH_FILTER_SIZE_1M:
5354                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5355                 pe_filt_size <<= (u32)settings->pe_filt_num;
5356                 break;
5357         default:
5358                 return I40E_ERR_PARAM;
5359         }
5360
5361         switch (settings->pe_cntx_num) {
5362         case I40E_DMA_CNTX_SIZE_512:
5363         case I40E_DMA_CNTX_SIZE_1K:
5364         case I40E_DMA_CNTX_SIZE_2K:
5365         case I40E_DMA_CNTX_SIZE_4K:
5366         case I40E_DMA_CNTX_SIZE_8K:
5367         case I40E_DMA_CNTX_SIZE_16K:
5368         case I40E_DMA_CNTX_SIZE_32K:
5369         case I40E_DMA_CNTX_SIZE_64K:
5370         case I40E_DMA_CNTX_SIZE_128K:
5371         case I40E_DMA_CNTX_SIZE_256K:
5372                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5373                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5374                 break;
5375         default:
5376                 return I40E_ERR_PARAM;
5377         }
5378
5379         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5380         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5381         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5382                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5383         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
5384                 return I40E_ERR_INVALID_SIZE;
5385
5386         return I40E_SUCCESS;
5387 }
5388
5389 /**
5390  * i40e_set_filter_control
5391  * @hw: pointer to the hardware structure
5392  * @settings: Filter control settings
5393  *
5394  * Set the Queue Filters for PE/FCoE and enable filters required
5395  * for a single PF. It is expected that these settings are programmed
5396  * at the driver initialization time.
5397  **/
5398 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5399                                 struct i40e_filter_control_settings *settings)
5400 {
5401         enum i40e_status_code ret = I40E_SUCCESS;
5402         u32 hash_lut_size = 0;
5403         u32 val;
5404
5405         if (!settings)
5406                 return I40E_ERR_PARAM;
5407
5408         /* Validate the input settings */
5409         ret = i40e_validate_filter_settings(hw, settings);
5410         if (ret)
5411                 return ret;
5412
5413         /* Read the PF Queue Filter control register */
5414         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5415
5416         /* Program required PE hash buckets for the PF */
5417         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5418         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5419                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5420         /* Program required PE contexts for the PF */
5421         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5422         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5423                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5424
5425         /* Program required FCoE hash buckets for the PF */
5426         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5427         val |= ((u32)settings->fcoe_filt_num <<
5428                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5429                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5430         /* Program required FCoE DDP contexts for the PF */
5431         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5432         val |= ((u32)settings->fcoe_cntx_num <<
5433                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5434                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5435
5436         /* Program Hash LUT size for the PF */
5437         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5438         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5439                 hash_lut_size = 1;
5440         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5441                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5442
5443         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5444         if (settings->enable_fdir)
5445                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5446         if (settings->enable_ethtype)
5447                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5448         if (settings->enable_macvlan)
5449                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5450
5451         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5452
5453         return I40E_SUCCESS;
5454 }
5455
5456 /**
5457  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5458  * @hw: pointer to the hw struct
5459  * @mac_addr: MAC address to use in the filter
5460  * @ethtype: Ethertype to use in the filter
5461  * @flags: Flags that needs to be applied to the filter
5462  * @vsi_seid: seid of the control VSI
5463  * @queue: VSI queue number to send the packet to
5464  * @is_add: Add control packet filter if True else remove
5465  * @stats: Structure to hold information on control filter counts
5466  * @cmd_details: pointer to command details structure or NULL
5467  *
5468  * This command will Add or Remove control packet filter for a control VSI.
5469  * In return it will update the total number of perfect filter count in
5470  * the stats member.
5471  **/
5472 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5473                                 u8 *mac_addr, u16 ethtype, u16 flags,
5474                                 u16 vsi_seid, u16 queue, bool is_add,
5475                                 struct i40e_control_filter_stats *stats,
5476                                 struct i40e_asq_cmd_details *cmd_details)
5477 {
5478         struct i40e_aq_desc desc;
5479         struct i40e_aqc_add_remove_control_packet_filter *cmd =
5480                 (struct i40e_aqc_add_remove_control_packet_filter *)
5481                 &desc.params.raw;
5482         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5483                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5484                 &desc.params.raw;
5485         enum i40e_status_code status;
5486
5487         if (vsi_seid == 0)
5488                 return I40E_ERR_PARAM;
5489
5490         if (is_add) {
5491                 i40e_fill_default_direct_cmd_desc(&desc,
5492                                 i40e_aqc_opc_add_control_packet_filter);
5493                 cmd->queue = CPU_TO_LE16(queue);
5494         } else {
5495                 i40e_fill_default_direct_cmd_desc(&desc,
5496                                 i40e_aqc_opc_remove_control_packet_filter);
5497         }
5498
5499         if (mac_addr)
5500                 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
5501                             I40E_NONDMA_TO_NONDMA);
5502
5503         cmd->etype = CPU_TO_LE16(ethtype);
5504         cmd->flags = CPU_TO_LE16(flags);
5505         cmd->seid = CPU_TO_LE16(vsi_seid);
5506
5507         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5508
5509         if (!status && stats) {
5510                 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5511                 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5512                 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5513                 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5514         }
5515
5516         return status;
5517 }
5518
5519 /**
5520  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5521  * @hw: pointer to the hw struct
5522  * @seid: VSI seid to add ethertype filter from
5523  **/
5524 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5525 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5526                                                     u16 seid)
5527 {
5528         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5529                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5530                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5531         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5532         enum i40e_status_code status;
5533
5534         status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5535                                                        seid, 0, true, NULL,
5536                                                        NULL);
5537         if (status)
5538                 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5539 }
5540
5541 /**
5542  * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5543  * @filters: list of cloud filters
5544  * @filter_count: length of list
5545  *
5546  * There's an issue in the device where the Geneve VNI layout needs
5547  * to be shifted 1 byte over from the VxLAN VNI
5548  **/
5549 STATIC void i40e_fix_up_geneve_vni(
5550         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5551         u8 filter_count)
5552 {
5553         struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters;
5554         int i;
5555
5556         for (i = 0; i < filter_count; i++) {
5557                 u16 tnl_type;
5558                 u32 ti;
5559
5560                 tnl_type = (LE16_TO_CPU(f[i].flags) &
5561                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5562                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5563                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5564                         ti = LE32_TO_CPU(f[i].tenant_id);
5565                         f[i].tenant_id = CPU_TO_LE32(ti << 8);
5566                 }
5567         }
5568 }
5569
5570 /**
5571  * i40e_aq_add_cloud_filters
5572  * @hw: pointer to the hardware structure
5573  * @seid: VSI seid to add cloud filters from
5574  * @filters: Buffer which contains the filters to be added
5575  * @filter_count: number of filters contained in the buffer
5576  *
5577  * Set the cloud filters for a given VSI.  The contents of the
5578  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5579  * in by the caller of the function.
5580  *
5581  **/
5582 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5583         u16 seid,
5584         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5585         u8 filter_count)
5586 {
5587         struct i40e_aq_desc desc;
5588         struct i40e_aqc_add_remove_cloud_filters *cmd =
5589         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5590         enum i40e_status_code status;
5591         u16 buff_len;
5592
5593         i40e_fill_default_direct_cmd_desc(&desc,
5594                                           i40e_aqc_opc_add_cloud_filters);
5595
5596         buff_len = filter_count * sizeof(*filters);
5597         desc.datalen = CPU_TO_LE16(buff_len);
5598         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5599         cmd->num_filters = filter_count;
5600         cmd->seid = CPU_TO_LE16(seid);
5601
5602         i40e_fix_up_geneve_vni(filters, filter_count);
5603
5604         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5605
5606         return status;
5607 }
5608
5609 /**
5610  * i40e_aq_remove_cloud_filters
5611  * @hw: pointer to the hardware structure
5612  * @seid: VSI seid to remove cloud filters from
5613  * @filters: Buffer which contains the filters to be removed
5614  * @filter_count: number of filters contained in the buffer
5615  *
5616  * Remove the cloud filters for a given VSI.  The contents of the
5617  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5618  * in by the caller of the function.
5619  *
5620  **/
5621 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5622                 u16 seid,
5623                 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5624                 u8 filter_count)
5625 {
5626         struct i40e_aq_desc desc;
5627         struct i40e_aqc_add_remove_cloud_filters *cmd =
5628         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5629         enum i40e_status_code status;
5630         u16 buff_len;
5631
5632         i40e_fill_default_direct_cmd_desc(&desc,
5633                                           i40e_aqc_opc_remove_cloud_filters);
5634
5635         buff_len = filter_count * sizeof(*filters);
5636         desc.datalen = CPU_TO_LE16(buff_len);
5637         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5638         cmd->num_filters = filter_count;
5639         cmd->seid = CPU_TO_LE16(seid);
5640
5641         i40e_fix_up_geneve_vni(filters, filter_count);
5642
5643         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5644
5645         return status;
5646 }
5647
5648 /**
5649  * i40e_aq_alternate_write
5650  * @hw: pointer to the hardware structure
5651  * @reg_addr0: address of first dword to be read
5652  * @reg_val0: value to be written under 'reg_addr0'
5653  * @reg_addr1: address of second dword to be read
5654  * @reg_val1: value to be written under 'reg_addr1'
5655  *
5656  * Write one or two dwords to alternate structure. Fields are indicated
5657  * by 'reg_addr0' and 'reg_addr1' register numbers.
5658  *
5659  **/
5660 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5661                                 u32 reg_addr0, u32 reg_val0,
5662                                 u32 reg_addr1, u32 reg_val1)
5663 {
5664         struct i40e_aq_desc desc;
5665         struct i40e_aqc_alternate_write *cmd_resp =
5666                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5667         enum i40e_status_code status;
5668
5669         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5670         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5671         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5672         cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5673         cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5674
5675         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5676
5677         return status;
5678 }
5679
5680 /**
5681  * i40e_aq_alternate_write_indirect
5682  * @hw: pointer to the hardware structure
5683  * @addr: address of a first register to be modified
5684  * @dw_count: number of alternate structure fields to write
5685  * @buffer: pointer to the command buffer
5686  *
5687  * Write 'dw_count' dwords from 'buffer' to alternate structure
5688  * starting at 'addr'.
5689  *
5690  **/
5691 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5692                                 u32 addr, u32 dw_count, void *buffer)
5693 {
5694         struct i40e_aq_desc desc;
5695         struct i40e_aqc_alternate_ind_write *cmd_resp =
5696                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5697         enum i40e_status_code status;
5698
5699         if (buffer == NULL)
5700                 return I40E_ERR_PARAM;
5701
5702         /* Indirect command */
5703         i40e_fill_default_direct_cmd_desc(&desc,
5704                                          i40e_aqc_opc_alternate_write_indirect);
5705
5706         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5707         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5708         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5709                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5710
5711         cmd_resp->address = CPU_TO_LE32(addr);
5712         cmd_resp->length = CPU_TO_LE32(dw_count);
5713
5714         status = i40e_asq_send_command(hw, &desc, buffer,
5715                                        I40E_LO_DWORD(4*dw_count), NULL);
5716
5717         return status;
5718 }
5719
5720 /**
5721  * i40e_aq_alternate_read
5722  * @hw: pointer to the hardware structure
5723  * @reg_addr0: address of first dword to be read
5724  * @reg_val0: pointer for data read from 'reg_addr0'
5725  * @reg_addr1: address of second dword to be read
5726  * @reg_val1: pointer for data read from 'reg_addr1'
5727  *
5728  * Read one or two dwords from alternate structure. Fields are indicated
5729  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5730  * is not passed then only register at 'reg_addr0' is read.
5731  *
5732  **/
5733 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5734                                 u32 reg_addr0, u32 *reg_val0,
5735                                 u32 reg_addr1, u32 *reg_val1)
5736 {
5737         struct i40e_aq_desc desc;
5738         struct i40e_aqc_alternate_write *cmd_resp =
5739                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5740         enum i40e_status_code status;
5741
5742         if (reg_val0 == NULL)
5743                 return I40E_ERR_PARAM;
5744
5745         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5746         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5747         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5748
5749         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5750
5751         if (status == I40E_SUCCESS) {
5752                 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5753
5754                 if (reg_val1 != NULL)
5755                         *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5756         }
5757
5758         return status;
5759 }
5760
5761 /**
5762  * i40e_aq_alternate_read_indirect
5763  * @hw: pointer to the hardware structure
5764  * @addr: address of the alternate structure field
5765  * @dw_count: number of alternate structure fields to read
5766  * @buffer: pointer to the command buffer
5767  *
5768  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5769  * place them in 'buffer'. The buffer should be allocated by caller.
5770  *
5771  **/
5772 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5773                                 u32 addr, u32 dw_count, void *buffer)
5774 {
5775         struct i40e_aq_desc desc;
5776         struct i40e_aqc_alternate_ind_write *cmd_resp =
5777                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5778         enum i40e_status_code status;
5779
5780         if (buffer == NULL)
5781                 return I40E_ERR_PARAM;
5782
5783         /* Indirect command */
5784         i40e_fill_default_direct_cmd_desc(&desc,
5785                 i40e_aqc_opc_alternate_read_indirect);
5786
5787         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5788         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5789         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5790                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5791
5792         cmd_resp->address = CPU_TO_LE32(addr);
5793         cmd_resp->length = CPU_TO_LE32(dw_count);
5794
5795         status = i40e_asq_send_command(hw, &desc, buffer,
5796                                        I40E_LO_DWORD(4*dw_count), NULL);
5797
5798         return status;
5799 }
5800
5801 /**
5802  *  i40e_aq_alternate_clear
5803  *  @hw: pointer to the HW structure.
5804  *
5805  *  Clear the alternate structures of the port from which the function
5806  *  is called.
5807  *
5808  **/
5809 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5810 {
5811         struct i40e_aq_desc desc;
5812         enum i40e_status_code status;
5813
5814         i40e_fill_default_direct_cmd_desc(&desc,
5815                                           i40e_aqc_opc_alternate_clear_port);
5816
5817         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5818
5819         return status;
5820 }
5821
5822 /**
5823  *  i40e_aq_alternate_write_done
5824  *  @hw: pointer to the HW structure.
5825  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
5826  *  @reset_needed: indicates the SW should trigger GLOBAL reset
5827  *
5828  *  Indicates to the FW that alternate structures have been changed.
5829  *
5830  **/
5831 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
5832                 u8 bios_mode, bool *reset_needed)
5833 {
5834         struct i40e_aq_desc desc;
5835         struct i40e_aqc_alternate_write_done *cmd =
5836                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5837         enum i40e_status_code status;
5838
5839         if (reset_needed == NULL)
5840                 return I40E_ERR_PARAM;
5841
5842         i40e_fill_default_direct_cmd_desc(&desc,
5843                                           i40e_aqc_opc_alternate_write_done);
5844
5845         cmd->cmd_flags = CPU_TO_LE16(bios_mode);
5846
5847         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5848         if (!status && reset_needed)
5849                 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
5850                                  I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
5851
5852         return status;
5853 }
5854
5855 /**
5856  *  i40e_aq_set_oem_mode
5857  *  @hw: pointer to the HW structure.
5858  *  @oem_mode: the OEM mode to be used
5859  *
5860  *  Sets the device to a specific operating mode. Currently the only supported
5861  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
5862  *
5863  **/
5864 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
5865                 u8 oem_mode)
5866 {
5867         struct i40e_aq_desc desc;
5868         struct i40e_aqc_alternate_write_done *cmd =
5869                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5870         enum i40e_status_code status;
5871
5872         i40e_fill_default_direct_cmd_desc(&desc,
5873                                           i40e_aqc_opc_alternate_set_mode);
5874
5875         cmd->cmd_flags = CPU_TO_LE16(oem_mode);
5876
5877         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5878
5879         return status;
5880 }
5881
5882 /**
5883  * i40e_aq_resume_port_tx
5884  * @hw: pointer to the hardware structure
5885  * @cmd_details: pointer to command details structure or NULL
5886  *
5887  * Resume port's Tx traffic
5888  **/
5889 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
5890                                 struct i40e_asq_cmd_details *cmd_details)
5891 {
5892         struct i40e_aq_desc desc;
5893         enum i40e_status_code status;
5894
5895         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
5896
5897         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5898
5899         return status;
5900 }
5901
5902 /**
5903  * i40e_set_pci_config_data - store PCI bus info
5904  * @hw: pointer to hardware structure
5905  * @link_status: the link status word from PCI config space
5906  *
5907  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
5908  **/
5909 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
5910 {
5911         hw->bus.type = i40e_bus_type_pci_express;
5912
5913         switch (link_status & I40E_PCI_LINK_WIDTH) {
5914         case I40E_PCI_LINK_WIDTH_1:
5915                 hw->bus.width = i40e_bus_width_pcie_x1;
5916                 break;
5917         case I40E_PCI_LINK_WIDTH_2:
5918                 hw->bus.width = i40e_bus_width_pcie_x2;
5919                 break;
5920         case I40E_PCI_LINK_WIDTH_4:
5921                 hw->bus.width = i40e_bus_width_pcie_x4;
5922                 break;
5923         case I40E_PCI_LINK_WIDTH_8:
5924                 hw->bus.width = i40e_bus_width_pcie_x8;
5925                 break;
5926         default:
5927                 hw->bus.width = i40e_bus_width_unknown;
5928                 break;
5929         }
5930
5931         switch (link_status & I40E_PCI_LINK_SPEED) {
5932         case I40E_PCI_LINK_SPEED_2500:
5933                 hw->bus.speed = i40e_bus_speed_2500;
5934                 break;
5935         case I40E_PCI_LINK_SPEED_5000:
5936                 hw->bus.speed = i40e_bus_speed_5000;
5937                 break;
5938         case I40E_PCI_LINK_SPEED_8000:
5939                 hw->bus.speed = i40e_bus_speed_8000;
5940                 break;
5941         default:
5942                 hw->bus.speed = i40e_bus_speed_unknown;
5943                 break;
5944         }
5945 }
5946
5947 /**
5948  * i40e_aq_debug_dump
5949  * @hw: pointer to the hardware structure
5950  * @cluster_id: specific cluster to dump
5951  * @table_id: table id within cluster
5952  * @start_index: index of line in the block to read
5953  * @buff_size: dump buffer size
5954  * @buff: dump buffer
5955  * @ret_buff_size: actual buffer size returned
5956  * @ret_next_table: next block to read
5957  * @ret_next_index: next index to read
5958  *
5959  * Dump internal FW/HW data for debug purposes.
5960  *
5961  **/
5962 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
5963                                 u8 table_id, u32 start_index, u16 buff_size,
5964                                 void *buff, u16 *ret_buff_size,
5965                                 u8 *ret_next_table, u32 *ret_next_index,
5966                                 struct i40e_asq_cmd_details *cmd_details)
5967 {
5968         struct i40e_aq_desc desc;
5969         struct i40e_aqc_debug_dump_internals *cmd =
5970                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5971         struct i40e_aqc_debug_dump_internals *resp =
5972                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5973         enum i40e_status_code status;
5974
5975         if (buff_size == 0 || !buff)
5976                 return I40E_ERR_PARAM;
5977
5978         i40e_fill_default_direct_cmd_desc(&desc,
5979                                           i40e_aqc_opc_debug_dump_internals);
5980         /* Indirect Command */
5981         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5982         if (buff_size > I40E_AQ_LARGE_BUF)
5983                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5984
5985         cmd->cluster_id = cluster_id;
5986         cmd->table_id = table_id;
5987         cmd->idx = CPU_TO_LE32(start_index);
5988
5989         desc.datalen = CPU_TO_LE16(buff_size);
5990
5991         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5992         if (!status) {
5993                 if (ret_buff_size != NULL)
5994                         *ret_buff_size = LE16_TO_CPU(desc.datalen);
5995                 if (ret_next_table != NULL)
5996                         *ret_next_table = resp->table_id;
5997                 if (ret_next_index != NULL)
5998                         *ret_next_index = LE32_TO_CPU(resp->idx);
5999         }
6000
6001         return status;
6002 }
6003
6004 /**
6005  * i40e_read_bw_from_alt_ram
6006  * @hw: pointer to the hardware structure
6007  * @max_bw: pointer for max_bw read
6008  * @min_bw: pointer for min_bw read
6009  * @min_valid: pointer for bool that is true if min_bw is a valid value
6010  * @max_valid: pointer for bool that is true if max_bw is a valid value
6011  *
6012  * Read bw from the alternate ram for the given pf
6013  **/
6014 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
6015                                         u32 *max_bw, u32 *min_bw,
6016                                         bool *min_valid, bool *max_valid)
6017 {
6018         enum i40e_status_code status;
6019         u32 max_bw_addr, min_bw_addr;
6020
6021         /* Calculate the address of the min/max bw registers */
6022         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6023                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
6024                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6025         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6026                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
6027                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6028
6029         /* Read the bandwidths from alt ram */
6030         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
6031                                         min_bw_addr, min_bw);
6032
6033         if (*min_bw & I40E_ALT_BW_VALID_MASK)
6034                 *min_valid = true;
6035         else
6036                 *min_valid = false;
6037
6038         if (*max_bw & I40E_ALT_BW_VALID_MASK)
6039                 *max_valid = true;
6040         else
6041                 *max_valid = false;
6042
6043         return status;
6044 }
6045
6046 /**
6047  * i40e_aq_configure_partition_bw
6048  * @hw: pointer to the hardware structure
6049  * @bw_data: Buffer holding valid pfs and bw limits
6050  * @cmd_details: pointer to command details
6051  *
6052  * Configure partitions guaranteed/max bw
6053  **/
6054 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6055                         struct i40e_aqc_configure_partition_bw_data *bw_data,
6056                         struct i40e_asq_cmd_details *cmd_details)
6057 {
6058         enum i40e_status_code status;
6059         struct i40e_aq_desc desc;
6060         u16 bwd_size = sizeof(*bw_data);
6061
6062         i40e_fill_default_direct_cmd_desc(&desc,
6063                                 i40e_aqc_opc_configure_partition_bw);
6064
6065         /* Indirect command */
6066         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6067         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6068
6069         desc.datalen = CPU_TO_LE16(bwd_size);
6070
6071         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6072
6073         return status;
6074 }
6075
6076 /**
6077  * i40e_read_phy_register_clause22
6078  * @hw: pointer to the HW structure
6079  * @reg: register address in the page
6080  * @phy_adr: PHY address on MDIO interface
6081  * @value: PHY register value
6082  *
6083  * Reads specified PHY register value
6084  **/
6085 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
6086                                         u16 reg, u8 phy_addr, u16 *value)
6087 {
6088         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6089         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6090         u32 command = 0;
6091         u16 retry = 1000;
6092
6093         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6094                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6095                   (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
6096                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6097                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6098         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6099         do {
6100                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6101                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6102                         status = I40E_SUCCESS;
6103                         break;
6104                 }
6105                 i40e_usec_delay(10);
6106                 retry--;
6107         } while (retry);
6108
6109         if (status) {
6110                 i40e_debug(hw, I40E_DEBUG_PHY,
6111                            "PHY: Can't write command to external PHY.\n");
6112         } else {
6113                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6114                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6115                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6116         }
6117
6118         return status;
6119 }
6120
6121 /**
6122  * i40e_write_phy_register_clause22
6123  * @hw: pointer to the HW structure
6124  * @reg: register address in the page
6125  * @phy_adr: PHY address on MDIO interface
6126  * @value: PHY register value
6127  *
6128  * Writes specified PHY register value
6129  **/
6130 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6131                                         u16 reg, u8 phy_addr, u16 value)
6132 {
6133         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6134         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6135         u32 command  = 0;
6136         u16 retry = 1000;
6137
6138         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6139         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6140
6141         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6142                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6143                   (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6144                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6145                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6146
6147         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6148         do {
6149                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6150                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6151                         status = I40E_SUCCESS;
6152                         break;
6153                 }
6154                 i40e_usec_delay(10);
6155                 retry--;
6156         } while (retry);
6157
6158         return status;
6159 }
6160
6161 /**
6162  * i40e_read_phy_register_clause45
6163  * @hw: pointer to the HW structure
6164  * @page: registers page number
6165  * @reg: register address in the page
6166  * @phy_adr: PHY address on MDIO interface
6167  * @value: PHY register value
6168  *
6169  * Reads specified PHY register value
6170  **/
6171 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6172                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6173 {
6174         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6175         u32 command  = 0;
6176         u16 retry = 1000;
6177         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6178
6179         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6180                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6181                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6182                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6183                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6184                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6185                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6186         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6187         do {
6188                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6189                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6190                         status = I40E_SUCCESS;
6191                         break;
6192                 }
6193                 i40e_usec_delay(10);
6194                 retry--;
6195         } while (retry);
6196
6197         if (status) {
6198                 i40e_debug(hw, I40E_DEBUG_PHY,
6199                            "PHY: Can't write command to external PHY.\n");
6200                 goto phy_read_end;
6201         }
6202
6203         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6204                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6205                   (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6206                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6207                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6208                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6209         status = I40E_ERR_TIMEOUT;
6210         retry = 1000;
6211         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6212         do {
6213                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6214                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6215                         status = I40E_SUCCESS;
6216                         break;
6217                 }
6218                 i40e_usec_delay(10);
6219                 retry--;
6220         } while (retry);
6221
6222         if (!status) {
6223                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6224                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6225                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6226         } else {
6227                 i40e_debug(hw, I40E_DEBUG_PHY,
6228                            "PHY: Can't read register value from external PHY.\n");
6229         }
6230
6231 phy_read_end:
6232         return status;
6233 }
6234
6235 /**
6236  * i40e_write_phy_register_clause45
6237  * @hw: pointer to the HW structure
6238  * @page: registers page number
6239  * @reg: register address in the page
6240  * @phy_adr: PHY address on MDIO interface
6241  * @value: PHY register value
6242  *
6243  * Writes value to specified PHY register
6244  **/
6245 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6246                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6247 {
6248         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6249         u32 command  = 0;
6250         u16 retry = 1000;
6251         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6252
6253         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6254                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6255                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6256                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6257                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6258                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6259                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6260         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6261         do {
6262                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6263                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6264                         status = I40E_SUCCESS;
6265                         break;
6266                 }
6267                 i40e_usec_delay(10);
6268                 retry--;
6269         } while (retry);
6270         if (status) {
6271                 i40e_debug(hw, I40E_DEBUG_PHY,
6272                            "PHY: Can't write command to external PHY.\n");
6273                 goto phy_write_end;
6274         }
6275
6276         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6277         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6278
6279         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6280                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6281                   (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6282                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6283                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6284                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6285         status = I40E_ERR_TIMEOUT;
6286         retry = 1000;
6287         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6288         do {
6289                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6290                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6291                         status = I40E_SUCCESS;
6292                         break;
6293                 }
6294                 i40e_usec_delay(10);
6295                 retry--;
6296         } while (retry);
6297
6298 phy_write_end:
6299         return status;
6300 }
6301
6302 /**
6303  * i40e_write_phy_register
6304  * @hw: pointer to the HW structure
6305  * @page: registers page number
6306  * @reg: register address in the page
6307  * @phy_adr: PHY address on MDIO interface
6308  * @value: PHY register value
6309  *
6310  * Writes value to specified PHY register
6311  **/
6312 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6313                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6314 {
6315         enum i40e_status_code status;
6316
6317         switch (hw->device_id) {
6318         case I40E_DEV_ID_1G_BASE_T_X722:
6319                 status = i40e_write_phy_register_clause22(hw,
6320                         reg, phy_addr, value);
6321                 break;
6322         case I40E_DEV_ID_10G_BASE_T:
6323         case I40E_DEV_ID_10G_BASE_T4:
6324         case I40E_DEV_ID_10G_BASE_T_X722:
6325         case I40E_DEV_ID_25G_B:
6326         case I40E_DEV_ID_25G_SFP28:
6327                 status = i40e_write_phy_register_clause45(hw,
6328                         page, reg, phy_addr, value);
6329                 break;
6330         default:
6331                 status = I40E_ERR_UNKNOWN_PHY;
6332                 break;
6333         }
6334
6335         return status;
6336 }
6337
6338 /**
6339  * i40e_read_phy_register
6340  * @hw: pointer to the HW structure
6341  * @page: registers page number
6342  * @reg: register address in the page
6343  * @phy_adr: PHY address on MDIO interface
6344  * @value: PHY register value
6345  *
6346  * Reads specified PHY register value
6347  **/
6348 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6349                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6350 {
6351         enum i40e_status_code status;
6352
6353         switch (hw->device_id) {
6354         case I40E_DEV_ID_1G_BASE_T_X722:
6355                 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6356                                                          value);
6357                 break;
6358         case I40E_DEV_ID_10G_BASE_T:
6359         case I40E_DEV_ID_10G_BASE_T4:
6360         case I40E_DEV_ID_10G_BASE_T_X722:
6361         case I40E_DEV_ID_25G_B:
6362         case I40E_DEV_ID_25G_SFP28:
6363                 status = i40e_read_phy_register_clause45(hw, page, reg,
6364                                                          phy_addr, value);
6365                 break;
6366         default:
6367                 status = I40E_ERR_UNKNOWN_PHY;
6368                 break;
6369         }
6370
6371         return status;
6372 }
6373
6374 /**
6375  * i40e_get_phy_address
6376  * @hw: pointer to the HW structure
6377  * @dev_num: PHY port num that address we want
6378  * @phy_addr: Returned PHY address
6379  *
6380  * Gets PHY address for current port
6381  **/
6382 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6383 {
6384         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6385         u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6386
6387         return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6388 }
6389
6390 /**
6391  * i40e_blink_phy_led
6392  * @hw: pointer to the HW structure
6393  * @time: time how long led will blinks in secs
6394  * @interval: gap between LED on and off in msecs
6395  *
6396  * Blinks PHY link LED
6397  **/
6398 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6399                                               u32 time, u32 interval)
6400 {
6401         enum i40e_status_code status = I40E_SUCCESS;
6402         u32 i;
6403         u16 led_ctl = 0;
6404         u16 gpio_led_port;
6405         u16 led_reg;
6406         u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6407         u8 phy_addr = 0;
6408         u8 port_num;
6409
6410         i = rd32(hw, I40E_PFGEN_PORTNUM);
6411         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6412         phy_addr = i40e_get_phy_address(hw, port_num);
6413
6414         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6415              led_addr++) {
6416                 status = i40e_read_phy_register_clause45(hw,
6417                                                          I40E_PHY_COM_REG_PAGE,
6418                                                          led_addr, phy_addr,
6419                                                          &led_reg);
6420                 if (status)
6421                         goto phy_blinking_end;
6422                 led_ctl = led_reg;
6423                 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6424                         led_reg = 0;
6425                         status = i40e_write_phy_register_clause45(hw,
6426                                                          I40E_PHY_COM_REG_PAGE,
6427                                                          led_addr, phy_addr,
6428                                                          led_reg);
6429                         if (status)
6430                                 goto phy_blinking_end;
6431                         break;
6432                 }
6433         }
6434
6435         if (time > 0 && interval > 0) {
6436                 for (i = 0; i < time * 1000; i += interval) {
6437                         status = i40e_read_phy_register_clause45(hw,
6438                                                 I40E_PHY_COM_REG_PAGE,
6439                                                 led_addr, phy_addr, &led_reg);
6440                         if (status)
6441                                 goto restore_config;
6442                         if (led_reg & I40E_PHY_LED_MANUAL_ON)
6443                                 led_reg = 0;
6444                         else
6445                                 led_reg = I40E_PHY_LED_MANUAL_ON;
6446                         status = i40e_write_phy_register_clause45(hw,
6447                                                 I40E_PHY_COM_REG_PAGE,
6448                                                 led_addr, phy_addr, led_reg);
6449                         if (status)
6450                                 goto restore_config;
6451                         i40e_msec_delay(interval);
6452                 }
6453         }
6454
6455 restore_config:
6456         status = i40e_write_phy_register_clause45(hw,
6457                                                   I40E_PHY_COM_REG_PAGE,
6458                                                   led_addr, phy_addr, led_ctl);
6459
6460 phy_blinking_end:
6461         return status;
6462 }
6463
6464 /**
6465  * i40e_led_get_phy - return current on/off mode
6466  * @hw: pointer to the hw struct
6467  * @led_addr: address of led register to use
6468  * @val: original value of register to use
6469  *
6470  **/
6471 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6472                                        u16 *val)
6473 {
6474         enum i40e_status_code status = I40E_SUCCESS;
6475         u16 gpio_led_port;
6476         u8 phy_addr = 0;
6477         u16 reg_val;
6478         u16 temp_addr;
6479         u8 port_num;
6480         u32 i;
6481
6482         temp_addr = I40E_PHY_LED_PROV_REG_1;
6483         i = rd32(hw, I40E_PFGEN_PORTNUM);
6484         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6485         phy_addr = i40e_get_phy_address(hw, port_num);
6486
6487         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6488              temp_addr++) {
6489                 status = i40e_read_phy_register_clause45(hw,
6490                                                          I40E_PHY_COM_REG_PAGE,
6491                                                          temp_addr, phy_addr,
6492                                                          &reg_val);
6493                 if (status)
6494                         return status;
6495                 *val = reg_val;
6496                 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6497                         *led_addr = temp_addr;
6498                         break;
6499                 }
6500         }
6501         return status;
6502 }
6503
6504 /**
6505  * i40e_led_set_phy
6506  * @hw: pointer to the HW structure
6507  * @on: true or false
6508  * @mode: original val plus bit for set or ignore
6509  * Set led's on or off when controlled by the PHY
6510  *
6511  **/
6512 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6513                                        u16 led_addr, u32 mode)
6514 {
6515         enum i40e_status_code status = I40E_SUCCESS;
6516         u16 led_ctl = 0;
6517         u16 led_reg = 0;
6518         u8 phy_addr = 0;
6519         u8 port_num;
6520         u32 i;
6521
6522         i = rd32(hw, I40E_PFGEN_PORTNUM);
6523         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6524         phy_addr = i40e_get_phy_address(hw, port_num);
6525         status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6526                                                  led_addr, phy_addr, &led_reg);
6527         if (status)
6528                 return status;
6529         led_ctl = led_reg;
6530         if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6531                 led_reg = 0;
6532                 status = i40e_write_phy_register_clause45(hw,
6533                                                           I40E_PHY_COM_REG_PAGE,
6534                                                           led_addr, phy_addr,
6535                                                           led_reg);
6536                 if (status)
6537                         return status;
6538         }
6539         status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6540                                                  led_addr, phy_addr, &led_reg);
6541         if (status)
6542                 goto restore_config;
6543         if (on)
6544                 led_reg = I40E_PHY_LED_MANUAL_ON;
6545         else
6546                 led_reg = 0;
6547         status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6548                                                   led_addr, phy_addr, led_reg);
6549         if (status)
6550                 goto restore_config;
6551         if (mode & I40E_PHY_LED_MODE_ORIG) {
6552                 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6553                 status = i40e_write_phy_register_clause45(hw,
6554                                                  I40E_PHY_COM_REG_PAGE,
6555                                                  led_addr, phy_addr, led_ctl);
6556         }
6557         return status;
6558 restore_config:
6559         status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6560                                                   led_addr, phy_addr, led_ctl);
6561         return status;
6562 }
6563 #endif /* PF_DRIVER */
6564
6565 /**
6566  * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6567  * @hw: pointer to the hw struct
6568  * @reg_addr: register address
6569  * @reg_val: ptr to register value
6570  * @cmd_details: pointer to command details structure or NULL
6571  *
6572  * Use the firmware to read the Rx control register,
6573  * especially useful if the Rx unit is under heavy pressure
6574  **/
6575 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6576                                 u32 reg_addr, u32 *reg_val,
6577                                 struct i40e_asq_cmd_details *cmd_details)
6578 {
6579         struct i40e_aq_desc desc;
6580         struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
6581                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6582         enum i40e_status_code status;
6583
6584         if (reg_val == NULL)
6585                 return I40E_ERR_PARAM;
6586
6587         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
6588
6589         cmd_resp->address = CPU_TO_LE32(reg_addr);
6590
6591         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6592
6593         if (status == I40E_SUCCESS)
6594                 *reg_val = LE32_TO_CPU(cmd_resp->value);
6595
6596         return status;
6597 }
6598
6599 /**
6600  * i40e_read_rx_ctl - read from an Rx control register
6601  * @hw: pointer to the hw struct
6602  * @reg_addr: register address
6603  **/
6604 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
6605 {
6606         enum i40e_status_code status = I40E_SUCCESS;
6607         bool use_register;
6608         int retry = 5;
6609         u32 val = 0;
6610
6611         use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6612         if (!use_register) {
6613 do_retry:
6614                 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
6615                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6616                         i40e_msec_delay(1);
6617                         retry--;
6618                         goto do_retry;
6619                 }
6620         }
6621
6622         /* if the AQ access failed, try the old-fashioned way */
6623         if (status || use_register)
6624                 val = rd32(hw, reg_addr);
6625
6626         return val;
6627 }
6628
6629 /**
6630  * i40e_aq_rx_ctl_write_register
6631  * @hw: pointer to the hw struct
6632  * @reg_addr: register address
6633  * @reg_val: register value
6634  * @cmd_details: pointer to command details structure or NULL
6635  *
6636  * Use the firmware to write to an Rx control register,
6637  * especially useful if the Rx unit is under heavy pressure
6638  **/
6639 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
6640                                 u32 reg_addr, u32 reg_val,
6641                                 struct i40e_asq_cmd_details *cmd_details)
6642 {
6643         struct i40e_aq_desc desc;
6644         struct i40e_aqc_rx_ctl_reg_read_write *cmd =
6645                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6646         enum i40e_status_code status;
6647
6648         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
6649
6650         cmd->address = CPU_TO_LE32(reg_addr);
6651         cmd->value = CPU_TO_LE32(reg_val);
6652
6653         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6654
6655         return status;
6656 }
6657
6658 /**
6659  * i40e_write_rx_ctl - write to an Rx control register
6660  * @hw: pointer to the hw struct
6661  * @reg_addr: register address
6662  * @reg_val: register value
6663  **/
6664 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
6665 {
6666         enum i40e_status_code status = I40E_SUCCESS;
6667         bool use_register;
6668         int retry = 5;
6669
6670         use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6671         if (!use_register) {
6672 do_retry:
6673                 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
6674                                                        reg_val, NULL);
6675                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6676                         i40e_msec_delay(1);
6677                         retry--;
6678                         goto do_retry;
6679                 }
6680         }
6681
6682         /* if the AQ access failed, try the old-fashioned way */
6683         if (status || use_register)
6684                 wr32(hw, reg_addr, reg_val);
6685 }
6686 #ifdef VF_DRIVER
6687
6688 /**
6689  * i40e_aq_send_msg_to_pf
6690  * @hw: pointer to the hardware structure
6691  * @v_opcode: opcodes for VF-PF communication
6692  * @v_retval: return error code
6693  * @msg: pointer to the msg buffer
6694  * @msglen: msg length
6695  * @cmd_details: pointer to command details
6696  *
6697  * Send message to PF driver using admin queue. By default, this message
6698  * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
6699  * completion before returning.
6700  **/
6701 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
6702                                 enum i40e_virtchnl_ops v_opcode,
6703                                 enum i40e_status_code v_retval,
6704                                 u8 *msg, u16 msglen,
6705                                 struct i40e_asq_cmd_details *cmd_details)
6706 {
6707         struct i40e_aq_desc desc;
6708         struct i40e_asq_cmd_details details;
6709         enum i40e_status_code status;
6710
6711         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
6712         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
6713         desc.cookie_high = CPU_TO_LE32(v_opcode);
6714         desc.cookie_low = CPU_TO_LE32(v_retval);
6715         if (msglen) {
6716                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
6717                                                 | I40E_AQ_FLAG_RD));
6718                 if (msglen > I40E_AQ_LARGE_BUF)
6719                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6720                 desc.datalen = CPU_TO_LE16(msglen);
6721         }
6722         if (!cmd_details) {
6723                 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
6724                 details.async = true;
6725                 cmd_details = &details;
6726         }
6727         status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
6728                                        msglen, cmd_details);
6729         return status;
6730 }
6731
6732 /**
6733  * i40e_vf_parse_hw_config
6734  * @hw: pointer to the hardware structure
6735  * @msg: pointer to the virtual channel VF resource structure
6736  *
6737  * Given a VF resource message from the PF, populate the hw struct
6738  * with appropriate information.
6739  **/
6740 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
6741                              struct i40e_virtchnl_vf_resource *msg)
6742 {
6743         struct i40e_virtchnl_vsi_resource *vsi_res;
6744         int i;
6745
6746         vsi_res = &msg->vsi_res[0];
6747
6748         hw->dev_caps.num_vsis = msg->num_vsis;
6749         hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
6750         hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
6751         hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
6752         hw->dev_caps.dcb = msg->vf_offload_flags &
6753                            I40E_VIRTCHNL_VF_OFFLOAD_L2;
6754         hw->dev_caps.fcoe = (msg->vf_offload_flags &
6755                              I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
6756         hw->dev_caps.iwarp = (msg->vf_offload_flags &
6757                               I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
6758         for (i = 0; i < msg->num_vsis; i++) {
6759                 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
6760                         i40e_memcpy(hw->mac.perm_addr,
6761                                     vsi_res->default_mac_addr,
6762                                     I40E_ETH_LENGTH_OF_ADDRESS,
6763                                     I40E_NONDMA_TO_NONDMA);
6764                         i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
6765                                     I40E_ETH_LENGTH_OF_ADDRESS,
6766                                     I40E_NONDMA_TO_NONDMA);
6767                 }
6768                 vsi_res++;
6769         }
6770 }
6771
6772 /**
6773  * i40e_vf_reset
6774  * @hw: pointer to the hardware structure
6775  *
6776  * Send a VF_RESET message to the PF. Does not wait for response from PF
6777  * as none will be forthcoming. Immediately after calling this function,
6778  * the admin queue should be shut down and (optionally) reinitialized.
6779  **/
6780 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
6781 {
6782         return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
6783                                       I40E_SUCCESS, NULL, 0, NULL);
6784 }
6785 #endif /* VF_DRIVER */
6786 #ifdef X722_SUPPORT
6787
6788 /**
6789  * i40e_aq_set_arp_proxy_config
6790  * @hw: pointer to the HW structure
6791  * @proxy_config - pointer to proxy config command table struct
6792  * @cmd_details: pointer to command details
6793  *
6794  * Set ARP offload parameters from pre-populated
6795  * i40e_aqc_arp_proxy_data struct
6796  **/
6797 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
6798                                 struct i40e_aqc_arp_proxy_data *proxy_config,
6799                                 struct i40e_asq_cmd_details *cmd_details)
6800 {
6801         struct i40e_aq_desc desc;
6802         enum i40e_status_code status;
6803
6804         if (!proxy_config)
6805                 return I40E_ERR_PARAM;
6806
6807         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
6808
6809         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6810         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6811         desc.params.external.addr_high =
6812                                   CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
6813         desc.params.external.addr_low =
6814                                   CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
6815         desc.datalen = sizeof(struct i40e_aqc_arp_proxy_data);
6816
6817         status = i40e_asq_send_command(hw, &desc, proxy_config,
6818                                        sizeof(struct i40e_aqc_arp_proxy_data),
6819                                        cmd_details);
6820
6821         return status;
6822 }
6823
6824 /**
6825  * i40e_aq_opc_set_ns_proxy_table_entry
6826  * @hw: pointer to the HW structure
6827  * @ns_proxy_table_entry: pointer to NS table entry command struct
6828  * @cmd_details: pointer to command details
6829  *
6830  * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
6831  * from pre-populated i40e_aqc_ns_proxy_data struct
6832  **/
6833 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
6834                         struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
6835                         struct i40e_asq_cmd_details *cmd_details)
6836 {
6837         struct i40e_aq_desc desc;
6838         enum i40e_status_code status;
6839
6840         if (!ns_proxy_table_entry)
6841                 return I40E_ERR_PARAM;
6842
6843         i40e_fill_default_direct_cmd_desc(&desc,
6844                                 i40e_aqc_opc_set_ns_proxy_table_entry);
6845
6846         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6847         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6848         desc.params.external.addr_high =
6849                 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
6850         desc.params.external.addr_low =
6851                 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
6852         desc.datalen = sizeof(struct i40e_aqc_ns_proxy_data);
6853
6854         status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
6855                                        sizeof(struct i40e_aqc_ns_proxy_data),
6856                                        cmd_details);
6857
6858         return status;
6859 }
6860
6861 /**
6862  * i40e_aq_set_clear_wol_filter
6863  * @hw: pointer to the hw struct
6864  * @filter_index: index of filter to modify (0-7)
6865  * @filter: buffer containing filter to be set
6866  * @set_filter: true to set filter, false to clear filter
6867  * @no_wol_tco: if true, pass through packets cannot cause wake-up
6868  *              if false, pass through packets may cause wake-up
6869  * @filter_valid: true if filter action is valid
6870  * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
6871  * @cmd_details: pointer to command details structure or NULL
6872  *
6873  * Set or clear WoL filter for port attached to the PF
6874  **/
6875 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
6876                                 u8 filter_index,
6877                                 struct i40e_aqc_set_wol_filter_data *filter,
6878                                 bool set_filter, bool no_wol_tco,
6879                                 bool filter_valid, bool no_wol_tco_valid,
6880                                 struct i40e_asq_cmd_details *cmd_details)
6881 {
6882         struct i40e_aq_desc desc;
6883         struct i40e_aqc_set_wol_filter *cmd =
6884                 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
6885         enum i40e_status_code status;
6886         u16 cmd_flags = 0;
6887         u16 valid_flags = 0;
6888         u16 buff_len = 0;
6889
6890         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
6891
6892         if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
6893                 return  I40E_ERR_PARAM;
6894         cmd->filter_index = CPU_TO_LE16(filter_index);
6895
6896         if (set_filter) {
6897                 if (!filter)
6898                         return  I40E_ERR_PARAM;
6899
6900                 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
6901                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR;
6902         }
6903
6904         if (no_wol_tco)
6905                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
6906         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
6907
6908         if (filter_valid)
6909                 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
6910         if (no_wol_tco_valid)
6911                 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
6912         cmd->valid_flags = CPU_TO_LE16(valid_flags);
6913
6914         buff_len = sizeof(*filter);
6915         desc.datalen = buff_len;
6916
6917         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6918         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6919
6920         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
6921         cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
6922
6923         status = i40e_asq_send_command(hw, &desc, filter,
6924                                        buff_len, cmd_details);
6925
6926         return status;
6927 }
6928
6929 /**
6930  * i40e_aq_get_wake_event_reason
6931  * @hw: pointer to the hw struct
6932  * @wake_reason: return value, index of matching filter
6933  * @cmd_details: pointer to command details structure or NULL
6934  *
6935  * Get information for the reason of a Wake Up event
6936  **/
6937 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
6938                                 u16 *wake_reason,
6939                                 struct i40e_asq_cmd_details *cmd_details)
6940 {
6941         struct i40e_aq_desc desc;
6942         struct i40e_aqc_get_wake_reason_completion *resp =
6943                 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
6944         enum i40e_status_code status;
6945
6946         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
6947
6948         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6949
6950         if (status == I40E_SUCCESS)
6951                 *wake_reason = LE16_TO_CPU(resp->wake_reason);
6952
6953         return status;
6954 }
6955
6956 /**
6957 * i40e_aq_clear_all_wol_filters
6958 * @hw: pointer to the hw struct
6959 * @cmd_details: pointer to command details structure or NULL
6960 *
6961 * Get information for the reason of a Wake Up event
6962 **/
6963 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw,
6964         struct i40e_asq_cmd_details *cmd_details)
6965 {
6966         struct i40e_aq_desc desc;
6967         enum i40e_status_code status;
6968
6969         i40e_fill_default_direct_cmd_desc(&desc,
6970                                           i40e_aqc_opc_clear_all_wol_filters);
6971
6972         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6973
6974         return status;
6975 }
6976 #endif /* X722_SUPPORT */