drivers/net/i40e/base/i40e_common.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001-2018
   3  */
   4
   5 #include "i40e_type.h"
   6 #include "i40e_adminq.h"
   7 #include "i40e_prototype.h"
   8 #include "virtchnl.h"
   9
  10 /**
  11  * i40e_set_mac_type - Sets MAC type
  12  * @hw: pointer to the HW structure
  13  *
  14  * This function sets the mac type of the adapter based on the
  15  * vendor ID and device ID stored in the hw structure.
  16  **/
  17 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  18 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  19 #else
  20 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  21 #endif
  22 {
  23         enum i40e_status_code status = I40E_SUCCESS;
  24
  25         DEBUGFUNC("i40e_set_mac_type\n");
  26
  27         if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
  28                 switch (hw->device_id) {
  29                 case I40E_DEV_ID_SFP_XL710:
  30                 case I40E_DEV_ID_QEMU:
  31                 case I40E_DEV_ID_KX_B:
  32                 case I40E_DEV_ID_KX_C:
  33                 case I40E_DEV_ID_QSFP_A:
  34                 case I40E_DEV_ID_QSFP_B:
  35                 case I40E_DEV_ID_QSFP_C:
  36                 case I40E_DEV_ID_10G_BASE_T:
  37                 case I40E_DEV_ID_10G_BASE_T4:
  38                 case I40E_DEV_ID_20G_KR2:
  39                 case I40E_DEV_ID_20G_KR2_A:
  40                 case I40E_DEV_ID_25G_B:
  41                 case I40E_DEV_ID_25G_SFP28:
  42                         hw->mac.type = I40E_MAC_XL710;
  43                         break;
  44 #ifdef X722_A0_SUPPORT
  45                 case I40E_DEV_ID_X722_A0:
  46 #endif
  47                 case I40E_DEV_ID_KX_X722:
  48                 case I40E_DEV_ID_QSFP_X722:
  49                 case I40E_DEV_ID_SFP_X722:
  50                 case I40E_DEV_ID_1G_BASE_T_X722:
  51                 case I40E_DEV_ID_10G_BASE_T_X722:
  52                 case I40E_DEV_ID_SFP_I_X722:
  53                         hw->mac.type = I40E_MAC_X722;
  54                         break;
  55 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  56                 case I40E_DEV_ID_X722_VF:
  57 #ifdef X722_A0_SUPPORT
  58                 case I40E_DEV_ID_X722_A0_VF:
  59 #endif
  60                         hw->mac.type = I40E_MAC_X722_VF;
  61                         break;
  62 #endif /* INTEGRATED_VF || VF_DRIVER */
  63 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  64                 case I40E_DEV_ID_VF:
  65                 case I40E_DEV_ID_VF_HV:
  66                 case I40E_DEV_ID_ADAPTIVE_VF:
  67                         hw->mac.type = I40E_MAC_VF;
  68                         break;
  69 #endif
  70                 default:
  71                         hw->mac.type = I40E_MAC_GENERIC;
  72                         break;
  73                 }
  74         } else {
  75                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
  76         }
  77
  78         DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
  79                   hw->mac.type, status);
  80         return status;
  81 }
  82
  83 /**
  84  * i40e_aq_str - convert AQ err code to a string
  85  * @hw: pointer to the HW structure
  86  * @aq_err: the AQ error code to convert
  87  **/
  88 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
  89 {
  90         switch (aq_err) {
  91         case I40E_AQ_RC_OK:
  92                 return "OK";
  93         case I40E_AQ_RC_EPERM:
  94                 return "I40E_AQ_RC_EPERM";
  95         case I40E_AQ_RC_ENOENT:
  96                 return "I40E_AQ_RC_ENOENT";
  97         case I40E_AQ_RC_ESRCH:
  98                 return "I40E_AQ_RC_ESRCH";
  99         case I40E_AQ_RC_EINTR:
 100                 return "I40E_AQ_RC_EINTR";
 101         case I40E_AQ_RC_EIO:
 102                 return "I40E_AQ_RC_EIO";
 103         case I40E_AQ_RC_ENXIO:
 104                 return "I40E_AQ_RC_ENXIO";
 105         case I40E_AQ_RC_E2BIG:
 106                 return "I40E_AQ_RC_E2BIG";
 107         case I40E_AQ_RC_EAGAIN:
 108                 return "I40E_AQ_RC_EAGAIN";
 109         case I40E_AQ_RC_ENOMEM:
 110                 return "I40E_AQ_RC_ENOMEM";
 111         case I40E_AQ_RC_EACCES:
 112                 return "I40E_AQ_RC_EACCES";
 113         case I40E_AQ_RC_EFAULT:
 114                 return "I40E_AQ_RC_EFAULT";
 115         case I40E_AQ_RC_EBUSY:
 116                 return "I40E_AQ_RC_EBUSY";
 117         case I40E_AQ_RC_EEXIST:
 118                 return "I40E_AQ_RC_EEXIST";
 119         case I40E_AQ_RC_EINVAL:
 120                 return "I40E_AQ_RC_EINVAL";
 121         case I40E_AQ_RC_ENOTTY:
 122                 return "I40E_AQ_RC_ENOTTY";
 123         case I40E_AQ_RC_ENOSPC:
 124                 return "I40E_AQ_RC_ENOSPC";
 125         case I40E_AQ_RC_ENOSYS:
 126                 return "I40E_AQ_RC_ENOSYS";
 127         case I40E_AQ_RC_ERANGE:
 128                 return "I40E_AQ_RC_ERANGE";
 129         case I40E_AQ_RC_EFLUSHED:
 130                 return "I40E_AQ_RC_EFLUSHED";
 131         case I40E_AQ_RC_BAD_ADDR:
 132                 return "I40E_AQ_RC_BAD_ADDR";
 133         case I40E_AQ_RC_EMODE:
 134                 return "I40E_AQ_RC_EMODE";
 135         case I40E_AQ_RC_EFBIG:
 136                 return "I40E_AQ_RC_EFBIG";
 137         }
 138
 139         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 140         return hw->err_str;
 141 }
 142
 143 /**
 144  * i40e_stat_str - convert status err code to a string
 145  * @hw: pointer to the HW structure
 146  * @stat_err: the status error code to convert
 147  **/
 148 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
 149 {
 150         switch (stat_err) {
 151         case I40E_SUCCESS:
 152                 return "OK";
 153         case I40E_ERR_NVM:
 154                 return "I40E_ERR_NVM";
 155         case I40E_ERR_NVM_CHECKSUM:
 156                 return "I40E_ERR_NVM_CHECKSUM";
 157         case I40E_ERR_PHY:
 158                 return "I40E_ERR_PHY";
 159         case I40E_ERR_CONFIG:
 160                 return "I40E_ERR_CONFIG";
 161         case I40E_ERR_PARAM:
 162                 return "I40E_ERR_PARAM";
 163         case I40E_ERR_MAC_TYPE:
 164                 return "I40E_ERR_MAC_TYPE";
 165         case I40E_ERR_UNKNOWN_PHY:
 166                 return "I40E_ERR_UNKNOWN_PHY";
 167         case I40E_ERR_LINK_SETUP:
 168                 return "I40E_ERR_LINK_SETUP";
 169         case I40E_ERR_ADAPTER_STOPPED:
 170                 return "I40E_ERR_ADAPTER_STOPPED";
 171         case I40E_ERR_INVALID_MAC_ADDR:
 172                 return "I40E_ERR_INVALID_MAC_ADDR";
 173         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 174                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 175         case I40E_ERR_MASTER_REQUESTS_PENDING:
 176                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 177         case I40E_ERR_INVALID_LINK_SETTINGS:
 178                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 179         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 180                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 181         case I40E_ERR_RESET_FAILED:
 182                 return "I40E_ERR_RESET_FAILED";
 183         case I40E_ERR_SWFW_SYNC:
 184                 return "I40E_ERR_SWFW_SYNC";
 185         case I40E_ERR_NO_AVAILABLE_VSI:
 186                 return "I40E_ERR_NO_AVAILABLE_VSI";
 187         case I40E_ERR_NO_MEMORY:
 188                 return "I40E_ERR_NO_MEMORY";
 189         case I40E_ERR_BAD_PTR:
 190                 return "I40E_ERR_BAD_PTR";
 191         case I40E_ERR_RING_FULL:
 192                 return "I40E_ERR_RING_FULL";
 193         case I40E_ERR_INVALID_PD_ID:
 194                 return "I40E_ERR_INVALID_PD_ID";
 195         case I40E_ERR_INVALID_QP_ID:
 196                 return "I40E_ERR_INVALID_QP_ID";
 197         case I40E_ERR_INVALID_CQ_ID:
 198                 return "I40E_ERR_INVALID_CQ_ID";
 199         case I40E_ERR_INVALID_CEQ_ID:
 200                 return "I40E_ERR_INVALID_CEQ_ID";
 201         case I40E_ERR_INVALID_AEQ_ID:
 202                 return "I40E_ERR_INVALID_AEQ_ID";
 203         case I40E_ERR_INVALID_SIZE:
 204                 return "I40E_ERR_INVALID_SIZE";
 205         case I40E_ERR_INVALID_ARP_INDEX:
 206                 return "I40E_ERR_INVALID_ARP_INDEX";
 207         case I40E_ERR_INVALID_FPM_FUNC_ID:
 208                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 209         case I40E_ERR_QP_INVALID_MSG_SIZE:
 210                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 211         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 212                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 213         case I40E_ERR_INVALID_FRAG_COUNT:
 214                 return "I40E_ERR_INVALID_FRAG_COUNT";
 215         case I40E_ERR_QUEUE_EMPTY:
 216                 return "I40E_ERR_QUEUE_EMPTY";
 217         case I40E_ERR_INVALID_ALIGNMENT:
 218                 return "I40E_ERR_INVALID_ALIGNMENT";
 219         case I40E_ERR_FLUSHED_QUEUE:
 220                 return "I40E_ERR_FLUSHED_QUEUE";
 221         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 222                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 223         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 224                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 225         case I40E_ERR_TIMEOUT:
 226                 return "I40E_ERR_TIMEOUT";
 227         case I40E_ERR_OPCODE_MISMATCH:
 228                 return "I40E_ERR_OPCODE_MISMATCH";
 229         case I40E_ERR_CQP_COMPL_ERROR:
 230                 return "I40E_ERR_CQP_COMPL_ERROR";
 231         case I40E_ERR_INVALID_VF_ID:
 232                 return "I40E_ERR_INVALID_VF_ID";
 233         case I40E_ERR_INVALID_HMCFN_ID:
 234                 return "I40E_ERR_INVALID_HMCFN_ID";
 235         case I40E_ERR_BACKING_PAGE_ERROR:
 236                 return "I40E_ERR_BACKING_PAGE_ERROR";
 237         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 238                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 239         case I40E_ERR_INVALID_PBLE_INDEX:
 240                 return "I40E_ERR_INVALID_PBLE_INDEX";
 241         case I40E_ERR_INVALID_SD_INDEX:
 242                 return "I40E_ERR_INVALID_SD_INDEX";
 243         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 244                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 245         case I40E_ERR_INVALID_SD_TYPE:
 246                 return "I40E_ERR_INVALID_SD_TYPE";
 247         case I40E_ERR_MEMCPY_FAILED:
 248                 return "I40E_ERR_MEMCPY_FAILED";
 249         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 250                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 251         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 252                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 253         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 254                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 255         case I40E_ERR_SRQ_ENABLED:
 256                 return "I40E_ERR_SRQ_ENABLED";
 257         case I40E_ERR_ADMIN_QUEUE_ERROR:
 258                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 259         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 260                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 261         case I40E_ERR_BUF_TOO_SHORT:
 262                 return "I40E_ERR_BUF_TOO_SHORT";
 263         case I40E_ERR_ADMIN_QUEUE_FULL:
 264                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 265         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 266                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 267         case I40E_ERR_BAD_IWARP_CQE:
 268                 return "I40E_ERR_BAD_IWARP_CQE";
 269         case I40E_ERR_NVM_BLANK_MODE:
 270                 return "I40E_ERR_NVM_BLANK_MODE";
 271         case I40E_ERR_NOT_IMPLEMENTED:
 272                 return "I40E_ERR_NOT_IMPLEMENTED";
 273         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 274                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 275         case I40E_ERR_DIAG_TEST_FAILED:
 276                 return "I40E_ERR_DIAG_TEST_FAILED";
 277         case I40E_ERR_NOT_READY:
 278                 return "I40E_ERR_NOT_READY";
 279         case I40E_NOT_SUPPORTED:
 280                 return "I40E_NOT_SUPPORTED";
 281         case I40E_ERR_FIRMWARE_API_VERSION:
 282                 return "I40E_ERR_FIRMWARE_API_VERSION";
 283         case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR:
 284                 return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR";
 285         }
 286
 287         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 288         return hw->err_str;
 289 }
 290
 291 /**
 292  * i40e_debug_aq
 293  * @hw: debug mask related to admin queue
 294  * @mask: debug mask
 295  * @desc: pointer to admin queue descriptor
 296  * @buffer: pointer to command buffer
 297  * @buf_len: max length of buffer
 298  *
 299  * Dumps debug log about adminq command with descriptor contents.
 300  **/
 301 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 302                    void *buffer, u16 buf_len)
 303 {
 304         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 305         u8 *buf = (u8 *)buffer;
 306         u16 len;
 307         u16 i = 0;
 308
 309         if ((!(mask & hw->debug_mask)) || (desc == NULL))
 310                 return;
 311
 312         len = LE16_TO_CPU(aq_desc->datalen);
 313
 314         i40e_debug(hw, mask,
 315                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 316                    LE16_TO_CPU(aq_desc->opcode),
 317                    LE16_TO_CPU(aq_desc->flags),
 318                    LE16_TO_CPU(aq_desc->datalen),
 319                    LE16_TO_CPU(aq_desc->retval));
 320         i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
 321                    LE32_TO_CPU(aq_desc->cookie_high),
 322                    LE32_TO_CPU(aq_desc->cookie_low));
 323         i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
 324                    LE32_TO_CPU(aq_desc->params.internal.param0),
 325                    LE32_TO_CPU(aq_desc->params.internal.param1));
 326         i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
 327                    LE32_TO_CPU(aq_desc->params.external.addr_high),
 328                    LE32_TO_CPU(aq_desc->params.external.addr_low));
 329
 330         if ((buffer != NULL) && (aq_desc->datalen != 0)) {
 331                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 332                 if (buf_len < len)
 333                         len = buf_len;
 334                 /* write the full 16-byte chunks */
 335                 for (i = 0; i < (len - 16); i += 16)
 336                         i40e_debug(hw, mask,
 337                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 338                                    i, buf[i], buf[i+1], buf[i+2], buf[i+3],
 339                                    buf[i+4], buf[i+5], buf[i+6], buf[i+7],
 340                                    buf[i+8], buf[i+9], buf[i+10], buf[i+11],
 341                                    buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
 342                 /* the most we could have left is 16 bytes, pad with zeros */
 343                 if (i < len) {
 344                         char d_buf[16];
 345                         int j, i_sav;
 346
 347                         i_sav = i;
 348                         memset(d_buf, 0, sizeof(d_buf));
 349                         for (j = 0; i < len; j++, i++)
 350                                 d_buf[j] = buf[i];
 351                         i40e_debug(hw, mask,
 352                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 353                                    i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
 354                                    d_buf[4], d_buf[5], d_buf[6], d_buf[7],
 355                                    d_buf[8], d_buf[9], d_buf[10], d_buf[11],
 356                                    d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
 357                 }
 358         }
 359 }
 360
 361 /**
 362  * i40e_check_asq_alive
 363  * @hw: pointer to the hw struct
 364  *
 365  * Returns true if Queue is enabled else false.
 366  **/
 367 bool i40e_check_asq_alive(struct i40e_hw *hw)
 368 {
 369         if (hw->aq.asq.len)
 370 #ifdef PF_DRIVER
 371 #ifdef INTEGRATED_VF
 372                 if (!i40e_is_vf(hw))
 373                         return !!(rd32(hw, hw->aq.asq.len) &
 374                                 I40E_PF_ATQLEN_ATQENABLE_MASK);
 375 #else
 376                 return !!(rd32(hw, hw->aq.asq.len) &
 377                         I40E_PF_ATQLEN_ATQENABLE_MASK);
 378 #endif /* INTEGRATED_VF */
 379 #endif /* PF_DRIVER */
 380 #ifdef VF_DRIVER
 381 #ifdef INTEGRATED_VF
 382                 if (i40e_is_vf(hw))
 383                         return !!(rd32(hw, hw->aq.asq.len) &
 384                                 I40E_VF_ATQLEN1_ATQENABLE_MASK);
 385 #else
 386                 return !!(rd32(hw, hw->aq.asq.len) &
 387                         I40E_VF_ATQLEN1_ATQENABLE_MASK);
 388 #endif /* INTEGRATED_VF */
 389 #endif /* VF_DRIVER */
 390         return false;
 391 }
 392
 393 /**
 394  * i40e_aq_queue_shutdown
 395  * @hw: pointer to the hw struct
 396  * @unloading: is the driver unloading itself
 397  *
 398  * Tell the Firmware that we're shutting down the AdminQ and whether
 399  * or not the driver is unloading as well.
 400  **/
 401 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
 402                                              bool unloading)
 403 {
 404         struct i40e_aq_desc desc;
 405         struct i40e_aqc_queue_shutdown *cmd =
 406                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 407         enum i40e_status_code status;
 408
 409         i40e_fill_default_direct_cmd_desc(&desc,
 410                                           i40e_aqc_opc_queue_shutdown);
 411
 412         if (unloading)
 413                 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
 414         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 415
 416         return status;
 417 }
 418
 419 /**
 420  * i40e_aq_get_set_rss_lut
 421  * @hw: pointer to the hardware structure
 422  * @vsi_id: vsi fw index
 423  * @pf_lut: for PF table set true, for VSI table set false
 424  * @lut: pointer to the lut buffer provided by the caller
 425  * @lut_size: size of the lut buffer
 426  * @set: set true to set the table, false to get the table
 427  *
 428  * Internal function to get or set RSS look up table
 429  **/
 430 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 431                                                      u16 vsi_id, bool pf_lut,
 432                                                      u8 *lut, u16 lut_size,
 433                                                      bool set)
 434 {
 435         enum i40e_status_code status;
 436         struct i40e_aq_desc desc;
 437         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 438                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 439
 440         if (set)
 441                 i40e_fill_default_direct_cmd_desc(&desc,
 442                                                   i40e_aqc_opc_set_rss_lut);
 443         else
 444                 i40e_fill_default_direct_cmd_desc(&desc,
 445                                                   i40e_aqc_opc_get_rss_lut);
 446
 447         /* Indirect command */
 448         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 449         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 450
 451         cmd_resp->vsi_id =
 452                         CPU_TO_LE16((u16)((vsi_id <<
 453                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 454                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 455         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 456
 457         if (pf_lut)
 458                 cmd_resp->flags |= CPU_TO_LE16((u16)
 459                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 460                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 461                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 462         else
 463                 cmd_resp->flags |= CPU_TO_LE16((u16)
 464                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 465                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 466                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 467
 468         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 469
 470         return status;
 471 }
 472
 473 /**
 474  * i40e_aq_get_rss_lut
 475  * @hw: pointer to the hardware structure
 476  * @vsi_id: vsi fw index
 477  * @pf_lut: for PF table set true, for VSI table set false
 478  * @lut: pointer to the lut buffer provided by the caller
 479  * @lut_size: size of the lut buffer
 480  *
 481  * get the RSS lookup table, PF or VSI type
 482  **/
 483 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 484                                           bool pf_lut, u8 *lut, u16 lut_size)
 485 {
 486         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 487                                        false);
 488 }
 489
 490 /**
 491  * i40e_aq_set_rss_lut
 492  * @hw: pointer to the hardware structure
 493  * @vsi_id: vsi fw index
 494  * @pf_lut: for PF table set true, for VSI table set false
 495  * @lut: pointer to the lut buffer provided by the caller
 496  * @lut_size: size of the lut buffer
 497  *
 498  * set the RSS lookup table, PF or VSI type
 499  **/
 500 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 501                                           bool pf_lut, u8 *lut, u16 lut_size)
 502 {
 503         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
 504 }
 505
 506 /**
 507  * i40e_aq_get_set_rss_key
 508  * @hw: pointer to the hw struct
 509  * @vsi_id: vsi fw index
 510  * @key: pointer to key info struct
 511  * @set: set true to set the key, false to get the key
 512  *
 513  * get the RSS key per VSI
 514  **/
 515 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 516                                       u16 vsi_id,
 517                                       struct i40e_aqc_get_set_rss_key_data *key,
 518                                       bool set)
 519 {
 520         enum i40e_status_code status;
 521         struct i40e_aq_desc desc;
 522         struct i40e_aqc_get_set_rss_key *cmd_resp =
 523                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 524         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 525
 526         if (set)
 527                 i40e_fill_default_direct_cmd_desc(&desc,
 528                                                   i40e_aqc_opc_set_rss_key);
 529         else
 530                 i40e_fill_default_direct_cmd_desc(&desc,
 531                                                   i40e_aqc_opc_get_rss_key);
 532
 533         /* Indirect command */
 534         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 535         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 536
 537         cmd_resp->vsi_id =
 538                         CPU_TO_LE16((u16)((vsi_id <<
 539                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 540                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 541         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 542
 543         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 544
 545         return status;
 546 }
 547
 548 /**
 549  * i40e_aq_get_rss_key
 550  * @hw: pointer to the hw struct
 551  * @vsi_id: vsi fw index
 552  * @key: pointer to key info struct
 553  *
 554  **/
 555 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
 556                                       u16 vsi_id,
 557                                       struct i40e_aqc_get_set_rss_key_data *key)
 558 {
 559         return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
 560 }
 561
 562 /**
 563  * i40e_aq_set_rss_key
 564  * @hw: pointer to the hw struct
 565  * @vsi_id: vsi fw index
 566  * @key: pointer to key info struct
 567  *
 568  * set the RSS key per VSI
 569  **/
 570 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
 571                                       u16 vsi_id,
 572                                       struct i40e_aqc_get_set_rss_key_data *key)
 573 {
 574         return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
 575 }
 576
 577 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 578  * hardware to a bit-field that can be used by SW to more easily determine the
 579  * packet type.
 580  *
 581  * Macros are used to shorten the table lines and make this table human
 582  * readable.
 583  *
 584  * We store the PTYPE in the top byte of the bit field - this is just so that
 585  * we can check that the table doesn't have a row missing, as the index into
 586  * the table should be the PTYPE.
 587  *
 588  * Typical work flow:
 589  *
 590  * IF NOT i40e_ptype_lookup[ptype].known
 591  * THEN
 592  *      Packet is unknown
 593  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 594  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 595  * ELSE
 596  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 597  * ENDIF
 598  */
 599
 600 /* macro to make the table lines short */
 601 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 602         {       PTYPE, \
 603                 1, \
 604                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 605                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 606                 I40E_RX_PTYPE_##OUTER_FRAG, \
 607                 I40E_RX_PTYPE_TUNNEL_##T, \
 608                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 609                 I40E_RX_PTYPE_##TEF, \
 610                 I40E_RX_PTYPE_INNER_PROT_##I, \
 611                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 612
 613 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 614                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 615
 616 /* shorter macros makes the table fit but are terse */
 617 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 618 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 619 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 620
 621 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 622 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 623         /* L2 Packet types */
 624         I40E_PTT_UNUSED_ENTRY(0),
 625         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 626         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 627         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 628         I40E_PTT_UNUSED_ENTRY(4),
 629         I40E_PTT_UNUSED_ENTRY(5),
 630         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 631         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 632         I40E_PTT_UNUSED_ENTRY(8),
 633         I40E_PTT_UNUSED_ENTRY(9),
 634         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 635         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 636         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 637         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 638         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 639         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 640         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 641         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 642         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 643         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 644         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 645         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 646
 647         /* Non Tunneled IPv4 */
 648         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 649         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 650         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 651         I40E_PTT_UNUSED_ENTRY(25),
 652         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 653         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 654         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 655
 656         /* IPv4 --> IPv4 */
 657         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 658         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 659         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 660         I40E_PTT_UNUSED_ENTRY(32),
 661         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 662         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 663         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 664
 665         /* IPv4 --> IPv6 */
 666         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 667         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 668         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 669         I40E_PTT_UNUSED_ENTRY(39),
 670         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 671         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 672         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 673
 674         /* IPv4 --> GRE/NAT */
 675         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 676
 677         /* IPv4 --> GRE/NAT --> IPv4 */
 678         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 679         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 680         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 681         I40E_PTT_UNUSED_ENTRY(47),
 682         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 683         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 684         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 685
 686         /* IPv4 --> GRE/NAT --> IPv6 */
 687         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 688         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 689         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 690         I40E_PTT_UNUSED_ENTRY(54),
 691         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 692         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 693         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 694
 695         /* IPv4 --> GRE/NAT --> MAC */
 696         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 697
 698         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 699         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 700         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 701         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 702         I40E_PTT_UNUSED_ENTRY(62),
 703         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 704         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 705         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 706
 707         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 708         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 709         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 710         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 711         I40E_PTT_UNUSED_ENTRY(69),
 712         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 713         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 714         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 715
 716         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 717         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 718
 719         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 720         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 721         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 722         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 723         I40E_PTT_UNUSED_ENTRY(77),
 724         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 725         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 726         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 727
 728         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 729         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 730         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 731         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 732         I40E_PTT_UNUSED_ENTRY(84),
 733         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 734         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 735         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 736
 737         /* Non Tunneled IPv6 */
 738         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 739         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 740         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
 741         I40E_PTT_UNUSED_ENTRY(91),
 742         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 743         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 744         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 745
 746         /* IPv6 --> IPv4 */
 747         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 748         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 749         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 750         I40E_PTT_UNUSED_ENTRY(98),
 751         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 752         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 753         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 754
 755         /* IPv6 --> IPv6 */
 756         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 757         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 758         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 759         I40E_PTT_UNUSED_ENTRY(105),
 760         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 761         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 762         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 763
 764         /* IPv6 --> GRE/NAT */
 765         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 766
 767         /* IPv6 --> GRE/NAT -> IPv4 */
 768         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 769         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 770         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 771         I40E_PTT_UNUSED_ENTRY(113),
 772         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 773         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 774         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 775
 776         /* IPv6 --> GRE/NAT -> IPv6 */
 777         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 778         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 779         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 780         I40E_PTT_UNUSED_ENTRY(120),
 781         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 782         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 783         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 784
 785         /* IPv6 --> GRE/NAT -> MAC */
 786         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 787
 788         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 789         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 790         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 791         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 792         I40E_PTT_UNUSED_ENTRY(128),
 793         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 794         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 795         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 796
 797         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 798         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 799         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 800         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 801         I40E_PTT_UNUSED_ENTRY(135),
 802         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 803         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 804         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 805
 806         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 807         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 808
 809         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 810         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 811         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 812         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 813         I40E_PTT_UNUSED_ENTRY(143),
 814         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 815         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 816         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 817
 818         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 819         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 820         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 821         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 822         I40E_PTT_UNUSED_ENTRY(150),
 823         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 824         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 825         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 826
 827         /* unused entries */
 828         I40E_PTT_UNUSED_ENTRY(154),
 829         I40E_PTT_UNUSED_ENTRY(155),
 830         I40E_PTT_UNUSED_ENTRY(156),
 831         I40E_PTT_UNUSED_ENTRY(157),
 832         I40E_PTT_UNUSED_ENTRY(158),
 833         I40E_PTT_UNUSED_ENTRY(159),
 834
 835         I40E_PTT_UNUSED_ENTRY(160),
 836         I40E_PTT_UNUSED_ENTRY(161),
 837         I40E_PTT_UNUSED_ENTRY(162),
 838         I40E_PTT_UNUSED_ENTRY(163),
 839         I40E_PTT_UNUSED_ENTRY(164),
 840         I40E_PTT_UNUSED_ENTRY(165),
 841         I40E_PTT_UNUSED_ENTRY(166),
 842         I40E_PTT_UNUSED_ENTRY(167),
 843         I40E_PTT_UNUSED_ENTRY(168),
 844         I40E_PTT_UNUSED_ENTRY(169),
 845
 846         I40E_PTT_UNUSED_ENTRY(170),
 847         I40E_PTT_UNUSED_ENTRY(171),
 848         I40E_PTT_UNUSED_ENTRY(172),
 849         I40E_PTT_UNUSED_ENTRY(173),
 850         I40E_PTT_UNUSED_ENTRY(174),
 851         I40E_PTT_UNUSED_ENTRY(175),
 852         I40E_PTT_UNUSED_ENTRY(176),
 853         I40E_PTT_UNUSED_ENTRY(177),
 854         I40E_PTT_UNUSED_ENTRY(178),
 855         I40E_PTT_UNUSED_ENTRY(179),
 856
 857         I40E_PTT_UNUSED_ENTRY(180),
 858         I40E_PTT_UNUSED_ENTRY(181),
 859         I40E_PTT_UNUSED_ENTRY(182),
 860         I40E_PTT_UNUSED_ENTRY(183),
 861         I40E_PTT_UNUSED_ENTRY(184),
 862         I40E_PTT_UNUSED_ENTRY(185),
 863         I40E_PTT_UNUSED_ENTRY(186),
 864         I40E_PTT_UNUSED_ENTRY(187),
 865         I40E_PTT_UNUSED_ENTRY(188),
 866         I40E_PTT_UNUSED_ENTRY(189),
 867
 868         I40E_PTT_UNUSED_ENTRY(190),
 869         I40E_PTT_UNUSED_ENTRY(191),
 870         I40E_PTT_UNUSED_ENTRY(192),
 871         I40E_PTT_UNUSED_ENTRY(193),
 872         I40E_PTT_UNUSED_ENTRY(194),
 873         I40E_PTT_UNUSED_ENTRY(195),
 874         I40E_PTT_UNUSED_ENTRY(196),
 875         I40E_PTT_UNUSED_ENTRY(197),
 876         I40E_PTT_UNUSED_ENTRY(198),
 877         I40E_PTT_UNUSED_ENTRY(199),
 878
 879         I40E_PTT_UNUSED_ENTRY(200),
 880         I40E_PTT_UNUSED_ENTRY(201),
 881         I40E_PTT_UNUSED_ENTRY(202),
 882         I40E_PTT_UNUSED_ENTRY(203),
 883         I40E_PTT_UNUSED_ENTRY(204),
 884         I40E_PTT_UNUSED_ENTRY(205),
 885         I40E_PTT_UNUSED_ENTRY(206),
 886         I40E_PTT_UNUSED_ENTRY(207),
 887         I40E_PTT_UNUSED_ENTRY(208),
 888         I40E_PTT_UNUSED_ENTRY(209),
 889
 890         I40E_PTT_UNUSED_ENTRY(210),
 891         I40E_PTT_UNUSED_ENTRY(211),
 892         I40E_PTT_UNUSED_ENTRY(212),
 893         I40E_PTT_UNUSED_ENTRY(213),
 894         I40E_PTT_UNUSED_ENTRY(214),
 895         I40E_PTT_UNUSED_ENTRY(215),
 896         I40E_PTT_UNUSED_ENTRY(216),
 897         I40E_PTT_UNUSED_ENTRY(217),
 898         I40E_PTT_UNUSED_ENTRY(218),
 899         I40E_PTT_UNUSED_ENTRY(219),
 900
 901         I40E_PTT_UNUSED_ENTRY(220),
 902         I40E_PTT_UNUSED_ENTRY(221),
 903         I40E_PTT_UNUSED_ENTRY(222),
 904         I40E_PTT_UNUSED_ENTRY(223),
 905         I40E_PTT_UNUSED_ENTRY(224),
 906         I40E_PTT_UNUSED_ENTRY(225),
 907         I40E_PTT_UNUSED_ENTRY(226),
 908         I40E_PTT_UNUSED_ENTRY(227),
 909         I40E_PTT_UNUSED_ENTRY(228),
 910         I40E_PTT_UNUSED_ENTRY(229),
 911
 912         I40E_PTT_UNUSED_ENTRY(230),
 913         I40E_PTT_UNUSED_ENTRY(231),
 914         I40E_PTT_UNUSED_ENTRY(232),
 915         I40E_PTT_UNUSED_ENTRY(233),
 916         I40E_PTT_UNUSED_ENTRY(234),
 917         I40E_PTT_UNUSED_ENTRY(235),
 918         I40E_PTT_UNUSED_ENTRY(236),
 919         I40E_PTT_UNUSED_ENTRY(237),
 920         I40E_PTT_UNUSED_ENTRY(238),
 921         I40E_PTT_UNUSED_ENTRY(239),
 922
 923         I40E_PTT_UNUSED_ENTRY(240),
 924         I40E_PTT_UNUSED_ENTRY(241),
 925         I40E_PTT_UNUSED_ENTRY(242),
 926         I40E_PTT_UNUSED_ENTRY(243),
 927         I40E_PTT_UNUSED_ENTRY(244),
 928         I40E_PTT_UNUSED_ENTRY(245),
 929         I40E_PTT_UNUSED_ENTRY(246),
 930         I40E_PTT_UNUSED_ENTRY(247),
 931         I40E_PTT_UNUSED_ENTRY(248),
 932         I40E_PTT_UNUSED_ENTRY(249),
 933
 934         I40E_PTT_UNUSED_ENTRY(250),
 935         I40E_PTT_UNUSED_ENTRY(251),
 936         I40E_PTT_UNUSED_ENTRY(252),
 937         I40E_PTT_UNUSED_ENTRY(253),
 938         I40E_PTT_UNUSED_ENTRY(254),
 939         I40E_PTT_UNUSED_ENTRY(255)
 940 };
 941
 942
 943 /**
 944  * i40e_validate_mac_addr - Validate unicast MAC address
 945  * @mac_addr: pointer to MAC address
 946  *
 947  * Tests a MAC address to ensure it is a valid Individual Address
 948  **/
 949 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
 950 {
 951         enum i40e_status_code status = I40E_SUCCESS;
 952
 953         DEBUGFUNC("i40e_validate_mac_addr");
 954
 955         /* Broadcast addresses ARE multicast addresses
 956          * Make sure it is not a multicast address
 957          * Reject the zero address
 958          */
 959         if (I40E_IS_MULTICAST(mac_addr) ||
 960             (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
 961               mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
 962                 status = I40E_ERR_INVALID_MAC_ADDR;
 963
 964         return status;
 965 }
 966 #ifdef PF_DRIVER
 967
 968 /**
 969  * i40e_init_shared_code - Initialize the shared code
 970  * @hw: pointer to hardware structure
 971  *
 972  * This assigns the MAC type and PHY code and inits the NVM.
 973  * Does not touch the hardware. This function must be called prior to any
 974  * other function in the shared code. The i40e_hw structure should be
 975  * memset to 0 prior to calling this function.  The following fields in
 976  * hw structure should be filled in prior to calling this function:
 977  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
 978  * subsystem_vendor_id, and revision_id
 979  **/
 980 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
 981 {
 982         enum i40e_status_code status = I40E_SUCCESS;
 983         u32 port, ari, func_rid;
 984
 985         DEBUGFUNC("i40e_init_shared_code");
 986
 987         i40e_set_mac_type(hw);
 988
 989         switch (hw->mac.type) {
 990         case I40E_MAC_XL710:
 991         case I40E_MAC_X722:
 992                 break;
 993         default:
 994                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
 995         }
 996
 997         hw->phy.get_link_info = true;
 998
 999         /* Determine port number and PF number*/
1000         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1001                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1002         hw->port = (u8)port;
1003         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1004                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1005         func_rid = rd32(hw, I40E_PF_FUNC_RID);
1006         if (ari)
1007                 hw->pf_id = (u8)(func_rid & 0xff);
1008         else
1009                 hw->pf_id = (u8)(func_rid & 0x7);
1010
1011         if (hw->mac.type == I40E_MAC_X722)
1012                 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE |
1013                              I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK;
1014
1015         status = i40e_init_nvm(hw);
1016         return status;
1017 }
1018
1019 /**
1020  * i40e_aq_mac_address_read - Retrieve the MAC addresses
1021  * @hw: pointer to the hw struct
1022  * @flags: a return indicator of what addresses were added to the addr store
1023  * @addrs: the requestor's mac addr store
1024  * @cmd_details: pointer to command details structure or NULL
1025  **/
1026 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1027                                    u16 *flags,
1028                                    struct i40e_aqc_mac_address_read_data *addrs,
1029                                    struct i40e_asq_cmd_details *cmd_details)
1030 {
1031         struct i40e_aq_desc desc;
1032         struct i40e_aqc_mac_address_read *cmd_data =
1033                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1034         enum i40e_status_code status;
1035
1036         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1037         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1038
1039         status = i40e_asq_send_command(hw, &desc, addrs,
1040                                        sizeof(*addrs), cmd_details);
1041         *flags = LE16_TO_CPU(cmd_data->command_flags);
1042
1043         return status;
1044 }
1045
1046 /**
1047  * i40e_aq_mac_address_write - Change the MAC addresses
1048  * @hw: pointer to the hw struct
1049  * @flags: indicates which MAC to be written
1050  * @mac_addr: address to write
1051  * @cmd_details: pointer to command details structure or NULL
1052  **/
1053 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1054                                     u16 flags, u8 *mac_addr,
1055                                     struct i40e_asq_cmd_details *cmd_details)
1056 {
1057         struct i40e_aq_desc desc;
1058         struct i40e_aqc_mac_address_write *cmd_data =
1059                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1060         enum i40e_status_code status;
1061
1062         i40e_fill_default_direct_cmd_desc(&desc,
1063                                           i40e_aqc_opc_mac_address_write);
1064         cmd_data->command_flags = CPU_TO_LE16(flags);
1065         cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1066         cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1067                                         ((u32)mac_addr[3] << 16) |
1068                                         ((u32)mac_addr[4] << 8) |
1069                                         mac_addr[5]);
1070
1071         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1072
1073         return status;
1074 }
1075
1076 /**
1077  * i40e_get_mac_addr - get MAC address
1078  * @hw: pointer to the HW structure
1079  * @mac_addr: pointer to MAC address
1080  *
1081  * Reads the adapter's MAC address from register
1082  **/
1083 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1084 {
1085         struct i40e_aqc_mac_address_read_data addrs;
1086         enum i40e_status_code status;
1087         u16 flags = 0;
1088
1089         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1090
1091         if (flags & I40E_AQC_LAN_ADDR_VALID)
1092                 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1093                         I40E_NONDMA_TO_NONDMA);
1094
1095         return status;
1096 }
1097
1098 /**
1099  * i40e_get_port_mac_addr - get Port MAC address
1100  * @hw: pointer to the HW structure
1101  * @mac_addr: pointer to Port MAC address
1102  *
1103  * Reads the adapter's Port MAC address
1104  **/
1105 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1106 {
1107         struct i40e_aqc_mac_address_read_data addrs;
1108         enum i40e_status_code status;
1109         u16 flags = 0;
1110
1111         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1112         if (status)
1113                 return status;
1114
1115         if (flags & I40E_AQC_PORT_ADDR_VALID)
1116                 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1117                         I40E_NONDMA_TO_NONDMA);
1118         else
1119                 status = I40E_ERR_INVALID_MAC_ADDR;
1120
1121         return status;
1122 }
1123
1124 /**
1125  * i40e_pre_tx_queue_cfg - pre tx queue configure
1126  * @hw: pointer to the HW structure
1127  * @queue: target pf queue index
1128  * @enable: state change request
1129  *
1130  * Handles hw requirement to indicate intention to enable
1131  * or disable target queue.
1132  **/
1133 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1134 {
1135         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1136         u32 reg_block = 0;
1137         u32 reg_val;
1138
1139         if (abs_queue_idx >= 128) {
1140                 reg_block = abs_queue_idx / 128;
1141                 abs_queue_idx %= 128;
1142         }
1143
1144         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1145         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1146         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1147
1148         if (enable)
1149                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1150         else
1151                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1152
1153         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1154 }
1155
1156 /**
1157  * i40e_get_san_mac_addr - get SAN MAC address
1158  * @hw: pointer to the HW structure
1159  * @mac_addr: pointer to SAN MAC address
1160  *
1161  * Reads the adapter's SAN MAC address from NVM
1162  **/
1163 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1164                                             u8 *mac_addr)
1165 {
1166         struct i40e_aqc_mac_address_read_data addrs;
1167         enum i40e_status_code status;
1168         u16 flags = 0;
1169
1170         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1171         if (status)
1172                 return status;
1173
1174         if (flags & I40E_AQC_SAN_ADDR_VALID)
1175                 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac),
1176                         I40E_NONDMA_TO_NONDMA);
1177         else
1178                 status = I40E_ERR_INVALID_MAC_ADDR;
1179
1180         return status;
1181 }
1182
1183 /**
1184  *  i40e_read_pba_string - Reads part number string from EEPROM
1185  *  @hw: pointer to hardware structure
1186  *  @pba_num: stores the part number string from the EEPROM
1187  *  @pba_num_size: part number string buffer length
1188  *
1189  *  Reads the part number string from the EEPROM.
1190  **/
1191 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1192                                             u32 pba_num_size)
1193 {
1194         enum i40e_status_code status = I40E_SUCCESS;
1195         u16 pba_word = 0;
1196         u16 pba_size = 0;
1197         u16 pba_ptr = 0;
1198         u16 i = 0;
1199
1200         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1201         if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1202                 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1203                 return status;
1204         }
1205
1206         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1207         if (status != I40E_SUCCESS) {
1208                 DEBUGOUT("Failed to read PBA Block pointer.\n");
1209                 return status;
1210         }
1211
1212         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1213         if (status != I40E_SUCCESS) {
1214                 DEBUGOUT("Failed to read PBA Block size.\n");
1215                 return status;
1216         }
1217
1218         /* Subtract one to get PBA word count (PBA Size word is included in
1219          * total size)
1220          */
1221         pba_size--;
1222         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1223                 DEBUGOUT("Buffer to small for PBA data.\n");
1224                 return I40E_ERR_PARAM;
1225         }
1226
1227         for (i = 0; i < pba_size; i++) {
1228                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1229                 if (status != I40E_SUCCESS) {
1230                         DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1231                         return status;
1232                 }
1233
1234                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1235                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1236         }
1237         pba_num[(pba_size * 2)] = '\0';
1238
1239         return status;
1240 }
1241
1242 /**
1243  * i40e_get_media_type - Gets media type
1244  * @hw: pointer to the hardware structure
1245  **/
1246 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1247 {
1248         enum i40e_media_type media;
1249
1250         switch (hw->phy.link_info.phy_type) {
1251         case I40E_PHY_TYPE_10GBASE_SR:
1252         case I40E_PHY_TYPE_10GBASE_LR:
1253         case I40E_PHY_TYPE_1000BASE_SX:
1254         case I40E_PHY_TYPE_1000BASE_LX:
1255         case I40E_PHY_TYPE_40GBASE_SR4:
1256         case I40E_PHY_TYPE_40GBASE_LR4:
1257         case I40E_PHY_TYPE_25GBASE_LR:
1258         case I40E_PHY_TYPE_25GBASE_SR:
1259                 media = I40E_MEDIA_TYPE_FIBER;
1260                 break;
1261         case I40E_PHY_TYPE_100BASE_TX:
1262         case I40E_PHY_TYPE_1000BASE_T:
1263         case I40E_PHY_TYPE_10GBASE_T:
1264                 media = I40E_MEDIA_TYPE_BASET;
1265                 break;
1266         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1267         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1268         case I40E_PHY_TYPE_10GBASE_CR1:
1269         case I40E_PHY_TYPE_40GBASE_CR4:
1270         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1271         case I40E_PHY_TYPE_40GBASE_AOC:
1272         case I40E_PHY_TYPE_10GBASE_AOC:
1273         case I40E_PHY_TYPE_25GBASE_CR:
1274         case I40E_PHY_TYPE_25GBASE_AOC:
1275         case I40E_PHY_TYPE_25GBASE_ACC:
1276                 media = I40E_MEDIA_TYPE_DA;
1277                 break;
1278         case I40E_PHY_TYPE_1000BASE_KX:
1279         case I40E_PHY_TYPE_10GBASE_KX4:
1280         case I40E_PHY_TYPE_10GBASE_KR:
1281         case I40E_PHY_TYPE_40GBASE_KR4:
1282         case I40E_PHY_TYPE_20GBASE_KR2:
1283         case I40E_PHY_TYPE_25GBASE_KR:
1284                 media = I40E_MEDIA_TYPE_BACKPLANE;
1285                 break;
1286         case I40E_PHY_TYPE_SGMII:
1287         case I40E_PHY_TYPE_XAUI:
1288         case I40E_PHY_TYPE_XFI:
1289         case I40E_PHY_TYPE_XLAUI:
1290         case I40E_PHY_TYPE_XLPPI:
1291         default:
1292                 media = I40E_MEDIA_TYPE_UNKNOWN;
1293                 break;
1294         }
1295
1296         return media;
1297 }
1298
1299 #define I40E_PF_RESET_WAIT_COUNT        200
1300 /**
1301  * i40e_pf_reset - Reset the PF
1302  * @hw: pointer to the hardware structure
1303  *
1304  * Assuming someone else has triggered a global reset,
1305  * assure the global reset is complete and then reset the PF
1306  **/
1307 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1308 {
1309         u32 cnt = 0;
1310         u32 cnt1 = 0;
1311         u32 reg = 0;
1312         u32 grst_del;
1313
1314         /* Poll for Global Reset steady state in case of recent GRST.
1315          * The grst delay value is in 100ms units, and we'll wait a
1316          * couple counts longer to be sure we don't just miss the end.
1317          */
1318         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1319                         I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1320                         I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1321
1322         grst_del = grst_del * 20;
1323
1324         for (cnt = 0; cnt < grst_del; cnt++) {
1325                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1326                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1327                         break;
1328                 i40e_msec_delay(100);
1329         }
1330         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1331                 DEBUGOUT("Global reset polling failed to complete.\n");
1332                 return I40E_ERR_RESET_FAILED;
1333         }
1334
1335         /* Now Wait for the FW to be ready */
1336         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1337                 reg = rd32(hw, I40E_GLNVM_ULD);
1338                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1339                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1340                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1341                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1342                         DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1343                         break;
1344                 }
1345                 i40e_msec_delay(10);
1346         }
1347         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1348                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1349                 DEBUGOUT("wait for FW Reset complete timedout\n");
1350                 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1351                 return I40E_ERR_RESET_FAILED;
1352         }
1353
1354         /* If there was a Global Reset in progress when we got here,
1355          * we don't need to do the PF Reset
1356          */
1357         if (!cnt) {
1358                 u32 reg2 = 0;
1359
1360                 reg = rd32(hw, I40E_PFGEN_CTRL);
1361                 wr32(hw, I40E_PFGEN_CTRL,
1362                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1363                 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1364                         reg = rd32(hw, I40E_PFGEN_CTRL);
1365                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1366                                 break;
1367                         reg2 = rd32(hw, I40E_GLGEN_RSTAT);
1368                         if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1369                                 DEBUGOUT("Core reset upcoming. Skipping PF reset request.\n");
1370                                 DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg2);
1371                                 return I40E_ERR_NOT_READY;
1372                         }
1373                         i40e_msec_delay(1);
1374                 }
1375                 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1376                         DEBUGOUT("PF reset polling failed to complete.\n");
1377                         return I40E_ERR_RESET_FAILED;
1378                 }
1379         }
1380
1381         i40e_clear_pxe_mode(hw);
1382
1383
1384         return I40E_SUCCESS;
1385 }
1386
1387 /**
1388  * i40e_clear_hw - clear out any left over hw state
1389  * @hw: pointer to the hw struct
1390  *
1391  * Clear queues and interrupts, typically called at init time,
1392  * but after the capabilities have been found so we know how many
1393  * queues and msix vectors have been allocated.
1394  **/
1395 void i40e_clear_hw(struct i40e_hw *hw)
1396 {
1397         u32 num_queues, base_queue;
1398         u32 num_pf_int;
1399         u32 num_vf_int;
1400         u32 num_vfs;
1401         u32 i, j;
1402         u32 val;
1403         u32 eol = 0x7ff;
1404
1405         /* get number of interrupts, queues, and vfs */
1406         val = rd32(hw, I40E_GLPCI_CNF2);
1407         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1408                         I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1409         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1410                         I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1411
1412         val = rd32(hw, I40E_PFLAN_QALLOC);
1413         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1414                         I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1415         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1416                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1417         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1418                 num_queues = (j - base_queue) + 1;
1419         else
1420                 num_queues = 0;
1421
1422         val = rd32(hw, I40E_PF_VT_PFALLOC);
1423         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1424                         I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1425         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1426                         I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1427         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1428                 num_vfs = (j - i) + 1;
1429         else
1430                 num_vfs = 0;
1431
1432         /* stop all the interrupts */
1433         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1434         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1435         for (i = 0; i < num_pf_int - 2; i++)
1436                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1437
1438         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1439         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1440         wr32(hw, I40E_PFINT_LNKLST0, val);
1441         for (i = 0; i < num_pf_int - 2; i++)
1442                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1443         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1444         for (i = 0; i < num_vfs; i++)
1445                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1446         for (i = 0; i < num_vf_int - 2; i++)
1447                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1448
1449         /* warn the HW of the coming Tx disables */
1450         for (i = 0; i < num_queues; i++) {
1451                 u32 abs_queue_idx = base_queue + i;
1452                 u32 reg_block = 0;
1453
1454                 if (abs_queue_idx >= 128) {
1455                         reg_block = abs_queue_idx / 128;
1456                         abs_queue_idx %= 128;
1457                 }
1458
1459                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1460                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1461                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1462                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1463
1464                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1465         }
1466         i40e_usec_delay(400);
1467
1468         /* stop all the queues */
1469         for (i = 0; i < num_queues; i++) {
1470                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1471                 wr32(hw, I40E_QTX_ENA(i), 0);
1472                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1473                 wr32(hw, I40E_QRX_ENA(i), 0);
1474         }
1475
1476         /* short wait for all queue disables to settle */
1477         i40e_usec_delay(50);
1478 }
1479
1480 /**
1481  * i40e_clear_pxe_mode - clear pxe operations mode
1482  * @hw: pointer to the hw struct
1483  *
1484  * Make sure all PXE mode settings are cleared, including things
1485  * like descriptor fetch/write-back mode.
1486  **/
1487 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1488 {
1489         if (i40e_check_asq_alive(hw))
1490                 i40e_aq_clear_pxe_mode(hw, NULL);
1491 }
1492
1493 /**
1494  * i40e_led_is_mine - helper to find matching led
1495  * @hw: pointer to the hw struct
1496  * @idx: index into GPIO registers
1497  *
1498  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1499  */
1500 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1501 {
1502         u32 gpio_val = 0;
1503         u32 port;
1504
1505         if (!hw->func_caps.led[idx])
1506                 return 0;
1507
1508         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1509         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1510                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1511
1512         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1513          * if it is not our port then ignore
1514          */
1515         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1516             (port != hw->port))
1517                 return 0;
1518
1519         return gpio_val;
1520 }
1521
1522 #define I40E_COMBINED_ACTIVITY 0xA
1523 #define I40E_FILTER_ACTIVITY 0xE
1524 #define I40E_LINK_ACTIVITY 0xC
1525 #define I40E_MAC_ACTIVITY 0xD
1526 #define I40E_LED0 22
1527
1528 /**
1529  * i40e_led_get - return current on/off mode
1530  * @hw: pointer to the hw struct
1531  *
1532  * The value returned is the 'mode' field as defined in the
1533  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1534  * values are variations of possible behaviors relating to
1535  * blink, link, and wire.
1536  **/
1537 u32 i40e_led_get(struct i40e_hw *hw)
1538 {
1539         u32 current_mode = 0;
1540         u32 mode = 0;
1541         int i;
1542
1543         /* as per the documentation GPIO 22-29 are the LED
1544          * GPIO pins named LED0..LED7
1545          */
1546         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1547                 u32 gpio_val = i40e_led_is_mine(hw, i);
1548
1549                 if (!gpio_val)
1550                         continue;
1551
1552                 /* ignore gpio LED src mode entries related to the activity
1553                  *  LEDs
1554                  */
1555                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1556                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1557                 switch (current_mode) {
1558                 case I40E_COMBINED_ACTIVITY:
1559                 case I40E_FILTER_ACTIVITY:
1560                 case I40E_MAC_ACTIVITY:
1561                 case I40E_LINK_ACTIVITY:
1562                         continue;
1563                 default:
1564                         break;
1565                 }
1566
1567                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1568                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1569                 break;
1570         }
1571
1572         return mode;
1573 }
1574
1575 /**
1576  * i40e_led_set - set new on/off mode
1577  * @hw: pointer to the hw struct
1578  * @mode: 0=off, 0xf=on (else see manual for mode details)
1579  * @blink: true if the LED should blink when on, false if steady
1580  *
1581  * if this function is used to turn on the blink it should
1582  * be used to disable the blink when restoring the original state.
1583  **/
1584 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1585 {
1586         u32 current_mode = 0;
1587         int i;
1588
1589         if (mode & 0xfffffff0)
1590                 DEBUGOUT1("invalid mode passed in %X\n", mode);
1591
1592         /* as per the documentation GPIO 22-29 are the LED
1593          * GPIO pins named LED0..LED7
1594          */
1595         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1596                 u32 gpio_val = i40e_led_is_mine(hw, i);
1597
1598                 if (!gpio_val)
1599                         continue;
1600
1601                 /* ignore gpio LED src mode entries related to the activity
1602                  * LEDs
1603                  */
1604                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1605                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1606                 switch (current_mode) {
1607                 case I40E_COMBINED_ACTIVITY:
1608                 case I40E_FILTER_ACTIVITY:
1609                 case I40E_MAC_ACTIVITY:
1610                 case I40E_LINK_ACTIVITY:
1611                         continue;
1612                 default:
1613                         break;
1614                 }
1615
1616                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1617                 /* this & is a bit of paranoia, but serves as a range check */
1618                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1619                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1620
1621                 if (blink)
1622                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1623                 else
1624                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1625
1626                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1627                 break;
1628         }
1629 }
1630
1631 /* Admin command wrappers */
1632
1633 /**
1634  * i40e_aq_get_phy_capabilities
1635  * @hw: pointer to the hw struct
1636  * @abilities: structure for PHY capabilities to be filled
1637  * @qualified_modules: report Qualified Modules
1638  * @report_init: report init capabilities (active are default)
1639  * @cmd_details: pointer to command details structure or NULL
1640  *
1641  * Returns the various PHY abilities supported on the Port.
1642  **/
1643 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1644                         bool qualified_modules, bool report_init,
1645                         struct i40e_aq_get_phy_abilities_resp *abilities,
1646                         struct i40e_asq_cmd_details *cmd_details)
1647 {
1648         struct i40e_aq_desc desc;
1649         enum i40e_status_code status;
1650         u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0;
1651         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1652
1653         if (!abilities)
1654                 return I40E_ERR_PARAM;
1655
1656         do {
1657                 i40e_fill_default_direct_cmd_desc(&desc,
1658                                                i40e_aqc_opc_get_phy_abilities);
1659
1660                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1661                 if (abilities_size > I40E_AQ_LARGE_BUF)
1662                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1663
1664                 if (qualified_modules)
1665                         desc.params.external.param0 |=
1666                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1667
1668                 if (report_init)
1669                         desc.params.external.param0 |=
1670                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1671
1672                 status = i40e_asq_send_command(hw, &desc, abilities,
1673                                                abilities_size, cmd_details);
1674
1675                 if (status != I40E_SUCCESS)
1676                         break;
1677
1678                 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) {
1679                         status = I40E_ERR_UNKNOWN_PHY;
1680                         break;
1681                 } else if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) {
1682                         i40e_msec_delay(1);
1683                         total_delay++;
1684                         status = I40E_ERR_TIMEOUT;
1685                 }
1686         } while ((hw->aq.asq_last_status != I40E_AQ_RC_OK) &&
1687                  (total_delay < max_delay));
1688
1689         if (status != I40E_SUCCESS)
1690                 return status;
1691
1692         if (report_init) {
1693                 if (hw->mac.type ==  I40E_MAC_XL710 &&
1694                     hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1695                     hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
1696                         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1697                 } else {
1698                         hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1699                         hw->phy.phy_types |=
1700                                         ((u64)abilities->phy_type_ext << 32);
1701                 }
1702         }
1703
1704         return status;
1705 }
1706
1707 /**
1708  * i40e_aq_set_phy_config
1709  * @hw: pointer to the hw struct
1710  * @config: structure with PHY configuration to be set
1711  * @cmd_details: pointer to command details structure or NULL
1712  *
1713  * Set the various PHY configuration parameters
1714  * supported on the Port.One or more of the Set PHY config parameters may be
1715  * ignored in an MFP mode as the PF may not have the privilege to set some
1716  * of the PHY Config parameters. This status will be indicated by the
1717  * command response.
1718  **/
1719 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1720                                 struct i40e_aq_set_phy_config *config,
1721                                 struct i40e_asq_cmd_details *cmd_details)
1722 {
1723         struct i40e_aq_desc desc;
1724         struct i40e_aq_set_phy_config *cmd =
1725                 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1726         enum i40e_status_code status;
1727
1728         if (!config)
1729                 return I40E_ERR_PARAM;
1730
1731         i40e_fill_default_direct_cmd_desc(&desc,
1732                                           i40e_aqc_opc_set_phy_config);
1733
1734         *cmd = *config;
1735
1736         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1737
1738         return status;
1739 }
1740
1741 /**
1742  * i40e_set_fc
1743  * @hw: pointer to the hw struct
1744  * @aq_failures: buffer to return AdminQ failure information
1745  * @atomic_restart: whether to enable atomic link restart
1746  *
1747  * Set the requested flow control mode using set_phy_config.
1748  **/
1749 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1750                                   bool atomic_restart)
1751 {
1752         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1753         struct i40e_aq_get_phy_abilities_resp abilities;
1754         struct i40e_aq_set_phy_config config;
1755         enum i40e_status_code status;
1756         u8 pause_mask = 0x0;
1757
1758         *aq_failures = 0x0;
1759
1760         switch (fc_mode) {
1761         case I40E_FC_FULL:
1762                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1763                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1764                 break;
1765         case I40E_FC_RX_PAUSE:
1766                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1767                 break;
1768         case I40E_FC_TX_PAUSE:
1769                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1770                 break;
1771         default:
1772                 break;
1773         }
1774
1775         /* Get the current phy config */
1776         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1777                                               NULL);
1778         if (status) {
1779                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1780                 return status;
1781         }
1782
1783         memset(&config, 0, sizeof(config));
1784         /* clear the old pause settings */
1785         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1786                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1787         /* set the new abilities */
1788         config.abilities |= pause_mask;
1789         /* If the abilities have changed, then set the new config */
1790         if (config.abilities != abilities.abilities) {
1791                 /* Auto restart link so settings take effect */
1792                 if (atomic_restart)
1793                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1794                 /* Copy over all the old settings */
1795                 config.phy_type = abilities.phy_type;
1796                 config.phy_type_ext = abilities.phy_type_ext;
1797                 config.link_speed = abilities.link_speed;
1798                 config.eee_capability = abilities.eee_capability;
1799                 config.eeer = abilities.eeer_val;
1800                 config.low_power_ctrl = abilities.d3_lpan;
1801                 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1802                                     I40E_AQ_PHY_FEC_CONFIG_MASK;
1803                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1804
1805                 if (status)
1806                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1807         }
1808         /* Update the link info */
1809         status = i40e_update_link_info(hw);
1810         if (status) {
1811                 /* Wait a little bit (on 40G cards it sometimes takes a really
1812                  * long time for link to come back from the atomic reset)
1813                  * and try once more
1814                  */
1815                 i40e_msec_delay(1000);
1816                 status = i40e_update_link_info(hw);
1817         }
1818         if (status)
1819                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1820
1821         return status;
1822 }
1823
1824 /**
1825  * i40e_aq_set_mac_config
1826  * @hw: pointer to the hw struct
1827  * @max_frame_size: Maximum Frame Size to be supported by the port
1828  * @crc_en: Tell HW to append a CRC to outgoing frames
1829  * @pacing: Pacing configurations
1830  * @cmd_details: pointer to command details structure or NULL
1831  *
1832  * Configure MAC settings for frame size, jumbo frame support and the
1833  * addition of a CRC by the hardware.
1834  **/
1835 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1836                                 u16 max_frame_size,
1837                                 bool crc_en, u16 pacing,
1838                                 struct i40e_asq_cmd_details *cmd_details)
1839 {
1840         struct i40e_aq_desc desc;
1841         struct i40e_aq_set_mac_config *cmd =
1842                 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1843         enum i40e_status_code status;
1844
1845         if (max_frame_size == 0)
1846                 return I40E_ERR_PARAM;
1847
1848         i40e_fill_default_direct_cmd_desc(&desc,
1849                                           i40e_aqc_opc_set_mac_config);
1850
1851         cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1852         cmd->params = ((u8)pacing & 0x0F) << 3;
1853         if (crc_en)
1854                 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1855
1856         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1857
1858         return status;
1859 }
1860
1861 /**
1862  * i40e_aq_clear_pxe_mode
1863  * @hw: pointer to the hw struct
1864  * @cmd_details: pointer to command details structure or NULL
1865  *
1866  * Tell the firmware that the driver is taking over from PXE
1867  **/
1868 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1869                         struct i40e_asq_cmd_details *cmd_details)
1870 {
1871         enum i40e_status_code status;
1872         struct i40e_aq_desc desc;
1873         struct i40e_aqc_clear_pxe *cmd =
1874                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1875
1876         i40e_fill_default_direct_cmd_desc(&desc,
1877                                           i40e_aqc_opc_clear_pxe_mode);
1878
1879         cmd->rx_cnt = 0x2;
1880
1881         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1882
1883         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1884
1885         return status;
1886 }
1887
1888 /**
1889  * i40e_aq_set_link_restart_an
1890  * @hw: pointer to the hw struct
1891  * @enable_link: if true: enable link, if false: disable link
1892  * @cmd_details: pointer to command details structure or NULL
1893  *
1894  * Sets up the link and restarts the Auto-Negotiation over the link.
1895  **/
1896 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1897                 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1898 {
1899         struct i40e_aq_desc desc;
1900         struct i40e_aqc_set_link_restart_an *cmd =
1901                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1902         enum i40e_status_code status;
1903
1904         i40e_fill_default_direct_cmd_desc(&desc,
1905                                           i40e_aqc_opc_set_link_restart_an);
1906
1907         cmd->command = I40E_AQ_PHY_RESTART_AN;
1908         if (enable_link)
1909                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1910         else
1911                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1912
1913         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1914
1915         return status;
1916 }
1917
1918 /**
1919  * i40e_aq_get_link_info
1920  * @hw: pointer to the hw struct
1921  * @enable_lse: enable/disable LinkStatusEvent reporting
1922  * @link: pointer to link status structure - optional
1923  * @cmd_details: pointer to command details structure or NULL
1924  *
1925  * Returns the link status of the adapter.
1926  **/
1927 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1928                                 bool enable_lse, struct i40e_link_status *link,
1929                                 struct i40e_asq_cmd_details *cmd_details)
1930 {
1931         struct i40e_aq_desc desc;
1932         struct i40e_aqc_get_link_status *resp =
1933                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1934         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1935         enum i40e_status_code status;
1936         bool tx_pause, rx_pause;
1937         u16 command_flags;
1938
1939         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1940
1941         if (enable_lse)
1942                 command_flags = I40E_AQ_LSE_ENABLE;
1943         else
1944                 command_flags = I40E_AQ_LSE_DISABLE;
1945         resp->command_flags = CPU_TO_LE16(command_flags);
1946
1947         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1948
1949         if (status != I40E_SUCCESS)
1950                 goto aq_get_link_info_exit;
1951
1952         /* save off old link status information */
1953         i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1954                     sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1955
1956         /* update link status */
1957         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1958         hw->phy.media_type = i40e_get_media_type(hw);
1959         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1960         hw_link_info->link_info = resp->link_info;
1961         hw_link_info->an_info = resp->an_info;
1962         hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
1963                                                  I40E_AQ_CONFIG_FEC_RS_ENA);
1964         hw_link_info->ext_info = resp->ext_info;
1965         hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
1966         hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1967         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1968
1969         /* update fc info */
1970         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1971         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1972         if (tx_pause & rx_pause)
1973                 hw->fc.current_mode = I40E_FC_FULL;
1974         else if (tx_pause)
1975                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1976         else if (rx_pause)
1977                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1978         else
1979                 hw->fc.current_mode = I40E_FC_NONE;
1980
1981         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1982                 hw_link_info->crc_enable = true;
1983         else
1984                 hw_link_info->crc_enable = false;
1985
1986         if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
1987                 hw_link_info->lse_enable = true;
1988         else
1989                 hw_link_info->lse_enable = false;
1990
1991         if ((hw->mac.type == I40E_MAC_XL710) &&
1992             (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1993              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1994                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1995
1996         if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1997             hw->aq.api_min_ver >= 7) {
1998                 __le32 tmp;
1999
2000                 i40e_memcpy(&tmp, resp->link_type, sizeof(tmp),
2001                             I40E_NONDMA_TO_NONDMA);
2002                 hw->phy.phy_types = LE32_TO_CPU(tmp);
2003                 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
2004         }
2005
2006         /* save link status information */
2007         if (link)
2008                 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
2009                             I40E_NONDMA_TO_NONDMA);
2010
2011         /* flag cleared so helper functions don't call AQ again */
2012         hw->phy.get_link_info = false;
2013
2014 aq_get_link_info_exit:
2015         return status;
2016 }
2017
2018 /**
2019  * i40e_aq_set_phy_int_mask
2020  * @hw: pointer to the hw struct
2021  * @mask: interrupt mask to be set
2022  * @cmd_details: pointer to command details structure or NULL
2023  *
2024  * Set link interrupt mask.
2025  **/
2026 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2027                                 u16 mask,
2028                                 struct i40e_asq_cmd_details *cmd_details)
2029 {
2030         struct i40e_aq_desc desc;
2031         struct i40e_aqc_set_phy_int_mask *cmd =
2032                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2033         enum i40e_status_code status;
2034
2035         i40e_fill_default_direct_cmd_desc(&desc,
2036                                           i40e_aqc_opc_set_phy_int_mask);
2037
2038         cmd->event_mask = CPU_TO_LE16(mask);
2039
2040         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2041
2042         return status;
2043 }
2044
2045 /**
2046  * i40e_aq_get_local_advt_reg
2047  * @hw: pointer to the hw struct
2048  * @advt_reg: local AN advertisement register value
2049  * @cmd_details: pointer to command details structure or NULL
2050  *
2051  * Get the Local AN advertisement register value.
2052  **/
2053 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2054                                 u64 *advt_reg,
2055                                 struct i40e_asq_cmd_details *cmd_details)
2056 {
2057         struct i40e_aq_desc desc;
2058         struct i40e_aqc_an_advt_reg *resp =
2059                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2060         enum i40e_status_code status;
2061
2062         i40e_fill_default_direct_cmd_desc(&desc,
2063                                           i40e_aqc_opc_get_local_advt_reg);
2064
2065         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2066
2067         if (status != I40E_SUCCESS)
2068                 goto aq_get_local_advt_reg_exit;
2069
2070         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2071         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2072
2073 aq_get_local_advt_reg_exit:
2074         return status;
2075 }
2076
2077 /**
2078  * i40e_aq_set_local_advt_reg
2079  * @hw: pointer to the hw struct
2080  * @advt_reg: local AN advertisement register value
2081  * @cmd_details: pointer to command details structure or NULL
2082  *
2083  * Get the Local AN advertisement register value.
2084  **/
2085 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2086                                 u64 advt_reg,
2087                                 struct i40e_asq_cmd_details *cmd_details)
2088 {
2089         struct i40e_aq_desc desc;
2090         struct i40e_aqc_an_advt_reg *cmd =
2091                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2092         enum i40e_status_code status;
2093
2094         i40e_fill_default_direct_cmd_desc(&desc,
2095                                           i40e_aqc_opc_get_local_advt_reg);
2096
2097         cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2098         cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2099
2100         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2101
2102         return status;
2103 }
2104
2105 /**
2106  * i40e_aq_get_partner_advt
2107  * @hw: pointer to the hw struct
2108  * @advt_reg: AN partner advertisement register value
2109  * @cmd_details: pointer to command details structure or NULL
2110  *
2111  * Get the link partner AN advertisement register value.
2112  **/
2113 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2114                                 u64 *advt_reg,
2115                                 struct i40e_asq_cmd_details *cmd_details)
2116 {
2117         struct i40e_aq_desc desc;
2118         struct i40e_aqc_an_advt_reg *resp =
2119                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2120         enum i40e_status_code status;
2121
2122         i40e_fill_default_direct_cmd_desc(&desc,
2123                                           i40e_aqc_opc_get_partner_advt);
2124
2125         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2126
2127         if (status != I40E_SUCCESS)
2128                 goto aq_get_partner_advt_exit;
2129
2130         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2131         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2132
2133 aq_get_partner_advt_exit:
2134         return status;
2135 }
2136
2137 /**
2138  * i40e_aq_set_lb_modes
2139  * @hw: pointer to the hw struct
2140  * @lb_modes: loopback mode to be set
2141  * @cmd_details: pointer to command details structure or NULL
2142  *
2143  * Sets loopback modes.
2144  **/
2145 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2146                                 u16 lb_modes,
2147                                 struct i40e_asq_cmd_details *cmd_details)
2148 {
2149         struct i40e_aq_desc desc;
2150         struct i40e_aqc_set_lb_mode *cmd =
2151                 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2152         enum i40e_status_code status;
2153
2154         i40e_fill_default_direct_cmd_desc(&desc,
2155                                           i40e_aqc_opc_set_lb_modes);
2156
2157         cmd->lb_mode = CPU_TO_LE16(lb_modes);
2158
2159         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2160
2161         return status;
2162 }
2163
2164 /**
2165  * i40e_aq_set_phy_debug
2166  * @hw: pointer to the hw struct
2167  * @cmd_flags: debug command flags
2168  * @cmd_details: pointer to command details structure or NULL
2169  *
2170  * Reset the external PHY.
2171  **/
2172 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2173                                 struct i40e_asq_cmd_details *cmd_details)
2174 {
2175         struct i40e_aq_desc desc;
2176         struct i40e_aqc_set_phy_debug *cmd =
2177                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2178         enum i40e_status_code status;
2179
2180         i40e_fill_default_direct_cmd_desc(&desc,
2181                                           i40e_aqc_opc_set_phy_debug);
2182
2183         cmd->command_flags = cmd_flags;
2184
2185         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2186
2187         return status;
2188 }
2189
2190 /**
2191  * i40e_aq_add_vsi
2192  * @hw: pointer to the hw struct
2193  * @vsi_ctx: pointer to a vsi context struct
2194  * @cmd_details: pointer to command details structure or NULL
2195  *
2196  * Add a VSI context to the hardware.
2197 **/
2198 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2199                                 struct i40e_vsi_context *vsi_ctx,
2200                                 struct i40e_asq_cmd_details *cmd_details)
2201 {
2202         struct i40e_aq_desc desc;
2203         struct i40e_aqc_add_get_update_vsi *cmd =
2204                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2205         struct i40e_aqc_add_get_update_vsi_completion *resp =
2206                 (struct i40e_aqc_add_get_update_vsi_completion *)
2207                 &desc.params.raw;
2208         enum i40e_status_code status;
2209
2210         i40e_fill_default_direct_cmd_desc(&desc,
2211                                           i40e_aqc_opc_add_vsi);
2212
2213         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2214         cmd->connection_type = vsi_ctx->connection_type;
2215         cmd->vf_id = vsi_ctx->vf_num;
2216         cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2217
2218         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2219
2220         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2221                                     sizeof(vsi_ctx->info), cmd_details);
2222
2223         if (status != I40E_SUCCESS)
2224                 goto aq_add_vsi_exit;
2225
2226         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2227         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2228         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2229         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2230
2231 aq_add_vsi_exit:
2232         return status;
2233 }
2234
2235 /**
2236  * i40e_aq_set_default_vsi
2237  * @hw: pointer to the hw struct
2238  * @seid: vsi number
2239  * @cmd_details: pointer to command details structure or NULL
2240  **/
2241 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2242                                 u16 seid,
2243                                 struct i40e_asq_cmd_details *cmd_details)
2244 {
2245         struct i40e_aq_desc desc;
2246         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2247                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2248                 &desc.params.raw;
2249         enum i40e_status_code status;
2250
2251         i40e_fill_default_direct_cmd_desc(&desc,
2252                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2253
2254         cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2255         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2256         cmd->seid = CPU_TO_LE16(seid);
2257
2258         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2259
2260         return status;
2261 }
2262
2263 /**
2264  * i40e_aq_clear_default_vsi
2265  * @hw: pointer to the hw struct
2266  * @seid: vsi number
2267  * @cmd_details: pointer to command details structure or NULL
2268  **/
2269 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2270                                 u16 seid,
2271                                 struct i40e_asq_cmd_details *cmd_details)
2272 {
2273         struct i40e_aq_desc desc;
2274         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2275                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2276                 &desc.params.raw;
2277         enum i40e_status_code status;
2278
2279         i40e_fill_default_direct_cmd_desc(&desc,
2280                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2281
2282         cmd->promiscuous_flags = CPU_TO_LE16(0);
2283         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2284         cmd->seid = CPU_TO_LE16(seid);
2285
2286         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2287
2288         return status;
2289 }
2290
2291 /**
2292  * i40e_aq_set_vsi_unicast_promiscuous
2293  * @hw: pointer to the hw struct
2294  * @seid: vsi number
2295  * @set: set unicast promiscuous enable/disable
2296  * @cmd_details: pointer to command details structure or NULL
2297  * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2298  **/
2299 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2300                                 u16 seid, bool set,
2301                                 struct i40e_asq_cmd_details *cmd_details,
2302                                 bool rx_only_promisc)
2303 {
2304         struct i40e_aq_desc desc;
2305         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2306                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2307         enum i40e_status_code status;
2308         u16 flags = 0;
2309
2310         i40e_fill_default_direct_cmd_desc(&desc,
2311                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2312
2313         if (set) {
2314                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2315                 if (rx_only_promisc &&
2316                     (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2317                      (hw->aq.api_maj_ver > 1)))
2318                         flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2319         }
2320
2321         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2322
2323         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2324         if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2325              (hw->aq.api_maj_ver > 1))
2326                 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2327
2328         cmd->seid = CPU_TO_LE16(seid);
2329         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2330
2331         return status;
2332 }
2333
2334 /**
2335  * i40e_aq_set_vsi_multicast_promiscuous
2336  * @hw: pointer to the hw struct
2337  * @seid: vsi number
2338  * @set: set multicast promiscuous enable/disable
2339  * @cmd_details: pointer to command details structure or NULL
2340  **/
2341 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2342                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2343 {
2344         struct i40e_aq_desc desc;
2345         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2346                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2347         enum i40e_status_code status;
2348         u16 flags = 0;
2349
2350         i40e_fill_default_direct_cmd_desc(&desc,
2351                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2352
2353         if (set)
2354                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2355
2356         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2357
2358         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2359
2360         cmd->seid = CPU_TO_LE16(seid);
2361         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2362
2363         return status;
2364 }
2365
2366 /**
2367 * i40e_aq_set_vsi_full_promiscuous
2368 * @hw: pointer to the hw struct
2369 * @seid: VSI number
2370 * @set: set promiscuous enable/disable
2371 * @cmd_details: pointer to command details structure or NULL
2372 **/
2373 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw,
2374                                 u16 seid, bool set,
2375                                 struct i40e_asq_cmd_details *cmd_details)
2376 {
2377         struct i40e_aq_desc desc;
2378         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2379                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2380         enum i40e_status_code status;
2381         u16 flags = 0;
2382
2383         i40e_fill_default_direct_cmd_desc(&desc,
2384                 i40e_aqc_opc_set_vsi_promiscuous_modes);
2385
2386         if (set)
2387                 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2388                         I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2389                         I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2390
2391         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2392
2393         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2394                                        I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2395                                        I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2396
2397         cmd->seid = CPU_TO_LE16(seid);
2398         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2399
2400         return status;
2401 }
2402
2403 /**
2404  * i40e_aq_set_vsi_mc_promisc_on_vlan
2405  * @hw: pointer to the hw struct
2406  * @seid: vsi number
2407  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2408  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2409  * @cmd_details: pointer to command details structure or NULL
2410  **/
2411 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2412                                 u16 seid, bool enable, u16 vid,
2413                                 struct i40e_asq_cmd_details *cmd_details)
2414 {
2415         struct i40e_aq_desc desc;
2416         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2417                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2418         enum i40e_status_code status;
2419         u16 flags = 0;
2420
2421         i40e_fill_default_direct_cmd_desc(&desc,
2422                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2423
2424         if (enable)
2425                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2426
2427         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2428         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2429         cmd->seid = CPU_TO_LE16(seid);
2430         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2431
2432         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2433
2434         return status;
2435 }
2436
2437 /**
2438  * i40e_aq_set_vsi_uc_promisc_on_vlan
2439  * @hw: pointer to the hw struct
2440  * @seid: vsi number
2441  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2442  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2443  * @cmd_details: pointer to command details structure or NULL
2444  **/
2445 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2446                                 u16 seid, bool enable, u16 vid,
2447                                 struct i40e_asq_cmd_details *cmd_details)
2448 {
2449         struct i40e_aq_desc desc;
2450         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2451                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2452         enum i40e_status_code status;
2453         u16 flags = 0;
2454
2455         i40e_fill_default_direct_cmd_desc(&desc,
2456                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2457
2458         if (enable)
2459                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2460
2461         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2462         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2463         cmd->seid = CPU_TO_LE16(seid);
2464         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2465
2466         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2467
2468         return status;
2469 }
2470
2471 /**
2472  * i40e_aq_set_vsi_bc_promisc_on_vlan
2473  * @hw: pointer to the hw struct
2474  * @seid: vsi number
2475  * @enable: set broadcast promiscuous enable/disable for a given VLAN
2476  * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2477  * @cmd_details: pointer to command details structure or NULL
2478  **/
2479 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2480                                 u16 seid, bool enable, u16 vid,
2481                                 struct i40e_asq_cmd_details *cmd_details)
2482 {
2483         struct i40e_aq_desc desc;
2484         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2485                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2486         enum i40e_status_code status;
2487         u16 flags = 0;
2488
2489         i40e_fill_default_direct_cmd_desc(&desc,
2490                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2491
2492         if (enable)
2493                 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2494
2495         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2496         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2497         cmd->seid = CPU_TO_LE16(seid);
2498         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2499
2500         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2501
2502         return status;
2503 }
2504
2505 /**
2506  * i40e_aq_set_vsi_broadcast
2507  * @hw: pointer to the hw struct
2508  * @seid: vsi number
2509  * @set_filter: true to set filter, false to clear filter
2510  * @cmd_details: pointer to command details structure or NULL
2511  *
2512  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2513  **/
2514 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2515                                 u16 seid, bool set_filter,
2516                                 struct i40e_asq_cmd_details *cmd_details)
2517 {
2518         struct i40e_aq_desc desc;
2519         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2520                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2521         enum i40e_status_code status;
2522
2523         i40e_fill_default_direct_cmd_desc(&desc,
2524                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2525
2526         if (set_filter)
2527                 cmd->promiscuous_flags
2528                             |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2529         else
2530                 cmd->promiscuous_flags
2531                             &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2532
2533         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2534         cmd->seid = CPU_TO_LE16(seid);
2535         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2536
2537         return status;
2538 }
2539
2540 /**
2541  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2542  * @hw: pointer to the hw struct
2543  * @seid: vsi number
2544  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2545  * @cmd_details: pointer to command details structure or NULL
2546  **/
2547 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2548                                 u16 seid, bool enable,
2549                                 struct i40e_asq_cmd_details *cmd_details)
2550 {
2551         struct i40e_aq_desc desc;
2552         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2553                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2554         enum i40e_status_code status;
2555         u16 flags = 0;
2556
2557         i40e_fill_default_direct_cmd_desc(&desc,
2558                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2559         if (enable)
2560                 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2561
2562         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2563         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2564         cmd->seid = CPU_TO_LE16(seid);
2565
2566         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2567
2568         return status;
2569 }
2570
2571 /**
2572  * i40e_get_vsi_params - get VSI configuration info
2573  * @hw: pointer to the hw struct
2574  * @vsi_ctx: pointer to a vsi context struct
2575  * @cmd_details: pointer to command details structure or NULL
2576  **/
2577 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2578                                 struct i40e_vsi_context *vsi_ctx,
2579                                 struct i40e_asq_cmd_details *cmd_details)
2580 {
2581         struct i40e_aq_desc desc;
2582         struct i40e_aqc_add_get_update_vsi *cmd =
2583                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2584         struct i40e_aqc_add_get_update_vsi_completion *resp =
2585                 (struct i40e_aqc_add_get_update_vsi_completion *)
2586                 &desc.params.raw;
2587         enum i40e_status_code status;
2588
2589         UNREFERENCED_1PARAMETER(cmd_details);
2590         i40e_fill_default_direct_cmd_desc(&desc,
2591                                           i40e_aqc_opc_get_vsi_parameters);
2592
2593         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2594
2595         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2596
2597         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2598                                     sizeof(vsi_ctx->info), NULL);
2599
2600         if (status != I40E_SUCCESS)
2601                 goto aq_get_vsi_params_exit;
2602
2603         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2604         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2605         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2606         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2607
2608 aq_get_vsi_params_exit:
2609         return status;
2610 }
2611
2612 /**
2613  * i40e_aq_update_vsi_params
2614  * @hw: pointer to the hw struct
2615  * @vsi_ctx: pointer to a vsi context struct
2616  * @cmd_details: pointer to command details structure or NULL
2617  *
2618  * Update a VSI context.
2619  **/
2620 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2621                                 struct i40e_vsi_context *vsi_ctx,
2622                                 struct i40e_asq_cmd_details *cmd_details)
2623 {
2624         struct i40e_aq_desc desc;
2625         struct i40e_aqc_add_get_update_vsi *cmd =
2626                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2627         struct i40e_aqc_add_get_update_vsi_completion *resp =
2628                 (struct i40e_aqc_add_get_update_vsi_completion *)
2629                 &desc.params.raw;
2630         enum i40e_status_code status;
2631
2632         i40e_fill_default_direct_cmd_desc(&desc,
2633                                           i40e_aqc_opc_update_vsi_parameters);
2634         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2635
2636         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2637
2638         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2639                                     sizeof(vsi_ctx->info), cmd_details);
2640
2641         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2642         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2643
2644         return status;
2645 }
2646
2647 /**
2648  * i40e_aq_get_switch_config
2649  * @hw: pointer to the hardware structure
2650  * @buf: pointer to the result buffer
2651  * @buf_size: length of input buffer
2652  * @start_seid: seid to start for the report, 0 == beginning
2653  * @cmd_details: pointer to command details structure or NULL
2654  *
2655  * Fill the buf with switch configuration returned from AdminQ command
2656  **/
2657 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2658                                 struct i40e_aqc_get_switch_config_resp *buf,
2659                                 u16 buf_size, u16 *start_seid,
2660                                 struct i40e_asq_cmd_details *cmd_details)
2661 {
2662         struct i40e_aq_desc desc;
2663         struct i40e_aqc_switch_seid *scfg =
2664                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2665         enum i40e_status_code status;
2666
2667         i40e_fill_default_direct_cmd_desc(&desc,
2668                                           i40e_aqc_opc_get_switch_config);
2669         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2670         if (buf_size > I40E_AQ_LARGE_BUF)
2671                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2672         scfg->seid = CPU_TO_LE16(*start_seid);
2673
2674         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2675         *start_seid = LE16_TO_CPU(scfg->seid);
2676
2677         return status;
2678 }
2679
2680 /**
2681  * i40e_aq_set_switch_config
2682  * @hw: pointer to the hardware structure
2683  * @flags: bit flag values to set
2684  * @mode: cloud filter mode
2685  * @valid_flags: which bit flags to set
2686  * @cmd_details: pointer to command details structure or NULL
2687  *
2688  * Set switch configuration bits
2689  **/
2690 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2691                                 u16 flags, u16 valid_flags, u8 mode,
2692                                 struct i40e_asq_cmd_details *cmd_details)
2693 {
2694         struct i40e_aq_desc desc;
2695         struct i40e_aqc_set_switch_config *scfg =
2696                 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2697         enum i40e_status_code status;
2698
2699         i40e_fill_default_direct_cmd_desc(&desc,
2700                                           i40e_aqc_opc_set_switch_config);
2701         scfg->flags = CPU_TO_LE16(flags);
2702         scfg->valid_flags = CPU_TO_LE16(valid_flags);
2703         scfg->mode = mode;
2704         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
2705                 scfg->switch_tag = CPU_TO_LE16(hw->switch_tag);
2706                 scfg->first_tag = CPU_TO_LE16(hw->first_tag);
2707                 scfg->second_tag = CPU_TO_LE16(hw->second_tag);
2708         }
2709         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2710
2711         return status;
2712 }
2713
2714 /**
2715  * i40e_aq_get_firmware_version
2716  * @hw: pointer to the hw struct
2717  * @fw_major_version: firmware major version
2718  * @fw_minor_version: firmware minor version
2719  * @fw_build: firmware build number
2720  * @api_major_version: major queue version
2721  * @api_minor_version: minor queue version
2722  * @cmd_details: pointer to command details structure or NULL
2723  *
2724  * Get the firmware version from the admin queue commands
2725  **/
2726 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2727                                 u16 *fw_major_version, u16 *fw_minor_version,
2728                                 u32 *fw_build,
2729                                 u16 *api_major_version, u16 *api_minor_version,
2730                                 struct i40e_asq_cmd_details *cmd_details)
2731 {
2732         struct i40e_aq_desc desc;
2733         struct i40e_aqc_get_version *resp =
2734                 (struct i40e_aqc_get_version *)&desc.params.raw;
2735         enum i40e_status_code status;
2736
2737         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2738
2739         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2740
2741         if (status == I40E_SUCCESS) {
2742                 if (fw_major_version != NULL)
2743                         *fw_major_version = LE16_TO_CPU(resp->fw_major);
2744                 if (fw_minor_version != NULL)
2745                         *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2746                 if (fw_build != NULL)
2747                         *fw_build = LE32_TO_CPU(resp->fw_build);
2748                 if (api_major_version != NULL)
2749                         *api_major_version = LE16_TO_CPU(resp->api_major);
2750                 if (api_minor_version != NULL)
2751                         *api_minor_version = LE16_TO_CPU(resp->api_minor);
2752
2753                 /* A workaround to fix the API version in SW */
2754                 if (api_major_version && api_minor_version &&
2755                     fw_major_version && fw_minor_version &&
2756                     ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2757                     (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2758                      (*fw_major_version > 4)))
2759                         *api_minor_version = 2;
2760         }
2761
2762         return status;
2763 }
2764
2765 /**
2766  * i40e_aq_send_driver_version
2767  * @hw: pointer to the hw struct
2768  * @dv: driver's major, minor version
2769  * @cmd_details: pointer to command details structure or NULL
2770  *
2771  * Send the driver version to the firmware
2772  **/
2773 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2774                                 struct i40e_driver_version *dv,
2775                                 struct i40e_asq_cmd_details *cmd_details)
2776 {
2777         struct i40e_aq_desc desc;
2778         struct i40e_aqc_driver_version *cmd =
2779                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2780         enum i40e_status_code status;
2781         u16 len;
2782
2783         if (dv == NULL)
2784                 return I40E_ERR_PARAM;
2785
2786         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2787
2788         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2789         cmd->driver_major_ver = dv->major_version;
2790         cmd->driver_minor_ver = dv->minor_version;
2791         cmd->driver_build_ver = dv->build_version;
2792         cmd->driver_subbuild_ver = dv->subbuild_version;
2793
2794         len = 0;
2795         while (len < sizeof(dv->driver_string) &&
2796                (dv->driver_string[len] < 0x80) &&
2797                dv->driver_string[len])
2798                 len++;
2799         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2800                                        len, cmd_details);
2801
2802         return status;
2803 }
2804
2805 /**
2806  * i40e_get_link_status - get status of the HW network link
2807  * @hw: pointer to the hw struct
2808  * @link_up: pointer to bool (true/false = linkup/linkdown)
2809  *
2810  * Variable link_up true if link is up, false if link is down.
2811  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2812  *
2813  * Side effect: LinkStatusEvent reporting becomes enabled
2814  **/
2815 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2816 {
2817         enum i40e_status_code status = I40E_SUCCESS;
2818
2819         if (hw->phy.get_link_info) {
2820                 status = i40e_update_link_info(hw);
2821
2822                 if (status != I40E_SUCCESS)
2823                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2824                                    status);
2825         }
2826
2827         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2828
2829         return status;
2830 }
2831
2832 /**
2833  * i40e_updatelink_status - update status of the HW network link
2834  * @hw: pointer to the hw struct
2835  **/
2836 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2837 {
2838         struct i40e_aq_get_phy_abilities_resp abilities;
2839         enum i40e_status_code status = I40E_SUCCESS;
2840
2841         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2842         if (status)
2843                 return status;
2844
2845         /* extra checking needed to ensure link info to user is timely */
2846         if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2847             ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2848              !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2849                 status = i40e_aq_get_phy_capabilities(hw, false, false,
2850                                                       &abilities, NULL);
2851                 if (status)
2852                         return status;
2853
2854                 hw->phy.link_info.req_fec_info =
2855                         abilities.fec_cfg_curr_mod_ext_info &
2856                         (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS);
2857
2858                 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2859                         sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2860         }
2861         return status;
2862 }
2863
2864
2865 /**
2866  * i40e_get_link_speed
2867  * @hw: pointer to the hw struct
2868  *
2869  * Returns the link speed of the adapter.
2870  **/
2871 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2872 {
2873         enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2874         enum i40e_status_code status = I40E_SUCCESS;
2875
2876         if (hw->phy.get_link_info) {
2877                 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2878
2879                 if (status != I40E_SUCCESS)
2880                         goto i40e_link_speed_exit;
2881         }
2882
2883         speed = hw->phy.link_info.link_speed;
2884
2885 i40e_link_speed_exit:
2886         return speed;
2887 }
2888
2889 /**
2890  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2891  * @hw: pointer to the hw struct
2892  * @uplink_seid: the MAC or other gizmo SEID
2893  * @downlink_seid: the VSI SEID
2894  * @enabled_tc: bitmap of TCs to be enabled
2895  * @default_port: true for default port VSI, false for control port
2896  * @veb_seid: pointer to where to put the resulting VEB SEID
2897  * @enable_stats: true to turn on VEB stats
2898  * @cmd_details: pointer to command details structure or NULL
2899  *
2900  * This asks the FW to add a VEB between the uplink and downlink
2901  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2902  **/
2903 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2904                                 u16 downlink_seid, u8 enabled_tc,
2905                                 bool default_port, u16 *veb_seid,
2906                                 bool enable_stats,
2907                                 struct i40e_asq_cmd_details *cmd_details)
2908 {
2909         struct i40e_aq_desc desc;
2910         struct i40e_aqc_add_veb *cmd =
2911                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2912         struct i40e_aqc_add_veb_completion *resp =
2913                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2914         enum i40e_status_code status;
2915         u16 veb_flags = 0;
2916
2917         /* SEIDs need to either both be set or both be 0 for floating VEB */
2918         if (!!uplink_seid != !!downlink_seid)
2919                 return I40E_ERR_PARAM;
2920
2921         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2922
2923         cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2924         cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2925         cmd->enable_tcs = enabled_tc;
2926         if (!uplink_seid)
2927                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2928         if (default_port)
2929                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2930         else
2931                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2932
2933         /* reverse logic here: set the bitflag to disable the stats */
2934         if (!enable_stats)
2935                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2936
2937         cmd->veb_flags = CPU_TO_LE16(veb_flags);
2938
2939         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2940
2941         if (!status && veb_seid)
2942                 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2943
2944         return status;
2945 }
2946
2947 /**
2948  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2949  * @hw: pointer to the hw struct
2950  * @veb_seid: the SEID of the VEB to query
2951  * @switch_id: the uplink switch id
2952  * @floating: set to true if the VEB is floating
2953  * @statistic_index: index of the stats counter block for this VEB
2954  * @vebs_used: number of VEB's used by function
2955  * @vebs_free: total VEB's not reserved by any function
2956  * @cmd_details: pointer to command details structure or NULL
2957  *
2958  * This retrieves the parameters for a particular VEB, specified by
2959  * uplink_seid, and returns them to the caller.
2960  **/
2961 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2962                                 u16 veb_seid, u16 *switch_id,
2963                                 bool *floating, u16 *statistic_index,
2964                                 u16 *vebs_used, u16 *vebs_free,
2965                                 struct i40e_asq_cmd_details *cmd_details)
2966 {
2967         struct i40e_aq_desc desc;
2968         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2969                 (struct i40e_aqc_get_veb_parameters_completion *)
2970                 &desc.params.raw;
2971         enum i40e_status_code status;
2972
2973         if (veb_seid == 0)
2974                 return I40E_ERR_PARAM;
2975
2976         i40e_fill_default_direct_cmd_desc(&desc,
2977                                           i40e_aqc_opc_get_veb_parameters);
2978         cmd_resp->seid = CPU_TO_LE16(veb_seid);
2979
2980         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2981         if (status)
2982                 goto get_veb_exit;
2983
2984         if (switch_id)
2985                 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2986         if (statistic_index)
2987                 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2988         if (vebs_used)
2989                 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2990         if (vebs_free)
2991                 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2992         if (floating) {
2993                 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2994
2995                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2996                         *floating = true;
2997                 else
2998                         *floating = false;
2999         }
3000
3001 get_veb_exit:
3002         return status;
3003 }
3004
3005 /**
3006  * i40e_aq_add_macvlan
3007  * @hw: pointer to the hw struct
3008  * @seid: VSI for the mac address
3009  * @mv_list: list of macvlans to be added
3010  * @count: length of the list
3011  * @cmd_details: pointer to command details structure or NULL
3012  *
3013  * Add MAC/VLAN addresses to the HW filtering
3014  **/
3015 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
3016                         struct i40e_aqc_add_macvlan_element_data *mv_list,
3017                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3018 {
3019         struct i40e_aq_desc desc;
3020         struct i40e_aqc_macvlan *cmd =
3021                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3022         enum i40e_status_code status;
3023         u16 buf_size;
3024         int i;
3025
3026         if (count == 0 || !mv_list || !hw)
3027                 return I40E_ERR_PARAM;
3028
3029         buf_size = count * sizeof(*mv_list);
3030
3031         /* prep the rest of the request */
3032         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
3033         cmd->num_addresses = CPU_TO_LE16(count);
3034         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3035         cmd->seid[1] = 0;
3036         cmd->seid[2] = 0;
3037
3038         for (i = 0; i < count; i++)
3039                 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
3040                         mv_list[i].flags |=
3041                             CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
3042
3043         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3044         if (buf_size > I40E_AQ_LARGE_BUF)
3045                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3046
3047         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3048                                        cmd_details);
3049
3050         return status;
3051 }
3052
3053 /**
3054  * i40e_aq_remove_macvlan
3055  * @hw: pointer to the hw struct
3056  * @seid: VSI for the mac address
3057  * @mv_list: list of macvlans to be removed
3058  * @count: length of the list
3059  * @cmd_details: pointer to command details structure or NULL
3060  *
3061  * Remove MAC/VLAN addresses from the HW filtering
3062  **/
3063 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
3064                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
3065                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3066 {
3067         struct i40e_aq_desc desc;
3068         struct i40e_aqc_macvlan *cmd =
3069                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3070         enum i40e_status_code status;
3071         u16 buf_size;
3072
3073         if (count == 0 || !mv_list || !hw)
3074                 return I40E_ERR_PARAM;
3075
3076         buf_size = count * sizeof(*mv_list);
3077
3078         /* prep the rest of the request */
3079         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
3080         cmd->num_addresses = CPU_TO_LE16(count);
3081         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3082         cmd->seid[1] = 0;
3083         cmd->seid[2] = 0;
3084
3085         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3086         if (buf_size > I40E_AQ_LARGE_BUF)
3087                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3088
3089         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3090                                        cmd_details);
3091
3092         return status;
3093 }
3094
3095 /**
3096  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3097  * @hw: pointer to the hw struct
3098  * @opcode: AQ opcode for add or delete mirror rule
3099  * @sw_seid: Switch SEID (to which rule refers)
3100  * @rule_type: Rule Type (ingress/egress/VLAN)
3101  * @id: Destination VSI SEID or Rule ID
3102  * @count: length of the list
3103  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3104  * @cmd_details: pointer to command details structure or NULL
3105  * @rule_id: Rule ID returned from FW
3106  * @rules_used: Number of rules used in internal switch
3107  * @rules_free: Number of rules free in internal switch
3108  *
3109  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3110  * VEBs/VEPA elements only
3111  **/
3112 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3113                         u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3114                         u16 count, __le16 *mr_list,
3115                         struct i40e_asq_cmd_details *cmd_details,
3116                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3117 {
3118         struct i40e_aq_desc desc;
3119         struct i40e_aqc_add_delete_mirror_rule *cmd =
3120                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3121         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3122         (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3123         enum i40e_status_code status;
3124         u16 buf_size;
3125
3126         buf_size = count * sizeof(*mr_list);
3127
3128         /* prep the rest of the request */
3129         i40e_fill_default_direct_cmd_desc(&desc, opcode);
3130         cmd->seid = CPU_TO_LE16(sw_seid);
3131         cmd->rule_type = CPU_TO_LE16(rule_type &
3132                                      I40E_AQC_MIRROR_RULE_TYPE_MASK);
3133         cmd->num_entries = CPU_TO_LE16(count);
3134         /* Dest VSI for add, rule_id for delete */
3135         cmd->destination = CPU_TO_LE16(id);
3136         if (mr_list) {
3137                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3138                                                 I40E_AQ_FLAG_RD));
3139                 if (buf_size > I40E_AQ_LARGE_BUF)
3140                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3141         }
3142
3143         status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3144                                        cmd_details);
3145         if (status == I40E_SUCCESS ||
3146             hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3147                 if (rule_id)
3148                         *rule_id = LE16_TO_CPU(resp->rule_id);
3149                 if (rules_used)
3150                         *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3151                 if (rules_free)
3152                         *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3153         }
3154         return status;
3155 }
3156
3157 /**
3158  * i40e_aq_add_mirrorrule - add a mirror rule
3159  * @hw: pointer to the hw struct
3160  * @sw_seid: Switch SEID (to which rule refers)
3161  * @rule_type: Rule Type (ingress/egress/VLAN)
3162  * @dest_vsi: SEID of VSI to which packets will be mirrored
3163  * @count: length of the list
3164  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3165  * @cmd_details: pointer to command details structure or NULL
3166  * @rule_id: Rule ID returned from FW
3167  * @rules_used: Number of rules used in internal switch
3168  * @rules_free: Number of rules free in internal switch
3169  *
3170  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3171  **/
3172 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3173                         u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3174                         struct i40e_asq_cmd_details *cmd_details,
3175                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3176 {
3177         if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3178             rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3179                 if (count == 0 || !mr_list)
3180                         return I40E_ERR_PARAM;
3181         }
3182
3183         return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3184                                   rule_type, dest_vsi, count, mr_list,
3185                                   cmd_details, rule_id, rules_used, rules_free);
3186 }
3187
3188 /**
3189  * i40e_aq_delete_mirrorrule - delete a mirror rule
3190  * @hw: pointer to the hw struct
3191  * @sw_seid: Switch SEID (to which rule refers)
3192  * @rule_type: Rule Type (ingress/egress/VLAN)
3193  * @count: length of the list
3194  * @rule_id: Rule ID that is returned in the receive desc as part of
3195  *              add_mirrorrule.
3196  * @mr_list: list of mirrored VLAN IDs to be removed
3197  * @cmd_details: pointer to command details structure or NULL
3198  * @rules_used: Number of rules used in internal switch
3199  * @rules_free: Number of rules free in internal switch
3200  *
3201  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3202  **/
3203 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3204                         u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3205                         struct i40e_asq_cmd_details *cmd_details,
3206                         u16 *rules_used, u16 *rules_free)
3207 {
3208         /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3209         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3210                 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3211                  * mirroring. For other rule_type, count and rule_type should
3212                  * not matter.
3213                  */
3214                 if (count == 0 || !mr_list)
3215                         return I40E_ERR_PARAM;
3216         }
3217
3218         return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3219                                   rule_type, rule_id, count, mr_list,
3220                                   cmd_details, NULL, rules_used, rules_free);
3221 }
3222
3223 /**
3224  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3225  * @hw: pointer to the hw struct
3226  * @seid: VSI for the vlan filters
3227  * @v_list: list of vlan filters to be added
3228  * @count: length of the list
3229  * @cmd_details: pointer to command details structure or NULL
3230  **/
3231 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3232                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3233                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3234 {
3235         struct i40e_aq_desc desc;
3236         struct i40e_aqc_macvlan *cmd =
3237                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3238         enum i40e_status_code status;
3239         u16 buf_size;
3240
3241         if (count == 0 || !v_list || !hw)
3242                 return I40E_ERR_PARAM;
3243
3244         buf_size = count * sizeof(*v_list);
3245
3246         /* prep the rest of the request */
3247         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3248         cmd->num_addresses = CPU_TO_LE16(count);
3249         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3250         cmd->seid[1] = 0;
3251         cmd->seid[2] = 0;
3252
3253         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3254         if (buf_size > I40E_AQ_LARGE_BUF)
3255                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3256
3257         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3258                                        cmd_details);
3259
3260         return status;
3261 }
3262
3263 /**
3264  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3265  * @hw: pointer to the hw struct
3266  * @seid: VSI for the vlan filters
3267  * @v_list: list of macvlans to be removed
3268  * @count: length of the list
3269  * @cmd_details: pointer to command details structure or NULL
3270  **/
3271 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3272                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3273                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3274 {
3275         struct i40e_aq_desc desc;
3276         struct i40e_aqc_macvlan *cmd =
3277                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3278         enum i40e_status_code status;
3279         u16 buf_size;
3280
3281         if (count == 0 || !v_list || !hw)
3282                 return I40E_ERR_PARAM;
3283
3284         buf_size = count * sizeof(*v_list);
3285
3286         /* prep the rest of the request */
3287         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3288         cmd->num_addresses = CPU_TO_LE16(count);
3289         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3290         cmd->seid[1] = 0;
3291         cmd->seid[2] = 0;
3292
3293         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3294         if (buf_size > I40E_AQ_LARGE_BUF)
3295                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3296
3297         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3298                                        cmd_details);
3299
3300         return status;
3301 }
3302
3303 /**
3304  * i40e_aq_send_msg_to_vf
3305  * @hw: pointer to the hardware structure
3306  * @vfid: vf id to send msg
3307  * @v_opcode: opcodes for VF-PF communication
3308  * @v_retval: return error code
3309  * @msg: pointer to the msg buffer
3310  * @msglen: msg length
3311  * @cmd_details: pointer to command details
3312  *
3313  * send msg to vf
3314  **/
3315 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3316                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3317                                 struct i40e_asq_cmd_details *cmd_details)
3318 {
3319         struct i40e_aq_desc desc;
3320         struct i40e_aqc_pf_vf_message *cmd =
3321                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3322         enum i40e_status_code status;
3323
3324         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3325         cmd->id = CPU_TO_LE32(vfid);
3326         desc.cookie_high = CPU_TO_LE32(v_opcode);
3327         desc.cookie_low = CPU_TO_LE32(v_retval);
3328         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3329         if (msglen) {
3330                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3331                                                 I40E_AQ_FLAG_RD));
3332                 if (msglen > I40E_AQ_LARGE_BUF)
3333                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3334                 desc.datalen = CPU_TO_LE16(msglen);
3335         }
3336         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3337
3338         return status;
3339 }
3340
3341 /**
3342  * i40e_aq_debug_read_register
3343  * @hw: pointer to the hw struct
3344  * @reg_addr: register address
3345  * @reg_val: register value
3346  * @cmd_details: pointer to command details structure or NULL
3347  *
3348  * Read the register using the admin queue commands
3349  **/
3350 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3351                                 u32 reg_addr, u64 *reg_val,
3352                                 struct i40e_asq_cmd_details *cmd_details)
3353 {
3354         struct i40e_aq_desc desc;
3355         struct i40e_aqc_debug_reg_read_write *cmd_resp =
3356                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3357         enum i40e_status_code status;
3358
3359         if (reg_val == NULL)
3360                 return I40E_ERR_PARAM;
3361
3362         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3363
3364         cmd_resp->address = CPU_TO_LE32(reg_addr);
3365
3366         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3367
3368         if (status == I40E_SUCCESS) {
3369                 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3370                            (u64)LE32_TO_CPU(cmd_resp->value_low);
3371         }
3372
3373         return status;
3374 }
3375
3376 /**
3377  * i40e_aq_debug_write_register
3378  * @hw: pointer to the hw struct
3379  * @reg_addr: register address
3380  * @reg_val: register value
3381  * @cmd_details: pointer to command details structure or NULL
3382  *
3383  * Write to a register using the admin queue commands
3384  **/
3385 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3386                                 u32 reg_addr, u64 reg_val,
3387                                 struct i40e_asq_cmd_details *cmd_details)
3388 {
3389         struct i40e_aq_desc desc;
3390         struct i40e_aqc_debug_reg_read_write *cmd =
3391                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3392         enum i40e_status_code status;
3393
3394         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3395
3396         cmd->address = CPU_TO_LE32(reg_addr);
3397         cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3398         cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3399
3400         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3401
3402         return status;
3403 }
3404
3405 /**
3406  * i40e_aq_request_resource
3407  * @hw: pointer to the hw struct
3408  * @resource: resource id
3409  * @access: access type
3410  * @sdp_number: resource number
3411  * @timeout: the maximum time in ms that the driver may hold the resource
3412  * @cmd_details: pointer to command details structure or NULL
3413  *
3414  * requests common resource using the admin queue commands
3415  **/
3416 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3417                                 enum i40e_aq_resources_ids resource,
3418                                 enum i40e_aq_resource_access_type access,
3419                                 u8 sdp_number, u64 *timeout,
3420                                 struct i40e_asq_cmd_details *cmd_details)
3421 {
3422         struct i40e_aq_desc desc;
3423         struct i40e_aqc_request_resource *cmd_resp =
3424                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3425         enum i40e_status_code status;
3426
3427         DEBUGFUNC("i40e_aq_request_resource");
3428
3429         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3430
3431         cmd_resp->resource_id = CPU_TO_LE16(resource);
3432         cmd_resp->access_type = CPU_TO_LE16(access);
3433         cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3434
3435         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3436         /* The completion specifies the maximum time in ms that the driver
3437          * may hold the resource in the Timeout field.
3438          * If the resource is held by someone else, the command completes with
3439          * busy return value and the timeout field indicates the maximum time
3440          * the current owner of the resource has to free it.
3441          */
3442         if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3443                 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3444
3445         return status;
3446 }
3447
3448 /**
3449  * i40e_aq_release_resource
3450  * @hw: pointer to the hw struct
3451  * @resource: resource id
3452  * @sdp_number: resource number
3453  * @cmd_details: pointer to command details structure or NULL
3454  *
3455  * release common resource using the admin queue commands
3456  **/
3457 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3458                                 enum i40e_aq_resources_ids resource,
3459                                 u8 sdp_number,
3460                                 struct i40e_asq_cmd_details *cmd_details)
3461 {
3462         struct i40e_aq_desc desc;
3463         struct i40e_aqc_request_resource *cmd =
3464                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3465         enum i40e_status_code status;
3466
3467         DEBUGFUNC("i40e_aq_release_resource");
3468
3469         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3470
3471         cmd->resource_id = CPU_TO_LE16(resource);
3472         cmd->resource_number = CPU_TO_LE32(sdp_number);
3473
3474         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3475
3476         return status;
3477 }
3478
3479 /**
3480  * i40e_aq_read_nvm
3481  * @hw: pointer to the hw struct
3482  * @module_pointer: module pointer location in words from the NVM beginning
3483  * @offset: byte offset from the module beginning
3484  * @length: length of the section to be read (in bytes from the offset)
3485  * @data: command buffer (size [bytes] = length)
3486  * @last_command: tells if this is the last command in a series
3487  * @cmd_details: pointer to command details structure or NULL
3488  *
3489  * Read the NVM using the admin queue commands
3490  **/
3491 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3492                                 u32 offset, u16 length, void *data,
3493                                 bool last_command,
3494                                 struct i40e_asq_cmd_details *cmd_details)
3495 {
3496         struct i40e_aq_desc desc;
3497         struct i40e_aqc_nvm_update *cmd =
3498                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3499         enum i40e_status_code status;
3500
3501         DEBUGFUNC("i40e_aq_read_nvm");
3502
3503         /* In offset the highest byte must be zeroed. */
3504         if (offset & 0xFF000000) {
3505                 status = I40E_ERR_PARAM;
3506                 goto i40e_aq_read_nvm_exit;
3507         }
3508
3509         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3510
3511         /* If this is the last command in a series, set the proper flag. */
3512         if (last_command)
3513                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3514         cmd->module_pointer = module_pointer;
3515         cmd->offset = CPU_TO_LE32(offset);
3516         cmd->length = CPU_TO_LE16(length);
3517
3518         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3519         if (length > I40E_AQ_LARGE_BUF)
3520                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3521
3522         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3523
3524 i40e_aq_read_nvm_exit:
3525         return status;
3526 }
3527
3528 /**
3529  * i40e_aq_read_nvm_config - read an nvm config block
3530  * @hw: pointer to the hw struct
3531  * @cmd_flags: NVM access admin command bits
3532  * @field_id: field or feature id
3533  * @data: buffer for result
3534  * @buf_size: buffer size
3535  * @element_count: pointer to count of elements read by FW
3536  * @cmd_details: pointer to command details structure or NULL
3537  **/
3538 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3539                                 u8 cmd_flags, u32 field_id, void *data,
3540                                 u16 buf_size, u16 *element_count,
3541                                 struct i40e_asq_cmd_details *cmd_details)
3542 {
3543         struct i40e_aq_desc desc;
3544         struct i40e_aqc_nvm_config_read *cmd =
3545                 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3546         enum i40e_status_code status;
3547
3548         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3549         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3550         if (buf_size > I40E_AQ_LARGE_BUF)
3551                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3552
3553         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3554         cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3555         if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3556                 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3557         else
3558                 cmd->element_id_msw = 0;
3559
3560         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3561
3562         if (!status && element_count)
3563                 *element_count = LE16_TO_CPU(cmd->element_count);
3564
3565         return status;
3566 }
3567
3568 /**
3569  * i40e_aq_write_nvm_config - write an nvm config block
3570  * @hw: pointer to the hw struct
3571  * @cmd_flags: NVM access admin command bits
3572  * @data: buffer for result
3573  * @buf_size: buffer size
3574  * @element_count: count of elements to be written
3575  * @cmd_details: pointer to command details structure or NULL
3576  **/
3577 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3578                                 u8 cmd_flags, void *data, u16 buf_size,
3579                                 u16 element_count,
3580                                 struct i40e_asq_cmd_details *cmd_details)
3581 {
3582         struct i40e_aq_desc desc;
3583         struct i40e_aqc_nvm_config_write *cmd =
3584                 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3585         enum i40e_status_code status;
3586
3587         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3588         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3589         if (buf_size > I40E_AQ_LARGE_BUF)
3590                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3591
3592         cmd->element_count = CPU_TO_LE16(element_count);
3593         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3594         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3595
3596         return status;
3597 }
3598
3599 /**
3600  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3601  * @hw: pointer to the hw struct
3602  * @buff: buffer for result
3603  * @buff_size: buffer size
3604  * @cmd_details: pointer to command details structure or NULL
3605  **/
3606 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3607                                 void *buff, u16 buff_size,
3608                                 struct i40e_asq_cmd_details *cmd_details)
3609 {
3610         struct i40e_aq_desc desc;
3611         enum i40e_status_code status;
3612
3613         UNREFERENCED_2PARAMETER(buff, buff_size);
3614
3615         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3616         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3617         if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3618                 status = I40E_ERR_NOT_IMPLEMENTED;
3619
3620         return status;
3621 }
3622
3623 /**
3624  * i40e_aq_erase_nvm
3625  * @hw: pointer to the hw struct
3626  * @module_pointer: module pointer location in words from the NVM beginning
3627  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3628  * @length: length of the section to be erased (expressed in 4 KB)
3629  * @last_command: tells if this is the last command in a series
3630  * @cmd_details: pointer to command details structure or NULL
3631  *
3632  * Erase the NVM sector using the admin queue commands
3633  **/
3634 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3635                                 u32 offset, u16 length, bool last_command,
3636                                 struct i40e_asq_cmd_details *cmd_details)
3637 {
3638         struct i40e_aq_desc desc;
3639         struct i40e_aqc_nvm_update *cmd =
3640                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3641         enum i40e_status_code status;
3642
3643         DEBUGFUNC("i40e_aq_erase_nvm");
3644
3645         /* In offset the highest byte must be zeroed. */
3646         if (offset & 0xFF000000) {
3647                 status = I40E_ERR_PARAM;
3648                 goto i40e_aq_erase_nvm_exit;
3649         }
3650
3651         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3652
3653         /* If this is the last command in a series, set the proper flag. */
3654         if (last_command)
3655                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3656         cmd->module_pointer = module_pointer;
3657         cmd->offset = CPU_TO_LE32(offset);
3658         cmd->length = CPU_TO_LE16(length);
3659
3660         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3661
3662 i40e_aq_erase_nvm_exit:
3663         return status;
3664 }
3665
3666 /**
3667  * i40e_parse_discover_capabilities
3668  * @hw: pointer to the hw struct
3669  * @buff: pointer to a buffer containing device/function capability records
3670  * @cap_count: number of capability records in the list
3671  * @list_type_opc: type of capabilities list to parse
3672  *
3673  * Parse the device/function capabilities list.
3674  **/
3675 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3676                                      u32 cap_count,
3677                                      enum i40e_admin_queue_opc list_type_opc)
3678 {
3679         struct i40e_aqc_list_capabilities_element_resp *cap;
3680         u32 valid_functions, num_functions;
3681         u32 number, logical_id, phys_id;
3682         struct i40e_hw_capabilities *p;
3683         enum i40e_status_code status;
3684         u16 id, ocp_cfg_word0;
3685         u8 major_rev;
3686         u32 i = 0;
3687
3688         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3689
3690         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3691                 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3692         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3693                 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3694         else
3695                 return;
3696
3697         for (i = 0; i < cap_count; i++, cap++) {
3698                 id = LE16_TO_CPU(cap->id);
3699                 number = LE32_TO_CPU(cap->number);
3700                 logical_id = LE32_TO_CPU(cap->logical_id);
3701                 phys_id = LE32_TO_CPU(cap->phys_id);
3702                 major_rev = cap->major_rev;
3703
3704                 switch (id) {
3705                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3706                         p->switch_mode = number;
3707                         i40e_debug(hw, I40E_DEBUG_INIT,
3708                                    "HW Capability: Switch mode = %d\n",
3709                                    p->switch_mode);
3710                         break;
3711                 case I40E_AQ_CAP_ID_MNG_MODE:
3712                         p->management_mode = number;
3713                         if (major_rev > 1) {
3714                                 p->mng_protocols_over_mctp = logical_id;
3715                                 i40e_debug(hw, I40E_DEBUG_INIT,
3716                                            "HW Capability: Protocols over MCTP = %d\n",
3717                                            p->mng_protocols_over_mctp);
3718                         } else {
3719                                 p->mng_protocols_over_mctp = 0;
3720                         }
3721                         i40e_debug(hw, I40E_DEBUG_INIT,
3722                                    "HW Capability: Management Mode = %d\n",
3723                                    p->management_mode);
3724                         break;
3725                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3726                         p->npar_enable = number;
3727                         i40e_debug(hw, I40E_DEBUG_INIT,
3728                                    "HW Capability: NPAR enable = %d\n",
3729                                    p->npar_enable);
3730                         break;
3731                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3732                         p->os2bmc = number;
3733                         i40e_debug(hw, I40E_DEBUG_INIT,
3734                                    "HW Capability: OS2BMC = %d\n", p->os2bmc);
3735                         break;
3736                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3737                         p->valid_functions = number;
3738                         i40e_debug(hw, I40E_DEBUG_INIT,
3739                                    "HW Capability: Valid Functions = %d\n",
3740                                    p->valid_functions);
3741                         break;
3742                 case I40E_AQ_CAP_ID_SRIOV:
3743                         if (number == 1)
3744                                 p->sr_iov_1_1 = true;
3745                         i40e_debug(hw, I40E_DEBUG_INIT,
3746                                    "HW Capability: SR-IOV = %d\n",
3747                                    p->sr_iov_1_1);
3748                         break;
3749                 case I40E_AQ_CAP_ID_VF:
3750                         p->num_vfs = number;
3751                         p->vf_base_id = logical_id;
3752                         i40e_debug(hw, I40E_DEBUG_INIT,
3753                                    "HW Capability: VF count = %d\n",
3754                                    p->num_vfs);
3755                         i40e_debug(hw, I40E_DEBUG_INIT,
3756                                    "HW Capability: VF base_id = %d\n",
3757                                    p->vf_base_id);
3758                         break;
3759                 case I40E_AQ_CAP_ID_VMDQ:
3760                         if (number == 1)
3761                                 p->vmdq = true;
3762                         i40e_debug(hw, I40E_DEBUG_INIT,
3763                                    "HW Capability: VMDQ = %d\n", p->vmdq);
3764                         break;
3765                 case I40E_AQ_CAP_ID_8021QBG:
3766                         if (number == 1)
3767                                 p->evb_802_1_qbg = true;
3768                         i40e_debug(hw, I40E_DEBUG_INIT,
3769                                    "HW Capability: 802.1Qbg = %d\n", number);
3770                         break;
3771                 case I40E_AQ_CAP_ID_8021QBR:
3772                         if (number == 1)
3773                                 p->evb_802_1_qbh = true;
3774                         i40e_debug(hw, I40E_DEBUG_INIT,
3775                                    "HW Capability: 802.1Qbh = %d\n", number);
3776                         break;
3777                 case I40E_AQ_CAP_ID_VSI:
3778                         p->num_vsis = number;
3779                         i40e_debug(hw, I40E_DEBUG_INIT,
3780                                    "HW Capability: VSI count = %d\n",
3781                                    p->num_vsis);
3782                         break;
3783                 case I40E_AQ_CAP_ID_DCB:
3784                         if (number == 1) {
3785                                 p->dcb = true;
3786                                 p->enabled_tcmap = logical_id;
3787                                 p->maxtc = phys_id;
3788                         }
3789                         i40e_debug(hw, I40E_DEBUG_INIT,
3790                                    "HW Capability: DCB = %d\n", p->dcb);
3791                         i40e_debug(hw, I40E_DEBUG_INIT,
3792                                    "HW Capability: TC Mapping = %d\n",
3793                                    logical_id);
3794                         i40e_debug(hw, I40E_DEBUG_INIT,
3795                                    "HW Capability: TC Max = %d\n", p->maxtc);
3796                         break;
3797                 case I40E_AQ_CAP_ID_FCOE:
3798                         if (number == 1)
3799                                 p->fcoe = true;
3800                         i40e_debug(hw, I40E_DEBUG_INIT,
3801                                    "HW Capability: FCOE = %d\n", p->fcoe);
3802                         break;
3803                 case I40E_AQ_CAP_ID_ISCSI:
3804                         if (number == 1)
3805                                 p->iscsi = true;
3806                         i40e_debug(hw, I40E_DEBUG_INIT,
3807                                    "HW Capability: iSCSI = %d\n", p->iscsi);
3808                         break;
3809                 case I40E_AQ_CAP_ID_RSS:
3810                         p->rss = true;
3811                         p->rss_table_size = number;
3812                         p->rss_table_entry_width = logical_id;
3813                         i40e_debug(hw, I40E_DEBUG_INIT,
3814                                    "HW Capability: RSS = %d\n", p->rss);
3815                         i40e_debug(hw, I40E_DEBUG_INIT,
3816                                    "HW Capability: RSS table size = %d\n",
3817                                    p->rss_table_size);
3818                         i40e_debug(hw, I40E_DEBUG_INIT,
3819                                    "HW Capability: RSS table width = %d\n",
3820                                    p->rss_table_entry_width);
3821                         break;
3822                 case I40E_AQ_CAP_ID_RXQ:
3823                         p->num_rx_qp = number;
3824                         p->base_queue = phys_id;
3825                         i40e_debug(hw, I40E_DEBUG_INIT,
3826                                    "HW Capability: Rx QP = %d\n", number);
3827                         i40e_debug(hw, I40E_DEBUG_INIT,
3828                                    "HW Capability: base_queue = %d\n",
3829                                    p->base_queue);
3830                         break;
3831                 case I40E_AQ_CAP_ID_TXQ:
3832                         p->num_tx_qp = number;
3833                         p->base_queue = phys_id;
3834                         i40e_debug(hw, I40E_DEBUG_INIT,
3835                                    "HW Capability: Tx QP = %d\n", number);
3836                         i40e_debug(hw, I40E_DEBUG_INIT,
3837                                    "HW Capability: base_queue = %d\n",
3838                                    p->base_queue);
3839                         break;
3840                 case I40E_AQ_CAP_ID_MSIX:
3841                         p->num_msix_vectors = number;
3842                         i40e_debug(hw, I40E_DEBUG_INIT,
3843                                    "HW Capability: MSIX vector count = %d\n",
3844                                    p->num_msix_vectors);
3845                         break;
3846                 case I40E_AQ_CAP_ID_VF_MSIX:
3847                         p->num_msix_vectors_vf = number;
3848                         i40e_debug(hw, I40E_DEBUG_INIT,
3849                                    "HW Capability: MSIX VF vector count = %d\n",
3850                                    p->num_msix_vectors_vf);
3851                         break;
3852                 case I40E_AQ_CAP_ID_FLEX10:
3853                         if (major_rev == 1) {
3854                                 if (number == 1) {
3855                                         p->flex10_enable = true;
3856                                         p->flex10_capable = true;
3857                                 }
3858                         } else {
3859                                 /* Capability revision >= 2 */
3860                                 if (number & 1)
3861                                         p->flex10_enable = true;
3862                                 if (number & 2)
3863                                         p->flex10_capable = true;
3864                         }
3865                         p->flex10_mode = logical_id;
3866                         p->flex10_status = phys_id;
3867                         i40e_debug(hw, I40E_DEBUG_INIT,
3868                                    "HW Capability: Flex10 mode = %d\n",
3869                                    p->flex10_mode);
3870                         i40e_debug(hw, I40E_DEBUG_INIT,
3871                                    "HW Capability: Flex10 status = %d\n",
3872                                    p->flex10_status);
3873                         break;
3874                 case I40E_AQ_CAP_ID_CEM:
3875                         if (number == 1)
3876                                 p->mgmt_cem = true;
3877                         i40e_debug(hw, I40E_DEBUG_INIT,
3878                                    "HW Capability: CEM = %d\n", p->mgmt_cem);
3879                         break;
3880                 case I40E_AQ_CAP_ID_IWARP:
3881                         if (number == 1)
3882                                 p->iwarp = true;
3883                         i40e_debug(hw, I40E_DEBUG_INIT,
3884                                    "HW Capability: iWARP = %d\n", p->iwarp);
3885                         break;
3886                 case I40E_AQ_CAP_ID_LED:
3887                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3888                                 p->led[phys_id] = true;
3889                         i40e_debug(hw, I40E_DEBUG_INIT,
3890                                    "HW Capability: LED - PIN %d\n", phys_id);
3891                         break;
3892                 case I40E_AQ_CAP_ID_SDP:
3893                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3894                                 p->sdp[phys_id] = true;
3895                         i40e_debug(hw, I40E_DEBUG_INIT,
3896                                    "HW Capability: SDP - PIN %d\n", phys_id);
3897                         break;
3898                 case I40E_AQ_CAP_ID_MDIO:
3899                         if (number == 1) {
3900                                 p->mdio_port_num = phys_id;
3901                                 p->mdio_port_mode = logical_id;
3902                         }
3903                         i40e_debug(hw, I40E_DEBUG_INIT,
3904                                    "HW Capability: MDIO port number = %d\n",
3905                                    p->mdio_port_num);
3906                         i40e_debug(hw, I40E_DEBUG_INIT,
3907                                    "HW Capability: MDIO port mode = %d\n",
3908                                    p->mdio_port_mode);
3909                         break;
3910                 case I40E_AQ_CAP_ID_1588:
3911                         if (number == 1)
3912                                 p->ieee_1588 = true;
3913                         i40e_debug(hw, I40E_DEBUG_INIT,
3914                                    "HW Capability: IEEE 1588 = %d\n",
3915                                    p->ieee_1588);
3916                         break;
3917                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3918                         p->fd = true;
3919                         p->fd_filters_guaranteed = number;
3920                         p->fd_filters_best_effort = logical_id;
3921                         i40e_debug(hw, I40E_DEBUG_INIT,
3922                                    "HW Capability: Flow Director = 1\n");
3923                         i40e_debug(hw, I40E_DEBUG_INIT,
3924                                    "HW Capability: Guaranteed FD filters = %d\n",
3925                                    p->fd_filters_guaranteed);
3926                         break;
3927                 case I40E_AQ_CAP_ID_WSR_PROT:
3928                         p->wr_csr_prot = (u64)number;
3929                         p->wr_csr_prot |= (u64)logical_id << 32;
3930                         i40e_debug(hw, I40E_DEBUG_INIT,
3931                                    "HW Capability: wr_csr_prot = 0x%llX\n\n",
3932                                    (p->wr_csr_prot & 0xffff));
3933                         break;
3934                 case I40E_AQ_CAP_ID_NVM_MGMT:
3935                         if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3936                                 p->sec_rev_disabled = true;
3937                         if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3938                                 p->update_disabled = true;
3939                         break;
3940                 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3941                         hw->num_wol_proxy_filters = (u16)number;
3942                         hw->wol_proxy_vsi_seid = (u16)logical_id;
3943                         p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3944                         if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3945                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3946                         else
3947                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3948                         p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3949                         i40e_debug(hw, I40E_DEBUG_INIT,
3950                                    "HW Capability: WOL proxy filters = %d\n",
3951                                    hw->num_wol_proxy_filters);
3952                         break;
3953                 default:
3954                         break;
3955                 }
3956         }
3957
3958         if (p->fcoe)
3959                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3960
3961         /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3962         p->fcoe = false;
3963
3964         /* count the enabled ports (aka the "not disabled" ports) */
3965         hw->num_ports = 0;
3966         for (i = 0; i < 4; i++) {
3967                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3968                 u64 port_cfg = 0;
3969
3970                 /* use AQ read to get the physical register offset instead
3971                  * of the port relative offset
3972                  */
3973                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3974                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3975                         hw->num_ports++;
3976         }
3977
3978         /* OCP cards case: if a mezz is removed the ethernet port is at
3979          * disabled state in PRTGEN_CNF register. Additional NVM read is
3980          * needed in order to check if we are dealing with OCP card.
3981          * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting
3982          * physical ports results in wrong partition id calculation and thus
3983          * not supporting WoL.
3984          */
3985         if (hw->mac.type == I40E_MAC_X722) {
3986                 if (i40e_acquire_nvm(hw, I40E_RESOURCE_READ) == I40E_SUCCESS) {
3987                         status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR,
3988                                                   2 * I40E_SR_OCP_CFG_WORD0,
3989                                                   sizeof(ocp_cfg_word0),
3990                                                   &ocp_cfg_word0, true, NULL);
3991                         if (status == I40E_SUCCESS &&
3992                             (ocp_cfg_word0 & I40E_SR_OCP_ENABLED))
3993                                 hw->num_ports = 4;
3994                         i40e_release_nvm(hw);
3995                 }
3996         }
3997
3998         valid_functions = p->valid_functions;
3999         num_functions = 0;
4000         while (valid_functions) {
4001                 if (valid_functions & 1)
4002                         num_functions++;
4003                 valid_functions >>= 1;
4004         }
4005
4006         /* partition id is 1-based, and functions are evenly spread
4007          * across the ports as partitions
4008          */
4009         if (hw->num_ports != 0) {
4010                 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
4011                 hw->num_partitions = num_functions / hw->num_ports;
4012         }
4013
4014         /* additional HW specific goodies that might
4015          * someday be HW version specific
4016          */
4017         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
4018 }
4019
4020 /**
4021  * i40e_aq_discover_capabilities
4022  * @hw: pointer to the hw struct
4023  * @buff: a virtual buffer to hold the capabilities
4024  * @buff_size: Size of the virtual buffer
4025  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
4026  * @list_type_opc: capabilities type to discover - pass in the command opcode
4027  * @cmd_details: pointer to command details structure or NULL
4028  *
4029  * Get the device capabilities descriptions from the firmware
4030  **/
4031 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
4032                                 void *buff, u16 buff_size, u16 *data_size,
4033                                 enum i40e_admin_queue_opc list_type_opc,
4034                                 struct i40e_asq_cmd_details *cmd_details)
4035 {
4036         struct i40e_aqc_list_capabilites *cmd;
4037         struct i40e_aq_desc desc;
4038         enum i40e_status_code status = I40E_SUCCESS;
4039
4040         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
4041
4042         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
4043                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
4044                 status = I40E_ERR_PARAM;
4045                 goto exit;
4046         }
4047
4048         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
4049
4050         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4051         if (buff_size > I40E_AQ_LARGE_BUF)
4052                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4053
4054         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4055         *data_size = LE16_TO_CPU(desc.datalen);
4056
4057         if (status)
4058                 goto exit;
4059
4060         i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
4061                                          list_type_opc);
4062
4063 exit:
4064         return status;
4065 }
4066
4067 /**
4068  * i40e_aq_update_nvm
4069  * @hw: pointer to the hw struct
4070  * @module_pointer: module pointer location in words from the NVM beginning
4071  * @offset: byte offset from the module beginning
4072  * @length: length of the section to be written (in bytes from the offset)
4073  * @data: command buffer (size [bytes] = length)
4074  * @last_command: tells if this is the last command in a series
4075  * @preservation_flags: Preservation mode flags
4076  * @cmd_details: pointer to command details structure or NULL
4077  *
4078  * Update the NVM using the admin queue commands
4079  **/
4080 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
4081                                 u32 offset, u16 length, void *data,
4082                                 bool last_command, u8 preservation_flags,
4083                                 struct i40e_asq_cmd_details *cmd_details)
4084 {
4085         struct i40e_aq_desc desc;
4086         struct i40e_aqc_nvm_update *cmd =
4087                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
4088         enum i40e_status_code status;
4089
4090         DEBUGFUNC("i40e_aq_update_nvm");
4091
4092         /* In offset the highest byte must be zeroed. */
4093         if (offset & 0xFF000000) {
4094                 status = I40E_ERR_PARAM;
4095                 goto i40e_aq_update_nvm_exit;
4096         }
4097
4098         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4099
4100         /* If this is the last command in a series, set the proper flag. */
4101         if (last_command)
4102                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
4103         if (hw->mac.type == I40E_MAC_X722) {
4104                 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED)
4105                         cmd->command_flags |=
4106                                 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED <<
4107                                  I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4108                 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL)
4109                         cmd->command_flags |=
4110                                 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL <<
4111                                  I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4112         }
4113         cmd->module_pointer = module_pointer;
4114         cmd->offset = CPU_TO_LE32(offset);
4115         cmd->length = CPU_TO_LE16(length);
4116
4117         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4118         if (length > I40E_AQ_LARGE_BUF)
4119                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4120
4121         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
4122
4123 i40e_aq_update_nvm_exit:
4124         return status;
4125 }
4126
4127 /**
4128  * i40e_aq_nvm_progress
4129  * @hw: pointer to the hw struct
4130  * @progress: pointer to progress returned from AQ
4131  * @cmd_details: pointer to command details structure or NULL
4132  *
4133  * Gets progress of flash rearrangement process
4134  **/
4135 enum i40e_status_code i40e_aq_nvm_progress(struct i40e_hw *hw, u8 *progress,
4136                                 struct i40e_asq_cmd_details *cmd_details)
4137 {
4138         enum i40e_status_code status;
4139         struct i40e_aq_desc desc;
4140
4141         DEBUGFUNC("i40e_aq_nvm_progress");
4142
4143         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_progress);
4144         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4145         *progress = desc.params.raw[0];
4146         return status;
4147 }
4148
4149 /**
4150  * i40e_aq_get_lldp_mib
4151  * @hw: pointer to the hw struct
4152  * @bridge_type: type of bridge requested
4153  * @mib_type: Local, Remote or both Local and Remote MIBs
4154  * @buff: pointer to a user supplied buffer to store the MIB block
4155  * @buff_size: size of the buffer (in bytes)
4156  * @local_len : length of the returned Local LLDP MIB
4157  * @remote_len: length of the returned Remote LLDP MIB
4158  * @cmd_details: pointer to command details structure or NULL
4159  *
4160  * Requests the complete LLDP MIB (entire packet).
4161  **/
4162 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4163                                 u8 mib_type, void *buff, u16 buff_size,
4164                                 u16 *local_len, u16 *remote_len,
4165                                 struct i40e_asq_cmd_details *cmd_details)
4166 {
4167         struct i40e_aq_desc desc;
4168         struct i40e_aqc_lldp_get_mib *cmd =
4169                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4170         struct i40e_aqc_lldp_get_mib *resp =
4171                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4172         enum i40e_status_code status;
4173
4174         if (buff_size == 0 || !buff)
4175                 return I40E_ERR_PARAM;
4176
4177         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4178         /* Indirect Command */
4179         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4180
4181         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4182         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4183                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4184
4185         desc.datalen = CPU_TO_LE16(buff_size);
4186
4187         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4188         if (buff_size > I40E_AQ_LARGE_BUF)
4189                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4190
4191         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4192         if (!status) {
4193                 if (local_len != NULL)
4194                         *local_len = LE16_TO_CPU(resp->local_len);
4195                 if (remote_len != NULL)
4196                         *remote_len = LE16_TO_CPU(resp->remote_len);
4197         }
4198
4199         return status;
4200 }
4201
4202  /**
4203  * i40e_aq_set_lldp_mib - Set the LLDP MIB
4204  * @hw: pointer to the hw struct
4205  * @mib_type: Local, Remote or both Local and Remote MIBs
4206  * @buff: pointer to a user supplied buffer to store the MIB block
4207  * @buff_size: size of the buffer (in bytes)
4208  * @cmd_details: pointer to command details structure or NULL
4209  *
4210  * Set the LLDP MIB.
4211  **/
4212 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4213                                 u8 mib_type, void *buff, u16 buff_size,
4214                                 struct i40e_asq_cmd_details *cmd_details)
4215 {
4216         struct i40e_aq_desc desc;
4217         struct i40e_aqc_lldp_set_local_mib *cmd =
4218                 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4219         enum i40e_status_code status;
4220
4221         if (buff_size == 0 || !buff)
4222                 return I40E_ERR_PARAM;
4223
4224         i40e_fill_default_direct_cmd_desc(&desc,
4225                                 i40e_aqc_opc_lldp_set_local_mib);
4226         /* Indirect Command */
4227         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4228         if (buff_size > I40E_AQ_LARGE_BUF)
4229                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4230         desc.datalen = CPU_TO_LE16(buff_size);
4231
4232         cmd->type = mib_type;
4233         cmd->length = CPU_TO_LE16(buff_size);
4234         cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4235         cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4236
4237         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4238         return status;
4239 }
4240
4241 /**
4242  * i40e_aq_cfg_lldp_mib_change_event
4243  * @hw: pointer to the hw struct
4244  * @enable_update: Enable or Disable event posting
4245  * @cmd_details: pointer to command details structure or NULL
4246  *
4247  * Enable or Disable posting of an event on ARQ when LLDP MIB
4248  * associated with the interface changes
4249  **/
4250 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4251                                 bool enable_update,
4252                                 struct i40e_asq_cmd_details *cmd_details)
4253 {
4254         struct i40e_aq_desc desc;
4255         struct i40e_aqc_lldp_update_mib *cmd =
4256                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4257         enum i40e_status_code status;
4258
4259         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4260
4261         if (!enable_update)
4262                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4263
4264         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4265
4266         return status;
4267 }
4268
4269 /**
4270  * i40e_aq_add_lldp_tlv
4271  * @hw: pointer to the hw struct
4272  * @bridge_type: type of bridge
4273  * @buff: buffer with TLV to add
4274  * @buff_size: length of the buffer
4275  * @tlv_len: length of the TLV to be added
4276  * @mib_len: length of the LLDP MIB returned in response
4277  * @cmd_details: pointer to command details structure or NULL
4278  *
4279  * Add the specified TLV to LLDP Local MIB for the given bridge type,
4280  * it is responsibility of the caller to make sure that the TLV is not
4281  * already present in the LLDPDU.
4282  * In return firmware will write the complete LLDP MIB with the newly
4283  * added TLV in the response buffer.
4284  **/
4285 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4286                                 void *buff, u16 buff_size, u16 tlv_len,
4287                                 u16 *mib_len,
4288                                 struct i40e_asq_cmd_details *cmd_details)
4289 {
4290         struct i40e_aq_desc desc;
4291         struct i40e_aqc_lldp_add_tlv *cmd =
4292                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4293         enum i40e_status_code status;
4294
4295         if (buff_size == 0 || !buff || tlv_len == 0)
4296                 return I40E_ERR_PARAM;
4297
4298         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4299
4300         /* Indirect Command */
4301         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4302         if (buff_size > I40E_AQ_LARGE_BUF)
4303                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4304         desc.datalen = CPU_TO_LE16(buff_size);
4305
4306         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4307                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4308         cmd->len = CPU_TO_LE16(tlv_len);
4309
4310         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4311         if (!status) {
4312                 if (mib_len != NULL)
4313                         *mib_len = LE16_TO_CPU(desc.datalen);
4314         }
4315
4316         return status;
4317 }
4318
4319 /**
4320  * i40e_aq_update_lldp_tlv
4321  * @hw: pointer to the hw struct
4322  * @bridge_type: type of bridge
4323  * @buff: buffer with TLV to update
4324  * @buff_size: size of the buffer holding original and updated TLVs
4325  * @old_len: Length of the Original TLV
4326  * @new_len: Length of the Updated TLV
4327  * @offset: offset of the updated TLV in the buff
4328  * @mib_len: length of the returned LLDP MIB
4329  * @cmd_details: pointer to command details structure or NULL
4330  *
4331  * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4332  * Firmware will place the complete LLDP MIB in response buffer with the
4333  * updated TLV.
4334  **/
4335 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4336                                 u8 bridge_type, void *buff, u16 buff_size,
4337                                 u16 old_len, u16 new_len, u16 offset,
4338                                 u16 *mib_len,
4339                                 struct i40e_asq_cmd_details *cmd_details)
4340 {
4341         struct i40e_aq_desc desc;
4342         struct i40e_aqc_lldp_update_tlv *cmd =
4343                 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4344         enum i40e_status_code status;
4345
4346         if (buff_size == 0 || !buff || offset == 0 ||
4347             old_len == 0 || new_len == 0)
4348                 return I40E_ERR_PARAM;
4349
4350         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4351
4352         /* Indirect Command */
4353         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4354         if (buff_size > I40E_AQ_LARGE_BUF)
4355                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4356         desc.datalen = CPU_TO_LE16(buff_size);
4357
4358         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4359                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4360         cmd->old_len = CPU_TO_LE16(old_len);
4361         cmd->new_offset = CPU_TO_LE16(offset);
4362         cmd->new_len = CPU_TO_LE16(new_len);
4363
4364         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4365         if (!status) {
4366                 if (mib_len != NULL)
4367                         *mib_len = LE16_TO_CPU(desc.datalen);
4368         }
4369
4370         return status;
4371 }
4372
4373 /**
4374  * i40e_aq_delete_lldp_tlv
4375  * @hw: pointer to the hw struct
4376  * @bridge_type: type of bridge
4377  * @buff: pointer to a user supplied buffer that has the TLV
4378  * @buff_size: length of the buffer
4379  * @tlv_len: length of the TLV to be deleted
4380  * @mib_len: length of the returned LLDP MIB
4381  * @cmd_details: pointer to command details structure or NULL
4382  *
4383  * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4384  * The firmware places the entire LLDP MIB in the response buffer.
4385  **/
4386 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4387                                 u8 bridge_type, void *buff, u16 buff_size,
4388                                 u16 tlv_len, u16 *mib_len,
4389                                 struct i40e_asq_cmd_details *cmd_details)
4390 {
4391         struct i40e_aq_desc desc;
4392         struct i40e_aqc_lldp_add_tlv *cmd =
4393                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4394         enum i40e_status_code status;
4395
4396         if (buff_size == 0 || !buff)
4397                 return I40E_ERR_PARAM;
4398
4399         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4400
4401         /* Indirect Command */
4402         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4403         if (buff_size > I40E_AQ_LARGE_BUF)
4404                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4405         desc.datalen = CPU_TO_LE16(buff_size);
4406         cmd->len = CPU_TO_LE16(tlv_len);
4407         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4408                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4409
4410         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4411         if (!status) {
4412                 if (mib_len != NULL)
4413                         *mib_len = LE16_TO_CPU(desc.datalen);
4414         }
4415
4416         return status;
4417 }
4418
4419 /**
4420  * i40e_aq_stop_lldp
4421  * @hw: pointer to the hw struct
4422  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4423  * @cmd_details: pointer to command details structure or NULL
4424  *
4425  * Stop or Shutdown the embedded LLDP Agent
4426  **/
4427 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4428                                 struct i40e_asq_cmd_details *cmd_details)
4429 {
4430         struct i40e_aq_desc desc;
4431         struct i40e_aqc_lldp_stop *cmd =
4432                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4433         enum i40e_status_code status;
4434
4435         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4436
4437         if (shutdown_agent)
4438                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4439
4440         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4441
4442         return status;
4443 }
4444
4445 /**
4446  * i40e_aq_start_lldp
4447  * @hw: pointer to the hw struct
4448  * @cmd_details: pointer to command details structure or NULL
4449  *
4450  * Start the embedded LLDP Agent on all ports.
4451  **/
4452 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4453                                 struct i40e_asq_cmd_details *cmd_details)
4454 {
4455         struct i40e_aq_desc desc;
4456         struct i40e_aqc_lldp_start *cmd =
4457                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4458         enum i40e_status_code status;
4459
4460         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4461
4462         cmd->command = I40E_AQ_LLDP_AGENT_START;
4463         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4464
4465         return status;
4466 }
4467
4468 /**
4469  * i40e_aq_set_dcb_parameters
4470  * @hw: pointer to the hw struct
4471  * @cmd_details: pointer to command details structure or NULL
4472  * @dcb_enable: True if DCB configuration needs to be applied
4473  *
4474  **/
4475 enum i40e_status_code
4476 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable,
4477                            struct i40e_asq_cmd_details *cmd_details)
4478 {
4479         struct i40e_aq_desc desc;
4480         struct i40e_aqc_set_dcb_parameters *cmd =
4481                 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw;
4482         enum i40e_status_code status;
4483
4484         i40e_fill_default_direct_cmd_desc(&desc,
4485                                           i40e_aqc_opc_set_dcb_parameters);
4486
4487         if (dcb_enable) {
4488                 cmd->valid_flags = I40E_DCB_VALID;
4489                 cmd->command = I40E_AQ_DCB_SET_AGENT;
4490         }
4491         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4492
4493         return status;
4494 }
4495
4496 /**
4497  * i40e_aq_get_cee_dcb_config
4498  * @hw: pointer to the hw struct
4499  * @buff: response buffer that stores CEE operational configuration
4500  * @buff_size: size of the buffer passed
4501  * @cmd_details: pointer to command details structure or NULL
4502  *
4503  * Get CEE DCBX mode operational configuration from firmware
4504  **/
4505 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4506                                 void *buff, u16 buff_size,
4507                                 struct i40e_asq_cmd_details *cmd_details)
4508 {
4509         struct i40e_aq_desc desc;
4510         enum i40e_status_code status;
4511
4512         if (buff_size == 0 || !buff)
4513                 return I40E_ERR_PARAM;
4514
4515         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4516
4517         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4518         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4519                                        cmd_details);
4520
4521         return status;
4522 }
4523
4524 /**
4525  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4526  * @hw: pointer to the hw struct
4527  * @start_agent: True if DCBx Agent needs to be Started
4528  *                              False if DCBx Agent needs to be Stopped
4529  * @cmd_details: pointer to command details structure or NULL
4530  *
4531  * Start/Stop the embedded dcbx Agent
4532  **/
4533 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4534                                 bool start_agent,
4535                                 struct i40e_asq_cmd_details *cmd_details)
4536 {
4537         struct i40e_aq_desc desc;
4538         struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4539                 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4540                                 &desc.params.raw;
4541         enum i40e_status_code status;
4542
4543         i40e_fill_default_direct_cmd_desc(&desc,
4544                                 i40e_aqc_opc_lldp_stop_start_spec_agent);
4545
4546         if (start_agent)
4547                 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4548
4549         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4550
4551         return status;
4552 }
4553
4554 /**
4555  * i40e_aq_add_udp_tunnel
4556  * @hw: pointer to the hw struct
4557  * @udp_port: the UDP port to add in Host byte order
4558  * @protocol_index: protocol index type
4559  * @filter_index: pointer to filter index
4560  * @cmd_details: pointer to command details structure or NULL
4561  *
4562  * Note: Firmware expects the udp_port value to be in Little Endian format,
4563  * and this function will call CPU_TO_LE16 to convert from Host byte order to
4564  * Little Endian order.
4565  **/
4566 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4567                                 u16 udp_port, u8 protocol_index,
4568                                 u8 *filter_index,
4569                                 struct i40e_asq_cmd_details *cmd_details)
4570 {
4571         struct i40e_aq_desc desc;
4572         struct i40e_aqc_add_udp_tunnel *cmd =
4573                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4574         struct i40e_aqc_del_udp_tunnel_completion *resp =
4575                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4576         enum i40e_status_code status;
4577
4578         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4579
4580         cmd->udp_port = CPU_TO_LE16(udp_port);
4581         cmd->protocol_type = protocol_index;
4582
4583         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4584
4585         if (!status && filter_index)
4586                 *filter_index = resp->index;
4587
4588         return status;
4589 }
4590
4591 /**
4592  * i40e_aq_del_udp_tunnel
4593  * @hw: pointer to the hw struct
4594  * @index: filter index
4595  * @cmd_details: pointer to command details structure or NULL
4596  **/
4597 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4598                                 struct i40e_asq_cmd_details *cmd_details)
4599 {
4600         struct i40e_aq_desc desc;
4601         struct i40e_aqc_remove_udp_tunnel *cmd =
4602                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4603         enum i40e_status_code status;
4604
4605         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4606
4607         cmd->index = index;
4608
4609         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4610
4611         return status;
4612 }
4613
4614 /**
4615  * i40e_aq_get_switch_resource_alloc (0x0204)
4616  * @hw: pointer to the hw struct
4617  * @num_entries: pointer to u8 to store the number of resource entries returned
4618  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
4619  *        to store the resource information for all resource types.  Each
4620  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
4621  * @count: size, in bytes, of the buffer provided
4622  * @cmd_details: pointer to command details structure or NULL
4623  *
4624  * Query the resources allocated to a function.
4625  **/
4626 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4627                         u8 *num_entries,
4628                         struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4629                         u16 count,
4630                         struct i40e_asq_cmd_details *cmd_details)
4631 {
4632         struct i40e_aq_desc desc;
4633         struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4634                 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4635         enum i40e_status_code status;
4636         u16 length = count * sizeof(*buf);
4637
4638         i40e_fill_default_direct_cmd_desc(&desc,
4639                                         i40e_aqc_opc_get_switch_resource_alloc);
4640
4641         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4642         if (length > I40E_AQ_LARGE_BUF)
4643                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4644
4645         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4646
4647         if (!status && num_entries)
4648                 *num_entries = cmd_resp->num_entries;
4649
4650         return status;
4651 }
4652
4653 /**
4654  * i40e_aq_delete_element - Delete switch element
4655  * @hw: pointer to the hw struct
4656  * @seid: the SEID to delete from the switch
4657  * @cmd_details: pointer to command details structure or NULL
4658  *
4659  * This deletes a switch element from the switch.
4660  **/
4661 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4662                                 struct i40e_asq_cmd_details *cmd_details)
4663 {
4664         struct i40e_aq_desc desc;
4665         struct i40e_aqc_switch_seid *cmd =
4666                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4667         enum i40e_status_code status;
4668
4669         if (seid == 0)
4670                 return I40E_ERR_PARAM;
4671
4672         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4673
4674         cmd->seid = CPU_TO_LE16(seid);
4675
4676         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4677
4678         return status;
4679 }
4680
4681 /**
4682  * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4683  * @hw: pointer to the hw struct
4684  * @flags: component flags
4685  * @mac_seid: uplink seid (MAC SEID)
4686  * @vsi_seid: connected vsi seid
4687  * @ret_seid: seid of create pv component
4688  *
4689  * This instantiates an i40e port virtualizer with specified flags.
4690  * Depending on specified flags the port virtualizer can act as a
4691  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4692  */
4693 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4694                                        u16 mac_seid, u16 vsi_seid,
4695                                        u16 *ret_seid)
4696 {
4697         struct i40e_aq_desc desc;
4698         struct i40e_aqc_add_update_pv *cmd =
4699                 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4700         struct i40e_aqc_add_update_pv_completion *resp =
4701                 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4702         enum i40e_status_code status;
4703
4704         if (vsi_seid == 0)
4705                 return I40E_ERR_PARAM;
4706
4707         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4708         cmd->command_flags = CPU_TO_LE16(flags);
4709         cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4710         cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4711
4712         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4713         if (!status && ret_seid)
4714                 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4715
4716         return status;
4717 }
4718
4719 /**
4720  * i40e_aq_add_tag - Add an S/E-tag
4721  * @hw: pointer to the hw struct
4722  * @direct_to_queue: should s-tag direct flow to a specific queue
4723  * @vsi_seid: VSI SEID to use this tag
4724  * @tag: value of the tag
4725  * @queue_num: queue number, only valid is direct_to_queue is true
4726  * @tags_used: return value, number of tags in use by this PF
4727  * @tags_free: return value, number of unallocated tags
4728  * @cmd_details: pointer to command details structure or NULL
4729  *
4730  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4731  * the number of tags allocated by the PF, and the number of unallocated
4732  * tags available.
4733  **/
4734 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4735                                 u16 vsi_seid, u16 tag, u16 queue_num,
4736                                 u16 *tags_used, u16 *tags_free,
4737                                 struct i40e_asq_cmd_details *cmd_details)
4738 {
4739         struct i40e_aq_desc desc;
4740         struct i40e_aqc_add_tag *cmd =
4741                 (struct i40e_aqc_add_tag *)&desc.params.raw;
4742         struct i40e_aqc_add_remove_tag_completion *resp =
4743                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4744         enum i40e_status_code status;
4745
4746         if (vsi_seid == 0)
4747                 return I40E_ERR_PARAM;
4748
4749         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4750
4751         cmd->seid = CPU_TO_LE16(vsi_seid);
4752         cmd->tag = CPU_TO_LE16(tag);
4753         if (direct_to_queue) {
4754                 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4755                 cmd->queue_number = CPU_TO_LE16(queue_num);
4756         }
4757
4758         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4759
4760         if (!status) {
4761                 if (tags_used != NULL)
4762                         *tags_used = LE16_TO_CPU(resp->tags_used);
4763                 if (tags_free != NULL)
4764                         *tags_free = LE16_TO_CPU(resp->tags_free);
4765         }
4766
4767         return status;
4768 }
4769
4770 /**
4771  * i40e_aq_remove_tag - Remove an S- or E-tag
4772  * @hw: pointer to the hw struct
4773  * @vsi_seid: VSI SEID this tag is associated with
4774  * @tag: value of the S-tag to delete
4775  * @tags_used: return value, number of tags in use by this PF
4776  * @tags_free: return value, number of unallocated tags
4777  * @cmd_details: pointer to command details structure or NULL
4778  *
4779  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4780  * the number of tags allocated by the PF, and the number of unallocated
4781  * tags available.
4782  **/
4783 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4784                                 u16 tag, u16 *tags_used, u16 *tags_free,
4785                                 struct i40e_asq_cmd_details *cmd_details)
4786 {
4787         struct i40e_aq_desc desc;
4788         struct i40e_aqc_remove_tag *cmd =
4789                 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4790         struct i40e_aqc_add_remove_tag_completion *resp =
4791                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4792         enum i40e_status_code status;
4793
4794         if (vsi_seid == 0)
4795                 return I40E_ERR_PARAM;
4796
4797         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4798
4799         cmd->seid = CPU_TO_LE16(vsi_seid);
4800         cmd->tag = CPU_TO_LE16(tag);
4801
4802         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4803
4804         if (!status) {
4805                 if (tags_used != NULL)
4806                         *tags_used = LE16_TO_CPU(resp->tags_used);
4807                 if (tags_free != NULL)
4808                         *tags_free = LE16_TO_CPU(resp->tags_free);
4809         }
4810
4811         return status;
4812 }
4813
4814 /**
4815  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4816  * @hw: pointer to the hw struct
4817  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4818  * @etag: value of E-tag to add
4819  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4820  * @buf: address of indirect buffer
4821  * @tags_used: return value, number of E-tags in use by this port
4822  * @tags_free: return value, number of unallocated M-tags
4823  * @cmd_details: pointer to command details structure or NULL
4824  *
4825  * This associates a multicast E-tag to a port virtualizer.  It will return
4826  * the number of tags allocated by the PF, and the number of unallocated
4827  * tags available.
4828  *
4829  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4830  * num_tags_in_buf long.
4831  **/
4832 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4833                                 u16 etag, u8 num_tags_in_buf, void *buf,
4834                                 u16 *tags_used, u16 *tags_free,
4835                                 struct i40e_asq_cmd_details *cmd_details)
4836 {
4837         struct i40e_aq_desc desc;
4838         struct i40e_aqc_add_remove_mcast_etag *cmd =
4839                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4840         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4841            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4842         enum i40e_status_code status;
4843         u16 length = sizeof(u16) * num_tags_in_buf;
4844
4845         if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4846                 return I40E_ERR_PARAM;
4847
4848         i40e_fill_default_direct_cmd_desc(&desc,
4849                                           i40e_aqc_opc_add_multicast_etag);
4850
4851         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4852         cmd->etag = CPU_TO_LE16(etag);
4853         cmd->num_unicast_etags = num_tags_in_buf;
4854
4855         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4856         if (length > I40E_AQ_LARGE_BUF)
4857                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4858
4859         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4860
4861         if (!status) {
4862                 if (tags_used != NULL)
4863                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4864                 if (tags_free != NULL)
4865                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4866         }
4867
4868         return status;
4869 }
4870
4871 /**
4872  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4873  * @hw: pointer to the hw struct
4874  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4875  * @etag: value of the E-tag to remove
4876  * @tags_used: return value, number of tags in use by this port
4877  * @tags_free: return value, number of unallocated tags
4878  * @cmd_details: pointer to command details structure or NULL
4879  *
4880  * This deletes an E-tag from the port virtualizer.  It will return
4881  * the number of tags allocated by the port, and the number of unallocated
4882  * tags available.
4883  **/
4884 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4885                                 u16 etag, u16 *tags_used, u16 *tags_free,
4886                                 struct i40e_asq_cmd_details *cmd_details)
4887 {
4888         struct i40e_aq_desc desc;
4889         struct i40e_aqc_add_remove_mcast_etag *cmd =
4890                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4891         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4892            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4893         enum i40e_status_code status;
4894
4895
4896         if (pv_seid == 0)
4897                 return I40E_ERR_PARAM;
4898
4899         i40e_fill_default_direct_cmd_desc(&desc,
4900                                           i40e_aqc_opc_remove_multicast_etag);
4901
4902         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4903         cmd->etag = CPU_TO_LE16(etag);
4904
4905         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4906
4907         if (!status) {
4908                 if (tags_used != NULL)
4909                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4910                 if (tags_free != NULL)
4911                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4912         }
4913
4914         return status;
4915 }
4916
4917 /**
4918  * i40e_aq_update_tag - Update an S/E-tag
4919  * @hw: pointer to the hw struct
4920  * @vsi_seid: VSI SEID using this S-tag
4921  * @old_tag: old tag value
4922  * @new_tag: new tag value
4923  * @tags_used: return value, number of tags in use by this PF
4924  * @tags_free: return value, number of unallocated tags
4925  * @cmd_details: pointer to command details structure or NULL
4926  *
4927  * This updates the value of the tag currently attached to this VSI
4928  * in the switch complex.  It will return the number of tags allocated
4929  * by the PF, and the number of unallocated tags available.
4930  **/
4931 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4932                                 u16 old_tag, u16 new_tag, u16 *tags_used,
4933                                 u16 *tags_free,
4934                                 struct i40e_asq_cmd_details *cmd_details)
4935 {
4936         struct i40e_aq_desc desc;
4937         struct i40e_aqc_update_tag *cmd =
4938                 (struct i40e_aqc_update_tag *)&desc.params.raw;
4939         struct i40e_aqc_update_tag_completion *resp =
4940                 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4941         enum i40e_status_code status;
4942
4943         if (vsi_seid == 0)
4944                 return I40E_ERR_PARAM;
4945
4946         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4947
4948         cmd->seid = CPU_TO_LE16(vsi_seid);
4949         cmd->old_tag = CPU_TO_LE16(old_tag);
4950         cmd->new_tag = CPU_TO_LE16(new_tag);
4951
4952         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4953
4954         if (!status) {
4955                 if (tags_used != NULL)
4956                         *tags_used = LE16_TO_CPU(resp->tags_used);
4957                 if (tags_free != NULL)
4958                         *tags_free = LE16_TO_CPU(resp->tags_free);
4959         }
4960
4961         return status;
4962 }
4963
4964 /**
4965  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4966  * @hw: pointer to the hw struct
4967  * @tcmap: TC map for request/release any ignore PFC condition
4968  * @request: request or release ignore PFC condition
4969  * @tcmap_ret: return TCs for which PFC is currently ignored
4970  * @cmd_details: pointer to command details structure or NULL
4971  *
4972  * This sends out request/release to ignore PFC condition for a TC.
4973  * It will return the TCs for which PFC is currently ignored.
4974  **/
4975 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4976                                 bool request, u8 *tcmap_ret,
4977                                 struct i40e_asq_cmd_details *cmd_details)
4978 {
4979         struct i40e_aq_desc desc;
4980         struct i40e_aqc_pfc_ignore *cmd_resp =
4981                 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4982         enum i40e_status_code status;
4983
4984         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4985
4986         if (request)
4987                 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4988
4989         cmd_resp->tc_bitmap = tcmap;
4990
4991         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4992
4993         if (!status) {
4994                 if (tcmap_ret != NULL)
4995                         *tcmap_ret = cmd_resp->tc_bitmap;
4996         }
4997
4998         return status;
4999 }
5000
5001 /**
5002  * i40e_aq_dcb_updated - DCB Updated Command
5003  * @hw: pointer to the hw struct
5004  * @cmd_details: pointer to command details structure or NULL
5005  *
5006  * When LLDP is handled in PF this command is used by the PF
5007  * to notify EMP that a DCB setting is modified.
5008  * When LLDP is handled in EMP this command is used by the PF
5009  * to notify EMP whenever one of the following parameters get
5010  * modified:
5011  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
5012  *   - PCIRTT in PRTDCB_GENC.PCIRTT
5013  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
5014  * EMP will return when the shared RPB settings have been
5015  * recomputed and modified. The retval field in the descriptor
5016  * will be set to 0 when RPB is modified.
5017  **/
5018 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
5019                                 struct i40e_asq_cmd_details *cmd_details)
5020 {
5021         struct i40e_aq_desc desc;
5022         enum i40e_status_code status;
5023
5024         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
5025
5026         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5027
5028         return status;
5029 }
5030
5031 /**
5032  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
5033  * @hw: pointer to the hw struct
5034  * @seid: defines the SEID of the switch for which the stats are requested
5035  * @vlan_id: the VLAN ID for which the statistics are requested
5036  * @stat_index: index of the statistics counters block assigned to this VLAN
5037  * @cmd_details: pointer to command details structure or NULL
5038  *
5039  * XL710 supports 128 smonVlanStats counters.This command is used to
5040  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
5041  * switch.
5042  **/
5043 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
5044                                 u16 vlan_id, u16 *stat_index,
5045                                 struct i40e_asq_cmd_details *cmd_details)
5046 {
5047         struct i40e_aq_desc desc;
5048         struct i40e_aqc_add_remove_statistics *cmd_resp =
5049                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5050         enum i40e_status_code status;
5051
5052         if ((seid == 0) || (stat_index == NULL))
5053                 return I40E_ERR_PARAM;
5054
5055         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
5056
5057         cmd_resp->seid = CPU_TO_LE16(seid);
5058         cmd_resp->vlan = CPU_TO_LE16(vlan_id);
5059
5060         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5061
5062         if (!status && stat_index)
5063                 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
5064
5065         return status;
5066 }
5067
5068 /**
5069  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
5070  * @hw: pointer to the hw struct
5071  * @seid: defines the SEID of the switch for which the stats are requested
5072  * @vlan_id: the VLAN ID for which the statistics are requested
5073  * @stat_index: index of the statistics counters block assigned to this VLAN
5074  * @cmd_details: pointer to command details structure or NULL
5075  *
5076  * XL710 supports 128 smonVlanStats counters.This command is used to
5077  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
5078  * switch.
5079  **/
5080 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
5081                                 u16 vlan_id, u16 stat_index,
5082                                 struct i40e_asq_cmd_details *cmd_details)
5083 {
5084         struct i40e_aq_desc desc;
5085         struct i40e_aqc_add_remove_statistics *cmd =
5086                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5087         enum i40e_status_code status;
5088
5089         if (seid == 0)
5090                 return I40E_ERR_PARAM;
5091
5092         i40e_fill_default_direct_cmd_desc(&desc,
5093                                           i40e_aqc_opc_remove_statistics);
5094
5095         cmd->seid = CPU_TO_LE16(seid);
5096         cmd->vlan  = CPU_TO_LE16(vlan_id);
5097         cmd->stat_index = CPU_TO_LE16(stat_index);
5098
5099         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5100
5101         return status;
5102 }
5103
5104 /**
5105  * i40e_aq_set_port_parameters - set physical port parameters.
5106  * @hw: pointer to the hw struct
5107  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
5108  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
5109  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
5110  * @double_vlan: if set double VLAN is enabled
5111  * @cmd_details: pointer to command details structure or NULL
5112  **/
5113 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
5114                                 u16 bad_frame_vsi, bool save_bad_pac,
5115                                 bool pad_short_pac, bool double_vlan,
5116                                 struct i40e_asq_cmd_details *cmd_details)
5117 {
5118         struct i40e_aqc_set_port_parameters *cmd;
5119         enum i40e_status_code status;
5120         struct i40e_aq_desc desc;
5121         u16 command_flags = 0;
5122
5123         cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
5124
5125         i40e_fill_default_direct_cmd_desc(&desc,
5126                                           i40e_aqc_opc_set_port_parameters);
5127
5128         cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
5129         if (save_bad_pac)
5130                 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
5131         if (pad_short_pac)
5132                 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
5133         if (double_vlan)
5134                 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
5135         cmd->command_flags = CPU_TO_LE16(command_flags);
5136
5137         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5138
5139         return status;
5140 }
5141
5142 /**
5143  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
5144  * @hw: pointer to the hw struct
5145  * @seid: seid for the physical port/switching component/vsi
5146  * @buff: Indirect buffer to hold data parameters and response
5147  * @buff_size: Indirect buffer size
5148  * @opcode: Tx scheduler AQ command opcode
5149  * @cmd_details: pointer to command details structure or NULL
5150  *
5151  * Generic command handler for Tx scheduler AQ commands
5152  **/
5153 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
5154                                 void *buff, u16 buff_size,
5155                                  enum i40e_admin_queue_opc opcode,
5156                                 struct i40e_asq_cmd_details *cmd_details)
5157 {
5158         struct i40e_aq_desc desc;
5159         struct i40e_aqc_tx_sched_ind *cmd =
5160                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
5161         enum i40e_status_code status;
5162         bool cmd_param_flag = false;
5163
5164         switch (opcode) {
5165         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
5166         case i40e_aqc_opc_configure_vsi_tc_bw:
5167         case i40e_aqc_opc_enable_switching_comp_ets:
5168         case i40e_aqc_opc_modify_switching_comp_ets:
5169         case i40e_aqc_opc_disable_switching_comp_ets:
5170         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
5171         case i40e_aqc_opc_configure_switching_comp_bw_config:
5172                 cmd_param_flag = true;
5173                 break;
5174         case i40e_aqc_opc_query_vsi_bw_config:
5175         case i40e_aqc_opc_query_vsi_ets_sla_config:
5176         case i40e_aqc_opc_query_switching_comp_ets_config:
5177         case i40e_aqc_opc_query_port_ets_config:
5178         case i40e_aqc_opc_query_switching_comp_bw_config:
5179                 cmd_param_flag = false;
5180                 break;
5181         default:
5182                 return I40E_ERR_PARAM;
5183         }
5184
5185         i40e_fill_default_direct_cmd_desc(&desc, opcode);
5186
5187         /* Indirect command */
5188         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5189         if (cmd_param_flag)
5190                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5191         if (buff_size > I40E_AQ_LARGE_BUF)
5192                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5193
5194         desc.datalen = CPU_TO_LE16(buff_size);
5195
5196         cmd->vsi_seid = CPU_TO_LE16(seid);
5197
5198         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5199
5200         return status;
5201 }
5202
5203 /**
5204  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5205  * @hw: pointer to the hw struct
5206  * @seid: VSI seid
5207  * @credit: BW limit credits (0 = disabled)
5208  * @max_credit: Max BW limit credits
5209  * @cmd_details: pointer to command details structure or NULL
5210  **/
5211 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5212                                 u16 seid, u16 credit, u8 max_credit,
5213                                 struct i40e_asq_cmd_details *cmd_details)
5214 {
5215         struct i40e_aq_desc desc;
5216         struct i40e_aqc_configure_vsi_bw_limit *cmd =
5217                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5218         enum i40e_status_code status;
5219
5220         i40e_fill_default_direct_cmd_desc(&desc,
5221                                           i40e_aqc_opc_configure_vsi_bw_limit);
5222
5223         cmd->vsi_seid = CPU_TO_LE16(seid);
5224         cmd->credit = CPU_TO_LE16(credit);
5225         cmd->max_credit = max_credit;
5226
5227         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5228
5229         return status;
5230 }
5231
5232 /**
5233  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5234  * @hw: pointer to the hw struct
5235  * @seid: switching component seid
5236  * @credit: BW limit credits (0 = disabled)
5237  * @max_bw: Max BW limit credits
5238  * @cmd_details: pointer to command details structure or NULL
5239  **/
5240 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5241                                 u16 seid, u16 credit, u8 max_bw,
5242                                 struct i40e_asq_cmd_details *cmd_details)
5243 {
5244         struct i40e_aq_desc desc;
5245         struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5246           (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5247         enum i40e_status_code status;
5248
5249         i40e_fill_default_direct_cmd_desc(&desc,
5250                                 i40e_aqc_opc_configure_switching_comp_bw_limit);
5251
5252         cmd->seid = CPU_TO_LE16(seid);
5253         cmd->credit = CPU_TO_LE16(credit);
5254         cmd->max_bw = max_bw;
5255
5256         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5257
5258         return status;
5259 }
5260
5261 /**
5262  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5263  * @hw: pointer to the hw struct
5264  * @seid: VSI seid
5265  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5266  * @cmd_details: pointer to command details structure or NULL
5267  **/
5268 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5269                         u16 seid,
5270                         struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5271                         struct i40e_asq_cmd_details *cmd_details)
5272 {
5273         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5274                                     i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5275                                     cmd_details);
5276 }
5277
5278 /**
5279  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5280  * @hw: pointer to the hw struct
5281  * @seid: VSI seid
5282  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5283  * @cmd_details: pointer to command details structure or NULL
5284  **/
5285 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5286                         u16 seid,
5287                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5288                         struct i40e_asq_cmd_details *cmd_details)
5289 {
5290         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5291                                     i40e_aqc_opc_configure_vsi_tc_bw,
5292                                     cmd_details);
5293 }
5294
5295 /**
5296  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5297  * @hw: pointer to the hw struct
5298  * @seid: seid of the switching component connected to Physical Port
5299  * @ets_data: Buffer holding ETS parameters
5300  * @opcode: Tx scheduler AQ command opcode
5301  * @cmd_details: pointer to command details structure or NULL
5302  **/
5303 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5304                 u16 seid,
5305                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5306                 enum i40e_admin_queue_opc opcode,
5307                 struct i40e_asq_cmd_details *cmd_details)
5308 {
5309         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5310                                     sizeof(*ets_data), opcode, cmd_details);
5311 }
5312
5313 /**
5314  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5315  * @hw: pointer to the hw struct
5316  * @seid: seid of the switching component
5317  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5318  * @cmd_details: pointer to command details structure or NULL
5319  **/
5320 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5321         u16 seid,
5322         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5323         struct i40e_asq_cmd_details *cmd_details)
5324 {
5325         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5326                             i40e_aqc_opc_configure_switching_comp_bw_config,
5327                             cmd_details);
5328 }
5329
5330 /**
5331  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5332  * @hw: pointer to the hw struct
5333  * @seid: seid of the switching component
5334  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5335  * @cmd_details: pointer to command details structure or NULL
5336  **/
5337 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5338         struct i40e_hw *hw, u16 seid,
5339         struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5340         struct i40e_asq_cmd_details *cmd_details)
5341 {
5342         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5343                             i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5344                             cmd_details);
5345 }
5346
5347 /**
5348  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5349  * @hw: pointer to the hw struct
5350  * @seid: seid of the VSI
5351  * @bw_data: Buffer to hold VSI BW configuration
5352  * @cmd_details: pointer to command details structure or NULL
5353  **/
5354 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5355                         u16 seid,
5356                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5357                         struct i40e_asq_cmd_details *cmd_details)
5358 {
5359         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5360                                     i40e_aqc_opc_query_vsi_bw_config,
5361                                     cmd_details);
5362 }
5363
5364 /**
5365  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5366  * @hw: pointer to the hw struct
5367  * @seid: seid of the VSI
5368  * @bw_data: Buffer to hold VSI BW configuration per TC
5369  * @cmd_details: pointer to command details structure or NULL
5370  **/
5371 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5372                         u16 seid,
5373                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5374                         struct i40e_asq_cmd_details *cmd_details)
5375 {
5376         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5377                                     i40e_aqc_opc_query_vsi_ets_sla_config,
5378                                     cmd_details);
5379 }
5380
5381 /**
5382  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5383  * @hw: pointer to the hw struct
5384  * @seid: seid of the switching component
5385  * @bw_data: Buffer to hold switching component's per TC BW config
5386  * @cmd_details: pointer to command details structure or NULL
5387  **/
5388 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5389                 u16 seid,
5390                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5391                 struct i40e_asq_cmd_details *cmd_details)
5392 {
5393         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5394                                    i40e_aqc_opc_query_switching_comp_ets_config,
5395                                    cmd_details);
5396 }
5397
5398 /**
5399  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5400  * @hw: pointer to the hw struct
5401  * @seid: seid of the VSI or switching component connected to Physical Port
5402  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5403  * @cmd_details: pointer to command details structure or NULL
5404  **/
5405 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5406                         u16 seid,
5407                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
5408                         struct i40e_asq_cmd_details *cmd_details)
5409 {
5410         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5411                                     i40e_aqc_opc_query_port_ets_config,
5412                                     cmd_details);
5413 }
5414
5415 /**
5416  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5417  * @hw: pointer to the hw struct
5418  * @seid: seid of the switching component
5419  * @bw_data: Buffer to hold switching component's BW configuration
5420  * @cmd_details: pointer to command details structure or NULL
5421  **/
5422 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5423                 u16 seid,
5424                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5425                 struct i40e_asq_cmd_details *cmd_details)
5426 {
5427         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5428                                     i40e_aqc_opc_query_switching_comp_bw_config,
5429                                     cmd_details);
5430 }
5431
5432 /**
5433  * i40e_validate_filter_settings
5434  * @hw: pointer to the hardware structure
5435  * @settings: Filter control settings
5436  *
5437  * Check and validate the filter control settings passed.
5438  * The function checks for the valid filter/context sizes being
5439  * passed for FCoE and PE.
5440  *
5441  * Returns I40E_SUCCESS if the values passed are valid and within
5442  * range else returns an error.
5443  **/
5444 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5445                                 struct i40e_filter_control_settings *settings)
5446 {
5447         u32 fcoe_cntx_size, fcoe_filt_size;
5448         u32 pe_cntx_size, pe_filt_size;
5449         u32 fcoe_fmax;
5450
5451         u32 val;
5452
5453         /* Validate FCoE settings passed */
5454         switch (settings->fcoe_filt_num) {
5455         case I40E_HASH_FILTER_SIZE_1K:
5456         case I40E_HASH_FILTER_SIZE_2K:
5457         case I40E_HASH_FILTER_SIZE_4K:
5458         case I40E_HASH_FILTER_SIZE_8K:
5459         case I40E_HASH_FILTER_SIZE_16K:
5460         case I40E_HASH_FILTER_SIZE_32K:
5461                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5462                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5463                 break;
5464         default:
5465                 return I40E_ERR_PARAM;
5466         }
5467
5468         switch (settings->fcoe_cntx_num) {
5469         case I40E_DMA_CNTX_SIZE_512:
5470         case I40E_DMA_CNTX_SIZE_1K:
5471         case I40E_DMA_CNTX_SIZE_2K:
5472         case I40E_DMA_CNTX_SIZE_4K:
5473                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5474                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5475                 break;
5476         default:
5477                 return I40E_ERR_PARAM;
5478         }
5479
5480         /* Validate PE settings passed */
5481         switch (settings->pe_filt_num) {
5482         case I40E_HASH_FILTER_SIZE_1K:
5483         case I40E_HASH_FILTER_SIZE_2K:
5484         case I40E_HASH_FILTER_SIZE_4K:
5485         case I40E_HASH_FILTER_SIZE_8K:
5486         case I40E_HASH_FILTER_SIZE_16K:
5487         case I40E_HASH_FILTER_SIZE_32K:
5488         case I40E_HASH_FILTER_SIZE_64K:
5489         case I40E_HASH_FILTER_SIZE_128K:
5490         case I40E_HASH_FILTER_SIZE_256K:
5491         case I40E_HASH_FILTER_SIZE_512K:
5492         case I40E_HASH_FILTER_SIZE_1M:
5493                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5494                 pe_filt_size <<= (u32)settings->pe_filt_num;
5495                 break;
5496         default:
5497                 return I40E_ERR_PARAM;
5498         }
5499
5500         switch (settings->pe_cntx_num) {
5501         case I40E_DMA_CNTX_SIZE_512:
5502         case I40E_DMA_CNTX_SIZE_1K:
5503         case I40E_DMA_CNTX_SIZE_2K:
5504         case I40E_DMA_CNTX_SIZE_4K:
5505         case I40E_DMA_CNTX_SIZE_8K:
5506         case I40E_DMA_CNTX_SIZE_16K:
5507         case I40E_DMA_CNTX_SIZE_32K:
5508         case I40E_DMA_CNTX_SIZE_64K:
5509         case I40E_DMA_CNTX_SIZE_128K:
5510         case I40E_DMA_CNTX_SIZE_256K:
5511                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5512                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5513                 break;
5514         default:
5515                 return I40E_ERR_PARAM;
5516         }
5517
5518         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5519         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5520         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5521                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5522         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
5523                 return I40E_ERR_INVALID_SIZE;
5524
5525         return I40E_SUCCESS;
5526 }
5527
5528 /**
5529  * i40e_set_filter_control
5530  * @hw: pointer to the hardware structure
5531  * @settings: Filter control settings
5532  *
5533  * Set the Queue Filters for PE/FCoE and enable filters required
5534  * for a single PF. It is expected that these settings are programmed
5535  * at the driver initialization time.
5536  **/
5537 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5538                                 struct i40e_filter_control_settings *settings)
5539 {
5540         enum i40e_status_code ret = I40E_SUCCESS;
5541         u32 hash_lut_size = 0;
5542         u32 val;
5543
5544         if (!settings)
5545                 return I40E_ERR_PARAM;
5546
5547         /* Validate the input settings */
5548         ret = i40e_validate_filter_settings(hw, settings);
5549         if (ret)
5550                 return ret;
5551
5552         /* Read the PF Queue Filter control register */
5553         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5554
5555         /* Program required PE hash buckets for the PF */
5556         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5557         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5558                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5559         /* Program required PE contexts for the PF */
5560         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5561         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5562                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5563
5564         /* Program required FCoE hash buckets for the PF */
5565         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5566         val |= ((u32)settings->fcoe_filt_num <<
5567                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5568                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5569         /* Program required FCoE DDP contexts for the PF */
5570         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5571         val |= ((u32)settings->fcoe_cntx_num <<
5572                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5573                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5574
5575         /* Program Hash LUT size for the PF */
5576         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5577         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5578                 hash_lut_size = 1;
5579         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5580                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5581
5582         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5583         if (settings->enable_fdir)
5584                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5585         if (settings->enable_ethtype)
5586                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5587         if (settings->enable_macvlan)
5588                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5589
5590         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5591
5592         return I40E_SUCCESS;
5593 }
5594
5595 /**
5596  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5597  * @hw: pointer to the hw struct
5598  * @mac_addr: MAC address to use in the filter
5599  * @ethtype: Ethertype to use in the filter
5600  * @flags: Flags that needs to be applied to the filter
5601  * @vsi_seid: seid of the control VSI
5602  * @queue: VSI queue number to send the packet to
5603  * @is_add: Add control packet filter if True else remove
5604  * @stats: Structure to hold information on control filter counts
5605  * @cmd_details: pointer to command details structure or NULL
5606  *
5607  * This command will Add or Remove control packet filter for a control VSI.
5608  * In return it will update the total number of perfect filter count in
5609  * the stats member.
5610  **/
5611 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5612                                 u8 *mac_addr, u16 ethtype, u16 flags,
5613                                 u16 vsi_seid, u16 queue, bool is_add,
5614                                 struct i40e_control_filter_stats *stats,
5615                                 struct i40e_asq_cmd_details *cmd_details)
5616 {
5617         struct i40e_aq_desc desc;
5618         struct i40e_aqc_add_remove_control_packet_filter *cmd =
5619                 (struct i40e_aqc_add_remove_control_packet_filter *)
5620                 &desc.params.raw;
5621         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5622                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5623                 &desc.params.raw;
5624         enum i40e_status_code status;
5625
5626         if (vsi_seid == 0)
5627                 return I40E_ERR_PARAM;
5628
5629         if (is_add) {
5630                 i40e_fill_default_direct_cmd_desc(&desc,
5631                                 i40e_aqc_opc_add_control_packet_filter);
5632                 cmd->queue = CPU_TO_LE16(queue);
5633         } else {
5634                 i40e_fill_default_direct_cmd_desc(&desc,
5635                                 i40e_aqc_opc_remove_control_packet_filter);
5636         }
5637
5638         if (mac_addr)
5639                 i40e_memcpy(cmd->mac, mac_addr, ETH_ALEN,
5640                             I40E_NONDMA_TO_NONDMA);
5641
5642         cmd->etype = CPU_TO_LE16(ethtype);
5643         cmd->flags = CPU_TO_LE16(flags);
5644         cmd->seid = CPU_TO_LE16(vsi_seid);
5645
5646         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5647
5648         if (!status && stats) {
5649                 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5650                 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5651                 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5652                 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5653         }
5654
5655         return status;
5656 }
5657
5658 /**
5659  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5660  * @hw: pointer to the hw struct
5661  * @seid: VSI seid to add ethertype filter from
5662  **/
5663 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5664                                                     u16 seid)
5665 {
5666 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5667         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5668                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5669                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5670         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5671         enum i40e_status_code status;
5672
5673         status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5674                                                        seid, 0, true, NULL,
5675                                                        NULL);
5676         if (status)
5677                 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5678 }
5679
5680 /**
5681  * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5682  * @filters: list of cloud filters
5683  * @filter_count: length of list
5684  *
5685  * There's an issue in the device where the Geneve VNI layout needs
5686  * to be shifted 1 byte over from the VxLAN VNI
5687  **/
5688 STATIC void i40e_fix_up_geneve_vni(
5689         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5690         u8 filter_count)
5691 {
5692         struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters;
5693         int i;
5694
5695         for (i = 0; i < filter_count; i++) {
5696                 u16 tnl_type;
5697                 u32 ti;
5698
5699                 tnl_type = (LE16_TO_CPU(f[i].flags) &
5700                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5701                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5702                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5703                         ti = LE32_TO_CPU(f[i].tenant_id);
5704                         f[i].tenant_id = CPU_TO_LE32(ti << 8);
5705                 }
5706         }
5707 }
5708
5709 /**
5710  * i40e_aq_add_cloud_filters
5711  * @hw: pointer to the hardware structure
5712  * @seid: VSI seid to add cloud filters from
5713  * @filters: Buffer which contains the filters to be added
5714  * @filter_count: number of filters contained in the buffer
5715  *
5716  * Set the cloud filters for a given VSI.  The contents of the
5717  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5718  * in by the caller of the function.
5719  *
5720  **/
5721 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5722         u16 seid,
5723         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5724         u8 filter_count)
5725 {
5726         struct i40e_aq_desc desc;
5727         struct i40e_aqc_add_remove_cloud_filters *cmd =
5728         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5729         enum i40e_status_code status;
5730         u16 buff_len;
5731
5732         i40e_fill_default_direct_cmd_desc(&desc,
5733                                           i40e_aqc_opc_add_cloud_filters);
5734
5735         buff_len = filter_count * sizeof(*filters);
5736         desc.datalen = CPU_TO_LE16(buff_len);
5737         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5738         cmd->num_filters = filter_count;
5739         cmd->seid = CPU_TO_LE16(seid);
5740
5741         i40e_fix_up_geneve_vni(filters, filter_count);
5742
5743         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5744
5745         return status;
5746 }
5747
5748 /**
5749  * i40e_aq_add_cloud_filters_big_buffer
5750  * @hw: pointer to the hardware structure
5751  * @seid: VSI seid to add cloud filters from
5752  * @filters: Buffer which contains the filters in big buffer to be added
5753  * @filter_count: number of filters contained in the buffer
5754  *
5755  * Set the cloud filters for a given VSI.  The contents of the
5756  * i40e_aqc_add_rm_cloud_filt_elem_ext are filled in by the caller of
5757  * the function.
5758  *
5759  **/
5760 enum i40e_status_code i40e_aq_add_cloud_filters_big_buffer(struct i40e_hw *hw,
5761         u16 seid,
5762         struct i40e_aqc_add_rm_cloud_filt_elem_ext *filters,
5763         u8 filter_count)
5764 {
5765         struct i40e_aq_desc desc;
5766         struct i40e_aqc_add_remove_cloud_filters *cmd =
5767         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5768         enum i40e_status_code status;
5769         u16 buff_len;
5770         int i;
5771
5772         i40e_fill_default_direct_cmd_desc(&desc,
5773                                           i40e_aqc_opc_add_cloud_filters);
5774
5775         buff_len = filter_count * sizeof(*filters);
5776         desc.datalen = CPU_TO_LE16(buff_len);
5777         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5778         cmd->num_filters = filter_count;
5779         cmd->seid = CPU_TO_LE16(seid);
5780         cmd->big_buffer_flag = I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER;
5781
5782         /* adjust Geneve VNI for HW issue */
5783         for (i = 0; i < filter_count; i++) {
5784                 u16 tnl_type;
5785                 u32 ti;
5786
5787                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5788                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5789                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5790                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5791                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5792                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5793                 }
5794         }
5795
5796         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5797
5798         return status;
5799 }
5800
5801 /**
5802  * i40e_aq_remove_cloud_filters
5803  * @hw: pointer to the hardware structure
5804  * @seid: VSI seid to remove cloud filters from
5805  * @filters: Buffer which contains the filters to be removed
5806  * @filter_count: number of filters contained in the buffer
5807  *
5808  * Remove the cloud filters for a given VSI.  The contents of the
5809  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5810  * in by the caller of the function.
5811  *
5812  **/
5813 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5814         u16 seid,
5815         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5816         u8 filter_count)
5817 {
5818         struct i40e_aq_desc desc;
5819         struct i40e_aqc_add_remove_cloud_filters *cmd =
5820         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5821         enum i40e_status_code status;
5822         u16 buff_len;
5823
5824         i40e_fill_default_direct_cmd_desc(&desc,
5825                                           i40e_aqc_opc_remove_cloud_filters);
5826
5827         buff_len = filter_count * sizeof(*filters);
5828         desc.datalen = CPU_TO_LE16(buff_len);
5829         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5830         cmd->num_filters = filter_count;
5831         cmd->seid = CPU_TO_LE16(seid);
5832
5833         i40e_fix_up_geneve_vni(filters, filter_count);
5834
5835         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5836
5837         return status;
5838 }
5839
5840 /**
5841  * i40e_aq_remove_cloud_filters_big_buffer
5842  * @hw: pointer to the hardware structure
5843  * @seid: VSI seid to remove cloud filters from
5844  * @filters: Buffer which contains the filters in big buffer to be removed
5845  * @filter_count: number of filters contained in the buffer
5846  *
5847  * Remove the cloud filters for a given VSI.  The contents of the
5848  * i40e_aqc_add_rm_cloud_filt_elem_ext are filled in by the caller of
5849  * the function.
5850  *
5851  **/
5852 enum i40e_status_code i40e_aq_remove_cloud_filters_big_buffer(
5853         struct i40e_hw *hw,
5854         u16 seid,
5855         struct i40e_aqc_add_rm_cloud_filt_elem_ext *filters,
5856         u8 filter_count)
5857 {
5858         struct i40e_aq_desc desc;
5859         struct i40e_aqc_add_remove_cloud_filters *cmd =
5860         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5861         enum i40e_status_code status;
5862         u16 buff_len;
5863         int i;
5864
5865         i40e_fill_default_direct_cmd_desc(&desc,
5866                                           i40e_aqc_opc_remove_cloud_filters);
5867
5868         buff_len = filter_count * sizeof(*filters);
5869         desc.datalen = CPU_TO_LE16(buff_len);
5870         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5871         cmd->num_filters = filter_count;
5872         cmd->seid = CPU_TO_LE16(seid);
5873         cmd->big_buffer_flag = I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER;
5874
5875         /* adjust Geneve VNI for HW issue */
5876         for (i = 0; i < filter_count; i++) {
5877                 u16 tnl_type;
5878                 u32 ti;
5879
5880                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5881                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5882                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5883                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5884                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5885                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5886                 }
5887         }
5888
5889         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5890
5891         return status;
5892 }
5893
5894 /**
5895  * i40e_aq_replace_cloud_filters - Replace cloud filter command
5896  * @hw: pointer to the hw struct
5897  * @filters: pointer to the i40e_aqc_replace_cloud_filter_cmd struct
5898  * @cmd_buf: pointer to the i40e_aqc_replace_cloud_filter_cmd_buf struct
5899  *
5900  **/
5901 enum
5902 i40e_status_code i40e_aq_replace_cloud_filters(struct i40e_hw *hw,
5903         struct i40e_aqc_replace_cloud_filters_cmd *filters,
5904         struct i40e_aqc_replace_cloud_filters_cmd_buf *cmd_buf)
5905 {
5906         struct i40e_aq_desc desc;
5907         struct i40e_aqc_replace_cloud_filters_cmd *cmd =
5908                 (struct i40e_aqc_replace_cloud_filters_cmd *)&desc.params.raw;
5909         enum i40e_status_code status = I40E_SUCCESS;
5910         int i = 0;
5911
5912         i40e_fill_default_direct_cmd_desc(&desc,
5913                                           i40e_aqc_opc_replace_cloud_filters);
5914
5915         desc.datalen = CPU_TO_LE16(32);
5916         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5917         cmd->old_filter_type = filters->old_filter_type;
5918         cmd->new_filter_type = filters->new_filter_type;
5919         cmd->valid_flags = filters->valid_flags;
5920         cmd->tr_bit = filters->tr_bit;
5921
5922         status = i40e_asq_send_command(hw, &desc, cmd_buf,
5923                 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf),  NULL);
5924
5925         /* for get cloud filters command */
5926         for (i = 0; i < 32; i += 4) {
5927                 cmd_buf->filters[i / 4].filter_type = cmd_buf->data[i];
5928                 cmd_buf->filters[i / 4].input[0] = cmd_buf->data[i + 1];
5929                 cmd_buf->filters[i / 4].input[1] = cmd_buf->data[i + 2];
5930                 cmd_buf->filters[i / 4].input[2] = cmd_buf->data[i + 3];
5931         }
5932
5933         return status;
5934 }
5935
5936
5937 /**
5938  * i40e_aq_alternate_write
5939  * @hw: pointer to the hardware structure
5940  * @reg_addr0: address of first dword to be read
5941  * @reg_val0: value to be written under 'reg_addr0'
5942  * @reg_addr1: address of second dword to be read
5943  * @reg_val1: value to be written under 'reg_addr1'
5944  *
5945  * Write one or two dwords to alternate structure. Fields are indicated
5946  * by 'reg_addr0' and 'reg_addr1' register numbers.
5947  *
5948  **/
5949 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5950                                 u32 reg_addr0, u32 reg_val0,
5951                                 u32 reg_addr1, u32 reg_val1)
5952 {
5953         struct i40e_aq_desc desc;
5954         struct i40e_aqc_alternate_write *cmd_resp =
5955                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5956         enum i40e_status_code status;
5957
5958         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5959         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5960         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5961         cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5962         cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5963
5964         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5965
5966         return status;
5967 }
5968
5969 /**
5970  * i40e_aq_alternate_write_indirect
5971  * @hw: pointer to the hardware structure
5972  * @addr: address of a first register to be modified
5973  * @dw_count: number of alternate structure fields to write
5974  * @buffer: pointer to the command buffer
5975  *
5976  * Write 'dw_count' dwords from 'buffer' to alternate structure
5977  * starting at 'addr'.
5978  *
5979  **/
5980 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5981                                 u32 addr, u32 dw_count, void *buffer)
5982 {
5983         struct i40e_aq_desc desc;
5984         struct i40e_aqc_alternate_ind_write *cmd_resp =
5985                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5986         enum i40e_status_code status;
5987
5988         if (buffer == NULL)
5989                 return I40E_ERR_PARAM;
5990
5991         /* Indirect command */
5992         i40e_fill_default_direct_cmd_desc(&desc,
5993                                          i40e_aqc_opc_alternate_write_indirect);
5994
5995         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5996         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5997         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5998                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5999
6000         cmd_resp->address = CPU_TO_LE32(addr);
6001         cmd_resp->length = CPU_TO_LE32(dw_count);
6002
6003         status = i40e_asq_send_command(hw, &desc, buffer,
6004                                        I40E_LO_DWORD(4*dw_count), NULL);
6005
6006         return status;
6007 }
6008
6009 /**
6010  * i40e_aq_alternate_read
6011  * @hw: pointer to the hardware structure
6012  * @reg_addr0: address of first dword to be read
6013  * @reg_val0: pointer for data read from 'reg_addr0'
6014  * @reg_addr1: address of second dword to be read
6015  * @reg_val1: pointer for data read from 'reg_addr1'
6016  *
6017  * Read one or two dwords from alternate structure. Fields are indicated
6018  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
6019  * is not passed then only register at 'reg_addr0' is read.
6020  *
6021  **/
6022 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
6023                                 u32 reg_addr0, u32 *reg_val0,
6024                                 u32 reg_addr1, u32 *reg_val1)
6025 {
6026         struct i40e_aq_desc desc;
6027         struct i40e_aqc_alternate_write *cmd_resp =
6028                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
6029         enum i40e_status_code status;
6030
6031         if (reg_val0 == NULL)
6032                 return I40E_ERR_PARAM;
6033
6034         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
6035         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
6036         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
6037
6038         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6039
6040         if (status == I40E_SUCCESS) {
6041                 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
6042
6043                 if (reg_val1 != NULL)
6044                         *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
6045         }
6046
6047         return status;
6048 }
6049
6050 /**
6051  * i40e_aq_alternate_read_indirect
6052  * @hw: pointer to the hardware structure
6053  * @addr: address of the alternate structure field
6054  * @dw_count: number of alternate structure fields to read
6055  * @buffer: pointer to the command buffer
6056  *
6057  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
6058  * place them in 'buffer'. The buffer should be allocated by caller.
6059  *
6060  **/
6061 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
6062                                 u32 addr, u32 dw_count, void *buffer)
6063 {
6064         struct i40e_aq_desc desc;
6065         struct i40e_aqc_alternate_ind_write *cmd_resp =
6066                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
6067         enum i40e_status_code status;
6068
6069         if (buffer == NULL)
6070                 return I40E_ERR_PARAM;
6071
6072         /* Indirect command */
6073         i40e_fill_default_direct_cmd_desc(&desc,
6074                 i40e_aqc_opc_alternate_read_indirect);
6075
6076         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6077         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6078         if (dw_count > (I40E_AQ_LARGE_BUF/4))
6079                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6080
6081         cmd_resp->address = CPU_TO_LE32(addr);
6082         cmd_resp->length = CPU_TO_LE32(dw_count);
6083
6084         status = i40e_asq_send_command(hw, &desc, buffer,
6085                                        I40E_LO_DWORD(4*dw_count), NULL);
6086
6087         return status;
6088 }
6089
6090 /**
6091  *  i40e_aq_alternate_clear
6092  *  @hw: pointer to the HW structure.
6093  *
6094  *  Clear the alternate structures of the port from which the function
6095  *  is called.
6096  *
6097  **/
6098 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
6099 {
6100         struct i40e_aq_desc desc;
6101         enum i40e_status_code status;
6102
6103         i40e_fill_default_direct_cmd_desc(&desc,
6104                                           i40e_aqc_opc_alternate_clear_port);
6105
6106         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6107
6108         return status;
6109 }
6110
6111 /**
6112  *  i40e_aq_alternate_write_done
6113  *  @hw: pointer to the HW structure.
6114  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
6115  *  @reset_needed: indicates the SW should trigger GLOBAL reset
6116  *
6117  *  Indicates to the FW that alternate structures have been changed.
6118  *
6119  **/
6120 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
6121                 u8 bios_mode, bool *reset_needed)
6122 {
6123         struct i40e_aq_desc desc;
6124         struct i40e_aqc_alternate_write_done *cmd =
6125                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6126         enum i40e_status_code status;
6127
6128         if (reset_needed == NULL)
6129                 return I40E_ERR_PARAM;
6130
6131         i40e_fill_default_direct_cmd_desc(&desc,
6132                                           i40e_aqc_opc_alternate_write_done);
6133
6134         cmd->cmd_flags = CPU_TO_LE16(bios_mode);
6135
6136         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6137         if (!status && reset_needed)
6138                 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
6139                                  I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
6140
6141         return status;
6142 }
6143
6144 /**
6145  *  i40e_aq_set_oem_mode
6146  *  @hw: pointer to the HW structure.
6147  *  @oem_mode: the OEM mode to be used
6148  *
6149  *  Sets the device to a specific operating mode. Currently the only supported
6150  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
6151  *
6152  **/
6153 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
6154                 u8 oem_mode)
6155 {
6156         struct i40e_aq_desc desc;
6157         struct i40e_aqc_alternate_write_done *cmd =
6158                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6159         enum i40e_status_code status;
6160
6161         i40e_fill_default_direct_cmd_desc(&desc,
6162                                           i40e_aqc_opc_alternate_set_mode);
6163
6164         cmd->cmd_flags = CPU_TO_LE16(oem_mode);
6165
6166         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6167
6168         return status;
6169 }
6170
6171 /**
6172  * i40e_aq_resume_port_tx
6173  * @hw: pointer to the hardware structure
6174  * @cmd_details: pointer to command details structure or NULL
6175  *
6176  * Resume port's Tx traffic
6177  **/
6178 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
6179                                 struct i40e_asq_cmd_details *cmd_details)
6180 {
6181         struct i40e_aq_desc desc;
6182         enum i40e_status_code status;
6183
6184         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
6185
6186         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6187
6188         return status;
6189 }
6190
6191 /**
6192  * i40e_set_pci_config_data - store PCI bus info
6193  * @hw: pointer to hardware structure
6194  * @link_status: the link status word from PCI config space
6195  *
6196  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
6197  **/
6198 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
6199 {
6200         hw->bus.type = i40e_bus_type_pci_express;
6201
6202         switch (link_status & I40E_PCI_LINK_WIDTH) {
6203         case I40E_PCI_LINK_WIDTH_1:
6204                 hw->bus.width = i40e_bus_width_pcie_x1;
6205                 break;
6206         case I40E_PCI_LINK_WIDTH_2:
6207                 hw->bus.width = i40e_bus_width_pcie_x2;
6208                 break;
6209         case I40E_PCI_LINK_WIDTH_4:
6210                 hw->bus.width = i40e_bus_width_pcie_x4;
6211                 break;
6212         case I40E_PCI_LINK_WIDTH_8:
6213                 hw->bus.width = i40e_bus_width_pcie_x8;
6214                 break;
6215         default:
6216                 hw->bus.width = i40e_bus_width_unknown;
6217                 break;
6218         }
6219
6220         switch (link_status & I40E_PCI_LINK_SPEED) {
6221         case I40E_PCI_LINK_SPEED_2500:
6222                 hw->bus.speed = i40e_bus_speed_2500;
6223                 break;
6224         case I40E_PCI_LINK_SPEED_5000:
6225                 hw->bus.speed = i40e_bus_speed_5000;
6226                 break;
6227         case I40E_PCI_LINK_SPEED_8000:
6228                 hw->bus.speed = i40e_bus_speed_8000;
6229                 break;
6230         default:
6231                 hw->bus.speed = i40e_bus_speed_unknown;
6232                 break;
6233         }
6234 }
6235
6236 /**
6237  * i40e_aq_debug_dump
6238  * @hw: pointer to the hardware structure
6239  * @cluster_id: specific cluster to dump
6240  * @table_id: table id within cluster
6241  * @start_index: index of line in the block to read
6242  * @buff_size: dump buffer size
6243  * @buff: dump buffer
6244  * @ret_buff_size: actual buffer size returned
6245  * @ret_next_table: next block to read
6246  * @ret_next_index: next index to read
6247  * @cmd_details: pointer to command details structure or NULL
6248  *
6249  * Dump internal FW/HW data for debug purposes.
6250  *
6251  **/
6252 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
6253                                 u8 table_id, u32 start_index, u16 buff_size,
6254                                 void *buff, u16 *ret_buff_size,
6255                                 u8 *ret_next_table, u32 *ret_next_index,
6256                                 struct i40e_asq_cmd_details *cmd_details)
6257 {
6258         struct i40e_aq_desc desc;
6259         struct i40e_aqc_debug_dump_internals *cmd =
6260                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6261         struct i40e_aqc_debug_dump_internals *resp =
6262                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6263         enum i40e_status_code status;
6264
6265         if (buff_size == 0 || !buff)
6266                 return I40E_ERR_PARAM;
6267
6268         i40e_fill_default_direct_cmd_desc(&desc,
6269                                           i40e_aqc_opc_debug_dump_internals);
6270         /* Indirect Command */
6271         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6272         if (buff_size > I40E_AQ_LARGE_BUF)
6273                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6274
6275         cmd->cluster_id = cluster_id;
6276         cmd->table_id = table_id;
6277         cmd->idx = CPU_TO_LE32(start_index);
6278
6279         desc.datalen = CPU_TO_LE16(buff_size);
6280
6281         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
6282         if (!status) {
6283                 if (ret_buff_size != NULL)
6284                         *ret_buff_size = LE16_TO_CPU(desc.datalen);
6285                 if (ret_next_table != NULL)
6286                         *ret_next_table = resp->table_id;
6287                 if (ret_next_index != NULL)
6288                         *ret_next_index = LE32_TO_CPU(resp->idx);
6289         }
6290
6291         return status;
6292 }
6293
6294 /**
6295  * i40e_read_bw_from_alt_ram
6296  * @hw: pointer to the hardware structure
6297  * @max_bw: pointer for max_bw read
6298  * @min_bw: pointer for min_bw read
6299  * @min_valid: pointer for bool that is true if min_bw is a valid value
6300  * @max_valid: pointer for bool that is true if max_bw is a valid value
6301  *
6302  * Read bw from the alternate ram for the given pf
6303  **/
6304 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
6305                                         u32 *max_bw, u32 *min_bw,
6306                                         bool *min_valid, bool *max_valid)
6307 {
6308         enum i40e_status_code status;
6309         u32 max_bw_addr, min_bw_addr;
6310
6311         /* Calculate the address of the min/max bw registers */
6312         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6313                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
6314                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6315         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6316                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
6317                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6318
6319         /* Read the bandwidths from alt ram */
6320         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
6321                                         min_bw_addr, min_bw);
6322
6323         if (*min_bw & I40E_ALT_BW_VALID_MASK)
6324                 *min_valid = true;
6325         else
6326                 *min_valid = false;
6327
6328         if (*max_bw & I40E_ALT_BW_VALID_MASK)
6329                 *max_valid = true;
6330         else
6331                 *max_valid = false;
6332
6333         return status;
6334 }
6335
6336 /**
6337  * i40e_aq_configure_partition_bw
6338  * @hw: pointer to the hardware structure
6339  * @bw_data: Buffer holding valid pfs and bw limits
6340  * @cmd_details: pointer to command details
6341  *
6342  * Configure partitions guaranteed/max bw
6343  **/
6344 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6345                         struct i40e_aqc_configure_partition_bw_data *bw_data,
6346                         struct i40e_asq_cmd_details *cmd_details)
6347 {
6348         enum i40e_status_code status;
6349         struct i40e_aq_desc desc;
6350         u16 bwd_size = sizeof(*bw_data);
6351
6352         i40e_fill_default_direct_cmd_desc(&desc,
6353                                 i40e_aqc_opc_configure_partition_bw);
6354
6355         /* Indirect command */
6356         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6357         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6358
6359         desc.datalen = CPU_TO_LE16(bwd_size);
6360
6361         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6362
6363         return status;
6364 }
6365
6366 /**
6367  * i40e_read_phy_register_clause22
6368  * @hw: pointer to the HW structure
6369  * @reg: register address in the page
6370  * @phy_addr: PHY address on MDIO interface
6371  * @value: PHY register value
6372  *
6373  * Reads specified PHY register value
6374  **/
6375 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
6376                                         u16 reg, u8 phy_addr, u16 *value)
6377 {
6378         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6379         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6380         u32 command = 0;
6381         u16 retry = 1000;
6382
6383         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6384                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6385                   (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
6386                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6387                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6388         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6389         do {
6390                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6391                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6392                         status = I40E_SUCCESS;
6393                         break;
6394                 }
6395                 i40e_usec_delay(10);
6396                 retry--;
6397         } while (retry);
6398
6399         if (status) {
6400                 i40e_debug(hw, I40E_DEBUG_PHY,
6401                            "PHY: Can't write command to external PHY.\n");
6402         } else {
6403                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6404                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6405                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6406         }
6407
6408         return status;
6409 }
6410
6411 /**
6412  * i40e_write_phy_register_clause22
6413  * @hw: pointer to the HW structure
6414  * @reg: register address in the page
6415  * @phy_addr: PHY address on MDIO interface
6416  * @value: PHY register value
6417  *
6418  * Writes specified PHY register value
6419  **/
6420 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6421                                         u16 reg, u8 phy_addr, u16 value)
6422 {
6423         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6424         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6425         u32 command  = 0;
6426         u16 retry = 1000;
6427
6428         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6429         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6430
6431         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6432                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6433                   (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6434                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6435                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6436
6437         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6438         do {
6439                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6440                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6441                         status = I40E_SUCCESS;
6442                         break;
6443                 }
6444                 i40e_usec_delay(10);
6445                 retry--;
6446         } while (retry);
6447
6448         return status;
6449 }
6450
6451 /**
6452  * i40e_read_phy_register_clause45
6453  * @hw: pointer to the HW structure
6454  * @page: registers page number
6455  * @reg: register address in the page
6456  * @phy_addr: PHY address on MDIO interface
6457  * @value: PHY register value
6458  *
6459  * Reads specified PHY register value
6460  **/
6461 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6462                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6463 {
6464         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6465         u32 command  = 0;
6466         u16 retry = 1000;
6467         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6468
6469         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6470                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6471                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6472                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6473                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6474                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6475                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6476         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6477         do {
6478                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6479                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6480                         status = I40E_SUCCESS;
6481                         break;
6482                 }
6483                 i40e_usec_delay(10);
6484                 retry--;
6485         } while (retry);
6486
6487         if (status) {
6488                 i40e_debug(hw, I40E_DEBUG_PHY,
6489                            "PHY: Can't write command to external PHY.\n");
6490                 goto phy_read_end;
6491         }
6492
6493         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6494                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6495                   (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6496                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6497                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6498                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6499         status = I40E_ERR_TIMEOUT;
6500         retry = 1000;
6501         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6502         do {
6503                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6504                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6505                         status = I40E_SUCCESS;
6506                         break;
6507                 }
6508                 i40e_usec_delay(10);
6509                 retry--;
6510         } while (retry);
6511
6512         if (!status) {
6513                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6514                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6515                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6516         } else {
6517                 i40e_debug(hw, I40E_DEBUG_PHY,
6518                            "PHY: Can't read register value from external PHY.\n");
6519         }
6520
6521 phy_read_end:
6522         return status;
6523 }
6524
6525 /**
6526  * i40e_write_phy_register_clause45
6527  * @hw: pointer to the HW structure
6528  * @page: registers page number
6529  * @reg: register address in the page
6530  * @phy_addr: PHY address on MDIO interface
6531  * @value: PHY register value
6532  *
6533  * Writes value to specified PHY register
6534  **/
6535 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6536                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6537 {
6538         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6539         u32 command  = 0;
6540         u16 retry = 1000;
6541         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6542
6543         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6544                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6545                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6546                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6547                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6548                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6549                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6550         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6551         do {
6552                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6553                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6554                         status = I40E_SUCCESS;
6555                         break;
6556                 }
6557                 i40e_usec_delay(10);
6558                 retry--;
6559         } while (retry);
6560         if (status) {
6561                 i40e_debug(hw, I40E_DEBUG_PHY,
6562                            "PHY: Can't write command to external PHY.\n");
6563                 goto phy_write_end;
6564         }
6565
6566         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6567         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6568
6569         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6570                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6571                   (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6572                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6573                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6574                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6575         status = I40E_ERR_TIMEOUT;
6576         retry = 1000;
6577         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6578         do {
6579                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6580                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6581                         status = I40E_SUCCESS;
6582                         break;
6583                 }
6584                 i40e_usec_delay(10);
6585                 retry--;
6586         } while (retry);
6587
6588 phy_write_end:
6589         return status;
6590 }
6591
6592 /**
6593  * i40e_write_phy_register
6594  * @hw: pointer to the HW structure
6595  * @page: registers page number
6596  * @reg: register address in the page
6597  * @phy_addr: PHY address on MDIO interface
6598  * @value: PHY register value
6599  *
6600  * Writes value to specified PHY register
6601  **/
6602 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6603                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6604 {
6605         enum i40e_status_code status;
6606
6607         switch (hw->device_id) {
6608         case I40E_DEV_ID_1G_BASE_T_X722:
6609                 status = i40e_write_phy_register_clause22(hw,
6610                         reg, phy_addr, value);
6611                 break;
6612         case I40E_DEV_ID_10G_BASE_T:
6613         case I40E_DEV_ID_10G_BASE_T4:
6614         case I40E_DEV_ID_10G_BASE_T_X722:
6615         case I40E_DEV_ID_25G_B:
6616         case I40E_DEV_ID_25G_SFP28:
6617                 status = i40e_write_phy_register_clause45(hw,
6618                         page, reg, phy_addr, value);
6619                 break;
6620         default:
6621                 status = I40E_ERR_UNKNOWN_PHY;
6622                 break;
6623         }
6624
6625         return status;
6626 }
6627
6628 /**
6629  * i40e_read_phy_register
6630  * @hw: pointer to the HW structure
6631  * @page: registers page number
6632  * @reg: register address in the page
6633  * @phy_addr: PHY address on MDIO interface
6634  * @value: PHY register value
6635  *
6636  * Reads specified PHY register value
6637  **/
6638 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6639                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6640 {
6641         enum i40e_status_code status;
6642
6643         switch (hw->device_id) {
6644         case I40E_DEV_ID_1G_BASE_T_X722:
6645                 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6646                                                          value);
6647                 break;
6648         case I40E_DEV_ID_10G_BASE_T:
6649         case I40E_DEV_ID_10G_BASE_T4:
6650         case I40E_DEV_ID_10G_BASE_T_X722:
6651         case I40E_DEV_ID_25G_B:
6652         case I40E_DEV_ID_25G_SFP28:
6653                 status = i40e_read_phy_register_clause45(hw, page, reg,
6654                                                          phy_addr, value);
6655                 break;
6656         default:
6657                 status = I40E_ERR_UNKNOWN_PHY;
6658                 break;
6659         }
6660
6661         return status;
6662 }
6663
6664 /**
6665  * i40e_get_phy_address
6666  * @hw: pointer to the HW structure
6667  * @dev_num: PHY port num that address we want
6668  *
6669  * Gets PHY address for current port
6670  **/
6671 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6672 {
6673         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6674         u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6675
6676         return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6677 }
6678
6679 /**
6680  * i40e_blink_phy_led
6681  * @hw: pointer to the HW structure
6682  * @time: time how long led will blinks in secs
6683  * @interval: gap between LED on and off in msecs
6684  *
6685  * Blinks PHY link LED
6686  **/
6687 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6688                                               u32 time, u32 interval)
6689 {
6690         enum i40e_status_code status = I40E_SUCCESS;
6691         u32 i;
6692         u16 led_ctl = 0;
6693         u16 gpio_led_port;
6694         u16 led_reg;
6695         u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6696         u8 phy_addr = 0;
6697         u8 port_num;
6698
6699         i = rd32(hw, I40E_PFGEN_PORTNUM);
6700         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6701         phy_addr = i40e_get_phy_address(hw, port_num);
6702
6703         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6704              led_addr++) {
6705                 status = i40e_read_phy_register_clause45(hw,
6706                                                          I40E_PHY_COM_REG_PAGE,
6707                                                          led_addr, phy_addr,
6708                                                          &led_reg);
6709                 if (status)
6710                         goto phy_blinking_end;
6711                 led_ctl = led_reg;
6712                 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6713                         led_reg = 0;
6714                         status = i40e_write_phy_register_clause45(hw,
6715                                                          I40E_PHY_COM_REG_PAGE,
6716                                                          led_addr, phy_addr,
6717                                                          led_reg);
6718                         if (status)
6719                                 goto phy_blinking_end;
6720                         break;
6721                 }
6722         }
6723
6724         if (time > 0 && interval > 0) {
6725                 for (i = 0; i < time * 1000; i += interval) {
6726                         status = i40e_read_phy_register_clause45(hw,
6727                                                 I40E_PHY_COM_REG_PAGE,
6728                                                 led_addr, phy_addr, &led_reg);
6729                         if (status)
6730                                 goto restore_config;
6731                         if (led_reg & I40E_PHY_LED_MANUAL_ON)
6732                                 led_reg = 0;
6733                         else
6734                                 led_reg = I40E_PHY_LED_MANUAL_ON;
6735                         status = i40e_write_phy_register_clause45(hw,
6736                                                 I40E_PHY_COM_REG_PAGE,
6737                                                 led_addr, phy_addr, led_reg);
6738                         if (status)
6739                                 goto restore_config;
6740                         i40e_msec_delay(interval);
6741                 }
6742         }
6743
6744 restore_config:
6745         status = i40e_write_phy_register_clause45(hw,
6746                                                   I40E_PHY_COM_REG_PAGE,
6747                                                   led_addr, phy_addr, led_ctl);
6748
6749 phy_blinking_end:
6750         return status;
6751 }
6752
6753 /**
6754  * i40e_led_get_reg - read LED register
6755  * @hw: pointer to the HW structure
6756  * @led_addr: LED register address
6757  * @reg_val: read register value
6758  **/
6759 static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr,
6760                                               u32 *reg_val)
6761 {
6762         enum i40e_status_code status;
6763         u8 phy_addr = 0;
6764
6765         *reg_val = 0;
6766         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6767                 status = i40e_aq_get_phy_register(hw,
6768                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6769                                                 I40E_PHY_COM_REG_PAGE,
6770                                                 I40E_PHY_LED_PROV_REG_1,
6771                                                 reg_val, NULL);
6772         } else {
6773                 phy_addr = i40e_get_phy_address(hw, hw->port);
6774                 status = i40e_read_phy_register_clause45(hw,
6775                                                          I40E_PHY_COM_REG_PAGE,
6776                                                          led_addr, phy_addr,
6777                                                          (u16 *)reg_val);
6778         }
6779         return status;
6780 }
6781
6782 /**
6783  * i40e_led_set_reg - write LED register
6784  * @hw: pointer to the HW structure
6785  * @led_addr: LED register address
6786  * @reg_val: register value to write
6787  **/
6788 static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr,
6789                                               u32 reg_val)
6790 {
6791         enum i40e_status_code status;
6792         u8 phy_addr = 0;
6793
6794         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6795                 status = i40e_aq_set_phy_register(hw,
6796                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6797                                                 I40E_PHY_COM_REG_PAGE,
6798                                                 I40E_PHY_LED_PROV_REG_1,
6799                                                 reg_val, NULL);
6800         } else {
6801                 phy_addr = i40e_get_phy_address(hw, hw->port);
6802                 status = i40e_write_phy_register_clause45(hw,
6803                                                           I40E_PHY_COM_REG_PAGE,
6804                                                           led_addr, phy_addr,
6805                                                           (u16)reg_val);
6806         }
6807
6808         return status;
6809 }
6810
6811 /**
6812  * i40e_led_get_phy - return current on/off mode
6813  * @hw: pointer to the hw struct
6814  * @led_addr: address of led register to use
6815  * @val: original value of register to use
6816  *
6817  **/
6818 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6819                                        u16 *val)
6820 {
6821         enum i40e_status_code status = I40E_SUCCESS;
6822         u16 gpio_led_port;
6823         u32 reg_val_aq;
6824         u16 temp_addr;
6825         u8 phy_addr = 0;
6826         u16 reg_val;
6827
6828         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6829                 status = i40e_aq_get_phy_register(hw,
6830                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6831                                                 I40E_PHY_COM_REG_PAGE,
6832                                                 I40E_PHY_LED_PROV_REG_1,
6833                                                 &reg_val_aq, NULL);
6834                 if (status == I40E_SUCCESS)
6835                         *val = (u16)reg_val_aq;
6836                 return status;
6837         }
6838         temp_addr = I40E_PHY_LED_PROV_REG_1;
6839         phy_addr = i40e_get_phy_address(hw, hw->port);
6840         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6841              temp_addr++) {
6842                 status = i40e_read_phy_register_clause45(hw,
6843                                                          I40E_PHY_COM_REG_PAGE,
6844                                                          temp_addr, phy_addr,
6845                                                          &reg_val);
6846                 if (status)
6847                         return status;
6848                 *val = reg_val;
6849                 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6850                         *led_addr = temp_addr;
6851                         break;
6852                 }
6853         }
6854         return status;
6855 }
6856
6857 /**
6858  * i40e_led_set_phy
6859  * @hw: pointer to the HW structure
6860  * @on: true or false
6861  * @led_addr: address of led register to use
6862  * @mode: original val plus bit for set or ignore
6863  *
6864  * Set led's on or off when controlled by the PHY
6865  *
6866  **/
6867 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6868                                        u16 led_addr, u32 mode)
6869 {
6870         enum i40e_status_code status = I40E_SUCCESS;
6871         u32 led_ctl = 0;
6872         u32 led_reg = 0;
6873
6874         status = i40e_led_get_reg(hw, led_addr, &led_reg);
6875         if (status)
6876                 return status;
6877         led_ctl = led_reg;
6878         if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6879                 led_reg = 0;
6880                 status = i40e_led_set_reg(hw, led_addr, led_reg);
6881                 if (status)
6882                         return status;
6883         }
6884         status = i40e_led_get_reg(hw, led_addr, &led_reg);
6885         if (status)
6886                 goto restore_config;
6887         if (on)
6888                 led_reg = I40E_PHY_LED_MANUAL_ON;
6889         else
6890                 led_reg = 0;
6891         status = i40e_led_set_reg(hw, led_addr, led_reg);
6892         if (status)
6893                 goto restore_config;
6894         if (mode & I40E_PHY_LED_MODE_ORIG) {
6895                 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6896                 status = i40e_led_set_reg(hw, led_addr, led_ctl);
6897         }
6898         return status;
6899
6900 restore_config:
6901         status = i40e_led_set_reg(hw, led_addr, led_ctl);
6902         return status;
6903 }
6904 #endif /* PF_DRIVER */
6905
6906 /**
6907  * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6908  * @hw: pointer to the hw struct
6909  * @reg_addr: register address
6910  * @reg_val: ptr to register value
6911  * @cmd_details: pointer to command details structure or NULL
6912  *
6913  * Use the firmware to read the Rx control register,
6914  * especially useful if the Rx unit is under heavy pressure
6915  **/
6916 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6917                                 u32 reg_addr, u32 *reg_val,
6918                                 struct i40e_asq_cmd_details *cmd_details)
6919 {
6920         struct i40e_aq_desc desc;
6921         struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
6922                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6923         enum i40e_status_code status;
6924
6925         if (reg_val == NULL)
6926                 return I40E_ERR_PARAM;
6927
6928         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
6929
6930         cmd_resp->address = CPU_TO_LE32(reg_addr);
6931
6932         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6933
6934         if (status == I40E_SUCCESS)
6935                 *reg_val = LE32_TO_CPU(cmd_resp->value);
6936
6937         return status;
6938 }
6939
6940 /**
6941  * i40e_read_rx_ctl - read from an Rx control register
6942  * @hw: pointer to the hw struct
6943  * @reg_addr: register address
6944  **/
6945 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
6946 {
6947         enum i40e_status_code status = I40E_SUCCESS;
6948         bool use_register;
6949         int retry = 5;
6950         u32 val = 0;
6951
6952         use_register = (((hw->aq.api_maj_ver == 1) &&
6953                         (hw->aq.api_min_ver < 5)) ||
6954                         (hw->mac.type == I40E_MAC_X722));
6955         if (!use_register) {
6956 do_retry:
6957                 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
6958                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6959                         i40e_msec_delay(1);
6960                         retry--;
6961                         goto do_retry;
6962                 }
6963         }
6964
6965         /* if the AQ access failed, try the old-fashioned way */
6966         if (status || use_register)
6967                 val = rd32(hw, reg_addr);
6968
6969         return val;
6970 }
6971
6972 /**
6973  * i40e_aq_rx_ctl_write_register
6974  * @hw: pointer to the hw struct
6975  * @reg_addr: register address
6976  * @reg_val: register value
6977  * @cmd_details: pointer to command details structure or NULL
6978  *
6979  * Use the firmware to write to an Rx control register,
6980  * especially useful if the Rx unit is under heavy pressure
6981  **/
6982 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
6983                                 u32 reg_addr, u32 reg_val,
6984                                 struct i40e_asq_cmd_details *cmd_details)
6985 {
6986         struct i40e_aq_desc desc;
6987         struct i40e_aqc_rx_ctl_reg_read_write *cmd =
6988                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6989         enum i40e_status_code status;
6990
6991         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
6992
6993         cmd->address = CPU_TO_LE32(reg_addr);
6994         cmd->value = CPU_TO_LE32(reg_val);
6995
6996         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6997
6998         return status;
6999 }
7000
7001 /**
7002  * i40e_write_rx_ctl - write to an Rx control register
7003  * @hw: pointer to the hw struct
7004  * @reg_addr: register address
7005  * @reg_val: register value
7006  **/
7007 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
7008 {
7009         enum i40e_status_code status = I40E_SUCCESS;
7010         bool use_register;
7011         int retry = 5;
7012
7013         use_register = (((hw->aq.api_maj_ver == 1) &&
7014                         (hw->aq.api_min_ver < 5)) ||
7015                         (hw->mac.type == I40E_MAC_X722));
7016         if (!use_register) {
7017 do_retry:
7018                 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
7019                                                        reg_val, NULL);
7020                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
7021                         i40e_msec_delay(1);
7022                         retry--;
7023                         goto do_retry;
7024                 }
7025         }
7026
7027         /* if the AQ access failed, try the old-fashioned way */
7028         if (status || use_register)
7029                 wr32(hw, reg_addr, reg_val);
7030 }
7031
7032 /**
7033  * i40e_aq_set_phy_register
7034  * @hw: pointer to the hw struct
7035  * @phy_select: select which phy should be accessed
7036  * @dev_addr: PHY device address
7037  * @reg_addr: PHY register address
7038  * @reg_val: new register value
7039  * @cmd_details: pointer to command details structure or NULL
7040  *
7041  * Write the external PHY register.
7042  **/
7043 enum i40e_status_code i40e_aq_set_phy_register(struct i40e_hw *hw,
7044                                 u8 phy_select, u8 dev_addr,
7045                                 u32 reg_addr, u32 reg_val,
7046                                 struct i40e_asq_cmd_details *cmd_details)
7047 {
7048         struct i40e_aq_desc desc;
7049         struct i40e_aqc_phy_register_access *cmd =
7050                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7051         enum i40e_status_code status;
7052
7053         i40e_fill_default_direct_cmd_desc(&desc,
7054                                           i40e_aqc_opc_set_phy_register);
7055
7056         cmd->phy_interface = phy_select;
7057         cmd->dev_addres = dev_addr;
7058         cmd->reg_address = CPU_TO_LE32(reg_addr);
7059         cmd->reg_value = CPU_TO_LE32(reg_val);
7060
7061         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7062
7063         return status;
7064 }
7065
7066 /**
7067  * i40e_aq_get_phy_register
7068  * @hw: pointer to the hw struct
7069  * @phy_select: select which phy should be accessed
7070  * @dev_addr: PHY device address
7071  * @reg_addr: PHY register address
7072  * @reg_val: read register value
7073  * @cmd_details: pointer to command details structure or NULL
7074  *
7075  * Read the external PHY register.
7076  **/
7077 enum i40e_status_code i40e_aq_get_phy_register(struct i40e_hw *hw,
7078                                 u8 phy_select, u8 dev_addr,
7079                                 u32 reg_addr, u32 *reg_val,
7080                                 struct i40e_asq_cmd_details *cmd_details)
7081 {
7082         struct i40e_aq_desc desc;
7083         struct i40e_aqc_phy_register_access *cmd =
7084                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7085         enum i40e_status_code status;
7086
7087         i40e_fill_default_direct_cmd_desc(&desc,
7088                                           i40e_aqc_opc_get_phy_register);
7089
7090         cmd->phy_interface = phy_select;
7091         cmd->dev_addres = dev_addr;
7092         cmd->reg_address = CPU_TO_LE32(reg_addr);
7093
7094         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7095         if (!status)
7096                 *reg_val = LE32_TO_CPU(cmd->reg_value);
7097
7098         return status;
7099 }
7100
7101 #ifdef VF_DRIVER
7102
7103 /**
7104  * i40e_aq_send_msg_to_pf
7105  * @hw: pointer to the hardware structure
7106  * @v_opcode: opcodes for VF-PF communication
7107  * @v_retval: return error code
7108  * @msg: pointer to the msg buffer
7109  * @msglen: msg length
7110  * @cmd_details: pointer to command details
7111  *
7112  * Send message to PF driver using admin queue. By default, this message
7113  * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
7114  * completion before returning.
7115  **/
7116 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
7117                                 enum virtchnl_ops v_opcode,
7118                                 enum i40e_status_code v_retval,
7119                                 u8 *msg, u16 msglen,
7120                                 struct i40e_asq_cmd_details *cmd_details)
7121 {
7122         struct i40e_aq_desc desc;
7123         struct i40e_asq_cmd_details details;
7124         enum i40e_status_code status;
7125
7126         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
7127         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
7128         desc.cookie_high = CPU_TO_LE32(v_opcode);
7129         desc.cookie_low = CPU_TO_LE32(v_retval);
7130         if (msglen) {
7131                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
7132                                                 | I40E_AQ_FLAG_RD));
7133                 if (msglen > I40E_AQ_LARGE_BUF)
7134                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7135                 desc.datalen = CPU_TO_LE16(msglen);
7136         }
7137         if (!cmd_details) {
7138                 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
7139                 details.async = true;
7140                 cmd_details = &details;
7141         }
7142         status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
7143                                        msglen, cmd_details);
7144         return status;
7145 }
7146
7147 /**
7148  * i40e_vf_parse_hw_config
7149  * @hw: pointer to the hardware structure
7150  * @msg: pointer to the virtual channel VF resource structure
7151  *
7152  * Given a VF resource message from the PF, populate the hw struct
7153  * with appropriate information.
7154  **/
7155 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
7156                              struct virtchnl_vf_resource *msg)
7157 {
7158         struct virtchnl_vsi_resource *vsi_res;
7159         int i;
7160
7161         vsi_res = &msg->vsi_res[0];
7162
7163         hw->dev_caps.num_vsis = msg->num_vsis;
7164         hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
7165         hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
7166         hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
7167         hw->dev_caps.dcb = msg->vf_cap_flags &
7168                            VIRTCHNL_VF_OFFLOAD_L2;
7169         hw->dev_caps.iwarp = (msg->vf_cap_flags &
7170                               VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
7171         for (i = 0; i < msg->num_vsis; i++) {
7172                 if (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) {
7173                         i40e_memcpy(hw->mac.perm_addr,
7174                                     vsi_res->default_mac_addr,
7175                                     ETH_ALEN,
7176                                     I40E_NONDMA_TO_NONDMA);
7177                         i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
7178                                     ETH_ALEN,
7179                                     I40E_NONDMA_TO_NONDMA);
7180                 }
7181                 vsi_res++;
7182         }
7183 }
7184
7185 /**
7186  * i40e_vf_reset
7187  * @hw: pointer to the hardware structure
7188  *
7189  * Send a VF_RESET message to the PF. Does not wait for response from PF
7190  * as none will be forthcoming. Immediately after calling this function,
7191  * the admin queue should be shut down and (optionally) reinitialized.
7192  **/
7193 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
7194 {
7195         return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF,
7196                                       I40E_SUCCESS, NULL, 0, NULL);
7197 }
7198 #endif /* VF_DRIVER */
7199
7200 /**
7201  * i40e_aq_set_arp_proxy_config
7202  * @hw: pointer to the HW structure
7203  * @proxy_config: pointer to proxy config command table struct
7204  * @cmd_details: pointer to command details
7205  *
7206  * Set ARP offload parameters from pre-populated
7207  * i40e_aqc_arp_proxy_data struct
7208  **/
7209 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
7210                                 struct i40e_aqc_arp_proxy_data *proxy_config,
7211                                 struct i40e_asq_cmd_details *cmd_details)
7212 {
7213         struct i40e_aq_desc desc;
7214         enum i40e_status_code status;
7215
7216         if (!proxy_config)
7217                 return I40E_ERR_PARAM;
7218
7219         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
7220
7221         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7222         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7223         desc.params.external.addr_high =
7224                                   CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
7225         desc.params.external.addr_low =
7226                                   CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
7227         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_arp_proxy_data));
7228
7229         status = i40e_asq_send_command(hw, &desc, proxy_config,
7230                                        sizeof(struct i40e_aqc_arp_proxy_data),
7231                                        cmd_details);
7232
7233         return status;
7234 }
7235
7236 /**
7237  * i40e_aq_opc_set_ns_proxy_table_entry
7238  * @hw: pointer to the HW structure
7239  * @ns_proxy_table_entry: pointer to NS table entry command struct
7240  * @cmd_details: pointer to command details
7241  *
7242  * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
7243  * from pre-populated i40e_aqc_ns_proxy_data struct
7244  **/
7245 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
7246                         struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
7247                         struct i40e_asq_cmd_details *cmd_details)
7248 {
7249         struct i40e_aq_desc desc;
7250         enum i40e_status_code status;
7251
7252         if (!ns_proxy_table_entry)
7253                 return I40E_ERR_PARAM;
7254
7255         i40e_fill_default_direct_cmd_desc(&desc,
7256                                 i40e_aqc_opc_set_ns_proxy_table_entry);
7257
7258         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7259         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7260         desc.params.external.addr_high =
7261                 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
7262         desc.params.external.addr_low =
7263                 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
7264         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_ns_proxy_data));
7265
7266         status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
7267                                        sizeof(struct i40e_aqc_ns_proxy_data),
7268                                        cmd_details);
7269
7270         return status;
7271 }
7272
7273 /**
7274  * i40e_aq_set_clear_wol_filter
7275  * @hw: pointer to the hw struct
7276  * @filter_index: index of filter to modify (0-7)
7277  * @filter: buffer containing filter to be set
7278  * @set_filter: true to set filter, false to clear filter
7279  * @no_wol_tco: if true, pass through packets cannot cause wake-up
7280  *              if false, pass through packets may cause wake-up
7281  * @filter_valid: true if filter action is valid
7282  * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
7283  * @cmd_details: pointer to command details structure or NULL
7284  *
7285  * Set or clear WoL filter for port attached to the PF
7286  **/
7287 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
7288                                 u8 filter_index,
7289                                 struct i40e_aqc_set_wol_filter_data *filter,
7290                                 bool set_filter, bool no_wol_tco,
7291                                 bool filter_valid, bool no_wol_tco_valid,
7292                                 struct i40e_asq_cmd_details *cmd_details)
7293 {
7294         struct i40e_aq_desc desc;
7295         struct i40e_aqc_set_wol_filter *cmd =
7296                 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
7297         enum i40e_status_code status;
7298         u16 cmd_flags = 0;
7299         u16 valid_flags = 0;
7300         u16 buff_len = 0;
7301
7302         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
7303
7304         if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
7305                 return  I40E_ERR_PARAM;
7306         cmd->filter_index = CPU_TO_LE16(filter_index);
7307
7308         if (set_filter) {
7309                 if (!filter)
7310                         return  I40E_ERR_PARAM;
7311
7312                 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
7313                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR;
7314         }
7315
7316         if (no_wol_tco)
7317                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
7318         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
7319
7320         if (filter_valid)
7321                 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
7322         if (no_wol_tco_valid)
7323                 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
7324         cmd->valid_flags = CPU_TO_LE16(valid_flags);
7325
7326         buff_len = sizeof(*filter);
7327         desc.datalen = CPU_TO_LE16(buff_len);
7328
7329         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7330         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7331
7332         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
7333         cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
7334
7335         status = i40e_asq_send_command(hw, &desc, filter,
7336                                        buff_len, cmd_details);
7337
7338         return status;
7339 }
7340
7341 /**
7342  * i40e_aq_get_wake_event_reason
7343  * @hw: pointer to the hw struct
7344  * @wake_reason: return value, index of matching filter
7345  * @cmd_details: pointer to command details structure or NULL
7346  *
7347  * Get information for the reason of a Wake Up event
7348  **/
7349 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
7350                                 u16 *wake_reason,
7351                                 struct i40e_asq_cmd_details *cmd_details)
7352 {
7353         struct i40e_aq_desc desc;
7354         struct i40e_aqc_get_wake_reason_completion *resp =
7355                 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
7356         enum i40e_status_code status;
7357
7358         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
7359
7360         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7361
7362         if (status == I40E_SUCCESS)
7363                 *wake_reason = LE16_TO_CPU(resp->wake_reason);
7364
7365         return status;
7366 }
7367
7368 /**
7369 * i40e_aq_clear_all_wol_filters
7370 * @hw: pointer to the hw struct
7371 * @cmd_details: pointer to command details structure or NULL
7372 *
7373 * Get information for the reason of a Wake Up event
7374 **/
7375 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw,
7376         struct i40e_asq_cmd_details *cmd_details)
7377 {
7378         struct i40e_aq_desc desc;
7379         enum i40e_status_code status;
7380
7381         i40e_fill_default_direct_cmd_desc(&desc,
7382                                           i40e_aqc_opc_clear_all_wol_filters);
7383
7384         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7385
7386         return status;
7387 }
7388
7389 /**
7390  * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
7391  * @hw: pointer to the hw struct
7392  * @buff: command buffer (size in bytes = buff_size)
7393  * @buff_size: buffer size in bytes
7394  * @track_id: package tracking id
7395  * @error_offset: returns error offset
7396  * @error_info: returns error information
7397  * @cmd_details: pointer to command details structure or NULL
7398  **/
7399 enum
7400 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
7401                                    u16 buff_size, u32 track_id,
7402                                    u32 *error_offset, u32 *error_info,
7403                                    struct i40e_asq_cmd_details *cmd_details)
7404 {
7405         struct i40e_aq_desc desc;
7406         struct i40e_aqc_write_personalization_profile *cmd =
7407                 (struct i40e_aqc_write_personalization_profile *)
7408                 &desc.params.raw;
7409         struct i40e_aqc_write_ddp_resp *resp;
7410         enum i40e_status_code status;
7411
7412         i40e_fill_default_direct_cmd_desc(&desc,
7413                                   i40e_aqc_opc_write_personalization_profile);
7414
7415         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
7416         if (buff_size > I40E_AQ_LARGE_BUF)
7417                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7418
7419         desc.datalen = CPU_TO_LE16(buff_size);
7420
7421         cmd->profile_track_id = CPU_TO_LE32(track_id);
7422
7423         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7424         if (!status) {
7425                 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
7426                 if (error_offset)
7427                         *error_offset = LE32_TO_CPU(resp->error_offset);
7428                 if (error_info)
7429                         *error_info = LE32_TO_CPU(resp->error_info);
7430         }
7431
7432         return status;
7433 }
7434
7435 /**
7436  * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
7437  * @hw: pointer to the hw struct
7438  * @buff: command buffer (size in bytes = buff_size)
7439  * @buff_size: buffer size in bytes
7440  * @flags: AdminQ command flags
7441  * @cmd_details: pointer to command details structure or NULL
7442  **/
7443 enum
7444 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
7445                                       u16 buff_size, u8 flags,
7446                                       struct i40e_asq_cmd_details *cmd_details)
7447 {
7448         struct i40e_aq_desc desc;
7449         struct i40e_aqc_get_applied_profiles *cmd =
7450                 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
7451         enum i40e_status_code status;
7452
7453         i40e_fill_default_direct_cmd_desc(&desc,
7454                           i40e_aqc_opc_get_personalization_profile_list);
7455
7456         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7457         if (buff_size > I40E_AQ_LARGE_BUF)
7458                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7459         desc.datalen = CPU_TO_LE16(buff_size);
7460
7461         cmd->flags = flags;
7462
7463         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7464
7465         return status;
7466 }
7467
7468 /**
7469  * i40e_find_segment_in_package
7470  * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
7471  * @pkg_hdr: pointer to the package header to be searched
7472  *
7473  * This function searches a package file for a particular segment type. On
7474  * success it returns a pointer to the segment header, otherwise it will
7475  * return NULL.
7476  **/
7477 struct i40e_generic_seg_header *
7478 i40e_find_segment_in_package(u32 segment_type,
7479                              struct i40e_package_header *pkg_hdr)
7480 {
7481         struct i40e_generic_seg_header *segment;
7482         u32 i;
7483
7484         /* Search all package segments for the requested segment type */
7485         for (i = 0; i < pkg_hdr->segment_count; i++) {
7486                 segment =
7487                         (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
7488                          pkg_hdr->segment_offset[i]);
7489
7490                 if (segment->type == segment_type)
7491                         return segment;
7492         }
7493
7494         return NULL;
7495 }
7496
7497 /* Get section table in profile */
7498 #define I40E_SECTION_TABLE(profile, sec_tbl)                            \
7499         do {                                                            \
7500                 struct i40e_profile_segment *p = (profile);             \
7501                 u32 count;                                              \
7502                 u32 *nvm;                                               \
7503                 count = p->device_table_count;                          \
7504                 nvm = (u32 *)&p->device_table[count];                   \
7505                 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \
7506         } while (0)
7507
7508 /* Get section header in profile */
7509 #define I40E_SECTION_HEADER(profile, offset)                            \
7510         (struct i40e_profile_section_header *)((u8 *)(profile) + (offset))
7511
7512 /**
7513  * i40e_find_section_in_profile
7514  * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE)
7515  * @profile: pointer to the i40e segment header to be searched
7516  *
7517  * This function searches i40e segment for a particular section type. On
7518  * success it returns a pointer to the section header, otherwise it will
7519  * return NULL.
7520  **/
7521 struct i40e_profile_section_header *
7522 i40e_find_section_in_profile(u32 section_type,
7523                              struct i40e_profile_segment *profile)
7524 {
7525         struct i40e_profile_section_header *sec;
7526         struct i40e_section_table *sec_tbl;
7527         u32 sec_off;
7528         u32 i;
7529
7530         if (profile->header.type != SEGMENT_TYPE_I40E)
7531                 return NULL;
7532
7533         I40E_SECTION_TABLE(profile, sec_tbl);
7534
7535         for (i = 0; i < sec_tbl->section_count; i++) {
7536                 sec_off = sec_tbl->section_offset[i];
7537                 sec = I40E_SECTION_HEADER(profile, sec_off);
7538                 if (sec->section.type == section_type)
7539                         return sec;
7540         }
7541
7542         return NULL;
7543 }
7544
7545 /**
7546  * i40e_ddp_exec_aq_section - Execute generic AQ for DDP
7547  * @hw: pointer to the hw struct
7548  * @aq: command buffer containing all data to execute AQ
7549  **/
7550 STATIC enum
7551 i40e_status_code i40e_ddp_exec_aq_section(struct i40e_hw *hw,
7552                                           struct i40e_profile_aq_section *aq)
7553 {
7554         enum i40e_status_code status;
7555         struct i40e_aq_desc desc;
7556         u8 *msg = NULL;
7557         u16 msglen;
7558
7559         i40e_fill_default_direct_cmd_desc(&desc, aq->opcode);
7560         desc.flags |= CPU_TO_LE16(aq->flags);
7561         i40e_memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw),
7562                     I40E_NONDMA_TO_NONDMA);
7563
7564         msglen = aq->datalen;
7565         if (msglen) {
7566                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
7567                                                 I40E_AQ_FLAG_RD));
7568                 if (msglen > I40E_AQ_LARGE_BUF)
7569                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7570                 desc.datalen = CPU_TO_LE16(msglen);
7571                 msg = &aq->data[0];
7572         }
7573
7574         status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL);
7575
7576         if (status != I40E_SUCCESS) {
7577                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7578                            "unable to exec DDP AQ opcode %u, error %d\n",
7579                            aq->opcode, status);
7580                 return status;
7581         }
7582
7583         /* copy returned desc to aq_buf */
7584         i40e_memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw),
7585                     I40E_NONDMA_TO_NONDMA);
7586
7587         return I40E_SUCCESS;
7588 }
7589
7590 /**
7591  * i40e_validate_profile
7592  * @hw: pointer to the hardware structure
7593  * @profile: pointer to the profile segment of the package to be validated
7594  * @track_id: package tracking id
7595  * @rollback: flag if the profile is for rollback.
7596  *
7597  * Validates supported devices and profile's sections.
7598  */
7599 STATIC enum i40e_status_code
7600 i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7601                       u32 track_id, bool rollback)
7602 {
7603         struct i40e_profile_section_header *sec = NULL;
7604         enum i40e_status_code status = I40E_SUCCESS;
7605         struct i40e_section_table *sec_tbl;
7606         u32 vendor_dev_id;
7607         u32 dev_cnt;
7608         u32 sec_off;
7609         u32 i;
7610
7611         if (track_id == I40E_DDP_TRACKID_INVALID) {
7612                 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n");
7613                 return I40E_NOT_SUPPORTED;
7614         }
7615
7616         dev_cnt = profile->device_table_count;
7617         for (i = 0; i < dev_cnt; i++) {
7618                 vendor_dev_id = profile->device_table[i].vendor_dev_id;
7619                 if ((vendor_dev_id >> 16) == I40E_INTEL_VENDOR_ID &&
7620                     hw->device_id == (vendor_dev_id & 0xFFFF))
7621                         break;
7622         }
7623         if (dev_cnt && (i == dev_cnt)) {
7624                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7625                            "Device doesn't support DDP\n");
7626                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
7627         }
7628
7629         I40E_SECTION_TABLE(profile, sec_tbl);
7630
7631         /* Validate sections types */
7632         for (i = 0; i < sec_tbl->section_count; i++) {
7633                 sec_off = sec_tbl->section_offset[i];
7634                 sec = I40E_SECTION_HEADER(profile, sec_off);
7635                 if (rollback) {
7636                         if (sec->section.type == SECTION_TYPE_MMIO ||
7637                             sec->section.type == SECTION_TYPE_AQ ||
7638                             sec->section.type == SECTION_TYPE_RB_AQ) {
7639                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7640                                            "Not a roll-back package\n");
7641                                 return I40E_NOT_SUPPORTED;
7642                         }
7643                 } else {
7644                         if (sec->section.type == SECTION_TYPE_RB_AQ ||
7645                             sec->section.type == SECTION_TYPE_RB_MMIO) {
7646                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7647                                            "Not an original package\n");
7648                                 return I40E_NOT_SUPPORTED;
7649                         }
7650                 }
7651         }
7652
7653         return status;
7654 }
7655
7656 /**
7657  * i40e_write_profile
7658  * @hw: pointer to the hardware structure
7659  * @profile: pointer to the profile segment of the package to be downloaded
7660  * @track_id: package tracking id
7661  *
7662  * Handles the download of a complete package.
7663  */
7664 enum i40e_status_code
7665 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7666                    u32 track_id)
7667 {
7668         enum i40e_status_code status = I40E_SUCCESS;
7669         struct i40e_section_table *sec_tbl;
7670         struct i40e_profile_section_header *sec = NULL;
7671         struct i40e_profile_aq_section *ddp_aq;
7672         u32 section_size = 0;
7673         u32 offset = 0, info = 0;
7674         u32 sec_off;
7675         u32 i;
7676
7677         status = i40e_validate_profile(hw, profile, track_id, false);
7678         if (status)
7679                 return status;
7680
7681         I40E_SECTION_TABLE(profile, sec_tbl);
7682
7683         for (i = 0; i < sec_tbl->section_count; i++) {
7684                 sec_off = sec_tbl->section_offset[i];
7685                 sec = I40E_SECTION_HEADER(profile, sec_off);
7686                 /* Process generic admin command */
7687                 if (sec->section.type == SECTION_TYPE_AQ) {
7688                         ddp_aq = (struct i40e_profile_aq_section *)&sec[1];
7689                         status = i40e_ddp_exec_aq_section(hw, ddp_aq);
7690                         if (status) {
7691                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7692                                            "Failed to execute aq: section %d, opcode %u\n",
7693                                            i, ddp_aq->opcode);
7694                                 break;
7695                         }
7696                         sec->section.type = SECTION_TYPE_RB_AQ;
7697                 }
7698
7699                 /* Skip any non-mmio sections */
7700                 if (sec->section.type != SECTION_TYPE_MMIO)
7701                         continue;
7702
7703                 section_size = sec->section.size +
7704                         sizeof(struct i40e_profile_section_header);
7705
7706                 /* Write MMIO section */
7707                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
7708                                            track_id, &offset, &info, NULL);
7709                 if (status) {
7710                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
7711                                    "Failed to write profile: section %d, offset %d, info %d\n",
7712                                    i, offset, info);
7713                         break;
7714                 }
7715         }
7716         return status;
7717 }
7718
7719 /**
7720  * i40e_rollback_profile
7721  * @hw: pointer to the hardware structure
7722  * @profile: pointer to the profile segment of the package to be removed
7723  * @track_id: package tracking id
7724  *
7725  * Rolls back previously loaded package.
7726  */
7727 enum i40e_status_code
7728 i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7729                       u32 track_id)
7730 {
7731         struct i40e_profile_section_header *sec = NULL;
7732         enum i40e_status_code status = I40E_SUCCESS;
7733         struct i40e_section_table *sec_tbl;
7734         u32 offset = 0, info = 0;
7735         u32 section_size = 0;
7736         u32 sec_off;
7737         int i;
7738
7739         status = i40e_validate_profile(hw, profile, track_id, true);
7740         if (status)
7741                 return status;
7742
7743         I40E_SECTION_TABLE(profile, sec_tbl);
7744
7745         /* For rollback write sections in reverse */
7746         for (i = sec_tbl->section_count - 1; i >= 0; i--) {
7747                 sec_off = sec_tbl->section_offset[i];
7748                 sec = I40E_SECTION_HEADER(profile, sec_off);
7749
7750                 /* Skip any non-rollback sections */
7751                 if (sec->section.type != SECTION_TYPE_RB_MMIO)
7752                         continue;
7753
7754                 section_size = sec->section.size +
7755                         sizeof(struct i40e_profile_section_header);
7756
7757                 /* Write roll-back MMIO section */
7758                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
7759                                            track_id, &offset, &info, NULL);
7760                 if (status) {
7761                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
7762                                    "Failed to write profile: section %d, offset %d, info %d\n",
7763                                    i, offset, info);
7764                         break;
7765                 }
7766         }
7767         return status;
7768 }
7769
7770 /**
7771  * i40e_add_pinfo_to_list
7772  * @hw: pointer to the hardware structure
7773  * @profile: pointer to the profile segment of the package
7774  * @profile_info_sec: buffer for information section
7775  * @track_id: package tracking id
7776  *
7777  * Register a profile to the list of loaded profiles.
7778  */
7779 enum i40e_status_code
7780 i40e_add_pinfo_to_list(struct i40e_hw *hw,
7781                        struct i40e_profile_segment *profile,
7782                        u8 *profile_info_sec, u32 track_id)
7783 {
7784         enum i40e_status_code status = I40E_SUCCESS;
7785         struct i40e_profile_section_header *sec = NULL;
7786         struct i40e_profile_info *pinfo;
7787         u32 offset = 0, info = 0;
7788
7789         sec = (struct i40e_profile_section_header *)profile_info_sec;
7790         sec->tbl_size = 1;
7791         sec->data_end = sizeof(struct i40e_profile_section_header) +
7792                         sizeof(struct i40e_profile_info);
7793         sec->section.type = SECTION_TYPE_INFO;
7794         sec->section.offset = sizeof(struct i40e_profile_section_header);
7795         sec->section.size = sizeof(struct i40e_profile_info);
7796         pinfo = (struct i40e_profile_info *)(profile_info_sec +
7797                                              sec->section.offset);
7798         pinfo->track_id = track_id;
7799         pinfo->version = profile->version;
7800         pinfo->op = I40E_DDP_ADD_TRACKID;
7801         i40e_memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE,
7802                     I40E_NONDMA_TO_NONDMA);
7803
7804         status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
7805                                    track_id, &offset, &info, NULL);
7806         return status;
7807 }