drivers/net/i40e/base/i40e_common.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "i40e_type.h"
  35 #include "i40e_adminq.h"
  36 #include "i40e_prototype.h"
  37 #include "i40e_virtchnl.h"
  38
  39
  40 /**
  41  * i40e_set_mac_type - Sets MAC type
  42  * @hw: pointer to the HW structure
  43  *
  44  * This function sets the mac type of the adapter based on the
  45  * vendor ID and device ID stored in the hw structure.
  46  **/
  47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  49 #else
  50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  51 #endif
  52 {
  53         enum i40e_status_code status = I40E_SUCCESS;
  54
  55         DEBUGFUNC("i40e_set_mac_type\n");
  56
  57         if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
  58                 switch (hw->device_id) {
  59                 case I40E_DEV_ID_SFP_XL710:
  60                 case I40E_DEV_ID_QEMU:
  61                 case I40E_DEV_ID_KX_A:
  62                 case I40E_DEV_ID_KX_B:
  63                 case I40E_DEV_ID_KX_C:
  64                 case I40E_DEV_ID_QSFP_A:
  65                 case I40E_DEV_ID_QSFP_B:
  66                 case I40E_DEV_ID_QSFP_C:
  67                 case I40E_DEV_ID_10G_BASE_T:
  68                 case I40E_DEV_ID_10G_BASE_T4:
  69                 case I40E_DEV_ID_20G_KR2:
  70                 case I40E_DEV_ID_20G_KR2_A:
  71                         hw->mac.type = I40E_MAC_XL710;
  72                         break;
  73 #ifdef X722_SUPPORT
  74 #ifdef X722_A0_SUPPORT
  75                 case I40E_DEV_ID_X722_A0:
  76 #endif
  77                 case I40E_DEV_ID_SFP_X722:
  78                 case I40E_DEV_ID_1G_BASE_T_X722:
  79                 case I40E_DEV_ID_10G_BASE_T_X722:
  80                         hw->mac.type = I40E_MAC_X722;
  81                         break;
  82 #endif
  83 #ifdef X722_SUPPORT
  84                 case I40E_DEV_ID_X722_VF:
  85                 case I40E_DEV_ID_X722_VF_HV:
  86                         hw->mac.type = I40E_MAC_X722_VF;
  87                         break;
  88 #endif
  89                 case I40E_DEV_ID_VF:
  90                 case I40E_DEV_ID_VF_HV:
  91                         hw->mac.type = I40E_MAC_VF;
  92                         break;
  93                 default:
  94                         hw->mac.type = I40E_MAC_GENERIC;
  95                         break;
  96                 }
  97         } else {
  98                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
  99         }
 100
 101         DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
 102                   hw->mac.type, status);
 103         return status;
 104 }
 105
 106 #ifndef I40E_NDIS_SUPPORT
 107 /**
 108  * i40e_aq_str - convert AQ err code to a string
 109  * @hw: pointer to the HW structure
 110  * @aq_err: the AQ error code to convert
 111  **/
 112 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
 113 {
 114         switch (aq_err) {
 115         case I40E_AQ_RC_OK:
 116                 return "OK";
 117         case I40E_AQ_RC_EPERM:
 118                 return "I40E_AQ_RC_EPERM";
 119         case I40E_AQ_RC_ENOENT:
 120                 return "I40E_AQ_RC_ENOENT";
 121         case I40E_AQ_RC_ESRCH:
 122                 return "I40E_AQ_RC_ESRCH";
 123         case I40E_AQ_RC_EINTR:
 124                 return "I40E_AQ_RC_EINTR";
 125         case I40E_AQ_RC_EIO:
 126                 return "I40E_AQ_RC_EIO";
 127         case I40E_AQ_RC_ENXIO:
 128                 return "I40E_AQ_RC_ENXIO";
 129         case I40E_AQ_RC_E2BIG:
 130                 return "I40E_AQ_RC_E2BIG";
 131         case I40E_AQ_RC_EAGAIN:
 132                 return "I40E_AQ_RC_EAGAIN";
 133         case I40E_AQ_RC_ENOMEM:
 134                 return "I40E_AQ_RC_ENOMEM";
 135         case I40E_AQ_RC_EACCES:
 136                 return "I40E_AQ_RC_EACCES";
 137         case I40E_AQ_RC_EFAULT:
 138                 return "I40E_AQ_RC_EFAULT";
 139         case I40E_AQ_RC_EBUSY:
 140                 return "I40E_AQ_RC_EBUSY";
 141         case I40E_AQ_RC_EEXIST:
 142                 return "I40E_AQ_RC_EEXIST";
 143         case I40E_AQ_RC_EINVAL:
 144                 return "I40E_AQ_RC_EINVAL";
 145         case I40E_AQ_RC_ENOTTY:
 146                 return "I40E_AQ_RC_ENOTTY";
 147         case I40E_AQ_RC_ENOSPC:
 148                 return "I40E_AQ_RC_ENOSPC";
 149         case I40E_AQ_RC_ENOSYS:
 150                 return "I40E_AQ_RC_ENOSYS";
 151         case I40E_AQ_RC_ERANGE:
 152                 return "I40E_AQ_RC_ERANGE";
 153         case I40E_AQ_RC_EFLUSHED:
 154                 return "I40E_AQ_RC_EFLUSHED";
 155         case I40E_AQ_RC_BAD_ADDR:
 156                 return "I40E_AQ_RC_BAD_ADDR";
 157         case I40E_AQ_RC_EMODE:
 158                 return "I40E_AQ_RC_EMODE";
 159         case I40E_AQ_RC_EFBIG:
 160                 return "I40E_AQ_RC_EFBIG";
 161         }
 162
 163         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 164         return hw->err_str;
 165 }
 166
 167 /**
 168  * i40e_stat_str - convert status err code to a string
 169  * @hw: pointer to the HW structure
 170  * @stat_err: the status error code to convert
 171  **/
 172 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
 173 {
 174         switch (stat_err) {
 175         case I40E_SUCCESS:
 176                 return "OK";
 177         case I40E_ERR_NVM:
 178                 return "I40E_ERR_NVM";
 179         case I40E_ERR_NVM_CHECKSUM:
 180                 return "I40E_ERR_NVM_CHECKSUM";
 181         case I40E_ERR_PHY:
 182                 return "I40E_ERR_PHY";
 183         case I40E_ERR_CONFIG:
 184                 return "I40E_ERR_CONFIG";
 185         case I40E_ERR_PARAM:
 186                 return "I40E_ERR_PARAM";
 187         case I40E_ERR_MAC_TYPE:
 188                 return "I40E_ERR_MAC_TYPE";
 189         case I40E_ERR_UNKNOWN_PHY:
 190                 return "I40E_ERR_UNKNOWN_PHY";
 191         case I40E_ERR_LINK_SETUP:
 192                 return "I40E_ERR_LINK_SETUP";
 193         case I40E_ERR_ADAPTER_STOPPED:
 194                 return "I40E_ERR_ADAPTER_STOPPED";
 195         case I40E_ERR_INVALID_MAC_ADDR:
 196                 return "I40E_ERR_INVALID_MAC_ADDR";
 197         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 198                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 199         case I40E_ERR_MASTER_REQUESTS_PENDING:
 200                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 201         case I40E_ERR_INVALID_LINK_SETTINGS:
 202                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 203         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 204                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 205         case I40E_ERR_RESET_FAILED:
 206                 return "I40E_ERR_RESET_FAILED";
 207         case I40E_ERR_SWFW_SYNC:
 208                 return "I40E_ERR_SWFW_SYNC";
 209         case I40E_ERR_NO_AVAILABLE_VSI:
 210                 return "I40E_ERR_NO_AVAILABLE_VSI";
 211         case I40E_ERR_NO_MEMORY:
 212                 return "I40E_ERR_NO_MEMORY";
 213         case I40E_ERR_BAD_PTR:
 214                 return "I40E_ERR_BAD_PTR";
 215         case I40E_ERR_RING_FULL:
 216                 return "I40E_ERR_RING_FULL";
 217         case I40E_ERR_INVALID_PD_ID:
 218                 return "I40E_ERR_INVALID_PD_ID";
 219         case I40E_ERR_INVALID_QP_ID:
 220                 return "I40E_ERR_INVALID_QP_ID";
 221         case I40E_ERR_INVALID_CQ_ID:
 222                 return "I40E_ERR_INVALID_CQ_ID";
 223         case I40E_ERR_INVALID_CEQ_ID:
 224                 return "I40E_ERR_INVALID_CEQ_ID";
 225         case I40E_ERR_INVALID_AEQ_ID:
 226                 return "I40E_ERR_INVALID_AEQ_ID";
 227         case I40E_ERR_INVALID_SIZE:
 228                 return "I40E_ERR_INVALID_SIZE";
 229         case I40E_ERR_INVALID_ARP_INDEX:
 230                 return "I40E_ERR_INVALID_ARP_INDEX";
 231         case I40E_ERR_INVALID_FPM_FUNC_ID:
 232                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 233         case I40E_ERR_QP_INVALID_MSG_SIZE:
 234                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 235         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 236                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 237         case I40E_ERR_INVALID_FRAG_COUNT:
 238                 return "I40E_ERR_INVALID_FRAG_COUNT";
 239         case I40E_ERR_QUEUE_EMPTY:
 240                 return "I40E_ERR_QUEUE_EMPTY";
 241         case I40E_ERR_INVALID_ALIGNMENT:
 242                 return "I40E_ERR_INVALID_ALIGNMENT";
 243         case I40E_ERR_FLUSHED_QUEUE:
 244                 return "I40E_ERR_FLUSHED_QUEUE";
 245         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 246                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 247         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 248                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 249         case I40E_ERR_TIMEOUT:
 250                 return "I40E_ERR_TIMEOUT";
 251         case I40E_ERR_OPCODE_MISMATCH:
 252                 return "I40E_ERR_OPCODE_MISMATCH";
 253         case I40E_ERR_CQP_COMPL_ERROR:
 254                 return "I40E_ERR_CQP_COMPL_ERROR";
 255         case I40E_ERR_INVALID_VF_ID:
 256                 return "I40E_ERR_INVALID_VF_ID";
 257         case I40E_ERR_INVALID_HMCFN_ID:
 258                 return "I40E_ERR_INVALID_HMCFN_ID";
 259         case I40E_ERR_BACKING_PAGE_ERROR:
 260                 return "I40E_ERR_BACKING_PAGE_ERROR";
 261         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 262                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 263         case I40E_ERR_INVALID_PBLE_INDEX:
 264                 return "I40E_ERR_INVALID_PBLE_INDEX";
 265         case I40E_ERR_INVALID_SD_INDEX:
 266                 return "I40E_ERR_INVALID_SD_INDEX";
 267         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 268                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 269         case I40E_ERR_INVALID_SD_TYPE:
 270                 return "I40E_ERR_INVALID_SD_TYPE";
 271         case I40E_ERR_MEMCPY_FAILED:
 272                 return "I40E_ERR_MEMCPY_FAILED";
 273         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 274                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 275         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 276                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 277         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 278                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 279         case I40E_ERR_SRQ_ENABLED:
 280                 return "I40E_ERR_SRQ_ENABLED";
 281         case I40E_ERR_ADMIN_QUEUE_ERROR:
 282                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 283         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 284                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 285         case I40E_ERR_BUF_TOO_SHORT:
 286                 return "I40E_ERR_BUF_TOO_SHORT";
 287         case I40E_ERR_ADMIN_QUEUE_FULL:
 288                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 289         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 290                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 291         case I40E_ERR_BAD_IWARP_CQE:
 292                 return "I40E_ERR_BAD_IWARP_CQE";
 293         case I40E_ERR_NVM_BLANK_MODE:
 294                 return "I40E_ERR_NVM_BLANK_MODE";
 295         case I40E_ERR_NOT_IMPLEMENTED:
 296                 return "I40E_ERR_NOT_IMPLEMENTED";
 297         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 298                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 299         case I40E_ERR_DIAG_TEST_FAILED:
 300                 return "I40E_ERR_DIAG_TEST_FAILED";
 301         case I40E_ERR_NOT_READY:
 302                 return "I40E_ERR_NOT_READY";
 303         case I40E_NOT_SUPPORTED:
 304                 return "I40E_NOT_SUPPORTED";
 305         case I40E_ERR_FIRMWARE_API_VERSION:
 306                 return "I40E_ERR_FIRMWARE_API_VERSION";
 307         }
 308
 309         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 310         return hw->err_str;
 311 }
 312
 313 #endif /* I40E_NDIS_SUPPORT */
 314 /**
 315  * i40e_debug_aq
 316  * @hw: debug mask related to admin queue
 317  * @mask: debug mask
 318  * @desc: pointer to admin queue descriptor
 319  * @buffer: pointer to command buffer
 320  * @buf_len: max length of buffer
 321  *
 322  * Dumps debug log about adminq command with descriptor contents.
 323  **/
 324 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 325                    void *buffer, u16 buf_len)
 326 {
 327         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 328         u16 len = LE16_TO_CPU(aq_desc->datalen);
 329         u8 *buf = (u8 *)buffer;
 330         u16 i = 0;
 331
 332         if ((!(mask & hw->debug_mask)) || (desc == NULL))
 333                 return;
 334
 335         i40e_debug(hw, mask,
 336                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 337                    LE16_TO_CPU(aq_desc->opcode),
 338                    LE16_TO_CPU(aq_desc->flags),
 339                    LE16_TO_CPU(aq_desc->datalen),
 340                    LE16_TO_CPU(aq_desc->retval));
 341         i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
 342                    LE32_TO_CPU(aq_desc->cookie_high),
 343                    LE32_TO_CPU(aq_desc->cookie_low));
 344         i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
 345                    LE32_TO_CPU(aq_desc->params.internal.param0),
 346                    LE32_TO_CPU(aq_desc->params.internal.param1));
 347         i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
 348                    LE32_TO_CPU(aq_desc->params.external.addr_high),
 349                    LE32_TO_CPU(aq_desc->params.external.addr_low));
 350
 351         if ((buffer != NULL) && (aq_desc->datalen != 0)) {
 352                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 353                 if (buf_len < len)
 354                         len = buf_len;
 355                 /* write the full 16-byte chunks */
 356                 for (i = 0; i < (len - 16); i += 16)
 357                         i40e_debug(hw, mask,
 358                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 359                                    i, buf[i], buf[i+1], buf[i+2], buf[i+3],
 360                                    buf[i+4], buf[i+5], buf[i+6], buf[i+7],
 361                                    buf[i+8], buf[i+9], buf[i+10], buf[i+11],
 362                                    buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
 363                 /* the most we could have left is 16 bytes, pad with zeros */
 364                 if (i < len) {
 365                         char d_buf[16];
 366                         int j;
 367
 368                         memset(d_buf, 0, sizeof(d_buf));
 369                         for (j = 0; i < len; j++, i++)
 370                                 d_buf[j] = buf[i];
 371                         i40e_debug(hw, mask,
 372                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 373                                    i, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
 374                                    d_buf[4], d_buf[5], d_buf[6], d_buf[7],
 375                                    d_buf[8], d_buf[9], d_buf[10], d_buf[11],
 376                                    d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
 377                 }
 378         }
 379 }
 380
 381 /**
 382  * i40e_check_asq_alive
 383  * @hw: pointer to the hw struct
 384  *
 385  * Returns true if Queue is enabled else false.
 386  **/
 387 bool i40e_check_asq_alive(struct i40e_hw *hw)
 388 {
 389         if (hw->aq.asq.len)
 390 #ifdef PF_DRIVER
 391 #ifdef INTEGRATED_VF
 392                 if (!i40e_is_vf(hw))
 393                         return !!(rd32(hw, hw->aq.asq.len) &
 394                                 I40E_PF_ATQLEN_ATQENABLE_MASK);
 395 #else
 396                 return !!(rd32(hw, hw->aq.asq.len) &
 397                         I40E_PF_ATQLEN_ATQENABLE_MASK);
 398 #endif /* INTEGRATED_VF */
 399 #endif /* PF_DRIVER */
 400 #ifdef VF_DRIVER
 401 #ifdef INTEGRATED_VF
 402                 if (i40e_is_vf(hw))
 403                         return !!(rd32(hw, hw->aq.asq.len) &
 404                                 I40E_VF_ATQLEN1_ATQENABLE_MASK);
 405 #else
 406                 return !!(rd32(hw, hw->aq.asq.len) &
 407                         I40E_VF_ATQLEN1_ATQENABLE_MASK);
 408 #endif /* INTEGRATED_VF */
 409 #endif /* VF_DRIVER */
 410         return false;
 411 }
 412
 413 /**
 414  * i40e_aq_queue_shutdown
 415  * @hw: pointer to the hw struct
 416  * @unloading: is the driver unloading itself
 417  *
 418  * Tell the Firmware that we're shutting down the AdminQ and whether
 419  * or not the driver is unloading as well.
 420  **/
 421 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
 422                                              bool unloading)
 423 {
 424         struct i40e_aq_desc desc;
 425         struct i40e_aqc_queue_shutdown *cmd =
 426                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 427         enum i40e_status_code status;
 428
 429         i40e_fill_default_direct_cmd_desc(&desc,
 430                                           i40e_aqc_opc_queue_shutdown);
 431
 432         if (unloading)
 433                 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
 434         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 435
 436         return status;
 437 }
 438
 439 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 440  * hardware to a bit-field that can be used by SW to more easily determine the
 441  * packet type.
 442  *
 443  * Macros are used to shorten the table lines and make this table human
 444  * readable.
 445  *
 446  * We store the PTYPE in the top byte of the bit field - this is just so that
 447  * we can check that the table doesn't have a row missing, as the index into
 448  * the table should be the PTYPE.
 449  *
 450  * Typical work flow:
 451  *
 452  * IF NOT i40e_ptype_lookup[ptype].known
 453  * THEN
 454  *      Packet is unknown
 455  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 456  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 457  * ELSE
 458  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 459  * ENDIF
 460  */
 461
 462 /* macro to make the table lines short */
 463 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 464         {       PTYPE, \
 465                 1, \
 466                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 467                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 468                 I40E_RX_PTYPE_##OUTER_FRAG, \
 469                 I40E_RX_PTYPE_TUNNEL_##T, \
 470                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 471                 I40E_RX_PTYPE_##TEF, \
 472                 I40E_RX_PTYPE_INNER_PROT_##I, \
 473                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 474
 475 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 476                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 477
 478 /* shorter macros makes the table fit but are terse */
 479 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 480 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 481 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 482
 483 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 484 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 485         /* L2 Packet types */
 486         I40E_PTT_UNUSED_ENTRY(0),
 487         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 488         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 489         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 490         I40E_PTT_UNUSED_ENTRY(4),
 491         I40E_PTT_UNUSED_ENTRY(5),
 492         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 493         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 494         I40E_PTT_UNUSED_ENTRY(8),
 495         I40E_PTT_UNUSED_ENTRY(9),
 496         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 497         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 498         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 499         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 500         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 501         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 502         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 503         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 504         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 505         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 506         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 507         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 508
 509         /* Non Tunneled IPv4 */
 510         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 511         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 512         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 513         I40E_PTT_UNUSED_ENTRY(25),
 514         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 515         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 516         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 517
 518         /* IPv4 --> IPv4 */
 519         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 520         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 521         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 522         I40E_PTT_UNUSED_ENTRY(32),
 523         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 524         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 525         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 526
 527         /* IPv4 --> IPv6 */
 528         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 529         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 530         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 531         I40E_PTT_UNUSED_ENTRY(39),
 532         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 533         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 534         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 535
 536         /* IPv4 --> GRE/NAT */
 537         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 538
 539         /* IPv4 --> GRE/NAT --> IPv4 */
 540         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 541         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 542         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 543         I40E_PTT_UNUSED_ENTRY(47),
 544         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 545         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 546         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 547
 548         /* IPv4 --> GRE/NAT --> IPv6 */
 549         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 550         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 551         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 552         I40E_PTT_UNUSED_ENTRY(54),
 553         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 554         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 555         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 556
 557         /* IPv4 --> GRE/NAT --> MAC */
 558         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 559
 560         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 561         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 562         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 563         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 564         I40E_PTT_UNUSED_ENTRY(62),
 565         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 566         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 567         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 568
 569         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 570         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 571         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 572         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 573         I40E_PTT_UNUSED_ENTRY(69),
 574         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 575         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 576         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 577
 578         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 579         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 580
 581         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 582         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 583         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 584         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 585         I40E_PTT_UNUSED_ENTRY(77),
 586         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 587         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 588         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 589
 590         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 591         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 592         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 593         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 594         I40E_PTT_UNUSED_ENTRY(84),
 595         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 596         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 597         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 598
 599         /* Non Tunneled IPv6 */
 600         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 601         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 602         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY3),
 603         I40E_PTT_UNUSED_ENTRY(91),
 604         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 605         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 606         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 607
 608         /* IPv6 --> IPv4 */
 609         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 610         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 611         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 612         I40E_PTT_UNUSED_ENTRY(98),
 613         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 614         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 615         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 616
 617         /* IPv6 --> IPv6 */
 618         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 619         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 620         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 621         I40E_PTT_UNUSED_ENTRY(105),
 622         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 623         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 624         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 625
 626         /* IPv6 --> GRE/NAT */
 627         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 628
 629         /* IPv6 --> GRE/NAT -> IPv4 */
 630         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 631         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 632         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 633         I40E_PTT_UNUSED_ENTRY(113),
 634         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 635         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 636         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 637
 638         /* IPv6 --> GRE/NAT -> IPv6 */
 639         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 640         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 641         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 642         I40E_PTT_UNUSED_ENTRY(120),
 643         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 644         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 645         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 646
 647         /* IPv6 --> GRE/NAT -> MAC */
 648         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 649
 650         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 651         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 652         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 653         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 654         I40E_PTT_UNUSED_ENTRY(128),
 655         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 656         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 657         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 658
 659         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 660         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 661         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 662         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 663         I40E_PTT_UNUSED_ENTRY(135),
 664         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 665         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 666         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 667
 668         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 669         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 670
 671         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 672         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 673         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 674         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 675         I40E_PTT_UNUSED_ENTRY(143),
 676         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 677         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 678         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 679
 680         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 681         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 682         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 683         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 684         I40E_PTT_UNUSED_ENTRY(150),
 685         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 686         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 687         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 688
 689         /* unused entries */
 690         I40E_PTT_UNUSED_ENTRY(154),
 691         I40E_PTT_UNUSED_ENTRY(155),
 692         I40E_PTT_UNUSED_ENTRY(156),
 693         I40E_PTT_UNUSED_ENTRY(157),
 694         I40E_PTT_UNUSED_ENTRY(158),
 695         I40E_PTT_UNUSED_ENTRY(159),
 696
 697         I40E_PTT_UNUSED_ENTRY(160),
 698         I40E_PTT_UNUSED_ENTRY(161),
 699         I40E_PTT_UNUSED_ENTRY(162),
 700         I40E_PTT_UNUSED_ENTRY(163),
 701         I40E_PTT_UNUSED_ENTRY(164),
 702         I40E_PTT_UNUSED_ENTRY(165),
 703         I40E_PTT_UNUSED_ENTRY(166),
 704         I40E_PTT_UNUSED_ENTRY(167),
 705         I40E_PTT_UNUSED_ENTRY(168),
 706         I40E_PTT_UNUSED_ENTRY(169),
 707
 708         I40E_PTT_UNUSED_ENTRY(170),
 709         I40E_PTT_UNUSED_ENTRY(171),
 710         I40E_PTT_UNUSED_ENTRY(172),
 711         I40E_PTT_UNUSED_ENTRY(173),
 712         I40E_PTT_UNUSED_ENTRY(174),
 713         I40E_PTT_UNUSED_ENTRY(175),
 714         I40E_PTT_UNUSED_ENTRY(176),
 715         I40E_PTT_UNUSED_ENTRY(177),
 716         I40E_PTT_UNUSED_ENTRY(178),
 717         I40E_PTT_UNUSED_ENTRY(179),
 718
 719         I40E_PTT_UNUSED_ENTRY(180),
 720         I40E_PTT_UNUSED_ENTRY(181),
 721         I40E_PTT_UNUSED_ENTRY(182),
 722         I40E_PTT_UNUSED_ENTRY(183),
 723         I40E_PTT_UNUSED_ENTRY(184),
 724         I40E_PTT_UNUSED_ENTRY(185),
 725         I40E_PTT_UNUSED_ENTRY(186),
 726         I40E_PTT_UNUSED_ENTRY(187),
 727         I40E_PTT_UNUSED_ENTRY(188),
 728         I40E_PTT_UNUSED_ENTRY(189),
 729
 730         I40E_PTT_UNUSED_ENTRY(190),
 731         I40E_PTT_UNUSED_ENTRY(191),
 732         I40E_PTT_UNUSED_ENTRY(192),
 733         I40E_PTT_UNUSED_ENTRY(193),
 734         I40E_PTT_UNUSED_ENTRY(194),
 735         I40E_PTT_UNUSED_ENTRY(195),
 736         I40E_PTT_UNUSED_ENTRY(196),
 737         I40E_PTT_UNUSED_ENTRY(197),
 738         I40E_PTT_UNUSED_ENTRY(198),
 739         I40E_PTT_UNUSED_ENTRY(199),
 740
 741         I40E_PTT_UNUSED_ENTRY(200),
 742         I40E_PTT_UNUSED_ENTRY(201),
 743         I40E_PTT_UNUSED_ENTRY(202),
 744         I40E_PTT_UNUSED_ENTRY(203),
 745         I40E_PTT_UNUSED_ENTRY(204),
 746         I40E_PTT_UNUSED_ENTRY(205),
 747         I40E_PTT_UNUSED_ENTRY(206),
 748         I40E_PTT_UNUSED_ENTRY(207),
 749         I40E_PTT_UNUSED_ENTRY(208),
 750         I40E_PTT_UNUSED_ENTRY(209),
 751
 752         I40E_PTT_UNUSED_ENTRY(210),
 753         I40E_PTT_UNUSED_ENTRY(211),
 754         I40E_PTT_UNUSED_ENTRY(212),
 755         I40E_PTT_UNUSED_ENTRY(213),
 756         I40E_PTT_UNUSED_ENTRY(214),
 757         I40E_PTT_UNUSED_ENTRY(215),
 758         I40E_PTT_UNUSED_ENTRY(216),
 759         I40E_PTT_UNUSED_ENTRY(217),
 760         I40E_PTT_UNUSED_ENTRY(218),
 761         I40E_PTT_UNUSED_ENTRY(219),
 762
 763         I40E_PTT_UNUSED_ENTRY(220),
 764         I40E_PTT_UNUSED_ENTRY(221),
 765         I40E_PTT_UNUSED_ENTRY(222),
 766         I40E_PTT_UNUSED_ENTRY(223),
 767         I40E_PTT_UNUSED_ENTRY(224),
 768         I40E_PTT_UNUSED_ENTRY(225),
 769         I40E_PTT_UNUSED_ENTRY(226),
 770         I40E_PTT_UNUSED_ENTRY(227),
 771         I40E_PTT_UNUSED_ENTRY(228),
 772         I40E_PTT_UNUSED_ENTRY(229),
 773
 774         I40E_PTT_UNUSED_ENTRY(230),
 775         I40E_PTT_UNUSED_ENTRY(231),
 776         I40E_PTT_UNUSED_ENTRY(232),
 777         I40E_PTT_UNUSED_ENTRY(233),
 778         I40E_PTT_UNUSED_ENTRY(234),
 779         I40E_PTT_UNUSED_ENTRY(235),
 780         I40E_PTT_UNUSED_ENTRY(236),
 781         I40E_PTT_UNUSED_ENTRY(237),
 782         I40E_PTT_UNUSED_ENTRY(238),
 783         I40E_PTT_UNUSED_ENTRY(239),
 784
 785         I40E_PTT_UNUSED_ENTRY(240),
 786         I40E_PTT_UNUSED_ENTRY(241),
 787         I40E_PTT_UNUSED_ENTRY(242),
 788         I40E_PTT_UNUSED_ENTRY(243),
 789         I40E_PTT_UNUSED_ENTRY(244),
 790         I40E_PTT_UNUSED_ENTRY(245),
 791         I40E_PTT_UNUSED_ENTRY(246),
 792         I40E_PTT_UNUSED_ENTRY(247),
 793         I40E_PTT_UNUSED_ENTRY(248),
 794         I40E_PTT_UNUSED_ENTRY(249),
 795
 796         I40E_PTT_UNUSED_ENTRY(250),
 797         I40E_PTT_UNUSED_ENTRY(251),
 798         I40E_PTT_UNUSED_ENTRY(252),
 799         I40E_PTT_UNUSED_ENTRY(253),
 800         I40E_PTT_UNUSED_ENTRY(254),
 801         I40E_PTT_UNUSED_ENTRY(255)
 802 };
 803
 804
 805 /**
 806  * i40e_validate_mac_addr - Validate unicast MAC address
 807  * @mac_addr: pointer to MAC address
 808  *
 809  * Tests a MAC address to ensure it is a valid Individual Address
 810  **/
 811 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
 812 {
 813         enum i40e_status_code status = I40E_SUCCESS;
 814
 815         DEBUGFUNC("i40e_validate_mac_addr");
 816
 817         /* Broadcast addresses ARE multicast addresses
 818          * Make sure it is not a multicast address
 819          * Reject the zero address
 820          */
 821         if (I40E_IS_MULTICAST(mac_addr) ||
 822             (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
 823               mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
 824                 status = I40E_ERR_INVALID_MAC_ADDR;
 825
 826         return status;
 827 }
 828 #ifdef PF_DRIVER
 829
 830 /**
 831  * i40e_init_shared_code - Initialize the shared code
 832  * @hw: pointer to hardware structure
 833  *
 834  * This assigns the MAC type and PHY code and inits the NVM.
 835  * Does not touch the hardware. This function must be called prior to any
 836  * other function in the shared code. The i40e_hw structure should be
 837  * memset to 0 prior to calling this function.  The following fields in
 838  * hw structure should be filled in prior to calling this function:
 839  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
 840  * subsystem_vendor_id, and revision_id
 841  **/
 842 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
 843 {
 844         enum i40e_status_code status = I40E_SUCCESS;
 845         u32 port, ari, func_rid;
 846
 847         DEBUGFUNC("i40e_init_shared_code");
 848
 849         i40e_set_mac_type(hw);
 850
 851         switch (hw->mac.type) {
 852         case I40E_MAC_XL710:
 853 #ifdef X722_SUPPORT
 854         case I40E_MAC_X722:
 855 #endif
 856                 break;
 857         default:
 858                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
 859         }
 860
 861         hw->phy.get_link_info = true;
 862
 863         /* Determine port number and PF number*/
 864         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
 865                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
 866         hw->port = (u8)port;
 867         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
 868                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
 869         func_rid = rd32(hw, I40E_PF_FUNC_RID);
 870         if (ari)
 871                 hw->pf_id = (u8)(func_rid & 0xff);
 872         else
 873                 hw->pf_id = (u8)(func_rid & 0x7);
 874
 875         status = i40e_init_nvm(hw);
 876         return status;
 877 }
 878
 879 /**
 880  * i40e_aq_mac_address_read - Retrieve the MAC addresses
 881  * @hw: pointer to the hw struct
 882  * @flags: a return indicator of what addresses were added to the addr store
 883  * @addrs: the requestor's mac addr store
 884  * @cmd_details: pointer to command details structure or NULL
 885  **/
 886 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
 887                                    u16 *flags,
 888                                    struct i40e_aqc_mac_address_read_data *addrs,
 889                                    struct i40e_asq_cmd_details *cmd_details)
 890 {
 891         struct i40e_aq_desc desc;
 892         struct i40e_aqc_mac_address_read *cmd_data =
 893                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
 894         enum i40e_status_code status;
 895
 896         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
 897         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
 898
 899         status = i40e_asq_send_command(hw, &desc, addrs,
 900                                        sizeof(*addrs), cmd_details);
 901         *flags = LE16_TO_CPU(cmd_data->command_flags);
 902
 903         return status;
 904 }
 905
 906 /**
 907  * i40e_aq_mac_address_write - Change the MAC addresses
 908  * @hw: pointer to the hw struct
 909  * @flags: indicates which MAC to be written
 910  * @mac_addr: address to write
 911  * @cmd_details: pointer to command details structure or NULL
 912  **/
 913 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
 914                                     u16 flags, u8 *mac_addr,
 915                                     struct i40e_asq_cmd_details *cmd_details)
 916 {
 917         struct i40e_aq_desc desc;
 918         struct i40e_aqc_mac_address_write *cmd_data =
 919                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
 920         enum i40e_status_code status;
 921
 922         i40e_fill_default_direct_cmd_desc(&desc,
 923                                           i40e_aqc_opc_mac_address_write);
 924         cmd_data->command_flags = CPU_TO_LE16(flags);
 925         cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
 926         cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
 927                                         ((u32)mac_addr[3] << 16) |
 928                                         ((u32)mac_addr[4] << 8) |
 929                                         mac_addr[5]);
 930
 931         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
 932
 933         return status;
 934 }
 935
 936 /**
 937  * i40e_get_mac_addr - get MAC address
 938  * @hw: pointer to the HW structure
 939  * @mac_addr: pointer to MAC address
 940  *
 941  * Reads the adapter's MAC address from register
 942  **/
 943 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
 944 {
 945         struct i40e_aqc_mac_address_read_data addrs;
 946         enum i40e_status_code status;
 947         u16 flags = 0;
 948
 949         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
 950
 951         if (flags & I40E_AQC_LAN_ADDR_VALID)
 952                 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
 953
 954         return status;
 955 }
 956
 957 /**
 958  * i40e_get_port_mac_addr - get Port MAC address
 959  * @hw: pointer to the HW structure
 960  * @mac_addr: pointer to Port MAC address
 961  *
 962  * Reads the adapter's Port MAC address
 963  **/
 964 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
 965 {
 966         struct i40e_aqc_mac_address_read_data addrs;
 967         enum i40e_status_code status;
 968         u16 flags = 0;
 969
 970         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
 971         if (status)
 972                 return status;
 973
 974         if (flags & I40E_AQC_PORT_ADDR_VALID)
 975                 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
 976         else
 977                 status = I40E_ERR_INVALID_MAC_ADDR;
 978
 979         return status;
 980 }
 981
 982 /**
 983  * i40e_pre_tx_queue_cfg - pre tx queue configure
 984  * @hw: pointer to the HW structure
 985  * @queue: target pf queue index
 986  * @enable: state change request
 987  *
 988  * Handles hw requirement to indicate intention to enable
 989  * or disable target queue.
 990  **/
 991 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
 992 {
 993         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
 994         u32 reg_block = 0;
 995         u32 reg_val;
 996
 997         if (abs_queue_idx >= 128) {
 998                 reg_block = abs_queue_idx / 128;
 999                 abs_queue_idx %= 128;
1000         }
1001
1002         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1003         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1004         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1005
1006         if (enable)
1007                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1008         else
1009                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1010
1011         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1012 }
1013
1014 /**
1015  *  i40e_read_pba_string - Reads part number string from EEPROM
1016  *  @hw: pointer to hardware structure
1017  *  @pba_num: stores the part number string from the EEPROM
1018  *  @pba_num_size: part number string buffer length
1019  *
1020  *  Reads the part number string from the EEPROM.
1021  **/
1022 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1023                                             u32 pba_num_size)
1024 {
1025         enum i40e_status_code status = I40E_SUCCESS;
1026         u16 pba_word = 0;
1027         u16 pba_size = 0;
1028         u16 pba_ptr = 0;
1029         u16 i = 0;
1030
1031         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1032         if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1033                 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1034                 return status;
1035         }
1036
1037         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1038         if (status != I40E_SUCCESS) {
1039                 DEBUGOUT("Failed to read PBA Block pointer.\n");
1040                 return status;
1041         }
1042
1043         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1044         if (status != I40E_SUCCESS) {
1045                 DEBUGOUT("Failed to read PBA Block size.\n");
1046                 return status;
1047         }
1048
1049         /* Subtract one to get PBA word count (PBA Size word is included in
1050          * total size)
1051          */
1052         pba_size--;
1053         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1054                 DEBUGOUT("Buffer to small for PBA data.\n");
1055                 return I40E_ERR_PARAM;
1056         }
1057
1058         for (i = 0; i < pba_size; i++) {
1059                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1060                 if (status != I40E_SUCCESS) {
1061                         DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1062                         return status;
1063                 }
1064
1065                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1066                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1067         }
1068         pba_num[(pba_size * 2)] = '\0';
1069
1070         return status;
1071 }
1072
1073 /**
1074  * i40e_get_media_type - Gets media type
1075  * @hw: pointer to the hardware structure
1076  **/
1077 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1078 {
1079         enum i40e_media_type media;
1080
1081         switch (hw->phy.link_info.phy_type) {
1082         case I40E_PHY_TYPE_10GBASE_SR:
1083         case I40E_PHY_TYPE_10GBASE_LR:
1084         case I40E_PHY_TYPE_1000BASE_SX:
1085         case I40E_PHY_TYPE_1000BASE_LX:
1086         case I40E_PHY_TYPE_40GBASE_SR4:
1087         case I40E_PHY_TYPE_40GBASE_LR4:
1088                 media = I40E_MEDIA_TYPE_FIBER;
1089                 break;
1090         case I40E_PHY_TYPE_100BASE_TX:
1091         case I40E_PHY_TYPE_1000BASE_T:
1092         case I40E_PHY_TYPE_10GBASE_T:
1093                 media = I40E_MEDIA_TYPE_BASET;
1094                 break;
1095         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1096         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1097         case I40E_PHY_TYPE_10GBASE_CR1:
1098         case I40E_PHY_TYPE_40GBASE_CR4:
1099         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1100         case I40E_PHY_TYPE_40GBASE_AOC:
1101         case I40E_PHY_TYPE_10GBASE_AOC:
1102                 media = I40E_MEDIA_TYPE_DA;
1103                 break;
1104         case I40E_PHY_TYPE_1000BASE_KX:
1105         case I40E_PHY_TYPE_10GBASE_KX4:
1106         case I40E_PHY_TYPE_10GBASE_KR:
1107         case I40E_PHY_TYPE_40GBASE_KR4:
1108         case I40E_PHY_TYPE_20GBASE_KR2:
1109                 media = I40E_MEDIA_TYPE_BACKPLANE;
1110                 break;
1111         case I40E_PHY_TYPE_SGMII:
1112         case I40E_PHY_TYPE_XAUI:
1113         case I40E_PHY_TYPE_XFI:
1114         case I40E_PHY_TYPE_XLAUI:
1115         case I40E_PHY_TYPE_XLPPI:
1116         default:
1117                 media = I40E_MEDIA_TYPE_UNKNOWN;
1118                 break;
1119         }
1120
1121         return media;
1122 }
1123
1124 #define I40E_PF_RESET_WAIT_COUNT        200
1125 /**
1126  * i40e_pf_reset - Reset the PF
1127  * @hw: pointer to the hardware structure
1128  *
1129  * Assuming someone else has triggered a global reset,
1130  * assure the global reset is complete and then reset the PF
1131  **/
1132 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1133 {
1134         u32 cnt = 0;
1135         u32 cnt1 = 0;
1136         u32 reg = 0;
1137         u32 grst_del;
1138
1139         /* Poll for Global Reset steady state in case of recent GRST.
1140          * The grst delay value is in 100ms units, and we'll wait a
1141          * couple counts longer to be sure we don't just miss the end.
1142          */
1143         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1144                         I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1145                         I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1146 #ifdef I40E_ESS_SUPPORT
1147         /* It can take upto 15 secs for GRST steady state */
1148         grst_del = grst_del * 20; /* bump it to 16 secs max to be safe */
1149 #endif
1150         for (cnt = 0; cnt < grst_del + 10; cnt++) {
1151                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1152                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1153                         break;
1154                 i40e_msec_delay(100);
1155         }
1156         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1157                 DEBUGOUT("Global reset polling failed to complete.\n");
1158                 return I40E_ERR_RESET_FAILED;
1159         }
1160
1161         /* Now Wait for the FW to be ready */
1162         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1163                 reg = rd32(hw, I40E_GLNVM_ULD);
1164                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1165                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1166                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1167                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1168                         DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1169                         break;
1170                 }
1171                 i40e_msec_delay(10);
1172         }
1173         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1174                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1175                 DEBUGOUT("wait for FW Reset complete timedout\n");
1176                 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1177                 return I40E_ERR_RESET_FAILED;
1178         }
1179
1180         /* If there was a Global Reset in progress when we got here,
1181          * we don't need to do the PF Reset
1182          */
1183         if (!cnt) {
1184                 reg = rd32(hw, I40E_PFGEN_CTRL);
1185                 wr32(hw, I40E_PFGEN_CTRL,
1186                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1187                 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1188                         reg = rd32(hw, I40E_PFGEN_CTRL);
1189                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1190                                 break;
1191                         i40e_msec_delay(1);
1192                 }
1193                 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1194                         DEBUGOUT("PF reset polling failed to complete.\n");
1195                         return I40E_ERR_RESET_FAILED;
1196                 }
1197         }
1198
1199         i40e_clear_pxe_mode(hw);
1200
1201
1202         return I40E_SUCCESS;
1203 }
1204
1205 /**
1206  * i40e_clear_hw - clear out any left over hw state
1207  * @hw: pointer to the hw struct
1208  *
1209  * Clear queues and interrupts, typically called at init time,
1210  * but after the capabilities have been found so we know how many
1211  * queues and msix vectors have been allocated.
1212  **/
1213 void i40e_clear_hw(struct i40e_hw *hw)
1214 {
1215         u32 num_queues, base_queue;
1216         u32 num_pf_int;
1217         u32 num_vf_int;
1218         u32 num_vfs;
1219         u32 i, j;
1220         u32 val;
1221         u32 eol = 0x7ff;
1222
1223         /* get number of interrupts, queues, and vfs */
1224         val = rd32(hw, I40E_GLPCI_CNF2);
1225         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1226                         I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1227         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1228                         I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1229
1230         val = rd32(hw, I40E_PFLAN_QALLOC);
1231         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1232                         I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1233         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1234                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1235         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1236                 num_queues = (j - base_queue) + 1;
1237         else
1238                 num_queues = 0;
1239
1240         val = rd32(hw, I40E_PF_VT_PFALLOC);
1241         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1242                         I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1243         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1244                         I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1245         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1246                 num_vfs = (j - i) + 1;
1247         else
1248                 num_vfs = 0;
1249
1250         /* stop all the interrupts */
1251         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1252         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1253         for (i = 0; i < num_pf_int - 2; i++)
1254                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1255
1256         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1257         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1258         wr32(hw, I40E_PFINT_LNKLST0, val);
1259         for (i = 0; i < num_pf_int - 2; i++)
1260                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1261         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1262         for (i = 0; i < num_vfs; i++)
1263                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1264         for (i = 0; i < num_vf_int - 2; i++)
1265                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1266
1267         /* warn the HW of the coming Tx disables */
1268         for (i = 0; i < num_queues; i++) {
1269                 u32 abs_queue_idx = base_queue + i;
1270                 u32 reg_block = 0;
1271
1272                 if (abs_queue_idx >= 128) {
1273                         reg_block = abs_queue_idx / 128;
1274                         abs_queue_idx %= 128;
1275                 }
1276
1277                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1278                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1279                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1280                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1281
1282                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1283         }
1284         i40e_usec_delay(400);
1285
1286         /* stop all the queues */
1287         for (i = 0; i < num_queues; i++) {
1288                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1289                 wr32(hw, I40E_QTX_ENA(i), 0);
1290                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1291                 wr32(hw, I40E_QRX_ENA(i), 0);
1292         }
1293
1294         /* short wait for all queue disables to settle */
1295         i40e_usec_delay(50);
1296 }
1297
1298 /**
1299  * i40e_clear_pxe_mode - clear pxe operations mode
1300  * @hw: pointer to the hw struct
1301  *
1302  * Make sure all PXE mode settings are cleared, including things
1303  * like descriptor fetch/write-back mode.
1304  **/
1305 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1306 {
1307         if (i40e_check_asq_alive(hw))
1308                 i40e_aq_clear_pxe_mode(hw, NULL);
1309 }
1310
1311 /**
1312  * i40e_led_is_mine - helper to find matching led
1313  * @hw: pointer to the hw struct
1314  * @idx: index into GPIO registers
1315  *
1316  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1317  */
1318 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1319 {
1320         u32 gpio_val = 0;
1321         u32 port;
1322
1323         if (!hw->func_caps.led[idx])
1324                 return 0;
1325
1326         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1327         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1328                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1329
1330         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1331          * if it is not our port then ignore
1332          */
1333         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1334             (port != hw->port))
1335                 return 0;
1336
1337         return gpio_val;
1338 }
1339
1340 #define I40E_COMBINED_ACTIVITY 0xA
1341 #define I40E_FILTER_ACTIVITY 0xE
1342 #define I40E_LINK_ACTIVITY 0xC
1343 #define I40E_MAC_ACTIVITY 0xD
1344 #define I40E_LED0 22
1345
1346 /**
1347  * i40e_led_get - return current on/off mode
1348  * @hw: pointer to the hw struct
1349  *
1350  * The value returned is the 'mode' field as defined in the
1351  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1352  * values are variations of possible behaviors relating to
1353  * blink, link, and wire.
1354  **/
1355 u32 i40e_led_get(struct i40e_hw *hw)
1356 {
1357         u32 current_mode = 0;
1358         u32 mode = 0;
1359         int i;
1360
1361         /* as per the documentation GPIO 22-29 are the LED
1362          * GPIO pins named LED0..LED7
1363          */
1364         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1365                 u32 gpio_val = i40e_led_is_mine(hw, i);
1366
1367                 if (!gpio_val)
1368                         continue;
1369
1370                 /* ignore gpio LED src mode entries related to the activity LEDs */
1371                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1372                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1373                 switch (current_mode) {
1374                 case I40E_COMBINED_ACTIVITY:
1375                 case I40E_FILTER_ACTIVITY:
1376                 case I40E_MAC_ACTIVITY:
1377                         continue;
1378                 default:
1379                         break;
1380                 }
1381
1382                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1383                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1384                 break;
1385         }
1386
1387         return mode;
1388 }
1389
1390 /**
1391  * i40e_led_set - set new on/off mode
1392  * @hw: pointer to the hw struct
1393  * @mode: 0=off, 0xf=on (else see manual for mode details)
1394  * @blink: true if the LED should blink when on, false if steady
1395  *
1396  * if this function is used to turn on the blink it should
1397  * be used to disable the blink when restoring the original state.
1398  **/
1399 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1400 {
1401         u32 current_mode = 0;
1402         int i;
1403
1404         if (mode & 0xfffffff0)
1405                 DEBUGOUT1("invalid mode passed in %X\n", mode);
1406
1407         /* as per the documentation GPIO 22-29 are the LED
1408          * GPIO pins named LED0..LED7
1409          */
1410         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1411                 u32 gpio_val = i40e_led_is_mine(hw, i);
1412
1413                 if (!gpio_val)
1414                         continue;
1415
1416                 /* ignore gpio LED src mode entries related to the activity LEDs */
1417                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1418                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1419                 switch (current_mode) {
1420                 case I40E_COMBINED_ACTIVITY:
1421                 case I40E_FILTER_ACTIVITY:
1422                 case I40E_MAC_ACTIVITY:
1423                         continue;
1424                 default:
1425                         break;
1426                 }
1427
1428                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1429                 /* this & is a bit of paranoia, but serves as a range check */
1430                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1431                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1432
1433                 if (mode == I40E_LINK_ACTIVITY)
1434                         blink = false;
1435
1436                 if (blink)
1437                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1438                 else
1439                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1440
1441                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1442                 break;
1443         }
1444 }
1445
1446 /* Admin command wrappers */
1447
1448 /**
1449  * i40e_aq_get_phy_capabilities
1450  * @hw: pointer to the hw struct
1451  * @abilities: structure for PHY capabilities to be filled
1452  * @qualified_modules: report Qualified Modules
1453  * @report_init: report init capabilities (active are default)
1454  * @cmd_details: pointer to command details structure or NULL
1455  *
1456  * Returns the various PHY abilities supported on the Port.
1457  **/
1458 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1459                         bool qualified_modules, bool report_init,
1460                         struct i40e_aq_get_phy_abilities_resp *abilities,
1461                         struct i40e_asq_cmd_details *cmd_details)
1462 {
1463         struct i40e_aq_desc desc;
1464         enum i40e_status_code status;
1465         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1466
1467         if (!abilities)
1468                 return I40E_ERR_PARAM;
1469
1470         i40e_fill_default_direct_cmd_desc(&desc,
1471                                           i40e_aqc_opc_get_phy_abilities);
1472
1473         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1474         if (abilities_size > I40E_AQ_LARGE_BUF)
1475                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1476
1477         if (qualified_modules)
1478                 desc.params.external.param0 |=
1479                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1480
1481         if (report_init)
1482                 desc.params.external.param0 |=
1483                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1484
1485         status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1486                                     cmd_details);
1487
1488         if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1489                 status = I40E_ERR_UNKNOWN_PHY;
1490
1491         if (report_init)
1492                 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1493
1494         return status;
1495 }
1496
1497 /**
1498  * i40e_aq_set_phy_config
1499  * @hw: pointer to the hw struct
1500  * @config: structure with PHY configuration to be set
1501  * @cmd_details: pointer to command details structure or NULL
1502  *
1503  * Set the various PHY configuration parameters
1504  * supported on the Port.One or more of the Set PHY config parameters may be
1505  * ignored in an MFP mode as the PF may not have the privilege to set some
1506  * of the PHY Config parameters. This status will be indicated by the
1507  * command response.
1508  **/
1509 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1510                                 struct i40e_aq_set_phy_config *config,
1511                                 struct i40e_asq_cmd_details *cmd_details)
1512 {
1513         struct i40e_aq_desc desc;
1514         struct i40e_aq_set_phy_config *cmd =
1515                 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1516         enum i40e_status_code status;
1517
1518         if (!config)
1519                 return I40E_ERR_PARAM;
1520
1521         i40e_fill_default_direct_cmd_desc(&desc,
1522                                           i40e_aqc_opc_set_phy_config);
1523
1524         *cmd = *config;
1525
1526         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1527
1528         return status;
1529 }
1530
1531 /**
1532  * i40e_set_fc
1533  * @hw: pointer to the hw struct
1534  *
1535  * Set the requested flow control mode using set_phy_config.
1536  **/
1537 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1538                                   bool atomic_restart)
1539 {
1540         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1541         struct i40e_aq_get_phy_abilities_resp abilities;
1542         struct i40e_aq_set_phy_config config;
1543         enum i40e_status_code status;
1544         u8 pause_mask = 0x0;
1545
1546         *aq_failures = 0x0;
1547
1548         switch (fc_mode) {
1549         case I40E_FC_FULL:
1550                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1551                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1552                 break;
1553         case I40E_FC_RX_PAUSE:
1554                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1555                 break;
1556         case I40E_FC_TX_PAUSE:
1557                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1558                 break;
1559         default:
1560                 break;
1561         }
1562
1563         /* Get the current phy config */
1564         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1565                                               NULL);
1566         if (status) {
1567                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1568                 return status;
1569         }
1570
1571         memset(&config, 0, sizeof(config));
1572         /* clear the old pause settings */
1573         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1574                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1575         /* set the new abilities */
1576         config.abilities |= pause_mask;
1577         /* If the abilities have changed, then set the new config */
1578         if (config.abilities != abilities.abilities) {
1579                 /* Auto restart link so settings take effect */
1580                 if (atomic_restart)
1581                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1582                 /* Copy over all the old settings */
1583                 config.phy_type = abilities.phy_type;
1584                 config.link_speed = abilities.link_speed;
1585                 config.eee_capability = abilities.eee_capability;
1586                 config.eeer = abilities.eeer_val;
1587                 config.low_power_ctrl = abilities.d3_lpan;
1588                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1589
1590                 if (status)
1591                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1592         }
1593         /* Update the link info */
1594         status = i40e_update_link_info(hw);
1595         if (status) {
1596                 /* Wait a little bit (on 40G cards it sometimes takes a really
1597                  * long time for link to come back from the atomic reset)
1598                  * and try once more
1599                  */
1600                 i40e_msec_delay(1000);
1601                 status = i40e_update_link_info(hw);
1602         }
1603         if (status)
1604                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1605
1606         return status;
1607 }
1608
1609 /**
1610  * i40e_aq_set_mac_config
1611  * @hw: pointer to the hw struct
1612  * @max_frame_size: Maximum Frame Size to be supported by the port
1613  * @crc_en: Tell HW to append a CRC to outgoing frames
1614  * @pacing: Pacing configurations
1615  * @cmd_details: pointer to command details structure or NULL
1616  *
1617  * Configure MAC settings for frame size, jumbo frame support and the
1618  * addition of a CRC by the hardware.
1619  **/
1620 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1621                                 u16 max_frame_size,
1622                                 bool crc_en, u16 pacing,
1623                                 struct i40e_asq_cmd_details *cmd_details)
1624 {
1625         struct i40e_aq_desc desc;
1626         struct i40e_aq_set_mac_config *cmd =
1627                 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1628         enum i40e_status_code status;
1629
1630         if (max_frame_size == 0)
1631                 return I40E_ERR_PARAM;
1632
1633         i40e_fill_default_direct_cmd_desc(&desc,
1634                                           i40e_aqc_opc_set_mac_config);
1635
1636         cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1637         cmd->params = ((u8)pacing & 0x0F) << 3;
1638         if (crc_en)
1639                 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1640
1641         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1642
1643         return status;
1644 }
1645
1646 /**
1647  * i40e_aq_clear_pxe_mode
1648  * @hw: pointer to the hw struct
1649  * @cmd_details: pointer to command details structure or NULL
1650  *
1651  * Tell the firmware that the driver is taking over from PXE
1652  **/
1653 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1654                         struct i40e_asq_cmd_details *cmd_details)
1655 {
1656         enum i40e_status_code status;
1657         struct i40e_aq_desc desc;
1658         struct i40e_aqc_clear_pxe *cmd =
1659                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1660
1661         i40e_fill_default_direct_cmd_desc(&desc,
1662                                           i40e_aqc_opc_clear_pxe_mode);
1663
1664         cmd->rx_cnt = 0x2;
1665
1666         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1667
1668         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1669
1670         return status;
1671 }
1672
1673 /**
1674  * i40e_aq_set_link_restart_an
1675  * @hw: pointer to the hw struct
1676  * @enable_link: if true: enable link, if false: disable link
1677  * @cmd_details: pointer to command details structure or NULL
1678  *
1679  * Sets up the link and restarts the Auto-Negotiation over the link.
1680  **/
1681 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1682                 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1683 {
1684         struct i40e_aq_desc desc;
1685         struct i40e_aqc_set_link_restart_an *cmd =
1686                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1687         enum i40e_status_code status;
1688
1689         i40e_fill_default_direct_cmd_desc(&desc,
1690                                           i40e_aqc_opc_set_link_restart_an);
1691
1692         cmd->command = I40E_AQ_PHY_RESTART_AN;
1693         if (enable_link)
1694                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1695         else
1696                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1697
1698         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1699
1700         return status;
1701 }
1702
1703 /**
1704  * i40e_aq_get_link_info
1705  * @hw: pointer to the hw struct
1706  * @enable_lse: enable/disable LinkStatusEvent reporting
1707  * @link: pointer to link status structure - optional
1708  * @cmd_details: pointer to command details structure or NULL
1709  *
1710  * Returns the link status of the adapter.
1711  **/
1712 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1713                                 bool enable_lse, struct i40e_link_status *link,
1714                                 struct i40e_asq_cmd_details *cmd_details)
1715 {
1716         struct i40e_aq_desc desc;
1717         struct i40e_aqc_get_link_status *resp =
1718                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1719         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1720         enum i40e_status_code status;
1721         bool tx_pause, rx_pause;
1722         u16 command_flags;
1723
1724         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1725
1726         if (enable_lse)
1727                 command_flags = I40E_AQ_LSE_ENABLE;
1728         else
1729                 command_flags = I40E_AQ_LSE_DISABLE;
1730         resp->command_flags = CPU_TO_LE16(command_flags);
1731
1732         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1733
1734         if (status != I40E_SUCCESS)
1735                 goto aq_get_link_info_exit;
1736
1737         /* save off old link status information */
1738         i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1739                     sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1740
1741         /* update link status */
1742         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1743         hw->phy.media_type = i40e_get_media_type(hw);
1744         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1745         hw_link_info->link_info = resp->link_info;
1746         hw_link_info->an_info = resp->an_info;
1747         hw_link_info->ext_info = resp->ext_info;
1748         hw_link_info->loopback = resp->loopback;
1749         hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1750         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1751
1752         /* update fc info */
1753         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1754         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1755         if (tx_pause & rx_pause)
1756                 hw->fc.current_mode = I40E_FC_FULL;
1757         else if (tx_pause)
1758                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1759         else if (rx_pause)
1760                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1761         else
1762                 hw->fc.current_mode = I40E_FC_NONE;
1763
1764         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1765                 hw_link_info->crc_enable = true;
1766         else
1767                 hw_link_info->crc_enable = false;
1768
1769         if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1770                 hw_link_info->lse_enable = true;
1771         else
1772                 hw_link_info->lse_enable = false;
1773
1774         if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1775              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1776                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1777
1778         /* save link status information */
1779         if (link)
1780                 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1781                             I40E_NONDMA_TO_NONDMA);
1782
1783         /* flag cleared so helper functions don't call AQ again */
1784         hw->phy.get_link_info = false;
1785
1786 aq_get_link_info_exit:
1787         return status;
1788 }
1789
1790 /**
1791  * i40e_aq_set_phy_int_mask
1792  * @hw: pointer to the hw struct
1793  * @mask: interrupt mask to be set
1794  * @cmd_details: pointer to command details structure or NULL
1795  *
1796  * Set link interrupt mask.
1797  **/
1798 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1799                                 u16 mask,
1800                                 struct i40e_asq_cmd_details *cmd_details)
1801 {
1802         struct i40e_aq_desc desc;
1803         struct i40e_aqc_set_phy_int_mask *cmd =
1804                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1805         enum i40e_status_code status;
1806
1807         i40e_fill_default_direct_cmd_desc(&desc,
1808                                           i40e_aqc_opc_set_phy_int_mask);
1809
1810         cmd->event_mask = CPU_TO_LE16(mask);
1811
1812         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1813
1814         return status;
1815 }
1816
1817 /**
1818  * i40e_aq_get_local_advt_reg
1819  * @hw: pointer to the hw struct
1820  * @advt_reg: local AN advertisement register value
1821  * @cmd_details: pointer to command details structure or NULL
1822  *
1823  * Get the Local AN advertisement register value.
1824  **/
1825 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
1826                                 u64 *advt_reg,
1827                                 struct i40e_asq_cmd_details *cmd_details)
1828 {
1829         struct i40e_aq_desc desc;
1830         struct i40e_aqc_an_advt_reg *resp =
1831                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1832         enum i40e_status_code status;
1833
1834         i40e_fill_default_direct_cmd_desc(&desc,
1835                                           i40e_aqc_opc_get_local_advt_reg);
1836
1837         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1838
1839         if (status != I40E_SUCCESS)
1840                 goto aq_get_local_advt_reg_exit;
1841
1842         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1843         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1844
1845 aq_get_local_advt_reg_exit:
1846         return status;
1847 }
1848
1849 /**
1850  * i40e_aq_set_local_advt_reg
1851  * @hw: pointer to the hw struct
1852  * @advt_reg: local AN advertisement register value
1853  * @cmd_details: pointer to command details structure or NULL
1854  *
1855  * Get the Local AN advertisement register value.
1856  **/
1857 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
1858                                 u64 advt_reg,
1859                                 struct i40e_asq_cmd_details *cmd_details)
1860 {
1861         struct i40e_aq_desc desc;
1862         struct i40e_aqc_an_advt_reg *cmd =
1863                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1864         enum i40e_status_code status;
1865
1866         i40e_fill_default_direct_cmd_desc(&desc,
1867                                           i40e_aqc_opc_get_local_advt_reg);
1868
1869         cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
1870         cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
1871
1872         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1873
1874         return status;
1875 }
1876
1877 /**
1878  * i40e_aq_get_partner_advt
1879  * @hw: pointer to the hw struct
1880  * @advt_reg: AN partner advertisement register value
1881  * @cmd_details: pointer to command details structure or NULL
1882  *
1883  * Get the link partner AN advertisement register value.
1884  **/
1885 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
1886                                 u64 *advt_reg,
1887                                 struct i40e_asq_cmd_details *cmd_details)
1888 {
1889         struct i40e_aq_desc desc;
1890         struct i40e_aqc_an_advt_reg *resp =
1891                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1892         enum i40e_status_code status;
1893
1894         i40e_fill_default_direct_cmd_desc(&desc,
1895                                           i40e_aqc_opc_get_partner_advt);
1896
1897         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1898
1899         if (status != I40E_SUCCESS)
1900                 goto aq_get_partner_advt_exit;
1901
1902         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1903         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1904
1905 aq_get_partner_advt_exit:
1906         return status;
1907 }
1908
1909 /**
1910  * i40e_aq_set_lb_modes
1911  * @hw: pointer to the hw struct
1912  * @lb_modes: loopback mode to be set
1913  * @cmd_details: pointer to command details structure or NULL
1914  *
1915  * Sets loopback modes.
1916  **/
1917 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
1918                                 u16 lb_modes,
1919                                 struct i40e_asq_cmd_details *cmd_details)
1920 {
1921         struct i40e_aq_desc desc;
1922         struct i40e_aqc_set_lb_mode *cmd =
1923                 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
1924         enum i40e_status_code status;
1925
1926         i40e_fill_default_direct_cmd_desc(&desc,
1927                                           i40e_aqc_opc_set_lb_modes);
1928
1929         cmd->lb_mode = CPU_TO_LE16(lb_modes);
1930
1931         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1932
1933         return status;
1934 }
1935
1936 /**
1937  * i40e_aq_set_phy_debug
1938  * @hw: pointer to the hw struct
1939  * @cmd_flags: debug command flags
1940  * @cmd_details: pointer to command details structure or NULL
1941  *
1942  * Reset the external PHY.
1943  **/
1944 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1945                                 struct i40e_asq_cmd_details *cmd_details)
1946 {
1947         struct i40e_aq_desc desc;
1948         struct i40e_aqc_set_phy_debug *cmd =
1949                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1950         enum i40e_status_code status;
1951
1952         i40e_fill_default_direct_cmd_desc(&desc,
1953                                           i40e_aqc_opc_set_phy_debug);
1954
1955         cmd->command_flags = cmd_flags;
1956
1957         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1958
1959         return status;
1960 }
1961
1962 /**
1963  * i40e_aq_add_vsi
1964  * @hw: pointer to the hw struct
1965  * @vsi_ctx: pointer to a vsi context struct
1966  * @cmd_details: pointer to command details structure or NULL
1967  *
1968  * Add a VSI context to the hardware.
1969 **/
1970 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
1971                                 struct i40e_vsi_context *vsi_ctx,
1972                                 struct i40e_asq_cmd_details *cmd_details)
1973 {
1974         struct i40e_aq_desc desc;
1975         struct i40e_aqc_add_get_update_vsi *cmd =
1976                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1977         struct i40e_aqc_add_get_update_vsi_completion *resp =
1978                 (struct i40e_aqc_add_get_update_vsi_completion *)
1979                 &desc.params.raw;
1980         enum i40e_status_code status;
1981
1982         i40e_fill_default_direct_cmd_desc(&desc,
1983                                           i40e_aqc_opc_add_vsi);
1984
1985         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
1986         cmd->connection_type = vsi_ctx->connection_type;
1987         cmd->vf_id = vsi_ctx->vf_num;
1988         cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
1989
1990         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1991
1992         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1993                                     sizeof(vsi_ctx->info), cmd_details);
1994
1995         if (status != I40E_SUCCESS)
1996                 goto aq_add_vsi_exit;
1997
1998         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
1999         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2000         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2001         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2002
2003 aq_add_vsi_exit:
2004         return status;
2005 }
2006
2007 /**
2008  * i40e_aq_set_default_vsi
2009  * @hw: pointer to the hw struct
2010  * @seid: vsi number
2011  * @cmd_details: pointer to command details structure or NULL
2012  **/
2013 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2014                                 u16 seid,
2015                                 struct i40e_asq_cmd_details *cmd_details)
2016 {
2017         struct i40e_aq_desc desc;
2018         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2019                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2020                 &desc.params.raw;
2021         enum i40e_status_code status;
2022
2023         i40e_fill_default_direct_cmd_desc(&desc,
2024                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2025
2026         cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2027         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2028         cmd->seid = CPU_TO_LE16(seid);
2029
2030         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2031
2032         return status;
2033 }
2034
2035 /**
2036  * i40e_aq_set_vsi_unicast_promiscuous
2037  * @hw: pointer to the hw struct
2038  * @seid: vsi number
2039  * @set: set unicast promiscuous enable/disable
2040  * @cmd_details: pointer to command details structure or NULL
2041  **/
2042 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2043                                 u16 seid, bool set,
2044                                 struct i40e_asq_cmd_details *cmd_details)
2045 {
2046         struct i40e_aq_desc desc;
2047         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2048                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2049         enum i40e_status_code status;
2050         u16 flags = 0;
2051
2052         i40e_fill_default_direct_cmd_desc(&desc,
2053                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2054
2055         if (set)
2056                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2057
2058         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2059
2060         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2061
2062         cmd->seid = CPU_TO_LE16(seid);
2063         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2064
2065         return status;
2066 }
2067
2068 /**
2069  * i40e_aq_set_vsi_multicast_promiscuous
2070  * @hw: pointer to the hw struct
2071  * @seid: vsi number
2072  * @set: set multicast promiscuous enable/disable
2073  * @cmd_details: pointer to command details structure or NULL
2074  **/
2075 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2076                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2077 {
2078         struct i40e_aq_desc desc;
2079         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2080                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2081         enum i40e_status_code status;
2082         u16 flags = 0;
2083
2084         i40e_fill_default_direct_cmd_desc(&desc,
2085                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2086
2087         if (set)
2088                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2089
2090         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2091
2092         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2093
2094         cmd->seid = CPU_TO_LE16(seid);
2095         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2096
2097         return status;
2098 }
2099
2100 /**
2101  * i40e_aq_set_vsi_mc_promisc_on_vlan
2102  * @hw: pointer to the hw struct
2103  * @seid: vsi number
2104  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2105  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2106  * @cmd_details: pointer to command details structure or NULL
2107  **/
2108 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2109                                 u16 seid, bool enable, u16 vid,
2110                                 struct i40e_asq_cmd_details *cmd_details)
2111 {
2112         struct i40e_aq_desc desc;
2113         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2114                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2115         enum i40e_status_code status;
2116         u16 flags = 0;
2117
2118         i40e_fill_default_direct_cmd_desc(&desc,
2119                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2120
2121         if (enable)
2122                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2123
2124         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2125         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2126         cmd->seid = CPU_TO_LE16(seid);
2127         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2128
2129         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2130
2131         return status;
2132 }
2133
2134 /**
2135  * i40e_aq_set_vsi_uc_promisc_on_vlan
2136  * @hw: pointer to the hw struct
2137  * @seid: vsi number
2138  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2139  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2140  * @cmd_details: pointer to command details structure or NULL
2141  **/
2142 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2143                                 u16 seid, bool enable, u16 vid,
2144                                 struct i40e_asq_cmd_details *cmd_details)
2145 {
2146         struct i40e_aq_desc desc;
2147         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2148                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2149         enum i40e_status_code status;
2150         u16 flags = 0;
2151
2152         i40e_fill_default_direct_cmd_desc(&desc,
2153                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2154
2155         if (enable)
2156                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2157
2158         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2159         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2160         cmd->seid = CPU_TO_LE16(seid);
2161         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2162
2163         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2164
2165         return status;
2166 }
2167
2168 /**
2169  * i40e_aq_set_vsi_broadcast
2170  * @hw: pointer to the hw struct
2171  * @seid: vsi number
2172  * @set_filter: true to set filter, false to clear filter
2173  * @cmd_details: pointer to command details structure or NULL
2174  *
2175  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2176  **/
2177 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2178                                 u16 seid, bool set_filter,
2179                                 struct i40e_asq_cmd_details *cmd_details)
2180 {
2181         struct i40e_aq_desc desc;
2182         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2183                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2184         enum i40e_status_code status;
2185
2186         i40e_fill_default_direct_cmd_desc(&desc,
2187                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2188
2189         if (set_filter)
2190                 cmd->promiscuous_flags
2191                             |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2192         else
2193                 cmd->promiscuous_flags
2194                             &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2195
2196         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2197         cmd->seid = CPU_TO_LE16(seid);
2198         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2199
2200         return status;
2201 }
2202
2203 /**
2204  * i40e_get_vsi_params - get VSI configuration info
2205  * @hw: pointer to the hw struct
2206  * @vsi_ctx: pointer to a vsi context struct
2207  * @cmd_details: pointer to command details structure or NULL
2208  **/
2209 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2210                                 struct i40e_vsi_context *vsi_ctx,
2211                                 struct i40e_asq_cmd_details *cmd_details)
2212 {
2213         struct i40e_aq_desc desc;
2214         struct i40e_aqc_add_get_update_vsi *cmd =
2215                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2216         struct i40e_aqc_add_get_update_vsi_completion *resp =
2217                 (struct i40e_aqc_add_get_update_vsi_completion *)
2218                 &desc.params.raw;
2219         enum i40e_status_code status;
2220
2221         UNREFERENCED_1PARAMETER(cmd_details);
2222         i40e_fill_default_direct_cmd_desc(&desc,
2223                                           i40e_aqc_opc_get_vsi_parameters);
2224
2225         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2226
2227         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2228
2229         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2230                                     sizeof(vsi_ctx->info), NULL);
2231
2232         if (status != I40E_SUCCESS)
2233                 goto aq_get_vsi_params_exit;
2234
2235         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2236         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2237         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2238         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2239
2240 aq_get_vsi_params_exit:
2241         return status;
2242 }
2243
2244 /**
2245  * i40e_aq_update_vsi_params
2246  * @hw: pointer to the hw struct
2247  * @vsi_ctx: pointer to a vsi context struct
2248  * @cmd_details: pointer to command details structure or NULL
2249  *
2250  * Update a VSI context.
2251  **/
2252 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2253                                 struct i40e_vsi_context *vsi_ctx,
2254                                 struct i40e_asq_cmd_details *cmd_details)
2255 {
2256         struct i40e_aq_desc desc;
2257         struct i40e_aqc_add_get_update_vsi *cmd =
2258                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2259         enum i40e_status_code status;
2260
2261         i40e_fill_default_direct_cmd_desc(&desc,
2262                                           i40e_aqc_opc_update_vsi_parameters);
2263         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2264
2265         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2266
2267         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2268                                     sizeof(vsi_ctx->info), cmd_details);
2269
2270         return status;
2271 }
2272
2273 /**
2274  * i40e_aq_get_switch_config
2275  * @hw: pointer to the hardware structure
2276  * @buf: pointer to the result buffer
2277  * @buf_size: length of input buffer
2278  * @start_seid: seid to start for the report, 0 == beginning
2279  * @cmd_details: pointer to command details structure or NULL
2280  *
2281  * Fill the buf with switch configuration returned from AdminQ command
2282  **/
2283 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2284                                 struct i40e_aqc_get_switch_config_resp *buf,
2285                                 u16 buf_size, u16 *start_seid,
2286                                 struct i40e_asq_cmd_details *cmd_details)
2287 {
2288         struct i40e_aq_desc desc;
2289         struct i40e_aqc_switch_seid *scfg =
2290                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2291         enum i40e_status_code status;
2292
2293         i40e_fill_default_direct_cmd_desc(&desc,
2294                                           i40e_aqc_opc_get_switch_config);
2295         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2296         if (buf_size > I40E_AQ_LARGE_BUF)
2297                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2298         scfg->seid = CPU_TO_LE16(*start_seid);
2299
2300         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2301         *start_seid = LE16_TO_CPU(scfg->seid);
2302
2303         return status;
2304 }
2305
2306 /**
2307  * i40e_aq_get_firmware_version
2308  * @hw: pointer to the hw struct
2309  * @fw_major_version: firmware major version
2310  * @fw_minor_version: firmware minor version
2311  * @fw_build: firmware build number
2312  * @api_major_version: major queue version
2313  * @api_minor_version: minor queue version
2314  * @cmd_details: pointer to command details structure or NULL
2315  *
2316  * Get the firmware version from the admin queue commands
2317  **/
2318 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2319                                 u16 *fw_major_version, u16 *fw_minor_version,
2320                                 u32 *fw_build,
2321                                 u16 *api_major_version, u16 *api_minor_version,
2322                                 struct i40e_asq_cmd_details *cmd_details)
2323 {
2324         struct i40e_aq_desc desc;
2325         struct i40e_aqc_get_version *resp =
2326                 (struct i40e_aqc_get_version *)&desc.params.raw;
2327         enum i40e_status_code status;
2328
2329         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2330
2331         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2332
2333         if (status == I40E_SUCCESS) {
2334                 if (fw_major_version != NULL)
2335                         *fw_major_version = LE16_TO_CPU(resp->fw_major);
2336                 if (fw_minor_version != NULL)
2337                         *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2338                 if (fw_build != NULL)
2339                         *fw_build = LE32_TO_CPU(resp->fw_build);
2340                 if (api_major_version != NULL)
2341                         *api_major_version = LE16_TO_CPU(resp->api_major);
2342                 if (api_minor_version != NULL)
2343                         *api_minor_version = LE16_TO_CPU(resp->api_minor);
2344
2345                 /* A workaround to fix the API version in SW */
2346                 if (api_major_version && api_minor_version &&
2347                     fw_major_version && fw_minor_version &&
2348                     ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2349                     (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2350                      (*fw_major_version > 4)))
2351                         *api_minor_version = 2;
2352         }
2353
2354         return status;
2355 }
2356
2357 /**
2358  * i40e_aq_send_driver_version
2359  * @hw: pointer to the hw struct
2360  * @dv: driver's major, minor version
2361  * @cmd_details: pointer to command details structure or NULL
2362  *
2363  * Send the driver version to the firmware
2364  **/
2365 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2366                                 struct i40e_driver_version *dv,
2367                                 struct i40e_asq_cmd_details *cmd_details)
2368 {
2369         struct i40e_aq_desc desc;
2370         struct i40e_aqc_driver_version *cmd =
2371                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2372         enum i40e_status_code status;
2373         u16 len;
2374
2375         if (dv == NULL)
2376                 return I40E_ERR_PARAM;
2377
2378         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2379
2380         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2381         cmd->driver_major_ver = dv->major_version;
2382         cmd->driver_minor_ver = dv->minor_version;
2383         cmd->driver_build_ver = dv->build_version;
2384         cmd->driver_subbuild_ver = dv->subbuild_version;
2385
2386         len = 0;
2387         while (len < sizeof(dv->driver_string) &&
2388                (dv->driver_string[len] < 0x80) &&
2389                dv->driver_string[len])
2390                 len++;
2391         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2392                                        len, cmd_details);
2393
2394         return status;
2395 }
2396
2397 /**
2398  * i40e_get_link_status - get status of the HW network link
2399  * @hw: pointer to the hw struct
2400  * @link_up: pointer to bool (true/false = linkup/linkdown)
2401  *
2402  * Variable link_up true if link is up, false if link is down.
2403  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2404  *
2405  * Side effect: LinkStatusEvent reporting becomes enabled
2406  **/
2407 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2408 {
2409         enum i40e_status_code status = I40E_SUCCESS;
2410
2411         if (hw->phy.get_link_info) {
2412                 status = i40e_update_link_info(hw);
2413
2414                 if (status != I40E_SUCCESS)
2415                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2416                                    status);
2417         }
2418
2419         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2420
2421         return status;
2422 }
2423
2424 /**
2425  * i40e_updatelink_status - update status of the HW network link
2426  * @hw: pointer to the hw struct
2427  **/
2428 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2429 {
2430         struct i40e_aq_get_phy_abilities_resp abilities;
2431         enum i40e_status_code status = I40E_SUCCESS;
2432
2433         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2434         if (status)
2435                 return status;
2436
2437         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
2438                                               NULL);
2439         if (status)
2440                 return status;
2441
2442         memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2443                 sizeof(hw->phy.link_info.module_type));
2444
2445         return status;
2446 }
2447
2448 /**
2449  * i40e_get_link_speed
2450  * @hw: pointer to the hw struct
2451  *
2452  * Returns the link speed of the adapter.
2453  **/
2454 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2455 {
2456         enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2457         enum i40e_status_code status = I40E_SUCCESS;
2458
2459         if (hw->phy.get_link_info) {
2460                 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2461
2462                 if (status != I40E_SUCCESS)
2463                         goto i40e_link_speed_exit;
2464         }
2465
2466         speed = hw->phy.link_info.link_speed;
2467
2468 i40e_link_speed_exit:
2469         return speed;
2470 }
2471
2472 /**
2473  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2474  * @hw: pointer to the hw struct
2475  * @uplink_seid: the MAC or other gizmo SEID
2476  * @downlink_seid: the VSI SEID
2477  * @enabled_tc: bitmap of TCs to be enabled
2478  * @default_port: true for default port VSI, false for control port
2479  * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
2480  * @veb_seid: pointer to where to put the resulting VEB SEID
2481  * @cmd_details: pointer to command details structure or NULL
2482  *
2483  * This asks the FW to add a VEB between the uplink and downlink
2484  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2485  **/
2486 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2487                                 u16 downlink_seid, u8 enabled_tc,
2488                                 bool default_port, bool enable_l2_filtering,
2489                                 u16 *veb_seid,
2490                                 struct i40e_asq_cmd_details *cmd_details)
2491 {
2492         struct i40e_aq_desc desc;
2493         struct i40e_aqc_add_veb *cmd =
2494                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2495         struct i40e_aqc_add_veb_completion *resp =
2496                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2497         enum i40e_status_code status;
2498         u16 veb_flags = 0;
2499
2500         /* SEIDs need to either both be set or both be 0 for floating VEB */
2501         if (!!uplink_seid != !!downlink_seid)
2502                 return I40E_ERR_PARAM;
2503
2504         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2505
2506         cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2507         cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2508         cmd->enable_tcs = enabled_tc;
2509         if (!uplink_seid)
2510                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2511         if (default_port)
2512                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2513         else
2514                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2515
2516         if (enable_l2_filtering)
2517                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
2518
2519         cmd->veb_flags = CPU_TO_LE16(veb_flags);
2520
2521         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2522
2523         if (!status && veb_seid)
2524                 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2525
2526         return status;
2527 }
2528
2529 /**
2530  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2531  * @hw: pointer to the hw struct
2532  * @veb_seid: the SEID of the VEB to query
2533  * @switch_id: the uplink switch id
2534  * @floating: set to true if the VEB is floating
2535  * @statistic_index: index of the stats counter block for this VEB
2536  * @vebs_used: number of VEB's used by function
2537  * @vebs_free: total VEB's not reserved by any function
2538  * @cmd_details: pointer to command details structure or NULL
2539  *
2540  * This retrieves the parameters for a particular VEB, specified by
2541  * uplink_seid, and returns them to the caller.
2542  **/
2543 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2544                                 u16 veb_seid, u16 *switch_id,
2545                                 bool *floating, u16 *statistic_index,
2546                                 u16 *vebs_used, u16 *vebs_free,
2547                                 struct i40e_asq_cmd_details *cmd_details)
2548 {
2549         struct i40e_aq_desc desc;
2550         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2551                 (struct i40e_aqc_get_veb_parameters_completion *)
2552                 &desc.params.raw;
2553         enum i40e_status_code status;
2554
2555         if (veb_seid == 0)
2556                 return I40E_ERR_PARAM;
2557
2558         i40e_fill_default_direct_cmd_desc(&desc,
2559                                           i40e_aqc_opc_get_veb_parameters);
2560         cmd_resp->seid = CPU_TO_LE16(veb_seid);
2561
2562         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2563         if (status)
2564                 goto get_veb_exit;
2565
2566         if (switch_id)
2567                 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2568         if (statistic_index)
2569                 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2570         if (vebs_used)
2571                 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2572         if (vebs_free)
2573                 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2574         if (floating) {
2575                 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2576                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2577                         *floating = true;
2578                 else
2579                         *floating = false;
2580         }
2581
2582 get_veb_exit:
2583         return status;
2584 }
2585
2586 /**
2587  * i40e_aq_add_macvlan
2588  * @hw: pointer to the hw struct
2589  * @seid: VSI for the mac address
2590  * @mv_list: list of macvlans to be added
2591  * @count: length of the list
2592  * @cmd_details: pointer to command details structure or NULL
2593  *
2594  * Add MAC/VLAN addresses to the HW filtering
2595  **/
2596 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2597                         struct i40e_aqc_add_macvlan_element_data *mv_list,
2598                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2599 {
2600         struct i40e_aq_desc desc;
2601         struct i40e_aqc_macvlan *cmd =
2602                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2603         enum i40e_status_code status;
2604         u16 buf_size;
2605
2606         if (count == 0 || !mv_list || !hw)
2607                 return I40E_ERR_PARAM;
2608
2609         buf_size = count * sizeof(*mv_list);
2610
2611         /* prep the rest of the request */
2612         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2613         cmd->num_addresses = CPU_TO_LE16(count);
2614         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2615         cmd->seid[1] = 0;
2616         cmd->seid[2] = 0;
2617
2618         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2619         if (buf_size > I40E_AQ_LARGE_BUF)
2620                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2621
2622         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2623                                     cmd_details);
2624
2625         return status;
2626 }
2627
2628 /**
2629  * i40e_aq_remove_macvlan
2630  * @hw: pointer to the hw struct
2631  * @seid: VSI for the mac address
2632  * @mv_list: list of macvlans to be removed
2633  * @count: length of the list
2634  * @cmd_details: pointer to command details structure or NULL
2635  *
2636  * Remove MAC/VLAN addresses from the HW filtering
2637  **/
2638 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2639                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
2640                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2641 {
2642         struct i40e_aq_desc desc;
2643         struct i40e_aqc_macvlan *cmd =
2644                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2645         enum i40e_status_code status;
2646         u16 buf_size;
2647
2648         if (count == 0 || !mv_list || !hw)
2649                 return I40E_ERR_PARAM;
2650
2651         buf_size = count * sizeof(*mv_list);
2652
2653         /* prep the rest of the request */
2654         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2655         cmd->num_addresses = CPU_TO_LE16(count);
2656         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2657         cmd->seid[1] = 0;
2658         cmd->seid[2] = 0;
2659
2660         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2661         if (buf_size > I40E_AQ_LARGE_BUF)
2662                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2663
2664         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2665                                        cmd_details);
2666
2667         return status;
2668 }
2669
2670 /**
2671  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
2672  * @hw: pointer to the hw struct
2673  * @seid: VSI for the vlan filters
2674  * @v_list: list of vlan filters to be added
2675  * @count: length of the list
2676  * @cmd_details: pointer to command details structure or NULL
2677  **/
2678 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
2679                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
2680                         u8 count, struct i40e_asq_cmd_details *cmd_details)
2681 {
2682         struct i40e_aq_desc desc;
2683         struct i40e_aqc_macvlan *cmd =
2684                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2685         enum i40e_status_code status;
2686         u16 buf_size;
2687
2688         if (count == 0 || !v_list || !hw)
2689                 return I40E_ERR_PARAM;
2690
2691         buf_size = count * sizeof(*v_list);
2692
2693         /* prep the rest of the request */
2694         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
2695         cmd->num_addresses = CPU_TO_LE16(count);
2696         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2697         cmd->seid[1] = 0;
2698         cmd->seid[2] = 0;
2699
2700         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2701         if (buf_size > I40E_AQ_LARGE_BUF)
2702                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2703
2704         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2705                                        cmd_details);
2706
2707         return status;
2708 }
2709
2710 /**
2711  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
2712  * @hw: pointer to the hw struct
2713  * @seid: VSI for the vlan filters
2714  * @v_list: list of macvlans to be removed
2715  * @count: length of the list
2716  * @cmd_details: pointer to command details structure or NULL
2717  **/
2718 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
2719                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
2720                         u8 count, struct i40e_asq_cmd_details *cmd_details)
2721 {
2722         struct i40e_aq_desc desc;
2723         struct i40e_aqc_macvlan *cmd =
2724                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2725         enum i40e_status_code status;
2726         u16 buf_size;
2727
2728         if (count == 0 || !v_list || !hw)
2729                 return I40E_ERR_PARAM;
2730
2731         buf_size = count * sizeof(*v_list);
2732
2733         /* prep the rest of the request */
2734         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
2735         cmd->num_addresses = CPU_TO_LE16(count);
2736         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2737         cmd->seid[1] = 0;
2738         cmd->seid[2] = 0;
2739
2740         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2741         if (buf_size > I40E_AQ_LARGE_BUF)
2742                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2743
2744         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2745                                        cmd_details);
2746
2747         return status;
2748 }
2749
2750 /**
2751  * i40e_aq_send_msg_to_vf
2752  * @hw: pointer to the hardware structure
2753  * @vfid: vf id to send msg
2754  * @v_opcode: opcodes for VF-PF communication
2755  * @v_retval: return error code
2756  * @msg: pointer to the msg buffer
2757  * @msglen: msg length
2758  * @cmd_details: pointer to command details
2759  *
2760  * send msg to vf
2761  **/
2762 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2763                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2764                                 struct i40e_asq_cmd_details *cmd_details)
2765 {
2766         struct i40e_aq_desc desc;
2767         struct i40e_aqc_pf_vf_message *cmd =
2768                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2769         enum i40e_status_code status;
2770
2771         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2772         cmd->id = CPU_TO_LE32(vfid);
2773         desc.cookie_high = CPU_TO_LE32(v_opcode);
2774         desc.cookie_low = CPU_TO_LE32(v_retval);
2775         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
2776         if (msglen) {
2777                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
2778                                                 I40E_AQ_FLAG_RD));
2779                 if (msglen > I40E_AQ_LARGE_BUF)
2780                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2781                 desc.datalen = CPU_TO_LE16(msglen);
2782         }
2783         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2784
2785         return status;
2786 }
2787
2788 /**
2789  * i40e_aq_debug_read_register
2790  * @hw: pointer to the hw struct
2791  * @reg_addr: register address
2792  * @reg_val: register value
2793  * @cmd_details: pointer to command details structure or NULL
2794  *
2795  * Read the register using the admin queue commands
2796  **/
2797 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
2798                                 u32 reg_addr, u64 *reg_val,
2799                                 struct i40e_asq_cmd_details *cmd_details)
2800 {
2801         struct i40e_aq_desc desc;
2802         struct i40e_aqc_debug_reg_read_write *cmd_resp =
2803                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2804         enum i40e_status_code status;
2805
2806         if (reg_val == NULL)
2807                 return I40E_ERR_PARAM;
2808
2809         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2810
2811         cmd_resp->address = CPU_TO_LE32(reg_addr);
2812
2813         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2814
2815         if (status == I40E_SUCCESS) {
2816                 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
2817                            (u64)LE32_TO_CPU(cmd_resp->value_low);
2818         }
2819
2820         return status;
2821 }
2822
2823 /**
2824  * i40e_aq_debug_write_register
2825  * @hw: pointer to the hw struct
2826  * @reg_addr: register address
2827  * @reg_val: register value
2828  * @cmd_details: pointer to command details structure or NULL
2829  *
2830  * Write to a register using the admin queue commands
2831  **/
2832 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
2833                                 u32 reg_addr, u64 reg_val,
2834                                 struct i40e_asq_cmd_details *cmd_details)
2835 {
2836         struct i40e_aq_desc desc;
2837         struct i40e_aqc_debug_reg_read_write *cmd =
2838                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2839         enum i40e_status_code status;
2840
2841         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2842
2843         cmd->address = CPU_TO_LE32(reg_addr);
2844         cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
2845         cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
2846
2847         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2848
2849         return status;
2850 }
2851
2852 /**
2853  * i40e_aq_get_hmc_resource_profile
2854  * @hw: pointer to the hw struct
2855  * @profile: type of profile the HMC is to be set as
2856  * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2857  * @cmd_details: pointer to command details structure or NULL
2858  *
2859  * query the HMC profile of the device.
2860  **/
2861 enum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw,
2862                                 enum i40e_aq_hmc_profile *profile,
2863                                 u8 *pe_vf_enabled_count,
2864                                 struct i40e_asq_cmd_details *cmd_details)
2865 {
2866         struct i40e_aq_desc desc;
2867         struct i40e_aq_get_set_hmc_resource_profile *resp =
2868                 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2869         enum i40e_status_code status;
2870
2871         i40e_fill_default_direct_cmd_desc(&desc,
2872                                 i40e_aqc_opc_query_hmc_resource_profile);
2873         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2874
2875         *profile = (enum i40e_aq_hmc_profile)(resp->pm_profile &
2876                    I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK);
2877         *pe_vf_enabled_count = resp->pe_vf_enabled &
2878                                I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK;
2879
2880         return status;
2881 }
2882
2883 /**
2884  * i40e_aq_set_hmc_resource_profile
2885  * @hw: pointer to the hw struct
2886  * @profile: type of profile the HMC is to be set as
2887  * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2888  * @cmd_details: pointer to command details structure or NULL
2889  *
2890  * set the HMC profile of the device.
2891  **/
2892 enum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2893                                 enum i40e_aq_hmc_profile profile,
2894                                 u8 pe_vf_enabled_count,
2895                                 struct i40e_asq_cmd_details *cmd_details)
2896 {
2897         struct i40e_aq_desc desc;
2898         struct i40e_aq_get_set_hmc_resource_profile *cmd =
2899                 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2900         enum i40e_status_code status;
2901
2902         i40e_fill_default_direct_cmd_desc(&desc,
2903                                         i40e_aqc_opc_set_hmc_resource_profile);
2904
2905         cmd->pm_profile = (u8)profile;
2906         cmd->pe_vf_enabled = pe_vf_enabled_count;
2907
2908         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2909
2910         return status;
2911 }
2912
2913 /**
2914  * i40e_aq_request_resource
2915  * @hw: pointer to the hw struct
2916  * @resource: resource id
2917  * @access: access type
2918  * @sdp_number: resource number
2919  * @timeout: the maximum time in ms that the driver may hold the resource
2920  * @cmd_details: pointer to command details structure or NULL
2921  *
2922  * requests common resource using the admin queue commands
2923  **/
2924 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
2925                                 enum i40e_aq_resources_ids resource,
2926                                 enum i40e_aq_resource_access_type access,
2927                                 u8 sdp_number, u64 *timeout,
2928                                 struct i40e_asq_cmd_details *cmd_details)
2929 {
2930         struct i40e_aq_desc desc;
2931         struct i40e_aqc_request_resource *cmd_resp =
2932                 (struct i40e_aqc_request_resource *)&desc.params.raw;
2933         enum i40e_status_code status;
2934
2935         DEBUGFUNC("i40e_aq_request_resource");
2936
2937         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2938
2939         cmd_resp->resource_id = CPU_TO_LE16(resource);
2940         cmd_resp->access_type = CPU_TO_LE16(access);
2941         cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
2942
2943         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2944         /* The completion specifies the maximum time in ms that the driver
2945          * may hold the resource in the Timeout field.
2946          * If the resource is held by someone else, the command completes with
2947          * busy return value and the timeout field indicates the maximum time
2948          * the current owner of the resource has to free it.
2949          */
2950         if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2951                 *timeout = LE32_TO_CPU(cmd_resp->timeout);
2952
2953         return status;
2954 }
2955
2956 /**
2957  * i40e_aq_release_resource
2958  * @hw: pointer to the hw struct
2959  * @resource: resource id
2960  * @sdp_number: resource number
2961  * @cmd_details: pointer to command details structure or NULL
2962  *
2963  * release common resource using the admin queue commands
2964  **/
2965 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
2966                                 enum i40e_aq_resources_ids resource,
2967                                 u8 sdp_number,
2968                                 struct i40e_asq_cmd_details *cmd_details)
2969 {
2970         struct i40e_aq_desc desc;
2971         struct i40e_aqc_request_resource *cmd =
2972                 (struct i40e_aqc_request_resource *)&desc.params.raw;
2973         enum i40e_status_code status;
2974
2975         DEBUGFUNC("i40e_aq_release_resource");
2976
2977         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2978
2979         cmd->resource_id = CPU_TO_LE16(resource);
2980         cmd->resource_number = CPU_TO_LE32(sdp_number);
2981
2982         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2983
2984         return status;
2985 }
2986
2987 /**
2988  * i40e_aq_read_nvm
2989  * @hw: pointer to the hw struct
2990  * @module_pointer: module pointer location in words from the NVM beginning
2991  * @offset: byte offset from the module beginning
2992  * @length: length of the section to be read (in bytes from the offset)
2993  * @data: command buffer (size [bytes] = length)
2994  * @last_command: tells if this is the last command in a series
2995  * @cmd_details: pointer to command details structure or NULL
2996  *
2997  * Read the NVM using the admin queue commands
2998  **/
2999 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3000                                 u32 offset, u16 length, void *data,
3001                                 bool last_command,
3002                                 struct i40e_asq_cmd_details *cmd_details)
3003 {
3004         struct i40e_aq_desc desc;
3005         struct i40e_aqc_nvm_update *cmd =
3006                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3007         enum i40e_status_code status;
3008
3009         DEBUGFUNC("i40e_aq_read_nvm");
3010
3011         /* In offset the highest byte must be zeroed. */
3012         if (offset & 0xFF000000) {
3013                 status = I40E_ERR_PARAM;
3014                 goto i40e_aq_read_nvm_exit;
3015         }
3016
3017         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3018
3019         /* If this is the last command in a series, set the proper flag. */
3020         if (last_command)
3021                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3022         cmd->module_pointer = module_pointer;
3023         cmd->offset = CPU_TO_LE32(offset);
3024         cmd->length = CPU_TO_LE16(length);
3025
3026         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3027         if (length > I40E_AQ_LARGE_BUF)
3028                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3029
3030         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3031
3032 i40e_aq_read_nvm_exit:
3033         return status;
3034 }
3035
3036 /**
3037  * i40e_aq_read_nvm_config - read an nvm config block
3038  * @hw: pointer to the hw struct
3039  * @cmd_flags: NVM access admin command bits
3040  * @field_id: field or feature id
3041  * @data: buffer for result
3042  * @buf_size: buffer size
3043  * @element_count: pointer to count of elements read by FW
3044  * @cmd_details: pointer to command details structure or NULL
3045  **/
3046 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3047                                 u8 cmd_flags, u32 field_id, void *data,
3048                                 u16 buf_size, u16 *element_count,
3049                                 struct i40e_asq_cmd_details *cmd_details)
3050 {
3051         struct i40e_aq_desc desc;
3052         struct i40e_aqc_nvm_config_read *cmd =
3053                 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3054         enum i40e_status_code status;
3055
3056         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3057         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3058         if (buf_size > I40E_AQ_LARGE_BUF)
3059                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3060
3061         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3062         cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3063         if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3064                 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3065         else
3066                 cmd->element_id_msw = 0;
3067
3068         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3069
3070         if (!status && element_count)
3071                 *element_count = LE16_TO_CPU(cmd->element_count);
3072
3073         return status;
3074 }
3075
3076 /**
3077  * i40e_aq_write_nvm_config - write an nvm config block
3078  * @hw: pointer to the hw struct
3079  * @cmd_flags: NVM access admin command bits
3080  * @data: buffer for result
3081  * @buf_size: buffer size
3082  * @element_count: count of elements to be written
3083  * @cmd_details: pointer to command details structure or NULL
3084  **/
3085 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3086                                 u8 cmd_flags, void *data, u16 buf_size,
3087                                 u16 element_count,
3088                                 struct i40e_asq_cmd_details *cmd_details)
3089 {
3090         struct i40e_aq_desc desc;
3091         struct i40e_aqc_nvm_config_write *cmd =
3092                 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3093         enum i40e_status_code status;
3094
3095         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3096         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3097         if (buf_size > I40E_AQ_LARGE_BUF)
3098                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3099
3100         cmd->element_count = CPU_TO_LE16(element_count);
3101         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3102         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3103
3104         return status;
3105 }
3106
3107 /**
3108  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3109  * @hw: pointer to the hw struct
3110  * @cmd_details: pointer to command details structure or NULL
3111  **/
3112 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3113                                 void *buff, u16 buff_size,
3114                                 struct i40e_asq_cmd_details *cmd_details)
3115 {
3116         struct i40e_aq_desc desc;
3117         enum i40e_status_code status;
3118
3119         UNREFERENCED_2PARAMETER(buff, buff_size);
3120
3121         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3122         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3123         if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3124                 status = I40E_ERR_NOT_IMPLEMENTED;
3125
3126         return status;
3127 }
3128
3129 /**
3130  * i40e_aq_erase_nvm
3131  * @hw: pointer to the hw struct
3132  * @module_pointer: module pointer location in words from the NVM beginning
3133  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3134  * @length: length of the section to be erased (expressed in 4 KB)
3135  * @last_command: tells if this is the last command in a series
3136  * @cmd_details: pointer to command details structure or NULL
3137  *
3138  * Erase the NVM sector using the admin queue commands
3139  **/
3140 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3141                                 u32 offset, u16 length, bool last_command,
3142                                 struct i40e_asq_cmd_details *cmd_details)
3143 {
3144         struct i40e_aq_desc desc;
3145         struct i40e_aqc_nvm_update *cmd =
3146                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3147         enum i40e_status_code status;
3148
3149         DEBUGFUNC("i40e_aq_erase_nvm");
3150
3151         /* In offset the highest byte must be zeroed. */
3152         if (offset & 0xFF000000) {
3153                 status = I40E_ERR_PARAM;
3154                 goto i40e_aq_erase_nvm_exit;
3155         }
3156
3157         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3158
3159         /* If this is the last command in a series, set the proper flag. */
3160         if (last_command)
3161                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3162         cmd->module_pointer = module_pointer;
3163         cmd->offset = CPU_TO_LE32(offset);
3164         cmd->length = CPU_TO_LE16(length);
3165
3166         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3167
3168 i40e_aq_erase_nvm_exit:
3169         return status;
3170 }
3171
3172 #define I40E_DEV_FUNC_CAP_SWITCH_MODE   0x01
3173 #define I40E_DEV_FUNC_CAP_MGMT_MODE     0x02
3174 #define I40E_DEV_FUNC_CAP_NPAR          0x03
3175 #define I40E_DEV_FUNC_CAP_OS2BMC        0x04
3176 #define I40E_DEV_FUNC_CAP_VALID_FUNC    0x05
3177 #define I40E_DEV_FUNC_CAP_SRIOV_1_1     0x12
3178 #define I40E_DEV_FUNC_CAP_VF            0x13
3179 #define I40E_DEV_FUNC_CAP_VMDQ          0x14
3180 #define I40E_DEV_FUNC_CAP_802_1_QBG     0x15
3181 #define I40E_DEV_FUNC_CAP_802_1_QBH     0x16
3182 #define I40E_DEV_FUNC_CAP_VSI           0x17
3183 #define I40E_DEV_FUNC_CAP_DCB           0x18
3184 #define I40E_DEV_FUNC_CAP_FCOE          0x21
3185 #define I40E_DEV_FUNC_CAP_ISCSI         0x22
3186 #define I40E_DEV_FUNC_CAP_RSS           0x40
3187 #define I40E_DEV_FUNC_CAP_RX_QUEUES     0x41
3188 #define I40E_DEV_FUNC_CAP_TX_QUEUES     0x42
3189 #define I40E_DEV_FUNC_CAP_MSIX          0x43
3190 #define I40E_DEV_FUNC_CAP_MSIX_VF       0x44
3191 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
3192 #define I40E_DEV_FUNC_CAP_IEEE_1588     0x46
3193 #define I40E_DEV_FUNC_CAP_FLEX10        0xF1
3194 #define I40E_DEV_FUNC_CAP_CEM           0xF2
3195 #define I40E_DEV_FUNC_CAP_IWARP         0x51
3196 #define I40E_DEV_FUNC_CAP_LED           0x61
3197 #define I40E_DEV_FUNC_CAP_SDP           0x62
3198 #define I40E_DEV_FUNC_CAP_MDIO          0x63
3199
3200 /**
3201  * i40e_parse_discover_capabilities
3202  * @hw: pointer to the hw struct
3203  * @buff: pointer to a buffer containing device/function capability records
3204  * @cap_count: number of capability records in the list
3205  * @list_type_opc: type of capabilities list to parse
3206  *
3207  * Parse the device/function capabilities list.
3208  **/
3209 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3210                                      u32 cap_count,
3211                                      enum i40e_admin_queue_opc list_type_opc)
3212 {
3213         struct i40e_aqc_list_capabilities_element_resp *cap;
3214         u32 valid_functions, num_functions;
3215         u32 number, logical_id, phys_id;
3216         struct i40e_hw_capabilities *p;
3217         u8 major_rev;
3218         u32 i = 0;
3219         u16 id;
3220
3221         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3222
3223         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3224                 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3225         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3226                 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3227         else
3228                 return;
3229
3230         for (i = 0; i < cap_count; i++, cap++) {
3231                 id = LE16_TO_CPU(cap->id);
3232                 number = LE32_TO_CPU(cap->number);
3233                 logical_id = LE32_TO_CPU(cap->logical_id);
3234                 phys_id = LE32_TO_CPU(cap->phys_id);
3235                 major_rev = cap->major_rev;
3236
3237                 switch (id) {
3238                 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
3239                         p->switch_mode = number;
3240                         break;
3241                 case I40E_DEV_FUNC_CAP_MGMT_MODE:
3242                         p->management_mode = number;
3243                         break;
3244                 case I40E_DEV_FUNC_CAP_NPAR:
3245                         p->npar_enable = number;
3246                         break;
3247                 case I40E_DEV_FUNC_CAP_OS2BMC:
3248                         p->os2bmc = number;
3249                         break;
3250                 case I40E_DEV_FUNC_CAP_VALID_FUNC:
3251                         p->valid_functions = number;
3252                         break;
3253                 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
3254                         if (number == 1)
3255                                 p->sr_iov_1_1 = true;
3256                         break;
3257                 case I40E_DEV_FUNC_CAP_VF:
3258                         p->num_vfs = number;
3259                         p->vf_base_id = logical_id;
3260                         break;
3261                 case I40E_DEV_FUNC_CAP_VMDQ:
3262                         if (number == 1)
3263                                 p->vmdq = true;
3264                         break;
3265                 case I40E_DEV_FUNC_CAP_802_1_QBG:
3266                         if (number == 1)
3267                                 p->evb_802_1_qbg = true;
3268                         break;
3269                 case I40E_DEV_FUNC_CAP_802_1_QBH:
3270                         if (number == 1)
3271                                 p->evb_802_1_qbh = true;
3272                         break;
3273                 case I40E_DEV_FUNC_CAP_VSI:
3274                         p->num_vsis = number;
3275                         break;
3276                 case I40E_DEV_FUNC_CAP_DCB:
3277                         if (number == 1) {
3278                                 p->dcb = true;
3279                                 p->enabled_tcmap = logical_id;
3280                                 p->maxtc = phys_id;
3281                         }
3282                         break;
3283                 case I40E_DEV_FUNC_CAP_FCOE:
3284                         if (number == 1)
3285                                 p->fcoe = true;
3286                         break;
3287                 case I40E_DEV_FUNC_CAP_ISCSI:
3288                         if (number == 1)
3289                                 p->iscsi = true;
3290                         break;
3291                 case I40E_DEV_FUNC_CAP_RSS:
3292                         p->rss = true;
3293                         p->rss_table_size = number;
3294                         p->rss_table_entry_width = logical_id;
3295                         break;
3296                 case I40E_DEV_FUNC_CAP_RX_QUEUES:
3297                         p->num_rx_qp = number;
3298                         p->base_queue = phys_id;
3299                         break;
3300                 case I40E_DEV_FUNC_CAP_TX_QUEUES:
3301                         p->num_tx_qp = number;
3302                         p->base_queue = phys_id;
3303                         break;
3304                 case I40E_DEV_FUNC_CAP_MSIX:
3305                         p->num_msix_vectors = number;
3306                         break;
3307                 case I40E_DEV_FUNC_CAP_MSIX_VF:
3308                         p->num_msix_vectors_vf = number;
3309                         break;
3310                 case I40E_DEV_FUNC_CAP_FLEX10:
3311                         if (major_rev == 1) {
3312                                 if (number == 1) {
3313                                         p->flex10_enable = true;
3314                                         p->flex10_capable = true;
3315                                 }
3316                         } else {
3317                                 /* Capability revision >= 2 */
3318                                 if (number & 1)
3319                                         p->flex10_enable = true;
3320                                 if (number & 2)
3321                                         p->flex10_capable = true;
3322                         }
3323                         p->flex10_mode = logical_id;
3324                         p->flex10_status = phys_id;
3325                         break;
3326                 case I40E_DEV_FUNC_CAP_CEM:
3327                         if (number == 1)
3328                                 p->mgmt_cem = true;
3329                         break;
3330                 case I40E_DEV_FUNC_CAP_IWARP:
3331                         if (number == 1)
3332                                 p->iwarp = true;
3333                         break;
3334                 case I40E_DEV_FUNC_CAP_LED:
3335                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3336                                 p->led[phys_id] = true;
3337                         break;
3338                 case I40E_DEV_FUNC_CAP_SDP:
3339                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3340                                 p->sdp[phys_id] = true;
3341                         break;
3342                 case I40E_DEV_FUNC_CAP_MDIO:
3343                         if (number == 1) {
3344                                 p->mdio_port_num = phys_id;
3345                                 p->mdio_port_mode = logical_id;
3346                         }
3347                         break;
3348                 case I40E_DEV_FUNC_CAP_IEEE_1588:
3349                         if (number == 1)
3350                                 p->ieee_1588 = true;
3351                         break;
3352                 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
3353                         p->fd = true;
3354                         p->fd_filters_guaranteed = number;
3355                         p->fd_filters_best_effort = logical_id;
3356                         break;
3357                 default:
3358                         break;
3359                 }
3360         }
3361
3362         if (p->fcoe)
3363                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3364
3365 #ifdef I40E_FCOE_ENA
3366         /* Software override ensuring FCoE is disabled if npar or mfp
3367          * mode because it is not supported in these modes.
3368          */
3369         if (p->npar_enable || p->flex10_enable)
3370                 p->fcoe = false;
3371 #else
3372         /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3373         p->fcoe = false;
3374 #endif
3375
3376         /* count the enabled ports (aka the "not disabled" ports) */
3377         hw->num_ports = 0;
3378         for (i = 0; i < 4; i++) {
3379                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3380                 u64 port_cfg = 0;
3381
3382                 /* use AQ read to get the physical register offset instead
3383                  * of the port relative offset
3384                  */
3385                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3386                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3387                         hw->num_ports++;
3388         }
3389
3390         valid_functions = p->valid_functions;
3391         num_functions = 0;
3392         while (valid_functions) {
3393                 if (valid_functions & 1)
3394                         num_functions++;
3395                 valid_functions >>= 1;
3396         }
3397
3398         /* partition id is 1-based, and functions are evenly spread
3399          * across the ports as partitions
3400          */
3401         hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3402         hw->num_partitions = num_functions / hw->num_ports;
3403
3404         /* additional HW specific goodies that might
3405          * someday be HW version specific
3406          */
3407         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3408 }
3409
3410 /**
3411  * i40e_aq_discover_capabilities
3412  * @hw: pointer to the hw struct
3413  * @buff: a virtual buffer to hold the capabilities
3414  * @buff_size: Size of the virtual buffer
3415  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3416  * @list_type_opc: capabilities type to discover - pass in the command opcode
3417  * @cmd_details: pointer to command details structure or NULL
3418  *
3419  * Get the device capabilities descriptions from the firmware
3420  **/
3421 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3422                                 void *buff, u16 buff_size, u16 *data_size,
3423                                 enum i40e_admin_queue_opc list_type_opc,
3424                                 struct i40e_asq_cmd_details *cmd_details)
3425 {
3426         struct i40e_aqc_list_capabilites *cmd;
3427         struct i40e_aq_desc desc;
3428         enum i40e_status_code status = I40E_SUCCESS;
3429
3430         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3431
3432         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3433                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3434                 status = I40E_ERR_PARAM;
3435                 goto exit;
3436         }
3437
3438         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3439
3440         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3441         if (buff_size > I40E_AQ_LARGE_BUF)
3442                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3443
3444         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3445         *data_size = LE16_TO_CPU(desc.datalen);
3446
3447         if (status)
3448                 goto exit;
3449
3450         i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3451                                          list_type_opc);
3452
3453 exit:
3454         return status;
3455 }
3456
3457 /**
3458  * i40e_aq_update_nvm
3459  * @hw: pointer to the hw struct
3460  * @module_pointer: module pointer location in words from the NVM beginning
3461  * @offset: byte offset from the module beginning
3462  * @length: length of the section to be written (in bytes from the offset)
3463  * @data: command buffer (size [bytes] = length)
3464  * @last_command: tells if this is the last command in a series
3465  * @cmd_details: pointer to command details structure or NULL
3466  *
3467  * Update the NVM using the admin queue commands
3468  **/
3469 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3470                                 u32 offset, u16 length, void *data,
3471                                 bool last_command,
3472                                 struct i40e_asq_cmd_details *cmd_details)
3473 {
3474         struct i40e_aq_desc desc;
3475         struct i40e_aqc_nvm_update *cmd =
3476                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3477         enum i40e_status_code status;
3478
3479         DEBUGFUNC("i40e_aq_update_nvm");
3480
3481         /* In offset the highest byte must be zeroed. */
3482         if (offset & 0xFF000000) {
3483                 status = I40E_ERR_PARAM;
3484                 goto i40e_aq_update_nvm_exit;
3485         }
3486
3487         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3488
3489         /* If this is the last command in a series, set the proper flag. */
3490         if (last_command)
3491                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3492         cmd->module_pointer = module_pointer;
3493         cmd->offset = CPU_TO_LE32(offset);
3494         cmd->length = CPU_TO_LE16(length);
3495
3496         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3497         if (length > I40E_AQ_LARGE_BUF)
3498                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3499
3500         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3501
3502 i40e_aq_update_nvm_exit:
3503         return status;
3504 }
3505
3506 /**
3507  * i40e_aq_get_lldp_mib
3508  * @hw: pointer to the hw struct
3509  * @bridge_type: type of bridge requested
3510  * @mib_type: Local, Remote or both Local and Remote MIBs
3511  * @buff: pointer to a user supplied buffer to store the MIB block
3512  * @buff_size: size of the buffer (in bytes)
3513  * @local_len : length of the returned Local LLDP MIB
3514  * @remote_len: length of the returned Remote LLDP MIB
3515  * @cmd_details: pointer to command details structure or NULL
3516  *
3517  * Requests the complete LLDP MIB (entire packet).
3518  **/
3519 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3520                                 u8 mib_type, void *buff, u16 buff_size,
3521                                 u16 *local_len, u16 *remote_len,
3522                                 struct i40e_asq_cmd_details *cmd_details)
3523 {
3524         struct i40e_aq_desc desc;
3525         struct i40e_aqc_lldp_get_mib *cmd =
3526                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3527         struct i40e_aqc_lldp_get_mib *resp =
3528                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3529         enum i40e_status_code status;
3530
3531         if (buff_size == 0 || !buff)
3532                 return I40E_ERR_PARAM;
3533
3534         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3535         /* Indirect Command */
3536         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3537
3538         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3539         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3540                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3541
3542         desc.datalen = CPU_TO_LE16(buff_size);
3543
3544         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3545         if (buff_size > I40E_AQ_LARGE_BUF)
3546                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3547
3548         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3549         if (!status) {
3550                 if (local_len != NULL)
3551                         *local_len = LE16_TO_CPU(resp->local_len);
3552                 if (remote_len != NULL)
3553                         *remote_len = LE16_TO_CPU(resp->remote_len);
3554         }
3555
3556         return status;
3557 }
3558
3559  /**
3560  * i40e_aq_set_lldp_mib - Set the LLDP MIB
3561  * @hw: pointer to the hw struct
3562  * @mib_type: Local, Remote or both Local and Remote MIBs
3563  * @buff: pointer to a user supplied buffer to store the MIB block
3564  * @buff_size: size of the buffer (in bytes)
3565  * @cmd_details: pointer to command details structure or NULL
3566  *
3567  * Set the LLDP MIB.
3568  **/
3569 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
3570                                 u8 mib_type, void *buff, u16 buff_size,
3571                                 struct i40e_asq_cmd_details *cmd_details)
3572 {
3573         struct i40e_aq_desc desc;
3574         struct i40e_aqc_lldp_set_local_mib *cmd =
3575                 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
3576         enum i40e_status_code status;
3577
3578         if (buff_size == 0 || !buff)
3579                 return I40E_ERR_PARAM;
3580
3581         i40e_fill_default_direct_cmd_desc(&desc,
3582                                 i40e_aqc_opc_lldp_set_local_mib);
3583         /* Indirect Command */
3584         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3585         if (buff_size > I40E_AQ_LARGE_BUF)
3586                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3587         desc.datalen = CPU_TO_LE16(buff_size);
3588
3589         cmd->type = mib_type;
3590         cmd->length = CPU_TO_LE16(buff_size);
3591         cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
3592         cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
3593
3594         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3595         return status;
3596 }
3597
3598 /**
3599  * i40e_aq_cfg_lldp_mib_change_event
3600  * @hw: pointer to the hw struct
3601  * @enable_update: Enable or Disable event posting
3602  * @cmd_details: pointer to command details structure or NULL
3603  *
3604  * Enable or Disable posting of an event on ARQ when LLDP MIB
3605  * associated with the interface changes
3606  **/
3607 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3608                                 bool enable_update,
3609                                 struct i40e_asq_cmd_details *cmd_details)
3610 {
3611         struct i40e_aq_desc desc;
3612         struct i40e_aqc_lldp_update_mib *cmd =
3613                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3614         enum i40e_status_code status;
3615
3616         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3617
3618         if (!enable_update)
3619                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3620
3621         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3622
3623         return status;
3624 }
3625
3626 /**
3627  * i40e_aq_add_lldp_tlv
3628  * @hw: pointer to the hw struct
3629  * @bridge_type: type of bridge
3630  * @buff: buffer with TLV to add
3631  * @buff_size: length of the buffer
3632  * @tlv_len: length of the TLV to be added
3633  * @mib_len: length of the LLDP MIB returned in response
3634  * @cmd_details: pointer to command details structure or NULL
3635  *
3636  * Add the specified TLV to LLDP Local MIB for the given bridge type,
3637  * it is responsibility of the caller to make sure that the TLV is not
3638  * already present in the LLDPDU.
3639  * In return firmware will write the complete LLDP MIB with the newly
3640  * added TLV in the response buffer.
3641  **/
3642 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
3643                                 void *buff, u16 buff_size, u16 tlv_len,
3644                                 u16 *mib_len,
3645                                 struct i40e_asq_cmd_details *cmd_details)
3646 {
3647         struct i40e_aq_desc desc;
3648         struct i40e_aqc_lldp_add_tlv *cmd =
3649                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3650         enum i40e_status_code status;
3651
3652         if (buff_size == 0 || !buff || tlv_len == 0)
3653                 return I40E_ERR_PARAM;
3654
3655         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
3656
3657         /* Indirect Command */
3658         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3659         if (buff_size > I40E_AQ_LARGE_BUF)
3660                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3661         desc.datalen = CPU_TO_LE16(buff_size);
3662
3663         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3664                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3665         cmd->len = CPU_TO_LE16(tlv_len);
3666
3667         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3668         if (!status) {
3669                 if (mib_len != NULL)
3670                         *mib_len = LE16_TO_CPU(desc.datalen);
3671         }
3672
3673         return status;
3674 }
3675
3676 /**
3677  * i40e_aq_update_lldp_tlv
3678  * @hw: pointer to the hw struct
3679  * @bridge_type: type of bridge
3680  * @buff: buffer with TLV to update
3681  * @buff_size: size of the buffer holding original and updated TLVs
3682  * @old_len: Length of the Original TLV
3683  * @new_len: Length of the Updated TLV
3684  * @offset: offset of the updated TLV in the buff
3685  * @mib_len: length of the returned LLDP MIB
3686  * @cmd_details: pointer to command details structure or NULL
3687  *
3688  * Update the specified TLV to the LLDP Local MIB for the given bridge type.
3689  * Firmware will place the complete LLDP MIB in response buffer with the
3690  * updated TLV.
3691  **/
3692 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
3693                                 u8 bridge_type, void *buff, u16 buff_size,
3694                                 u16 old_len, u16 new_len, u16 offset,
3695                                 u16 *mib_len,
3696                                 struct i40e_asq_cmd_details *cmd_details)
3697 {
3698         struct i40e_aq_desc desc;
3699         struct i40e_aqc_lldp_update_tlv *cmd =
3700                 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
3701         enum i40e_status_code status;
3702
3703         if (buff_size == 0 || !buff || offset == 0 ||
3704             old_len == 0 || new_len == 0)
3705                 return I40E_ERR_PARAM;
3706
3707         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
3708
3709         /* Indirect Command */
3710         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3711         if (buff_size > I40E_AQ_LARGE_BUF)
3712                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3713         desc.datalen = CPU_TO_LE16(buff_size);
3714
3715         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3716                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3717         cmd->old_len = CPU_TO_LE16(old_len);
3718         cmd->new_offset = CPU_TO_LE16(offset);
3719         cmd->new_len = CPU_TO_LE16(new_len);
3720
3721         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3722         if (!status) {
3723                 if (mib_len != NULL)
3724                         *mib_len = LE16_TO_CPU(desc.datalen);
3725         }
3726
3727         return status;
3728 }
3729
3730 /**
3731  * i40e_aq_delete_lldp_tlv
3732  * @hw: pointer to the hw struct
3733  * @bridge_type: type of bridge
3734  * @buff: pointer to a user supplied buffer that has the TLV
3735  * @buff_size: length of the buffer
3736  * @tlv_len: length of the TLV to be deleted
3737  * @mib_len: length of the returned LLDP MIB
3738  * @cmd_details: pointer to command details structure or NULL
3739  *
3740  * Delete the specified TLV from LLDP Local MIB for the given bridge type.
3741  * The firmware places the entire LLDP MIB in the response buffer.
3742  **/
3743 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
3744                                 u8 bridge_type, void *buff, u16 buff_size,
3745                                 u16 tlv_len, u16 *mib_len,
3746                                 struct i40e_asq_cmd_details *cmd_details)
3747 {
3748         struct i40e_aq_desc desc;
3749         struct i40e_aqc_lldp_add_tlv *cmd =
3750                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3751         enum i40e_status_code status;
3752
3753         if (buff_size == 0 || !buff)
3754                 return I40E_ERR_PARAM;
3755
3756         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
3757
3758         /* Indirect Command */
3759         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3760         if (buff_size > I40E_AQ_LARGE_BUF)
3761                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3762         desc.datalen = CPU_TO_LE16(buff_size);
3763         cmd->len = CPU_TO_LE16(tlv_len);
3764         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3765                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3766
3767         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3768         if (!status) {
3769                 if (mib_len != NULL)
3770                         *mib_len = LE16_TO_CPU(desc.datalen);
3771         }
3772
3773         return status;
3774 }
3775
3776 /**
3777  * i40e_aq_stop_lldp
3778  * @hw: pointer to the hw struct
3779  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3780  * @cmd_details: pointer to command details structure or NULL
3781  *
3782  * Stop or Shutdown the embedded LLDP Agent
3783  **/
3784 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3785                                 struct i40e_asq_cmd_details *cmd_details)
3786 {
3787         struct i40e_aq_desc desc;
3788         struct i40e_aqc_lldp_stop *cmd =
3789                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3790         enum i40e_status_code status;
3791
3792         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3793
3794         if (shutdown_agent)
3795                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3796
3797         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3798
3799         return status;
3800 }
3801
3802 /**
3803  * i40e_aq_start_lldp
3804  * @hw: pointer to the hw struct
3805  * @cmd_details: pointer to command details structure or NULL
3806  *
3807  * Start the embedded LLDP Agent on all ports.
3808  **/
3809 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
3810                                 struct i40e_asq_cmd_details *cmd_details)
3811 {
3812         struct i40e_aq_desc desc;
3813         struct i40e_aqc_lldp_start *cmd =
3814                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3815         enum i40e_status_code status;
3816
3817         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3818
3819         cmd->command = I40E_AQ_LLDP_AGENT_START;
3820
3821         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3822
3823         return status;
3824 }
3825
3826 /**
3827  * i40e_aq_get_cee_dcb_config
3828  * @hw: pointer to the hw struct
3829  * @buff: response buffer that stores CEE operational configuration
3830  * @buff_size: size of the buffer passed
3831  * @cmd_details: pointer to command details structure or NULL
3832  *
3833  * Get CEE DCBX mode operational configuration from firmware
3834  **/
3835 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3836                                 void *buff, u16 buff_size,
3837                                 struct i40e_asq_cmd_details *cmd_details)
3838 {
3839         struct i40e_aq_desc desc;
3840         enum i40e_status_code status;
3841
3842         if (buff_size == 0 || !buff)
3843                 return I40E_ERR_PARAM;
3844
3845         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3846
3847         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3848         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3849                                        cmd_details);
3850
3851         return status;
3852 }
3853
3854 /**
3855  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
3856  * @hw: pointer to the hw struct
3857  * @start_agent: True if DCBx Agent needs to be Started
3858  *                              False if DCBx Agent needs to be Stopped
3859  * @cmd_details: pointer to command details structure or NULL
3860  *
3861  * Start/Stop the embedded dcbx Agent
3862  **/
3863 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
3864                                 bool start_agent,
3865                                 struct i40e_asq_cmd_details *cmd_details)
3866 {
3867         struct i40e_aq_desc desc;
3868         struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
3869                 (struct i40e_aqc_lldp_stop_start_specific_agent *)
3870                                 &desc.params.raw;
3871         enum i40e_status_code status;
3872
3873         i40e_fill_default_direct_cmd_desc(&desc,
3874                                 i40e_aqc_opc_lldp_stop_start_spec_agent);
3875
3876         if (start_agent)
3877                 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
3878
3879         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3880
3881         return status;
3882 }
3883
3884 /**
3885  * i40e_aq_add_udp_tunnel
3886  * @hw: pointer to the hw struct
3887  * @udp_port: the UDP port to add
3888  * @header_len: length of the tunneling header length in DWords
3889  * @protocol_index: protocol index type
3890  * @filter_index: pointer to filter index
3891  * @cmd_details: pointer to command details structure or NULL
3892  **/
3893 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3894                                 u16 udp_port, u8 protocol_index,
3895                                 u8 *filter_index,
3896                                 struct i40e_asq_cmd_details *cmd_details)
3897 {
3898         struct i40e_aq_desc desc;
3899         struct i40e_aqc_add_udp_tunnel *cmd =
3900                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3901         struct i40e_aqc_del_udp_tunnel_completion *resp =
3902                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3903         enum i40e_status_code status;
3904
3905         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3906
3907         cmd->udp_port = CPU_TO_LE16(udp_port);
3908         cmd->protocol_type = protocol_index;
3909
3910         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3911
3912         if (!status && filter_index)
3913                 *filter_index = resp->index;
3914
3915         return status;
3916 }
3917
3918 /**
3919  * i40e_aq_del_udp_tunnel
3920  * @hw: pointer to the hw struct
3921  * @index: filter index
3922  * @cmd_details: pointer to command details structure or NULL
3923  **/
3924 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3925                                 struct i40e_asq_cmd_details *cmd_details)
3926 {
3927         struct i40e_aq_desc desc;
3928         struct i40e_aqc_remove_udp_tunnel *cmd =
3929                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3930         enum i40e_status_code status;
3931
3932         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3933
3934         cmd->index = index;
3935
3936         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3937
3938         return status;
3939 }
3940
3941 /**
3942  * i40e_aq_get_switch_resource_alloc (0x0204)
3943  * @hw: pointer to the hw struct
3944  * @num_entries: pointer to u8 to store the number of resource entries returned
3945  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
3946  *        to store the resource information for all resource types.  Each
3947  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
3948  * @count: size, in bytes, of the buffer provided
3949  * @cmd_details: pointer to command details structure or NULL
3950  *
3951  * Query the resources allocated to a function.
3952  **/
3953 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
3954                         u8 *num_entries,
3955                         struct i40e_aqc_switch_resource_alloc_element_resp *buf,
3956                         u16 count,
3957                         struct i40e_asq_cmd_details *cmd_details)
3958 {
3959         struct i40e_aq_desc desc;
3960         struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
3961                 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
3962         enum i40e_status_code status;
3963         u16 length = count * sizeof(*buf);
3964
3965         i40e_fill_default_direct_cmd_desc(&desc,
3966                                         i40e_aqc_opc_get_switch_resource_alloc);
3967
3968         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3969         if (length > I40E_AQ_LARGE_BUF)
3970                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3971
3972         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
3973
3974         if (!status && num_entries)
3975                 *num_entries = cmd_resp->num_entries;
3976
3977         return status;
3978 }
3979
3980 /**
3981  * i40e_aq_delete_element - Delete switch element
3982  * @hw: pointer to the hw struct
3983  * @seid: the SEID to delete from the switch
3984  * @cmd_details: pointer to command details structure or NULL
3985  *
3986  * This deletes a switch element from the switch.
3987  **/
3988 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3989                                 struct i40e_asq_cmd_details *cmd_details)
3990 {
3991         struct i40e_aq_desc desc;
3992         struct i40e_aqc_switch_seid *cmd =
3993                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3994         enum i40e_status_code status;
3995
3996         if (seid == 0)
3997                 return I40E_ERR_PARAM;
3998
3999         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4000
4001         cmd->seid = CPU_TO_LE16(seid);
4002
4003         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4004
4005         return status;
4006 }
4007
4008 /**
4009  * i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4010  * @hw: pointer to the hw struct
4011  * @flags: component flags
4012  * @mac_seid: uplink seid (MAC SEID)
4013  * @vsi_seid: connected vsi seid
4014  * @ret_seid: seid of create pv component
4015  *
4016  * This instantiates an i40e port virtualizer with specified flags.
4017  * Depending on specified flags the port virtualizer can act as a
4018  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4019  */
4020 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4021                                        u16 mac_seid, u16 vsi_seid,
4022                                        u16 *ret_seid)
4023 {
4024         struct i40e_aq_desc desc;
4025         struct i40e_aqc_add_update_pv *cmd =
4026                 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4027         struct i40e_aqc_add_update_pv_completion *resp =
4028                 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4029         enum i40e_status_code status;
4030
4031         if (vsi_seid == 0)
4032                 return I40E_ERR_PARAM;
4033
4034         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4035         cmd->command_flags = CPU_TO_LE16(flags);
4036         cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4037         cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4038
4039         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4040         if (!status && ret_seid)
4041                 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4042
4043         return status;
4044 }
4045
4046 /**
4047  * i40e_aq_add_tag - Add an S/E-tag
4048  * @hw: pointer to the hw struct
4049  * @direct_to_queue: should s-tag direct flow to a specific queue
4050  * @vsi_seid: VSI SEID to use this tag
4051  * @tag: value of the tag
4052  * @queue_num: queue number, only valid is direct_to_queue is true
4053  * @tags_used: return value, number of tags in use by this PF
4054  * @tags_free: return value, number of unallocated tags
4055  * @cmd_details: pointer to command details structure or NULL
4056  *
4057  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4058  * the number of tags allocated by the PF, and the number of unallocated
4059  * tags available.
4060  **/
4061 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4062                                 u16 vsi_seid, u16 tag, u16 queue_num,
4063                                 u16 *tags_used, u16 *tags_free,
4064                                 struct i40e_asq_cmd_details *cmd_details)
4065 {
4066         struct i40e_aq_desc desc;
4067         struct i40e_aqc_add_tag *cmd =
4068                 (struct i40e_aqc_add_tag *)&desc.params.raw;
4069         struct i40e_aqc_add_remove_tag_completion *resp =
4070                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4071         enum i40e_status_code status;
4072
4073         if (vsi_seid == 0)
4074                 return I40E_ERR_PARAM;
4075
4076         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4077
4078         cmd->seid = CPU_TO_LE16(vsi_seid);
4079         cmd->tag = CPU_TO_LE16(tag);
4080         if (direct_to_queue) {
4081                 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4082                 cmd->queue_number = CPU_TO_LE16(queue_num);
4083         }
4084
4085         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4086
4087         if (!status) {
4088                 if (tags_used != NULL)
4089                         *tags_used = LE16_TO_CPU(resp->tags_used);
4090                 if (tags_free != NULL)
4091                         *tags_free = LE16_TO_CPU(resp->tags_free);
4092         }
4093
4094         return status;
4095 }
4096
4097 /**
4098  * i40e_aq_remove_tag - Remove an S- or E-tag
4099  * @hw: pointer to the hw struct
4100  * @vsi_seid: VSI SEID this tag is associated with
4101  * @tag: value of the S-tag to delete
4102  * @tags_used: return value, number of tags in use by this PF
4103  * @tags_free: return value, number of unallocated tags
4104  * @cmd_details: pointer to command details structure or NULL
4105  *
4106  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4107  * the number of tags allocated by the PF, and the number of unallocated
4108  * tags available.
4109  **/
4110 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4111                                 u16 tag, u16 *tags_used, u16 *tags_free,
4112                                 struct i40e_asq_cmd_details *cmd_details)
4113 {
4114         struct i40e_aq_desc desc;
4115         struct i40e_aqc_remove_tag *cmd =
4116                 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4117         struct i40e_aqc_add_remove_tag_completion *resp =
4118                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4119         enum i40e_status_code status;
4120
4121         if (vsi_seid == 0)
4122                 return I40E_ERR_PARAM;
4123
4124         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4125
4126         cmd->seid = CPU_TO_LE16(vsi_seid);
4127         cmd->tag = CPU_TO_LE16(tag);
4128
4129         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4130
4131         if (!status) {
4132                 if (tags_used != NULL)
4133                         *tags_used = LE16_TO_CPU(resp->tags_used);
4134                 if (tags_free != NULL)
4135                         *tags_free = LE16_TO_CPU(resp->tags_free);
4136         }
4137
4138         return status;
4139 }
4140
4141 /**
4142  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4143  * @hw: pointer to the hw struct
4144  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4145  * @etag: value of E-tag to add
4146  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4147  * @buf: address of indirect buffer
4148  * @tags_used: return value, number of E-tags in use by this port
4149  * @tags_free: return value, number of unallocated M-tags
4150  * @cmd_details: pointer to command details structure or NULL
4151  *
4152  * This associates a multicast E-tag to a port virtualizer.  It will return
4153  * the number of tags allocated by the PF, and the number of unallocated
4154  * tags available.
4155  *
4156  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4157  * num_tags_in_buf long.
4158  **/
4159 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4160                                 u16 etag, u8 num_tags_in_buf, void *buf,
4161                                 u16 *tags_used, u16 *tags_free,
4162                                 struct i40e_asq_cmd_details *cmd_details)
4163 {
4164         struct i40e_aq_desc desc;
4165         struct i40e_aqc_add_remove_mcast_etag *cmd =
4166                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4167         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4168            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4169         enum i40e_status_code status;
4170         u16 length = sizeof(u16) * num_tags_in_buf;
4171
4172         if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4173                 return I40E_ERR_PARAM;
4174
4175         i40e_fill_default_direct_cmd_desc(&desc,
4176                                           i40e_aqc_opc_add_multicast_etag);
4177
4178         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4179         cmd->etag = CPU_TO_LE16(etag);
4180         cmd->num_unicast_etags = num_tags_in_buf;
4181
4182         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4183         if (length > I40E_AQ_LARGE_BUF)
4184                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4185
4186         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4187
4188         if (!status) {
4189                 if (tags_used != NULL)
4190                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4191                 if (tags_free != NULL)
4192                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4193         }
4194
4195         return status;
4196 }
4197
4198 /**
4199  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4200  * @hw: pointer to the hw struct
4201  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4202  * @etag: value of the E-tag to remove
4203  * @tags_used: return value, number of tags in use by this port
4204  * @tags_free: return value, number of unallocated tags
4205  * @cmd_details: pointer to command details structure or NULL
4206  *
4207  * This deletes an E-tag from the port virtualizer.  It will return
4208  * the number of tags allocated by the port, and the number of unallocated
4209  * tags available.
4210  **/
4211 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4212                                 u16 etag, u16 *tags_used, u16 *tags_free,
4213                                 struct i40e_asq_cmd_details *cmd_details)
4214 {
4215         struct i40e_aq_desc desc;
4216         struct i40e_aqc_add_remove_mcast_etag *cmd =
4217                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4218         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4219            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4220         enum i40e_status_code status;
4221
4222
4223         if (pv_seid == 0)
4224                 return I40E_ERR_PARAM;
4225
4226         i40e_fill_default_direct_cmd_desc(&desc,
4227                                           i40e_aqc_opc_remove_multicast_etag);
4228
4229         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4230         cmd->etag = CPU_TO_LE16(etag);
4231
4232         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4233
4234         if (!status) {
4235                 if (tags_used != NULL)
4236                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4237                 if (tags_free != NULL)
4238                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4239         }
4240
4241         return status;
4242 }
4243
4244 /**
4245  * i40e_aq_update_tag - Update an S/E-tag
4246  * @hw: pointer to the hw struct
4247  * @vsi_seid: VSI SEID using this S-tag
4248  * @old_tag: old tag value
4249  * @new_tag: new tag value
4250  * @tags_used: return value, number of tags in use by this PF
4251  * @tags_free: return value, number of unallocated tags
4252  * @cmd_details: pointer to command details structure or NULL
4253  *
4254  * This updates the value of the tag currently attached to this VSI
4255  * in the switch complex.  It will return the number of tags allocated
4256  * by the PF, and the number of unallocated tags available.
4257  **/
4258 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4259                                 u16 old_tag, u16 new_tag, u16 *tags_used,
4260                                 u16 *tags_free,
4261                                 struct i40e_asq_cmd_details *cmd_details)
4262 {
4263         struct i40e_aq_desc desc;
4264         struct i40e_aqc_update_tag *cmd =
4265                 (struct i40e_aqc_update_tag *)&desc.params.raw;
4266         struct i40e_aqc_update_tag_completion *resp =
4267                 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4268         enum i40e_status_code status;
4269
4270         if (vsi_seid == 0)
4271                 return I40E_ERR_PARAM;
4272
4273         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4274
4275         cmd->seid = CPU_TO_LE16(vsi_seid);
4276         cmd->old_tag = CPU_TO_LE16(old_tag);
4277         cmd->new_tag = CPU_TO_LE16(new_tag);
4278
4279         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4280
4281         if (!status) {
4282                 if (tags_used != NULL)
4283                         *tags_used = LE16_TO_CPU(resp->tags_used);
4284                 if (tags_free != NULL)
4285                         *tags_free = LE16_TO_CPU(resp->tags_free);
4286         }
4287
4288         return status;
4289 }
4290
4291 /**
4292  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4293  * @hw: pointer to the hw struct
4294  * @tcmap: TC map for request/release any ignore PFC condition
4295  * @request: request or release ignore PFC condition
4296  * @tcmap_ret: return TCs for which PFC is currently ignored
4297  * @cmd_details: pointer to command details structure or NULL
4298  *
4299  * This sends out request/release to ignore PFC condition for a TC.
4300  * It will return the TCs for which PFC is currently ignored.
4301  **/
4302 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4303                                 bool request, u8 *tcmap_ret,
4304                                 struct i40e_asq_cmd_details *cmd_details)
4305 {
4306         struct i40e_aq_desc desc;
4307         struct i40e_aqc_pfc_ignore *cmd_resp =
4308                 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4309         enum i40e_status_code status;
4310
4311         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4312
4313         if (request)
4314                 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4315
4316         cmd_resp->tc_bitmap = tcmap;
4317
4318         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4319
4320         if (!status) {
4321                 if (tcmap_ret != NULL)
4322                         *tcmap_ret = cmd_resp->tc_bitmap;
4323         }
4324
4325         return status;
4326 }
4327
4328 /**
4329  * i40e_aq_dcb_updated - DCB Updated Command
4330  * @hw: pointer to the hw struct
4331  * @cmd_details: pointer to command details structure or NULL
4332  *
4333  * When LLDP is handled in PF this command is used by the PF
4334  * to notify EMP that a DCB setting is modified.
4335  * When LLDP is handled in EMP this command is used by the PF
4336  * to notify EMP whenever one of the following parameters get
4337  * modified:
4338  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4339  *   - PCIRTT in PRTDCB_GENC.PCIRTT
4340  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4341  * EMP will return when the shared RPB settings have been
4342  * recomputed and modified. The retval field in the descriptor
4343  * will be set to 0 when RPB is modified.
4344  **/
4345 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4346                                 struct i40e_asq_cmd_details *cmd_details)
4347 {
4348         struct i40e_aq_desc desc;
4349         enum i40e_status_code status;
4350
4351         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4352
4353         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4354
4355         return status;
4356 }
4357
4358 /**
4359  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4360  * @hw: pointer to the hw struct
4361  * @seid: defines the SEID of the switch for which the stats are requested
4362  * @vlan_id: the VLAN ID for which the statistics are requested
4363  * @stat_index: index of the statistics counters block assigned to this VLAN
4364  * @cmd_details: pointer to command details structure or NULL
4365  *
4366  * XL710 supports 128 smonVlanStats counters.This command is used to
4367  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4368  * switch.
4369  **/
4370 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4371                                 u16 vlan_id, u16 *stat_index,
4372                                 struct i40e_asq_cmd_details *cmd_details)
4373 {
4374         struct i40e_aq_desc desc;
4375         struct i40e_aqc_add_remove_statistics *cmd_resp =
4376                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4377         enum i40e_status_code status;
4378
4379         if ((seid == 0) || (stat_index == NULL))
4380                 return I40E_ERR_PARAM;
4381
4382         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4383
4384         cmd_resp->seid = CPU_TO_LE16(seid);
4385         cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4386
4387         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4388
4389         if (!status && stat_index)
4390                 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4391
4392         return status;
4393 }
4394
4395 /**
4396  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4397  * @hw: pointer to the hw struct
4398  * @seid: defines the SEID of the switch for which the stats are requested
4399  * @vlan_id: the VLAN ID for which the statistics are requested
4400  * @stat_index: index of the statistics counters block assigned to this VLAN
4401  * @cmd_details: pointer to command details structure or NULL
4402  *
4403  * XL710 supports 128 smonVlanStats counters.This command is used to
4404  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4405  * switch.
4406  **/
4407 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4408                                 u16 vlan_id, u16 stat_index,
4409                                 struct i40e_asq_cmd_details *cmd_details)
4410 {
4411         struct i40e_aq_desc desc;
4412         struct i40e_aqc_add_remove_statistics *cmd =
4413                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4414         enum i40e_status_code status;
4415
4416         if (seid == 0)
4417                 return I40E_ERR_PARAM;
4418
4419         i40e_fill_default_direct_cmd_desc(&desc,
4420                                           i40e_aqc_opc_remove_statistics);
4421
4422         cmd->seid = CPU_TO_LE16(seid);
4423         cmd->vlan  = CPU_TO_LE16(vlan_id);
4424         cmd->stat_index = CPU_TO_LE16(stat_index);
4425
4426         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4427
4428         return status;
4429 }
4430
4431 /**
4432  * i40e_aq_set_port_parameters - set physical port parameters.
4433  * @hw: pointer to the hw struct
4434  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4435  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4436  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4437  * @double_vlan: if set double VLAN is enabled
4438  * @cmd_details: pointer to command details structure or NULL
4439  **/
4440 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4441                                 u16 bad_frame_vsi, bool save_bad_pac,
4442                                 bool pad_short_pac, bool double_vlan,
4443                                 struct i40e_asq_cmd_details *cmd_details)
4444 {
4445         struct i40e_aqc_set_port_parameters *cmd;
4446         enum i40e_status_code status;
4447         struct i40e_aq_desc desc;
4448         u16 command_flags = 0;
4449
4450         cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4451
4452         i40e_fill_default_direct_cmd_desc(&desc,
4453                                           i40e_aqc_opc_set_port_parameters);
4454
4455         cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4456         if (save_bad_pac)
4457                 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4458         if (pad_short_pac)
4459                 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4460         if (double_vlan)
4461                 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4462         cmd->command_flags = CPU_TO_LE16(command_flags);
4463
4464         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4465
4466         return status;
4467 }
4468
4469 /**
4470  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
4471  * @hw: pointer to the hw struct
4472  * @seid: seid for the physical port/switching component/vsi
4473  * @buff: Indirect buffer to hold data parameters and response
4474  * @buff_size: Indirect buffer size
4475  * @opcode: Tx scheduler AQ command opcode
4476  * @cmd_details: pointer to command details structure or NULL
4477  *
4478  * Generic command handler for Tx scheduler AQ commands
4479  **/
4480 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
4481                                 void *buff, u16 buff_size,
4482                                  enum i40e_admin_queue_opc opcode,
4483                                 struct i40e_asq_cmd_details *cmd_details)
4484 {
4485         struct i40e_aq_desc desc;
4486         struct i40e_aqc_tx_sched_ind *cmd =
4487                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4488         enum i40e_status_code status;
4489         bool cmd_param_flag = false;
4490
4491         switch (opcode) {
4492         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
4493         case i40e_aqc_opc_configure_vsi_tc_bw:
4494         case i40e_aqc_opc_enable_switching_comp_ets:
4495         case i40e_aqc_opc_modify_switching_comp_ets:
4496         case i40e_aqc_opc_disable_switching_comp_ets:
4497         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
4498         case i40e_aqc_opc_configure_switching_comp_bw_config:
4499                 cmd_param_flag = true;
4500                 break;
4501         case i40e_aqc_opc_query_vsi_bw_config:
4502         case i40e_aqc_opc_query_vsi_ets_sla_config:
4503         case i40e_aqc_opc_query_switching_comp_ets_config:
4504         case i40e_aqc_opc_query_port_ets_config:
4505         case i40e_aqc_opc_query_switching_comp_bw_config:
4506                 cmd_param_flag = false;
4507                 break;
4508         default:
4509                 return I40E_ERR_PARAM;
4510         }
4511
4512         i40e_fill_default_direct_cmd_desc(&desc, opcode);
4513
4514         /* Indirect command */
4515         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4516         if (cmd_param_flag)
4517                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4518         if (buff_size > I40E_AQ_LARGE_BUF)
4519                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4520
4521         desc.datalen = CPU_TO_LE16(buff_size);
4522
4523         cmd->vsi_seid = CPU_TO_LE16(seid);
4524
4525         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4526
4527         return status;
4528 }
4529
4530 /**
4531  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
4532  * @hw: pointer to the hw struct
4533  * @seid: VSI seid
4534  * @credit: BW limit credits (0 = disabled)
4535  * @max_credit: Max BW limit credits
4536  * @cmd_details: pointer to command details structure or NULL
4537  **/
4538 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
4539                                 u16 seid, u16 credit, u8 max_credit,
4540                                 struct i40e_asq_cmd_details *cmd_details)
4541 {
4542         struct i40e_aq_desc desc;
4543         struct i40e_aqc_configure_vsi_bw_limit *cmd =
4544                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
4545         enum i40e_status_code status;
4546
4547         i40e_fill_default_direct_cmd_desc(&desc,
4548                                           i40e_aqc_opc_configure_vsi_bw_limit);
4549
4550         cmd->vsi_seid = CPU_TO_LE16(seid);
4551         cmd->credit = CPU_TO_LE16(credit);
4552         cmd->max_credit = max_credit;
4553
4554         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4555
4556         return status;
4557 }
4558
4559 /**
4560  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
4561  * @hw: pointer to the hw struct
4562  * @seid: switching component seid
4563  * @credit: BW limit credits (0 = disabled)
4564  * @max_bw: Max BW limit credits
4565  * @cmd_details: pointer to command details structure or NULL
4566  **/
4567 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
4568                                 u16 seid, u16 credit, u8 max_bw,
4569                                 struct i40e_asq_cmd_details *cmd_details)
4570 {
4571         struct i40e_aq_desc desc;
4572         struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
4573           (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
4574         enum i40e_status_code status;
4575
4576         i40e_fill_default_direct_cmd_desc(&desc,
4577                                 i40e_aqc_opc_configure_switching_comp_bw_limit);
4578
4579         cmd->seid = CPU_TO_LE16(seid);
4580         cmd->credit = CPU_TO_LE16(credit);
4581         cmd->max_bw = max_bw;
4582
4583         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4584
4585         return status;
4586 }
4587
4588 /**
4589  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
4590  * @hw: pointer to the hw struct
4591  * @seid: VSI seid
4592  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4593  * @cmd_details: pointer to command details structure or NULL
4594  **/
4595 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
4596                         u16 seid,
4597                         struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
4598                         struct i40e_asq_cmd_details *cmd_details)
4599 {
4600         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4601                                     i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
4602                                     cmd_details);
4603 }
4604
4605 /**
4606  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
4607  * @hw: pointer to the hw struct
4608  * @seid: VSI seid
4609  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
4610  * @cmd_details: pointer to command details structure or NULL
4611  **/
4612 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
4613                         u16 seid,
4614                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
4615                         struct i40e_asq_cmd_details *cmd_details)
4616 {
4617         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4618                                     i40e_aqc_opc_configure_vsi_tc_bw,
4619                                     cmd_details);
4620 }
4621
4622 /**
4623  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
4624  * @hw: pointer to the hw struct
4625  * @seid: seid of the switching component connected to Physical Port
4626  * @ets_data: Buffer holding ETS parameters
4627  * @cmd_details: pointer to command details structure or NULL
4628  **/
4629 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
4630                 u16 seid,
4631                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
4632                 enum i40e_admin_queue_opc opcode,
4633                 struct i40e_asq_cmd_details *cmd_details)
4634 {
4635         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
4636                                     sizeof(*ets_data), opcode, cmd_details);
4637 }
4638
4639 /**
4640  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
4641  * @hw: pointer to the hw struct
4642  * @seid: seid of the switching component
4643  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
4644  * @cmd_details: pointer to command details structure or NULL
4645  **/
4646 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
4647         u16 seid,
4648         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
4649         struct i40e_asq_cmd_details *cmd_details)
4650 {
4651         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4652                             i40e_aqc_opc_configure_switching_comp_bw_config,
4653                             cmd_details);
4654 }
4655
4656 /**
4657  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
4658  * @hw: pointer to the hw struct
4659  * @seid: seid of the switching component
4660  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4661  * @cmd_details: pointer to command details structure or NULL
4662  **/
4663 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
4664         struct i40e_hw *hw, u16 seid,
4665         struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
4666         struct i40e_asq_cmd_details *cmd_details)
4667 {
4668         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4669                             i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
4670                             cmd_details);
4671 }
4672
4673 /**
4674  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
4675  * @hw: pointer to the hw struct
4676  * @seid: seid of the VSI
4677  * @bw_data: Buffer to hold VSI BW configuration
4678  * @cmd_details: pointer to command details structure or NULL
4679  **/
4680 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
4681                         u16 seid,
4682                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
4683                         struct i40e_asq_cmd_details *cmd_details)
4684 {
4685         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4686                                     i40e_aqc_opc_query_vsi_bw_config,
4687                                     cmd_details);
4688 }
4689
4690 /**
4691  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
4692  * @hw: pointer to the hw struct
4693  * @seid: seid of the VSI
4694  * @bw_data: Buffer to hold VSI BW configuration per TC
4695  * @cmd_details: pointer to command details structure or NULL
4696  **/
4697 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
4698                         u16 seid,
4699                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
4700                         struct i40e_asq_cmd_details *cmd_details)
4701 {
4702         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4703                                     i40e_aqc_opc_query_vsi_ets_sla_config,
4704                                     cmd_details);
4705 }
4706
4707 /**
4708  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
4709  * @hw: pointer to the hw struct
4710  * @seid: seid of the switching component
4711  * @bw_data: Buffer to hold switching component's per TC BW config
4712  * @cmd_details: pointer to command details structure or NULL
4713  **/
4714 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
4715                 u16 seid,
4716                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
4717                 struct i40e_asq_cmd_details *cmd_details)
4718 {
4719         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4720                                    i40e_aqc_opc_query_switching_comp_ets_config,
4721                                    cmd_details);
4722 }
4723
4724 /**
4725  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
4726  * @hw: pointer to the hw struct
4727  * @seid: seid of the VSI or switching component connected to Physical Port
4728  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
4729  * @cmd_details: pointer to command details structure or NULL
4730  **/
4731 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
4732                         u16 seid,
4733                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
4734                         struct i40e_asq_cmd_details *cmd_details)
4735 {
4736         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4737                                     i40e_aqc_opc_query_port_ets_config,
4738                                     cmd_details);
4739 }
4740
4741 /**
4742  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
4743  * @hw: pointer to the hw struct
4744  * @seid: seid of the switching component
4745  * @bw_data: Buffer to hold switching component's BW configuration
4746  * @cmd_details: pointer to command details structure or NULL
4747  **/
4748 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
4749                 u16 seid,
4750                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
4751                 struct i40e_asq_cmd_details *cmd_details)
4752 {
4753         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4754                                     i40e_aqc_opc_query_switching_comp_bw_config,
4755                                     cmd_details);
4756 }
4757
4758 /**
4759  * i40e_validate_filter_settings
4760  * @hw: pointer to the hardware structure
4761  * @settings: Filter control settings
4762  *
4763  * Check and validate the filter control settings passed.
4764  * The function checks for the valid filter/context sizes being
4765  * passed for FCoE and PE.
4766  *
4767  * Returns I40E_SUCCESS if the values passed are valid and within
4768  * range else returns an error.
4769  **/
4770 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
4771                                 struct i40e_filter_control_settings *settings)
4772 {
4773         u32 fcoe_cntx_size, fcoe_filt_size;
4774         u32 pe_cntx_size, pe_filt_size;
4775         u32 fcoe_fmax;
4776
4777         u32 val;
4778
4779         /* Validate FCoE settings passed */
4780         switch (settings->fcoe_filt_num) {
4781         case I40E_HASH_FILTER_SIZE_1K:
4782         case I40E_HASH_FILTER_SIZE_2K:
4783         case I40E_HASH_FILTER_SIZE_4K:
4784         case I40E_HASH_FILTER_SIZE_8K:
4785         case I40E_HASH_FILTER_SIZE_16K:
4786         case I40E_HASH_FILTER_SIZE_32K:
4787                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4788                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
4789                 break;
4790         default:
4791                 return I40E_ERR_PARAM;
4792         }
4793
4794         switch (settings->fcoe_cntx_num) {
4795         case I40E_DMA_CNTX_SIZE_512:
4796         case I40E_DMA_CNTX_SIZE_1K:
4797         case I40E_DMA_CNTX_SIZE_2K:
4798         case I40E_DMA_CNTX_SIZE_4K:
4799                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4800                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
4801                 break;
4802         default:
4803                 return I40E_ERR_PARAM;
4804         }
4805
4806         /* Validate PE settings passed */
4807         switch (settings->pe_filt_num) {
4808         case I40E_HASH_FILTER_SIZE_1K:
4809         case I40E_HASH_FILTER_SIZE_2K:
4810         case I40E_HASH_FILTER_SIZE_4K:
4811         case I40E_HASH_FILTER_SIZE_8K:
4812         case I40E_HASH_FILTER_SIZE_16K:
4813         case I40E_HASH_FILTER_SIZE_32K:
4814         case I40E_HASH_FILTER_SIZE_64K:
4815         case I40E_HASH_FILTER_SIZE_128K:
4816         case I40E_HASH_FILTER_SIZE_256K:
4817         case I40E_HASH_FILTER_SIZE_512K:
4818         case I40E_HASH_FILTER_SIZE_1M:
4819                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4820                 pe_filt_size <<= (u32)settings->pe_filt_num;
4821                 break;
4822         default:
4823                 return I40E_ERR_PARAM;
4824         }
4825
4826         switch (settings->pe_cntx_num) {
4827         case I40E_DMA_CNTX_SIZE_512:
4828         case I40E_DMA_CNTX_SIZE_1K:
4829         case I40E_DMA_CNTX_SIZE_2K:
4830         case I40E_DMA_CNTX_SIZE_4K:
4831         case I40E_DMA_CNTX_SIZE_8K:
4832         case I40E_DMA_CNTX_SIZE_16K:
4833         case I40E_DMA_CNTX_SIZE_32K:
4834         case I40E_DMA_CNTX_SIZE_64K:
4835         case I40E_DMA_CNTX_SIZE_128K:
4836         case I40E_DMA_CNTX_SIZE_256K:
4837                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4838                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
4839                 break;
4840         default:
4841                 return I40E_ERR_PARAM;
4842         }
4843
4844         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
4845         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
4846         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
4847                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
4848         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
4849                 return I40E_ERR_INVALID_SIZE;
4850
4851         return I40E_SUCCESS;
4852 }
4853
4854 /**
4855  * i40e_set_filter_control
4856  * @hw: pointer to the hardware structure
4857  * @settings: Filter control settings
4858  *
4859  * Set the Queue Filters for PE/FCoE and enable filters required
4860  * for a single PF. It is expected that these settings are programmed
4861  * at the driver initialization time.
4862  **/
4863 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
4864                                 struct i40e_filter_control_settings *settings)
4865 {
4866         enum i40e_status_code ret = I40E_SUCCESS;
4867         u32 hash_lut_size = 0;
4868         u32 val;
4869
4870         if (!settings)
4871                 return I40E_ERR_PARAM;
4872
4873         /* Validate the input settings */
4874         ret = i40e_validate_filter_settings(hw, settings);
4875         if (ret)
4876                 return ret;
4877
4878         /* Read the PF Queue Filter control register */
4879         val = rd32(hw, I40E_PFQF_CTL_0);
4880
4881         /* Program required PE hash buckets for the PF */
4882         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
4883         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
4884                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
4885         /* Program required PE contexts for the PF */
4886         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
4887         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
4888                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
4889
4890         /* Program required FCoE hash buckets for the PF */
4891         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4892         val |= ((u32)settings->fcoe_filt_num <<
4893                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
4894                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4895         /* Program required FCoE DDP contexts for the PF */
4896         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4897         val |= ((u32)settings->fcoe_cntx_num <<
4898                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
4899                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4900
4901         /* Program Hash LUT size for the PF */
4902         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4903         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
4904                 hash_lut_size = 1;
4905         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
4906                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4907
4908         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
4909         if (settings->enable_fdir)
4910                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
4911         if (settings->enable_ethtype)
4912                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
4913         if (settings->enable_macvlan)
4914                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
4915
4916         wr32(hw, I40E_PFQF_CTL_0, val);
4917
4918         return I40E_SUCCESS;
4919 }
4920
4921 /**
4922  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
4923  * @hw: pointer to the hw struct
4924  * @mac_addr: MAC address to use in the filter
4925  * @ethtype: Ethertype to use in the filter
4926  * @flags: Flags that needs to be applied to the filter
4927  * @vsi_seid: seid of the control VSI
4928  * @queue: VSI queue number to send the packet to
4929  * @is_add: Add control packet filter if True else remove
4930  * @stats: Structure to hold information on control filter counts
4931  * @cmd_details: pointer to command details structure or NULL
4932  *
4933  * This command will Add or Remove control packet filter for a control VSI.
4934  * In return it will update the total number of perfect filter count in
4935  * the stats member.
4936  **/
4937 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
4938                                 u8 *mac_addr, u16 ethtype, u16 flags,
4939                                 u16 vsi_seid, u16 queue, bool is_add,
4940                                 struct i40e_control_filter_stats *stats,
4941                                 struct i40e_asq_cmd_details *cmd_details)
4942 {
4943         struct i40e_aq_desc desc;
4944         struct i40e_aqc_add_remove_control_packet_filter *cmd =
4945                 (struct i40e_aqc_add_remove_control_packet_filter *)
4946                 &desc.params.raw;
4947         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
4948                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
4949                 &desc.params.raw;
4950         enum i40e_status_code status;
4951
4952         if (vsi_seid == 0)
4953                 return I40E_ERR_PARAM;
4954
4955         if (is_add) {
4956                 i40e_fill_default_direct_cmd_desc(&desc,
4957                                 i40e_aqc_opc_add_control_packet_filter);
4958                 cmd->queue = CPU_TO_LE16(queue);
4959         } else {
4960                 i40e_fill_default_direct_cmd_desc(&desc,
4961                                 i40e_aqc_opc_remove_control_packet_filter);
4962         }
4963
4964         if (mac_addr)
4965                 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
4966                             I40E_NONDMA_TO_NONDMA);
4967
4968         cmd->etype = CPU_TO_LE16(ethtype);
4969         cmd->flags = CPU_TO_LE16(flags);
4970         cmd->seid = CPU_TO_LE16(vsi_seid);
4971
4972         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4973
4974         if (!status && stats) {
4975                 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
4976                 stats->etype_used = LE16_TO_CPU(resp->etype_used);
4977                 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
4978                 stats->etype_free = LE16_TO_CPU(resp->etype_free);
4979         }
4980
4981         return status;
4982 }
4983
4984 /**
4985  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
4986  * @hw: pointer to the hw struct
4987  * @seid: VSI seid to add ethertype filter from
4988  **/
4989 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
4990 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
4991                                                     u16 seid)
4992 {
4993         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
4994                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
4995                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
4996         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
4997         enum i40e_status_code status;
4998
4999         status = i40e_aq_add_rem_control_packet_filter(hw, 0, ethtype, flag,
5000                                                        seid, 0, true, NULL,
5001                                                        NULL);
5002         if (status)
5003                 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5004 }
5005
5006 /**
5007  * i40e_aq_add_cloud_filters
5008  * @hw: pointer to the hardware structure
5009  * @seid: VSI seid to add cloud filters from
5010  * @filters: Buffer which contains the filters to be added
5011  * @filter_count: number of filters contained in the buffer
5012  *
5013  * Set the cloud filters for a given VSI.  The contents of the
5014  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5015  * in by the caller of the function.
5016  *
5017  **/
5018 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5019         u16 seid,
5020         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5021         u8 filter_count)
5022 {
5023         struct i40e_aq_desc desc;
5024         struct i40e_aqc_add_remove_cloud_filters *cmd =
5025         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5026         u16 buff_len;
5027         enum i40e_status_code status;
5028
5029         i40e_fill_default_direct_cmd_desc(&desc,
5030                                           i40e_aqc_opc_add_cloud_filters);
5031
5032         buff_len = filter_count * sizeof(*filters);
5033         desc.datalen = CPU_TO_LE16(buff_len);
5034         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5035         cmd->num_filters = filter_count;
5036         cmd->seid = CPU_TO_LE16(seid);
5037
5038         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5039
5040         return status;
5041 }
5042
5043 /**
5044  * i40e_aq_remove_cloud_filters
5045  * @hw: pointer to the hardware structure
5046  * @seid: VSI seid to remove cloud filters from
5047  * @filters: Buffer which contains the filters to be removed
5048  * @filter_count: number of filters contained in the buffer
5049  *
5050  * Remove the cloud filters for a given VSI.  The contents of the
5051  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5052  * in by the caller of the function.
5053  *
5054  **/
5055 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5056                 u16 seid,
5057                 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5058                 u8 filter_count)
5059 {
5060         struct i40e_aq_desc desc;
5061         struct i40e_aqc_add_remove_cloud_filters *cmd =
5062         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5063         enum i40e_status_code status;
5064         u16 buff_len;
5065
5066         i40e_fill_default_direct_cmd_desc(&desc,
5067                                           i40e_aqc_opc_remove_cloud_filters);
5068
5069         buff_len = filter_count * sizeof(*filters);
5070         desc.datalen = CPU_TO_LE16(buff_len);
5071         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5072         cmd->num_filters = filter_count;
5073         cmd->seid = CPU_TO_LE16(seid);
5074
5075         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5076
5077         return status;
5078 }
5079
5080 /**
5081  * i40e_aq_alternate_write
5082  * @hw: pointer to the hardware structure
5083  * @reg_addr0: address of first dword to be read
5084  * @reg_val0: value to be written under 'reg_addr0'
5085  * @reg_addr1: address of second dword to be read
5086  * @reg_val1: value to be written under 'reg_addr1'
5087  *
5088  * Write one or two dwords to alternate structure. Fields are indicated
5089  * by 'reg_addr0' and 'reg_addr1' register numbers.
5090  *
5091  **/
5092 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5093                                 u32 reg_addr0, u32 reg_val0,
5094                                 u32 reg_addr1, u32 reg_val1)
5095 {
5096         struct i40e_aq_desc desc;
5097         struct i40e_aqc_alternate_write *cmd_resp =
5098                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5099         enum i40e_status_code status;
5100
5101         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5102         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5103         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5104         cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5105         cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5106
5107         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5108
5109         return status;
5110 }
5111
5112 /**
5113  * i40e_aq_alternate_write_indirect
5114  * @hw: pointer to the hardware structure
5115  * @addr: address of a first register to be modified
5116  * @dw_count: number of alternate structure fields to write
5117  * @buffer: pointer to the command buffer
5118  *
5119  * Write 'dw_count' dwords from 'buffer' to alternate structure
5120  * starting at 'addr'.
5121  *
5122  **/
5123 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5124                                 u32 addr, u32 dw_count, void *buffer)
5125 {
5126         struct i40e_aq_desc desc;
5127         struct i40e_aqc_alternate_ind_write *cmd_resp =
5128                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5129         enum i40e_status_code status;
5130
5131         if (buffer == NULL)
5132                 return I40E_ERR_PARAM;
5133
5134         /* Indirect command */
5135         i40e_fill_default_direct_cmd_desc(&desc,
5136                                          i40e_aqc_opc_alternate_write_indirect);
5137
5138         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5139         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5140         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5141                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5142
5143         cmd_resp->address = CPU_TO_LE32(addr);
5144         cmd_resp->length = CPU_TO_LE32(dw_count);
5145
5146         status = i40e_asq_send_command(hw, &desc, buffer,
5147                                        I40E_LO_DWORD(4*dw_count), NULL);
5148
5149         return status;
5150 }
5151
5152 /**
5153  * i40e_aq_alternate_read
5154  * @hw: pointer to the hardware structure
5155  * @reg_addr0: address of first dword to be read
5156  * @reg_val0: pointer for data read from 'reg_addr0'
5157  * @reg_addr1: address of second dword to be read
5158  * @reg_val1: pointer for data read from 'reg_addr1'
5159  *
5160  * Read one or two dwords from alternate structure. Fields are indicated
5161  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5162  * is not passed then only register at 'reg_addr0' is read.
5163  *
5164  **/
5165 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5166                                 u32 reg_addr0, u32 *reg_val0,
5167                                 u32 reg_addr1, u32 *reg_val1)
5168 {
5169         struct i40e_aq_desc desc;
5170         struct i40e_aqc_alternate_write *cmd_resp =
5171                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5172         enum i40e_status_code status;
5173
5174         if (reg_val0 == NULL)
5175                 return I40E_ERR_PARAM;
5176
5177         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5178         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5179         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5180
5181         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5182
5183         if (status == I40E_SUCCESS) {
5184                 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5185
5186                 if (reg_val1 != NULL)
5187                         *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5188         }
5189
5190         return status;
5191 }
5192
5193 /**
5194  * i40e_aq_alternate_read_indirect
5195  * @hw: pointer to the hardware structure
5196  * @addr: address of the alternate structure field
5197  * @dw_count: number of alternate structure fields to read
5198  * @buffer: pointer to the command buffer
5199  *
5200  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5201  * place them in 'buffer'. The buffer should be allocated by caller.
5202  *
5203  **/
5204 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5205                                 u32 addr, u32 dw_count, void *buffer)
5206 {
5207         struct i40e_aq_desc desc;
5208         struct i40e_aqc_alternate_ind_write *cmd_resp =
5209                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5210         enum i40e_status_code status;
5211
5212         if (buffer == NULL)
5213                 return I40E_ERR_PARAM;
5214
5215         /* Indirect command */
5216         i40e_fill_default_direct_cmd_desc(&desc,
5217                 i40e_aqc_opc_alternate_read_indirect);
5218
5219         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5220         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5221         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5222                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5223
5224         cmd_resp->address = CPU_TO_LE32(addr);
5225         cmd_resp->length = CPU_TO_LE32(dw_count);
5226
5227         status = i40e_asq_send_command(hw, &desc, buffer,
5228                                        I40E_LO_DWORD(4*dw_count), NULL);
5229
5230         return status;
5231 }
5232
5233 /**
5234  *  i40e_aq_alternate_clear
5235  *  @hw: pointer to the HW structure.
5236  *
5237  *  Clear the alternate structures of the port from which the function
5238  *  is called.
5239  *
5240  **/
5241 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5242 {
5243         struct i40e_aq_desc desc;
5244         enum i40e_status_code status;
5245
5246         i40e_fill_default_direct_cmd_desc(&desc,
5247                                           i40e_aqc_opc_alternate_clear_port);
5248
5249         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5250
5251         return status;
5252 }
5253
5254 /**
5255  *  i40e_aq_alternate_write_done
5256  *  @hw: pointer to the HW structure.
5257  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
5258  *  @reset_needed: indicates the SW should trigger GLOBAL reset
5259  *
5260  *  Indicates to the FW that alternate structures have been changed.
5261  *
5262  **/
5263 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
5264                 u8 bios_mode, bool *reset_needed)
5265 {
5266         struct i40e_aq_desc desc;
5267         struct i40e_aqc_alternate_write_done *cmd =
5268                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5269         enum i40e_status_code status;
5270
5271         if (reset_needed == NULL)
5272                 return I40E_ERR_PARAM;
5273
5274         i40e_fill_default_direct_cmd_desc(&desc,
5275                                           i40e_aqc_opc_alternate_write_done);
5276
5277         cmd->cmd_flags = CPU_TO_LE16(bios_mode);
5278
5279         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5280         if (!status && reset_needed)
5281                 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
5282                                  I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
5283
5284         return status;
5285 }
5286
5287 /**
5288  *  i40e_aq_set_oem_mode
5289  *  @hw: pointer to the HW structure.
5290  *  @oem_mode: the OEM mode to be used
5291  *
5292  *  Sets the device to a specific operating mode. Currently the only supported
5293  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
5294  *
5295  **/
5296 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
5297                 u8 oem_mode)
5298 {
5299         struct i40e_aq_desc desc;
5300         struct i40e_aqc_alternate_write_done *cmd =
5301                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5302         enum i40e_status_code status;
5303
5304         i40e_fill_default_direct_cmd_desc(&desc,
5305                                           i40e_aqc_opc_alternate_set_mode);
5306
5307         cmd->cmd_flags = CPU_TO_LE16(oem_mode);
5308
5309         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5310
5311         return status;
5312 }
5313
5314 /**
5315  * i40e_aq_resume_port_tx
5316  * @hw: pointer to the hardware structure
5317  * @cmd_details: pointer to command details structure or NULL
5318  *
5319  * Resume port's Tx traffic
5320  **/
5321 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
5322                                 struct i40e_asq_cmd_details *cmd_details)
5323 {
5324         struct i40e_aq_desc desc;
5325         enum i40e_status_code status;
5326
5327         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
5328
5329         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5330
5331         return status;
5332 }
5333
5334 /**
5335  * i40e_set_pci_config_data - store PCI bus info
5336  * @hw: pointer to hardware structure
5337  * @link_status: the link status word from PCI config space
5338  *
5339  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
5340  **/
5341 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
5342 {
5343         hw->bus.type = i40e_bus_type_pci_express;
5344
5345         switch (link_status & I40E_PCI_LINK_WIDTH) {
5346         case I40E_PCI_LINK_WIDTH_1:
5347                 hw->bus.width = i40e_bus_width_pcie_x1;
5348                 break;
5349         case I40E_PCI_LINK_WIDTH_2:
5350                 hw->bus.width = i40e_bus_width_pcie_x2;
5351                 break;
5352         case I40E_PCI_LINK_WIDTH_4:
5353                 hw->bus.width = i40e_bus_width_pcie_x4;
5354                 break;
5355         case I40E_PCI_LINK_WIDTH_8:
5356                 hw->bus.width = i40e_bus_width_pcie_x8;
5357                 break;
5358         default:
5359                 hw->bus.width = i40e_bus_width_unknown;
5360                 break;
5361         }
5362
5363         switch (link_status & I40E_PCI_LINK_SPEED) {
5364         case I40E_PCI_LINK_SPEED_2500:
5365                 hw->bus.speed = i40e_bus_speed_2500;
5366                 break;
5367         case I40E_PCI_LINK_SPEED_5000:
5368                 hw->bus.speed = i40e_bus_speed_5000;
5369                 break;
5370         case I40E_PCI_LINK_SPEED_8000:
5371                 hw->bus.speed = i40e_bus_speed_8000;
5372                 break;
5373         default:
5374                 hw->bus.speed = i40e_bus_speed_unknown;
5375                 break;
5376         }
5377 }
5378
5379 /**
5380  * i40e_aq_debug_dump
5381  * @hw: pointer to the hardware structure
5382  * @cluster_id: specific cluster to dump
5383  * @table_id: table id within cluster
5384  * @start_index: index of line in the block to read
5385  * @buff_size: dump buffer size
5386  * @buff: dump buffer
5387  * @ret_buff_size: actual buffer size returned
5388  * @ret_next_table: next block to read
5389  * @ret_next_index: next index to read
5390  *
5391  * Dump internal FW/HW data for debug purposes.
5392  *
5393  **/
5394 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
5395                                 u8 table_id, u32 start_index, u16 buff_size,
5396                                 void *buff, u16 *ret_buff_size,
5397                                 u8 *ret_next_table, u32 *ret_next_index,
5398                                 struct i40e_asq_cmd_details *cmd_details)
5399 {
5400         struct i40e_aq_desc desc;
5401         struct i40e_aqc_debug_dump_internals *cmd =
5402                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5403         struct i40e_aqc_debug_dump_internals *resp =
5404                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5405         enum i40e_status_code status;
5406
5407         if (buff_size == 0 || !buff)
5408                 return I40E_ERR_PARAM;
5409
5410         i40e_fill_default_direct_cmd_desc(&desc,
5411                                           i40e_aqc_opc_debug_dump_internals);
5412         /* Indirect Command */
5413         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5414         if (buff_size > I40E_AQ_LARGE_BUF)
5415                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5416
5417         cmd->cluster_id = cluster_id;
5418         cmd->table_id = table_id;
5419         cmd->idx = CPU_TO_LE32(start_index);
5420
5421         desc.datalen = CPU_TO_LE16(buff_size);
5422
5423         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5424         if (!status) {
5425                 if (ret_buff_size != NULL)
5426                         *ret_buff_size = LE16_TO_CPU(desc.datalen);
5427                 if (ret_next_table != NULL)
5428                         *ret_next_table = resp->table_id;
5429                 if (ret_next_index != NULL)
5430                         *ret_next_index = LE32_TO_CPU(resp->idx);
5431         }
5432
5433         return status;
5434 }
5435
5436 /**
5437  * i40e_read_bw_from_alt_ram
5438  * @hw: pointer to the hardware structure
5439  * @max_bw: pointer for max_bw read
5440  * @min_bw: pointer for min_bw read
5441  * @min_valid: pointer for bool that is true if min_bw is a valid value
5442  * @max_valid: pointer for bool that is true if max_bw is a valid value
5443  *
5444  * Read bw from the alternate ram for the given pf
5445  **/
5446 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
5447                                         u32 *max_bw, u32 *min_bw,
5448                                         bool *min_valid, bool *max_valid)
5449 {
5450         enum i40e_status_code status;
5451         u32 max_bw_addr, min_bw_addr;
5452
5453         /* Calculate the address of the min/max bw registers */
5454         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5455                 I40E_ALT_STRUCT_MAX_BW_OFFSET +
5456                 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
5457         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5458                 I40E_ALT_STRUCT_MIN_BW_OFFSET +
5459                 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
5460
5461         /* Read the bandwidths from alt ram */
5462         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
5463                                         min_bw_addr, min_bw);
5464
5465         if (*min_bw & I40E_ALT_BW_VALID_MASK)
5466                 *min_valid = true;
5467         else
5468                 *min_valid = false;
5469
5470         if (*max_bw & I40E_ALT_BW_VALID_MASK)
5471                 *max_valid = true;
5472         else
5473                 *max_valid = false;
5474
5475         return status;
5476 }
5477
5478 /**
5479  * i40e_aq_configure_partition_bw
5480  * @hw: pointer to the hardware structure
5481  * @bw_data: Buffer holding valid pfs and bw limits
5482  * @cmd_details: pointer to command details
5483  *
5484  * Configure partitions guaranteed/max bw
5485  **/
5486 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
5487                         struct i40e_aqc_configure_partition_bw_data *bw_data,
5488                         struct i40e_asq_cmd_details *cmd_details)
5489 {
5490         enum i40e_status_code status;
5491         struct i40e_aq_desc desc;
5492         u16 bwd_size = sizeof(*bw_data);
5493
5494         i40e_fill_default_direct_cmd_desc(&desc,
5495                                 i40e_aqc_opc_configure_partition_bw);
5496
5497         /* Indirect command */
5498         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5499         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5500
5501         if (bwd_size > I40E_AQ_LARGE_BUF)
5502                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5503
5504         desc.datalen = CPU_TO_LE16(bwd_size);
5505
5506         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
5507
5508         return status;
5509 }
5510 #endif /* PF_DRIVER */
5511 #ifdef VF_DRIVER
5512
5513 /**
5514  * i40e_aq_send_msg_to_pf
5515  * @hw: pointer to the hardware structure
5516  * @v_opcode: opcodes for VF-PF communication
5517  * @v_retval: return error code
5518  * @msg: pointer to the msg buffer
5519  * @msglen: msg length
5520  * @cmd_details: pointer to command details
5521  *
5522  * Send message to PF driver using admin queue. By default, this message
5523  * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
5524  * completion before returning.
5525  **/
5526 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
5527                                 enum i40e_virtchnl_ops v_opcode,
5528                                 enum i40e_status_code v_retval,
5529                                 u8 *msg, u16 msglen,
5530                                 struct i40e_asq_cmd_details *cmd_details)
5531 {
5532         struct i40e_aq_desc desc;
5533         struct i40e_asq_cmd_details details;
5534         enum i40e_status_code status;
5535
5536         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
5537         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
5538         desc.cookie_high = CPU_TO_LE32(v_opcode);
5539         desc.cookie_low = CPU_TO_LE32(v_retval);
5540         if (msglen) {
5541                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
5542                                                 | I40E_AQ_FLAG_RD));
5543                 if (msglen > I40E_AQ_LARGE_BUF)
5544                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5545                 desc.datalen = CPU_TO_LE16(msglen);
5546         }
5547         if (!cmd_details) {
5548                 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
5549                 details.async = true;
5550                 cmd_details = &details;
5551         }
5552         status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
5553                                        msglen, cmd_details);
5554         return status;
5555 }
5556
5557 /**
5558  * i40e_vf_parse_hw_config
5559  * @hw: pointer to the hardware structure
5560  * @msg: pointer to the virtual channel VF resource structure
5561  *
5562  * Given a VF resource message from the PF, populate the hw struct
5563  * with appropriate information.
5564  **/
5565 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
5566                              struct i40e_virtchnl_vf_resource *msg)
5567 {
5568         struct i40e_virtchnl_vsi_resource *vsi_res;
5569         int i;
5570
5571         vsi_res = &msg->vsi_res[0];
5572
5573         hw->dev_caps.num_vsis = msg->num_vsis;
5574         hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
5575         hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
5576         hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
5577         hw->dev_caps.dcb = msg->vf_offload_flags &
5578                            I40E_VIRTCHNL_VF_OFFLOAD_L2;
5579         hw->dev_caps.fcoe = (msg->vf_offload_flags &
5580                              I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
5581         hw->dev_caps.iwarp = (msg->vf_offload_flags &
5582                               I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
5583         for (i = 0; i < msg->num_vsis; i++) {
5584                 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
5585                         i40e_memcpy(hw->mac.perm_addr,
5586                                     vsi_res->default_mac_addr,
5587                                     I40E_ETH_LENGTH_OF_ADDRESS,
5588                                     I40E_NONDMA_TO_NONDMA);
5589                         i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
5590                                     I40E_ETH_LENGTH_OF_ADDRESS,
5591                                     I40E_NONDMA_TO_NONDMA);
5592                 }
5593                 vsi_res++;
5594         }
5595 }
5596
5597 /**
5598  * i40e_vf_reset
5599  * @hw: pointer to the hardware structure
5600  *
5601  * Send a VF_RESET message to the PF. Does not wait for response from PF
5602  * as none will be forthcoming. Immediately after calling this function,
5603  * the admin queue should be shut down and (optionally) reinitialized.
5604  **/
5605 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
5606 {
5607         return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
5608                                       I40E_SUCCESS, NULL, 0, NULL);
5609 }
5610 #endif /* VF_DRIVER */