drivers/net/i40e/base/i40e_common.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "i40e_type.h"
  35 #include "i40e_adminq.h"
  36 #include "i40e_prototype.h"
  37 #include "virtchnl.h"
  38
  39
  40 /**
  41  * i40e_set_mac_type - Sets MAC type
  42  * @hw: pointer to the HW structure
  43  *
  44  * This function sets the mac type of the adapter based on the
  45  * vendor ID and device ID stored in the hw structure.
  46  **/
  47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  49 #else
  50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  51 #endif
  52 {
  53         enum i40e_status_code status = I40E_SUCCESS;
  54
  55         DEBUGFUNC("i40e_set_mac_type\n");
  56
  57         if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
  58                 switch (hw->device_id) {
  59                 case I40E_DEV_ID_SFP_XL710:
  60                 case I40E_DEV_ID_QEMU:
  61                 case I40E_DEV_ID_KX_B:
  62                 case I40E_DEV_ID_KX_C:
  63                 case I40E_DEV_ID_QSFP_A:
  64                 case I40E_DEV_ID_QSFP_B:
  65                 case I40E_DEV_ID_QSFP_C:
  66                 case I40E_DEV_ID_10G_BASE_T:
  67                 case I40E_DEV_ID_10G_BASE_T4:
  68                 case I40E_DEV_ID_20G_KR2:
  69                 case I40E_DEV_ID_20G_KR2_A:
  70                 case I40E_DEV_ID_25G_B:
  71                 case I40E_DEV_ID_25G_SFP28:
  72                         hw->mac.type = I40E_MAC_XL710;
  73                         break;
  74 #ifdef X722_A0_SUPPORT
  75                 case I40E_DEV_ID_X722_A0:
  76 #endif
  77                 case I40E_DEV_ID_KX_X722:
  78                 case I40E_DEV_ID_QSFP_X722:
  79                 case I40E_DEV_ID_SFP_X722:
  80                 case I40E_DEV_ID_1G_BASE_T_X722:
  81                 case I40E_DEV_ID_10G_BASE_T_X722:
  82                 case I40E_DEV_ID_SFP_I_X722:
  83                         hw->mac.type = I40E_MAC_X722;
  84                         break;
  85 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  86                 case I40E_DEV_ID_X722_VF:
  87 #ifdef X722_A0_SUPPORT
  88                 case I40E_DEV_ID_X722_A0_VF:
  89 #endif
  90                         hw->mac.type = I40E_MAC_X722_VF;
  91                         break;
  92 #endif /* INTEGRATED_VF || VF_DRIVER */
  93 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  94                 case I40E_DEV_ID_VF:
  95                 case I40E_DEV_ID_VF_HV:
  96                 case I40E_DEV_ID_ADAPTIVE_VF:
  97                         hw->mac.type = I40E_MAC_VF;
  98                         break;
  99 #endif
 100                 default:
 101                         hw->mac.type = I40E_MAC_GENERIC;
 102                         break;
 103                 }
 104         } else {
 105                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
 106         }
 107
 108         DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
 109                   hw->mac.type, status);
 110         return status;
 111 }
 112
 113 /**
 114  * i40e_aq_str - convert AQ err code to a string
 115  * @hw: pointer to the HW structure
 116  * @aq_err: the AQ error code to convert
 117  **/
 118 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
 119 {
 120         switch (aq_err) {
 121         case I40E_AQ_RC_OK:
 122                 return "OK";
 123         case I40E_AQ_RC_EPERM:
 124                 return "I40E_AQ_RC_EPERM";
 125         case I40E_AQ_RC_ENOENT:
 126                 return "I40E_AQ_RC_ENOENT";
 127         case I40E_AQ_RC_ESRCH:
 128                 return "I40E_AQ_RC_ESRCH";
 129         case I40E_AQ_RC_EINTR:
 130                 return "I40E_AQ_RC_EINTR";
 131         case I40E_AQ_RC_EIO:
 132                 return "I40E_AQ_RC_EIO";
 133         case I40E_AQ_RC_ENXIO:
 134                 return "I40E_AQ_RC_ENXIO";
 135         case I40E_AQ_RC_E2BIG:
 136                 return "I40E_AQ_RC_E2BIG";
 137         case I40E_AQ_RC_EAGAIN:
 138                 return "I40E_AQ_RC_EAGAIN";
 139         case I40E_AQ_RC_ENOMEM:
 140                 return "I40E_AQ_RC_ENOMEM";
 141         case I40E_AQ_RC_EACCES:
 142                 return "I40E_AQ_RC_EACCES";
 143         case I40E_AQ_RC_EFAULT:
 144                 return "I40E_AQ_RC_EFAULT";
 145         case I40E_AQ_RC_EBUSY:
 146                 return "I40E_AQ_RC_EBUSY";
 147         case I40E_AQ_RC_EEXIST:
 148                 return "I40E_AQ_RC_EEXIST";
 149         case I40E_AQ_RC_EINVAL:
 150                 return "I40E_AQ_RC_EINVAL";
 151         case I40E_AQ_RC_ENOTTY:
 152                 return "I40E_AQ_RC_ENOTTY";
 153         case I40E_AQ_RC_ENOSPC:
 154                 return "I40E_AQ_RC_ENOSPC";
 155         case I40E_AQ_RC_ENOSYS:
 156                 return "I40E_AQ_RC_ENOSYS";
 157         case I40E_AQ_RC_ERANGE:
 158                 return "I40E_AQ_RC_ERANGE";
 159         case I40E_AQ_RC_EFLUSHED:
 160                 return "I40E_AQ_RC_EFLUSHED";
 161         case I40E_AQ_RC_BAD_ADDR:
 162                 return "I40E_AQ_RC_BAD_ADDR";
 163         case I40E_AQ_RC_EMODE:
 164                 return "I40E_AQ_RC_EMODE";
 165         case I40E_AQ_RC_EFBIG:
 166                 return "I40E_AQ_RC_EFBIG";
 167         }
 168
 169         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 170         return hw->err_str;
 171 }
 172
 173 /**
 174  * i40e_stat_str - convert status err code to a string
 175  * @hw: pointer to the HW structure
 176  * @stat_err: the status error code to convert
 177  **/
 178 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
 179 {
 180         switch (stat_err) {
 181         case I40E_SUCCESS:
 182                 return "OK";
 183         case I40E_ERR_NVM:
 184                 return "I40E_ERR_NVM";
 185         case I40E_ERR_NVM_CHECKSUM:
 186                 return "I40E_ERR_NVM_CHECKSUM";
 187         case I40E_ERR_PHY:
 188                 return "I40E_ERR_PHY";
 189         case I40E_ERR_CONFIG:
 190                 return "I40E_ERR_CONFIG";
 191         case I40E_ERR_PARAM:
 192                 return "I40E_ERR_PARAM";
 193         case I40E_ERR_MAC_TYPE:
 194                 return "I40E_ERR_MAC_TYPE";
 195         case I40E_ERR_UNKNOWN_PHY:
 196                 return "I40E_ERR_UNKNOWN_PHY";
 197         case I40E_ERR_LINK_SETUP:
 198                 return "I40E_ERR_LINK_SETUP";
 199         case I40E_ERR_ADAPTER_STOPPED:
 200                 return "I40E_ERR_ADAPTER_STOPPED";
 201         case I40E_ERR_INVALID_MAC_ADDR:
 202                 return "I40E_ERR_INVALID_MAC_ADDR";
 203         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 204                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 205         case I40E_ERR_MASTER_REQUESTS_PENDING:
 206                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 207         case I40E_ERR_INVALID_LINK_SETTINGS:
 208                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 209         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 210                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 211         case I40E_ERR_RESET_FAILED:
 212                 return "I40E_ERR_RESET_FAILED";
 213         case I40E_ERR_SWFW_SYNC:
 214                 return "I40E_ERR_SWFW_SYNC";
 215         case I40E_ERR_NO_AVAILABLE_VSI:
 216                 return "I40E_ERR_NO_AVAILABLE_VSI";
 217         case I40E_ERR_NO_MEMORY:
 218                 return "I40E_ERR_NO_MEMORY";
 219         case I40E_ERR_BAD_PTR:
 220                 return "I40E_ERR_BAD_PTR";
 221         case I40E_ERR_RING_FULL:
 222                 return "I40E_ERR_RING_FULL";
 223         case I40E_ERR_INVALID_PD_ID:
 224                 return "I40E_ERR_INVALID_PD_ID";
 225         case I40E_ERR_INVALID_QP_ID:
 226                 return "I40E_ERR_INVALID_QP_ID";
 227         case I40E_ERR_INVALID_CQ_ID:
 228                 return "I40E_ERR_INVALID_CQ_ID";
 229         case I40E_ERR_INVALID_CEQ_ID:
 230                 return "I40E_ERR_INVALID_CEQ_ID";
 231         case I40E_ERR_INVALID_AEQ_ID:
 232                 return "I40E_ERR_INVALID_AEQ_ID";
 233         case I40E_ERR_INVALID_SIZE:
 234                 return "I40E_ERR_INVALID_SIZE";
 235         case I40E_ERR_INVALID_ARP_INDEX:
 236                 return "I40E_ERR_INVALID_ARP_INDEX";
 237         case I40E_ERR_INVALID_FPM_FUNC_ID:
 238                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 239         case I40E_ERR_QP_INVALID_MSG_SIZE:
 240                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 241         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 242                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 243         case I40E_ERR_INVALID_FRAG_COUNT:
 244                 return "I40E_ERR_INVALID_FRAG_COUNT";
 245         case I40E_ERR_QUEUE_EMPTY:
 246                 return "I40E_ERR_QUEUE_EMPTY";
 247         case I40E_ERR_INVALID_ALIGNMENT:
 248                 return "I40E_ERR_INVALID_ALIGNMENT";
 249         case I40E_ERR_FLUSHED_QUEUE:
 250                 return "I40E_ERR_FLUSHED_QUEUE";
 251         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 252                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 253         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 254                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 255         case I40E_ERR_TIMEOUT:
 256                 return "I40E_ERR_TIMEOUT";
 257         case I40E_ERR_OPCODE_MISMATCH:
 258                 return "I40E_ERR_OPCODE_MISMATCH";
 259         case I40E_ERR_CQP_COMPL_ERROR:
 260                 return "I40E_ERR_CQP_COMPL_ERROR";
 261         case I40E_ERR_INVALID_VF_ID:
 262                 return "I40E_ERR_INVALID_VF_ID";
 263         case I40E_ERR_INVALID_HMCFN_ID:
 264                 return "I40E_ERR_INVALID_HMCFN_ID";
 265         case I40E_ERR_BACKING_PAGE_ERROR:
 266                 return "I40E_ERR_BACKING_PAGE_ERROR";
 267         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 268                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 269         case I40E_ERR_INVALID_PBLE_INDEX:
 270                 return "I40E_ERR_INVALID_PBLE_INDEX";
 271         case I40E_ERR_INVALID_SD_INDEX:
 272                 return "I40E_ERR_INVALID_SD_INDEX";
 273         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 274                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 275         case I40E_ERR_INVALID_SD_TYPE:
 276                 return "I40E_ERR_INVALID_SD_TYPE";
 277         case I40E_ERR_MEMCPY_FAILED:
 278                 return "I40E_ERR_MEMCPY_FAILED";
 279         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 280                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 281         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 282                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 283         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 284                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 285         case I40E_ERR_SRQ_ENABLED:
 286                 return "I40E_ERR_SRQ_ENABLED";
 287         case I40E_ERR_ADMIN_QUEUE_ERROR:
 288                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 289         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 290                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 291         case I40E_ERR_BUF_TOO_SHORT:
 292                 return "I40E_ERR_BUF_TOO_SHORT";
 293         case I40E_ERR_ADMIN_QUEUE_FULL:
 294                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 295         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 296                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 297         case I40E_ERR_BAD_IWARP_CQE:
 298                 return "I40E_ERR_BAD_IWARP_CQE";
 299         case I40E_ERR_NVM_BLANK_MODE:
 300                 return "I40E_ERR_NVM_BLANK_MODE";
 301         case I40E_ERR_NOT_IMPLEMENTED:
 302                 return "I40E_ERR_NOT_IMPLEMENTED";
 303         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 304                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 305         case I40E_ERR_DIAG_TEST_FAILED:
 306                 return "I40E_ERR_DIAG_TEST_FAILED";
 307         case I40E_ERR_NOT_READY:
 308                 return "I40E_ERR_NOT_READY";
 309         case I40E_NOT_SUPPORTED:
 310                 return "I40E_NOT_SUPPORTED";
 311         case I40E_ERR_FIRMWARE_API_VERSION:
 312                 return "I40E_ERR_FIRMWARE_API_VERSION";
 313         }
 314
 315         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 316         return hw->err_str;
 317 }
 318
 319 /**
 320  * i40e_debug_aq
 321  * @hw: debug mask related to admin queue
 322  * @mask: debug mask
 323  * @desc: pointer to admin queue descriptor
 324  * @buffer: pointer to command buffer
 325  * @buf_len: max length of buffer
 326  *
 327  * Dumps debug log about adminq command with descriptor contents.
 328  **/
 329 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 330                    void *buffer, u16 buf_len)
 331 {
 332         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 333         u8 *buf = (u8 *)buffer;
 334         u16 len;
 335         u16 i = 0;
 336
 337         if ((!(mask & hw->debug_mask)) || (desc == NULL))
 338                 return;
 339
 340         len = LE16_TO_CPU(aq_desc->datalen);
 341
 342         i40e_debug(hw, mask,
 343                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 344                    LE16_TO_CPU(aq_desc->opcode),
 345                    LE16_TO_CPU(aq_desc->flags),
 346                    LE16_TO_CPU(aq_desc->datalen),
 347                    LE16_TO_CPU(aq_desc->retval));
 348         i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
 349                    LE32_TO_CPU(aq_desc->cookie_high),
 350                    LE32_TO_CPU(aq_desc->cookie_low));
 351         i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
 352                    LE32_TO_CPU(aq_desc->params.internal.param0),
 353                    LE32_TO_CPU(aq_desc->params.internal.param1));
 354         i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
 355                    LE32_TO_CPU(aq_desc->params.external.addr_high),
 356                    LE32_TO_CPU(aq_desc->params.external.addr_low));
 357
 358         if ((buffer != NULL) && (aq_desc->datalen != 0)) {
 359                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 360                 if (buf_len < len)
 361                         len = buf_len;
 362                 /* write the full 16-byte chunks */
 363                 for (i = 0; i < (len - 16); i += 16)
 364                         i40e_debug(hw, mask,
 365                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 366                                    i, buf[i], buf[i+1], buf[i+2], buf[i+3],
 367                                    buf[i+4], buf[i+5], buf[i+6], buf[i+7],
 368                                    buf[i+8], buf[i+9], buf[i+10], buf[i+11],
 369                                    buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
 370                 /* the most we could have left is 16 bytes, pad with zeros */
 371                 if (i < len) {
 372                         char d_buf[16];
 373                         int j, i_sav;
 374
 375                         i_sav = i;
 376                         memset(d_buf, 0, sizeof(d_buf));
 377                         for (j = 0; i < len; j++, i++)
 378                                 d_buf[j] = buf[i];
 379                         i40e_debug(hw, mask,
 380                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 381                                    i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
 382                                    d_buf[4], d_buf[5], d_buf[6], d_buf[7],
 383                                    d_buf[8], d_buf[9], d_buf[10], d_buf[11],
 384                                    d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
 385                 }
 386         }
 387 }
 388
 389 /**
 390  * i40e_check_asq_alive
 391  * @hw: pointer to the hw struct
 392  *
 393  * Returns true if Queue is enabled else false.
 394  **/
 395 bool i40e_check_asq_alive(struct i40e_hw *hw)
 396 {
 397         if (hw->aq.asq.len)
 398 #ifdef PF_DRIVER
 399 #ifdef INTEGRATED_VF
 400                 if (!i40e_is_vf(hw))
 401                         return !!(rd32(hw, hw->aq.asq.len) &
 402                                 I40E_PF_ATQLEN_ATQENABLE_MASK);
 403 #else
 404                 return !!(rd32(hw, hw->aq.asq.len) &
 405                         I40E_PF_ATQLEN_ATQENABLE_MASK);
 406 #endif /* INTEGRATED_VF */
 407 #endif /* PF_DRIVER */
 408 #ifdef VF_DRIVER
 409 #ifdef INTEGRATED_VF
 410                 if (i40e_is_vf(hw))
 411                         return !!(rd32(hw, hw->aq.asq.len) &
 412                                 I40E_VF_ATQLEN1_ATQENABLE_MASK);
 413 #else
 414                 return !!(rd32(hw, hw->aq.asq.len) &
 415                         I40E_VF_ATQLEN1_ATQENABLE_MASK);
 416 #endif /* INTEGRATED_VF */
 417 #endif /* VF_DRIVER */
 418         return false;
 419 }
 420
 421 /**
 422  * i40e_aq_queue_shutdown
 423  * @hw: pointer to the hw struct
 424  * @unloading: is the driver unloading itself
 425  *
 426  * Tell the Firmware that we're shutting down the AdminQ and whether
 427  * or not the driver is unloading as well.
 428  **/
 429 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
 430                                              bool unloading)
 431 {
 432         struct i40e_aq_desc desc;
 433         struct i40e_aqc_queue_shutdown *cmd =
 434                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 435         enum i40e_status_code status;
 436
 437         i40e_fill_default_direct_cmd_desc(&desc,
 438                                           i40e_aqc_opc_queue_shutdown);
 439
 440         if (unloading)
 441                 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
 442         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 443
 444         return status;
 445 }
 446
 447 /**
 448  * i40e_aq_get_set_rss_lut
 449  * @hw: pointer to the hardware structure
 450  * @vsi_id: vsi fw index
 451  * @pf_lut: for PF table set true, for VSI table set false
 452  * @lut: pointer to the lut buffer provided by the caller
 453  * @lut_size: size of the lut buffer
 454  * @set: set true to set the table, false to get the table
 455  *
 456  * Internal function to get or set RSS look up table
 457  **/
 458 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 459                                                      u16 vsi_id, bool pf_lut,
 460                                                      u8 *lut, u16 lut_size,
 461                                                      bool set)
 462 {
 463         enum i40e_status_code status;
 464         struct i40e_aq_desc desc;
 465         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 466                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 467
 468         if (set)
 469                 i40e_fill_default_direct_cmd_desc(&desc,
 470                                                   i40e_aqc_opc_set_rss_lut);
 471         else
 472                 i40e_fill_default_direct_cmd_desc(&desc,
 473                                                   i40e_aqc_opc_get_rss_lut);
 474
 475         /* Indirect command */
 476         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 477         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 478
 479         cmd_resp->vsi_id =
 480                         CPU_TO_LE16((u16)((vsi_id <<
 481                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 482                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 483         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 484
 485         if (pf_lut)
 486                 cmd_resp->flags |= CPU_TO_LE16((u16)
 487                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 488                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 489                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 490         else
 491                 cmd_resp->flags |= CPU_TO_LE16((u16)
 492                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 493                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 494                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 495
 496         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 497
 498         return status;
 499 }
 500
 501 /**
 502  * i40e_aq_get_rss_lut
 503  * @hw: pointer to the hardware structure
 504  * @vsi_id: vsi fw index
 505  * @pf_lut: for PF table set true, for VSI table set false
 506  * @lut: pointer to the lut buffer provided by the caller
 507  * @lut_size: size of the lut buffer
 508  *
 509  * get the RSS lookup table, PF or VSI type
 510  **/
 511 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 512                                           bool pf_lut, u8 *lut, u16 lut_size)
 513 {
 514         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 515                                        false);
 516 }
 517
 518 /**
 519  * i40e_aq_set_rss_lut
 520  * @hw: pointer to the hardware structure
 521  * @vsi_id: vsi fw index
 522  * @pf_lut: for PF table set true, for VSI table set false
 523  * @lut: pointer to the lut buffer provided by the caller
 524  * @lut_size: size of the lut buffer
 525  *
 526  * set the RSS lookup table, PF or VSI type
 527  **/
 528 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 529                                           bool pf_lut, u8 *lut, u16 lut_size)
 530 {
 531         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
 532 }
 533
 534 /**
 535  * i40e_aq_get_set_rss_key
 536  * @hw: pointer to the hw struct
 537  * @vsi_id: vsi fw index
 538  * @key: pointer to key info struct
 539  * @set: set true to set the key, false to get the key
 540  *
 541  * get the RSS key per VSI
 542  **/
 543 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 544                                       u16 vsi_id,
 545                                       struct i40e_aqc_get_set_rss_key_data *key,
 546                                       bool set)
 547 {
 548         enum i40e_status_code status;
 549         struct i40e_aq_desc desc;
 550         struct i40e_aqc_get_set_rss_key *cmd_resp =
 551                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 552         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 553
 554         if (set)
 555                 i40e_fill_default_direct_cmd_desc(&desc,
 556                                                   i40e_aqc_opc_set_rss_key);
 557         else
 558                 i40e_fill_default_direct_cmd_desc(&desc,
 559                                                   i40e_aqc_opc_get_rss_key);
 560
 561         /* Indirect command */
 562         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 563         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 564
 565         cmd_resp->vsi_id =
 566                         CPU_TO_LE16((u16)((vsi_id <<
 567                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 568                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 569         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 570
 571         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 572
 573         return status;
 574 }
 575
 576 /**
 577  * i40e_aq_get_rss_key
 578  * @hw: pointer to the hw struct
 579  * @vsi_id: vsi fw index
 580  * @key: pointer to key info struct
 581  *
 582  **/
 583 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
 584                                       u16 vsi_id,
 585                                       struct i40e_aqc_get_set_rss_key_data *key)
 586 {
 587         return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
 588 }
 589
 590 /**
 591  * i40e_aq_set_rss_key
 592  * @hw: pointer to the hw struct
 593  * @vsi_id: vsi fw index
 594  * @key: pointer to key info struct
 595  *
 596  * set the RSS key per VSI
 597  **/
 598 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
 599                                       u16 vsi_id,
 600                                       struct i40e_aqc_get_set_rss_key_data *key)
 601 {
 602         return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
 603 }
 604
 605 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 606  * hardware to a bit-field that can be used by SW to more easily determine the
 607  * packet type.
 608  *
 609  * Macros are used to shorten the table lines and make this table human
 610  * readable.
 611  *
 612  * We store the PTYPE in the top byte of the bit field - this is just so that
 613  * we can check that the table doesn't have a row missing, as the index into
 614  * the table should be the PTYPE.
 615  *
 616  * Typical work flow:
 617  *
 618  * IF NOT i40e_ptype_lookup[ptype].known
 619  * THEN
 620  *      Packet is unknown
 621  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 622  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 623  * ELSE
 624  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 625  * ENDIF
 626  */
 627
 628 /* macro to make the table lines short */
 629 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 630         {       PTYPE, \
 631                 1, \
 632                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 633                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 634                 I40E_RX_PTYPE_##OUTER_FRAG, \
 635                 I40E_RX_PTYPE_TUNNEL_##T, \
 636                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 637                 I40E_RX_PTYPE_##TEF, \
 638                 I40E_RX_PTYPE_INNER_PROT_##I, \
 639                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 640
 641 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 642                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 643
 644 /* shorter macros makes the table fit but are terse */
 645 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 646 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 647 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 648
 649 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 650 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 651         /* L2 Packet types */
 652         I40E_PTT_UNUSED_ENTRY(0),
 653         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 654         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 655         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 656         I40E_PTT_UNUSED_ENTRY(4),
 657         I40E_PTT_UNUSED_ENTRY(5),
 658         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 659         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 660         I40E_PTT_UNUSED_ENTRY(8),
 661         I40E_PTT_UNUSED_ENTRY(9),
 662         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 663         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 664         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 665         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 666         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 667         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 668         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 669         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 670         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 671         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 672         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 673         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 674
 675         /* Non Tunneled IPv4 */
 676         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 677         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 678         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 679         I40E_PTT_UNUSED_ENTRY(25),
 680         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 681         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 682         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 683
 684         /* IPv4 --> IPv4 */
 685         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 686         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 687         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 688         I40E_PTT_UNUSED_ENTRY(32),
 689         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 690         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 691         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 692
 693         /* IPv4 --> IPv6 */
 694         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 695         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 696         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 697         I40E_PTT_UNUSED_ENTRY(39),
 698         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 699         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 700         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 701
 702         /* IPv4 --> GRE/NAT */
 703         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 704
 705         /* IPv4 --> GRE/NAT --> IPv4 */
 706         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 707         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 708         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 709         I40E_PTT_UNUSED_ENTRY(47),
 710         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 711         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 712         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 713
 714         /* IPv4 --> GRE/NAT --> IPv6 */
 715         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 716         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 717         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 718         I40E_PTT_UNUSED_ENTRY(54),
 719         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 720         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 721         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 722
 723         /* IPv4 --> GRE/NAT --> MAC */
 724         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 725
 726         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 727         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 728         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 729         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 730         I40E_PTT_UNUSED_ENTRY(62),
 731         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 732         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 733         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 734
 735         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 736         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 737         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 738         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 739         I40E_PTT_UNUSED_ENTRY(69),
 740         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 741         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 742         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 743
 744         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 745         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 746
 747         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 748         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 749         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 750         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 751         I40E_PTT_UNUSED_ENTRY(77),
 752         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 753         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 754         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 755
 756         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 757         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 758         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 759         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 760         I40E_PTT_UNUSED_ENTRY(84),
 761         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 762         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 763         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 764
 765         /* Non Tunneled IPv6 */
 766         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 767         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 768         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
 769         I40E_PTT_UNUSED_ENTRY(91),
 770         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 771         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 772         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 773
 774         /* IPv6 --> IPv4 */
 775         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 776         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 777         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 778         I40E_PTT_UNUSED_ENTRY(98),
 779         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 780         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 781         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 782
 783         /* IPv6 --> IPv6 */
 784         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 785         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 786         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 787         I40E_PTT_UNUSED_ENTRY(105),
 788         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 789         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 790         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 791
 792         /* IPv6 --> GRE/NAT */
 793         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 794
 795         /* IPv6 --> GRE/NAT -> IPv4 */
 796         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 797         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 798         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 799         I40E_PTT_UNUSED_ENTRY(113),
 800         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 801         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 802         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 803
 804         /* IPv6 --> GRE/NAT -> IPv6 */
 805         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 806         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 807         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 808         I40E_PTT_UNUSED_ENTRY(120),
 809         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 810         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 811         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 812
 813         /* IPv6 --> GRE/NAT -> MAC */
 814         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 815
 816         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 817         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 818         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 819         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 820         I40E_PTT_UNUSED_ENTRY(128),
 821         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 822         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 823         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 824
 825         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 826         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 827         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 828         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 829         I40E_PTT_UNUSED_ENTRY(135),
 830         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 831         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 832         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 833
 834         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 835         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 836
 837         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 838         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 839         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 840         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 841         I40E_PTT_UNUSED_ENTRY(143),
 842         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 843         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 844         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 845
 846         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 847         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 848         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 849         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 850         I40E_PTT_UNUSED_ENTRY(150),
 851         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 852         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 853         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 854
 855         /* unused entries */
 856         I40E_PTT_UNUSED_ENTRY(154),
 857         I40E_PTT_UNUSED_ENTRY(155),
 858         I40E_PTT_UNUSED_ENTRY(156),
 859         I40E_PTT_UNUSED_ENTRY(157),
 860         I40E_PTT_UNUSED_ENTRY(158),
 861         I40E_PTT_UNUSED_ENTRY(159),
 862
 863         I40E_PTT_UNUSED_ENTRY(160),
 864         I40E_PTT_UNUSED_ENTRY(161),
 865         I40E_PTT_UNUSED_ENTRY(162),
 866         I40E_PTT_UNUSED_ENTRY(163),
 867         I40E_PTT_UNUSED_ENTRY(164),
 868         I40E_PTT_UNUSED_ENTRY(165),
 869         I40E_PTT_UNUSED_ENTRY(166),
 870         I40E_PTT_UNUSED_ENTRY(167),
 871         I40E_PTT_UNUSED_ENTRY(168),
 872         I40E_PTT_UNUSED_ENTRY(169),
 873
 874         I40E_PTT_UNUSED_ENTRY(170),
 875         I40E_PTT_UNUSED_ENTRY(171),
 876         I40E_PTT_UNUSED_ENTRY(172),
 877         I40E_PTT_UNUSED_ENTRY(173),
 878         I40E_PTT_UNUSED_ENTRY(174),
 879         I40E_PTT_UNUSED_ENTRY(175),
 880         I40E_PTT_UNUSED_ENTRY(176),
 881         I40E_PTT_UNUSED_ENTRY(177),
 882         I40E_PTT_UNUSED_ENTRY(178),
 883         I40E_PTT_UNUSED_ENTRY(179),
 884
 885         I40E_PTT_UNUSED_ENTRY(180),
 886         I40E_PTT_UNUSED_ENTRY(181),
 887         I40E_PTT_UNUSED_ENTRY(182),
 888         I40E_PTT_UNUSED_ENTRY(183),
 889         I40E_PTT_UNUSED_ENTRY(184),
 890         I40E_PTT_UNUSED_ENTRY(185),
 891         I40E_PTT_UNUSED_ENTRY(186),
 892         I40E_PTT_UNUSED_ENTRY(187),
 893         I40E_PTT_UNUSED_ENTRY(188),
 894         I40E_PTT_UNUSED_ENTRY(189),
 895
 896         I40E_PTT_UNUSED_ENTRY(190),
 897         I40E_PTT_UNUSED_ENTRY(191),
 898         I40E_PTT_UNUSED_ENTRY(192),
 899         I40E_PTT_UNUSED_ENTRY(193),
 900         I40E_PTT_UNUSED_ENTRY(194),
 901         I40E_PTT_UNUSED_ENTRY(195),
 902         I40E_PTT_UNUSED_ENTRY(196),
 903         I40E_PTT_UNUSED_ENTRY(197),
 904         I40E_PTT_UNUSED_ENTRY(198),
 905         I40E_PTT_UNUSED_ENTRY(199),
 906
 907         I40E_PTT_UNUSED_ENTRY(200),
 908         I40E_PTT_UNUSED_ENTRY(201),
 909         I40E_PTT_UNUSED_ENTRY(202),
 910         I40E_PTT_UNUSED_ENTRY(203),
 911         I40E_PTT_UNUSED_ENTRY(204),
 912         I40E_PTT_UNUSED_ENTRY(205),
 913         I40E_PTT_UNUSED_ENTRY(206),
 914         I40E_PTT_UNUSED_ENTRY(207),
 915         I40E_PTT_UNUSED_ENTRY(208),
 916         I40E_PTT_UNUSED_ENTRY(209),
 917
 918         I40E_PTT_UNUSED_ENTRY(210),
 919         I40E_PTT_UNUSED_ENTRY(211),
 920         I40E_PTT_UNUSED_ENTRY(212),
 921         I40E_PTT_UNUSED_ENTRY(213),
 922         I40E_PTT_UNUSED_ENTRY(214),
 923         I40E_PTT_UNUSED_ENTRY(215),
 924         I40E_PTT_UNUSED_ENTRY(216),
 925         I40E_PTT_UNUSED_ENTRY(217),
 926         I40E_PTT_UNUSED_ENTRY(218),
 927         I40E_PTT_UNUSED_ENTRY(219),
 928
 929         I40E_PTT_UNUSED_ENTRY(220),
 930         I40E_PTT_UNUSED_ENTRY(221),
 931         I40E_PTT_UNUSED_ENTRY(222),
 932         I40E_PTT_UNUSED_ENTRY(223),
 933         I40E_PTT_UNUSED_ENTRY(224),
 934         I40E_PTT_UNUSED_ENTRY(225),
 935         I40E_PTT_UNUSED_ENTRY(226),
 936         I40E_PTT_UNUSED_ENTRY(227),
 937         I40E_PTT_UNUSED_ENTRY(228),
 938         I40E_PTT_UNUSED_ENTRY(229),
 939
 940         I40E_PTT_UNUSED_ENTRY(230),
 941         I40E_PTT_UNUSED_ENTRY(231),
 942         I40E_PTT_UNUSED_ENTRY(232),
 943         I40E_PTT_UNUSED_ENTRY(233),
 944         I40E_PTT_UNUSED_ENTRY(234),
 945         I40E_PTT_UNUSED_ENTRY(235),
 946         I40E_PTT_UNUSED_ENTRY(236),
 947         I40E_PTT_UNUSED_ENTRY(237),
 948         I40E_PTT_UNUSED_ENTRY(238),
 949         I40E_PTT_UNUSED_ENTRY(239),
 950
 951         I40E_PTT_UNUSED_ENTRY(240),
 952         I40E_PTT_UNUSED_ENTRY(241),
 953         I40E_PTT_UNUSED_ENTRY(242),
 954         I40E_PTT_UNUSED_ENTRY(243),
 955         I40E_PTT_UNUSED_ENTRY(244),
 956         I40E_PTT_UNUSED_ENTRY(245),
 957         I40E_PTT_UNUSED_ENTRY(246),
 958         I40E_PTT_UNUSED_ENTRY(247),
 959         I40E_PTT_UNUSED_ENTRY(248),
 960         I40E_PTT_UNUSED_ENTRY(249),
 961
 962         I40E_PTT_UNUSED_ENTRY(250),
 963         I40E_PTT_UNUSED_ENTRY(251),
 964         I40E_PTT_UNUSED_ENTRY(252),
 965         I40E_PTT_UNUSED_ENTRY(253),
 966         I40E_PTT_UNUSED_ENTRY(254),
 967         I40E_PTT_UNUSED_ENTRY(255)
 968 };
 969
 970
 971 /**
 972  * i40e_validate_mac_addr - Validate unicast MAC address
 973  * @mac_addr: pointer to MAC address
 974  *
 975  * Tests a MAC address to ensure it is a valid Individual Address
 976  **/
 977 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
 978 {
 979         enum i40e_status_code status = I40E_SUCCESS;
 980
 981         DEBUGFUNC("i40e_validate_mac_addr");
 982
 983         /* Broadcast addresses ARE multicast addresses
 984          * Make sure it is not a multicast address
 985          * Reject the zero address
 986          */
 987         if (I40E_IS_MULTICAST(mac_addr) ||
 988             (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
 989               mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
 990                 status = I40E_ERR_INVALID_MAC_ADDR;
 991
 992         return status;
 993 }
 994 #ifdef PF_DRIVER
 995
 996 /**
 997  * i40e_init_shared_code - Initialize the shared code
 998  * @hw: pointer to hardware structure
 999  *
1000  * This assigns the MAC type and PHY code and inits the NVM.
1001  * Does not touch the hardware. This function must be called prior to any
1002  * other function in the shared code. The i40e_hw structure should be
1003  * memset to 0 prior to calling this function.  The following fields in
1004  * hw structure should be filled in prior to calling this function:
1005  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1006  * subsystem_vendor_id, and revision_id
1007  **/
1008 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
1009 {
1010         enum i40e_status_code status = I40E_SUCCESS;
1011         u32 port, ari, func_rid;
1012
1013         DEBUGFUNC("i40e_init_shared_code");
1014
1015         i40e_set_mac_type(hw);
1016
1017         switch (hw->mac.type) {
1018         case I40E_MAC_XL710:
1019         case I40E_MAC_X722:
1020                 break;
1021         default:
1022                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1023         }
1024
1025         hw->phy.get_link_info = true;
1026
1027         /* Determine port number and PF number*/
1028         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1029                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1030         hw->port = (u8)port;
1031         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1032                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1033         func_rid = rd32(hw, I40E_PF_FUNC_RID);
1034         if (ari)
1035                 hw->pf_id = (u8)(func_rid & 0xff);
1036         else
1037                 hw->pf_id = (u8)(func_rid & 0x7);
1038
1039         if (hw->mac.type == I40E_MAC_X722)
1040                 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE |
1041                              I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK;
1042
1043         status = i40e_init_nvm(hw);
1044         return status;
1045 }
1046
1047 /**
1048  * i40e_aq_mac_address_read - Retrieve the MAC addresses
1049  * @hw: pointer to the hw struct
1050  * @flags: a return indicator of what addresses were added to the addr store
1051  * @addrs: the requestor's mac addr store
1052  * @cmd_details: pointer to command details structure or NULL
1053  **/
1054 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1055                                    u16 *flags,
1056                                    struct i40e_aqc_mac_address_read_data *addrs,
1057                                    struct i40e_asq_cmd_details *cmd_details)
1058 {
1059         struct i40e_aq_desc desc;
1060         struct i40e_aqc_mac_address_read *cmd_data =
1061                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1062         enum i40e_status_code status;
1063
1064         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1065         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1066
1067         status = i40e_asq_send_command(hw, &desc, addrs,
1068                                        sizeof(*addrs), cmd_details);
1069         *flags = LE16_TO_CPU(cmd_data->command_flags);
1070
1071         return status;
1072 }
1073
1074 /**
1075  * i40e_aq_mac_address_write - Change the MAC addresses
1076  * @hw: pointer to the hw struct
1077  * @flags: indicates which MAC to be written
1078  * @mac_addr: address to write
1079  * @cmd_details: pointer to command details structure or NULL
1080  **/
1081 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1082                                     u16 flags, u8 *mac_addr,
1083                                     struct i40e_asq_cmd_details *cmd_details)
1084 {
1085         struct i40e_aq_desc desc;
1086         struct i40e_aqc_mac_address_write *cmd_data =
1087                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1088         enum i40e_status_code status;
1089
1090         i40e_fill_default_direct_cmd_desc(&desc,
1091                                           i40e_aqc_opc_mac_address_write);
1092         cmd_data->command_flags = CPU_TO_LE16(flags);
1093         cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1094         cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1095                                         ((u32)mac_addr[3] << 16) |
1096                                         ((u32)mac_addr[4] << 8) |
1097                                         mac_addr[5]);
1098
1099         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1100
1101         return status;
1102 }
1103
1104 /**
1105  * i40e_get_mac_addr - get MAC address
1106  * @hw: pointer to the HW structure
1107  * @mac_addr: pointer to MAC address
1108  *
1109  * Reads the adapter's MAC address from register
1110  **/
1111 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1112 {
1113         struct i40e_aqc_mac_address_read_data addrs;
1114         enum i40e_status_code status;
1115         u16 flags = 0;
1116
1117         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1118
1119         if (flags & I40E_AQC_LAN_ADDR_VALID)
1120                 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1121                         I40E_NONDMA_TO_NONDMA);
1122
1123         return status;
1124 }
1125
1126 /**
1127  * i40e_get_port_mac_addr - get Port MAC address
1128  * @hw: pointer to the HW structure
1129  * @mac_addr: pointer to Port MAC address
1130  *
1131  * Reads the adapter's Port MAC address
1132  **/
1133 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1134 {
1135         struct i40e_aqc_mac_address_read_data addrs;
1136         enum i40e_status_code status;
1137         u16 flags = 0;
1138
1139         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1140         if (status)
1141                 return status;
1142
1143         if (flags & I40E_AQC_PORT_ADDR_VALID)
1144                 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1145                         I40E_NONDMA_TO_NONDMA);
1146         else
1147                 status = I40E_ERR_INVALID_MAC_ADDR;
1148
1149         return status;
1150 }
1151
1152 /**
1153  * i40e_pre_tx_queue_cfg - pre tx queue configure
1154  * @hw: pointer to the HW structure
1155  * @queue: target pf queue index
1156  * @enable: state change request
1157  *
1158  * Handles hw requirement to indicate intention to enable
1159  * or disable target queue.
1160  **/
1161 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1162 {
1163         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1164         u32 reg_block = 0;
1165         u32 reg_val;
1166
1167         if (abs_queue_idx >= 128) {
1168                 reg_block = abs_queue_idx / 128;
1169                 abs_queue_idx %= 128;
1170         }
1171
1172         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1173         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1174         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1175
1176         if (enable)
1177                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1178         else
1179                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1180
1181         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1182 }
1183
1184 /**
1185  * i40e_get_san_mac_addr - get SAN MAC address
1186  * @hw: pointer to the HW structure
1187  * @mac_addr: pointer to SAN MAC address
1188  *
1189  * Reads the adapter's SAN MAC address from NVM
1190  **/
1191 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1192                                             u8 *mac_addr)
1193 {
1194         struct i40e_aqc_mac_address_read_data addrs;
1195         enum i40e_status_code status;
1196         u16 flags = 0;
1197
1198         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1199         if (status)
1200                 return status;
1201
1202         if (flags & I40E_AQC_SAN_ADDR_VALID)
1203                 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac),
1204                         I40E_NONDMA_TO_NONDMA);
1205         else
1206                 status = I40E_ERR_INVALID_MAC_ADDR;
1207
1208         return status;
1209 }
1210
1211 /**
1212  *  i40e_read_pba_string - Reads part number string from EEPROM
1213  *  @hw: pointer to hardware structure
1214  *  @pba_num: stores the part number string from the EEPROM
1215  *  @pba_num_size: part number string buffer length
1216  *
1217  *  Reads the part number string from the EEPROM.
1218  **/
1219 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1220                                             u32 pba_num_size)
1221 {
1222         enum i40e_status_code status = I40E_SUCCESS;
1223         u16 pba_word = 0;
1224         u16 pba_size = 0;
1225         u16 pba_ptr = 0;
1226         u16 i = 0;
1227
1228         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1229         if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1230                 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1231                 return status;
1232         }
1233
1234         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1235         if (status != I40E_SUCCESS) {
1236                 DEBUGOUT("Failed to read PBA Block pointer.\n");
1237                 return status;
1238         }
1239
1240         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1241         if (status != I40E_SUCCESS) {
1242                 DEBUGOUT("Failed to read PBA Block size.\n");
1243                 return status;
1244         }
1245
1246         /* Subtract one to get PBA word count (PBA Size word is included in
1247          * total size)
1248          */
1249         pba_size--;
1250         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1251                 DEBUGOUT("Buffer to small for PBA data.\n");
1252                 return I40E_ERR_PARAM;
1253         }
1254
1255         for (i = 0; i < pba_size; i++) {
1256                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1257                 if (status != I40E_SUCCESS) {
1258                         DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1259                         return status;
1260                 }
1261
1262                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1263                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1264         }
1265         pba_num[(pba_size * 2)] = '\0';
1266
1267         return status;
1268 }
1269
1270 /**
1271  * i40e_get_media_type - Gets media type
1272  * @hw: pointer to the hardware structure
1273  **/
1274 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1275 {
1276         enum i40e_media_type media;
1277
1278         switch (hw->phy.link_info.phy_type) {
1279         case I40E_PHY_TYPE_10GBASE_SR:
1280         case I40E_PHY_TYPE_10GBASE_LR:
1281         case I40E_PHY_TYPE_1000BASE_SX:
1282         case I40E_PHY_TYPE_1000BASE_LX:
1283         case I40E_PHY_TYPE_40GBASE_SR4:
1284         case I40E_PHY_TYPE_40GBASE_LR4:
1285         case I40E_PHY_TYPE_25GBASE_LR:
1286         case I40E_PHY_TYPE_25GBASE_SR:
1287                 media = I40E_MEDIA_TYPE_FIBER;
1288                 break;
1289         case I40E_PHY_TYPE_100BASE_TX:
1290         case I40E_PHY_TYPE_1000BASE_T:
1291         case I40E_PHY_TYPE_10GBASE_T:
1292                 media = I40E_MEDIA_TYPE_BASET;
1293                 break;
1294         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1295         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1296         case I40E_PHY_TYPE_10GBASE_CR1:
1297         case I40E_PHY_TYPE_40GBASE_CR4:
1298         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1299         case I40E_PHY_TYPE_40GBASE_AOC:
1300         case I40E_PHY_TYPE_10GBASE_AOC:
1301         case I40E_PHY_TYPE_25GBASE_CR:
1302         case I40E_PHY_TYPE_25GBASE_AOC:
1303         case I40E_PHY_TYPE_25GBASE_ACC:
1304                 media = I40E_MEDIA_TYPE_DA;
1305                 break;
1306         case I40E_PHY_TYPE_1000BASE_KX:
1307         case I40E_PHY_TYPE_10GBASE_KX4:
1308         case I40E_PHY_TYPE_10GBASE_KR:
1309         case I40E_PHY_TYPE_40GBASE_KR4:
1310         case I40E_PHY_TYPE_20GBASE_KR2:
1311         case I40E_PHY_TYPE_25GBASE_KR:
1312                 media = I40E_MEDIA_TYPE_BACKPLANE;
1313                 break;
1314         case I40E_PHY_TYPE_SGMII:
1315         case I40E_PHY_TYPE_XAUI:
1316         case I40E_PHY_TYPE_XFI:
1317         case I40E_PHY_TYPE_XLAUI:
1318         case I40E_PHY_TYPE_XLPPI:
1319         default:
1320                 media = I40E_MEDIA_TYPE_UNKNOWN;
1321                 break;
1322         }
1323
1324         return media;
1325 }
1326
1327 #define I40E_PF_RESET_WAIT_COUNT        200
1328 /**
1329  * i40e_pf_reset - Reset the PF
1330  * @hw: pointer to the hardware structure
1331  *
1332  * Assuming someone else has triggered a global reset,
1333  * assure the global reset is complete and then reset the PF
1334  **/
1335 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1336 {
1337         u32 cnt = 0;
1338         u32 cnt1 = 0;
1339         u32 reg = 0;
1340         u32 grst_del;
1341
1342         /* Poll for Global Reset steady state in case of recent GRST.
1343          * The grst delay value is in 100ms units, and we'll wait a
1344          * couple counts longer to be sure we don't just miss the end.
1345          */
1346         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1347                         I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1348                         I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1349
1350         grst_del = grst_del * 20;
1351
1352         for (cnt = 0; cnt < grst_del; cnt++) {
1353                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1354                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1355                         break;
1356                 i40e_msec_delay(100);
1357         }
1358         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1359                 DEBUGOUT("Global reset polling failed to complete.\n");
1360                 return I40E_ERR_RESET_FAILED;
1361         }
1362
1363         /* Now Wait for the FW to be ready */
1364         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1365                 reg = rd32(hw, I40E_GLNVM_ULD);
1366                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1367                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1368                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1369                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1370                         DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1371                         break;
1372                 }
1373                 i40e_msec_delay(10);
1374         }
1375         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1376                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1377                 DEBUGOUT("wait for FW Reset complete timedout\n");
1378                 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1379                 return I40E_ERR_RESET_FAILED;
1380         }
1381
1382         /* If there was a Global Reset in progress when we got here,
1383          * we don't need to do the PF Reset
1384          */
1385         if (!cnt) {
1386                 u32 reg2 = 0;
1387
1388                 reg = rd32(hw, I40E_PFGEN_CTRL);
1389                 wr32(hw, I40E_PFGEN_CTRL,
1390                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1391                 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1392                         reg = rd32(hw, I40E_PFGEN_CTRL);
1393                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1394                                 break;
1395                         reg2 = rd32(hw, I40E_GLGEN_RSTAT);
1396                         if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1397                                 DEBUGOUT("Core reset upcoming.\n");
1398                                 DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg2);
1399                                 return I40E_ERR_NOT_READY;
1400                         }
1401                         i40e_msec_delay(1);
1402                 }
1403                 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1404                         DEBUGOUT("PF reset polling failed to complete.\n");
1405                         return I40E_ERR_RESET_FAILED;
1406                 }
1407         }
1408
1409         i40e_clear_pxe_mode(hw);
1410
1411
1412         return I40E_SUCCESS;
1413 }
1414
1415 /**
1416  * i40e_clear_hw - clear out any left over hw state
1417  * @hw: pointer to the hw struct
1418  *
1419  * Clear queues and interrupts, typically called at init time,
1420  * but after the capabilities have been found so we know how many
1421  * queues and msix vectors have been allocated.
1422  **/
1423 void i40e_clear_hw(struct i40e_hw *hw)
1424 {
1425         u32 num_queues, base_queue;
1426         u32 num_pf_int;
1427         u32 num_vf_int;
1428         u32 num_vfs;
1429         u32 i, j;
1430         u32 val;
1431         u32 eol = 0x7ff;
1432
1433         /* get number of interrupts, queues, and vfs */
1434         val = rd32(hw, I40E_GLPCI_CNF2);
1435         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1436                         I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1437         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1438                         I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1439
1440         val = rd32(hw, I40E_PFLAN_QALLOC);
1441         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1442                         I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1443         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1444                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1445         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1446                 num_queues = (j - base_queue) + 1;
1447         else
1448                 num_queues = 0;
1449
1450         val = rd32(hw, I40E_PF_VT_PFALLOC);
1451         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1452                         I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1453         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1454                         I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1455         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1456                 num_vfs = (j - i) + 1;
1457         else
1458                 num_vfs = 0;
1459
1460         /* stop all the interrupts */
1461         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1462         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1463         for (i = 0; i < num_pf_int - 2; i++)
1464                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1465
1466         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1467         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1468         wr32(hw, I40E_PFINT_LNKLST0, val);
1469         for (i = 0; i < num_pf_int - 2; i++)
1470                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1471         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1472         for (i = 0; i < num_vfs; i++)
1473                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1474         for (i = 0; i < num_vf_int - 2; i++)
1475                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1476
1477         /* warn the HW of the coming Tx disables */
1478         for (i = 0; i < num_queues; i++) {
1479                 u32 abs_queue_idx = base_queue + i;
1480                 u32 reg_block = 0;
1481
1482                 if (abs_queue_idx >= 128) {
1483                         reg_block = abs_queue_idx / 128;
1484                         abs_queue_idx %= 128;
1485                 }
1486
1487                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1488                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1489                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1490                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1491
1492                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1493         }
1494         i40e_usec_delay(400);
1495
1496         /* stop all the queues */
1497         for (i = 0; i < num_queues; i++) {
1498                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1499                 wr32(hw, I40E_QTX_ENA(i), 0);
1500                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1501                 wr32(hw, I40E_QRX_ENA(i), 0);
1502         }
1503
1504         /* short wait for all queue disables to settle */
1505         i40e_usec_delay(50);
1506 }
1507
1508 /**
1509  * i40e_clear_pxe_mode - clear pxe operations mode
1510  * @hw: pointer to the hw struct
1511  *
1512  * Make sure all PXE mode settings are cleared, including things
1513  * like descriptor fetch/write-back mode.
1514  **/
1515 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1516 {
1517         if (i40e_check_asq_alive(hw))
1518                 i40e_aq_clear_pxe_mode(hw, NULL);
1519 }
1520
1521 /**
1522  * i40e_led_is_mine - helper to find matching led
1523  * @hw: pointer to the hw struct
1524  * @idx: index into GPIO registers
1525  *
1526  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1527  */
1528 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1529 {
1530         u32 gpio_val = 0;
1531         u32 port;
1532
1533         if (!hw->func_caps.led[idx])
1534                 return 0;
1535
1536         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1537         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1538                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1539
1540         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1541          * if it is not our port then ignore
1542          */
1543         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1544             (port != hw->port))
1545                 return 0;
1546
1547         return gpio_val;
1548 }
1549
1550 #define I40E_COMBINED_ACTIVITY 0xA
1551 #define I40E_FILTER_ACTIVITY 0xE
1552 #define I40E_LINK_ACTIVITY 0xC
1553 #define I40E_MAC_ACTIVITY 0xD
1554 #define I40E_LED0 22
1555
1556 /**
1557  * i40e_led_get - return current on/off mode
1558  * @hw: pointer to the hw struct
1559  *
1560  * The value returned is the 'mode' field as defined in the
1561  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1562  * values are variations of possible behaviors relating to
1563  * blink, link, and wire.
1564  **/
1565 u32 i40e_led_get(struct i40e_hw *hw)
1566 {
1567         u32 current_mode = 0;
1568         u32 mode = 0;
1569         int i;
1570
1571         /* as per the documentation GPIO 22-29 are the LED
1572          * GPIO pins named LED0..LED7
1573          */
1574         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1575                 u32 gpio_val = i40e_led_is_mine(hw, i);
1576
1577                 if (!gpio_val)
1578                         continue;
1579
1580                 /* ignore gpio LED src mode entries related to the activity
1581                  *  LEDs
1582                  */
1583                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1584                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1585                 switch (current_mode) {
1586                 case I40E_COMBINED_ACTIVITY:
1587                 case I40E_FILTER_ACTIVITY:
1588                 case I40E_MAC_ACTIVITY:
1589                         continue;
1590                 default:
1591                         break;
1592                 }
1593
1594                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1595                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1596                 break;
1597         }
1598
1599         return mode;
1600 }
1601
1602 /**
1603  * i40e_led_set - set new on/off mode
1604  * @hw: pointer to the hw struct
1605  * @mode: 0=off, 0xf=on (else see manual for mode details)
1606  * @blink: true if the LED should blink when on, false if steady
1607  *
1608  * if this function is used to turn on the blink it should
1609  * be used to disable the blink when restoring the original state.
1610  **/
1611 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1612 {
1613         u32 current_mode = 0;
1614         int i;
1615
1616         if (mode & 0xfffffff0)
1617                 DEBUGOUT1("invalid mode passed in %X\n", mode);
1618
1619         /* as per the documentation GPIO 22-29 are the LED
1620          * GPIO pins named LED0..LED7
1621          */
1622         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1623                 u32 gpio_val = i40e_led_is_mine(hw, i);
1624
1625                 if (!gpio_val)
1626                         continue;
1627
1628                 /* ignore gpio LED src mode entries related to the activity
1629                  * LEDs
1630                  */
1631                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1632                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1633                 switch (current_mode) {
1634                 case I40E_COMBINED_ACTIVITY:
1635                 case I40E_FILTER_ACTIVITY:
1636                 case I40E_MAC_ACTIVITY:
1637                         continue;
1638                 default:
1639                         break;
1640                 }
1641
1642                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1643                 /* this & is a bit of paranoia, but serves as a range check */
1644                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1645                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1646
1647                 if (mode == I40E_LINK_ACTIVITY)
1648                         blink = false;
1649
1650                 if (blink)
1651                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1652                 else
1653                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1654
1655                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1656                 break;
1657         }
1658 }
1659
1660 /* Admin command wrappers */
1661
1662 /**
1663  * i40e_aq_get_phy_capabilities
1664  * @hw: pointer to the hw struct
1665  * @abilities: structure for PHY capabilities to be filled
1666  * @qualified_modules: report Qualified Modules
1667  * @report_init: report init capabilities (active are default)
1668  * @cmd_details: pointer to command details structure or NULL
1669  *
1670  * Returns the various PHY abilities supported on the Port.
1671  **/
1672 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1673                         bool qualified_modules, bool report_init,
1674                         struct i40e_aq_get_phy_abilities_resp *abilities,
1675                         struct i40e_asq_cmd_details *cmd_details)
1676 {
1677         struct i40e_aq_desc desc;
1678         enum i40e_status_code status;
1679         u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0;
1680         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1681
1682         if (!abilities)
1683                 return I40E_ERR_PARAM;
1684
1685         do {
1686                 i40e_fill_default_direct_cmd_desc(&desc,
1687                                                i40e_aqc_opc_get_phy_abilities);
1688
1689                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1690                 if (abilities_size > I40E_AQ_LARGE_BUF)
1691                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1692
1693                 if (qualified_modules)
1694                         desc.params.external.param0 |=
1695                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1696
1697                 if (report_init)
1698                         desc.params.external.param0 |=
1699                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1700
1701                 status = i40e_asq_send_command(hw, &desc, abilities,
1702                                                abilities_size, cmd_details);
1703
1704                 if (status != I40E_SUCCESS)
1705                         break;
1706
1707                 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) {
1708                         status = I40E_ERR_UNKNOWN_PHY;
1709                         break;
1710                 } else if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) {
1711                         i40e_msec_delay(1);
1712                         total_delay++;
1713                         status = I40E_ERR_TIMEOUT;
1714                 }
1715         } while ((hw->aq.asq_last_status != I40E_AQ_RC_OK) &&
1716                  (total_delay < max_delay));
1717
1718         if (status != I40E_SUCCESS)
1719                 return status;
1720
1721         if (report_init) {
1722                 if (hw->mac.type ==  I40E_MAC_XL710 &&
1723                     hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1724                     hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
1725                         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1726                 } else {
1727                         hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1728                         hw->phy.phy_types |=
1729                                         ((u64)abilities->phy_type_ext << 32);
1730                 }
1731         }
1732
1733         return status;
1734 }
1735
1736 /**
1737  * i40e_aq_set_phy_config
1738  * @hw: pointer to the hw struct
1739  * @config: structure with PHY configuration to be set
1740  * @cmd_details: pointer to command details structure or NULL
1741  *
1742  * Set the various PHY configuration parameters
1743  * supported on the Port.One or more of the Set PHY config parameters may be
1744  * ignored in an MFP mode as the PF may not have the privilege to set some
1745  * of the PHY Config parameters. This status will be indicated by the
1746  * command response.
1747  **/
1748 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1749                                 struct i40e_aq_set_phy_config *config,
1750                                 struct i40e_asq_cmd_details *cmd_details)
1751 {
1752         struct i40e_aq_desc desc;
1753         struct i40e_aq_set_phy_config *cmd =
1754                 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1755         enum i40e_status_code status;
1756
1757         if (!config)
1758                 return I40E_ERR_PARAM;
1759
1760         i40e_fill_default_direct_cmd_desc(&desc,
1761                                           i40e_aqc_opc_set_phy_config);
1762
1763         *cmd = *config;
1764
1765         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1766
1767         return status;
1768 }
1769
1770 /**
1771  * i40e_set_fc
1772  * @hw: pointer to the hw struct
1773  *
1774  * Set the requested flow control mode using set_phy_config.
1775  **/
1776 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1777                                   bool atomic_restart)
1778 {
1779         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1780         struct i40e_aq_get_phy_abilities_resp abilities;
1781         struct i40e_aq_set_phy_config config;
1782         enum i40e_status_code status;
1783         u8 pause_mask = 0x0;
1784
1785         *aq_failures = 0x0;
1786
1787         switch (fc_mode) {
1788         case I40E_FC_FULL:
1789                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1790                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1791                 break;
1792         case I40E_FC_RX_PAUSE:
1793                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1794                 break;
1795         case I40E_FC_TX_PAUSE:
1796                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1797                 break;
1798         default:
1799                 break;
1800         }
1801
1802         /* Get the current phy config */
1803         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1804                                               NULL);
1805         if (status) {
1806                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1807                 return status;
1808         }
1809
1810         memset(&config, 0, sizeof(config));
1811         /* clear the old pause settings */
1812         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1813                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1814         /* set the new abilities */
1815         config.abilities |= pause_mask;
1816         /* If the abilities have changed, then set the new config */
1817         if (config.abilities != abilities.abilities) {
1818                 /* Auto restart link so settings take effect */
1819                 if (atomic_restart)
1820                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1821                 /* Copy over all the old settings */
1822                 config.phy_type = abilities.phy_type;
1823                 config.phy_type_ext = abilities.phy_type_ext;
1824                 config.link_speed = abilities.link_speed;
1825                 config.eee_capability = abilities.eee_capability;
1826                 config.eeer = abilities.eeer_val;
1827                 config.low_power_ctrl = abilities.d3_lpan;
1828                 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1829                                     I40E_AQ_PHY_FEC_CONFIG_MASK;
1830                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1831
1832                 if (status)
1833                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1834         }
1835         /* Update the link info */
1836         status = i40e_update_link_info(hw);
1837         if (status) {
1838                 /* Wait a little bit (on 40G cards it sometimes takes a really
1839                  * long time for link to come back from the atomic reset)
1840                  * and try once more
1841                  */
1842                 i40e_msec_delay(1000);
1843                 status = i40e_update_link_info(hw);
1844         }
1845         if (status)
1846                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1847
1848         return status;
1849 }
1850
1851 /**
1852  * i40e_aq_set_mac_config
1853  * @hw: pointer to the hw struct
1854  * @max_frame_size: Maximum Frame Size to be supported by the port
1855  * @crc_en: Tell HW to append a CRC to outgoing frames
1856  * @pacing: Pacing configurations
1857  * @cmd_details: pointer to command details structure or NULL
1858  *
1859  * Configure MAC settings for frame size, jumbo frame support and the
1860  * addition of a CRC by the hardware.
1861  **/
1862 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1863                                 u16 max_frame_size,
1864                                 bool crc_en, u16 pacing,
1865                                 struct i40e_asq_cmd_details *cmd_details)
1866 {
1867         struct i40e_aq_desc desc;
1868         struct i40e_aq_set_mac_config *cmd =
1869                 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1870         enum i40e_status_code status;
1871
1872         if (max_frame_size == 0)
1873                 return I40E_ERR_PARAM;
1874
1875         i40e_fill_default_direct_cmd_desc(&desc,
1876                                           i40e_aqc_opc_set_mac_config);
1877
1878         cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1879         cmd->params = ((u8)pacing & 0x0F) << 3;
1880         if (crc_en)
1881                 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1882
1883         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1884
1885         return status;
1886 }
1887
1888 /**
1889  * i40e_aq_clear_pxe_mode
1890  * @hw: pointer to the hw struct
1891  * @cmd_details: pointer to command details structure or NULL
1892  *
1893  * Tell the firmware that the driver is taking over from PXE
1894  **/
1895 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1896                         struct i40e_asq_cmd_details *cmd_details)
1897 {
1898         enum i40e_status_code status;
1899         struct i40e_aq_desc desc;
1900         struct i40e_aqc_clear_pxe *cmd =
1901                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1902
1903         i40e_fill_default_direct_cmd_desc(&desc,
1904                                           i40e_aqc_opc_clear_pxe_mode);
1905
1906         cmd->rx_cnt = 0x2;
1907
1908         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1909
1910         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1911
1912         return status;
1913 }
1914
1915 /**
1916  * i40e_aq_set_link_restart_an
1917  * @hw: pointer to the hw struct
1918  * @enable_link: if true: enable link, if false: disable link
1919  * @cmd_details: pointer to command details structure or NULL
1920  *
1921  * Sets up the link and restarts the Auto-Negotiation over the link.
1922  **/
1923 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1924                 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1925 {
1926         struct i40e_aq_desc desc;
1927         struct i40e_aqc_set_link_restart_an *cmd =
1928                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1929         enum i40e_status_code status;
1930
1931         i40e_fill_default_direct_cmd_desc(&desc,
1932                                           i40e_aqc_opc_set_link_restart_an);
1933
1934         cmd->command = I40E_AQ_PHY_RESTART_AN;
1935         if (enable_link)
1936                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1937         else
1938                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1939
1940         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1941
1942         return status;
1943 }
1944
1945 /**
1946  * i40e_aq_get_link_info
1947  * @hw: pointer to the hw struct
1948  * @enable_lse: enable/disable LinkStatusEvent reporting
1949  * @link: pointer to link status structure - optional
1950  * @cmd_details: pointer to command details structure or NULL
1951  *
1952  * Returns the link status of the adapter.
1953  **/
1954 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1955                                 bool enable_lse, struct i40e_link_status *link,
1956                                 struct i40e_asq_cmd_details *cmd_details)
1957 {
1958         struct i40e_aq_desc desc;
1959         struct i40e_aqc_get_link_status *resp =
1960                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1961         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1962         enum i40e_status_code status;
1963         bool tx_pause, rx_pause;
1964         u16 command_flags;
1965
1966         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1967
1968         if (enable_lse)
1969                 command_flags = I40E_AQ_LSE_ENABLE;
1970         else
1971                 command_flags = I40E_AQ_LSE_DISABLE;
1972         resp->command_flags = CPU_TO_LE16(command_flags);
1973
1974         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1975
1976         if (status != I40E_SUCCESS)
1977                 goto aq_get_link_info_exit;
1978
1979         /* save off old link status information */
1980         i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1981                     sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1982
1983         /* update link status */
1984         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1985         hw->phy.media_type = i40e_get_media_type(hw);
1986         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1987         hw_link_info->link_info = resp->link_info;
1988         hw_link_info->an_info = resp->an_info;
1989         hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
1990                                                  I40E_AQ_CONFIG_FEC_RS_ENA);
1991         hw_link_info->ext_info = resp->ext_info;
1992         hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
1993         hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1994         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1995
1996         /* update fc info */
1997         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1998         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1999         if (tx_pause & rx_pause)
2000                 hw->fc.current_mode = I40E_FC_FULL;
2001         else if (tx_pause)
2002                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
2003         else if (rx_pause)
2004                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
2005         else
2006                 hw->fc.current_mode = I40E_FC_NONE;
2007
2008         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
2009                 hw_link_info->crc_enable = true;
2010         else
2011                 hw_link_info->crc_enable = false;
2012
2013         if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
2014                 hw_link_info->lse_enable = true;
2015         else
2016                 hw_link_info->lse_enable = false;
2017
2018         if ((hw->mac.type == I40E_MAC_XL710) &&
2019             (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
2020              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
2021                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
2022
2023         if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
2024             hw->aq.api_min_ver >= 7) {
2025                 hw->phy.phy_types = LE32_TO_CPU(*(__le32 *)resp->link_type);
2026                 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
2027         }
2028
2029         /* save link status information */
2030         if (link)
2031                 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
2032                             I40E_NONDMA_TO_NONDMA);
2033
2034         /* flag cleared so helper functions don't call AQ again */
2035         hw->phy.get_link_info = false;
2036
2037 aq_get_link_info_exit:
2038         return status;
2039 }
2040
2041 /**
2042  * i40e_aq_set_phy_int_mask
2043  * @hw: pointer to the hw struct
2044  * @mask: interrupt mask to be set
2045  * @cmd_details: pointer to command details structure or NULL
2046  *
2047  * Set link interrupt mask.
2048  **/
2049 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2050                                 u16 mask,
2051                                 struct i40e_asq_cmd_details *cmd_details)
2052 {
2053         struct i40e_aq_desc desc;
2054         struct i40e_aqc_set_phy_int_mask *cmd =
2055                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2056         enum i40e_status_code status;
2057
2058         i40e_fill_default_direct_cmd_desc(&desc,
2059                                           i40e_aqc_opc_set_phy_int_mask);
2060
2061         cmd->event_mask = CPU_TO_LE16(mask);
2062
2063         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2064
2065         return status;
2066 }
2067
2068 /**
2069  * i40e_aq_get_local_advt_reg
2070  * @hw: pointer to the hw struct
2071  * @advt_reg: local AN advertisement register value
2072  * @cmd_details: pointer to command details structure or NULL
2073  *
2074  * Get the Local AN advertisement register value.
2075  **/
2076 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2077                                 u64 *advt_reg,
2078                                 struct i40e_asq_cmd_details *cmd_details)
2079 {
2080         struct i40e_aq_desc desc;
2081         struct i40e_aqc_an_advt_reg *resp =
2082                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2083         enum i40e_status_code status;
2084
2085         i40e_fill_default_direct_cmd_desc(&desc,
2086                                           i40e_aqc_opc_get_local_advt_reg);
2087
2088         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2089
2090         if (status != I40E_SUCCESS)
2091                 goto aq_get_local_advt_reg_exit;
2092
2093         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2094         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2095
2096 aq_get_local_advt_reg_exit:
2097         return status;
2098 }
2099
2100 /**
2101  * i40e_aq_set_local_advt_reg
2102  * @hw: pointer to the hw struct
2103  * @advt_reg: local AN advertisement register value
2104  * @cmd_details: pointer to command details structure or NULL
2105  *
2106  * Get the Local AN advertisement register value.
2107  **/
2108 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2109                                 u64 advt_reg,
2110                                 struct i40e_asq_cmd_details *cmd_details)
2111 {
2112         struct i40e_aq_desc desc;
2113         struct i40e_aqc_an_advt_reg *cmd =
2114                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2115         enum i40e_status_code status;
2116
2117         i40e_fill_default_direct_cmd_desc(&desc,
2118                                           i40e_aqc_opc_get_local_advt_reg);
2119
2120         cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2121         cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2122
2123         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2124
2125         return status;
2126 }
2127
2128 /**
2129  * i40e_aq_get_partner_advt
2130  * @hw: pointer to the hw struct
2131  * @advt_reg: AN partner advertisement register value
2132  * @cmd_details: pointer to command details structure or NULL
2133  *
2134  * Get the link partner AN advertisement register value.
2135  **/
2136 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2137                                 u64 *advt_reg,
2138                                 struct i40e_asq_cmd_details *cmd_details)
2139 {
2140         struct i40e_aq_desc desc;
2141         struct i40e_aqc_an_advt_reg *resp =
2142                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2143         enum i40e_status_code status;
2144
2145         i40e_fill_default_direct_cmd_desc(&desc,
2146                                           i40e_aqc_opc_get_partner_advt);
2147
2148         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2149
2150         if (status != I40E_SUCCESS)
2151                 goto aq_get_partner_advt_exit;
2152
2153         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2154         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2155
2156 aq_get_partner_advt_exit:
2157         return status;
2158 }
2159
2160 /**
2161  * i40e_aq_set_lb_modes
2162  * @hw: pointer to the hw struct
2163  * @lb_modes: loopback mode to be set
2164  * @cmd_details: pointer to command details structure or NULL
2165  *
2166  * Sets loopback modes.
2167  **/
2168 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2169                                 u16 lb_modes,
2170                                 struct i40e_asq_cmd_details *cmd_details)
2171 {
2172         struct i40e_aq_desc desc;
2173         struct i40e_aqc_set_lb_mode *cmd =
2174                 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2175         enum i40e_status_code status;
2176
2177         i40e_fill_default_direct_cmd_desc(&desc,
2178                                           i40e_aqc_opc_set_lb_modes);
2179
2180         cmd->lb_mode = CPU_TO_LE16(lb_modes);
2181
2182         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2183
2184         return status;
2185 }
2186
2187 /**
2188  * i40e_aq_set_phy_debug
2189  * @hw: pointer to the hw struct
2190  * @cmd_flags: debug command flags
2191  * @cmd_details: pointer to command details structure or NULL
2192  *
2193  * Reset the external PHY.
2194  **/
2195 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2196                                 struct i40e_asq_cmd_details *cmd_details)
2197 {
2198         struct i40e_aq_desc desc;
2199         struct i40e_aqc_set_phy_debug *cmd =
2200                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2201         enum i40e_status_code status;
2202
2203         i40e_fill_default_direct_cmd_desc(&desc,
2204                                           i40e_aqc_opc_set_phy_debug);
2205
2206         cmd->command_flags = cmd_flags;
2207
2208         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2209
2210         return status;
2211 }
2212
2213 /**
2214  * i40e_aq_add_vsi
2215  * @hw: pointer to the hw struct
2216  * @vsi_ctx: pointer to a vsi context struct
2217  * @cmd_details: pointer to command details structure or NULL
2218  *
2219  * Add a VSI context to the hardware.
2220 **/
2221 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2222                                 struct i40e_vsi_context *vsi_ctx,
2223                                 struct i40e_asq_cmd_details *cmd_details)
2224 {
2225         struct i40e_aq_desc desc;
2226         struct i40e_aqc_add_get_update_vsi *cmd =
2227                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2228         struct i40e_aqc_add_get_update_vsi_completion *resp =
2229                 (struct i40e_aqc_add_get_update_vsi_completion *)
2230                 &desc.params.raw;
2231         enum i40e_status_code status;
2232
2233         i40e_fill_default_direct_cmd_desc(&desc,
2234                                           i40e_aqc_opc_add_vsi);
2235
2236         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2237         cmd->connection_type = vsi_ctx->connection_type;
2238         cmd->vf_id = vsi_ctx->vf_num;
2239         cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2240
2241         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2242
2243         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2244                                     sizeof(vsi_ctx->info), cmd_details);
2245
2246         if (status != I40E_SUCCESS)
2247                 goto aq_add_vsi_exit;
2248
2249         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2250         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2251         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2252         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2253
2254 aq_add_vsi_exit:
2255         return status;
2256 }
2257
2258 /**
2259  * i40e_aq_set_default_vsi
2260  * @hw: pointer to the hw struct
2261  * @seid: vsi number
2262  * @cmd_details: pointer to command details structure or NULL
2263  **/
2264 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2265                                 u16 seid,
2266                                 struct i40e_asq_cmd_details *cmd_details)
2267 {
2268         struct i40e_aq_desc desc;
2269         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2270                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2271                 &desc.params.raw;
2272         enum i40e_status_code status;
2273
2274         i40e_fill_default_direct_cmd_desc(&desc,
2275                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2276
2277         cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2278         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2279         cmd->seid = CPU_TO_LE16(seid);
2280
2281         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2282
2283         return status;
2284 }
2285
2286 /**
2287  * i40e_aq_clear_default_vsi
2288  * @hw: pointer to the hw struct
2289  * @seid: vsi number
2290  * @cmd_details: pointer to command details structure or NULL
2291  **/
2292 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2293                                 u16 seid,
2294                                 struct i40e_asq_cmd_details *cmd_details)
2295 {
2296         struct i40e_aq_desc desc;
2297         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2298                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2299                 &desc.params.raw;
2300         enum i40e_status_code status;
2301
2302         i40e_fill_default_direct_cmd_desc(&desc,
2303                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2304
2305         cmd->promiscuous_flags = CPU_TO_LE16(0);
2306         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2307         cmd->seid = CPU_TO_LE16(seid);
2308
2309         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2310
2311         return status;
2312 }
2313
2314 /**
2315  * i40e_aq_set_vsi_unicast_promiscuous
2316  * @hw: pointer to the hw struct
2317  * @seid: vsi number
2318  * @set: set unicast promiscuous enable/disable
2319  * @cmd_details: pointer to command details structure or NULL
2320  * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2321  **/
2322 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2323                                 u16 seid, bool set,
2324                                 struct i40e_asq_cmd_details *cmd_details,
2325                                 bool rx_only_promisc)
2326 {
2327         struct i40e_aq_desc desc;
2328         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2329                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2330         enum i40e_status_code status;
2331         u16 flags = 0;
2332
2333         i40e_fill_default_direct_cmd_desc(&desc,
2334                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2335
2336         if (set) {
2337                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2338                 if (rx_only_promisc &&
2339                     (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2340                      (hw->aq.api_maj_ver > 1)))
2341                         flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2342         }
2343
2344         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2345
2346         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2347         if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2348              (hw->aq.api_maj_ver > 1))
2349                 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2350
2351         cmd->seid = CPU_TO_LE16(seid);
2352         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2353
2354         return status;
2355 }
2356
2357 /**
2358  * i40e_aq_set_vsi_multicast_promiscuous
2359  * @hw: pointer to the hw struct
2360  * @seid: vsi number
2361  * @set: set multicast promiscuous enable/disable
2362  * @cmd_details: pointer to command details structure or NULL
2363  **/
2364 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2365                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2366 {
2367         struct i40e_aq_desc desc;
2368         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2369                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2370         enum i40e_status_code status;
2371         u16 flags = 0;
2372
2373         i40e_fill_default_direct_cmd_desc(&desc,
2374                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2375
2376         if (set)
2377                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2378
2379         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2380
2381         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2382
2383         cmd->seid = CPU_TO_LE16(seid);
2384         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2385
2386         return status;
2387 }
2388
2389 /**
2390 * i40e_aq_set_vsi_full_promiscuous
2391 * @hw: pointer to the hw struct
2392 * @seid: VSI number
2393 * @set: set promiscuous enable/disable
2394 * @cmd_details: pointer to command details structure or NULL
2395 **/
2396 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw,
2397                                 u16 seid, bool set,
2398                                 struct i40e_asq_cmd_details *cmd_details)
2399 {
2400         struct i40e_aq_desc desc;
2401         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2402                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2403         enum i40e_status_code status;
2404         u16 flags = 0;
2405
2406         i40e_fill_default_direct_cmd_desc(&desc,
2407                 i40e_aqc_opc_set_vsi_promiscuous_modes);
2408
2409         if (set)
2410                 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2411                         I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2412                         I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2413
2414         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2415
2416         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2417                                        I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2418                                        I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2419
2420         cmd->seid = CPU_TO_LE16(seid);
2421         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2422
2423         return status;
2424 }
2425
2426 /**
2427  * i40e_aq_set_vsi_mc_promisc_on_vlan
2428  * @hw: pointer to the hw struct
2429  * @seid: vsi number
2430  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2431  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2432  * @cmd_details: pointer to command details structure or NULL
2433  **/
2434 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2435                                 u16 seid, bool enable, u16 vid,
2436                                 struct i40e_asq_cmd_details *cmd_details)
2437 {
2438         struct i40e_aq_desc desc;
2439         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2440                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2441         enum i40e_status_code status;
2442         u16 flags = 0;
2443
2444         i40e_fill_default_direct_cmd_desc(&desc,
2445                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2446
2447         if (enable)
2448                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2449
2450         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2451         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2452         cmd->seid = CPU_TO_LE16(seid);
2453         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2454
2455         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2456
2457         return status;
2458 }
2459
2460 /**
2461  * i40e_aq_set_vsi_uc_promisc_on_vlan
2462  * @hw: pointer to the hw struct
2463  * @seid: vsi number
2464  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2465  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2466  * @cmd_details: pointer to command details structure or NULL
2467  **/
2468 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2469                                 u16 seid, bool enable, u16 vid,
2470                                 struct i40e_asq_cmd_details *cmd_details)
2471 {
2472         struct i40e_aq_desc desc;
2473         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2474                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2475         enum i40e_status_code status;
2476         u16 flags = 0;
2477
2478         i40e_fill_default_direct_cmd_desc(&desc,
2479                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2480
2481         if (enable)
2482                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2483
2484         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2485         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2486         cmd->seid = CPU_TO_LE16(seid);
2487         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2488
2489         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2490
2491         return status;
2492 }
2493
2494 /**
2495  * i40e_aq_set_vsi_bc_promisc_on_vlan
2496  * @hw: pointer to the hw struct
2497  * @seid: vsi number
2498  * @enable: set broadcast promiscuous enable/disable for a given VLAN
2499  * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2500  * @cmd_details: pointer to command details structure or NULL
2501  **/
2502 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2503                                 u16 seid, bool enable, u16 vid,
2504                                 struct i40e_asq_cmd_details *cmd_details)
2505 {
2506         struct i40e_aq_desc desc;
2507         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2508                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2509         enum i40e_status_code status;
2510         u16 flags = 0;
2511
2512         i40e_fill_default_direct_cmd_desc(&desc,
2513                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2514
2515         if (enable)
2516                 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2517
2518         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2519         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2520         cmd->seid = CPU_TO_LE16(seid);
2521         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2522
2523         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2524
2525         return status;
2526 }
2527
2528 /**
2529  * i40e_aq_set_vsi_broadcast
2530  * @hw: pointer to the hw struct
2531  * @seid: vsi number
2532  * @set_filter: true to set filter, false to clear filter
2533  * @cmd_details: pointer to command details structure or NULL
2534  *
2535  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2536  **/
2537 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2538                                 u16 seid, bool set_filter,
2539                                 struct i40e_asq_cmd_details *cmd_details)
2540 {
2541         struct i40e_aq_desc desc;
2542         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2543                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2544         enum i40e_status_code status;
2545
2546         i40e_fill_default_direct_cmd_desc(&desc,
2547                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2548
2549         if (set_filter)
2550                 cmd->promiscuous_flags
2551                             |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2552         else
2553                 cmd->promiscuous_flags
2554                             &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2555
2556         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2557         cmd->seid = CPU_TO_LE16(seid);
2558         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2559
2560         return status;
2561 }
2562
2563 /**
2564  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2565  * @hw: pointer to the hw struct
2566  * @seid: vsi number
2567  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2568  * @cmd_details: pointer to command details structure or NULL
2569  **/
2570 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2571                                 u16 seid, bool enable,
2572                                 struct i40e_asq_cmd_details *cmd_details)
2573 {
2574         struct i40e_aq_desc desc;
2575         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2576                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2577         enum i40e_status_code status;
2578         u16 flags = 0;
2579
2580         i40e_fill_default_direct_cmd_desc(&desc,
2581                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2582         if (enable)
2583                 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2584
2585         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2586         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2587         cmd->seid = CPU_TO_LE16(seid);
2588
2589         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2590
2591         return status;
2592 }
2593
2594 /**
2595  * i40e_get_vsi_params - get VSI configuration info
2596  * @hw: pointer to the hw struct
2597  * @vsi_ctx: pointer to a vsi context struct
2598  * @cmd_details: pointer to command details structure or NULL
2599  **/
2600 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2601                                 struct i40e_vsi_context *vsi_ctx,
2602                                 struct i40e_asq_cmd_details *cmd_details)
2603 {
2604         struct i40e_aq_desc desc;
2605         struct i40e_aqc_add_get_update_vsi *cmd =
2606                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2607         struct i40e_aqc_add_get_update_vsi_completion *resp =
2608                 (struct i40e_aqc_add_get_update_vsi_completion *)
2609                 &desc.params.raw;
2610         enum i40e_status_code status;
2611
2612         UNREFERENCED_1PARAMETER(cmd_details);
2613         i40e_fill_default_direct_cmd_desc(&desc,
2614                                           i40e_aqc_opc_get_vsi_parameters);
2615
2616         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2617
2618         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2619
2620         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2621                                     sizeof(vsi_ctx->info), NULL);
2622
2623         if (status != I40E_SUCCESS)
2624                 goto aq_get_vsi_params_exit;
2625
2626         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2627         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2628         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2629         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2630
2631 aq_get_vsi_params_exit:
2632         return status;
2633 }
2634
2635 /**
2636  * i40e_aq_update_vsi_params
2637  * @hw: pointer to the hw struct
2638  * @vsi_ctx: pointer to a vsi context struct
2639  * @cmd_details: pointer to command details structure or NULL
2640  *
2641  * Update a VSI context.
2642  **/
2643 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2644                                 struct i40e_vsi_context *vsi_ctx,
2645                                 struct i40e_asq_cmd_details *cmd_details)
2646 {
2647         struct i40e_aq_desc desc;
2648         struct i40e_aqc_add_get_update_vsi *cmd =
2649                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2650         struct i40e_aqc_add_get_update_vsi_completion *resp =
2651                 (struct i40e_aqc_add_get_update_vsi_completion *)
2652                 &desc.params.raw;
2653         enum i40e_status_code status;
2654
2655         i40e_fill_default_direct_cmd_desc(&desc,
2656                                           i40e_aqc_opc_update_vsi_parameters);
2657         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2658
2659         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2660
2661         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2662                                     sizeof(vsi_ctx->info), cmd_details);
2663
2664         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2665         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2666
2667         return status;
2668 }
2669
2670 /**
2671  * i40e_aq_get_switch_config
2672  * @hw: pointer to the hardware structure
2673  * @buf: pointer to the result buffer
2674  * @buf_size: length of input buffer
2675  * @start_seid: seid to start for the report, 0 == beginning
2676  * @cmd_details: pointer to command details structure or NULL
2677  *
2678  * Fill the buf with switch configuration returned from AdminQ command
2679  **/
2680 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2681                                 struct i40e_aqc_get_switch_config_resp *buf,
2682                                 u16 buf_size, u16 *start_seid,
2683                                 struct i40e_asq_cmd_details *cmd_details)
2684 {
2685         struct i40e_aq_desc desc;
2686         struct i40e_aqc_switch_seid *scfg =
2687                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2688         enum i40e_status_code status;
2689
2690         i40e_fill_default_direct_cmd_desc(&desc,
2691                                           i40e_aqc_opc_get_switch_config);
2692         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2693         if (buf_size > I40E_AQ_LARGE_BUF)
2694                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2695         scfg->seid = CPU_TO_LE16(*start_seid);
2696
2697         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2698         *start_seid = LE16_TO_CPU(scfg->seid);
2699
2700         return status;
2701 }
2702
2703 /**
2704  * i40e_aq_set_switch_config
2705  * @hw: pointer to the hardware structure
2706  * @flags: bit flag values to set
2707  * @valid_flags: which bit flags to set
2708  * @cmd_details: pointer to command details structure or NULL
2709  *
2710  * Set switch configuration bits
2711  **/
2712 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2713                                 u16 flags, u16 valid_flags,
2714                                 struct i40e_asq_cmd_details *cmd_details)
2715 {
2716         struct i40e_aq_desc desc;
2717         struct i40e_aqc_set_switch_config *scfg =
2718                 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2719         enum i40e_status_code status;
2720
2721         i40e_fill_default_direct_cmd_desc(&desc,
2722                                           i40e_aqc_opc_set_switch_config);
2723         scfg->flags = CPU_TO_LE16(flags);
2724         scfg->valid_flags = CPU_TO_LE16(valid_flags);
2725         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
2726                 scfg->switch_tag = CPU_TO_LE16(hw->switch_tag);
2727                 scfg->first_tag = CPU_TO_LE16(hw->first_tag);
2728                 scfg->second_tag = CPU_TO_LE16(hw->second_tag);
2729         }
2730         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2731
2732         return status;
2733 }
2734
2735 /**
2736  * i40e_aq_get_firmware_version
2737  * @hw: pointer to the hw struct
2738  * @fw_major_version: firmware major version
2739  * @fw_minor_version: firmware minor version
2740  * @fw_build: firmware build number
2741  * @api_major_version: major queue version
2742  * @api_minor_version: minor queue version
2743  * @cmd_details: pointer to command details structure or NULL
2744  *
2745  * Get the firmware version from the admin queue commands
2746  **/
2747 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2748                                 u16 *fw_major_version, u16 *fw_minor_version,
2749                                 u32 *fw_build,
2750                                 u16 *api_major_version, u16 *api_minor_version,
2751                                 struct i40e_asq_cmd_details *cmd_details)
2752 {
2753         struct i40e_aq_desc desc;
2754         struct i40e_aqc_get_version *resp =
2755                 (struct i40e_aqc_get_version *)&desc.params.raw;
2756         enum i40e_status_code status;
2757
2758         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2759
2760         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2761
2762         if (status == I40E_SUCCESS) {
2763                 if (fw_major_version != NULL)
2764                         *fw_major_version = LE16_TO_CPU(resp->fw_major);
2765                 if (fw_minor_version != NULL)
2766                         *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2767                 if (fw_build != NULL)
2768                         *fw_build = LE32_TO_CPU(resp->fw_build);
2769                 if (api_major_version != NULL)
2770                         *api_major_version = LE16_TO_CPU(resp->api_major);
2771                 if (api_minor_version != NULL)
2772                         *api_minor_version = LE16_TO_CPU(resp->api_minor);
2773
2774                 /* A workaround to fix the API version in SW */
2775                 if (api_major_version && api_minor_version &&
2776                     fw_major_version && fw_minor_version &&
2777                     ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2778                     (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2779                      (*fw_major_version > 4)))
2780                         *api_minor_version = 2;
2781         }
2782
2783         return status;
2784 }
2785
2786 /**
2787  * i40e_aq_send_driver_version
2788  * @hw: pointer to the hw struct
2789  * @dv: driver's major, minor version
2790  * @cmd_details: pointer to command details structure or NULL
2791  *
2792  * Send the driver version to the firmware
2793  **/
2794 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2795                                 struct i40e_driver_version *dv,
2796                                 struct i40e_asq_cmd_details *cmd_details)
2797 {
2798         struct i40e_aq_desc desc;
2799         struct i40e_aqc_driver_version *cmd =
2800                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2801         enum i40e_status_code status;
2802         u16 len;
2803
2804         if (dv == NULL)
2805                 return I40E_ERR_PARAM;
2806
2807         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2808
2809         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2810         cmd->driver_major_ver = dv->major_version;
2811         cmd->driver_minor_ver = dv->minor_version;
2812         cmd->driver_build_ver = dv->build_version;
2813         cmd->driver_subbuild_ver = dv->subbuild_version;
2814
2815         len = 0;
2816         while (len < sizeof(dv->driver_string) &&
2817                (dv->driver_string[len] < 0x80) &&
2818                dv->driver_string[len])
2819                 len++;
2820         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2821                                        len, cmd_details);
2822
2823         return status;
2824 }
2825
2826 /**
2827  * i40e_get_link_status - get status of the HW network link
2828  * @hw: pointer to the hw struct
2829  * @link_up: pointer to bool (true/false = linkup/linkdown)
2830  *
2831  * Variable link_up true if link is up, false if link is down.
2832  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2833  *
2834  * Side effect: LinkStatusEvent reporting becomes enabled
2835  **/
2836 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2837 {
2838         enum i40e_status_code status = I40E_SUCCESS;
2839
2840         if (hw->phy.get_link_info) {
2841                 status = i40e_update_link_info(hw);
2842
2843                 if (status != I40E_SUCCESS)
2844                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2845                                    status);
2846         }
2847
2848         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2849
2850         return status;
2851 }
2852
2853 /**
2854  * i40e_updatelink_status - update status of the HW network link
2855  * @hw: pointer to the hw struct
2856  **/
2857 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2858 {
2859         struct i40e_aq_get_phy_abilities_resp abilities;
2860         enum i40e_status_code status = I40E_SUCCESS;
2861
2862         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2863         if (status)
2864                 return status;
2865
2866         /* extra checking needed to ensure link info to user is timely */
2867         if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2868             ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2869              !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2870                 status = i40e_aq_get_phy_capabilities(hw, false, false,
2871                                                       &abilities, NULL);
2872                 if (status)
2873                         return status;
2874
2875                 hw->phy.link_info.req_fec_info =
2876                         abilities.fec_cfg_curr_mod_ext_info &
2877                         (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS);
2878
2879                 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2880                         sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2881         }
2882         return status;
2883 }
2884
2885
2886 /**
2887  * i40e_get_link_speed
2888  * @hw: pointer to the hw struct
2889  *
2890  * Returns the link speed of the adapter.
2891  **/
2892 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2893 {
2894         enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2895         enum i40e_status_code status = I40E_SUCCESS;
2896
2897         if (hw->phy.get_link_info) {
2898                 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2899
2900                 if (status != I40E_SUCCESS)
2901                         goto i40e_link_speed_exit;
2902         }
2903
2904         speed = hw->phy.link_info.link_speed;
2905
2906 i40e_link_speed_exit:
2907         return speed;
2908 }
2909
2910 /**
2911  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2912  * @hw: pointer to the hw struct
2913  * @uplink_seid: the MAC or other gizmo SEID
2914  * @downlink_seid: the VSI SEID
2915  * @enabled_tc: bitmap of TCs to be enabled
2916  * @default_port: true for default port VSI, false for control port
2917  * @veb_seid: pointer to where to put the resulting VEB SEID
2918  * @enable_stats: true to turn on VEB stats
2919  * @cmd_details: pointer to command details structure or NULL
2920  *
2921  * This asks the FW to add a VEB between the uplink and downlink
2922  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2923  **/
2924 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2925                                 u16 downlink_seid, u8 enabled_tc,
2926                                 bool default_port, u16 *veb_seid,
2927                                 bool enable_stats,
2928                                 struct i40e_asq_cmd_details *cmd_details)
2929 {
2930         struct i40e_aq_desc desc;
2931         struct i40e_aqc_add_veb *cmd =
2932                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2933         struct i40e_aqc_add_veb_completion *resp =
2934                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2935         enum i40e_status_code status;
2936         u16 veb_flags = 0;
2937
2938         /* SEIDs need to either both be set or both be 0 for floating VEB */
2939         if (!!uplink_seid != !!downlink_seid)
2940                 return I40E_ERR_PARAM;
2941
2942         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2943
2944         cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2945         cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2946         cmd->enable_tcs = enabled_tc;
2947         if (!uplink_seid)
2948                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2949         if (default_port)
2950                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2951         else
2952                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2953
2954         /* reverse logic here: set the bitflag to disable the stats */
2955         if (!enable_stats)
2956                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2957
2958         cmd->veb_flags = CPU_TO_LE16(veb_flags);
2959
2960         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2961
2962         if (!status && veb_seid)
2963                 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2964
2965         return status;
2966 }
2967
2968 /**
2969  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2970  * @hw: pointer to the hw struct
2971  * @veb_seid: the SEID of the VEB to query
2972  * @switch_id: the uplink switch id
2973  * @floating: set to true if the VEB is floating
2974  * @statistic_index: index of the stats counter block for this VEB
2975  * @vebs_used: number of VEB's used by function
2976  * @vebs_free: total VEB's not reserved by any function
2977  * @cmd_details: pointer to command details structure or NULL
2978  *
2979  * This retrieves the parameters for a particular VEB, specified by
2980  * uplink_seid, and returns them to the caller.
2981  **/
2982 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2983                                 u16 veb_seid, u16 *switch_id,
2984                                 bool *floating, u16 *statistic_index,
2985                                 u16 *vebs_used, u16 *vebs_free,
2986                                 struct i40e_asq_cmd_details *cmd_details)
2987 {
2988         struct i40e_aq_desc desc;
2989         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2990                 (struct i40e_aqc_get_veb_parameters_completion *)
2991                 &desc.params.raw;
2992         enum i40e_status_code status;
2993
2994         if (veb_seid == 0)
2995                 return I40E_ERR_PARAM;
2996
2997         i40e_fill_default_direct_cmd_desc(&desc,
2998                                           i40e_aqc_opc_get_veb_parameters);
2999         cmd_resp->seid = CPU_TO_LE16(veb_seid);
3000
3001         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3002         if (status)
3003                 goto get_veb_exit;
3004
3005         if (switch_id)
3006                 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
3007         if (statistic_index)
3008                 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
3009         if (vebs_used)
3010                 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
3011         if (vebs_free)
3012                 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
3013         if (floating) {
3014                 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
3015
3016                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
3017                         *floating = true;
3018                 else
3019                         *floating = false;
3020         }
3021
3022 get_veb_exit:
3023         return status;
3024 }
3025
3026 /**
3027  * i40e_aq_add_macvlan
3028  * @hw: pointer to the hw struct
3029  * @seid: VSI for the mac address
3030  * @mv_list: list of macvlans to be added
3031  * @count: length of the list
3032  * @cmd_details: pointer to command details structure or NULL
3033  *
3034  * Add MAC/VLAN addresses to the HW filtering
3035  **/
3036 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
3037                         struct i40e_aqc_add_macvlan_element_data *mv_list,
3038                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3039 {
3040         struct i40e_aq_desc desc;
3041         struct i40e_aqc_macvlan *cmd =
3042                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3043         enum i40e_status_code status;
3044         u16 buf_size;
3045         int i;
3046
3047         if (count == 0 || !mv_list || !hw)
3048                 return I40E_ERR_PARAM;
3049
3050         buf_size = count * sizeof(*mv_list);
3051
3052         /* prep the rest of the request */
3053         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
3054         cmd->num_addresses = CPU_TO_LE16(count);
3055         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3056         cmd->seid[1] = 0;
3057         cmd->seid[2] = 0;
3058
3059         for (i = 0; i < count; i++)
3060                 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
3061                         mv_list[i].flags |=
3062                             CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
3063
3064         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3065         if (buf_size > I40E_AQ_LARGE_BUF)
3066                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3067
3068         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3069                                        cmd_details);
3070
3071         return status;
3072 }
3073
3074 /**
3075  * i40e_aq_remove_macvlan
3076  * @hw: pointer to the hw struct
3077  * @seid: VSI for the mac address
3078  * @mv_list: list of macvlans to be removed
3079  * @count: length of the list
3080  * @cmd_details: pointer to command details structure or NULL
3081  *
3082  * Remove MAC/VLAN addresses from the HW filtering
3083  **/
3084 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
3085                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
3086                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3087 {
3088         struct i40e_aq_desc desc;
3089         struct i40e_aqc_macvlan *cmd =
3090                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3091         enum i40e_status_code status;
3092         u16 buf_size;
3093
3094         if (count == 0 || !mv_list || !hw)
3095                 return I40E_ERR_PARAM;
3096
3097         buf_size = count * sizeof(*mv_list);
3098
3099         /* prep the rest of the request */
3100         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
3101         cmd->num_addresses = CPU_TO_LE16(count);
3102         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3103         cmd->seid[1] = 0;
3104         cmd->seid[2] = 0;
3105
3106         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3107         if (buf_size > I40E_AQ_LARGE_BUF)
3108                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3109
3110         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3111                                        cmd_details);
3112
3113         return status;
3114 }
3115
3116 /**
3117  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3118  * @hw: pointer to the hw struct
3119  * @opcode: AQ opcode for add or delete mirror rule
3120  * @sw_seid: Switch SEID (to which rule refers)
3121  * @rule_type: Rule Type (ingress/egress/VLAN)
3122  * @id: Destination VSI SEID or Rule ID
3123  * @count: length of the list
3124  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3125  * @cmd_details: pointer to command details structure or NULL
3126  * @rule_id: Rule ID returned from FW
3127  * @rule_used: Number of rules used in internal switch
3128  * @rule_free: Number of rules free in internal switch
3129  *
3130  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3131  * VEBs/VEPA elements only
3132  **/
3133 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3134                         u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3135                         u16 count, __le16 *mr_list,
3136                         struct i40e_asq_cmd_details *cmd_details,
3137                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3138 {
3139         struct i40e_aq_desc desc;
3140         struct i40e_aqc_add_delete_mirror_rule *cmd =
3141                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3142         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3143         (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3144         enum i40e_status_code status;
3145         u16 buf_size;
3146
3147         buf_size = count * sizeof(*mr_list);
3148
3149         /* prep the rest of the request */
3150         i40e_fill_default_direct_cmd_desc(&desc, opcode);
3151         cmd->seid = CPU_TO_LE16(sw_seid);
3152         cmd->rule_type = CPU_TO_LE16(rule_type &
3153                                      I40E_AQC_MIRROR_RULE_TYPE_MASK);
3154         cmd->num_entries = CPU_TO_LE16(count);
3155         /* Dest VSI for add, rule_id for delete */
3156         cmd->destination = CPU_TO_LE16(id);
3157         if (mr_list) {
3158                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3159                                                 I40E_AQ_FLAG_RD));
3160                 if (buf_size > I40E_AQ_LARGE_BUF)
3161                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3162         }
3163
3164         status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3165                                        cmd_details);
3166         if (status == I40E_SUCCESS ||
3167             hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3168                 if (rule_id)
3169                         *rule_id = LE16_TO_CPU(resp->rule_id);
3170                 if (rules_used)
3171                         *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3172                 if (rules_free)
3173                         *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3174         }
3175         return status;
3176 }
3177
3178 /**
3179  * i40e_aq_add_mirrorrule - add a mirror rule
3180  * @hw: pointer to the hw struct
3181  * @sw_seid: Switch SEID (to which rule refers)
3182  * @rule_type: Rule Type (ingress/egress/VLAN)
3183  * @dest_vsi: SEID of VSI to which packets will be mirrored
3184  * @count: length of the list
3185  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3186  * @cmd_details: pointer to command details structure or NULL
3187  * @rule_id: Rule ID returned from FW
3188  * @rule_used: Number of rules used in internal switch
3189  * @rule_free: Number of rules free in internal switch
3190  *
3191  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3192  **/
3193 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3194                         u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3195                         struct i40e_asq_cmd_details *cmd_details,
3196                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3197 {
3198         if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3199             rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3200                 if (count == 0 || !mr_list)
3201                         return I40E_ERR_PARAM;
3202         }
3203
3204         return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3205                                   rule_type, dest_vsi, count, mr_list,
3206                                   cmd_details, rule_id, rules_used, rules_free);
3207 }
3208
3209 /**
3210  * i40e_aq_delete_mirrorrule - delete a mirror rule
3211  * @hw: pointer to the hw struct
3212  * @sw_seid: Switch SEID (to which rule refers)
3213  * @rule_type: Rule Type (ingress/egress/VLAN)
3214  * @count: length of the list
3215  * @rule_id: Rule ID that is returned in the receive desc as part of
3216  *              add_mirrorrule.
3217  * @mr_list: list of mirrored VLAN IDs to be removed
3218  * @cmd_details: pointer to command details structure or NULL
3219  * @rule_used: Number of rules used in internal switch
3220  * @rule_free: Number of rules free in internal switch
3221  *
3222  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3223  **/
3224 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3225                         u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3226                         struct i40e_asq_cmd_details *cmd_details,
3227                         u16 *rules_used, u16 *rules_free)
3228 {
3229         /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3230         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3231                 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3232                  * mirroring. For other rule_type, count and rule_type should
3233                  * not matter.
3234                  */
3235                 if (count == 0 || !mr_list)
3236                         return I40E_ERR_PARAM;
3237         }
3238
3239         return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3240                                   rule_type, rule_id, count, mr_list,
3241                                   cmd_details, NULL, rules_used, rules_free);
3242 }
3243
3244 /**
3245  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3246  * @hw: pointer to the hw struct
3247  * @seid: VSI for the vlan filters
3248  * @v_list: list of vlan filters to be added
3249  * @count: length of the list
3250  * @cmd_details: pointer to command details structure or NULL
3251  **/
3252 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3253                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3254                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3255 {
3256         struct i40e_aq_desc desc;
3257         struct i40e_aqc_macvlan *cmd =
3258                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3259         enum i40e_status_code status;
3260         u16 buf_size;
3261
3262         if (count == 0 || !v_list || !hw)
3263                 return I40E_ERR_PARAM;
3264
3265         buf_size = count * sizeof(*v_list);
3266
3267         /* prep the rest of the request */
3268         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3269         cmd->num_addresses = CPU_TO_LE16(count);
3270         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3271         cmd->seid[1] = 0;
3272         cmd->seid[2] = 0;
3273
3274         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3275         if (buf_size > I40E_AQ_LARGE_BUF)
3276                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3277
3278         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3279                                        cmd_details);
3280
3281         return status;
3282 }
3283
3284 /**
3285  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3286  * @hw: pointer to the hw struct
3287  * @seid: VSI for the vlan filters
3288  * @v_list: list of macvlans to be removed
3289  * @count: length of the list
3290  * @cmd_details: pointer to command details structure or NULL
3291  **/
3292 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3293                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3294                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3295 {
3296         struct i40e_aq_desc desc;
3297         struct i40e_aqc_macvlan *cmd =
3298                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3299         enum i40e_status_code status;
3300         u16 buf_size;
3301
3302         if (count == 0 || !v_list || !hw)
3303                 return I40E_ERR_PARAM;
3304
3305         buf_size = count * sizeof(*v_list);
3306
3307         /* prep the rest of the request */
3308         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3309         cmd->num_addresses = CPU_TO_LE16(count);
3310         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3311         cmd->seid[1] = 0;
3312         cmd->seid[2] = 0;
3313
3314         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3315         if (buf_size > I40E_AQ_LARGE_BUF)
3316                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3317
3318         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3319                                        cmd_details);
3320
3321         return status;
3322 }
3323
3324 /**
3325  * i40e_aq_send_msg_to_vf
3326  * @hw: pointer to the hardware structure
3327  * @vfid: vf id to send msg
3328  * @v_opcode: opcodes for VF-PF communication
3329  * @v_retval: return error code
3330  * @msg: pointer to the msg buffer
3331  * @msglen: msg length
3332  * @cmd_details: pointer to command details
3333  *
3334  * send msg to vf
3335  **/
3336 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3337                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3338                                 struct i40e_asq_cmd_details *cmd_details)
3339 {
3340         struct i40e_aq_desc desc;
3341         struct i40e_aqc_pf_vf_message *cmd =
3342                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3343         enum i40e_status_code status;
3344
3345         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3346         cmd->id = CPU_TO_LE32(vfid);
3347         desc.cookie_high = CPU_TO_LE32(v_opcode);
3348         desc.cookie_low = CPU_TO_LE32(v_retval);
3349         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3350         if (msglen) {
3351                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3352                                                 I40E_AQ_FLAG_RD));
3353                 if (msglen > I40E_AQ_LARGE_BUF)
3354                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3355                 desc.datalen = CPU_TO_LE16(msglen);
3356         }
3357         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3358
3359         return status;
3360 }
3361
3362 /**
3363  * i40e_aq_debug_read_register
3364  * @hw: pointer to the hw struct
3365  * @reg_addr: register address
3366  * @reg_val: register value
3367  * @cmd_details: pointer to command details structure or NULL
3368  *
3369  * Read the register using the admin queue commands
3370  **/
3371 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3372                                 u32 reg_addr, u64 *reg_val,
3373                                 struct i40e_asq_cmd_details *cmd_details)
3374 {
3375         struct i40e_aq_desc desc;
3376         struct i40e_aqc_debug_reg_read_write *cmd_resp =
3377                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3378         enum i40e_status_code status;
3379
3380         if (reg_val == NULL)
3381                 return I40E_ERR_PARAM;
3382
3383         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3384
3385         cmd_resp->address = CPU_TO_LE32(reg_addr);
3386
3387         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3388
3389         if (status == I40E_SUCCESS) {
3390                 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3391                            (u64)LE32_TO_CPU(cmd_resp->value_low);
3392         }
3393
3394         return status;
3395 }
3396
3397 /**
3398  * i40e_aq_debug_write_register
3399  * @hw: pointer to the hw struct
3400  * @reg_addr: register address
3401  * @reg_val: register value
3402  * @cmd_details: pointer to command details structure or NULL
3403  *
3404  * Write to a register using the admin queue commands
3405  **/
3406 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3407                                 u32 reg_addr, u64 reg_val,
3408                                 struct i40e_asq_cmd_details *cmd_details)
3409 {
3410         struct i40e_aq_desc desc;
3411         struct i40e_aqc_debug_reg_read_write *cmd =
3412                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3413         enum i40e_status_code status;
3414
3415         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3416
3417         cmd->address = CPU_TO_LE32(reg_addr);
3418         cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3419         cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3420
3421         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3422
3423         return status;
3424 }
3425
3426 /**
3427  * i40e_aq_request_resource
3428  * @hw: pointer to the hw struct
3429  * @resource: resource id
3430  * @access: access type
3431  * @sdp_number: resource number
3432  * @timeout: the maximum time in ms that the driver may hold the resource
3433  * @cmd_details: pointer to command details structure or NULL
3434  *
3435  * requests common resource using the admin queue commands
3436  **/
3437 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3438                                 enum i40e_aq_resources_ids resource,
3439                                 enum i40e_aq_resource_access_type access,
3440                                 u8 sdp_number, u64 *timeout,
3441                                 struct i40e_asq_cmd_details *cmd_details)
3442 {
3443         struct i40e_aq_desc desc;
3444         struct i40e_aqc_request_resource *cmd_resp =
3445                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3446         enum i40e_status_code status;
3447
3448         DEBUGFUNC("i40e_aq_request_resource");
3449
3450         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3451
3452         cmd_resp->resource_id = CPU_TO_LE16(resource);
3453         cmd_resp->access_type = CPU_TO_LE16(access);
3454         cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3455
3456         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3457         /* The completion specifies the maximum time in ms that the driver
3458          * may hold the resource in the Timeout field.
3459          * If the resource is held by someone else, the command completes with
3460          * busy return value and the timeout field indicates the maximum time
3461          * the current owner of the resource has to free it.
3462          */
3463         if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3464                 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3465
3466         return status;
3467 }
3468
3469 /**
3470  * i40e_aq_release_resource
3471  * @hw: pointer to the hw struct
3472  * @resource: resource id
3473  * @sdp_number: resource number
3474  * @cmd_details: pointer to command details structure or NULL
3475  *
3476  * release common resource using the admin queue commands
3477  **/
3478 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3479                                 enum i40e_aq_resources_ids resource,
3480                                 u8 sdp_number,
3481                                 struct i40e_asq_cmd_details *cmd_details)
3482 {
3483         struct i40e_aq_desc desc;
3484         struct i40e_aqc_request_resource *cmd =
3485                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3486         enum i40e_status_code status;
3487
3488         DEBUGFUNC("i40e_aq_release_resource");
3489
3490         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3491
3492         cmd->resource_id = CPU_TO_LE16(resource);
3493         cmd->resource_number = CPU_TO_LE32(sdp_number);
3494
3495         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3496
3497         return status;
3498 }
3499
3500 /**
3501  * i40e_aq_read_nvm
3502  * @hw: pointer to the hw struct
3503  * @module_pointer: module pointer location in words from the NVM beginning
3504  * @offset: byte offset from the module beginning
3505  * @length: length of the section to be read (in bytes from the offset)
3506  * @data: command buffer (size [bytes] = length)
3507  * @last_command: tells if this is the last command in a series
3508  * @cmd_details: pointer to command details structure or NULL
3509  *
3510  * Read the NVM using the admin queue commands
3511  **/
3512 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3513                                 u32 offset, u16 length, void *data,
3514                                 bool last_command,
3515                                 struct i40e_asq_cmd_details *cmd_details)
3516 {
3517         struct i40e_aq_desc desc;
3518         struct i40e_aqc_nvm_update *cmd =
3519                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3520         enum i40e_status_code status;
3521
3522         DEBUGFUNC("i40e_aq_read_nvm");
3523
3524         /* In offset the highest byte must be zeroed. */
3525         if (offset & 0xFF000000) {
3526                 status = I40E_ERR_PARAM;
3527                 goto i40e_aq_read_nvm_exit;
3528         }
3529
3530         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3531
3532         /* If this is the last command in a series, set the proper flag. */
3533         if (last_command)
3534                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3535         cmd->module_pointer = module_pointer;
3536         cmd->offset = CPU_TO_LE32(offset);
3537         cmd->length = CPU_TO_LE16(length);
3538
3539         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3540         if (length > I40E_AQ_LARGE_BUF)
3541                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3542
3543         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3544
3545 i40e_aq_read_nvm_exit:
3546         return status;
3547 }
3548
3549 /**
3550  * i40e_aq_read_nvm_config - read an nvm config block
3551  * @hw: pointer to the hw struct
3552  * @cmd_flags: NVM access admin command bits
3553  * @field_id: field or feature id
3554  * @data: buffer for result
3555  * @buf_size: buffer size
3556  * @element_count: pointer to count of elements read by FW
3557  * @cmd_details: pointer to command details structure or NULL
3558  **/
3559 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3560                                 u8 cmd_flags, u32 field_id, void *data,
3561                                 u16 buf_size, u16 *element_count,
3562                                 struct i40e_asq_cmd_details *cmd_details)
3563 {
3564         struct i40e_aq_desc desc;
3565         struct i40e_aqc_nvm_config_read *cmd =
3566                 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3567         enum i40e_status_code status;
3568
3569         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3570         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3571         if (buf_size > I40E_AQ_LARGE_BUF)
3572                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3573
3574         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3575         cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3576         if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3577                 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3578         else
3579                 cmd->element_id_msw = 0;
3580
3581         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3582
3583         if (!status && element_count)
3584                 *element_count = LE16_TO_CPU(cmd->element_count);
3585
3586         return status;
3587 }
3588
3589 /**
3590  * i40e_aq_write_nvm_config - write an nvm config block
3591  * @hw: pointer to the hw struct
3592  * @cmd_flags: NVM access admin command bits
3593  * @data: buffer for result
3594  * @buf_size: buffer size
3595  * @element_count: count of elements to be written
3596  * @cmd_details: pointer to command details structure or NULL
3597  **/
3598 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3599                                 u8 cmd_flags, void *data, u16 buf_size,
3600                                 u16 element_count,
3601                                 struct i40e_asq_cmd_details *cmd_details)
3602 {
3603         struct i40e_aq_desc desc;
3604         struct i40e_aqc_nvm_config_write *cmd =
3605                 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3606         enum i40e_status_code status;
3607
3608         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3609         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3610         if (buf_size > I40E_AQ_LARGE_BUF)
3611                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3612
3613         cmd->element_count = CPU_TO_LE16(element_count);
3614         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3615         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3616
3617         return status;
3618 }
3619
3620 /**
3621  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3622  * @hw: pointer to the hw struct
3623  * @cmd_details: pointer to command details structure or NULL
3624  **/
3625 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3626                                 void *buff, u16 buff_size,
3627                                 struct i40e_asq_cmd_details *cmd_details)
3628 {
3629         struct i40e_aq_desc desc;
3630         enum i40e_status_code status;
3631
3632         UNREFERENCED_2PARAMETER(buff, buff_size);
3633
3634         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3635         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3636         if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3637                 status = I40E_ERR_NOT_IMPLEMENTED;
3638
3639         return status;
3640 }
3641
3642 /**
3643  * i40e_aq_erase_nvm
3644  * @hw: pointer to the hw struct
3645  * @module_pointer: module pointer location in words from the NVM beginning
3646  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3647  * @length: length of the section to be erased (expressed in 4 KB)
3648  * @last_command: tells if this is the last command in a series
3649  * @cmd_details: pointer to command details structure or NULL
3650  *
3651  * Erase the NVM sector using the admin queue commands
3652  **/
3653 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3654                                 u32 offset, u16 length, bool last_command,
3655                                 struct i40e_asq_cmd_details *cmd_details)
3656 {
3657         struct i40e_aq_desc desc;
3658         struct i40e_aqc_nvm_update *cmd =
3659                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3660         enum i40e_status_code status;
3661
3662         DEBUGFUNC("i40e_aq_erase_nvm");
3663
3664         /* In offset the highest byte must be zeroed. */
3665         if (offset & 0xFF000000) {
3666                 status = I40E_ERR_PARAM;
3667                 goto i40e_aq_erase_nvm_exit;
3668         }
3669
3670         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3671
3672         /* If this is the last command in a series, set the proper flag. */
3673         if (last_command)
3674                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3675         cmd->module_pointer = module_pointer;
3676         cmd->offset = CPU_TO_LE32(offset);
3677         cmd->length = CPU_TO_LE16(length);
3678
3679         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3680
3681 i40e_aq_erase_nvm_exit:
3682         return status;
3683 }
3684
3685 /**
3686  * i40e_parse_discover_capabilities
3687  * @hw: pointer to the hw struct
3688  * @buff: pointer to a buffer containing device/function capability records
3689  * @cap_count: number of capability records in the list
3690  * @list_type_opc: type of capabilities list to parse
3691  *
3692  * Parse the device/function capabilities list.
3693  **/
3694 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3695                                      u32 cap_count,
3696                                      enum i40e_admin_queue_opc list_type_opc)
3697 {
3698         struct i40e_aqc_list_capabilities_element_resp *cap;
3699         u32 valid_functions, num_functions;
3700         u32 number, logical_id, phys_id;
3701         struct i40e_hw_capabilities *p;
3702         u8 major_rev;
3703         u32 i = 0;
3704         u16 id;
3705
3706         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3707
3708         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3709                 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3710         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3711                 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3712         else
3713                 return;
3714
3715         for (i = 0; i < cap_count; i++, cap++) {
3716                 id = LE16_TO_CPU(cap->id);
3717                 number = LE32_TO_CPU(cap->number);
3718                 logical_id = LE32_TO_CPU(cap->logical_id);
3719                 phys_id = LE32_TO_CPU(cap->phys_id);
3720                 major_rev = cap->major_rev;
3721
3722                 switch (id) {
3723                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3724                         p->switch_mode = number;
3725                         i40e_debug(hw, I40E_DEBUG_INIT,
3726                                    "HW Capability: Switch mode = %d\n",
3727                                    p->switch_mode);
3728                         break;
3729                 case I40E_AQ_CAP_ID_MNG_MODE:
3730                         p->management_mode = number;
3731                         if (major_rev > 1) {
3732                                 p->mng_protocols_over_mctp = logical_id;
3733                                 i40e_debug(hw, I40E_DEBUG_INIT,
3734                                            "HW Capability: Protocols over MCTP = %d\n",
3735                                            p->mng_protocols_over_mctp);
3736                         } else {
3737                                 p->mng_protocols_over_mctp = 0;
3738                         }
3739                         i40e_debug(hw, I40E_DEBUG_INIT,
3740                                    "HW Capability: Management Mode = %d\n",
3741                                    p->management_mode);
3742                         break;
3743                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3744                         p->npar_enable = number;
3745                         i40e_debug(hw, I40E_DEBUG_INIT,
3746                                    "HW Capability: NPAR enable = %d\n",
3747                                    p->npar_enable);
3748                         break;
3749                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3750                         p->os2bmc = number;
3751                         i40e_debug(hw, I40E_DEBUG_INIT,
3752                                    "HW Capability: OS2BMC = %d\n", p->os2bmc);
3753                         break;
3754                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3755                         p->valid_functions = number;
3756                         i40e_debug(hw, I40E_DEBUG_INIT,
3757                                    "HW Capability: Valid Functions = %d\n",
3758                                    p->valid_functions);
3759                         break;
3760                 case I40E_AQ_CAP_ID_SRIOV:
3761                         if (number == 1)
3762                                 p->sr_iov_1_1 = true;
3763                         i40e_debug(hw, I40E_DEBUG_INIT,
3764                                    "HW Capability: SR-IOV = %d\n",
3765                                    p->sr_iov_1_1);
3766                         break;
3767                 case I40E_AQ_CAP_ID_VF:
3768                         p->num_vfs = number;
3769                         p->vf_base_id = logical_id;
3770                         i40e_debug(hw, I40E_DEBUG_INIT,
3771                                    "HW Capability: VF count = %d\n",
3772                                    p->num_vfs);
3773                         i40e_debug(hw, I40E_DEBUG_INIT,
3774                                    "HW Capability: VF base_id = %d\n",
3775                                    p->vf_base_id);
3776                         break;
3777                 case I40E_AQ_CAP_ID_VMDQ:
3778                         if (number == 1)
3779                                 p->vmdq = true;
3780                         i40e_debug(hw, I40E_DEBUG_INIT,
3781                                    "HW Capability: VMDQ = %d\n", p->vmdq);
3782                         break;
3783                 case I40E_AQ_CAP_ID_8021QBG:
3784                         if (number == 1)
3785                                 p->evb_802_1_qbg = true;
3786                         i40e_debug(hw, I40E_DEBUG_INIT,
3787                                    "HW Capability: 802.1Qbg = %d\n", number);
3788                         break;
3789                 case I40E_AQ_CAP_ID_8021QBR:
3790                         if (number == 1)
3791                                 p->evb_802_1_qbh = true;
3792                         i40e_debug(hw, I40E_DEBUG_INIT,
3793                                    "HW Capability: 802.1Qbh = %d\n", number);
3794                         break;
3795                 case I40E_AQ_CAP_ID_VSI:
3796                         p->num_vsis = number;
3797                         i40e_debug(hw, I40E_DEBUG_INIT,
3798                                    "HW Capability: VSI count = %d\n",
3799                                    p->num_vsis);
3800                         break;
3801                 case I40E_AQ_CAP_ID_DCB:
3802                         if (number == 1) {
3803                                 p->dcb = true;
3804                                 p->enabled_tcmap = logical_id;
3805                                 p->maxtc = phys_id;
3806                         }
3807                         i40e_debug(hw, I40E_DEBUG_INIT,
3808                                    "HW Capability: DCB = %d\n", p->dcb);
3809                         i40e_debug(hw, I40E_DEBUG_INIT,
3810                                    "HW Capability: TC Mapping = %d\n",
3811                                    logical_id);
3812                         i40e_debug(hw, I40E_DEBUG_INIT,
3813                                    "HW Capability: TC Max = %d\n", p->maxtc);
3814                         break;
3815                 case I40E_AQ_CAP_ID_FCOE:
3816                         if (number == 1)
3817                                 p->fcoe = true;
3818                         i40e_debug(hw, I40E_DEBUG_INIT,
3819                                    "HW Capability: FCOE = %d\n", p->fcoe);
3820                         break;
3821                 case I40E_AQ_CAP_ID_ISCSI:
3822                         if (number == 1)
3823                                 p->iscsi = true;
3824                         i40e_debug(hw, I40E_DEBUG_INIT,
3825                                    "HW Capability: iSCSI = %d\n", p->iscsi);
3826                         break;
3827                 case I40E_AQ_CAP_ID_RSS:
3828                         p->rss = true;
3829                         p->rss_table_size = number;
3830                         p->rss_table_entry_width = logical_id;
3831                         i40e_debug(hw, I40E_DEBUG_INIT,
3832                                    "HW Capability: RSS = %d\n", p->rss);
3833                         i40e_debug(hw, I40E_DEBUG_INIT,
3834                                    "HW Capability: RSS table size = %d\n",
3835                                    p->rss_table_size);
3836                         i40e_debug(hw, I40E_DEBUG_INIT,
3837                                    "HW Capability: RSS table width = %d\n",
3838                                    p->rss_table_entry_width);
3839                         break;
3840                 case I40E_AQ_CAP_ID_RXQ:
3841                         p->num_rx_qp = number;
3842                         p->base_queue = phys_id;
3843                         i40e_debug(hw, I40E_DEBUG_INIT,
3844                                    "HW Capability: Rx QP = %d\n", number);
3845                         i40e_debug(hw, I40E_DEBUG_INIT,
3846                                    "HW Capability: base_queue = %d\n",
3847                                    p->base_queue);
3848                         break;
3849                 case I40E_AQ_CAP_ID_TXQ:
3850                         p->num_tx_qp = number;
3851                         p->base_queue = phys_id;
3852                         i40e_debug(hw, I40E_DEBUG_INIT,
3853                                    "HW Capability: Tx QP = %d\n", number);
3854                         i40e_debug(hw, I40E_DEBUG_INIT,
3855                                    "HW Capability: base_queue = %d\n",
3856                                    p->base_queue);
3857                         break;
3858                 case I40E_AQ_CAP_ID_MSIX:
3859                         p->num_msix_vectors = number;
3860                         i40e_debug(hw, I40E_DEBUG_INIT,
3861                                    "HW Capability: MSIX vector count = %d\n",
3862                                    p->num_msix_vectors);
3863                         break;
3864                 case I40E_AQ_CAP_ID_VF_MSIX:
3865                         p->num_msix_vectors_vf = number;
3866                         i40e_debug(hw, I40E_DEBUG_INIT,
3867                                    "HW Capability: MSIX VF vector count = %d\n",
3868                                    p->num_msix_vectors_vf);
3869                         break;
3870                 case I40E_AQ_CAP_ID_FLEX10:
3871                         if (major_rev == 1) {
3872                                 if (number == 1) {
3873                                         p->flex10_enable = true;
3874                                         p->flex10_capable = true;
3875                                 }
3876                         } else {
3877                                 /* Capability revision >= 2 */
3878                                 if (number & 1)
3879                                         p->flex10_enable = true;
3880                                 if (number & 2)
3881                                         p->flex10_capable = true;
3882                         }
3883                         p->flex10_mode = logical_id;
3884                         p->flex10_status = phys_id;
3885                         i40e_debug(hw, I40E_DEBUG_INIT,
3886                                    "HW Capability: Flex10 mode = %d\n",
3887                                    p->flex10_mode);
3888                         i40e_debug(hw, I40E_DEBUG_INIT,
3889                                    "HW Capability: Flex10 status = %d\n",
3890                                    p->flex10_status);
3891                         break;
3892                 case I40E_AQ_CAP_ID_CEM:
3893                         if (number == 1)
3894                                 p->mgmt_cem = true;
3895                         i40e_debug(hw, I40E_DEBUG_INIT,
3896                                    "HW Capability: CEM = %d\n", p->mgmt_cem);
3897                         break;
3898                 case I40E_AQ_CAP_ID_IWARP:
3899                         if (number == 1)
3900                                 p->iwarp = true;
3901                         i40e_debug(hw, I40E_DEBUG_INIT,
3902                                    "HW Capability: iWARP = %d\n", p->iwarp);
3903                         break;
3904                 case I40E_AQ_CAP_ID_LED:
3905                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3906                                 p->led[phys_id] = true;
3907                         i40e_debug(hw, I40E_DEBUG_INIT,
3908                                    "HW Capability: LED - PIN %d\n", phys_id);
3909                         break;
3910                 case I40E_AQ_CAP_ID_SDP:
3911                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3912                                 p->sdp[phys_id] = true;
3913                         i40e_debug(hw, I40E_DEBUG_INIT,
3914                                    "HW Capability: SDP - PIN %d\n", phys_id);
3915                         break;
3916                 case I40E_AQ_CAP_ID_MDIO:
3917                         if (number == 1) {
3918                                 p->mdio_port_num = phys_id;
3919                                 p->mdio_port_mode = logical_id;
3920                         }
3921                         i40e_debug(hw, I40E_DEBUG_INIT,
3922                                    "HW Capability: MDIO port number = %d\n",
3923                                    p->mdio_port_num);
3924                         i40e_debug(hw, I40E_DEBUG_INIT,
3925                                    "HW Capability: MDIO port mode = %d\n",
3926                                    p->mdio_port_mode);
3927                         break;
3928                 case I40E_AQ_CAP_ID_1588:
3929                         if (number == 1)
3930                                 p->ieee_1588 = true;
3931                         i40e_debug(hw, I40E_DEBUG_INIT,
3932                                    "HW Capability: IEEE 1588 = %d\n",
3933                                    p->ieee_1588);
3934                         break;
3935                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3936                         p->fd = true;
3937                         p->fd_filters_guaranteed = number;
3938                         p->fd_filters_best_effort = logical_id;
3939                         i40e_debug(hw, I40E_DEBUG_INIT,
3940                                    "HW Capability: Flow Director = 1\n");
3941                         i40e_debug(hw, I40E_DEBUG_INIT,
3942                                    "HW Capability: Guaranteed FD filters = %d\n",
3943                                    p->fd_filters_guaranteed);
3944                         break;
3945                 case I40E_AQ_CAP_ID_WSR_PROT:
3946                         p->wr_csr_prot = (u64)number;
3947                         p->wr_csr_prot |= (u64)logical_id << 32;
3948                         i40e_debug(hw, I40E_DEBUG_INIT,
3949                                    "HW Capability: wr_csr_prot = 0x%llX\n\n",
3950                                    (p->wr_csr_prot & 0xffff));
3951                         break;
3952                 case I40E_AQ_CAP_ID_NVM_MGMT:
3953                         if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3954                                 p->sec_rev_disabled = true;
3955                         if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3956                                 p->update_disabled = true;
3957                         break;
3958                 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3959                         hw->num_wol_proxy_filters = (u16)number;
3960                         hw->wol_proxy_vsi_seid = (u16)logical_id;
3961                         p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3962                         if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3963                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3964                         else
3965                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3966                         p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3967                         i40e_debug(hw, I40E_DEBUG_INIT,
3968                                    "HW Capability: WOL proxy filters = %d\n",
3969                                    hw->num_wol_proxy_filters);
3970                         break;
3971                 default:
3972                         break;
3973                 }
3974         }
3975
3976         if (p->fcoe)
3977                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3978
3979         /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3980         p->fcoe = false;
3981
3982         /* count the enabled ports (aka the "not disabled" ports) */
3983         hw->num_ports = 0;
3984         for (i = 0; i < 4; i++) {
3985                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3986                 u64 port_cfg = 0;
3987
3988                 /* use AQ read to get the physical register offset instead
3989                  * of the port relative offset
3990                  */
3991                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3992                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3993                         hw->num_ports++;
3994         }
3995
3996         valid_functions = p->valid_functions;
3997         num_functions = 0;
3998         while (valid_functions) {
3999                 if (valid_functions & 1)
4000                         num_functions++;
4001                 valid_functions >>= 1;
4002         }
4003
4004         /* partition id is 1-based, and functions are evenly spread
4005          * across the ports as partitions
4006          */
4007         if (hw->num_ports != 0) {
4008                 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
4009                 hw->num_partitions = num_functions / hw->num_ports;
4010         }
4011
4012         /* additional HW specific goodies that might
4013          * someday be HW version specific
4014          */
4015         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
4016 }
4017
4018 /**
4019  * i40e_aq_discover_capabilities
4020  * @hw: pointer to the hw struct
4021  * @buff: a virtual buffer to hold the capabilities
4022  * @buff_size: Size of the virtual buffer
4023  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
4024  * @list_type_opc: capabilities type to discover - pass in the command opcode
4025  * @cmd_details: pointer to command details structure or NULL
4026  *
4027  * Get the device capabilities descriptions from the firmware
4028  **/
4029 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
4030                                 void *buff, u16 buff_size, u16 *data_size,
4031                                 enum i40e_admin_queue_opc list_type_opc,
4032                                 struct i40e_asq_cmd_details *cmd_details)
4033 {
4034         struct i40e_aqc_list_capabilites *cmd;
4035         struct i40e_aq_desc desc;
4036         enum i40e_status_code status = I40E_SUCCESS;
4037
4038         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
4039
4040         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
4041                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
4042                 status = I40E_ERR_PARAM;
4043                 goto exit;
4044         }
4045
4046         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
4047
4048         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4049         if (buff_size > I40E_AQ_LARGE_BUF)
4050                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4051
4052         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4053         *data_size = LE16_TO_CPU(desc.datalen);
4054
4055         if (status)
4056                 goto exit;
4057
4058         i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
4059                                          list_type_opc);
4060
4061 exit:
4062         return status;
4063 }
4064
4065 /**
4066  * i40e_aq_update_nvm
4067  * @hw: pointer to the hw struct
4068  * @module_pointer: module pointer location in words from the NVM beginning
4069  * @offset: byte offset from the module beginning
4070  * @length: length of the section to be written (in bytes from the offset)
4071  * @data: command buffer (size [bytes] = length)
4072  * @last_command: tells if this is the last command in a series
4073  * @cmd_details: pointer to command details structure or NULL
4074  *
4075  * Update the NVM using the admin queue commands
4076  **/
4077 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
4078                                 u32 offset, u16 length, void *data,
4079                                 bool last_command,
4080                                 struct i40e_asq_cmd_details *cmd_details)
4081 {
4082         struct i40e_aq_desc desc;
4083         struct i40e_aqc_nvm_update *cmd =
4084                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
4085         enum i40e_status_code status;
4086
4087         DEBUGFUNC("i40e_aq_update_nvm");
4088
4089         /* In offset the highest byte must be zeroed. */
4090         if (offset & 0xFF000000) {
4091                 status = I40E_ERR_PARAM;
4092                 goto i40e_aq_update_nvm_exit;
4093         }
4094
4095         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4096
4097         /* If this is the last command in a series, set the proper flag. */
4098         if (last_command)
4099                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
4100         cmd->module_pointer = module_pointer;
4101         cmd->offset = CPU_TO_LE32(offset);
4102         cmd->length = CPU_TO_LE16(length);
4103
4104         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4105         if (length > I40E_AQ_LARGE_BUF)
4106                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4107
4108         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
4109
4110 i40e_aq_update_nvm_exit:
4111         return status;
4112 }
4113
4114 /**
4115  * i40e_aq_get_lldp_mib
4116  * @hw: pointer to the hw struct
4117  * @bridge_type: type of bridge requested
4118  * @mib_type: Local, Remote or both Local and Remote MIBs
4119  * @buff: pointer to a user supplied buffer to store the MIB block
4120  * @buff_size: size of the buffer (in bytes)
4121  * @local_len : length of the returned Local LLDP MIB
4122  * @remote_len: length of the returned Remote LLDP MIB
4123  * @cmd_details: pointer to command details structure or NULL
4124  *
4125  * Requests the complete LLDP MIB (entire packet).
4126  **/
4127 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4128                                 u8 mib_type, void *buff, u16 buff_size,
4129                                 u16 *local_len, u16 *remote_len,
4130                                 struct i40e_asq_cmd_details *cmd_details)
4131 {
4132         struct i40e_aq_desc desc;
4133         struct i40e_aqc_lldp_get_mib *cmd =
4134                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4135         struct i40e_aqc_lldp_get_mib *resp =
4136                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4137         enum i40e_status_code status;
4138
4139         if (buff_size == 0 || !buff)
4140                 return I40E_ERR_PARAM;
4141
4142         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4143         /* Indirect Command */
4144         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4145
4146         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4147         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4148                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4149
4150         desc.datalen = CPU_TO_LE16(buff_size);
4151
4152         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4153         if (buff_size > I40E_AQ_LARGE_BUF)
4154                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4155
4156         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4157         if (!status) {
4158                 if (local_len != NULL)
4159                         *local_len = LE16_TO_CPU(resp->local_len);
4160                 if (remote_len != NULL)
4161                         *remote_len = LE16_TO_CPU(resp->remote_len);
4162         }
4163
4164         return status;
4165 }
4166
4167  /**
4168  * i40e_aq_set_lldp_mib - Set the LLDP MIB
4169  * @hw: pointer to the hw struct
4170  * @mib_type: Local, Remote or both Local and Remote MIBs
4171  * @buff: pointer to a user supplied buffer to store the MIB block
4172  * @buff_size: size of the buffer (in bytes)
4173  * @cmd_details: pointer to command details structure or NULL
4174  *
4175  * Set the LLDP MIB.
4176  **/
4177 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4178                                 u8 mib_type, void *buff, u16 buff_size,
4179                                 struct i40e_asq_cmd_details *cmd_details)
4180 {
4181         struct i40e_aq_desc desc;
4182         struct i40e_aqc_lldp_set_local_mib *cmd =
4183                 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4184         enum i40e_status_code status;
4185
4186         if (buff_size == 0 || !buff)
4187                 return I40E_ERR_PARAM;
4188
4189         i40e_fill_default_direct_cmd_desc(&desc,
4190                                 i40e_aqc_opc_lldp_set_local_mib);
4191         /* Indirect Command */
4192         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4193         if (buff_size > I40E_AQ_LARGE_BUF)
4194                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4195         desc.datalen = CPU_TO_LE16(buff_size);
4196
4197         cmd->type = mib_type;
4198         cmd->length = CPU_TO_LE16(buff_size);
4199         cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4200         cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4201
4202         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4203         return status;
4204 }
4205
4206 /**
4207  * i40e_aq_cfg_lldp_mib_change_event
4208  * @hw: pointer to the hw struct
4209  * @enable_update: Enable or Disable event posting
4210  * @cmd_details: pointer to command details structure or NULL
4211  *
4212  * Enable or Disable posting of an event on ARQ when LLDP MIB
4213  * associated with the interface changes
4214  **/
4215 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4216                                 bool enable_update,
4217                                 struct i40e_asq_cmd_details *cmd_details)
4218 {
4219         struct i40e_aq_desc desc;
4220         struct i40e_aqc_lldp_update_mib *cmd =
4221                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4222         enum i40e_status_code status;
4223
4224         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4225
4226         if (!enable_update)
4227                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4228
4229         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4230
4231         return status;
4232 }
4233
4234 /**
4235  * i40e_aq_add_lldp_tlv
4236  * @hw: pointer to the hw struct
4237  * @bridge_type: type of bridge
4238  * @buff: buffer with TLV to add
4239  * @buff_size: length of the buffer
4240  * @tlv_len: length of the TLV to be added
4241  * @mib_len: length of the LLDP MIB returned in response
4242  * @cmd_details: pointer to command details structure or NULL
4243  *
4244  * Add the specified TLV to LLDP Local MIB for the given bridge type,
4245  * it is responsibility of the caller to make sure that the TLV is not
4246  * already present in the LLDPDU.
4247  * In return firmware will write the complete LLDP MIB with the newly
4248  * added TLV in the response buffer.
4249  **/
4250 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4251                                 void *buff, u16 buff_size, u16 tlv_len,
4252                                 u16 *mib_len,
4253                                 struct i40e_asq_cmd_details *cmd_details)
4254 {
4255         struct i40e_aq_desc desc;
4256         struct i40e_aqc_lldp_add_tlv *cmd =
4257                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4258         enum i40e_status_code status;
4259
4260         if (buff_size == 0 || !buff || tlv_len == 0)
4261                 return I40E_ERR_PARAM;
4262
4263         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4264
4265         /* Indirect Command */
4266         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4267         if (buff_size > I40E_AQ_LARGE_BUF)
4268                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4269         desc.datalen = CPU_TO_LE16(buff_size);
4270
4271         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4272                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4273         cmd->len = CPU_TO_LE16(tlv_len);
4274
4275         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4276         if (!status) {
4277                 if (mib_len != NULL)
4278                         *mib_len = LE16_TO_CPU(desc.datalen);
4279         }
4280
4281         return status;
4282 }
4283
4284 /**
4285  * i40e_aq_update_lldp_tlv
4286  * @hw: pointer to the hw struct
4287  * @bridge_type: type of bridge
4288  * @buff: buffer with TLV to update
4289  * @buff_size: size of the buffer holding original and updated TLVs
4290  * @old_len: Length of the Original TLV
4291  * @new_len: Length of the Updated TLV
4292  * @offset: offset of the updated TLV in the buff
4293  * @mib_len: length of the returned LLDP MIB
4294  * @cmd_details: pointer to command details structure or NULL
4295  *
4296  * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4297  * Firmware will place the complete LLDP MIB in response buffer with the
4298  * updated TLV.
4299  **/
4300 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4301                                 u8 bridge_type, void *buff, u16 buff_size,
4302                                 u16 old_len, u16 new_len, u16 offset,
4303                                 u16 *mib_len,
4304                                 struct i40e_asq_cmd_details *cmd_details)
4305 {
4306         struct i40e_aq_desc desc;
4307         struct i40e_aqc_lldp_update_tlv *cmd =
4308                 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4309         enum i40e_status_code status;
4310
4311         if (buff_size == 0 || !buff || offset == 0 ||
4312             old_len == 0 || new_len == 0)
4313                 return I40E_ERR_PARAM;
4314
4315         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4316
4317         /* Indirect Command */
4318         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4319         if (buff_size > I40E_AQ_LARGE_BUF)
4320                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4321         desc.datalen = CPU_TO_LE16(buff_size);
4322
4323         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4324                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4325         cmd->old_len = CPU_TO_LE16(old_len);
4326         cmd->new_offset = CPU_TO_LE16(offset);
4327         cmd->new_len = CPU_TO_LE16(new_len);
4328
4329         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4330         if (!status) {
4331                 if (mib_len != NULL)
4332                         *mib_len = LE16_TO_CPU(desc.datalen);
4333         }
4334
4335         return status;
4336 }
4337
4338 /**
4339  * i40e_aq_delete_lldp_tlv
4340  * @hw: pointer to the hw struct
4341  * @bridge_type: type of bridge
4342  * @buff: pointer to a user supplied buffer that has the TLV
4343  * @buff_size: length of the buffer
4344  * @tlv_len: length of the TLV to be deleted
4345  * @mib_len: length of the returned LLDP MIB
4346  * @cmd_details: pointer to command details structure or NULL
4347  *
4348  * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4349  * The firmware places the entire LLDP MIB in the response buffer.
4350  **/
4351 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4352                                 u8 bridge_type, void *buff, u16 buff_size,
4353                                 u16 tlv_len, u16 *mib_len,
4354                                 struct i40e_asq_cmd_details *cmd_details)
4355 {
4356         struct i40e_aq_desc desc;
4357         struct i40e_aqc_lldp_add_tlv *cmd =
4358                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4359         enum i40e_status_code status;
4360
4361         if (buff_size == 0 || !buff)
4362                 return I40E_ERR_PARAM;
4363
4364         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4365
4366         /* Indirect Command */
4367         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4368         if (buff_size > I40E_AQ_LARGE_BUF)
4369                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4370         desc.datalen = CPU_TO_LE16(buff_size);
4371         cmd->len = CPU_TO_LE16(tlv_len);
4372         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4373                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4374
4375         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4376         if (!status) {
4377                 if (mib_len != NULL)
4378                         *mib_len = LE16_TO_CPU(desc.datalen);
4379         }
4380
4381         return status;
4382 }
4383
4384 /**
4385  * i40e_aq_stop_lldp
4386  * @hw: pointer to the hw struct
4387  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4388  * @cmd_details: pointer to command details structure or NULL
4389  *
4390  * Stop or Shutdown the embedded LLDP Agent
4391  **/
4392 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4393                                 struct i40e_asq_cmd_details *cmd_details)
4394 {
4395         struct i40e_aq_desc desc;
4396         struct i40e_aqc_lldp_stop *cmd =
4397                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4398         enum i40e_status_code status;
4399
4400         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4401
4402         if (shutdown_agent)
4403                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4404
4405         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4406
4407         return status;
4408 }
4409
4410 /**
4411  * i40e_aq_start_lldp
4412  * @hw: pointer to the hw struct
4413  * @cmd_details: pointer to command details structure or NULL
4414  *
4415  * Start the embedded LLDP Agent on all ports.
4416  **/
4417 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4418                                 struct i40e_asq_cmd_details *cmd_details)
4419 {
4420         struct i40e_aq_desc desc;
4421         struct i40e_aqc_lldp_start *cmd =
4422                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4423         enum i40e_status_code status;
4424
4425         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4426
4427         cmd->command = I40E_AQ_LLDP_AGENT_START;
4428         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4429
4430         return status;
4431 }
4432
4433 /**
4434  * i40e_aq_set_dcb_parameters
4435  * @hw: pointer to the hw struct
4436  * @cmd_details: pointer to command details structure or NULL
4437  * @dcb_enable: True if DCB configuration needs to be applied
4438  *
4439  **/
4440 enum i40e_status_code
4441 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable,
4442                            struct i40e_asq_cmd_details *cmd_details)
4443 {
4444         struct i40e_aq_desc desc;
4445         struct i40e_aqc_set_dcb_parameters *cmd =
4446                 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw;
4447         enum i40e_status_code status;
4448
4449         i40e_fill_default_direct_cmd_desc(&desc,
4450                                           i40e_aqc_opc_set_dcb_parameters);
4451
4452         if (dcb_enable) {
4453                 cmd->valid_flags = I40E_DCB_VALID;
4454                 cmd->command = I40E_AQ_DCB_SET_AGENT;
4455         }
4456         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4457
4458         return status;
4459 }
4460
4461 /**
4462  * i40e_aq_get_cee_dcb_config
4463  * @hw: pointer to the hw struct
4464  * @buff: response buffer that stores CEE operational configuration
4465  * @buff_size: size of the buffer passed
4466  * @cmd_details: pointer to command details structure or NULL
4467  *
4468  * Get CEE DCBX mode operational configuration from firmware
4469  **/
4470 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4471                                 void *buff, u16 buff_size,
4472                                 struct i40e_asq_cmd_details *cmd_details)
4473 {
4474         struct i40e_aq_desc desc;
4475         enum i40e_status_code status;
4476
4477         if (buff_size == 0 || !buff)
4478                 return I40E_ERR_PARAM;
4479
4480         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4481
4482         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4483         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4484                                        cmd_details);
4485
4486         return status;
4487 }
4488
4489 /**
4490  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4491  * @hw: pointer to the hw struct
4492  * @start_agent: True if DCBx Agent needs to be Started
4493  *                              False if DCBx Agent needs to be Stopped
4494  * @cmd_details: pointer to command details structure or NULL
4495  *
4496  * Start/Stop the embedded dcbx Agent
4497  **/
4498 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4499                                 bool start_agent,
4500                                 struct i40e_asq_cmd_details *cmd_details)
4501 {
4502         struct i40e_aq_desc desc;
4503         struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4504                 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4505                                 &desc.params.raw;
4506         enum i40e_status_code status;
4507
4508         i40e_fill_default_direct_cmd_desc(&desc,
4509                                 i40e_aqc_opc_lldp_stop_start_spec_agent);
4510
4511         if (start_agent)
4512                 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4513
4514         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4515
4516         return status;
4517 }
4518
4519 /**
4520  * i40e_aq_add_udp_tunnel
4521  * @hw: pointer to the hw struct
4522  * @udp_port: the UDP port to add in Host byte order
4523  * @header_len: length of the tunneling header length in DWords
4524  * @protocol_index: protocol index type
4525  * @filter_index: pointer to filter index
4526  * @cmd_details: pointer to command details structure or NULL
4527  *
4528  * Note: Firmware expects the udp_port value to be in Little Endian format,
4529  * and this function will call CPU_TO_LE16 to convert from Host byte order to
4530  * Little Endian order.
4531  **/
4532 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4533                                 u16 udp_port, u8 protocol_index,
4534                                 u8 *filter_index,
4535                                 struct i40e_asq_cmd_details *cmd_details)
4536 {
4537         struct i40e_aq_desc desc;
4538         struct i40e_aqc_add_udp_tunnel *cmd =
4539                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4540         struct i40e_aqc_del_udp_tunnel_completion *resp =
4541                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4542         enum i40e_status_code status;
4543
4544         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4545
4546         cmd->udp_port = CPU_TO_LE16(udp_port);
4547         cmd->protocol_type = protocol_index;
4548
4549         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4550
4551         if (!status && filter_index)
4552                 *filter_index = resp->index;
4553
4554         return status;
4555 }
4556
4557 /**
4558  * i40e_aq_del_udp_tunnel
4559  * @hw: pointer to the hw struct
4560  * @index: filter index
4561  * @cmd_details: pointer to command details structure or NULL
4562  **/
4563 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4564                                 struct i40e_asq_cmd_details *cmd_details)
4565 {
4566         struct i40e_aq_desc desc;
4567         struct i40e_aqc_remove_udp_tunnel *cmd =
4568                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4569         enum i40e_status_code status;
4570
4571         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4572
4573         cmd->index = index;
4574
4575         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4576
4577         return status;
4578 }
4579
4580 /**
4581  * i40e_aq_get_switch_resource_alloc (0x0204)
4582  * @hw: pointer to the hw struct
4583  * @num_entries: pointer to u8 to store the number of resource entries returned
4584  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
4585  *        to store the resource information for all resource types.  Each
4586  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
4587  * @count: size, in bytes, of the buffer provided
4588  * @cmd_details: pointer to command details structure or NULL
4589  *
4590  * Query the resources allocated to a function.
4591  **/
4592 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4593                         u8 *num_entries,
4594                         struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4595                         u16 count,
4596                         struct i40e_asq_cmd_details *cmd_details)
4597 {
4598         struct i40e_aq_desc desc;
4599         struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4600                 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4601         enum i40e_status_code status;
4602         u16 length = count * sizeof(*buf);
4603
4604         i40e_fill_default_direct_cmd_desc(&desc,
4605                                         i40e_aqc_opc_get_switch_resource_alloc);
4606
4607         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4608         if (length > I40E_AQ_LARGE_BUF)
4609                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4610
4611         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4612
4613         if (!status && num_entries)
4614                 *num_entries = cmd_resp->num_entries;
4615
4616         return status;
4617 }
4618
4619 /**
4620  * i40e_aq_delete_element - Delete switch element
4621  * @hw: pointer to the hw struct
4622  * @seid: the SEID to delete from the switch
4623  * @cmd_details: pointer to command details structure or NULL
4624  *
4625  * This deletes a switch element from the switch.
4626  **/
4627 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4628                                 struct i40e_asq_cmd_details *cmd_details)
4629 {
4630         struct i40e_aq_desc desc;
4631         struct i40e_aqc_switch_seid *cmd =
4632                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4633         enum i40e_status_code status;
4634
4635         if (seid == 0)
4636                 return I40E_ERR_PARAM;
4637
4638         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4639
4640         cmd->seid = CPU_TO_LE16(seid);
4641
4642         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4643
4644         return status;
4645 }
4646
4647 /**
4648  * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4649  * @hw: pointer to the hw struct
4650  * @flags: component flags
4651  * @mac_seid: uplink seid (MAC SEID)
4652  * @vsi_seid: connected vsi seid
4653  * @ret_seid: seid of create pv component
4654  *
4655  * This instantiates an i40e port virtualizer with specified flags.
4656  * Depending on specified flags the port virtualizer can act as a
4657  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4658  */
4659 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4660                                        u16 mac_seid, u16 vsi_seid,
4661                                        u16 *ret_seid)
4662 {
4663         struct i40e_aq_desc desc;
4664         struct i40e_aqc_add_update_pv *cmd =
4665                 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4666         struct i40e_aqc_add_update_pv_completion *resp =
4667                 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4668         enum i40e_status_code status;
4669
4670         if (vsi_seid == 0)
4671                 return I40E_ERR_PARAM;
4672
4673         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4674         cmd->command_flags = CPU_TO_LE16(flags);
4675         cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4676         cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4677
4678         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4679         if (!status && ret_seid)
4680                 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4681
4682         return status;
4683 }
4684
4685 /**
4686  * i40e_aq_add_tag - Add an S/E-tag
4687  * @hw: pointer to the hw struct
4688  * @direct_to_queue: should s-tag direct flow to a specific queue
4689  * @vsi_seid: VSI SEID to use this tag
4690  * @tag: value of the tag
4691  * @queue_num: queue number, only valid is direct_to_queue is true
4692  * @tags_used: return value, number of tags in use by this PF
4693  * @tags_free: return value, number of unallocated tags
4694  * @cmd_details: pointer to command details structure or NULL
4695  *
4696  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4697  * the number of tags allocated by the PF, and the number of unallocated
4698  * tags available.
4699  **/
4700 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4701                                 u16 vsi_seid, u16 tag, u16 queue_num,
4702                                 u16 *tags_used, u16 *tags_free,
4703                                 struct i40e_asq_cmd_details *cmd_details)
4704 {
4705         struct i40e_aq_desc desc;
4706         struct i40e_aqc_add_tag *cmd =
4707                 (struct i40e_aqc_add_tag *)&desc.params.raw;
4708         struct i40e_aqc_add_remove_tag_completion *resp =
4709                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4710         enum i40e_status_code status;
4711
4712         if (vsi_seid == 0)
4713                 return I40E_ERR_PARAM;
4714
4715         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4716
4717         cmd->seid = CPU_TO_LE16(vsi_seid);
4718         cmd->tag = CPU_TO_LE16(tag);
4719         if (direct_to_queue) {
4720                 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4721                 cmd->queue_number = CPU_TO_LE16(queue_num);
4722         }
4723
4724         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4725
4726         if (!status) {
4727                 if (tags_used != NULL)
4728                         *tags_used = LE16_TO_CPU(resp->tags_used);
4729                 if (tags_free != NULL)
4730                         *tags_free = LE16_TO_CPU(resp->tags_free);
4731         }
4732
4733         return status;
4734 }
4735
4736 /**
4737  * i40e_aq_remove_tag - Remove an S- or E-tag
4738  * @hw: pointer to the hw struct
4739  * @vsi_seid: VSI SEID this tag is associated with
4740  * @tag: value of the S-tag to delete
4741  * @tags_used: return value, number of tags in use by this PF
4742  * @tags_free: return value, number of unallocated tags
4743  * @cmd_details: pointer to command details structure or NULL
4744  *
4745  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4746  * the number of tags allocated by the PF, and the number of unallocated
4747  * tags available.
4748  **/
4749 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4750                                 u16 tag, u16 *tags_used, u16 *tags_free,
4751                                 struct i40e_asq_cmd_details *cmd_details)
4752 {
4753         struct i40e_aq_desc desc;
4754         struct i40e_aqc_remove_tag *cmd =
4755                 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4756         struct i40e_aqc_add_remove_tag_completion *resp =
4757                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4758         enum i40e_status_code status;
4759
4760         if (vsi_seid == 0)
4761                 return I40E_ERR_PARAM;
4762
4763         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4764
4765         cmd->seid = CPU_TO_LE16(vsi_seid);
4766         cmd->tag = CPU_TO_LE16(tag);
4767
4768         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4769
4770         if (!status) {
4771                 if (tags_used != NULL)
4772                         *tags_used = LE16_TO_CPU(resp->tags_used);
4773                 if (tags_free != NULL)
4774                         *tags_free = LE16_TO_CPU(resp->tags_free);
4775         }
4776
4777         return status;
4778 }
4779
4780 /**
4781  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4782  * @hw: pointer to the hw struct
4783  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4784  * @etag: value of E-tag to add
4785  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4786  * @buf: address of indirect buffer
4787  * @tags_used: return value, number of E-tags in use by this port
4788  * @tags_free: return value, number of unallocated M-tags
4789  * @cmd_details: pointer to command details structure or NULL
4790  *
4791  * This associates a multicast E-tag to a port virtualizer.  It will return
4792  * the number of tags allocated by the PF, and the number of unallocated
4793  * tags available.
4794  *
4795  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4796  * num_tags_in_buf long.
4797  **/
4798 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4799                                 u16 etag, u8 num_tags_in_buf, void *buf,
4800                                 u16 *tags_used, u16 *tags_free,
4801                                 struct i40e_asq_cmd_details *cmd_details)
4802 {
4803         struct i40e_aq_desc desc;
4804         struct i40e_aqc_add_remove_mcast_etag *cmd =
4805                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4806         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4807            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4808         enum i40e_status_code status;
4809         u16 length = sizeof(u16) * num_tags_in_buf;
4810
4811         if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4812                 return I40E_ERR_PARAM;
4813
4814         i40e_fill_default_direct_cmd_desc(&desc,
4815                                           i40e_aqc_opc_add_multicast_etag);
4816
4817         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4818         cmd->etag = CPU_TO_LE16(etag);
4819         cmd->num_unicast_etags = num_tags_in_buf;
4820
4821         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4822         if (length > I40E_AQ_LARGE_BUF)
4823                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4824
4825         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4826
4827         if (!status) {
4828                 if (tags_used != NULL)
4829                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4830                 if (tags_free != NULL)
4831                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4832         }
4833
4834         return status;
4835 }
4836
4837 /**
4838  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4839  * @hw: pointer to the hw struct
4840  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4841  * @etag: value of the E-tag to remove
4842  * @tags_used: return value, number of tags in use by this port
4843  * @tags_free: return value, number of unallocated tags
4844  * @cmd_details: pointer to command details structure or NULL
4845  *
4846  * This deletes an E-tag from the port virtualizer.  It will return
4847  * the number of tags allocated by the port, and the number of unallocated
4848  * tags available.
4849  **/
4850 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4851                                 u16 etag, u16 *tags_used, u16 *tags_free,
4852                                 struct i40e_asq_cmd_details *cmd_details)
4853 {
4854         struct i40e_aq_desc desc;
4855         struct i40e_aqc_add_remove_mcast_etag *cmd =
4856                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4857         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4858            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4859         enum i40e_status_code status;
4860
4861
4862         if (pv_seid == 0)
4863                 return I40E_ERR_PARAM;
4864
4865         i40e_fill_default_direct_cmd_desc(&desc,
4866                                           i40e_aqc_opc_remove_multicast_etag);
4867
4868         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4869         cmd->etag = CPU_TO_LE16(etag);
4870
4871         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4872
4873         if (!status) {
4874                 if (tags_used != NULL)
4875                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4876                 if (tags_free != NULL)
4877                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4878         }
4879
4880         return status;
4881 }
4882
4883 /**
4884  * i40e_aq_update_tag - Update an S/E-tag
4885  * @hw: pointer to the hw struct
4886  * @vsi_seid: VSI SEID using this S-tag
4887  * @old_tag: old tag value
4888  * @new_tag: new tag value
4889  * @tags_used: return value, number of tags in use by this PF
4890  * @tags_free: return value, number of unallocated tags
4891  * @cmd_details: pointer to command details structure or NULL
4892  *
4893  * This updates the value of the tag currently attached to this VSI
4894  * in the switch complex.  It will return the number of tags allocated
4895  * by the PF, and the number of unallocated tags available.
4896  **/
4897 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4898                                 u16 old_tag, u16 new_tag, u16 *tags_used,
4899                                 u16 *tags_free,
4900                                 struct i40e_asq_cmd_details *cmd_details)
4901 {
4902         struct i40e_aq_desc desc;
4903         struct i40e_aqc_update_tag *cmd =
4904                 (struct i40e_aqc_update_tag *)&desc.params.raw;
4905         struct i40e_aqc_update_tag_completion *resp =
4906                 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4907         enum i40e_status_code status;
4908
4909         if (vsi_seid == 0)
4910                 return I40E_ERR_PARAM;
4911
4912         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4913
4914         cmd->seid = CPU_TO_LE16(vsi_seid);
4915         cmd->old_tag = CPU_TO_LE16(old_tag);
4916         cmd->new_tag = CPU_TO_LE16(new_tag);
4917
4918         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4919
4920         if (!status) {
4921                 if (tags_used != NULL)
4922                         *tags_used = LE16_TO_CPU(resp->tags_used);
4923                 if (tags_free != NULL)
4924                         *tags_free = LE16_TO_CPU(resp->tags_free);
4925         }
4926
4927         return status;
4928 }
4929
4930 /**
4931  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4932  * @hw: pointer to the hw struct
4933  * @tcmap: TC map for request/release any ignore PFC condition
4934  * @request: request or release ignore PFC condition
4935  * @tcmap_ret: return TCs for which PFC is currently ignored
4936  * @cmd_details: pointer to command details structure or NULL
4937  *
4938  * This sends out request/release to ignore PFC condition for a TC.
4939  * It will return the TCs for which PFC is currently ignored.
4940  **/
4941 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4942                                 bool request, u8 *tcmap_ret,
4943                                 struct i40e_asq_cmd_details *cmd_details)
4944 {
4945         struct i40e_aq_desc desc;
4946         struct i40e_aqc_pfc_ignore *cmd_resp =
4947                 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4948         enum i40e_status_code status;
4949
4950         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4951
4952         if (request)
4953                 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4954
4955         cmd_resp->tc_bitmap = tcmap;
4956
4957         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4958
4959         if (!status) {
4960                 if (tcmap_ret != NULL)
4961                         *tcmap_ret = cmd_resp->tc_bitmap;
4962         }
4963
4964         return status;
4965 }
4966
4967 /**
4968  * i40e_aq_dcb_updated - DCB Updated Command
4969  * @hw: pointer to the hw struct
4970  * @cmd_details: pointer to command details structure or NULL
4971  *
4972  * When LLDP is handled in PF this command is used by the PF
4973  * to notify EMP that a DCB setting is modified.
4974  * When LLDP is handled in EMP this command is used by the PF
4975  * to notify EMP whenever one of the following parameters get
4976  * modified:
4977  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4978  *   - PCIRTT in PRTDCB_GENC.PCIRTT
4979  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4980  * EMP will return when the shared RPB settings have been
4981  * recomputed and modified. The retval field in the descriptor
4982  * will be set to 0 when RPB is modified.
4983  **/
4984 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4985                                 struct i40e_asq_cmd_details *cmd_details)
4986 {
4987         struct i40e_aq_desc desc;
4988         enum i40e_status_code status;
4989
4990         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4991
4992         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4993
4994         return status;
4995 }
4996
4997 /**
4998  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4999  * @hw: pointer to the hw struct
5000  * @seid: defines the SEID of the switch for which the stats are requested
5001  * @vlan_id: the VLAN ID for which the statistics are requested
5002  * @stat_index: index of the statistics counters block assigned to this VLAN
5003  * @cmd_details: pointer to command details structure or NULL
5004  *
5005  * XL710 supports 128 smonVlanStats counters.This command is used to
5006  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
5007  * switch.
5008  **/
5009 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
5010                                 u16 vlan_id, u16 *stat_index,
5011                                 struct i40e_asq_cmd_details *cmd_details)
5012 {
5013         struct i40e_aq_desc desc;
5014         struct i40e_aqc_add_remove_statistics *cmd_resp =
5015                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5016         enum i40e_status_code status;
5017
5018         if ((seid == 0) || (stat_index == NULL))
5019                 return I40E_ERR_PARAM;
5020
5021         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
5022
5023         cmd_resp->seid = CPU_TO_LE16(seid);
5024         cmd_resp->vlan = CPU_TO_LE16(vlan_id);
5025
5026         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5027
5028         if (!status && stat_index)
5029                 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
5030
5031         return status;
5032 }
5033
5034 /**
5035  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
5036  * @hw: pointer to the hw struct
5037  * @seid: defines the SEID of the switch for which the stats are requested
5038  * @vlan_id: the VLAN ID for which the statistics are requested
5039  * @stat_index: index of the statistics counters block assigned to this VLAN
5040  * @cmd_details: pointer to command details structure or NULL
5041  *
5042  * XL710 supports 128 smonVlanStats counters.This command is used to
5043  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
5044  * switch.
5045  **/
5046 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
5047                                 u16 vlan_id, u16 stat_index,
5048                                 struct i40e_asq_cmd_details *cmd_details)
5049 {
5050         struct i40e_aq_desc desc;
5051         struct i40e_aqc_add_remove_statistics *cmd =
5052                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5053         enum i40e_status_code status;
5054
5055         if (seid == 0)
5056                 return I40E_ERR_PARAM;
5057
5058         i40e_fill_default_direct_cmd_desc(&desc,
5059                                           i40e_aqc_opc_remove_statistics);
5060
5061         cmd->seid = CPU_TO_LE16(seid);
5062         cmd->vlan  = CPU_TO_LE16(vlan_id);
5063         cmd->stat_index = CPU_TO_LE16(stat_index);
5064
5065         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5066
5067         return status;
5068 }
5069
5070 /**
5071  * i40e_aq_set_port_parameters - set physical port parameters.
5072  * @hw: pointer to the hw struct
5073  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
5074  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
5075  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
5076  * @double_vlan: if set double VLAN is enabled
5077  * @cmd_details: pointer to command details structure or NULL
5078  **/
5079 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
5080                                 u16 bad_frame_vsi, bool save_bad_pac,
5081                                 bool pad_short_pac, bool double_vlan,
5082                                 struct i40e_asq_cmd_details *cmd_details)
5083 {
5084         struct i40e_aqc_set_port_parameters *cmd;
5085         enum i40e_status_code status;
5086         struct i40e_aq_desc desc;
5087         u16 command_flags = 0;
5088
5089         cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
5090
5091         i40e_fill_default_direct_cmd_desc(&desc,
5092                                           i40e_aqc_opc_set_port_parameters);
5093
5094         cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
5095         if (save_bad_pac)
5096                 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
5097         if (pad_short_pac)
5098                 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
5099         if (double_vlan)
5100                 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
5101         cmd->command_flags = CPU_TO_LE16(command_flags);
5102
5103         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5104
5105         return status;
5106 }
5107
5108 /**
5109  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
5110  * @hw: pointer to the hw struct
5111  * @seid: seid for the physical port/switching component/vsi
5112  * @buff: Indirect buffer to hold data parameters and response
5113  * @buff_size: Indirect buffer size
5114  * @opcode: Tx scheduler AQ command opcode
5115  * @cmd_details: pointer to command details structure or NULL
5116  *
5117  * Generic command handler for Tx scheduler AQ commands
5118  **/
5119 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
5120                                 void *buff, u16 buff_size,
5121                                  enum i40e_admin_queue_opc opcode,
5122                                 struct i40e_asq_cmd_details *cmd_details)
5123 {
5124         struct i40e_aq_desc desc;
5125         struct i40e_aqc_tx_sched_ind *cmd =
5126                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
5127         enum i40e_status_code status;
5128         bool cmd_param_flag = false;
5129
5130         switch (opcode) {
5131         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
5132         case i40e_aqc_opc_configure_vsi_tc_bw:
5133         case i40e_aqc_opc_enable_switching_comp_ets:
5134         case i40e_aqc_opc_modify_switching_comp_ets:
5135         case i40e_aqc_opc_disable_switching_comp_ets:
5136         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
5137         case i40e_aqc_opc_configure_switching_comp_bw_config:
5138                 cmd_param_flag = true;
5139                 break;
5140         case i40e_aqc_opc_query_vsi_bw_config:
5141         case i40e_aqc_opc_query_vsi_ets_sla_config:
5142         case i40e_aqc_opc_query_switching_comp_ets_config:
5143         case i40e_aqc_opc_query_port_ets_config:
5144         case i40e_aqc_opc_query_switching_comp_bw_config:
5145                 cmd_param_flag = false;
5146                 break;
5147         default:
5148                 return I40E_ERR_PARAM;
5149         }
5150
5151         i40e_fill_default_direct_cmd_desc(&desc, opcode);
5152
5153         /* Indirect command */
5154         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5155         if (cmd_param_flag)
5156                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5157         if (buff_size > I40E_AQ_LARGE_BUF)
5158                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5159
5160         desc.datalen = CPU_TO_LE16(buff_size);
5161
5162         cmd->vsi_seid = CPU_TO_LE16(seid);
5163
5164         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5165
5166         return status;
5167 }
5168
5169 /**
5170  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5171  * @hw: pointer to the hw struct
5172  * @seid: VSI seid
5173  * @credit: BW limit credits (0 = disabled)
5174  * @max_credit: Max BW limit credits
5175  * @cmd_details: pointer to command details structure or NULL
5176  **/
5177 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5178                                 u16 seid, u16 credit, u8 max_credit,
5179                                 struct i40e_asq_cmd_details *cmd_details)
5180 {
5181         struct i40e_aq_desc desc;
5182         struct i40e_aqc_configure_vsi_bw_limit *cmd =
5183                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5184         enum i40e_status_code status;
5185
5186         i40e_fill_default_direct_cmd_desc(&desc,
5187                                           i40e_aqc_opc_configure_vsi_bw_limit);
5188
5189         cmd->vsi_seid = CPU_TO_LE16(seid);
5190         cmd->credit = CPU_TO_LE16(credit);
5191         cmd->max_credit = max_credit;
5192
5193         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5194
5195         return status;
5196 }
5197
5198 /**
5199  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5200  * @hw: pointer to the hw struct
5201  * @seid: switching component seid
5202  * @credit: BW limit credits (0 = disabled)
5203  * @max_bw: Max BW limit credits
5204  * @cmd_details: pointer to command details structure or NULL
5205  **/
5206 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5207                                 u16 seid, u16 credit, u8 max_bw,
5208                                 struct i40e_asq_cmd_details *cmd_details)
5209 {
5210         struct i40e_aq_desc desc;
5211         struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5212           (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5213         enum i40e_status_code status;
5214
5215         i40e_fill_default_direct_cmd_desc(&desc,
5216                                 i40e_aqc_opc_configure_switching_comp_bw_limit);
5217
5218         cmd->seid = CPU_TO_LE16(seid);
5219         cmd->credit = CPU_TO_LE16(credit);
5220         cmd->max_bw = max_bw;
5221
5222         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5223
5224         return status;
5225 }
5226
5227 /**
5228  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5229  * @hw: pointer to the hw struct
5230  * @seid: VSI seid
5231  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5232  * @cmd_details: pointer to command details structure or NULL
5233  **/
5234 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5235                         u16 seid,
5236                         struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5237                         struct i40e_asq_cmd_details *cmd_details)
5238 {
5239         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5240                                     i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5241                                     cmd_details);
5242 }
5243
5244 /**
5245  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5246  * @hw: pointer to the hw struct
5247  * @seid: VSI seid
5248  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5249  * @cmd_details: pointer to command details structure or NULL
5250  **/
5251 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5252                         u16 seid,
5253                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5254                         struct i40e_asq_cmd_details *cmd_details)
5255 {
5256         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5257                                     i40e_aqc_opc_configure_vsi_tc_bw,
5258                                     cmd_details);
5259 }
5260
5261 /**
5262  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5263  * @hw: pointer to the hw struct
5264  * @seid: seid of the switching component connected to Physical Port
5265  * @ets_data: Buffer holding ETS parameters
5266  * @cmd_details: pointer to command details structure or NULL
5267  **/
5268 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5269                 u16 seid,
5270                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5271                 enum i40e_admin_queue_opc opcode,
5272                 struct i40e_asq_cmd_details *cmd_details)
5273 {
5274         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5275                                     sizeof(*ets_data), opcode, cmd_details);
5276 }
5277
5278 /**
5279  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5280  * @hw: pointer to the hw struct
5281  * @seid: seid of the switching component
5282  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5283  * @cmd_details: pointer to command details structure or NULL
5284  **/
5285 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5286         u16 seid,
5287         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5288         struct i40e_asq_cmd_details *cmd_details)
5289 {
5290         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5291                             i40e_aqc_opc_configure_switching_comp_bw_config,
5292                             cmd_details);
5293 }
5294
5295 /**
5296  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5297  * @hw: pointer to the hw struct
5298  * @seid: seid of the switching component
5299  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5300  * @cmd_details: pointer to command details structure or NULL
5301  **/
5302 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5303         struct i40e_hw *hw, u16 seid,
5304         struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5305         struct i40e_asq_cmd_details *cmd_details)
5306 {
5307         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5308                             i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5309                             cmd_details);
5310 }
5311
5312 /**
5313  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5314  * @hw: pointer to the hw struct
5315  * @seid: seid of the VSI
5316  * @bw_data: Buffer to hold VSI BW configuration
5317  * @cmd_details: pointer to command details structure or NULL
5318  **/
5319 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5320                         u16 seid,
5321                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5322                         struct i40e_asq_cmd_details *cmd_details)
5323 {
5324         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5325                                     i40e_aqc_opc_query_vsi_bw_config,
5326                                     cmd_details);
5327 }
5328
5329 /**
5330  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5331  * @hw: pointer to the hw struct
5332  * @seid: seid of the VSI
5333  * @bw_data: Buffer to hold VSI BW configuration per TC
5334  * @cmd_details: pointer to command details structure or NULL
5335  **/
5336 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5337                         u16 seid,
5338                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5339                         struct i40e_asq_cmd_details *cmd_details)
5340 {
5341         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5342                                     i40e_aqc_opc_query_vsi_ets_sla_config,
5343                                     cmd_details);
5344 }
5345
5346 /**
5347  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5348  * @hw: pointer to the hw struct
5349  * @seid: seid of the switching component
5350  * @bw_data: Buffer to hold switching component's per TC BW config
5351  * @cmd_details: pointer to command details structure or NULL
5352  **/
5353 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5354                 u16 seid,
5355                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5356                 struct i40e_asq_cmd_details *cmd_details)
5357 {
5358         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5359                                    i40e_aqc_opc_query_switching_comp_ets_config,
5360                                    cmd_details);
5361 }
5362
5363 /**
5364  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5365  * @hw: pointer to the hw struct
5366  * @seid: seid of the VSI or switching component connected to Physical Port
5367  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5368  * @cmd_details: pointer to command details structure or NULL
5369  **/
5370 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5371                         u16 seid,
5372                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
5373                         struct i40e_asq_cmd_details *cmd_details)
5374 {
5375         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5376                                     i40e_aqc_opc_query_port_ets_config,
5377                                     cmd_details);
5378 }
5379
5380 /**
5381  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5382  * @hw: pointer to the hw struct
5383  * @seid: seid of the switching component
5384  * @bw_data: Buffer to hold switching component's BW configuration
5385  * @cmd_details: pointer to command details structure or NULL
5386  **/
5387 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5388                 u16 seid,
5389                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5390                 struct i40e_asq_cmd_details *cmd_details)
5391 {
5392         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5393                                     i40e_aqc_opc_query_switching_comp_bw_config,
5394                                     cmd_details);
5395 }
5396
5397 /**
5398  * i40e_validate_filter_settings
5399  * @hw: pointer to the hardware structure
5400  * @settings: Filter control settings
5401  *
5402  * Check and validate the filter control settings passed.
5403  * The function checks for the valid filter/context sizes being
5404  * passed for FCoE and PE.
5405  *
5406  * Returns I40E_SUCCESS if the values passed are valid and within
5407  * range else returns an error.
5408  **/
5409 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5410                                 struct i40e_filter_control_settings *settings)
5411 {
5412         u32 fcoe_cntx_size, fcoe_filt_size;
5413         u32 pe_cntx_size, pe_filt_size;
5414         u32 fcoe_fmax;
5415
5416         u32 val;
5417
5418         /* Validate FCoE settings passed */
5419         switch (settings->fcoe_filt_num) {
5420         case I40E_HASH_FILTER_SIZE_1K:
5421         case I40E_HASH_FILTER_SIZE_2K:
5422         case I40E_HASH_FILTER_SIZE_4K:
5423         case I40E_HASH_FILTER_SIZE_8K:
5424         case I40E_HASH_FILTER_SIZE_16K:
5425         case I40E_HASH_FILTER_SIZE_32K:
5426                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5427                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5428                 break;
5429         default:
5430                 return I40E_ERR_PARAM;
5431         }
5432
5433         switch (settings->fcoe_cntx_num) {
5434         case I40E_DMA_CNTX_SIZE_512:
5435         case I40E_DMA_CNTX_SIZE_1K:
5436         case I40E_DMA_CNTX_SIZE_2K:
5437         case I40E_DMA_CNTX_SIZE_4K:
5438                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5439                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5440                 break;
5441         default:
5442                 return I40E_ERR_PARAM;
5443         }
5444
5445         /* Validate PE settings passed */
5446         switch (settings->pe_filt_num) {
5447         case I40E_HASH_FILTER_SIZE_1K:
5448         case I40E_HASH_FILTER_SIZE_2K:
5449         case I40E_HASH_FILTER_SIZE_4K:
5450         case I40E_HASH_FILTER_SIZE_8K:
5451         case I40E_HASH_FILTER_SIZE_16K:
5452         case I40E_HASH_FILTER_SIZE_32K:
5453         case I40E_HASH_FILTER_SIZE_64K:
5454         case I40E_HASH_FILTER_SIZE_128K:
5455         case I40E_HASH_FILTER_SIZE_256K:
5456         case I40E_HASH_FILTER_SIZE_512K:
5457         case I40E_HASH_FILTER_SIZE_1M:
5458                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5459                 pe_filt_size <<= (u32)settings->pe_filt_num;
5460                 break;
5461         default:
5462                 return I40E_ERR_PARAM;
5463         }
5464
5465         switch (settings->pe_cntx_num) {
5466         case I40E_DMA_CNTX_SIZE_512:
5467         case I40E_DMA_CNTX_SIZE_1K:
5468         case I40E_DMA_CNTX_SIZE_2K:
5469         case I40E_DMA_CNTX_SIZE_4K:
5470         case I40E_DMA_CNTX_SIZE_8K:
5471         case I40E_DMA_CNTX_SIZE_16K:
5472         case I40E_DMA_CNTX_SIZE_32K:
5473         case I40E_DMA_CNTX_SIZE_64K:
5474         case I40E_DMA_CNTX_SIZE_128K:
5475         case I40E_DMA_CNTX_SIZE_256K:
5476                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5477                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5478                 break;
5479         default:
5480                 return I40E_ERR_PARAM;
5481         }
5482
5483         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5484         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5485         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5486                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5487         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
5488                 return I40E_ERR_INVALID_SIZE;
5489
5490         return I40E_SUCCESS;
5491 }
5492
5493 /**
5494  * i40e_set_filter_control
5495  * @hw: pointer to the hardware structure
5496  * @settings: Filter control settings
5497  *
5498  * Set the Queue Filters for PE/FCoE and enable filters required
5499  * for a single PF. It is expected that these settings are programmed
5500  * at the driver initialization time.
5501  **/
5502 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5503                                 struct i40e_filter_control_settings *settings)
5504 {
5505         enum i40e_status_code ret = I40E_SUCCESS;
5506         u32 hash_lut_size = 0;
5507         u32 val;
5508
5509         if (!settings)
5510                 return I40E_ERR_PARAM;
5511
5512         /* Validate the input settings */
5513         ret = i40e_validate_filter_settings(hw, settings);
5514         if (ret)
5515                 return ret;
5516
5517         /* Read the PF Queue Filter control register */
5518         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5519
5520         /* Program required PE hash buckets for the PF */
5521         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5522         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5523                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5524         /* Program required PE contexts for the PF */
5525         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5526         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5527                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5528
5529         /* Program required FCoE hash buckets for the PF */
5530         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5531         val |= ((u32)settings->fcoe_filt_num <<
5532                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5533                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5534         /* Program required FCoE DDP contexts for the PF */
5535         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5536         val |= ((u32)settings->fcoe_cntx_num <<
5537                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5538                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5539
5540         /* Program Hash LUT size for the PF */
5541         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5542         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5543                 hash_lut_size = 1;
5544         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5545                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5546
5547         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5548         if (settings->enable_fdir)
5549                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5550         if (settings->enable_ethtype)
5551                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5552         if (settings->enable_macvlan)
5553                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5554
5555         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5556
5557         return I40E_SUCCESS;
5558 }
5559
5560 /**
5561  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5562  * @hw: pointer to the hw struct
5563  * @mac_addr: MAC address to use in the filter
5564  * @ethtype: Ethertype to use in the filter
5565  * @flags: Flags that needs to be applied to the filter
5566  * @vsi_seid: seid of the control VSI
5567  * @queue: VSI queue number to send the packet to
5568  * @is_add: Add control packet filter if True else remove
5569  * @stats: Structure to hold information on control filter counts
5570  * @cmd_details: pointer to command details structure or NULL
5571  *
5572  * This command will Add or Remove control packet filter for a control VSI.
5573  * In return it will update the total number of perfect filter count in
5574  * the stats member.
5575  **/
5576 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5577                                 u8 *mac_addr, u16 ethtype, u16 flags,
5578                                 u16 vsi_seid, u16 queue, bool is_add,
5579                                 struct i40e_control_filter_stats *stats,
5580                                 struct i40e_asq_cmd_details *cmd_details)
5581 {
5582         struct i40e_aq_desc desc;
5583         struct i40e_aqc_add_remove_control_packet_filter *cmd =
5584                 (struct i40e_aqc_add_remove_control_packet_filter *)
5585                 &desc.params.raw;
5586         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5587                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5588                 &desc.params.raw;
5589         enum i40e_status_code status;
5590
5591         if (vsi_seid == 0)
5592                 return I40E_ERR_PARAM;
5593
5594         if (is_add) {
5595                 i40e_fill_default_direct_cmd_desc(&desc,
5596                                 i40e_aqc_opc_add_control_packet_filter);
5597                 cmd->queue = CPU_TO_LE16(queue);
5598         } else {
5599                 i40e_fill_default_direct_cmd_desc(&desc,
5600                                 i40e_aqc_opc_remove_control_packet_filter);
5601         }
5602
5603         if (mac_addr)
5604                 i40e_memcpy(cmd->mac, mac_addr, ETH_ALEN,
5605                             I40E_NONDMA_TO_NONDMA);
5606
5607         cmd->etype = CPU_TO_LE16(ethtype);
5608         cmd->flags = CPU_TO_LE16(flags);
5609         cmd->seid = CPU_TO_LE16(vsi_seid);
5610
5611         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5612
5613         if (!status && stats) {
5614                 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5615                 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5616                 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5617                 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5618         }
5619
5620         return status;
5621 }
5622
5623 /**
5624  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5625  * @hw: pointer to the hw struct
5626  * @seid: VSI seid to add ethertype filter from
5627  **/
5628 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5629 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5630                                                     u16 seid)
5631 {
5632         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5633                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5634                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5635         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5636         enum i40e_status_code status;
5637
5638         status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5639                                                        seid, 0, true, NULL,
5640                                                        NULL);
5641         if (status)
5642                 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5643 }
5644
5645 /**
5646  * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5647  * @filters: list of cloud filters
5648  * @filter_count: length of list
5649  *
5650  * There's an issue in the device where the Geneve VNI layout needs
5651  * to be shifted 1 byte over from the VxLAN VNI
5652  **/
5653 STATIC void i40e_fix_up_geneve_vni(
5654         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5655         u8 filter_count)
5656 {
5657         struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters;
5658         int i;
5659
5660         for (i = 0; i < filter_count; i++) {
5661                 u16 tnl_type;
5662                 u32 ti;
5663
5664                 tnl_type = (LE16_TO_CPU(f[i].flags) &
5665                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5666                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5667                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5668                         ti = LE32_TO_CPU(f[i].tenant_id);
5669                         f[i].tenant_id = CPU_TO_LE32(ti << 8);
5670                 }
5671         }
5672 }
5673
5674 /**
5675  * i40e_aq_add_cloud_filters
5676  * @hw: pointer to the hardware structure
5677  * @seid: VSI seid to add cloud filters from
5678  * @filters: Buffer which contains the filters to be added
5679  * @filter_count: number of filters contained in the buffer
5680  *
5681  * Set the cloud filters for a given VSI.  The contents of the
5682  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5683  * in by the caller of the function.
5684  *
5685  **/
5686 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5687         u16 seid,
5688         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5689         u8 filter_count)
5690 {
5691         struct i40e_aq_desc desc;
5692         struct i40e_aqc_add_remove_cloud_filters *cmd =
5693         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5694         enum i40e_status_code status;
5695         u16 buff_len;
5696
5697         i40e_fill_default_direct_cmd_desc(&desc,
5698                                           i40e_aqc_opc_add_cloud_filters);
5699
5700         buff_len = filter_count * sizeof(*filters);
5701         desc.datalen = CPU_TO_LE16(buff_len);
5702         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5703         cmd->num_filters = filter_count;
5704         cmd->seid = CPU_TO_LE16(seid);
5705
5706         i40e_fix_up_geneve_vni(filters, filter_count);
5707
5708         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5709
5710         return status;
5711 }
5712
5713 /**
5714  * i40e_aq_add_cloud_filters_big_buffer
5715  * @hw: pointer to the hardware structure
5716  * @seid: VSI seid to add cloud filters from
5717  * @filters: Buffer which contains the filters in big buffer to be added
5718  * @filter_count: number of filters contained in the buffer
5719  *
5720  * Set the cloud filters for a given VSI.  The contents of the
5721  * i40e_aqc_add_rm_cloud_filt_elem_ext are filled in by the caller of
5722  * the function.
5723  *
5724  **/
5725 enum i40e_status_code i40e_aq_add_cloud_filters_big_buffer(struct i40e_hw *hw,
5726         u16 seid,
5727         struct i40e_aqc_add_rm_cloud_filt_elem_ext *filters,
5728         u8 filter_count)
5729 {
5730         struct i40e_aq_desc desc;
5731         struct i40e_aqc_add_remove_cloud_filters *cmd =
5732         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5733         enum i40e_status_code status;
5734         u16 buff_len;
5735         int i;
5736
5737         i40e_fill_default_direct_cmd_desc(&desc,
5738                                           i40e_aqc_opc_add_cloud_filters);
5739
5740         buff_len = filter_count * sizeof(*filters);
5741         desc.datalen = CPU_TO_LE16(buff_len);
5742         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5743         cmd->num_filters = filter_count;
5744         cmd->seid = CPU_TO_LE16(seid);
5745         cmd->big_buffer_flag = I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER;
5746
5747         /* adjust Geneve VNI for HW issue */
5748         for (i = 0; i < filter_count; i++) {
5749                 u16 tnl_type;
5750                 u32 ti;
5751
5752                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5753                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5754                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5755                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5756                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5757                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5758                 }
5759         }
5760
5761         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5762
5763         return status;
5764 }
5765
5766 /**
5767  * i40e_aq_remove_cloud_filters
5768  * @hw: pointer to the hardware structure
5769  * @seid: VSI seid to remove cloud filters from
5770  * @filters: Buffer which contains the filters to be removed
5771  * @filter_count: number of filters contained in the buffer
5772  *
5773  * Remove the cloud filters for a given VSI.  The contents of the
5774  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5775  * in by the caller of the function.
5776  *
5777  **/
5778 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5779         u16 seid,
5780         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5781         u8 filter_count)
5782 {
5783         struct i40e_aq_desc desc;
5784         struct i40e_aqc_add_remove_cloud_filters *cmd =
5785         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5786         enum i40e_status_code status;
5787         u16 buff_len;
5788
5789         i40e_fill_default_direct_cmd_desc(&desc,
5790                                           i40e_aqc_opc_remove_cloud_filters);
5791
5792         buff_len = filter_count * sizeof(*filters);
5793         desc.datalen = CPU_TO_LE16(buff_len);
5794         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5795         cmd->num_filters = filter_count;
5796         cmd->seid = CPU_TO_LE16(seid);
5797
5798         i40e_fix_up_geneve_vni(filters, filter_count);
5799
5800         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5801
5802         return status;
5803 }
5804
5805 /**
5806  * i40e_aq_remove_cloud_filters_big_buffer
5807  * @hw: pointer to the hardware structure
5808  * @seid: VSI seid to remove cloud filters from
5809  * @filters: Buffer which contains the filters in big buffer to be removed
5810  * @filter_count: number of filters contained in the buffer
5811  *
5812  * Remove the cloud filters for a given VSI.  The contents of the
5813  * i40e_aqc_add_rm_cloud_filt_elem_ext are filled in by the caller of
5814  * the function.
5815  *
5816  **/
5817 enum i40e_status_code i40e_aq_remove_cloud_filters_big_buffer(
5818         struct i40e_hw *hw,
5819         u16 seid,
5820         struct i40e_aqc_add_rm_cloud_filt_elem_ext *filters,
5821         u8 filter_count)
5822 {
5823         struct i40e_aq_desc desc;
5824         struct i40e_aqc_add_remove_cloud_filters *cmd =
5825         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5826         enum i40e_status_code status;
5827         u16 buff_len;
5828         int i;
5829
5830         i40e_fill_default_direct_cmd_desc(&desc,
5831                                           i40e_aqc_opc_remove_cloud_filters);
5832
5833         buff_len = filter_count * sizeof(*filters);
5834         desc.datalen = CPU_TO_LE16(buff_len);
5835         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5836         cmd->num_filters = filter_count;
5837         cmd->seid = CPU_TO_LE16(seid);
5838         cmd->big_buffer_flag = I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER;
5839
5840         /* adjust Geneve VNI for HW issue */
5841         for (i = 0; i < filter_count; i++) {
5842                 u16 tnl_type;
5843                 u32 ti;
5844
5845                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5846                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5847                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5848                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5849                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5850                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5851                 }
5852         }
5853
5854         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5855
5856         return status;
5857 }
5858
5859 /**
5860  * i40e_aq_replace_cloud_filters - Replace cloud filter command
5861  * @hw: pointer to the hw struct
5862  * @filters: pointer to the i40e_aqc_replace_cloud_filter_cmd struct
5863  * @cmd_buf: pointer to the i40e_aqc_replace_cloud_filter_cmd_buf struct
5864  *
5865  **/
5866 enum
5867 i40e_status_code i40e_aq_replace_cloud_filters(struct i40e_hw *hw,
5868         struct i40e_aqc_replace_cloud_filters_cmd *filters,
5869         struct i40e_aqc_replace_cloud_filters_cmd_buf *cmd_buf)
5870 {
5871         struct i40e_aq_desc desc;
5872         struct i40e_aqc_replace_cloud_filters_cmd *cmd =
5873                 (struct i40e_aqc_replace_cloud_filters_cmd *)&desc.params.raw;
5874         enum i40e_status_code status = I40E_SUCCESS;
5875         int i = 0;
5876
5877         i40e_fill_default_direct_cmd_desc(&desc,
5878                                           i40e_aqc_opc_replace_cloud_filters);
5879
5880         desc.datalen = CPU_TO_LE16(32);
5881         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5882         cmd->old_filter_type = filters->old_filter_type;
5883         cmd->new_filter_type = filters->new_filter_type;
5884         cmd->valid_flags = filters->valid_flags;
5885         cmd->tr_bit = filters->tr_bit;
5886
5887         status = i40e_asq_send_command(hw, &desc, cmd_buf,
5888                 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf),  NULL);
5889
5890         /* for get cloud filters command */
5891         for (i = 0; i < 32; i += 4) {
5892                 cmd_buf->filters[i / 4].filter_type = cmd_buf->data[i];
5893                 cmd_buf->filters[i / 4].input[0] = cmd_buf->data[i + 1];
5894                 cmd_buf->filters[i / 4].input[1] = cmd_buf->data[i + 2];
5895                 cmd_buf->filters[i / 4].input[2] = cmd_buf->data[i + 3];
5896         }
5897
5898         return status;
5899 }
5900
5901
5902 /**
5903  * i40e_aq_alternate_write
5904  * @hw: pointer to the hardware structure
5905  * @reg_addr0: address of first dword to be read
5906  * @reg_val0: value to be written under 'reg_addr0'
5907  * @reg_addr1: address of second dword to be read
5908  * @reg_val1: value to be written under 'reg_addr1'
5909  *
5910  * Write one or two dwords to alternate structure. Fields are indicated
5911  * by 'reg_addr0' and 'reg_addr1' register numbers.
5912  *
5913  **/
5914 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5915                                 u32 reg_addr0, u32 reg_val0,
5916                                 u32 reg_addr1, u32 reg_val1)
5917 {
5918         struct i40e_aq_desc desc;
5919         struct i40e_aqc_alternate_write *cmd_resp =
5920                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5921         enum i40e_status_code status;
5922
5923         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5924         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5925         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5926         cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5927         cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5928
5929         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5930
5931         return status;
5932 }
5933
5934 /**
5935  * i40e_aq_alternate_write_indirect
5936  * @hw: pointer to the hardware structure
5937  * @addr: address of a first register to be modified
5938  * @dw_count: number of alternate structure fields to write
5939  * @buffer: pointer to the command buffer
5940  *
5941  * Write 'dw_count' dwords from 'buffer' to alternate structure
5942  * starting at 'addr'.
5943  *
5944  **/
5945 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5946                                 u32 addr, u32 dw_count, void *buffer)
5947 {
5948         struct i40e_aq_desc desc;
5949         struct i40e_aqc_alternate_ind_write *cmd_resp =
5950                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5951         enum i40e_status_code status;
5952
5953         if (buffer == NULL)
5954                 return I40E_ERR_PARAM;
5955
5956         /* Indirect command */
5957         i40e_fill_default_direct_cmd_desc(&desc,
5958                                          i40e_aqc_opc_alternate_write_indirect);
5959
5960         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5961         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5962         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5963                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5964
5965         cmd_resp->address = CPU_TO_LE32(addr);
5966         cmd_resp->length = CPU_TO_LE32(dw_count);
5967
5968         status = i40e_asq_send_command(hw, &desc, buffer,
5969                                        I40E_LO_DWORD(4*dw_count), NULL);
5970
5971         return status;
5972 }
5973
5974 /**
5975  * i40e_aq_alternate_read
5976  * @hw: pointer to the hardware structure
5977  * @reg_addr0: address of first dword to be read
5978  * @reg_val0: pointer for data read from 'reg_addr0'
5979  * @reg_addr1: address of second dword to be read
5980  * @reg_val1: pointer for data read from 'reg_addr1'
5981  *
5982  * Read one or two dwords from alternate structure. Fields are indicated
5983  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5984  * is not passed then only register at 'reg_addr0' is read.
5985  *
5986  **/
5987 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5988                                 u32 reg_addr0, u32 *reg_val0,
5989                                 u32 reg_addr1, u32 *reg_val1)
5990 {
5991         struct i40e_aq_desc desc;
5992         struct i40e_aqc_alternate_write *cmd_resp =
5993                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5994         enum i40e_status_code status;
5995
5996         if (reg_val0 == NULL)
5997                 return I40E_ERR_PARAM;
5998
5999         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
6000         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
6001         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
6002
6003         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6004
6005         if (status == I40E_SUCCESS) {
6006                 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
6007
6008                 if (reg_val1 != NULL)
6009                         *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
6010         }
6011
6012         return status;
6013 }
6014
6015 /**
6016  * i40e_aq_alternate_read_indirect
6017  * @hw: pointer to the hardware structure
6018  * @addr: address of the alternate structure field
6019  * @dw_count: number of alternate structure fields to read
6020  * @buffer: pointer to the command buffer
6021  *
6022  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
6023  * place them in 'buffer'. The buffer should be allocated by caller.
6024  *
6025  **/
6026 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
6027                                 u32 addr, u32 dw_count, void *buffer)
6028 {
6029         struct i40e_aq_desc desc;
6030         struct i40e_aqc_alternate_ind_write *cmd_resp =
6031                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
6032         enum i40e_status_code status;
6033
6034         if (buffer == NULL)
6035                 return I40E_ERR_PARAM;
6036
6037         /* Indirect command */
6038         i40e_fill_default_direct_cmd_desc(&desc,
6039                 i40e_aqc_opc_alternate_read_indirect);
6040
6041         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6042         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6043         if (dw_count > (I40E_AQ_LARGE_BUF/4))
6044                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6045
6046         cmd_resp->address = CPU_TO_LE32(addr);
6047         cmd_resp->length = CPU_TO_LE32(dw_count);
6048
6049         status = i40e_asq_send_command(hw, &desc, buffer,
6050                                        I40E_LO_DWORD(4*dw_count), NULL);
6051
6052         return status;
6053 }
6054
6055 /**
6056  *  i40e_aq_alternate_clear
6057  *  @hw: pointer to the HW structure.
6058  *
6059  *  Clear the alternate structures of the port from which the function
6060  *  is called.
6061  *
6062  **/
6063 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
6064 {
6065         struct i40e_aq_desc desc;
6066         enum i40e_status_code status;
6067
6068         i40e_fill_default_direct_cmd_desc(&desc,
6069                                           i40e_aqc_opc_alternate_clear_port);
6070
6071         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6072
6073         return status;
6074 }
6075
6076 /**
6077  *  i40e_aq_alternate_write_done
6078  *  @hw: pointer to the HW structure.
6079  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
6080  *  @reset_needed: indicates the SW should trigger GLOBAL reset
6081  *
6082  *  Indicates to the FW that alternate structures have been changed.
6083  *
6084  **/
6085 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
6086                 u8 bios_mode, bool *reset_needed)
6087 {
6088         struct i40e_aq_desc desc;
6089         struct i40e_aqc_alternate_write_done *cmd =
6090                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6091         enum i40e_status_code status;
6092
6093         if (reset_needed == NULL)
6094                 return I40E_ERR_PARAM;
6095
6096         i40e_fill_default_direct_cmd_desc(&desc,
6097                                           i40e_aqc_opc_alternate_write_done);
6098
6099         cmd->cmd_flags = CPU_TO_LE16(bios_mode);
6100
6101         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6102         if (!status && reset_needed)
6103                 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
6104                                  I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
6105
6106         return status;
6107 }
6108
6109 /**
6110  *  i40e_aq_set_oem_mode
6111  *  @hw: pointer to the HW structure.
6112  *  @oem_mode: the OEM mode to be used
6113  *
6114  *  Sets the device to a specific operating mode. Currently the only supported
6115  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
6116  *
6117  **/
6118 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
6119                 u8 oem_mode)
6120 {
6121         struct i40e_aq_desc desc;
6122         struct i40e_aqc_alternate_write_done *cmd =
6123                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6124         enum i40e_status_code status;
6125
6126         i40e_fill_default_direct_cmd_desc(&desc,
6127                                           i40e_aqc_opc_alternate_set_mode);
6128
6129         cmd->cmd_flags = CPU_TO_LE16(oem_mode);
6130
6131         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6132
6133         return status;
6134 }
6135
6136 /**
6137  * i40e_aq_resume_port_tx
6138  * @hw: pointer to the hardware structure
6139  * @cmd_details: pointer to command details structure or NULL
6140  *
6141  * Resume port's Tx traffic
6142  **/
6143 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
6144                                 struct i40e_asq_cmd_details *cmd_details)
6145 {
6146         struct i40e_aq_desc desc;
6147         enum i40e_status_code status;
6148
6149         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
6150
6151         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6152
6153         return status;
6154 }
6155
6156 /**
6157  * i40e_set_pci_config_data - store PCI bus info
6158  * @hw: pointer to hardware structure
6159  * @link_status: the link status word from PCI config space
6160  *
6161  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
6162  **/
6163 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
6164 {
6165         hw->bus.type = i40e_bus_type_pci_express;
6166
6167         switch (link_status & I40E_PCI_LINK_WIDTH) {
6168         case I40E_PCI_LINK_WIDTH_1:
6169                 hw->bus.width = i40e_bus_width_pcie_x1;
6170                 break;
6171         case I40E_PCI_LINK_WIDTH_2:
6172                 hw->bus.width = i40e_bus_width_pcie_x2;
6173                 break;
6174         case I40E_PCI_LINK_WIDTH_4:
6175                 hw->bus.width = i40e_bus_width_pcie_x4;
6176                 break;
6177         case I40E_PCI_LINK_WIDTH_8:
6178                 hw->bus.width = i40e_bus_width_pcie_x8;
6179                 break;
6180         default:
6181                 hw->bus.width = i40e_bus_width_unknown;
6182                 break;
6183         }
6184
6185         switch (link_status & I40E_PCI_LINK_SPEED) {
6186         case I40E_PCI_LINK_SPEED_2500:
6187                 hw->bus.speed = i40e_bus_speed_2500;
6188                 break;
6189         case I40E_PCI_LINK_SPEED_5000:
6190                 hw->bus.speed = i40e_bus_speed_5000;
6191                 break;
6192         case I40E_PCI_LINK_SPEED_8000:
6193                 hw->bus.speed = i40e_bus_speed_8000;
6194                 break;
6195         default:
6196                 hw->bus.speed = i40e_bus_speed_unknown;
6197                 break;
6198         }
6199 }
6200
6201 /**
6202  * i40e_aq_debug_dump
6203  * @hw: pointer to the hardware structure
6204  * @cluster_id: specific cluster to dump
6205  * @table_id: table id within cluster
6206  * @start_index: index of line in the block to read
6207  * @buff_size: dump buffer size
6208  * @buff: dump buffer
6209  * @ret_buff_size: actual buffer size returned
6210  * @ret_next_table: next block to read
6211  * @ret_next_index: next index to read
6212  *
6213  * Dump internal FW/HW data for debug purposes.
6214  *
6215  **/
6216 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
6217                                 u8 table_id, u32 start_index, u16 buff_size,
6218                                 void *buff, u16 *ret_buff_size,
6219                                 u8 *ret_next_table, u32 *ret_next_index,
6220                                 struct i40e_asq_cmd_details *cmd_details)
6221 {
6222         struct i40e_aq_desc desc;
6223         struct i40e_aqc_debug_dump_internals *cmd =
6224                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6225         struct i40e_aqc_debug_dump_internals *resp =
6226                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6227         enum i40e_status_code status;
6228
6229         if (buff_size == 0 || !buff)
6230                 return I40E_ERR_PARAM;
6231
6232         i40e_fill_default_direct_cmd_desc(&desc,
6233                                           i40e_aqc_opc_debug_dump_internals);
6234         /* Indirect Command */
6235         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6236         if (buff_size > I40E_AQ_LARGE_BUF)
6237                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6238
6239         cmd->cluster_id = cluster_id;
6240         cmd->table_id = table_id;
6241         cmd->idx = CPU_TO_LE32(start_index);
6242
6243         desc.datalen = CPU_TO_LE16(buff_size);
6244
6245         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
6246         if (!status) {
6247                 if (ret_buff_size != NULL)
6248                         *ret_buff_size = LE16_TO_CPU(desc.datalen);
6249                 if (ret_next_table != NULL)
6250                         *ret_next_table = resp->table_id;
6251                 if (ret_next_index != NULL)
6252                         *ret_next_index = LE32_TO_CPU(resp->idx);
6253         }
6254
6255         return status;
6256 }
6257
6258 /**
6259  * i40e_read_bw_from_alt_ram
6260  * @hw: pointer to the hardware structure
6261  * @max_bw: pointer for max_bw read
6262  * @min_bw: pointer for min_bw read
6263  * @min_valid: pointer for bool that is true if min_bw is a valid value
6264  * @max_valid: pointer for bool that is true if max_bw is a valid value
6265  *
6266  * Read bw from the alternate ram for the given pf
6267  **/
6268 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
6269                                         u32 *max_bw, u32 *min_bw,
6270                                         bool *min_valid, bool *max_valid)
6271 {
6272         enum i40e_status_code status;
6273         u32 max_bw_addr, min_bw_addr;
6274
6275         /* Calculate the address of the min/max bw registers */
6276         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6277                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
6278                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6279         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6280                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
6281                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6282
6283         /* Read the bandwidths from alt ram */
6284         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
6285                                         min_bw_addr, min_bw);
6286
6287         if (*min_bw & I40E_ALT_BW_VALID_MASK)
6288                 *min_valid = true;
6289         else
6290                 *min_valid = false;
6291
6292         if (*max_bw & I40E_ALT_BW_VALID_MASK)
6293                 *max_valid = true;
6294         else
6295                 *max_valid = false;
6296
6297         return status;
6298 }
6299
6300 /**
6301  * i40e_aq_configure_partition_bw
6302  * @hw: pointer to the hardware structure
6303  * @bw_data: Buffer holding valid pfs and bw limits
6304  * @cmd_details: pointer to command details
6305  *
6306  * Configure partitions guaranteed/max bw
6307  **/
6308 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6309                         struct i40e_aqc_configure_partition_bw_data *bw_data,
6310                         struct i40e_asq_cmd_details *cmd_details)
6311 {
6312         enum i40e_status_code status;
6313         struct i40e_aq_desc desc;
6314         u16 bwd_size = sizeof(*bw_data);
6315
6316         i40e_fill_default_direct_cmd_desc(&desc,
6317                                 i40e_aqc_opc_configure_partition_bw);
6318
6319         /* Indirect command */
6320         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6321         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6322
6323         desc.datalen = CPU_TO_LE16(bwd_size);
6324
6325         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6326
6327         return status;
6328 }
6329
6330 /**
6331  * i40e_read_phy_register_clause22
6332  * @hw: pointer to the HW structure
6333  * @reg: register address in the page
6334  * @phy_adr: PHY address on MDIO interface
6335  * @value: PHY register value
6336  *
6337  * Reads specified PHY register value
6338  **/
6339 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
6340                                         u16 reg, u8 phy_addr, u16 *value)
6341 {
6342         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6343         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6344         u32 command = 0;
6345         u16 retry = 1000;
6346
6347         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6348                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6349                   (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
6350                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6351                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6352         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6353         do {
6354                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6355                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6356                         status = I40E_SUCCESS;
6357                         break;
6358                 }
6359                 i40e_usec_delay(10);
6360                 retry--;
6361         } while (retry);
6362
6363         if (status) {
6364                 i40e_debug(hw, I40E_DEBUG_PHY,
6365                            "PHY: Can't write command to external PHY.\n");
6366         } else {
6367                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6368                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6369                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6370         }
6371
6372         return status;
6373 }
6374
6375 /**
6376  * i40e_write_phy_register_clause22
6377  * @hw: pointer to the HW structure
6378  * @reg: register address in the page
6379  * @phy_adr: PHY address on MDIO interface
6380  * @value: PHY register value
6381  *
6382  * Writes specified PHY register value
6383  **/
6384 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6385                                         u16 reg, u8 phy_addr, u16 value)
6386 {
6387         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6388         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6389         u32 command  = 0;
6390         u16 retry = 1000;
6391
6392         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6393         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6394
6395         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6396                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6397                   (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6398                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6399                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6400
6401         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6402         do {
6403                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6404                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6405                         status = I40E_SUCCESS;
6406                         break;
6407                 }
6408                 i40e_usec_delay(10);
6409                 retry--;
6410         } while (retry);
6411
6412         return status;
6413 }
6414
6415 /**
6416  * i40e_read_phy_register_clause45
6417  * @hw: pointer to the HW structure
6418  * @page: registers page number
6419  * @reg: register address in the page
6420  * @phy_adr: PHY address on MDIO interface
6421  * @value: PHY register value
6422  *
6423  * Reads specified PHY register value
6424  **/
6425 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6426                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6427 {
6428         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6429         u32 command  = 0;
6430         u16 retry = 1000;
6431         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6432
6433         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6434                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6435                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6436                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6437                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6438                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6439                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6440         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6441         do {
6442                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6443                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6444                         status = I40E_SUCCESS;
6445                         break;
6446                 }
6447                 i40e_usec_delay(10);
6448                 retry--;
6449         } while (retry);
6450
6451         if (status) {
6452                 i40e_debug(hw, I40E_DEBUG_PHY,
6453                            "PHY: Can't write command to external PHY.\n");
6454                 goto phy_read_end;
6455         }
6456
6457         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6458                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6459                   (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6460                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6461                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6462                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6463         status = I40E_ERR_TIMEOUT;
6464         retry = 1000;
6465         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6466         do {
6467                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6468                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6469                         status = I40E_SUCCESS;
6470                         break;
6471                 }
6472                 i40e_usec_delay(10);
6473                 retry--;
6474         } while (retry);
6475
6476         if (!status) {
6477                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6478                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6479                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6480         } else {
6481                 i40e_debug(hw, I40E_DEBUG_PHY,
6482                            "PHY: Can't read register value from external PHY.\n");
6483         }
6484
6485 phy_read_end:
6486         return status;
6487 }
6488
6489 /**
6490  * i40e_write_phy_register_clause45
6491  * @hw: pointer to the HW structure
6492  * @page: registers page number
6493  * @reg: register address in the page
6494  * @phy_adr: PHY address on MDIO interface
6495  * @value: PHY register value
6496  *
6497  * Writes value to specified PHY register
6498  **/
6499 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6500                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6501 {
6502         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6503         u32 command  = 0;
6504         u16 retry = 1000;
6505         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6506
6507         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6508                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6509                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6510                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6511                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6512                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6513                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6514         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6515         do {
6516                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6517                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6518                         status = I40E_SUCCESS;
6519                         break;
6520                 }
6521                 i40e_usec_delay(10);
6522                 retry--;
6523         } while (retry);
6524         if (status) {
6525                 i40e_debug(hw, I40E_DEBUG_PHY,
6526                            "PHY: Can't write command to external PHY.\n");
6527                 goto phy_write_end;
6528         }
6529
6530         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6531         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6532
6533         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6534                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6535                   (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6536                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6537                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6538                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6539         status = I40E_ERR_TIMEOUT;
6540         retry = 1000;
6541         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6542         do {
6543                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6544                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6545                         status = I40E_SUCCESS;
6546                         break;
6547                 }
6548                 i40e_usec_delay(10);
6549                 retry--;
6550         } while (retry);
6551
6552 phy_write_end:
6553         return status;
6554 }
6555
6556 /**
6557  * i40e_write_phy_register
6558  * @hw: pointer to the HW structure
6559  * @page: registers page number
6560  * @reg: register address in the page
6561  * @phy_adr: PHY address on MDIO interface
6562  * @value: PHY register value
6563  *
6564  * Writes value to specified PHY register
6565  **/
6566 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6567                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6568 {
6569         enum i40e_status_code status;
6570
6571         switch (hw->device_id) {
6572         case I40E_DEV_ID_1G_BASE_T_X722:
6573                 status = i40e_write_phy_register_clause22(hw,
6574                         reg, phy_addr, value);
6575                 break;
6576         case I40E_DEV_ID_10G_BASE_T:
6577         case I40E_DEV_ID_10G_BASE_T4:
6578         case I40E_DEV_ID_10G_BASE_T_X722:
6579         case I40E_DEV_ID_25G_B:
6580         case I40E_DEV_ID_25G_SFP28:
6581                 status = i40e_write_phy_register_clause45(hw,
6582                         page, reg, phy_addr, value);
6583                 break;
6584         default:
6585                 status = I40E_ERR_UNKNOWN_PHY;
6586                 break;
6587         }
6588
6589         return status;
6590 }
6591
6592 /**
6593  * i40e_read_phy_register
6594  * @hw: pointer to the HW structure
6595  * @page: registers page number
6596  * @reg: register address in the page
6597  * @phy_adr: PHY address on MDIO interface
6598  * @value: PHY register value
6599  *
6600  * Reads specified PHY register value
6601  **/
6602 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6603                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6604 {
6605         enum i40e_status_code status;
6606
6607         switch (hw->device_id) {
6608         case I40E_DEV_ID_1G_BASE_T_X722:
6609                 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6610                                                          value);
6611                 break;
6612         case I40E_DEV_ID_10G_BASE_T:
6613         case I40E_DEV_ID_10G_BASE_T4:
6614         case I40E_DEV_ID_10G_BASE_T_X722:
6615         case I40E_DEV_ID_25G_B:
6616         case I40E_DEV_ID_25G_SFP28:
6617                 status = i40e_read_phy_register_clause45(hw, page, reg,
6618                                                          phy_addr, value);
6619                 break;
6620         default:
6621                 status = I40E_ERR_UNKNOWN_PHY;
6622                 break;
6623         }
6624
6625         return status;
6626 }
6627
6628 /**
6629  * i40e_get_phy_address
6630  * @hw: pointer to the HW structure
6631  * @dev_num: PHY port num that address we want
6632  * @phy_addr: Returned PHY address
6633  *
6634  * Gets PHY address for current port
6635  **/
6636 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6637 {
6638         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6639         u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6640
6641         return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6642 }
6643
6644 /**
6645  * i40e_blink_phy_led
6646  * @hw: pointer to the HW structure
6647  * @time: time how long led will blinks in secs
6648  * @interval: gap between LED on and off in msecs
6649  *
6650  * Blinks PHY link LED
6651  **/
6652 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6653                                               u32 time, u32 interval)
6654 {
6655         enum i40e_status_code status = I40E_SUCCESS;
6656         u32 i;
6657         u16 led_ctl = 0;
6658         u16 gpio_led_port;
6659         u16 led_reg;
6660         u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6661         u8 phy_addr = 0;
6662         u8 port_num;
6663
6664         i = rd32(hw, I40E_PFGEN_PORTNUM);
6665         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6666         phy_addr = i40e_get_phy_address(hw, port_num);
6667
6668         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6669              led_addr++) {
6670                 status = i40e_read_phy_register_clause45(hw,
6671                                                          I40E_PHY_COM_REG_PAGE,
6672                                                          led_addr, phy_addr,
6673                                                          &led_reg);
6674                 if (status)
6675                         goto phy_blinking_end;
6676                 led_ctl = led_reg;
6677                 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6678                         led_reg = 0;
6679                         status = i40e_write_phy_register_clause45(hw,
6680                                                          I40E_PHY_COM_REG_PAGE,
6681                                                          led_addr, phy_addr,
6682                                                          led_reg);
6683                         if (status)
6684                                 goto phy_blinking_end;
6685                         break;
6686                 }
6687         }
6688
6689         if (time > 0 && interval > 0) {
6690                 for (i = 0; i < time * 1000; i += interval) {
6691                         status = i40e_read_phy_register_clause45(hw,
6692                                                 I40E_PHY_COM_REG_PAGE,
6693                                                 led_addr, phy_addr, &led_reg);
6694                         if (status)
6695                                 goto restore_config;
6696                         if (led_reg & I40E_PHY_LED_MANUAL_ON)
6697                                 led_reg = 0;
6698                         else
6699                                 led_reg = I40E_PHY_LED_MANUAL_ON;
6700                         status = i40e_write_phy_register_clause45(hw,
6701                                                 I40E_PHY_COM_REG_PAGE,
6702                                                 led_addr, phy_addr, led_reg);
6703                         if (status)
6704                                 goto restore_config;
6705                         i40e_msec_delay(interval);
6706                 }
6707         }
6708
6709 restore_config:
6710         status = i40e_write_phy_register_clause45(hw,
6711                                                   I40E_PHY_COM_REG_PAGE,
6712                                                   led_addr, phy_addr, led_ctl);
6713
6714 phy_blinking_end:
6715         return status;
6716 }
6717
6718 /**
6719  * i40e_led_get_reg - read LED register
6720  * @hw: pointer to the HW structure
6721  * @led_addr: LED register address
6722  * @reg_val: read register value
6723  **/
6724 static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr,
6725                                               u32 *reg_val)
6726 {
6727         enum i40e_status_code status;
6728         u8 phy_addr = 0;
6729
6730         *reg_val = 0;
6731         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6732                 status = i40e_aq_get_phy_register(hw,
6733                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6734                                                 I40E_PHY_COM_REG_PAGE,
6735                                                 I40E_PHY_LED_PROV_REG_1,
6736                                                 reg_val, NULL);
6737         } else {
6738                 phy_addr = i40e_get_phy_address(hw, hw->port);
6739                 status = i40e_read_phy_register_clause45(hw,
6740                                                          I40E_PHY_COM_REG_PAGE,
6741                                                          led_addr, phy_addr,
6742                                                          (u16 *)reg_val);
6743         }
6744         return status;
6745 }
6746
6747 /**
6748  * i40e_led_set_reg - write LED register
6749  * @hw: pointer to the HW structure
6750  * @led_addr: LED register address
6751  * @reg_val: register value to write
6752  **/
6753 static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr,
6754                                               u32 reg_val)
6755 {
6756         enum i40e_status_code status;
6757         u8 phy_addr = 0;
6758
6759         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6760                 status = i40e_aq_set_phy_register(hw,
6761                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6762                                                 I40E_PHY_COM_REG_PAGE,
6763                                                 I40E_PHY_LED_PROV_REG_1,
6764                                                 reg_val, NULL);
6765         } else {
6766                 phy_addr = i40e_get_phy_address(hw, hw->port);
6767                 status = i40e_write_phy_register_clause45(hw,
6768                                                           I40E_PHY_COM_REG_PAGE,
6769                                                           led_addr, phy_addr,
6770                                                           (u16)reg_val);
6771         }
6772
6773         return status;
6774 }
6775
6776 /**
6777  * i40e_led_get_phy - return current on/off mode
6778  * @hw: pointer to the hw struct
6779  * @led_addr: address of led register to use
6780  * @val: original value of register to use
6781  *
6782  **/
6783 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6784                                        u16 *val)
6785 {
6786         enum i40e_status_code status = I40E_SUCCESS;
6787         u16 gpio_led_port;
6788         u32 reg_val_aq;
6789         u16 temp_addr;
6790         u8 phy_addr = 0;
6791         u16 reg_val;
6792
6793         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6794                 status = i40e_aq_get_phy_register(hw,
6795                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6796                                                 I40E_PHY_COM_REG_PAGE,
6797                                                 I40E_PHY_LED_PROV_REG_1,
6798                                                 &reg_val_aq, NULL);
6799                 if (status == I40E_SUCCESS)
6800                         *val = (u16)reg_val_aq;
6801                 return status;
6802         }
6803         temp_addr = I40E_PHY_LED_PROV_REG_1;
6804         phy_addr = i40e_get_phy_address(hw, hw->port);
6805         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6806              temp_addr++) {
6807                 status = i40e_read_phy_register_clause45(hw,
6808                                                          I40E_PHY_COM_REG_PAGE,
6809                                                          temp_addr, phy_addr,
6810                                                          &reg_val);
6811                 if (status)
6812                         return status;
6813                 *val = reg_val;
6814                 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6815                         *led_addr = temp_addr;
6816                         break;
6817                 }
6818         }
6819         return status;
6820 }
6821
6822 /**
6823  * i40e_led_set_phy
6824  * @hw: pointer to the HW structure
6825  * @on: true or false
6826  * @mode: original val plus bit for set or ignore
6827  * Set led's on or off when controlled by the PHY
6828  *
6829  **/
6830 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6831                                        u16 led_addr, u32 mode)
6832 {
6833         enum i40e_status_code status = I40E_SUCCESS;
6834         u32 led_ctl = 0;
6835         u32 led_reg = 0;
6836
6837         status = i40e_led_get_reg(hw, led_addr, &led_reg);
6838         if (status)
6839                 return status;
6840         led_ctl = led_reg;
6841         if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6842                 led_reg = 0;
6843                 status = i40e_led_set_reg(hw, led_addr, led_reg);
6844                 if (status)
6845                         return status;
6846         }
6847         status = i40e_led_get_reg(hw, led_addr, &led_reg);
6848         if (status)
6849                 goto restore_config;
6850         if (on)
6851                 led_reg = I40E_PHY_LED_MANUAL_ON;
6852         else
6853                 led_reg = 0;
6854         status = i40e_led_set_reg(hw, led_addr, led_reg);
6855         if (status)
6856                 goto restore_config;
6857         if (mode & I40E_PHY_LED_MODE_ORIG) {
6858                 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6859                 status = i40e_led_set_reg(hw, led_addr, led_ctl);
6860         }
6861         return status;
6862
6863 restore_config:
6864         status = i40e_led_set_reg(hw, led_addr, led_ctl);
6865         return status;
6866 }
6867 #endif /* PF_DRIVER */
6868
6869 /**
6870  * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6871  * @hw: pointer to the hw struct
6872  * @reg_addr: register address
6873  * @reg_val: ptr to register value
6874  * @cmd_details: pointer to command details structure or NULL
6875  *
6876  * Use the firmware to read the Rx control register,
6877  * especially useful if the Rx unit is under heavy pressure
6878  **/
6879 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6880                                 u32 reg_addr, u32 *reg_val,
6881                                 struct i40e_asq_cmd_details *cmd_details)
6882 {
6883         struct i40e_aq_desc desc;
6884         struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
6885                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6886         enum i40e_status_code status;
6887
6888         if (reg_val == NULL)
6889                 return I40E_ERR_PARAM;
6890
6891         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
6892
6893         cmd_resp->address = CPU_TO_LE32(reg_addr);
6894
6895         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6896
6897         if (status == I40E_SUCCESS)
6898                 *reg_val = LE32_TO_CPU(cmd_resp->value);
6899
6900         return status;
6901 }
6902
6903 /**
6904  * i40e_read_rx_ctl - read from an Rx control register
6905  * @hw: pointer to the hw struct
6906  * @reg_addr: register address
6907  **/
6908 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
6909 {
6910         enum i40e_status_code status = I40E_SUCCESS;
6911         bool use_register;
6912         int retry = 5;
6913         u32 val = 0;
6914
6915         use_register = (((hw->aq.api_maj_ver == 1) &&
6916                         (hw->aq.api_min_ver < 5)) ||
6917                         (hw->mac.type == I40E_MAC_X722));
6918         if (!use_register) {
6919 do_retry:
6920                 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
6921                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6922                         i40e_msec_delay(1);
6923                         retry--;
6924                         goto do_retry;
6925                 }
6926         }
6927
6928         /* if the AQ access failed, try the old-fashioned way */
6929         if (status || use_register)
6930                 val = rd32(hw, reg_addr);
6931
6932         return val;
6933 }
6934
6935 /**
6936  * i40e_aq_rx_ctl_write_register
6937  * @hw: pointer to the hw struct
6938  * @reg_addr: register address
6939  * @reg_val: register value
6940  * @cmd_details: pointer to command details structure or NULL
6941  *
6942  * Use the firmware to write to an Rx control register,
6943  * especially useful if the Rx unit is under heavy pressure
6944  **/
6945 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
6946                                 u32 reg_addr, u32 reg_val,
6947                                 struct i40e_asq_cmd_details *cmd_details)
6948 {
6949         struct i40e_aq_desc desc;
6950         struct i40e_aqc_rx_ctl_reg_read_write *cmd =
6951                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6952         enum i40e_status_code status;
6953
6954         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
6955
6956         cmd->address = CPU_TO_LE32(reg_addr);
6957         cmd->value = CPU_TO_LE32(reg_val);
6958
6959         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6960
6961         return status;
6962 }
6963
6964 /**
6965  * i40e_write_rx_ctl - write to an Rx control register
6966  * @hw: pointer to the hw struct
6967  * @reg_addr: register address
6968  * @reg_val: register value
6969  **/
6970 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
6971 {
6972         enum i40e_status_code status = I40E_SUCCESS;
6973         bool use_register;
6974         int retry = 5;
6975
6976         use_register = (((hw->aq.api_maj_ver == 1) &&
6977                         (hw->aq.api_min_ver < 5)) ||
6978                         (hw->mac.type == I40E_MAC_X722));
6979         if (!use_register) {
6980 do_retry:
6981                 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
6982                                                        reg_val, NULL);
6983                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6984                         i40e_msec_delay(1);
6985                         retry--;
6986                         goto do_retry;
6987                 }
6988         }
6989
6990         /* if the AQ access failed, try the old-fashioned way */
6991         if (status || use_register)
6992                 wr32(hw, reg_addr, reg_val);
6993 }
6994
6995 /**
6996  * i40e_aq_set_phy_register
6997  * @hw: pointer to the hw struct
6998  * @phy_select: select which phy should be accessed
6999  * @dev_addr: PHY device address
7000  * @reg_addr: PHY register address
7001  * @reg_val: new register value
7002  * @cmd_details: pointer to command details structure or NULL
7003  *
7004  * Write the external PHY register.
7005  **/
7006 enum i40e_status_code i40e_aq_set_phy_register(struct i40e_hw *hw,
7007                                 u8 phy_select, u8 dev_addr,
7008                                 u32 reg_addr, u32 reg_val,
7009                                 struct i40e_asq_cmd_details *cmd_details)
7010 {
7011         struct i40e_aq_desc desc;
7012         struct i40e_aqc_phy_register_access *cmd =
7013                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7014         enum i40e_status_code status;
7015
7016         i40e_fill_default_direct_cmd_desc(&desc,
7017                                           i40e_aqc_opc_set_phy_register);
7018
7019         cmd->phy_interface = phy_select;
7020         cmd->dev_addres = dev_addr;
7021         cmd->reg_address = CPU_TO_LE32(reg_addr);
7022         cmd->reg_value = CPU_TO_LE32(reg_val);
7023
7024         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7025
7026         return status;
7027 }
7028
7029 /**
7030  * i40e_aq_get_phy_register
7031  * @hw: pointer to the hw struct
7032  * @phy_select: select which phy should be accessed
7033  * @dev_addr: PHY device address
7034  * @reg_addr: PHY register address
7035  * @reg_val: read register value
7036  * @cmd_details: pointer to command details structure or NULL
7037  *
7038  * Read the external PHY register.
7039  **/
7040 enum i40e_status_code i40e_aq_get_phy_register(struct i40e_hw *hw,
7041                                 u8 phy_select, u8 dev_addr,
7042                                 u32 reg_addr, u32 *reg_val,
7043                                 struct i40e_asq_cmd_details *cmd_details)
7044 {
7045         struct i40e_aq_desc desc;
7046         struct i40e_aqc_phy_register_access *cmd =
7047                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7048         enum i40e_status_code status;
7049
7050         i40e_fill_default_direct_cmd_desc(&desc,
7051                                           i40e_aqc_opc_get_phy_register);
7052
7053         cmd->phy_interface = phy_select;
7054         cmd->dev_addres = dev_addr;
7055         cmd->reg_address = CPU_TO_LE32(reg_addr);
7056
7057         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7058         if (!status)
7059                 *reg_val = LE32_TO_CPU(cmd->reg_value);
7060
7061         return status;
7062 }
7063
7064 #ifdef VF_DRIVER
7065
7066 /**
7067  * i40e_aq_send_msg_to_pf
7068  * @hw: pointer to the hardware structure
7069  * @v_opcode: opcodes for VF-PF communication
7070  * @v_retval: return error code
7071  * @msg: pointer to the msg buffer
7072  * @msglen: msg length
7073  * @cmd_details: pointer to command details
7074  *
7075  * Send message to PF driver using admin queue. By default, this message
7076  * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
7077  * completion before returning.
7078  **/
7079 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
7080                                 enum virtchnl_ops v_opcode,
7081                                 enum i40e_status_code v_retval,
7082                                 u8 *msg, u16 msglen,
7083                                 struct i40e_asq_cmd_details *cmd_details)
7084 {
7085         struct i40e_aq_desc desc;
7086         struct i40e_asq_cmd_details details;
7087         enum i40e_status_code status;
7088
7089         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
7090         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
7091         desc.cookie_high = CPU_TO_LE32(v_opcode);
7092         desc.cookie_low = CPU_TO_LE32(v_retval);
7093         if (msglen) {
7094                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
7095                                                 | I40E_AQ_FLAG_RD));
7096                 if (msglen > I40E_AQ_LARGE_BUF)
7097                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7098                 desc.datalen = CPU_TO_LE16(msglen);
7099         }
7100         if (!cmd_details) {
7101                 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
7102                 details.async = true;
7103                 cmd_details = &details;
7104         }
7105         status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
7106                                        msglen, cmd_details);
7107         return status;
7108 }
7109
7110 /**
7111  * i40e_vf_parse_hw_config
7112  * @hw: pointer to the hardware structure
7113  * @msg: pointer to the virtual channel VF resource structure
7114  *
7115  * Given a VF resource message from the PF, populate the hw struct
7116  * with appropriate information.
7117  **/
7118 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
7119                              struct virtchnl_vf_resource *msg)
7120 {
7121         struct virtchnl_vsi_resource *vsi_res;
7122         int i;
7123
7124         vsi_res = &msg->vsi_res[0];
7125
7126         hw->dev_caps.num_vsis = msg->num_vsis;
7127         hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
7128         hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
7129         hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
7130         hw->dev_caps.dcb = msg->vf_offload_flags &
7131                            VIRTCHNL_VF_OFFLOAD_L2;
7132         hw->dev_caps.iwarp = (msg->vf_offload_flags &
7133                               VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
7134         for (i = 0; i < msg->num_vsis; i++) {
7135                 if (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) {
7136                         i40e_memcpy(hw->mac.perm_addr,
7137                                     vsi_res->default_mac_addr,
7138                                     ETH_ALEN,
7139                                     I40E_NONDMA_TO_NONDMA);
7140                         i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
7141                                     ETH_ALEN,
7142                                     I40E_NONDMA_TO_NONDMA);
7143                 }
7144                 vsi_res++;
7145         }
7146 }
7147
7148 /**
7149  * i40e_vf_reset
7150  * @hw: pointer to the hardware structure
7151  *
7152  * Send a VF_RESET message to the PF. Does not wait for response from PF
7153  * as none will be forthcoming. Immediately after calling this function,
7154  * the admin queue should be shut down and (optionally) reinitialized.
7155  **/
7156 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
7157 {
7158         return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF,
7159                                       I40E_SUCCESS, NULL, 0, NULL);
7160 }
7161 #endif /* VF_DRIVER */
7162
7163 /**
7164  * i40e_aq_set_arp_proxy_config
7165  * @hw: pointer to the HW structure
7166  * @proxy_config - pointer to proxy config command table struct
7167  * @cmd_details: pointer to command details
7168  *
7169  * Set ARP offload parameters from pre-populated
7170  * i40e_aqc_arp_proxy_data struct
7171  **/
7172 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
7173                                 struct i40e_aqc_arp_proxy_data *proxy_config,
7174                                 struct i40e_asq_cmd_details *cmd_details)
7175 {
7176         struct i40e_aq_desc desc;
7177         enum i40e_status_code status;
7178
7179         if (!proxy_config)
7180                 return I40E_ERR_PARAM;
7181
7182         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
7183
7184         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7185         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7186         desc.params.external.addr_high =
7187                                   CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
7188         desc.params.external.addr_low =
7189                                   CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
7190         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_arp_proxy_data));
7191
7192         status = i40e_asq_send_command(hw, &desc, proxy_config,
7193                                        sizeof(struct i40e_aqc_arp_proxy_data),
7194                                        cmd_details);
7195
7196         return status;
7197 }
7198
7199 /**
7200  * i40e_aq_opc_set_ns_proxy_table_entry
7201  * @hw: pointer to the HW structure
7202  * @ns_proxy_table_entry: pointer to NS table entry command struct
7203  * @cmd_details: pointer to command details
7204  *
7205  * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
7206  * from pre-populated i40e_aqc_ns_proxy_data struct
7207  **/
7208 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
7209                         struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
7210                         struct i40e_asq_cmd_details *cmd_details)
7211 {
7212         struct i40e_aq_desc desc;
7213         enum i40e_status_code status;
7214
7215         if (!ns_proxy_table_entry)
7216                 return I40E_ERR_PARAM;
7217
7218         i40e_fill_default_direct_cmd_desc(&desc,
7219                                 i40e_aqc_opc_set_ns_proxy_table_entry);
7220
7221         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7222         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7223         desc.params.external.addr_high =
7224                 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
7225         desc.params.external.addr_low =
7226                 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
7227         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_ns_proxy_data));
7228
7229         status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
7230                                        sizeof(struct i40e_aqc_ns_proxy_data),
7231                                        cmd_details);
7232
7233         return status;
7234 }
7235
7236 /**
7237  * i40e_aq_set_clear_wol_filter
7238  * @hw: pointer to the hw struct
7239  * @filter_index: index of filter to modify (0-7)
7240  * @filter: buffer containing filter to be set
7241  * @set_filter: true to set filter, false to clear filter
7242  * @no_wol_tco: if true, pass through packets cannot cause wake-up
7243  *              if false, pass through packets may cause wake-up
7244  * @filter_valid: true if filter action is valid
7245  * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
7246  * @cmd_details: pointer to command details structure or NULL
7247  *
7248  * Set or clear WoL filter for port attached to the PF
7249  **/
7250 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
7251                                 u8 filter_index,
7252                                 struct i40e_aqc_set_wol_filter_data *filter,
7253                                 bool set_filter, bool no_wol_tco,
7254                                 bool filter_valid, bool no_wol_tco_valid,
7255                                 struct i40e_asq_cmd_details *cmd_details)
7256 {
7257         struct i40e_aq_desc desc;
7258         struct i40e_aqc_set_wol_filter *cmd =
7259                 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
7260         enum i40e_status_code status;
7261         u16 cmd_flags = 0;
7262         u16 valid_flags = 0;
7263         u16 buff_len = 0;
7264
7265         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
7266
7267         if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
7268                 return  I40E_ERR_PARAM;
7269         cmd->filter_index = CPU_TO_LE16(filter_index);
7270
7271         if (set_filter) {
7272                 if (!filter)
7273                         return  I40E_ERR_PARAM;
7274
7275                 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
7276                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR;
7277         }
7278
7279         if (no_wol_tco)
7280                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
7281         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
7282
7283         if (filter_valid)
7284                 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
7285         if (no_wol_tco_valid)
7286                 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
7287         cmd->valid_flags = CPU_TO_LE16(valid_flags);
7288
7289         buff_len = sizeof(*filter);
7290         desc.datalen = CPU_TO_LE16(buff_len);
7291
7292         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7293         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7294
7295         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
7296         cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
7297
7298         status = i40e_asq_send_command(hw, &desc, filter,
7299                                        buff_len, cmd_details);
7300
7301         return status;
7302 }
7303
7304 /**
7305  * i40e_aq_get_wake_event_reason
7306  * @hw: pointer to the hw struct
7307  * @wake_reason: return value, index of matching filter
7308  * @cmd_details: pointer to command details structure or NULL
7309  *
7310  * Get information for the reason of a Wake Up event
7311  **/
7312 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
7313                                 u16 *wake_reason,
7314                                 struct i40e_asq_cmd_details *cmd_details)
7315 {
7316         struct i40e_aq_desc desc;
7317         struct i40e_aqc_get_wake_reason_completion *resp =
7318                 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
7319         enum i40e_status_code status;
7320
7321         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
7322
7323         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7324
7325         if (status == I40E_SUCCESS)
7326                 *wake_reason = LE16_TO_CPU(resp->wake_reason);
7327
7328         return status;
7329 }
7330
7331 /**
7332 * i40e_aq_clear_all_wol_filters
7333 * @hw: pointer to the hw struct
7334 * @cmd_details: pointer to command details structure or NULL
7335 *
7336 * Get information for the reason of a Wake Up event
7337 **/
7338 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw,
7339         struct i40e_asq_cmd_details *cmd_details)
7340 {
7341         struct i40e_aq_desc desc;
7342         enum i40e_status_code status;
7343
7344         i40e_fill_default_direct_cmd_desc(&desc,
7345                                           i40e_aqc_opc_clear_all_wol_filters);
7346
7347         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7348
7349         return status;
7350 }
7351
7352
7353 /**
7354  * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
7355  * @hw: pointer to the hw struct
7356  * @buff: command buffer (size in bytes = buff_size)
7357  * @buff_size: buffer size in bytes
7358  * @track_id: package tracking id
7359  * @error_offset: returns error offset
7360  * @error_info: returns error information
7361  * @cmd_details: pointer to command details structure or NULL
7362  **/
7363 enum
7364 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
7365                                    u16 buff_size, u32 track_id,
7366                                    u32 *error_offset, u32 *error_info,
7367                                    struct i40e_asq_cmd_details *cmd_details)
7368 {
7369         struct i40e_aq_desc desc;
7370         struct i40e_aqc_write_personalization_profile *cmd =
7371                 (struct i40e_aqc_write_personalization_profile *)
7372                 &desc.params.raw;
7373         struct i40e_aqc_write_ddp_resp *resp;
7374         enum i40e_status_code status;
7375
7376         i40e_fill_default_direct_cmd_desc(&desc,
7377                                   i40e_aqc_opc_write_personalization_profile);
7378
7379         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
7380         if (buff_size > I40E_AQ_LARGE_BUF)
7381                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7382
7383         desc.datalen = CPU_TO_LE16(buff_size);
7384
7385         cmd->profile_track_id = CPU_TO_LE32(track_id);
7386
7387         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7388         if (!status) {
7389                 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
7390                 if (error_offset)
7391                         *error_offset = LE32_TO_CPU(resp->error_offset);
7392                 if (error_info)
7393                         *error_info = LE32_TO_CPU(resp->error_info);
7394         }
7395
7396         return status;
7397 }
7398
7399 /**
7400  * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
7401  * @hw: pointer to the hw struct
7402  * @buff: command buffer (size in bytes = buff_size)
7403  * @buff_size: buffer size in bytes
7404  * @cmd_details: pointer to command details structure or NULL
7405  **/
7406 enum
7407 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
7408                                       u16 buff_size, u8 flags,
7409                                       struct i40e_asq_cmd_details *cmd_details)
7410 {
7411         struct i40e_aq_desc desc;
7412         struct i40e_aqc_get_applied_profiles *cmd =
7413                 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
7414         enum i40e_status_code status;
7415
7416         i40e_fill_default_direct_cmd_desc(&desc,
7417                           i40e_aqc_opc_get_personalization_profile_list);
7418
7419         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7420         if (buff_size > I40E_AQ_LARGE_BUF)
7421                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7422         desc.datalen = CPU_TO_LE16(buff_size);
7423
7424         cmd->flags = flags;
7425
7426         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7427
7428         return status;
7429 }
7430
7431 /**
7432  * i40e_find_segment_in_package
7433  * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
7434  * @pkg_hdr: pointer to the package header to be searched
7435  *
7436  * This function searches a package file for a particular segment type. On
7437  * success it returns a pointer to the segment header, otherwise it will
7438  * return NULL.
7439  **/
7440 struct i40e_generic_seg_header *
7441 i40e_find_segment_in_package(u32 segment_type,
7442                              struct i40e_package_header *pkg_hdr)
7443 {
7444         struct i40e_generic_seg_header *segment;
7445         u32 i;
7446
7447         /* Search all package segments for the requested segment type */
7448         for (i = 0; i < pkg_hdr->segment_count; i++) {
7449                 segment =
7450                         (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
7451                          pkg_hdr->segment_offset[i]);
7452
7453                 if (segment->type == segment_type)
7454                         return segment;
7455         }
7456
7457         return NULL;
7458 }
7459
7460 /* Get section table in profile */
7461 #define I40E_SECTION_TABLE(profile, sec_tbl)                            \
7462         do {                                                            \
7463                 struct i40e_profile_segment *p = (profile);             \
7464                 u32 count;                                              \
7465                 u32 *nvm;                                               \
7466                 count = p->device_table_count;                          \
7467                 nvm = (u32 *)&p->device_table[count];                   \
7468                 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \
7469         } while (0)
7470
7471 /* Get section header in profile */
7472 #define I40E_SECTION_HEADER(profile, offset)                            \
7473         (struct i40e_profile_section_header *)((u8 *)(profile) + (offset))
7474
7475 /**
7476  * i40e_find_section_in_profile
7477  * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE)
7478  * @profile: pointer to the i40e segment header to be searched
7479  *
7480  * This function searches i40e segment for a particular section type. On
7481  * success it returns a pointer to the section header, otherwise it will
7482  * return NULL.
7483  **/
7484 struct i40e_profile_section_header *
7485 i40e_find_section_in_profile(u32 section_type,
7486                              struct i40e_profile_segment *profile)
7487 {
7488         struct i40e_profile_section_header *sec;
7489         struct i40e_section_table *sec_tbl;
7490         u32 sec_off;
7491         u32 i;
7492
7493         if (profile->header.type != SEGMENT_TYPE_I40E)
7494                 return NULL;
7495
7496         I40E_SECTION_TABLE(profile, sec_tbl);
7497
7498         for (i = 0; i < sec_tbl->section_count; i++) {
7499                 sec_off = sec_tbl->section_offset[i];
7500                 sec = I40E_SECTION_HEADER(profile, sec_off);
7501                 if (sec->section.type == section_type)
7502                         return sec;
7503         }
7504
7505         return NULL;
7506 }
7507
7508 /**
7509  * i40e_ddp_exec_aq_section - Execute generic AQ for DDP
7510  * @hw: pointer to the hw struct
7511  * @aq: command buffer containing all data to execute AQ
7512  **/
7513 STATIC enum
7514 i40e_status_code i40e_ddp_exec_aq_section(struct i40e_hw *hw,
7515                                           struct i40e_profile_aq_section *aq)
7516 {
7517         enum i40e_status_code status;
7518         struct i40e_aq_desc desc;
7519         u8 *msg = NULL;
7520         u16 msglen;
7521
7522         i40e_fill_default_direct_cmd_desc(&desc, aq->opcode);
7523         desc.flags |= CPU_TO_LE16(aq->flags);
7524         i40e_memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw),
7525                     I40E_NONDMA_TO_NONDMA);
7526
7527         msglen = aq->datalen;
7528         if (msglen) {
7529                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
7530                                                 I40E_AQ_FLAG_RD));
7531                 if (msglen > I40E_AQ_LARGE_BUF)
7532                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7533                 desc.datalen = CPU_TO_LE16(msglen);
7534                 msg = &aq->data[0];
7535         }
7536
7537         status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL);
7538
7539         if (status != I40E_SUCCESS) {
7540                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7541                            "unable to exec DDP AQ opcode %u, error %d\n",
7542                            aq->opcode, status);
7543                 return status;
7544         }
7545
7546         /* copy returned desc to aq_buf */
7547         i40e_memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw),
7548                     I40E_NONDMA_TO_NONDMA);
7549
7550         return I40E_SUCCESS;
7551 }
7552
7553 /**
7554  * i40e_validate_profile
7555  * @hw: pointer to the hardware structure
7556  * @profile: pointer to the profile segment of the package to be validated
7557  * @track_id: package tracking id
7558  * @rollback: flag if the profile is for rollback.
7559  *
7560  * Validates supported devices and profile's sections.
7561  */
7562 STATIC enum i40e_status_code
7563 i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7564                       u32 track_id, bool rollback)
7565 {
7566         struct i40e_profile_section_header *sec = NULL;
7567         enum i40e_status_code status = I40E_SUCCESS;
7568         struct i40e_section_table *sec_tbl;
7569         u32 vendor_dev_id;
7570         u32 dev_cnt;
7571         u32 sec_off;
7572         u32 i;
7573
7574         if (track_id == I40E_DDP_TRACKID_INVALID) {
7575                 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n");
7576                 return I40E_NOT_SUPPORTED;
7577         }
7578
7579         dev_cnt = profile->device_table_count;
7580         for (i = 0; i < dev_cnt; i++) {
7581                 vendor_dev_id = profile->device_table[i].vendor_dev_id;
7582                 if ((vendor_dev_id >> 16) == I40E_INTEL_VENDOR_ID &&
7583                     hw->device_id == (vendor_dev_id & 0xFFFF))
7584                         break;
7585         }
7586         if (dev_cnt && (i == dev_cnt)) {
7587                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7588                            "Device doesn't support DDP\n");
7589                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
7590         }
7591
7592         I40E_SECTION_TABLE(profile, sec_tbl);
7593
7594         /* Validate sections types */
7595         for (i = 0; i < sec_tbl->section_count; i++) {
7596                 sec_off = sec_tbl->section_offset[i];
7597                 sec = I40E_SECTION_HEADER(profile, sec_off);
7598                 if (rollback) {
7599                         if (sec->section.type == SECTION_TYPE_MMIO ||
7600                             sec->section.type == SECTION_TYPE_AQ ||
7601                             sec->section.type == SECTION_TYPE_RB_AQ) {
7602                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7603                                            "Not a roll-back package\n");
7604                                 return I40E_NOT_SUPPORTED;
7605                         }
7606                 } else {
7607                         if (sec->section.type == SECTION_TYPE_RB_AQ ||
7608                             sec->section.type == SECTION_TYPE_RB_MMIO) {
7609                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7610                                            "Not an original package\n");
7611                                 return I40E_NOT_SUPPORTED;
7612                         }
7613                 }
7614         }
7615
7616         return status;
7617 }
7618
7619 /**
7620  * i40e_write_profile
7621  * @hw: pointer to the hardware structure
7622  * @profile: pointer to the profile segment of the package to be downloaded
7623  * @track_id: package tracking id
7624  *
7625  * Handles the download of a complete package.
7626  */
7627 enum i40e_status_code
7628 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7629                    u32 track_id)
7630 {
7631         enum i40e_status_code status = I40E_SUCCESS;
7632         struct i40e_section_table *sec_tbl;
7633         struct i40e_profile_section_header *sec = NULL;
7634         struct i40e_profile_aq_section *ddp_aq;
7635         u32 section_size = 0;
7636         u32 offset = 0, info = 0;
7637         u32 sec_off;
7638         u32 i;
7639
7640         status = i40e_validate_profile(hw, profile, track_id, false);
7641         if (status)
7642                 return status;
7643
7644         I40E_SECTION_TABLE(profile, sec_tbl);
7645
7646         for (i = 0; i < sec_tbl->section_count; i++) {
7647                 sec_off = sec_tbl->section_offset[i];
7648                 sec = I40E_SECTION_HEADER(profile, sec_off);
7649                 /* Process generic admin command */
7650                 if (sec->section.type == SECTION_TYPE_AQ) {
7651                         ddp_aq = (struct i40e_profile_aq_section *)&sec[1];
7652                         status = i40e_ddp_exec_aq_section(hw, ddp_aq);
7653                         if (status) {
7654                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7655                                            "Failed to execute aq: section %d, opcode %u\n",
7656                                            i, ddp_aq->opcode);
7657                                 break;
7658                         }
7659                         sec->section.type = SECTION_TYPE_RB_AQ;
7660                 }
7661
7662                 /* Skip any non-mmio sections */
7663                 if (sec->section.type != SECTION_TYPE_MMIO)
7664                         continue;
7665
7666                 section_size = sec->section.size +
7667                         sizeof(struct i40e_profile_section_header);
7668
7669                 /* Write MMIO section */
7670                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
7671                                            track_id, &offset, &info, NULL);
7672                 if (status) {
7673                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
7674                                    "Failed to write profile: section %d, offset %d, info %d\n",
7675                                    i, offset, info);
7676                         break;
7677                 }
7678         }
7679         return status;
7680 }
7681
7682 /**
7683  * i40e_rollback_profile
7684  * @hw: pointer to the hardware structure
7685  * @profile: pointer to the profile segment of the package to be removed
7686  * @track_id: package tracking id
7687  *
7688  * Rolls back previously loaded package.
7689  */
7690 enum i40e_status_code
7691 i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7692                       u32 track_id)
7693 {
7694         struct i40e_profile_section_header *sec = NULL;
7695         enum i40e_status_code status = I40E_SUCCESS;
7696         struct i40e_section_table *sec_tbl;
7697         u32 offset = 0, info = 0;
7698         u32 section_size = 0;
7699         u32 sec_off;
7700         int i;
7701
7702         status = i40e_validate_profile(hw, profile, track_id, true);
7703         if (status)
7704                 return status;
7705
7706         I40E_SECTION_TABLE(profile, sec_tbl);
7707
7708         /* For rollback write sections in reverse */
7709         for (i = sec_tbl->section_count - 1; i >= 0; i--) {
7710                 sec_off = sec_tbl->section_offset[i];
7711                 sec = I40E_SECTION_HEADER(profile, sec_off);
7712
7713                 /* Skip any non-rollback sections */
7714                 if (sec->section.type != SECTION_TYPE_RB_MMIO)
7715                         continue;
7716
7717                 section_size = sec->section.size +
7718                         sizeof(struct i40e_profile_section_header);
7719
7720                 /* Write roll-back MMIO section */
7721                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
7722                                            track_id, &offset, &info, NULL);
7723                 if (status) {
7724                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
7725                                    "Failed to write profile: section %d, offset %d, info %d\n",
7726                                    i, offset, info);
7727                         break;
7728                 }
7729         }
7730         return status;
7731 }
7732
7733 /**
7734  * i40e_add_pinfo_to_list
7735  * @hw: pointer to the hardware structure
7736  * @profile: pointer to the profile segment of the package
7737  * @profile_info_sec: buffer for information section
7738  * @track_id: package tracking id
7739  *
7740  * Register a profile to the list of loaded profiles.
7741  */
7742 enum i40e_status_code
7743 i40e_add_pinfo_to_list(struct i40e_hw *hw,
7744                        struct i40e_profile_segment *profile,
7745                        u8 *profile_info_sec, u32 track_id)
7746 {
7747         enum i40e_status_code status = I40E_SUCCESS;
7748         struct i40e_profile_section_header *sec = NULL;
7749         struct i40e_profile_info *pinfo;
7750         u32 offset = 0, info = 0;
7751
7752         sec = (struct i40e_profile_section_header *)profile_info_sec;
7753         sec->tbl_size = 1;
7754         sec->data_end = sizeof(struct i40e_profile_section_header) +
7755                         sizeof(struct i40e_profile_info);
7756         sec->section.type = SECTION_TYPE_INFO;
7757         sec->section.offset = sizeof(struct i40e_profile_section_header);
7758         sec->section.size = sizeof(struct i40e_profile_info);
7759         pinfo = (struct i40e_profile_info *)(profile_info_sec +
7760                                              sec->section.offset);
7761         pinfo->track_id = track_id;
7762         pinfo->version = profile->version;
7763         pinfo->op = I40E_DDP_ADD_TRACKID;
7764         i40e_memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE,
7765                     I40E_NONDMA_TO_NONDMA);
7766
7767         status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
7768                                    track_id, &offset, &info, NULL);
7769         return status;
7770 }